Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 38
- Boot result: FAIL
- Errors: 2
- Kernel Warnings: 24
- Warnings: 0
1 12:46:11.192645 lava-dispatcher, installed at version: 2023.05.1
2 12:46:11.192878 start: 0 validate
3 12:46:11.193016 Start time: 2023-07-20 12:46:11.193008+00:00 (UTC)
4 12:46:11.193158 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:46:11.193294 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:46:11.460955 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:46:11.461206 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.38-cip1-7-g5cff59cac977b%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:46:11.727094 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:46:11.727352 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.38-cip1-7-g5cff59cac977b%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:46:55.374022 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:46:55.374203 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.38-cip1-7-g5cff59cac977b%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:46:55.907897 validate duration: 44.71
14 12:46:55.908167 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:46:55.908277 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:46:55.908369 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:46:55.908496 Not decompressing ramdisk as can be used compressed.
18 12:46:55.908582 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 12:46:55.908646 saving as /var/lib/lava/dispatcher/tmp/11118904/tftp-deploy-3o_274nx/ramdisk/rootfs.cpio.gz
20 12:46:55.908707 total size: 34390042 (32MB)
21 12:46:58.473575 progress 0% (0MB)
22 12:46:58.485211 progress 5% (1MB)
23 12:46:58.496810 progress 10% (3MB)
24 12:46:58.507074 progress 15% (4MB)
25 12:46:58.516454 progress 20% (6MB)
26 12:46:58.528598 progress 25% (8MB)
27 12:46:58.537620 progress 30% (9MB)
28 12:46:58.546956 progress 35% (11MB)
29 12:46:58.555956 progress 40% (13MB)
30 12:46:58.565242 progress 45% (14MB)
31 12:46:58.574643 progress 50% (16MB)
32 12:46:58.583787 progress 55% (18MB)
33 12:46:58.593141 progress 60% (19MB)
34 12:46:58.602669 progress 65% (21MB)
35 12:46:58.611825 progress 70% (22MB)
36 12:46:58.621796 progress 75% (24MB)
37 12:46:58.631766 progress 80% (26MB)
38 12:46:58.641297 progress 85% (27MB)
39 12:46:58.650493 progress 90% (29MB)
40 12:46:58.659589 progress 95% (31MB)
41 12:46:58.668437 progress 100% (32MB)
42 12:46:58.668637 32MB downloaded in 2.76s (11.88MB/s)
43 12:46:58.668794 end: 1.1.1 http-download (duration 00:00:03) [common]
45 12:46:58.669037 end: 1.1 download-retry (duration 00:00:03) [common]
46 12:46:58.669127 start: 1.2 download-retry (timeout 00:09:57) [common]
47 12:46:58.669212 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 12:46:58.669358 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.38-cip1-7-g5cff59cac977b/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:46:58.669433 saving as /var/lib/lava/dispatcher/tmp/11118904/tftp-deploy-3o_274nx/kernel/Image
50 12:46:58.669497 total size: 48564736 (46MB)
51 12:46:58.669559 No compression specified
52 12:46:58.670977 progress 0% (0MB)
53 12:46:58.683898 progress 5% (2MB)
54 12:46:58.696764 progress 10% (4MB)
55 12:46:58.709838 progress 15% (6MB)
56 12:46:58.723123 progress 20% (9MB)
57 12:46:58.736319 progress 25% (11MB)
58 12:46:58.749224 progress 30% (13MB)
59 12:46:58.762287 progress 35% (16MB)
60 12:46:58.775296 progress 40% (18MB)
61 12:46:58.788573 progress 45% (20MB)
62 12:46:58.801480 progress 50% (23MB)
63 12:46:58.814572 progress 55% (25MB)
64 12:46:58.827737 progress 60% (27MB)
65 12:46:58.841523 progress 65% (30MB)
66 12:46:58.855054 progress 70% (32MB)
67 12:46:58.867794 progress 75% (34MB)
68 12:46:58.880671 progress 80% (37MB)
69 12:46:58.893495 progress 85% (39MB)
70 12:46:58.906280 progress 90% (41MB)
71 12:46:58.918792 progress 95% (44MB)
72 12:46:58.931541 progress 100% (46MB)
73 12:46:58.931697 46MB downloaded in 0.26s (176.64MB/s)
74 12:46:58.931854 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:46:58.932088 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:46:58.932176 start: 1.3 download-retry (timeout 00:09:57) [common]
78 12:46:58.932263 start: 1.3.1 http-download (timeout 00:09:57) [common]
79 12:46:58.932425 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.38-cip1-7-g5cff59cac977b/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:46:58.932505 saving as /var/lib/lava/dispatcher/tmp/11118904/tftp-deploy-3o_274nx/dtb/mt8192-asurada-spherion-r0.dtb
81 12:46:58.932570 total size: 46924 (0MB)
82 12:46:58.932632 No compression specified
83 12:46:58.933752 progress 69% (0MB)
84 12:46:58.934039 progress 100% (0MB)
85 12:46:58.934199 0MB downloaded in 0.00s (27.51MB/s)
86 12:46:58.934324 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:46:58.934637 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:46:58.934726 start: 1.4 download-retry (timeout 00:09:57) [common]
90 12:46:58.934811 start: 1.4.1 http-download (timeout 00:09:57) [common]
91 12:46:58.934930 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.38-cip1-7-g5cff59cac977b/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:46:58.935001 saving as /var/lib/lava/dispatcher/tmp/11118904/tftp-deploy-3o_274nx/modules/modules.tar
93 12:46:58.935064 total size: 8543056 (8MB)
94 12:46:58.935125 Using unxz to decompress xz
95 12:46:58.939081 progress 0% (0MB)
96 12:46:58.960975 progress 5% (0MB)
97 12:46:58.987201 progress 10% (0MB)
98 12:46:59.011638 progress 15% (1MB)
99 12:46:59.038717 progress 20% (1MB)
100 12:46:59.064561 progress 25% (2MB)
101 12:46:59.090374 progress 30% (2MB)
102 12:46:59.116193 progress 35% (2MB)
103 12:46:59.142006 progress 40% (3MB)
104 12:46:59.169293 progress 45% (3MB)
105 12:46:59.194944 progress 50% (4MB)
106 12:46:59.223263 progress 55% (4MB)
107 12:46:59.250683 progress 60% (4MB)
108 12:46:59.280559 progress 65% (5MB)
109 12:46:59.313996 progress 70% (5MB)
110 12:46:59.345897 progress 75% (6MB)
111 12:46:59.373671 progress 80% (6MB)
112 12:46:59.406951 progress 85% (6MB)
113 12:46:59.431490 progress 90% (7MB)
114 12:46:59.456151 progress 95% (7MB)
115 12:46:59.481533 progress 100% (8MB)
116 12:46:59.487695 8MB downloaded in 0.55s (14.74MB/s)
117 12:46:59.488086 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:46:59.488475 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:46:59.488611 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 12:46:59.488750 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 12:46:59.488870 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:46:59.488998 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 12:46:59.489317 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv
125 12:46:59.489516 makedir: /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin
126 12:46:59.489675 makedir: /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/tests
127 12:46:59.489825 makedir: /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/results
128 12:46:59.489989 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-add-keys
129 12:46:59.490203 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-add-sources
130 12:46:59.490392 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-background-process-start
131 12:46:59.490580 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-background-process-stop
132 12:46:59.490774 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-common-functions
133 12:46:59.490960 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-echo-ipv4
134 12:46:59.491146 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-install-packages
135 12:46:59.491329 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-installed-packages
136 12:46:59.491515 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-os-build
137 12:46:59.491698 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-probe-channel
138 12:46:59.491882 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-probe-ip
139 12:46:59.492064 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-target-ip
140 12:46:59.492250 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-target-mac
141 12:46:59.492435 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-target-storage
142 12:46:59.492626 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-test-case
143 12:46:59.492813 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-test-event
144 12:46:59.493002 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-test-feedback
145 12:46:59.493186 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-test-raise
146 12:46:59.493376 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-test-reference
147 12:46:59.493565 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-test-runner
148 12:46:59.493750 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-test-set
149 12:46:59.493938 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-test-shell
150 12:46:59.494129 Updating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-install-packages (oe)
151 12:46:59.494346 Updating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/bin/lava-installed-packages (oe)
152 12:46:59.494527 Creating /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/environment
153 12:46:59.494688 LAVA metadata
154 12:46:59.494800 - LAVA_JOB_ID=11118904
155 12:46:59.494900 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:46:59.495054 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 12:46:59.495159 skipped lava-vland-overlay
158 12:46:59.495273 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:46:59.495406 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 12:46:59.495522 skipped lava-multinode-overlay
161 12:46:59.495643 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:46:59.495775 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 12:46:59.495891 Loading test definitions
164 12:46:59.496031 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:56) [common]
165 12:46:59.496146 Using /lava-11118904 at stage 0
166 12:46:59.496621 uuid=11118904_1.5.2.3.1 testdef=None
167 12:46:59.496748 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:46:59.496873 start: 1.5.2.3.2 test-overlay (timeout 00:09:56) [common]
169 12:46:59.497623 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:46:59.497963 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:56) [common]
172 12:46:59.498880 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:46:59.499226 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:56) [common]
175 12:46:59.500154 runner path: /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/0/tests/0_cros-ec test_uuid 11118904_1.5.2.3.1
176 12:46:59.500366 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:46:59.500697 Creating lava-test-runner.conf files
179 12:46:59.500794 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11118904/lava-overlay-so_zy2rv/lava-11118904/0 for stage 0
180 12:46:59.500935 - 0_cros-ec
181 12:46:59.501075 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:46:59.501199 start: 1.5.2.4 compress-overlay (timeout 00:09:56) [common]
183 12:46:59.510606 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:46:59.510758 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:56) [common]
185 12:46:59.510887 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:46:59.511015 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:46:59.511147 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
188 12:47:00.796206 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:47:00.796686 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
190 12:47:00.796848 extracting modules file /var/lib/lava/dispatcher/tmp/11118904/tftp-deploy-3o_274nx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11118904/extract-overlay-ramdisk-sj1b99gj/ramdisk
191 12:47:01.118372 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:47:01.118554 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
193 12:47:01.118669 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11118904/compress-overlay-afpz91ij/overlay-1.5.2.4.tar.gz to ramdisk
194 12:47:01.118742 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11118904/compress-overlay-afpz91ij/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11118904/extract-overlay-ramdisk-sj1b99gj/ramdisk
195 12:47:01.125947 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:47:01.126069 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
197 12:47:01.126172 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:47:01.126265 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
199 12:47:01.126348 Building ramdisk /var/lib/lava/dispatcher/tmp/11118904/extract-overlay-ramdisk-sj1b99gj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11118904/extract-overlay-ramdisk-sj1b99gj/ramdisk
200 12:47:02.055511 >> 269521 blocks
201 12:47:06.961071 rename /var/lib/lava/dispatcher/tmp/11118904/extract-overlay-ramdisk-sj1b99gj/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11118904/tftp-deploy-3o_274nx/ramdisk/ramdisk.cpio.gz
202 12:47:06.961521 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 12:47:06.961632 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 12:47:06.961734 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 12:47:06.961842 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11118904/tftp-deploy-3o_274nx/kernel/Image'
206 12:47:20.406195 Returned 0 in 13 seconds
207 12:47:20.506744 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11118904/tftp-deploy-3o_274nx/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11118904/tftp-deploy-3o_274nx/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11118904/tftp-deploy-3o_274nx/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11118904/tftp-deploy-3o_274nx/kernel/image.itb
208 12:47:21.205448 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:47:21.206049 output: Created: Thu Jul 20 13:47:21 2023
210 12:47:21.206197 output: Image 0 (kernel-1)
211 12:47:21.206316 output: Description:
212 12:47:21.206489 output: Created: Thu Jul 20 13:47:21 2023
213 12:47:21.206618 output: Type: Kernel Image
214 12:47:21.206733 output: Compression: lzma compressed
215 12:47:21.206876 output: Data Size: 10808178 Bytes = 10554.86 KiB = 10.31 MiB
216 12:47:21.206992 output: Architecture: AArch64
217 12:47:21.207101 output: OS: Linux
218 12:47:21.207212 output: Load Address: 0x00000000
219 12:47:21.207325 output: Entry Point: 0x00000000
220 12:47:21.207467 output: Hash algo: crc32
221 12:47:21.207606 output: Hash value: 96f4d49d
222 12:47:21.207744 output: Image 1 (fdt-1)
223 12:47:21.207877 output: Description: mt8192-asurada-spherion-r0
224 12:47:21.208012 output: Created: Thu Jul 20 13:47:21 2023
225 12:47:21.208117 output: Type: Flat Device Tree
226 12:47:21.208222 output: Compression: uncompressed
227 12:47:21.208325 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 12:47:21.208429 output: Architecture: AArch64
229 12:47:21.208532 output: Hash algo: crc32
230 12:47:21.208636 output: Hash value: 1df858fa
231 12:47:21.208741 output: Image 2 (ramdisk-1)
232 12:47:21.208846 output: Description: unavailable
233 12:47:21.208951 output: Created: Thu Jul 20 13:47:21 2023
234 12:47:21.209056 output: Type: RAMDisk Image
235 12:47:21.209161 output: Compression: Unknown Compression
236 12:47:21.209265 output: Data Size: 47382310 Bytes = 46271.79 KiB = 45.19 MiB
237 12:47:21.209370 output: Architecture: AArch64
238 12:47:21.209474 output: OS: Linux
239 12:47:21.209576 output: Load Address: unavailable
240 12:47:21.209680 output: Entry Point: unavailable
241 12:47:21.209783 output: Hash algo: crc32
242 12:47:21.209886 output: Hash value: 8e04ce52
243 12:47:21.209989 output: Default Configuration: 'conf-1'
244 12:47:21.210094 output: Configuration 0 (conf-1)
245 12:47:21.210196 output: Description: mt8192-asurada-spherion-r0
246 12:47:21.210300 output: Kernel: kernel-1
247 12:47:21.210405 output: Init Ramdisk: ramdisk-1
248 12:47:21.210509 output: FDT: fdt-1
249 12:47:21.210615 output: Loadables: kernel-1
250 12:47:21.210730 output:
251 12:47:21.211019 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 12:47:21.211181 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 12:47:21.211387 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 12:47:21.211538 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
255 12:47:21.211668 No LXC device requested
256 12:47:21.211801 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:47:21.211949 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
258 12:47:21.212087 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:47:21.212214 Checking files for TFTP limit of 4294967296 bytes.
260 12:47:21.213026 end: 1 tftp-deploy (duration 00:00:25) [common]
261 12:47:21.213179 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:47:21.213326 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:47:21.213515 substitutions:
264 12:47:21.213630 - {DTB}: 11118904/tftp-deploy-3o_274nx/dtb/mt8192-asurada-spherion-r0.dtb
265 12:47:21.213746 - {INITRD}: 11118904/tftp-deploy-3o_274nx/ramdisk/ramdisk.cpio.gz
266 12:47:21.213852 - {KERNEL}: 11118904/tftp-deploy-3o_274nx/kernel/Image
267 12:47:21.213957 - {LAVA_MAC}: None
268 12:47:21.214062 - {PRESEED_CONFIG}: None
269 12:47:21.214166 - {PRESEED_LOCAL}: None
270 12:47:21.214271 - {RAMDISK}: 11118904/tftp-deploy-3o_274nx/ramdisk/ramdisk.cpio.gz
271 12:47:21.214375 - {ROOT_PART}: None
272 12:47:21.214478 - {ROOT}: None
273 12:47:21.214582 - {SERVER_IP}: 192.168.201.1
274 12:47:21.214719 - {TEE}: None
275 12:47:21.214822 Parsed boot commands:
276 12:47:21.214924 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:47:21.215196 Parsed boot commands: tftpboot 192.168.201.1 11118904/tftp-deploy-3o_274nx/kernel/image.itb 11118904/tftp-deploy-3o_274nx/kernel/cmdline
278 12:47:21.215341 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:47:21.215513 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:47:21.215668 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:47:21.215813 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:47:21.215937 Not connected, no need to disconnect.
283 12:47:21.216091 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:47:21.216227 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:47:21.216345 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
286 12:47:21.221169 Setting prompt string to ['lava-test: # ']
287 12:47:21.221742 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:47:21.221958 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:47:21.222116 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:47:21.222309 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:47:21.222698 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
292 12:47:26.357436 >> Command sent successfully.
293 12:47:26.359851 Returned 0 in 5 seconds
294 12:47:26.460242 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:47:26.460846 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:47:26.460944 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:47:26.461036 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:47:26.461102 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:47:26.461170 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:47:26.461443 [Enter `^Ec?' for help]
302 12:47:26.632786
303 12:47:26.632953
304 12:47:26.633027 F0: 102B 0000
305 12:47:26.633092
306 12:47:26.633152 F3: 1001 0000 [0200]
307 12:47:26.633212
308 12:47:26.636434 F3: 1001 0000
309 12:47:26.636521
310 12:47:26.636588 F7: 102D 0000
311 12:47:26.636651
312 12:47:26.636712 F1: 0000 0000
313 12:47:26.640388
314 12:47:26.640471 V0: 0000 0000 [0001]
315 12:47:26.640538
316 12:47:26.640600 00: 0007 8000
317 12:47:26.640661
318 12:47:26.643219 01: 0000 0000
319 12:47:26.643304
320 12:47:26.643371 BP: 0C00 0209 [0000]
321 12:47:26.643433
322 12:47:26.646536 G0: 1182 0000
323 12:47:26.646629
324 12:47:26.646704 EC: 0000 0021 [4000]
325 12:47:26.646762
326 12:47:26.649938 S7: 0000 0000 [0000]
327 12:47:26.650021
328 12:47:26.650088 CC: 0000 0000 [0001]
329 12:47:26.650150
330 12:47:26.653172 T0: 0000 0040 [010F]
331 12:47:26.653259
332 12:47:26.653326 Jump to BL
333 12:47:26.653388
334 12:47:26.679188
335 12:47:26.679321
336 12:47:26.679393
337 12:47:26.686379 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:47:26.690101 ARM64: Exception handlers installed.
339 12:47:26.693218 ARM64: Testing exception
340 12:47:26.696744 ARM64: Done test exception
341 12:47:26.704201 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:47:26.714151 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:47:26.720712 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:47:26.730816 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:47:26.737561 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:47:26.744415 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:47:26.756076 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:47:26.762047 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:47:26.782278 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:47:26.785682 WDT: Last reset was cold boot
351 12:47:26.788840 SPI1(PAD0) initialized at 2873684 Hz
352 12:47:26.792232 SPI5(PAD0) initialized at 992727 Hz
353 12:47:26.795438 VBOOT: Loading verstage.
354 12:47:26.802413 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:47:26.805488 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:47:26.809081 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:47:26.812663 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:47:26.819886 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:47:26.825980 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:47:26.837147 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 12:47:26.837268
362 12:47:26.837339
363 12:47:26.847205 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:47:26.850511 ARM64: Exception handlers installed.
365 12:47:26.854310 ARM64: Testing exception
366 12:47:26.854424 ARM64: Done test exception
367 12:47:26.860822 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:47:26.863624 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:47:26.878373 Probing TPM: . done!
370 12:47:26.878475 TPM ready after 0 ms
371 12:47:26.885098 Connected to device vid:did:rid of 1ae0:0028:00
372 12:47:26.894891 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 12:47:26.933106 Initialized TPM device CR50 revision 0
374 12:47:26.944820 tlcl_send_startup: Startup return code is 0
375 12:47:26.944939 TPM: setup succeeded
376 12:47:26.956614 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:47:26.965017 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:47:26.971873 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:47:26.983877 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:47:26.987282 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:47:26.990904 in-header: 03 07 00 00 08 00 00 00
382 12:47:26.994162 in-data: aa e4 47 04 13 02 00 00
383 12:47:26.997506 Chrome EC: UHEPI supported
384 12:47:27.004099 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:47:27.007596 in-header: 03 ad 00 00 08 00 00 00
386 12:47:27.010985 in-data: 00 20 20 08 00 00 00 00
387 12:47:27.011071 Phase 1
388 12:47:27.014239 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:47:27.020631 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:47:27.027139 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:47:27.030415 Recovery requested (1009000e)
392 12:47:27.034406 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:47:27.043051 tlcl_extend: response is 0
394 12:47:27.051014 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:47:27.055855 tlcl_extend: response is 0
396 12:47:27.062507 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:47:27.083371 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 12:47:27.090059 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:47:27.090163
400 12:47:27.090230
401 12:47:27.100801 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:47:27.104648 ARM64: Exception handlers installed.
403 12:47:27.104738 ARM64: Testing exception
404 12:47:27.107754 ARM64: Done test exception
405 12:47:27.129309 pmic_efuse_setting: Set efuses in 11 msecs
406 12:47:27.132699 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:47:27.140182 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:47:27.143501 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:47:27.146829 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:47:27.152988 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:47:27.156301 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:47:27.163516 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:47:27.167189 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:47:27.170274 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:47:27.177020 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:47:27.180161 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:47:27.186633 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:47:27.189906 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:47:27.193179 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:47:27.200211 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:47:27.206883 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:47:27.213473 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:47:27.216948 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:47:27.223438 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:47:27.230207 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:47:27.233556 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:47:27.240398 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:47:27.247732 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:47:27.251028 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:47:27.258403 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:47:27.262336 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:47:27.268968 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:47:27.272287 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:47:27.279312 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:47:27.282545 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:47:27.285895 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:47:27.292618 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:47:27.296171 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:47:27.303282 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:47:27.306302 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:47:27.313038 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:47:27.316223 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:47:27.323721 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:47:27.327158 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:47:27.333903 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:47:27.337196 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:47:27.341025 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:47:27.344226 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:47:27.350885 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:47:27.354236 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:47:27.357693 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:47:27.363874 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:47:27.367415 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:47:27.370790 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:47:27.376923 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:47:27.380709 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:47:27.383695 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:47:27.390780 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:47:27.400182 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:47:27.403889 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:47:27.413788 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:47:27.420122 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:47:27.426846 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:47:27.430258 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:47:27.433098 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:47:27.441220 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x32
467 12:47:27.448277 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:47:27.451714 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
469 12:47:27.607516 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:47:27.608544 [RTC]rtc_get_frequency_meter,154: input=15, output=834
471 12:47:27.609014 [RTC]rtc_get_frequency_meter,154: input=7, output=709
472 12:47:27.609451 [RTC]rtc_get_frequency_meter,154: input=11, output=772
473 12:47:27.609870 [RTC]rtc_get_frequency_meter,154: input=13, output=804
474 12:47:27.610239 [RTC]rtc_get_frequency_meter,154: input=12, output=787
475 12:47:27.610634 [RTC]rtc_get_frequency_meter,154: input=12, output=788
476 12:47:27.610938 [RTC]rtc_get_frequency_meter,154: input=13, output=803
477 12:47:27.611199 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
478 12:47:27.611683 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
479 12:47:27.612127 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 12:47:27.612547 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 12:47:27.612838 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 12:47:27.612928 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 12:47:27.613017 ADC[4]: Raw value=903031 ID=7
484 12:47:27.613105 ADC[3]: Raw value=213282 ID=1
485 12:47:27.613193 RAM Code: 0x71
486 12:47:27.613281 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 12:47:27.613370 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 12:47:27.613460 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 12:47:27.613549 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 12:47:27.613638 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 12:47:27.613726 in-header: 03 07 00 00 08 00 00 00
492 12:47:27.613813 in-data: aa e4 47 04 13 02 00 00
493 12:47:27.613899 Chrome EC: UHEPI supported
494 12:47:27.613987 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 12:47:27.614075 in-header: 03 dd 00 00 08 00 00 00
496 12:47:27.614161 in-data: 90 20 60 08 00 00 00 00
497 12:47:27.654740 MRC: failed to locate region type 0.
498 12:47:27.654959 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 12:47:27.655102 DRAM-K: Running full calibration
500 12:47:27.655230 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 12:47:27.655338 header.status = 0x0
502 12:47:27.655652 header.version = 0x6 (expected: 0x6)
503 12:47:27.655763 header.size = 0xd00 (expected: 0xd00)
504 12:47:27.655882 header.flags = 0x0
505 12:47:27.656004 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 12:47:27.661685 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
507 12:47:27.666761 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 12:47:27.669600 dram_init: ddr_geometry: 2
509 12:47:27.673106 [EMI] MDL number = 2
510 12:47:27.673251 [EMI] Get MDL freq = 0
511 12:47:27.676337 dram_init: ddr_type: 0
512 12:47:27.676499 is_discrete_lpddr4: 1
513 12:47:27.679670 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 12:47:27.679828
515 12:47:27.679960
516 12:47:27.683015 [Bian_co] ETT version 0.0.0.1
517 12:47:27.689927 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 12:47:27.690097
519 12:47:27.692766 dramc_set_vcore_voltage set vcore to 650000
520 12:47:27.696259 Read voltage for 800, 4
521 12:47:27.696451 Vio18 = 0
522 12:47:27.696581 Vcore = 650000
523 12:47:27.699652 Vdram = 0
524 12:47:27.699771 Vddq = 0
525 12:47:27.699865 Vmddr = 0
526 12:47:27.703168 dram_init: config_dvfs: 1
527 12:47:27.706626 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 12:47:27.713459 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 12:47:27.716639 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
530 12:47:27.719791 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
531 12:47:27.722860 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
532 12:47:27.726229 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
533 12:47:27.729787 MEM_TYPE=3, freq_sel=18
534 12:47:27.732867 sv_algorithm_assistance_LP4_1600
535 12:47:27.736166 ============ PULL DRAM RESETB DOWN ============
536 12:47:27.743154 ========== PULL DRAM RESETB DOWN end =========
537 12:47:27.746010 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 12:47:27.749819 ===================================
539 12:47:27.752877 LPDDR4 DRAM CONFIGURATION
540 12:47:27.756071 ===================================
541 12:47:27.756214 EX_ROW_EN[0] = 0x0
542 12:47:27.759817 EX_ROW_EN[1] = 0x0
543 12:47:27.759957 LP4Y_EN = 0x0
544 12:47:27.763002 WORK_FSP = 0x0
545 12:47:27.763139 WL = 0x2
546 12:47:27.766347 RL = 0x2
547 12:47:27.766465 BL = 0x2
548 12:47:27.769556 RPST = 0x0
549 12:47:27.769680 RD_PRE = 0x0
550 12:47:27.772475 WR_PRE = 0x1
551 12:47:27.772621 WR_PST = 0x0
552 12:47:27.775941 DBI_WR = 0x0
553 12:47:27.779640 DBI_RD = 0x0
554 12:47:27.779773 OTF = 0x1
555 12:47:27.783012 ===================================
556 12:47:27.785798 ===================================
557 12:47:27.785911 ANA top config
558 12:47:27.789228 ===================================
559 12:47:27.792517 DLL_ASYNC_EN = 0
560 12:47:27.795983 ALL_SLAVE_EN = 1
561 12:47:27.799439 NEW_RANK_MODE = 1
562 12:47:27.802672 DLL_IDLE_MODE = 1
563 12:47:27.802842 LP45_APHY_COMB_EN = 1
564 12:47:27.805851 TX_ODT_DIS = 1
565 12:47:27.809406 NEW_8X_MODE = 1
566 12:47:27.812862 ===================================
567 12:47:27.815683 ===================================
568 12:47:27.819191 data_rate = 1600
569 12:47:27.822322 CKR = 1
570 12:47:27.822483 DQ_P2S_RATIO = 8
571 12:47:27.825641 ===================================
572 12:47:27.829362 CA_P2S_RATIO = 8
573 12:47:27.832827 DQ_CA_OPEN = 0
574 12:47:27.835820 DQ_SEMI_OPEN = 0
575 12:47:27.839511 CA_SEMI_OPEN = 0
576 12:47:27.842563 CA_FULL_RATE = 0
577 12:47:27.842737 DQ_CKDIV4_EN = 1
578 12:47:27.845635 CA_CKDIV4_EN = 1
579 12:47:27.849019 CA_PREDIV_EN = 0
580 12:47:27.852382 PH8_DLY = 0
581 12:47:27.855522 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 12:47:27.858969 DQ_AAMCK_DIV = 4
583 12:47:27.859100 CA_AAMCK_DIV = 4
584 12:47:27.862428 CA_ADMCK_DIV = 4
585 12:47:27.865665 DQ_TRACK_CA_EN = 0
586 12:47:27.868944 CA_PICK = 800
587 12:47:27.872524 CA_MCKIO = 800
588 12:47:27.875785 MCKIO_SEMI = 0
589 12:47:27.879091 PLL_FREQ = 3068
590 12:47:27.879212 DQ_UI_PI_RATIO = 32
591 12:47:27.882442 CA_UI_PI_RATIO = 0
592 12:47:27.885910 ===================================
593 12:47:27.889423 ===================================
594 12:47:27.892295 memory_type:LPDDR4
595 12:47:27.895484 GP_NUM : 10
596 12:47:27.895647 SRAM_EN : 1
597 12:47:27.898960 MD32_EN : 0
598 12:47:27.902564 ===================================
599 12:47:27.902718 [ANA_INIT] >>>>>>>>>>>>>>
600 12:47:27.905804 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 12:47:27.909248 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 12:47:27.912783 ===================================
603 12:47:27.915575 data_rate = 1600,PCW = 0X7600
604 12:47:27.918858 ===================================
605 12:47:27.922391 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 12:47:27.928966 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 12:47:27.932500 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 12:47:27.938930 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 12:47:27.942481 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 12:47:27.945353 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 12:47:27.949165 [ANA_INIT] flow start
612 12:47:27.949301 [ANA_INIT] PLL >>>>>>>>
613 12:47:27.952572 [ANA_INIT] PLL <<<<<<<<
614 12:47:27.955541 [ANA_INIT] MIDPI >>>>>>>>
615 12:47:27.955670 [ANA_INIT] MIDPI <<<<<<<<
616 12:47:27.959208 [ANA_INIT] DLL >>>>>>>>
617 12:47:27.962319 [ANA_INIT] flow end
618 12:47:27.965842 ============ LP4 DIFF to SE enter ============
619 12:47:27.969020 ============ LP4 DIFF to SE exit ============
620 12:47:27.972355 [ANA_INIT] <<<<<<<<<<<<<
621 12:47:27.976084 [Flow] Enable top DCM control >>>>>
622 12:47:27.978812 [Flow] Enable top DCM control <<<<<
623 12:47:27.982215 Enable DLL master slave shuffle
624 12:47:27.985738 ==============================================================
625 12:47:27.989046 Gating Mode config
626 12:47:27.995467 ==============================================================
627 12:47:27.995623 Config description:
628 12:47:28.005404 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 12:47:28.012463 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 12:47:28.015192 SELPH_MODE 0: By rank 1: By Phase
631 12:47:28.022115 ==============================================================
632 12:47:28.025637 GAT_TRACK_EN = 1
633 12:47:28.028898 RX_GATING_MODE = 2
634 12:47:28.032316 RX_GATING_TRACK_MODE = 2
635 12:47:28.035441 SELPH_MODE = 1
636 12:47:28.038844 PICG_EARLY_EN = 1
637 12:47:28.041742 VALID_LAT_VALUE = 1
638 12:47:28.045165 ==============================================================
639 12:47:28.048549 Enter into Gating configuration >>>>
640 12:47:28.052061 Exit from Gating configuration <<<<
641 12:47:28.055750 Enter into DVFS_PRE_config >>>>>
642 12:47:28.065180 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 12:47:28.068543 Exit from DVFS_PRE_config <<<<<
644 12:47:28.071896 Enter into PICG configuration >>>>
645 12:47:28.075459 Exit from PICG configuration <<<<
646 12:47:28.078208 [RX_INPUT] configuration >>>>>
647 12:47:28.081528 [RX_INPUT] configuration <<<<<
648 12:47:28.088472 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 12:47:28.091818 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 12:47:28.099219 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 12:47:28.106050 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 12:47:28.110160 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 12:47:28.117123 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 12:47:28.120624 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 12:47:28.124586 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 12:47:28.128143 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 12:47:28.132120 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 12:47:28.135802 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 12:47:28.143172 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 12:47:28.147192 ===================================
661 12:47:28.147314 LPDDR4 DRAM CONFIGURATION
662 12:47:28.150559 ===================================
663 12:47:28.154063 EX_ROW_EN[0] = 0x0
664 12:47:28.154150 EX_ROW_EN[1] = 0x0
665 12:47:28.158072 LP4Y_EN = 0x0
666 12:47:28.158171 WORK_FSP = 0x0
667 12:47:28.161429 WL = 0x2
668 12:47:28.161505 RL = 0x2
669 12:47:28.165296 BL = 0x2
670 12:47:28.165373 RPST = 0x0
671 12:47:28.165436 RD_PRE = 0x0
672 12:47:28.169164 WR_PRE = 0x1
673 12:47:28.169249 WR_PST = 0x0
674 12:47:28.172732 DBI_WR = 0x0
675 12:47:28.172817 DBI_RD = 0x0
676 12:47:28.176139 OTF = 0x1
677 12:47:28.179933 ===================================
678 12:47:28.183736 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 12:47:28.187968 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 12:47:28.191413 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 12:47:28.195135 ===================================
682 12:47:28.198693 LPDDR4 DRAM CONFIGURATION
683 12:47:28.198818 ===================================
684 12:47:28.202362 EX_ROW_EN[0] = 0x10
685 12:47:28.205798 EX_ROW_EN[1] = 0x0
686 12:47:28.205894 LP4Y_EN = 0x0
687 12:47:28.209905 WORK_FSP = 0x0
688 12:47:28.209999 WL = 0x2
689 12:47:28.210068 RL = 0x2
690 12:47:28.213370 BL = 0x2
691 12:47:28.213458 RPST = 0x0
692 12:47:28.217361 RD_PRE = 0x0
693 12:47:28.217468 WR_PRE = 0x1
694 12:47:28.221126 WR_PST = 0x0
695 12:47:28.221216 DBI_WR = 0x0
696 12:47:28.224880 DBI_RD = 0x0
697 12:47:28.224968 OTF = 0x1
698 12:47:28.228107 ===================================
699 12:47:28.234912 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 12:47:28.238879 nWR fixed to 40
701 12:47:28.242486 [ModeRegInit_LP4] CH0 RK0
702 12:47:28.242583 [ModeRegInit_LP4] CH0 RK1
703 12:47:28.245930 [ModeRegInit_LP4] CH1 RK0
704 12:47:28.246030 [ModeRegInit_LP4] CH1 RK1
705 12:47:28.249857 match AC timing 13
706 12:47:28.253191 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 12:47:28.256648 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 12:47:28.263083 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 12:47:28.267409 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 12:47:28.270227 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 12:47:28.273565 [EMI DOE] emi_dcm 0
712 12:47:28.277186 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 12:47:28.277292 ==
714 12:47:28.280112 Dram Type= 6, Freq= 0, CH_0, rank 0
715 12:47:28.283618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 12:47:28.286624 ==
717 12:47:28.290528 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 12:47:28.296989 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 12:47:28.305805 [CA 0] Center 37 (6~68) winsize 63
720 12:47:28.308976 [CA 1] Center 36 (6~67) winsize 62
721 12:47:28.312619 [CA 2] Center 34 (4~65) winsize 62
722 12:47:28.315700 [CA 3] Center 34 (4~65) winsize 62
723 12:47:28.319496 [CA 4] Center 34 (4~64) winsize 61
724 12:47:28.322471 [CA 5] Center 33 (3~64) winsize 62
725 12:47:28.322555
726 12:47:28.326480 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 12:47:28.326564
728 12:47:28.329389 [CATrainingPosCal] consider 1 rank data
729 12:47:28.332895 u2DelayCellTimex100 = 270/100 ps
730 12:47:28.336210 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
731 12:47:28.339653 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
732 12:47:28.342878 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 12:47:28.349378 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 12:47:28.352717 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
735 12:47:28.356244 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 12:47:28.356328
737 12:47:28.359703 CA PerBit enable=1, Macro0, CA PI delay=33
738 12:47:28.359788
739 12:47:28.362527 [CBTSetCACLKResult] CA Dly = 33
740 12:47:28.362650 CS Dly: 6 (0~37)
741 12:47:28.362719 ==
742 12:47:28.366019 Dram Type= 6, Freq= 0, CH_0, rank 1
743 12:47:28.372961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 12:47:28.373047 ==
745 12:47:28.376169 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 12:47:28.382725 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 12:47:28.392011 [CA 0] Center 37 (6~68) winsize 63
748 12:47:28.395222 [CA 1] Center 37 (7~68) winsize 62
749 12:47:28.398661 [CA 2] Center 34 (4~65) winsize 62
750 12:47:28.402030 [CA 3] Center 34 (4~65) winsize 62
751 12:47:28.405473 [CA 4] Center 33 (3~64) winsize 62
752 12:47:28.408345 [CA 5] Center 33 (2~64) winsize 63
753 12:47:28.408429
754 12:47:28.411651 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 12:47:28.411735
756 12:47:28.414951 [CATrainingPosCal] consider 2 rank data
757 12:47:28.418924 u2DelayCellTimex100 = 270/100 ps
758 12:47:28.421590 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
759 12:47:28.428846 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
760 12:47:28.432252 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 12:47:28.435527 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 12:47:28.439596 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
763 12:47:28.443528 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 12:47:28.443621
765 12:47:28.446911 CA PerBit enable=1, Macro0, CA PI delay=33
766 12:47:28.447008
767 12:47:28.447077 [CBTSetCACLKResult] CA Dly = 33
768 12:47:28.450759 CS Dly: 6 (0~38)
769 12:47:28.450844
770 12:47:28.454421 ----->DramcWriteLeveling(PI) begin...
771 12:47:28.454526 ==
772 12:47:28.458305 Dram Type= 6, Freq= 0, CH_0, rank 0
773 12:47:28.461796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 12:47:28.461917 ==
775 12:47:28.465178 Write leveling (Byte 0): 33 => 33
776 12:47:28.468647 Write leveling (Byte 1): 29 => 29
777 12:47:28.472158 DramcWriteLeveling(PI) end<-----
778 12:47:28.472241
779 12:47:28.472307 ==
780 12:47:28.475008 Dram Type= 6, Freq= 0, CH_0, rank 0
781 12:47:28.478309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 12:47:28.478419 ==
783 12:47:28.481966 [Gating] SW mode calibration
784 12:47:28.488651 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 12:47:28.492140 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 12:47:28.498630 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 12:47:28.502080 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 12:47:28.505211 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 12:47:28.511959 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 12:47:28.515346 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:47:28.518545 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:47:28.524759 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:47:28.528169 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:47:28.532185 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:47:28.538408 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:47:28.541739 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:47:28.545143 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:47:28.551806 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:47:28.555358 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:47:28.558438 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:47:28.564878 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:47:28.568489 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:47:28.571825 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 12:47:28.578095 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
805 12:47:28.581612 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
806 12:47:28.584684 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:47:28.591436 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:47:28.594800 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:47:28.598266 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:47:28.604788 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:47:28.608142 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:47:28.611407 0 9 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
813 12:47:28.615118 0 9 12 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
814 12:47:28.621364 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:47:28.624868 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 12:47:28.628102 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 12:47:28.634764 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 12:47:28.637923 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 12:47:28.641153 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 0)
820 12:47:28.648271 0 10 8 | B1->B0 | 3333 2d2d | 0 0 | (0 1) (0 0)
821 12:47:28.651108 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
822 12:47:28.654575 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:47:28.661057 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:47:28.664433 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:47:28.667840 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:47:28.674709 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:47:28.678102 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:47:28.681072 0 11 8 | B1->B0 | 2828 4141 | 0 0 | (0 0) (1 1)
829 12:47:28.688157 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
830 12:47:28.691066 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:47:28.694440 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 12:47:28.701205 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 12:47:28.704286 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:47:28.707511 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:47:28.714635 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 12:47:28.717803 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 12:47:28.721033 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:47:28.727493 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:47:28.731143 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:47:28.734469 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:47:28.740733 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:47:28.744162 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:47:28.747224 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:47:28.754173 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:47:28.757424 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:47:28.760871 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:47:28.766953 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:47:28.770391 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:47:28.773871 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:47:28.780684 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:47:28.784095 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 12:47:28.787642 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 12:47:28.791217 Total UI for P1: 0, mck2ui 16
854 12:47:28.794143 best dqsien dly found for B0: ( 0, 14, 6)
855 12:47:28.797473 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 12:47:28.801426 Total UI for P1: 0, mck2ui 16
857 12:47:28.804843 best dqsien dly found for B1: ( 0, 14, 8)
858 12:47:28.808767 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 12:47:28.812132 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 12:47:28.812220
861 12:47:28.815904 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 12:47:28.819918 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 12:47:28.823335 [Gating] SW calibration Done
864 12:47:28.823422 ==
865 12:47:28.826647 Dram Type= 6, Freq= 0, CH_0, rank 0
866 12:47:28.830195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 12:47:28.830288 ==
868 12:47:28.830356 RX Vref Scan: 0
869 12:47:28.830418
870 12:47:28.834129 RX Vref 0 -> 0, step: 1
871 12:47:28.834215
872 12:47:28.838133 RX Delay -130 -> 252, step: 16
873 12:47:28.841574 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 12:47:28.844969 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 12:47:28.848169 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 12:47:28.852595 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 12:47:28.856046 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 12:47:28.859657 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 12:47:28.863391 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
880 12:47:28.870467 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
881 12:47:28.874437 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
882 12:47:28.877260 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
883 12:47:28.880822 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 12:47:28.884165 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 12:47:28.887670 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
886 12:47:28.893910 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 12:47:28.897204 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 12:47:28.901014 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 12:47:28.901115 ==
890 12:47:28.903861 Dram Type= 6, Freq= 0, CH_0, rank 0
891 12:47:28.907756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 12:47:28.907844 ==
893 12:47:28.910998 DQS Delay:
894 12:47:28.911081 DQS0 = 0, DQS1 = 0
895 12:47:28.914320 DQM Delay:
896 12:47:28.914404 DQM0 = 86, DQM1 = 74
897 12:47:28.914470 DQ Delay:
898 12:47:28.917856 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 12:47:28.921712 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
900 12:47:28.925269 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
901 12:47:28.929587 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
902 12:47:28.930095
903 12:47:28.930422
904 12:47:28.930808 ==
905 12:47:28.932727 Dram Type= 6, Freq= 0, CH_0, rank 0
906 12:47:28.936613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 12:47:28.937332 ==
908 12:47:28.937893
909 12:47:28.938337
910 12:47:28.939666 TX Vref Scan disable
911 12:47:28.943320 == TX Byte 0 ==
912 12:47:28.946578 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
913 12:47:28.950015 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
914 12:47:28.953358 == TX Byte 1 ==
915 12:47:28.956754 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 12:47:28.959873 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 12:47:28.960093 ==
918 12:47:28.962800 Dram Type= 6, Freq= 0, CH_0, rank 0
919 12:47:28.966220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 12:47:28.969641 ==
921 12:47:28.980903 TX Vref=22, minBit 3, minWin=27, winSum=439
922 12:47:28.984370 TX Vref=24, minBit 5, minWin=27, winSum=442
923 12:47:28.987559 TX Vref=26, minBit 8, minWin=27, winSum=447
924 12:47:28.991092 TX Vref=28, minBit 4, minWin=27, winSum=443
925 12:47:28.994814 TX Vref=30, minBit 8, minWin=27, winSum=448
926 12:47:29.001123 TX Vref=32, minBit 8, minWin=27, winSum=445
927 12:47:29.004358 [TxChooseVref] Worse bit 8, Min win 27, Win sum 448, Final Vref 30
928 12:47:29.004464
929 12:47:29.007784 Final TX Range 1 Vref 30
930 12:47:29.007873
931 12:47:29.007940 ==
932 12:47:29.011049 Dram Type= 6, Freq= 0, CH_0, rank 0
933 12:47:29.014422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 12:47:29.014541 ==
935 12:47:29.014670
936 12:47:29.017323
937 12:47:29.017409 TX Vref Scan disable
938 12:47:29.020694 == TX Byte 0 ==
939 12:47:29.023946 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
940 12:47:29.027879 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
941 12:47:29.030743 == TX Byte 1 ==
942 12:47:29.034177 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 12:47:29.041067 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 12:47:29.041178
945 12:47:29.041279 [DATLAT]
946 12:47:29.041372 Freq=800, CH0 RK0
947 12:47:29.041461
948 12:47:29.044041 DATLAT Default: 0xa
949 12:47:29.044125 0, 0xFFFF, sum = 0
950 12:47:29.047148 1, 0xFFFF, sum = 0
951 12:47:29.047260 2, 0xFFFF, sum = 0
952 12:47:29.050504 3, 0xFFFF, sum = 0
953 12:47:29.050655 4, 0xFFFF, sum = 0
954 12:47:29.053886 5, 0xFFFF, sum = 0
955 12:47:29.057830 6, 0xFFFF, sum = 0
956 12:47:29.057934 7, 0xFFFF, sum = 0
957 12:47:29.060467 8, 0xFFFF, sum = 0
958 12:47:29.060570 9, 0x0, sum = 1
959 12:47:29.060664 10, 0x0, sum = 2
960 12:47:29.063854 11, 0x0, sum = 3
961 12:47:29.063961 12, 0x0, sum = 4
962 12:47:29.067533 best_step = 10
963 12:47:29.067638
964 12:47:29.067730 ==
965 12:47:29.070502 Dram Type= 6, Freq= 0, CH_0, rank 0
966 12:47:29.073961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 12:47:29.074046 ==
968 12:47:29.077517 RX Vref Scan: 1
969 12:47:29.077615
970 12:47:29.077683 Set Vref Range= 32 -> 127
971 12:47:29.080789
972 12:47:29.080872 RX Vref 32 -> 127, step: 1
973 12:47:29.080938
974 12:47:29.083755 RX Delay -111 -> 252, step: 8
975 12:47:29.083864
976 12:47:29.087111 Set Vref, RX VrefLevel [Byte0]: 32
977 12:47:29.090462 [Byte1]: 32
978 12:47:29.090546
979 12:47:29.094309 Set Vref, RX VrefLevel [Byte0]: 33
980 12:47:29.097208 [Byte1]: 33
981 12:47:29.101289
982 12:47:29.101371 Set Vref, RX VrefLevel [Byte0]: 34
983 12:47:29.104622 [Byte1]: 34
984 12:47:29.109059
985 12:47:29.109143 Set Vref, RX VrefLevel [Byte0]: 35
986 12:47:29.112230 [Byte1]: 35
987 12:47:29.116656
988 12:47:29.116750 Set Vref, RX VrefLevel [Byte0]: 36
989 12:47:29.120078 [Byte1]: 36
990 12:47:29.124736
991 12:47:29.124833 Set Vref, RX VrefLevel [Byte0]: 37
992 12:47:29.128147 [Byte1]: 37
993 12:47:29.131780
994 12:47:29.131866 Set Vref, RX VrefLevel [Byte0]: 38
995 12:47:29.135275 [Byte1]: 38
996 12:47:29.139719
997 12:47:29.139813 Set Vref, RX VrefLevel [Byte0]: 39
998 12:47:29.142501 [Byte1]: 39
999 12:47:29.147139
1000 12:47:29.147265 Set Vref, RX VrefLevel [Byte0]: 40
1001 12:47:29.150450 [Byte1]: 40
1002 12:47:29.155030
1003 12:47:29.155117 Set Vref, RX VrefLevel [Byte0]: 41
1004 12:47:29.157980 [Byte1]: 41
1005 12:47:29.162502
1006 12:47:29.162652 Set Vref, RX VrefLevel [Byte0]: 42
1007 12:47:29.165777 [Byte1]: 42
1008 12:47:29.170373
1009 12:47:29.170457 Set Vref, RX VrefLevel [Byte0]: 43
1010 12:47:29.173522 [Byte1]: 43
1011 12:47:29.177633
1012 12:47:29.177718 Set Vref, RX VrefLevel [Byte0]: 44
1013 12:47:29.181372 [Byte1]: 44
1014 12:47:29.185259
1015 12:47:29.185343 Set Vref, RX VrefLevel [Byte0]: 45
1016 12:47:29.188658 [Byte1]: 45
1017 12:47:29.193182
1018 12:47:29.193304 Set Vref, RX VrefLevel [Byte0]: 46
1019 12:47:29.196152 [Byte1]: 46
1020 12:47:29.200649
1021 12:47:29.200775 Set Vref, RX VrefLevel [Byte0]: 47
1022 12:47:29.203879 [Byte1]: 47
1023 12:47:29.208412
1024 12:47:29.208570 Set Vref, RX VrefLevel [Byte0]: 48
1025 12:47:29.211442 [Byte1]: 48
1026 12:47:29.215947
1027 12:47:29.216080 Set Vref, RX VrefLevel [Byte0]: 49
1028 12:47:29.219255 [Byte1]: 49
1029 12:47:29.223849
1030 12:47:29.223932 Set Vref, RX VrefLevel [Byte0]: 50
1031 12:47:29.226764 [Byte1]: 50
1032 12:47:29.231383
1033 12:47:29.231465 Set Vref, RX VrefLevel [Byte0]: 51
1034 12:47:29.234348 [Byte1]: 51
1035 12:47:29.238771
1036 12:47:29.238859 Set Vref, RX VrefLevel [Byte0]: 52
1037 12:47:29.242050 [Byte1]: 52
1038 12:47:29.246699
1039 12:47:29.246828 Set Vref, RX VrefLevel [Byte0]: 53
1040 12:47:29.250159 [Byte1]: 53
1041 12:47:29.254077
1042 12:47:29.254203 Set Vref, RX VrefLevel [Byte0]: 54
1043 12:47:29.257477 [Byte1]: 54
1044 12:47:29.262052
1045 12:47:29.262142 Set Vref, RX VrefLevel [Byte0]: 55
1046 12:47:29.265454 [Byte1]: 55
1047 12:47:29.269487
1048 12:47:29.269599 Set Vref, RX VrefLevel [Byte0]: 56
1049 12:47:29.273019 [Byte1]: 56
1050 12:47:29.277033
1051 12:47:29.277129 Set Vref, RX VrefLevel [Byte0]: 57
1052 12:47:29.280634 [Byte1]: 57
1053 12:47:29.284839
1054 12:47:29.284964 Set Vref, RX VrefLevel [Byte0]: 58
1055 12:47:29.287899 [Byte1]: 58
1056 12:47:29.292127
1057 12:47:29.292263 Set Vref, RX VrefLevel [Byte0]: 59
1058 12:47:29.296097 [Byte1]: 59
1059 12:47:29.299810
1060 12:47:29.299942 Set Vref, RX VrefLevel [Byte0]: 60
1061 12:47:29.303283 [Byte1]: 60
1062 12:47:29.307568
1063 12:47:29.307659 Set Vref, RX VrefLevel [Byte0]: 61
1064 12:47:29.310959 [Byte1]: 61
1065 12:47:29.315547
1066 12:47:29.315680 Set Vref, RX VrefLevel [Byte0]: 62
1067 12:47:29.321822 [Byte1]: 62
1068 12:47:29.321996
1069 12:47:29.325234 Set Vref, RX VrefLevel [Byte0]: 63
1070 12:47:29.328115 [Byte1]: 63
1071 12:47:29.328200
1072 12:47:29.331542 Set Vref, RX VrefLevel [Byte0]: 64
1073 12:47:29.335094 [Byte1]: 64
1074 12:47:29.338571
1075 12:47:29.338670 Set Vref, RX VrefLevel [Byte0]: 65
1076 12:47:29.341730 [Byte1]: 65
1077 12:47:29.346232
1078 12:47:29.346349 Set Vref, RX VrefLevel [Byte0]: 66
1079 12:47:29.349150 [Byte1]: 66
1080 12:47:29.353343
1081 12:47:29.356807 Set Vref, RX VrefLevel [Byte0]: 67
1082 12:47:29.356917 [Byte1]: 67
1083 12:47:29.361753
1084 12:47:29.361871 Set Vref, RX VrefLevel [Byte0]: 68
1085 12:47:29.365285 [Byte1]: 68
1086 12:47:29.369407
1087 12:47:29.369609 Set Vref, RX VrefLevel [Byte0]: 69
1088 12:47:29.372877 [Byte1]: 69
1089 12:47:29.376401
1090 12:47:29.379812 Set Vref, RX VrefLevel [Byte0]: 70
1091 12:47:29.379901 [Byte1]: 70
1092 12:47:29.384492
1093 12:47:29.384600 Set Vref, RX VrefLevel [Byte0]: 71
1094 12:47:29.388103 [Byte1]: 71
1095 12:47:29.392187
1096 12:47:29.392286 Set Vref, RX VrefLevel [Byte0]: 72
1097 12:47:29.395211 [Byte1]: 72
1098 12:47:29.399617
1099 12:47:29.399768 Set Vref, RX VrefLevel [Byte0]: 73
1100 12:47:29.402907 [Byte1]: 73
1101 12:47:29.407026
1102 12:47:29.410484 Set Vref, RX VrefLevel [Byte0]: 74
1103 12:47:29.410663 [Byte1]: 74
1104 12:47:29.415349
1105 12:47:29.415489 Set Vref, RX VrefLevel [Byte0]: 75
1106 12:47:29.418790 [Byte1]: 75
1107 12:47:29.422457
1108 12:47:29.422617 Set Vref, RX VrefLevel [Byte0]: 76
1109 12:47:29.426204 [Byte1]: 76
1110 12:47:29.430259
1111 12:47:29.430378 Set Vref, RX VrefLevel [Byte0]: 77
1112 12:47:29.433834 [Byte1]: 77
1113 12:47:29.437924
1114 12:47:29.438061 Set Vref, RX VrefLevel [Byte0]: 78
1115 12:47:29.441444 [Byte1]: 78
1116 12:47:29.445460
1117 12:47:29.448842 Set Vref, RX VrefLevel [Byte0]: 79
1118 12:47:29.448978 [Byte1]: 79
1119 12:47:29.453705
1120 12:47:29.453835 Set Vref, RX VrefLevel [Byte0]: 80
1121 12:47:29.456438 [Byte1]: 80
1122 12:47:29.460595
1123 12:47:29.460756 Set Vref, RX VrefLevel [Byte0]: 81
1124 12:47:29.463918 [Byte1]: 81
1125 12:47:29.468454
1126 12:47:29.468584 Set Vref, RX VrefLevel [Byte0]: 82
1127 12:47:29.472050 [Byte1]: 82
1128 12:47:29.476697
1129 12:47:29.476803 Final RX Vref Byte 0 = 67 to rank0
1130 12:47:29.480165 Final RX Vref Byte 1 = 63 to rank0
1131 12:47:29.483623 Final RX Vref Byte 0 = 67 to rank1
1132 12:47:29.487378 Final RX Vref Byte 1 = 63 to rank1==
1133 12:47:29.490971 Dram Type= 6, Freq= 0, CH_0, rank 0
1134 12:47:29.495003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1135 12:47:29.495120 ==
1136 12:47:29.495193 DQS Delay:
1137 12:47:29.498537 DQS0 = 0, DQS1 = 0
1138 12:47:29.498679 DQM Delay:
1139 12:47:29.502123 DQM0 = 88, DQM1 = 75
1140 12:47:29.502243 DQ Delay:
1141 12:47:29.505745 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1142 12:47:29.509276 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1143 12:47:29.509394 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1144 12:47:29.512875 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
1145 12:47:29.516508
1146 12:47:29.516813
1147 12:47:29.523411 [DQSOSCAuto] RK0, (LSB)MR18= 0x4829, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
1148 12:47:29.526996 CH0 RK0: MR19=606, MR18=4829
1149 12:47:29.530629 CH0_RK0: MR19=0x606, MR18=0x4829, DQSOSC=391, MR23=63, INC=96, DEC=64
1150 12:47:29.530876
1151 12:47:29.534375 ----->DramcWriteLeveling(PI) begin...
1152 12:47:29.534691 ==
1153 12:47:29.537861 Dram Type= 6, Freq= 0, CH_0, rank 1
1154 12:47:29.541922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1155 12:47:29.542233 ==
1156 12:47:29.545437 Write leveling (Byte 0): 31 => 31
1157 12:47:29.549102 Write leveling (Byte 1): 30 => 30
1158 12:47:29.552868 DramcWriteLeveling(PI) end<-----
1159 12:47:29.553373
1160 12:47:29.553806 ==
1161 12:47:29.556460 Dram Type= 6, Freq= 0, CH_0, rank 1
1162 12:47:29.600511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1163 12:47:29.601071 ==
1164 12:47:29.601629 [Gating] SW mode calibration
1165 12:47:29.602478 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1166 12:47:29.602923 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1167 12:47:29.603245 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1168 12:47:29.603551 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1169 12:47:29.603846 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1170 12:47:29.604138 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:47:29.604425 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:47:29.604715 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:47:29.644756 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:47:29.645505 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:47:29.646405 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:47:29.646945 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:47:29.647424 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:47:29.647923 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:47:29.648386 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:47:29.648875 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:47:29.649323 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 12:47:29.649767 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 12:47:29.689138 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 12:47:29.690131 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1185 12:47:29.690525 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1186 12:47:29.690914 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 12:47:29.691226 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 12:47:29.691528 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 12:47:29.691881 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:47:29.692195 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:47:29.692518 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:47:29.692808 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:47:29.717679 0 9 8 | B1->B0 | 2424 2f2e | 1 1 | (0 0) (0 0)
1194 12:47:29.718479 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1195 12:47:29.719051 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 12:47:29.719860 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 12:47:29.720217 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 12:47:29.720530 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1199 12:47:29.721421 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 12:47:29.725623 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1201 12:47:29.729255 0 10 8 | B1->B0 | 2f2f 2727 | 0 0 | (0 1) (0 0)
1202 12:47:29.732494 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 12:47:29.736283 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 12:47:29.743337 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 12:47:29.747256 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 12:47:29.750661 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 12:47:29.754432 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 12:47:29.761859 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1209 12:47:29.765525 0 11 8 | B1->B0 | 3434 4545 | 0 0 | (0 0) (0 0)
1210 12:47:29.769515 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1211 12:47:29.773166 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 12:47:29.776591 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 12:47:29.783451 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 12:47:29.787835 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 12:47:29.791056 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 12:47:29.795212 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 12:47:29.798691 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1218 12:47:29.802667 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 12:47:29.810259 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 12:47:29.813694 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 12:47:29.817202 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 12:47:29.821409 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 12:47:29.824504 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 12:47:29.831636 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 12:47:29.835139 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 12:47:29.838080 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 12:47:29.844567 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 12:47:29.847888 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 12:47:29.851241 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 12:47:29.854519 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 12:47:29.861332 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 12:47:29.864640 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1233 12:47:29.867649 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1234 12:47:29.874626 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 12:47:29.877965 Total UI for P1: 0, mck2ui 16
1236 12:47:29.880963 best dqsien dly found for B0: ( 0, 14, 6)
1237 12:47:29.884368 Total UI for P1: 0, mck2ui 16
1238 12:47:29.887721 best dqsien dly found for B1: ( 0, 14, 8)
1239 12:47:29.890736 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1240 12:47:29.894203 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1241 12:47:29.894285
1242 12:47:29.897727 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1243 12:47:29.900709 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1244 12:47:29.904151 [Gating] SW calibration Done
1245 12:47:29.904242 ==
1246 12:47:29.907681 Dram Type= 6, Freq= 0, CH_0, rank 1
1247 12:47:29.910620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1248 12:47:29.910715 ==
1249 12:47:29.914122 RX Vref Scan: 0
1250 12:47:29.914210
1251 12:47:29.914308 RX Vref 0 -> 0, step: 1
1252 12:47:29.914398
1253 12:47:29.917782 RX Delay -130 -> 252, step: 16
1254 12:47:29.924286 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1255 12:47:29.927750 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1256 12:47:29.930758 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1257 12:47:29.934239 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1258 12:47:29.937553 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1259 12:47:29.944468 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1260 12:47:29.947433 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1261 12:47:29.950933 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1262 12:47:29.954249 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1263 12:47:29.957749 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1264 12:47:29.964141 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1265 12:47:29.967315 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1266 12:47:29.970639 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1267 12:47:29.974102 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1268 12:47:29.977170 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1269 12:47:29.984124 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1270 12:47:29.984448 ==
1271 12:47:29.987264 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 12:47:29.990881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 12:47:29.991131 ==
1274 12:47:29.991326 DQS Delay:
1275 12:47:29.993907 DQS0 = 0, DQS1 = 0
1276 12:47:29.994099 DQM Delay:
1277 12:47:29.997425 DQM0 = 85, DQM1 = 76
1278 12:47:29.997621 DQ Delay:
1279 12:47:30.000344 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1280 12:47:30.003687 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1281 12:47:30.007152 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1282 12:47:30.010660 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1283 12:47:30.010833
1284 12:47:30.010969
1285 12:47:30.011098 ==
1286 12:47:30.013706 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 12:47:30.017201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 12:47:30.020143 ==
1289 12:47:30.020242
1290 12:47:30.020341
1291 12:47:30.020434 TX Vref Scan disable
1292 12:47:30.023687 == TX Byte 0 ==
1293 12:47:30.027082 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1294 12:47:30.030536 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1295 12:47:30.033401 == TX Byte 1 ==
1296 12:47:30.036878 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1297 12:47:30.040284 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1298 12:47:30.043961 ==
1299 12:47:30.046836 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 12:47:30.050433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 12:47:30.050524 ==
1302 12:47:30.062823 TX Vref=22, minBit 8, minWin=27, winSum=443
1303 12:47:30.065553 TX Vref=24, minBit 8, minWin=27, winSum=445
1304 12:47:30.068994 TX Vref=26, minBit 0, minWin=28, winSum=450
1305 12:47:30.072295 TX Vref=28, minBit 9, minWin=27, winSum=450
1306 12:47:30.075768 TX Vref=30, minBit 9, minWin=27, winSum=448
1307 12:47:30.082495 TX Vref=32, minBit 9, minWin=27, winSum=448
1308 12:47:30.085982 [TxChooseVref] Worse bit 0, Min win 28, Win sum 450, Final Vref 26
1309 12:47:30.086096
1310 12:47:30.088801 Final TX Range 1 Vref 26
1311 12:47:30.088883
1312 12:47:30.088947 ==
1313 12:47:30.092386 Dram Type= 6, Freq= 0, CH_0, rank 1
1314 12:47:30.095455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1315 12:47:30.095538 ==
1316 12:47:30.098726
1317 12:47:30.098833
1318 12:47:30.098926 TX Vref Scan disable
1319 12:47:30.102072 == TX Byte 0 ==
1320 12:47:30.105631 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1321 12:47:30.112244 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1322 12:47:30.112343 == TX Byte 1 ==
1323 12:47:30.115775 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1324 12:47:30.122242 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1325 12:47:30.122330
1326 12:47:30.122395 [DATLAT]
1327 12:47:30.122455 Freq=800, CH0 RK1
1328 12:47:30.122514
1329 12:47:30.125904 DATLAT Default: 0xa
1330 12:47:30.126086 0, 0xFFFF, sum = 0
1331 12:47:30.128722 1, 0xFFFF, sum = 0
1332 12:47:30.132277 2, 0xFFFF, sum = 0
1333 12:47:30.132439 3, 0xFFFF, sum = 0
1334 12:47:30.135579 4, 0xFFFF, sum = 0
1335 12:47:30.135689 5, 0xFFFF, sum = 0
1336 12:47:30.138975 6, 0xFFFF, sum = 0
1337 12:47:30.139059 7, 0xFFFF, sum = 0
1338 12:47:30.142737 8, 0xFFFF, sum = 0
1339 12:47:30.142899 9, 0x0, sum = 1
1340 12:47:30.145540 10, 0x0, sum = 2
1341 12:47:30.145699 11, 0x0, sum = 3
1342 12:47:30.145773 12, 0x0, sum = 4
1343 12:47:30.149242 best_step = 10
1344 12:47:30.149662
1345 12:47:30.149989 ==
1346 12:47:30.152173 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 12:47:30.155602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 12:47:30.156022 ==
1349 12:47:30.158989 RX Vref Scan: 0
1350 12:47:30.159399
1351 12:47:30.159728 RX Vref 0 -> 0, step: 1
1352 12:47:30.162369
1353 12:47:30.162858 RX Delay -95 -> 252, step: 8
1354 12:47:30.169081 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1355 12:47:30.172613 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1356 12:47:30.175983 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1357 12:47:30.179325 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1358 12:47:30.182759 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1359 12:47:30.189268 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1360 12:47:30.192815 iDelay=217, Bit 6, Center 96 (-15 ~ 208) 224
1361 12:47:30.196118 iDelay=217, Bit 7, Center 100 (-15 ~ 216) 232
1362 12:47:30.199482 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1363 12:47:30.202587 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1364 12:47:30.209357 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1365 12:47:30.212500 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1366 12:47:30.215587 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1367 12:47:30.219165 iDelay=217, Bit 13, Center 80 (-31 ~ 192) 224
1368 12:47:30.225298 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1369 12:47:30.228885 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1370 12:47:30.229017 ==
1371 12:47:30.232449 Dram Type= 6, Freq= 0, CH_0, rank 1
1372 12:47:30.235372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1373 12:47:30.235487 ==
1374 12:47:30.235577 DQS Delay:
1375 12:47:30.238889 DQS0 = 0, DQS1 = 0
1376 12:47:30.239059 DQM Delay:
1377 12:47:30.242414 DQM0 = 86, DQM1 = 76
1378 12:47:30.242588 DQ Delay:
1379 12:47:30.245433 DQ0 =84, DQ1 =92, DQ2 =76, DQ3 =80
1380 12:47:30.249098 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =100
1381 12:47:30.252657 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1382 12:47:30.255480 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1383 12:47:30.255909
1384 12:47:30.256347
1385 12:47:30.265743 [DQSOSCAuto] RK1, (LSB)MR18= 0x4208, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1386 12:47:30.266179 CH0 RK1: MR19=606, MR18=4208
1387 12:47:30.271929 CH0_RK1: MR19=0x606, MR18=0x4208, DQSOSC=393, MR23=63, INC=95, DEC=63
1388 12:47:30.275711 [RxdqsGatingPostProcess] freq 800
1389 12:47:30.282070 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1390 12:47:30.285483 Pre-setting of DQS Precalculation
1391 12:47:30.289006 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1392 12:47:30.289447 ==
1393 12:47:30.291787 Dram Type= 6, Freq= 0, CH_1, rank 0
1394 12:47:30.298659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 12:47:30.299109 ==
1396 12:47:30.302197 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1397 12:47:30.308913 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1398 12:47:30.317534 [CA 0] Center 36 (6~67) winsize 62
1399 12:47:30.321496 [CA 1] Center 36 (6~67) winsize 62
1400 12:47:30.324313 [CA 2] Center 34 (4~65) winsize 62
1401 12:47:30.327540 [CA 3] Center 34 (3~65) winsize 63
1402 12:47:30.330641 [CA 4] Center 34 (4~65) winsize 62
1403 12:47:30.333972 [CA 5] Center 34 (3~65) winsize 63
1404 12:47:30.334113
1405 12:47:30.337457 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1406 12:47:30.337578
1407 12:47:30.340476 [CATrainingPosCal] consider 1 rank data
1408 12:47:30.343899 u2DelayCellTimex100 = 270/100 ps
1409 12:47:30.347734 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1410 12:47:30.354069 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1411 12:47:30.356988 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1412 12:47:30.360546 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1413 12:47:30.363664 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1414 12:47:30.366820 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1415 12:47:30.366902
1416 12:47:30.370435 CA PerBit enable=1, Macro0, CA PI delay=34
1417 12:47:30.370542
1418 12:47:30.373595 [CBTSetCACLKResult] CA Dly = 34
1419 12:47:30.376946 CS Dly: 5 (0~36)
1420 12:47:30.377106 ==
1421 12:47:30.380276 Dram Type= 6, Freq= 0, CH_1, rank 1
1422 12:47:30.383374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1423 12:47:30.383530 ==
1424 12:47:30.390567 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1425 12:47:30.394031 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1426 12:47:30.403882 [CA 0] Center 36 (6~67) winsize 62
1427 12:47:30.407483 [CA 1] Center 36 (6~67) winsize 62
1428 12:47:30.410870 [CA 2] Center 34 (4~65) winsize 62
1429 12:47:30.413968 [CA 3] Center 34 (3~65) winsize 63
1430 12:47:30.417462 [CA 4] Center 34 (4~65) winsize 62
1431 12:47:30.420952 [CA 5] Center 34 (3~65) winsize 63
1432 12:47:30.421466
1433 12:47:30.424231 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1434 12:47:30.424779
1435 12:47:30.427129 [CATrainingPosCal] consider 2 rank data
1436 12:47:30.430242 u2DelayCellTimex100 = 270/100 ps
1437 12:47:30.433873 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1438 12:47:30.440791 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1439 12:47:30.444033 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1440 12:47:30.446902 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1441 12:47:30.450341 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1442 12:47:30.453783 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1443 12:47:30.454099
1444 12:47:30.456627 CA PerBit enable=1, Macro0, CA PI delay=34
1445 12:47:30.456895
1446 12:47:30.460044 [CBTSetCACLKResult] CA Dly = 34
1447 12:47:30.460280 CS Dly: 6 (0~38)
1448 12:47:30.463700
1449 12:47:30.466772 ----->DramcWriteLeveling(PI) begin...
1450 12:47:30.466932 ==
1451 12:47:30.469852 Dram Type= 6, Freq= 0, CH_1, rank 0
1452 12:47:30.473240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1453 12:47:30.473382 ==
1454 12:47:30.476800 Write leveling (Byte 0): 28 => 28
1455 12:47:30.479707 Write leveling (Byte 1): 29 => 29
1456 12:47:30.483281 DramcWriteLeveling(PI) end<-----
1457 12:47:30.483392
1458 12:47:30.483501 ==
1459 12:47:30.486753 Dram Type= 6, Freq= 0, CH_1, rank 0
1460 12:47:30.489466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1461 12:47:30.489563 ==
1462 12:47:30.493228 [Gating] SW mode calibration
1463 12:47:30.499529 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1464 12:47:30.506438 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1465 12:47:30.509823 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1466 12:47:30.512682 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1467 12:47:30.519401 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1468 12:47:30.523152 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:47:30.526021 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:47:30.533048 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:47:30.535881 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:47:30.539393 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:47:30.545935 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:47:30.549145 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:47:30.552901 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:47:30.559275 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:47:30.562791 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:47:30.566205 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:47:30.569105 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 12:47:30.575943 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 12:47:30.579419 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1482 12:47:30.582929 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1483 12:47:30.589315 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 12:47:30.592137 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 12:47:30.595536 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:47:30.602249 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:47:30.605749 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:47:30.608676 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:47:30.615561 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:47:30.619013 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:47:30.621886 0 9 8 | B1->B0 | 2c2c 3030 | 1 1 | (1 1) (1 1)
1492 12:47:30.629131 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 12:47:30.631914 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 12:47:30.635630 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 12:47:30.641874 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 12:47:30.645358 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 12:47:30.648635 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1498 12:47:30.655480 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1499 12:47:30.658609 0 10 8 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
1500 12:47:30.661888 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 12:47:30.668662 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 12:47:30.672174 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 12:47:30.675052 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 12:47:30.681941 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 12:47:30.684929 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 12:47:30.688437 0 11 4 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
1507 12:47:30.694893 0 11 8 | B1->B0 | 3939 4040 | 1 0 | (0 0) (1 1)
1508 12:47:30.698385 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 12:47:30.701825 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 12:47:30.708726 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 12:47:30.711903 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 12:47:30.714890 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 12:47:30.721663 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 12:47:30.725152 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1515 12:47:30.728135 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:47:30.735074 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:47:30.738456 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 12:47:30.741616 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 12:47:30.748373 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 12:47:30.751763 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 12:47:30.755053 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 12:47:30.761438 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 12:47:30.764643 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 12:47:30.768117 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 12:47:30.771309 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 12:47:30.777870 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 12:47:30.781219 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 12:47:30.784654 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 12:47:30.791128 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 12:47:30.794549 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1531 12:47:30.798110 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1532 12:47:30.801560 Total UI for P1: 0, mck2ui 16
1533 12:47:30.804881 best dqsien dly found for B0: ( 0, 14, 4)
1534 12:47:30.811506 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 12:47:30.814369 Total UI for P1: 0, mck2ui 16
1536 12:47:30.817870 best dqsien dly found for B1: ( 0, 14, 8)
1537 12:47:30.821624 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1538 12:47:30.824660 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1539 12:47:30.824756
1540 12:47:30.827695 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1541 12:47:30.830889 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1542 12:47:30.834338 [Gating] SW calibration Done
1543 12:47:30.834445 ==
1544 12:47:30.837990 Dram Type= 6, Freq= 0, CH_1, rank 0
1545 12:47:30.841073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1546 12:47:30.841231 ==
1547 12:47:30.844294 RX Vref Scan: 0
1548 12:47:30.844383
1549 12:47:30.844449 RX Vref 0 -> 0, step: 1
1550 12:47:30.844510
1551 12:47:30.847892 RX Delay -130 -> 252, step: 16
1552 12:47:30.854175 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1553 12:47:30.857714 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1554 12:47:30.860919 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1555 12:47:30.864604 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1556 12:47:30.867777 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1557 12:47:30.874232 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1558 12:47:30.877524 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1559 12:47:30.881017 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1560 12:47:30.884093 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1561 12:47:30.887861 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1562 12:47:30.894415 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1563 12:47:30.897952 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1564 12:47:30.900810 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1565 12:47:30.904315 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1566 12:47:30.907728 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1567 12:47:30.913992 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1568 12:47:30.914193 ==
1569 12:47:30.917509 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 12:47:30.920966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 12:47:30.921129 ==
1572 12:47:30.921264 DQS Delay:
1573 12:47:30.924443 DQS0 = 0, DQS1 = 0
1574 12:47:30.924591 DQM Delay:
1575 12:47:30.927383 DQM0 = 89, DQM1 = 80
1576 12:47:30.927529 DQ Delay:
1577 12:47:30.930795 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1578 12:47:30.933920 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1579 12:47:30.937551 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1580 12:47:30.941000 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1581 12:47:30.941166
1582 12:47:30.941301
1583 12:47:30.941428 ==
1584 12:47:30.944116 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 12:47:30.947043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 12:47:30.950570 ==
1587 12:47:30.950776
1588 12:47:30.950911
1589 12:47:30.951038 TX Vref Scan disable
1590 12:47:30.954042 == TX Byte 0 ==
1591 12:47:30.956978 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1592 12:47:30.960384 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1593 12:47:30.963601 == TX Byte 1 ==
1594 12:47:30.967245 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1595 12:47:30.970517 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1596 12:47:30.974033 ==
1597 12:47:30.974231 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 12:47:30.980747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 12:47:30.980945 ==
1600 12:47:30.992771 TX Vref=22, minBit 10, minWin=26, winSum=443
1601 12:47:30.995686 TX Vref=24, minBit 8, minWin=27, winSum=448
1602 12:47:30.999192 TX Vref=26, minBit 9, minWin=27, winSum=449
1603 12:47:31.002634 TX Vref=28, minBit 10, minWin=27, winSum=450
1604 12:47:31.006230 TX Vref=30, minBit 13, minWin=27, winSum=453
1605 12:47:31.012422 TX Vref=32, minBit 8, minWin=27, winSum=446
1606 12:47:31.015901 [TxChooseVref] Worse bit 13, Min win 27, Win sum 453, Final Vref 30
1607 12:47:31.016082
1608 12:47:31.018888 Final TX Range 1 Vref 30
1609 12:47:31.019043
1610 12:47:31.019175 ==
1611 12:47:31.022443 Dram Type= 6, Freq= 0, CH_1, rank 0
1612 12:47:31.025935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1613 12:47:31.028784 ==
1614 12:47:31.028948
1615 12:47:31.029083
1616 12:47:31.029210 TX Vref Scan disable
1617 12:47:31.032943 == TX Byte 0 ==
1618 12:47:31.036414 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1619 12:47:31.039564 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1620 12:47:31.042753 == TX Byte 1 ==
1621 12:47:31.045993 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1622 12:47:31.049520 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1623 12:47:31.052614
1624 12:47:31.052776 [DATLAT]
1625 12:47:31.052913 Freq=800, CH1 RK0
1626 12:47:31.053042
1627 12:47:31.056011 DATLAT Default: 0xa
1628 12:47:31.056169 0, 0xFFFF, sum = 0
1629 12:47:31.059526 1, 0xFFFF, sum = 0
1630 12:47:31.059679 2, 0xFFFF, sum = 0
1631 12:47:31.062991 3, 0xFFFF, sum = 0
1632 12:47:31.063152 4, 0xFFFF, sum = 0
1633 12:47:31.065951 5, 0xFFFF, sum = 0
1634 12:47:31.069422 6, 0xFFFF, sum = 0
1635 12:47:31.069590 7, 0xFFFF, sum = 0
1636 12:47:31.072769 8, 0xFFFF, sum = 0
1637 12:47:31.072923 9, 0x0, sum = 1
1638 12:47:31.073060 10, 0x0, sum = 2
1639 12:47:31.076254 11, 0x0, sum = 3
1640 12:47:31.076404 12, 0x0, sum = 4
1641 12:47:31.079589 best_step = 10
1642 12:47:31.079727
1643 12:47:31.079858 ==
1644 12:47:31.082552 Dram Type= 6, Freq= 0, CH_1, rank 0
1645 12:47:31.086032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1646 12:47:31.086189 ==
1647 12:47:31.089918 RX Vref Scan: 1
1648 12:47:31.090081
1649 12:47:31.090217 Set Vref Range= 32 -> 127
1650 12:47:31.090345
1651 12:47:31.092837 RX Vref 32 -> 127, step: 1
1652 12:47:31.092983
1653 12:47:31.096291 RX Delay -95 -> 252, step: 8
1654 12:47:31.096438
1655 12:47:31.099637 Set Vref, RX VrefLevel [Byte0]: 32
1656 12:47:31.103295 [Byte1]: 32
1657 12:47:31.103474
1658 12:47:31.106271 Set Vref, RX VrefLevel [Byte0]: 33
1659 12:47:31.109098 [Byte1]: 33
1660 12:47:31.113192
1661 12:47:31.113376 Set Vref, RX VrefLevel [Byte0]: 34
1662 12:47:31.116521 [Byte1]: 34
1663 12:47:31.120655
1664 12:47:31.120826 Set Vref, RX VrefLevel [Byte0]: 35
1665 12:47:31.124166 [Byte1]: 35
1666 12:47:31.128236
1667 12:47:31.128411 Set Vref, RX VrefLevel [Byte0]: 36
1668 12:47:31.131646 [Byte1]: 36
1669 12:47:31.135645
1670 12:47:31.135844 Set Vref, RX VrefLevel [Byte0]: 37
1671 12:47:31.139234 [Byte1]: 37
1672 12:47:31.143413
1673 12:47:31.143628 Set Vref, RX VrefLevel [Byte0]: 38
1674 12:47:31.161728 [Byte1]: 38
1675 12:47:31.161874
1676 12:47:31.161940 Set Vref, RX VrefLevel [Byte0]: 39
1677 12:47:31.162002 [Byte1]: 39
1678 12:47:31.162075
1679 12:47:31.162182 Set Vref, RX VrefLevel [Byte0]: 40
1680 12:47:31.162459 [Byte1]: 40
1681 12:47:31.166232
1682 12:47:31.166416 Set Vref, RX VrefLevel [Byte0]: 41
1683 12:47:31.169823 [Byte1]: 41
1684 12:47:31.173981
1685 12:47:31.174191 Set Vref, RX VrefLevel [Byte0]: 42
1686 12:47:31.177214 [Byte1]: 42
1687 12:47:31.181523
1688 12:47:31.181747 Set Vref, RX VrefLevel [Byte0]: 43
1689 12:47:31.184808 [Byte1]: 43
1690 12:47:31.189085
1691 12:47:31.189319 Set Vref, RX VrefLevel [Byte0]: 44
1692 12:47:31.192178 [Byte1]: 44
1693 12:47:31.196820
1694 12:47:31.197018 Set Vref, RX VrefLevel [Byte0]: 45
1695 12:47:31.199751 [Byte1]: 45
1696 12:47:31.204376
1697 12:47:31.204620 Set Vref, RX VrefLevel [Byte0]: 46
1698 12:47:31.207585 [Byte1]: 46
1699 12:47:31.212703
1700 12:47:31.212890 Set Vref, RX VrefLevel [Byte0]: 47
1701 12:47:31.215103 [Byte1]: 47
1702 12:47:31.219520
1703 12:47:31.219721 Set Vref, RX VrefLevel [Byte0]: 48
1704 12:47:31.222701 [Byte1]: 48
1705 12:47:31.227035
1706 12:47:31.227186 Set Vref, RX VrefLevel [Byte0]: 49
1707 12:47:31.230516 [Byte1]: 49
1708 12:47:31.234521
1709 12:47:31.234689 Set Vref, RX VrefLevel [Byte0]: 50
1710 12:47:31.238086 [Byte1]: 50
1711 12:47:31.242210
1712 12:47:31.242349 Set Vref, RX VrefLevel [Byte0]: 51
1713 12:47:31.245767 [Byte1]: 51
1714 12:47:31.249841
1715 12:47:31.249982 Set Vref, RX VrefLevel [Byte0]: 52
1716 12:47:31.253219 [Byte1]: 52
1717 12:47:31.257329
1718 12:47:31.257457 Set Vref, RX VrefLevel [Byte0]: 53
1719 12:47:31.260712 [Byte1]: 53
1720 12:47:31.264940
1721 12:47:31.265080 Set Vref, RX VrefLevel [Byte0]: 54
1722 12:47:31.268425 [Byte1]: 54
1723 12:47:31.272723
1724 12:47:31.272900 Set Vref, RX VrefLevel [Byte0]: 55
1725 12:47:31.275778 [Byte1]: 55
1726 12:47:31.280488
1727 12:47:31.280634 Set Vref, RX VrefLevel [Byte0]: 56
1728 12:47:31.283845 [Byte1]: 56
1729 12:47:31.287699
1730 12:47:31.287868 Set Vref, RX VrefLevel [Byte0]: 57
1731 12:47:31.291367 [Byte1]: 57
1732 12:47:31.295270
1733 12:47:31.295408 Set Vref, RX VrefLevel [Byte0]: 58
1734 12:47:31.298897 [Byte1]: 58
1735 12:47:31.302834
1736 12:47:31.302978 Set Vref, RX VrefLevel [Byte0]: 59
1737 12:47:31.306337 [Byte1]: 59
1738 12:47:31.310470
1739 12:47:31.310682 Set Vref, RX VrefLevel [Byte0]: 60
1740 12:47:31.313968 [Byte1]: 60
1741 12:47:31.318029
1742 12:47:31.318228 Set Vref, RX VrefLevel [Byte0]: 61
1743 12:47:31.321766 [Byte1]: 61
1744 12:47:31.325691
1745 12:47:31.325918 Set Vref, RX VrefLevel [Byte0]: 62
1746 12:47:31.329184 [Byte1]: 62
1747 12:47:31.333442
1748 12:47:31.333649 Set Vref, RX VrefLevel [Byte0]: 63
1749 12:47:31.336798 [Byte1]: 63
1750 12:47:31.340953
1751 12:47:31.344291 Set Vref, RX VrefLevel [Byte0]: 64
1752 12:47:31.347170 [Byte1]: 64
1753 12:47:31.347338
1754 12:47:31.350780 Set Vref, RX VrefLevel [Byte0]: 65
1755 12:47:31.354238 [Byte1]: 65
1756 12:47:31.354392
1757 12:47:31.357210 Set Vref, RX VrefLevel [Byte0]: 66
1758 12:47:31.360635 [Byte1]: 66
1759 12:47:31.360806
1760 12:47:31.364054 Set Vref, RX VrefLevel [Byte0]: 67
1761 12:47:31.367525 [Byte1]: 67
1762 12:47:31.371108
1763 12:47:31.371303 Set Vref, RX VrefLevel [Byte0]: 68
1764 12:47:31.374549 [Byte1]: 68
1765 12:47:31.379206
1766 12:47:31.379399 Set Vref, RX VrefLevel [Byte0]: 69
1767 12:47:31.382114 [Byte1]: 69
1768 12:47:31.386563
1769 12:47:31.386752 Set Vref, RX VrefLevel [Byte0]: 70
1770 12:47:31.389642 [Byte1]: 70
1771 12:47:31.393958
1772 12:47:31.394142 Set Vref, RX VrefLevel [Byte0]: 71
1773 12:47:31.397837 [Byte1]: 71
1774 12:47:31.401726
1775 12:47:31.401893 Set Vref, RX VrefLevel [Byte0]: 72
1776 12:47:31.405025 [Byte1]: 72
1777 12:47:31.409241
1778 12:47:31.409432 Set Vref, RX VrefLevel [Byte0]: 73
1779 12:47:31.412695 [Byte1]: 73
1780 12:47:31.416771
1781 12:47:31.416973 Set Vref, RX VrefLevel [Byte0]: 74
1782 12:47:31.420222 [Byte1]: 74
1783 12:47:31.424556
1784 12:47:31.424743 Set Vref, RX VrefLevel [Byte0]: 75
1785 12:47:31.427660 [Byte1]: 75
1786 12:47:31.432142
1787 12:47:31.432319 Set Vref, RX VrefLevel [Byte0]: 76
1788 12:47:31.435336 [Byte1]: 76
1789 12:47:31.439670
1790 12:47:31.442965 Set Vref, RX VrefLevel [Byte0]: 77
1791 12:47:31.446556 [Byte1]: 77
1792 12:47:31.446759
1793 12:47:31.449400 Set Vref, RX VrefLevel [Byte0]: 78
1794 12:47:31.452807 [Byte1]: 78
1795 12:47:31.453013
1796 12:47:31.455915 Final RX Vref Byte 0 = 55 to rank0
1797 12:47:31.459496 Final RX Vref Byte 1 = 66 to rank0
1798 12:47:31.462968 Final RX Vref Byte 0 = 55 to rank1
1799 12:47:31.466358 Final RX Vref Byte 1 = 66 to rank1==
1800 12:47:31.469547 Dram Type= 6, Freq= 0, CH_1, rank 0
1801 12:47:31.472806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 12:47:31.473004 ==
1803 12:47:31.476199 DQS Delay:
1804 12:47:31.476392 DQS0 = 0, DQS1 = 0
1805 12:47:31.476530 DQM Delay:
1806 12:47:31.479222 DQM0 = 86, DQM1 = 78
1807 12:47:31.479380 DQ Delay:
1808 12:47:31.482652 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1809 12:47:31.486135 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =80
1810 12:47:31.489649 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1811 12:47:31.492616 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1812 12:47:31.492816
1813 12:47:31.492956
1814 12:47:31.502735 [DQSOSCAuto] RK0, (LSB)MR18= 0x3622, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1815 12:47:31.506033 CH1 RK0: MR19=606, MR18=3622
1816 12:47:31.509013 CH1_RK0: MR19=0x606, MR18=0x3622, DQSOSC=396, MR23=63, INC=94, DEC=62
1817 12:47:31.509133
1818 12:47:31.512715 ----->DramcWriteLeveling(PI) begin...
1819 12:47:31.515821 ==
1820 12:47:31.519165 Dram Type= 6, Freq= 0, CH_1, rank 1
1821 12:47:31.522470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1822 12:47:31.522704 ==
1823 12:47:31.526175 Write leveling (Byte 0): 27 => 27
1824 12:47:31.529408 Write leveling (Byte 1): 29 => 29
1825 12:47:31.532534 DramcWriteLeveling(PI) end<-----
1826 12:47:31.532725
1827 12:47:31.532856 ==
1828 12:47:31.535864 Dram Type= 6, Freq= 0, CH_1, rank 1
1829 12:47:31.538932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1830 12:47:31.539111 ==
1831 12:47:31.542446 [Gating] SW mode calibration
1832 12:47:31.548981 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1833 12:47:31.555867 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1834 12:47:31.558623 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1835 12:47:31.562410 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1836 12:47:31.565572 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 12:47:31.572500 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 12:47:31.575435 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 12:47:31.579007 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 12:47:31.585389 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 12:47:31.588967 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:47:31.591934 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:47:31.598940 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:47:31.601921 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:47:31.605377 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 12:47:31.612127 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 12:47:31.615109 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 12:47:31.618511 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 12:47:31.624958 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 12:47:31.628425 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 12:47:31.631568 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1852 12:47:31.638769 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1853 12:47:31.642005 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 12:47:31.644973 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 12:47:31.651651 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 12:47:31.654987 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 12:47:31.658434 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 12:47:31.665094 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 12:47:31.668592 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 12:47:31.671760 0 9 8 | B1->B0 | 3333 2727 | 1 0 | (1 1) (0 0)
1861 12:47:31.678155 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1862 12:47:31.681635 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1863 12:47:31.685176 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1864 12:47:31.691639 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1865 12:47:31.695201 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1866 12:47:31.698082 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1867 12:47:31.705033 0 10 4 | B1->B0 | 3131 3333 | 1 1 | (1 0) (1 0)
1868 12:47:31.708160 0 10 8 | B1->B0 | 2626 2f2f | 0 1 | (0 0) (1 0)
1869 12:47:31.711392 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 12:47:31.714777 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 12:47:31.721702 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 12:47:31.724725 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 12:47:31.728225 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 12:47:31.734711 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 12:47:31.738014 0 11 4 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1876 12:47:31.741500 0 11 8 | B1->B0 | 4545 3e3e | 0 0 | (0 0) (0 0)
1877 12:47:31.748123 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 12:47:31.751654 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 12:47:31.754955 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 12:47:31.761284 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 12:47:31.764525 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 12:47:31.768103 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1883 12:47:31.774663 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1884 12:47:31.777803 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 12:47:31.781257 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 12:47:31.788017 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 12:47:31.791029 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 12:47:31.794447 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 12:47:31.801513 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 12:47:31.804514 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 12:47:31.807888 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 12:47:31.814418 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 12:47:31.817745 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 12:47:31.821207 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 12:47:31.827538 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 12:47:31.831045 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 12:47:31.834534 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 12:47:31.840905 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 12:47:31.844379 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1900 12:47:31.847881 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1901 12:47:31.851149 Total UI for P1: 0, mck2ui 16
1902 12:47:31.854575 best dqsien dly found for B0: ( 0, 14, 4)
1903 12:47:31.857764 Total UI for P1: 0, mck2ui 16
1904 12:47:31.861124 best dqsien dly found for B1: ( 0, 14, 4)
1905 12:47:31.864157 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1906 12:47:31.867667 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1907 12:47:31.867882
1908 12:47:31.870541 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1909 12:47:31.877491 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1910 12:47:31.877714 [Gating] SW calibration Done
1911 12:47:31.877857 ==
1912 12:47:31.880756 Dram Type= 6, Freq= 0, CH_1, rank 1
1913 12:47:31.887514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1914 12:47:31.887738 ==
1915 12:47:31.887876 RX Vref Scan: 0
1916 12:47:31.887996
1917 12:47:31.890709 RX Vref 0 -> 0, step: 1
1918 12:47:31.890862
1919 12:47:31.893854 RX Delay -130 -> 252, step: 16
1920 12:47:31.897227 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1921 12:47:31.900777 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1922 12:47:31.904200 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1923 12:47:31.910728 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1924 12:47:31.914233 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1925 12:47:31.917091 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1926 12:47:31.920600 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1927 12:47:31.923808 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1928 12:47:31.930276 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1929 12:47:31.933803 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1930 12:47:31.936806 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1931 12:47:31.940293 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1932 12:47:31.943812 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1933 12:47:31.950559 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1934 12:47:31.953554 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1935 12:47:31.956817 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1936 12:47:31.956950 ==
1937 12:47:31.960358 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 12:47:31.963834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 12:47:31.966851 ==
1940 12:47:31.967000 DQS Delay:
1941 12:47:31.967078 DQS0 = 0, DQS1 = 0
1942 12:47:31.970302 DQM Delay:
1943 12:47:31.970430 DQM0 = 87, DQM1 = 80
1944 12:47:31.973884 DQ Delay:
1945 12:47:31.977085 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1946 12:47:31.977231 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1947 12:47:31.980486 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1948 12:47:31.986802 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1949 12:47:31.986956
1950 12:47:31.987030
1951 12:47:31.987091 ==
1952 12:47:31.990252 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 12:47:31.993531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 12:47:31.993671 ==
1955 12:47:31.993741
1956 12:47:31.993802
1957 12:47:31.996716 TX Vref Scan disable
1958 12:47:31.996835 == TX Byte 0 ==
1959 12:47:32.003210 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1960 12:47:32.006525 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1961 12:47:32.006700 == TX Byte 1 ==
1962 12:47:32.013539 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1963 12:47:32.016382 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1964 12:47:32.016532 ==
1965 12:47:32.019866 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 12:47:32.023434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 12:47:32.023577 ==
1968 12:47:32.037126 TX Vref=22, minBit 9, minWin=26, winSum=444
1969 12:47:32.040083 TX Vref=24, minBit 9, minWin=27, winSum=449
1970 12:47:32.043631 TX Vref=26, minBit 8, minWin=27, winSum=447
1971 12:47:32.047018 TX Vref=28, minBit 8, minWin=27, winSum=449
1972 12:47:32.050284 TX Vref=30, minBit 0, minWin=28, winSum=449
1973 12:47:32.056742 TX Vref=32, minBit 8, minWin=27, winSum=451
1974 12:47:32.060119 [TxChooseVref] Worse bit 0, Min win 28, Win sum 449, Final Vref 30
1975 12:47:32.060267
1976 12:47:32.063600 Final TX Range 1 Vref 30
1977 12:47:32.063737
1978 12:47:32.063808 ==
1979 12:47:32.067133 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 12:47:32.070071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 12:47:32.073007 ==
1982 12:47:32.073142
1983 12:47:32.073215
1984 12:47:32.073280 TX Vref Scan disable
1985 12:47:32.077116 == TX Byte 0 ==
1986 12:47:32.080553 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1987 12:47:32.084099 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1988 12:47:32.086939 == TX Byte 1 ==
1989 12:47:32.090255 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1990 12:47:32.093928 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1991 12:47:32.097179
1992 12:47:32.097362 [DATLAT]
1993 12:47:32.097438 Freq=800, CH1 RK1
1994 12:47:32.097502
1995 12:47:32.100630 DATLAT Default: 0xa
1996 12:47:32.100757 0, 0xFFFF, sum = 0
1997 12:47:32.103540 1, 0xFFFF, sum = 0
1998 12:47:32.103664 2, 0xFFFF, sum = 0
1999 12:47:32.107046 3, 0xFFFF, sum = 0
2000 12:47:32.107190 4, 0xFFFF, sum = 0
2001 12:47:32.110387 5, 0xFFFF, sum = 0
2002 12:47:32.113801 6, 0xFFFF, sum = 0
2003 12:47:32.113949 7, 0xFFFF, sum = 0
2004 12:47:32.117159 8, 0xFFFF, sum = 0
2005 12:47:32.117252 9, 0x0, sum = 1
2006 12:47:32.117321 10, 0x0, sum = 2
2007 12:47:32.120439 11, 0x0, sum = 3
2008 12:47:32.120557 12, 0x0, sum = 4
2009 12:47:32.123542 best_step = 10
2010 12:47:32.123672
2011 12:47:32.123740 ==
2012 12:47:32.127003 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 12:47:32.130148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 12:47:32.130290 ==
2015 12:47:32.133574 RX Vref Scan: 0
2016 12:47:32.133740
2017 12:47:32.133844 RX Vref 0 -> 0, step: 1
2018 12:47:32.133935
2019 12:47:32.137062 RX Delay -95 -> 252, step: 8
2020 12:47:32.143564 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2021 12:47:32.147098 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2022 12:47:32.150486 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2023 12:47:32.153798 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2024 12:47:32.157226 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2025 12:47:32.163510 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2026 12:47:32.167073 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2027 12:47:32.170529 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2028 12:47:32.173461 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2029 12:47:32.176994 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2030 12:47:32.183609 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2031 12:47:32.186693 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2032 12:47:32.190130 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2033 12:47:32.193699 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2034 12:47:32.200103 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2035 12:47:32.203493 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2036 12:47:32.203637 ==
2037 12:47:32.206608 Dram Type= 6, Freq= 0, CH_1, rank 1
2038 12:47:32.209964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2039 12:47:32.210107 ==
2040 12:47:32.213432 DQS Delay:
2041 12:47:32.213560 DQS0 = 0, DQS1 = 0
2042 12:47:32.213633 DQM Delay:
2043 12:47:32.216938 DQM0 = 87, DQM1 = 79
2044 12:47:32.217067 DQ Delay:
2045 12:47:32.219872 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2046 12:47:32.223377 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2047 12:47:32.226932 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =68
2048 12:47:32.230353 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =88
2049 12:47:32.230515
2050 12:47:32.230631
2051 12:47:32.240026 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2052 12:47:32.240192 CH1 RK1: MR19=606, MR18=1E17
2053 12:47:32.246677 CH1_RK1: MR19=0x606, MR18=0x1E17, DQSOSC=402, MR23=63, INC=91, DEC=60
2054 12:47:32.249745 [RxdqsGatingPostProcess] freq 800
2055 12:47:32.256479 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2056 12:47:32.259854 Pre-setting of DQS Precalculation
2057 12:47:32.263369 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2058 12:47:32.269615 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2059 12:47:32.279566 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2060 12:47:32.279707
2061 12:47:32.279781
2062 12:47:32.283058 [Calibration Summary] 1600 Mbps
2063 12:47:32.283176 CH 0, Rank 0
2064 12:47:32.286501 SW Impedance : PASS
2065 12:47:32.286654 DUTY Scan : NO K
2066 12:47:32.289976 ZQ Calibration : PASS
2067 12:47:32.292886 Jitter Meter : NO K
2068 12:47:32.293021 CBT Training : PASS
2069 12:47:32.296393 Write leveling : PASS
2070 12:47:32.299927 RX DQS gating : PASS
2071 12:47:32.300059 RX DQ/DQS(RDDQC) : PASS
2072 12:47:32.302759 TX DQ/DQS : PASS
2073 12:47:32.302878 RX DATLAT : PASS
2074 12:47:32.306338 RX DQ/DQS(Engine): PASS
2075 12:47:32.309478 TX OE : NO K
2076 12:47:32.309633 All Pass.
2077 12:47:32.309741
2078 12:47:32.309825 CH 0, Rank 1
2079 12:47:32.312917 SW Impedance : PASS
2080 12:47:32.315921 DUTY Scan : NO K
2081 12:47:32.316070 ZQ Calibration : PASS
2082 12:47:32.319163 Jitter Meter : NO K
2083 12:47:32.322745 CBT Training : PASS
2084 12:47:32.322905 Write leveling : PASS
2085 12:47:32.326136 RX DQS gating : PASS
2086 12:47:32.329092 RX DQ/DQS(RDDQC) : PASS
2087 12:47:32.329233 TX DQ/DQS : PASS
2088 12:47:32.332616 RX DATLAT : PASS
2089 12:47:32.336084 RX DQ/DQS(Engine): PASS
2090 12:47:32.336247 TX OE : NO K
2091 12:47:32.339018 All Pass.
2092 12:47:32.339148
2093 12:47:32.339217 CH 1, Rank 0
2094 12:47:32.342378 SW Impedance : PASS
2095 12:47:32.342518 DUTY Scan : NO K
2096 12:47:32.345849 ZQ Calibration : PASS
2097 12:47:32.349193 Jitter Meter : NO K
2098 12:47:32.349335 CBT Training : PASS
2099 12:47:32.352366 Write leveling : PASS
2100 12:47:32.355687 RX DQS gating : PASS
2101 12:47:32.355824 RX DQ/DQS(RDDQC) : PASS
2102 12:47:32.359381 TX DQ/DQS : PASS
2103 12:47:32.362526 RX DATLAT : PASS
2104 12:47:32.362692 RX DQ/DQS(Engine): PASS
2105 12:47:32.365624 TX OE : NO K
2106 12:47:32.365823 All Pass.
2107 12:47:32.365935
2108 12:47:32.369027 CH 1, Rank 1
2109 12:47:32.369215 SW Impedance : PASS
2110 12:47:32.372424 DUTY Scan : NO K
2111 12:47:32.372593 ZQ Calibration : PASS
2112 12:47:32.375347 Jitter Meter : NO K
2113 12:47:32.378833 CBT Training : PASS
2114 12:47:32.379023 Write leveling : PASS
2115 12:47:32.382430 RX DQS gating : PASS
2116 12:47:32.385369 RX DQ/DQS(RDDQC) : PASS
2117 12:47:32.385548 TX DQ/DQS : PASS
2118 12:47:32.388850 RX DATLAT : PASS
2119 12:47:32.392658 RX DQ/DQS(Engine): PASS
2120 12:47:32.392866 TX OE : NO K
2121 12:47:32.395444 All Pass.
2122 12:47:32.395612
2123 12:47:32.395720 DramC Write-DBI off
2124 12:47:32.398951 PER_BANK_REFRESH: Hybrid Mode
2125 12:47:32.399128 TX_TRACKING: ON
2126 12:47:32.402463 [GetDramInforAfterCalByMRR] Vendor 6.
2127 12:47:32.409000 [GetDramInforAfterCalByMRR] Revision 606.
2128 12:47:32.411803 [GetDramInforAfterCalByMRR] Revision 2 0.
2129 12:47:32.411975 MR0 0x3b3b
2130 12:47:32.412083 MR8 0x5151
2131 12:47:32.415242 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2132 12:47:32.418575
2133 12:47:32.418760 MR0 0x3b3b
2134 12:47:32.418864 MR8 0x5151
2135 12:47:32.421889 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2136 12:47:32.422045
2137 12:47:32.431787 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2138 12:47:32.435070 [FAST_K] Save calibration result to emmc
2139 12:47:32.438407 [FAST_K] Save calibration result to emmc
2140 12:47:32.441898 dram_init: config_dvfs: 1
2141 12:47:32.445265 dramc_set_vcore_voltage set vcore to 662500
2142 12:47:32.448615 Read voltage for 1200, 2
2143 12:47:32.448770 Vio18 = 0
2144 12:47:32.448846 Vcore = 662500
2145 12:47:32.451511 Vdram = 0
2146 12:47:32.451665 Vddq = 0
2147 12:47:32.451737 Vmddr = 0
2148 12:47:32.458273 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2149 12:47:32.461546 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2150 12:47:32.464922 MEM_TYPE=3, freq_sel=15
2151 12:47:32.468395 sv_algorithm_assistance_LP4_1600
2152 12:47:32.471622 ============ PULL DRAM RESETB DOWN ============
2153 12:47:32.478488 ========== PULL DRAM RESETB DOWN end =========
2154 12:47:32.481744 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2155 12:47:32.485235 ===================================
2156 12:47:32.488118 LPDDR4 DRAM CONFIGURATION
2157 12:47:32.491577 ===================================
2158 12:47:32.491756 EX_ROW_EN[0] = 0x0
2159 12:47:32.495154 EX_ROW_EN[1] = 0x0
2160 12:47:32.495346 LP4Y_EN = 0x0
2161 12:47:32.497837 WORK_FSP = 0x0
2162 12:47:32.497995 WL = 0x4
2163 12:47:32.501299 RL = 0x4
2164 12:47:32.501481 BL = 0x2
2165 12:47:32.504870 RPST = 0x0
2166 12:47:32.505049 RD_PRE = 0x0
2167 12:47:32.507868 WR_PRE = 0x1
2168 12:47:32.508054 WR_PST = 0x0
2169 12:47:32.511311 DBI_WR = 0x0
2170 12:47:32.511492 DBI_RD = 0x0
2171 12:47:32.515106 OTF = 0x1
2172 12:47:32.517784 ===================================
2173 12:47:32.521375 ===================================
2174 12:47:32.521581 ANA top config
2175 12:47:32.524821 ===================================
2176 12:47:32.528476 DLL_ASYNC_EN = 0
2177 12:47:32.531172 ALL_SLAVE_EN = 0
2178 12:47:32.534543 NEW_RANK_MODE = 1
2179 12:47:32.534742 DLL_IDLE_MODE = 1
2180 12:47:32.538340 LP45_APHY_COMB_EN = 1
2181 12:47:32.541326 TX_ODT_DIS = 1
2182 12:47:32.544797 NEW_8X_MODE = 1
2183 12:47:32.547743 ===================================
2184 12:47:32.551038 ===================================
2185 12:47:32.554394 data_rate = 2400
2186 12:47:32.557802 CKR = 1
2187 12:47:32.557981 DQ_P2S_RATIO = 8
2188 12:47:32.561181 ===================================
2189 12:47:32.564772 CA_P2S_RATIO = 8
2190 12:47:32.567668 DQ_CA_OPEN = 0
2191 12:47:32.571050 DQ_SEMI_OPEN = 0
2192 12:47:32.574489 CA_SEMI_OPEN = 0
2193 12:47:32.577908 CA_FULL_RATE = 0
2194 12:47:32.578074 DQ_CKDIV4_EN = 0
2195 12:47:32.581178 CA_CKDIV4_EN = 0
2196 12:47:32.584355 CA_PREDIV_EN = 0
2197 12:47:32.588047 PH8_DLY = 17
2198 12:47:32.591220 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2199 12:47:32.591369 DQ_AAMCK_DIV = 4
2200 12:47:32.594789 CA_AAMCK_DIV = 4
2201 12:47:32.597712 CA_ADMCK_DIV = 4
2202 12:47:32.601167 DQ_TRACK_CA_EN = 0
2203 12:47:32.604600 CA_PICK = 1200
2204 12:47:32.608155 CA_MCKIO = 1200
2205 12:47:32.611148 MCKIO_SEMI = 0
2206 12:47:32.614698 PLL_FREQ = 2366
2207 12:47:32.614848 DQ_UI_PI_RATIO = 32
2208 12:47:32.618074 CA_UI_PI_RATIO = 0
2209 12:47:32.620971 ===================================
2210 12:47:32.624505 ===================================
2211 12:47:32.628060 memory_type:LPDDR4
2212 12:47:32.630895 GP_NUM : 10
2213 12:47:32.631052 SRAM_EN : 1
2214 12:47:32.634413 MD32_EN : 0
2215 12:47:32.637871 ===================================
2216 12:47:32.638026 [ANA_INIT] >>>>>>>>>>>>>>
2217 12:47:32.641320 <<<<<< [CONFIGURE PHASE]: ANA_TX
2218 12:47:32.644216 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2219 12:47:32.647604 ===================================
2220 12:47:32.651122 data_rate = 2400,PCW = 0X5b00
2221 12:47:32.654271 ===================================
2222 12:47:32.657666 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2223 12:47:32.664194 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2224 12:47:32.670908 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2225 12:47:32.674300 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2226 12:47:32.677518 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2227 12:47:32.681004 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2228 12:47:32.684510 [ANA_INIT] flow start
2229 12:47:32.684657 [ANA_INIT] PLL >>>>>>>>
2230 12:47:32.687838 [ANA_INIT] PLL <<<<<<<<
2231 12:47:32.691148 [ANA_INIT] MIDPI >>>>>>>>
2232 12:47:32.691294 [ANA_INIT] MIDPI <<<<<<<<
2233 12:47:32.694040 [ANA_INIT] DLL >>>>>>>>
2234 12:47:32.697675 [ANA_INIT] DLL <<<<<<<<
2235 12:47:32.697831 [ANA_INIT] flow end
2236 12:47:32.704470 ============ LP4 DIFF to SE enter ============
2237 12:47:32.707759 ============ LP4 DIFF to SE exit ============
2238 12:47:32.711133 [ANA_INIT] <<<<<<<<<<<<<
2239 12:47:32.714434 [Flow] Enable top DCM control >>>>>
2240 12:47:32.714649 [Flow] Enable top DCM control <<<<<
2241 12:47:32.717310 Enable DLL master slave shuffle
2242 12:47:32.724197 ==============================================================
2243 12:47:32.727161 Gating Mode config
2244 12:47:32.730790 ==============================================================
2245 12:47:32.733655 Config description:
2246 12:47:32.743678 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2247 12:47:32.750697 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2248 12:47:32.753995 SELPH_MODE 0: By rank 1: By Phase
2249 12:47:32.760120 ==============================================================
2250 12:47:32.763971 GAT_TRACK_EN = 1
2251 12:47:32.766943 RX_GATING_MODE = 2
2252 12:47:32.770154 RX_GATING_TRACK_MODE = 2
2253 12:47:32.773582 SELPH_MODE = 1
2254 12:47:32.773762 PICG_EARLY_EN = 1
2255 12:47:32.776551 VALID_LAT_VALUE = 1
2256 12:47:32.783737 ==============================================================
2257 12:47:32.786851 Enter into Gating configuration >>>>
2258 12:47:32.790240 Exit from Gating configuration <<<<
2259 12:47:32.793519 Enter into DVFS_PRE_config >>>>>
2260 12:47:32.803242 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2261 12:47:32.806844 Exit from DVFS_PRE_config <<<<<
2262 12:47:32.810039 Enter into PICG configuration >>>>
2263 12:47:32.813407 Exit from PICG configuration <<<<
2264 12:47:32.816770 [RX_INPUT] configuration >>>>>
2265 12:47:32.819674 [RX_INPUT] configuration <<<<<
2266 12:47:32.823092 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2267 12:47:32.829498 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2268 12:47:32.836550 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2269 12:47:32.842980 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2270 12:47:32.849546 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2271 12:47:32.856440 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2272 12:47:32.859742 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2273 12:47:32.862688 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2274 12:47:32.866026 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2275 12:47:32.872856 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2276 12:47:32.876236 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2277 12:47:32.879688 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2278 12:47:32.882456 ===================================
2279 12:47:32.885981 LPDDR4 DRAM CONFIGURATION
2280 12:47:32.889526 ===================================
2281 12:47:32.889715 EX_ROW_EN[0] = 0x0
2282 12:47:32.892598 EX_ROW_EN[1] = 0x0
2283 12:47:32.892745 LP4Y_EN = 0x0
2284 12:47:32.896042 WORK_FSP = 0x0
2285 12:47:32.899140 WL = 0x4
2286 12:47:32.899301 RL = 0x4
2287 12:47:32.902535 BL = 0x2
2288 12:47:32.902719 RPST = 0x0
2289 12:47:32.906119 RD_PRE = 0x0
2290 12:47:32.906250 WR_PRE = 0x1
2291 12:47:32.909487 WR_PST = 0x0
2292 12:47:32.909620 DBI_WR = 0x0
2293 12:47:32.912638 DBI_RD = 0x0
2294 12:47:32.912795 OTF = 0x1
2295 12:47:32.915792 ===================================
2296 12:47:32.919034 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2297 12:47:32.926001 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2298 12:47:32.929579 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2299 12:47:32.932508 ===================================
2300 12:47:32.936067 LPDDR4 DRAM CONFIGURATION
2301 12:47:32.939005 ===================================
2302 12:47:32.939136 EX_ROW_EN[0] = 0x10
2303 12:47:32.942418 EX_ROW_EN[1] = 0x0
2304 12:47:32.942537 LP4Y_EN = 0x0
2305 12:47:32.945932 WORK_FSP = 0x0
2306 12:47:32.946060 WL = 0x4
2307 12:47:32.948871 RL = 0x4
2308 12:47:32.949058 BL = 0x2
2309 12:47:32.952471 RPST = 0x0
2310 12:47:32.952666 RD_PRE = 0x0
2311 12:47:32.955861 WR_PRE = 0x1
2312 12:47:32.956045 WR_PST = 0x0
2313 12:47:32.959457 DBI_WR = 0x0
2314 12:47:32.962061 DBI_RD = 0x0
2315 12:47:32.962242 OTF = 0x1
2316 12:47:32.965529 ===================================
2317 12:47:32.972302 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2318 12:47:32.972497 ==
2319 12:47:32.975594 Dram Type= 6, Freq= 0, CH_0, rank 0
2320 12:47:32.978995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2321 12:47:32.979176 ==
2322 12:47:32.982522 [Duty_Offset_Calibration]
2323 12:47:32.985454 B0:1 B1:-1 CA:0
2324 12:47:32.985632
2325 12:47:32.988863 [DutyScan_Calibration_Flow] k_type=0
2326 12:47:32.996733
2327 12:47:32.996927 ==CLK 0==
2328 12:47:32.999891 Final CLK duty delay cell = 0
2329 12:47:33.003493 [0] MAX Duty = 5125%(X100), DQS PI = 24
2330 12:47:33.006625 [0] MIN Duty = 4907%(X100), DQS PI = 8
2331 12:47:33.006795 [0] AVG Duty = 5016%(X100)
2332 12:47:33.006896
2333 12:47:33.010188 CH0 CLK Duty spec in!! Max-Min= 218%
2334 12:47:33.016685 [DutyScan_Calibration_Flow] ====Done====
2335 12:47:33.016859
2336 12:47:33.019988 [DutyScan_Calibration_Flow] k_type=1
2337 12:47:33.034899
2338 12:47:33.035051 ==DQS 0 ==
2339 12:47:33.037634 Final DQS duty delay cell = -4
2340 12:47:33.041259 [-4] MAX Duty = 5062%(X100), DQS PI = 18
2341 12:47:33.044737 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2342 12:47:33.047544 [-4] AVG Duty = 4968%(X100)
2343 12:47:33.047654
2344 12:47:33.047722 ==DQS 1 ==
2345 12:47:33.050969 Final DQS duty delay cell = -4
2346 12:47:33.054455 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2347 12:47:33.057341 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2348 12:47:33.060784 [-4] AVG Duty = 4938%(X100)
2349 12:47:33.060956
2350 12:47:33.064254 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2351 12:47:33.064433
2352 12:47:33.067733 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2353 12:47:33.070637 [DutyScan_Calibration_Flow] ====Done====
2354 12:47:33.070804
2355 12:47:33.074044 [DutyScan_Calibration_Flow] k_type=3
2356 12:47:33.092561
2357 12:47:33.092784 ==DQM 0 ==
2358 12:47:33.095778 Final DQM duty delay cell = 0
2359 12:47:33.099256 [0] MAX Duty = 5031%(X100), DQS PI = 16
2360 12:47:33.102271 [0] MIN Duty = 4875%(X100), DQS PI = 6
2361 12:47:33.102481 [0] AVG Duty = 4953%(X100)
2362 12:47:33.105579
2363 12:47:33.105788 ==DQM 1 ==
2364 12:47:33.108765 Final DQM duty delay cell = 4
2365 12:47:33.112025 [4] MAX Duty = 5187%(X100), DQS PI = 14
2366 12:47:33.115599 [4] MIN Duty = 5000%(X100), DQS PI = 22
2367 12:47:33.118803 [4] AVG Duty = 5093%(X100)
2368 12:47:33.118991
2369 12:47:33.122560 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2370 12:47:33.122761
2371 12:47:33.125701 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2372 12:47:33.128886 [DutyScan_Calibration_Flow] ====Done====
2373 12:47:33.129086
2374 12:47:33.132158 [DutyScan_Calibration_Flow] k_type=2
2375 12:47:33.147386
2376 12:47:33.147541 ==DQ 0 ==
2377 12:47:33.150761 Final DQ duty delay cell = -4
2378 12:47:33.153595 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2379 12:47:33.157142 [-4] MIN Duty = 4907%(X100), DQS PI = 46
2380 12:47:33.160651 [-4] AVG Duty = 4969%(X100)
2381 12:47:33.160785
2382 12:47:33.160855 ==DQ 1 ==
2383 12:47:33.163683 Final DQ duty delay cell = -4
2384 12:47:33.167296 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2385 12:47:33.170504 [-4] MIN Duty = 4876%(X100), DQS PI = 14
2386 12:47:33.173872 [-4] AVG Duty = 4938%(X100)
2387 12:47:33.174031
2388 12:47:33.176823 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2389 12:47:33.176950
2390 12:47:33.180190 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2391 12:47:33.183634 [DutyScan_Calibration_Flow] ====Done====
2392 12:47:33.183776 ==
2393 12:47:33.187019 Dram Type= 6, Freq= 0, CH_1, rank 0
2394 12:47:33.190555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2395 12:47:33.190730 ==
2396 12:47:33.193531 [Duty_Offset_Calibration]
2397 12:47:33.193663 B0:-1 B1:1 CA:1
2398 12:47:33.196791
2399 12:47:33.196923 [DutyScan_Calibration_Flow] k_type=0
2400 12:47:33.207705
2401 12:47:33.207896 ==CLK 0==
2402 12:47:33.211335 Final CLK duty delay cell = 0
2403 12:47:33.214509 [0] MAX Duty = 5156%(X100), DQS PI = 20
2404 12:47:33.217742 [0] MIN Duty = 4969%(X100), DQS PI = 60
2405 12:47:33.220980 [0] AVG Duty = 5062%(X100)
2406 12:47:33.221137
2407 12:47:33.224474 CH1 CLK Duty spec in!! Max-Min= 187%
2408 12:47:33.227419 [DutyScan_Calibration_Flow] ====Done====
2409 12:47:33.227566
2410 12:47:33.230717 [DutyScan_Calibration_Flow] k_type=1
2411 12:47:33.247426
2412 12:47:33.247620 ==DQS 0 ==
2413 12:47:33.250470 Final DQS duty delay cell = 0
2414 12:47:33.254151 [0] MAX Duty = 5125%(X100), DQS PI = 18
2415 12:47:33.257234 [0] MIN Duty = 4875%(X100), DQS PI = 8
2416 12:47:33.257411 [0] AVG Duty = 5000%(X100)
2417 12:47:33.260354
2418 12:47:33.260474 ==DQS 1 ==
2419 12:47:33.263781 Final DQS duty delay cell = 0
2420 12:47:33.267332 [0] MAX Duty = 5094%(X100), DQS PI = 14
2421 12:47:33.270842 [0] MIN Duty = 4969%(X100), DQS PI = 58
2422 12:47:33.270987 [0] AVG Duty = 5031%(X100)
2423 12:47:33.273704
2424 12:47:33.277115 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2425 12:47:33.277252
2426 12:47:33.280580 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2427 12:47:33.283879 [DutyScan_Calibration_Flow] ====Done====
2428 12:47:33.284013
2429 12:47:33.286813 [DutyScan_Calibration_Flow] k_type=3
2430 12:47:33.302793
2431 12:47:33.303006 ==DQM 0 ==
2432 12:47:33.306230 Final DQM duty delay cell = -4
2433 12:47:33.309705 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2434 12:47:33.312645 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2435 12:47:33.316186 [-4] AVG Duty = 4969%(X100)
2436 12:47:33.316350
2437 12:47:33.316453 ==DQM 1 ==
2438 12:47:33.319660 Final DQM duty delay cell = 0
2439 12:47:33.322985 [0] MAX Duty = 5187%(X100), DQS PI = 4
2440 12:47:33.326135 [0] MIN Duty = 5000%(X100), DQS PI = 28
2441 12:47:33.329520 [0] AVG Duty = 5093%(X100)
2442 12:47:33.329676
2443 12:47:33.332558 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2444 12:47:33.332694
2445 12:47:33.335983 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2446 12:47:33.339477 [DutyScan_Calibration_Flow] ====Done====
2447 12:47:33.339619
2448 12:47:33.342866 [DutyScan_Calibration_Flow] k_type=2
2449 12:47:33.359570
2450 12:47:33.359766 ==DQ 0 ==
2451 12:47:33.363110 Final DQ duty delay cell = 0
2452 12:47:33.366215 [0] MAX Duty = 5187%(X100), DQS PI = 32
2453 12:47:33.369626 [0] MIN Duty = 4907%(X100), DQS PI = 8
2454 12:47:33.369854 [0] AVG Duty = 5047%(X100)
2455 12:47:33.373178
2456 12:47:33.373366 ==DQ 1 ==
2457 12:47:33.376133 Final DQ duty delay cell = 0
2458 12:47:33.379825 [0] MAX Duty = 5156%(X100), DQS PI = 10
2459 12:47:33.383282 [0] MIN Duty = 4969%(X100), DQS PI = 60
2460 12:47:33.383477 [0] AVG Duty = 5062%(X100)
2461 12:47:33.383611
2462 12:47:33.386030 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2463 12:47:33.389381
2464 12:47:33.392792 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2465 12:47:33.396158 [DutyScan_Calibration_Flow] ====Done====
2466 12:47:33.399631 nWR fixed to 30
2467 12:47:33.399815 [ModeRegInit_LP4] CH0 RK0
2468 12:47:33.402513 [ModeRegInit_LP4] CH0 RK1
2469 12:47:33.406363 [ModeRegInit_LP4] CH1 RK0
2470 12:47:33.406542 [ModeRegInit_LP4] CH1 RK1
2471 12:47:33.409875 match AC timing 7
2472 12:47:33.412706 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2473 12:47:33.419699 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2474 12:47:33.422473 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2475 12:47:33.429533 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2476 12:47:33.432807 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2477 12:47:33.432935 ==
2478 12:47:33.436004 Dram Type= 6, Freq= 0, CH_0, rank 0
2479 12:47:33.439465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2480 12:47:33.439647 ==
2481 12:47:33.445810 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2482 12:47:33.452305 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2483 12:47:33.459434 [CA 0] Center 39 (9~70) winsize 62
2484 12:47:33.462749 [CA 1] Center 39 (9~70) winsize 62
2485 12:47:33.465920 [CA 2] Center 35 (5~66) winsize 62
2486 12:47:33.469337 [CA 3] Center 35 (5~65) winsize 61
2487 12:47:33.472678 [CA 4] Center 33 (3~64) winsize 62
2488 12:47:33.475991 [CA 5] Center 33 (4~63) winsize 60
2489 12:47:33.476112
2490 12:47:33.479503 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2491 12:47:33.479627
2492 12:47:33.482490 [CATrainingPosCal] consider 1 rank data
2493 12:47:33.486102 u2DelayCellTimex100 = 270/100 ps
2494 12:47:33.489260 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2495 12:47:33.496278 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2496 12:47:33.499620 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2497 12:47:33.502933 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2498 12:47:33.506138 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2499 12:47:33.509426 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2500 12:47:33.509553
2501 12:47:33.512789 CA PerBit enable=1, Macro0, CA PI delay=33
2502 12:47:33.512915
2503 12:47:33.516259 [CBTSetCACLKResult] CA Dly = 33
2504 12:47:33.516392 CS Dly: 8 (0~39)
2505 12:47:33.519410 ==
2506 12:47:33.522832 Dram Type= 6, Freq= 0, CH_0, rank 1
2507 12:47:33.526312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 12:47:33.526467 ==
2509 12:47:33.529262 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2510 12:47:33.535735 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2511 12:47:33.545638 [CA 0] Center 39 (8~70) winsize 63
2512 12:47:33.548550 [CA 1] Center 39 (9~70) winsize 62
2513 12:47:33.552060 [CA 2] Center 35 (5~66) winsize 62
2514 12:47:33.555552 [CA 3] Center 34 (4~65) winsize 62
2515 12:47:33.558449 [CA 4] Center 33 (3~64) winsize 62
2516 12:47:33.562031 [CA 5] Center 33 (3~63) winsize 61
2517 12:47:33.562174
2518 12:47:33.565554 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2519 12:47:33.565663
2520 12:47:33.568443 [CATrainingPosCal] consider 2 rank data
2521 12:47:33.571634 u2DelayCellTimex100 = 270/100 ps
2522 12:47:33.575248 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2523 12:47:33.578511 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2524 12:47:33.585445 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2525 12:47:33.588315 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2526 12:47:33.591711 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2527 12:47:33.595008 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2528 12:47:33.595202
2529 12:47:33.598352 CA PerBit enable=1, Macro0, CA PI delay=33
2530 12:47:33.598527
2531 12:47:33.602061 [CBTSetCACLKResult] CA Dly = 33
2532 12:47:33.602193 CS Dly: 8 (0~40)
2533 12:47:33.602299
2534 12:47:33.605026 ----->DramcWriteLeveling(PI) begin...
2535 12:47:33.608674 ==
2536 12:47:33.611610 Dram Type= 6, Freq= 0, CH_0, rank 0
2537 12:47:33.615217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2538 12:47:33.615373 ==
2539 12:47:33.618273 Write leveling (Byte 0): 31 => 31
2540 12:47:33.621803 Write leveling (Byte 1): 30 => 30
2541 12:47:33.625163 DramcWriteLeveling(PI) end<-----
2542 12:47:33.625359
2543 12:47:33.625473 ==
2544 12:47:33.628417 Dram Type= 6, Freq= 0, CH_0, rank 0
2545 12:47:33.631906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2546 12:47:33.632048 ==
2547 12:47:33.635412 [Gating] SW mode calibration
2548 12:47:33.641883 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2549 12:47:33.648023 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2550 12:47:33.651742 0 15 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2551 12:47:33.655176 0 15 4 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
2552 12:47:33.661528 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2553 12:47:33.665066 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2554 12:47:33.667977 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2555 12:47:33.671504 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2556 12:47:33.678360 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2557 12:47:33.681781 0 15 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
2558 12:47:33.684456 1 0 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
2559 12:47:33.691171 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2560 12:47:33.694624 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2561 12:47:33.697947 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2562 12:47:33.704892 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2563 12:47:33.707826 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2564 12:47:33.711603 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2565 12:47:33.718173 1 0 28 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
2566 12:47:33.721593 1 1 0 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2567 12:47:33.724943 1 1 4 | B1->B0 | 4140 4646 | 1 0 | (0 0) (0 0)
2568 12:47:33.731145 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 12:47:33.734537 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 12:47:33.738113 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2571 12:47:33.744662 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 12:47:33.748295 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 12:47:33.751207 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2574 12:47:33.757873 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2575 12:47:33.761082 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2576 12:47:33.764501 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 12:47:33.770982 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 12:47:33.774455 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 12:47:33.778099 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 12:47:33.784728 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 12:47:33.787485 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 12:47:33.790780 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 12:47:33.797469 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 12:47:33.800795 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 12:47:33.804139 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 12:47:33.811219 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 12:47:33.814010 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 12:47:33.817394 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2589 12:47:33.821050 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2590 12:47:33.827462 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2591 12:47:33.831025 Total UI for P1: 0, mck2ui 16
2592 12:47:33.834175 best dqsien dly found for B0: ( 1, 3, 26)
2593 12:47:33.837701 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 12:47:33.840943 Total UI for P1: 0, mck2ui 16
2595 12:47:33.844047 best dqsien dly found for B1: ( 1, 4, 0)
2596 12:47:33.847426 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2597 12:47:33.850644 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2598 12:47:33.850838
2599 12:47:33.854047 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2600 12:47:33.857571 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2601 12:47:33.861054 [Gating] SW calibration Done
2602 12:47:33.861186 ==
2603 12:47:33.864312 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 12:47:33.867611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 12:47:33.870929 ==
2606 12:47:33.871071 RX Vref Scan: 0
2607 12:47:33.871168
2608 12:47:33.874422 RX Vref 0 -> 0, step: 1
2609 12:47:33.874567
2610 12:47:33.877320 RX Delay -40 -> 252, step: 8
2611 12:47:33.880793 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2612 12:47:33.884294 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2613 12:47:33.887124 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2614 12:47:33.890631 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2615 12:47:33.897467 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2616 12:47:33.900710 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2617 12:47:33.904111 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2618 12:47:33.907435 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2619 12:47:33.910390 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2620 12:47:33.917335 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2621 12:47:33.920598 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2622 12:47:33.924009 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2623 12:47:33.927323 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2624 12:47:33.930685 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2625 12:47:33.937399 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2626 12:47:33.940325 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2627 12:47:33.940515 ==
2628 12:47:33.943817 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 12:47:33.947315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 12:47:33.947517 ==
2631 12:47:33.950610 DQS Delay:
2632 12:47:33.950797 DQS0 = 0, DQS1 = 0
2633 12:47:33.950936 DQM Delay:
2634 12:47:33.953730 DQM0 = 119, DQM1 = 107
2635 12:47:33.953932 DQ Delay:
2636 12:47:33.956972 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2637 12:47:33.960901 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127
2638 12:47:33.963559 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2639 12:47:33.969957 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2640 12:47:33.970116
2641 12:47:33.970192
2642 12:47:33.970261 ==
2643 12:47:33.973321 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 12:47:33.976982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 12:47:33.977166 ==
2646 12:47:33.977280
2647 12:47:33.977376
2648 12:47:33.980430 TX Vref Scan disable
2649 12:47:33.980554 == TX Byte 0 ==
2650 12:47:33.986866 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2651 12:47:33.990362 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2652 12:47:33.990535 == TX Byte 1 ==
2653 12:47:33.996862 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2654 12:47:34.000316 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2655 12:47:34.000443 ==
2656 12:47:34.003831 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 12:47:34.007029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 12:47:34.007163 ==
2659 12:47:34.019234 TX Vref=22, minBit 1, minWin=25, winSum=415
2660 12:47:34.022634 TX Vref=24, minBit 0, minWin=26, winSum=421
2661 12:47:34.026054 TX Vref=26, minBit 4, minWin=26, winSum=430
2662 12:47:34.029382 TX Vref=28, minBit 4, minWin=26, winSum=435
2663 12:47:34.032848 TX Vref=30, minBit 4, minWin=26, winSum=431
2664 12:47:34.036474 TX Vref=32, minBit 4, minWin=26, winSum=432
2665 12:47:34.042518 [TxChooseVref] Worse bit 4, Min win 26, Win sum 435, Final Vref 28
2666 12:47:34.042728
2667 12:47:34.046066 Final TX Range 1 Vref 28
2668 12:47:34.046253
2669 12:47:34.046361 ==
2670 12:47:34.049454 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 12:47:34.052940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 12:47:34.053111 ==
2673 12:47:34.055877
2674 12:47:34.056028
2675 12:47:34.056130 TX Vref Scan disable
2676 12:47:34.059601 == TX Byte 0 ==
2677 12:47:34.062541 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2678 12:47:34.066205 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2679 12:47:34.069081 == TX Byte 1 ==
2680 12:47:34.072343 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2681 12:47:34.075665 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2682 12:47:34.079243
2683 12:47:34.079411 [DATLAT]
2684 12:47:34.079517 Freq=1200, CH0 RK0
2685 12:47:34.079614
2686 12:47:34.082501 DATLAT Default: 0xd
2687 12:47:34.082654 0, 0xFFFF, sum = 0
2688 12:47:34.086199 1, 0xFFFF, sum = 0
2689 12:47:34.086364 2, 0xFFFF, sum = 0
2690 12:47:34.089168 3, 0xFFFF, sum = 0
2691 12:47:34.089304 4, 0xFFFF, sum = 0
2692 12:47:34.092586 5, 0xFFFF, sum = 0
2693 12:47:34.092743 6, 0xFFFF, sum = 0
2694 12:47:34.096135 7, 0xFFFF, sum = 0
2695 12:47:34.098940 8, 0xFFFF, sum = 0
2696 12:47:34.099099 9, 0xFFFF, sum = 0
2697 12:47:34.102485 10, 0xFFFF, sum = 0
2698 12:47:34.102650 11, 0xFFFF, sum = 0
2699 12:47:34.105997 12, 0x0, sum = 1
2700 12:47:34.106166 13, 0x0, sum = 2
2701 12:47:34.108889 14, 0x0, sum = 3
2702 12:47:34.109045 15, 0x0, sum = 4
2703 12:47:34.109152 best_step = 13
2704 12:47:34.109247
2705 12:47:34.112444 ==
2706 12:47:34.115856 Dram Type= 6, Freq= 0, CH_0, rank 0
2707 12:47:34.119133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2708 12:47:34.119264 ==
2709 12:47:34.119360 RX Vref Scan: 1
2710 12:47:34.119454
2711 12:47:34.122723 Set Vref Range= 32 -> 127
2712 12:47:34.122897
2713 12:47:34.125733 RX Vref 32 -> 127, step: 1
2714 12:47:34.125878
2715 12:47:34.129148 RX Delay -21 -> 252, step: 4
2716 12:47:34.129310
2717 12:47:34.132525 Set Vref, RX VrefLevel [Byte0]: 32
2718 12:47:34.135941 [Byte1]: 32
2719 12:47:34.136097
2720 12:47:34.138946 Set Vref, RX VrefLevel [Byte0]: 33
2721 12:47:34.142570 [Byte1]: 33
2722 12:47:34.142720
2723 12:47:34.146171 Set Vref, RX VrefLevel [Byte0]: 34
2724 12:47:34.148871 [Byte1]: 34
2725 12:47:34.153510
2726 12:47:34.153692 Set Vref, RX VrefLevel [Byte0]: 35
2727 12:47:34.156954 [Byte1]: 35
2728 12:47:34.161611
2729 12:47:34.161777 Set Vref, RX VrefLevel [Byte0]: 36
2730 12:47:34.165021 [Byte1]: 36
2731 12:47:34.169640
2732 12:47:34.169834 Set Vref, RX VrefLevel [Byte0]: 37
2733 12:47:34.172834 [Byte1]: 37
2734 12:47:34.177394
2735 12:47:34.177568 Set Vref, RX VrefLevel [Byte0]: 38
2736 12:47:34.180722 [Byte1]: 38
2737 12:47:34.185231
2738 12:47:34.185397 Set Vref, RX VrefLevel [Byte0]: 39
2739 12:47:34.188343 [Byte1]: 39
2740 12:47:34.192966
2741 12:47:34.193124 Set Vref, RX VrefLevel [Byte0]: 40
2742 12:47:34.196184 [Byte1]: 40
2743 12:47:34.200800
2744 12:47:34.200962 Set Vref, RX VrefLevel [Byte0]: 41
2745 12:47:34.204176 [Byte1]: 41
2746 12:47:34.208885
2747 12:47:34.209088 Set Vref, RX VrefLevel [Byte0]: 42
2748 12:47:34.212355 [Byte1]: 42
2749 12:47:34.217087
2750 12:47:34.217279 Set Vref, RX VrefLevel [Byte0]: 43
2751 12:47:34.219976 [Byte1]: 43
2752 12:47:34.225151
2753 12:47:34.225325 Set Vref, RX VrefLevel [Byte0]: 44
2754 12:47:34.228039 [Byte1]: 44
2755 12:47:34.232742
2756 12:47:34.232917 Set Vref, RX VrefLevel [Byte0]: 45
2757 12:47:34.236303 [Byte1]: 45
2758 12:47:34.240691
2759 12:47:34.240868 Set Vref, RX VrefLevel [Byte0]: 46
2760 12:47:34.243996 [Byte1]: 46
2761 12:47:34.248874
2762 12:47:34.249043 Set Vref, RX VrefLevel [Byte0]: 47
2763 12:47:34.251964 [Byte1]: 47
2764 12:47:34.256328
2765 12:47:34.256497 Set Vref, RX VrefLevel [Byte0]: 48
2766 12:47:34.259792 [Byte1]: 48
2767 12:47:34.264490
2768 12:47:34.264656 Set Vref, RX VrefLevel [Byte0]: 49
2769 12:47:34.267907 [Byte1]: 49
2770 12:47:34.272542
2771 12:47:34.272708 Set Vref, RX VrefLevel [Byte0]: 50
2772 12:47:34.275899 [Byte1]: 50
2773 12:47:34.280501
2774 12:47:34.280688 Set Vref, RX VrefLevel [Byte0]: 51
2775 12:47:34.283832 [Byte1]: 51
2776 12:47:34.288369
2777 12:47:34.288565 Set Vref, RX VrefLevel [Byte0]: 52
2778 12:47:34.291762 [Byte1]: 52
2779 12:47:34.295997
2780 12:47:34.296178 Set Vref, RX VrefLevel [Byte0]: 53
2781 12:47:34.299598 [Byte1]: 53
2782 12:47:34.304286
2783 12:47:34.304497 Set Vref, RX VrefLevel [Byte0]: 54
2784 12:47:34.307442 [Byte1]: 54
2785 12:47:34.312020
2786 12:47:34.312204 Set Vref, RX VrefLevel [Byte0]: 55
2787 12:47:34.315522 [Byte1]: 55
2788 12:47:34.320192
2789 12:47:34.320375 Set Vref, RX VrefLevel [Byte0]: 56
2790 12:47:34.323046 [Byte1]: 56
2791 12:47:34.327755
2792 12:47:34.327932 Set Vref, RX VrefLevel [Byte0]: 57
2793 12:47:34.331116 [Byte1]: 57
2794 12:47:34.335726
2795 12:47:34.335920 Set Vref, RX VrefLevel [Byte0]: 58
2796 12:47:34.339111 [Byte1]: 58
2797 12:47:34.343599
2798 12:47:34.343792 Set Vref, RX VrefLevel [Byte0]: 59
2799 12:47:34.347072 [Byte1]: 59
2800 12:47:34.351621
2801 12:47:34.351830 Set Vref, RX VrefLevel [Byte0]: 60
2802 12:47:34.355189 [Byte1]: 60
2803 12:47:34.359405
2804 12:47:34.359586 Set Vref, RX VrefLevel [Byte0]: 61
2805 12:47:34.362906 [Byte1]: 61
2806 12:47:34.367556
2807 12:47:34.367750 Set Vref, RX VrefLevel [Byte0]: 62
2808 12:47:34.371030 [Byte1]: 62
2809 12:47:34.375703
2810 12:47:34.375910 Set Vref, RX VrefLevel [Byte0]: 63
2811 12:47:34.379150 [Byte1]: 63
2812 12:47:34.383617
2813 12:47:34.383807 Set Vref, RX VrefLevel [Byte0]: 64
2814 12:47:34.386379 [Byte1]: 64
2815 12:47:34.391582
2816 12:47:34.391761 Set Vref, RX VrefLevel [Byte0]: 65
2817 12:47:34.394337 [Byte1]: 65
2818 12:47:34.399552
2819 12:47:34.399735 Set Vref, RX VrefLevel [Byte0]: 66
2820 12:47:34.402418 [Byte1]: 66
2821 12:47:34.407029
2822 12:47:34.407233 Set Vref, RX VrefLevel [Byte0]: 67
2823 12:47:34.410572 [Byte1]: 67
2824 12:47:34.415332
2825 12:47:34.415532 Set Vref, RX VrefLevel [Byte0]: 68
2826 12:47:34.418647 [Byte1]: 68
2827 12:47:34.423200
2828 12:47:34.423346 Set Vref, RX VrefLevel [Byte0]: 69
2829 12:47:34.426623 [Byte1]: 69
2830 12:47:34.430680
2831 12:47:34.430904 Set Vref, RX VrefLevel [Byte0]: 70
2832 12:47:34.434153 [Byte1]: 70
2833 12:47:34.438899
2834 12:47:34.439114 Set Vref, RX VrefLevel [Byte0]: 71
2835 12:47:34.442361 [Byte1]: 71
2836 12:47:34.447225
2837 12:47:34.447403 Set Vref, RX VrefLevel [Byte0]: 72
2838 12:47:34.449857 [Byte1]: 72
2839 12:47:34.455157
2840 12:47:34.455337 Set Vref, RX VrefLevel [Byte0]: 73
2841 12:47:34.458161 [Byte1]: 73
2842 12:47:34.462804
2843 12:47:34.462984 Set Vref, RX VrefLevel [Byte0]: 74
2844 12:47:34.466207 [Byte1]: 74
2845 12:47:34.470400
2846 12:47:34.473725 Set Vref, RX VrefLevel [Byte0]: 75
2847 12:47:34.477226 [Byte1]: 75
2848 12:47:34.477396
2849 12:47:34.480110 Set Vref, RX VrefLevel [Byte0]: 76
2850 12:47:34.483432 [Byte1]: 76
2851 12:47:34.483609
2852 12:47:34.486888 Final RX Vref Byte 0 = 59 to rank0
2853 12:47:34.489752 Final RX Vref Byte 1 = 51 to rank0
2854 12:47:34.493284 Final RX Vref Byte 0 = 59 to rank1
2855 12:47:34.496760 Final RX Vref Byte 1 = 51 to rank1==
2856 12:47:34.500065 Dram Type= 6, Freq= 0, CH_0, rank 0
2857 12:47:34.503381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2858 12:47:34.506797 ==
2859 12:47:34.506969 DQS Delay:
2860 12:47:34.507068 DQS0 = 0, DQS1 = 0
2861 12:47:34.509633 DQM Delay:
2862 12:47:34.509779 DQM0 = 118, DQM1 = 107
2863 12:47:34.513232 DQ Delay:
2864 12:47:34.516605 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =114
2865 12:47:34.519724 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =126
2866 12:47:34.522728 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =100
2867 12:47:34.526472 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =116
2868 12:47:34.526654
2869 12:47:34.526766
2870 12:47:34.533030 [DQSOSCAuto] RK0, (LSB)MR18= 0x13ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 402 ps
2871 12:47:34.536456 CH0 RK0: MR19=403, MR18=13FF
2872 12:47:34.542991 CH0_RK0: MR19=0x403, MR18=0x13FF, DQSOSC=402, MR23=63, INC=40, DEC=27
2873 12:47:34.543183
2874 12:47:34.546506 ----->DramcWriteLeveling(PI) begin...
2875 12:47:34.546690 ==
2876 12:47:34.549462 Dram Type= 6, Freq= 0, CH_0, rank 1
2877 12:47:34.556305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2878 12:47:34.556493 ==
2879 12:47:34.559688 Write leveling (Byte 0): 35 => 35
2880 12:47:34.559843 Write leveling (Byte 1): 30 => 30
2881 12:47:34.562696 DramcWriteLeveling(PI) end<-----
2882 12:47:34.562842
2883 12:47:34.562957 ==
2884 12:47:34.566114 Dram Type= 6, Freq= 0, CH_0, rank 1
2885 12:47:34.572788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2886 12:47:34.572993 ==
2887 12:47:34.576374 [Gating] SW mode calibration
2888 12:47:34.582768 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2889 12:47:34.586189 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2890 12:47:34.592435 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
2891 12:47:34.595978 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2892 12:47:34.599467 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 12:47:34.605957 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 12:47:34.608989 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 12:47:34.612760 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 12:47:34.618883 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 12:47:34.622402 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2898 12:47:34.625757 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
2899 12:47:34.632363 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2900 12:47:34.635986 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 12:47:34.639106 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 12:47:34.645526 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 12:47:34.649147 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 12:47:34.652070 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 12:47:34.658426 1 0 28 | B1->B0 | 2525 3737 | 0 0 | (0 0) (0 0)
2906 12:47:34.662218 1 1 0 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
2907 12:47:34.665260 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 12:47:34.671892 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 12:47:34.675310 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 12:47:34.678714 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 12:47:34.682101 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 12:47:34.688781 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 12:47:34.692088 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2914 12:47:34.695540 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2915 12:47:34.701993 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 12:47:34.705388 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 12:47:34.708338 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 12:47:34.715424 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 12:47:34.718627 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 12:47:34.721976 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 12:47:34.728605 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 12:47:34.732086 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 12:47:34.735259 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 12:47:34.741540 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 12:47:34.745245 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 12:47:34.748436 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 12:47:34.754772 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 12:47:34.758336 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 12:47:34.761246 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2930 12:47:34.768431 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2931 12:47:34.768627 Total UI for P1: 0, mck2ui 16
2932 12:47:34.774685 best dqsien dly found for B0: ( 1, 3, 28)
2933 12:47:34.777950 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 12:47:34.781368 Total UI for P1: 0, mck2ui 16
2935 12:47:34.784914 best dqsien dly found for B1: ( 1, 4, 0)
2936 12:47:34.787734 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2937 12:47:34.791265 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2938 12:47:34.791441
2939 12:47:34.794692 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2940 12:47:34.797935 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2941 12:47:34.801444 [Gating] SW calibration Done
2942 12:47:34.801612 ==
2943 12:47:34.804846 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 12:47:34.807663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 12:47:34.811294 ==
2946 12:47:34.811461 RX Vref Scan: 0
2947 12:47:34.811566
2948 12:47:34.814605 RX Vref 0 -> 0, step: 1
2949 12:47:34.814731
2950 12:47:34.818034 RX Delay -40 -> 252, step: 8
2951 12:47:34.821014 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2952 12:47:34.824447 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2953 12:47:34.827792 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2954 12:47:34.830765 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2955 12:47:34.837678 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2956 12:47:34.840980 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2957 12:47:34.844431 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2958 12:47:34.847421 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2959 12:47:34.850737 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2960 12:47:34.854457 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2961 12:47:34.860775 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2962 12:47:34.864356 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2963 12:47:34.867719 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2964 12:47:34.871110 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2965 12:47:34.877346 iDelay=200, Bit 14, Center 123 (48 ~ 199) 152
2966 12:47:34.880679 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2967 12:47:34.880805 ==
2968 12:47:34.884005 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 12:47:34.887540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 12:47:34.887669 ==
2971 12:47:34.890373 DQS Delay:
2972 12:47:34.890473 DQS0 = 0, DQS1 = 0
2973 12:47:34.890541 DQM Delay:
2974 12:47:34.893833 DQM0 = 117, DQM1 = 108
2975 12:47:34.893945 DQ Delay:
2976 12:47:34.897446 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
2977 12:47:34.900434 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2978 12:47:34.903945 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2979 12:47:34.910462 DQ12 =111, DQ13 =119, DQ14 =123, DQ15 =111
2980 12:47:34.910666
2981 12:47:34.910774
2982 12:47:34.910867 ==
2983 12:47:34.913889 Dram Type= 6, Freq= 0, CH_0, rank 1
2984 12:47:34.916888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2985 12:47:34.917042 ==
2986 12:47:34.917147
2987 12:47:34.917241
2988 12:47:34.920351 TX Vref Scan disable
2989 12:47:34.920479 == TX Byte 0 ==
2990 12:47:34.926810 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2991 12:47:34.930353 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2992 12:47:34.930511 == TX Byte 1 ==
2993 12:47:34.937071 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2994 12:47:34.940142 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2995 12:47:34.940282 ==
2996 12:47:34.943492 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 12:47:34.946738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 12:47:34.946898 ==
2999 12:47:34.960328 TX Vref=22, minBit 2, minWin=25, winSum=416
3000 12:47:34.963508 TX Vref=24, minBit 0, minWin=26, winSum=423
3001 12:47:34.967138 TX Vref=26, minBit 0, minWin=26, winSum=425
3002 12:47:34.970140 TX Vref=28, minBit 1, minWin=26, winSum=428
3003 12:47:34.973268 TX Vref=30, minBit 1, minWin=26, winSum=432
3004 12:47:34.976508 TX Vref=32, minBit 4, minWin=26, winSum=434
3005 12:47:34.983540 [TxChooseVref] Worse bit 4, Min win 26, Win sum 434, Final Vref 32
3006 12:47:34.983700
3007 12:47:34.986818 Final TX Range 1 Vref 32
3008 12:47:34.986929
3009 12:47:34.987000 ==
3010 12:47:34.990059 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 12:47:34.993582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 12:47:34.993757 ==
3013 12:47:34.996578
3014 12:47:34.996682
3015 12:47:34.996786 TX Vref Scan disable
3016 12:47:35.000151 == TX Byte 0 ==
3017 12:47:35.003813 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3018 12:47:35.006854 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3019 12:47:35.010002 == TX Byte 1 ==
3020 12:47:35.013664 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3021 12:47:35.016671 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3022 12:47:35.020055
3023 12:47:35.020218 [DATLAT]
3024 12:47:35.020322 Freq=1200, CH0 RK1
3025 12:47:35.020417
3026 12:47:35.023664 DATLAT Default: 0xd
3027 12:47:35.023841 0, 0xFFFF, sum = 0
3028 12:47:35.026875 1, 0xFFFF, sum = 0
3029 12:47:35.026992 2, 0xFFFF, sum = 0
3030 12:47:35.029734 3, 0xFFFF, sum = 0
3031 12:47:35.029846 4, 0xFFFF, sum = 0
3032 12:47:35.033379 5, 0xFFFF, sum = 0
3033 12:47:35.036786 6, 0xFFFF, sum = 0
3034 12:47:35.036910 7, 0xFFFF, sum = 0
3035 12:47:35.039676 8, 0xFFFF, sum = 0
3036 12:47:35.039795 9, 0xFFFF, sum = 0
3037 12:47:35.043441 10, 0xFFFF, sum = 0
3038 12:47:35.043564 11, 0xFFFF, sum = 0
3039 12:47:35.046333 12, 0x0, sum = 1
3040 12:47:35.046453 13, 0x0, sum = 2
3041 12:47:35.049808 14, 0x0, sum = 3
3042 12:47:35.049928 15, 0x0, sum = 4
3043 12:47:35.049999 best_step = 13
3044 12:47:35.053097
3045 12:47:35.053208 ==
3046 12:47:35.056625 Dram Type= 6, Freq= 0, CH_0, rank 1
3047 12:47:35.060008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3048 12:47:35.060179 ==
3049 12:47:35.060291 RX Vref Scan: 0
3050 12:47:35.060387
3051 12:47:35.063008 RX Vref 0 -> 0, step: 1
3052 12:47:35.063133
3053 12:47:35.066489 RX Delay -21 -> 252, step: 4
3054 12:47:35.069788 iDelay=199, Bit 0, Center 112 (47 ~ 178) 132
3055 12:47:35.076485 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3056 12:47:35.079866 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3057 12:47:35.083448 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3058 12:47:35.086262 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3059 12:47:35.089501 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3060 12:47:35.096544 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3061 12:47:35.099490 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3062 12:47:35.103028 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3063 12:47:35.106546 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3064 12:47:35.109486 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3065 12:47:35.116018 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3066 12:47:35.119427 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3067 12:47:35.122983 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3068 12:47:35.126398 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3069 12:47:35.129569 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3070 12:47:35.132986 ==
3071 12:47:35.133121 Dram Type= 6, Freq= 0, CH_0, rank 1
3072 12:47:35.139518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 12:47:35.139665 ==
3074 12:47:35.139740 DQS Delay:
3075 12:47:35.143049 DQS0 = 0, DQS1 = 0
3076 12:47:35.143179 DQM Delay:
3077 12:47:35.145857 DQM0 = 116, DQM1 = 108
3078 12:47:35.145969 DQ Delay:
3079 12:47:35.149435 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3080 12:47:35.152723 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3081 12:47:35.155729 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3082 12:47:35.159163 DQ12 =114, DQ13 =114, DQ14 =120, DQ15 =116
3083 12:47:35.159342
3084 12:47:35.159451
3085 12:47:35.168889 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 403 ps
3086 12:47:35.172438 CH0 RK1: MR19=403, MR18=10EA
3087 12:47:35.175764 CH0_RK1: MR19=0x403, MR18=0x10EA, DQSOSC=403, MR23=63, INC=40, DEC=26
3088 12:47:35.178964 [RxdqsGatingPostProcess] freq 1200
3089 12:47:35.185503 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3090 12:47:35.188947 best DQS0 dly(2T, 0.5T) = (0, 11)
3091 12:47:35.192448 best DQS1 dly(2T, 0.5T) = (0, 12)
3092 12:47:35.195823 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3093 12:47:35.199185 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3094 12:47:35.202532 best DQS0 dly(2T, 0.5T) = (0, 11)
3095 12:47:35.206035 best DQS1 dly(2T, 0.5T) = (0, 12)
3096 12:47:35.208971 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3097 12:47:35.209129 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3098 12:47:35.212463 Pre-setting of DQS Precalculation
3099 12:47:35.218863 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3100 12:47:35.219049 ==
3101 12:47:35.222405 Dram Type= 6, Freq= 0, CH_1, rank 0
3102 12:47:35.225836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3103 12:47:35.226020 ==
3104 12:47:35.232309 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3105 12:47:35.238553 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3106 12:47:35.246167 [CA 0] Center 37 (7~68) winsize 62
3107 12:47:35.249752 [CA 1] Center 37 (7~68) winsize 62
3108 12:47:35.252698 [CA 2] Center 34 (4~64) winsize 61
3109 12:47:35.256184 [CA 3] Center 33 (3~64) winsize 62
3110 12:47:35.259657 [CA 4] Center 34 (4~64) winsize 61
3111 12:47:35.262742 [CA 5] Center 33 (3~64) winsize 62
3112 12:47:35.262868
3113 12:47:35.265865 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3114 12:47:35.265960
3115 12:47:35.269122 [CATrainingPosCal] consider 1 rank data
3116 12:47:35.272519 u2DelayCellTimex100 = 270/100 ps
3117 12:47:35.276431 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3118 12:47:35.282588 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3119 12:47:35.285880 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3120 12:47:35.289404 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3121 12:47:35.292531 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3122 12:47:35.295655 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3123 12:47:35.295802
3124 12:47:35.299110 CA PerBit enable=1, Macro0, CA PI delay=33
3125 12:47:35.299237
3126 12:47:35.302460 [CBTSetCACLKResult] CA Dly = 33
3127 12:47:35.302640 CS Dly: 5 (0~36)
3128 12:47:35.305919 ==
3129 12:47:35.309224 Dram Type= 6, Freq= 0, CH_1, rank 1
3130 12:47:35.312669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 12:47:35.312810 ==
3132 12:47:35.315615 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3133 12:47:35.322651 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3134 12:47:35.331955 [CA 0] Center 37 (7~68) winsize 62
3135 12:47:35.335306 [CA 1] Center 37 (7~68) winsize 62
3136 12:47:35.338208 [CA 2] Center 34 (4~65) winsize 62
3137 12:47:35.341784 [CA 3] Center 33 (3~64) winsize 62
3138 12:47:35.344809 [CA 4] Center 34 (3~65) winsize 63
3139 12:47:35.348395 [CA 5] Center 33 (3~64) winsize 62
3140 12:47:35.348523
3141 12:47:35.351840 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3142 12:47:35.351960
3143 12:47:35.354677 [CATrainingPosCal] consider 2 rank data
3144 12:47:35.358432 u2DelayCellTimex100 = 270/100 ps
3145 12:47:35.361434 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3146 12:47:35.368517 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3147 12:47:35.371421 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3148 12:47:35.374671 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3149 12:47:35.378431 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3150 12:47:35.381581 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3151 12:47:35.381754
3152 12:47:35.384936 CA PerBit enable=1, Macro0, CA PI delay=33
3153 12:47:35.385079
3154 12:47:35.388386 [CBTSetCACLKResult] CA Dly = 33
3155 12:47:35.388511 CS Dly: 7 (0~40)
3156 12:47:35.391337
3157 12:47:35.394741 ----->DramcWriteLeveling(PI) begin...
3158 12:47:35.394872 ==
3159 12:47:35.398248 Dram Type= 6, Freq= 0, CH_1, rank 0
3160 12:47:35.401176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3161 12:47:35.401316 ==
3162 12:47:35.404697 Write leveling (Byte 0): 26 => 26
3163 12:47:35.408000 Write leveling (Byte 1): 28 => 28
3164 12:47:35.411277 DramcWriteLeveling(PI) end<-----
3165 12:47:35.411425
3166 12:47:35.411496 ==
3167 12:47:35.414803 Dram Type= 6, Freq= 0, CH_1, rank 0
3168 12:47:35.418364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3169 12:47:35.418528 ==
3170 12:47:35.421200 [Gating] SW mode calibration
3171 12:47:35.427698 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3172 12:47:35.434306 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3173 12:47:35.438244 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3174 12:47:35.441125 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3175 12:47:35.447736 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 12:47:35.451197 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 12:47:35.454575 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 12:47:35.461091 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 12:47:35.464445 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
3180 12:47:35.467940 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (1 0)
3181 12:47:35.470973 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 12:47:35.477905 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 12:47:35.481307 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 12:47:35.484408 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 12:47:35.491239 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 12:47:35.494393 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 12:47:35.498026 1 0 24 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
3188 12:47:35.504224 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3189 12:47:35.507953 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 12:47:35.510874 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 12:47:35.518045 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 12:47:35.520969 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 12:47:35.524445 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 12:47:35.531355 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 12:47:35.534819 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3196 12:47:35.537737 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3197 12:47:35.544693 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 12:47:35.547602 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 12:47:35.551040 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 12:47:35.557475 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 12:47:35.561088 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 12:47:35.564464 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 12:47:35.570906 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 12:47:35.574272 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 12:47:35.577218 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 12:47:35.583977 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 12:47:35.587009 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 12:47:35.590627 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 12:47:35.597193 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 12:47:35.600619 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 12:47:35.604085 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3212 12:47:35.610343 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3213 12:47:35.610531 Total UI for P1: 0, mck2ui 16
3214 12:47:35.617133 best dqsien dly found for B0: ( 1, 3, 24)
3215 12:47:35.620313 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 12:47:35.623806 Total UI for P1: 0, mck2ui 16
3217 12:47:35.627007 best dqsien dly found for B1: ( 1, 3, 26)
3218 12:47:35.630147 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3219 12:47:35.633583 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3220 12:47:35.633714
3221 12:47:35.637152 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3222 12:47:35.640479 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3223 12:47:35.643498 [Gating] SW calibration Done
3224 12:47:35.643639 ==
3225 12:47:35.647049 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 12:47:35.650563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 12:47:35.650717 ==
3228 12:47:35.653377 RX Vref Scan: 0
3229 12:47:35.653509
3230 12:47:35.656836 RX Vref 0 -> 0, step: 1
3231 12:47:35.656959
3232 12:47:35.657029 RX Delay -40 -> 252, step: 8
3233 12:47:35.663385 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3234 12:47:35.666981 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3235 12:47:35.670430 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3236 12:47:35.673229 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3237 12:47:35.676764 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3238 12:47:35.683312 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3239 12:47:35.686754 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3240 12:47:35.690000 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3241 12:47:35.693570 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3242 12:47:35.696703 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3243 12:47:35.703161 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3244 12:47:35.706602 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3245 12:47:35.710157 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3246 12:47:35.713526 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3247 12:47:35.716452 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3248 12:47:35.723171 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3249 12:47:35.723344 ==
3250 12:47:35.726476 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 12:47:35.729976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 12:47:35.730139 ==
3253 12:47:35.730246 DQS Delay:
3254 12:47:35.733506 DQS0 = 0, DQS1 = 0
3255 12:47:35.733644 DQM Delay:
3256 12:47:35.736542 DQM0 = 118, DQM1 = 109
3257 12:47:35.736699 DQ Delay:
3258 12:47:35.740305 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3259 12:47:35.743222 DQ4 =115, DQ5 =131, DQ6 =123, DQ7 =115
3260 12:47:35.746662 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3261 12:47:35.749841 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3262 12:47:35.750006
3263 12:47:35.750107
3264 12:47:35.753384 ==
3265 12:47:35.753539 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 12:47:35.759897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 12:47:35.760073 ==
3268 12:47:35.760177
3269 12:47:35.760270
3270 12:47:35.763513 TX Vref Scan disable
3271 12:47:35.763656 == TX Byte 0 ==
3272 12:47:35.766435 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3273 12:47:35.772850 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3274 12:47:35.773027 == TX Byte 1 ==
3275 12:47:35.776537 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3276 12:47:35.782915 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3277 12:47:35.783107 ==
3278 12:47:35.786412 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 12:47:35.789322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 12:47:35.789475 ==
3281 12:47:35.801429 TX Vref=22, minBit 3, minWin=25, winSum=415
3282 12:47:35.805331 TX Vref=24, minBit 9, minWin=25, winSum=423
3283 12:47:35.808685 TX Vref=26, minBit 8, minWin=25, winSum=428
3284 12:47:35.811594 TX Vref=28, minBit 10, minWin=25, winSum=432
3285 12:47:35.814975 TX Vref=30, minBit 4, minWin=26, winSum=431
3286 12:47:35.821633 TX Vref=32, minBit 9, minWin=25, winSum=426
3287 12:47:35.825067 [TxChooseVref] Worse bit 4, Min win 26, Win sum 431, Final Vref 30
3288 12:47:35.825221
3289 12:47:35.827910 Final TX Range 1 Vref 30
3290 12:47:35.828025
3291 12:47:35.828093 ==
3292 12:47:35.831405 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 12:47:35.834492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3294 12:47:35.837802 ==
3295 12:47:35.837977
3296 12:47:35.838089
3297 12:47:35.838183 TX Vref Scan disable
3298 12:47:35.841346 == TX Byte 0 ==
3299 12:47:35.844834 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3300 12:47:35.851262 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3301 12:47:35.851425 == TX Byte 1 ==
3302 12:47:35.854779 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3303 12:47:35.861091 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3304 12:47:35.861234
3305 12:47:35.861304 [DATLAT]
3306 12:47:35.861366 Freq=1200, CH1 RK0
3307 12:47:35.861425
3308 12:47:35.864504 DATLAT Default: 0xd
3309 12:47:35.864629 0, 0xFFFF, sum = 0
3310 12:47:35.868029 1, 0xFFFF, sum = 0
3311 12:47:35.871033 2, 0xFFFF, sum = 0
3312 12:47:35.871166 3, 0xFFFF, sum = 0
3313 12:47:35.874628 4, 0xFFFF, sum = 0
3314 12:47:35.874757 5, 0xFFFF, sum = 0
3315 12:47:35.878098 6, 0xFFFF, sum = 0
3316 12:47:35.878250 7, 0xFFFF, sum = 0
3317 12:47:35.881092 8, 0xFFFF, sum = 0
3318 12:47:35.881217 9, 0xFFFF, sum = 0
3319 12:47:35.884656 10, 0xFFFF, sum = 0
3320 12:47:35.884778 11, 0xFFFF, sum = 0
3321 12:47:35.888032 12, 0x0, sum = 1
3322 12:47:35.888155 13, 0x0, sum = 2
3323 12:47:35.891068 14, 0x0, sum = 3
3324 12:47:35.891215 15, 0x0, sum = 4
3325 12:47:35.891317 best_step = 13
3326 12:47:35.894620
3327 12:47:35.894737 ==
3328 12:47:35.897976 Dram Type= 6, Freq= 0, CH_1, rank 0
3329 12:47:35.901015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3330 12:47:35.901142 ==
3331 12:47:35.901211 RX Vref Scan: 1
3332 12:47:35.901272
3333 12:47:35.904491 Set Vref Range= 32 -> 127
3334 12:47:35.904637
3335 12:47:35.908102 RX Vref 32 -> 127, step: 1
3336 12:47:35.908228
3337 12:47:35.911037 RX Delay -21 -> 252, step: 4
3338 12:47:35.911181
3339 12:47:35.914054 Set Vref, RX VrefLevel [Byte0]: 32
3340 12:47:35.917546 [Byte1]: 32
3341 12:47:35.917707
3342 12:47:35.921059 Set Vref, RX VrefLevel [Byte0]: 33
3343 12:47:35.924614 [Byte1]: 33
3344 12:47:35.927615
3345 12:47:35.927749 Set Vref, RX VrefLevel [Byte0]: 34
3346 12:47:35.930877 [Byte1]: 34
3347 12:47:35.935703
3348 12:47:35.935834 Set Vref, RX VrefLevel [Byte0]: 35
3349 12:47:35.939284 [Byte1]: 35
3350 12:47:35.943431
3351 12:47:35.943582 Set Vref, RX VrefLevel [Byte0]: 36
3352 12:47:35.946828 [Byte1]: 36
3353 12:47:35.951352
3354 12:47:35.951496 Set Vref, RX VrefLevel [Byte0]: 37
3355 12:47:35.954845 [Byte1]: 37
3356 12:47:35.959479
3357 12:47:35.959627 Set Vref, RX VrefLevel [Byte0]: 38
3358 12:47:35.963544 [Byte1]: 38
3359 12:47:35.967332
3360 12:47:35.967559 Set Vref, RX VrefLevel [Byte0]: 39
3361 12:47:35.970883 [Byte1]: 39
3362 12:47:35.975472
3363 12:47:35.975697 Set Vref, RX VrefLevel [Byte0]: 40
3364 12:47:35.978662 [Byte1]: 40
3365 12:47:35.983445
3366 12:47:35.983691 Set Vref, RX VrefLevel [Byte0]: 41
3367 12:47:35.986346 [Byte1]: 41
3368 12:47:35.991075
3369 12:47:35.991286 Set Vref, RX VrefLevel [Byte0]: 42
3370 12:47:35.994818 [Byte1]: 42
3371 12:47:35.999143
3372 12:47:35.999358 Set Vref, RX VrefLevel [Byte0]: 43
3373 12:47:36.002605 [Byte1]: 43
3374 12:47:36.007203
3375 12:47:36.007409 Set Vref, RX VrefLevel [Byte0]: 44
3376 12:47:36.010134 [Byte1]: 44
3377 12:47:36.014831
3378 12:47:36.015058 Set Vref, RX VrefLevel [Byte0]: 45
3379 12:47:36.018377 [Byte1]: 45
3380 12:47:36.023102
3381 12:47:36.023320 Set Vref, RX VrefLevel [Byte0]: 46
3382 12:47:36.026032 [Byte1]: 46
3383 12:47:36.030554
3384 12:47:36.030781 Set Vref, RX VrefLevel [Byte0]: 47
3385 12:47:36.034033 [Byte1]: 47
3386 12:47:36.038717
3387 12:47:36.038854 Set Vref, RX VrefLevel [Byte0]: 48
3388 12:47:36.041780 [Byte1]: 48
3389 12:47:36.046412
3390 12:47:36.046560 Set Vref, RX VrefLevel [Byte0]: 49
3391 12:47:36.049981 [Byte1]: 49
3392 12:47:36.054567
3393 12:47:36.054717 Set Vref, RX VrefLevel [Byte0]: 50
3394 12:47:36.057585 [Byte1]: 50
3395 12:47:36.062653
3396 12:47:36.062790 Set Vref, RX VrefLevel [Byte0]: 51
3397 12:47:36.065856 [Byte1]: 51
3398 12:47:36.070439
3399 12:47:36.070609 Set Vref, RX VrefLevel [Byte0]: 52
3400 12:47:36.073682 [Byte1]: 52
3401 12:47:36.078505
3402 12:47:36.078669 Set Vref, RX VrefLevel [Byte0]: 53
3403 12:47:36.081851 [Byte1]: 53
3404 12:47:36.086047
3405 12:47:36.086185 Set Vref, RX VrefLevel [Byte0]: 54
3406 12:47:36.089665 [Byte1]: 54
3407 12:47:36.094465
3408 12:47:36.094644 Set Vref, RX VrefLevel [Byte0]: 55
3409 12:47:36.097388 [Byte1]: 55
3410 12:47:36.102113
3411 12:47:36.102255 Set Vref, RX VrefLevel [Byte0]: 56
3412 12:47:36.105022 [Byte1]: 56
3413 12:47:36.110246
3414 12:47:36.110420 Set Vref, RX VrefLevel [Byte0]: 57
3415 12:47:36.113103 [Byte1]: 57
3416 12:47:36.117822
3417 12:47:36.117961 Set Vref, RX VrefLevel [Byte0]: 58
3418 12:47:36.121482 [Byte1]: 58
3419 12:47:36.125616
3420 12:47:36.125753 Set Vref, RX VrefLevel [Byte0]: 59
3421 12:47:36.129058 [Byte1]: 59
3422 12:47:36.133761
3423 12:47:36.133902 Set Vref, RX VrefLevel [Byte0]: 60
3424 12:47:36.140250 [Byte1]: 60
3425 12:47:36.140384
3426 12:47:36.143722 Set Vref, RX VrefLevel [Byte0]: 61
3427 12:47:36.146798 [Byte1]: 61
3428 12:47:36.146911
3429 12:47:36.149979 Set Vref, RX VrefLevel [Byte0]: 62
3430 12:47:36.153203 [Byte1]: 62
3431 12:47:36.157369
3432 12:47:36.157602 Set Vref, RX VrefLevel [Byte0]: 63
3433 12:47:36.160708 [Byte1]: 63
3434 12:47:36.165096
3435 12:47:36.165262 Set Vref, RX VrefLevel [Byte0]: 64
3436 12:47:36.168939 [Byte1]: 64
3437 12:47:36.173453
3438 12:47:36.173641 Set Vref, RX VrefLevel [Byte0]: 65
3439 12:47:36.176552 [Byte1]: 65
3440 12:47:36.181140
3441 12:47:36.181294 Set Vref, RX VrefLevel [Byte0]: 66
3442 12:47:36.184572 [Byte1]: 66
3443 12:47:36.189181
3444 12:47:36.189357 Set Vref, RX VrefLevel [Byte0]: 67
3445 12:47:36.192735 [Byte1]: 67
3446 12:47:36.196994
3447 12:47:36.197122 Set Vref, RX VrefLevel [Byte0]: 68
3448 12:47:36.200447 [Byte1]: 68
3449 12:47:36.204898
3450 12:47:36.205071 Set Vref, RX VrefLevel [Byte0]: 69
3451 12:47:36.208382 [Byte1]: 69
3452 12:47:36.265505
3453 12:47:36.265696 Final RX Vref Byte 0 = 51 to rank0
3454 12:47:36.265836 Final RX Vref Byte 1 = 61 to rank0
3455 12:47:36.265965 Final RX Vref Byte 0 = 51 to rank1
3456 12:47:36.266073 Final RX Vref Byte 1 = 61 to rank1==
3457 12:47:36.266140 Dram Type= 6, Freq= 0, CH_1, rank 0
3458 12:47:36.266201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3459 12:47:36.266261 ==
3460 12:47:36.266318 DQS Delay:
3461 12:47:36.266373 DQS0 = 0, DQS1 = 0
3462 12:47:36.266427 DQM Delay:
3463 12:47:36.266482 DQM0 = 115, DQM1 = 112
3464 12:47:36.266535 DQ Delay:
3465 12:47:36.266613 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =110
3466 12:47:36.266687 DQ4 =112, DQ5 =128, DQ6 =124, DQ7 =112
3467 12:47:36.266741 DQ8 =100, DQ9 =100, DQ10 =116, DQ11 =102
3468 12:47:36.266794 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =122
3469 12:47:36.266848
3470 12:47:36.266900
3471 12:47:36.266953 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 409 ps
3472 12:47:36.267007 CH1 RK0: MR19=403, MR18=2F6
3473 12:47:36.269121 CH1_RK0: MR19=0x403, MR18=0x2F6, DQSOSC=409, MR23=63, INC=39, DEC=26
3474 12:47:36.269204
3475 12:47:36.272209 ----->DramcWriteLeveling(PI) begin...
3476 12:47:36.272295 ==
3477 12:47:36.275861 Dram Type= 6, Freq= 0, CH_1, rank 1
3478 12:47:36.282399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 12:47:36.282559 ==
3480 12:47:36.285944 Write leveling (Byte 0): 24 => 24
3481 12:47:36.286064 Write leveling (Byte 1): 28 => 28
3482 12:47:36.289177 DramcWriteLeveling(PI) end<-----
3483 12:47:36.289308
3484 12:47:36.291996 ==
3485 12:47:36.292082 Dram Type= 6, Freq= 0, CH_1, rank 1
3486 12:47:36.299028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3487 12:47:36.299173 ==
3488 12:47:36.302060 [Gating] SW mode calibration
3489 12:47:36.308631 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3490 12:47:36.312101 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3491 12:47:36.318673 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3492 12:47:36.322224 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 12:47:36.325130 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 12:47:36.331622 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 12:47:36.335093 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 12:47:36.338570 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 12:47:36.344952 0 15 24 | B1->B0 | 2d2d 3131 | 1 0 | (1 0) (0 1)
3498 12:47:36.348443 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (1 0) (1 0)
3499 12:47:36.351434 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 12:47:36.358462 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 12:47:36.361558 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 12:47:36.364995 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 12:47:36.371458 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 12:47:36.374685 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3505 12:47:36.377797 1 0 24 | B1->B0 | 3434 2727 | 1 0 | (0 0) (0 0)
3506 12:47:36.384722 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 12:47:36.387795 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 12:47:36.391124 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 12:47:36.397974 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 12:47:36.400952 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 12:47:36.404491 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 12:47:36.411358 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 12:47:36.414437 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3514 12:47:36.417739 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3515 12:47:36.424287 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 12:47:36.427333 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 12:47:36.430804 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 12:47:36.437343 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 12:47:36.440880 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 12:47:36.444070 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 12:47:36.450860 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 12:47:36.453803 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 12:47:36.457432 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 12:47:36.464052 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 12:47:36.466975 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 12:47:36.470492 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 12:47:36.476993 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 12:47:36.480620 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 12:47:36.483410 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3530 12:47:36.490528 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3531 12:47:36.490692 Total UI for P1: 0, mck2ui 16
3532 12:47:36.496745 best dqsien dly found for B1: ( 1, 3, 24)
3533 12:47:36.500393 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 12:47:36.503503 Total UI for P1: 0, mck2ui 16
3535 12:47:36.506832 best dqsien dly found for B0: ( 1, 3, 26)
3536 12:47:36.510232 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3537 12:47:36.513750 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3538 12:47:36.513882
3539 12:47:36.516511 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3540 12:47:36.519954 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3541 12:47:36.523460 [Gating] SW calibration Done
3542 12:47:36.523580 ==
3543 12:47:36.526611 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 12:47:36.530081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 12:47:36.533067 ==
3546 12:47:36.533238 RX Vref Scan: 0
3547 12:47:36.533348
3548 12:47:36.536747 RX Vref 0 -> 0, step: 1
3549 12:47:36.536858
3550 12:47:36.539738 RX Delay -40 -> 252, step: 8
3551 12:47:36.543201 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3552 12:47:36.546165 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3553 12:47:36.549638 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3554 12:47:36.553164 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3555 12:47:36.559491 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3556 12:47:36.563067 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3557 12:47:36.566041 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3558 12:47:36.569617 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3559 12:47:36.573085 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3560 12:47:36.579684 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3561 12:47:36.582659 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3562 12:47:36.586234 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3563 12:47:36.589160 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3564 12:47:36.592548 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3565 12:47:36.599597 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3566 12:47:36.602434 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3567 12:47:36.602555 ==
3568 12:47:36.605976 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 12:47:36.609242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 12:47:36.609361 ==
3571 12:47:36.612911 DQS Delay:
3572 12:47:36.613037 DQS0 = 0, DQS1 = 0
3573 12:47:36.613107 DQM Delay:
3574 12:47:36.616408 DQM0 = 115, DQM1 = 110
3575 12:47:36.616525 DQ Delay:
3576 12:47:36.619200 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3577 12:47:36.622658 DQ4 =115, DQ5 =123, DQ6 =127, DQ7 =115
3578 12:47:36.626250 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =103
3579 12:47:36.632512 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3580 12:47:36.632663
3581 12:47:36.632734
3582 12:47:36.632796 ==
3583 12:47:36.635911 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 12:47:36.639202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 12:47:36.639330 ==
3586 12:47:36.639399
3587 12:47:36.639461
3588 12:47:36.642475 TX Vref Scan disable
3589 12:47:36.642579 == TX Byte 0 ==
3590 12:47:36.649034 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3591 12:47:36.652085 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3592 12:47:36.655573 == TX Byte 1 ==
3593 12:47:36.658566 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3594 12:47:36.662203 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3595 12:47:36.662354 ==
3596 12:47:36.665123 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 12:47:36.668702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 12:47:36.671681 ==
3599 12:47:36.681744 TX Vref=22, minBit 1, minWin=26, winSum=427
3600 12:47:36.685370 TX Vref=24, minBit 8, minWin=26, winSum=430
3601 12:47:36.688315 TX Vref=26, minBit 8, minWin=26, winSum=432
3602 12:47:36.691859 TX Vref=28, minBit 9, minWin=26, winSum=435
3603 12:47:36.695452 TX Vref=30, minBit 9, minWin=26, winSum=436
3604 12:47:36.698811 TX Vref=32, minBit 8, minWin=26, winSum=433
3605 12:47:36.705306 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 30
3606 12:47:36.705458
3607 12:47:36.708447 Final TX Range 1 Vref 30
3608 12:47:36.708559
3609 12:47:36.708626 ==
3610 12:47:36.711917 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 12:47:36.714879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 12:47:36.715041 ==
3613 12:47:36.718183
3614 12:47:36.718294
3615 12:47:36.718363 TX Vref Scan disable
3616 12:47:36.721669 == TX Byte 0 ==
3617 12:47:36.725053 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3618 12:47:36.728295 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3619 12:47:36.731591 == TX Byte 1 ==
3620 12:47:36.735131 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3621 12:47:36.738522 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3622 12:47:36.741379
3623 12:47:36.741500 [DATLAT]
3624 12:47:36.741568 Freq=1200, CH1 RK1
3625 12:47:36.741631
3626 12:47:36.744940 DATLAT Default: 0xd
3627 12:47:36.745052 0, 0xFFFF, sum = 0
3628 12:47:36.748275 1, 0xFFFF, sum = 0
3629 12:47:36.748398 2, 0xFFFF, sum = 0
3630 12:47:36.751692 3, 0xFFFF, sum = 0
3631 12:47:36.754611 4, 0xFFFF, sum = 0
3632 12:47:36.754729 5, 0xFFFF, sum = 0
3633 12:47:36.758107 6, 0xFFFF, sum = 0
3634 12:47:36.758241 7, 0xFFFF, sum = 0
3635 12:47:36.761690 8, 0xFFFF, sum = 0
3636 12:47:36.761801 9, 0xFFFF, sum = 0
3637 12:47:36.764648 10, 0xFFFF, sum = 0
3638 12:47:36.764753 11, 0xFFFF, sum = 0
3639 12:47:36.768384 12, 0x0, sum = 1
3640 12:47:36.768498 13, 0x0, sum = 2
3641 12:47:36.771247 14, 0x0, sum = 3
3642 12:47:36.771345 15, 0x0, sum = 4
3643 12:47:36.774754 best_step = 13
3644 12:47:36.774884
3645 12:47:36.774989 ==
3646 12:47:36.778238 Dram Type= 6, Freq= 0, CH_1, rank 1
3647 12:47:36.781623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3648 12:47:36.781775 ==
3649 12:47:36.781881 RX Vref Scan: 0
3650 12:47:36.781986
3651 12:47:36.784601 RX Vref 0 -> 0, step: 1
3652 12:47:36.784723
3653 12:47:36.788254 RX Delay -13 -> 252, step: 4
3654 12:47:36.791196 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3655 12:47:36.797821 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3656 12:47:36.801453 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3657 12:47:36.804351 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3658 12:47:36.807853 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3659 12:47:36.814425 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3660 12:47:36.817555 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3661 12:47:36.821126 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3662 12:47:36.824472 iDelay=199, Bit 8, Center 100 (35 ~ 166) 132
3663 12:47:36.827749 iDelay=199, Bit 9, Center 98 (35 ~ 162) 128
3664 12:47:36.834212 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3665 12:47:36.837519 iDelay=199, Bit 11, Center 104 (39 ~ 170) 132
3666 12:47:36.840748 iDelay=199, Bit 12, Center 118 (55 ~ 182) 128
3667 12:47:36.844122 iDelay=199, Bit 13, Center 118 (55 ~ 182) 128
3668 12:47:36.846944 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3669 12:47:36.853937 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3670 12:47:36.854126 ==
3671 12:47:36.857131 Dram Type= 6, Freq= 0, CH_1, rank 1
3672 12:47:36.860237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3673 12:47:36.860402 ==
3674 12:47:36.860519 DQS Delay:
3675 12:47:36.864058 DQS0 = 0, DQS1 = 0
3676 12:47:36.864196 DQM Delay:
3677 12:47:36.867075 DQM0 = 117, DQM1 = 111
3678 12:47:36.867182 DQ Delay:
3679 12:47:36.870547 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =112
3680 12:47:36.873618 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =116
3681 12:47:36.877187 DQ8 =100, DQ9 =98, DQ10 =112, DQ11 =104
3682 12:47:36.880173 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3683 12:47:36.883712
3684 12:47:36.883848
3685 12:47:36.890195 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6f1, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
3686 12:47:36.893262 CH1 RK1: MR19=303, MR18=F6F1
3687 12:47:36.899871 CH1_RK1: MR19=0x303, MR18=0xF6F1, DQSOSC=414, MR23=63, INC=38, DEC=25
3688 12:47:36.903408 [RxdqsGatingPostProcess] freq 1200
3689 12:47:36.906611 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3690 12:47:36.910142 best DQS0 dly(2T, 0.5T) = (0, 11)
3691 12:47:36.913162 best DQS1 dly(2T, 0.5T) = (0, 11)
3692 12:47:36.916711 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3693 12:47:36.919681 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3694 12:47:36.923046 best DQS0 dly(2T, 0.5T) = (0, 11)
3695 12:47:36.926794 best DQS1 dly(2T, 0.5T) = (0, 11)
3696 12:47:36.929862 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3697 12:47:36.933281 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3698 12:47:36.936414 Pre-setting of DQS Precalculation
3699 12:47:36.939980 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3700 12:47:36.949428 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3701 12:47:36.956444 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3702 12:47:36.956583
3703 12:47:36.956651
3704 12:47:36.959339 [Calibration Summary] 2400 Mbps
3705 12:47:36.959444 CH 0, Rank 0
3706 12:47:36.962619 SW Impedance : PASS
3707 12:47:36.962733 DUTY Scan : NO K
3708 12:47:36.965834 ZQ Calibration : PASS
3709 12:47:36.969292 Jitter Meter : NO K
3710 12:47:36.969422 CBT Training : PASS
3711 12:47:36.972665 Write leveling : PASS
3712 12:47:36.976241 RX DQS gating : PASS
3713 12:47:36.976368 RX DQ/DQS(RDDQC) : PASS
3714 12:47:36.979278 TX DQ/DQS : PASS
3715 12:47:36.982337 RX DATLAT : PASS
3716 12:47:36.982454 RX DQ/DQS(Engine): PASS
3717 12:47:36.985877 TX OE : NO K
3718 12:47:36.986013 All Pass.
3719 12:47:36.986122
3720 12:47:36.989346 CH 0, Rank 1
3721 12:47:36.989473 SW Impedance : PASS
3722 12:47:36.992317 DUTY Scan : NO K
3723 12:47:36.995856 ZQ Calibration : PASS
3724 12:47:36.995978 Jitter Meter : NO K
3725 12:47:36.998797 CBT Training : PASS
3726 12:47:37.002542 Write leveling : PASS
3727 12:47:37.002676 RX DQS gating : PASS
3728 12:47:37.005485 RX DQ/DQS(RDDQC) : PASS
3729 12:47:37.005581 TX DQ/DQS : PASS
3730 12:47:37.009091 RX DATLAT : PASS
3731 12:47:37.012385 RX DQ/DQS(Engine): PASS
3732 12:47:37.012506 TX OE : NO K
3733 12:47:37.015309 All Pass.
3734 12:47:37.015417
3735 12:47:37.015486 CH 1, Rank 0
3736 12:47:37.018951 SW Impedance : PASS
3737 12:47:37.019064 DUTY Scan : NO K
3738 12:47:37.021971 ZQ Calibration : PASS
3739 12:47:37.025592 Jitter Meter : NO K
3740 12:47:37.025721 CBT Training : PASS
3741 12:47:37.028583 Write leveling : PASS
3742 12:47:37.032309 RX DQS gating : PASS
3743 12:47:37.032445 RX DQ/DQS(RDDQC) : PASS
3744 12:47:37.035252 TX DQ/DQS : PASS
3745 12:47:37.038349 RX DATLAT : PASS
3746 12:47:37.038488 RX DQ/DQS(Engine): PASS
3747 12:47:37.042000 TX OE : NO K
3748 12:47:37.042141 All Pass.
3749 12:47:37.042244
3750 12:47:37.045001 CH 1, Rank 1
3751 12:47:37.045124 SW Impedance : PASS
3752 12:47:37.048503 DUTY Scan : NO K
3753 12:47:37.051926 ZQ Calibration : PASS
3754 12:47:37.052044 Jitter Meter : NO K
3755 12:47:37.055351 CBT Training : PASS
3756 12:47:37.058151 Write leveling : PASS
3757 12:47:37.058260 RX DQS gating : PASS
3758 12:47:37.061341 RX DQ/DQS(RDDQC) : PASS
3759 12:47:37.064970 TX DQ/DQS : PASS
3760 12:47:37.065120 RX DATLAT : PASS
3761 12:47:37.068133 RX DQ/DQS(Engine): PASS
3762 12:47:37.071646 TX OE : NO K
3763 12:47:37.071802 All Pass.
3764 12:47:37.071914
3765 12:47:37.072013 DramC Write-DBI off
3766 12:47:37.074932 PER_BANK_REFRESH: Hybrid Mode
3767 12:47:37.077975 TX_TRACKING: ON
3768 12:47:37.084450 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3769 12:47:37.088082 [FAST_K] Save calibration result to emmc
3770 12:47:37.094480 dramc_set_vcore_voltage set vcore to 650000
3771 12:47:37.094673 Read voltage for 600, 5
3772 12:47:37.098020 Vio18 = 0
3773 12:47:37.098137 Vcore = 650000
3774 12:47:37.098207 Vdram = 0
3775 12:47:37.101184 Vddq = 0
3776 12:47:37.101288 Vmddr = 0
3777 12:47:37.104755 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3778 12:47:37.111285 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3779 12:47:37.114873 MEM_TYPE=3, freq_sel=19
3780 12:47:37.117626 sv_algorithm_assistance_LP4_1600
3781 12:47:37.121384 ============ PULL DRAM RESETB DOWN ============
3782 12:47:37.124277 ========== PULL DRAM RESETB DOWN end =========
3783 12:47:37.130937 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3784 12:47:37.131077 ===================================
3785 12:47:37.134117 LPDDR4 DRAM CONFIGURATION
3786 12:47:37.137748 ===================================
3787 12:47:37.141230 EX_ROW_EN[0] = 0x0
3788 12:47:37.141366 EX_ROW_EN[1] = 0x0
3789 12:47:37.144767 LP4Y_EN = 0x0
3790 12:47:37.144933 WORK_FSP = 0x0
3791 12:47:37.147712 WL = 0x2
3792 12:47:37.147852 RL = 0x2
3793 12:47:37.151086 BL = 0x2
3794 12:47:37.151208 RPST = 0x0
3795 12:47:37.154405 RD_PRE = 0x0
3796 12:47:37.157807 WR_PRE = 0x1
3797 12:47:37.157919 WR_PST = 0x0
3798 12:47:37.161111 DBI_WR = 0x0
3799 12:47:37.161247 DBI_RD = 0x0
3800 12:47:37.164376 OTF = 0x1
3801 12:47:37.167235 ===================================
3802 12:47:37.170982 ===================================
3803 12:47:37.171141 ANA top config
3804 12:47:37.173773 ===================================
3805 12:47:37.177476 DLL_ASYNC_EN = 0
3806 12:47:37.180686 ALL_SLAVE_EN = 1
3807 12:47:37.180800 NEW_RANK_MODE = 1
3808 12:47:37.184100 DLL_IDLE_MODE = 1
3809 12:47:37.186931 LP45_APHY_COMB_EN = 1
3810 12:47:37.190173 TX_ODT_DIS = 1
3811 12:47:37.193447 NEW_8X_MODE = 1
3812 12:47:37.196988 ===================================
3813 12:47:37.197104 ===================================
3814 12:47:37.200541 data_rate = 1200
3815 12:47:37.203712 CKR = 1
3816 12:47:37.207201 DQ_P2S_RATIO = 8
3817 12:47:37.210206 ===================================
3818 12:47:37.213795 CA_P2S_RATIO = 8
3819 12:47:37.216767 DQ_CA_OPEN = 0
3820 12:47:37.220165 DQ_SEMI_OPEN = 0
3821 12:47:37.220280 CA_SEMI_OPEN = 0
3822 12:47:37.223757 CA_FULL_RATE = 0
3823 12:47:37.226630 DQ_CKDIV4_EN = 1
3824 12:47:37.230342 CA_CKDIV4_EN = 1
3825 12:47:37.233332 CA_PREDIV_EN = 0
3826 12:47:37.236964 PH8_DLY = 0
3827 12:47:37.237073 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3828 12:47:37.239987 DQ_AAMCK_DIV = 4
3829 12:47:37.243065 CA_AAMCK_DIV = 4
3830 12:47:37.246449 CA_ADMCK_DIV = 4
3831 12:47:37.250032 DQ_TRACK_CA_EN = 0
3832 12:47:37.252962 CA_PICK = 600
3833 12:47:37.256491 CA_MCKIO = 600
3834 12:47:37.256605 MCKIO_SEMI = 0
3835 12:47:37.259420 PLL_FREQ = 2288
3836 12:47:37.263001 DQ_UI_PI_RATIO = 32
3837 12:47:37.266362 CA_UI_PI_RATIO = 0
3838 12:47:37.269874 ===================================
3839 12:47:37.272659 ===================================
3840 12:47:37.276211 memory_type:LPDDR4
3841 12:47:37.276346 GP_NUM : 10
3842 12:47:37.279594 SRAM_EN : 1
3843 12:47:37.282888 MD32_EN : 0
3844 12:47:37.286171 ===================================
3845 12:47:37.286310 [ANA_INIT] >>>>>>>>>>>>>>
3846 12:47:37.288996 <<<<<< [CONFIGURE PHASE]: ANA_TX
3847 12:47:37.292541 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3848 12:47:37.296030 ===================================
3849 12:47:37.299446 data_rate = 1200,PCW = 0X5800
3850 12:47:37.302473 ===================================
3851 12:47:37.306094 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3852 12:47:37.312432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3853 12:47:37.315397 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3854 12:47:37.322575 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3855 12:47:37.325659 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3856 12:47:37.328684 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3857 12:47:37.332179 [ANA_INIT] flow start
3858 12:47:37.332329 [ANA_INIT] PLL >>>>>>>>
3859 12:47:37.335817 [ANA_INIT] PLL <<<<<<<<
3860 12:47:37.338916 [ANA_INIT] MIDPI >>>>>>>>
3861 12:47:37.339056 [ANA_INIT] MIDPI <<<<<<<<
3862 12:47:37.342439 [ANA_INIT] DLL >>>>>>>>
3863 12:47:37.345477 [ANA_INIT] flow end
3864 12:47:37.349049 ============ LP4 DIFF to SE enter ============
3865 12:47:37.352447 ============ LP4 DIFF to SE exit ============
3866 12:47:37.355473 [ANA_INIT] <<<<<<<<<<<<<
3867 12:47:37.358393 [Flow] Enable top DCM control >>>>>
3868 12:47:37.362005 [Flow] Enable top DCM control <<<<<
3869 12:47:37.365521 Enable DLL master slave shuffle
3870 12:47:37.368443 ==============================================================
3871 12:47:37.371822 Gating Mode config
3872 12:47:37.378918 ==============================================================
3873 12:47:37.379093 Config description:
3874 12:47:37.388397 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3875 12:47:37.395532 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3876 12:47:37.398462 SELPH_MODE 0: By rank 1: By Phase
3877 12:47:37.404912 ==============================================================
3878 12:47:37.408600 GAT_TRACK_EN = 1
3879 12:47:37.411991 RX_GATING_MODE = 2
3880 12:47:37.415017 RX_GATING_TRACK_MODE = 2
3881 12:47:37.418166 SELPH_MODE = 1
3882 12:47:37.421853 PICG_EARLY_EN = 1
3883 12:47:37.424755 VALID_LAT_VALUE = 1
3884 12:47:37.428417 ==============================================================
3885 12:47:37.431483 Enter into Gating configuration >>>>
3886 12:47:37.435040 Exit from Gating configuration <<<<
3887 12:47:37.438606 Enter into DVFS_PRE_config >>>>>
3888 12:47:37.451513 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3889 12:47:37.451654 Exit from DVFS_PRE_config <<<<<
3890 12:47:37.454761 Enter into PICG configuration >>>>
3891 12:47:37.458351 Exit from PICG configuration <<<<
3892 12:47:37.461232 [RX_INPUT] configuration >>>>>
3893 12:47:37.464601 [RX_INPUT] configuration <<<<<
3894 12:47:37.471161 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3895 12:47:37.474552 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3896 12:47:37.481651 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3897 12:47:37.487638 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3898 12:47:37.494718 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3899 12:47:37.501358 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3900 12:47:37.504088 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3901 12:47:37.507743 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3902 12:47:37.511269 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3903 12:47:37.517731 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3904 12:47:37.521145 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3905 12:47:37.524338 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3906 12:47:37.527502 ===================================
3907 12:47:37.530872 LPDDR4 DRAM CONFIGURATION
3908 12:47:37.534229 ===================================
3909 12:47:37.537739 EX_ROW_EN[0] = 0x0
3910 12:47:37.537887 EX_ROW_EN[1] = 0x0
3911 12:47:37.541097 LP4Y_EN = 0x0
3912 12:47:37.541262 WORK_FSP = 0x0
3913 12:47:37.544562 WL = 0x2
3914 12:47:37.544680 RL = 0x2
3915 12:47:37.547557 BL = 0x2
3916 12:47:37.547713 RPST = 0x0
3917 12:47:37.551140 RD_PRE = 0x0
3918 12:47:37.551257 WR_PRE = 0x1
3919 12:47:37.554051 WR_PST = 0x0
3920 12:47:37.554164 DBI_WR = 0x0
3921 12:47:37.557538 DBI_RD = 0x0
3922 12:47:37.557652 OTF = 0x1
3923 12:47:37.560402 ===================================
3924 12:47:37.567045 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3925 12:47:37.570428 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3926 12:47:37.573878 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3927 12:47:37.577361 ===================================
3928 12:47:37.580164 LPDDR4 DRAM CONFIGURATION
3929 12:47:37.583571 ===================================
3930 12:47:37.587182 EX_ROW_EN[0] = 0x10
3931 12:47:37.587313 EX_ROW_EN[1] = 0x0
3932 12:47:37.590177 LP4Y_EN = 0x0
3933 12:47:37.590295 WORK_FSP = 0x0
3934 12:47:37.593627 WL = 0x2
3935 12:47:37.593755 RL = 0x2
3936 12:47:37.596720 BL = 0x2
3937 12:47:37.596825 RPST = 0x0
3938 12:47:37.600376 RD_PRE = 0x0
3939 12:47:37.600487 WR_PRE = 0x1
3940 12:47:37.603452 WR_PST = 0x0
3941 12:47:37.603561 DBI_WR = 0x0
3942 12:47:37.607177 DBI_RD = 0x0
3943 12:47:37.607321 OTF = 0x1
3944 12:47:37.610296 ===================================
3945 12:47:37.616597 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3946 12:47:37.621260 nWR fixed to 30
3947 12:47:37.624690 [ModeRegInit_LP4] CH0 RK0
3948 12:47:37.624829 [ModeRegInit_LP4] CH0 RK1
3949 12:47:37.628433 [ModeRegInit_LP4] CH1 RK0
3950 12:47:37.631374 [ModeRegInit_LP4] CH1 RK1
3951 12:47:37.631489 match AC timing 17
3952 12:47:37.638386 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3953 12:47:37.641415 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3954 12:47:37.644805 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3955 12:47:37.651287 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3956 12:47:37.654334 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3957 12:47:37.654470 ==
3958 12:47:37.657911 Dram Type= 6, Freq= 0, CH_0, rank 0
3959 12:47:37.661041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3960 12:47:37.661171 ==
3961 12:47:37.667969 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3962 12:47:37.674343 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3963 12:47:37.677736 [CA 0] Center 36 (6~66) winsize 61
3964 12:47:37.681253 [CA 1] Center 36 (6~66) winsize 61
3965 12:47:37.684235 [CA 2] Center 33 (3~64) winsize 62
3966 12:47:37.687622 [CA 3] Center 34 (4~64) winsize 61
3967 12:47:37.691260 [CA 4] Center 33 (3~64) winsize 62
3968 12:47:37.694324 [CA 5] Center 33 (3~64) winsize 62
3969 12:47:37.694461
3970 12:47:37.697670 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3971 12:47:37.697825
3972 12:47:37.701331 [CATrainingPosCal] consider 1 rank data
3973 12:47:37.704460 u2DelayCellTimex100 = 270/100 ps
3974 12:47:37.707796 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3975 12:47:37.710861 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3976 12:47:37.714369 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
3977 12:47:37.717196 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3978 12:47:37.723848 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3979 12:47:37.727434 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3980 12:47:37.727538
3981 12:47:37.730221 CA PerBit enable=1, Macro0, CA PI delay=33
3982 12:47:37.730326
3983 12:47:37.733678 [CBTSetCACLKResult] CA Dly = 33
3984 12:47:37.733769 CS Dly: 5 (0~36)
3985 12:47:37.733856 ==
3986 12:47:37.737340 Dram Type= 6, Freq= 0, CH_0, rank 1
3987 12:47:37.743688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3988 12:47:37.743801 ==
3989 12:47:37.746790 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3990 12:47:37.753344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3991 12:47:37.756838 [CA 0] Center 35 (5~66) winsize 62
3992 12:47:37.759835 [CA 1] Center 36 (6~66) winsize 61
3993 12:47:37.763098 [CA 2] Center 34 (4~64) winsize 61
3994 12:47:37.766742 [CA 3] Center 33 (3~64) winsize 62
3995 12:47:37.770072 [CA 4] Center 33 (2~64) winsize 63
3996 12:47:37.773259 [CA 5] Center 33 (2~64) winsize 63
3997 12:47:37.773357
3998 12:47:37.776763 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3999 12:47:37.776882
4000 12:47:37.779924 [CATrainingPosCal] consider 2 rank data
4001 12:47:37.783088 u2DelayCellTimex100 = 270/100 ps
4002 12:47:37.786927 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4003 12:47:37.792850 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4004 12:47:37.796476 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4005 12:47:37.799472 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4006 12:47:37.802887 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4007 12:47:37.805921 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4008 12:47:37.806017
4009 12:47:37.809534 CA PerBit enable=1, Macro0, CA PI delay=33
4010 12:47:37.809623
4011 12:47:37.812546 [CBTSetCACLKResult] CA Dly = 33
4012 12:47:37.816199 CS Dly: 5 (0~36)
4013 12:47:37.816303
4014 12:47:37.819243 ----->DramcWriteLeveling(PI) begin...
4015 12:47:37.819333 ==
4016 12:47:37.822711 Dram Type= 6, Freq= 0, CH_0, rank 0
4017 12:47:37.826021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 12:47:37.826116 ==
4019 12:47:37.829080 Write leveling (Byte 0): 32 => 32
4020 12:47:37.832547 Write leveling (Byte 1): 31 => 31
4021 12:47:37.835920 DramcWriteLeveling(PI) end<-----
4022 12:47:37.836046
4023 12:47:37.836119 ==
4024 12:47:37.839557 Dram Type= 6, Freq= 0, CH_0, rank 0
4025 12:47:37.842221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4026 12:47:37.842310 ==
4027 12:47:37.845841 [Gating] SW mode calibration
4028 12:47:37.852466 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4029 12:47:37.859007 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4030 12:47:37.861990 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4031 12:47:37.868689 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 12:47:37.872361 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4033 12:47:37.875386 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
4034 12:47:37.879034 0 9 16 | B1->B0 | 2f2f 2727 | 1 0 | (1 0) (1 0)
4035 12:47:37.885425 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 12:47:37.888442 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 12:47:37.894834 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 12:47:37.898519 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 12:47:37.901533 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 12:47:37.908548 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 12:47:37.911725 0 10 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4042 12:47:37.915047 0 10 16 | B1->B0 | 3434 4141 | 0 0 | (0 0) (0 0)
4043 12:47:37.921230 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 12:47:37.924725 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 12:47:37.927725 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 12:47:37.934633 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 12:47:37.937824 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 12:47:37.941396 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 12:47:37.947517 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4050 12:47:37.951167 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 12:47:37.954218 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 12:47:37.960851 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 12:47:37.963984 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 12:47:37.967527 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 12:47:37.974192 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 12:47:37.977073 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 12:47:37.980708 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 12:47:37.987258 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 12:47:37.990222 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 12:47:37.993896 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 12:47:38.000429 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 12:47:38.003693 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 12:47:38.007215 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 12:47:38.013706 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 12:47:38.017062 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4066 12:47:38.020588 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4067 12:47:38.023643 Total UI for P1: 0, mck2ui 16
4068 12:47:38.026985 best dqsien dly found for B0: ( 0, 13, 12)
4069 12:47:38.030379 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 12:47:38.033225 Total UI for P1: 0, mck2ui 16
4071 12:47:38.036427 best dqsien dly found for B1: ( 0, 13, 14)
4072 12:47:38.043233 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4073 12:47:38.046454 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4074 12:47:38.046557
4075 12:47:38.050119 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4076 12:47:38.053376 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4077 12:47:38.056279 [Gating] SW calibration Done
4078 12:47:38.056388 ==
4079 12:47:38.059856 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 12:47:38.062914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 12:47:38.063007 ==
4082 12:47:38.066501 RX Vref Scan: 0
4083 12:47:38.066597
4084 12:47:38.066665 RX Vref 0 -> 0, step: 1
4085 12:47:38.066727
4086 12:47:38.069491 RX Delay -230 -> 252, step: 16
4087 12:47:38.076466 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4088 12:47:38.079471 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4089 12:47:38.083031 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4090 12:47:38.086122 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4091 12:47:38.089665 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4092 12:47:38.096364 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4093 12:47:38.099335 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4094 12:47:38.103022 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4095 12:47:38.105988 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4096 12:47:38.113084 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4097 12:47:38.116344 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4098 12:47:38.119373 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4099 12:47:38.122782 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4100 12:47:38.129362 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4101 12:47:38.132530 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4102 12:47:38.135899 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4103 12:47:38.136000 ==
4104 12:47:38.138982 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 12:47:38.142569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 12:47:38.142718 ==
4107 12:47:38.145636 DQS Delay:
4108 12:47:38.145727 DQS0 = 0, DQS1 = 0
4109 12:47:38.149293 DQM Delay:
4110 12:47:38.149406 DQM0 = 44, DQM1 = 33
4111 12:47:38.149475 DQ Delay:
4112 12:47:38.152263 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4113 12:47:38.155744 DQ4 =49, DQ5 =41, DQ6 =49, DQ7 =49
4114 12:47:38.158635 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4115 12:47:38.162391 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4116 12:47:38.162490
4117 12:47:38.162560
4118 12:47:38.165542 ==
4119 12:47:38.168648 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 12:47:38.172039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 12:47:38.172141 ==
4122 12:47:38.172209
4123 12:47:38.172269
4124 12:47:38.175674 TX Vref Scan disable
4125 12:47:38.175762 == TX Byte 0 ==
4126 12:47:38.182187 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4127 12:47:38.185166 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4128 12:47:38.185278 == TX Byte 1 ==
4129 12:47:38.191922 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4130 12:47:38.195491 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4131 12:47:38.195591 ==
4132 12:47:38.198504 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 12:47:38.202141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 12:47:38.202231 ==
4135 12:47:38.202299
4136 12:47:38.202359
4137 12:47:38.205052 TX Vref Scan disable
4138 12:47:38.208777 == TX Byte 0 ==
4139 12:47:38.211552 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4140 12:47:38.215031 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4141 12:47:38.218930 == TX Byte 1 ==
4142 12:47:38.221862 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4143 12:47:38.224912 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4144 12:47:38.228256
4145 12:47:38.228355 [DATLAT]
4146 12:47:38.228423 Freq=600, CH0 RK0
4147 12:47:38.228484
4148 12:47:38.231228 DATLAT Default: 0x9
4149 12:47:38.231316 0, 0xFFFF, sum = 0
4150 12:47:38.234834 1, 0xFFFF, sum = 0
4151 12:47:38.234934 2, 0xFFFF, sum = 0
4152 12:47:38.238280 3, 0xFFFF, sum = 0
4153 12:47:38.238371 4, 0xFFFF, sum = 0
4154 12:47:38.241224 5, 0xFFFF, sum = 0
4155 12:47:38.244773 6, 0xFFFF, sum = 0
4156 12:47:38.244865 7, 0xFFFF, sum = 0
4157 12:47:38.244933 8, 0x0, sum = 1
4158 12:47:38.248242 9, 0x0, sum = 2
4159 12:47:38.248331 10, 0x0, sum = 3
4160 12:47:38.251163 11, 0x0, sum = 4
4161 12:47:38.251253 best_step = 9
4162 12:47:38.251319
4163 12:47:38.251380 ==
4164 12:47:38.254487 Dram Type= 6, Freq= 0, CH_0, rank 0
4165 12:47:38.261730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 12:47:38.261862 ==
4167 12:47:38.261946 RX Vref Scan: 1
4168 12:47:38.262025
4169 12:47:38.264837 RX Vref 0 -> 0, step: 1
4170 12:47:38.264923
4171 12:47:38.268193 RX Delay -195 -> 252, step: 8
4172 12:47:38.268280
4173 12:47:38.271297 Set Vref, RX VrefLevel [Byte0]: 59
4174 12:47:38.274407 [Byte1]: 51
4175 12:47:38.274495
4176 12:47:38.278096 Final RX Vref Byte 0 = 59 to rank0
4177 12:47:38.281155 Final RX Vref Byte 1 = 51 to rank0
4178 12:47:38.284511 Final RX Vref Byte 0 = 59 to rank1
4179 12:47:38.287884 Final RX Vref Byte 1 = 51 to rank1==
4180 12:47:38.290821 Dram Type= 6, Freq= 0, CH_0, rank 0
4181 12:47:38.294183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 12:47:38.294277 ==
4183 12:47:38.297825 DQS Delay:
4184 12:47:38.297915 DQS0 = 0, DQS1 = 0
4185 12:47:38.300780 DQM Delay:
4186 12:47:38.300865 DQM0 = 43, DQM1 = 32
4187 12:47:38.300930 DQ Delay:
4188 12:47:38.304320 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4189 12:47:38.307384 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4190 12:47:38.311029 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4191 12:47:38.313916 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4192 12:47:38.314003
4193 12:47:38.314068
4194 12:47:38.324145 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d44, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 389 ps
4195 12:47:38.327515 CH0 RK0: MR19=808, MR18=6D44
4196 12:47:38.334306 CH0_RK0: MR19=0x808, MR18=0x6D44, DQSOSC=389, MR23=63, INC=173, DEC=115
4197 12:47:38.334433
4198 12:47:38.337438 ----->DramcWriteLeveling(PI) begin...
4199 12:47:38.337528 ==
4200 12:47:38.340785 Dram Type= 6, Freq= 0, CH_0, rank 1
4201 12:47:38.343764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 12:47:38.343855 ==
4203 12:47:38.347314 Write leveling (Byte 0): 34 => 34
4204 12:47:38.350931 Write leveling (Byte 1): 30 => 30
4205 12:47:38.353778 DramcWriteLeveling(PI) end<-----
4206 12:47:38.353875
4207 12:47:38.353957 ==
4208 12:47:38.357336 Dram Type= 6, Freq= 0, CH_0, rank 1
4209 12:47:38.360218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 12:47:38.360326 ==
4211 12:47:38.363824 [Gating] SW mode calibration
4212 12:47:38.370356 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4213 12:47:38.376964 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4214 12:47:38.380522 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4215 12:47:38.383371 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 12:47:38.390214 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4217 12:47:38.393685 0 9 12 | B1->B0 | 3333 3333 | 1 1 | (1 0) (1 0)
4218 12:47:38.396953 0 9 16 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
4219 12:47:38.403406 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 12:47:38.406625 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 12:47:38.410194 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 12:47:38.416646 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 12:47:38.420071 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 12:47:38.423090 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 12:47:38.429624 0 10 12 | B1->B0 | 2626 2b2b | 1 0 | (0 0) (0 0)
4226 12:47:38.433170 0 10 16 | B1->B0 | 3f3f 4343 | 0 0 | (0 0) (0 0)
4227 12:47:38.436487 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 12:47:38.443046 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 12:47:38.446730 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 12:47:38.449710 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 12:47:38.456516 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 12:47:38.459692 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 12:47:38.463500 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4234 12:47:38.469577 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4235 12:47:38.472553 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 12:47:38.476103 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 12:47:38.482726 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 12:47:38.486292 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 12:47:38.489294 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 12:47:38.496226 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 12:47:38.499099 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 12:47:38.502467 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 12:47:38.509343 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 12:47:38.512703 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 12:47:38.515914 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 12:47:38.522131 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 12:47:38.525493 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 12:47:38.529122 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 12:47:38.535584 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4250 12:47:38.538859 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 12:47:38.542100 Total UI for P1: 0, mck2ui 16
4252 12:47:38.545693 best dqsien dly found for B0: ( 0, 13, 12)
4253 12:47:38.548729 Total UI for P1: 0, mck2ui 16
4254 12:47:38.552295 best dqsien dly found for B1: ( 0, 13, 12)
4255 12:47:38.555876 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4256 12:47:38.558904 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4257 12:47:38.559004
4258 12:47:38.561846 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4259 12:47:38.565380 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4260 12:47:38.568851 [Gating] SW calibration Done
4261 12:47:38.568944 ==
4262 12:47:38.572283 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 12:47:38.575349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 12:47:38.578881 ==
4265 12:47:38.578978 RX Vref Scan: 0
4266 12:47:38.579044
4267 12:47:38.581945 RX Vref 0 -> 0, step: 1
4268 12:47:38.582032
4269 12:47:38.584963 RX Delay -230 -> 252, step: 16
4270 12:47:38.588558 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4271 12:47:38.591492 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4272 12:47:38.594882 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4273 12:47:38.601863 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4274 12:47:38.604833 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4275 12:47:38.608265 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4276 12:47:38.611652 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4277 12:47:38.614870 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4278 12:47:38.621623 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4279 12:47:38.624635 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4280 12:47:38.628115 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4281 12:47:38.631267 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4282 12:47:38.637904 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4283 12:47:38.640908 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4284 12:47:38.644731 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4285 12:47:38.650910 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4286 12:47:38.651045 ==
4287 12:47:38.654150 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 12:47:38.657427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 12:47:38.657527 ==
4290 12:47:38.657595 DQS Delay:
4291 12:47:38.660643 DQS0 = 0, DQS1 = 0
4292 12:47:38.660773 DQM Delay:
4293 12:47:38.664264 DQM0 = 41, DQM1 = 34
4294 12:47:38.664358 DQ Delay:
4295 12:47:38.667414 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4296 12:47:38.670918 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4297 12:47:38.673916 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4298 12:47:38.677575 DQ12 =33, DQ13 =49, DQ14 =49, DQ15 =33
4299 12:47:38.677671
4300 12:47:38.677735
4301 12:47:38.677795 ==
4302 12:47:38.680853 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 12:47:38.684167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 12:47:38.684256 ==
4305 12:47:38.684322
4306 12:47:38.687172
4307 12:47:38.687256 TX Vref Scan disable
4308 12:47:38.690841 == TX Byte 0 ==
4309 12:47:38.693679 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4310 12:47:38.697299 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4311 12:47:38.700826 == TX Byte 1 ==
4312 12:47:38.703834 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4313 12:47:38.707444 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4314 12:47:38.707574 ==
4315 12:47:38.710422 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 12:47:38.717094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 12:47:38.717220 ==
4318 12:47:38.717287
4319 12:47:38.717348
4320 12:47:38.720606 TX Vref Scan disable
4321 12:47:38.720693 == TX Byte 0 ==
4322 12:47:38.727154 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4323 12:47:38.730144 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4324 12:47:38.730235 == TX Byte 1 ==
4325 12:47:38.736596 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4326 12:47:38.739986 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4327 12:47:38.740110
4328 12:47:38.740177 [DATLAT]
4329 12:47:38.743691 Freq=600, CH0 RK1
4330 12:47:38.743782
4331 12:47:38.743852 DATLAT Default: 0x9
4332 12:47:38.746529 0, 0xFFFF, sum = 0
4333 12:47:38.746657 1, 0xFFFF, sum = 0
4334 12:47:38.749866 2, 0xFFFF, sum = 0
4335 12:47:38.749953 3, 0xFFFF, sum = 0
4336 12:47:38.753135 4, 0xFFFF, sum = 0
4337 12:47:38.756666 5, 0xFFFF, sum = 0
4338 12:47:38.756756 6, 0xFFFF, sum = 0
4339 12:47:38.760174 7, 0xFFFF, sum = 0
4340 12:47:38.760261 8, 0x0, sum = 1
4341 12:47:38.760328 9, 0x0, sum = 2
4342 12:47:38.763162 10, 0x0, sum = 3
4343 12:47:38.763250 11, 0x0, sum = 4
4344 12:47:38.766660 best_step = 9
4345 12:47:38.766763
4346 12:47:38.766842 ==
4347 12:47:38.769944 Dram Type= 6, Freq= 0, CH_0, rank 1
4348 12:47:38.773310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4349 12:47:38.773401 ==
4350 12:47:38.776720 RX Vref Scan: 0
4351 12:47:38.776808
4352 12:47:38.776872 RX Vref 0 -> 0, step: 1
4353 12:47:38.776933
4354 12:47:38.779717 RX Delay -179 -> 252, step: 8
4355 12:47:38.787386 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4356 12:47:38.790279 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4357 12:47:38.793629 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4358 12:47:38.796700 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4359 12:47:38.803271 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4360 12:47:38.807195 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4361 12:47:38.810378 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4362 12:47:38.813384 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4363 12:47:38.819927 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4364 12:47:38.823405 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4365 12:47:38.826649 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4366 12:47:38.829586 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4367 12:47:38.836139 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4368 12:47:38.839712 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4369 12:47:38.843227 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4370 12:47:38.846058 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4371 12:47:38.846156 ==
4372 12:47:38.849626 Dram Type= 6, Freq= 0, CH_0, rank 1
4373 12:47:38.856462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 12:47:38.856579 ==
4375 12:47:38.856646 DQS Delay:
4376 12:47:38.859267 DQS0 = 0, DQS1 = 0
4377 12:47:38.859353 DQM Delay:
4378 12:47:38.859419 DQM0 = 41, DQM1 = 36
4379 12:47:38.862577 DQ Delay:
4380 12:47:38.866164 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4381 12:47:38.869136 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4382 12:47:38.872623 DQ8 =24, DQ9 =20, DQ10 =40, DQ11 =28
4383 12:47:38.876080 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4384 12:47:38.876174
4385 12:47:38.876240
4386 12:47:38.882335 [DQSOSCAuto] RK1, (LSB)MR18= 0x6112, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4387 12:47:38.885831 CH0 RK1: MR19=808, MR18=6112
4388 12:47:38.892395 CH0_RK1: MR19=0x808, MR18=0x6112, DQSOSC=391, MR23=63, INC=171, DEC=114
4389 12:47:38.895707 [RxdqsGatingPostProcess] freq 600
4390 12:47:38.902330 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4391 12:47:38.902449 Pre-setting of DQS Precalculation
4392 12:47:38.909061 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4393 12:47:38.909184 ==
4394 12:47:38.912470 Dram Type= 6, Freq= 0, CH_1, rank 0
4395 12:47:38.915481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 12:47:38.915574 ==
4397 12:47:38.922148 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4398 12:47:38.928863 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4399 12:47:38.931679 [CA 0] Center 35 (5~66) winsize 62
4400 12:47:38.935371 [CA 1] Center 35 (5~66) winsize 62
4401 12:47:38.938332 [CA 2] Center 34 (4~65) winsize 62
4402 12:47:38.941891 [CA 3] Center 33 (3~64) winsize 62
4403 12:47:38.944941 [CA 4] Center 34 (4~64) winsize 61
4404 12:47:38.948375 [CA 5] Center 33 (3~64) winsize 62
4405 12:47:38.948478
4406 12:47:38.951943 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4407 12:47:38.952037
4408 12:47:38.955272 [CATrainingPosCal] consider 1 rank data
4409 12:47:38.958164 u2DelayCellTimex100 = 270/100 ps
4410 12:47:38.961664 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4411 12:47:38.965090 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4412 12:47:38.968563 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4413 12:47:38.971468 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4414 12:47:38.974916 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4415 12:47:38.981503 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4416 12:47:38.981652
4417 12:47:38.985006 CA PerBit enable=1, Macro0, CA PI delay=33
4418 12:47:38.985096
4419 12:47:38.987879 [CBTSetCACLKResult] CA Dly = 33
4420 12:47:38.987969 CS Dly: 5 (0~36)
4421 12:47:38.988036 ==
4422 12:47:38.991272 Dram Type= 6, Freq= 0, CH_1, rank 1
4423 12:47:38.995314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 12:47:38.998093 ==
4425 12:47:39.001029 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4426 12:47:39.007792 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4427 12:47:39.011342 [CA 0] Center 35 (5~66) winsize 62
4428 12:47:39.014384 [CA 1] Center 36 (6~66) winsize 61
4429 12:47:39.017913 [CA 2] Center 34 (4~65) winsize 62
4430 12:47:39.020939 [CA 3] Center 34 (3~65) winsize 63
4431 12:47:39.024435 [CA 4] Center 34 (4~65) winsize 62
4432 12:47:39.027511 [CA 5] Center 34 (3~65) winsize 63
4433 12:47:39.027606
4434 12:47:39.031456 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4435 12:47:39.031554
4436 12:47:39.034500 [CATrainingPosCal] consider 2 rank data
4437 12:47:39.037889 u2DelayCellTimex100 = 270/100 ps
4438 12:47:39.040709 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4439 12:47:39.044379 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4440 12:47:39.050876 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4441 12:47:39.054351 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4442 12:47:39.057220 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4443 12:47:39.060713 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4444 12:47:39.060835
4445 12:47:39.064259 CA PerBit enable=1, Macro0, CA PI delay=33
4446 12:47:39.064378
4447 12:47:39.067179 [CBTSetCACLKResult] CA Dly = 33
4448 12:47:39.067282 CS Dly: 5 (0~36)
4449 12:47:39.067350
4450 12:47:39.101344 ----->DramcWriteLeveling(PI) begin...
4451 12:47:39.101717 ==
4452 12:47:39.101811 Dram Type= 6, Freq= 0, CH_1, rank 0
4453 12:47:39.101889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 12:47:39.101968 ==
4455 12:47:39.102056 Write leveling (Byte 0): 29 => 29
4456 12:47:39.102144 Write leveling (Byte 1): 33 => 33
4457 12:47:39.102201 DramcWriteLeveling(PI) end<-----
4458 12:47:39.102256
4459 12:47:39.102312 ==
4460 12:47:39.102368 Dram Type= 6, Freq= 0, CH_1, rank 0
4461 12:47:39.102423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 12:47:39.102478 ==
4463 12:47:39.102532 [Gating] SW mode calibration
4464 12:47:39.106938 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4465 12:47:39.113219 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4466 12:47:39.116616 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4467 12:47:39.119802 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4468 12:47:39.126408 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4469 12:47:39.130028 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
4470 12:47:39.133005 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4471 12:47:39.139934 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 12:47:39.143190 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 12:47:39.146020 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 12:47:39.153077 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 12:47:39.156007 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 12:47:39.159633 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 12:47:39.166164 0 10 12 | B1->B0 | 3030 3d3d | 0 0 | (0 0) (0 0)
4478 12:47:39.169630 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 12:47:39.172521 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 12:47:39.179058 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 12:47:39.182453 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 12:47:39.186086 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 12:47:39.192652 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 12:47:39.195617 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 12:47:39.199117 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4486 12:47:39.205454 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4487 12:47:39.208940 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 12:47:39.212299 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 12:47:39.219014 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 12:47:39.222670 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 12:47:39.225388 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 12:47:39.232699 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 12:47:39.235609 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 12:47:39.238563 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 12:47:39.245247 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 12:47:39.248479 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 12:47:39.251789 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 12:47:39.258430 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 12:47:39.262060 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 12:47:39.264976 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 12:47:39.271403 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4502 12:47:39.275017 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 12:47:39.278082 Total UI for P1: 0, mck2ui 16
4504 12:47:39.281744 best dqsien dly found for B0: ( 0, 13, 12)
4505 12:47:39.284939 Total UI for P1: 0, mck2ui 16
4506 12:47:39.288437 best dqsien dly found for B1: ( 0, 13, 12)
4507 12:47:39.291734 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4508 12:47:39.294646 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4509 12:47:39.294737
4510 12:47:39.298193 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4511 12:47:39.301253 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4512 12:47:39.304809 [Gating] SW calibration Done
4513 12:47:39.304943 ==
4514 12:47:39.308092 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 12:47:39.311704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 12:47:39.314817 ==
4517 12:47:39.314931 RX Vref Scan: 0
4518 12:47:39.314999
4519 12:47:39.318359 RX Vref 0 -> 0, step: 1
4520 12:47:39.318469
4521 12:47:39.321134 RX Delay -230 -> 252, step: 16
4522 12:47:39.324389 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4523 12:47:39.328079 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4524 12:47:39.331121 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4525 12:47:39.337706 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4526 12:47:39.341247 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4527 12:47:39.344914 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4528 12:47:39.347853 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4529 12:47:39.351122 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4530 12:47:39.358148 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4531 12:47:39.361006 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4532 12:47:39.364660 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4533 12:47:39.367646 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4534 12:47:39.374495 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4535 12:47:39.377635 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4536 12:47:39.381244 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4537 12:47:39.384258 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4538 12:47:39.384349 ==
4539 12:47:39.387655 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 12:47:39.394423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 12:47:39.394578 ==
4542 12:47:39.394706 DQS Delay:
4543 12:47:39.397351 DQS0 = 0, DQS1 = 0
4544 12:47:39.397461 DQM Delay:
4545 12:47:39.397555 DQM0 = 48, DQM1 = 33
4546 12:47:39.401023 DQ Delay:
4547 12:47:39.403969 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =41
4548 12:47:39.407689 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =49
4549 12:47:39.410446 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4550 12:47:39.413964 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =49
4551 12:47:39.414057
4552 12:47:39.414123
4553 12:47:39.414183 ==
4554 12:47:39.417457 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 12:47:39.420438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 12:47:39.420553 ==
4557 12:47:39.420700
4558 12:47:39.420791
4559 12:47:39.423757 TX Vref Scan disable
4560 12:47:39.427236 == TX Byte 0 ==
4561 12:47:39.430559 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4562 12:47:39.433679 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4563 12:47:39.437188 == TX Byte 1 ==
4564 12:47:39.440202 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4565 12:47:39.443836 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4566 12:47:39.443928 ==
4567 12:47:39.447461 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 12:47:39.453536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 12:47:39.453645 ==
4570 12:47:39.453716
4571 12:47:39.453776
4572 12:47:39.453833 TX Vref Scan disable
4573 12:47:39.457890 == TX Byte 0 ==
4574 12:47:39.461352 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4575 12:47:39.467669 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4576 12:47:39.467792 == TX Byte 1 ==
4577 12:47:39.470720 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4578 12:47:39.477616 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4579 12:47:39.477732
4580 12:47:39.477802 [DATLAT]
4581 12:47:39.477863 Freq=600, CH1 RK0
4582 12:47:39.477921
4583 12:47:39.481151 DATLAT Default: 0x9
4584 12:47:39.481241 0, 0xFFFF, sum = 0
4585 12:47:39.484205 1, 0xFFFF, sum = 0
4586 12:47:39.487749 2, 0xFFFF, sum = 0
4587 12:47:39.487838 3, 0xFFFF, sum = 0
4588 12:47:39.491176 4, 0xFFFF, sum = 0
4589 12:47:39.491264 5, 0xFFFF, sum = 0
4590 12:47:39.494066 6, 0xFFFF, sum = 0
4591 12:47:39.494169 7, 0xFFFF, sum = 0
4592 12:47:39.497471 8, 0x0, sum = 1
4593 12:47:39.497576 9, 0x0, sum = 2
4594 12:47:39.497675 10, 0x0, sum = 3
4595 12:47:39.500801 11, 0x0, sum = 4
4596 12:47:39.500891 best_step = 9
4597 12:47:39.500956
4598 12:47:39.501016 ==
4599 12:47:39.504226 Dram Type= 6, Freq= 0, CH_1, rank 0
4600 12:47:39.510931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 12:47:39.511062 ==
4602 12:47:39.511136 RX Vref Scan: 1
4603 12:47:39.511198
4604 12:47:39.513720 RX Vref 0 -> 0, step: 1
4605 12:47:39.513837
4606 12:47:39.517548 RX Delay -195 -> 252, step: 8
4607 12:47:39.517641
4608 12:47:39.520377 Set Vref, RX VrefLevel [Byte0]: 51
4609 12:47:39.523995 [Byte1]: 61
4610 12:47:39.524091
4611 12:47:39.527456 Final RX Vref Byte 0 = 51 to rank0
4612 12:47:39.530458 Final RX Vref Byte 1 = 61 to rank0
4613 12:47:39.533631 Final RX Vref Byte 0 = 51 to rank1
4614 12:47:39.536961 Final RX Vref Byte 1 = 61 to rank1==
4615 12:47:39.540397 Dram Type= 6, Freq= 0, CH_1, rank 0
4616 12:47:39.543838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 12:47:39.546798 ==
4618 12:47:39.546910 DQS Delay:
4619 12:47:39.546991 DQS0 = 0, DQS1 = 0
4620 12:47:39.550312 DQM Delay:
4621 12:47:39.550404 DQM0 = 48, DQM1 = 38
4622 12:47:39.553289 DQ Delay:
4623 12:47:39.553405 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4624 12:47:39.556952 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4625 12:47:39.559890 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4626 12:47:39.563501 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4627 12:47:39.563602
4628 12:47:39.566968
4629 12:47:39.573283 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c31, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4630 12:47:39.576616 CH1 RK0: MR19=808, MR18=4C31
4631 12:47:39.583196 CH1_RK0: MR19=0x808, MR18=0x4C31, DQSOSC=395, MR23=63, INC=168, DEC=112
4632 12:47:39.583300
4633 12:47:39.586477 ----->DramcWriteLeveling(PI) begin...
4634 12:47:39.586610 ==
4635 12:47:39.589911 Dram Type= 6, Freq= 0, CH_1, rank 1
4636 12:47:39.593363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 12:47:39.593465 ==
4638 12:47:39.596270 Write leveling (Byte 0): 29 => 29
4639 12:47:39.599827 Write leveling (Byte 1): 32 => 32
4640 12:47:39.603289 DramcWriteLeveling(PI) end<-----
4641 12:47:39.603411
4642 12:47:39.603477 ==
4643 12:47:39.606422 Dram Type= 6, Freq= 0, CH_1, rank 1
4644 12:47:39.609466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 12:47:39.609559 ==
4646 12:47:39.612930 [Gating] SW mode calibration
4647 12:47:39.619515 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4648 12:47:39.626132 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4649 12:47:39.629610 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4650 12:47:39.635932 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4651 12:47:39.639027 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4652 12:47:39.642490 0 9 12 | B1->B0 | 3030 3131 | 0 0 | (0 0) (1 0)
4653 12:47:39.649178 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4654 12:47:39.652171 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 12:47:39.655732 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 12:47:39.662416 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 12:47:39.665925 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 12:47:39.668932 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 12:47:39.675546 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 12:47:39.679142 0 10 12 | B1->B0 | 3030 2828 | 0 0 | (0 0) (0 0)
4661 12:47:39.682143 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4662 12:47:39.688513 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 12:47:39.692003 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 12:47:39.695526 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 12:47:39.701957 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 12:47:39.705279 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 12:47:39.708352 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 12:47:39.715101 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4669 12:47:39.718458 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 12:47:39.722039 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 12:47:39.728329 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 12:47:39.731344 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 12:47:39.734857 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 12:47:39.741451 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 12:47:39.744991 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 12:47:39.748000 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 12:47:39.754840 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 12:47:39.757740 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 12:47:39.761337 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 12:47:39.767987 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 12:47:39.770941 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 12:47:39.774511 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 12:47:39.780941 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 12:47:39.784128 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4685 12:47:39.787499 Total UI for P1: 0, mck2ui 16
4686 12:47:39.790921 best dqsien dly found for B1: ( 0, 13, 10)
4687 12:47:39.794315 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 12:47:39.797477 Total UI for P1: 0, mck2ui 16
4689 12:47:39.800490 best dqsien dly found for B0: ( 0, 13, 12)
4690 12:47:39.803964 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4691 12:47:39.807448 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4692 12:47:39.807537
4693 12:47:39.813489 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4694 12:47:39.816955 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4695 12:47:39.820502 [Gating] SW calibration Done
4696 12:47:39.820629 ==
4697 12:47:39.823642 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 12:47:39.827133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 12:47:39.827222 ==
4700 12:47:39.827289 RX Vref Scan: 0
4701 12:47:39.827350
4702 12:47:39.830013 RX Vref 0 -> 0, step: 1
4703 12:47:39.830120
4704 12:47:39.833378 RX Delay -230 -> 252, step: 16
4705 12:47:39.836740 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4706 12:47:39.840262 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4707 12:47:39.846531 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4708 12:47:39.850074 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4709 12:47:39.853810 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4710 12:47:39.856504 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4711 12:47:39.863492 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4712 12:47:39.866494 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4713 12:47:39.870066 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4714 12:47:39.873678 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4715 12:47:39.880154 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4716 12:47:39.883141 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4717 12:47:39.886708 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4718 12:47:39.889620 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4719 12:47:39.896235 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4720 12:47:39.899498 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4721 12:47:39.899583 ==
4722 12:47:39.903110 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 12:47:39.905957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 12:47:39.906041 ==
4725 12:47:39.909492 DQS Delay:
4726 12:47:39.909576 DQS0 = 0, DQS1 = 0
4727 12:47:39.909641 DQM Delay:
4728 12:47:39.912939 DQM0 = 45, DQM1 = 37
4729 12:47:39.913057 DQ Delay:
4730 12:47:39.916060 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4731 12:47:39.919607 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4732 12:47:39.922683 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4733 12:47:39.926170 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4734 12:47:39.926274
4735 12:47:39.926365
4736 12:47:39.926452 ==
4737 12:47:39.929419 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 12:47:39.935793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 12:47:39.935907 ==
4740 12:47:39.936002
4741 12:47:39.936091
4742 12:47:39.936178 TX Vref Scan disable
4743 12:47:39.939514 == TX Byte 0 ==
4744 12:47:39.943033 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4745 12:47:39.949192 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4746 12:47:39.949277 == TX Byte 1 ==
4747 12:47:39.952696 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4748 12:47:39.959281 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4749 12:47:39.959374 ==
4750 12:47:39.962737 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 12:47:39.966073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 12:47:39.966158 ==
4753 12:47:39.966224
4754 12:47:39.966286
4755 12:47:39.969085 TX Vref Scan disable
4756 12:47:39.972530 == TX Byte 0 ==
4757 12:47:39.976290 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4758 12:47:39.979219 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4759 12:47:39.982717 == TX Byte 1 ==
4760 12:47:39.986219 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4761 12:47:39.989374 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4762 12:47:39.989465
4763 12:47:39.989535 [DATLAT]
4764 12:47:39.992422 Freq=600, CH1 RK1
4765 12:47:39.992505
4766 12:47:39.992570 DATLAT Default: 0x9
4767 12:47:39.995964 0, 0xFFFF, sum = 0
4768 12:47:39.999585 1, 0xFFFF, sum = 0
4769 12:47:39.999670 2, 0xFFFF, sum = 0
4770 12:47:40.002373 3, 0xFFFF, sum = 0
4771 12:47:40.002457 4, 0xFFFF, sum = 0
4772 12:47:40.005879 5, 0xFFFF, sum = 0
4773 12:47:40.005964 6, 0xFFFF, sum = 0
4774 12:47:40.008905 7, 0xFFFF, sum = 0
4775 12:47:40.008989 8, 0x0, sum = 1
4776 12:47:40.012435 9, 0x0, sum = 2
4777 12:47:40.012519 10, 0x0, sum = 3
4778 12:47:40.015935 11, 0x0, sum = 4
4779 12:47:40.016019 best_step = 9
4780 12:47:40.016085
4781 12:47:40.016145 ==
4782 12:47:40.018908 Dram Type= 6, Freq= 0, CH_1, rank 1
4783 12:47:40.022501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4784 12:47:40.022658 ==
4785 12:47:40.025456 RX Vref Scan: 0
4786 12:47:40.025560
4787 12:47:40.029053 RX Vref 0 -> 0, step: 1
4788 12:47:40.029138
4789 12:47:40.029244 RX Delay -195 -> 252, step: 8
4790 12:47:40.036899 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4791 12:47:40.040100 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4792 12:47:40.043615 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4793 12:47:40.046508 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4794 12:47:40.053016 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4795 12:47:40.056382 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4796 12:47:40.059707 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4797 12:47:40.063233 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4798 12:47:40.066798 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4799 12:47:40.073332 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4800 12:47:40.076632 iDelay=213, Bit 10, Center 40 (-115 ~ 196) 312
4801 12:47:40.079855 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4802 12:47:40.083441 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4803 12:47:40.089780 iDelay=213, Bit 13, Center 40 (-115 ~ 196) 312
4804 12:47:40.092850 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4805 12:47:40.096287 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4806 12:47:40.096421 ==
4807 12:47:40.099385 Dram Type= 6, Freq= 0, CH_1, rank 1
4808 12:47:40.103325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4809 12:47:40.106062 ==
4810 12:47:40.106145 DQS Delay:
4811 12:47:40.106211 DQS0 = 0, DQS1 = 0
4812 12:47:40.109599 DQM Delay:
4813 12:47:40.109681 DQM0 = 45, DQM1 = 36
4814 12:47:40.112691 DQ Delay:
4815 12:47:40.116332 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4816 12:47:40.116414 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4817 12:47:40.119661 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4818 12:47:40.126196 DQ12 =48, DQ13 =40, DQ14 =44, DQ15 =48
4819 12:47:40.126303
4820 12:47:40.126398
4821 12:47:40.132747 [DQSOSCAuto] RK1, (LSB)MR18= 0x342a, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
4822 12:47:40.136200 CH1 RK1: MR19=808, MR18=342A
4823 12:47:40.142485 CH1_RK1: MR19=0x808, MR18=0x342A, DQSOSC=400, MR23=63, INC=163, DEC=109
4824 12:47:40.146276 [RxdqsGatingPostProcess] freq 600
4825 12:47:40.149506 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4826 12:47:40.152437 Pre-setting of DQS Precalculation
4827 12:47:40.158983 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4828 12:47:40.166188 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4829 12:47:40.172497 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4830 12:47:40.172587
4831 12:47:40.172652
4832 12:47:40.175429 [Calibration Summary] 1200 Mbps
4833 12:47:40.175513 CH 0, Rank 0
4834 12:47:40.178794 SW Impedance : PASS
4835 12:47:40.182570 DUTY Scan : NO K
4836 12:47:40.182697 ZQ Calibration : PASS
4837 12:47:40.185845 Jitter Meter : NO K
4838 12:47:40.189259 CBT Training : PASS
4839 12:47:40.189342 Write leveling : PASS
4840 12:47:40.192509 RX DQS gating : PASS
4841 12:47:40.195566 RX DQ/DQS(RDDQC) : PASS
4842 12:47:40.195648 TX DQ/DQS : PASS
4843 12:47:40.198761 RX DATLAT : PASS
4844 12:47:40.198844 RX DQ/DQS(Engine): PASS
4845 12:47:40.202282 TX OE : NO K
4846 12:47:40.202366 All Pass.
4847 12:47:40.202432
4848 12:47:40.205799 CH 0, Rank 1
4849 12:47:40.205882 SW Impedance : PASS
4850 12:47:40.209010 DUTY Scan : NO K
4851 12:47:40.227201 ZQ Calibration : PASS
4852 12:47:40.227400 Jitter Meter : NO K
4853 12:47:40.227539 CBT Training : PASS
4854 12:47:40.227650 Write leveling : PASS
4855 12:47:40.227710 RX DQS gating : PASS
4856 12:47:40.227800 RX DQ/DQS(RDDQC) : PASS
4857 12:47:40.227858 TX DQ/DQS : PASS
4858 12:47:40.227915 RX DATLAT : PASS
4859 12:47:40.228907 RX DQ/DQS(Engine): PASS
4860 12:47:40.231995 TX OE : NO K
4861 12:47:40.232079 All Pass.
4862 12:47:40.232145
4863 12:47:40.232206 CH 1, Rank 0
4864 12:47:40.235458 SW Impedance : PASS
4865 12:47:40.238517 DUTY Scan : NO K
4866 12:47:40.238648 ZQ Calibration : PASS
4867 12:47:40.241928 Jitter Meter : NO K
4868 12:47:40.245508 CBT Training : PASS
4869 12:47:40.245594 Write leveling : PASS
4870 12:47:40.248519 RX DQS gating : PASS
4871 12:47:40.251867 RX DQ/DQS(RDDQC) : PASS
4872 12:47:40.251951 TX DQ/DQS : PASS
4873 12:47:40.255137 RX DATLAT : PASS
4874 12:47:40.255241 RX DQ/DQS(Engine): PASS
4875 12:47:40.258395 TX OE : NO K
4876 12:47:40.258506 All Pass.
4877 12:47:40.258625
4878 12:47:40.261849 CH 1, Rank 1
4879 12:47:40.261932 SW Impedance : PASS
4880 12:47:40.264878 DUTY Scan : NO K
4881 12:47:40.268599 ZQ Calibration : PASS
4882 12:47:40.268685 Jitter Meter : NO K
4883 12:47:40.271609 CBT Training : PASS
4884 12:47:40.275161 Write leveling : PASS
4885 12:47:40.275246 RX DQS gating : PASS
4886 12:47:40.278548 RX DQ/DQS(RDDQC) : PASS
4887 12:47:40.281544 TX DQ/DQS : PASS
4888 12:47:40.281629 RX DATLAT : PASS
4889 12:47:40.285128 RX DQ/DQS(Engine): PASS
4890 12:47:40.287976 TX OE : NO K
4891 12:47:40.288062 All Pass.
4892 12:47:40.288129
4893 12:47:40.291748 DramC Write-DBI off
4894 12:47:40.291831 PER_BANK_REFRESH: Hybrid Mode
4895 12:47:40.294659 TX_TRACKING: ON
4896 12:47:40.301476 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4897 12:47:40.307854 [FAST_K] Save calibration result to emmc
4898 12:47:40.311794 dramc_set_vcore_voltage set vcore to 662500
4899 12:47:40.311911 Read voltage for 933, 3
4900 12:47:40.314595 Vio18 = 0
4901 12:47:40.314695 Vcore = 662500
4902 12:47:40.314760 Vdram = 0
4903 12:47:40.318036 Vddq = 0
4904 12:47:40.318120 Vmddr = 0
4905 12:47:40.321507 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4906 12:47:40.328022 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4907 12:47:40.330947 MEM_TYPE=3, freq_sel=17
4908 12:47:40.334577 sv_algorithm_assistance_LP4_1600
4909 12:47:40.337616 ============ PULL DRAM RESETB DOWN ============
4910 12:47:40.341263 ========== PULL DRAM RESETB DOWN end =========
4911 12:47:40.347578 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4912 12:47:40.351026 ===================================
4913 12:47:40.351117 LPDDR4 DRAM CONFIGURATION
4914 12:47:40.354065 ===================================
4915 12:47:40.357563 EX_ROW_EN[0] = 0x0
4916 12:47:40.357647 EX_ROW_EN[1] = 0x0
4917 12:47:40.360979 LP4Y_EN = 0x0
4918 12:47:40.364140 WORK_FSP = 0x0
4919 12:47:40.364239 WL = 0x3
4920 12:47:40.367445 RL = 0x3
4921 12:47:40.367535 BL = 0x2
4922 12:47:40.371117 RPST = 0x0
4923 12:47:40.371200 RD_PRE = 0x0
4924 12:47:40.373877 WR_PRE = 0x1
4925 12:47:40.373963 WR_PST = 0x0
4926 12:47:40.377446 DBI_WR = 0x0
4927 12:47:40.377529 DBI_RD = 0x0
4928 12:47:40.380414 OTF = 0x1
4929 12:47:40.383933 ===================================
4930 12:47:40.387522 ===================================
4931 12:47:40.387614 ANA top config
4932 12:47:40.390438 ===================================
4933 12:47:40.394007 DLL_ASYNC_EN = 0
4934 12:47:40.397504 ALL_SLAVE_EN = 1
4935 12:47:40.397593 NEW_RANK_MODE = 1
4936 12:47:40.400432 DLL_IDLE_MODE = 1
4937 12:47:40.404090 LP45_APHY_COMB_EN = 1
4938 12:47:40.406922 TX_ODT_DIS = 1
4939 12:47:40.410485 NEW_8X_MODE = 1
4940 12:47:40.413873 ===================================
4941 12:47:40.416806 ===================================
4942 12:47:40.416892 data_rate = 1866
4943 12:47:40.420138 CKR = 1
4944 12:47:40.423689 DQ_P2S_RATIO = 8
4945 12:47:40.427012 ===================================
4946 12:47:40.430382 CA_P2S_RATIO = 8
4947 12:47:40.433585 DQ_CA_OPEN = 0
4948 12:47:40.436740 DQ_SEMI_OPEN = 0
4949 12:47:40.436852 CA_SEMI_OPEN = 0
4950 12:47:40.440455 CA_FULL_RATE = 0
4951 12:47:40.443773 DQ_CKDIV4_EN = 1
4952 12:47:40.446604 CA_CKDIV4_EN = 1
4953 12:47:40.450105 CA_PREDIV_EN = 0
4954 12:47:40.453624 PH8_DLY = 0
4955 12:47:40.453741 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4956 12:47:40.456538 DQ_AAMCK_DIV = 4
4957 12:47:40.460008 CA_AAMCK_DIV = 4
4958 12:47:40.463587 CA_ADMCK_DIV = 4
4959 12:47:40.466531 DQ_TRACK_CA_EN = 0
4960 12:47:40.469975 CA_PICK = 933
4961 12:47:40.473076 CA_MCKIO = 933
4962 12:47:40.473160 MCKIO_SEMI = 0
4963 12:47:40.476373 PLL_FREQ = 3732
4964 12:47:40.479932 DQ_UI_PI_RATIO = 32
4965 12:47:40.482945 CA_UI_PI_RATIO = 0
4966 12:47:40.486531 ===================================
4967 12:47:40.490048 ===================================
4968 12:47:40.493051 memory_type:LPDDR4
4969 12:47:40.493135 GP_NUM : 10
4970 12:47:40.496516 SRAM_EN : 1
4971 12:47:40.499420 MD32_EN : 0
4972 12:47:40.502988 ===================================
4973 12:47:40.503075 [ANA_INIT] >>>>>>>>>>>>>>
4974 12:47:40.506745 <<<<<< [CONFIGURE PHASE]: ANA_TX
4975 12:47:40.509484 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4976 12:47:40.512995 ===================================
4977 12:47:40.516479 data_rate = 1866,PCW = 0X8f00
4978 12:47:40.519542 ===================================
4979 12:47:40.523116 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4980 12:47:40.529653 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4981 12:47:40.532851 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4982 12:47:40.539215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4983 12:47:40.542482 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4984 12:47:40.545903 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4985 12:47:40.545989 [ANA_INIT] flow start
4986 12:47:40.549191 [ANA_INIT] PLL >>>>>>>>
4987 12:47:40.552527 [ANA_INIT] PLL <<<<<<<<
4988 12:47:40.556262 [ANA_INIT] MIDPI >>>>>>>>
4989 12:47:40.556371 [ANA_INIT] MIDPI <<<<<<<<
4990 12:47:40.559623 [ANA_INIT] DLL >>>>>>>>
4991 12:47:40.562498 [ANA_INIT] flow end
4992 12:47:40.566192 ============ LP4 DIFF to SE enter ============
4993 12:47:40.569231 ============ LP4 DIFF to SE exit ============
4994 12:47:40.572786 [ANA_INIT] <<<<<<<<<<<<<
4995 12:47:40.575708 [Flow] Enable top DCM control >>>>>
4996 12:47:40.578938 [Flow] Enable top DCM control <<<<<
4997 12:47:40.582143 Enable DLL master slave shuffle
4998 12:47:40.585570 ==============================================================
4999 12:47:40.589071 Gating Mode config
5000 12:47:40.595627 ==============================================================
5001 12:47:40.595722 Config description:
5002 12:47:40.605753 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5003 12:47:40.612281 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5004 12:47:40.615291 SELPH_MODE 0: By rank 1: By Phase
5005 12:47:40.622229 ==============================================================
5006 12:47:40.625258 GAT_TRACK_EN = 1
5007 12:47:40.628745 RX_GATING_MODE = 2
5008 12:47:40.632053 RX_GATING_TRACK_MODE = 2
5009 12:47:40.635590 SELPH_MODE = 1
5010 12:47:40.639047 PICG_EARLY_EN = 1
5011 12:47:40.641661 VALID_LAT_VALUE = 1
5012 12:47:40.644927 ==============================================================
5013 12:47:40.648365 Enter into Gating configuration >>>>
5014 12:47:40.651915 Exit from Gating configuration <<<<
5015 12:47:40.654755 Enter into DVFS_PRE_config >>>>>
5016 12:47:40.668262 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5017 12:47:40.671710 Exit from DVFS_PRE_config <<<<<
5018 12:47:40.671801 Enter into PICG configuration >>>>
5019 12:47:40.674798 Exit from PICG configuration <<<<
5020 12:47:40.678363 [RX_INPUT] configuration >>>>>
5021 12:47:40.681331 [RX_INPUT] configuration <<<<<
5022 12:47:40.688132 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5023 12:47:40.691118 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5024 12:47:40.698193 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5025 12:47:40.704766 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5026 12:47:40.711350 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5027 12:47:40.717954 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5028 12:47:40.721452 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5029 12:47:40.724853 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5030 12:47:40.727836 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5031 12:47:40.734438 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5032 12:47:40.737967 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5033 12:47:40.740915 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5034 12:47:40.744482 ===================================
5035 12:47:40.747797 LPDDR4 DRAM CONFIGURATION
5036 12:47:40.750977 ===================================
5037 12:47:40.754431 EX_ROW_EN[0] = 0x0
5038 12:47:40.754541 EX_ROW_EN[1] = 0x0
5039 12:47:40.757507 LP4Y_EN = 0x0
5040 12:47:40.757628 WORK_FSP = 0x0
5041 12:47:40.760836 WL = 0x3
5042 12:47:40.760955 RL = 0x3
5043 12:47:40.764464 BL = 0x2
5044 12:47:40.764580 RPST = 0x0
5045 12:47:40.767418 RD_PRE = 0x0
5046 12:47:40.767544 WR_PRE = 0x1
5047 12:47:40.770811 WR_PST = 0x0
5048 12:47:40.770921 DBI_WR = 0x0
5049 12:47:40.774278 DBI_RD = 0x0
5050 12:47:40.774385 OTF = 0x1
5051 12:47:40.777469 ===================================
5052 12:47:40.783973 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5053 12:47:40.787614 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5054 12:47:40.790507 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5055 12:47:40.794194 ===================================
5056 12:47:40.797090 LPDDR4 DRAM CONFIGURATION
5057 12:47:40.800378 ===================================
5058 12:47:40.803960 EX_ROW_EN[0] = 0x10
5059 12:47:40.804070 EX_ROW_EN[1] = 0x0
5060 12:47:40.806915 LP4Y_EN = 0x0
5061 12:47:40.807022 WORK_FSP = 0x0
5062 12:47:40.810598 WL = 0x3
5063 12:47:40.810721 RL = 0x3
5064 12:47:40.813678 BL = 0x2
5065 12:47:40.813783 RPST = 0x0
5066 12:47:40.817190 RD_PRE = 0x0
5067 12:47:40.817296 WR_PRE = 0x1
5068 12:47:40.820242 WR_PST = 0x0
5069 12:47:40.820346 DBI_WR = 0x0
5070 12:47:40.823772 DBI_RD = 0x0
5071 12:47:40.826716 OTF = 0x1
5072 12:47:40.826826 ===================================
5073 12:47:40.833314 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5074 12:47:40.838547 nWR fixed to 30
5075 12:47:40.841597 [ModeRegInit_LP4] CH0 RK0
5076 12:47:40.841712 [ModeRegInit_LP4] CH0 RK1
5077 12:47:40.845253 [ModeRegInit_LP4] CH1 RK0
5078 12:47:40.848511 [ModeRegInit_LP4] CH1 RK1
5079 12:47:40.848622 match AC timing 9
5080 12:47:40.855287 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5081 12:47:40.858154 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5082 12:47:40.861478 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5083 12:47:40.868398 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5084 12:47:40.871790 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5085 12:47:40.871910 ==
5086 12:47:40.874779 Dram Type= 6, Freq= 0, CH_0, rank 0
5087 12:47:40.878321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 12:47:40.878432 ==
5089 12:47:40.885172 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5090 12:47:40.891558 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5091 12:47:40.895102 [CA 0] Center 37 (7~68) winsize 62
5092 12:47:40.898069 [CA 1] Center 37 (7~68) winsize 62
5093 12:47:40.901703 [CA 2] Center 34 (4~65) winsize 62
5094 12:47:40.905232 [CA 3] Center 34 (4~65) winsize 62
5095 12:47:40.908258 [CA 4] Center 33 (3~64) winsize 62
5096 12:47:40.911676 [CA 5] Center 33 (3~63) winsize 61
5097 12:47:40.911786
5098 12:47:40.914836 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5099 12:47:40.914947
5100 12:47:40.918033 [CATrainingPosCal] consider 1 rank data
5101 12:47:40.921151 u2DelayCellTimex100 = 270/100 ps
5102 12:47:40.924694 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5103 12:47:40.928121 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5104 12:47:40.931030 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5105 12:47:40.934503 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5106 12:47:40.938043 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5107 12:47:40.944644 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5108 12:47:40.944771
5109 12:47:40.947678 CA PerBit enable=1, Macro0, CA PI delay=33
5110 12:47:40.947789
5111 12:47:40.951227 [CBTSetCACLKResult] CA Dly = 33
5112 12:47:40.951338 CS Dly: 7 (0~38)
5113 12:47:40.951436 ==
5114 12:47:40.954194 Dram Type= 6, Freq= 0, CH_0, rank 1
5115 12:47:40.957642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5116 12:47:40.961202 ==
5117 12:47:40.964253 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5118 12:47:40.971118 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5119 12:47:40.974166 [CA 0] Center 37 (7~68) winsize 62
5120 12:47:40.977486 [CA 1] Center 37 (7~68) winsize 62
5121 12:47:40.980668 [CA 2] Center 34 (4~65) winsize 62
5122 12:47:40.984169 [CA 3] Center 34 (4~65) winsize 62
5123 12:47:40.987611 [CA 4] Center 33 (3~64) winsize 62
5124 12:47:40.991014 [CA 5] Center 32 (2~63) winsize 62
5125 12:47:40.991124
5126 12:47:40.993861 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5127 12:47:40.993972
5128 12:47:40.997432 [CATrainingPosCal] consider 2 rank data
5129 12:47:41.000330 u2DelayCellTimex100 = 270/100 ps
5130 12:47:41.003839 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5131 12:47:41.006918 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5132 12:47:41.010509 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5133 12:47:41.017097 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5134 12:47:41.020499 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5135 12:47:41.024026 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5136 12:47:41.024145
5137 12:47:41.026881 CA PerBit enable=1, Macro0, CA PI delay=33
5138 12:47:41.026992
5139 12:47:41.030255 [CBTSetCACLKResult] CA Dly = 33
5140 12:47:41.030367 CS Dly: 7 (0~39)
5141 12:47:41.030465
5142 12:47:41.033407 ----->DramcWriteLeveling(PI) begin...
5143 12:47:41.036975 ==
5144 12:47:41.037087 Dram Type= 6, Freq= 0, CH_0, rank 0
5145 12:47:41.043935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 12:47:41.044060 ==
5147 12:47:41.046868 Write leveling (Byte 0): 33 => 33
5148 12:47:41.050472 Write leveling (Byte 1): 29 => 29
5149 12:47:41.053514 DramcWriteLeveling(PI) end<-----
5150 12:47:41.053631
5151 12:47:41.053729 ==
5152 12:47:41.057071 Dram Type= 6, Freq= 0, CH_0, rank 0
5153 12:47:41.060060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5154 12:47:41.060173 ==
5155 12:47:41.063628 [Gating] SW mode calibration
5156 12:47:41.070052 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5157 12:47:41.073533 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5158 12:47:41.079838 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5159 12:47:41.083227 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 12:47:41.086746 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 12:47:41.093455 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 12:47:41.096734 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 12:47:41.100001 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 12:47:41.106300 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 12:47:41.109876 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
5166 12:47:41.113384 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5167 12:47:41.119932 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 12:47:41.122761 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 12:47:41.126347 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 12:47:41.132795 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 12:47:41.136435 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 12:47:41.139392 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 12:47:41.146032 0 15 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5174 12:47:41.149538 1 0 0 | B1->B0 | 3232 4545 | 0 0 | (0 0) (1 1)
5175 12:47:41.152461 1 0 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5176 12:47:41.159459 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 12:47:41.162445 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 12:47:41.165999 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 12:47:41.172504 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 12:47:41.176055 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5181 12:47:41.179114 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5182 12:47:41.185960 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5183 12:47:41.188861 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 12:47:41.192386 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 12:47:41.198834 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 12:47:41.201998 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 12:47:41.205606 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 12:47:41.212341 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 12:47:41.215737 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 12:47:41.218857 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 12:47:41.225422 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 12:47:41.228834 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 12:47:41.231831 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 12:47:41.238908 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 12:47:41.241941 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 12:47:41.245525 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 12:47:41.252190 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 12:47:41.255153 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5199 12:47:41.258489 Total UI for P1: 0, mck2ui 16
5200 12:47:41.261674 best dqsien dly found for B0: ( 1, 2, 30)
5201 12:47:41.265352 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 12:47:41.268338 Total UI for P1: 0, mck2ui 16
5203 12:47:41.271573 best dqsien dly found for B1: ( 1, 3, 0)
5204 12:47:41.275087 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5205 12:47:41.278698 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5206 12:47:41.278817
5207 12:47:41.284935 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5208 12:47:41.288385 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5209 12:47:41.288514 [Gating] SW calibration Done
5210 12:47:41.291814 ==
5211 12:47:41.291926 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 12:47:41.298432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 12:47:41.298570 ==
5214 12:47:41.298694 RX Vref Scan: 0
5215 12:47:41.298786
5216 12:47:41.301502 RX Vref 0 -> 0, step: 1
5217 12:47:41.301606
5218 12:47:41.305028 RX Delay -80 -> 252, step: 8
5219 12:47:41.307969 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5220 12:47:41.311538 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5221 12:47:41.315209 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5222 12:47:41.321406 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5223 12:47:41.324721 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5224 12:47:41.328332 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5225 12:47:41.331693 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5226 12:47:41.334430 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5227 12:47:41.338084 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5228 12:47:41.344646 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5229 12:47:41.347651 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5230 12:47:41.351245 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5231 12:47:41.354825 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5232 12:47:41.357821 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5233 12:47:41.364328 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5234 12:47:41.367660 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5235 12:47:41.367798 ==
5236 12:47:41.371306 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 12:47:41.374122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 12:47:41.374235 ==
5239 12:47:41.377807 DQS Delay:
5240 12:47:41.377918 DQS0 = 0, DQS1 = 0
5241 12:47:41.378013 DQM Delay:
5242 12:47:41.380806 DQM0 = 97, DQM1 = 84
5243 12:47:41.380924 DQ Delay:
5244 12:47:41.384352 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5245 12:47:41.387468 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5246 12:47:41.391262 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =79
5247 12:47:41.394111 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5248 12:47:41.394226
5249 12:47:41.394323
5250 12:47:41.394416 ==
5251 12:47:41.397749 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 12:47:41.404380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 12:47:41.404495 ==
5254 12:47:41.404586
5255 12:47:41.404671
5256 12:47:41.404754 TX Vref Scan disable
5257 12:47:41.407917 == TX Byte 0 ==
5258 12:47:41.410886 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5259 12:47:41.417826 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5260 12:47:41.417946 == TX Byte 1 ==
5261 12:47:41.421159 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5262 12:47:41.427717 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5263 12:47:41.427839 ==
5264 12:47:41.430794 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 12:47:41.433940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 12:47:41.434062 ==
5267 12:47:41.434159
5268 12:47:41.434253
5269 12:47:41.437271 TX Vref Scan disable
5270 12:47:41.441000 == TX Byte 0 ==
5271 12:47:41.444267 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5272 12:47:41.447522 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5273 12:47:41.450779 == TX Byte 1 ==
5274 12:47:41.453849 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5275 12:47:41.456899 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5276 12:47:41.457014
5277 12:47:41.457113 [DATLAT]
5278 12:47:41.460483 Freq=933, CH0 RK0
5279 12:47:41.460593
5280 12:47:41.463432 DATLAT Default: 0xd
5281 12:47:41.463544 0, 0xFFFF, sum = 0
5282 12:47:41.467024 1, 0xFFFF, sum = 0
5283 12:47:41.467135 2, 0xFFFF, sum = 0
5284 12:47:41.470533 3, 0xFFFF, sum = 0
5285 12:47:41.470671 4, 0xFFFF, sum = 0
5286 12:47:41.473403 5, 0xFFFF, sum = 0
5287 12:47:41.473516 6, 0xFFFF, sum = 0
5288 12:47:41.477032 7, 0xFFFF, sum = 0
5289 12:47:41.477149 8, 0xFFFF, sum = 0
5290 12:47:41.480068 9, 0xFFFF, sum = 0
5291 12:47:41.480184 10, 0x0, sum = 1
5292 12:47:41.483578 11, 0x0, sum = 2
5293 12:47:41.483696 12, 0x0, sum = 3
5294 12:47:41.487134 13, 0x0, sum = 4
5295 12:47:41.487276 best_step = 11
5296 12:47:41.487373
5297 12:47:41.487464 ==
5298 12:47:41.490210 Dram Type= 6, Freq= 0, CH_0, rank 0
5299 12:47:41.493359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 12:47:41.496618 ==
5301 12:47:41.496737 RX Vref Scan: 1
5302 12:47:41.496835
5303 12:47:41.499993 RX Vref 0 -> 0, step: 1
5304 12:47:41.500099
5305 12:47:41.503529 RX Delay -69 -> 252, step: 4
5306 12:47:41.503638
5307 12:47:41.506501 Set Vref, RX VrefLevel [Byte0]: 59
5308 12:47:41.509955 [Byte1]: 51
5309 12:47:41.510070
5310 12:47:41.513478 Final RX Vref Byte 0 = 59 to rank0
5311 12:47:41.516440 Final RX Vref Byte 1 = 51 to rank0
5312 12:47:41.519394 Final RX Vref Byte 0 = 59 to rank1
5313 12:47:41.522952 Final RX Vref Byte 1 = 51 to rank1==
5314 12:47:41.526416 Dram Type= 6, Freq= 0, CH_0, rank 0
5315 12:47:41.529426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 12:47:41.529540 ==
5317 12:47:41.533137 DQS Delay:
5318 12:47:41.533229 DQS0 = 0, DQS1 = 0
5319 12:47:41.533295 DQM Delay:
5320 12:47:41.535798 DQM0 = 97, DQM1 = 84
5321 12:47:41.535881 DQ Delay:
5322 12:47:41.539458 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =92
5323 12:47:41.542883 DQ4 =96, DQ5 =88, DQ6 =110, DQ7 =106
5324 12:47:41.546061 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =80
5325 12:47:41.549384 DQ12 =88, DQ13 =86, DQ14 =96, DQ15 =90
5326 12:47:41.549468
5327 12:47:41.549532
5328 12:47:41.558993 [DQSOSCAuto] RK0, (LSB)MR18= 0x3016, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 406 ps
5329 12:47:41.562576 CH0 RK0: MR19=505, MR18=3016
5330 12:47:41.566125 CH0_RK0: MR19=0x505, MR18=0x3016, DQSOSC=406, MR23=63, INC=65, DEC=43
5331 12:47:41.569191
5332 12:47:41.572698 ----->DramcWriteLeveling(PI) begin...
5333 12:47:41.572783 ==
5334 12:47:41.575595 Dram Type= 6, Freq= 0, CH_0, rank 1
5335 12:47:41.579129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 12:47:41.579219 ==
5337 12:47:41.582729 Write leveling (Byte 0): 36 => 36
5338 12:47:41.585728 Write leveling (Byte 1): 34 => 34
5339 12:47:41.588717 DramcWriteLeveling(PI) end<-----
5340 12:47:41.588805
5341 12:47:41.588871 ==
5342 12:47:41.592342 Dram Type= 6, Freq= 0, CH_0, rank 1
5343 12:47:41.595385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 12:47:41.595472 ==
5345 12:47:41.598877 [Gating] SW mode calibration
5346 12:47:41.605260 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5347 12:47:41.612342 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5348 12:47:41.615777 0 14 0 | B1->B0 | 2929 3232 | 1 1 | (0 0) (1 1)
5349 12:47:41.618568 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 12:47:41.625431 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 12:47:41.628665 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 12:47:41.632048 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 12:47:41.638562 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 12:47:41.641961 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 12:47:41.644957 0 14 28 | B1->B0 | 3434 2e2e | 0 0 | (0 1) (0 0)
5356 12:47:41.651744 0 15 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
5357 12:47:41.655051 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 12:47:41.658386 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 12:47:41.664889 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 12:47:41.668495 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 12:47:41.671525 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 12:47:41.678595 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 12:47:41.681177 0 15 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (1 1)
5364 12:47:41.684870 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
5365 12:47:41.691439 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 12:47:41.694467 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 12:47:41.697975 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 12:47:41.704432 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 12:47:41.707854 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 12:47:41.711354 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 12:47:41.717691 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5372 12:47:41.720765 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 12:47:41.724290 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 12:47:41.730674 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 12:47:41.734343 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 12:47:41.737599 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 12:47:41.744072 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 12:47:41.747380 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 12:47:41.750338 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 12:47:41.757298 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 12:47:41.760649 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 12:47:41.764006 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 12:47:41.770425 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 12:47:41.774098 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 12:47:41.777051 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 12:47:41.783411 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 12:47:41.786829 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5388 12:47:41.790491 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 12:47:41.793453 Total UI for P1: 0, mck2ui 16
5390 12:47:41.797096 best dqsien dly found for B0: ( 1, 2, 28)
5391 12:47:41.799977 Total UI for P1: 0, mck2ui 16
5392 12:47:41.803679 best dqsien dly found for B1: ( 1, 2, 28)
5393 12:47:41.806614 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5394 12:47:41.809919 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5395 12:47:41.810030
5396 12:47:41.816890 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5397 12:47:41.820296 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5398 12:47:41.820409 [Gating] SW calibration Done
5399 12:47:41.823300 ==
5400 12:47:41.823406 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 12:47:41.829833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 12:47:41.829961 ==
5403 12:47:41.830077 RX Vref Scan: 0
5404 12:47:41.830140
5405 12:47:41.833304 RX Vref 0 -> 0, step: 1
5406 12:47:41.833435
5407 12:47:41.836813 RX Delay -80 -> 252, step: 8
5408 12:47:41.840060 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5409 12:47:41.843072 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5410 12:47:41.846285 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5411 12:47:41.853340 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5412 12:47:41.856453 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5413 12:47:41.860131 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5414 12:47:41.862868 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5415 12:47:41.866145 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5416 12:47:41.869454 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5417 12:47:41.876461 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5418 12:47:41.879426 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5419 12:47:41.882959 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5420 12:47:41.885948 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5421 12:47:41.889403 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5422 12:47:41.895899 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5423 12:47:41.899494 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5424 12:47:41.899598 ==
5425 12:47:41.902548 Dram Type= 6, Freq= 0, CH_0, rank 1
5426 12:47:41.906084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5427 12:47:41.906160 ==
5428 12:47:41.909107 DQS Delay:
5429 12:47:41.909179 DQS0 = 0, DQS1 = 0
5430 12:47:41.909293 DQM Delay:
5431 12:47:41.912664 DQM0 = 97, DQM1 = 87
5432 12:47:41.912783 DQ Delay:
5433 12:47:41.916188 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5434 12:47:41.918987 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5435 12:47:41.922365 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5436 12:47:41.925803 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5437 12:47:41.925886
5438 12:47:41.925952
5439 12:47:41.926012 ==
5440 12:47:41.928859 Dram Type= 6, Freq= 0, CH_0, rank 1
5441 12:47:41.935449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5442 12:47:41.935536 ==
5443 12:47:41.935601
5444 12:47:41.935661
5445 12:47:41.935719 TX Vref Scan disable
5446 12:47:41.939384 == TX Byte 0 ==
5447 12:47:41.942882 Update DQ dly =720 (2 ,6, 16) DQ OEN =(2 ,3)
5448 12:47:41.949439 Update DQM dly =720 (2 ,6, 16) DQM OEN =(2 ,3)
5449 12:47:41.949517 == TX Byte 1 ==
5450 12:47:41.952368 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5451 12:47:41.959179 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5452 12:47:41.959260 ==
5453 12:47:41.962800 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 12:47:41.965523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 12:47:41.965637 ==
5456 12:47:41.965771
5457 12:47:41.965859
5458 12:47:41.969415 TX Vref Scan disable
5459 12:47:41.969518 == TX Byte 0 ==
5460 12:47:41.975443 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5461 12:47:41.979308 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5462 12:47:41.982447 == TX Byte 1 ==
5463 12:47:41.985185 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5464 12:47:41.988857 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5465 12:47:41.988971
5466 12:47:41.989066 [DATLAT]
5467 12:47:41.991943 Freq=933, CH0 RK1
5468 12:47:41.992053
5469 12:47:41.995302 DATLAT Default: 0xb
5470 12:47:41.995411 0, 0xFFFF, sum = 0
5471 12:47:41.998840 1, 0xFFFF, sum = 0
5472 12:47:41.998952 2, 0xFFFF, sum = 0
5473 12:47:42.001789 3, 0xFFFF, sum = 0
5474 12:47:42.001914 4, 0xFFFF, sum = 0
5475 12:47:42.005348 5, 0xFFFF, sum = 0
5476 12:47:42.005457 6, 0xFFFF, sum = 0
5477 12:47:42.008373 7, 0xFFFF, sum = 0
5478 12:47:42.008482 8, 0xFFFF, sum = 0
5479 12:47:42.011922 9, 0xFFFF, sum = 0
5480 12:47:42.012031 10, 0x0, sum = 1
5481 12:47:42.014839 11, 0x0, sum = 2
5482 12:47:42.014949 12, 0x0, sum = 3
5483 12:47:42.018221 13, 0x0, sum = 4
5484 12:47:42.018330 best_step = 11
5485 12:47:42.018424
5486 12:47:42.018515 ==
5487 12:47:42.021817 Dram Type= 6, Freq= 0, CH_0, rank 1
5488 12:47:42.025329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 12:47:42.028241 ==
5490 12:47:42.028352 RX Vref Scan: 0
5491 12:47:42.028449
5492 12:47:42.032006 RX Vref 0 -> 0, step: 1
5493 12:47:42.032114
5494 12:47:42.034836 RX Delay -61 -> 252, step: 4
5495 12:47:42.038417 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5496 12:47:42.041412 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5497 12:47:42.044705 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5498 12:47:42.051133 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5499 12:47:42.054822 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5500 12:47:42.057743 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5501 12:47:42.061379 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5502 12:47:42.064293 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5503 12:47:42.071226 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5504 12:47:42.074609 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5505 12:47:42.077710 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5506 12:47:42.081088 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5507 12:47:42.084375 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5508 12:47:42.090763 iDelay=203, Bit 13, Center 94 (-1 ~ 190) 192
5509 12:47:42.094087 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5510 12:47:42.097754 iDelay=203, Bit 15, Center 94 (-1 ~ 190) 192
5511 12:47:42.097900 ==
5512 12:47:42.100777 Dram Type= 6, Freq= 0, CH_0, rank 1
5513 12:47:42.104113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 12:47:42.104280 ==
5515 12:47:42.107681 DQS Delay:
5516 12:47:42.107809 DQS0 = 0, DQS1 = 0
5517 12:47:42.110639 DQM Delay:
5518 12:47:42.110780 DQM0 = 95, DQM1 = 87
5519 12:47:42.110908 DQ Delay:
5520 12:47:42.114412 DQ0 =92, DQ1 =98, DQ2 =90, DQ3 =94
5521 12:47:42.117350 DQ4 =94, DQ5 =86, DQ6 =106, DQ7 =104
5522 12:47:42.120830 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =78
5523 12:47:42.123668 DQ12 =92, DQ13 =94, DQ14 =100, DQ15 =94
5524 12:47:42.127086
5525 12:47:42.127231
5526 12:47:42.134132 [DQSOSCAuto] RK1, (LSB)MR18= 0x28f8, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 409 ps
5527 12:47:42.137134 CH0 RK1: MR19=504, MR18=28F8
5528 12:47:42.143717 CH0_RK1: MR19=0x504, MR18=0x28F8, DQSOSC=409, MR23=63, INC=64, DEC=43
5529 12:47:42.147587 [RxdqsGatingPostProcess] freq 933
5530 12:47:42.150832 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5531 12:47:42.153782 best DQS0 dly(2T, 0.5T) = (0, 10)
5532 12:47:42.157303 best DQS1 dly(2T, 0.5T) = (0, 11)
5533 12:47:42.160378 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5534 12:47:42.164036 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5535 12:47:42.167087 best DQS0 dly(2T, 0.5T) = (0, 10)
5536 12:47:42.170660 best DQS1 dly(2T, 0.5T) = (0, 10)
5537 12:47:42.173529 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5538 12:47:42.176988 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5539 12:47:42.180571 Pre-setting of DQS Precalculation
5540 12:47:42.183728 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5541 12:47:42.183888 ==
5542 12:47:42.187198 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 12:47:42.193774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 12:47:42.193927 ==
5545 12:47:42.197103 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5546 12:47:42.203738 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5547 12:47:42.206954 [CA 0] Center 36 (6~67) winsize 62
5548 12:47:42.210486 [CA 1] Center 37 (6~68) winsize 63
5549 12:47:42.213631 [CA 2] Center 34 (4~65) winsize 62
5550 12:47:42.216594 [CA 3] Center 33 (3~64) winsize 62
5551 12:47:42.220225 [CA 4] Center 34 (4~64) winsize 61
5552 12:47:42.223232 [CA 5] Center 33 (3~64) winsize 62
5553 12:47:42.223375
5554 12:47:42.226478 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5555 12:47:42.226631
5556 12:47:42.230168 [CATrainingPosCal] consider 1 rank data
5557 12:47:42.233162 u2DelayCellTimex100 = 270/100 ps
5558 12:47:42.236632 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5559 12:47:42.240112 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5560 12:47:42.246614 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5561 12:47:42.249509 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5562 12:47:42.252945 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5563 12:47:42.256444 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5564 12:47:42.256559
5565 12:47:42.259387 CA PerBit enable=1, Macro0, CA PI delay=33
5566 12:47:42.259495
5567 12:47:42.263099 [CBTSetCACLKResult] CA Dly = 33
5568 12:47:42.263207 CS Dly: 6 (0~37)
5569 12:47:42.266032 ==
5570 12:47:42.269708 Dram Type= 6, Freq= 0, CH_1, rank 1
5571 12:47:42.272727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 12:47:42.272840 ==
5573 12:47:42.276226 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5574 12:47:42.282670 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5575 12:47:42.286306 [CA 0] Center 36 (6~67) winsize 62
5576 12:47:42.289846 [CA 1] Center 37 (7~67) winsize 61
5577 12:47:42.292821 [CA 2] Center 34 (4~65) winsize 62
5578 12:47:42.296116 [CA 3] Center 33 (3~64) winsize 62
5579 12:47:42.299573 [CA 4] Center 34 (3~65) winsize 63
5580 12:47:42.303224 [CA 5] Center 33 (3~64) winsize 62
5581 12:47:42.303339
5582 12:47:42.306314 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5583 12:47:42.306423
5584 12:47:42.309846 [CATrainingPosCal] consider 2 rank data
5585 12:47:42.312588 u2DelayCellTimex100 = 270/100 ps
5586 12:47:42.315832 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5587 12:47:42.322395 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5588 12:47:42.325883 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5589 12:47:42.329409 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5590 12:47:42.332314 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5591 12:47:42.336140 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5592 12:47:42.336233
5593 12:47:42.338937 CA PerBit enable=1, Macro0, CA PI delay=33
5594 12:47:42.339026
5595 12:47:42.342484 [CBTSetCACLKResult] CA Dly = 33
5596 12:47:42.346069 CS Dly: 7 (0~39)
5597 12:47:42.346157
5598 12:47:42.349115 ----->DramcWriteLeveling(PI) begin...
5599 12:47:42.349202 ==
5600 12:47:42.352534 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 12:47:42.355533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 12:47:42.355626 ==
5603 12:47:42.359031 Write leveling (Byte 0): 29 => 29
5604 12:47:42.362568 Write leveling (Byte 1): 31 => 31
5605 12:47:42.365647 DramcWriteLeveling(PI) end<-----
5606 12:47:42.365740
5607 12:47:42.365825 ==
5608 12:47:42.369206 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 12:47:42.372235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 12:47:42.372338 ==
5611 12:47:42.375882 [Gating] SW mode calibration
5612 12:47:42.382291 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5613 12:47:42.388810 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5614 12:47:42.392481 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5615 12:47:42.395590 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 12:47:42.402148 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 12:47:42.405392 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 12:47:42.408860 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 12:47:42.415076 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 12:47:42.418420 0 14 24 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 0)
5621 12:47:42.421898 0 14 28 | B1->B0 | 2e2e 2727 | 0 0 | (1 0) (0 0)
5622 12:47:42.428478 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5623 12:47:42.431728 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 12:47:42.435332 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 12:47:42.441694 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 12:47:42.445211 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 12:47:42.448207 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 12:47:42.454803 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5629 12:47:42.457805 0 15 28 | B1->B0 | 3737 3c3c | 0 1 | (0 0) (0 0)
5630 12:47:42.461469 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 12:47:42.467906 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 12:47:42.471702 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 12:47:42.474467 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 12:47:42.481549 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 12:47:42.484448 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 12:47:42.487876 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5637 12:47:42.494466 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5638 12:47:42.497935 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5639 12:47:42.501147 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 12:47:42.507702 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 12:47:42.511061 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 12:47:42.514620 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 12:47:42.521242 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 12:47:42.524609 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 12:47:42.527602 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 12:47:42.534471 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 12:47:42.537260 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 12:47:42.540848 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 12:47:42.547827 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 12:47:42.550646 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 12:47:42.554281 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 12:47:42.560722 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5653 12:47:42.560895 Total UI for P1: 0, mck2ui 16
5654 12:47:42.567312 best dqsien dly found for B0: ( 1, 2, 22)
5655 12:47:42.570697 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 12:47:42.573682 Total UI for P1: 0, mck2ui 16
5657 12:47:42.577260 best dqsien dly found for B1: ( 1, 2, 24)
5658 12:47:42.580693 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5659 12:47:42.583724 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5660 12:47:42.583854
5661 12:47:42.587370 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5662 12:47:42.590152 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5663 12:47:42.593482 [Gating] SW calibration Done
5664 12:47:42.593618 ==
5665 12:47:42.596935 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 12:47:42.600451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 12:47:42.603519 ==
5668 12:47:42.603670 RX Vref Scan: 0
5669 12:47:42.603799
5670 12:47:42.607084 RX Vref 0 -> 0, step: 1
5671 12:47:42.607207
5672 12:47:42.607332 RX Delay -80 -> 252, step: 8
5673 12:47:42.613596 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5674 12:47:42.616918 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5675 12:47:42.620679 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5676 12:47:42.623856 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5677 12:47:42.627190 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5678 12:47:42.630219 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5679 12:47:42.637060 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5680 12:47:42.640564 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5681 12:47:42.644034 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5682 12:47:42.646836 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5683 12:47:42.650513 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5684 12:47:42.656728 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5685 12:47:42.660092 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5686 12:47:42.663626 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5687 12:47:42.666618 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5688 12:47:42.670137 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5689 12:47:42.670418 ==
5690 12:47:42.673699 Dram Type= 6, Freq= 0, CH_1, rank 0
5691 12:47:42.680345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5692 12:47:42.680516 ==
5693 12:47:42.680621 DQS Delay:
5694 12:47:42.683265 DQS0 = 0, DQS1 = 0
5695 12:47:42.683380 DQM Delay:
5696 12:47:42.686902 DQM0 = 101, DQM1 = 91
5697 12:47:42.687032 DQ Delay:
5698 12:47:42.689911 DQ0 =107, DQ1 =95, DQ2 =95, DQ3 =99
5699 12:47:42.693362 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5700 12:47:42.696442 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5701 12:47:42.699702 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5702 12:47:42.699842
5703 12:47:42.699940
5704 12:47:42.700031 ==
5705 12:47:42.702701 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 12:47:42.706342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 12:47:42.706508 ==
5708 12:47:42.706650
5709 12:47:42.706743
5710 12:47:42.709399 TX Vref Scan disable
5711 12:47:42.712947 == TX Byte 0 ==
5712 12:47:42.716578 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5713 12:47:42.719846 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5714 12:47:42.722581 == TX Byte 1 ==
5715 12:47:42.726127 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5716 12:47:42.729134 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5717 12:47:42.729276 ==
5718 12:47:42.732665 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 12:47:42.739080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 12:47:42.739252 ==
5721 12:47:42.739357
5722 12:47:42.739449
5723 12:47:42.739538 TX Vref Scan disable
5724 12:47:42.743168 == TX Byte 0 ==
5725 12:47:42.746548 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5726 12:47:42.753427 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5727 12:47:42.753689 == TX Byte 1 ==
5728 12:47:42.756774 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5729 12:47:42.763256 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5730 12:47:42.763429
5731 12:47:42.763534 [DATLAT]
5732 12:47:42.763635 Freq=933, CH1 RK0
5733 12:47:42.763731
5734 12:47:42.766511 DATLAT Default: 0xd
5735 12:47:42.769807 0, 0xFFFF, sum = 0
5736 12:47:42.769938 1, 0xFFFF, sum = 0
5737 12:47:42.772742 2, 0xFFFF, sum = 0
5738 12:47:42.772916 3, 0xFFFF, sum = 0
5739 12:47:42.776180 4, 0xFFFF, sum = 0
5740 12:47:42.776373 5, 0xFFFF, sum = 0
5741 12:47:42.779275 6, 0xFFFF, sum = 0
5742 12:47:42.779417 7, 0xFFFF, sum = 0
5743 12:47:42.782948 8, 0xFFFF, sum = 0
5744 12:47:42.783097 9, 0xFFFF, sum = 0
5745 12:47:42.785897 10, 0x0, sum = 1
5746 12:47:42.786025 11, 0x0, sum = 2
5747 12:47:42.789430 12, 0x0, sum = 3
5748 12:47:42.789664 13, 0x0, sum = 4
5749 12:47:42.792404 best_step = 11
5750 12:47:42.792569
5751 12:47:42.792710 ==
5752 12:47:42.795927 Dram Type= 6, Freq= 0, CH_1, rank 0
5753 12:47:42.798940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5754 12:47:42.799117 ==
5755 12:47:42.799264 RX Vref Scan: 1
5756 12:47:42.802377
5757 12:47:42.802516 RX Vref 0 -> 0, step: 1
5758 12:47:42.802654
5759 12:47:42.805987 RX Delay -61 -> 252, step: 4
5760 12:47:42.806157
5761 12:47:42.808845 Set Vref, RX VrefLevel [Byte0]: 51
5762 12:47:42.812632 [Byte1]: 61
5763 12:47:42.816122
5764 12:47:42.816260 Final RX Vref Byte 0 = 51 to rank0
5765 12:47:42.819119 Final RX Vref Byte 1 = 61 to rank0
5766 12:47:42.822513 Final RX Vref Byte 0 = 51 to rank1
5767 12:47:42.825970 Final RX Vref Byte 1 = 61 to rank1==
5768 12:47:42.828970 Dram Type= 6, Freq= 0, CH_1, rank 0
5769 12:47:42.835675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 12:47:42.835851 ==
5771 12:47:42.835954 DQS Delay:
5772 12:47:42.836046 DQS0 = 0, DQS1 = 0
5773 12:47:42.839118 DQM Delay:
5774 12:47:42.839240 DQM0 = 100, DQM1 = 93
5775 12:47:42.842761 DQ Delay:
5776 12:47:42.845530 DQ0 =104, DQ1 =98, DQ2 =90, DQ3 =96
5777 12:47:42.848723 DQ4 =98, DQ5 =110, DQ6 =112, DQ7 =96
5778 12:47:42.852133 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =84
5779 12:47:42.855598 DQ12 =100, DQ13 =100, DQ14 =100, DQ15 =102
5780 12:47:42.855714
5781 12:47:42.855811
5782 12:47:42.862505 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a0a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5783 12:47:42.865279 CH1 RK0: MR19=505, MR18=1A0A
5784 12:47:42.872139 CH1_RK0: MR19=0x505, MR18=0x1A0A, DQSOSC=413, MR23=63, INC=63, DEC=42
5785 12:47:42.872264
5786 12:47:42.875575 ----->DramcWriteLeveling(PI) begin...
5787 12:47:42.875689 ==
5788 12:47:42.878829 Dram Type= 6, Freq= 0, CH_1, rank 1
5789 12:47:42.882054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5790 12:47:42.885112 ==
5791 12:47:42.885225 Write leveling (Byte 0): 27 => 27
5792 12:47:42.888596 Write leveling (Byte 1): 28 => 28
5793 12:47:42.891613 DramcWriteLeveling(PI) end<-----
5794 12:47:42.891724
5795 12:47:42.891822 ==
5796 12:47:42.895229 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 12:47:42.901722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 12:47:42.901841 ==
5799 12:47:42.901941 [Gating] SW mode calibration
5800 12:47:42.911494 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5801 12:47:42.915106 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5802 12:47:42.921811 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 12:47:42.925081 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 12:47:42.927959 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 12:47:42.934854 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 12:47:42.937980 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 12:47:42.941594 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 12:47:42.948194 0 14 24 | B1->B0 | 3131 3434 | 1 0 | (1 0) (0 0)
5809 12:47:42.951162 0 14 28 | B1->B0 | 2727 2e2e | 0 0 | (0 0) (0 0)
5810 12:47:42.954533 0 15 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5811 12:47:42.957898 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 12:47:42.964528 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 12:47:42.967568 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 12:47:42.974448 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 12:47:42.977592 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 12:47:42.981234 0 15 24 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5817 12:47:42.987462 0 15 28 | B1->B0 | 3c3c 3838 | 0 0 | (0 0) (1 1)
5818 12:47:42.990638 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 12:47:42.994366 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 12:47:43.000884 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 12:47:43.003847 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 12:47:43.007523 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 12:47:43.013950 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 12:47:43.016890 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5825 12:47:43.020441 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5826 12:47:43.027101 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 12:47:43.030484 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 12:47:43.033522 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 12:47:43.040509 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 12:47:43.043535 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 12:47:43.047038 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 12:47:43.053707 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 12:47:43.056845 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 12:47:43.060077 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 12:47:43.063581 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 12:47:43.069989 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 12:47:43.073550 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 12:47:43.076512 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 12:47:43.083236 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 12:47:43.086628 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 12:47:43.090045 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5842 12:47:43.096422 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 12:47:43.100011 Total UI for P1: 0, mck2ui 16
5844 12:47:43.103076 best dqsien dly found for B0: ( 1, 2, 28)
5845 12:47:43.106360 Total UI for P1: 0, mck2ui 16
5846 12:47:43.109730 best dqsien dly found for B1: ( 1, 2, 28)
5847 12:47:43.112828 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5848 12:47:43.116170 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5849 12:47:43.116258
5850 12:47:43.119838 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5851 12:47:43.122792 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5852 12:47:43.126314 [Gating] SW calibration Done
5853 12:47:43.126407 ==
5854 12:47:43.129342 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 12:47:43.132792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 12:47:43.132878 ==
5857 12:47:43.136195 RX Vref Scan: 0
5858 12:47:43.136269
5859 12:47:43.139704 RX Vref 0 -> 0, step: 1
5860 12:47:43.139792
5861 12:47:43.139858 RX Delay -80 -> 252, step: 8
5862 12:47:43.146238 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5863 12:47:43.149213 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5864 12:47:43.152784 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5865 12:47:43.155812 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5866 12:47:43.159362 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5867 12:47:43.163001 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5868 12:47:43.169267 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5869 12:47:43.172610 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5870 12:47:43.175598 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5871 12:47:43.179083 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5872 12:47:43.182629 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5873 12:47:43.189211 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5874 12:47:43.192090 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5875 12:47:43.195306 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5876 12:47:43.199116 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5877 12:47:43.202393 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5878 12:47:43.202509 ==
5879 12:47:43.205690 Dram Type= 6, Freq= 0, CH_1, rank 1
5880 12:47:43.211884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5881 12:47:43.212019 ==
5882 12:47:43.212120 DQS Delay:
5883 12:47:43.215142 DQS0 = 0, DQS1 = 0
5884 12:47:43.215258 DQM Delay:
5885 12:47:43.218479 DQM0 = 100, DQM1 = 92
5886 12:47:43.218618 DQ Delay:
5887 12:47:43.221918 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5888 12:47:43.225456 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5889 12:47:43.228519 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5890 12:47:43.232034 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5891 12:47:43.232151
5892 12:47:43.232248
5893 12:47:43.232340 ==
5894 12:47:43.235162 Dram Type= 6, Freq= 0, CH_1, rank 1
5895 12:47:43.238163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5896 12:47:43.238278 ==
5897 12:47:43.238372
5898 12:47:43.241582
5899 12:47:43.241692 TX Vref Scan disable
5900 12:47:43.244754 == TX Byte 0 ==
5901 12:47:43.248468 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5902 12:47:43.251473 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5903 12:47:43.255099 == TX Byte 1 ==
5904 12:47:43.258059 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5905 12:47:43.261608 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5906 12:47:43.261703 ==
5907 12:47:43.264561 Dram Type= 6, Freq= 0, CH_1, rank 1
5908 12:47:43.271679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5909 12:47:43.271791 ==
5910 12:47:43.271861
5911 12:47:43.271922
5912 12:47:43.271980 TX Vref Scan disable
5913 12:47:43.275584 == TX Byte 0 ==
5914 12:47:43.279221 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5915 12:47:43.285798 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5916 12:47:43.285917 == TX Byte 1 ==
5917 12:47:43.288836 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5918 12:47:43.295429 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5919 12:47:43.295540
5920 12:47:43.295608 [DATLAT]
5921 12:47:43.295669 Freq=933, CH1 RK1
5922 12:47:43.295729
5923 12:47:43.298957 DATLAT Default: 0xb
5924 12:47:43.299052 0, 0xFFFF, sum = 0
5925 12:47:43.302391 1, 0xFFFF, sum = 0
5926 12:47:43.305071 2, 0xFFFF, sum = 0
5927 12:47:43.305168 3, 0xFFFF, sum = 0
5928 12:47:43.308335 4, 0xFFFF, sum = 0
5929 12:47:43.308428 5, 0xFFFF, sum = 0
5930 12:47:43.311618 6, 0xFFFF, sum = 0
5931 12:47:43.311709 7, 0xFFFF, sum = 0
5932 12:47:43.315195 8, 0xFFFF, sum = 0
5933 12:47:43.315287 9, 0xFFFF, sum = 0
5934 12:47:43.318506 10, 0x0, sum = 1
5935 12:47:43.318601 11, 0x0, sum = 2
5936 12:47:43.321628 12, 0x0, sum = 3
5937 12:47:43.321715 13, 0x0, sum = 4
5938 12:47:43.321817 best_step = 11
5939 12:47:43.325379
5940 12:47:43.325466 ==
5941 12:47:43.328594 Dram Type= 6, Freq= 0, CH_1, rank 1
5942 12:47:43.332018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5943 12:47:43.332114 ==
5944 12:47:43.332184 RX Vref Scan: 0
5945 12:47:43.332247
5946 12:47:43.335070 RX Vref 0 -> 0, step: 1
5947 12:47:43.335156
5948 12:47:43.338068 RX Delay -61 -> 252, step: 4
5949 12:47:43.345029 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5950 12:47:43.348336 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5951 12:47:43.351411 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5952 12:47:43.354869 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5953 12:47:43.357880 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
5954 12:47:43.361508 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5955 12:47:43.368359 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5956 12:47:43.371455 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5957 12:47:43.374500 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
5958 12:47:43.378181 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5959 12:47:43.381048 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5960 12:47:43.387995 iDelay=207, Bit 11, Center 84 (-9 ~ 178) 188
5961 12:47:43.391442 iDelay=207, Bit 12, Center 100 (11 ~ 190) 180
5962 12:47:43.394425 iDelay=207, Bit 13, Center 100 (11 ~ 190) 180
5963 12:47:43.398051 iDelay=207, Bit 14, Center 102 (15 ~ 190) 176
5964 12:47:43.401296 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5965 12:47:43.404573 ==
5966 12:47:43.404700 Dram Type= 6, Freq= 0, CH_1, rank 1
5967 12:47:43.411028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5968 12:47:43.411163 ==
5969 12:47:43.411262 DQS Delay:
5970 12:47:43.414418 DQS0 = 0, DQS1 = 0
5971 12:47:43.414530 DQM Delay:
5972 12:47:43.417500 DQM0 = 101, DQM1 = 93
5973 12:47:43.417613 DQ Delay:
5974 12:47:43.420779 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =98
5975 12:47:43.423822 DQ4 =98, DQ5 =110, DQ6 =114, DQ7 =98
5976 12:47:43.427324 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =84
5977 12:47:43.430551 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5978 12:47:43.430677
5979 12:47:43.430746
5980 12:47:43.440137 [DQSOSCAuto] RK1, (LSB)MR18= 0x701, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
5981 12:47:43.440297 CH1 RK1: MR19=505, MR18=701
5982 12:47:43.446959 CH1_RK1: MR19=0x505, MR18=0x701, DQSOSC=419, MR23=63, INC=61, DEC=41
5983 12:47:43.450144 [RxdqsGatingPostProcess] freq 933
5984 12:47:43.456680 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5985 12:47:43.460431 best DQS0 dly(2T, 0.5T) = (0, 10)
5986 12:47:43.463931 best DQS1 dly(2T, 0.5T) = (0, 10)
5987 12:47:43.466706 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5988 12:47:43.470456 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5989 12:47:43.470578 best DQS0 dly(2T, 0.5T) = (0, 10)
5990 12:47:43.473299 best DQS1 dly(2T, 0.5T) = (0, 10)
5991 12:47:43.476676 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5992 12:47:43.480266 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5993 12:47:43.483147 Pre-setting of DQS Precalculation
5994 12:47:43.490426 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5995 12:47:43.496743 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5996 12:47:43.503330 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5997 12:47:43.503513
5998 12:47:43.503615
5999 12:47:43.506369 [Calibration Summary] 1866 Mbps
6000 12:47:43.509835 CH 0, Rank 0
6001 12:47:43.509960 SW Impedance : PASS
6002 12:47:43.513323 DUTY Scan : NO K
6003 12:47:43.513436 ZQ Calibration : PASS
6004 12:47:43.516115 Jitter Meter : NO K
6005 12:47:43.519605 CBT Training : PASS
6006 12:47:43.519719 Write leveling : PASS
6007 12:47:43.523188 RX DQS gating : PASS
6008 12:47:43.526143 RX DQ/DQS(RDDQC) : PASS
6009 12:47:43.526287 TX DQ/DQS : PASS
6010 12:47:43.529805 RX DATLAT : PASS
6011 12:47:43.532770 RX DQ/DQS(Engine): PASS
6012 12:47:43.532925 TX OE : NO K
6013 12:47:43.536058 All Pass.
6014 12:47:43.536231
6015 12:47:43.536330 CH 0, Rank 1
6016 12:47:43.539609 SW Impedance : PASS
6017 12:47:43.539758 DUTY Scan : NO K
6018 12:47:43.542376 ZQ Calibration : PASS
6019 12:47:43.546268 Jitter Meter : NO K
6020 12:47:43.546432 CBT Training : PASS
6021 12:47:43.549446 Write leveling : PASS
6022 12:47:43.552304 RX DQS gating : PASS
6023 12:47:43.552404 RX DQ/DQS(RDDQC) : PASS
6024 12:47:43.555822 TX DQ/DQS : PASS
6025 12:47:43.559163 RX DATLAT : PASS
6026 12:47:43.559265 RX DQ/DQS(Engine): PASS
6027 12:47:43.562755 TX OE : NO K
6028 12:47:43.562844 All Pass.
6029 12:47:43.562932
6030 12:47:43.565793 CH 1, Rank 0
6031 12:47:43.565905 SW Impedance : PASS
6032 12:47:43.569275 DUTY Scan : NO K
6033 12:47:43.572263 ZQ Calibration : PASS
6034 12:47:43.572371 Jitter Meter : NO K
6035 12:47:43.575849 CBT Training : PASS
6036 12:47:43.578992 Write leveling : PASS
6037 12:47:43.579111 RX DQS gating : PASS
6038 12:47:43.582332 RX DQ/DQS(RDDQC) : PASS
6039 12:47:43.582445 TX DQ/DQS : PASS
6040 12:47:43.585805 RX DATLAT : PASS
6041 12:47:43.588781 RX DQ/DQS(Engine): PASS
6042 12:47:43.588919 TX OE : NO K
6043 12:47:43.592431 All Pass.
6044 12:47:43.592555
6045 12:47:43.592655 CH 1, Rank 1
6046 12:47:43.595275 SW Impedance : PASS
6047 12:47:43.595390 DUTY Scan : NO K
6048 12:47:43.598677 ZQ Calibration : PASS
6049 12:47:43.602285 Jitter Meter : NO K
6050 12:47:43.602417 CBT Training : PASS
6051 12:47:43.605324 Write leveling : PASS
6052 12:47:43.608350 RX DQS gating : PASS
6053 12:47:43.608472 RX DQ/DQS(RDDQC) : PASS
6054 12:47:43.611905 TX DQ/DQS : PASS
6055 12:47:43.614857 RX DATLAT : PASS
6056 12:47:43.614975 RX DQ/DQS(Engine): PASS
6057 12:47:43.618297 TX OE : NO K
6058 12:47:43.618407 All Pass.
6059 12:47:43.618499
6060 12:47:43.621624 DramC Write-DBI off
6061 12:47:43.625075 PER_BANK_REFRESH: Hybrid Mode
6062 12:47:43.625170 TX_TRACKING: ON
6063 12:47:43.634583 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6064 12:47:43.638136 [FAST_K] Save calibration result to emmc
6065 12:47:43.641300 dramc_set_vcore_voltage set vcore to 650000
6066 12:47:43.644636 Read voltage for 400, 6
6067 12:47:43.644768 Vio18 = 0
6068 12:47:43.644869 Vcore = 650000
6069 12:47:43.648141 Vdram = 0
6070 12:47:43.648256 Vddq = 0
6071 12:47:43.648354 Vmddr = 0
6072 12:47:43.655019 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6073 12:47:43.658270 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6074 12:47:43.661287 MEM_TYPE=3, freq_sel=20
6075 12:47:43.665106 sv_algorithm_assistance_LP4_800
6076 12:47:43.668214 ============ PULL DRAM RESETB DOWN ============
6077 12:47:43.674576 ========== PULL DRAM RESETB DOWN end =========
6078 12:47:43.678227 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6079 12:47:43.681151 ===================================
6080 12:47:43.684550 LPDDR4 DRAM CONFIGURATION
6081 12:47:43.687982 ===================================
6082 12:47:43.688095 EX_ROW_EN[0] = 0x0
6083 12:47:43.690968 EX_ROW_EN[1] = 0x0
6084 12:47:43.691074 LP4Y_EN = 0x0
6085 12:47:43.694495 WORK_FSP = 0x0
6086 12:47:43.694628 WL = 0x2
6087 12:47:43.697931 RL = 0x2
6088 12:47:43.698037 BL = 0x2
6089 12:47:43.700949 RPST = 0x0
6090 12:47:43.701058 RD_PRE = 0x0
6091 12:47:43.704368 WR_PRE = 0x1
6092 12:47:43.704524 WR_PST = 0x0
6093 12:47:43.707540 DBI_WR = 0x0
6094 12:47:43.710964 DBI_RD = 0x0
6095 12:47:43.711092 OTF = 0x1
6096 12:47:43.714536 ===================================
6097 12:47:43.718024 ===================================
6098 12:47:43.718225 ANA top config
6099 12:47:43.721049 ===================================
6100 12:47:43.724445 DLL_ASYNC_EN = 0
6101 12:47:43.727766 ALL_SLAVE_EN = 1
6102 12:47:43.731039 NEW_RANK_MODE = 1
6103 12:47:43.734078 DLL_IDLE_MODE = 1
6104 12:47:43.734194 LP45_APHY_COMB_EN = 1
6105 12:47:43.737671 TX_ODT_DIS = 1
6106 12:47:43.740596 NEW_8X_MODE = 1
6107 12:47:43.744174 ===================================
6108 12:47:43.747522 ===================================
6109 12:47:43.750710 data_rate = 800
6110 12:47:43.754237 CKR = 1
6111 12:47:43.754348 DQ_P2S_RATIO = 4
6112 12:47:43.757075 ===================================
6113 12:47:43.760635 CA_P2S_RATIO = 4
6114 12:47:43.764261 DQ_CA_OPEN = 0
6115 12:47:43.767450 DQ_SEMI_OPEN = 1
6116 12:47:43.770627 CA_SEMI_OPEN = 1
6117 12:47:43.773799 CA_FULL_RATE = 0
6118 12:47:43.773914 DQ_CKDIV4_EN = 0
6119 12:47:43.777349 CA_CKDIV4_EN = 1
6120 12:47:43.780390 CA_PREDIV_EN = 0
6121 12:47:43.784031 PH8_DLY = 0
6122 12:47:43.786965 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6123 12:47:43.790444 DQ_AAMCK_DIV = 0
6124 12:47:43.790555 CA_AAMCK_DIV = 0
6125 12:47:43.793845 CA_ADMCK_DIV = 4
6126 12:47:43.796788 DQ_TRACK_CA_EN = 0
6127 12:47:43.800414 CA_PICK = 800
6128 12:47:43.803294 CA_MCKIO = 400
6129 12:47:43.806785 MCKIO_SEMI = 400
6130 12:47:43.809746 PLL_FREQ = 3016
6131 12:47:43.813301 DQ_UI_PI_RATIO = 32
6132 12:47:43.813433 CA_UI_PI_RATIO = 32
6133 12:47:43.816405 ===================================
6134 12:47:43.820059 ===================================
6135 12:47:43.823424 memory_type:LPDDR4
6136 12:47:43.826466 GP_NUM : 10
6137 12:47:43.826554 SRAM_EN : 1
6138 12:47:43.829816 MD32_EN : 0
6139 12:47:43.833128 ===================================
6140 12:47:43.836494 [ANA_INIT] >>>>>>>>>>>>>>
6141 12:47:43.839993 <<<<<< [CONFIGURE PHASE]: ANA_TX
6142 12:47:43.843081 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6143 12:47:43.846707 ===================================
6144 12:47:43.846819 data_rate = 800,PCW = 0X7400
6145 12:47:43.849567 ===================================
6146 12:47:43.853117 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6147 12:47:43.859605 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6148 12:47:43.873127 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6149 12:47:43.876605 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6150 12:47:43.879563 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6151 12:47:43.882979 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6152 12:47:43.886359 [ANA_INIT] flow start
6153 12:47:43.886465 [ANA_INIT] PLL >>>>>>>>
6154 12:47:43.889792 [ANA_INIT] PLL <<<<<<<<
6155 12:47:43.892619 [ANA_INIT] MIDPI >>>>>>>>
6156 12:47:43.892722 [ANA_INIT] MIDPI <<<<<<<<
6157 12:47:43.896071 [ANA_INIT] DLL >>>>>>>>
6158 12:47:43.899522 [ANA_INIT] flow end
6159 12:47:43.902510 ============ LP4 DIFF to SE enter ============
6160 12:47:43.906006 ============ LP4 DIFF to SE exit ============
6161 12:47:43.909053 [ANA_INIT] <<<<<<<<<<<<<
6162 12:47:43.912497 [Flow] Enable top DCM control >>>>>
6163 12:47:43.915886 [Flow] Enable top DCM control <<<<<
6164 12:47:43.919480 Enable DLL master slave shuffle
6165 12:47:43.925869 ==============================================================
6166 12:47:43.925975 Gating Mode config
6167 12:47:43.932307 ==============================================================
6168 12:47:43.932416 Config description:
6169 12:47:43.942461 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6170 12:47:43.948947 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6171 12:47:43.955578 SELPH_MODE 0: By rank 1: By Phase
6172 12:47:43.958583 ==============================================================
6173 12:47:43.962148 GAT_TRACK_EN = 0
6174 12:47:43.965456 RX_GATING_MODE = 2
6175 12:47:43.968625 RX_GATING_TRACK_MODE = 2
6176 12:47:43.971958 SELPH_MODE = 1
6177 12:47:43.975561 PICG_EARLY_EN = 1
6178 12:47:43.978567 VALID_LAT_VALUE = 1
6179 12:47:43.985178 ==============================================================
6180 12:47:43.988832 Enter into Gating configuration >>>>
6181 12:47:43.991849 Exit from Gating configuration <<<<
6182 12:47:43.991933 Enter into DVFS_PRE_config >>>>>
6183 12:47:44.005250 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6184 12:47:44.008515 Exit from DVFS_PRE_config <<<<<
6185 12:47:44.011631 Enter into PICG configuration >>>>
6186 12:47:44.014833 Exit from PICG configuration <<<<
6187 12:47:44.014914 [RX_INPUT] configuration >>>>>
6188 12:47:44.018450 [RX_INPUT] configuration <<<<<
6189 12:47:44.025228 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6190 12:47:44.031867 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6191 12:47:44.034878 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6192 12:47:44.041999 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6193 12:47:44.048527 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6194 12:47:44.054955 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6195 12:47:44.057951 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6196 12:47:44.061562 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6197 12:47:44.068123 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6198 12:47:44.071729 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6199 12:47:44.074986 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6200 12:47:44.081593 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6201 12:47:44.085120 ===================================
6202 12:47:44.085450 LPDDR4 DRAM CONFIGURATION
6203 12:47:44.087916 ===================================
6204 12:47:44.091528 EX_ROW_EN[0] = 0x0
6205 12:47:44.091861 EX_ROW_EN[1] = 0x0
6206 12:47:44.094549 LP4Y_EN = 0x0
6207 12:47:44.094904 WORK_FSP = 0x0
6208 12:47:44.098029 WL = 0x2
6209 12:47:44.101665 RL = 0x2
6210 12:47:44.102061 BL = 0x2
6211 12:47:44.104516 RPST = 0x0
6212 12:47:44.104863 RD_PRE = 0x0
6213 12:47:44.107822 WR_PRE = 0x1
6214 12:47:44.108152 WR_PST = 0x0
6215 12:47:44.111321 DBI_WR = 0x0
6216 12:47:44.111655 DBI_RD = 0x0
6217 12:47:44.114244 OTF = 0x1
6218 12:47:44.117821 ===================================
6219 12:47:44.120805 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6220 12:47:44.124319 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6221 12:47:44.130535 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6222 12:47:44.133903 ===================================
6223 12:47:44.134099 LPDDR4 DRAM CONFIGURATION
6224 12:47:44.137431 ===================================
6225 12:47:44.140494 EX_ROW_EN[0] = 0x10
6226 12:47:44.140638 EX_ROW_EN[1] = 0x0
6227 12:47:44.144086 LP4Y_EN = 0x0
6228 12:47:44.144230 WORK_FSP = 0x0
6229 12:47:44.146976 WL = 0x2
6230 12:47:44.150489 RL = 0x2
6231 12:47:44.150600 BL = 0x2
6232 12:47:44.153826 RPST = 0x0
6233 12:47:44.153932 RD_PRE = 0x0
6234 12:47:44.157249 WR_PRE = 0x1
6235 12:47:44.157355 WR_PST = 0x0
6236 12:47:44.160263 DBI_WR = 0x0
6237 12:47:44.160369 DBI_RD = 0x0
6238 12:47:44.163781 OTF = 0x1
6239 12:47:44.166875 ===================================
6240 12:47:44.173177 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6241 12:47:44.176915 nWR fixed to 30
6242 12:47:44.177022 [ModeRegInit_LP4] CH0 RK0
6243 12:47:44.179977 [ModeRegInit_LP4] CH0 RK1
6244 12:47:44.183345 [ModeRegInit_LP4] CH1 RK0
6245 12:47:44.186489 [ModeRegInit_LP4] CH1 RK1
6246 12:47:44.186563 match AC timing 19
6247 12:47:44.189914 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6248 12:47:44.196399 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6249 12:47:44.200171 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6250 12:47:44.206609 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6251 12:47:44.209690 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6252 12:47:44.209778 ==
6253 12:47:44.213118 Dram Type= 6, Freq= 0, CH_0, rank 0
6254 12:47:44.216476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 12:47:44.216603 ==
6256 12:47:44.223324 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6257 12:47:44.229595 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6258 12:47:44.232985 [CA 0] Center 36 (8~64) winsize 57
6259 12:47:44.236395 [CA 1] Center 36 (8~64) winsize 57
6260 12:47:44.236729 [CA 2] Center 36 (8~64) winsize 57
6261 12:47:44.239430 [CA 3] Center 36 (8~64) winsize 57
6262 12:47:44.242745 [CA 4] Center 36 (8~64) winsize 57
6263 12:47:44.245977 [CA 5] Center 36 (8~64) winsize 57
6264 12:47:44.246317
6265 12:47:44.249283 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6266 12:47:44.252771
6267 12:47:44.256225 [CATrainingPosCal] consider 1 rank data
6268 12:47:44.256558 u2DelayCellTimex100 = 270/100 ps
6269 12:47:44.262964 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 12:47:44.265847 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 12:47:44.269460 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 12:47:44.272567 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 12:47:44.276064 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 12:47:44.279070 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 12:47:44.279433
6276 12:47:44.282695 CA PerBit enable=1, Macro0, CA PI delay=36
6277 12:47:44.283052
6278 12:47:44.285629 [CBTSetCACLKResult] CA Dly = 36
6279 12:47:44.289319 CS Dly: 1 (0~32)
6280 12:47:44.289752 ==
6281 12:47:44.292321 Dram Type= 6, Freq= 0, CH_0, rank 1
6282 12:47:44.295763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 12:47:44.296184 ==
6284 12:47:44.302320 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6285 12:47:44.308943 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6286 12:47:44.309365 [CA 0] Center 36 (8~64) winsize 57
6287 12:47:44.312473 [CA 1] Center 36 (8~64) winsize 57
6288 12:47:44.315475 [CA 2] Center 36 (8~64) winsize 57
6289 12:47:44.319219 [CA 3] Center 36 (8~64) winsize 57
6290 12:47:44.321994 [CA 4] Center 36 (8~64) winsize 57
6291 12:47:44.325291 [CA 5] Center 36 (8~64) winsize 57
6292 12:47:44.325771
6293 12:47:44.328627 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6294 12:47:44.329189
6295 12:47:44.331932 [CATrainingPosCal] consider 2 rank data
6296 12:47:44.335565 u2DelayCellTimex100 = 270/100 ps
6297 12:47:44.338433 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 12:47:44.344962 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 12:47:44.348385 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 12:47:44.351621 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 12:47:44.355085 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 12:47:44.358558 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 12:47:44.358851
6304 12:47:44.361446 CA PerBit enable=1, Macro0, CA PI delay=36
6305 12:47:44.361785
6306 12:47:44.365009 [CBTSetCACLKResult] CA Dly = 36
6307 12:47:44.365343 CS Dly: 1 (0~32)
6308 12:47:44.367882
6309 12:47:44.371641 ----->DramcWriteLeveling(PI) begin...
6310 12:47:44.371754 ==
6311 12:47:44.374558 Dram Type= 6, Freq= 0, CH_0, rank 0
6312 12:47:44.378336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6313 12:47:44.378445 ==
6314 12:47:44.381294 Write leveling (Byte 0): 40 => 8
6315 12:47:44.385091 Write leveling (Byte 1): 32 => 0
6316 12:47:44.387791 DramcWriteLeveling(PI) end<-----
6317 12:47:44.387908
6318 12:47:44.387999 ==
6319 12:47:44.391495 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 12:47:44.394339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 12:47:44.394461 ==
6322 12:47:44.398019 [Gating] SW mode calibration
6323 12:47:44.404635 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6324 12:47:44.411178 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6325 12:47:44.414502 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6326 12:47:44.417575 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6327 12:47:44.424133 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6328 12:47:44.427594 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6329 12:47:44.431089 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6330 12:47:44.437919 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6331 12:47:44.440825 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 12:47:44.444406 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6333 12:47:44.450927 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6334 12:47:44.451015 Total UI for P1: 0, mck2ui 16
6335 12:47:44.454293 best dqsien dly found for B0: ( 0, 14, 24)
6336 12:47:44.457341 Total UI for P1: 0, mck2ui 16
6337 12:47:44.460886 best dqsien dly found for B1: ( 0, 14, 24)
6338 12:47:44.467152 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6339 12:47:44.470357 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6340 12:47:44.470445
6341 12:47:44.473727 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6342 12:47:44.477016 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6343 12:47:44.480419 [Gating] SW calibration Done
6344 12:47:44.480515 ==
6345 12:47:44.483788 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 12:47:44.487317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 12:47:44.487442 ==
6348 12:47:44.490396 RX Vref Scan: 0
6349 12:47:44.490497
6350 12:47:44.490588 RX Vref 0 -> 0, step: 1
6351 12:47:44.490711
6352 12:47:44.493938 RX Delay -410 -> 252, step: 16
6353 12:47:44.500553 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6354 12:47:44.503503 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6355 12:47:44.507138 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6356 12:47:44.510068 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6357 12:47:44.517102 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6358 12:47:44.520436 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6359 12:47:44.523659 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6360 12:47:44.526630 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6361 12:47:44.533474 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6362 12:47:44.536505 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6363 12:47:44.539993 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6364 12:47:44.543531 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6365 12:47:44.549993 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6366 12:47:44.553504 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6367 12:47:44.556547 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6368 12:47:44.563626 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6369 12:47:44.563766 ==
6370 12:47:44.566436 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 12:47:44.569849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 12:47:44.569962 ==
6373 12:47:44.570057 DQS Delay:
6374 12:47:44.573353 DQS0 = 43, DQS1 = 59
6375 12:47:44.573466 DQM Delay:
6376 12:47:44.576533 DQM0 = 9, DQM1 = 11
6377 12:47:44.576650 DQ Delay:
6378 12:47:44.580123 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6379 12:47:44.583097 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6380 12:47:44.586349 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6381 12:47:44.590087 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6382 12:47:44.590183
6383 12:47:44.590248
6384 12:47:44.590308 ==
6385 12:47:44.593054 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 12:47:44.596418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 12:47:44.596509 ==
6388 12:47:44.596576
6389 12:47:44.596646
6390 12:47:44.599500 TX Vref Scan disable
6391 12:47:44.599583 == TX Byte 0 ==
6392 12:47:44.606147 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6393 12:47:44.609814 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6394 12:47:44.609906 == TX Byte 1 ==
6395 12:47:44.616547 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6396 12:47:44.619358 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6397 12:47:44.619476 ==
6398 12:47:44.622938 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 12:47:44.625806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 12:47:44.625919 ==
6401 12:47:44.626013
6402 12:47:44.626110
6403 12:47:44.629143 TX Vref Scan disable
6404 12:47:44.632544 == TX Byte 0 ==
6405 12:47:44.635833 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6406 12:47:44.639310 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6407 12:47:44.642581 == TX Byte 1 ==
6408 12:47:44.645869 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6409 12:47:44.649252 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6410 12:47:44.649376
6411 12:47:44.649472 [DATLAT]
6412 12:47:44.652337 Freq=400, CH0 RK0
6413 12:47:44.652439
6414 12:47:44.655851 DATLAT Default: 0xf
6415 12:47:44.655962 0, 0xFFFF, sum = 0
6416 12:47:44.658881 1, 0xFFFF, sum = 0
6417 12:47:44.658986 2, 0xFFFF, sum = 0
6418 12:47:44.662338 3, 0xFFFF, sum = 0
6419 12:47:44.662446 4, 0xFFFF, sum = 0
6420 12:47:44.665764 5, 0xFFFF, sum = 0
6421 12:47:44.665880 6, 0xFFFF, sum = 0
6422 12:47:44.668767 7, 0xFFFF, sum = 0
6423 12:47:44.668880 8, 0xFFFF, sum = 0
6424 12:47:44.671915 9, 0xFFFF, sum = 0
6425 12:47:44.672046 10, 0xFFFF, sum = 0
6426 12:47:44.675411 11, 0xFFFF, sum = 0
6427 12:47:44.675501 12, 0xFFFF, sum = 0
6428 12:47:44.678420 13, 0x0, sum = 1
6429 12:47:44.678536 14, 0x0, sum = 2
6430 12:47:44.682126 15, 0x0, sum = 3
6431 12:47:44.682237 16, 0x0, sum = 4
6432 12:47:44.685241 best_step = 14
6433 12:47:44.685372
6434 12:47:44.685515 ==
6435 12:47:44.688695 Dram Type= 6, Freq= 0, CH_0, rank 0
6436 12:47:44.692280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 12:47:44.692401 ==
6438 12:47:44.695164 RX Vref Scan: 1
6439 12:47:44.695267
6440 12:47:44.695358 RX Vref 0 -> 0, step: 1
6441 12:47:44.695451
6442 12:47:44.698380 RX Delay -359 -> 252, step: 8
6443 12:47:44.698467
6444 12:47:44.702251 Set Vref, RX VrefLevel [Byte0]: 59
6445 12:47:44.705042 [Byte1]: 51
6446 12:47:44.709838
6447 12:47:44.709967 Final RX Vref Byte 0 = 59 to rank0
6448 12:47:44.713427 Final RX Vref Byte 1 = 51 to rank0
6449 12:47:44.716399 Final RX Vref Byte 0 = 59 to rank1
6450 12:47:44.719936 Final RX Vref Byte 1 = 51 to rank1==
6451 12:47:44.723013 Dram Type= 6, Freq= 0, CH_0, rank 0
6452 12:47:44.729505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6453 12:47:44.729641 ==
6454 12:47:44.729766 DQS Delay:
6455 12:47:44.733009 DQS0 = 48, DQS1 = 60
6456 12:47:44.733116 DQM Delay:
6457 12:47:44.735847 DQM0 = 12, DQM1 = 12
6458 12:47:44.735930 DQ Delay:
6459 12:47:44.739460 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6460 12:47:44.742987 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6461 12:47:44.745664 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6462 12:47:44.749014 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6463 12:47:44.749140
6464 12:47:44.749326
6465 12:47:44.755913 [DQSOSCAuto] RK0, (LSB)MR18= 0xc082, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6466 12:47:44.758972 CH0 RK0: MR19=C0C, MR18=C082
6467 12:47:44.765510 CH0_RK0: MR19=0xC0C, MR18=0xC082, DQSOSC=386, MR23=63, INC=396, DEC=264
6468 12:47:44.765664 ==
6469 12:47:44.769005 Dram Type= 6, Freq= 0, CH_0, rank 1
6470 12:47:44.772514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 12:47:44.772635 ==
6472 12:47:44.775481 [Gating] SW mode calibration
6473 12:47:44.782031 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6474 12:47:44.788878 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6475 12:47:44.791871 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6476 12:47:44.798451 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6477 12:47:44.801821 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6478 12:47:44.805066 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6479 12:47:44.808467 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6480 12:47:44.815361 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6481 12:47:44.818260 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 12:47:44.821873 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6483 12:47:44.828309 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6484 12:47:44.831931 Total UI for P1: 0, mck2ui 16
6485 12:47:44.834841 best dqsien dly found for B0: ( 0, 14, 24)
6486 12:47:44.837852 Total UI for P1: 0, mck2ui 16
6487 12:47:44.841396 best dqsien dly found for B1: ( 0, 14, 24)
6488 12:47:44.845019 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6489 12:47:44.848001 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6490 12:47:44.848081
6491 12:47:44.851701 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6492 12:47:44.854504 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6493 12:47:44.858047 [Gating] SW calibration Done
6494 12:47:44.858139 ==
6495 12:47:44.861384 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 12:47:44.864413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 12:47:44.864515 ==
6498 12:47:44.867840 RX Vref Scan: 0
6499 12:47:44.867929
6500 12:47:44.871562 RX Vref 0 -> 0, step: 1
6501 12:47:44.871654
6502 12:47:44.874530 RX Delay -410 -> 252, step: 16
6503 12:47:44.877632 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6504 12:47:44.881058 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6505 12:47:44.884612 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6506 12:47:44.891119 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6507 12:47:44.894490 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6508 12:47:44.897189 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6509 12:47:44.901002 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6510 12:47:44.907624 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6511 12:47:44.910882 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6512 12:47:44.914183 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6513 12:47:44.917547 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6514 12:47:44.924336 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6515 12:47:44.927338 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6516 12:47:44.930831 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6517 12:47:44.937310 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6518 12:47:44.940299 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6519 12:47:44.940410 ==
6520 12:47:44.943802 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 12:47:44.947355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 12:47:44.947458 ==
6523 12:47:44.950259 DQS Delay:
6524 12:47:44.950346 DQS0 = 35, DQS1 = 59
6525 12:47:44.950415 DQM Delay:
6526 12:47:44.953749 DQM0 = 3, DQM1 = 16
6527 12:47:44.953834 DQ Delay:
6528 12:47:44.957370 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6529 12:47:44.960352 DQ4 =0, DQ5 =0, DQ6 =8, DQ7 =8
6530 12:47:44.963841 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6531 12:47:44.966732 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6532 12:47:44.966848
6533 12:47:44.966962
6534 12:47:44.967026 ==
6535 12:47:44.970308 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 12:47:44.973884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 12:47:44.973978 ==
6538 12:47:44.974044
6539 12:47:44.974106
6540 12:47:44.976918 TX Vref Scan disable
6541 12:47:44.980414 == TX Byte 0 ==
6542 12:47:44.983457 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6543 12:47:44.986929 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6544 12:47:44.989954 == TX Byte 1 ==
6545 12:47:44.993196 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6546 12:47:44.996980 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6547 12:47:44.997079 ==
6548 12:47:45.000461 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 12:47:45.003339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 12:47:45.003435 ==
6551 12:47:45.006834
6552 12:47:45.006928
6553 12:47:45.006997 TX Vref Scan disable
6554 12:47:45.009849 == TX Byte 0 ==
6555 12:47:45.013262 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6556 12:47:45.016368 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6557 12:47:45.019852 == TX Byte 1 ==
6558 12:47:45.022939 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6559 12:47:45.026295 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6560 12:47:45.026391
6561 12:47:45.026459 [DATLAT]
6562 12:47:45.029535 Freq=400, CH0 RK1
6563 12:47:45.029676
6564 12:47:45.032951 DATLAT Default: 0xe
6565 12:47:45.033045 0, 0xFFFF, sum = 0
6566 12:47:45.036512 1, 0xFFFF, sum = 0
6567 12:47:45.036602 2, 0xFFFF, sum = 0
6568 12:47:45.039434 3, 0xFFFF, sum = 0
6569 12:47:45.039556 4, 0xFFFF, sum = 0
6570 12:47:45.043101 5, 0xFFFF, sum = 0
6571 12:47:45.043194 6, 0xFFFF, sum = 0
6572 12:47:45.045953 7, 0xFFFF, sum = 0
6573 12:47:45.046061 8, 0xFFFF, sum = 0
6574 12:47:45.049516 9, 0xFFFF, sum = 0
6575 12:47:45.049628 10, 0xFFFF, sum = 0
6576 12:47:45.053038 11, 0xFFFF, sum = 0
6577 12:47:45.053128 12, 0xFFFF, sum = 0
6578 12:47:45.055975 13, 0x0, sum = 1
6579 12:47:45.056082 14, 0x0, sum = 2
6580 12:47:45.059533 15, 0x0, sum = 3
6581 12:47:45.059624 16, 0x0, sum = 4
6582 12:47:45.062382 best_step = 14
6583 12:47:45.062473
6584 12:47:45.062602 ==
6585 12:47:45.065902 Dram Type= 6, Freq= 0, CH_0, rank 1
6586 12:47:45.069373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 12:47:45.069476 ==
6588 12:47:45.072558 RX Vref Scan: 0
6589 12:47:45.072645
6590 12:47:45.072712 RX Vref 0 -> 0, step: 1
6591 12:47:45.072774
6592 12:47:45.075890 RX Delay -359 -> 252, step: 8
6593 12:47:45.084114 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6594 12:47:45.087355 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6595 12:47:45.090323 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6596 12:47:45.094127 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6597 12:47:45.100352 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6598 12:47:45.104198 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6599 12:47:45.106960 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6600 12:47:45.113573 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6601 12:47:45.117151 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6602 12:47:45.120021 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6603 12:47:45.123352 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6604 12:47:45.129802 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6605 12:47:45.133329 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6606 12:47:45.136724 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6607 12:47:45.140214 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6608 12:47:45.146770 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6609 12:47:45.146890 ==
6610 12:47:45.149631 Dram Type= 6, Freq= 0, CH_0, rank 1
6611 12:47:45.153271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 12:47:45.153369 ==
6613 12:47:45.153437 DQS Delay:
6614 12:47:45.156268 DQS0 = 44, DQS1 = 60
6615 12:47:45.156396 DQM Delay:
6616 12:47:45.159943 DQM0 = 7, DQM1 = 14
6617 12:47:45.160028 DQ Delay:
6618 12:47:45.162874 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6619 12:47:45.166199 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6620 12:47:45.169722 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6621 12:47:45.173114 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6622 12:47:45.173213
6623 12:47:45.173279
6624 12:47:45.179526 [DQSOSCAuto] RK1, (LSB)MR18= 0xbb46, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6625 12:47:45.182991 CH0 RK1: MR19=C0C, MR18=BB46
6626 12:47:45.189607 CH0_RK1: MR19=0xC0C, MR18=0xBB46, DQSOSC=386, MR23=63, INC=396, DEC=264
6627 12:47:45.192770 [RxdqsGatingPostProcess] freq 400
6628 12:47:45.199488 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6629 12:47:45.202463 best DQS0 dly(2T, 0.5T) = (0, 10)
6630 12:47:45.205861 best DQS1 dly(2T, 0.5T) = (0, 10)
6631 12:47:45.268968 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6632 12:47:45.269575 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6633 12:47:45.270084 best DQS0 dly(2T, 0.5T) = (0, 10)
6634 12:47:45.270578 best DQS1 dly(2T, 0.5T) = (0, 10)
6635 12:47:45.271104 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6636 12:47:45.271523 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6637 12:47:45.271910 Pre-setting of DQS Precalculation
6638 12:47:45.272415 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6639 12:47:45.272835 ==
6640 12:47:45.273135 Dram Type= 6, Freq= 0, CH_1, rank 0
6641 12:47:45.273417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 12:47:45.273702 ==
6643 12:47:45.273759 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6644 12:47:45.273815 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6645 12:47:45.273871 [CA 0] Center 36 (8~64) winsize 57
6646 12:47:45.273926 [CA 1] Center 36 (8~64) winsize 57
6647 12:47:45.273980 [CA 2] Center 36 (8~64) winsize 57
6648 12:47:45.274035 [CA 3] Center 36 (8~64) winsize 57
6649 12:47:45.274090 [CA 4] Center 36 (8~64) winsize 57
6650 12:47:45.274172 [CA 5] Center 36 (8~64) winsize 57
6651 12:47:45.274226
6652 12:47:45.274471 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6653 12:47:45.275292
6654 12:47:45.278520 [CATrainingPosCal] consider 1 rank data
6655 12:47:45.278647 u2DelayCellTimex100 = 270/100 ps
6656 12:47:45.285070 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 12:47:45.288664 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 12:47:45.291666 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 12:47:45.295166 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 12:47:45.298057 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 12:47:45.301668 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 12:47:45.301776
6663 12:47:45.304717 CA PerBit enable=1, Macro0, CA PI delay=36
6664 12:47:45.304812
6665 12:47:45.308553 [CBTSetCACLKResult] CA Dly = 36
6666 12:47:45.311191 CS Dly: 1 (0~32)
6667 12:47:45.311281 ==
6668 12:47:45.314807 Dram Type= 6, Freq= 0, CH_1, rank 1
6669 12:47:45.318248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 12:47:45.318343 ==
6671 12:47:45.324508 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6672 12:47:45.331223 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6673 12:47:45.331347 [CA 0] Center 36 (8~64) winsize 57
6674 12:47:45.334554 [CA 1] Center 36 (8~64) winsize 57
6675 12:47:45.338098 [CA 2] Center 36 (8~64) winsize 57
6676 12:47:45.341264 [CA 3] Center 36 (8~64) winsize 57
6677 12:47:45.344662 [CA 4] Center 36 (8~64) winsize 57
6678 12:47:45.347534 [CA 5] Center 36 (8~64) winsize 57
6679 12:47:45.347634
6680 12:47:45.350946 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6681 12:47:45.351040
6682 12:47:45.354447 [CATrainingPosCal] consider 2 rank data
6683 12:47:45.357935 u2DelayCellTimex100 = 270/100 ps
6684 12:47:45.360797 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 12:47:45.367468 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 12:47:45.370950 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 12:47:45.373909 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 12:47:45.377473 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 12:47:45.380410 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 12:47:45.380508
6691 12:47:45.383889 CA PerBit enable=1, Macro0, CA PI delay=36
6692 12:47:45.383979
6693 12:47:45.387491 [CBTSetCACLKResult] CA Dly = 36
6694 12:47:45.387580 CS Dly: 1 (0~32)
6695 12:47:45.390448
6696 12:47:45.394040 ----->DramcWriteLeveling(PI) begin...
6697 12:47:45.394140 ==
6698 12:47:45.397575 Dram Type= 6, Freq= 0, CH_1, rank 0
6699 12:47:45.400663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6700 12:47:45.400755 ==
6701 12:47:45.404025 Write leveling (Byte 0): 40 => 8
6702 12:47:45.407583 Write leveling (Byte 1): 40 => 8
6703 12:47:45.410554 DramcWriteLeveling(PI) end<-----
6704 12:47:45.410693
6705 12:47:45.410761 ==
6706 12:47:45.413597 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 12:47:45.417084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 12:47:45.417182 ==
6709 12:47:45.420586 [Gating] SW mode calibration
6710 12:47:45.427114 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6711 12:47:45.433524 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6712 12:47:45.436784 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6713 12:47:45.440422 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6714 12:47:45.446641 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6715 12:47:45.449938 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6716 12:47:45.453314 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6717 12:47:45.459858 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6718 12:47:45.463186 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 12:47:45.466624 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6720 12:47:45.473119 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6721 12:47:45.473258 Total UI for P1: 0, mck2ui 16
6722 12:47:45.479579 best dqsien dly found for B0: ( 0, 14, 24)
6723 12:47:45.479689 Total UI for P1: 0, mck2ui 16
6724 12:47:45.485926 best dqsien dly found for B1: ( 0, 14, 24)
6725 12:47:45.489415 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6726 12:47:45.493030 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6727 12:47:45.493132
6728 12:47:45.496069 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6729 12:47:45.499073 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6730 12:47:45.502634 [Gating] SW calibration Done
6731 12:47:45.502733 ==
6732 12:47:45.505751 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 12:47:45.509097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 12:47:45.509194 ==
6735 12:47:45.512672 RX Vref Scan: 0
6736 12:47:45.512760
6737 12:47:45.515578 RX Vref 0 -> 0, step: 1
6738 12:47:45.515698
6739 12:47:45.515764 RX Delay -410 -> 252, step: 16
6740 12:47:45.522152 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6741 12:47:45.525592 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6742 12:47:45.528629 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6743 12:47:45.535750 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6744 12:47:45.538765 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6745 12:47:45.542254 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6746 12:47:45.545487 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6747 12:47:45.552278 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6748 12:47:45.555099 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6749 12:47:45.558648 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6750 12:47:45.562054 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6751 12:47:45.568615 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6752 12:47:45.572085 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6753 12:47:45.575379 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6754 12:47:45.578237 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6755 12:47:45.585509 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6756 12:47:45.585639 ==
6757 12:47:45.588427 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 12:47:45.591914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 12:47:45.592028 ==
6760 12:47:45.592099 DQS Delay:
6761 12:47:45.594811 DQS0 = 43, DQS1 = 51
6762 12:47:45.594899 DQM Delay:
6763 12:47:45.598352 DQM0 = 12, DQM1 = 14
6764 12:47:45.598439 DQ Delay:
6765 12:47:45.602035 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6766 12:47:45.605090 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6767 12:47:45.608099 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6768 12:47:45.611603 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6769 12:47:45.611711
6770 12:47:45.611824
6771 12:47:45.611891 ==
6772 12:47:45.614459 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 12:47:45.618143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 12:47:45.618301 ==
6775 12:47:45.618396
6776 12:47:45.621222
6777 12:47:45.621302 TX Vref Scan disable
6778 12:47:45.624758 == TX Byte 0 ==
6779 12:47:45.628124 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6780 12:47:45.631607 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6781 12:47:45.634533 == TX Byte 1 ==
6782 12:47:45.638158 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6783 12:47:45.641247 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6784 12:47:45.641355 ==
6785 12:47:45.644236 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 12:47:45.647803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 12:47:45.651382 ==
6788 12:47:45.651512
6789 12:47:45.651612
6790 12:47:45.651710 TX Vref Scan disable
6791 12:47:45.654603 == TX Byte 0 ==
6792 12:47:45.657565 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6793 12:47:45.660647 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6794 12:47:45.664118 == TX Byte 1 ==
6795 12:47:45.667099 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6796 12:47:45.670649 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6797 12:47:45.670755
6798 12:47:45.674219 [DATLAT]
6799 12:47:45.674312 Freq=400, CH1 RK0
6800 12:47:45.674381
6801 12:47:45.676892 DATLAT Default: 0xf
6802 12:47:45.676981 0, 0xFFFF, sum = 0
6803 12:47:45.680683 1, 0xFFFF, sum = 0
6804 12:47:45.680784 2, 0xFFFF, sum = 0
6805 12:47:45.683487 3, 0xFFFF, sum = 0
6806 12:47:45.683593 4, 0xFFFF, sum = 0
6807 12:47:45.686908 5, 0xFFFF, sum = 0
6808 12:47:45.687003 6, 0xFFFF, sum = 0
6809 12:47:45.690522 7, 0xFFFF, sum = 0
6810 12:47:45.690629 8, 0xFFFF, sum = 0
6811 12:47:45.693590 9, 0xFFFF, sum = 0
6812 12:47:45.693686 10, 0xFFFF, sum = 0
6813 12:47:45.696768 11, 0xFFFF, sum = 0
6814 12:47:45.700238 12, 0xFFFF, sum = 0
6815 12:47:45.700338 13, 0x0, sum = 1
6816 12:47:45.703748 14, 0x0, sum = 2
6817 12:47:45.703865 15, 0x0, sum = 3
6818 12:47:45.703936 16, 0x0, sum = 4
6819 12:47:45.706734 best_step = 14
6820 12:47:45.706822
6821 12:47:45.706890 ==
6822 12:47:45.710450 Dram Type= 6, Freq= 0, CH_1, rank 0
6823 12:47:45.713759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 12:47:45.713861 ==
6825 12:47:45.716959 RX Vref Scan: 1
6826 12:47:45.717055
6827 12:47:45.719961 RX Vref 0 -> 0, step: 1
6828 12:47:45.720055
6829 12:47:45.720125 RX Delay -343 -> 252, step: 8
6830 12:47:45.720188
6831 12:47:45.723521 Set Vref, RX VrefLevel [Byte0]: 51
6832 12:47:45.726493 [Byte1]: 61
6833 12:47:45.731726
6834 12:47:45.731871 Final RX Vref Byte 0 = 51 to rank0
6835 12:47:45.735298 Final RX Vref Byte 1 = 61 to rank0
6836 12:47:45.738295 Final RX Vref Byte 0 = 51 to rank1
6837 12:47:45.741904 Final RX Vref Byte 1 = 61 to rank1==
6838 12:47:45.744854 Dram Type= 6, Freq= 0, CH_1, rank 0
6839 12:47:45.752068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6840 12:47:45.752191 ==
6841 12:47:45.752258 DQS Delay:
6842 12:47:45.755043 DQS0 = 44, DQS1 = 56
6843 12:47:45.755129 DQM Delay:
6844 12:47:45.755195 DQM0 = 7, DQM1 = 11
6845 12:47:45.758560 DQ Delay:
6846 12:47:45.761523 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =4
6847 12:47:45.761643 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6848 12:47:45.765146 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6849 12:47:45.768387 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =20
6850 12:47:45.768483
6851 12:47:45.771399
6852 12:47:45.778023 [DQSOSCAuto] RK0, (LSB)MR18= 0x9b72, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6853 12:47:45.781694 CH1 RK0: MR19=C0C, MR18=9B72
6854 12:47:45.788046 CH1_RK0: MR19=0xC0C, MR18=0x9B72, DQSOSC=390, MR23=63, INC=388, DEC=258
6855 12:47:45.788197 ==
6856 12:47:45.791332 Dram Type= 6, Freq= 0, CH_1, rank 1
6857 12:47:45.794762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 12:47:45.794879 ==
6859 12:47:45.797950 [Gating] SW mode calibration
6860 12:47:45.804209 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6861 12:47:45.811362 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6862 12:47:45.814194 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6863 12:47:45.817493 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6864 12:47:45.824660 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6865 12:47:45.827681 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6866 12:47:45.831385 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6867 12:47:45.837523 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6868 12:47:45.841422 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 12:47:45.843991 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6870 12:47:45.851092 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6871 12:47:45.851193 Total UI for P1: 0, mck2ui 16
6872 12:47:45.857585 best dqsien dly found for B0: ( 0, 14, 24)
6873 12:47:45.857698 Total UI for P1: 0, mck2ui 16
6874 12:47:45.860963 best dqsien dly found for B1: ( 0, 14, 24)
6875 12:47:45.867317 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6876 12:47:45.870808 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6877 12:47:45.870904
6878 12:47:45.873827 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6879 12:47:45.877173 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6880 12:47:45.880429 [Gating] SW calibration Done
6881 12:47:45.880536 ==
6882 12:47:45.883896 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 12:47:45.887227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 12:47:45.887333 ==
6885 12:47:45.890348 RX Vref Scan: 0
6886 12:47:45.890446
6887 12:47:45.890515 RX Vref 0 -> 0, step: 1
6888 12:47:45.890577
6889 12:47:45.893893 RX Delay -410 -> 252, step: 16
6890 12:47:45.900775 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6891 12:47:45.904052 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6892 12:47:45.907027 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6893 12:47:45.910722 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6894 12:47:45.916977 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6895 12:47:45.920251 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6896 12:47:45.923686 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6897 12:47:45.927149 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6898 12:47:45.933573 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6899 12:47:45.936900 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6900 12:47:45.939798 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6901 12:47:45.943418 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6902 12:47:45.950017 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6903 12:47:45.952950 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6904 12:47:45.956542 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6905 12:47:45.963218 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6906 12:47:45.963339 ==
6907 12:47:45.966266 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 12:47:45.969722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 12:47:45.969808 ==
6910 12:47:45.969905 DQS Delay:
6911 12:47:45.973570 DQS0 = 43, DQS1 = 59
6912 12:47:45.973657 DQM Delay:
6913 12:47:45.976277 DQM0 = 12, DQM1 = 21
6914 12:47:45.976363 DQ Delay:
6915 12:47:45.979385 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6916 12:47:45.982946 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6917 12:47:45.986502 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6918 12:47:45.989271 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6919 12:47:45.989396
6920 12:47:45.989465
6921 12:47:45.989528 ==
6922 12:47:45.992594 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 12:47:45.995994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 12:47:45.996089 ==
6925 12:47:45.996156
6926 12:47:45.996217
6927 12:47:45.999267 TX Vref Scan disable
6928 12:47:46.002382 == TX Byte 0 ==
6929 12:47:46.005665 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6930 12:47:46.009151 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6931 12:47:46.009262 == TX Byte 1 ==
6932 12:47:46.015634 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6933 12:47:46.019190 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6934 12:47:46.019301 ==
6935 12:47:46.022265 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 12:47:46.026094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 12:47:46.026202 ==
6938 12:47:46.026273
6939 12:47:46.028810
6940 12:47:46.028904 TX Vref Scan disable
6941 12:47:46.032179 == TX Byte 0 ==
6942 12:47:46.035611 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6943 12:47:46.038706 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6944 12:47:46.042231 == TX Byte 1 ==
6945 12:47:46.045577 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6946 12:47:46.049095 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6947 12:47:46.049205
6948 12:47:46.049275 [DATLAT]
6949 12:47:46.052043 Freq=400, CH1 RK1
6950 12:47:46.052131
6951 12:47:46.052197 DATLAT Default: 0xe
6952 12:47:46.055615 0, 0xFFFF, sum = 0
6953 12:47:46.058574 1, 0xFFFF, sum = 0
6954 12:47:46.058694 2, 0xFFFF, sum = 0
6955 12:47:46.062226 3, 0xFFFF, sum = 0
6956 12:47:46.062318 4, 0xFFFF, sum = 0
6957 12:47:46.065213 5, 0xFFFF, sum = 0
6958 12:47:46.065305 6, 0xFFFF, sum = 0
6959 12:47:46.068889 7, 0xFFFF, sum = 0
6960 12:47:46.068993 8, 0xFFFF, sum = 0
6961 12:47:46.071843 9, 0xFFFF, sum = 0
6962 12:47:46.071940 10, 0xFFFF, sum = 0
6963 12:47:46.075355 11, 0xFFFF, sum = 0
6964 12:47:46.075445 12, 0xFFFF, sum = 0
6965 12:47:46.078413 13, 0x0, sum = 1
6966 12:47:46.078508 14, 0x0, sum = 2
6967 12:47:46.081842 15, 0x0, sum = 3
6968 12:47:46.081932 16, 0x0, sum = 4
6969 12:47:46.084883 best_step = 14
6970 12:47:46.085000
6971 12:47:46.085065 ==
6972 12:47:46.088378 Dram Type= 6, Freq= 0, CH_1, rank 1
6973 12:47:46.091420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6974 12:47:46.091549 ==
6975 12:47:46.095024 RX Vref Scan: 0
6976 12:47:46.095174
6977 12:47:46.095297 RX Vref 0 -> 0, step: 1
6978 12:47:46.095414
6979 12:47:46.098508 RX Delay -359 -> 252, step: 8
6980 12:47:46.106182 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
6981 12:47:46.109676 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6982 12:47:46.112683 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6983 12:47:46.119139 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6984 12:47:46.122400 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
6985 12:47:46.125818 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
6986 12:47:46.128886 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6987 12:47:46.135637 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6988 12:47:46.138979 iDelay=225, Bit 8, Center -60 (-311 ~ 192) 504
6989 12:47:46.142244 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6990 12:47:46.145667 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
6991 12:47:46.152477 iDelay=225, Bit 11, Center -52 (-303 ~ 200) 504
6992 12:47:46.155803 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6993 12:47:46.159057 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6994 12:47:46.162493 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6995 12:47:46.169160 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
6996 12:47:46.169284 ==
6997 12:47:46.172068 Dram Type= 6, Freq= 0, CH_1, rank 1
6998 12:47:46.175562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6999 12:47:46.175660 ==
7000 12:47:46.175730 DQS Delay:
7001 12:47:46.179108 DQS0 = 48, DQS1 = 60
7002 12:47:46.179202 DQM Delay:
7003 12:47:46.182090 DQM0 = 12, DQM1 = 14
7004 12:47:46.182179 DQ Delay:
7005 12:47:46.185645 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
7006 12:47:46.188650 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
7007 12:47:46.192166 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
7008 12:47:46.195320 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
7009 12:47:46.195424
7010 12:47:46.195494
7011 12:47:46.201881 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f5e, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
7012 12:47:46.205513 CH1 RK1: MR19=C0C, MR18=6F5E
7013 12:47:46.212009 CH1_RK1: MR19=0xC0C, MR18=0x6F5E, DQSOSC=395, MR23=63, INC=378, DEC=252
7014 12:47:46.215130 [RxdqsGatingPostProcess] freq 400
7015 12:47:46.221840 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7016 12:47:46.225011 best DQS0 dly(2T, 0.5T) = (0, 10)
7017 12:47:46.228230 best DQS1 dly(2T, 0.5T) = (0, 10)
7018 12:47:46.231967 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7019 12:47:46.234867 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7020 12:47:46.234978 best DQS0 dly(2T, 0.5T) = (0, 10)
7021 12:47:46.238373 best DQS1 dly(2T, 0.5T) = (0, 10)
7022 12:47:46.241915 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7023 12:47:46.245114 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7024 12:47:46.248376 Pre-setting of DQS Precalculation
7025 12:47:46.255082 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7026 12:47:46.261573 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7027 12:47:46.268293 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7028 12:47:46.268425
7029 12:47:46.268497
7030 12:47:46.271276 [Calibration Summary] 800 Mbps
7031 12:47:46.271365 CH 0, Rank 0
7032 12:47:46.274869 SW Impedance : PASS
7033 12:47:46.277776 DUTY Scan : NO K
7034 12:47:46.277876 ZQ Calibration : PASS
7035 12:47:46.281468 Jitter Meter : NO K
7036 12:47:46.284355 CBT Training : PASS
7037 12:47:46.284465 Write leveling : PASS
7038 12:47:46.288002 RX DQS gating : PASS
7039 12:47:46.291507 RX DQ/DQS(RDDQC) : PASS
7040 12:47:46.291602 TX DQ/DQS : PASS
7041 12:47:46.294421 RX DATLAT : PASS
7042 12:47:46.298089 RX DQ/DQS(Engine): PASS
7043 12:47:46.298221 TX OE : NO K
7044 12:47:46.301173 All Pass.
7045 12:47:46.301264
7046 12:47:46.301347 CH 0, Rank 1
7047 12:47:46.304726 SW Impedance : PASS
7048 12:47:46.304819 DUTY Scan : NO K
7049 12:47:46.307739 ZQ Calibration : PASS
7050 12:47:46.311468 Jitter Meter : NO K
7051 12:47:46.311564 CBT Training : PASS
7052 12:47:46.314425 Write leveling : NO K
7053 12:47:46.317905 RX DQS gating : PASS
7054 12:47:46.318002 RX DQ/DQS(RDDQC) : PASS
7055 12:47:46.320810 TX DQ/DQS : PASS
7056 12:47:46.320902 RX DATLAT : PASS
7057 12:47:46.324276 RX DQ/DQS(Engine): PASS
7058 12:47:46.327655 TX OE : NO K
7059 12:47:46.327753 All Pass.
7060 12:47:46.327821
7061 12:47:46.327883 CH 1, Rank 0
7062 12:47:46.331048 SW Impedance : PASS
7063 12:47:46.334369 DUTY Scan : NO K
7064 12:47:46.334464 ZQ Calibration : PASS
7065 12:47:46.337237 Jitter Meter : NO K
7066 12:47:46.340731 CBT Training : PASS
7067 12:47:46.340834 Write leveling : PASS
7068 12:47:46.343845 RX DQS gating : PASS
7069 12:47:46.347381 RX DQ/DQS(RDDQC) : PASS
7070 12:47:46.347478 TX DQ/DQS : PASS
7071 12:47:46.350642 RX DATLAT : PASS
7072 12:47:46.354149 RX DQ/DQS(Engine): PASS
7073 12:47:46.354262 TX OE : NO K
7074 12:47:46.357712 All Pass.
7075 12:47:46.357809
7076 12:47:46.357877 CH 1, Rank 1
7077 12:47:46.360500 SW Impedance : PASS
7078 12:47:46.360591 DUTY Scan : NO K
7079 12:47:46.363966 ZQ Calibration : PASS
7080 12:47:46.367361 Jitter Meter : NO K
7081 12:47:46.367451 CBT Training : PASS
7082 12:47:46.370259 Write leveling : NO K
7083 12:47:46.373736 RX DQS gating : PASS
7084 12:47:46.373836 RX DQ/DQS(RDDQC) : PASS
7085 12:47:46.377265 TX DQ/DQS : PASS
7086 12:47:46.380282 RX DATLAT : PASS
7087 12:47:46.380400 RX DQ/DQS(Engine): PASS
7088 12:47:46.383885 TX OE : NO K
7089 12:47:46.384016 All Pass.
7090 12:47:46.384087
7091 12:47:46.386890 DramC Write-DBI off
7092 12:47:46.390469 PER_BANK_REFRESH: Hybrid Mode
7093 12:47:46.390565 TX_TRACKING: ON
7094 12:47:46.400081 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7095 12:47:46.403066 [FAST_K] Save calibration result to emmc
7096 12:47:46.406553 dramc_set_vcore_voltage set vcore to 725000
7097 12:47:46.410072 Read voltage for 1600, 0
7098 12:47:46.410179 Vio18 = 0
7099 12:47:46.410249 Vcore = 725000
7100 12:47:46.413032 Vdram = 0
7101 12:47:46.413142 Vddq = 0
7102 12:47:46.413236 Vmddr = 0
7103 12:47:46.419743 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7104 12:47:46.423277 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7105 12:47:46.426221 MEM_TYPE=3, freq_sel=13
7106 12:47:46.429741 sv_algorithm_assistance_LP4_3733
7107 12:47:46.433019 ============ PULL DRAM RESETB DOWN ============
7108 12:47:46.439534 ========== PULL DRAM RESETB DOWN end =========
7109 12:47:46.443172 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7110 12:47:46.446025 ===================================
7111 12:47:46.449710 LPDDR4 DRAM CONFIGURATION
7112 12:47:46.453032 ===================================
7113 12:47:46.453128 EX_ROW_EN[0] = 0x0
7114 12:47:46.456324 EX_ROW_EN[1] = 0x0
7115 12:47:46.456419 LP4Y_EN = 0x0
7116 12:47:46.459535 WORK_FSP = 0x1
7117 12:47:46.459627 WL = 0x5
7118 12:47:46.462920 RL = 0x5
7119 12:47:46.463017 BL = 0x2
7120 12:47:46.466104 RPST = 0x0
7121 12:47:46.466195 RD_PRE = 0x0
7122 12:47:46.469253 WR_PRE = 0x1
7123 12:47:46.469367 WR_PST = 0x1
7124 12:47:46.472611 DBI_WR = 0x0
7125 12:47:46.475980 DBI_RD = 0x0
7126 12:47:46.476106 OTF = 0x1
7127 12:47:46.479083 ===================================
7128 12:47:46.482197 ===================================
7129 12:47:46.482317 ANA top config
7130 12:47:46.485663 ===================================
7131 12:47:46.489137 DLL_ASYNC_EN = 0
7132 12:47:46.492282 ALL_SLAVE_EN = 0
7133 12:47:46.495330 NEW_RANK_MODE = 1
7134 12:47:46.498921 DLL_IDLE_MODE = 1
7135 12:47:46.499040 LP45_APHY_COMB_EN = 1
7136 12:47:46.502366 TX_ODT_DIS = 0
7137 12:47:46.505293 NEW_8X_MODE = 1
7138 12:47:46.508857 ===================================
7139 12:47:46.511794 ===================================
7140 12:47:46.515357 data_rate = 3200
7141 12:47:46.518309 CKR = 1
7142 12:47:46.521864 DQ_P2S_RATIO = 8
7143 12:47:46.525439 ===================================
7144 12:47:46.525544 CA_P2S_RATIO = 8
7145 12:47:46.528466 DQ_CA_OPEN = 0
7146 12:47:46.531991 DQ_SEMI_OPEN = 0
7147 12:47:46.535020 CA_SEMI_OPEN = 0
7148 12:47:46.538461 CA_FULL_RATE = 0
7149 12:47:46.541341 DQ_CKDIV4_EN = 0
7150 12:47:46.541438 CA_CKDIV4_EN = 0
7151 12:47:46.545047 CA_PREDIV_EN = 0
7152 12:47:46.547869 PH8_DLY = 12
7153 12:47:46.551466 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7154 12:47:46.554937 DQ_AAMCK_DIV = 4
7155 12:47:46.557933 CA_AAMCK_DIV = 4
7156 12:47:46.558029 CA_ADMCK_DIV = 4
7157 12:47:46.561414 DQ_TRACK_CA_EN = 0
7158 12:47:46.564918 CA_PICK = 1600
7159 12:47:46.567760 CA_MCKIO = 1600
7160 12:47:46.571151 MCKIO_SEMI = 0
7161 12:47:46.574267 PLL_FREQ = 3068
7162 12:47:46.578035 DQ_UI_PI_RATIO = 32
7163 12:47:46.581312 CA_UI_PI_RATIO = 0
7164 12:47:46.584408 ===================================
7165 12:47:46.587768 ===================================
7166 12:47:46.587872 memory_type:LPDDR4
7167 12:47:46.591084 GP_NUM : 10
7168 12:47:46.594388 SRAM_EN : 1
7169 12:47:46.594488 MD32_EN : 0
7170 12:47:46.597439 ===================================
7171 12:47:46.600939 [ANA_INIT] >>>>>>>>>>>>>>
7172 12:47:46.604442 <<<<<< [CONFIGURE PHASE]: ANA_TX
7173 12:47:46.607418 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7174 12:47:46.611016 ===================================
7175 12:47:46.613979 data_rate = 3200,PCW = 0X7600
7176 12:47:46.617474 ===================================
7177 12:47:46.620978 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7178 12:47:46.623964 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7179 12:47:46.631023 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7180 12:47:46.634066 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7181 12:47:46.637639 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7182 12:47:46.640596 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7183 12:47:46.644252 [ANA_INIT] flow start
7184 12:47:46.647107 [ANA_INIT] PLL >>>>>>>>
7185 12:47:46.647220 [ANA_INIT] PLL <<<<<<<<
7186 12:47:46.651085 [ANA_INIT] MIDPI >>>>>>>>
7187 12:47:46.654219 [ANA_INIT] MIDPI <<<<<<<<
7188 12:47:46.654306 [ANA_INIT] DLL >>>>>>>>
7189 12:47:46.657450 [ANA_INIT] DLL <<<<<<<<
7190 12:47:46.660878 [ANA_INIT] flow end
7191 12:47:46.663933 ============ LP4 DIFF to SE enter ============
7192 12:47:46.667722 ============ LP4 DIFF to SE exit ============
7193 12:47:46.670522 [ANA_INIT] <<<<<<<<<<<<<
7194 12:47:46.673774 [Flow] Enable top DCM control >>>>>
7195 12:47:46.676984 [Flow] Enable top DCM control <<<<<
7196 12:47:46.680286 Enable DLL master slave shuffle
7197 12:47:46.686763 ==============================================================
7198 12:47:46.686866 Gating Mode config
7199 12:47:46.693762 ==============================================================
7200 12:47:46.693869 Config description:
7201 12:47:46.703359 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7202 12:47:46.709919 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7203 12:47:46.716959 SELPH_MODE 0: By rank 1: By Phase
7204 12:47:46.719853 ==============================================================
7205 12:47:46.723417 GAT_TRACK_EN = 1
7206 12:47:46.726331 RX_GATING_MODE = 2
7207 12:47:46.729918 RX_GATING_TRACK_MODE = 2
7208 12:47:46.732874 SELPH_MODE = 1
7209 12:47:46.736757 PICG_EARLY_EN = 1
7210 12:47:46.739778 VALID_LAT_VALUE = 1
7211 12:47:46.746239 ==============================================================
7212 12:47:46.749902 Enter into Gating configuration >>>>
7213 12:47:46.752918 Exit from Gating configuration <<<<
7214 12:47:46.756491 Enter into DVFS_PRE_config >>>>>
7215 12:47:46.766466 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7216 12:47:46.769822 Exit from DVFS_PRE_config <<<<<
7217 12:47:46.772852 Enter into PICG configuration >>>>
7218 12:47:46.776407 Exit from PICG configuration <<<<
7219 12:47:46.779965 [RX_INPUT] configuration >>>>>
7220 12:47:46.780328 [RX_INPUT] configuration <<<<<
7221 12:47:46.786415 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7222 12:47:46.792947 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7223 12:47:46.796233 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7224 12:47:46.803203 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7225 12:47:46.809651 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7226 12:47:46.816083 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7227 12:47:46.819457 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7228 12:47:46.822661 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7229 12:47:46.829057 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7230 12:47:46.832617 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7231 12:47:46.835775 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7232 12:47:46.842473 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7233 12:47:46.845491 ===================================
7234 12:47:46.845857 LPDDR4 DRAM CONFIGURATION
7235 12:47:46.849028 ===================================
7236 12:47:46.852624 EX_ROW_EN[0] = 0x0
7237 12:47:46.852982 EX_ROW_EN[1] = 0x0
7238 12:47:46.855665 LP4Y_EN = 0x0
7239 12:47:46.859190 WORK_FSP = 0x1
7240 12:47:46.859551 WL = 0x5
7241 12:47:46.862196 RL = 0x5
7242 12:47:46.862557 BL = 0x2
7243 12:47:46.865756 RPST = 0x0
7244 12:47:46.866115 RD_PRE = 0x0
7245 12:47:46.869247 WR_PRE = 0x1
7246 12:47:46.869606 WR_PST = 0x1
7247 12:47:46.872058 DBI_WR = 0x0
7248 12:47:46.872418 DBI_RD = 0x0
7249 12:47:46.875334 OTF = 0x1
7250 12:47:46.878890 ===================================
7251 12:47:46.882706 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7252 12:47:46.885490 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7253 12:47:46.892199 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7254 12:47:46.895601 ===================================
7255 12:47:46.896022 LPDDR4 DRAM CONFIGURATION
7256 12:47:46.898831 ===================================
7257 12:47:46.902043 EX_ROW_EN[0] = 0x10
7258 12:47:46.902407 EX_ROW_EN[1] = 0x0
7259 12:47:46.905457 LP4Y_EN = 0x0
7260 12:47:46.905815 WORK_FSP = 0x1
7261 12:47:46.908570 WL = 0x5
7262 12:47:46.912038 RL = 0x5
7263 12:47:46.912397 BL = 0x2
7264 12:47:46.915080 RPST = 0x0
7265 12:47:46.915441 RD_PRE = 0x0
7266 12:47:46.918634 WR_PRE = 0x1
7267 12:47:46.918994 WR_PST = 0x1
7268 12:47:46.921710 DBI_WR = 0x0
7269 12:47:46.922069 DBI_RD = 0x0
7270 12:47:46.925321 OTF = 0x1
7271 12:47:46.928337 ===================================
7272 12:47:46.935000 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7273 12:47:46.935503 ==
7274 12:47:46.938172 Dram Type= 6, Freq= 0, CH_0, rank 0
7275 12:47:46.941635 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7276 12:47:46.942112 ==
7277 12:47:46.945112 [Duty_Offset_Calibration]
7278 12:47:46.945607 B0:1 B1:-1 CA:0
7279 12:47:46.946018
7280 12:47:46.947913 [DutyScan_Calibration_Flow] k_type=0
7281 12:47:46.958672
7282 12:47:46.959028 ==CLK 0==
7283 12:47:46.962268 Final CLK duty delay cell = 0
7284 12:47:46.965164 [0] MAX Duty = 5125%(X100), DQS PI = 20
7285 12:47:46.968320 [0] MIN Duty = 4907%(X100), DQS PI = 8
7286 12:47:46.972003 [0] AVG Duty = 5016%(X100)
7287 12:47:46.972474
7288 12:47:46.975359 CH0 CLK Duty spec in!! Max-Min= 218%
7289 12:47:46.978359 [DutyScan_Calibration_Flow] ====Done====
7290 12:47:46.978837
7291 12:47:46.981670 [DutyScan_Calibration_Flow] k_type=1
7292 12:47:46.997890
7293 12:47:46.998346 ==DQS 0 ==
7294 12:47:47.000819 Final DQS duty delay cell = -4
7295 12:47:47.004669 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7296 12:47:47.007843 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7297 12:47:47.011295 [-4] AVG Duty = 4922%(X100)
7298 12:47:47.011777
7299 12:47:47.012180 ==DQS 1 ==
7300 12:47:47.014544 Final DQS duty delay cell = 0
7301 12:47:47.017831 [0] MAX Duty = 5156%(X100), DQS PI = 0
7302 12:47:47.021351 [0] MIN Duty = 5031%(X100), DQS PI = 18
7303 12:47:47.024337 [0] AVG Duty = 5093%(X100)
7304 12:47:47.024705
7305 12:47:47.027320 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7306 12:47:47.027789
7307 12:47:47.030902 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7308 12:47:47.034406 [DutyScan_Calibration_Flow] ====Done====
7309 12:47:47.034818
7310 12:47:47.037419 [DutyScan_Calibration_Flow] k_type=3
7311 12:47:47.055039
7312 12:47:47.055430 ==DQM 0 ==
7313 12:47:47.058550 Final DQM duty delay cell = 0
7314 12:47:47.061677 [0] MAX Duty = 5124%(X100), DQS PI = 22
7315 12:47:47.065131 [0] MIN Duty = 4907%(X100), DQS PI = 10
7316 12:47:47.068686 [0] AVG Duty = 5015%(X100)
7317 12:47:47.069120
7318 12:47:47.069514 ==DQM 1 ==
7319 12:47:47.071711 Final DQM duty delay cell = 0
7320 12:47:47.075149 [0] MAX Duty = 5031%(X100), DQS PI = 12
7321 12:47:47.078578 [0] MIN Duty = 4813%(X100), DQS PI = 20
7322 12:47:47.081653 [0] AVG Duty = 4922%(X100)
7323 12:47:47.082091
7324 12:47:47.085160 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7325 12:47:47.085580
7326 12:47:47.088075 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7327 12:47:47.091883 [DutyScan_Calibration_Flow] ====Done====
7328 12:47:47.092313
7329 12:47:47.094640 [DutyScan_Calibration_Flow] k_type=2
7330 12:47:47.111866
7331 12:47:47.112227 ==DQ 0 ==
7332 12:47:47.115182 Final DQ duty delay cell = -4
7333 12:47:47.118403 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7334 12:47:47.121818 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7335 12:47:47.125181 [-4] AVG Duty = 4953%(X100)
7336 12:47:47.125557
7337 12:47:47.125846 ==DQ 1 ==
7338 12:47:47.128614 Final DQ duty delay cell = 0
7339 12:47:47.131481 [0] MAX Duty = 5125%(X100), DQS PI = 2
7340 12:47:47.134947 [0] MIN Duty = 4969%(X100), DQS PI = 38
7341 12:47:47.137884 [0] AVG Duty = 5047%(X100)
7342 12:47:47.138272
7343 12:47:47.141551 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7344 12:47:47.141926
7345 12:47:47.144930 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7346 12:47:47.147942 [DutyScan_Calibration_Flow] ====Done====
7347 12:47:47.148348 ==
7348 12:47:47.151489 Dram Type= 6, Freq= 0, CH_1, rank 0
7349 12:47:47.154497 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7350 12:47:47.154961 ==
7351 12:47:47.158091 [Duty_Offset_Calibration]
7352 12:47:47.158478 B0:-1 B1:1 CA:2
7353 12:47:47.158912
7354 12:47:47.161123 [DutyScan_Calibration_Flow] k_type=0
7355 12:47:47.172507
7356 12:47:47.172995 ==CLK 0==
7357 12:47:47.175587 Final CLK duty delay cell = 0
7358 12:47:47.178874 [0] MAX Duty = 5187%(X100), DQS PI = 22
7359 12:47:47.182254 [0] MIN Duty = 4969%(X100), DQS PI = 0
7360 12:47:47.185267 [0] AVG Duty = 5078%(X100)
7361 12:47:47.185653
7362 12:47:47.188908 CH1 CLK Duty spec in!! Max-Min= 218%
7363 12:47:47.191889 [DutyScan_Calibration_Flow] ====Done====
7364 12:47:47.192274
7365 12:47:47.195431 [DutyScan_Calibration_Flow] k_type=1
7366 12:47:47.212202
7367 12:47:47.212586 ==DQS 0 ==
7368 12:47:47.215197 Final DQS duty delay cell = 0
7369 12:47:47.218682 [0] MAX Duty = 5156%(X100), DQS PI = 18
7370 12:47:47.222053 [0] MIN Duty = 4907%(X100), DQS PI = 10
7371 12:47:47.225216 [0] AVG Duty = 5031%(X100)
7372 12:47:47.225734
7373 12:47:47.226150 ==DQS 1 ==
7374 12:47:47.228491 Final DQS duty delay cell = 0
7375 12:47:47.231985 [0] MAX Duty = 5093%(X100), DQS PI = 24
7376 12:47:47.235190 [0] MIN Duty = 4969%(X100), DQS PI = 56
7377 12:47:47.238336 [0] AVG Duty = 5031%(X100)
7378 12:47:47.238909
7379 12:47:47.242052 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7380 12:47:47.242483
7381 12:47:47.244836 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7382 12:47:47.248492 [DutyScan_Calibration_Flow] ====Done====
7383 12:47:47.248924
7384 12:47:47.251502 [DutyScan_Calibration_Flow] k_type=3
7385 12:47:47.268181
7386 12:47:47.268608 ==DQM 0 ==
7387 12:47:47.271762 Final DQM duty delay cell = -4
7388 12:47:47.274883 [-4] MAX Duty = 5062%(X100), DQS PI = 18
7389 12:47:47.278019 [-4] MIN Duty = 4782%(X100), DQS PI = 10
7390 12:47:47.281168 [-4] AVG Duty = 4922%(X100)
7391 12:47:47.281593
7392 12:47:47.281929 ==DQM 1 ==
7393 12:47:47.284719 Final DQM duty delay cell = 0
7394 12:47:47.287954 [0] MAX Duty = 5156%(X100), DQS PI = 6
7395 12:47:47.291175 [0] MIN Duty = 4969%(X100), DQS PI = 30
7396 12:47:47.294389 [0] AVG Duty = 5062%(X100)
7397 12:47:47.294870
7398 12:47:47.297440 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7399 12:47:47.297868
7400 12:47:47.301148 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7401 12:47:47.304218 [DutyScan_Calibration_Flow] ====Done====
7402 12:47:47.304609
7403 12:47:47.307572 [DutyScan_Calibration_Flow] k_type=2
7404 12:47:47.325199
7405 12:47:47.325629 ==DQ 0 ==
7406 12:47:47.328615 Final DQ duty delay cell = 0
7407 12:47:47.331843 [0] MAX Duty = 5187%(X100), DQS PI = 32
7408 12:47:47.334990 [0] MIN Duty = 4906%(X100), DQS PI = 8
7409 12:47:47.335387 [0] AVG Duty = 5046%(X100)
7410 12:47:47.335759
7411 12:47:47.338578 ==DQ 1 ==
7412 12:47:47.341888 Final DQ duty delay cell = 0
7413 12:47:47.345205 [0] MAX Duty = 5156%(X100), DQS PI = 8
7414 12:47:47.348709 [0] MIN Duty = 4969%(X100), DQS PI = 56
7415 12:47:47.349103 [0] AVG Duty = 5062%(X100)
7416 12:47:47.349415
7417 12:47:47.351629 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7418 12:47:47.355233
7419 12:47:47.358266 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7420 12:47:47.361942 [DutyScan_Calibration_Flow] ====Done====
7421 12:47:47.364931 nWR fixed to 30
7422 12:47:47.365325 [ModeRegInit_LP4] CH0 RK0
7423 12:47:47.368677 [ModeRegInit_LP4] CH0 RK1
7424 12:47:47.371470 [ModeRegInit_LP4] CH1 RK0
7425 12:47:47.374967 [ModeRegInit_LP4] CH1 RK1
7426 12:47:47.375359 match AC timing 5
7427 12:47:47.377884 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7428 12:47:47.384602 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7429 12:47:47.388047 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7430 12:47:47.394661 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7431 12:47:47.397766 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7432 12:47:47.398208 [MiockJmeterHQA]
7433 12:47:47.398525
7434 12:47:47.401439 [DramcMiockJmeter] u1RxGatingPI = 0
7435 12:47:47.404810 0 : 4363, 4137
7436 12:47:47.405343 4 : 4258, 4029
7437 12:47:47.407931 8 : 4255, 4029
7438 12:47:47.408328 12 : 4255, 4029
7439 12:47:47.408646 16 : 4363, 4138
7440 12:47:47.411596 20 : 4365, 4140
7441 12:47:47.412125 24 : 4365, 4140
7442 12:47:47.414706 28 : 4363, 4137
7443 12:47:47.415108 32 : 4363, 4138
7444 12:47:47.417609 36 : 4252, 4027
7445 12:47:47.418041 40 : 4253, 4026
7446 12:47:47.420774 44 : 4250, 4027
7447 12:47:47.421147 48 : 4250, 4027
7448 12:47:47.421522 52 : 4250, 4027
7449 12:47:47.424528 56 : 4250, 4027
7450 12:47:47.424882 60 : 4250, 4026
7451 12:47:47.427545 64 : 4255, 4030
7452 12:47:47.427940 68 : 4250, 4027
7453 12:47:47.431033 72 : 4361, 4137
7454 12:47:47.431464 76 : 4361, 4138
7455 12:47:47.434180 80 : 4250, 4026
7456 12:47:47.434637 84 : 4363, 4138
7457 12:47:47.434999 88 : 4250, 4026
7458 12:47:47.437568 92 : 4250, 719
7459 12:47:47.437899 96 : 4360, 0
7460 12:47:47.440829 100 : 4253, 0
7461 12:47:47.441196 104 : 4250, 0
7462 12:47:47.441488 108 : 4360, 0
7463 12:47:47.443963 112 : 4363, 0
7464 12:47:47.444493 116 : 4250, 0
7465 12:47:47.447474 120 : 4253, 0
7466 12:47:47.447910 124 : 4254, 0
7467 12:47:47.448227 128 : 4252, 0
7468 12:47:47.450850 132 : 4250, 0
7469 12:47:47.451245 136 : 4253, 0
7470 12:47:47.453973 140 : 4255, 0
7471 12:47:47.454367 144 : 4250, 0
7472 12:47:47.454750 148 : 4250, 0
7473 12:47:47.457298 152 : 4250, 0
7474 12:47:47.457775 156 : 4255, 0
7475 12:47:47.460839 160 : 4360, 0
7476 12:47:47.461266 164 : 4363, 0
7477 12:47:47.461588 168 : 4250, 0
7478 12:47:47.463691 172 : 4250, 0
7479 12:47:47.464068 176 : 4252, 0
7480 12:47:47.464399 180 : 4250, 0
7481 12:47:47.467304 184 : 4250, 0
7482 12:47:47.467710 188 : 4254, 0
7483 12:47:47.470220 192 : 4255, 0
7484 12:47:47.470654 196 : 4253, 0
7485 12:47:47.470985 200 : 4250, 0
7486 12:47:47.473915 204 : 4250, 0
7487 12:47:47.474420 208 : 4250, 0
7488 12:47:47.476956 212 : 4360, 0
7489 12:47:47.477350 216 : 4363, 0
7490 12:47:47.477666 220 : 4252, 0
7491 12:47:47.480424 224 : 4250, 233
7492 12:47:47.480820 228 : 4361, 3300
7493 12:47:47.484064 232 : 4360, 4138
7494 12:47:47.484471 236 : 4360, 4137
7495 12:47:47.487027 240 : 4250, 4026
7496 12:47:47.487422 244 : 4253, 4029
7497 12:47:47.490040 248 : 4252, 4030
7498 12:47:47.490438 252 : 4250, 4027
7499 12:47:47.493666 256 : 4250, 4026
7500 12:47:47.494064 260 : 4361, 4137
7501 12:47:47.496716 264 : 4250, 4027
7502 12:47:47.497116 268 : 4249, 4027
7503 12:47:47.497433 272 : 4250, 4026
7504 12:47:47.500022 276 : 4250, 4026
7505 12:47:47.500418 280 : 4361, 4138
7506 12:47:47.503168 284 : 4250, 4027
7507 12:47:47.503587 288 : 4360, 4137
7508 12:47:47.506558 292 : 4250, 4026
7509 12:47:47.507022 296 : 4250, 4027
7510 12:47:47.509899 300 : 4250, 4027
7511 12:47:47.510297 304 : 4250, 4027
7512 12:47:47.513486 308 : 4255, 4029
7513 12:47:47.513882 312 : 4361, 4137
7514 12:47:47.516420 316 : 4250, 4027
7515 12:47:47.516822 320 : 4249, 4027
7516 12:47:47.519993 324 : 4253, 4026
7517 12:47:47.520387 328 : 4250, 4026
7518 12:47:47.523789 332 : 4363, 4138
7519 12:47:47.524329 336 : 4250, 3931
7520 12:47:47.524670 340 : 4363, 2057
7521 12:47:47.526298
7522 12:47:47.526725 MIOCK jitter meter ch=0
7523 12:47:47.527045
7524 12:47:47.529708 1T = (340-92) = 248 dly cells
7525 12:47:47.536375 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7526 12:47:47.536786 ==
7527 12:47:47.540049 Dram Type= 6, Freq= 0, CH_0, rank 0
7528 12:47:47.542933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7529 12:47:47.543363 ==
7530 12:47:47.549833 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7531 12:47:47.553018 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7532 12:47:47.556283 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7533 12:47:47.562418 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7534 12:47:47.571980 [CA 0] Center 43 (12~74) winsize 63
7535 12:47:47.575676 [CA 1] Center 42 (12~73) winsize 62
7536 12:47:47.578692 [CA 2] Center 38 (9~68) winsize 60
7537 12:47:47.582304 [CA 3] Center 38 (8~68) winsize 61
7538 12:47:47.585814 [CA 4] Center 36 (7~66) winsize 60
7539 12:47:47.588854 [CA 5] Center 35 (6~65) winsize 60
7540 12:47:47.589241
7541 12:47:47.591878 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7542 12:47:47.592254
7543 12:47:47.595482 [CATrainingPosCal] consider 1 rank data
7544 12:47:47.599005 u2DelayCellTimex100 = 262/100 ps
7545 12:47:47.601830 CA0 delay=43 (12~74),Diff = 8 PI (29 cell)
7546 12:47:47.608394 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7547 12:47:47.611621 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7548 12:47:47.615205 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7549 12:47:47.618687 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7550 12:47:47.621997 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7551 12:47:47.622382
7552 12:47:47.625322 CA PerBit enable=1, Macro0, CA PI delay=35
7553 12:47:47.625745
7554 12:47:47.628408 [CBTSetCACLKResult] CA Dly = 35
7555 12:47:47.631916 CS Dly: 12 (0~43)
7556 12:47:47.634751 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7557 12:47:47.638170 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7558 12:47:47.638525 ==
7559 12:47:47.641406 Dram Type= 6, Freq= 0, CH_0, rank 1
7560 12:47:47.648211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 12:47:47.648716 ==
7562 12:47:47.651721 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7563 12:47:47.657876 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7564 12:47:47.661512 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7565 12:47:47.668059 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7566 12:47:47.675749 [CA 0] Center 43 (13~74) winsize 62
7567 12:47:47.679406 [CA 1] Center 44 (14~74) winsize 61
7568 12:47:47.682386 [CA 2] Center 38 (9~68) winsize 60
7569 12:47:47.685387 [CA 3] Center 38 (9~68) winsize 60
7570 12:47:47.688905 [CA 4] Center 36 (7~66) winsize 60
7571 12:47:47.691850 [CA 5] Center 36 (6~66) winsize 61
7572 12:47:47.692349
7573 12:47:47.695385 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7574 12:47:47.695902
7575 12:47:47.701991 [CATrainingPosCal] consider 2 rank data
7576 12:47:47.702470 u2DelayCellTimex100 = 262/100 ps
7577 12:47:47.708373 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7578 12:47:47.711857 CA1 delay=43 (14~73),Diff = 8 PI (29 cell)
7579 12:47:47.715360 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7580 12:47:47.718701 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7581 12:47:47.721912 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7582 12:47:47.725047 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7583 12:47:47.725480
7584 12:47:47.728409 CA PerBit enable=1, Macro0, CA PI delay=35
7585 12:47:47.728838
7586 12:47:47.731842 [CBTSetCACLKResult] CA Dly = 35
7587 12:47:47.735376 CS Dly: 12 (0~44)
7588 12:47:47.738333 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7589 12:47:47.741908 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7590 12:47:47.742464
7591 12:47:47.744962 ----->DramcWriteLeveling(PI) begin...
7592 12:47:47.745393 ==
7593 12:47:47.748314 Dram Type= 6, Freq= 0, CH_0, rank 0
7594 12:47:47.755300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7595 12:47:47.755862 ==
7596 12:47:47.758216 Write leveling (Byte 0): 36 => 36
7597 12:47:47.761719 Write leveling (Byte 1): 28 => 28
7598 12:47:47.765322 DramcWriteLeveling(PI) end<-----
7599 12:47:47.765748
7600 12:47:47.766086 ==
7601 12:47:47.768356 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 12:47:47.771564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 12:47:47.771994 ==
7604 12:47:47.774984 [Gating] SW mode calibration
7605 12:47:47.781283 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7606 12:47:47.784507 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7607 12:47:47.791044 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 12:47:47.794511 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 12:47:47.798200 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 12:47:47.804223 1 4 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7611 12:47:47.807797 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7612 12:47:47.810850 1 4 20 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
7613 12:47:47.817635 1 4 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7614 12:47:47.820878 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7615 12:47:47.824293 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7616 12:47:47.830721 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7617 12:47:47.834175 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7618 12:47:47.837460 1 5 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7619 12:47:47.844412 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7620 12:47:47.847251 1 5 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
7621 12:47:47.850843 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
7622 12:47:47.857426 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7623 12:47:47.860698 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 12:47:47.863894 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7625 12:47:47.870799 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7626 12:47:47.873600 1 6 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7627 12:47:47.876881 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7628 12:47:47.883483 1 6 20 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7629 12:47:47.886897 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7630 12:47:47.890186 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 12:47:47.897014 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 12:47:47.900094 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 12:47:47.903777 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7634 12:47:47.910193 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7635 12:47:47.913787 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7636 12:47:47.916785 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7637 12:47:47.923078 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7638 12:47:47.926816 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 12:47:47.929788 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 12:47:47.936581 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 12:47:47.939525 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 12:47:47.942916 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 12:47:47.949797 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 12:47:47.953145 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 12:47:47.956419 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 12:47:47.962887 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 12:47:47.966318 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 12:47:47.969283 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 12:47:47.975939 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7650 12:47:47.979740 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7651 12:47:47.982628 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7652 12:47:47.985953 Total UI for P1: 0, mck2ui 16
7653 12:47:47.989103 best dqsien dly found for B0: ( 1, 9, 10)
7654 12:47:47.996112 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7655 12:47:47.999280 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 12:47:48.002634 Total UI for P1: 0, mck2ui 16
7657 12:47:48.006160 best dqsien dly found for B1: ( 1, 9, 20)
7658 12:47:48.009090 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7659 12:47:48.012727 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7660 12:47:48.013119
7661 12:47:48.015741 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7662 12:47:48.019256 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7663 12:47:48.022644 [Gating] SW calibration Done
7664 12:47:48.023164 ==
7665 12:47:48.026167 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 12:47:48.032667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 12:47:48.033061 ==
7668 12:47:48.033371 RX Vref Scan: 0
7669 12:47:48.033661
7670 12:47:48.035606 RX Vref 0 -> 0, step: 1
7671 12:47:48.035996
7672 12:47:48.039225 RX Delay 0 -> 252, step: 8
7673 12:47:48.042267 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7674 12:47:48.045664 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7675 12:47:48.048736 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7676 12:47:48.052793 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7677 12:47:48.059227 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7678 12:47:48.062304 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7679 12:47:48.065777 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7680 12:47:48.068795 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7681 12:47:48.072156 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7682 12:47:48.078633 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7683 12:47:48.082001 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7684 12:47:48.085604 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7685 12:47:48.088931 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7686 12:47:48.092113 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7687 12:47:48.098677 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7688 12:47:48.101618 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7689 12:47:48.102144 ==
7690 12:47:48.105135 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 12:47:48.108358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 12:47:48.108881 ==
7693 12:47:48.111872 DQS Delay:
7694 12:47:48.112288 DQS0 = 0, DQS1 = 0
7695 12:47:48.112621 DQM Delay:
7696 12:47:48.115406 DQM0 = 134, DQM1 = 126
7697 12:47:48.115854 DQ Delay:
7698 12:47:48.118503 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7699 12:47:48.121924 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =147
7700 12:47:48.128231 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7701 12:47:48.132023 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7702 12:47:48.132448
7703 12:47:48.132811
7704 12:47:48.133128 ==
7705 12:47:48.134910 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 12:47:48.138518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 12:47:48.139010 ==
7708 12:47:48.139437
7709 12:47:48.139779
7710 12:47:48.141459 TX Vref Scan disable
7711 12:47:48.145149 == TX Byte 0 ==
7712 12:47:48.148069 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7713 12:47:48.151397 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7714 12:47:48.154549 == TX Byte 1 ==
7715 12:47:48.158029 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7716 12:47:48.161704 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7717 12:47:48.162130 ==
7718 12:47:48.164745 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 12:47:48.167709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 12:47:48.171082 ==
7721 12:47:48.182850
7722 12:47:48.186394 TX Vref early break, caculate TX vref
7723 12:47:48.189942 TX Vref=16, minBit 4, minWin=22, winSum=375
7724 12:47:48.193331 TX Vref=18, minBit 2, minWin=23, winSum=377
7725 12:47:48.196720 TX Vref=20, minBit 1, minWin=24, winSum=395
7726 12:47:48.199586 TX Vref=22, minBit 1, minWin=23, winSum=402
7727 12:47:48.202845 TX Vref=24, minBit 1, minWin=25, winSum=414
7728 12:47:48.209535 TX Vref=26, minBit 0, minWin=25, winSum=421
7729 12:47:48.212971 TX Vref=28, minBit 0, minWin=24, winSum=416
7730 12:47:48.215807 TX Vref=30, minBit 4, minWin=24, winSum=412
7731 12:47:48.219152 TX Vref=32, minBit 7, minWin=23, winSum=401
7732 12:47:48.222638 TX Vref=34, minBit 5, minWin=23, winSum=388
7733 12:47:48.229196 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 26
7734 12:47:48.229395
7735 12:47:48.232051 Final TX Range 0 Vref 26
7736 12:47:48.232213
7737 12:47:48.232321 ==
7738 12:47:48.235555 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 12:47:48.238555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 12:47:48.238710 ==
7741 12:47:48.238807
7742 12:47:48.238923
7743 12:47:48.242079 TX Vref Scan disable
7744 12:47:48.248536 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7745 12:47:48.248683 == TX Byte 0 ==
7746 12:47:48.252343 u2DelayCellOfst[0]=18 cells (5 PI)
7747 12:47:48.255202 u2DelayCellOfst[1]=18 cells (5 PI)
7748 12:47:48.258537 u2DelayCellOfst[2]=14 cells (4 PI)
7749 12:47:48.261516 u2DelayCellOfst[3]=14 cells (4 PI)
7750 12:47:48.265147 u2DelayCellOfst[4]=11 cells (3 PI)
7751 12:47:48.268691 u2DelayCellOfst[5]=0 cells (0 PI)
7752 12:47:48.271580 u2DelayCellOfst[6]=22 cells (6 PI)
7753 12:47:48.275045 u2DelayCellOfst[7]=22 cells (6 PI)
7754 12:47:48.278507 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7755 12:47:48.281350 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7756 12:47:48.284787 == TX Byte 1 ==
7757 12:47:48.288110 u2DelayCellOfst[8]=0 cells (0 PI)
7758 12:47:48.291399 u2DelayCellOfst[9]=0 cells (0 PI)
7759 12:47:48.294974 u2DelayCellOfst[10]=7 cells (2 PI)
7760 12:47:48.295071 u2DelayCellOfst[11]=3 cells (1 PI)
7761 12:47:48.297979 u2DelayCellOfst[12]=11 cells (3 PI)
7762 12:47:48.301637 u2DelayCellOfst[13]=11 cells (3 PI)
7763 12:47:48.304846 u2DelayCellOfst[14]=11 cells (3 PI)
7764 12:47:48.308115 u2DelayCellOfst[15]=11 cells (3 PI)
7765 12:47:48.314569 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7766 12:47:48.318145 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7767 12:47:48.318235 DramC Write-DBI on
7768 12:47:48.320925 ==
7769 12:47:48.324281 Dram Type= 6, Freq= 0, CH_0, rank 0
7770 12:47:48.327704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7771 12:47:48.327806 ==
7772 12:47:48.327876
7773 12:47:48.327953
7774 12:47:48.331351 TX Vref Scan disable
7775 12:47:48.331455 == TX Byte 0 ==
7776 12:47:48.337413 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7777 12:47:48.337546 == TX Byte 1 ==
7778 12:47:48.341077 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7779 12:47:48.344258 DramC Write-DBI off
7780 12:47:48.344381
7781 12:47:48.344479 [DATLAT]
7782 12:47:48.347734 Freq=1600, CH0 RK0
7783 12:47:48.347845
7784 12:47:48.347940 DATLAT Default: 0xf
7785 12:47:48.350821 0, 0xFFFF, sum = 0
7786 12:47:48.350955 1, 0xFFFF, sum = 0
7787 12:47:48.354355 2, 0xFFFF, sum = 0
7788 12:47:48.354478 3, 0xFFFF, sum = 0
7789 12:47:48.357265 4, 0xFFFF, sum = 0
7790 12:47:48.357395 5, 0xFFFF, sum = 0
7791 12:47:48.360839 6, 0xFFFF, sum = 0
7792 12:47:48.363883 7, 0xFFFF, sum = 0
7793 12:47:48.363998 8, 0xFFFF, sum = 0
7794 12:47:48.367495 9, 0xFFFF, sum = 0
7795 12:47:48.367629 10, 0xFFFF, sum = 0
7796 12:47:48.370538 11, 0xFFFF, sum = 0
7797 12:47:48.370655 12, 0xFFFF, sum = 0
7798 12:47:48.374081 13, 0xFFFF, sum = 0
7799 12:47:48.374186 14, 0x0, sum = 1
7800 12:47:48.377518 15, 0x0, sum = 2
7801 12:47:48.377628 16, 0x0, sum = 3
7802 12:47:48.380695 17, 0x0, sum = 4
7803 12:47:48.380800 best_step = 15
7804 12:47:48.380895
7805 12:47:48.380985 ==
7806 12:47:48.384079 Dram Type= 6, Freq= 0, CH_0, rank 0
7807 12:47:48.387222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7808 12:47:48.390210 ==
7809 12:47:48.390323 RX Vref Scan: 1
7810 12:47:48.390418
7811 12:47:48.393676 Set Vref Range= 24 -> 127
7812 12:47:48.393777
7813 12:47:48.397020 RX Vref 24 -> 127, step: 1
7814 12:47:48.397122
7815 12:47:48.397218 RX Delay 11 -> 252, step: 4
7816 12:47:48.397309
7817 12:47:48.400400 Set Vref, RX VrefLevel [Byte0]: 24
7818 12:47:48.403550 [Byte1]: 24
7819 12:47:48.407565
7820 12:47:48.407683 Set Vref, RX VrefLevel [Byte0]: 25
7821 12:47:48.412391 [Byte1]: 25
7822 12:47:48.415189
7823 12:47:48.415280 Set Vref, RX VrefLevel [Byte0]: 26
7824 12:47:48.418584 [Byte1]: 26
7825 12:47:48.422974
7826 12:47:48.423061 Set Vref, RX VrefLevel [Byte0]: 27
7827 12:47:48.425919 [Byte1]: 27
7828 12:47:48.430571
7829 12:47:48.430756 Set Vref, RX VrefLevel [Byte0]: 28
7830 12:47:48.433796 [Byte1]: 28
7831 12:47:48.441875
7832 12:47:48.441995 Set Vref, RX VrefLevel [Byte0]: 29
7833 12:47:48.442097 [Byte1]: 29
7834 12:47:48.445279
7835 12:47:48.445387 Set Vref, RX VrefLevel [Byte0]: 30
7836 12:47:48.448833 [Byte1]: 30
7837 12:47:48.453070
7838 12:47:48.453175 Set Vref, RX VrefLevel [Byte0]: 31
7839 12:47:48.461332 [Byte1]: 31
7840 12:47:48.461440
7841 12:47:48.461542 Set Vref, RX VrefLevel [Byte0]: 32
7842 12:47:48.463786 [Byte1]: 32
7843 12:47:48.468566
7844 12:47:48.468673 Set Vref, RX VrefLevel [Byte0]: 33
7845 12:47:48.471498 [Byte1]: 33
7846 12:47:48.475848
7847 12:47:48.475998 Set Vref, RX VrefLevel [Byte0]: 34
7848 12:47:48.479307 [Byte1]: 34
7849 12:47:48.483954
7850 12:47:48.484067 Set Vref, RX VrefLevel [Byte0]: 35
7851 12:47:48.488938 [Byte1]: 35
7852 12:47:48.491140
7853 12:47:48.491250 Set Vref, RX VrefLevel [Byte0]: 36
7854 12:47:48.494622 [Byte1]: 36
7855 12:47:48.498982
7856 12:47:48.499088 Set Vref, RX VrefLevel [Byte0]: 37
7857 12:47:48.501887 [Byte1]: 37
7858 12:47:48.506426
7859 12:47:48.506541 Set Vref, RX VrefLevel [Byte0]: 38
7860 12:47:48.509592 [Byte1]: 38
7861 12:47:48.514428
7862 12:47:48.514544 Set Vref, RX VrefLevel [Byte0]: 39
7863 12:47:48.517323 [Byte1]: 39
7864 12:47:48.521818
7865 12:47:48.521928 Set Vref, RX VrefLevel [Byte0]: 40
7866 12:47:48.525237 [Byte1]: 40
7867 12:47:48.528893
7868 12:47:48.532335 Set Vref, RX VrefLevel [Byte0]: 41
7869 12:47:48.535826 [Byte1]: 41
7870 12:47:48.535972
7871 12:47:48.542938 Set Vref, RX VrefLevel [Byte0]: 42
7872 12:47:48.543233 [Byte1]: 42
7873 12:47:48.543341
7874 12:47:48.545343 Set Vref, RX VrefLevel [Byte0]: 43
7875 12:47:48.549056 [Byte1]: 43
7876 12:47:48.551992
7877 12:47:48.552122 Set Vref, RX VrefLevel [Byte0]: 44
7878 12:47:48.555616 [Byte1]: 44
7879 12:47:48.559785
7880 12:47:48.559869 Set Vref, RX VrefLevel [Byte0]: 45
7881 12:47:48.566362 [Byte1]: 45
7882 12:47:48.566794
7883 12:47:48.569860 Set Vref, RX VrefLevel [Byte0]: 46
7884 12:47:48.572923 [Byte1]: 46
7885 12:47:48.573247
7886 12:47:48.576658 Set Vref, RX VrefLevel [Byte0]: 47
7887 12:47:48.579704 [Byte1]: 47
7888 12:47:48.579958
7889 12:47:48.582760 Set Vref, RX VrefLevel [Byte0]: 48
7890 12:47:48.586229 [Byte1]: 48
7891 12:47:48.590108
7892 12:47:48.590306 Set Vref, RX VrefLevel [Byte0]: 49
7893 12:47:48.593688 [Byte1]: 49
7894 12:47:48.597873
7895 12:47:48.598043 Set Vref, RX VrefLevel [Byte0]: 50
7896 12:47:48.600882 [Byte1]: 50
7897 12:47:48.605559
7898 12:47:48.605684 Set Vref, RX VrefLevel [Byte0]: 51
7899 12:47:48.608616 [Byte1]: 51
7900 12:47:48.613036
7901 12:47:48.613132 Set Vref, RX VrefLevel [Byte0]: 52
7902 12:47:48.616114 [Byte1]: 52
7903 12:47:48.620935
7904 12:47:48.621048 Set Vref, RX VrefLevel [Byte0]: 53
7905 12:47:48.624212 [Byte1]: 53
7906 12:47:48.628573
7907 12:47:48.628684 Set Vref, RX VrefLevel [Byte0]: 54
7908 12:47:48.631587 [Byte1]: 54
7909 12:47:48.635947
7910 12:47:48.636035 Set Vref, RX VrefLevel [Byte0]: 55
7911 12:47:48.639183 [Byte1]: 55
7912 12:47:48.643469
7913 12:47:48.643559 Set Vref, RX VrefLevel [Byte0]: 56
7914 12:47:48.646945 [Byte1]: 56
7915 12:47:48.650956
7916 12:47:48.651043 Set Vref, RX VrefLevel [Byte0]: 57
7917 12:47:48.654559 [Byte1]: 57
7918 12:47:48.658650
7919 12:47:48.658737 Set Vref, RX VrefLevel [Byte0]: 58
7920 12:47:48.662369 [Byte1]: 58
7921 12:47:48.666851
7922 12:47:48.666960 Set Vref, RX VrefLevel [Byte0]: 59
7923 12:47:48.669749 [Byte1]: 59
7924 12:47:48.673728
7925 12:47:48.673808 Set Vref, RX VrefLevel [Byte0]: 60
7926 12:47:48.677480 [Byte1]: 60
7927 12:47:48.681614
7928 12:47:48.681693 Set Vref, RX VrefLevel [Byte0]: 61
7929 12:47:48.684663 [Byte1]: 61
7930 12:47:48.689472
7931 12:47:48.689552 Set Vref, RX VrefLevel [Byte0]: 62
7932 12:47:48.692288 [Byte1]: 62
7933 12:47:48.697076
7934 12:47:48.697185 Set Vref, RX VrefLevel [Byte0]: 63
7935 12:47:48.700093 [Byte1]: 63
7936 12:47:48.704383
7937 12:47:48.704461 Set Vref, RX VrefLevel [Byte0]: 64
7938 12:47:48.707936 [Byte1]: 64
7939 12:47:48.712152
7940 12:47:48.712227 Set Vref, RX VrefLevel [Byte0]: 65
7941 12:47:48.715145 [Byte1]: 65
7942 12:47:48.719884
7943 12:47:48.720011 Set Vref, RX VrefLevel [Byte0]: 66
7944 12:47:48.722851 [Byte1]: 66
7945 12:47:48.727076
7946 12:47:48.727187 Set Vref, RX VrefLevel [Byte0]: 67
7947 12:47:48.730799 [Byte1]: 67
7948 12:47:48.734800
7949 12:47:48.734883 Set Vref, RX VrefLevel [Byte0]: 68
7950 12:47:48.738038 [Byte1]: 68
7951 12:47:48.742557
7952 12:47:48.742673 Set Vref, RX VrefLevel [Byte0]: 69
7953 12:47:48.745722 [Byte1]: 69
7954 12:47:48.749834
7955 12:47:48.749923 Set Vref, RX VrefLevel [Byte0]: 70
7956 12:47:48.753400 [Byte1]: 70
7957 12:47:48.757639
7958 12:47:48.757722 Set Vref, RX VrefLevel [Byte0]: 71
7959 12:47:48.763848 [Byte1]: 71
7960 12:47:48.763928
7961 12:47:48.767157 Set Vref, RX VrefLevel [Byte0]: 72
7962 12:47:48.770839 [Byte1]: 72
7963 12:47:48.770940
7964 12:47:48.774349 Set Vref, RX VrefLevel [Byte0]: 73
7965 12:47:48.777162 [Byte1]: 73
7966 12:47:48.780280
7967 12:47:48.780355 Set Vref, RX VrefLevel [Byte0]: 74
7968 12:47:48.783943 [Byte1]: 74
7969 12:47:48.788118
7970 12:47:48.788224 Set Vref, RX VrefLevel [Byte0]: 75
7971 12:47:48.791265 [Byte1]: 75
7972 12:47:48.795905
7973 12:47:48.796009 Set Vref, RX VrefLevel [Byte0]: 76
7974 12:47:48.799462 [Byte1]: 76
7975 12:47:48.803418
7976 12:47:48.803506 Set Vref, RX VrefLevel [Byte0]: 77
7977 12:47:48.806463 [Byte1]: 77
7978 12:47:48.811361
7979 12:47:48.811492 Set Vref, RX VrefLevel [Byte0]: 78
7980 12:47:48.814179 [Byte1]: 78
7981 12:47:48.818497
7982 12:47:48.818656 Set Vref, RX VrefLevel [Byte0]: 79
7983 12:47:48.821988 [Byte1]: 79
7984 12:47:48.825923
7985 12:47:48.826019 Set Vref, RX VrefLevel [Byte0]: 80
7986 12:47:48.829508 [Byte1]: 80
7987 12:47:48.833796
7988 12:47:48.833880 Set Vref, RX VrefLevel [Byte0]: 81
7989 12:47:48.837373 [Byte1]: 81
7990 12:47:48.841679
7991 12:47:48.841761 Final RX Vref Byte 0 = 65 to rank0
7992 12:47:48.844892 Final RX Vref Byte 1 = 61 to rank0
7993 12:47:48.847823 Final RX Vref Byte 0 = 65 to rank1
7994 12:47:48.851181 Final RX Vref Byte 1 = 61 to rank1==
7995 12:47:48.854413 Dram Type= 6, Freq= 0, CH_0, rank 0
7996 12:47:48.861357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7997 12:47:48.861444 ==
7998 12:47:48.861561 DQS Delay:
7999 12:47:48.864390 DQS0 = 0, DQS1 = 0
8000 12:47:48.864471 DQM Delay:
8001 12:47:48.864531 DQM0 = 132, DQM1 = 123
8002 12:47:48.868051 DQ Delay:
8003 12:47:48.870891 DQ0 =130, DQ1 =136, DQ2 =130, DQ3 =132
8004 12:47:48.874277 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =140
8005 12:47:48.877654 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8006 12:47:48.881224 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =128
8007 12:47:48.881307
8008 12:47:48.881371
8009 12:47:48.881455
8010 12:47:48.884383 [DramC_TX_OE_Calibration] TA2
8011 12:47:48.887906 Original DQ_B0 (3 6) =30, OEN = 27
8012 12:47:48.890893 Original DQ_B1 (3 6) =30, OEN = 27
8013 12:47:48.894546 24, 0x0, End_B0=24 End_B1=24
8014 12:47:48.894686 25, 0x0, End_B0=25 End_B1=25
8015 12:47:48.897628 26, 0x0, End_B0=26 End_B1=26
8016 12:47:48.901058 27, 0x0, End_B0=27 End_B1=27
8017 12:47:48.904203 28, 0x0, End_B0=28 End_B1=28
8018 12:47:48.907677 29, 0x0, End_B0=29 End_B1=29
8019 12:47:48.907756 30, 0x0, End_B0=30 End_B1=30
8020 12:47:48.910695 31, 0x4141, End_B0=30 End_B1=30
8021 12:47:48.914367 Byte0 end_step=30 best_step=27
8022 12:47:48.917336 Byte1 end_step=30 best_step=27
8023 12:47:48.920944 Byte0 TX OE(2T, 0.5T) = (3, 3)
8024 12:47:48.923952 Byte1 TX OE(2T, 0.5T) = (3, 3)
8025 12:47:48.924030
8026 12:47:48.924093
8027 12:47:48.930474 [DQSOSCAuto] RK0, (LSB)MR18= 0x2011, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
8028 12:47:48.933917 CH0 RK0: MR19=303, MR18=2011
8029 12:47:48.940645 CH0_RK0: MR19=0x303, MR18=0x2011, DQSOSC=393, MR23=63, INC=23, DEC=15
8030 12:47:48.940725
8031 12:47:48.944308 ----->DramcWriteLeveling(PI) begin...
8032 12:47:48.944392 ==
8033 12:47:48.947262 Dram Type= 6, Freq= 0, CH_0, rank 1
8034 12:47:48.950850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8035 12:47:48.950933 ==
8036 12:47:48.954098 Write leveling (Byte 0): 34 => 34
8037 12:47:48.957151 Write leveling (Byte 1): 28 => 28
8038 12:47:48.960589 DramcWriteLeveling(PI) end<-----
8039 12:47:48.960665
8040 12:47:48.960729 ==
8041 12:47:48.963840 Dram Type= 6, Freq= 0, CH_0, rank 1
8042 12:47:48.967058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8043 12:47:48.967135 ==
8044 12:47:48.970289 [Gating] SW mode calibration
8045 12:47:48.976762 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8046 12:47:48.983396 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8047 12:47:48.986827 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8048 12:47:48.993467 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 12:47:48.997081 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 12:47:49.000163 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8051 12:47:49.006853 1 4 16 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8052 12:47:49.010216 1 4 20 | B1->B0 | 3131 3434 | 0 1 | (1 1) (1 1)
8053 12:47:49.013683 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8054 12:47:49.020132 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8055 12:47:49.023159 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8056 12:47:49.026747 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8057 12:47:49.033209 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8058 12:47:49.036742 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8059 12:47:49.039620 1 5 16 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
8060 12:47:49.046313 1 5 20 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
8061 12:47:49.049883 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 12:47:49.052867 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 12:47:49.059528 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 12:47:49.062623 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 12:47:49.066291 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 12:47:49.072685 1 6 12 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
8067 12:47:49.076003 1 6 16 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8068 12:47:49.079380 1 6 20 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
8069 12:47:49.085928 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8070 12:47:49.089398 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 12:47:49.092701 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 12:47:49.099322 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 12:47:49.102326 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 12:47:49.106028 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8075 12:47:49.112210 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8076 12:47:49.115713 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8077 12:47:49.119112 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 12:47:49.126058 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 12:47:49.128809 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 12:47:49.132602 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 12:47:49.138518 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 12:47:49.142106 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 12:47:49.145408 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 12:47:49.152110 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 12:47:49.155197 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 12:47:49.158311 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 12:47:49.165396 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 12:47:49.168152 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 12:47:49.171474 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 12:47:49.178170 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8091 12:47:49.181639 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8092 12:47:49.184998 Total UI for P1: 0, mck2ui 16
8093 12:47:49.188313 best dqsien dly found for B0: ( 1, 9, 12)
8094 12:47:49.191394 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8095 12:47:49.197996 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8096 12:47:49.198112 Total UI for P1: 0, mck2ui 16
8097 12:47:49.201390 best dqsien dly found for B1: ( 1, 9, 18)
8098 12:47:49.207823 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8099 12:47:49.211359 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8100 12:47:49.211445
8101 12:47:49.214390 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8102 12:47:49.217989 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8103 12:47:49.220941 [Gating] SW calibration Done
8104 12:47:49.221017 ==
8105 12:47:49.224597 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 12:47:49.227995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 12:47:49.228098 ==
8108 12:47:49.230914 RX Vref Scan: 0
8109 12:47:49.230994
8110 12:47:49.231058 RX Vref 0 -> 0, step: 1
8111 12:47:49.231119
8112 12:47:49.234366 RX Delay 0 -> 252, step: 8
8113 12:47:49.237902 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8114 12:47:49.244487 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8115 12:47:49.247432 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8116 12:47:49.250914 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8117 12:47:49.253860 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8118 12:47:49.257553 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8119 12:47:49.264162 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8120 12:47:49.267691 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8121 12:47:49.270707 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8122 12:47:49.274282 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8123 12:47:49.277239 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8124 12:47:49.284002 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8125 12:47:49.287636 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8126 12:47:49.290529 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8127 12:47:49.293766 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8128 12:47:49.300933 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8129 12:47:49.301050 ==
8130 12:47:49.303947 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 12:47:49.306983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 12:47:49.307064 ==
8133 12:47:49.307134 DQS Delay:
8134 12:47:49.310442 DQS0 = 0, DQS1 = 0
8135 12:47:49.310564 DQM Delay:
8136 12:47:49.313705 DQM0 = 132, DQM1 = 127
8137 12:47:49.313807 DQ Delay:
8138 12:47:49.316981 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8139 12:47:49.320364 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8140 12:47:49.323803 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8141 12:47:49.327103 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8142 12:47:49.327178
8143 12:47:49.327239
8144 12:47:49.330366 ==
8145 12:47:49.333351 Dram Type= 6, Freq= 0, CH_0, rank 1
8146 12:47:49.337026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8147 12:47:49.337154 ==
8148 12:47:49.337271
8149 12:47:49.337369
8150 12:47:49.340328 TX Vref Scan disable
8151 12:47:49.340431 == TX Byte 0 ==
8152 12:47:49.343486 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8153 12:47:49.350045 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8154 12:47:49.350152 == TX Byte 1 ==
8155 12:47:49.353909 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8156 12:47:49.360084 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8157 12:47:49.360172 ==
8158 12:47:49.363194 Dram Type= 6, Freq= 0, CH_0, rank 1
8159 12:47:49.366786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8160 12:47:49.366872 ==
8161 12:47:49.380417
8162 12:47:49.383441 TX Vref early break, caculate TX vref
8163 12:47:49.386859 TX Vref=16, minBit 4, minWin=22, winSum=380
8164 12:47:49.390443 TX Vref=18, minBit 0, minWin=23, winSum=384
8165 12:47:49.393664 TX Vref=20, minBit 2, minWin=23, winSum=394
8166 12:47:49.396657 TX Vref=22, minBit 1, minWin=24, winSum=404
8167 12:47:49.399909 TX Vref=24, minBit 7, minWin=24, winSum=411
8168 12:47:49.406882 TX Vref=26, minBit 1, minWin=24, winSum=415
8169 12:47:49.409790 TX Vref=28, minBit 0, minWin=25, winSum=413
8170 12:47:49.413415 TX Vref=30, minBit 0, minWin=24, winSum=403
8171 12:47:49.416348 TX Vref=32, minBit 0, minWin=24, winSum=396
8172 12:47:49.419796 TX Vref=34, minBit 0, minWin=23, winSum=384
8173 12:47:49.426459 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 28
8174 12:47:49.426548
8175 12:47:49.429629 Final TX Range 0 Vref 28
8176 12:47:49.429713
8177 12:47:49.429806 ==
8178 12:47:49.433207 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 12:47:49.436728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 12:47:49.436813 ==
8181 12:47:49.436879
8182 12:47:49.436939
8183 12:47:49.439764 TX Vref Scan disable
8184 12:47:49.446536 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8185 12:47:49.446681 == TX Byte 0 ==
8186 12:47:49.449556 u2DelayCellOfst[0]=14 cells (4 PI)
8187 12:47:49.452968 u2DelayCellOfst[1]=18 cells (5 PI)
8188 12:47:49.456431 u2DelayCellOfst[2]=14 cells (4 PI)
8189 12:47:49.459506 u2DelayCellOfst[3]=18 cells (5 PI)
8190 12:47:49.462943 u2DelayCellOfst[4]=11 cells (3 PI)
8191 12:47:49.466266 u2DelayCellOfst[5]=0 cells (0 PI)
8192 12:47:49.469555 u2DelayCellOfst[6]=22 cells (6 PI)
8193 12:47:49.472671 u2DelayCellOfst[7]=22 cells (6 PI)
8194 12:47:49.476275 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8195 12:47:49.479298 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8196 12:47:49.482921 == TX Byte 1 ==
8197 12:47:49.486058 u2DelayCellOfst[8]=0 cells (0 PI)
8198 12:47:49.489660 u2DelayCellOfst[9]=0 cells (0 PI)
8199 12:47:49.489750 u2DelayCellOfst[10]=7 cells (2 PI)
8200 12:47:49.492819 u2DelayCellOfst[11]=0 cells (0 PI)
8201 12:47:49.496351 u2DelayCellOfst[12]=11 cells (3 PI)
8202 12:47:49.499365 u2DelayCellOfst[13]=14 cells (4 PI)
8203 12:47:49.502648 u2DelayCellOfst[14]=14 cells (4 PI)
8204 12:47:49.505818 u2DelayCellOfst[15]=11 cells (3 PI)
8205 12:47:49.512692 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8206 12:47:49.515722 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8207 12:47:49.515808 DramC Write-DBI on
8208 12:47:49.515875 ==
8209 12:47:49.519402 Dram Type= 6, Freq= 0, CH_0, rank 1
8210 12:47:49.525907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8211 12:47:49.525994 ==
8212 12:47:49.526061
8213 12:47:49.526141
8214 12:47:49.526273 TX Vref Scan disable
8215 12:47:49.529772 == TX Byte 0 ==
8216 12:47:49.533297 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8217 12:47:49.536352 == TX Byte 1 ==
8218 12:47:49.539881 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8219 12:47:49.543277 DramC Write-DBI off
8220 12:47:49.543365
8221 12:47:49.543431 [DATLAT]
8222 12:47:49.543492 Freq=1600, CH0 RK1
8223 12:47:49.543551
8224 12:47:49.546250 DATLAT Default: 0xf
8225 12:47:49.546334 0, 0xFFFF, sum = 0
8226 12:47:49.549869 1, 0xFFFF, sum = 0
8227 12:47:49.552877 2, 0xFFFF, sum = 0
8228 12:47:49.552981 3, 0xFFFF, sum = 0
8229 12:47:49.556553 4, 0xFFFF, sum = 0
8230 12:47:49.556638 5, 0xFFFF, sum = 0
8231 12:47:49.559631 6, 0xFFFF, sum = 0
8232 12:47:49.559716 7, 0xFFFF, sum = 0
8233 12:47:49.562712 8, 0xFFFF, sum = 0
8234 12:47:49.562823 9, 0xFFFF, sum = 0
8235 12:47:49.566285 10, 0xFFFF, sum = 0
8236 12:47:49.566394 11, 0xFFFF, sum = 0
8237 12:47:49.569665 12, 0xFFFF, sum = 0
8238 12:47:49.569750 13, 0xFFFF, sum = 0
8239 12:47:49.572621 14, 0x0, sum = 1
8240 12:47:49.572733 15, 0x0, sum = 2
8241 12:47:49.576253 16, 0x0, sum = 3
8242 12:47:49.576337 17, 0x0, sum = 4
8243 12:47:49.579308 best_step = 15
8244 12:47:49.579391
8245 12:47:49.579456 ==
8246 12:47:49.582981 Dram Type= 6, Freq= 0, CH_0, rank 1
8247 12:47:49.585898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8248 12:47:49.585983 ==
8249 12:47:49.589526 RX Vref Scan: 0
8250 12:47:49.589612
8251 12:47:49.589679 RX Vref 0 -> 0, step: 1
8252 12:47:49.589740
8253 12:47:49.592544 RX Delay 11 -> 252, step: 4
8254 12:47:49.599119 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8255 12:47:49.602740 iDelay=195, Bit 1, Center 136 (83 ~ 190) 108
8256 12:47:49.606449 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8257 12:47:49.609091 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8258 12:47:49.612614 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8259 12:47:49.619246 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8260 12:47:49.622654 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8261 12:47:49.625586 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8262 12:47:49.629341 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8263 12:47:49.632127 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8264 12:47:49.638765 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8265 12:47:49.642236 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8266 12:47:49.645630 iDelay=195, Bit 12, Center 128 (75 ~ 182) 108
8267 12:47:49.648462 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8268 12:47:49.655158 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8269 12:47:49.658422 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8270 12:47:49.658508 ==
8271 12:47:49.662003 Dram Type= 6, Freq= 0, CH_0, rank 1
8272 12:47:49.665440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8273 12:47:49.665524 ==
8274 12:47:49.665589 DQS Delay:
8275 12:47:49.668845 DQS0 = 0, DQS1 = 0
8276 12:47:49.668929 DQM Delay:
8277 12:47:49.671847 DQM0 = 130, DQM1 = 125
8278 12:47:49.671931 DQ Delay:
8279 12:47:49.675249 DQ0 =128, DQ1 =136, DQ2 =124, DQ3 =128
8280 12:47:49.678867 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8281 12:47:49.681915 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8282 12:47:49.688637 DQ12 =128, DQ13 =132, DQ14 =136, DQ15 =132
8283 12:47:49.688726
8284 12:47:49.688793
8285 12:47:49.688853
8286 12:47:49.688911 [DramC_TX_OE_Calibration] TA2
8287 12:47:49.691615 Original DQ_B0 (3 6) =30, OEN = 27
8288 12:47:49.695237 Original DQ_B1 (3 6) =30, OEN = 27
8289 12:47:49.698220 24, 0x0, End_B0=24 End_B1=24
8290 12:47:49.701826 25, 0x0, End_B0=25 End_B1=25
8291 12:47:49.704830 26, 0x0, End_B0=26 End_B1=26
8292 12:47:49.704918 27, 0x0, End_B0=27 End_B1=27
8293 12:47:49.708441 28, 0x0, End_B0=28 End_B1=28
8294 12:47:49.711497 29, 0x0, End_B0=29 End_B1=29
8295 12:47:49.714892 30, 0x0, End_B0=30 End_B1=30
8296 12:47:49.718245 31, 0x5151, End_B0=30 End_B1=30
8297 12:47:49.721437 Byte0 end_step=30 best_step=27
8298 12:47:49.721521 Byte1 end_step=30 best_step=27
8299 12:47:49.724830 Byte0 TX OE(2T, 0.5T) = (3, 3)
8300 12:47:49.728113 Byte1 TX OE(2T, 0.5T) = (3, 3)
8301 12:47:49.728196
8302 12:47:49.728262
8303 12:47:49.738122 [DQSOSCAuto] RK1, (LSB)MR18= 0x2205, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps
8304 12:47:49.738213 CH0 RK1: MR19=303, MR18=2205
8305 12:47:49.744557 CH0_RK1: MR19=0x303, MR18=0x2205, DQSOSC=392, MR23=63, INC=24, DEC=16
8306 12:47:49.747729 [RxdqsGatingPostProcess] freq 1600
8307 12:47:49.754798 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8308 12:47:49.757675 best DQS0 dly(2T, 0.5T) = (1, 1)
8309 12:47:49.761415 best DQS1 dly(2T, 0.5T) = (1, 1)
8310 12:47:49.764501 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8311 12:47:49.768312 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8312 12:47:49.768397 best DQS0 dly(2T, 0.5T) = (1, 1)
8313 12:47:49.770986 best DQS1 dly(2T, 0.5T) = (1, 1)
8314 12:47:49.774375 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8315 12:47:49.777840 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8316 12:47:49.781306 Pre-setting of DQS Precalculation
8317 12:47:49.787971 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8318 12:47:49.788062 ==
8319 12:47:49.791080 Dram Type= 6, Freq= 0, CH_1, rank 0
8320 12:47:49.793991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 12:47:49.794074 ==
8322 12:47:49.801149 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8323 12:47:49.804173 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8324 12:47:49.807302 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8325 12:47:49.813911 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8326 12:47:49.823358 [CA 0] Center 41 (12~71) winsize 60
8327 12:47:49.826072 [CA 1] Center 42 (12~72) winsize 61
8328 12:47:49.829621 [CA 2] Center 36 (7~66) winsize 60
8329 12:47:49.833130 [CA 3] Center 36 (7~65) winsize 59
8330 12:47:49.835983 [CA 4] Center 36 (7~66) winsize 60
8331 12:47:49.839646 [CA 5] Center 36 (6~66) winsize 61
8332 12:47:49.839731
8333 12:47:49.842716 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8334 12:47:49.842806
8335 12:47:49.845955 [CATrainingPosCal] consider 1 rank data
8336 12:47:49.849505 u2DelayCellTimex100 = 262/100 ps
8337 12:47:49.856205 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8338 12:47:49.859266 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8339 12:47:49.862363 CA2 delay=36 (7~66),Diff = 0 PI (0 cell)
8340 12:47:49.865979 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8341 12:47:49.869515 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8342 12:47:49.872643 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8343 12:47:49.872742
8344 12:47:49.875992 CA PerBit enable=1, Macro0, CA PI delay=36
8345 12:47:49.876074
8346 12:47:49.879175 [CBTSetCACLKResult] CA Dly = 36
8347 12:47:49.882417 CS Dly: 9 (0~40)
8348 12:47:49.885668 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8349 12:47:49.889282 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8350 12:47:49.889381 ==
8351 12:47:49.892684 Dram Type= 6, Freq= 0, CH_1, rank 1
8352 12:47:49.895653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8353 12:47:49.899297 ==
8354 12:47:49.902303 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8355 12:47:49.905316 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8356 12:47:49.912105 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8357 12:47:49.918566 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8358 12:47:49.926315 [CA 0] Center 41 (12~71) winsize 60
8359 12:47:49.929250 [CA 1] Center 42 (12~72) winsize 61
8360 12:47:49.932669 [CA 2] Center 37 (8~67) winsize 60
8361 12:47:49.935922 [CA 3] Center 37 (8~66) winsize 59
8362 12:47:49.939605 [CA 4] Center 37 (7~67) winsize 61
8363 12:47:49.942550 [CA 5] Center 37 (7~67) winsize 61
8364 12:47:49.942699
8365 12:47:49.946010 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8366 12:47:49.946095
8367 12:47:49.949384 [CATrainingPosCal] consider 2 rank data
8368 12:47:49.952517 u2DelayCellTimex100 = 262/100 ps
8369 12:47:49.956048 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8370 12:47:49.962456 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8371 12:47:49.965999 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8372 12:47:49.969236 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8373 12:47:49.972842 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8374 12:47:49.975682 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8375 12:47:49.975767
8376 12:47:49.979071 CA PerBit enable=1, Macro0, CA PI delay=36
8377 12:47:49.979157
8378 12:47:49.982254 [CBTSetCACLKResult] CA Dly = 36
8379 12:47:49.985689 CS Dly: 10 (0~43)
8380 12:47:49.988915 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8381 12:47:49.992293 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8382 12:47:49.992379
8383 12:47:49.995458 ----->DramcWriteLeveling(PI) begin...
8384 12:47:49.995567 ==
8385 12:47:49.998902 Dram Type= 6, Freq= 0, CH_1, rank 0
8386 12:47:50.005468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8387 12:47:50.005556 ==
8388 12:47:50.008978 Write leveling (Byte 0): 23 => 23
8389 12:47:50.009062 Write leveling (Byte 1): 27 => 27
8390 12:47:50.012009 DramcWriteLeveling(PI) end<-----
8391 12:47:50.012092
8392 12:47:50.012158 ==
8393 12:47:50.015611 Dram Type= 6, Freq= 0, CH_1, rank 0
8394 12:47:50.022260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8395 12:47:50.022345 ==
8396 12:47:50.025315 [Gating] SW mode calibration
8397 12:47:50.031920 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8398 12:47:50.035578 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8399 12:47:50.041879 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 12:47:50.045435 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 12:47:50.048559 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8402 12:47:50.055543 1 4 12 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8403 12:47:50.058648 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8404 12:47:50.061601 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8405 12:47:50.068546 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8406 12:47:50.071870 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8407 12:47:50.074809 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8408 12:47:50.081584 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8409 12:47:50.084841 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8410 12:47:50.088179 1 5 12 | B1->B0 | 3434 2727 | 0 0 | (0 1) (1 0)
8411 12:47:50.094631 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8412 12:47:50.098168 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 12:47:50.101226 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 12:47:50.107881 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 12:47:50.111546 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 12:47:50.114522 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 12:47:50.121179 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8418 12:47:50.124782 1 6 12 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
8419 12:47:50.127808 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 12:47:50.134504 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 12:47:50.138047 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8422 12:47:50.141022 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 12:47:50.147650 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 12:47:50.151031 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8425 12:47:50.153991 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8426 12:47:50.160592 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8427 12:47:50.164070 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8428 12:47:50.167535 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 12:47:50.174308 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 12:47:50.177618 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 12:47:50.180396 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 12:47:50.187414 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 12:47:50.190434 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 12:47:50.193983 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 12:47:50.200305 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 12:47:50.204132 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 12:47:50.207142 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 12:47:50.213821 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 12:47:50.216831 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 12:47:50.220501 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 12:47:50.226990 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8442 12:47:50.230121 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8443 12:47:50.233535 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8444 12:47:50.236644 Total UI for P1: 0, mck2ui 16
8445 12:47:50.240215 best dqsien dly found for B0: ( 1, 9, 10)
8446 12:47:50.243360 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8447 12:47:50.246923 Total UI for P1: 0, mck2ui 16
8448 12:47:50.250114 best dqsien dly found for B1: ( 1, 9, 14)
8449 12:47:50.253671 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8450 12:47:50.260110 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8451 12:47:50.260485
8452 12:47:50.263569 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8453 12:47:50.267064 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8454 12:47:50.270577 [Gating] SW calibration Done
8455 12:47:50.271054 ==
8456 12:47:50.273607 Dram Type= 6, Freq= 0, CH_1, rank 0
8457 12:47:50.277034 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8458 12:47:50.277410 ==
8459 12:47:50.280108 RX Vref Scan: 0
8460 12:47:50.280476
8461 12:47:50.280844 RX Vref 0 -> 0, step: 1
8462 12:47:50.281224
8463 12:47:50.283681 RX Delay 0 -> 252, step: 8
8464 12:47:50.286908 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8465 12:47:50.293538 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8466 12:47:50.296593 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8467 12:47:50.300277 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8468 12:47:50.303712 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8469 12:47:50.306517 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8470 12:47:50.313489 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8471 12:47:50.316659 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8472 12:47:50.319861 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8473 12:47:50.323300 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8474 12:47:50.326314 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8475 12:47:50.332894 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8476 12:47:50.336427 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8477 12:47:50.339541 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8478 12:47:50.343131 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8479 12:47:50.346183 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8480 12:47:50.349914 ==
8481 12:47:50.352798 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 12:47:50.356423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 12:47:50.356857 ==
8484 12:47:50.357159 DQS Delay:
8485 12:47:50.359771 DQS0 = 0, DQS1 = 0
8486 12:47:50.360133 DQM Delay:
8487 12:47:50.362545 DQM0 = 138, DQM1 = 129
8488 12:47:50.362963 DQ Delay:
8489 12:47:50.366145 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =135
8490 12:47:50.369424 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8491 12:47:50.372987 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8492 12:47:50.376018 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8493 12:47:50.376451
8494 12:47:50.376747
8495 12:47:50.379238 ==
8496 12:47:50.382822 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 12:47:50.385880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8498 12:47:50.386336 ==
8499 12:47:50.386671
8500 12:47:50.386948
8501 12:47:50.389215 TX Vref Scan disable
8502 12:47:50.389707 == TX Byte 0 ==
8503 12:47:50.392462 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8504 12:47:50.399231 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8505 12:47:50.399707 == TX Byte 1 ==
8506 12:47:50.405413 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8507 12:47:50.408813 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8508 12:47:50.409377 ==
8509 12:47:50.412419 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 12:47:50.415392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 12:47:50.415933 ==
8512 12:47:50.428618
8513 12:47:50.432007 TX Vref early break, caculate TX vref
8514 12:47:50.435305 TX Vref=16, minBit 0, minWin=22, winSum=377
8515 12:47:50.438869 TX Vref=18, minBit 0, minWin=22, winSum=385
8516 12:47:50.441952 TX Vref=20, minBit 5, minWin=23, winSum=395
8517 12:47:50.445110 TX Vref=22, minBit 5, minWin=23, winSum=404
8518 12:47:50.448395 TX Vref=24, minBit 0, minWin=24, winSum=411
8519 12:47:50.455190 TX Vref=26, minBit 0, minWin=25, winSum=423
8520 12:47:50.458726 TX Vref=28, minBit 1, minWin=24, winSum=420
8521 12:47:50.461764 TX Vref=30, minBit 1, minWin=24, winSum=414
8522 12:47:50.464857 TX Vref=32, minBit 0, minWin=23, winSum=401
8523 12:47:50.468597 TX Vref=34, minBit 0, minWin=23, winSum=394
8524 12:47:50.475095 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 26
8525 12:47:50.475483
8526 12:47:50.478021 Final TX Range 0 Vref 26
8527 12:47:50.478537
8528 12:47:50.479000 ==
8529 12:47:50.481485 Dram Type= 6, Freq= 0, CH_1, rank 0
8530 12:47:50.484646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8531 12:47:50.485073 ==
8532 12:47:50.485387
8533 12:47:50.485703
8534 12:47:50.488388 TX Vref Scan disable
8535 12:47:50.494984 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8536 12:47:50.495380 == TX Byte 0 ==
8537 12:47:50.497970 u2DelayCellOfst[0]=22 cells (6 PI)
8538 12:47:50.501600 u2DelayCellOfst[1]=14 cells (4 PI)
8539 12:47:50.504871 u2DelayCellOfst[2]=0 cells (0 PI)
8540 12:47:50.508161 u2DelayCellOfst[3]=7 cells (2 PI)
8541 12:47:50.511356 u2DelayCellOfst[4]=11 cells (3 PI)
8542 12:47:50.514441 u2DelayCellOfst[5]=26 cells (7 PI)
8543 12:47:50.517772 u2DelayCellOfst[6]=22 cells (6 PI)
8544 12:47:50.521246 u2DelayCellOfst[7]=7 cells (2 PI)
8545 12:47:50.524421 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8546 12:47:50.527988 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8547 12:47:50.530974 == TX Byte 1 ==
8548 12:47:50.534634 u2DelayCellOfst[8]=0 cells (0 PI)
8549 12:47:50.535044 u2DelayCellOfst[9]=3 cells (1 PI)
8550 12:47:50.537991 u2DelayCellOfst[10]=11 cells (3 PI)
8551 12:47:50.540938 u2DelayCellOfst[11]=3 cells (1 PI)
8552 12:47:50.544138 u2DelayCellOfst[12]=14 cells (4 PI)
8553 12:47:50.547966 u2DelayCellOfst[13]=14 cells (4 PI)
8554 12:47:50.550947 u2DelayCellOfst[14]=18 cells (5 PI)
8555 12:47:50.554373 u2DelayCellOfst[15]=18 cells (5 PI)
8556 12:47:50.560747 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8557 12:47:50.564351 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8558 12:47:50.564742 DramC Write-DBI on
8559 12:47:50.565052 ==
8560 12:47:50.567372 Dram Type= 6, Freq= 0, CH_1, rank 0
8561 12:47:50.574420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8562 12:47:50.574880 ==
8563 12:47:50.575197
8564 12:47:50.575482
8565 12:47:50.575760 TX Vref Scan disable
8566 12:47:50.578049 == TX Byte 0 ==
8567 12:47:50.581085 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8568 12:47:50.584759 == TX Byte 1 ==
8569 12:47:50.587653 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8570 12:47:50.591427 DramC Write-DBI off
8571 12:47:50.591854
8572 12:47:50.592266 [DATLAT]
8573 12:47:50.592567 Freq=1600, CH1 RK0
8574 12:47:50.592853
8575 12:47:50.594696 DATLAT Default: 0xf
8576 12:47:50.595089 0, 0xFFFF, sum = 0
8577 12:47:50.598086 1, 0xFFFF, sum = 0
8578 12:47:50.601487 2, 0xFFFF, sum = 0
8579 12:47:50.601885 3, 0xFFFF, sum = 0
8580 12:47:50.604282 4, 0xFFFF, sum = 0
8581 12:47:50.604677 5, 0xFFFF, sum = 0
8582 12:47:50.607942 6, 0xFFFF, sum = 0
8583 12:47:50.608339 7, 0xFFFF, sum = 0
8584 12:47:50.610934 8, 0xFFFF, sum = 0
8585 12:47:50.611329 9, 0xFFFF, sum = 0
8586 12:47:50.614645 10, 0xFFFF, sum = 0
8587 12:47:50.615049 11, 0xFFFF, sum = 0
8588 12:47:50.617698 12, 0xFFFF, sum = 0
8589 12:47:50.618132 13, 0xFFFF, sum = 0
8590 12:47:50.620775 14, 0x0, sum = 1
8591 12:47:50.621175 15, 0x0, sum = 2
8592 12:47:50.624044 16, 0x0, sum = 3
8593 12:47:50.624441 17, 0x0, sum = 4
8594 12:47:50.627886 best_step = 15
8595 12:47:50.628335
8596 12:47:50.628790 ==
8597 12:47:50.630848 Dram Type= 6, Freq= 0, CH_1, rank 0
8598 12:47:50.634191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8599 12:47:50.634667 ==
8600 12:47:50.637408 RX Vref Scan: 1
8601 12:47:50.637794
8602 12:47:50.638101 Set Vref Range= 24 -> 127
8603 12:47:50.638390
8604 12:47:50.640603 RX Vref 24 -> 127, step: 1
8605 12:47:50.640992
8606 12:47:50.644153 RX Delay 11 -> 252, step: 4
8607 12:47:50.644545
8608 12:47:50.647247 Set Vref, RX VrefLevel [Byte0]: 24
8609 12:47:50.650322 [Byte1]: 24
8610 12:47:50.650862
8611 12:47:50.653578 Set Vref, RX VrefLevel [Byte0]: 25
8612 12:47:50.657330 [Byte1]: 25
8613 12:47:50.660628
8614 12:47:50.661153 Set Vref, RX VrefLevel [Byte0]: 26
8615 12:47:50.664130 [Byte1]: 26
8616 12:47:50.668419
8617 12:47:50.668846 Set Vref, RX VrefLevel [Byte0]: 27
8618 12:47:50.671500 [Byte1]: 27
8619 12:47:50.676436
8620 12:47:50.676835 Set Vref, RX VrefLevel [Byte0]: 28
8621 12:47:50.679427 [Byte1]: 28
8622 12:47:50.683764
8623 12:47:50.684217 Set Vref, RX VrefLevel [Byte0]: 29
8624 12:47:50.687449 [Byte1]: 29
8625 12:47:50.691474
8626 12:47:50.691858 Set Vref, RX VrefLevel [Byte0]: 30
8627 12:47:50.694671 [Byte1]: 30
8628 12:47:50.698824
8629 12:47:50.699312 Set Vref, RX VrefLevel [Byte0]: 31
8630 12:47:50.702297 [Byte1]: 31
8631 12:47:50.707090
8632 12:47:50.707509 Set Vref, RX VrefLevel [Byte0]: 32
8633 12:47:50.709830 [Byte1]: 32
8634 12:47:50.714487
8635 12:47:50.714946 Set Vref, RX VrefLevel [Byte0]: 33
8636 12:47:50.717733 [Byte1]: 33
8637 12:47:50.721920
8638 12:47:50.722372 Set Vref, RX VrefLevel [Byte0]: 34
8639 12:47:50.724924 [Byte1]: 34
8640 12:47:50.729734
8641 12:47:50.730016 Set Vref, RX VrefLevel [Byte0]: 35
8642 12:47:50.732624 [Byte1]: 35
8643 12:47:50.736609
8644 12:47:50.736825 Set Vref, RX VrefLevel [Byte0]: 36
8645 12:47:50.740301 [Byte1]: 36
8646 12:47:50.744439
8647 12:47:50.744614 Set Vref, RX VrefLevel [Byte0]: 37
8648 12:47:50.747652 [Byte1]: 37
8649 12:47:50.751772
8650 12:47:50.751947 Set Vref, RX VrefLevel [Byte0]: 38
8651 12:47:50.755536 [Byte1]: 38
8652 12:47:50.759755
8653 12:47:50.759928 Set Vref, RX VrefLevel [Byte0]: 39
8654 12:47:50.762789 [Byte1]: 39
8655 12:47:50.767116
8656 12:47:50.767279 Set Vref, RX VrefLevel [Byte0]: 40
8657 12:47:50.770385 [Byte1]: 40
8658 12:47:50.774520
8659 12:47:50.774612 Set Vref, RX VrefLevel [Byte0]: 41
8660 12:47:50.778259 [Byte1]: 41
8661 12:47:50.782540
8662 12:47:50.782666 Set Vref, RX VrefLevel [Byte0]: 42
8663 12:47:50.785554 [Byte1]: 42
8664 12:47:50.789791
8665 12:47:50.789873 Set Vref, RX VrefLevel [Byte0]: 43
8666 12:47:50.793377 [Byte1]: 43
8667 12:47:50.797631
8668 12:47:50.797719 Set Vref, RX VrefLevel [Byte0]: 44
8669 12:47:50.800602 [Byte1]: 44
8670 12:47:50.805369
8671 12:47:50.805471 Set Vref, RX VrefLevel [Byte0]: 45
8672 12:47:50.808335 [Byte1]: 45
8673 12:47:50.813345
8674 12:47:50.813732 Set Vref, RX VrefLevel [Byte0]: 46
8675 12:47:50.816311 [Byte1]: 46
8676 12:47:50.820719
8677 12:47:50.821169 Set Vref, RX VrefLevel [Byte0]: 47
8678 12:47:50.823936 [Byte1]: 47
8679 12:47:50.828648
8680 12:47:50.829130 Set Vref, RX VrefLevel [Byte0]: 48
8681 12:47:50.831974 [Byte1]: 48
8682 12:47:50.836017
8683 12:47:50.836407 Set Vref, RX VrefLevel [Byte0]: 49
8684 12:47:50.839500 [Byte1]: 49
8685 12:47:50.843715
8686 12:47:50.844104 Set Vref, RX VrefLevel [Byte0]: 50
8687 12:47:50.847277 [Byte1]: 50
8688 12:47:50.851149
8689 12:47:50.851680 Set Vref, RX VrefLevel [Byte0]: 51
8690 12:47:50.854429 [Byte1]: 51
8691 12:47:50.858682
8692 12:47:50.859136 Set Vref, RX VrefLevel [Byte0]: 52
8693 12:47:50.862137 [Byte1]: 52
8694 12:47:50.866324
8695 12:47:50.866860 Set Vref, RX VrefLevel [Byte0]: 53
8696 12:47:50.870124 [Byte1]: 53
8697 12:47:50.873960
8698 12:47:50.874420 Set Vref, RX VrefLevel [Byte0]: 54
8699 12:47:50.877117 [Byte1]: 54
8700 12:47:50.882021
8701 12:47:50.882398 Set Vref, RX VrefLevel [Byte0]: 55
8702 12:47:50.884903 [Byte1]: 55
8703 12:47:50.889369
8704 12:47:50.889802 Set Vref, RX VrefLevel [Byte0]: 56
8705 12:47:50.892495 [Byte1]: 56
8706 12:47:50.896753
8707 12:47:50.897141 Set Vref, RX VrefLevel [Byte0]: 57
8708 12:47:50.900468 [Byte1]: 57
8709 12:47:50.904574
8710 12:47:50.905083 Set Vref, RX VrefLevel [Byte0]: 58
8711 12:47:50.907643 [Byte1]: 58
8712 12:47:50.911963
8713 12:47:50.912353 Set Vref, RX VrefLevel [Byte0]: 59
8714 12:47:50.915440 [Byte1]: 59
8715 12:47:50.919678
8716 12:47:50.920067 Set Vref, RX VrefLevel [Byte0]: 60
8717 12:47:50.923324 [Byte1]: 60
8718 12:47:50.927338
8719 12:47:50.927834 Set Vref, RX VrefLevel [Byte0]: 61
8720 12:47:50.930536 [Byte1]: 61
8721 12:47:50.935025
8722 12:47:50.935499 Set Vref, RX VrefLevel [Byte0]: 62
8723 12:47:50.938033 [Byte1]: 62
8724 12:47:50.942319
8725 12:47:50.942887 Set Vref, RX VrefLevel [Byte0]: 63
8726 12:47:50.946008 [Byte1]: 63
8727 12:47:50.950256
8728 12:47:50.950729 Set Vref, RX VrefLevel [Byte0]: 64
8729 12:47:50.953313 [Byte1]: 64
8730 12:47:50.957830
8731 12:47:50.958251 Set Vref, RX VrefLevel [Byte0]: 65
8732 12:47:50.961121 [Byte1]: 65
8733 12:47:50.965358
8734 12:47:50.965748 Set Vref, RX VrefLevel [Byte0]: 66
8735 12:47:50.968426 [Byte1]: 66
8736 12:47:50.973151
8737 12:47:50.973537 Set Vref, RX VrefLevel [Byte0]: 67
8738 12:47:50.976359 [Byte1]: 67
8739 12:47:50.980934
8740 12:47:50.981324 Set Vref, RX VrefLevel [Byte0]: 68
8741 12:47:50.984128 [Byte1]: 68
8742 12:47:50.988010
8743 12:47:50.988398 Set Vref, RX VrefLevel [Byte0]: 69
8744 12:47:50.991428 [Byte1]: 69
8745 12:47:50.995588
8746 12:47:50.996068 Set Vref, RX VrefLevel [Byte0]: 70
8747 12:47:50.998891 [Byte1]: 70
8748 12:47:51.003671
8749 12:47:51.004053 Set Vref, RX VrefLevel [Byte0]: 71
8750 12:47:51.006668 [Byte1]: 71
8751 12:47:51.010843
8752 12:47:51.011117 Set Vref, RX VrefLevel [Byte0]: 72
8753 12:47:51.014512 [Byte1]: 72
8754 12:47:51.018559
8755 12:47:51.018816 Set Vref, RX VrefLevel [Byte0]: 73
8756 12:47:51.021638 [Byte1]: 73
8757 12:47:51.026404
8758 12:47:51.026606 Set Vref, RX VrefLevel [Byte0]: 74
8759 12:47:51.029440 [Byte1]: 74
8760 12:47:51.033443
8761 12:47:51.033570 Set Vref, RX VrefLevel [Byte0]: 75
8762 12:47:51.037125 [Byte1]: 75
8763 12:47:51.041477
8764 12:47:51.041576 Set Vref, RX VrefLevel [Byte0]: 76
8765 12:47:51.044400 [Byte1]: 76
8766 12:47:51.048583
8767 12:47:51.048678 Set Vref, RX VrefLevel [Byte0]: 77
8768 12:47:51.052212 [Byte1]: 77
8769 12:47:51.056479
8770 12:47:51.056560 Final RX Vref Byte 0 = 52 to rank0
8771 12:47:51.059970 Final RX Vref Byte 1 = 60 to rank0
8772 12:47:51.063242 Final RX Vref Byte 0 = 52 to rank1
8773 12:47:51.066543 Final RX Vref Byte 1 = 60 to rank1==
8774 12:47:51.069660 Dram Type= 6, Freq= 0, CH_1, rank 0
8775 12:47:51.076295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 12:47:51.076382 ==
8777 12:47:51.076448 DQS Delay:
8778 12:47:51.079392 DQS0 = 0, DQS1 = 0
8779 12:47:51.079474 DQM Delay:
8780 12:47:51.079539 DQM0 = 134, DQM1 = 128
8781 12:47:51.082832 DQ Delay:
8782 12:47:51.086333 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8783 12:47:51.089627 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8784 12:47:51.093089 DQ8 =116, DQ9 =114, DQ10 =130, DQ11 =118
8785 12:47:51.095973 DQ12 =136, DQ13 =134, DQ14 =138, DQ15 =138
8786 12:47:51.096057
8787 12:47:51.096124
8788 12:47:51.096183
8789 12:47:51.099631 [DramC_TX_OE_Calibration] TA2
8790 12:47:51.102526 Original DQ_B0 (3 6) =30, OEN = 27
8791 12:47:51.106322 Original DQ_B1 (3 6) =30, OEN = 27
8792 12:47:51.109148 24, 0x0, End_B0=24 End_B1=24
8793 12:47:51.109239 25, 0x0, End_B0=25 End_B1=25
8794 12:47:51.112940 26, 0x0, End_B0=26 End_B1=26
8795 12:47:51.115993 27, 0x0, End_B0=27 End_B1=27
8796 12:47:51.118983 28, 0x0, End_B0=28 End_B1=28
8797 12:47:51.122553 29, 0x0, End_B0=29 End_B1=29
8798 12:47:51.122672 30, 0x0, End_B0=30 End_B1=30
8799 12:47:51.126088 31, 0x4545, End_B0=30 End_B1=30
8800 12:47:51.129127 Byte0 end_step=30 best_step=27
8801 12:47:51.132709 Byte1 end_step=30 best_step=27
8802 12:47:51.135745 Byte0 TX OE(2T, 0.5T) = (3, 3)
8803 12:47:51.138558 Byte1 TX OE(2T, 0.5T) = (3, 3)
8804 12:47:51.138690
8805 12:47:51.138756
8806 12:47:51.145550 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
8807 12:47:51.148812 CH1 RK0: MR19=303, MR18=1A0F
8808 12:47:51.155528 CH1_RK0: MR19=0x303, MR18=0x1A0F, DQSOSC=396, MR23=63, INC=23, DEC=15
8809 12:47:51.155618
8810 12:47:51.158548 ----->DramcWriteLeveling(PI) begin...
8811 12:47:51.158681 ==
8812 12:47:51.161618 Dram Type= 6, Freq= 0, CH_1, rank 1
8813 12:47:51.165229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8814 12:47:51.165319 ==
8815 12:47:51.168572 Write leveling (Byte 0): 23 => 23
8816 12:47:51.171836 Write leveling (Byte 1): 29 => 29
8817 12:47:51.175373 DramcWriteLeveling(PI) end<-----
8818 12:47:51.175456
8819 12:47:51.175530 ==
8820 12:47:51.178387 Dram Type= 6, Freq= 0, CH_1, rank 1
8821 12:47:51.182054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8822 12:47:51.185082 ==
8823 12:47:51.185172 [Gating] SW mode calibration
8824 12:47:51.194738 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8825 12:47:51.198539 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8826 12:47:51.201515 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 12:47:51.208254 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 12:47:51.211635 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8829 12:47:51.214910 1 4 12 | B1->B0 | 3232 2424 | 1 0 | (1 1) (1 1)
8830 12:47:51.221234 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 12:47:51.224733 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 12:47:51.227773 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 12:47:51.234324 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 12:47:51.237934 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 12:47:51.241467 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 12:47:51.247552 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 12:47:51.251007 1 5 12 | B1->B0 | 3333 3434 | 0 0 | (0 1) (0 1)
8838 12:47:51.254662 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 12:47:51.260988 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 12:47:51.264664 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 12:47:51.267701 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 12:47:51.274189 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 12:47:51.277556 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 12:47:51.280906 1 6 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8845 12:47:51.287568 1 6 12 | B1->B0 | 4545 3030 | 0 1 | (0 0) (0 0)
8846 12:47:51.290860 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 12:47:51.293831 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 12:47:51.300860 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 12:47:51.303723 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 12:47:51.307089 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 12:47:51.313592 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 12:47:51.317159 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 12:47:51.320255 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8854 12:47:51.327098 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8855 12:47:51.330525 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 12:47:51.333452 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 12:47:51.340119 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 12:47:51.343710 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 12:47:51.346587 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 12:47:51.353367 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 12:47:51.356978 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 12:47:51.360072 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 12:47:51.366725 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 12:47:51.369973 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 12:47:51.373624 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 12:47:51.380044 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 12:47:51.383186 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8868 12:47:51.386424 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8869 12:47:51.393066 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8870 12:47:51.393156 Total UI for P1: 0, mck2ui 16
8871 12:47:51.399722 best dqsien dly found for B1: ( 1, 9, 6)
8872 12:47:51.403377 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8873 12:47:51.406323 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8874 12:47:51.410048 Total UI for P1: 0, mck2ui 16
8875 12:47:51.413235 best dqsien dly found for B0: ( 1, 9, 12)
8876 12:47:51.416513 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8877 12:47:51.419568 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8878 12:47:51.419734
8879 12:47:51.423146 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8880 12:47:51.429731 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8881 12:47:51.429821 [Gating] SW calibration Done
8882 12:47:51.433331 ==
8883 12:47:51.433415 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 12:47:51.439387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 12:47:51.439481 ==
8886 12:47:51.439548 RX Vref Scan: 0
8887 12:47:51.439608
8888 12:47:51.442668 RX Vref 0 -> 0, step: 1
8889 12:47:51.442751
8890 12:47:51.446044 RX Delay 0 -> 252, step: 8
8891 12:47:51.449660 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8892 12:47:51.452582 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8893 12:47:51.456310 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8894 12:47:51.462352 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8895 12:47:51.465954 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8896 12:47:51.468981 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8897 12:47:51.472713 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8898 12:47:51.475921 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8899 12:47:51.482329 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8900 12:47:51.485970 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8901 12:47:51.488874 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8902 12:47:51.492252 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8903 12:47:51.498997 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8904 12:47:51.502076 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8905 12:47:51.505630 iDelay=208, Bit 14, Center 135 (72 ~ 199) 128
8906 12:47:51.508556 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8907 12:47:51.508641 ==
8908 12:47:51.512177 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 12:47:51.518762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 12:47:51.518850 ==
8911 12:47:51.518916 DQS Delay:
8912 12:47:51.518977 DQS0 = 0, DQS1 = 0
8913 12:47:51.522414 DQM Delay:
8914 12:47:51.522495 DQM0 = 138, DQM1 = 129
8915 12:47:51.525410 DQ Delay:
8916 12:47:51.528530 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =135
8917 12:47:51.532096 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8918 12:47:51.535081 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8919 12:47:51.538542 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8920 12:47:51.538714
8921 12:47:51.538795
8922 12:47:51.538871 ==
8923 12:47:51.541583 Dram Type= 6, Freq= 0, CH_1, rank 1
8924 12:47:51.545167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8925 12:47:51.548357 ==
8926 12:47:51.548442
8927 12:47:51.548506
8928 12:47:51.548567 TX Vref Scan disable
8929 12:47:51.551693 == TX Byte 0 ==
8930 12:47:51.555059 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8931 12:47:51.558379 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8932 12:47:51.561458 == TX Byte 1 ==
8933 12:47:51.564948 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8934 12:47:51.567967 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8935 12:47:51.571690 ==
8936 12:47:51.571776 Dram Type= 6, Freq= 0, CH_1, rank 1
8937 12:47:51.578246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8938 12:47:51.578356 ==
8939 12:47:51.590958
8940 12:47:51.593896 TX Vref early break, caculate TX vref
8941 12:47:51.597526 TX Vref=16, minBit 0, minWin=22, winSum=382
8942 12:47:51.601046 TX Vref=18, minBit 0, minWin=23, winSum=395
8943 12:47:51.604242 TX Vref=20, minBit 0, minWin=24, winSum=404
8944 12:47:51.607002 TX Vref=22, minBit 0, minWin=24, winSum=406
8945 12:47:51.610797 TX Vref=24, minBit 5, minWin=24, winSum=410
8946 12:47:51.617342 TX Vref=26, minBit 0, minWin=25, winSum=418
8947 12:47:51.620576 TX Vref=28, minBit 0, minWin=25, winSum=421
8948 12:47:51.624181 TX Vref=30, minBit 0, minWin=24, winSum=414
8949 12:47:51.627613 TX Vref=32, minBit 0, minWin=23, winSum=406
8950 12:47:51.630895 TX Vref=34, minBit 0, minWin=23, winSum=397
8951 12:47:51.637276 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 28
8952 12:47:51.637700
8953 12:47:51.640331 Final TX Range 0 Vref 28
8954 12:47:51.640754
8955 12:47:51.641088 ==
8956 12:47:51.643943 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 12:47:51.647580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 12:47:51.648216 ==
8959 12:47:51.648570
8960 12:47:51.648921
8961 12:47:51.650577 TX Vref Scan disable
8962 12:47:51.657208 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8963 12:47:51.657636 == TX Byte 0 ==
8964 12:47:51.660474 u2DelayCellOfst[0]=22 cells (6 PI)
8965 12:47:51.663729 u2DelayCellOfst[1]=18 cells (5 PI)
8966 12:47:51.667146 u2DelayCellOfst[2]=0 cells (0 PI)
8967 12:47:51.670494 u2DelayCellOfst[3]=7 cells (2 PI)
8968 12:47:51.673542 u2DelayCellOfst[4]=11 cells (3 PI)
8969 12:47:51.676792 u2DelayCellOfst[5]=22 cells (6 PI)
8970 12:47:51.680257 u2DelayCellOfst[6]=22 cells (6 PI)
8971 12:47:51.683400 u2DelayCellOfst[7]=7 cells (2 PI)
8972 12:47:51.686975 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8973 12:47:51.690018 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8974 12:47:51.693298 == TX Byte 1 ==
8975 12:47:51.696428 u2DelayCellOfst[8]=0 cells (0 PI)
8976 12:47:51.696849 u2DelayCellOfst[9]=3 cells (1 PI)
8977 12:47:51.700017 u2DelayCellOfst[10]=14 cells (4 PI)
8978 12:47:51.703398 u2DelayCellOfst[11]=3 cells (1 PI)
8979 12:47:51.706200 u2DelayCellOfst[12]=18 cells (5 PI)
8980 12:47:51.709649 u2DelayCellOfst[13]=14 cells (4 PI)
8981 12:47:51.713002 u2DelayCellOfst[14]=18 cells (5 PI)
8982 12:47:51.716568 u2DelayCellOfst[15]=18 cells (5 PI)
8983 12:47:51.723422 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8984 12:47:51.726291 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8985 12:47:51.726817 DramC Write-DBI on
8986 12:47:51.727172 ==
8987 12:47:51.729879 Dram Type= 6, Freq= 0, CH_1, rank 1
8988 12:47:51.736676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8989 12:47:51.737111 ==
8990 12:47:51.737453
8991 12:47:51.737767
8992 12:47:51.738073 TX Vref Scan disable
8993 12:47:51.740312 == TX Byte 0 ==
8994 12:47:51.743904 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8995 12:47:51.746814 == TX Byte 1 ==
8996 12:47:51.750386 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8997 12:47:51.753462 DramC Write-DBI off
8998 12:47:51.754015
8999 12:47:51.754496 [DATLAT]
9000 12:47:51.754904 Freq=1600, CH1 RK1
9001 12:47:51.755383
9002 12:47:51.757161 DATLAT Default: 0xf
9003 12:47:51.757578 0, 0xFFFF, sum = 0
9004 12:47:51.760184 1, 0xFFFF, sum = 0
9005 12:47:51.763581 2, 0xFFFF, sum = 0
9006 12:47:51.764007 3, 0xFFFF, sum = 0
9007 12:47:51.766512 4, 0xFFFF, sum = 0
9008 12:47:51.767116 5, 0xFFFF, sum = 0
9009 12:47:51.770339 6, 0xFFFF, sum = 0
9010 12:47:51.770855 7, 0xFFFF, sum = 0
9011 12:47:51.773203 8, 0xFFFF, sum = 0
9012 12:47:51.773697 9, 0xFFFF, sum = 0
9013 12:47:51.776718 10, 0xFFFF, sum = 0
9014 12:47:51.777322 11, 0xFFFF, sum = 0
9015 12:47:51.779847 12, 0xFFFF, sum = 0
9016 12:47:51.780273 13, 0xFFFF, sum = 0
9017 12:47:51.783509 14, 0x0, sum = 1
9018 12:47:51.783935 15, 0x0, sum = 2
9019 12:47:51.786427 16, 0x0, sum = 3
9020 12:47:51.786902 17, 0x0, sum = 4
9021 12:47:51.790086 best_step = 15
9022 12:47:51.790506
9023 12:47:51.790894 ==
9024 12:47:51.793103 Dram Type= 6, Freq= 0, CH_1, rank 1
9025 12:47:51.796634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9026 12:47:51.797097 ==
9027 12:47:51.799692 RX Vref Scan: 0
9028 12:47:51.800111
9029 12:47:51.800442 RX Vref 0 -> 0, step: 1
9030 12:47:51.800752
9031 12:47:51.802866 RX Delay 11 -> 252, step: 4
9032 12:47:51.809623 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9033 12:47:51.813225 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9034 12:47:51.816411 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9035 12:47:51.819934 iDelay=203, Bit 3, Center 132 (83 ~ 182) 100
9036 12:47:51.822792 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9037 12:47:51.829438 iDelay=203, Bit 5, Center 146 (95 ~ 198) 104
9038 12:47:51.833042 iDelay=203, Bit 6, Center 148 (95 ~ 202) 108
9039 12:47:51.836052 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9040 12:47:51.839815 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9041 12:47:51.842727 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9042 12:47:51.849389 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9043 12:47:51.852551 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9044 12:47:51.856126 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9045 12:47:51.859068 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9046 12:47:51.865644 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9047 12:47:51.869338 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9048 12:47:51.869768 ==
9049 12:47:51.872417 Dram Type= 6, Freq= 0, CH_1, rank 1
9050 12:47:51.875963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9051 12:47:51.876516 ==
9052 12:47:51.878820 DQS Delay:
9053 12:47:51.879201 DQS0 = 0, DQS1 = 0
9054 12:47:51.879561 DQM Delay:
9055 12:47:51.882080 DQM0 = 134, DQM1 = 126
9056 12:47:51.882498 DQ Delay:
9057 12:47:51.885571 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =132
9058 12:47:51.889076 DQ4 =134, DQ5 =146, DQ6 =148, DQ7 =130
9059 12:47:51.891989 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9060 12:47:51.898687 DQ12 =136, DQ13 =134, DQ14 =134, DQ15 =138
9061 12:47:51.899137
9062 12:47:51.899476
9063 12:47:51.899792
9064 12:47:51.902213 [DramC_TX_OE_Calibration] TA2
9065 12:47:51.905115 Original DQ_B0 (3 6) =30, OEN = 27
9066 12:47:51.905544 Original DQ_B1 (3 6) =30, OEN = 27
9067 12:47:51.908679 24, 0x0, End_B0=24 End_B1=24
9068 12:47:51.911951 25, 0x0, End_B0=25 End_B1=25
9069 12:47:51.915203 26, 0x0, End_B0=26 End_B1=26
9070 12:47:51.918373 27, 0x0, End_B0=27 End_B1=27
9071 12:47:51.918933 28, 0x0, End_B0=28 End_B1=28
9072 12:47:51.921719 29, 0x0, End_B0=29 End_B1=29
9073 12:47:51.925063 30, 0x0, End_B0=30 End_B1=30
9074 12:47:51.928172 31, 0x4545, End_B0=30 End_B1=30
9075 12:47:51.931923 Byte0 end_step=30 best_step=27
9076 12:47:51.934853 Byte1 end_step=30 best_step=27
9077 12:47:51.935279 Byte0 TX OE(2T, 0.5T) = (3, 3)
9078 12:47:51.938442 Byte1 TX OE(2T, 0.5T) = (3, 3)
9079 12:47:51.938969
9080 12:47:51.939309
9081 12:47:51.948181 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
9082 12:47:51.948609 CH1 RK1: MR19=303, MR18=E0A
9083 12:47:51.955158 CH1_RK1: MR19=0x303, MR18=0xE0A, DQSOSC=402, MR23=63, INC=22, DEC=15
9084 12:47:51.958397 [RxdqsGatingPostProcess] freq 1600
9085 12:47:51.965041 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9086 12:47:51.968062 best DQS0 dly(2T, 0.5T) = (1, 1)
9087 12:47:51.971870 best DQS1 dly(2T, 0.5T) = (1, 1)
9088 12:47:51.974942 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9089 12:47:51.977825 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9090 12:47:51.978247 best DQS0 dly(2T, 0.5T) = (1, 1)
9091 12:47:51.981388 best DQS1 dly(2T, 0.5T) = (1, 1)
9092 12:47:51.984757 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9093 12:47:51.988088 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9094 12:47:51.991679 Pre-setting of DQS Precalculation
9095 12:47:51.997941 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9096 12:47:52.004498 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9097 12:47:52.011167 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9098 12:47:52.011590
9099 12:47:52.011921
9100 12:47:52.014369 [Calibration Summary] 3200 Mbps
9101 12:47:52.014823 CH 0, Rank 0
9102 12:47:52.017829 SW Impedance : PASS
9103 12:47:52.020868 DUTY Scan : NO K
9104 12:47:52.021351 ZQ Calibration : PASS
9105 12:47:52.023949 Jitter Meter : NO K
9106 12:47:52.027731 CBT Training : PASS
9107 12:47:52.028149 Write leveling : PASS
9108 12:47:52.030712 RX DQS gating : PASS
9109 12:47:52.034023 RX DQ/DQS(RDDQC) : PASS
9110 12:47:52.034441 TX DQ/DQS : PASS
9111 12:47:52.037269 RX DATLAT : PASS
9112 12:47:52.040922 RX DQ/DQS(Engine): PASS
9113 12:47:52.041341 TX OE : PASS
9114 12:47:52.043958 All Pass.
9115 12:47:52.044377
9116 12:47:52.044709 CH 0, Rank 1
9117 12:47:52.047102 SW Impedance : PASS
9118 12:47:52.047520 DUTY Scan : NO K
9119 12:47:52.050273 ZQ Calibration : PASS
9120 12:47:52.053986 Jitter Meter : NO K
9121 12:47:52.054538 CBT Training : PASS
9122 12:47:52.057133 Write leveling : PASS
9123 12:47:52.060726 RX DQS gating : PASS
9124 12:47:52.061411 RX DQ/DQS(RDDQC) : PASS
9125 12:47:52.063410 TX DQ/DQS : PASS
9126 12:47:52.066689 RX DATLAT : PASS
9127 12:47:52.067209 RX DQ/DQS(Engine): PASS
9128 12:47:52.070218 TX OE : PASS
9129 12:47:52.070679 All Pass.
9130 12:47:52.071020
9131 12:47:52.073653 CH 1, Rank 0
9132 12:47:52.074071 SW Impedance : PASS
9133 12:47:52.076791 DUTY Scan : NO K
9134 12:47:52.080335 ZQ Calibration : PASS
9135 12:47:52.080753 Jitter Meter : NO K
9136 12:47:52.083412 CBT Training : PASS
9137 12:47:52.086439 Write leveling : PASS
9138 12:47:52.086939 RX DQS gating : PASS
9139 12:47:52.090136 RX DQ/DQS(RDDQC) : PASS
9140 12:47:52.090636 TX DQ/DQS : PASS
9141 12:47:52.093252 RX DATLAT : PASS
9142 12:47:52.096684 RX DQ/DQS(Engine): PASS
9143 12:47:52.097265 TX OE : PASS
9144 12:47:52.099804 All Pass.
9145 12:47:52.100235
9146 12:47:52.100572 CH 1, Rank 1
9147 12:47:52.103136 SW Impedance : PASS
9148 12:47:52.103571 DUTY Scan : NO K
9149 12:47:52.106749 ZQ Calibration : PASS
9150 12:47:52.109741 Jitter Meter : NO K
9151 12:47:52.110176 CBT Training : PASS
9152 12:47:52.113430 Write leveling : PASS
9153 12:47:52.116529 RX DQS gating : PASS
9154 12:47:52.116998 RX DQ/DQS(RDDQC) : PASS
9155 12:47:52.119887 TX DQ/DQS : PASS
9156 12:47:52.122714 RX DATLAT : PASS
9157 12:47:52.123014 RX DQ/DQS(Engine): PASS
9158 12:47:52.126419 TX OE : PASS
9159 12:47:52.126753 All Pass.
9160 12:47:52.126997
9161 12:47:52.129764 DramC Write-DBI on
9162 12:47:52.132529 PER_BANK_REFRESH: Hybrid Mode
9163 12:47:52.132828 TX_TRACKING: ON
9164 12:47:52.142610 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9165 12:47:52.149229 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9166 12:47:52.155893 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9167 12:47:52.162619 [FAST_K] Save calibration result to emmc
9168 12:47:52.163064 sync common calibartion params.
9169 12:47:52.166195 sync cbt_mode0:1, 1:1
9170 12:47:52.169252 dram_init: ddr_geometry: 2
9171 12:47:52.169673 dram_init: ddr_geometry: 2
9172 12:47:52.172834 dram_init: ddr_geometry: 2
9173 12:47:52.175563 0:dram_rank_size:100000000
9174 12:47:52.179385 1:dram_rank_size:100000000
9175 12:47:52.182332 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9176 12:47:52.185911 DFS_SHUFFLE_HW_MODE: ON
9177 12:47:52.188787 dramc_set_vcore_voltage set vcore to 725000
9178 12:47:52.192541 Read voltage for 1600, 0
9179 12:47:52.192963 Vio18 = 0
9180 12:47:52.195373 Vcore = 725000
9181 12:47:52.195798 Vdram = 0
9182 12:47:52.196142 Vddq = 0
9183 12:47:52.196661 Vmddr = 0
9184 12:47:52.199040 switch to 3200 Mbps bootup
9185 12:47:52.202505 [DramcRunTimeConfig]
9186 12:47:52.203045 PHYPLL
9187 12:47:52.205541 DPM_CONTROL_AFTERK: ON
9188 12:47:52.205962 PER_BANK_REFRESH: ON
9189 12:47:52.209297 REFRESH_OVERHEAD_REDUCTION: ON
9190 12:47:52.211976 CMD_PICG_NEW_MODE: OFF
9191 12:47:52.212394 XRTWTW_NEW_MODE: ON
9192 12:47:52.215329 XRTRTR_NEW_MODE: ON
9193 12:47:52.215927 TX_TRACKING: ON
9194 12:47:52.218679 RDSEL_TRACKING: OFF
9195 12:47:52.219129 DQS Precalculation for DVFS: ON
9196 12:47:52.222158 RX_TRACKING: OFF
9197 12:47:52.222579 HW_GATING DBG: ON
9198 12:47:52.225751 ZQCS_ENABLE_LP4: ON
9199 12:47:52.228720 RX_PICG_NEW_MODE: ON
9200 12:47:52.229144 TX_PICG_NEW_MODE: ON
9201 12:47:52.232392 ENABLE_RX_DCM_DPHY: ON
9202 12:47:52.235341 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9203 12:47:52.235758 DUMMY_READ_FOR_TRACKING: OFF
9204 12:47:52.238837 !!! SPM_CONTROL_AFTERK: OFF
9205 12:47:52.242231 !!! SPM could not control APHY
9206 12:47:52.245867 IMPEDANCE_TRACKING: ON
9207 12:47:52.246282 TEMP_SENSOR: ON
9208 12:47:52.248639 HW_SAVE_FOR_SR: OFF
9209 12:47:52.251938 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9210 12:47:52.255280 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9211 12:47:52.255716 Read ODT Tracking: ON
9212 12:47:52.258956 Refresh Rate DeBounce: ON
9213 12:47:52.261817 DFS_NO_QUEUE_FLUSH: ON
9214 12:47:52.264908 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9215 12:47:52.265348 ENABLE_DFS_RUNTIME_MRW: OFF
9216 12:47:52.268529 DDR_RESERVE_NEW_MODE: ON
9217 12:47:52.271494 MR_CBT_SWITCH_FREQ: ON
9218 12:47:52.271931 =========================
9219 12:47:52.292082 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9220 12:47:52.295090 dram_init: ddr_geometry: 2
9221 12:47:52.313459 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9222 12:47:52.316365 dram_init: dram init end (result: 0)
9223 12:47:52.323138 DRAM-K: Full calibration passed in 24691 msecs
9224 12:47:52.326655 MRC: failed to locate region type 0.
9225 12:47:52.327095 DRAM rank0 size:0x100000000,
9226 12:47:52.330048 DRAM rank1 size=0x100000000
9227 12:47:52.339727 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9228 12:47:52.346467 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9229 12:47:52.352906 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9230 12:47:52.359674 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9231 12:47:52.363107 DRAM rank0 size:0x100000000,
9232 12:47:52.366712 DRAM rank1 size=0x100000000
9233 12:47:52.367139 CBMEM:
9234 12:47:52.369719 IMD: root @ 0xfffff000 254 entries.
9235 12:47:52.373153 IMD: root @ 0xffffec00 62 entries.
9236 12:47:52.376036 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9237 12:47:52.382721 WARNING: RO_VPD is uninitialized or empty.
9238 12:47:52.385781 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9239 12:47:52.393301 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9240 12:47:52.405982 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9241 12:47:52.417430 BS: romstage times (exec / console): total (unknown) / 24171 ms
9242 12:47:52.417883
9243 12:47:52.418219
9244 12:47:52.427590 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9245 12:47:52.430892 ARM64: Exception handlers installed.
9246 12:47:52.434210 ARM64: Testing exception
9247 12:47:52.437433 ARM64: Done test exception
9248 12:47:52.437858 Enumerating buses...
9249 12:47:52.440293 Show all devs... Before device enumeration.
9250 12:47:52.443841 Root Device: enabled 1
9251 12:47:52.447412 CPU_CLUSTER: 0: enabled 1
9252 12:47:52.447835 CPU: 00: enabled 1
9253 12:47:52.450283 Compare with tree...
9254 12:47:52.450764 Root Device: enabled 1
9255 12:47:52.453841 CPU_CLUSTER: 0: enabled 1
9256 12:47:52.456800 CPU: 00: enabled 1
9257 12:47:52.457221 Root Device scanning...
9258 12:47:52.459921 scan_static_bus for Root Device
9259 12:47:52.463268 CPU_CLUSTER: 0 enabled
9260 12:47:52.466548 scan_static_bus for Root Device done
9261 12:47:52.469848 scan_bus: bus Root Device finished in 8 msecs
9262 12:47:52.470271 done
9263 12:47:52.476763 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9264 12:47:52.479692 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9265 12:47:52.486271 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9266 12:47:52.492982 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9267 12:47:52.493408 Allocating resources...
9268 12:47:52.496566 Reading resources...
9269 12:47:52.499695 Root Device read_resources bus 0 link: 0
9270 12:47:52.502985 DRAM rank0 size:0x100000000,
9271 12:47:52.503466 DRAM rank1 size=0x100000000
9272 12:47:52.509707 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9273 12:47:52.510130 CPU: 00 missing read_resources
9274 12:47:52.516460 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9275 12:47:52.519368 Root Device read_resources bus 0 link: 0 done
9276 12:47:52.522993 Done reading resources.
9277 12:47:52.526147 Show resources in subtree (Root Device)...After reading.
9278 12:47:52.529340 Root Device child on link 0 CPU_CLUSTER: 0
9279 12:47:52.532653 CPU_CLUSTER: 0 child on link 0 CPU: 00
9280 12:47:52.543011 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9281 12:47:52.543490 CPU: 00
9282 12:47:52.549123 Root Device assign_resources, bus 0 link: 0
9283 12:47:52.552748 CPU_CLUSTER: 0 missing set_resources
9284 12:47:52.555666 Root Device assign_resources, bus 0 link: 0 done
9285 12:47:52.556086 Done setting resources.
9286 12:47:52.562254 Show resources in subtree (Root Device)...After assigning values.
9287 12:47:52.565722 Root Device child on link 0 CPU_CLUSTER: 0
9288 12:47:52.572350 CPU_CLUSTER: 0 child on link 0 CPU: 00
9289 12:47:52.578921 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9290 12:47:52.579480 CPU: 00
9291 12:47:52.582031 Done allocating resources.
9292 12:47:52.588654 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9293 12:47:52.589189 Enabling resources...
9294 12:47:52.592216 done.
9295 12:47:52.595274 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9296 12:47:52.598922 Initializing devices...
9297 12:47:52.599341 Root Device init
9298 12:47:52.602145 init hardware done!
9299 12:47:52.602568 0x00000018: ctrlr->caps
9300 12:47:52.605666 52.000 MHz: ctrlr->f_max
9301 12:47:52.608580 0.400 MHz: ctrlr->f_min
9302 12:47:52.609010 0x40ff8080: ctrlr->voltages
9303 12:47:52.611984 sclk: 390625
9304 12:47:52.612425 Bus Width = 1
9305 12:47:52.615396 sclk: 390625
9306 12:47:52.615825 Bus Width = 1
9307 12:47:52.618548 Early init status = 3
9308 12:47:52.622240 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9309 12:47:52.628913 in-header: 03 fc 00 00 01 00 00 00
9310 12:47:52.629336 in-data: 00
9311 12:47:52.632272 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9312 12:47:52.636809 in-header: 03 fd 00 00 00 00 00 00
9313 12:47:52.640254 in-data:
9314 12:47:52.643490 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9315 12:47:52.647095 in-header: 03 fc 00 00 01 00 00 00
9316 12:47:52.649982 in-data: 00
9317 12:47:52.653544 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9318 12:47:52.660422 in-header: 03 fd 00 00 00 00 00 00
9319 12:47:52.663981 in-data:
9320 12:47:52.667022 [SSUSB] Setting up USB HOST controller...
9321 12:47:52.670567 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9322 12:47:52.674029 [SSUSB] phy power-on done.
9323 12:47:52.677155 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9324 12:47:52.683642 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9325 12:47:52.687484 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9326 12:47:52.693942 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9327 12:47:52.700142 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9328 12:47:52.706874 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9329 12:47:52.713547 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9330 12:47:52.720205 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9331 12:47:52.723077 SPM: binary array size = 0x9dc
9332 12:47:52.726409 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9333 12:47:52.733025 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9334 12:47:52.740032 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9335 12:47:52.746542 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9336 12:47:52.749708 configure_display: Starting display init
9337 12:47:52.783751 anx7625_power_on_init: Init interface.
9338 12:47:52.787052 anx7625_disable_pd_protocol: Disabled PD feature.
9339 12:47:52.790240 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9340 12:47:52.818325 anx7625_start_dp_work: Secure OCM version=00
9341 12:47:52.821544 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9342 12:47:52.836317 sp_tx_get_edid_block: EDID Block = 1
9343 12:47:52.938669 Extracted contents:
9344 12:47:52.942063 header: 00 ff ff ff ff ff ff 00
9345 12:47:52.945406 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9346 12:47:52.948735 version: 01 04
9347 12:47:52.952216 basic params: 95 1f 11 78 0a
9348 12:47:52.955237 chroma info: 76 90 94 55 54 90 27 21 50 54
9349 12:47:52.959202 established: 00 00 00
9350 12:47:52.965195 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9351 12:47:52.968383 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9352 12:47:52.975501 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9353 12:47:52.981916 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9354 12:47:52.988484 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9355 12:47:52.991482 extensions: 00
9356 12:47:52.991904 checksum: fb
9357 12:47:52.992240
9358 12:47:52.995220 Manufacturer: IVO Model 57d Serial Number 0
9359 12:47:52.998261 Made week 0 of 2020
9360 12:47:53.001534 EDID version: 1.4
9361 12:47:53.001958 Digital display
9362 12:47:53.004936 6 bits per primary color channel
9363 12:47:53.005371 DisplayPort interface
9364 12:47:53.008271 Maximum image size: 31 cm x 17 cm
9365 12:47:53.011519 Gamma: 220%
9366 12:47:53.012094 Check DPMS levels
9367 12:47:53.015075 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9368 12:47:53.021655 First detailed timing is preferred timing
9369 12:47:53.022253 Established timings supported:
9370 12:47:53.024898 Standard timings supported:
9371 12:47:53.028507 Detailed timings
9372 12:47:53.031497 Hex of detail: 383680a07038204018303c0035ae10000019
9373 12:47:53.038148 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9374 12:47:53.041208 0780 0798 07c8 0820 hborder 0
9375 12:47:53.044709 0438 043b 0447 0458 vborder 0
9376 12:47:53.047865 -hsync -vsync
9377 12:47:53.048283 Did detailed timing
9378 12:47:53.054225 Hex of detail: 000000000000000000000000000000000000
9379 12:47:53.057679 Manufacturer-specified data, tag 0
9380 12:47:53.061438 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9381 12:47:53.064510 ASCII string: InfoVision
9382 12:47:53.067935 Hex of detail: 000000fe00523134304e574635205248200a
9383 12:47:53.070959 ASCII string: R140NWF5 RH
9384 12:47:53.071521 Checksum
9385 12:47:53.074636 Checksum: 0xfb (valid)
9386 12:47:53.077988 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9387 12:47:53.081265 DSI data_rate: 832800000 bps
9388 12:47:53.087973 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9389 12:47:53.090799 anx7625_parse_edid: pixelclock(138800).
9390 12:47:53.094477 hactive(1920), hsync(48), hfp(24), hbp(88)
9391 12:47:53.097423 vactive(1080), vsync(12), vfp(3), vbp(17)
9392 12:47:53.101166 anx7625_dsi_config: config dsi.
9393 12:47:53.107994 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9394 12:47:53.120592 anx7625_dsi_config: success to config DSI
9395 12:47:53.124041 anx7625_dp_start: MIPI phy setup OK.
9396 12:47:53.127725 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9397 12:47:53.131023 mtk_ddp_mode_set invalid vrefresh 60
9398 12:47:53.133960 main_disp_path_setup
9399 12:47:53.134416 ovl_layer_smi_id_en
9400 12:47:53.137721 ovl_layer_smi_id_en
9401 12:47:53.138237 ccorr_config
9402 12:47:53.138583 aal_config
9403 12:47:53.140872 gamma_config
9404 12:47:53.141297 postmask_config
9405 12:47:53.143853 dither_config
9406 12:47:53.147535 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9407 12:47:53.154004 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9408 12:47:53.157667 Root Device init finished in 554 msecs
9409 12:47:53.160795 CPU_CLUSTER: 0 init
9410 12:47:53.167257 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9411 12:47:53.173826 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9412 12:47:53.174256 APU_MBOX 0x190000b0 = 0x10001
9413 12:47:53.176906 APU_MBOX 0x190001b0 = 0x10001
9414 12:47:53.180406 APU_MBOX 0x190005b0 = 0x10001
9415 12:47:53.183810 APU_MBOX 0x190006b0 = 0x10001
9416 12:47:53.190258 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9417 12:47:53.199994 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9418 12:47:53.212503 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9419 12:47:53.218904 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9420 12:47:53.230588 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9421 12:47:53.239412 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9422 12:47:53.243129 CPU_CLUSTER: 0 init finished in 81 msecs
9423 12:47:53.246664 Devices initialized
9424 12:47:53.249677 Show all devs... After init.
9425 12:47:53.250104 Root Device: enabled 1
9426 12:47:53.253300 CPU_CLUSTER: 0: enabled 1
9427 12:47:53.256259 CPU: 00: enabled 1
9428 12:47:53.259763 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9429 12:47:53.262796 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9430 12:47:53.266225 ELOG: NV offset 0x57f000 size 0x1000
9431 12:47:53.272986 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9432 12:47:53.279657 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9433 12:47:53.282689 ELOG: Event(17) added with size 13 at 2023-07-20 12:47:56 UTC
9434 12:47:53.289403 out: cmd=0x121: 03 db 21 01 00 00 00 00
9435 12:47:53.292438 in-header: 03 80 00 00 2c 00 00 00
9436 12:47:53.302462 in-data: df 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9437 12:47:53.308960 ELOG: Event(A1) added with size 10 at 2023-07-20 12:47:56 UTC
9438 12:47:53.315606 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9439 12:47:53.322128 ELOG: Event(A0) added with size 9 at 2023-07-20 12:47:56 UTC
9440 12:47:53.325663 elog_add_boot_reason: Logged dev mode boot
9441 12:47:53.332035 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9442 12:47:53.332465 Finalize devices...
9443 12:47:53.335808 Devices finalized
9444 12:47:53.338801 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9445 12:47:53.342547 Writing coreboot table at 0xffe64000
9446 12:47:53.345909 0. 000000000010a000-0000000000113fff: RAMSTAGE
9447 12:47:53.349051 1. 0000000040000000-00000000400fffff: RAM
9448 12:47:53.355662 2. 0000000040100000-000000004032afff: RAMSTAGE
9449 12:47:53.358952 3. 000000004032b000-00000000545fffff: RAM
9450 12:47:53.362341 4. 0000000054600000-000000005465ffff: BL31
9451 12:47:53.365757 5. 0000000054660000-00000000ffe63fff: RAM
9452 12:47:53.372240 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9453 12:47:53.375305 7. 0000000100000000-000000023fffffff: RAM
9454 12:47:53.378736 Passing 5 GPIOs to payload:
9455 12:47:53.381908 NAME | PORT | POLARITY | VALUE
9456 12:47:53.389022 EC in RW | 0x000000aa | low | undefined
9457 12:47:53.391824 EC interrupt | 0x00000005 | low | undefined
9458 12:47:53.395425 TPM interrupt | 0x000000ab | high | undefined
9459 12:47:53.402008 SD card detect | 0x00000011 | high | undefined
9460 12:47:53.404892 speaker enable | 0x00000093 | high | undefined
9461 12:47:53.408707 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9462 12:47:53.412285 in-header: 03 f9 00 00 02 00 00 00
9463 12:47:53.415110 in-data: 02 00
9464 12:47:53.418262 ADC[4]: Raw value=904509 ID=7
9465 12:47:53.418732 ADC[3]: Raw value=213652 ID=1
9466 12:47:53.421474 RAM Code: 0x71
9467 12:47:53.425081 ADC[6]: Raw value=74667 ID=0
9468 12:47:53.425522 ADC[5]: Raw value=212543 ID=1
9469 12:47:53.428351 SKU Code: 0x1
9470 12:47:53.431413 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a12d
9471 12:47:53.435026 coreboot table: 964 bytes.
9472 12:47:53.438530 IMD ROOT 0. 0xfffff000 0x00001000
9473 12:47:53.441814 IMD SMALL 1. 0xffffe000 0x00001000
9474 12:47:53.444998 RO MCACHE 2. 0xffffc000 0x00001104
9475 12:47:53.448603 CONSOLE 3. 0xfff7c000 0x00080000
9476 12:47:53.451461 FMAP 4. 0xfff7b000 0x00000452
9477 12:47:53.454823 TIME STAMP 5. 0xfff7a000 0x00000910
9478 12:47:53.457946 VBOOT WORK 6. 0xfff66000 0x00014000
9479 12:47:53.461634 RAMOOPS 7. 0xffe66000 0x00100000
9480 12:47:53.464674 COREBOOT 8. 0xffe64000 0x00002000
9481 12:47:53.467682 IMD small region:
9482 12:47:53.471061 IMD ROOT 0. 0xffffec00 0x00000400
9483 12:47:53.474774 VPD 1. 0xffffeba0 0x0000004c
9484 12:47:53.477727 MMC STATUS 2. 0xffffeb80 0x00000004
9485 12:47:53.481410 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9486 12:47:53.484431 Probing TPM: done!
9487 12:47:53.487856 Connected to device vid:did:rid of 1ae0:0028:00
9488 12:47:53.498257 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9489 12:47:53.501885 Initialized TPM device CR50 revision 0
9490 12:47:53.505572 Checking cr50 for pending updates
9491 12:47:53.509127 Reading cr50 TPM mode
9492 12:47:53.517682 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9493 12:47:53.524239 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9494 12:47:56.204669 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9495 12:47:56.205945 Checking segment from ROM address 0x40100000
9496 12:47:56.206648 Checking segment from ROM address 0x4010001c
9497 12:47:56.207195 Loading segment from ROM address 0x40100000
9498 12:47:56.207714 code (compression=0)
9499 12:47:56.208201 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9500 12:47:56.208678 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9501 12:47:56.209134 it's not compressed!
9502 12:47:56.209588 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9503 12:47:56.209781 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9504 12:47:56.209899 Loading segment from ROM address 0x4010001c
9505 12:47:56.210000 Entry Point 0x80000000
9506 12:47:56.210129 Loaded segments
9507 12:47:56.210243 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9508 12:47:56.210333 Jumping to boot code at 0x80000000(0xffe64000)
9509 12:47:56.210421 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9510 12:47:56.210508 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9511 12:47:56.210601 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9512 12:47:56.210689 Checking segment from ROM address 0x40100000
9513 12:47:56.210775 Checking segment from ROM address 0x4010001c
9514 12:47:56.210864 Loading segment from ROM address 0x40100000
9515 12:47:56.210949 code (compression=1)
9516 12:47:56.211034 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9517 12:47:56.211121 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9518 12:47:56.211206 using LZMA
9519 12:47:56.211291 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9520 12:47:56.211380 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9521 12:47:56.211466 Loading segment from ROM address 0x4010001c
9522 12:47:56.211551 Entry Point 0x54601000
9523 12:47:56.211634 Loaded segments
9524 12:47:56.211718 NOTICE: MT8192 bl31_setup
9525 12:47:56.211804 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9526 12:47:56.211894 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9527 12:47:56.211979 WARNING: region 0:
9528 12:47:56.212064 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9529 12:47:56.212149 WARNING: region 1:
9530 12:47:56.212234 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9531 12:47:56.212318 WARNING: region 2:
9532 12:47:56.212406 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9533 12:47:56.212491 WARNING: region 3:
9534 12:47:56.212576 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9535 12:47:56.212660 WARNING: region 4:
9536 12:47:56.212745 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9537 12:47:56.212829 WARNING: region 5:
9538 12:47:56.212916 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9539 12:47:56.213001 WARNING: region 6:
9540 12:47:56.213086 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9541 12:47:56.213170 WARNING: region 7:
9542 12:47:56.213254 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9543 12:47:56.213339 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9544 12:47:56.213427 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9545 12:47:56.213513 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9546 12:47:56.213598 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9547 12:47:56.213684 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9548 12:47:56.213769 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9549 12:47:56.213854 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9550 12:47:56.213942 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9551 12:47:56.214028 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9552 12:47:56.214113 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9553 12:47:56.214198 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9554 12:47:56.214283 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9555 12:47:56.214368 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9556 12:47:56.214458 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9557 12:47:56.214562 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9558 12:47:56.214659 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9559 12:47:56.214745 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9560 12:47:56.214830 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9561 12:47:56.214916 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9562 12:47:56.215004 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9563 12:47:56.215090 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9564 12:47:56.215175 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9565 12:47:56.215260 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9566 12:47:56.215345 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9567 12:47:56.215430 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9568 12:47:56.215516 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9569 12:47:56.215603 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9570 12:47:56.215688 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9571 12:47:56.215773 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9572 12:47:56.215857 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9573 12:47:56.215942 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9574 12:47:56.216026 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9575 12:47:56.216115 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9576 12:47:56.216200 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9577 12:47:56.216285 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9578 12:47:56.216369 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9579 12:47:56.216649 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9580 12:47:56.216743 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9581 12:47:56.216830 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9582 12:47:56.216916 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9583 12:47:56.217001 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9584 12:47:56.217087 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9585 12:47:56.217175 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9586 12:47:56.217260 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9587 12:47:56.217345 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9588 12:47:56.217430 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9589 12:47:56.217515 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9590 12:47:56.217600 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9591 12:47:56.217688 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9592 12:47:56.217773 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9593 12:47:56.217858 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9594 12:47:56.217943 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9595 12:47:56.218028 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9596 12:47:56.218113 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9597 12:47:56.218201 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9598 12:47:56.218297 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9599 12:47:56.218391 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9600 12:47:56.218481 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9601 12:47:56.218567 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9602 12:47:56.218665 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9603 12:47:56.218752 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9604 12:47:56.218837 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9605 12:47:56.218922 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9606 12:47:56.219007 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9607 12:47:56.219092 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9608 12:47:56.219180 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9609 12:47:56.219267 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9610 12:47:56.219352 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9611 12:47:56.219437 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9612 12:47:56.219522 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9613 12:47:56.219607 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9614 12:47:56.219694 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9615 12:47:56.219780 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9616 12:47:56.219865 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9617 12:47:56.219950 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9618 12:47:56.220037 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9619 12:47:56.220124 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9620 12:47:56.220209 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9621 12:47:56.220297 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9622 12:47:56.220382 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9623 12:47:56.220467 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9624 12:47:56.220552 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9625 12:47:56.220637 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9626 12:47:56.220721 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9627 12:47:56.220810 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9628 12:47:56.220895 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9629 12:47:56.220980 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9630 12:47:56.221068 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9631 12:47:56.221153 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9632 12:47:56.221242 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9633 12:47:56.221330 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9634 12:47:56.221416 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9635 12:47:56.221501 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9636 12:47:56.221586 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9637 12:47:56.221671 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9638 12:47:56.221756 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9639 12:47:56.221844 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9640 12:47:56.221929 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9641 12:47:56.222014 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9642 12:47:56.222099 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9643 12:47:56.222184 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9644 12:47:56.222269 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9645 12:47:56.222357 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9646 12:47:56.222450 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9647 12:47:56.222536 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9648 12:47:56.222628 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9649 12:47:56.222714 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9650 12:47:56.222799 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9651 12:47:56.222888 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9652 12:47:56.222973 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9653 12:47:56.223058 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9654 12:47:56.223143 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9655 12:47:56.223421 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9656 12:47:56.223514 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9657 12:47:56.223600 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9658 12:47:56.223686 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9659 12:47:56.223773 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9660 12:47:56.223859 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9661 12:47:56.223950 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9662 12:47:56.224037 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9663 12:47:56.224122 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9664 12:47:56.224207 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9665 12:47:56.224294 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9666 12:47:56.224382 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9667 12:47:56.224471 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9668 12:47:56.224556 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9669 12:47:56.224641 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9670 12:47:56.224728 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9671 12:47:56.224816 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9672 12:47:56.224905 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9673 12:47:56.224993 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9674 12:47:56.225079 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9675 12:47:56.225164 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9676 12:47:56.225251 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9677 12:47:56.225336 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9678 12:47:56.225421 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9679 12:47:56.225506 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9680 12:47:56.225591 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9681 12:47:56.225676 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9682 12:47:56.225761 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9683 12:47:56.225845 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9684 12:47:56.225930 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9685 12:47:56.226015 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9686 12:47:56.226101 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9687 12:47:56.226188 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9688 12:47:56.226273 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9689 12:47:56.226358 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9690 12:47:56.226443 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9691 12:47:56.226528 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9692 12:47:56.226620 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9693 12:47:56.226709 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9694 12:47:56.226795 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9695 12:47:56.226880 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9696 12:47:56.226965 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9697 12:47:56.227050 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9698 12:47:56.227135 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9699 12:47:56.227223 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9700 12:47:56.227309 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9701 12:47:56.227399 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9702 12:47:56.227487 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9703 12:47:56.227572 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9704 12:47:56.227657 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9705 12:47:56.227745 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9706 12:47:56.227830 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9707 12:47:56.227914 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9708 12:47:56.228001 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9709 12:47:56.228087 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9710 12:47:56.228177 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9711 12:47:56.228275 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9712 12:47:56.228363 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9713 12:47:56.228448 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9714 12:47:56.228538 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9715 12:47:56.228626 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9716 12:47:56.228713 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9717 12:47:56.228809 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9718 12:47:56.228914 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9719 12:47:56.229004 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9720 12:47:56.229091 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9721 12:47:56.229176 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9722 12:47:56.229260 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9723 12:47:56.229357 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9724 12:47:56.229443 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9725 12:47:56.229528 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9726 12:47:56.229626 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9727 12:47:56.229709 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9728 12:47:56.229807 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9729 12:47:56.229904 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9730 12:47:56.229989 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9731 12:47:56.230075 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9732 12:47:56.230400 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9733 12:47:56.230508 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9734 12:47:56.230646 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9735 12:47:56.230729 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9736 12:47:56.230828 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9737 12:47:56.230926 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9738 12:47:56.231023 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9739 12:47:56.231119 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9740 12:47:56.231237 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9741 12:47:56.231345 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9742 12:47:56.231470 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9743 12:47:56.231564 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9744 12:47:56.231689 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9745 12:47:56.231782 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9746 12:47:56.231905 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9747 12:47:56.232061 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9748 12:47:56.232154 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9749 12:47:56.232274 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9750 12:47:56.232395 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9751 12:47:56.232516 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9752 12:47:56.232609 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9753 12:47:56.232731 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9754 12:47:56.232851 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9755 12:47:56.232987 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9756 12:47:56.233110 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9757 12:47:56.233206 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9758 12:47:56.233301 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9759 12:47:56.233395 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9760 12:47:56.233490 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9761 12:47:56.233584 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9762 12:47:56.233679 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9763 12:47:56.233773 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9764 12:47:56.233867 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9765 12:47:56.233961 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9766 12:47:56.234055 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9767 12:47:56.234149 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9768 12:47:56.234243 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9769 12:47:56.234337 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9770 12:47:56.234433 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9771 12:47:56.234528 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9772 12:47:56.234644 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9773 12:47:56.234738 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9774 12:47:56.234831 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9775 12:47:56.234924 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9776 12:47:56.235017 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9777 12:47:56.235109 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9778 12:47:56.235201 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9779 12:47:56.235294 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9780 12:47:56.235386 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9781 12:47:56.235478 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9782 12:47:56.235586 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9783 12:47:56.235694 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9784 12:47:56.235786 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9785 12:47:56.235878 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9786 12:47:56.235970 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9787 12:47:56.236077 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9788 12:47:56.236184 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9789 12:47:56.236319 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9790 12:47:56.236412 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9791 12:47:56.236506 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9792 12:47:56.236599 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9793 12:47:56.236723 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9794 12:47:56.236818 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9795 12:47:56.236912 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9796 12:47:56.237006 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9797 12:47:56.237099 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9798 12:47:56.237193 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9799 12:47:56.237287 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9800 12:47:56.237385 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9801 12:47:56.237479 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9802 12:47:56.237572 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9803 12:47:56.237666 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9804 12:47:56.237786 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9805 12:47:56.237891 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9806 12:47:56.237983 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9807 12:47:56.238130 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9808 12:47:56.238235 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9809 12:47:56.238541 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9810 12:47:56.238712 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9811 12:47:56.238877 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9812 12:47:56.239026 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9813 12:47:56.239115 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9814 12:47:56.239203 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9815 12:47:56.239289 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9816 12:47:56.239375 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9817 12:47:56.239461 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9818 12:47:56.239547 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9819 12:47:56.239633 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9820 12:47:56.239718 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9821 12:47:56.239804 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9822 12:47:56.239889 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9823 12:47:56.239974 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9824 12:47:56.240059 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9825 12:47:56.240145 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9826 12:47:56.240230 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9827 12:47:56.240315 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9828 12:47:56.240401 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9829 12:47:56.240486 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9830 12:47:56.240571 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9831 12:47:56.240656 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9832 12:47:56.240741 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9833 12:47:56.240827 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9834 12:47:56.240912 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9835 12:47:56.240997 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9836 12:47:56.241082 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9837 12:47:56.241167 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9838 12:47:56.241252 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9839 12:47:56.241338 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9840 12:47:56.241423 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9841 12:47:56.241508 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9842 12:47:56.241593 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9843 12:47:56.241691 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9844 12:47:56.241805 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9845 12:47:56.241906 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9846 12:47:56.241991 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9847 12:47:56.242076 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9848 12:47:56.242161 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9849 12:47:56.242247 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9850 12:47:56.242332 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9851 12:47:56.242417 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9852 12:47:56.242502 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9853 12:47:56.242587 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9854 12:47:56.242669 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9855 12:47:56.242725 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9856 12:47:56.242779 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9857 12:47:56.242832 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9858 12:47:56.242885 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9859 12:47:56.242939 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9860 12:47:56.242992 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9861 12:47:56.243045 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9862 12:47:56.243097 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9863 12:47:56.243151 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9864 12:47:56.243203 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9865 12:47:56.243257 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9866 12:47:56.243310 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9867 12:47:56.243363 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9868 12:47:56.243416 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9869 12:47:56.243469 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9870 12:47:56.243522 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9871 12:47:56.243575 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9872 12:47:56.243628 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9873 12:47:56.243681 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9874 12:47:56.243734 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9875 12:47:56.243787 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9876 12:47:56.243869 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9877 12:47:56.243923 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9878 12:47:56.243976 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9879 12:47:56.244030 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9880 12:47:56.244083 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9881 12:47:56.244136 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9882 12:47:56.244189 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9883 12:47:56.244243 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9884 12:47:56.244312 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9885 12:47:56.244408 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9886 12:47:56.244695 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9887 12:47:56.244789 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9888 12:47:56.244858 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9889 12:47:56.244942 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9890 12:47:56.245012 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9891 12:47:56.245067 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9892 12:47:56.245122 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9893 12:47:56.245177 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9894 12:47:56.245261 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9895 12:47:56.245315 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9896 12:47:56.245369 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9897 12:47:56.245437 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9898 12:47:56.245505 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9899 12:47:56.245573 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9900 12:47:56.245641 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9901 12:47:56.245709 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9902 12:47:56.245762 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9903 12:47:56.245842 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9904 12:47:56.245925 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9905 12:47:56.245992 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9906 12:47:56.246047 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9907 12:47:56.246101 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9908 12:47:56.246156 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9909 12:47:56.246210 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9910 12:47:56.246265 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9911 12:47:56.246318 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9912 12:47:56.246373 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9913 12:47:56.246427 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9914 12:47:56.246482 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9915 12:47:56.246536 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9916 12:47:56.246599 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9917 12:47:56.246686 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9918 12:47:56.246754 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9919 12:47:56.246807 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9920 12:47:56.246860 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9921 12:47:56.246913 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9922 12:47:56.246966 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9923 12:47:56.247019 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9924 12:47:56.247072 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9925 12:47:56.247126 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9926 12:47:56.247179 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9927 12:47:56.247247 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9928 12:47:56.247301 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9929 12:47:56.247355 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9930 12:47:56.247409 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9931 12:47:56.247463 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9932 12:47:56.247517 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9933 12:47:56.247571 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9934 12:47:56.247625 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9935 12:47:56.247679 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9936 12:47:56.247734 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9937 12:47:56.247788 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9938 12:47:56.247843 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9939 12:47:56.247897 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9940 12:47:56.247952 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9941 12:47:56.248006 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9942 12:47:56.248061 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9943 12:47:56.248115 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9944 12:47:56.248169 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9945 12:47:56.248224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9946 12:47:56.248279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9947 12:47:56.248333 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9948 12:47:56.248388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9949 12:47:56.248443 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9950 12:47:56.248498 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9951 12:47:56.248552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9952 12:47:56.248606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9953 12:47:56.248660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9954 12:47:56.248714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9955 12:47:56.248769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9956 12:47:56.248823 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9957 12:47:56.248878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9958 12:47:56.248932 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9959 12:47:56.248986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9960 12:47:56.249224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9961 12:47:56.249288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9962 12:47:56.249344 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9963 12:47:56.249399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9964 12:47:56.249454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9965 12:47:56.249509 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9966 12:47:56.249564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9967 12:47:56.249618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9968 12:47:56.249673 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9969 12:47:56.249728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9970 12:47:56.249811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9971 12:47:56.249867 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9972 12:47:56.249921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9973 12:47:56.249976 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9974 12:47:56.250030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9975 12:47:56.250085 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9976 12:47:56.250140 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9977 12:47:56.250195 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9978 12:47:56.250249 INFO: [APUAPC] vio 0
9979 12:47:56.250304 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9980 12:47:56.250359 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9981 12:47:56.250414 INFO: [APUAPC] D0_APC_0: 0x400510
9982 12:47:56.250469 INFO: [APUAPC] D0_APC_1: 0x0
9983 12:47:56.250524 INFO: [APUAPC] D0_APC_2: 0x1540
9984 12:47:56.250578 INFO: [APUAPC] D0_APC_3: 0x0
9985 12:47:56.250653 INFO: [APUAPC] D1_APC_0: 0xffffffff
9986 12:47:56.250707 INFO: [APUAPC] D1_APC_1: 0xffffffff
9987 12:47:56.250761 INFO: [APUAPC] D1_APC_2: 0x3fffff
9988 12:47:56.250814 INFO: [APUAPC] D1_APC_3: 0x0
9989 12:47:56.250867 INFO: [APUAPC] D2_APC_0: 0xffffffff
9990 12:47:56.250921 INFO: [APUAPC] D2_APC_1: 0xffffffff
9991 12:47:56.250973 INFO: [APUAPC] D2_APC_2: 0x3fffff
9992 12:47:56.251026 INFO: [APUAPC] D2_APC_3: 0x0
9993 12:47:56.251080 INFO: [APUAPC] D3_APC_0: 0xffffffff
9994 12:47:56.251133 INFO: [APUAPC] D3_APC_1: 0xffffffff
9995 12:47:56.251186 INFO: [APUAPC] D3_APC_2: 0x3fffff
9996 12:47:56.251239 INFO: [APUAPC] D3_APC_3: 0x0
9997 12:47:56.251292 INFO: [APUAPC] D4_APC_0: 0xffffffff
9998 12:47:56.251345 INFO: [APUAPC] D4_APC_1: 0xffffffff
9999 12:47:56.251398 INFO: [APUAPC] D4_APC_2: 0x3fffff
10000 12:47:56.251452 INFO: [APUAPC] D4_APC_3: 0x0
10001 12:47:56.251505 INFO: [APUAPC] D5_APC_0: 0xffffffff
10002 12:47:56.251558 INFO: [APUAPC] D5_APC_1: 0xffffffff
10003 12:47:56.251611 INFO: [APUAPC] D5_APC_2: 0x3fffff
10004 12:47:56.251664 INFO: [APUAPC] D5_APC_3: 0x0
10005 12:47:56.251717 INFO: [APUAPC] D6_APC_0: 0xffffffff
10006 12:47:56.251770 INFO: [APUAPC] D6_APC_1: 0xffffffff
10007 12:47:56.251823 INFO: [APUAPC] D6_APC_2: 0x3fffff
10008 12:47:56.251876 INFO: [APUAPC] D6_APC_3: 0x0
10009 12:47:56.251942 INFO: [APUAPC] D7_APC_0: 0xffffffff
10010 12:47:56.251996 INFO: [APUAPC] D7_APC_1: 0xffffffff
10011 12:47:56.252050 INFO: [APUAPC] D7_APC_2: 0x3fffff
10012 12:47:56.252104 INFO: [APUAPC] D7_APC_3: 0x0
10013 12:47:56.252158 INFO: [APUAPC] D8_APC_0: 0xffffffff
10014 12:47:56.252213 INFO: [APUAPC] D8_APC_1: 0xffffffff
10015 12:47:56.252267 INFO: [APUAPC] D8_APC_2: 0x3fffff
10016 12:47:56.252321 INFO: [APUAPC] D8_APC_3: 0x0
10017 12:47:56.252375 INFO: [APUAPC] D9_APC_0: 0xffffffff
10018 12:47:56.252430 INFO: [APUAPC] D9_APC_1: 0xffffffff
10019 12:47:56.252484 INFO: [APUAPC] D9_APC_2: 0x3fffff
10020 12:47:56.252538 INFO: [APUAPC] D9_APC_3: 0x0
10021 12:47:56.252592 INFO: [APUAPC] D10_APC_0: 0xffffffff
10022 12:47:56.252646 INFO: [APUAPC] D10_APC_1: 0xffffffff
10023 12:47:56.252699 INFO: [APUAPC] D10_APC_2: 0x3fffff
10024 12:47:56.252753 INFO: [APUAPC] D10_APC_3: 0x0
10025 12:47:56.252808 INFO: [APUAPC] D11_APC_0: 0xffffffff
10026 12:47:56.252861 INFO: [APUAPC] D11_APC_1: 0xffffffff
10027 12:47:56.252915 INFO: [APUAPC] D11_APC_2: 0x3fffff
10028 12:47:56.252969 INFO: [APUAPC] D11_APC_3: 0x0
10029 12:47:56.253023 INFO: [APUAPC] D12_APC_0: 0xffffffff
10030 12:47:56.253077 INFO: [APUAPC] D12_APC_1: 0xffffffff
10031 12:47:56.253131 INFO: [APUAPC] D12_APC_2: 0x3fffff
10032 12:47:56.253185 INFO: [APUAPC] D12_APC_3: 0x0
10033 12:47:56.253238 INFO: [APUAPC] D13_APC_0: 0xffffffff
10034 12:47:56.253293 INFO: [APUAPC] D13_APC_1: 0xffffffff
10035 12:47:56.253347 INFO: [APUAPC] D13_APC_2: 0x3fffff
10036 12:47:56.253401 INFO: [APUAPC] D13_APC_3: 0x0
10037 12:47:56.253454 INFO: [APUAPC] D14_APC_0: 0xffffffff
10038 12:47:56.253508 INFO: [APUAPC] D14_APC_1: 0xffffffff
10039 12:47:56.253562 INFO: [APUAPC] D14_APC_2: 0x3fffff
10040 12:47:56.253616 INFO: [APUAPC] D14_APC_3: 0x0
10041 12:47:56.253670 INFO: [APUAPC] D15_APC_0: 0xffffffff
10042 12:47:56.253725 INFO: [APUAPC] D15_APC_1: 0xffffffff
10043 12:47:56.253779 INFO: [APUAPC] D15_APC_2: 0x3fffff
10044 12:47:56.253833 INFO: [APUAPC] D15_APC_3: 0x0
10045 12:47:56.253887 INFO: [APUAPC] APC_CON: 0x4
10046 12:47:56.253941 INFO: [NOCDAPC] D0_APC_0: 0x0
10047 12:47:56.253994 INFO: [NOCDAPC] D0_APC_1: 0x0
10048 12:47:56.254049 INFO: [NOCDAPC] D1_APC_0: 0x0
10049 12:47:56.254103 INFO: [NOCDAPC] D1_APC_1: 0xfff
10050 12:47:56.254158 INFO: [NOCDAPC] D2_APC_0: 0x0
10051 12:47:56.254212 INFO: [NOCDAPC] D2_APC_1: 0xfff
10052 12:47:56.254265 INFO: [NOCDAPC] D3_APC_0: 0x0
10053 12:47:56.254324 INFO: [NOCDAPC] D3_APC_1: 0xfff
10054 12:47:56.254399 INFO: [NOCDAPC] D4_APC_0: 0x0
10055 12:47:56.254455 INFO: [NOCDAPC] D4_APC_1: 0xfff
10056 12:47:56.254510 INFO: [NOCDAPC] D5_APC_0: 0x0
10057 12:47:56.254564 INFO: [NOCDAPC] D5_APC_1: 0xfff
10058 12:47:56.254634 INFO: [NOCDAPC] D6_APC_0: 0x0
10059 12:47:56.254691 INFO: [NOCDAPC] D6_APC_1: 0xfff
10060 12:47:56.254924 INFO: [NOCDAPC] D7_APC_0: 0x0
10061 12:47:56.254985 INFO: [NOCDAPC] D7_APC_1: 0xfff
10062 12:47:56.255041 INFO: [NOCDAPC] D8_APC_0: 0x0
10063 12:47:56.255096 INFO: [NOCDAPC] D8_APC_1: 0xfff
10064 12:47:56.255151 INFO: [NOCDAPC] D9_APC_0: 0x0
10065 12:47:56.255205 INFO: [NOCDAPC] D9_APC_1: 0xfff
10066 12:47:56.255260 INFO: [NOCDAPC] D10_APC_0: 0x0
10067 12:47:56.255314 INFO: [NOCDAPC] D10_APC_1: 0xfff
10068 12:47:56.255369 INFO: [NOCDAPC] D11_APC_0: 0x0
10069 12:47:56.255423 INFO: [NOCDAPC] D11_APC_1: 0xfff
10070 12:47:56.255478 INFO: [NOCDAPC] D12_APC_0: 0x0
10071 12:47:56.255532 INFO: [NOCDAPC] D12_APC_1: 0xfff
10072 12:47:56.255587 INFO: [NOCDAPC] D13_APC_0: 0x0
10073 12:47:56.255642 INFO: [NOCDAPC] D13_APC_1: 0xfff
10074 12:47:56.255696 INFO: [NOCDAPC] D14_APC_0: 0x0
10075 12:47:56.255750 INFO: [NOCDAPC] D14_APC_1: 0xfff
10076 12:47:56.255804 INFO: [NOCDAPC] D15_APC_0: 0x0
10077 12:47:56.255858 INFO: [NOCDAPC] D15_APC_1: 0xfff
10078 12:47:56.255912 INFO: [NOCDAPC] APC_CON: 0x4
10079 12:47:56.255966 INFO: [APUAPC] set_apusys_apc done
10080 12:47:56.256020 INFO: [DEVAPC] devapc_init done
10081 12:47:56.256074 INFO: GICv3 without legacy support detected.
10082 12:47:56.256129 INFO: ARM GICv3 driver initialized in EL3
10083 12:47:56.256183 INFO: Maximum SPI INTID supported: 639
10084 12:47:56.256238 INFO: BL31: Initializing runtime services
10085 12:47:56.256293 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10086 12:47:56.256348 INFO: SPM: enable CPC mode
10087 12:47:56.256402 INFO: mcdi ready for mcusys-off-idle and system suspend
10088 12:47:56.256456 INFO: BL31: Preparing for EL3 exit to normal world
10089 12:47:56.256511 INFO: Entry point address = 0x80000000
10090 12:47:56.256566 INFO: SPSR = 0x8
10091 12:47:56.256620
10092 12:47:56.256703
10093 12:47:56.256758
10094 12:47:56.256812 Starting depthcharge on Spherion...
10095 12:47:56.256867
10096 12:47:56.256919 Wipe memory regions:
10097 12:47:56.256973
10098 12:47:56.257026 [0x00000040000000, 0x00000054600000)
10099 12:47:56.257657 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10100 12:47:56.257757 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10101 12:47:56.257843 Setting prompt string to ['asurada:']
10102 12:47:56.257924 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10103 12:47:56.298309
10104 12:47:56.298436 [0x00000054660000, 0x00000080000000)
10105 12:47:56.558901
10106 12:47:56.559413 [0x000000821a7280, 0x000000ffe64000)
10107 12:47:57.303997
10108 12:47:57.304485 [0x00000100000000, 0x00000240000000)
10109 12:48:00.196890
10110 12:48:00.197644 Initializing XHCI USB controller at 0x11200000.
10111 12:48:00.197804
10112 12:48:00.197897 R8152: Initializing
10113 12:48:00.197988
10114 12:48:00.198083 Version 9 (ocp_data = 6010)
10115 12:48:00.198180
10116 12:48:00.198282 R8152: Done initializing
10117 12:48:00.198367
10118 12:48:00.198451 Adding net device
10119 12:48:00.708015
10120 12:48:00.711194 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10121 12:48:00.711626
10122 12:48:00.711990
10123 12:48:00.712306
10124 12:48:00.713090 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10126 12:48:00.814290 asurada: tftpboot 192.168.201.1 11118904/tftp-deploy-3o_274nx/kernel/image.itb 11118904/tftp-deploy-3o_274nx/kernel/cmdline
10127 12:48:00.814724 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10128 12:48:00.815035 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10129 12:48:00.819604 tftpboot 192.168.201.1 11118904/tftp-deploy-3o_274nx/kernel/image.ittp-deploy-3o_274nx/kernel/cmdline
10130 12:48:00.819857
10131 12:48:00.820078 Waiting for link
10132 12:48:01.021458
10133 12:48:01.021624 done.
10134 12:48:01.021723
10135 12:48:01.021815 MAC: f4:f5:e8:50:de:0a
10136 12:48:01.021903
10137 12:48:01.025074 Sending DHCP discover... done.
10138 12:48:01.025176
10139 12:48:02.649075 Waiting for reply... done.
10140 12:48:02.649241
10141 12:48:02.649338 Sending DHCP request... done.
10142 12:48:02.652527
10143 12:48:02.696998 Waiting for reply... done.
10144 12:48:02.697130
10145 12:48:02.697225 My ip is 192.168.201.14
10146 12:48:02.697319
10147 12:48:02.700465 The DHCP server ip is 192.168.201.1
10148 12:48:02.700568
10149 12:48:02.706748 TFTP server IP predefined by user: 192.168.201.1
10150 12:48:02.706860
10151 12:48:02.713453 Bootfile predefined by user: 11118904/tftp-deploy-3o_274nx/kernel/image.itb
10152 12:48:02.713571
10153 12:48:02.716932 Sending tftp read request... done.
10154 12:48:02.717035
10155 12:48:02.720041 Waiting for the transfer...
10156 12:48:02.720131
10157 12:48:02.963344 00000000 ################################################################
10158 12:48:02.963516
10159 12:48:03.193521 00080000 ################################################################
10160 12:48:03.193656
10161 12:48:03.421922 00100000 ################################################################
10162 12:48:03.422098
10163 12:48:03.649948 00180000 ################################################################
10164 12:48:03.650094
10165 12:48:03.882407 00200000 ################################################################
10166 12:48:03.882581
10167 12:48:04.118111 00280000 ################################################################
10168 12:48:04.118259
10169 12:48:04.366458 00300000 ################################################################
10170 12:48:04.366663
10171 12:48:04.598501 00380000 ################################################################
10172 12:48:04.598698
10173 12:48:04.826858 00400000 ################################################################
10174 12:48:04.826996
10175 12:48:05.058614 00480000 ################################################################
10176 12:48:05.058791
10177 12:48:05.304051 00500000 ################################################################
10178 12:48:05.304198
10179 12:48:05.594427 00580000 ################################################################
10180 12:48:05.594622
10181 12:48:05.887882 00600000 ################################################################
10182 12:48:05.888021
10183 12:48:06.117441 00680000 ################################################################
10184 12:48:06.117620
10185 12:48:06.351074 00700000 ################################################################
10186 12:48:06.351227
10187 12:48:06.590428 00780000 ################################################################
10188 12:48:06.590583
10189 12:48:06.832925 00800000 ################################################################
10190 12:48:06.833075
10191 12:48:07.072717 00880000 ################################################################
10192 12:48:07.072870
10193 12:48:07.322565 00900000 ################################################################
10194 12:48:07.322777
10195 12:48:07.567719 00980000 ################################################################
10196 12:48:07.567852
10197 12:48:07.800842 00a00000 ################################################################
10198 12:48:07.800978
10199 12:48:08.034453 00a80000 ################################################################
10200 12:48:08.034628
10201 12:48:08.265459 00b00000 ################################################################
10202 12:48:08.265592
10203 12:48:08.492429 00b80000 ################################################################
10204 12:48:08.492595
10205 12:48:08.719573 00c00000 ################################################################
10206 12:48:08.719705
10207 12:48:08.951979 00c80000 ################################################################
10208 12:48:08.952143
10209 12:48:09.184136 00d00000 ################################################################
10210 12:48:09.184275
10211 12:48:09.413998 00d80000 ################################################################
10212 12:48:09.414152
10213 12:48:09.644389 00e00000 ################################################################
10214 12:48:09.644536
10215 12:48:09.875834 00e80000 ################################################################
10216 12:48:09.876004
10217 12:48:10.101937 00f00000 ################################################################
10218 12:48:10.102091
10219 12:48:10.330510 00f80000 ################################################################
10220 12:48:10.330691
10221 12:48:10.570556 01000000 ################################################################
10222 12:48:10.570737
10223 12:48:10.851156 01080000 ################################################################
10224 12:48:10.851324
10225 12:48:11.074931 01100000 ################################################################
10226 12:48:11.075074
10227 12:48:11.304046 01180000 ################################################################
10228 12:48:11.304179
10229 12:48:11.532006 01200000 ################################################################
10230 12:48:11.532182
10231 12:48:11.751577 01280000 ################################################################
10232 12:48:11.751711
10233 12:48:11.983551 01300000 ################################################################
10234 12:48:11.983719
10235 12:48:12.205600 01380000 ################################################################
10236 12:48:12.205741
10237 12:48:12.428614 01400000 ################################################################
10238 12:48:12.428752
10239 12:48:12.653231 01480000 ################################################################
10240 12:48:12.653379
10241 12:48:12.886167 01500000 ################################################################
10242 12:48:12.886340
10243 12:48:13.121693 01580000 ################################################################
10244 12:48:13.121857
10245 12:48:13.365412 01600000 ################################################################
10246 12:48:13.365580
10247 12:48:13.593836 01680000 ################################################################
10248 12:48:13.593999
10249 12:48:13.836684 01700000 ################################################################
10250 12:48:13.836859
10251 12:48:14.057575 01780000 ################################################################
10252 12:48:14.057806
10253 12:48:14.294074 01800000 ################################################################
10254 12:48:14.294217
10255 12:48:14.516834 01880000 ################################################################
10256 12:48:14.516983
10257 12:48:14.748005 01900000 ################################################################
10258 12:48:14.748150
10259 12:48:14.989096 01980000 ################################################################
10260 12:48:14.989254
10261 12:48:15.240538 01a00000 ################################################################
10262 12:48:15.240687
10263 12:48:15.484197 01a80000 ################################################################
10264 12:48:15.484328
10265 12:48:15.736052 01b00000 ################################################################
10266 12:48:15.736192
10267 12:48:15.988194 01b80000 ################################################################
10268 12:48:15.988341
10269 12:48:16.247756 01c00000 ################################################################
10270 12:48:16.247888
10271 12:48:16.511976 01c80000 ################################################################
10272 12:48:16.512115
10273 12:48:16.771898 01d00000 ################################################################
10274 12:48:16.772035
10275 12:48:17.017597 01d80000 ################################################################
10276 12:48:17.017756
10277 12:48:17.245843 01e00000 ################################################################
10278 12:48:17.245983
10279 12:48:17.501794 01e80000 ################################################################
10280 12:48:17.501934
10281 12:48:17.768352 01f00000 ################################################################
10282 12:48:17.768496
10283 12:48:18.070565 01f80000 ################################################################
10284 12:48:18.070776
10285 12:48:18.257362 02000000 ################################################################
10286 12:48:18.257502
10287 12:48:18.507312 02080000 ################################################################
10288 12:48:18.507453
10289 12:48:18.743037 02100000 ################################################################
10290 12:48:18.743198
10291 12:48:19.003651 02180000 ################################################################
10292 12:48:19.003787
10293 12:48:19.243297 02200000 ################################################################
10294 12:48:19.243428
10295 12:48:19.471980 02280000 ################################################################
10296 12:48:19.472139
10297 12:48:19.706402 02300000 ################################################################
10298 12:48:19.706540
10299 12:48:19.936619 02380000 ################################################################
10300 12:48:19.936760
10301 12:48:20.161427 02400000 ################################################################
10302 12:48:20.161608
10303 12:48:20.602032 02480000 ################################################################
10304 12:48:20.602189
10305 12:48:20.613266 02500000 ################################################################
10306 12:48:20.613414
10307 12:48:20.838413 02580000 ################################################################
10308 12:48:20.838558
10309 12:48:21.077693 02600000 ################################################################
10310 12:48:21.077845
10311 12:48:21.308671 02680000 ################################################################
10312 12:48:21.308904
10313 12:48:21.554726 02700000 ################################################################
10314 12:48:21.554868
10315 12:48:21.807301 02780000 ################################################################
10316 12:48:21.807450
10317 12:48:22.046645 02800000 ################################################################
10318 12:48:22.046798
10319 12:48:22.774731 02880000 ################################################################
10320 12:48:22.774899
10321 12:48:22.775011 02900000 ################################################################
10322 12:48:22.775081
10323 12:48:22.791441 02980000 ################################################################
10324 12:48:22.791616
10325 12:48:23.033959 02a00000 ################################################################
10326 12:48:23.034097
10327 12:48:24.035422 02a80000 ################################################################
10328 12:48:24.035644
10329 12:48:24.035758 02b00000 ################################################################
10330 12:48:24.035852
10331 12:48:24.035974 02b80000 ################################################################
10332 12:48:24.036066
10333 12:48:24.036161 02c00000 ################################################################
10334 12:48:24.036250
10335 12:48:24.226100 02c80000 ################################################################
10336 12:48:24.226269
10337 12:48:24.951760 02d00000 ################################################################
10338 12:48:24.951981
10339 12:48:24.952132 02d80000 ################################################################
10340 12:48:24.952249
10341 12:48:24.954804 02e00000 ################################################################
10342 12:48:24.954929
10343 12:48:25.194647 02e80000 ################################################################
10344 12:48:25.194790
10345 12:48:25.452540 02f00000 ################################################################
10346 12:48:25.452673
10347 12:48:26.052508 02f80000 ################################################################
10348 12:48:26.052709
10349 12:48:26.052777 03000000 ################################################################
10350 12:48:26.052851
10351 12:48:26.155132 03080000 ################################################################
10352 12:48:26.155269
10353 12:48:26.414351 03100000 ################################################################
10354 12:48:26.414544
10355 12:48:26.664754 03180000 ################################################################
10356 12:48:26.664904
10357 12:48:26.922238 03200000 ################################################################
10358 12:48:26.922414
10359 12:48:27.174042 03280000 ################################################################
10360 12:48:27.174193
10361 12:48:27.411553 03300000 ################################################################
10362 12:48:27.411697
10363 12:48:27.649879 03380000 ################################################################
10364 12:48:27.650015
10365 12:48:27.885944 03400000 ################################################################
10366 12:48:27.886120
10367 12:48:28.122412 03480000 ################################################################
10368 12:48:28.122581
10369 12:48:28.359809 03500000 ################################################################
10370 12:48:28.359947
10371 12:48:28.597400 03580000 ################################################################
10372 12:48:28.597565
10373 12:48:28.839378 03600000 ################################################################
10374 12:48:28.839560
10375 12:48:29.089417 03680000 ################################################################
10376 12:48:29.089595
10377 12:48:29.318151 03700000 ################################################################
10378 12:48:29.318305
10379 12:48:29.336439 03780000 ###### done.
10380 12:48:29.336561
10381 12:48:29.340067 The bootfile was 58239446 bytes long.
10382 12:48:29.340156
10383 12:48:29.343186 Sending tftp read request... done.
10384 12:48:29.343268
10385 12:48:29.346399 Waiting for the transfer...
10386 12:48:29.346503
10387 12:48:29.346622 00000000 # done.
10388 12:48:29.346708
10389 12:48:29.356316 Command line loaded dynamically from TFTP file: 11118904/tftp-deploy-3o_274nx/kernel/cmdline
10390 12:48:29.356400
10391 12:48:29.369546 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10392 12:48:29.369628
10393 12:48:29.369697 Loading FIT.
10394 12:48:29.369760
10395 12:48:29.373241 Image ramdisk-1 has 47382310 bytes.
10396 12:48:29.373314
10397 12:48:29.376368 Image fdt-1 has 46924 bytes.
10398 12:48:29.376442
10399 12:48:29.379828 Image kernel-1 has 10808178 bytes.
10400 12:48:29.379908
10401 12:48:29.386457 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10402 12:48:29.386566
10403 12:48:29.406254 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10404 12:48:29.406357
10405 12:48:29.409315 Choosing best match conf-1 for compat google,spherion-rev2.
10406 12:48:29.414357
10407 12:48:29.418793 Connected to device vid:did:rid of 1ae0:0028:00
10408 12:48:29.426281
10409 12:48:29.429352 tpm_get_response: command 0x17b, return code 0x0
10410 12:48:29.429430
10411 12:48:29.433031 ec_init: CrosEC protocol v3 supported (256, 248)
10412 12:48:29.436555
10413 12:48:29.440519 tpm_cleanup: add release locality here.
10414 12:48:29.440599
10415 12:48:29.440664 Shutting down all USB controllers.
10416 12:48:29.443531
10417 12:48:29.443616 Removing current net device
10418 12:48:29.443683
10419 12:48:29.450425 Exiting depthcharge with code 4 at timestamp: 62766959
10420 12:48:29.450537
10421 12:48:29.453481 LZMA decompressing kernel-1 to 0x821a6718
10422 12:48:29.453566
10423 12:48:29.456661 LZMA decompressing kernel-1 to 0x40000000
10424 12:48:31.978497
10425 12:48:31.979352 jumping to kernel
10426 12:48:31.981648 end: 2.2.4 bootloader-commands (duration 00:00:36) [common]
10427 12:48:31.982464 start: 2.2.5 auto-login-action (timeout 00:03:49) [common]
10428 12:48:31.983108 Setting prompt string to ['Linux version [0-9]']
10429 12:48:31.983693 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10430 12:48:31.984391 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10431 12:48:31.985835
10432 12:48:31.986397 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10433 12:48:31.987028 [ 0.000000] Linux version 6.1.38-cip1 (KernelCI@build-j6766-arm64-gcc-10-defconfig-arm64-chromebook-9w8v6) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Jul 20 12:35:57 UTC 2023
10434 12:48:31.987552 [ 0.000000] random: crng init done
10435 12:48:31.988064 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10436 12:48:31.988669 [ 0.000000] efi: UEFI not found.
10437 12:48:31.989269 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10438 12:48:31.989916 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10439 12:48:31.990491 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10440 12:48:31.991091 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10441 12:48:31.991648 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10442 12:48:31.992262 [ 0.000000] printk: bootconsole [mtk8250] enabled
10443 12:48:31.992798 [ 0.000000] NUMA: No NUMA configuration found
10444 12:48:31.993301 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10445 12:48:31.993827 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10446 12:48:31.994327 [ 0.000000] Zone ranges:
10447 12:48:31.994744 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10448 12:48:31.995064 [ 0.000000] DMA32 empty
10449 12:48:31.995378 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10450 12:48:31.995687 [ 0.000000] Movable zone start for each node
10451 12:48:31.996040 [ 0.000000] Early memory node ranges
10452 12:48:31.996401 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10453 12:48:31.996772 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10454 12:48:31.997128 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10455 12:48:31.997447 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10456 12:48:31.997765 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10457 12:48:31.998106 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10458 12:48:31.998448 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10459 12:48:31.998800 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10460 12:48:31.999142 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10461 12:48:31.999462 [ 0.000000] psci: probing for conduit method from DT.
10462 12:48:31.999709 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10463 12:48:31.999941 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10464 12:48:32.000198 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10465 12:48:32.000429 [ 0.000000] psci: SMC Calling Convention v1.2
10466 12:48:32.000686 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10467 12:48:32.000918 [ 0.000000] Detected VIPT I-cache on CPU0
10468 12:48:32.001171 [ 0.000000] CPU features: detected: GIC system register CPU interface
10469 12:48:32.001407 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10470 12:48:32.001656 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10471 12:48:32.001894 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10472 12:48:32.002126 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10473 12:48:32.002382 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10474 12:48:32.002644 [ 0.000000] alternatives: applying boot alternatives
10475 12:48:32.002901 [ 0.000000] Fallback order for Node 0: 0
10476 12:48:32.003147 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10477 12:48:32.003436 [ 0.000000] Policy zone: Normal
10478 12:48:32.003708 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10479 12:48:32.003983 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10480 12:48:32.004247 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10481 12:48:32.004510 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10482 12:48:32.004707 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10483 12:48:32.004895 <6>[ 0.000000] software IO TLB: area num 8.
10484 12:48:32.005103 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10485 12:48:32.005301 <6>[ 0.000000] Memory: 7923928K/8385536K available (17984K kernel code, 4098K rwdata, 16796K rodata, 8384K init, 615K bss, 428840K reserved, 32768K cma-reserved)
10486 12:48:32.006390 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10487 12:48:32.006642 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10488 12:48:32.006855 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10489 12:48:32.007076 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10490 12:48:32.007284 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10491 12:48:32.007482 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10492 12:48:32.007701 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10493 12:48:32.007896 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10494 12:48:32.008091 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10495 12:48:32.008303 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10496 12:48:32.008494 <6>[ 0.000000] GICv3: 608 SPIs implemented
10497 12:48:32.008683 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10498 12:48:32.008809 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10499 12:48:32.008931 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10500 12:48:32.009052 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10501 12:48:32.009174 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10502 12:48:32.009298 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10503 12:48:32.009435 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10504 12:48:32.009536 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10505 12:48:32.009637 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10506 12:48:32.009739 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10507 12:48:32.009850 <6>[ 0.009177] Console: colour dummy device 80x25
10508 12:48:32.009982 <6>[ 0.013902] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10509 12:48:32.010098 <6>[ 0.024408] pid_max: default: 32768 minimum: 301
10510 12:48:32.010202 <6>[ 0.029311] LSM: Security Framework initializing
10511 12:48:32.010345 <6>[ 0.034246] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10512 12:48:32.010522 <6>[ 0.042059] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10513 12:48:32.010675 <6>[ 0.051487] cblist_init_generic: Setting adjustable number of callback queues.
10514 12:48:32.010800 <6>[ 0.058942] cblist_init_generic: Setting shift to 3 and lim to 1.
10515 12:48:32.010960 <6>[ 0.065318] cblist_init_generic: Setting shift to 3 and lim to 1.
10516 12:48:32.011066 <6>[ 0.071727] rcu: Hierarchical SRCU implementation.
10517 12:48:32.011168 <6>[ 0.076740] rcu: Max phase no-delay instances is 1000.
10518 12:48:32.011269 <6>[ 0.083740] EFI services will not be available.
10519 12:48:32.011368 <6>[ 0.088716] smp: Bringing up secondary CPUs ...
10520 12:48:32.011504 <6>[ 0.093797] Detected VIPT I-cache on CPU1
10521 12:48:32.011607 <6>[ 0.093866] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10522 12:48:32.011709 <6>[ 0.093897] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10523 12:48:32.011809 <6>[ 0.094228] Detected VIPT I-cache on CPU2
10524 12:48:32.011930 <6>[ 0.094280] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10525 12:48:32.012038 <6>[ 0.094298] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10526 12:48:32.012139 <6>[ 0.094555] Detected VIPT I-cache on CPU3
10527 12:48:32.012238 <6>[ 0.094601] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10528 12:48:32.012338 <6>[ 0.094616] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10529 12:48:32.012466 <6>[ 0.094919] CPU features: detected: Spectre-v4
10530 12:48:32.012571 <6>[ 0.094926] CPU features: detected: Spectre-BHB
10531 12:48:32.012672 <6>[ 0.094932] Detected PIPT I-cache on CPU4
10532 12:48:32.012772 <6>[ 0.094990] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10533 12:48:32.012871 <6>[ 0.095008] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10534 12:48:32.012996 <6>[ 0.095298] Detected PIPT I-cache on CPU5
10535 12:48:32.013102 <6>[ 0.095362] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10536 12:48:32.013202 <6>[ 0.095379] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10537 12:48:32.013362 <6>[ 0.095661] Detected PIPT I-cache on CPU6
10538 12:48:32.013541 <6>[ 0.095726] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10539 12:48:32.013702 <6>[ 0.095743] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10540 12:48:32.013863 <6>[ 0.096041] Detected PIPT I-cache on CPU7
10541 12:48:32.013971 <6>[ 0.096107] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10542 12:48:32.014453 <6>[ 0.096124] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10543 12:48:32.014555 <6>[ 0.096171] smp: Brought up 1 node, 8 CPUs
10544 12:48:32.014671 <6>[ 0.237413] SMP: Total of 8 processors activated.
10545 12:48:32.014764 <6>[ 0.242334] CPU features: detected: 32-bit EL0 Support
10546 12:48:32.014854 <6>[ 0.247697] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10547 12:48:32.014943 <6>[ 0.256552] CPU features: detected: Common not Private translations
10548 12:48:32.015030 <6>[ 0.263067] CPU features: detected: CRC32 instructions
10549 12:48:32.015115 <6>[ 0.268419] CPU features: detected: RCpc load-acquire (LDAPR)
10550 12:48:32.015200 <6>[ 0.274378] CPU features: detected: LSE atomic instructions
10551 12:48:32.015285 <6>[ 0.280160] CPU features: detected: Privileged Access Never
10552 12:48:32.015370 <6>[ 0.285975] CPU features: detected: RAS Extension Support
10553 12:48:32.015454 <6>[ 0.291583] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10554 12:48:32.015539 <6>[ 0.298803] CPU: All CPU(s) started at EL2
10555 12:48:32.015624 <6>[ 0.303147] alternatives: applying system-wide alternatives
10556 12:48:32.015709 <6>[ 0.313834] devtmpfs: initialized
10557 12:48:32.015793 <6>[ 0.322911] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10558 12:48:32.015879 <6>[ 0.332876] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10559 12:48:32.015964 <6>[ 0.340886] pinctrl core: initialized pinctrl subsystem
10560 12:48:32.016048 <6>[ 0.347555] DMI not present or invalid.
10561 12:48:32.016132 <6>[ 0.351964] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10562 12:48:32.016218 <6>[ 0.358828] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10563 12:48:32.016306 <6>[ 0.366410] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10564 12:48:32.016399 <6>[ 0.374626] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10565 12:48:32.016519 <6>[ 0.382869] audit: initializing netlink subsys (disabled)
10566 12:48:32.020964 <5>[ 0.388567] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10567 12:48:32.027145 <6>[ 0.389271] thermal_sys: Registered thermal governor 'step_wise'
10568 12:48:32.034011 <6>[ 0.396539] thermal_sys: Registered thermal governor 'power_allocator'
10569 12:48:32.036924 <6>[ 0.402797] cpuidle: using governor menu
10570 12:48:32.043759 <6>[ 0.413763] NET: Registered PF_QIPCRTR protocol family
10571 12:48:32.050158 <6>[ 0.419254] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10572 12:48:32.056683 <6>[ 0.426363] ASID allocator initialised with 32768 entries
10573 12:48:32.060058 <6>[ 0.432936] Serial: AMBA PL011 UART driver
10574 12:48:32.069827 <4>[ 0.441620] Trying to register duplicate clock ID: 134
10575 12:48:32.126147 <6>[ 0.500991] KASLR enabled
10576 12:48:32.140767 <6>[ 0.508723] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10577 12:48:32.147173 <6>[ 0.515738] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10578 12:48:32.153734 <6>[ 0.522228] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10579 12:48:32.160317 <6>[ 0.529235] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10580 12:48:32.166892 <6>[ 0.535725] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10581 12:48:32.173929 <6>[ 0.542733] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10582 12:48:32.180371 <6>[ 0.549221] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10583 12:48:32.186924 <6>[ 0.556228] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10584 12:48:32.189822 <6>[ 0.563706] ACPI: Interpreter disabled.
10585 12:48:32.198713 <6>[ 0.570102] iommu: Default domain type: Translated
10586 12:48:32.205166 <6>[ 0.575261] iommu: DMA domain TLB invalidation policy: strict mode
10587 12:48:32.208139 <5>[ 0.581928] SCSI subsystem initialized
10588 12:48:32.215273 <6>[ 0.586176] usbcore: registered new interface driver usbfs
10589 12:48:32.221880 <6>[ 0.591910] usbcore: registered new interface driver hub
10590 12:48:32.224905 <6>[ 0.597467] usbcore: registered new device driver usb
10591 12:48:32.232259 <6>[ 0.603572] pps_core: LinuxPPS API ver. 1 registered
10592 12:48:33.829782 <6>[ 0.608766] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10593 12:48:33.830735 <6>[ 0.618112] PTP clock support registered
10594 12:48:33.831552 <6>[ 0.622353] EDAC MC: Ver: 3.0.0
10595 12:48:33.832224 <6>[ 0.627527] FPGA manager framework
10596 12:48:33.832981 <6>[ 0.631205] Advanced Linux Sound Architecture Driver Initialized.
10597 12:48:33.833748 <6>[ 0.637987] vgaarb: loaded
10598 12:48:33.834477 <6>[ 0.641153] clocksource: Switched to clocksource arch_sys_counter
10599 12:48:33.834627 <5>[ 0.647611] VFS: Disk quotas dquot_6.6.0
10600 12:48:33.834753 <6>[ 0.651794] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10601 12:48:33.834860 <6>[ 0.658988] pnp: PnP ACPI: disabled
10602 12:48:33.834963 <6>[ 0.665699] NET: Registered PF_INET protocol family
10603 12:48:33.835084 <6>[ 0.671298] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10604 12:48:33.835210 <6>[ 0.683606] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10605 12:48:33.835333 <6>[ 0.692426] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10606 12:48:33.835454 <6>[ 0.700399] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10607 12:48:33.835578 <6>[ 0.709100] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10608 12:48:33.835681 <6>[ 0.718839] TCP: Hash tables configured (established 65536 bind 65536)
10609 12:48:33.835774 <6>[ 0.725699] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10610 12:48:33.835874 <6>[ 0.732899] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10611 12:48:33.835978 <6>[ 0.740606] NET: Registered PF_UNIX/PF_LOCAL protocol family
10612 12:48:33.836080 <6>[ 0.746784] RPC: Registered named UNIX socket transport module.
10613 12:48:33.836179 <6>[ 0.752943] RPC: Registered udp transport module.
10614 12:48:33.836268 <6>[ 0.757878] RPC: Registered tcp transport module.
10615 12:48:33.836364 <6>[ 0.762812] RPC: Registered tcp NFSv4.1 backchannel transport module.
10616 12:48:33.836459 <6>[ 0.769481] PCI: CLS 0 bytes, default 64
10617 12:48:33.836547 <6>[ 0.773879] Unpacking initramfs...
10618 12:48:33.836636 <6>[ 0.793258] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10619 12:48:33.836725 <6>[ 0.801924] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10620 12:48:33.836813 <6>[ 0.810768] kvm [1]: IPA Size Limit: 40 bits
10621 12:48:33.836900 <6>[ 0.815298] kvm [1]: GICv3: no GICV resource entry
10622 12:48:33.836987 <6>[ 0.820320] kvm [1]: disabling GICv2 emulation
10623 12:48:33.837080 <6>[ 0.825007] kvm [1]: GIC system register CPU interface enabled
10624 12:48:33.837192 <6>[ 0.831178] kvm [1]: vgic interrupt IRQ18
10625 12:48:33.837303 <6>[ 0.835540] kvm [1]: VHE mode initialized successfully
10626 12:48:33.837406 <5>[ 0.841999] Initialise system trusted keyrings
10627 12:48:33.837502 <6>[ 0.846808] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10628 12:48:33.837590 <6>[ 0.857028] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10629 12:48:33.837677 <5>[ 0.863421] NFS: Registering the id_resolver key type
10630 12:48:33.837764 <5>[ 0.868741] Key type id_resolver registered
10631 12:48:33.837850 <5>[ 0.873159] Key type id_legacy registered
10632 12:48:33.837937 <6>[ 0.877439] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10633 12:48:33.838024 <6>[ 0.884363] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10634 12:48:33.838111 <6>[ 0.892093] 9p: Installing v9fs 9p2000 file system support
10635 12:48:33.838197 <5>[ 0.929120] Key type asymmetric registered
10636 12:48:33.838284 <5>[ 0.933453] Asymmetric key parser 'x509' registered
10637 12:48:33.838371 <6>[ 0.938596] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10638 12:48:33.838457 <6>[ 0.946212] io scheduler mq-deadline registered
10639 12:48:33.838543 <6>[ 0.950994] io scheduler kyber registered
10640 12:48:33.838648 <6>[ 0.967769] EINJ: ACPI disabled.
10641 12:48:33.838706 <4>[ 0.993138] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10642 12:48:33.838762 <4>[ 1.003752] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10643 12:48:33.838817 <6>[ 1.024378] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10644 12:48:33.838873 <6>[ 1.032352] printk: console [ttyS0] disabled
10645 12:48:33.838928 <6>[ 1.057000] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10646 12:48:33.838983 <6>[ 1.066479] printk: console [ttyS0] enabled
10647 12:48:33.839037 <6>[ 1.066479] printk: console [ttyS0] enabled
10648 12:48:33.839092 <6>[ 1.075372] printk: bootconsole [mtk8250] disabled
10649 12:48:33.839146 <6>[ 1.075372] printk: bootconsole [mtk8250] disabled
10650 12:48:33.839201 <6>[ 1.086659] SuperH (H)SCI(F) driver initialized
10651 12:48:33.839254 <6>[ 1.091938] msm_serial: driver initialized
10652 12:48:33.839338 <6>[ 1.100876] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10653 12:48:33.839701 <6>[ 1.109425] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10654 12:48:33.839781 <6>[ 1.117967] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10655 12:48:33.839842 <6>[ 1.126595] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10656 12:48:33.839901 <6>[ 1.135310] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10657 12:48:33.839958 <6>[ 1.144026] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10658 12:48:33.840014 <6>[ 1.152568] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10659 12:48:33.840070 <6>[ 1.161370] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10660 12:48:33.840126 <6>[ 1.169914] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10661 12:48:33.840182 <6>[ 1.185683] loop: module loaded
10662 12:48:33.840237 <6>[ 1.191730] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10663 12:48:33.840293 <4>[ 1.215192] mtk-pmic-keys: Failed to locate of_node [id: -1]
10664 12:48:33.840348 <6>[ 1.221885] megasas: 07.719.03.00-rc1
10665 12:48:33.840403 <6>[ 1.231447] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10666 12:48:33.840459 <6>[ 1.240525] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10667 12:48:33.840515 <6>[ 1.257198] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10668 12:48:33.840570 <6>[ 1.311374] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10669 12:48:34.394279 <6>[ 2.765574] Freeing initrd memory: 46268K
10670 12:48:34.404335 <6>[ 2.775863] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10671 12:48:34.415517 <6>[ 2.786807] tun: Universal TUN/TAP device driver, 1.6
10672 12:48:34.418485 <6>[ 2.792850] thunder_xcv, ver 1.0
10673 12:48:34.422010 <6>[ 2.796357] thunder_bgx, ver 1.0
10674 12:48:34.425544 <6>[ 2.799852] nicpf, ver 1.0
10675 12:48:34.435568 <6>[ 2.803850] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10676 12:48:34.439132 <6>[ 2.811325] hns3: Copyright (c) 2017 Huawei Corporation.
10677 12:48:34.445647 <6>[ 2.816913] hclge is initializing
10678 12:48:34.449279 <6>[ 2.820494] e1000: Intel(R) PRO/1000 Network Driver
10679 12:48:34.455729 <6>[ 2.825622] e1000: Copyright (c) 1999-2006 Intel Corporation.
10680 12:48:34.458949 <6>[ 2.831635] e1000e: Intel(R) PRO/1000 Network Driver
10681 12:48:34.465534 <6>[ 2.836851] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10682 12:48:34.471900 <6>[ 2.843035] igb: Intel(R) Gigabit Ethernet Network Driver
10683 12:48:34.479115 <6>[ 2.848684] igb: Copyright (c) 2007-2014 Intel Corporation.
10684 12:48:34.485506 <6>[ 2.854522] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10685 12:48:34.492008 <6>[ 2.861040] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10686 12:48:34.495594 <6>[ 2.867496] sky2: driver version 1.30
10687 12:48:34.501762 <6>[ 2.872463] VFIO - User Level meta-driver version: 0.3
10688 12:48:34.509218 <6>[ 2.880683] usbcore: registered new interface driver usb-storage
10689 12:48:34.516013 <6>[ 2.887133] usbcore: registered new device driver onboard-usb-hub
10690 12:48:34.524743 <6>[ 2.896196] mt6397-rtc mt6359-rtc: registered as rtc0
10691 12:48:34.534650 <6>[ 2.901653] mt6397-rtc mt6359-rtc: setting system clock to 2023-07-20T12:48:37 UTC (1689857317)
10692 12:48:34.537901 <6>[ 2.911210] i2c_dev: i2c /dev entries driver
10693 12:48:34.554981 <6>[ 2.922848] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10694 12:48:34.561596 <6>[ 2.933041] sdhci: Secure Digital Host Controller Interface driver
10695 12:48:34.568318 <6>[ 2.939481] sdhci: Copyright(c) Pierre Ossman
10696 12:48:34.574786 <6>[ 2.944874] Synopsys Designware Multimedia Card Interface Driver
10697 12:48:34.578400 <6>[ 2.951469] mmc0: CQHCI version 5.10
10698 12:48:34.584856 <6>[ 2.952021] sdhci-pltfm: SDHCI platform and OF driver helper
10699 12:48:34.591993 <6>[ 2.963325] ledtrig-cpu: registered to indicate activity on CPUs
10700 12:48:34.602909 <6>[ 2.970691] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10701 12:48:34.605798 <6>[ 2.978079] usbcore: registered new interface driver usbhid
10702 12:48:34.612768 <6>[ 2.983906] usbhid: USB HID core driver
10703 12:48:34.619137 <6>[ 2.988146] spi_master spi0: will run message pump with realtime priority
10704 12:48:34.665821 <6>[ 3.030481] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10705 12:48:34.684758 <6>[ 3.045719] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10706 12:48:34.688189 <6>[ 3.059310] mmc0: Command Queue Engine enabled
10707 12:48:34.694517 <6>[ 3.060953] cros-ec-spi spi0.0: Chrome EC device registered
10708 12:48:34.701072 <6>[ 3.064057] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10709 12:48:34.704729 <6>[ 3.077199] mmcblk0: mmc0:0001 DA4128 116 GiB
10710 12:48:34.716827 <6>[ 3.087885] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10711 12:48:34.726586 <6>[ 3.088209] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10712 12:48:34.733164 <6>[ 3.095277] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10713 12:48:34.736527 <6>[ 3.105212] NET: Registered PF_PACKET protocol family
10714 12:48:34.743254 <6>[ 3.109005] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10715 12:48:34.746142 <6>[ 3.113751] 9pnet: Installing 9P2000 support
10716 12:48:34.753109 <6>[ 3.119485] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10717 12:48:34.759683 <5>[ 3.123429] Key type dns_resolver registered
10718 12:48:34.762690 <6>[ 3.134950] registered taskstats version 1
10719 12:48:34.769574 <5>[ 3.139332] Loading compiled-in X.509 certificates
10720 12:48:34.801135 <4>[ 3.165853] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10721 12:48:34.810547 <4>[ 3.176521] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10722 12:48:34.820802 <3>[ 3.189274] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10723 12:48:34.832822 <6>[ 3.204559] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10724 12:48:34.839916 <6>[ 3.211311] xhci-mtk 11200000.usb: xHCI Host Controller
10725 12:48:34.846553 <6>[ 3.216820] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10726 12:48:34.856341 <6>[ 3.224685] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10727 12:48:34.863037 <6>[ 3.234136] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10728 12:48:34.870022 <6>[ 3.240349] xhci-mtk 11200000.usb: xHCI Host Controller
10729 12:48:34.876533 <6>[ 3.245859] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10730 12:48:34.882768 <6>[ 3.253516] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10731 12:48:34.889987 <6>[ 3.261416] hub 1-0:1.0: USB hub found
10732 12:48:34.893273 <6>[ 3.265451] hub 1-0:1.0: 1 port detected
10733 12:48:34.903238 <6>[ 3.269803] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10734 12:48:34.906626 <6>[ 3.278634] hub 2-0:1.0: USB hub found
10735 12:48:34.909321 <6>[ 3.282676] hub 2-0:1.0: 1 port detected
10736 12:48:34.918058 <6>[ 3.289789] mtk-msdc 11f70000.mmc: Got CD GPIO
10737 12:48:34.935266 <6>[ 3.303403] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10738 12:48:34.941774 <6>[ 3.311437] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10739 12:48:34.951356 <4>[ 3.319426] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10740 12:48:34.961549 <6>[ 3.329085] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10741 12:48:34.968460 <6>[ 3.337170] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10742 12:48:34.978456 <6>[ 3.345203] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10743 12:48:34.985051 <6>[ 3.353127] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10744 12:48:34.991647 <6>[ 3.360949] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10745 12:48:35.000740 <6>[ 3.368771] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10746 12:48:35.010832 <6>[ 3.379451] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10747 12:48:35.020852 <6>[ 3.387818] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10748 12:48:35.027440 <6>[ 3.396171] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10749 12:48:35.037522 <6>[ 3.404517] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10750 12:48:35.044244 <6>[ 3.412861] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10751 12:48:35.054148 <6>[ 3.421205] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10752 12:48:35.060542 <6>[ 3.429550] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10753 12:48:35.070666 <6>[ 3.437894] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10754 12:48:35.077141 <6>[ 3.446238] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10755 12:48:35.087219 <6>[ 3.454582] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10756 12:48:35.093836 <6>[ 3.462927] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10757 12:48:35.103454 <6>[ 3.471271] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10758 12:48:35.110277 <6>[ 3.479616] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10759 12:48:35.119877 <6>[ 3.487971] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10760 12:48:35.126524 <6>[ 3.496317] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10761 12:48:35.133787 <6>[ 3.505242] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10762 12:48:35.141166 <6>[ 3.512676] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10763 12:48:35.148177 <6>[ 3.519697] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10764 12:48:35.158572 <6>[ 3.526783] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10765 12:48:35.165122 <6>[ 3.534054] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10766 12:48:35.175313 <6>[ 3.540953] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10767 12:48:35.182032 <6>[ 3.550102] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10768 12:48:35.191750 <6>[ 3.559231] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10769 12:48:35.201608 <6>[ 3.568534] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10770 12:48:35.211650 <6>[ 3.578009] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10771 12:48:35.221404 <6>[ 3.587484] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10772 12:48:35.227877 <6>[ 3.596612] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10773 12:48:35.237930 <6>[ 3.606088] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10774 12:48:35.247843 <6>[ 3.615215] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10775 12:48:35.257473 <6>[ 3.624517] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10776 12:48:35.267397 <6>[ 3.634683] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10777 12:48:35.277660 <6>[ 3.646116] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10778 12:48:35.301343 <6>[ 3.669622] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10779 12:48:35.328144 <6>[ 3.699898] hub 2-1:1.0: USB hub found
10780 12:48:35.331571 <6>[ 3.704296] hub 2-1:1.0: 3 ports detected
10781 12:48:35.452885 <6>[ 3.821428] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10782 12:48:35.607116 <6>[ 3.978713] hub 1-1:1.0: USB hub found
10783 12:48:35.610523 <6>[ 3.983167] hub 1-1:1.0: 4 ports detected
10784 12:48:35.932949 <6>[ 4.301427] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10785 12:48:36.064245 <6>[ 4.435472] hub 1-1.1:1.0: USB hub found
10786 12:48:36.067396 <6>[ 4.439766] hub 1-1.1:1.0: 4 ports detected
10787 12:48:36.181207 <6>[ 4.549208] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10788 12:48:36.313607 <6>[ 4.685283] hub 1-1.4:1.0: USB hub found
10789 12:48:36.316808 <6>[ 4.689909] hub 1-1.4:1.0: 2 ports detected
10790 12:48:36.393084 <6>[ 4.761425] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10791 12:48:36.580902 <6>[ 4.949428] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10792 12:48:36.666213 <3>[ 5.037636] usb 1-1.1.4: device descriptor read/64, error -32
10793 12:48:36.857920 <3>[ 5.229637] usb 1-1.1.4: device descriptor read/64, error -32
10794 12:48:37.052826 <6>[ 5.421428] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10795 12:48:37.241134 <6>[ 5.609430] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10796 12:48:37.325633 <3>[ 5.697634] usb 1-1.1.4: device descriptor read/64, error -32
10797 12:48:37.517515 <3>[ 5.889660] usb 1-1.1.4: device descriptor read/64, error -32
10798 12:48:37.629963 <6>[ 6.002006] usb 1-1.1-port4: attempt power cycle
10799 12:48:37.716911 <6>[ 6.085427] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10800 12:48:38.241008 <6>[ 6.609426] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10801 12:48:38.247559 <4>[ 6.616780] usb 1-1.1.4: Device not responding to setup address.
10802 12:48:38.457580 <4>[ 6.829706] usb 1-1.1.4: Device not responding to setup address.
10803 12:48:38.669015 <3>[ 7.041446] usb 1-1.1.4: device not accepting address 10, error -71
10804 12:48:38.756322 <6>[ 7.125427] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10805 12:48:38.763206 <4>[ 7.132876] usb 1-1.1.4: Device not responding to setup address.
10806 12:48:38.973595 <4>[ 7.345702] usb 1-1.1.4: Device not responding to setup address.
10807 12:48:39.185511 <3>[ 7.557418] usb 1-1.1.4: device not accepting address 11, error -71
10808 12:48:39.556991 <3>[ 7.564367] usb 1-1.1-port4: unable to enumerate USB device
10809 12:48:47.569935 <6>[ 15.945997] ALSA device list:
10810 12:48:47.576174 <6>[ 15.949253] No soundcards found.
10811 12:48:47.588653 <6>[ 15.961648] Freeing unused kernel memory: 8384K
10812 12:48:47.592154 <6>[ 15.966522] Run /init as init process
10813 12:48:47.621870 <6>[ 15.994552] NET: Registered PF_INET6 protocol family
10814 12:48:47.628402 <6>[ 16.001028] Segment Routing with IPv6
10815 12:48:47.632259 <6>[ 16.005001] In-situ OAM (IOAM) with IPv6
10816 12:48:47.665984 <30>[ 16.019380] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10817 12:48:47.669372 <30>[ 16.043487] systemd[1]: Detected architecture arm64.
10818 12:48:47.672940
10819 12:48:47.676385 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10820 12:48:47.676876
10821 12:48:47.693337 <30>[ 16.065574] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10822 12:48:47.844623 <30>[ 16.214062] systemd[1]: Queued start job for default target Graphical Interface.
10823 12:48:47.886113 <30>[ 16.258938] systemd[1]: Created slice system-getty.slice.
10824 12:48:47.892711 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10825 12:48:47.909201 <30>[ 16.282097] systemd[1]: Created slice system-modprobe.slice.
10826 12:48:47.915558 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10827 12:48:47.933700 <30>[ 16.306543] systemd[1]: Created slice system-serial\x2dgetty.slice.
10828 12:48:47.943366 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10829 12:48:47.956618 <30>[ 16.329952] systemd[1]: Created slice User and Session Slice.
10830 12:48:47.963165 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10831 12:48:47.984238 <30>[ 16.353990] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10832 12:48:47.994258 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10833 12:48:48.012033 <30>[ 16.381930] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10834 12:48:48.018983 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10835 12:48:48.039207 <30>[ 16.405550] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10836 12:48:48.045821 <30>[ 16.417595] systemd[1]: Reached target Local Encrypted Volumes.
10837 12:48:48.052743 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10838 12:48:48.068484 <30>[ 16.441803] systemd[1]: Reached target Paths.
10839 12:48:48.072063 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10840 12:48:48.088221 <30>[ 16.461480] systemd[1]: Reached target Remote File Systems.
10841 12:48:48.094790 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10842 12:48:48.112698 <30>[ 16.485701] systemd[1]: Reached target Slices.
10843 12:48:48.119235 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10844 12:48:48.132765 <30>[ 16.505516] systemd[1]: Reached target Swap.
10845 12:48:48.135782 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10846 12:48:48.155801 <30>[ 16.525783] systemd[1]: Listening on initctl Compatibility Named Pipe.
10847 12:48:48.162410 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10848 12:48:48.169343 <30>[ 16.540504] systemd[1]: Listening on Journal Audit Socket.
10849 12:48:48.175693 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10850 12:48:48.188813 <30>[ 16.561754] systemd[1]: Listening on Journal Socket (/dev/log).
10851 12:48:48.195259 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10852 12:48:48.213226 <30>[ 16.586223] systemd[1]: Listening on Journal Socket.
10853 12:48:48.219602 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10854 12:48:48.236094 <30>[ 16.605858] systemd[1]: Listening on Network Service Netlink Socket.
10855 12:48:48.242325 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10856 12:48:48.256793 <30>[ 16.630188] systemd[1]: Listening on udev Control Socket.
10857 12:48:48.263552 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10858 12:48:48.281152 <30>[ 16.654161] systemd[1]: Listening on udev Kernel Socket.
10859 12:48:48.287848 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10860 12:48:48.324668 <30>[ 16.697827] systemd[1]: Mounting Huge Pages File System...
10861 12:48:48.331145 Mounting [0;1;39mHuge Pages File System[0m...
10862 12:48:48.346512 <30>[ 16.719630] systemd[1]: Mounting POSIX Message Queue File System...
10863 12:48:48.353633 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10864 12:48:48.370250 <30>[ 16.743542] systemd[1]: Mounting Kernel Debug File System...
10865 12:48:48.377233 Mounting [0;1;39mKernel Debug File System[0m...
10866 12:48:48.396244 <30>[ 16.765898] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10867 12:48:48.407203 <30>[ 16.776884] systemd[1]: Starting Create list of static device nodes for the current kernel...
10868 12:48:48.413605 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10869 12:48:48.430514 <30>[ 16.803868] systemd[1]: Starting Load Kernel Module configfs...
10870 12:48:48.437376 Starting [0;1;39mLoad Kernel Module configfs[0m...
10871 12:48:48.454540 <30>[ 16.827674] systemd[1]: Starting Load Kernel Module drm...
10872 12:48:48.460902 Starting [0;1;39mLoad Kernel Module drm[0m...
10873 12:48:48.479758 <30>[ 16.849688] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10874 12:48:48.490311 <30>[ 16.863448] systemd[1]: Starting Journal Service...
10875 12:48:48.493588 Starting [0;1;39mJournal Service[0m...
10876 12:48:48.511211 <30>[ 16.884280] systemd[1]: Starting Load Kernel Modules...
10877 12:48:48.517473 Starting [0;1;39mLoad Kernel Modules[0m...
10878 12:48:48.537986 <30>[ 16.908222] systemd[1]: Starting Remount Root and Kernel File Systems...
10879 12:48:48.545011 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10880 12:48:48.563050 <30>[ 16.936139] systemd[1]: Starting Coldplug All udev Devices...
10881 12:48:48.569375 Starting [0;1;39mColdplug All udev Devices[0m...
10882 12:48:48.586868 <30>[ 16.960281] systemd[1]: Mounted Huge Pages File System.
10883 12:48:48.593264 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10884 12:48:48.608533 <30>[ 16.981963] systemd[1]: Started Journal Service.
10885 12:48:48.615389 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10886 12:48:48.629844 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10887 12:48:48.645329 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10888 12:48:48.665151 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10889 12:48:48.681870 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10890 12:48:48.697924 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10891 12:48:48.713623 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10892 12:48:48.733119 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10893 12:48:48.748362 See 'systemctl status systemd-remount-fs.service' for details.
10894 12:48:48.785961 Mounting [0;1;39mKernel Configuration File System[0m...
10895 12:48:48.802943 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10896 12:48:48.819899 <46>[ 17.190136] systemd-journald[175]: Received client request to flush runtime journal.
10897 12:48:48.828411 Starting [0;1;39mLoad/Save Random Seed[0m...
10898 12:48:48.851163 Starting [0;1;39mApply Kernel Variables[0m...
10899 12:48:48.870855 Starting [0;1;39mCreate System Users[0m...
10900 12:48:48.890375 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10901 12:48:48.917306 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10902 12:48:48.929774 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10903 12:48:48.945922 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10904 12:48:48.961727 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10905 12:48:48.976970 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10906 12:48:49.025445 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10907 12:48:49.047591 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10908 12:48:49.061063 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10909 12:48:49.076524 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10910 12:48:49.117402 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10911 12:48:49.140911 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10912 12:48:49.158321 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10913 12:48:49.181091 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10914 12:48:49.201937 Starting [0;1;39mNetwork Service[0m...
10915 12:48:49.222586 Starting [0;1;39mNetwork Time Synchronization[0m...
10916 12:48:49.235364 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10917 12:48:49.277676 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10918 12:48:49.299515 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10919 12:48:49.334755 Starting [0;1;39mNetwork Name Resolution[0m...
10920 12:48:49.354430 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10921 12:48:49.390472 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10922 12:48:49.410365 <6>[ 17.780051] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10923 12:48:49.423642 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.<6>[ 17.793859] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10924 12:48:49.424365
10925 12:48:49.433073 <3>[ 17.797573] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10926 12:48:49.439994 <3>[ 17.810083] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10927 12:48:49.449445 <6>[ 17.810972] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10928 12:48:49.452861 <6>[ 17.819456] mc: Linux media interface: v0.10
10929 12:48:49.462703 <3>[ 17.822101] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10930 12:48:49.469444 <3>[ 17.822233] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10931 12:48:49.479172 <3>[ 17.822242] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10932 12:48:49.486250 <3>[ 17.822249] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10933 12:48:49.492619 <3>[ 17.822260] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10934 12:48:49.502581 <3>[ 17.822268] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10935 12:48:49.509485 <3>[ 17.822324] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10936 12:48:49.519114 <3>[ 17.822382] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10937 12:48:49.526008 <3>[ 17.822390] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10938 12:48:49.536044 <3>[ 17.822397] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10939 12:48:49.542579 <3>[ 17.822450] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10940 12:48:49.552757 <3>[ 17.822458] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10941 12:48:49.558843 <3>[ 17.822465] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10942 12:48:49.565168 <3>[ 17.822472] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10943 12:48:49.575573 <3>[ 17.822478] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10944 12:48:49.581700 <3>[ 17.822516] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10945 12:48:49.591618 <6>[ 17.827123] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10946 12:48:49.598965 <4>[ 17.828027] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10947 12:48:49.605100 <4>[ 17.833392] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10948 12:48:49.611943 <6>[ 17.834218] remoteproc remoteproc0: scp is available
10949 12:48:49.617980 <6>[ 17.834306] remoteproc remoteproc0: powering up scp
10950 12:48:49.624816 <6>[ 17.834312] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10951 12:48:49.631509 <6>[ 17.834326] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10952 12:48:49.638267 <6>[ 17.858854] usbcore: registered new interface driver r8152
10953 12:48:49.641369 <6>[ 17.953312] videodev: Linux video capture interface: v2.00
10954 12:48:49.651777 <6>[ 17.953486] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10955 12:48:49.658752 <6>[ 17.958506] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10956 12:48:49.661914 <6>[ 17.958515] pci_bus 0000:00: root bus resource [bus 00-ff]
10957 12:48:49.671786 <6>[ 17.958521] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10958 12:48:49.681243 <6>[ 17.958527] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10959 12:48:49.688315 <6>[ 17.958561] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10960 12:48:49.695036 <6>[ 17.958582] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10961 12:48:49.699039 <6>[ 17.958674] pci 0000:00:00.0: supports D1 D2
10962 12:48:49.706205 <6>[ 17.958678] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10963 12:48:49.715578 <6>[ 17.959835] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10964 12:48:49.722141 <6>[ 17.959844] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10965 12:48:49.728760 <6>[ 17.959850] remoteproc remoteproc0: remote processor scp is now up
10966 12:48:49.735516 <6>[ 17.960706] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10967 12:48:49.742685 <6>[ 17.960864] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10968 12:48:49.748728 <6>[ 17.960899] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10969 12:48:49.758842 <6>[ 17.960920] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10970 12:48:49.765139 <6>[ 17.960940] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10971 12:48:49.768641 <6>[ 17.961100] pci 0000:01:00.0: supports D1 D2
10972 12:48:49.777991 <6>[ 17.973943] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10973 12:48:49.784974 <6>[ 17.977606] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10974 12:48:49.795646 <4>[ 17.988969] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10975 12:48:49.799222 <4>[ 17.988969] Fallback method does not support PEC.
10976 12:48:49.806685 <6>[ 18.001311] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10977 12:48:49.813600 <6>[ 18.005848] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10978 12:48:49.819936 <6>[ 18.009265] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10979 12:48:49.830081 <3>[ 18.031755] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 12:48:49.839930 <6>[ 18.035619] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10981 12:48:49.849961 <6>[ 18.053771] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10982 12:48:49.856930 <6>[ 18.058396] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10983 12:48:49.867010 <6>[ 18.065065] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10984 12:48:49.873902 <6>[ 18.072115] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10985 12:48:49.883549 <3>[ 18.080437] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10986 12:48:49.890115 <6>[ 18.084211] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10987 12:48:49.896818 <3>[ 18.092793] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10988 12:48:49.903202 <6>[ 18.099940] pci 0000:00:00.0: PCI bridge to [bus 01]
10989 12:48:49.910026 <6>[ 18.100421] usbcore: registered new interface driver cdc_ether
10990 12:48:49.916446 <6>[ 18.106318] usbcore: registered new interface driver r8153_ecm
10991 12:48:49.923330 <6>[ 18.113925] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10992 12:48:49.926054 <6>[ 18.114808] Bluetooth: Core ver 2.22
10993 12:48:49.933336 <6>[ 18.114883] NET: Registered PF_BLUETOOTH protocol family
10994 12:48:49.939804 <6>[ 18.114887] Bluetooth: HCI device and connection manager initialized
10995 12:48:49.943332 <6>[ 18.114904] Bluetooth: HCI socket layer initialized
10996 12:48:49.949510 <6>[ 18.114910] Bluetooth: L2CAP socket layer initialized
10997 12:48:49.956382 <6>[ 18.114921] Bluetooth: SCO socket layer initialized
10998 12:48:49.962909 <6>[ 18.116403] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10999 12:48:49.972926 <6>[ 18.118192] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11000 12:48:49.979385 <6>[ 18.134028] r8152 1-1.1.1:1.0: load rtl8153b-2 v1 10/23/19 successfully
11001 12:48:49.985925 <6>[ 18.135808] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11002 12:48:49.993042 <6>[ 18.148694] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11003 12:48:49.995799 <6>[ 18.148927] usbcore: registered new interface driver btusb
11004 12:48:50.008981 <4>[ 18.149824] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11005 12:48:50.015804 <3>[ 18.149833] Bluetooth: hci0: Failed to load firmware file (-2)
11006 12:48:50.019308 <3>[ 18.149837] Bluetooth: hci0: Failed to set up firmware (-2)
11007 12:48:50.028984 <4>[ 18.149856] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11008 12:48:50.035665 <6>[ 18.157885] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11009 12:48:50.048776 <6>[ 18.165012] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11010 12:48:50.058942 <3>[ 18.174210] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11011 12:48:50.062111 <6>[ 18.177700] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11012 12:48:50.068402 <6>[ 18.178549] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11013 12:48:50.078388 <3>[ 18.181473] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11014 12:48:50.088336 <3>[ 18.182341] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11015 12:48:50.094688 <6>[ 18.184772] usbcore: registered new interface driver uvcvideo
11016 12:48:50.098700 <6>[ 18.193279] r8152 1-1.1.1:1.0 eth0: v1.12.13
11017 12:48:50.104899 <5>[ 18.211838] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11018 12:48:50.111766 <6>[ 18.230050] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
11019 12:48:50.117868 <5>[ 18.245588] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11020 12:48:50.128184 <3>[ 18.251906] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11021 12:48:50.134418 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11022 12:48:50.160392 <3>[ 18.529948] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11023 12:48:50.170826 <4>[ 18.540332] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11024 12:48:50.177468 <6>[ 18.549277] cfg80211: failed to load regulatory.db
11025 12:48:50.191221 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m..<3>[ 18.560598] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11026 12:48:50.191748 .
11027 12:48:50.216860 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m<6>[ 18.587943] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11028 12:48:50.217391 .
11029 12:48:50.226703 <3>[ 18.594231] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11030 12:48:50.233305 <6>[ 18.596024] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11031 12:48:50.243214 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11032 12:48:50.258809 <6>[ 18.631682] mt7921e 0000:01:00.0: ASIC revision: 79610010
11033 12:48:50.265080 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11034 12:48:50.366718 <4>[ 18.733013] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11035 12:48:50.443053 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11036 12:48:50.456416 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11037 12:48:50.490959 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Nam<4>[ 18.856433] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11038 12:48:50.491538 e Lookups[0m.
11039 12:48:50.505785 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11040 12:48:50.524122 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11041 12:48:50.539745 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11042 12:48:50.552627 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11043 12:48:50.572336 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11044 12:48:50.585036 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11045 12:48:50.611291 [[0;32m OK [0m] Reached targ<4>[ 18.975828] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11046 12:48:50.614859 et [0;1;39mBasic System[0m.
11047 12:48:50.633946 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11048 12:48:50.665058 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11049 12:48:50.691188 Starting [0;1;39mUser Login Management[0m...
11050 12:48:50.706993 Starting [0;1;39mPermit User Sessions[0m...
11051 12:48:50.731787 <4>[ 19.098271] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11052 12:48:50.738287 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11053 12:48:50.747102 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11054 12:48:50.759301 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11055 12:48:50.778473 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11056 12:48:50.796766 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11057 12:48:50.816948 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11058 12:48:50.853624 [[0;32m OK [0m] Started [0;1;39mUser Login <4>[ 19.220656] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11059 12:48:50.856481 Management[0m.
11060 12:48:50.875719 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11061 12:48:50.896787 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11062 12:48:50.952770 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11063 12:48:50.974990 <4>[ 19.341297] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11064 12:48:50.981589 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11065 12:48:51.003574
11066 12:48:51.004142
11067 12:48:51.006904 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11068 12:48:51.007408
11069 12:48:51.010137 debian-bullseye-arm64 login: root (automatic login)
11070 12:48:51.010630
11071 12:48:51.011008
11072 12:48:51.026913 Linux debian-bullseye-arm64 6.1.38-cip1 #1 SMP PREEMPT Thu Jul 20 12:35:57 UTC 2023 aarch64
11073 12:48:51.027465
11074 12:48:51.033283 The programs included with the Debian GNU/Linux system are free software;
11075 12:48:51.039969 the exact distribution terms for each program are described in the
11076 12:48:51.043244 individual files in /usr/share/doc/*/copyright.
11077 12:48:51.043705
11078 12:48:51.049998 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11079 12:48:51.053143 permitted by applicable law.
11080 12:48:51.093154 / # <4>[ 19.459777] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11081 12:48:51.213403 <4>[ 19.579909] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11082 12:48:51.333652 <4>[ 19.699893] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11083 12:48:51.453058 <4>[ 19.819871] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11084 12:48:51.473692 <6>[ 19.843526] IPv6: ADDRCONF(NETDEV_CHANGE): enxf4f5e850de0a: link becomes ready
11085 12:48:51.479902 <6>[ 19.851526] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
11086 12:48:51.564353 <3>[ 19.937589] mt7921e 0000:01:00.0: hardware init failed
11087 12:49:17.773678 <6>[ 46.153503] vpu: disabling
11088 12:49:17.776590 <6>[ 46.156561] vproc2: disabling
11089 12:49:17.780059 <6>[ 46.159841] vproc1: disabling
11090 12:49:17.783425 <6>[ 46.163107] vaud18: disabling
11091 12:49:17.789836 <6>[ 46.166516] vsram_others: disabling
11092 12:49:17.793081 <6>[ 46.170394] va09: disabling
11093 12:49:17.796517 <6>[ 46.173499] vsram_md: disabling
11094 12:49:17.799456 <6>[ 46.176984] Vgpu: disabling
11096 12:52:20.982752 end: 2.2.5 auto-login-action (duration 00:03:49) [common]
11098 12:52:20.982956 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 229 seconds'
11100 12:52:20.983109 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
11103 12:52:20.983356 end: 2 depthcharge-action (duration 00:05:00) [common]
11105 12:52:20.983569 Cleaning after the job
11106 12:52:20.983661 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11118904/tftp-deploy-3o_274nx/ramdisk
11107 12:52:20.989824 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11118904/tftp-deploy-3o_274nx/kernel
11108 12:52:21.005014 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11118904/tftp-deploy-3o_274nx/dtb
11109 12:52:21.005200 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11118904/tftp-deploy-3o_274nx/modules
11110 12:52:21.011992 start: 4.1 power-off (timeout 00:00:30) [common]
11111 12:52:21.012159 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11112 12:52:21.090542 >> Command sent successfully.
11113 12:52:21.092890 Returned 0 in 0 seconds
11114 12:52:21.193304 end: 4.1 power-off (duration 00:00:00) [common]
11116 12:52:21.193751 start: 4.2 read-feedback (timeout 00:10:00) [common]
11117 12:52:21.194089 Listened to connection for namespace 'common' for up to 1s
11118 12:52:22.194701 Finalising connection for namespace 'common'
11119 12:52:22.194931 Disconnecting from shell: Finalise
11120 12:52:22.295282 end: 4.2 read-feedback (duration 00:00:01) [common]
11121 12:52:22.295483 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11118904
11122 12:52:22.423392 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11118904
11123 12:52:22.423580 JobError: Your job cannot terminate cleanly.