Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 41
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 27
- Warnings: 1
1 12:46:36.442212 lava-dispatcher, installed at version: 2023.05.1
2 12:46:36.442418 start: 0 validate
3 12:46:36.442545 Start time: 2023-07-20 12:46:36.442537+00:00 (UTC)
4 12:46:36.442667 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:46:36.442797 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 12:46:36.702450 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:46:36.702640 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.38-cip1-7-g5cff59cac977b%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:46:57.711265 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:46:57.711471 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.38-cip1-7-g5cff59cac977b%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:46:57.978470 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:46:57.979199 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:46:58.506355 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:46:58.506567 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.38-cip1-7-g5cff59cac977b%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:47:05.510609 validate duration: 29.07
16 12:47:05.510927 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:47:05.511053 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:47:05.511159 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:47:05.511328 Not decompressing ramdisk as can be used compressed.
20 12:47:05.511434 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 12:47:05.511513 saving as /var/lib/lava/dispatcher/tmp/11118924/tftp-deploy-pu23uz5a/ramdisk/initrd.cpio.gz
22 12:47:05.511605 total size: 4665412 (4MB)
23 12:47:05.777016 progress 0% (0MB)
24 12:47:05.778559 progress 5% (0MB)
25 12:47:05.779893 progress 10% (0MB)
26 12:47:05.781215 progress 15% (0MB)
27 12:47:05.782555 progress 20% (0MB)
28 12:47:05.783867 progress 25% (1MB)
29 12:47:05.785145 progress 30% (1MB)
30 12:47:05.786399 progress 35% (1MB)
31 12:47:05.787679 progress 40% (1MB)
32 12:47:05.789069 progress 45% (2MB)
33 12:47:05.790324 progress 50% (2MB)
34 12:47:05.791641 progress 55% (2MB)
35 12:47:05.792864 progress 60% (2MB)
36 12:47:05.794094 progress 65% (2MB)
37 12:47:05.795313 progress 70% (3MB)
38 12:47:05.796569 progress 75% (3MB)
39 12:47:05.797795 progress 80% (3MB)
40 12:47:05.799184 progress 85% (3MB)
41 12:47:05.800453 progress 90% (4MB)
42 12:47:05.801674 progress 95% (4MB)
43 12:47:05.802941 progress 100% (4MB)
44 12:47:05.803098 4MB downloaded in 0.29s (15.26MB/s)
45 12:47:05.803248 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:47:05.803489 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:47:05.803618 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:47:05.803704 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:47:05.803842 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.38-cip1-7-g5cff59cac977b/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:47:05.803912 saving as /var/lib/lava/dispatcher/tmp/11118924/tftp-deploy-pu23uz5a/kernel/Image
52 12:47:05.803971 total size: 48564736 (46MB)
53 12:47:05.804030 No compression specified
54 12:47:05.805132 progress 0% (0MB)
55 12:47:05.817831 progress 5% (2MB)
56 12:47:05.830483 progress 10% (4MB)
57 12:47:05.843609 progress 15% (6MB)
58 12:47:05.856598 progress 20% (9MB)
59 12:47:05.869427 progress 25% (11MB)
60 12:47:05.882477 progress 30% (13MB)
61 12:47:05.895242 progress 35% (16MB)
62 12:47:05.907842 progress 40% (18MB)
63 12:47:05.920593 progress 45% (20MB)
64 12:47:05.933751 progress 50% (23MB)
65 12:47:05.946682 progress 55% (25MB)
66 12:47:05.959654 progress 60% (27MB)
67 12:47:05.972463 progress 65% (30MB)
68 12:47:05.985379 progress 70% (32MB)
69 12:47:05.997962 progress 75% (34MB)
70 12:47:06.010459 progress 80% (37MB)
71 12:47:06.022923 progress 85% (39MB)
72 12:47:06.035941 progress 90% (41MB)
73 12:47:06.049389 progress 95% (44MB)
74 12:47:06.062462 progress 100% (46MB)
75 12:47:06.062630 46MB downloaded in 0.26s (179.06MB/s)
76 12:47:06.062782 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:47:06.063020 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:47:06.063106 start: 1.3 download-retry (timeout 00:09:59) [common]
80 12:47:06.063197 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 12:47:06.063328 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.38-cip1-7-g5cff59cac977b/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:47:06.063399 saving as /var/lib/lava/dispatcher/tmp/11118924/tftp-deploy-pu23uz5a/dtb/mt8192-asurada-spherion-r0.dtb
83 12:47:06.063459 total size: 46924 (0MB)
84 12:47:06.063541 No compression specified
85 12:47:06.064661 progress 69% (0MB)
86 12:47:06.064934 progress 100% (0MB)
87 12:47:06.065088 0MB downloaded in 0.00s (27.53MB/s)
88 12:47:06.065207 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:47:06.065429 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:47:06.065513 start: 1.4 download-retry (timeout 00:09:59) [common]
92 12:47:06.065592 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 12:47:06.065704 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 12:47:06.065771 saving as /var/lib/lava/dispatcher/tmp/11118924/tftp-deploy-pu23uz5a/nfsrootfs/full.rootfs.tar
95 12:47:06.065831 total size: 125290964 (119MB)
96 12:47:06.065889 Using unxz to decompress xz
97 12:47:06.070013 progress 0% (0MB)
98 12:47:06.409629 progress 5% (6MB)
99 12:47:06.751716 progress 10% (11MB)
100 12:47:07.086997 progress 15% (17MB)
101 12:47:07.274945 progress 20% (23MB)
102 12:47:07.453434 progress 25% (29MB)
103 12:47:07.809023 progress 30% (35MB)
104 12:47:08.174772 progress 35% (41MB)
105 12:47:08.569188 progress 40% (47MB)
106 12:47:08.957286 progress 45% (53MB)
107 12:47:09.357251 progress 50% (59MB)
108 12:47:09.719615 progress 55% (65MB)
109 12:47:10.098844 progress 60% (71MB)
110 12:47:10.448562 progress 65% (77MB)
111 12:47:10.826248 progress 70% (83MB)
112 12:47:11.225654 progress 75% (89MB)
113 12:47:11.669690 progress 80% (95MB)
114 12:47:12.108916 progress 85% (101MB)
115 12:47:12.366102 progress 90% (107MB)
116 12:47:12.708335 progress 95% (113MB)
117 12:47:13.082799 progress 100% (119MB)
118 12:47:13.088399 119MB downloaded in 7.02s (17.01MB/s)
119 12:47:13.088796 end: 1.4.1 http-download (duration 00:00:07) [common]
121 12:47:13.089205 end: 1.4 download-retry (duration 00:00:07) [common]
122 12:47:13.089336 start: 1.5 download-retry (timeout 00:09:52) [common]
123 12:47:13.089468 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 12:47:13.089682 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.38-cip1-7-g5cff59cac977b/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:47:13.089793 saving as /var/lib/lava/dispatcher/tmp/11118924/tftp-deploy-pu23uz5a/modules/modules.tar
126 12:47:13.089894 total size: 8543056 (8MB)
127 12:47:13.089995 Using unxz to decompress xz
128 12:47:13.358752 progress 0% (0MB)
129 12:47:13.380317 progress 5% (0MB)
130 12:47:13.405544 progress 10% (0MB)
131 12:47:13.429314 progress 15% (1MB)
132 12:47:13.456823 progress 20% (1MB)
133 12:47:13.482784 progress 25% (2MB)
134 12:47:13.508705 progress 30% (2MB)
135 12:47:13.534106 progress 35% (2MB)
136 12:47:13.559840 progress 40% (3MB)
137 12:47:13.585732 progress 45% (3MB)
138 12:47:13.610039 progress 50% (4MB)
139 12:47:13.635366 progress 55% (4MB)
140 12:47:13.660645 progress 60% (4MB)
141 12:47:13.686059 progress 65% (5MB)
142 12:47:13.714408 progress 70% (5MB)
143 12:47:13.744259 progress 75% (6MB)
144 12:47:13.770042 progress 80% (6MB)
145 12:47:13.795228 progress 85% (6MB)
146 12:47:13.819897 progress 90% (7MB)
147 12:47:13.844834 progress 95% (7MB)
148 12:47:13.870840 progress 100% (8MB)
149 12:47:13.876994 8MB downloaded in 0.79s (10.35MB/s)
150 12:47:13.877313 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:47:13.877582 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:47:13.877675 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 12:47:13.877768 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 12:47:16.095711 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11118924/extract-nfsrootfs-0csouspo
156 12:47:16.095952 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 12:47:16.096122 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 12:47:16.096327 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte
159 12:47:16.096482 makedir: /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin
160 12:47:16.096600 makedir: /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/tests
161 12:47:16.096718 makedir: /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/results
162 12:47:16.096839 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-add-keys
163 12:47:16.097035 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-add-sources
164 12:47:16.097214 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-background-process-start
165 12:47:16.097386 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-background-process-stop
166 12:47:16.097535 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-common-functions
167 12:47:16.097684 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-echo-ipv4
168 12:47:16.097855 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-install-packages
169 12:47:16.098000 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-installed-packages
170 12:47:16.098144 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-os-build
171 12:47:16.098290 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-probe-channel
172 12:47:16.098440 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-probe-ip
173 12:47:16.098613 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-target-ip
174 12:47:16.098785 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-target-mac
175 12:47:16.098958 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-target-storage
176 12:47:16.099132 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-test-case
177 12:47:16.099281 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-test-event
178 12:47:16.099436 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-test-feedback
179 12:47:16.099647 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-test-raise
180 12:47:16.099795 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-test-reference
181 12:47:16.099941 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-test-runner
182 12:47:16.100090 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-test-set
183 12:47:16.100264 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-test-shell
184 12:47:16.100436 Updating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-install-packages (oe)
185 12:47:16.100615 Updating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/bin/lava-installed-packages (oe)
186 12:47:16.100760 Creating /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/environment
187 12:47:16.100890 LAVA metadata
188 12:47:16.101012 - LAVA_JOB_ID=11118924
189 12:47:16.101114 - LAVA_DISPATCHER_IP=192.168.201.1
190 12:47:16.101280 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
191 12:47:16.101381 skipped lava-vland-overlay
192 12:47:16.101503 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 12:47:16.101627 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
194 12:47:16.101732 skipped lava-multinode-overlay
195 12:47:16.101852 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 12:47:16.101976 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
197 12:47:16.102093 Loading test definitions
198 12:47:16.102234 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
199 12:47:16.102342 Using /lava-11118924 at stage 0
200 12:47:16.102793 uuid=11118924_1.6.2.3.1 testdef=None
201 12:47:16.102918 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 12:47:16.103045 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
203 12:47:16.103822 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 12:47:16.104107 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
206 12:47:16.104801 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 12:47:16.105067 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
209 12:47:16.105717 runner path: /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/0/tests/0_dmesg test_uuid 11118924_1.6.2.3.1
210 12:47:16.105893 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 12:47:16.106153 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:49) [common]
213 12:47:16.106262 Using /lava-11118924 at stage 1
214 12:47:16.106707 uuid=11118924_1.6.2.3.5 testdef=None
215 12:47:16.106832 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 12:47:16.106958 start: 1.6.2.3.6 test-overlay (timeout 00:09:49) [common]
217 12:47:16.107783 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 12:47:16.108064 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:49) [common]
220 12:47:16.108756 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 12:47:16.109020 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:49) [common]
223 12:47:16.109681 runner path: /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/1/tests/1_bootrr test_uuid 11118924_1.6.2.3.5
224 12:47:16.109853 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 12:47:16.110088 Creating lava-test-runner.conf files
227 12:47:16.110190 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/0 for stage 0
228 12:47:16.110331 - 0_dmesg
229 12:47:16.110448 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11118924/lava-overlay-dk6i_kte/lava-11118924/1 for stage 1
230 12:47:16.110590 - 1_bootrr
231 12:47:16.110730 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 12:47:16.110860 start: 1.6.2.4 compress-overlay (timeout 00:09:49) [common]
233 12:47:16.120174 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 12:47:16.120341 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:49) [common]
235 12:47:16.120467 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 12:47:16.120576 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 12:47:16.120681 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:49) [common]
238 12:47:16.244020 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 12:47:16.244392 start: 1.6.4 extract-modules (timeout 00:09:49) [common]
240 12:47:16.244516 extracting modules file /var/lib/lava/dispatcher/tmp/11118924/tftp-deploy-pu23uz5a/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11118924/extract-nfsrootfs-0csouspo
241 12:47:16.471711 extracting modules file /var/lib/lava/dispatcher/tmp/11118924/tftp-deploy-pu23uz5a/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11118924/extract-overlay-ramdisk-krq0t21a/ramdisk
242 12:47:16.702763 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 12:47:16.702958 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 12:47:16.703075 [common] Applying overlay to NFS
245 12:47:16.703158 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11118924/compress-overlay-f4cdvw4n/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11118924/extract-nfsrootfs-0csouspo
246 12:47:16.711239 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 12:47:16.711400 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 12:47:16.711614 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 12:47:16.711715 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 12:47:16.711799 Building ramdisk /var/lib/lava/dispatcher/tmp/11118924/extract-overlay-ramdisk-krq0t21a/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11118924/extract-overlay-ramdisk-krq0t21a/ramdisk
251 12:47:17.048547 >> 117852 blocks
252 12:47:18.981297 rename /var/lib/lava/dispatcher/tmp/11118924/extract-overlay-ramdisk-krq0t21a/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11118924/tftp-deploy-pu23uz5a/ramdisk/ramdisk.cpio.gz
253 12:47:18.981748 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 12:47:18.981879 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 12:47:18.981983 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 12:47:18.982092 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11118924/tftp-deploy-pu23uz5a/kernel/Image'
257 12:47:32.179354 Returned 0 in 13 seconds
258 12:47:32.280008 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11118924/tftp-deploy-pu23uz5a/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11118924/tftp-deploy-pu23uz5a/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11118924/tftp-deploy-pu23uz5a/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11118924/tftp-deploy-pu23uz5a/kernel/image.itb
259 12:47:32.634829 output: FIT description: Kernel Image image with one or more FDT blobs
260 12:47:32.635203 output: Created: Thu Jul 20 13:47:32 2023
261 12:47:32.635281 output: Image 0 (kernel-1)
262 12:47:32.635347 output: Description:
263 12:47:32.635412 output: Created: Thu Jul 20 13:47:32 2023
264 12:47:32.635475 output: Type: Kernel Image
265 12:47:32.635582 output: Compression: lzma compressed
266 12:47:32.635646 output: Data Size: 10808178 Bytes = 10554.86 KiB = 10.31 MiB
267 12:47:32.635708 output: Architecture: AArch64
268 12:47:32.635769 output: OS: Linux
269 12:47:32.635828 output: Load Address: 0x00000000
270 12:47:32.635887 output: Entry Point: 0x00000000
271 12:47:32.635944 output: Hash algo: crc32
272 12:47:32.635999 output: Hash value: 96f4d49d
273 12:47:32.636053 output: Image 1 (fdt-1)
274 12:47:32.636107 output: Description: mt8192-asurada-spherion-r0
275 12:47:32.636160 output: Created: Thu Jul 20 13:47:32 2023
276 12:47:32.636214 output: Type: Flat Device Tree
277 12:47:32.636268 output: Compression: uncompressed
278 12:47:32.636324 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
279 12:47:32.636377 output: Architecture: AArch64
280 12:47:32.636430 output: Hash algo: crc32
281 12:47:32.636483 output: Hash value: 1df858fa
282 12:47:32.636537 output: Image 2 (ramdisk-1)
283 12:47:32.636590 output: Description: unavailable
284 12:47:32.636643 output: Created: Thu Jul 20 13:47:32 2023
285 12:47:32.636696 output: Type: RAMDisk Image
286 12:47:32.636750 output: Compression: Unknown Compression
287 12:47:32.636803 output: Data Size: 17644299 Bytes = 17230.76 KiB = 16.83 MiB
288 12:47:32.636857 output: Architecture: AArch64
289 12:47:32.636910 output: OS: Linux
290 12:47:32.636963 output: Load Address: unavailable
291 12:47:32.637016 output: Entry Point: unavailable
292 12:47:32.637069 output: Hash algo: crc32
293 12:47:32.637121 output: Hash value: 024e3876
294 12:47:32.637175 output: Default Configuration: 'conf-1'
295 12:47:32.637228 output: Configuration 0 (conf-1)
296 12:47:32.637281 output: Description: mt8192-asurada-spherion-r0
297 12:47:32.637334 output: Kernel: kernel-1
298 12:47:32.637386 output: Init Ramdisk: ramdisk-1
299 12:47:32.637439 output: FDT: fdt-1
300 12:47:32.637492 output: Loadables: kernel-1
301 12:47:32.637545 output:
302 12:47:32.637758 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
303 12:47:32.637857 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
304 12:47:32.637962 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
305 12:47:32.638055 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:33) [common]
306 12:47:32.638135 No LXC device requested
307 12:47:32.638213 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 12:47:32.638301 start: 1.8 deploy-device-env (timeout 00:09:33) [common]
309 12:47:32.638378 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 12:47:32.638449 Checking files for TFTP limit of 4294967296 bytes.
311 12:47:32.638969 end: 1 tftp-deploy (duration 00:00:27) [common]
312 12:47:32.639078 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 12:47:32.639174 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 12:47:32.639304 substitutions:
315 12:47:32.639370 - {DTB}: 11118924/tftp-deploy-pu23uz5a/dtb/mt8192-asurada-spherion-r0.dtb
316 12:47:32.639432 - {INITRD}: 11118924/tftp-deploy-pu23uz5a/ramdisk/ramdisk.cpio.gz
317 12:47:32.639491 - {KERNEL}: 11118924/tftp-deploy-pu23uz5a/kernel/Image
318 12:47:32.639587 - {LAVA_MAC}: None
319 12:47:32.639644 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11118924/extract-nfsrootfs-0csouspo
320 12:47:32.639701 - {NFS_SERVER_IP}: 192.168.201.1
321 12:47:32.639757 - {PRESEED_CONFIG}: None
322 12:47:32.639812 - {PRESEED_LOCAL}: None
323 12:47:32.639867 - {RAMDISK}: 11118924/tftp-deploy-pu23uz5a/ramdisk/ramdisk.cpio.gz
324 12:47:32.639923 - {ROOT_PART}: None
325 12:47:32.639978 - {ROOT}: None
326 12:47:32.640032 - {SERVER_IP}: 192.168.201.1
327 12:47:32.640087 - {TEE}: None
328 12:47:32.640141 Parsed boot commands:
329 12:47:32.640195 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 12:47:32.640382 Parsed boot commands: tftpboot 192.168.201.1 11118924/tftp-deploy-pu23uz5a/kernel/image.itb 11118924/tftp-deploy-pu23uz5a/kernel/cmdline
331 12:47:32.640540 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 12:47:32.640626 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 12:47:32.640719 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 12:47:32.640808 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 12:47:32.640879 Not connected, no need to disconnect.
336 12:47:32.640956 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 12:47:32.641038 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 12:47:32.641105 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
339 12:47:32.645159 Setting prompt string to ['lava-test: # ']
340 12:47:32.645537 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 12:47:32.645648 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 12:47:32.645744 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 12:47:32.645836 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 12:47:32.646034 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
345 12:47:37.777477 >> Command sent successfully.
346 12:47:37.780840 Returned 0 in 5 seconds
347 12:47:37.881343 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 12:47:37.881862 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 12:47:37.882008 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 12:47:37.882151 Setting prompt string to 'Starting depthcharge on Spherion...'
352 12:47:37.882272 Changing prompt to 'Starting depthcharge on Spherion...'
353 12:47:37.882381 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 12:47:37.882831 [Enter `^Ec?' for help]
355 12:47:38.055369
356 12:47:38.055598
357 12:47:38.055708 F0: 102B 0000
358 12:47:38.055813
359 12:47:38.055919 F3: 1001 0000 [0200]
360 12:47:38.056021
361 12:47:38.059024 F3: 1001 0000
362 12:47:38.059205
363 12:47:38.059306 F7: 102D 0000
364 12:47:38.059406
365 12:47:38.059495 F1: 0000 0000
366 12:47:38.059612
367 12:47:38.062875 V0: 0000 0000 [0001]
368 12:47:38.063090
369 12:47:38.063215 00: 0007 8000
370 12:47:38.063345
371 12:47:38.066873 01: 0000 0000
372 12:47:38.067079
373 12:47:38.067187 BP: 0C00 0209 [0000]
374 12:47:38.067280
375 12:47:38.067384 G0: 1182 0000
376 12:47:38.070232
377 12:47:38.070436 EC: 0000 0021 [4000]
378 12:47:38.070542
379 12:47:38.073903 S7: 0000 0000 [0000]
380 12:47:38.074100
381 12:47:38.074213 CC: 0000 0000 [0001]
382 12:47:38.074314
383 12:47:38.077272 T0: 0000 0040 [010F]
384 12:47:38.077468
385 12:47:38.077581 Jump to BL
386 12:47:38.077676
387 12:47:38.102137
388 12:47:38.102328
389 12:47:38.102436
390 12:47:38.109901 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 12:47:38.113468 ARM64: Exception handlers installed.
392 12:47:38.117056 ARM64: Testing exception
393 12:47:38.120795 ARM64: Done test exception
394 12:47:38.128714 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 12:47:38.134968 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 12:47:38.145371 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 12:47:38.155155 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 12:47:38.161918 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 12:47:38.168501 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 12:47:38.178986 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 12:47:38.185863 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 12:47:38.204814 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 12:47:38.208214 WDT: Last reset was cold boot
404 12:47:38.211673 SPI1(PAD0) initialized at 2873684 Hz
405 12:47:38.215146 SPI5(PAD0) initialized at 992727 Hz
406 12:47:38.218562 VBOOT: Loading verstage.
407 12:47:38.224809 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 12:47:38.228717 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 12:47:38.231807 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 12:47:38.235013 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 12:47:38.242672 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 12:47:38.248981 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 12:47:38.259886 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
414 12:47:38.260054
415 12:47:38.260133
416 12:47:38.270710 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 12:47:38.274013 ARM64: Exception handlers installed.
418 12:47:38.277631 ARM64: Testing exception
419 12:47:38.277823 ARM64: Done test exception
420 12:47:38.284340 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 12:47:38.287080 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:47:38.301247 Probing TPM: . done!
423 12:47:38.301442 TPM ready after 0 ms
424 12:47:38.308566 Connected to device vid:did:rid of 1ae0:0028:00
425 12:47:38.315436 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
426 12:47:38.376101 Initialized TPM device CR50 revision 0
427 12:47:38.385560 tlcl_send_startup: Startup return code is 0
428 12:47:38.385771 TPM: setup succeeded
429 12:47:38.396985 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 12:47:38.405663 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 12:47:38.420064 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 12:47:38.427247 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 12:47:38.430615 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 12:47:38.433602 in-header: 03 07 00 00 08 00 00 00
435 12:47:38.437707 in-data: aa e4 47 04 13 02 00 00
436 12:47:38.441029 Chrome EC: UHEPI supported
437 12:47:38.448442 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 12:47:38.452226 in-header: 03 95 00 00 08 00 00 00
439 12:47:38.455965 in-data: 18 20 20 08 00 00 00 00
440 12:47:38.456184 Phase 1
441 12:47:38.459836 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 12:47:38.466887 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 12:47:38.470724 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 12:47:38.474726 Recovery requested (1009000e)
445 12:47:38.482262 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 12:47:38.487796 tlcl_extend: response is 0
447 12:47:38.497526 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 12:47:38.502819 tlcl_extend: response is 0
449 12:47:38.510432 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 12:47:38.529625 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
451 12:47:38.536955 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 12:47:38.537178
453 12:47:38.537299
454 12:47:38.546898 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 12:47:38.549899 ARM64: Exception handlers installed.
456 12:47:38.553383 ARM64: Testing exception
457 12:47:38.553588 ARM64: Done test exception
458 12:47:38.575272 pmic_efuse_setting: Set efuses in 11 msecs
459 12:47:38.578809 pmwrap_interface_init: Select PMIF_VLD_RDY
460 12:47:38.585274 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 12:47:38.588738 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 12:47:38.596368 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 12:47:38.599812 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 12:47:38.603297 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 12:47:38.610816 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 12:47:38.614586 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 12:47:38.618664 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 12:47:38.622196 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 12:47:38.629680 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 12:47:38.633555 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 12:47:38.637165 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 12:47:38.641048 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 12:47:38.648247 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 12:47:38.652232 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 12:47:38.659250 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 12:47:38.663371 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 12:47:38.671218 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 12:47:38.674824 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 12:47:38.682575 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 12:47:38.686010 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 12:47:38.693613 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 12:47:38.696925 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 12:47:38.704712 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 12:47:38.708204 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 12:47:38.715804 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 12:47:38.719357 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 12:47:38.723317 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 12:47:38.730484 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 12:47:38.734721 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 12:47:38.737914 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 12:47:38.745092 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 12:47:38.748701 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 12:47:38.756199 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 12:47:38.759963 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 12:47:38.763709 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 12:47:38.771096 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 12:47:38.774892 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 12:47:38.778621 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 12:47:38.781976 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 12:47:38.785777 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 12:47:38.793123 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 12:47:38.797104 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 12:47:38.800704 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 12:47:38.804220 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 12:47:38.811191 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 12:47:38.814966 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 12:47:38.818707 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 12:47:38.822130 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 12:47:38.825725 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 12:47:38.829555 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 12:47:38.836527 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 12:47:38.847931 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 12:47:38.851757 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 12:47:38.859149 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 12:47:38.866273 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 12:47:38.874308 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 12:47:38.877944 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 12:47:38.881257 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 12:47:38.888878 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x19
520 12:47:38.892380 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 12:47:38.900956 [RTC]rtc_osc_init,62: osc32con val = 0xde70
522 12:47:38.903747 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 12:47:38.913309 [RTC]rtc_get_frequency_meter,154: input=15, output=758
524 12:47:38.922973 [RTC]rtc_get_frequency_meter,154: input=23, output=942
525 12:47:38.931741 [RTC]rtc_get_frequency_meter,154: input=19, output=849
526 12:47:38.941865 [RTC]rtc_get_frequency_meter,154: input=17, output=806
527 12:47:38.951236 [RTC]rtc_get_frequency_meter,154: input=16, output=782
528 12:47:38.960852 [RTC]rtc_get_frequency_meter,154: input=16, output=782
529 12:47:38.970874 [RTC]rtc_get_frequency_meter,154: input=17, output=806
530 12:47:38.974195 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
531 12:47:38.978224 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
532 12:47:38.981864 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 12:47:38.989657 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 12:47:38.993156 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 12:47:38.997161 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 12:47:39.000923 ADC[4]: Raw value=905834 ID=7
537 12:47:39.001151 ADC[3]: Raw value=213810 ID=1
538 12:47:39.004487 RAM Code: 0x71
539 12:47:39.008013 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 12:47:39.012018 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 12:47:39.019489 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 12:47:39.027151 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 12:47:39.030606 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 12:47:39.034937 in-header: 03 07 00 00 08 00 00 00
545 12:47:39.038508 in-data: aa e4 47 04 13 02 00 00
546 12:47:39.042223 Chrome EC: UHEPI supported
547 12:47:39.049540 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 12:47:39.052867 in-header: 03 95 00 00 08 00 00 00
549 12:47:39.057450 in-data: 18 20 20 08 00 00 00 00
550 12:47:39.060434 MRC: failed to locate region type 0.
551 12:47:39.064085 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 12:47:39.068029 DRAM-K: Running full calibration
553 12:47:39.076039 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 12:47:39.076270 header.status = 0x0
555 12:47:39.079723 header.version = 0x6 (expected: 0x6)
556 12:47:39.083073 header.size = 0xd00 (expected: 0xd00)
557 12:47:39.083293 header.flags = 0x0
558 12:47:39.090453 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 12:47:39.108584 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
560 12:47:39.115872 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 12:47:39.119497 dram_init: ddr_geometry: 2
562 12:47:39.119721 [EMI] MDL number = 2
563 12:47:39.122955 [EMI] Get MDL freq = 0
564 12:47:39.123141 dram_init: ddr_type: 0
565 12:47:39.127030 is_discrete_lpddr4: 1
566 12:47:39.130389 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 12:47:39.130580
568 12:47:39.130664
569 12:47:39.130750 [Bian_co] ETT version 0.0.0.1
570 12:47:39.137924 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 12:47:39.138113
572 12:47:39.141237 dramc_set_vcore_voltage set vcore to 650000
573 12:47:39.141423 Read voltage for 800, 4
574 12:47:39.145355 Vio18 = 0
575 12:47:39.145576 Vcore = 650000
576 12:47:39.145891 Vdram = 0
577 12:47:39.146006 Vddq = 0
578 12:47:39.149151 Vmddr = 0
579 12:47:39.149347 dram_init: config_dvfs: 1
580 12:47:39.157013 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 12:47:39.160476 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 12:47:39.164490 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
583 12:47:39.167587 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
584 12:47:39.171775 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
585 12:47:39.175218 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
586 12:47:39.178308 MEM_TYPE=3, freq_sel=18
587 12:47:39.181814 sv_algorithm_assistance_LP4_1600
588 12:47:39.185084 ============ PULL DRAM RESETB DOWN ============
589 12:47:39.188528 ========== PULL DRAM RESETB DOWN end =========
590 12:47:39.195619 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 12:47:39.199365 ===================================
592 12:47:39.199569 LPDDR4 DRAM CONFIGURATION
593 12:47:39.203289 ===================================
594 12:47:39.206724 EX_ROW_EN[0] = 0x0
595 12:47:39.206927 EX_ROW_EN[1] = 0x0
596 12:47:39.210792 LP4Y_EN = 0x0
597 12:47:39.210972 WORK_FSP = 0x0
598 12:47:39.211108 WL = 0x2
599 12:47:39.214347 RL = 0x2
600 12:47:39.214539 BL = 0x2
601 12:47:39.217601 RPST = 0x0
602 12:47:39.217773 RD_PRE = 0x0
603 12:47:39.220706 WR_PRE = 0x1
604 12:47:39.223941 WR_PST = 0x0
605 12:47:39.224131 DBI_WR = 0x0
606 12:47:39.227417 DBI_RD = 0x0
607 12:47:39.227618 OTF = 0x1
608 12:47:39.230727 ===================================
609 12:47:39.234665 ===================================
610 12:47:39.234885 ANA top config
611 12:47:39.238198 ===================================
612 12:47:39.242181 DLL_ASYNC_EN = 0
613 12:47:39.245669 ALL_SLAVE_EN = 1
614 12:47:39.245866 NEW_RANK_MODE = 1
615 12:47:39.248595 DLL_IDLE_MODE = 1
616 12:47:39.252378 LP45_APHY_COMB_EN = 1
617 12:47:39.255584 TX_ODT_DIS = 1
618 12:47:39.255812 NEW_8X_MODE = 1
619 12:47:39.259178 ===================================
620 12:47:39.263286 ===================================
621 12:47:39.266774 data_rate = 1600
622 12:47:39.269852 CKR = 1
623 12:47:39.273235 DQ_P2S_RATIO = 8
624 12:47:39.276258 ===================================
625 12:47:39.276448 CA_P2S_RATIO = 8
626 12:47:39.280019 DQ_CA_OPEN = 0
627 12:47:39.283135 DQ_SEMI_OPEN = 0
628 12:47:39.286620 CA_SEMI_OPEN = 0
629 12:47:39.290329 CA_FULL_RATE = 0
630 12:47:39.293246 DQ_CKDIV4_EN = 1
631 12:47:39.293435 CA_CKDIV4_EN = 1
632 12:47:39.296317 CA_PREDIV_EN = 0
633 12:47:39.300126 PH8_DLY = 0
634 12:47:39.303510 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 12:47:39.306838 DQ_AAMCK_DIV = 4
636 12:47:39.310304 CA_AAMCK_DIV = 4
637 12:47:39.310540 CA_ADMCK_DIV = 4
638 12:47:39.313454 DQ_TRACK_CA_EN = 0
639 12:47:39.316900 CA_PICK = 800
640 12:47:39.320416 CA_MCKIO = 800
641 12:47:39.324333 MCKIO_SEMI = 0
642 12:47:39.324552 PLL_FREQ = 3068
643 12:47:39.328089 DQ_UI_PI_RATIO = 32
644 12:47:39.331562 CA_UI_PI_RATIO = 0
645 12:47:39.335297 ===================================
646 12:47:39.339232 ===================================
647 12:47:39.339449 memory_type:LPDDR4
648 12:47:39.343250 GP_NUM : 10
649 12:47:39.343461 SRAM_EN : 1
650 12:47:39.346749 MD32_EN : 0
651 12:47:39.350232 ===================================
652 12:47:39.354321 [ANA_INIT] >>>>>>>>>>>>>>
653 12:47:39.354547 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 12:47:39.358002 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 12:47:39.361297 ===================================
656 12:47:39.364426 data_rate = 1600,PCW = 0X7600
657 12:47:39.367893 ===================================
658 12:47:39.371596 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 12:47:39.378438 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 12:47:39.381167 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 12:47:39.387917 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 12:47:39.391301 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 12:47:39.394872 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 12:47:39.395093 [ANA_INIT] flow start
665 12:47:39.397840 [ANA_INIT] PLL >>>>>>>>
666 12:47:39.401514 [ANA_INIT] PLL <<<<<<<<
667 12:47:39.401711 [ANA_INIT] MIDPI >>>>>>>>
668 12:47:39.404996 [ANA_INIT] MIDPI <<<<<<<<
669 12:47:39.408056 [ANA_INIT] DLL >>>>>>>>
670 12:47:39.408287 [ANA_INIT] flow end
671 12:47:39.414788 ============ LP4 DIFF to SE enter ============
672 12:47:39.418201 ============ LP4 DIFF to SE exit ============
673 12:47:39.418392 [ANA_INIT] <<<<<<<<<<<<<
674 12:47:39.421941 [Flow] Enable top DCM control >>>>>
675 12:47:39.424672 [Flow] Enable top DCM control <<<<<
676 12:47:39.428237 Enable DLL master slave shuffle
677 12:47:39.434712 ==============================================================
678 12:47:39.434905 Gating Mode config
679 12:47:39.441425 ==============================================================
680 12:47:39.444893 Config description:
681 12:47:39.455085 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 12:47:39.461347 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 12:47:39.465082 SELPH_MODE 0: By rank 1: By Phase
684 12:47:39.471688 ==============================================================
685 12:47:39.474703 GAT_TRACK_EN = 1
686 12:47:39.474891 RX_GATING_MODE = 2
687 12:47:39.478265 RX_GATING_TRACK_MODE = 2
688 12:47:39.481657 SELPH_MODE = 1
689 12:47:39.485097 PICG_EARLY_EN = 1
690 12:47:39.488397 VALID_LAT_VALUE = 1
691 12:47:39.495291 ==============================================================
692 12:47:39.498418 Enter into Gating configuration >>>>
693 12:47:39.501820 Exit from Gating configuration <<<<
694 12:47:39.505110 Enter into DVFS_PRE_config >>>>>
695 12:47:39.515118 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 12:47:39.518253 Exit from DVFS_PRE_config <<<<<
697 12:47:39.522023 Enter into PICG configuration >>>>
698 12:47:39.524996 Exit from PICG configuration <<<<
699 12:47:39.528665 [RX_INPUT] configuration >>>>>
700 12:47:39.528881 [RX_INPUT] configuration <<<<<
701 12:47:39.535152 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 12:47:39.541877 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 12:47:39.545086 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 12:47:39.552073 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 12:47:39.558893 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 12:47:39.565257 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 12:47:39.568804 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 12:47:39.572119 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 12:47:39.578728 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 12:47:39.582164 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 12:47:39.585322 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 12:47:39.588735 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 12:47:39.592045 ===================================
714 12:47:39.595624 LPDDR4 DRAM CONFIGURATION
715 12:47:39.598579 ===================================
716 12:47:39.602023 EX_ROW_EN[0] = 0x0
717 12:47:39.602173 EX_ROW_EN[1] = 0x0
718 12:47:39.605664 LP4Y_EN = 0x0
719 12:47:39.605865 WORK_FSP = 0x0
720 12:47:39.608794 WL = 0x2
721 12:47:39.608987 RL = 0x2
722 12:47:39.612310 BL = 0x2
723 12:47:39.612480 RPST = 0x0
724 12:47:39.616185 RD_PRE = 0x0
725 12:47:39.616379 WR_PRE = 0x1
726 12:47:39.618599 WR_PST = 0x0
727 12:47:39.618764 DBI_WR = 0x0
728 12:47:39.622062 DBI_RD = 0x0
729 12:47:39.622233 OTF = 0x1
730 12:47:39.625780 ===================================
731 12:47:39.632559 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 12:47:39.635779 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 12:47:39.638830 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 12:47:39.642090 ===================================
735 12:47:39.645601 LPDDR4 DRAM CONFIGURATION
736 12:47:39.648958 ===================================
737 12:47:39.649119 EX_ROW_EN[0] = 0x10
738 12:47:39.652240 EX_ROW_EN[1] = 0x0
739 12:47:39.655902 LP4Y_EN = 0x0
740 12:47:39.656135 WORK_FSP = 0x0
741 12:47:39.659265 WL = 0x2
742 12:47:39.659432 RL = 0x2
743 12:47:39.662624 BL = 0x2
744 12:47:39.662807 RPST = 0x0
745 12:47:39.665598 RD_PRE = 0x0
746 12:47:39.665789 WR_PRE = 0x1
747 12:47:39.669191 WR_PST = 0x0
748 12:47:39.669383 DBI_WR = 0x0
749 12:47:39.672406 DBI_RD = 0x0
750 12:47:39.672589 OTF = 0x1
751 12:47:39.675937 ===================================
752 12:47:39.682317 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 12:47:39.687053 nWR fixed to 40
754 12:47:39.689862 [ModeRegInit_LP4] CH0 RK0
755 12:47:39.690078 [ModeRegInit_LP4] CH0 RK1
756 12:47:39.693101 [ModeRegInit_LP4] CH1 RK0
757 12:47:39.696787 [ModeRegInit_LP4] CH1 RK1
758 12:47:39.696998 match AC timing 13
759 12:47:39.703089 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 12:47:39.706433 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 12:47:39.710155 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 12:47:39.716648 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 12:47:39.720171 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 12:47:39.720361 [EMI DOE] emi_dcm 0
765 12:47:39.726391 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 12:47:39.726588 ==
767 12:47:39.729758 Dram Type= 6, Freq= 0, CH_0, rank 0
768 12:47:39.733206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 12:47:39.733393 ==
770 12:47:39.739920 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 12:47:39.746697 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 12:47:39.753960 [CA 0] Center 36 (6~67) winsize 62
773 12:47:39.757256 [CA 1] Center 36 (6~67) winsize 62
774 12:47:39.760879 [CA 2] Center 34 (4~65) winsize 62
775 12:47:39.764234 [CA 3] Center 33 (3~64) winsize 62
776 12:47:39.767762 [CA 4] Center 33 (3~64) winsize 62
777 12:47:39.770892 [CA 5] Center 33 (3~63) winsize 61
778 12:47:39.771072
779 12:47:39.774036 [CmdBusTrainingLP45] Vref(ca) range 1: 34
780 12:47:39.774219
781 12:47:39.777578 [CATrainingPosCal] consider 1 rank data
782 12:47:39.780568 u2DelayCellTimex100 = 270/100 ps
783 12:47:39.783942 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
784 12:47:39.786993 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
785 12:47:39.793920 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
786 12:47:39.797085 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
787 12:47:39.800634 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
788 12:47:39.804074 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
789 12:47:39.804305
790 12:47:39.807693 CA PerBit enable=1, Macro0, CA PI delay=33
791 12:47:39.807876
792 12:47:39.810645 [CBTSetCACLKResult] CA Dly = 33
793 12:47:39.810841 CS Dly: 5 (0~36)
794 12:47:39.810948 ==
795 12:47:39.813984 Dram Type= 6, Freq= 0, CH_0, rank 1
796 12:47:39.820675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 12:47:39.820865 ==
798 12:47:39.824075 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 12:47:39.830699 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 12:47:39.840042 [CA 0] Center 36 (6~67) winsize 62
801 12:47:39.843224 [CA 1] Center 36 (6~67) winsize 62
802 12:47:39.846984 [CA 2] Center 34 (4~65) winsize 62
803 12:47:39.850005 [CA 3] Center 34 (3~65) winsize 63
804 12:47:39.853775 [CA 4] Center 33 (3~64) winsize 62
805 12:47:39.856479 [CA 5] Center 32 (2~63) winsize 62
806 12:47:39.856665
807 12:47:39.860116 [CmdBusTrainingLP45] Vref(ca) range 1: 34
808 12:47:39.860286
809 12:47:39.863431 [CATrainingPosCal] consider 2 rank data
810 12:47:39.866762 u2DelayCellTimex100 = 270/100 ps
811 12:47:39.870205 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
812 12:47:39.873496 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
813 12:47:39.876904 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
814 12:47:39.883426 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
815 12:47:39.886999 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
816 12:47:39.890155 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
817 12:47:39.890327
818 12:47:39.893485 CA PerBit enable=1, Macro0, CA PI delay=33
819 12:47:39.893653
820 12:47:39.896995 [CBTSetCACLKResult] CA Dly = 33
821 12:47:39.897165 CS Dly: 5 (0~36)
822 12:47:39.897239
823 12:47:39.900485 ----->DramcWriteLeveling(PI) begin...
824 12:47:39.900655 ==
825 12:47:39.904002 Dram Type= 6, Freq= 0, CH_0, rank 0
826 12:47:39.908291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 12:47:39.908492 ==
828 12:47:39.912016 Write leveling (Byte 0): 34 => 34
829 12:47:39.915094 Write leveling (Byte 1): 31 => 31
830 12:47:39.918988 DramcWriteLeveling(PI) end<-----
831 12:47:39.919179
832 12:47:39.919293 ==
833 12:47:39.921898 Dram Type= 6, Freq= 0, CH_0, rank 0
834 12:47:39.925258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 12:47:39.925459 ==
836 12:47:39.928750 [Gating] SW mode calibration
837 12:47:39.936563 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 12:47:39.942721 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 12:47:39.946440 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 12:47:39.949565 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
841 12:47:39.953079 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
842 12:47:39.959951 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 12:47:39.963252 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 12:47:39.966059 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 12:47:39.973216 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 12:47:39.976128 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 12:47:39.979900 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 12:47:39.986556 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 12:47:39.989591 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 12:47:39.993076 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 12:47:39.999872 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 12:47:40.003114 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 12:47:40.006576 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 12:47:40.013705 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 12:47:40.016760 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 12:47:40.019918 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
857 12:47:40.023065 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
858 12:47:40.029899 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
859 12:47:40.033373 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:47:40.036272 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:47:40.043420 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:47:40.046487 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:47:40.049959 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:47:40.056642 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:47:40.060061 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
866 12:47:40.063062 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
867 12:47:40.070421 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 12:47:40.073541 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 12:47:40.076626 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 12:47:40.083206 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 12:47:40.086826 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 12:47:40.090108 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
873 12:47:40.096520 0 10 8 | B1->B0 | 3333 2525 | 0 0 | (0 0) (0 0)
874 12:47:40.099889 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 12:47:40.103672 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 12:47:40.106660 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 12:47:40.113672 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 12:47:40.116651 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 12:47:40.120449 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 12:47:40.127101 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
881 12:47:40.130052 0 11 8 | B1->B0 | 2929 3e3e | 0 0 | (0 0) (0 0)
882 12:47:40.133797 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
883 12:47:40.139952 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 12:47:40.143800 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 12:47:40.146810 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 12:47:40.153778 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 12:47:40.156631 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 12:47:40.160524 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
889 12:47:40.166843 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
890 12:47:40.169924 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 12:47:40.173352 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 12:47:40.179972 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 12:47:40.183719 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 12:47:40.187200 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 12:47:40.190380 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 12:47:40.196961 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 12:47:40.200242 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 12:47:40.203868 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 12:47:40.210087 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 12:47:40.213522 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 12:47:40.217048 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 12:47:40.223900 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 12:47:40.227424 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 12:47:40.230495 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
905 12:47:40.237306 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
906 12:47:40.237475 Total UI for P1: 0, mck2ui 16
907 12:47:40.240636 best dqsien dly found for B0: ( 0, 14, 4)
908 12:47:40.247418 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
909 12:47:40.250752 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
910 12:47:40.254053 Total UI for P1: 0, mck2ui 16
911 12:47:40.258226 best dqsien dly found for B1: ( 0, 14, 10)
912 12:47:40.261568 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
913 12:47:40.264746 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
914 12:47:40.264930
915 12:47:40.267925 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
916 12:47:40.271368 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
917 12:47:40.274610 [Gating] SW calibration Done
918 12:47:40.274755 ==
919 12:47:40.277957 Dram Type= 6, Freq= 0, CH_0, rank 0
920 12:47:40.281520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 12:47:40.281711 ==
922 12:47:40.284984 RX Vref Scan: 0
923 12:47:40.285165
924 12:47:40.288053 RX Vref 0 -> 0, step: 1
925 12:47:40.288251
926 12:47:40.288360 RX Delay -130 -> 252, step: 16
927 12:47:40.294891 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
928 12:47:40.298002 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
929 12:47:40.301343 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
930 12:47:40.305061 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
931 12:47:40.308390 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
932 12:47:40.315198 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
933 12:47:40.318188 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
934 12:47:40.321614 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
935 12:47:40.324966 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
936 12:47:40.328447 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
937 12:47:40.335298 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
938 12:47:40.338116 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
939 12:47:40.341794 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
940 12:47:40.345039 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
941 12:47:40.348427 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
942 12:47:40.355189 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
943 12:47:40.355400 ==
944 12:47:40.358618 Dram Type= 6, Freq= 0, CH_0, rank 0
945 12:47:40.361387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
946 12:47:40.361579 ==
947 12:47:40.361677 DQS Delay:
948 12:47:40.364638 DQS0 = 0, DQS1 = 0
949 12:47:40.364820 DQM Delay:
950 12:47:40.368484 DQM0 = 90, DQM1 = 85
951 12:47:40.368678 DQ Delay:
952 12:47:40.371759 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
953 12:47:40.374986 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
954 12:47:40.378589 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
955 12:47:40.381723 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
956 12:47:40.381905
957 12:47:40.382008
958 12:47:40.382099 ==
959 12:47:40.385029 Dram Type= 6, Freq= 0, CH_0, rank 0
960 12:47:40.388340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 12:47:40.388491 ==
962 12:47:40.388567
963 12:47:40.391675
964 12:47:40.391859 TX Vref Scan disable
965 12:47:40.395254 == TX Byte 0 ==
966 12:47:40.398356 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
967 12:47:40.401849 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
968 12:47:40.405324 == TX Byte 1 ==
969 12:47:40.408717 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
970 12:47:40.411680 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
971 12:47:40.411880 ==
972 12:47:40.414938 Dram Type= 6, Freq= 0, CH_0, rank 0
973 12:47:40.421726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 12:47:40.421885 ==
975 12:47:40.433576 TX Vref=22, minBit 9, minWin=27, winSum=448
976 12:47:40.436894 TX Vref=24, minBit 10, minWin=27, winSum=453
977 12:47:40.440678 TX Vref=26, minBit 9, minWin=27, winSum=454
978 12:47:40.443433 TX Vref=28, minBit 9, minWin=27, winSum=457
979 12:47:40.447017 TX Vref=30, minBit 5, minWin=28, winSum=455
980 12:47:40.450320 TX Vref=32, minBit 4, minWin=28, winSum=454
981 12:47:40.456981 [TxChooseVref] Worse bit 5, Min win 28, Win sum 455, Final Vref 30
982 12:47:40.457173
983 12:47:40.460500 Final TX Range 1 Vref 30
984 12:47:40.460665
985 12:47:40.460776 ==
986 12:47:40.463911 Dram Type= 6, Freq= 0, CH_0, rank 0
987 12:47:40.467197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 12:47:40.467414 ==
989 12:47:40.467561
990 12:47:40.470357
991 12:47:40.470491 TX Vref Scan disable
992 12:47:40.473675 == TX Byte 0 ==
993 12:47:40.477228 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
994 12:47:40.480639 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
995 12:47:40.483773 == TX Byte 1 ==
996 12:47:40.486943 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
997 12:47:40.490193 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
998 12:47:40.493744
999 12:47:40.493895 [DATLAT]
1000 12:47:40.494017 Freq=800, CH0 RK0
1001 12:47:40.494134
1002 12:47:40.496999 DATLAT Default: 0xa
1003 12:47:40.497137 0, 0xFFFF, sum = 0
1004 12:47:40.500578 1, 0xFFFF, sum = 0
1005 12:47:40.500738 2, 0xFFFF, sum = 0
1006 12:47:40.503964 3, 0xFFFF, sum = 0
1007 12:47:40.504142 4, 0xFFFF, sum = 0
1008 12:47:40.507230 5, 0xFFFF, sum = 0
1009 12:47:40.507375 6, 0xFFFF, sum = 0
1010 12:47:40.510598 7, 0xFFFF, sum = 0
1011 12:47:40.513547 8, 0xFFFF, sum = 0
1012 12:47:40.513696 9, 0x0, sum = 1
1013 12:47:40.513795 10, 0x0, sum = 2
1014 12:47:40.517105 11, 0x0, sum = 3
1015 12:47:40.517263 12, 0x0, sum = 4
1016 12:47:40.520583 best_step = 10
1017 12:47:40.520725
1018 12:47:40.520798 ==
1019 12:47:40.523559 Dram Type= 6, Freq= 0, CH_0, rank 0
1020 12:47:40.527461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1021 12:47:40.527643 ==
1022 12:47:40.530269 RX Vref Scan: 1
1023 12:47:40.530423
1024 12:47:40.530495 Set Vref Range= 32 -> 127
1025 12:47:40.530601
1026 12:47:40.533634 RX Vref 32 -> 127, step: 1
1027 12:47:40.533775
1028 12:47:40.537098 RX Delay -79 -> 252, step: 8
1029 12:47:40.537240
1030 12:47:40.540590 Set Vref, RX VrefLevel [Byte0]: 32
1031 12:47:40.544050 [Byte1]: 32
1032 12:47:40.544255
1033 12:47:40.547435 Set Vref, RX VrefLevel [Byte0]: 33
1034 12:47:40.550373 [Byte1]: 33
1035 12:47:40.553764
1036 12:47:40.553988 Set Vref, RX VrefLevel [Byte0]: 34
1037 12:47:40.557057 [Byte1]: 34
1038 12:47:40.561807
1039 12:47:40.562006 Set Vref, RX VrefLevel [Byte0]: 35
1040 12:47:40.565122 [Byte1]: 35
1041 12:47:40.569207
1042 12:47:40.569364 Set Vref, RX VrefLevel [Byte0]: 36
1043 12:47:40.572710 [Byte1]: 36
1044 12:47:40.577251
1045 12:47:40.577403 Set Vref, RX VrefLevel [Byte0]: 37
1046 12:47:40.580397 [Byte1]: 37
1047 12:47:40.584496
1048 12:47:40.584673 Set Vref, RX VrefLevel [Byte0]: 38
1049 12:47:40.587881 [Byte1]: 38
1050 12:47:40.592215
1051 12:47:40.592374 Set Vref, RX VrefLevel [Byte0]: 39
1052 12:47:40.595403 [Byte1]: 39
1053 12:47:40.599803
1054 12:47:40.599996 Set Vref, RX VrefLevel [Byte0]: 40
1055 12:47:40.603240 [Byte1]: 40
1056 12:47:40.606805
1057 12:47:40.606994 Set Vref, RX VrefLevel [Byte0]: 41
1058 12:47:40.610042 [Byte1]: 41
1059 12:47:40.614667
1060 12:47:40.614823 Set Vref, RX VrefLevel [Byte0]: 42
1061 12:47:40.617399 [Byte1]: 42
1062 12:47:40.622012
1063 12:47:40.622205 Set Vref, RX VrefLevel [Byte0]: 43
1064 12:47:40.625084 [Byte1]: 43
1065 12:47:40.629448
1066 12:47:40.629671 Set Vref, RX VrefLevel [Byte0]: 44
1067 12:47:40.632561 [Byte1]: 44
1068 12:47:40.637346
1069 12:47:40.637542 Set Vref, RX VrefLevel [Byte0]: 45
1070 12:47:40.640428 [Byte1]: 45
1071 12:47:40.644617
1072 12:47:40.644821 Set Vref, RX VrefLevel [Byte0]: 46
1073 12:47:40.647828 [Byte1]: 46
1074 12:47:40.651883
1075 12:47:40.652099 Set Vref, RX VrefLevel [Byte0]: 47
1076 12:47:40.655289 [Byte1]: 47
1077 12:47:40.659725
1078 12:47:40.659970 Set Vref, RX VrefLevel [Byte0]: 48
1079 12:47:40.663164 [Byte1]: 48
1080 12:47:40.667190
1081 12:47:40.667356 Set Vref, RX VrefLevel [Byte0]: 49
1082 12:47:40.670732 [Byte1]: 49
1083 12:47:40.675118
1084 12:47:40.675341 Set Vref, RX VrefLevel [Byte0]: 50
1085 12:47:40.678012 [Byte1]: 50
1086 12:47:40.682372
1087 12:47:40.682563 Set Vref, RX VrefLevel [Byte0]: 51
1088 12:47:40.685231 [Byte1]: 51
1089 12:47:40.689877
1090 12:47:40.690040 Set Vref, RX VrefLevel [Byte0]: 52
1091 12:47:40.693227 [Byte1]: 52
1092 12:47:40.697269
1093 12:47:40.697460 Set Vref, RX VrefLevel [Byte0]: 53
1094 12:47:40.700429 [Byte1]: 53
1095 12:47:40.704791
1096 12:47:40.704946 Set Vref, RX VrefLevel [Byte0]: 54
1097 12:47:40.708148 [Byte1]: 54
1098 12:47:40.712513
1099 12:47:40.712697 Set Vref, RX VrefLevel [Byte0]: 55
1100 12:47:40.715945 [Byte1]: 55
1101 12:47:40.720121
1102 12:47:40.720322 Set Vref, RX VrefLevel [Byte0]: 56
1103 12:47:40.723335 [Byte1]: 56
1104 12:47:40.727600
1105 12:47:40.727753 Set Vref, RX VrefLevel [Byte0]: 57
1106 12:47:40.730476 [Byte1]: 57
1107 12:47:40.735005
1108 12:47:40.735207 Set Vref, RX VrefLevel [Byte0]: 58
1109 12:47:40.738642 [Byte1]: 58
1110 12:47:40.742930
1111 12:47:40.743157 Set Vref, RX VrefLevel [Byte0]: 59
1112 12:47:40.746228 [Byte1]: 59
1113 12:47:40.749935
1114 12:47:40.750153 Set Vref, RX VrefLevel [Byte0]: 60
1115 12:47:40.753276 [Byte1]: 60
1116 12:47:40.757879
1117 12:47:40.758074 Set Vref, RX VrefLevel [Byte0]: 61
1118 12:47:40.760761 [Byte1]: 61
1119 12:47:40.765211
1120 12:47:40.765391 Set Vref, RX VrefLevel [Byte0]: 62
1121 12:47:40.768719 [Byte1]: 62
1122 12:47:40.772702
1123 12:47:40.772872 Set Vref, RX VrefLevel [Byte0]: 63
1124 12:47:40.776092 [Byte1]: 63
1125 12:47:40.780189
1126 12:47:40.780364 Set Vref, RX VrefLevel [Byte0]: 64
1127 12:47:40.783761 [Byte1]: 64
1128 12:47:40.788107
1129 12:47:40.788287 Set Vref, RX VrefLevel [Byte0]: 65
1130 12:47:40.790990 [Byte1]: 65
1131 12:47:40.795583
1132 12:47:40.795762 Set Vref, RX VrefLevel [Byte0]: 66
1133 12:47:40.798868 [Byte1]: 66
1134 12:47:40.802924
1135 12:47:40.803123 Set Vref, RX VrefLevel [Byte0]: 67
1136 12:47:40.806545 [Byte1]: 67
1137 12:47:40.810425
1138 12:47:40.810612 Set Vref, RX VrefLevel [Byte0]: 68
1139 12:47:40.814284 [Byte1]: 68
1140 12:47:40.818167
1141 12:47:40.818424 Set Vref, RX VrefLevel [Byte0]: 69
1142 12:47:40.821542 [Byte1]: 69
1143 12:47:40.825795
1144 12:47:40.825977 Set Vref, RX VrefLevel [Byte0]: 70
1145 12:47:40.828919 [Byte1]: 70
1146 12:47:40.833184
1147 12:47:40.833362 Set Vref, RX VrefLevel [Byte0]: 71
1148 12:47:40.836617 [Byte1]: 71
1149 12:47:40.840743
1150 12:47:40.840889 Set Vref, RX VrefLevel [Byte0]: 72
1151 12:47:40.843985 [Byte1]: 72
1152 12:47:40.848366
1153 12:47:40.848553 Set Vref, RX VrefLevel [Byte0]: 73
1154 12:47:40.851459 [Byte1]: 73
1155 12:47:40.855770
1156 12:47:40.855955 Set Vref, RX VrefLevel [Byte0]: 74
1157 12:47:40.859008 [Byte1]: 74
1158 12:47:40.863317
1159 12:47:40.863550 Set Vref, RX VrefLevel [Byte0]: 75
1160 12:47:40.866432 [Byte1]: 75
1161 12:47:40.871036
1162 12:47:40.871224 Final RX Vref Byte 0 = 61 to rank0
1163 12:47:40.874379 Final RX Vref Byte 1 = 55 to rank0
1164 12:47:40.877547 Final RX Vref Byte 0 = 61 to rank1
1165 12:47:40.880754 Final RX Vref Byte 1 = 55 to rank1==
1166 12:47:40.884365 Dram Type= 6, Freq= 0, CH_0, rank 0
1167 12:47:40.891005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1168 12:47:40.891197 ==
1169 12:47:40.891314 DQS Delay:
1170 12:47:40.891439 DQS0 = 0, DQS1 = 0
1171 12:47:40.893937 DQM Delay:
1172 12:47:40.894085 DQM0 = 92, DQM1 = 85
1173 12:47:40.897422 DQ Delay:
1174 12:47:40.901105 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1175 12:47:40.904109 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1176 12:47:40.907566 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
1177 12:47:40.910932 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1178 12:47:40.911126
1179 12:47:40.911239
1180 12:47:40.917392 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a3f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1181 12:47:40.920737 CH0 RK0: MR19=606, MR18=4A3F
1182 12:47:40.927307 CH0_RK0: MR19=0x606, MR18=0x4A3F, DQSOSC=391, MR23=63, INC=96, DEC=64
1183 12:47:40.927485
1184 12:47:40.931034 ----->DramcWriteLeveling(PI) begin...
1185 12:47:40.931225 ==
1186 12:47:40.934070 Dram Type= 6, Freq= 0, CH_0, rank 1
1187 12:47:40.937613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1188 12:47:40.937762 ==
1189 12:47:40.940792 Write leveling (Byte 0): 33 => 33
1190 12:47:40.944123 Write leveling (Byte 1): 30 => 30
1191 12:47:40.947545 DramcWriteLeveling(PI) end<-----
1192 12:47:40.947696
1193 12:47:40.947774 ==
1194 12:47:40.951233 Dram Type= 6, Freq= 0, CH_0, rank 1
1195 12:47:40.954339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1196 12:47:40.954522 ==
1197 12:47:40.957891 [Gating] SW mode calibration
1198 12:47:40.964670 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1199 12:47:40.971215 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1200 12:47:40.974616 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1201 12:47:41.018282 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1202 12:47:41.018692 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1203 12:47:41.018815 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 12:47:41.018911 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 12:47:41.019046 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 12:47:41.019396 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 12:47:41.019748 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 12:47:41.019861 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 12:47:41.019955 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 12:47:41.020476 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 12:47:41.025515 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 12:47:41.028290 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 12:47:41.031929 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 12:47:41.035290 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 12:47:41.042313 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 12:47:41.045326 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 12:47:41.048833 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1218 12:47:41.052407 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1219 12:47:41.058734 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 12:47:41.062218 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 12:47:41.065129 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 12:47:41.072035 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 12:47:41.075466 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 12:47:41.078741 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 12:47:41.085456 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:47:41.088995 0 9 8 | B1->B0 | 3030 2c2c | 1 1 | (1 1) (1 1)
1227 12:47:41.092060 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1228 12:47:41.098923 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1229 12:47:41.102212 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1230 12:47:41.105736 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1231 12:47:41.112092 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1232 12:47:41.115592 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1233 12:47:41.119010 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1234 12:47:41.121924 0 10 8 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 1)
1235 12:47:41.128696 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 12:47:41.131900 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 12:47:41.135482 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 12:47:41.141886 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 12:47:41.145698 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 12:47:41.149277 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 12:47:41.153173 0 11 4 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
1242 12:47:41.157445 0 11 8 | B1->B0 | 3c3c 3a3a | 1 0 | (0 0) (0 0)
1243 12:47:41.165261 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1244 12:47:41.167927 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1245 12:47:41.171466 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1246 12:47:41.175450 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1247 12:47:41.182180 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1248 12:47:41.185732 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1249 12:47:41.189152 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 12:47:41.195863 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1251 12:47:41.199414 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1252 12:47:41.202486 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 12:47:41.205856 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 12:47:41.212678 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 12:47:41.215677 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 12:47:41.219057 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 12:47:41.225781 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 12:47:41.229006 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 12:47:41.232328 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 12:47:41.239171 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 12:47:41.242568 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 12:47:41.246074 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 12:47:41.252335 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 12:47:41.255755 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 12:47:41.259136 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 12:47:41.265609 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1267 12:47:41.265797 Total UI for P1: 0, mck2ui 16
1268 12:47:41.269459 best dqsien dly found for B0: ( 0, 14, 6)
1269 12:47:41.275908 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 12:47:41.279190 Total UI for P1: 0, mck2ui 16
1271 12:47:41.282420 best dqsien dly found for B1: ( 0, 14, 8)
1272 12:47:41.285704 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1273 12:47:41.289154 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1274 12:47:41.289353
1275 12:47:41.292777 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1276 12:47:41.296145 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1277 12:47:41.299471 [Gating] SW calibration Done
1278 12:47:41.299647 ==
1279 12:47:41.302651 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 12:47:41.306168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1281 12:47:41.306334 ==
1282 12:47:41.309797 RX Vref Scan: 0
1283 12:47:41.309994
1284 12:47:41.310114 RX Vref 0 -> 0, step: 1
1285 12:47:41.310185
1286 12:47:41.312652 RX Delay -130 -> 252, step: 16
1287 12:47:41.319670 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1288 12:47:41.322495 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1289 12:47:41.326014 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1290 12:47:41.329761 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1291 12:47:41.332749 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1292 12:47:41.335986 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1293 12:47:41.342510 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1294 12:47:41.345799 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1295 12:47:41.349174 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1296 12:47:41.352769 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1297 12:47:41.356012 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1298 12:47:41.362778 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1299 12:47:41.366210 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1300 12:47:41.369641 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1301 12:47:41.372481 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1302 12:47:41.379225 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1303 12:47:41.379423 ==
1304 12:47:41.382937 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 12:47:41.385926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 12:47:41.386106 ==
1307 12:47:41.386208 DQS Delay:
1308 12:47:41.389613 DQS0 = 0, DQS1 = 0
1309 12:47:41.389841 DQM Delay:
1310 12:47:41.392694 DQM0 = 92, DQM1 = 82
1311 12:47:41.392903 DQ Delay:
1312 12:47:41.396338 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1313 12:47:41.399547 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1314 12:47:41.403319 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1315 12:47:41.405895 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1316 12:47:41.406084
1317 12:47:41.406184
1318 12:47:41.406289 ==
1319 12:47:41.410084 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 12:47:41.412990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 12:47:41.413244 ==
1322 12:47:41.413369
1323 12:47:41.413471
1324 12:47:41.416408 TX Vref Scan disable
1325 12:47:41.419810 == TX Byte 0 ==
1326 12:47:41.423332 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1327 12:47:41.426266 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1328 12:47:41.429652 == TX Byte 1 ==
1329 12:47:41.432933 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1330 12:47:41.436560 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1331 12:47:41.436779 ==
1332 12:47:41.439840 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 12:47:41.443079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 12:47:41.446304 ==
1335 12:47:41.457559 TX Vref=22, minBit 8, minWin=27, winSum=448
1336 12:47:41.461041 TX Vref=24, minBit 9, minWin=27, winSum=451
1337 12:47:41.464345 TX Vref=26, minBit 1, minWin=28, winSum=456
1338 12:47:41.467420 TX Vref=28, minBit 4, minWin=28, winSum=456
1339 12:47:41.470884 TX Vref=30, minBit 4, minWin=28, winSum=455
1340 12:47:41.477756 TX Vref=32, minBit 8, minWin=27, winSum=450
1341 12:47:41.481282 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 26
1342 12:47:41.481503
1343 12:47:41.484042 Final TX Range 1 Vref 26
1344 12:47:41.484234
1345 12:47:41.484333 ==
1346 12:47:41.487982 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 12:47:41.491435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 12:47:41.491664 ==
1349 12:47:41.491771
1350 12:47:41.494622
1351 12:47:41.494772 TX Vref Scan disable
1352 12:47:41.497609 == TX Byte 0 ==
1353 12:47:41.500728 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1354 12:47:41.507689 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1355 12:47:41.507897 == TX Byte 1 ==
1356 12:47:41.510870 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1357 12:47:41.514410 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1358 12:47:41.517900
1359 12:47:41.518074 [DATLAT]
1360 12:47:41.518191 Freq=800, CH0 RK1
1361 12:47:41.518298
1362 12:47:41.521120 DATLAT Default: 0xa
1363 12:47:41.521310 0, 0xFFFF, sum = 0
1364 12:47:41.524713 1, 0xFFFF, sum = 0
1365 12:47:41.524888 2, 0xFFFF, sum = 0
1366 12:47:41.527948 3, 0xFFFF, sum = 0
1367 12:47:41.528144 4, 0xFFFF, sum = 0
1368 12:47:41.531299 5, 0xFFFF, sum = 0
1369 12:47:41.531460 6, 0xFFFF, sum = 0
1370 12:47:41.534329 7, 0xFFFF, sum = 0
1371 12:47:41.537659 8, 0xFFFF, sum = 0
1372 12:47:41.537828 9, 0x0, sum = 1
1373 12:47:41.537928 10, 0x0, sum = 2
1374 12:47:41.540940 11, 0x0, sum = 3
1375 12:47:41.541076 12, 0x0, sum = 4
1376 12:47:41.544511 best_step = 10
1377 12:47:41.544679
1378 12:47:41.544777 ==
1379 12:47:41.548030 Dram Type= 6, Freq= 0, CH_0, rank 1
1380 12:47:41.551195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 12:47:41.551371 ==
1382 12:47:41.554270 RX Vref Scan: 0
1383 12:47:41.554454
1384 12:47:41.554579 RX Vref 0 -> 0, step: 1
1385 12:47:41.554646
1386 12:47:41.557635 RX Delay -79 -> 252, step: 8
1387 12:47:41.564712 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1388 12:47:41.567496 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1389 12:47:41.571320 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1390 12:47:41.574848 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1391 12:47:41.578115 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1392 12:47:41.584557 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1393 12:47:41.587820 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1394 12:47:41.591169 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1395 12:47:41.594825 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1396 12:47:41.598368 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1397 12:47:41.604363 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1398 12:47:41.608028 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1399 12:47:41.611151 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1400 12:47:41.615091 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1401 12:47:41.617873 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1402 12:47:41.624790 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1403 12:47:41.624986 ==
1404 12:47:41.628210 Dram Type= 6, Freq= 0, CH_0, rank 1
1405 12:47:41.631628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 12:47:41.631782 ==
1407 12:47:41.631867 DQS Delay:
1408 12:47:41.634776 DQS0 = 0, DQS1 = 0
1409 12:47:41.634949 DQM Delay:
1410 12:47:41.638179 DQM0 = 92, DQM1 = 83
1411 12:47:41.638320 DQ Delay:
1412 12:47:41.641670 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =88
1413 12:47:41.644674 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1414 12:47:41.648079 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1415 12:47:41.651573 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =88
1416 12:47:41.651776
1417 12:47:41.651880
1418 12:47:41.657909 [DQSOSCAuto] RK1, (LSB)MR18= 0x4111, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1419 12:47:41.661646 CH0 RK1: MR19=606, MR18=4111
1420 12:47:41.668058 CH0_RK1: MR19=0x606, MR18=0x4111, DQSOSC=393, MR23=63, INC=95, DEC=63
1421 12:47:41.671259 [RxdqsGatingPostProcess] freq 800
1422 12:47:41.677945 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1423 12:47:41.678125 Pre-setting of DQS Precalculation
1424 12:47:41.684920 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1425 12:47:41.685105 ==
1426 12:47:41.688176 Dram Type= 6, Freq= 0, CH_1, rank 0
1427 12:47:41.691644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1428 12:47:41.691798 ==
1429 12:47:41.698472 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1430 12:47:41.704982 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1431 12:47:41.713308 [CA 0] Center 36 (5~67) winsize 63
1432 12:47:41.716216 [CA 1] Center 36 (6~67) winsize 62
1433 12:47:41.719570 [CA 2] Center 35 (5~66) winsize 62
1434 12:47:41.723102 [CA 3] Center 34 (4~65) winsize 62
1435 12:47:41.725916 [CA 4] Center 34 (4~65) winsize 62
1436 12:47:41.729501 [CA 5] Center 33 (3~64) winsize 62
1437 12:47:41.729639
1438 12:47:41.732804 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1439 12:47:41.733014
1440 12:47:41.736226 [CATrainingPosCal] consider 1 rank data
1441 12:47:41.739423 u2DelayCellTimex100 = 270/100 ps
1442 12:47:41.742703 CA0 delay=36 (5~67),Diff = 3 PI (21 cell)
1443 12:47:41.746271 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1444 12:47:41.752604 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
1445 12:47:41.756100 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1446 12:47:41.759509 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1447 12:47:41.763197 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1448 12:47:41.763372
1449 12:47:41.765968 CA PerBit enable=1, Macro0, CA PI delay=33
1450 12:47:41.766105
1451 12:47:41.769455 [CBTSetCACLKResult] CA Dly = 33
1452 12:47:41.769600 CS Dly: 6 (0~37)
1453 12:47:41.769670 ==
1454 12:47:41.772881 Dram Type= 6, Freq= 0, CH_1, rank 1
1455 12:47:41.779538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1456 12:47:41.779765 ==
1457 12:47:41.782766 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1458 12:47:41.789801 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1459 12:47:41.799134 [CA 0] Center 36 (6~67) winsize 62
1460 12:47:41.802538 [CA 1] Center 36 (6~67) winsize 62
1461 12:47:41.805652 [CA 2] Center 35 (4~66) winsize 63
1462 12:47:41.808984 [CA 3] Center 35 (5~65) winsize 61
1463 12:47:41.813249 [CA 4] Center 35 (4~66) winsize 63
1464 12:47:41.816877 [CA 5] Center 34 (4~65) winsize 62
1465 12:47:41.817057
1466 12:47:41.820597 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1467 12:47:41.820787
1468 12:47:41.824015 [CATrainingPosCal] consider 2 rank data
1469 12:47:41.827573 u2DelayCellTimex100 = 270/100 ps
1470 12:47:41.831768 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1471 12:47:41.835283 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1472 12:47:41.838451 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1473 12:47:41.842493 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1474 12:47:41.845724 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1475 12:47:41.849324 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1476 12:47:41.849519
1477 12:47:41.853066 CA PerBit enable=1, Macro0, CA PI delay=34
1478 12:47:41.853239
1479 12:47:41.856370 [CBTSetCACLKResult] CA Dly = 34
1480 12:47:41.856531 CS Dly: 6 (0~38)
1481 12:47:41.856616
1482 12:47:41.859862 ----->DramcWriteLeveling(PI) begin...
1483 12:47:41.860008 ==
1484 12:47:41.862543 Dram Type= 6, Freq= 0, CH_1, rank 0
1485 12:47:41.869605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1486 12:47:41.869783 ==
1487 12:47:41.872984 Write leveling (Byte 0): 26 => 26
1488 12:47:41.873131 Write leveling (Byte 1): 29 => 29
1489 12:47:41.876418 DramcWriteLeveling(PI) end<-----
1490 12:47:41.876577
1491 12:47:41.879918 ==
1492 12:47:41.880079 Dram Type= 6, Freq= 0, CH_1, rank 0
1493 12:47:41.886414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1494 12:47:41.886597 ==
1495 12:47:41.889595 [Gating] SW mode calibration
1496 12:47:41.896420 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1497 12:47:41.899586 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1498 12:47:41.903545 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1499 12:47:41.910030 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1500 12:47:41.912927 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 12:47:41.916658 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 12:47:41.922914 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 12:47:41.926208 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 12:47:41.929642 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 12:47:41.936256 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 12:47:41.939676 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 12:47:41.942938 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 12:47:41.949673 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 12:47:41.953057 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 12:47:41.956407 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 12:47:41.963307 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 12:47:41.966441 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 12:47:41.969721 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 12:47:41.976638 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1515 12:47:41.979514 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1516 12:47:41.982748 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1517 12:47:41.989524 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 12:47:41.992992 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 12:47:41.996351 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 12:47:42.003045 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 12:47:42.006181 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 12:47:42.009485 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 12:47:42.016209 0 9 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1524 12:47:42.019573 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1525 12:47:42.023051 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1526 12:47:42.026411 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1527 12:47:42.033195 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1528 12:47:42.036694 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1529 12:47:42.039469 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1530 12:47:42.046208 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1531 12:47:42.049784 0 10 4 | B1->B0 | 3232 2f2f | 0 0 | (1 1) (1 0)
1532 12:47:42.053072 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1533 12:47:42.060105 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 12:47:42.063206 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 12:47:42.066372 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 12:47:42.073229 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 12:47:42.076767 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 12:47:42.079861 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 12:47:42.086586 0 11 4 | B1->B0 | 2a2a 3434 | 0 0 | (0 0) (0 0)
1540 12:47:42.090375 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1541 12:47:42.092853 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1542 12:47:42.096886 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1543 12:47:42.102933 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1544 12:47:42.106900 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1545 12:47:42.109742 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1546 12:47:42.116626 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 12:47:42.120016 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1548 12:47:42.123543 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 12:47:42.129899 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 12:47:42.133639 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 12:47:42.137011 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 12:47:42.143573 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 12:47:42.146920 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 12:47:42.150372 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 12:47:42.156817 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 12:47:42.160458 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 12:47:42.163447 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 12:47:42.166699 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 12:47:42.173286 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 12:47:42.177044 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 12:47:42.180032 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 12:47:42.186792 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1563 12:47:42.190219 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1564 12:47:42.193420 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 12:47:42.196912 Total UI for P1: 0, mck2ui 16
1566 12:47:42.200608 best dqsien dly found for B0: ( 0, 14, 2)
1567 12:47:42.203608 Total UI for P1: 0, mck2ui 16
1568 12:47:42.206866 best dqsien dly found for B1: ( 0, 14, 2)
1569 12:47:42.210192 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1570 12:47:42.213608 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1571 12:47:42.213787
1572 12:47:42.217269 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1573 12:47:42.223838 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1574 12:47:42.223979 [Gating] SW calibration Done
1575 12:47:42.224056 ==
1576 12:47:42.227114 Dram Type= 6, Freq= 0, CH_1, rank 0
1577 12:47:42.233645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1578 12:47:42.233830 ==
1579 12:47:42.233981 RX Vref Scan: 0
1580 12:47:42.234090
1581 12:47:42.237036 RX Vref 0 -> 0, step: 1
1582 12:47:42.237193
1583 12:47:42.240357 RX Delay -130 -> 252, step: 16
1584 12:47:42.243909 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1585 12:47:42.247209 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1586 12:47:42.250620 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1587 12:47:42.257020 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1588 12:47:42.260187 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1589 12:47:42.263543 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1590 12:47:42.267173 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1591 12:47:42.270284 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1592 12:47:42.277315 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1593 12:47:42.280277 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1594 12:47:42.283572 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1595 12:47:42.287083 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1596 12:47:42.290261 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1597 12:47:42.296907 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1598 12:47:42.300341 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1599 12:47:42.303840 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1600 12:47:42.304010 ==
1601 12:47:42.307300 Dram Type= 6, Freq= 0, CH_1, rank 0
1602 12:47:42.310427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1603 12:47:42.310599 ==
1604 12:47:42.313530 DQS Delay:
1605 12:47:42.313727 DQS0 = 0, DQS1 = 0
1606 12:47:42.316812 DQM Delay:
1607 12:47:42.317010 DQM0 = 93, DQM1 = 87
1608 12:47:42.317110 DQ Delay:
1609 12:47:42.320307 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1610 12:47:42.323752 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1611 12:47:42.327160 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1612 12:47:42.330539 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1613 12:47:42.330733
1614 12:47:42.330846
1615 12:47:42.333582 ==
1616 12:47:42.333766 Dram Type= 6, Freq= 0, CH_1, rank 0
1617 12:47:42.340356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1618 12:47:42.340526 ==
1619 12:47:42.340634
1620 12:47:42.340725
1621 12:47:42.343531 TX Vref Scan disable
1622 12:47:42.343710 == TX Byte 0 ==
1623 12:47:42.347061 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1624 12:47:42.353925 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1625 12:47:42.354129 == TX Byte 1 ==
1626 12:47:42.357187 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1627 12:47:42.363677 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1628 12:47:42.363978 ==
1629 12:47:42.367092 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 12:47:42.370505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 12:47:42.370708 ==
1632 12:47:42.383879 TX Vref=22, minBit 0, minWin=26, winSum=433
1633 12:47:42.386924 TX Vref=24, minBit 0, minWin=27, winSum=442
1634 12:47:42.390653 TX Vref=26, minBit 1, minWin=27, winSum=444
1635 12:47:42.394184 TX Vref=28, minBit 1, minWin=27, winSum=444
1636 12:47:42.397841 TX Vref=30, minBit 0, minWin=27, winSum=447
1637 12:47:42.401113 TX Vref=32, minBit 0, minWin=27, winSum=445
1638 12:47:42.407698 [TxChooseVref] Worse bit 0, Min win 27, Win sum 447, Final Vref 30
1639 12:47:42.407855
1640 12:47:42.410994 Final TX Range 1 Vref 30
1641 12:47:42.411160
1642 12:47:42.411260 ==
1643 12:47:42.414359 Dram Type= 6, Freq= 0, CH_1, rank 0
1644 12:47:42.417811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1645 12:47:42.417995 ==
1646 12:47:42.418111
1647 12:47:42.418203
1648 12:47:42.421011 TX Vref Scan disable
1649 12:47:42.424562 == TX Byte 0 ==
1650 12:47:42.427790 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1651 12:47:42.430745 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1652 12:47:42.434054 == TX Byte 1 ==
1653 12:47:42.437423 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1654 12:47:42.441006 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1655 12:47:42.441193
1656 12:47:42.444369 [DATLAT]
1657 12:47:42.444562 Freq=800, CH1 RK0
1658 12:47:42.444691
1659 12:47:42.447968 DATLAT Default: 0xa
1660 12:47:42.448139 0, 0xFFFF, sum = 0
1661 12:47:42.451200 1, 0xFFFF, sum = 0
1662 12:47:42.451369 2, 0xFFFF, sum = 0
1663 12:47:42.453876 3, 0xFFFF, sum = 0
1664 12:47:42.454025 4, 0xFFFF, sum = 0
1665 12:47:42.457528 5, 0xFFFF, sum = 0
1666 12:47:42.457694 6, 0xFFFF, sum = 0
1667 12:47:42.460860 7, 0xFFFF, sum = 0
1668 12:47:42.460999 8, 0xFFFF, sum = 0
1669 12:47:42.464162 9, 0x0, sum = 1
1670 12:47:42.464308 10, 0x0, sum = 2
1671 12:47:42.467351 11, 0x0, sum = 3
1672 12:47:42.467532 12, 0x0, sum = 4
1673 12:47:42.470820 best_step = 10
1674 12:47:42.470995
1675 12:47:42.471095 ==
1676 12:47:42.474199 Dram Type= 6, Freq= 0, CH_1, rank 0
1677 12:47:42.477514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1678 12:47:42.477704 ==
1679 12:47:42.480715 RX Vref Scan: 1
1680 12:47:42.480895
1681 12:47:42.480998 Set Vref Range= 32 -> 127
1682 12:47:42.481089
1683 12:47:42.484196 RX Vref 32 -> 127, step: 1
1684 12:47:42.484409
1685 12:47:42.489642 RX Delay -79 -> 252, step: 8
1686 12:47:42.489816
1687 12:47:42.490925 Set Vref, RX VrefLevel [Byte0]: 32
1688 12:47:42.494376 [Byte1]: 32
1689 12:47:42.494651
1690 12:47:42.497651 Set Vref, RX VrefLevel [Byte0]: 33
1691 12:47:42.501272 [Byte1]: 33
1692 12:47:42.501654
1693 12:47:42.504004 Set Vref, RX VrefLevel [Byte0]: 34
1694 12:47:42.507393 [Byte1]: 34
1695 12:47:42.511108
1696 12:47:42.511303 Set Vref, RX VrefLevel [Byte0]: 35
1697 12:47:42.514513 [Byte1]: 35
1698 12:47:42.519183
1699 12:47:42.519370 Set Vref, RX VrefLevel [Byte0]: 36
1700 12:47:42.522233 [Byte1]: 36
1701 12:47:42.526181
1702 12:47:42.526369 Set Vref, RX VrefLevel [Byte0]: 37
1703 12:47:42.529654 [Byte1]: 37
1704 12:47:42.534120
1705 12:47:42.534306 Set Vref, RX VrefLevel [Byte0]: 38
1706 12:47:42.537528 [Byte1]: 38
1707 12:47:42.541416
1708 12:47:42.541643 Set Vref, RX VrefLevel [Byte0]: 39
1709 12:47:42.544799 [Byte1]: 39
1710 12:47:42.549015
1711 12:47:42.549205 Set Vref, RX VrefLevel [Byte0]: 40
1712 12:47:42.552394 [Byte1]: 40
1713 12:47:42.556524
1714 12:47:42.556739 Set Vref, RX VrefLevel [Byte0]: 41
1715 12:47:42.559747 [Byte1]: 41
1716 12:47:42.564091
1717 12:47:42.564269 Set Vref, RX VrefLevel [Byte0]: 42
1718 12:47:42.567149 [Byte1]: 42
1719 12:47:42.571817
1720 12:47:42.571973 Set Vref, RX VrefLevel [Byte0]: 43
1721 12:47:42.575047 [Byte1]: 43
1722 12:47:42.579434
1723 12:47:42.579641 Set Vref, RX VrefLevel [Byte0]: 44
1724 12:47:42.582606 [Byte1]: 44
1725 12:47:42.586642
1726 12:47:42.586828 Set Vref, RX VrefLevel [Byte0]: 45
1727 12:47:42.590271 [Byte1]: 45
1728 12:47:42.594097
1729 12:47:42.594287 Set Vref, RX VrefLevel [Byte0]: 46
1730 12:47:42.597691 [Byte1]: 46
1731 12:47:42.602074
1732 12:47:42.602278 Set Vref, RX VrefLevel [Byte0]: 47
1733 12:47:42.605532 [Byte1]: 47
1734 12:47:42.609487
1735 12:47:42.609784 Set Vref, RX VrefLevel [Byte0]: 48
1736 12:47:42.612948 [Byte1]: 48
1737 12:47:42.616929
1738 12:47:42.617112 Set Vref, RX VrefLevel [Byte0]: 49
1739 12:47:42.620659 [Byte1]: 49
1740 12:47:42.624516
1741 12:47:42.624680 Set Vref, RX VrefLevel [Byte0]: 50
1742 12:47:42.628068 [Byte1]: 50
1743 12:47:42.632146
1744 12:47:42.632327 Set Vref, RX VrefLevel [Byte0]: 51
1745 12:47:42.635445 [Byte1]: 51
1746 12:47:42.639648
1747 12:47:42.639829 Set Vref, RX VrefLevel [Byte0]: 52
1748 12:47:42.643040 [Byte1]: 52
1749 12:47:42.647247
1750 12:47:42.647437 Set Vref, RX VrefLevel [Byte0]: 53
1751 12:47:42.650775 [Byte1]: 53
1752 12:47:42.654836
1753 12:47:42.655027 Set Vref, RX VrefLevel [Byte0]: 54
1754 12:47:42.658329 [Byte1]: 54
1755 12:47:42.662417
1756 12:47:42.662600 Set Vref, RX VrefLevel [Byte0]: 55
1757 12:47:42.665836 [Byte1]: 55
1758 12:47:42.670003
1759 12:47:42.670205 Set Vref, RX VrefLevel [Byte0]: 56
1760 12:47:42.673176 [Byte1]: 56
1761 12:47:42.677262
1762 12:47:42.677442 Set Vref, RX VrefLevel [Byte0]: 57
1763 12:47:42.680796 [Byte1]: 57
1764 12:47:42.684720
1765 12:47:42.684918 Set Vref, RX VrefLevel [Byte0]: 58
1766 12:47:42.688145 [Byte1]: 58
1767 12:47:42.692412
1768 12:47:42.692602 Set Vref, RX VrefLevel [Byte0]: 59
1769 12:47:42.695477 [Byte1]: 59
1770 12:47:42.700160
1771 12:47:42.700452 Set Vref, RX VrefLevel [Byte0]: 60
1772 12:47:42.703686 [Byte1]: 60
1773 12:47:42.707489
1774 12:47:42.707757 Set Vref, RX VrefLevel [Byte0]: 61
1775 12:47:42.711033 [Byte1]: 61
1776 12:47:42.714908
1777 12:47:42.715117 Set Vref, RX VrefLevel [Byte0]: 62
1778 12:47:42.718474 [Byte1]: 62
1779 12:47:42.723062
1780 12:47:42.723267 Set Vref, RX VrefLevel [Byte0]: 63
1781 12:47:42.725845 [Byte1]: 63
1782 12:47:42.730453
1783 12:47:42.730653 Set Vref, RX VrefLevel [Byte0]: 64
1784 12:47:42.733474 [Byte1]: 64
1785 12:47:42.737622
1786 12:47:42.737776 Set Vref, RX VrefLevel [Byte0]: 65
1787 12:47:42.740939 [Byte1]: 65
1788 12:47:42.745316
1789 12:47:42.745509 Set Vref, RX VrefLevel [Byte0]: 66
1790 12:47:42.748661 [Byte1]: 66
1791 12:47:42.752631
1792 12:47:42.752826 Set Vref, RX VrefLevel [Byte0]: 67
1793 12:47:42.756215 [Byte1]: 67
1794 12:47:42.760161
1795 12:47:42.760365 Set Vref, RX VrefLevel [Byte0]: 68
1796 12:47:42.763735 [Byte1]: 68
1797 12:47:42.767919
1798 12:47:42.768097 Set Vref, RX VrefLevel [Byte0]: 69
1799 12:47:42.771214 [Byte1]: 69
1800 12:47:42.775599
1801 12:47:42.775795 Set Vref, RX VrefLevel [Byte0]: 70
1802 12:47:42.779272 [Byte1]: 70
1803 12:47:42.783098
1804 12:47:42.783276 Set Vref, RX VrefLevel [Byte0]: 71
1805 12:47:42.786473 [Byte1]: 71
1806 12:47:42.790421
1807 12:47:42.790624 Set Vref, RX VrefLevel [Byte0]: 72
1808 12:47:42.793690 [Byte1]: 72
1809 12:47:42.798242
1810 12:47:42.798455 Set Vref, RX VrefLevel [Byte0]: 73
1811 12:47:42.801642 [Byte1]: 73
1812 12:47:42.805627
1813 12:47:42.805828 Set Vref, RX VrefLevel [Byte0]: 74
1814 12:47:42.808988 [Byte1]: 74
1815 12:47:42.813605
1816 12:47:42.813776 Set Vref, RX VrefLevel [Byte0]: 75
1817 12:47:42.816227 [Byte1]: 75
1818 12:47:42.821242
1819 12:47:42.821429 Final RX Vref Byte 0 = 55 to rank0
1820 12:47:42.823893 Final RX Vref Byte 1 = 54 to rank0
1821 12:47:42.827210 Final RX Vref Byte 0 = 55 to rank1
1822 12:47:42.830887 Final RX Vref Byte 1 = 54 to rank1==
1823 12:47:42.834072 Dram Type= 6, Freq= 0, CH_1, rank 0
1824 12:47:42.837626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1825 12:47:42.840900 ==
1826 12:47:42.841038 DQS Delay:
1827 12:47:42.841142 DQS0 = 0, DQS1 = 0
1828 12:47:42.844103 DQM Delay:
1829 12:47:42.844329 DQM0 = 95, DQM1 = 90
1830 12:47:42.847281 DQ Delay:
1831 12:47:42.850953 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =96
1832 12:47:42.851125 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
1833 12:47:42.854331 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1834 12:47:42.857813 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1835 12:47:42.861057
1836 12:47:42.861267
1837 12:47:42.867826 [DQSOSCAuto] RK0, (LSB)MR18= 0x324e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1838 12:47:42.871155 CH1 RK0: MR19=606, MR18=324E
1839 12:47:42.877532 CH1_RK0: MR19=0x606, MR18=0x324E, DQSOSC=390, MR23=63, INC=97, DEC=64
1840 12:47:42.877725
1841 12:47:42.880720 ----->DramcWriteLeveling(PI) begin...
1842 12:47:42.880871 ==
1843 12:47:42.884434 Dram Type= 6, Freq= 0, CH_1, rank 1
1844 12:47:42.887764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1845 12:47:42.887941 ==
1846 12:47:42.891231 Write leveling (Byte 0): 28 => 28
1847 12:47:42.894162 Write leveling (Byte 1): 28 => 28
1848 12:47:42.897847 DramcWriteLeveling(PI) end<-----
1849 12:47:42.898054
1850 12:47:42.898180 ==
1851 12:47:42.901061 Dram Type= 6, Freq= 0, CH_1, rank 1
1852 12:47:42.904535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1853 12:47:42.904708 ==
1854 12:47:42.907444 [Gating] SW mode calibration
1855 12:47:42.914573 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1856 12:47:42.920826 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1857 12:47:42.924087 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1858 12:47:42.927904 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1859 12:47:42.934723 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 12:47:42.937696 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 12:47:42.940944 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 12:47:42.948100 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 12:47:42.951073 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 12:47:42.954342 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 12:47:42.957532 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 12:47:42.964855 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 12:47:42.967581 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 12:47:42.971058 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 12:47:42.978079 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 12:47:42.980904 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 12:47:42.984752 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 12:47:42.990988 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 12:47:42.994437 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1874 12:47:42.997709 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1875 12:47:43.004512 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1876 12:47:43.008045 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 12:47:43.011473 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 12:47:43.018133 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 12:47:43.021474 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 12:47:43.024690 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 12:47:43.027852 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 12:47:43.034602 0 9 4 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1883 12:47:43.038055 0 9 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
1884 12:47:43.041442 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1885 12:47:43.048301 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1886 12:47:43.051662 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1887 12:47:43.054720 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 12:47:43.061499 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 12:47:43.064809 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 12:47:43.067869 0 10 4 | B1->B0 | 2b2b 3232 | 0 0 | (0 0) (0 0)
1891 12:47:43.074844 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 12:47:43.078104 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 12:47:43.081591 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 12:47:43.087897 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 12:47:43.091155 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 12:47:43.094601 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 12:47:43.101413 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 12:47:43.105065 0 11 4 | B1->B0 | 3939 2e2e | 0 0 | (1 1) (0 0)
1899 12:47:43.108371 0 11 8 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
1900 12:47:43.114675 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1901 12:47:43.118043 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 12:47:43.121400 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 12:47:43.124708 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 12:47:43.131843 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 12:47:43.135079 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 12:47:43.138550 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1907 12:47:43.144929 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1908 12:47:43.148457 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 12:47:43.151797 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 12:47:43.158078 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 12:47:43.161480 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 12:47:43.165099 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 12:47:43.171722 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 12:47:43.175062 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 12:47:43.178429 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 12:47:43.185050 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 12:47:43.188264 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 12:47:43.191917 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 12:47:43.195153 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 12:47:43.202017 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 12:47:43.205679 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1922 12:47:43.208223 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1923 12:47:43.215182 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 12:47:43.218496 Total UI for P1: 0, mck2ui 16
1925 12:47:43.221957 best dqsien dly found for B0: ( 0, 14, 4)
1926 12:47:43.222144 Total UI for P1: 0, mck2ui 16
1927 12:47:43.228723 best dqsien dly found for B1: ( 0, 14, 2)
1928 12:47:43.231505 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1929 12:47:43.234958 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1930 12:47:43.235171
1931 12:47:43.238585 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1932 12:47:43.241621 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1933 12:47:43.245129 [Gating] SW calibration Done
1934 12:47:43.245335 ==
1935 12:47:43.248605 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 12:47:43.252083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 12:47:43.252254 ==
1938 12:47:43.255506 RX Vref Scan: 0
1939 12:47:43.255655
1940 12:47:43.255728 RX Vref 0 -> 0, step: 1
1941 12:47:43.255791
1942 12:47:43.258881 RX Delay -130 -> 252, step: 16
1943 12:47:43.261998 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1944 12:47:43.268669 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1945 12:47:43.271935 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1946 12:47:43.275590 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1947 12:47:43.278967 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1948 12:47:43.281889 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1949 12:47:43.285260 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1950 12:47:43.292344 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1951 12:47:43.295656 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1952 12:47:43.298671 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1953 12:47:43.301851 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1954 12:47:43.308519 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1955 12:47:43.312104 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1956 12:47:43.315528 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1957 12:47:43.318596 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1958 12:47:43.321761 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1959 12:47:43.321926 ==
1960 12:47:43.325049 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 12:47:43.331863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 12:47:43.332058 ==
1963 12:47:43.332168 DQS Delay:
1964 12:47:43.335285 DQS0 = 0, DQS1 = 0
1965 12:47:43.335439 DQM Delay:
1966 12:47:43.338605 DQM0 = 92, DQM1 = 87
1967 12:47:43.338772 DQ Delay:
1968 12:47:43.341559 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1969 12:47:43.344807 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1970 12:47:43.348276 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1971 12:47:43.351684 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1972 12:47:43.351856
1973 12:47:43.351965
1974 12:47:43.352069 ==
1975 12:47:43.355158 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 12:47:43.358610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 12:47:43.358765 ==
1978 12:47:43.358837
1979 12:47:43.358905
1980 12:47:43.361649 TX Vref Scan disable
1981 12:47:43.365012 == TX Byte 0 ==
1982 12:47:43.368527 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1983 12:47:43.371546 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1984 12:47:43.375128 == TX Byte 1 ==
1985 12:47:43.378408 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1986 12:47:43.381441 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1987 12:47:43.381611 ==
1988 12:47:43.385164 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 12:47:43.388137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 12:47:43.391780 ==
1991 12:47:43.403147 TX Vref=22, minBit 1, minWin=26, winSum=441
1992 12:47:43.406052 TX Vref=24, minBit 1, minWin=26, winSum=443
1993 12:47:43.409556 TX Vref=26, minBit 0, minWin=27, winSum=449
1994 12:47:43.412952 TX Vref=28, minBit 2, minWin=27, winSum=453
1995 12:47:43.416220 TX Vref=30, minBit 2, minWin=27, winSum=452
1996 12:47:43.419819 TX Vref=32, minBit 1, minWin=27, winSum=448
1997 12:47:43.426233 [TxChooseVref] Worse bit 2, Min win 27, Win sum 453, Final Vref 28
1998 12:47:43.426466
1999 12:47:43.429953 Final TX Range 1 Vref 28
2000 12:47:43.430150
2001 12:47:43.430250 ==
2002 12:47:43.432817 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 12:47:43.436512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 12:47:43.436698 ==
2005 12:47:43.436822
2006 12:47:43.439950
2007 12:47:43.440125 TX Vref Scan disable
2008 12:47:43.442766 == TX Byte 0 ==
2009 12:47:43.446087 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2010 12:47:43.449515 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2011 12:47:43.452992 == TX Byte 1 ==
2012 12:47:43.456240 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2013 12:47:43.459471 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2014 12:47:43.462972
2015 12:47:43.463162 [DATLAT]
2016 12:47:43.463266 Freq=800, CH1 RK1
2017 12:47:43.463379
2018 12:47:43.466343 DATLAT Default: 0xa
2019 12:47:43.466480 0, 0xFFFF, sum = 0
2020 12:47:43.469948 1, 0xFFFF, sum = 0
2021 12:47:43.470108 2, 0xFFFF, sum = 0
2022 12:47:43.472970 3, 0xFFFF, sum = 0
2023 12:47:43.473162 4, 0xFFFF, sum = 0
2024 12:47:43.476351 5, 0xFFFF, sum = 0
2025 12:47:43.476492 6, 0xFFFF, sum = 0
2026 12:47:43.479733 7, 0xFFFF, sum = 0
2027 12:47:43.483128 8, 0xFFFF, sum = 0
2028 12:47:43.483324 9, 0x0, sum = 1
2029 12:47:43.483500 10, 0x0, sum = 2
2030 12:47:43.486600 11, 0x0, sum = 3
2031 12:47:43.486844 12, 0x0, sum = 4
2032 12:47:43.489592 best_step = 10
2033 12:47:43.489754
2034 12:47:43.489854 ==
2035 12:47:43.493000 Dram Type= 6, Freq= 0, CH_1, rank 1
2036 12:47:43.496435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2037 12:47:43.496617 ==
2038 12:47:43.499831 RX Vref Scan: 0
2039 12:47:43.500036
2040 12:47:43.500164 RX Vref 0 -> 0, step: 1
2041 12:47:43.500280
2042 12:47:43.502950 RX Delay -79 -> 252, step: 8
2043 12:47:43.509497 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2044 12:47:43.512786 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2045 12:47:43.516191 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2046 12:47:43.519883 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2047 12:47:43.523220 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2048 12:47:43.526217 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2049 12:47:43.533009 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2050 12:47:43.536461 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2051 12:47:43.539902 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2052 12:47:43.543218 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2053 12:47:43.546193 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2054 12:47:43.553287 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2055 12:47:43.556683 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2056 12:47:43.560087 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2057 12:47:43.563491 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2058 12:47:43.566635 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2059 12:47:43.566851 ==
2060 12:47:43.570100 Dram Type= 6, Freq= 0, CH_1, rank 1
2061 12:47:43.576451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2062 12:47:43.576744 ==
2063 12:47:43.576858 DQS Delay:
2064 12:47:43.579623 DQS0 = 0, DQS1 = 0
2065 12:47:43.579807 DQM Delay:
2066 12:47:43.579906 DQM0 = 97, DQM1 = 91
2067 12:47:43.583171 DQ Delay:
2068 12:47:43.586692 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2069 12:47:43.589753 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2070 12:47:43.593035 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2071 12:47:43.596750 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2072 12:47:43.596972
2073 12:47:43.597086
2074 12:47:43.603591 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
2075 12:47:43.606796 CH1 RK1: MR19=606, MR18=4B15
2076 12:47:43.613526 CH1_RK1: MR19=0x606, MR18=0x4B15, DQSOSC=391, MR23=63, INC=96, DEC=64
2077 12:47:43.616981 [RxdqsGatingPostProcess] freq 800
2078 12:47:43.620203 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2079 12:47:43.623419 Pre-setting of DQS Precalculation
2080 12:47:43.630168 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2081 12:47:43.636892 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2082 12:47:43.643129 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2083 12:47:43.643326
2084 12:47:43.643465
2085 12:47:43.646537 [Calibration Summary] 1600 Mbps
2086 12:47:43.646716 CH 0, Rank 0
2087 12:47:43.650093 SW Impedance : PASS
2088 12:47:43.653491 DUTY Scan : NO K
2089 12:47:43.653699 ZQ Calibration : PASS
2090 12:47:43.656953 Jitter Meter : NO K
2091 12:47:43.660038 CBT Training : PASS
2092 12:47:43.660219 Write leveling : PASS
2093 12:47:43.663626 RX DQS gating : PASS
2094 12:47:43.667017 RX DQ/DQS(RDDQC) : PASS
2095 12:47:43.667186 TX DQ/DQS : PASS
2096 12:47:43.670037 RX DATLAT : PASS
2097 12:47:43.670202 RX DQ/DQS(Engine): PASS
2098 12:47:43.673595 TX OE : NO K
2099 12:47:43.673764 All Pass.
2100 12:47:43.673869
2101 12:47:43.676869 CH 0, Rank 1
2102 12:47:43.677059 SW Impedance : PASS
2103 12:47:43.680012 DUTY Scan : NO K
2104 12:47:43.683676 ZQ Calibration : PASS
2105 12:47:43.683862 Jitter Meter : NO K
2106 12:47:43.686466 CBT Training : PASS
2107 12:47:43.690199 Write leveling : PASS
2108 12:47:43.690362 RX DQS gating : PASS
2109 12:47:43.693455 RX DQ/DQS(RDDQC) : PASS
2110 12:47:43.697095 TX DQ/DQS : PASS
2111 12:47:43.697292 RX DATLAT : PASS
2112 12:47:43.700360 RX DQ/DQS(Engine): PASS
2113 12:47:43.703645 TX OE : NO K
2114 12:47:43.703815 All Pass.
2115 12:47:43.703949
2116 12:47:43.704018 CH 1, Rank 0
2117 12:47:43.706865 SW Impedance : PASS
2118 12:47:43.710393 DUTY Scan : NO K
2119 12:47:43.710579 ZQ Calibration : PASS
2120 12:47:43.713401 Jitter Meter : NO K
2121 12:47:43.713573 CBT Training : PASS
2122 12:47:43.716955 Write leveling : PASS
2123 12:47:43.719869 RX DQS gating : PASS
2124 12:47:43.720146 RX DQ/DQS(RDDQC) : PASS
2125 12:47:43.723494 TX DQ/DQS : PASS
2126 12:47:43.726991 RX DATLAT : PASS
2127 12:47:43.727190 RX DQ/DQS(Engine): PASS
2128 12:47:43.729885 TX OE : NO K
2129 12:47:43.730076 All Pass.
2130 12:47:43.730201
2131 12:47:43.733696 CH 1, Rank 1
2132 12:47:43.733900 SW Impedance : PASS
2133 12:47:43.736503 DUTY Scan : NO K
2134 12:47:43.740119 ZQ Calibration : PASS
2135 12:47:43.740337 Jitter Meter : NO K
2136 12:47:43.743666 CBT Training : PASS
2137 12:47:43.746914 Write leveling : PASS
2138 12:47:43.747077 RX DQS gating : PASS
2139 12:47:43.750196 RX DQ/DQS(RDDQC) : PASS
2140 12:47:43.750411 TX DQ/DQS : PASS
2141 12:47:43.753603 RX DATLAT : PASS
2142 12:47:43.756854 RX DQ/DQS(Engine): PASS
2143 12:47:43.757014 TX OE : NO K
2144 12:47:43.759911 All Pass.
2145 12:47:43.760081
2146 12:47:43.760190 DramC Write-DBI off
2147 12:47:43.764000 PER_BANK_REFRESH: Hybrid Mode
2148 12:47:43.766893 TX_TRACKING: ON
2149 12:47:43.770118 [GetDramInforAfterCalByMRR] Vendor 6.
2150 12:47:43.773476 [GetDramInforAfterCalByMRR] Revision 606.
2151 12:47:43.776898 [GetDramInforAfterCalByMRR] Revision 2 0.
2152 12:47:43.777073 MR0 0x3b3b
2153 12:47:43.777171 MR8 0x5151
2154 12:47:43.783435 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2155 12:47:43.783629
2156 12:47:43.783733 MR0 0x3b3b
2157 12:47:43.783829 MR8 0x5151
2158 12:47:43.786706 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2159 12:47:43.786972
2160 12:47:43.796316 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2161 12:47:43.800075 [FAST_K] Save calibration result to emmc
2162 12:47:43.803451 [FAST_K] Save calibration result to emmc
2163 12:47:43.806616 dram_init: config_dvfs: 1
2164 12:47:43.810019 dramc_set_vcore_voltage set vcore to 662500
2165 12:47:43.813227 Read voltage for 1200, 2
2166 12:47:43.813441 Vio18 = 0
2167 12:47:43.813572 Vcore = 662500
2168 12:47:43.817034 Vdram = 0
2169 12:47:43.817217 Vddq = 0
2170 12:47:43.817314 Vmddr = 0
2171 12:47:43.823134 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2172 12:47:43.827004 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2173 12:47:43.829708 MEM_TYPE=3, freq_sel=15
2174 12:47:43.833339 sv_algorithm_assistance_LP4_1600
2175 12:47:43.836429 ============ PULL DRAM RESETB DOWN ============
2176 12:47:43.840115 ========== PULL DRAM RESETB DOWN end =========
2177 12:47:43.846328 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2178 12:47:43.849919 ===================================
2179 12:47:43.853460 LPDDR4 DRAM CONFIGURATION
2180 12:47:43.856901 ===================================
2181 12:47:43.857077 EX_ROW_EN[0] = 0x0
2182 12:47:43.860326 EX_ROW_EN[1] = 0x0
2183 12:47:43.860496 LP4Y_EN = 0x0
2184 12:47:43.863145 WORK_FSP = 0x0
2185 12:47:43.863287 WL = 0x4
2186 12:47:43.866553 RL = 0x4
2187 12:47:43.866728 BL = 0x2
2188 12:47:43.869982 RPST = 0x0
2189 12:47:43.870115 RD_PRE = 0x0
2190 12:47:43.873503 WR_PRE = 0x1
2191 12:47:43.873666 WR_PST = 0x0
2192 12:47:43.876982 DBI_WR = 0x0
2193 12:47:43.877160 DBI_RD = 0x0
2194 12:47:43.879881 OTF = 0x1
2195 12:47:43.883735 ===================================
2196 12:47:43.886655 ===================================
2197 12:47:43.886842 ANA top config
2198 12:47:43.889772 ===================================
2199 12:47:43.893105 DLL_ASYNC_EN = 0
2200 12:47:43.896527 ALL_SLAVE_EN = 0
2201 12:47:43.899986 NEW_RANK_MODE = 1
2202 12:47:43.900218 DLL_IDLE_MODE = 1
2203 12:47:43.903365 LP45_APHY_COMB_EN = 1
2204 12:47:43.906867 TX_ODT_DIS = 1
2205 12:47:43.910471 NEW_8X_MODE = 1
2206 12:47:43.913343 ===================================
2207 12:47:43.916682 ===================================
2208 12:47:43.920295 data_rate = 2400
2209 12:47:43.920478 CKR = 1
2210 12:47:43.923150 DQ_P2S_RATIO = 8
2211 12:47:43.926411 ===================================
2212 12:47:43.930078 CA_P2S_RATIO = 8
2213 12:47:43.933164 DQ_CA_OPEN = 0
2214 12:47:43.937089 DQ_SEMI_OPEN = 0
2215 12:47:43.937268 CA_SEMI_OPEN = 0
2216 12:47:43.940001 CA_FULL_RATE = 0
2217 12:47:43.943287 DQ_CKDIV4_EN = 0
2218 12:47:43.946912 CA_CKDIV4_EN = 0
2219 12:47:43.949993 CA_PREDIV_EN = 0
2220 12:47:43.953331 PH8_DLY = 17
2221 12:47:43.953532 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2222 12:47:43.956905 DQ_AAMCK_DIV = 4
2223 12:47:43.960292 CA_AAMCK_DIV = 4
2224 12:47:43.963313 CA_ADMCK_DIV = 4
2225 12:47:43.966751 DQ_TRACK_CA_EN = 0
2226 12:47:43.970098 CA_PICK = 1200
2227 12:47:43.973461 CA_MCKIO = 1200
2228 12:47:43.973654 MCKIO_SEMI = 0
2229 12:47:43.976967 PLL_FREQ = 2366
2230 12:47:43.980387 DQ_UI_PI_RATIO = 32
2231 12:47:43.983339 CA_UI_PI_RATIO = 0
2232 12:47:43.986698 ===================================
2233 12:47:43.990219 ===================================
2234 12:47:43.993723 memory_type:LPDDR4
2235 12:47:43.993897 GP_NUM : 10
2236 12:47:43.997156 SRAM_EN : 1
2237 12:47:43.997335 MD32_EN : 0
2238 12:47:44.000393 ===================================
2239 12:47:44.003886 [ANA_INIT] >>>>>>>>>>>>>>
2240 12:47:44.007313 <<<<<< [CONFIGURE PHASE]: ANA_TX
2241 12:47:44.010063 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2242 12:47:44.013385 ===================================
2243 12:47:44.017342 data_rate = 2400,PCW = 0X5b00
2244 12:47:44.020466 ===================================
2245 12:47:44.023666 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2246 12:47:44.027422 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2247 12:47:44.033916 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2248 12:47:44.040357 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2249 12:47:44.043693 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2250 12:47:44.047314 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2251 12:47:44.047514 [ANA_INIT] flow start
2252 12:47:44.050532 [ANA_INIT] PLL >>>>>>>>
2253 12:47:44.053786 [ANA_INIT] PLL <<<<<<<<
2254 12:47:44.053970 [ANA_INIT] MIDPI >>>>>>>>
2255 12:47:44.057394 [ANA_INIT] MIDPI <<<<<<<<
2256 12:47:44.060834 [ANA_INIT] DLL >>>>>>>>
2257 12:47:44.061023 [ANA_INIT] DLL <<<<<<<<
2258 12:47:44.063825 [ANA_INIT] flow end
2259 12:47:44.067651 ============ LP4 DIFF to SE enter ============
2260 12:47:44.070569 ============ LP4 DIFF to SE exit ============
2261 12:47:44.073969 [ANA_INIT] <<<<<<<<<<<<<
2262 12:47:44.077176 [Flow] Enable top DCM control >>>>>
2263 12:47:44.080562 [Flow] Enable top DCM control <<<<<
2264 12:47:44.084195 Enable DLL master slave shuffle
2265 12:47:44.090625 ==============================================================
2266 12:47:44.090825 Gating Mode config
2267 12:47:44.097489 ==============================================================
2268 12:47:44.097668 Config description:
2269 12:47:44.107504 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2270 12:47:44.114255 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2271 12:47:44.120799 SELPH_MODE 0: By rank 1: By Phase
2272 12:47:44.124194 ==============================================================
2273 12:47:44.127820 GAT_TRACK_EN = 1
2274 12:47:44.130912 RX_GATING_MODE = 2
2275 12:47:44.134117 RX_GATING_TRACK_MODE = 2
2276 12:47:44.137536 SELPH_MODE = 1
2277 12:47:44.141161 PICG_EARLY_EN = 1
2278 12:47:44.144512 VALID_LAT_VALUE = 1
2279 12:47:44.147455 ==============================================================
2280 12:47:44.150872 Enter into Gating configuration >>>>
2281 12:47:44.154380 Exit from Gating configuration <<<<
2282 12:47:44.157874 Enter into DVFS_PRE_config >>>>>
2283 12:47:44.167901 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2284 12:47:44.171117 Exit from DVFS_PRE_config <<<<<
2285 12:47:44.174357 Enter into PICG configuration >>>>
2286 12:47:44.178002 Exit from PICG configuration <<<<
2287 12:47:44.181276 [RX_INPUT] configuration >>>>>
2288 12:47:44.184787 [RX_INPUT] configuration <<<<<
2289 12:47:44.191110 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2290 12:47:44.194329 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2291 12:47:44.200987 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2292 12:47:44.208184 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2293 12:47:44.214542 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2294 12:47:44.221257 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2295 12:47:44.224556 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2296 12:47:44.227984 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2297 12:47:44.231404 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2298 12:47:44.234881 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2299 12:47:44.241496 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2300 12:47:44.244404 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2301 12:47:44.247809 ===================================
2302 12:47:44.251547 LPDDR4 DRAM CONFIGURATION
2303 12:47:44.254869 ===================================
2304 12:47:44.255090 EX_ROW_EN[0] = 0x0
2305 12:47:44.257968 EX_ROW_EN[1] = 0x0
2306 12:47:44.258141 LP4Y_EN = 0x0
2307 12:47:44.261356 WORK_FSP = 0x0
2308 12:47:44.261531 WL = 0x4
2309 12:47:44.264874 RL = 0x4
2310 12:47:44.265053 BL = 0x2
2311 12:47:44.268542 RPST = 0x0
2312 12:47:44.268710 RD_PRE = 0x0
2313 12:47:44.271649 WR_PRE = 0x1
2314 12:47:44.271841 WR_PST = 0x0
2315 12:47:44.274999 DBI_WR = 0x0
2316 12:47:44.275183 DBI_RD = 0x0
2317 12:47:44.278065 OTF = 0x1
2318 12:47:44.281374 ===================================
2319 12:47:44.284778 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2320 12:47:44.288083 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2321 12:47:44.294625 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2322 12:47:44.298252 ===================================
2323 12:47:44.298450 LPDDR4 DRAM CONFIGURATION
2324 12:47:44.301551 ===================================
2325 12:47:44.305260 EX_ROW_EN[0] = 0x10
2326 12:47:44.307925 EX_ROW_EN[1] = 0x0
2327 12:47:44.308118 LP4Y_EN = 0x0
2328 12:47:44.311418 WORK_FSP = 0x0
2329 12:47:44.311654 WL = 0x4
2330 12:47:44.314853 RL = 0x4
2331 12:47:44.315032 BL = 0x2
2332 12:47:44.318061 RPST = 0x0
2333 12:47:44.318246 RD_PRE = 0x0
2334 12:47:44.321313 WR_PRE = 0x1
2335 12:47:44.321501 WR_PST = 0x0
2336 12:47:44.324986 DBI_WR = 0x0
2337 12:47:44.325167 DBI_RD = 0x0
2338 12:47:44.327964 OTF = 0x1
2339 12:47:44.331318 ===================================
2340 12:47:44.337920 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2341 12:47:44.338077 ==
2342 12:47:44.341832 Dram Type= 6, Freq= 0, CH_0, rank 0
2343 12:47:44.345200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2344 12:47:44.345401 ==
2345 12:47:44.348090 [Duty_Offset_Calibration]
2346 12:47:44.348263 B0:2 B1:1 CA:1
2347 12:47:44.348382
2348 12:47:44.351263 [DutyScan_Calibration_Flow] k_type=0
2349 12:47:44.361551
2350 12:47:44.361750 ==CLK 0==
2351 12:47:44.365234 Final CLK duty delay cell = 0
2352 12:47:44.368512 [0] MAX Duty = 5218%(X100), DQS PI = 24
2353 12:47:44.371923 [0] MIN Duty = 4844%(X100), DQS PI = 48
2354 12:47:44.372129 [0] AVG Duty = 5031%(X100)
2355 12:47:44.375003
2356 12:47:44.378243 CH0 CLK Duty spec in!! Max-Min= 374%
2357 12:47:44.381437 [DutyScan_Calibration_Flow] ====Done====
2358 12:47:44.381622
2359 12:47:44.384550 [DutyScan_Calibration_Flow] k_type=1
2360 12:47:44.399442
2361 12:47:44.399648 ==DQS 0 ==
2362 12:47:44.402841 Final DQS duty delay cell = -4
2363 12:47:44.406153 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2364 12:47:44.409726 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2365 12:47:44.412666 [-4] AVG Duty = 4953%(X100)
2366 12:47:44.412805
2367 12:47:44.412877 ==DQS 1 ==
2368 12:47:44.416079 Final DQS duty delay cell = -4
2369 12:47:44.419673 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2370 12:47:44.422487 [-4] MIN Duty = 4844%(X100), DQS PI = 30
2371 12:47:44.426161 [-4] AVG Duty = 4906%(X100)
2372 12:47:44.426373
2373 12:47:44.429311 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2374 12:47:44.429507
2375 12:47:44.432890 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2376 12:47:44.436305 [DutyScan_Calibration_Flow] ====Done====
2377 12:47:44.436515
2378 12:47:44.439499 [DutyScan_Calibration_Flow] k_type=3
2379 12:47:44.456580
2380 12:47:44.456802 ==DQM 0 ==
2381 12:47:44.460146 Final DQM duty delay cell = 0
2382 12:47:44.463080 [0] MAX Duty = 5156%(X100), DQS PI = 26
2383 12:47:44.466663 [0] MIN Duty = 4906%(X100), DQS PI = 52
2384 12:47:44.466846 [0] AVG Duty = 5031%(X100)
2385 12:47:44.470110
2386 12:47:44.470306 ==DQM 1 ==
2387 12:47:44.473169 Final DQM duty delay cell = 0
2388 12:47:44.476301 [0] MAX Duty = 5125%(X100), DQS PI = 60
2389 12:47:44.479664 [0] MIN Duty = 5031%(X100), DQS PI = 36
2390 12:47:44.483028 [0] AVG Duty = 5078%(X100)
2391 12:47:44.483256
2392 12:47:44.486647 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2393 12:47:44.486865
2394 12:47:44.489821 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2395 12:47:44.493173 [DutyScan_Calibration_Flow] ====Done====
2396 12:47:44.493368
2397 12:47:44.496931 [DutyScan_Calibration_Flow] k_type=2
2398 12:47:44.513522
2399 12:47:44.513714 ==DQ 0 ==
2400 12:47:44.516240 Final DQ duty delay cell = 0
2401 12:47:44.519689 [0] MAX Duty = 5062%(X100), DQS PI = 32
2402 12:47:44.523300 [0] MIN Duty = 4906%(X100), DQS PI = 0
2403 12:47:44.523479 [0] AVG Duty = 4984%(X100)
2404 12:47:44.523597
2405 12:47:44.526751 ==DQ 1 ==
2406 12:47:44.526926 Final DQ duty delay cell = 0
2407 12:47:44.533094 [0] MAX Duty = 5093%(X100), DQS PI = 10
2408 12:47:44.536853 [0] MIN Duty = 4938%(X100), DQS PI = 36
2409 12:47:44.537072 [0] AVG Duty = 5015%(X100)
2410 12:47:44.537179
2411 12:47:44.540087 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2412 12:47:44.540293
2413 12:47:44.543539 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2414 12:47:44.549845 [DutyScan_Calibration_Flow] ====Done====
2415 12:47:44.550052 ==
2416 12:47:44.553235 Dram Type= 6, Freq= 0, CH_1, rank 0
2417 12:47:44.556811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2418 12:47:44.556987 ==
2419 12:47:44.559996 [Duty_Offset_Calibration]
2420 12:47:44.560149 B0:1 B1:0 CA:0
2421 12:47:44.560221
2422 12:47:44.563602 [DutyScan_Calibration_Flow] k_type=0
2423 12:47:44.571940
2424 12:47:44.572157 ==CLK 0==
2425 12:47:44.575442 Final CLK duty delay cell = -4
2426 12:47:44.578940 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2427 12:47:44.582164 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2428 12:47:44.585583 [-4] AVG Duty = 4937%(X100)
2429 12:47:44.585779
2430 12:47:44.589089 CH1 CLK Duty spec in!! Max-Min= 125%
2431 12:47:44.592547 [DutyScan_Calibration_Flow] ====Done====
2432 12:47:44.592737
2433 12:47:44.595187 [DutyScan_Calibration_Flow] k_type=1
2434 12:47:44.611110
2435 12:47:44.611273 ==DQS 0 ==
2436 12:47:44.614823 Final DQS duty delay cell = 0
2437 12:47:44.617834 [0] MAX Duty = 5094%(X100), DQS PI = 26
2438 12:47:44.621210 [0] MIN Duty = 4875%(X100), DQS PI = 0
2439 12:47:44.624601 [0] AVG Duty = 4984%(X100)
2440 12:47:44.624797
2441 12:47:44.624904 ==DQS 1 ==
2442 12:47:44.628022 Final DQS duty delay cell = -4
2443 12:47:44.631202 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2444 12:47:44.634460 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2445 12:47:44.638172 [-4] AVG Duty = 4906%(X100)
2446 12:47:44.638388
2447 12:47:44.641465 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2448 12:47:44.641664
2449 12:47:44.644159 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2450 12:47:44.647950 [DutyScan_Calibration_Flow] ====Done====
2451 12:47:44.648138
2452 12:47:44.650743 [DutyScan_Calibration_Flow] k_type=3
2453 12:47:44.667865
2454 12:47:44.668082 ==DQM 0 ==
2455 12:47:44.671308 Final DQM duty delay cell = 0
2456 12:47:44.675111 [0] MAX Duty = 5156%(X100), DQS PI = 6
2457 12:47:44.678287 [0] MIN Duty = 5031%(X100), DQS PI = 0
2458 12:47:44.678466 [0] AVG Duty = 5093%(X100)
2459 12:47:44.678572
2460 12:47:44.681470 ==DQM 1 ==
2461 12:47:44.684844 Final DQM duty delay cell = 0
2462 12:47:44.688296 [0] MAX Duty = 5062%(X100), DQS PI = 28
2463 12:47:44.691442 [0] MIN Duty = 4907%(X100), DQS PI = 36
2464 12:47:44.691651 [0] AVG Duty = 4984%(X100)
2465 12:47:44.691728
2466 12:47:44.698328 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2467 12:47:44.698514
2468 12:47:44.701777 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2469 12:47:44.705047 [DutyScan_Calibration_Flow] ====Done====
2470 12:47:44.705227
2471 12:47:44.708487 [DutyScan_Calibration_Flow] k_type=2
2472 12:47:44.723750
2473 12:47:44.723940 ==DQ 0 ==
2474 12:47:44.727361 Final DQ duty delay cell = -4
2475 12:47:44.730666 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2476 12:47:44.734189 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2477 12:47:44.734400 [-4] AVG Duty = 5000%(X100)
2478 12:47:44.737435
2479 12:47:44.737623 ==DQ 1 ==
2480 12:47:44.740727 Final DQ duty delay cell = 0
2481 12:47:44.744057 [0] MAX Duty = 5125%(X100), DQS PI = 20
2482 12:47:44.747348 [0] MIN Duty = 4938%(X100), DQS PI = 34
2483 12:47:44.747552 [0] AVG Duty = 5031%(X100)
2484 12:47:44.747661
2485 12:47:44.750678 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2486 12:47:44.754157
2487 12:47:44.757104 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2488 12:47:44.760943 [DutyScan_Calibration_Flow] ====Done====
2489 12:47:44.764081 nWR fixed to 30
2490 12:47:44.764264 [ModeRegInit_LP4] CH0 RK0
2491 12:47:44.767275 [ModeRegInit_LP4] CH0 RK1
2492 12:47:44.770650 [ModeRegInit_LP4] CH1 RK0
2493 12:47:44.770841 [ModeRegInit_LP4] CH1 RK1
2494 12:47:44.773821 match AC timing 7
2495 12:47:44.777366 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2496 12:47:44.780688 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2497 12:47:44.787195 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2498 12:47:44.790771 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2499 12:47:44.797719 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2500 12:47:44.797908 ==
2501 12:47:44.800593 Dram Type= 6, Freq= 0, CH_0, rank 0
2502 12:47:44.804078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2503 12:47:44.804243 ==
2504 12:47:44.810957 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2505 12:47:44.814008 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2506 12:47:44.824345 [CA 0] Center 39 (8~70) winsize 63
2507 12:47:44.827396 [CA 1] Center 39 (8~70) winsize 63
2508 12:47:44.830980 [CA 2] Center 35 (5~66) winsize 62
2509 12:47:44.834369 [CA 3] Center 34 (4~65) winsize 62
2510 12:47:44.837414 [CA 4] Center 33 (3~64) winsize 62
2511 12:47:44.840551 [CA 5] Center 32 (3~62) winsize 60
2512 12:47:44.840764
2513 12:47:44.843961 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2514 12:47:44.844150
2515 12:47:44.847346 [CATrainingPosCal] consider 1 rank data
2516 12:47:44.851132 u2DelayCellTimex100 = 270/100 ps
2517 12:47:44.854320 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2518 12:47:44.857652 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2519 12:47:44.863875 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2520 12:47:44.867356 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2521 12:47:44.870864 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2522 12:47:44.874056 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2523 12:47:44.874225
2524 12:47:44.877800 CA PerBit enable=1, Macro0, CA PI delay=32
2525 12:47:44.877968
2526 12:47:44.881233 [CBTSetCACLKResult] CA Dly = 32
2527 12:47:44.881402 CS Dly: 6 (0~37)
2528 12:47:44.881515 ==
2529 12:47:44.883932 Dram Type= 6, Freq= 0, CH_0, rank 1
2530 12:47:44.890962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2531 12:47:44.891163 ==
2532 12:47:44.894456 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2533 12:47:44.900844 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2534 12:47:44.909710 [CA 0] Center 38 (8~69) winsize 62
2535 12:47:44.913152 [CA 1] Center 38 (8~69) winsize 62
2536 12:47:44.916735 [CA 2] Center 35 (5~66) winsize 62
2537 12:47:44.919834 [CA 3] Center 34 (4~65) winsize 62
2538 12:47:44.923508 [CA 4] Center 33 (3~64) winsize 62
2539 12:47:44.926763 [CA 5] Center 32 (3~62) winsize 60
2540 12:47:44.926945
2541 12:47:44.929633 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2542 12:47:44.929778
2543 12:47:44.933506 [CATrainingPosCal] consider 2 rank data
2544 12:47:44.936380 u2DelayCellTimex100 = 270/100 ps
2545 12:47:44.939895 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2546 12:47:44.943307 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2547 12:47:44.949917 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2548 12:47:44.953955 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2549 12:47:44.956779 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2550 12:47:44.960351 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2551 12:47:44.960566
2552 12:47:44.963380 CA PerBit enable=1, Macro0, CA PI delay=32
2553 12:47:44.963589
2554 12:47:44.966456 [CBTSetCACLKResult] CA Dly = 32
2555 12:47:44.966706 CS Dly: 6 (0~38)
2556 12:47:44.966837
2557 12:47:44.970235 ----->DramcWriteLeveling(PI) begin...
2558 12:47:44.973383 ==
2559 12:47:44.973600 Dram Type= 6, Freq= 0, CH_0, rank 0
2560 12:47:44.979832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2561 12:47:44.980016 ==
2562 12:47:44.983293 Write leveling (Byte 0): 33 => 33
2563 12:47:44.986533 Write leveling (Byte 1): 29 => 29
2564 12:47:44.986725 DramcWriteLeveling(PI) end<-----
2565 12:47:44.990173
2566 12:47:44.990333 ==
2567 12:47:44.993399 Dram Type= 6, Freq= 0, CH_0, rank 0
2568 12:47:44.996573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2569 12:47:44.996730 ==
2570 12:47:45.000442 [Gating] SW mode calibration
2571 12:47:45.006517 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2572 12:47:45.010093 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2573 12:47:45.016912 0 15 0 | B1->B0 | 2323 3333 | 1 1 | (0 0) (1 1)
2574 12:47:45.019846 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2575 12:47:45.023207 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2576 12:47:45.030138 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2577 12:47:45.033584 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2578 12:47:45.036693 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2579 12:47:45.043724 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2580 12:47:45.046708 0 15 28 | B1->B0 | 3333 2323 | 1 0 | (1 0) (1 0)
2581 12:47:45.050041 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2582 12:47:45.057210 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2583 12:47:45.060258 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2584 12:47:45.063588 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 12:47:45.070049 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2586 12:47:45.073553 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 12:47:45.076790 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2588 12:47:45.080106 1 0 28 | B1->B0 | 2b2b 4646 | 1 0 | (0 0) (0 0)
2589 12:47:45.087191 1 1 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
2590 12:47:45.090617 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2591 12:47:45.093772 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 12:47:45.100609 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 12:47:45.104178 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 12:47:45.106981 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 12:47:45.114009 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2596 12:47:45.117580 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2597 12:47:45.120718 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2598 12:47:45.127322 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 12:47:45.130694 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 12:47:45.134211 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 12:47:45.137161 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 12:47:45.143800 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 12:47:45.147213 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 12:47:45.150496 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 12:47:45.157218 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 12:47:45.160686 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 12:47:45.163896 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 12:47:45.170460 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 12:47:45.173798 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 12:47:45.177350 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 12:47:45.183904 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 12:47:45.187509 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2613 12:47:45.190799 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2614 12:47:45.193960 Total UI for P1: 0, mck2ui 16
2615 12:47:45.197230 best dqsien dly found for B0: ( 1, 3, 28)
2616 12:47:45.203922 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 12:47:45.204078 Total UI for P1: 0, mck2ui 16
2618 12:47:45.207856 best dqsien dly found for B1: ( 1, 4, 0)
2619 12:47:45.213874 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2620 12:47:45.217485 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2621 12:47:45.217708
2622 12:47:45.220387 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2623 12:47:45.223858 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2624 12:47:45.227085 [Gating] SW calibration Done
2625 12:47:45.227260 ==
2626 12:47:45.230620 Dram Type= 6, Freq= 0, CH_0, rank 0
2627 12:47:45.233942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2628 12:47:45.234115 ==
2629 12:47:45.237337 RX Vref Scan: 0
2630 12:47:45.237511
2631 12:47:45.237616 RX Vref 0 -> 0, step: 1
2632 12:47:45.237719
2633 12:47:45.240836 RX Delay -40 -> 252, step: 8
2634 12:47:45.243708 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2635 12:47:45.250675 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2636 12:47:45.253423 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2637 12:47:45.257515 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2638 12:47:45.260595 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2639 12:47:45.264069 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2640 12:47:45.267170 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2641 12:47:45.274095 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2642 12:47:45.277498 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2643 12:47:45.280776 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2644 12:47:45.284262 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2645 12:47:45.287109 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2646 12:47:45.293868 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2647 12:47:45.297256 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2648 12:47:45.300884 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2649 12:47:45.304215 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2650 12:47:45.304406 ==
2651 12:47:45.307239 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 12:47:45.310680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2653 12:47:45.313987 ==
2654 12:47:45.314181 DQS Delay:
2655 12:47:45.314284 DQS0 = 0, DQS1 = 0
2656 12:47:45.317406 DQM Delay:
2657 12:47:45.317576 DQM0 = 121, DQM1 = 113
2658 12:47:45.320694 DQ Delay:
2659 12:47:45.324203 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2660 12:47:45.327209 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2661 12:47:45.330798 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2662 12:47:45.333995 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2663 12:47:45.334168
2664 12:47:45.334269
2665 12:47:45.334359 ==
2666 12:47:45.337511 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 12:47:45.340651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 12:47:45.340844 ==
2669 12:47:45.340980
2670 12:47:45.341098
2671 12:47:45.344369 TX Vref Scan disable
2672 12:47:45.347270 == TX Byte 0 ==
2673 12:47:45.350745 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2674 12:47:45.353910 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2675 12:47:45.357439 == TX Byte 1 ==
2676 12:47:45.360622 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2677 12:47:45.363928 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2678 12:47:45.364108 ==
2679 12:47:45.367230 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 12:47:45.374339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 12:47:45.374525 ==
2682 12:47:45.384655 TX Vref=22, minBit 0, minWin=25, winSum=410
2683 12:47:45.388149 TX Vref=24, minBit 0, minWin=25, winSum=415
2684 12:47:45.391304 TX Vref=26, minBit 4, minWin=25, winSum=422
2685 12:47:45.394465 TX Vref=28, minBit 0, minWin=26, winSum=427
2686 12:47:45.397737 TX Vref=30, minBit 0, minWin=26, winSum=426
2687 12:47:45.401710 TX Vref=32, minBit 0, minWin=26, winSum=426
2688 12:47:45.408072 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
2689 12:47:45.408288
2690 12:47:45.411458 Final TX Range 1 Vref 28
2691 12:47:45.411627
2692 12:47:45.411701 ==
2693 12:47:45.414944 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 12:47:45.418039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 12:47:45.418222 ==
2696 12:47:45.418323
2697 12:47:45.418423
2698 12:47:45.421689 TX Vref Scan disable
2699 12:47:45.425040 == TX Byte 0 ==
2700 12:47:45.427919 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2701 12:47:45.431422 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2702 12:47:45.434676 == TX Byte 1 ==
2703 12:47:45.438189 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2704 12:47:45.441571 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2705 12:47:45.441757
2706 12:47:45.445134 [DATLAT]
2707 12:47:45.445333 Freq=1200, CH0 RK0
2708 12:47:45.445457
2709 12:47:45.448169 DATLAT Default: 0xd
2710 12:47:45.448355 0, 0xFFFF, sum = 0
2711 12:47:45.451320 1, 0xFFFF, sum = 0
2712 12:47:45.451532 2, 0xFFFF, sum = 0
2713 12:47:45.454941 3, 0xFFFF, sum = 0
2714 12:47:45.455130 4, 0xFFFF, sum = 0
2715 12:47:45.458335 5, 0xFFFF, sum = 0
2716 12:47:45.458536 6, 0xFFFF, sum = 0
2717 12:47:45.461344 7, 0xFFFF, sum = 0
2718 12:47:45.461525 8, 0xFFFF, sum = 0
2719 12:47:45.464602 9, 0xFFFF, sum = 0
2720 12:47:45.464791 10, 0xFFFF, sum = 0
2721 12:47:45.467995 11, 0xFFFF, sum = 0
2722 12:47:45.468189 12, 0x0, sum = 1
2723 12:47:45.471363 13, 0x0, sum = 2
2724 12:47:45.471600 14, 0x0, sum = 3
2725 12:47:45.474735 15, 0x0, sum = 4
2726 12:47:45.474914 best_step = 13
2727 12:47:45.475024
2728 12:47:45.475111 ==
2729 12:47:45.478195 Dram Type= 6, Freq= 0, CH_0, rank 0
2730 12:47:45.485145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2731 12:47:45.485361 ==
2732 12:47:45.485488 RX Vref Scan: 1
2733 12:47:45.485601
2734 12:47:45.488006 Set Vref Range= 32 -> 127
2735 12:47:45.488184
2736 12:47:45.491483 RX Vref 32 -> 127, step: 1
2737 12:47:45.491674
2738 12:47:45.491783 RX Delay -13 -> 252, step: 4
2739 12:47:45.495201
2740 12:47:45.495381 Set Vref, RX VrefLevel [Byte0]: 32
2741 12:47:45.498395 [Byte1]: 32
2742 12:47:45.503056
2743 12:47:45.503252 Set Vref, RX VrefLevel [Byte0]: 33
2744 12:47:45.506618 [Byte1]: 33
2745 12:47:45.510446
2746 12:47:45.513687 Set Vref, RX VrefLevel [Byte0]: 34
2747 12:47:45.513842 [Byte1]: 34
2748 12:47:45.518900
2749 12:47:45.519070 Set Vref, RX VrefLevel [Byte0]: 35
2750 12:47:45.522038 [Byte1]: 35
2751 12:47:45.526590
2752 12:47:45.526759 Set Vref, RX VrefLevel [Byte0]: 36
2753 12:47:45.529644 [Byte1]: 36
2754 12:47:45.534766
2755 12:47:45.534937 Set Vref, RX VrefLevel [Byte0]: 37
2756 12:47:45.537533 [Byte1]: 37
2757 12:47:45.542169
2758 12:47:45.542375 Set Vref, RX VrefLevel [Byte0]: 38
2759 12:47:45.545568 [Byte1]: 38
2760 12:47:45.550165
2761 12:47:45.550365 Set Vref, RX VrefLevel [Byte0]: 39
2762 12:47:45.553657 [Byte1]: 39
2763 12:47:45.558197
2764 12:47:45.558404 Set Vref, RX VrefLevel [Byte0]: 40
2765 12:47:45.561106 [Byte1]: 40
2766 12:47:45.565809
2767 12:47:45.566008 Set Vref, RX VrefLevel [Byte0]: 41
2768 12:47:45.569057 [Byte1]: 41
2769 12:47:45.573959
2770 12:47:45.574140 Set Vref, RX VrefLevel [Byte0]: 42
2771 12:47:45.577402 [Byte1]: 42
2772 12:47:45.581943
2773 12:47:45.582119 Set Vref, RX VrefLevel [Byte0]: 43
2774 12:47:45.584862 [Byte1]: 43
2775 12:47:45.589546
2776 12:47:45.589724 Set Vref, RX VrefLevel [Byte0]: 44
2777 12:47:45.593126 [Byte1]: 44
2778 12:47:45.597656
2779 12:47:45.597796 Set Vref, RX VrefLevel [Byte0]: 45
2780 12:47:45.600712 [Byte1]: 45
2781 12:47:45.605216
2782 12:47:45.605353 Set Vref, RX VrefLevel [Byte0]: 46
2783 12:47:45.608810 [Byte1]: 46
2784 12:47:45.613077
2785 12:47:45.613193 Set Vref, RX VrefLevel [Byte0]: 47
2786 12:47:45.616445 [Byte1]: 47
2787 12:47:45.621294
2788 12:47:45.621449 Set Vref, RX VrefLevel [Byte0]: 48
2789 12:47:45.624616 [Byte1]: 48
2790 12:47:45.629347
2791 12:47:45.629516 Set Vref, RX VrefLevel [Byte0]: 49
2792 12:47:45.632616 [Byte1]: 49
2793 12:47:45.636749
2794 12:47:45.636910 Set Vref, RX VrefLevel [Byte0]: 50
2795 12:47:45.640502 [Byte1]: 50
2796 12:47:45.644817
2797 12:47:45.644987 Set Vref, RX VrefLevel [Byte0]: 51
2798 12:47:45.648124 [Byte1]: 51
2799 12:47:45.652597
2800 12:47:45.652793 Set Vref, RX VrefLevel [Byte0]: 52
2801 12:47:45.656148 [Byte1]: 52
2802 12:47:45.660834
2803 12:47:45.660999 Set Vref, RX VrefLevel [Byte0]: 53
2804 12:47:45.663616 [Byte1]: 53
2805 12:47:45.668574
2806 12:47:45.668738 Set Vref, RX VrefLevel [Byte0]: 54
2807 12:47:45.671695 [Byte1]: 54
2808 12:47:45.676270
2809 12:47:45.676469 Set Vref, RX VrefLevel [Byte0]: 55
2810 12:47:45.679468 [Byte1]: 55
2811 12:47:45.684210
2812 12:47:45.684375 Set Vref, RX VrefLevel [Byte0]: 56
2813 12:47:45.687649 [Byte1]: 56
2814 12:47:45.692277
2815 12:47:45.692453 Set Vref, RX VrefLevel [Byte0]: 57
2816 12:47:45.695649 [Byte1]: 57
2817 12:47:45.700516
2818 12:47:45.700671 Set Vref, RX VrefLevel [Byte0]: 58
2819 12:47:45.703187 [Byte1]: 58
2820 12:47:45.708137
2821 12:47:45.708293 Set Vref, RX VrefLevel [Byte0]: 59
2822 12:47:45.711393 [Byte1]: 59
2823 12:47:45.715998
2824 12:47:45.716166 Set Vref, RX VrefLevel [Byte0]: 60
2825 12:47:45.719312 [Byte1]: 60
2826 12:47:45.723898
2827 12:47:45.724073 Set Vref, RX VrefLevel [Byte0]: 61
2828 12:47:45.727050 [Byte1]: 61
2829 12:47:45.731925
2830 12:47:45.732090 Set Vref, RX VrefLevel [Byte0]: 62
2831 12:47:45.734631 [Byte1]: 62
2832 12:47:45.739245
2833 12:47:45.739412 Set Vref, RX VrefLevel [Byte0]: 63
2834 12:47:45.742790 [Byte1]: 63
2835 12:47:45.747436
2836 12:47:45.747602 Set Vref, RX VrefLevel [Byte0]: 64
2837 12:47:45.750478 [Byte1]: 64
2838 12:47:45.755396
2839 12:47:45.755579 Set Vref, RX VrefLevel [Byte0]: 65
2840 12:47:45.758831 [Byte1]: 65
2841 12:47:45.762874
2842 12:47:45.763019 Set Vref, RX VrefLevel [Byte0]: 66
2843 12:47:45.766379 [Byte1]: 66
2844 12:47:45.771251
2845 12:47:45.771410 Set Vref, RX VrefLevel [Byte0]: 67
2846 12:47:45.774064 [Byte1]: 67
2847 12:47:45.779168
2848 12:47:45.779330 Set Vref, RX VrefLevel [Byte0]: 68
2849 12:47:45.782366 [Byte1]: 68
2850 12:47:45.787152
2851 12:47:45.787331 Set Vref, RX VrefLevel [Byte0]: 69
2852 12:47:45.790312 [Byte1]: 69
2853 12:47:45.794616
2854 12:47:45.794801 Set Vref, RX VrefLevel [Byte0]: 70
2855 12:47:45.797836 [Byte1]: 70
2856 12:47:45.802567
2857 12:47:45.802741 Final RX Vref Byte 0 = 56 to rank0
2858 12:47:45.806104 Final RX Vref Byte 1 = 49 to rank0
2859 12:47:45.808997 Final RX Vref Byte 0 = 56 to rank1
2860 12:47:45.812607 Final RX Vref Byte 1 = 49 to rank1==
2861 12:47:45.816064 Dram Type= 6, Freq= 0, CH_0, rank 0
2862 12:47:45.822741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2863 12:47:45.822954 ==
2864 12:47:45.823084 DQS Delay:
2865 12:47:45.823202 DQS0 = 0, DQS1 = 0
2866 12:47:45.825642 DQM Delay:
2867 12:47:45.825797 DQM0 = 120, DQM1 = 112
2868 12:47:45.829060 DQ Delay:
2869 12:47:45.833151 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2870 12:47:45.835791 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2871 12:47:45.839205 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2872 12:47:45.842674 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2873 12:47:45.842858
2874 12:47:45.842977
2875 12:47:45.852404 [DQSOSCAuto] RK0, (LSB)MR18= 0x120b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2876 12:47:45.852598 CH0 RK0: MR19=404, MR18=120B
2877 12:47:45.859285 CH0_RK0: MR19=0x404, MR18=0x120B, DQSOSC=403, MR23=63, INC=40, DEC=26
2878 12:47:45.859478
2879 12:47:45.862740 ----->DramcWriteLeveling(PI) begin...
2880 12:47:45.862920 ==
2881 12:47:45.865976 Dram Type= 6, Freq= 0, CH_0, rank 1
2882 12:47:45.869349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2883 12:47:45.872602 ==
2884 12:47:45.872760 Write leveling (Byte 0): 34 => 34
2885 12:47:45.876049 Write leveling (Byte 1): 28 => 28
2886 12:47:45.879307 DramcWriteLeveling(PI) end<-----
2887 12:47:45.879464
2888 12:47:45.879587 ==
2889 12:47:45.882763 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 12:47:45.889334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 12:47:45.889530 ==
2892 12:47:45.889644 [Gating] SW mode calibration
2893 12:47:45.899754 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2894 12:47:45.903078 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2895 12:47:45.905826 0 15 0 | B1->B0 | 3333 3131 | 1 0 | (1 1) (0 0)
2896 12:47:45.912961 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 12:47:45.916089 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 12:47:45.919721 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 12:47:45.926268 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 12:47:45.929274 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 12:47:45.933048 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2902 12:47:45.939813 0 15 28 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (0 1)
2903 12:47:45.943088 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 12:47:45.945947 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 12:47:45.953215 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 12:47:45.956603 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 12:47:45.959313 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 12:47:45.966486 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 12:47:45.972229 1 0 24 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
2910 12:47:45.972677 1 0 28 | B1->B0 | 3232 3737 | 0 0 | (0 0) (0 0)
2911 12:47:45.979823 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2912 12:47:45.983363 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 12:47:45.986224 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 12:47:45.989458 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 12:47:45.996531 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 12:47:45.999710 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 12:47:46.002691 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 12:47:46.009671 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2919 12:47:46.012988 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 12:47:46.016549 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 12:47:46.022823 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 12:47:46.026121 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 12:47:46.029513 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 12:47:46.036195 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 12:47:46.039477 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 12:47:46.043246 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 12:47:46.049725 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 12:47:46.053257 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 12:47:46.056488 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 12:47:46.060159 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 12:47:46.066542 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 12:47:46.070048 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 12:47:46.073261 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 12:47:46.080119 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2935 12:47:46.083308 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2936 12:47:46.086895 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 12:47:46.090039 Total UI for P1: 0, mck2ui 16
2938 12:47:46.093523 best dqsien dly found for B0: ( 1, 3, 30)
2939 12:47:46.096899 Total UI for P1: 0, mck2ui 16
2940 12:47:46.100083 best dqsien dly found for B1: ( 1, 3, 30)
2941 12:47:46.103917 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2942 12:47:46.107062 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2943 12:47:46.107259
2944 12:47:46.110492 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2945 12:47:46.117344 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2946 12:47:46.117544 [Gating] SW calibration Done
2947 12:47:46.117660 ==
2948 12:47:46.120448 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 12:47:46.127038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 12:47:46.127247 ==
2951 12:47:46.127385 RX Vref Scan: 0
2952 12:47:46.127490
2953 12:47:46.130589 RX Vref 0 -> 0, step: 1
2954 12:47:46.130760
2955 12:47:46.133811 RX Delay -40 -> 252, step: 8
2956 12:47:46.136709 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2957 12:47:46.140137 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2958 12:47:46.143540 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2959 12:47:46.150166 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2960 12:47:46.153560 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2961 12:47:46.157275 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2962 12:47:46.160698 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2963 12:47:46.163642 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2964 12:47:46.166919 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2965 12:47:46.173742 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2966 12:47:46.177230 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2967 12:47:46.180531 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2968 12:47:46.183677 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2969 12:47:46.187490 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2970 12:47:46.194046 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2971 12:47:46.197051 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2972 12:47:46.197252 ==
2973 12:47:46.200324 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 12:47:46.203685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 12:47:46.203867 ==
2976 12:47:46.206997 DQS Delay:
2977 12:47:46.207170 DQS0 = 0, DQS1 = 0
2978 12:47:46.207281 DQM Delay:
2979 12:47:46.210793 DQM0 = 121, DQM1 = 112
2980 12:47:46.211024 DQ Delay:
2981 12:47:46.213836 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2982 12:47:46.217400 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2983 12:47:46.220721 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2984 12:47:46.227219 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2985 12:47:46.227419
2986 12:47:46.227536
2987 12:47:46.227627 ==
2988 12:47:46.230478 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 12:47:46.233944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 12:47:46.234101 ==
2991 12:47:46.234223
2992 12:47:46.234325
2993 12:47:46.237238 TX Vref Scan disable
2994 12:47:46.237380 == TX Byte 0 ==
2995 12:47:46.244352 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2996 12:47:46.247029 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2997 12:47:46.247180 == TX Byte 1 ==
2998 12:47:46.253621 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2999 12:47:46.257275 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3000 12:47:46.257440 ==
3001 12:47:46.260879 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 12:47:46.263812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 12:47:46.263916 ==
3004 12:47:46.276848 TX Vref=22, minBit 1, minWin=25, winSum=417
3005 12:47:46.280288 TX Vref=24, minBit 3, minWin=25, winSum=419
3006 12:47:46.283861 TX Vref=26, minBit 1, minWin=26, winSum=424
3007 12:47:46.286700 TX Vref=28, minBit 1, minWin=26, winSum=426
3008 12:47:46.290281 TX Vref=30, minBit 0, minWin=26, winSum=424
3009 12:47:46.293520 TX Vref=32, minBit 5, minWin=25, winSum=422
3010 12:47:46.300487 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 28
3011 12:47:46.300642
3012 12:47:46.303652 Final TX Range 1 Vref 28
3013 12:47:46.303747
3014 12:47:46.303817 ==
3015 12:47:46.307114 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 12:47:46.310550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 12:47:46.310707 ==
3018 12:47:46.310821
3019 12:47:46.313825
3020 12:47:46.313959 TX Vref Scan disable
3021 12:47:46.317123 == TX Byte 0 ==
3022 12:47:46.320479 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3023 12:47:46.323757 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3024 12:47:46.326986 == TX Byte 1 ==
3025 12:47:46.330218 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3026 12:47:46.333688 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3027 12:47:46.333852
3028 12:47:46.336960 [DATLAT]
3029 12:47:46.337104 Freq=1200, CH0 RK1
3030 12:47:46.337218
3031 12:47:46.340571 DATLAT Default: 0xd
3032 12:47:46.340734 0, 0xFFFF, sum = 0
3033 12:47:46.343681 1, 0xFFFF, sum = 0
3034 12:47:46.343821 2, 0xFFFF, sum = 0
3035 12:47:46.346916 3, 0xFFFF, sum = 0
3036 12:47:46.347083 4, 0xFFFF, sum = 0
3037 12:47:46.350321 5, 0xFFFF, sum = 0
3038 12:47:46.350474 6, 0xFFFF, sum = 0
3039 12:47:46.353584 7, 0xFFFF, sum = 0
3040 12:47:46.353723 8, 0xFFFF, sum = 0
3041 12:47:46.357037 9, 0xFFFF, sum = 0
3042 12:47:46.360364 10, 0xFFFF, sum = 0
3043 12:47:46.360524 11, 0xFFFF, sum = 0
3044 12:47:46.363604 12, 0x0, sum = 1
3045 12:47:46.363734 13, 0x0, sum = 2
3046 12:47:46.363843 14, 0x0, sum = 3
3047 12:47:46.367422 15, 0x0, sum = 4
3048 12:47:46.367584 best_step = 13
3049 12:47:46.367692
3050 12:47:46.367792 ==
3051 12:47:46.370157 Dram Type= 6, Freq= 0, CH_0, rank 1
3052 12:47:46.377094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3053 12:47:46.377244 ==
3054 12:47:46.377355 RX Vref Scan: 0
3055 12:47:46.377452
3056 12:47:46.380695 RX Vref 0 -> 0, step: 1
3057 12:47:46.380791
3058 12:47:46.383675 RX Delay -13 -> 252, step: 4
3059 12:47:46.386957 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3060 12:47:46.390469 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3061 12:47:46.396966 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3062 12:47:46.400343 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3063 12:47:46.403462 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3064 12:47:46.406823 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3065 12:47:46.410803 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3066 12:47:46.417023 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3067 12:47:46.420370 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3068 12:47:46.423959 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3069 12:47:46.427079 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3070 12:47:46.430126 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3071 12:47:46.437239 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3072 12:47:46.440230 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3073 12:47:46.443616 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3074 12:47:46.447039 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3075 12:47:46.447146 ==
3076 12:47:46.450279 Dram Type= 6, Freq= 0, CH_0, rank 1
3077 12:47:46.454021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 12:47:46.456952 ==
3079 12:47:46.457063 DQS Delay:
3080 12:47:46.457158 DQS0 = 0, DQS1 = 0
3081 12:47:46.460300 DQM Delay:
3082 12:47:46.460388 DQM0 = 120, DQM1 = 110
3083 12:47:46.463915 DQ Delay:
3084 12:47:46.467348 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3085 12:47:46.470384 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3086 12:47:46.474081 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3087 12:47:46.477239 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3088 12:47:46.477407
3089 12:47:46.477506
3090 12:47:46.484013 [DQSOSCAuto] RK1, (LSB)MR18= 0xded, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3091 12:47:46.487447 CH0 RK1: MR19=403, MR18=DED
3092 12:47:46.493885 CH0_RK1: MR19=0x403, MR18=0xDED, DQSOSC=405, MR23=63, INC=39, DEC=26
3093 12:47:46.497246 [RxdqsGatingPostProcess] freq 1200
3094 12:47:46.503974 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3095 12:47:46.504155 best DQS0 dly(2T, 0.5T) = (0, 11)
3096 12:47:46.506951 best DQS1 dly(2T, 0.5T) = (0, 12)
3097 12:47:46.510687 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3098 12:47:46.513937 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3099 12:47:46.517588 best DQS0 dly(2T, 0.5T) = (0, 11)
3100 12:47:46.520693 best DQS1 dly(2T, 0.5T) = (0, 11)
3101 12:47:46.524007 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3102 12:47:46.527555 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3103 12:47:46.531169 Pre-setting of DQS Precalculation
3104 12:47:46.534196 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3105 12:47:46.537291 ==
3106 12:47:46.537407 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 12:47:46.543929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 12:47:46.544049 ==
3109 12:47:46.547167 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3110 12:47:46.553969 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3111 12:47:46.562953 [CA 0] Center 38 (8~68) winsize 61
3112 12:47:46.566597 [CA 1] Center 37 (7~68) winsize 62
3113 12:47:46.569575 [CA 2] Center 35 (5~65) winsize 61
3114 12:47:46.572733 [CA 3] Center 34 (4~64) winsize 61
3115 12:47:46.576097 [CA 4] Center 34 (4~64) winsize 61
3116 12:47:46.579741 [CA 5] Center 33 (3~63) winsize 61
3117 12:47:46.579888
3118 12:47:46.583341 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3119 12:47:46.583480
3120 12:47:46.586173 [CATrainingPosCal] consider 1 rank data
3121 12:47:46.589517 u2DelayCellTimex100 = 270/100 ps
3122 12:47:46.593246 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3123 12:47:46.596476 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3124 12:47:46.599945 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3125 12:47:46.606181 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3126 12:47:46.609819 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3127 12:47:46.613049 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3128 12:47:46.613180
3129 12:47:46.616787 CA PerBit enable=1, Macro0, CA PI delay=33
3130 12:47:46.616920
3131 12:47:46.620042 [CBTSetCACLKResult] CA Dly = 33
3132 12:47:46.620156 CS Dly: 8 (0~39)
3133 12:47:46.620259 ==
3134 12:47:46.623196 Dram Type= 6, Freq= 0, CH_1, rank 1
3135 12:47:46.630151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 12:47:46.630272 ==
3137 12:47:46.633450 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3138 12:47:46.639638 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3139 12:47:46.648353 [CA 0] Center 37 (7~68) winsize 62
3140 12:47:46.651943 [CA 1] Center 37 (7~68) winsize 62
3141 12:47:46.655185 [CA 2] Center 35 (5~66) winsize 62
3142 12:47:46.658580 [CA 3] Center 34 (4~65) winsize 62
3143 12:47:46.662133 [CA 4] Center 34 (4~65) winsize 62
3144 12:47:46.665564 [CA 5] Center 34 (4~64) winsize 61
3145 12:47:46.665689
3146 12:47:46.668887 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3147 12:47:46.669005
3148 12:47:46.671729 [CATrainingPosCal] consider 2 rank data
3149 12:47:46.675627 u2DelayCellTimex100 = 270/100 ps
3150 12:47:46.678944 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3151 12:47:46.682356 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3152 12:47:46.688528 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3153 12:47:46.692380 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3154 12:47:46.695315 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3155 12:47:46.698639 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3156 12:47:46.698795
3157 12:47:46.702029 CA PerBit enable=1, Macro0, CA PI delay=33
3158 12:47:46.702162
3159 12:47:46.705540 [CBTSetCACLKResult] CA Dly = 33
3160 12:47:46.705654 CS Dly: 9 (0~41)
3161 12:47:46.705755
3162 12:47:46.709321 ----->DramcWriteLeveling(PI) begin...
3163 12:47:46.709449 ==
3164 12:47:46.712345 Dram Type= 6, Freq= 0, CH_1, rank 0
3165 12:47:46.718951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3166 12:47:46.719146 ==
3167 12:47:46.722026 Write leveling (Byte 0): 26 => 26
3168 12:47:46.725436 Write leveling (Byte 1): 28 => 28
3169 12:47:46.725598 DramcWriteLeveling(PI) end<-----
3170 12:47:46.725703
3171 12:47:46.728969 ==
3172 12:47:46.732340 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 12:47:46.735833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 12:47:46.735959 ==
3175 12:47:46.739144 [Gating] SW mode calibration
3176 12:47:46.745462 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3177 12:47:46.748714 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3178 12:47:46.755314 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 12:47:46.759370 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 12:47:46.762285 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 12:47:46.769167 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 12:47:46.772332 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 12:47:46.775858 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 12:47:46.782167 0 15 24 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
3185 12:47:46.785705 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3186 12:47:46.789073 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 12:47:46.795464 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 12:47:46.799047 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 12:47:46.802499 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 12:47:46.806120 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 12:47:46.812577 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 12:47:46.815898 1 0 24 | B1->B0 | 2d2d 3b3b | 0 1 | (1 1) (0 0)
3193 12:47:46.819298 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 12:47:46.825700 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 12:47:46.828890 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 12:47:46.832261 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 12:47:46.839693 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 12:47:46.842492 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 12:47:46.845987 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 12:47:46.852714 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3201 12:47:46.856018 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3202 12:47:46.859103 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 12:47:46.865876 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 12:47:46.869389 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 12:47:46.872817 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 12:47:46.876194 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 12:47:46.882446 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 12:47:46.885877 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 12:47:46.889331 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 12:47:46.896099 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 12:47:46.899597 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 12:47:46.902668 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 12:47:46.909228 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 12:47:46.912726 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 12:47:46.916127 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 12:47:46.922311 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3217 12:47:46.926086 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 12:47:46.929382 Total UI for P1: 0, mck2ui 16
3219 12:47:46.932498 best dqsien dly found for B0: ( 1, 3, 24)
3220 12:47:46.936413 Total UI for P1: 0, mck2ui 16
3221 12:47:46.939196 best dqsien dly found for B1: ( 1, 3, 24)
3222 12:47:46.942625 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3223 12:47:46.945588 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3224 12:47:46.945670
3225 12:47:46.949673 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3226 12:47:46.952879 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3227 12:47:46.955791 [Gating] SW calibration Done
3228 12:47:46.955882 ==
3229 12:47:46.959285 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 12:47:46.962615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 12:47:46.962718 ==
3232 12:47:46.965944 RX Vref Scan: 0
3233 12:47:46.966026
3234 12:47:46.969433 RX Vref 0 -> 0, step: 1
3235 12:47:46.969539
3236 12:47:46.969623 RX Delay -40 -> 252, step: 8
3237 12:47:46.976146 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3238 12:47:46.979540 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3239 12:47:46.982791 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3240 12:47:46.986421 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3241 12:47:46.989733 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3242 12:47:46.996387 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3243 12:47:46.999144 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3244 12:47:47.002710 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3245 12:47:47.006286 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3246 12:47:47.009290 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3247 12:47:47.016151 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3248 12:47:47.019360 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3249 12:47:47.022818 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3250 12:47:47.026191 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3251 12:47:47.029709 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3252 12:47:47.035890 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3253 12:47:47.035996 ==
3254 12:47:47.039373 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 12:47:47.042809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 12:47:47.042894 ==
3257 12:47:47.042990 DQS Delay:
3258 12:47:47.046273 DQS0 = 0, DQS1 = 0
3259 12:47:47.046382 DQM Delay:
3260 12:47:47.049506 DQM0 = 120, DQM1 = 116
3261 12:47:47.049585 DQ Delay:
3262 12:47:47.052814 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3263 12:47:47.055870 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3264 12:47:47.059386 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3265 12:47:47.062948 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3266 12:47:47.063025
3267 12:47:47.063089
3268 12:47:47.066261 ==
3269 12:47:47.066338 Dram Type= 6, Freq= 0, CH_1, rank 0
3270 12:47:47.072997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3271 12:47:47.073087 ==
3272 12:47:47.073161
3273 12:47:47.073241
3274 12:47:47.076142 TX Vref Scan disable
3275 12:47:47.076235 == TX Byte 0 ==
3276 12:47:47.079279 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3277 12:47:47.086420 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3278 12:47:47.086505 == TX Byte 1 ==
3279 12:47:47.089237 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3280 12:47:47.095998 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3281 12:47:47.096081 ==
3282 12:47:47.099358 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 12:47:47.102591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 12:47:47.102711 ==
3285 12:47:47.114514 TX Vref=22, minBit 9, minWin=24, winSum=410
3286 12:47:47.117810 TX Vref=24, minBit 9, minWin=24, winSum=415
3287 12:47:47.121094 TX Vref=26, minBit 8, minWin=25, winSum=418
3288 12:47:47.125107 TX Vref=28, minBit 10, minWin=25, winSum=424
3289 12:47:47.128218 TX Vref=30, minBit 8, minWin=26, winSum=429
3290 12:47:47.131099 TX Vref=32, minBit 8, minWin=26, winSum=426
3291 12:47:47.137885 [TxChooseVref] Worse bit 8, Min win 26, Win sum 429, Final Vref 30
3292 12:47:47.137999
3293 12:47:47.141430 Final TX Range 1 Vref 30
3294 12:47:47.141539
3295 12:47:47.141631 ==
3296 12:47:47.144696 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 12:47:47.148064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 12:47:47.148148 ==
3299 12:47:47.148212
3300 12:47:47.148280
3301 12:47:47.151129 TX Vref Scan disable
3302 12:47:47.154988 == TX Byte 0 ==
3303 12:47:47.158167 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3304 12:47:47.161380 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3305 12:47:47.164867 == TX Byte 1 ==
3306 12:47:47.168188 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3307 12:47:47.171471 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3308 12:47:47.171573
3309 12:47:47.174661 [DATLAT]
3310 12:47:47.174740 Freq=1200, CH1 RK0
3311 12:47:47.174806
3312 12:47:47.178383 DATLAT Default: 0xd
3313 12:47:47.178493 0, 0xFFFF, sum = 0
3314 12:47:47.181707 1, 0xFFFF, sum = 0
3315 12:47:47.181810 2, 0xFFFF, sum = 0
3316 12:47:47.185202 3, 0xFFFF, sum = 0
3317 12:47:47.185294 4, 0xFFFF, sum = 0
3318 12:47:47.188311 5, 0xFFFF, sum = 0
3319 12:47:47.188401 6, 0xFFFF, sum = 0
3320 12:47:47.191213 7, 0xFFFF, sum = 0
3321 12:47:47.191326 8, 0xFFFF, sum = 0
3322 12:47:47.194979 9, 0xFFFF, sum = 0
3323 12:47:47.195099 10, 0xFFFF, sum = 0
3324 12:47:47.198093 11, 0xFFFF, sum = 0
3325 12:47:47.198173 12, 0x0, sum = 1
3326 12:47:47.201825 13, 0x0, sum = 2
3327 12:47:47.201902 14, 0x0, sum = 3
3328 12:47:47.204555 15, 0x0, sum = 4
3329 12:47:47.204640 best_step = 13
3330 12:47:47.204725
3331 12:47:47.204815 ==
3332 12:47:47.208682 Dram Type= 6, Freq= 0, CH_1, rank 0
3333 12:47:47.214550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3334 12:47:47.214661 ==
3335 12:47:47.214757 RX Vref Scan: 1
3336 12:47:47.214857
3337 12:47:47.218123 Set Vref Range= 32 -> 127
3338 12:47:47.218220
3339 12:47:47.221754 RX Vref 32 -> 127, step: 1
3340 12:47:47.221865
3341 12:47:47.221957 RX Delay -5 -> 252, step: 4
3342 12:47:47.224597
3343 12:47:47.228222 Set Vref, RX VrefLevel [Byte0]: 32
3344 12:47:47.231026 [Byte1]: 32
3345 12:47:47.231145
3346 12:47:47.234835 Set Vref, RX VrefLevel [Byte0]: 33
3347 12:47:47.237827 [Byte1]: 33
3348 12:47:47.237975
3349 12:47:47.241173 Set Vref, RX VrefLevel [Byte0]: 34
3350 12:47:47.244549 [Byte1]: 34
3351 12:47:47.248801
3352 12:47:47.248915 Set Vref, RX VrefLevel [Byte0]: 35
3353 12:47:47.251645 [Byte1]: 35
3354 12:47:47.256067
3355 12:47:47.256183 Set Vref, RX VrefLevel [Byte0]: 36
3356 12:47:47.259501 [Byte1]: 36
3357 12:47:47.264377
3358 12:47:47.264495 Set Vref, RX VrefLevel [Byte0]: 37
3359 12:47:47.267294 [Byte1]: 37
3360 12:47:47.271727
3361 12:47:47.271852 Set Vref, RX VrefLevel [Byte0]: 38
3362 12:47:47.274932 [Byte1]: 38
3363 12:47:47.279919
3364 12:47:47.280037 Set Vref, RX VrefLevel [Byte0]: 39
3365 12:47:47.283417 [Byte1]: 39
3366 12:47:47.287435
3367 12:47:47.287640 Set Vref, RX VrefLevel [Byte0]: 40
3368 12:47:47.291006 [Byte1]: 40
3369 12:47:47.295807
3370 12:47:47.295978 Set Vref, RX VrefLevel [Byte0]: 41
3371 12:47:47.298825 [Byte1]: 41
3372 12:47:47.303148
3373 12:47:47.303280 Set Vref, RX VrefLevel [Byte0]: 42
3374 12:47:47.306628 [Byte1]: 42
3375 12:47:47.311182
3376 12:47:47.311301 Set Vref, RX VrefLevel [Byte0]: 43
3377 12:47:47.314573 [Byte1]: 43
3378 12:47:47.319139
3379 12:47:47.319257 Set Vref, RX VrefLevel [Byte0]: 44
3380 12:47:47.322358 [Byte1]: 44
3381 12:47:47.326553
3382 12:47:47.326674 Set Vref, RX VrefLevel [Byte0]: 45
3383 12:47:47.330059 [Byte1]: 45
3384 12:47:47.334700
3385 12:47:47.334820 Set Vref, RX VrefLevel [Byte0]: 46
3386 12:47:47.337698 [Byte1]: 46
3387 12:47:47.342353
3388 12:47:47.342468 Set Vref, RX VrefLevel [Byte0]: 47
3389 12:47:47.345994 [Byte1]: 47
3390 12:47:47.350174
3391 12:47:47.350263 Set Vref, RX VrefLevel [Byte0]: 48
3392 12:47:47.353615 [Byte1]: 48
3393 12:47:47.358180
3394 12:47:47.358295 Set Vref, RX VrefLevel [Byte0]: 49
3395 12:47:47.361589 [Byte1]: 49
3396 12:47:47.365925
3397 12:47:47.366035 Set Vref, RX VrefLevel [Byte0]: 50
3398 12:47:47.369420 [Byte1]: 50
3399 12:47:47.374178
3400 12:47:47.374260 Set Vref, RX VrefLevel [Byte0]: 51
3401 12:47:47.377408 [Byte1]: 51
3402 12:47:47.382470
3403 12:47:47.382584 Set Vref, RX VrefLevel [Byte0]: 52
3404 12:47:47.385123 [Byte1]: 52
3405 12:47:47.389676
3406 12:47:47.389795 Set Vref, RX VrefLevel [Byte0]: 53
3407 12:47:47.393019 [Byte1]: 53
3408 12:47:47.397700
3409 12:47:47.397818 Set Vref, RX VrefLevel [Byte0]: 54
3410 12:47:47.400507 [Byte1]: 54
3411 12:47:47.405599
3412 12:47:47.405713 Set Vref, RX VrefLevel [Byte0]: 55
3413 12:47:47.409093 [Byte1]: 55
3414 12:47:47.413153
3415 12:47:47.413268 Set Vref, RX VrefLevel [Byte0]: 56
3416 12:47:47.416294 [Byte1]: 56
3417 12:47:47.420803
3418 12:47:47.420936 Set Vref, RX VrefLevel [Byte0]: 57
3419 12:47:47.424056 [Byte1]: 57
3420 12:47:47.428709
3421 12:47:47.428841 Set Vref, RX VrefLevel [Byte0]: 58
3422 12:47:47.432059 [Byte1]: 58
3423 12:47:47.436636
3424 12:47:47.436758 Set Vref, RX VrefLevel [Byte0]: 59
3425 12:47:47.440104 [Byte1]: 59
3426 12:47:47.444731
3427 12:47:47.444853 Set Vref, RX VrefLevel [Byte0]: 60
3428 12:47:47.448218 [Byte1]: 60
3429 12:47:47.452527
3430 12:47:47.452631 Set Vref, RX VrefLevel [Byte0]: 61
3431 12:47:47.455977 [Byte1]: 61
3432 12:47:47.460335
3433 12:47:47.460420 Set Vref, RX VrefLevel [Byte0]: 62
3434 12:47:47.463661 [Byte1]: 62
3435 12:47:47.468212
3436 12:47:47.468338 Set Vref, RX VrefLevel [Byte0]: 63
3437 12:47:47.471514 [Byte1]: 63
3438 12:47:47.476043
3439 12:47:47.476172 Set Vref, RX VrefLevel [Byte0]: 64
3440 12:47:47.479460 [Byte1]: 64
3441 12:47:47.483765
3442 12:47:47.483887 Set Vref, RX VrefLevel [Byte0]: 65
3443 12:47:47.487007 [Byte1]: 65
3444 12:47:47.491866
3445 12:47:47.491957 Set Vref, RX VrefLevel [Byte0]: 66
3446 12:47:47.494958 [Byte1]: 66
3447 12:47:47.499488
3448 12:47:47.499585 Set Vref, RX VrefLevel [Byte0]: 67
3449 12:47:47.502931 [Byte1]: 67
3450 12:47:47.507441
3451 12:47:47.507548 Set Vref, RX VrefLevel [Byte0]: 68
3452 12:47:47.511155 [Byte1]: 68
3453 12:47:47.515033
3454 12:47:47.515109 Set Vref, RX VrefLevel [Byte0]: 69
3455 12:47:47.518441 [Byte1]: 69
3456 12:47:47.523171
3457 12:47:47.523275 Set Vref, RX VrefLevel [Byte0]: 70
3458 12:47:47.526298 [Byte1]: 70
3459 12:47:47.531097
3460 12:47:47.531204 Final RX Vref Byte 0 = 51 to rank0
3461 12:47:47.534127 Final RX Vref Byte 1 = 48 to rank0
3462 12:47:47.537569 Final RX Vref Byte 0 = 51 to rank1
3463 12:47:47.541189 Final RX Vref Byte 1 = 48 to rank1==
3464 12:47:47.544233 Dram Type= 6, Freq= 0, CH_1, rank 0
3465 12:47:47.547622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3466 12:47:47.551133 ==
3467 12:47:47.551239 DQS Delay:
3468 12:47:47.551331 DQS0 = 0, DQS1 = 0
3469 12:47:47.553973 DQM Delay:
3470 12:47:47.554046 DQM0 = 119, DQM1 = 116
3471 12:47:47.557242 DQ Delay:
3472 12:47:47.560977 DQ0 =122, DQ1 =114, DQ2 =110, DQ3 =116
3473 12:47:47.564059 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3474 12:47:47.567813 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3475 12:47:47.570935 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3476 12:47:47.571014
3477 12:47:47.571079
3478 12:47:47.577486 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3479 12:47:47.580842 CH1 RK0: MR19=404, MR18=114
3480 12:47:47.587599 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3481 12:47:47.587684
3482 12:47:47.591176 ----->DramcWriteLeveling(PI) begin...
3483 12:47:47.591279 ==
3484 12:47:47.594268 Dram Type= 6, Freq= 0, CH_1, rank 1
3485 12:47:47.597976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3486 12:47:47.598081 ==
3487 12:47:47.601238 Write leveling (Byte 0): 24 => 24
3488 12:47:47.604550 Write leveling (Byte 1): 29 => 29
3489 12:47:47.607870 DramcWriteLeveling(PI) end<-----
3490 12:47:47.607950
3491 12:47:47.608015 ==
3492 12:47:47.611380 Dram Type= 6, Freq= 0, CH_1, rank 1
3493 12:47:47.614804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 12:47:47.618176 ==
3495 12:47:47.618277 [Gating] SW mode calibration
3496 12:47:47.624622 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3497 12:47:47.631282 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3498 12:47:47.634714 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 12:47:47.641390 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 12:47:47.644603 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 12:47:47.648100 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 12:47:47.654805 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 12:47:47.658219 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3504 12:47:47.661614 0 15 24 | B1->B0 | 2929 3131 | 1 1 | (1 0) (1 1)
3505 12:47:47.668235 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3506 12:47:47.671219 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 12:47:47.674551 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 12:47:47.677795 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 12:47:47.684624 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 12:47:47.687831 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 12:47:47.691269 1 0 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3512 12:47:47.697898 1 0 24 | B1->B0 | 3f3f 3131 | 0 1 | (0 0) (1 1)
3513 12:47:47.701144 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 12:47:47.704558 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 12:47:47.711465 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 12:47:47.714568 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 12:47:47.717812 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 12:47:47.724559 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 12:47:47.727975 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3520 12:47:47.730998 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3521 12:47:47.738008 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3522 12:47:47.741575 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 12:47:47.744217 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 12:47:47.750972 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 12:47:47.754596 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 12:47:47.758122 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 12:47:47.764345 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 12:47:47.767800 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 12:47:47.771264 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 12:47:47.777749 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 12:47:47.781198 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 12:47:47.784246 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 12:47:47.791085 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 12:47:47.794506 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 12:47:47.797835 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 12:47:47.801141 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3537 12:47:47.807629 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3538 12:47:47.811070 Total UI for P1: 0, mck2ui 16
3539 12:47:47.814593 best dqsien dly found for B1: ( 1, 3, 24)
3540 12:47:47.817687 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 12:47:47.821093 Total UI for P1: 0, mck2ui 16
3542 12:47:47.824506 best dqsien dly found for B0: ( 1, 3, 28)
3543 12:47:47.827903 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3544 12:47:47.831111 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3545 12:47:47.831232
3546 12:47:47.834525 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3547 12:47:47.837947 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3548 12:47:47.840882 [Gating] SW calibration Done
3549 12:47:47.841000 ==
3550 12:47:47.844290 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 12:47:47.847833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 12:47:47.851027 ==
3553 12:47:47.851142 RX Vref Scan: 0
3554 12:47:47.851247
3555 12:47:47.854171 RX Vref 0 -> 0, step: 1
3556 12:47:47.854284
3557 12:47:47.857437 RX Delay -40 -> 252, step: 8
3558 12:47:47.860745 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3559 12:47:47.864313 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3560 12:47:47.867363 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3561 12:47:47.870835 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3562 12:47:47.877490 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3563 12:47:47.880737 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3564 12:47:47.884183 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3565 12:47:47.887267 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3566 12:47:47.890446 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3567 12:47:47.897502 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3568 12:47:47.900602 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3569 12:47:47.904067 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3570 12:47:47.907181 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3571 12:47:47.913636 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3572 12:47:47.916658 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3573 12:47:47.920228 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3574 12:47:47.920337 ==
3575 12:47:47.923850 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 12:47:47.926974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 12:47:47.927085 ==
3578 12:47:47.930239 DQS Delay:
3579 12:47:47.930343 DQS0 = 0, DQS1 = 0
3580 12:47:47.933614 DQM Delay:
3581 12:47:47.933718 DQM0 = 120, DQM1 = 118
3582 12:47:47.936888 DQ Delay:
3583 12:47:47.940331 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3584 12:47:47.943620 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3585 12:47:47.946583 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3586 12:47:47.950294 DQ12 =127, DQ13 =123, DQ14 =123, DQ15 =123
3587 12:47:47.950397
3588 12:47:47.950490
3589 12:47:47.950582 ==
3590 12:47:47.953219 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 12:47:47.956611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 12:47:47.956715 ==
3593 12:47:47.956813
3594 12:47:47.956902
3595 12:47:47.960276 TX Vref Scan disable
3596 12:47:47.963704 == TX Byte 0 ==
3597 12:47:47.966603 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3598 12:47:47.969877 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3599 12:47:47.973492 == TX Byte 1 ==
3600 12:47:47.976514 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3601 12:47:47.979951 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3602 12:47:47.980091 ==
3603 12:47:47.983249 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 12:47:47.986608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 12:47:47.989958 ==
3606 12:47:48.000242 TX Vref=22, minBit 10, minWin=24, winSum=412
3607 12:47:48.003893 TX Vref=24, minBit 9, minWin=25, winSum=423
3608 12:47:48.007109 TX Vref=26, minBit 4, minWin=26, winSum=428
3609 12:47:48.010560 TX Vref=28, minBit 8, minWin=26, winSum=429
3610 12:47:48.013491 TX Vref=30, minBit 9, minWin=26, winSum=431
3611 12:47:48.020140 TX Vref=32, minBit 9, minWin=26, winSum=432
3612 12:47:48.023382 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 32
3613 12:47:48.023505
3614 12:47:48.027068 Final TX Range 1 Vref 32
3615 12:47:48.027192
3616 12:47:48.027291 ==
3617 12:47:48.030061 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 12:47:48.033428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 12:47:48.033538 ==
3620 12:47:48.036696
3621 12:47:48.036803
3622 12:47:48.036895 TX Vref Scan disable
3623 12:47:48.040090 == TX Byte 0 ==
3624 12:47:48.043559 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3625 12:47:48.046750 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3626 12:47:48.050253 == TX Byte 1 ==
3627 12:47:48.053221 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3628 12:47:48.060143 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3629 12:47:48.060255
3630 12:47:48.060360 [DATLAT]
3631 12:47:48.060452 Freq=1200, CH1 RK1
3632 12:47:48.060542
3633 12:47:48.063958 DATLAT Default: 0xd
3634 12:47:48.064057 0, 0xFFFF, sum = 0
3635 12:47:48.066496 1, 0xFFFF, sum = 0
3636 12:47:48.070091 2, 0xFFFF, sum = 0
3637 12:47:48.070198 3, 0xFFFF, sum = 0
3638 12:47:48.073693 4, 0xFFFF, sum = 0
3639 12:47:48.073793 5, 0xFFFF, sum = 0
3640 12:47:48.076403 6, 0xFFFF, sum = 0
3641 12:47:48.076512 7, 0xFFFF, sum = 0
3642 12:47:48.079807 8, 0xFFFF, sum = 0
3643 12:47:48.079916 9, 0xFFFF, sum = 0
3644 12:47:48.083070 10, 0xFFFF, sum = 0
3645 12:47:48.083181 11, 0xFFFF, sum = 0
3646 12:47:48.086544 12, 0x0, sum = 1
3647 12:47:48.086654 13, 0x0, sum = 2
3648 12:47:48.089985 14, 0x0, sum = 3
3649 12:47:48.090060 15, 0x0, sum = 4
3650 12:47:48.093233 best_step = 13
3651 12:47:48.093337
3652 12:47:48.093444 ==
3653 12:47:48.096389 Dram Type= 6, Freq= 0, CH_1, rank 1
3654 12:47:48.099817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3655 12:47:48.099919 ==
3656 12:47:48.100022 RX Vref Scan: 0
3657 12:47:48.100114
3658 12:47:48.103253 RX Vref 0 -> 0, step: 1
3659 12:47:48.103355
3660 12:47:48.106182 RX Delay -5 -> 252, step: 4
3661 12:47:48.109850 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3662 12:47:48.116850 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3663 12:47:48.119503 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3664 12:47:48.122871 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3665 12:47:48.126293 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3666 12:47:48.129789 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3667 12:47:48.136135 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3668 12:47:48.139617 iDelay=195, Bit 7, Center 118 (55 ~ 182) 128
3669 12:47:48.143146 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3670 12:47:48.146590 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3671 12:47:48.149686 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3672 12:47:48.156307 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3673 12:47:48.159879 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3674 12:47:48.163173 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3675 12:47:48.166082 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3676 12:47:48.169514 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3677 12:47:48.173022 ==
3678 12:47:48.176042 Dram Type= 6, Freq= 0, CH_1, rank 1
3679 12:47:48.179345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3680 12:47:48.179470 ==
3681 12:47:48.179588 DQS Delay:
3682 12:47:48.182991 DQS0 = 0, DQS1 = 0
3683 12:47:48.183109 DQM Delay:
3684 12:47:48.186231 DQM0 = 120, DQM1 = 116
3685 12:47:48.186352 DQ Delay:
3686 12:47:48.189784 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3687 12:47:48.193230 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =118
3688 12:47:48.196447 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3689 12:47:48.199795 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3690 12:47:48.199915
3691 12:47:48.200026
3692 12:47:48.209667 [DQSOSCAuto] RK1, (LSB)MR18= 0x13f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3693 12:47:48.212976 CH1 RK1: MR19=403, MR18=13F0
3694 12:47:48.216234 CH1_RK1: MR19=0x403, MR18=0x13F0, DQSOSC=402, MR23=63, INC=40, DEC=27
3695 12:47:48.219586 [RxdqsGatingPostProcess] freq 1200
3696 12:47:48.226407 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3697 12:47:48.229606 best DQS0 dly(2T, 0.5T) = (0, 11)
3698 12:47:48.232556 best DQS1 dly(2T, 0.5T) = (0, 11)
3699 12:47:48.236117 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3700 12:47:48.239301 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3701 12:47:48.242701 best DQS0 dly(2T, 0.5T) = (0, 11)
3702 12:47:48.246020 best DQS1 dly(2T, 0.5T) = (0, 11)
3703 12:47:48.249790 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3704 12:47:48.252839 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3705 12:47:48.252960 Pre-setting of DQS Precalculation
3706 12:47:48.259438 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3707 12:47:48.266351 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3708 12:47:48.272557 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3709 12:47:48.272682
3710 12:47:48.272793
3711 12:47:48.275938 [Calibration Summary] 2400 Mbps
3712 12:47:48.279577 CH 0, Rank 0
3713 12:47:48.279697 SW Impedance : PASS
3714 12:47:48.282505 DUTY Scan : NO K
3715 12:47:48.286036 ZQ Calibration : PASS
3716 12:47:48.286158 Jitter Meter : NO K
3717 12:47:48.289289 CBT Training : PASS
3718 12:47:48.292748 Write leveling : PASS
3719 12:47:48.292855 RX DQS gating : PASS
3720 12:47:48.296098 RX DQ/DQS(RDDQC) : PASS
3721 12:47:48.299465 TX DQ/DQS : PASS
3722 12:47:48.299587 RX DATLAT : PASS
3723 12:47:48.302511 RX DQ/DQS(Engine): PASS
3724 12:47:48.302616 TX OE : NO K
3725 12:47:48.306025 All Pass.
3726 12:47:48.306129
3727 12:47:48.306229 CH 0, Rank 1
3728 12:47:48.309321 SW Impedance : PASS
3729 12:47:48.309445 DUTY Scan : NO K
3730 12:47:48.312529 ZQ Calibration : PASS
3731 12:47:48.316058 Jitter Meter : NO K
3732 12:47:48.316180 CBT Training : PASS
3733 12:47:48.318850 Write leveling : PASS
3734 12:47:48.322278 RX DQS gating : PASS
3735 12:47:48.322399 RX DQ/DQS(RDDQC) : PASS
3736 12:47:48.325820 TX DQ/DQS : PASS
3737 12:47:48.329082 RX DATLAT : PASS
3738 12:47:48.329207 RX DQ/DQS(Engine): PASS
3739 12:47:48.332392 TX OE : NO K
3740 12:47:48.332513 All Pass.
3741 12:47:48.332622
3742 12:47:48.335876 CH 1, Rank 0
3743 12:47:48.335996 SW Impedance : PASS
3744 12:47:48.339386 DUTY Scan : NO K
3745 12:47:48.342571 ZQ Calibration : PASS
3746 12:47:48.342689 Jitter Meter : NO K
3747 12:47:48.345960 CBT Training : PASS
3748 12:47:48.348815 Write leveling : PASS
3749 12:47:48.348934 RX DQS gating : PASS
3750 12:47:48.352533 RX DQ/DQS(RDDQC) : PASS
3751 12:47:48.352654 TX DQ/DQS : PASS
3752 12:47:48.355797 RX DATLAT : PASS
3753 12:47:48.359118 RX DQ/DQS(Engine): PASS
3754 12:47:48.359238 TX OE : NO K
3755 12:47:48.362568 All Pass.
3756 12:47:48.362690
3757 12:47:48.362799 CH 1, Rank 1
3758 12:47:48.365876 SW Impedance : PASS
3759 12:47:48.365996 DUTY Scan : NO K
3760 12:47:48.369213 ZQ Calibration : PASS
3761 12:47:48.372093 Jitter Meter : NO K
3762 12:47:48.372215 CBT Training : PASS
3763 12:47:48.375321 Write leveling : PASS
3764 12:47:48.378699 RX DQS gating : PASS
3765 12:47:48.378820 RX DQ/DQS(RDDQC) : PASS
3766 12:47:48.382120 TX DQ/DQS : PASS
3767 12:47:48.385415 RX DATLAT : PASS
3768 12:47:48.385535 RX DQ/DQS(Engine): PASS
3769 12:47:48.388948 TX OE : NO K
3770 12:47:48.389070 All Pass.
3771 12:47:48.389176
3772 12:47:48.392357 DramC Write-DBI off
3773 12:47:48.395248 PER_BANK_REFRESH: Hybrid Mode
3774 12:47:48.395368 TX_TRACKING: ON
3775 12:47:48.405364 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3776 12:47:48.408795 [FAST_K] Save calibration result to emmc
3777 12:47:48.412133 dramc_set_vcore_voltage set vcore to 650000
3778 12:47:48.415631 Read voltage for 600, 5
3779 12:47:48.415752 Vio18 = 0
3780 12:47:48.415862 Vcore = 650000
3781 12:47:48.418584 Vdram = 0
3782 12:47:48.418702 Vddq = 0
3783 12:47:48.418813 Vmddr = 0
3784 12:47:48.425371 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3785 12:47:48.429028 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3786 12:47:48.432161 MEM_TYPE=3, freq_sel=19
3787 12:47:48.435448 sv_algorithm_assistance_LP4_1600
3788 12:47:48.438906 ============ PULL DRAM RESETB DOWN ============
3789 12:47:48.442459 ========== PULL DRAM RESETB DOWN end =========
3790 12:47:48.449007 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3791 12:47:48.451872 ===================================
3792 12:47:48.451993 LPDDR4 DRAM CONFIGURATION
3793 12:47:48.455257 ===================================
3794 12:47:48.459054 EX_ROW_EN[0] = 0x0
3795 12:47:48.462194 EX_ROW_EN[1] = 0x0
3796 12:47:48.462315 LP4Y_EN = 0x0
3797 12:47:48.465386 WORK_FSP = 0x0
3798 12:47:48.465500 WL = 0x2
3799 12:47:48.468794 RL = 0x2
3800 12:47:48.468880 BL = 0x2
3801 12:47:48.472198 RPST = 0x0
3802 12:47:48.472299 RD_PRE = 0x0
3803 12:47:48.475720 WR_PRE = 0x1
3804 12:47:48.475823 WR_PST = 0x0
3805 12:47:48.478694 DBI_WR = 0x0
3806 12:47:48.478798 DBI_RD = 0x0
3807 12:47:48.481807 OTF = 0x1
3808 12:47:48.485801 ===================================
3809 12:47:48.489024 ===================================
3810 12:47:48.489132 ANA top config
3811 12:47:48.491887 ===================================
3812 12:47:48.495567 DLL_ASYNC_EN = 0
3813 12:47:48.498845 ALL_SLAVE_EN = 1
3814 12:47:48.498952 NEW_RANK_MODE = 1
3815 12:47:48.502237 DLL_IDLE_MODE = 1
3816 12:47:48.505795 LP45_APHY_COMB_EN = 1
3817 12:47:48.508785 TX_ODT_DIS = 1
3818 12:47:48.508890 NEW_8X_MODE = 1
3819 12:47:48.512428 ===================================
3820 12:47:48.515694 ===================================
3821 12:47:48.518788 data_rate = 1200
3822 12:47:48.522206 CKR = 1
3823 12:47:48.525710 DQ_P2S_RATIO = 8
3824 12:47:48.529019 ===================================
3825 12:47:48.532137 CA_P2S_RATIO = 8
3826 12:47:48.535608 DQ_CA_OPEN = 0
3827 12:47:48.535693 DQ_SEMI_OPEN = 0
3828 12:47:48.538839 CA_SEMI_OPEN = 0
3829 12:47:48.542194 CA_FULL_RATE = 0
3830 12:47:48.545695 DQ_CKDIV4_EN = 1
3831 12:47:48.549380 CA_CKDIV4_EN = 1
3832 12:47:48.552184 CA_PREDIV_EN = 0
3833 12:47:48.552260 PH8_DLY = 0
3834 12:47:48.555409 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3835 12:47:48.558804 DQ_AAMCK_DIV = 4
3836 12:47:48.562220 CA_AAMCK_DIV = 4
3837 12:47:48.565643 CA_ADMCK_DIV = 4
3838 12:47:48.568888 DQ_TRACK_CA_EN = 0
3839 12:47:48.572127 CA_PICK = 600
3840 12:47:48.572207 CA_MCKIO = 600
3841 12:47:48.575281 MCKIO_SEMI = 0
3842 12:47:48.578994 PLL_FREQ = 2288
3843 12:47:48.582224 DQ_UI_PI_RATIO = 32
3844 12:47:48.585361 CA_UI_PI_RATIO = 0
3845 12:47:48.588448 ===================================
3846 12:47:48.591818 ===================================
3847 12:47:48.595198 memory_type:LPDDR4
3848 12:47:48.595301 GP_NUM : 10
3849 12:47:48.598432 SRAM_EN : 1
3850 12:47:48.598536 MD32_EN : 0
3851 12:47:48.601981 ===================================
3852 12:47:48.605415 [ANA_INIT] >>>>>>>>>>>>>>
3853 12:47:48.608886 <<<<<< [CONFIGURE PHASE]: ANA_TX
3854 12:47:48.612248 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3855 12:47:48.615357 ===================================
3856 12:47:48.618633 data_rate = 1200,PCW = 0X5800
3857 12:47:48.621943 ===================================
3858 12:47:48.625575 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3859 12:47:48.628410 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3860 12:47:48.635190 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3861 12:47:48.641629 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3862 12:47:48.645087 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3863 12:47:48.648518 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3864 12:47:48.648628 [ANA_INIT] flow start
3865 12:47:48.651903 [ANA_INIT] PLL >>>>>>>>
3866 12:47:48.654864 [ANA_INIT] PLL <<<<<<<<
3867 12:47:48.654969 [ANA_INIT] MIDPI >>>>>>>>
3868 12:47:48.658094 [ANA_INIT] MIDPI <<<<<<<<
3869 12:47:48.661505 [ANA_INIT] DLL >>>>>>>>
3870 12:47:48.661590 [ANA_INIT] flow end
3871 12:47:48.668187 ============ LP4 DIFF to SE enter ============
3872 12:47:48.671769 ============ LP4 DIFF to SE exit ============
3873 12:47:48.671875 [ANA_INIT] <<<<<<<<<<<<<
3874 12:47:48.674733 [Flow] Enable top DCM control >>>>>
3875 12:47:48.678017 [Flow] Enable top DCM control <<<<<
3876 12:47:48.681506 Enable DLL master slave shuffle
3877 12:47:48.688030 ==============================================================
3878 12:47:48.691542 Gating Mode config
3879 12:47:48.694804 ==============================================================
3880 12:47:48.698269 Config description:
3881 12:47:48.708471 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3882 12:47:48.714613 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3883 12:47:48.717976 SELPH_MODE 0: By rank 1: By Phase
3884 12:47:48.724819 ==============================================================
3885 12:47:48.727843 GAT_TRACK_EN = 1
3886 12:47:48.731137 RX_GATING_MODE = 2
3887 12:47:48.734562 RX_GATING_TRACK_MODE = 2
3888 12:47:48.738200 SELPH_MODE = 1
3889 12:47:48.738337 PICG_EARLY_EN = 1
3890 12:47:48.740940 VALID_LAT_VALUE = 1
3891 12:47:48.747682 ==============================================================
3892 12:47:48.751216 Enter into Gating configuration >>>>
3893 12:47:48.754331 Exit from Gating configuration <<<<
3894 12:47:48.757434 Enter into DVFS_PRE_config >>>>>
3895 12:47:48.767641 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3896 12:47:48.770887 Exit from DVFS_PRE_config <<<<<
3897 12:47:48.774267 Enter into PICG configuration >>>>
3898 12:47:48.777771 Exit from PICG configuration <<<<
3899 12:47:48.780915 [RX_INPUT] configuration >>>>>
3900 12:47:48.784061 [RX_INPUT] configuration <<<<<
3901 12:47:48.787407 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3902 12:47:48.794419 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3903 12:47:48.800604 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3904 12:47:48.807535 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3905 12:47:48.814079 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3906 12:47:48.817533 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3907 12:47:48.824208 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3908 12:47:48.827410 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3909 12:47:48.830564 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3910 12:47:48.833944 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3911 12:47:48.840708 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3912 12:47:48.844414 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3913 12:47:48.847568 ===================================
3914 12:47:48.851032 LPDDR4 DRAM CONFIGURATION
3915 12:47:48.853860 ===================================
3916 12:47:48.853988 EX_ROW_EN[0] = 0x0
3917 12:47:48.857329 EX_ROW_EN[1] = 0x0
3918 12:47:48.857455 LP4Y_EN = 0x0
3919 12:47:48.860819 WORK_FSP = 0x0
3920 12:47:48.860939 WL = 0x2
3921 12:47:48.863804 RL = 0x2
3922 12:47:48.863929 BL = 0x2
3923 12:47:48.867298 RPST = 0x0
3924 12:47:48.867417 RD_PRE = 0x0
3925 12:47:48.870370 WR_PRE = 0x1
3926 12:47:48.870494 WR_PST = 0x0
3927 12:47:48.873937 DBI_WR = 0x0
3928 12:47:48.874059 DBI_RD = 0x0
3929 12:47:48.877186 OTF = 0x1
3930 12:47:48.880720 ===================================
3931 12:47:48.883837 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3932 12:47:48.887463 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3933 12:47:48.893949 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3934 12:47:48.897685 ===================================
3935 12:47:48.897816 LPDDR4 DRAM CONFIGURATION
3936 12:47:48.900538 ===================================
3937 12:47:48.904297 EX_ROW_EN[0] = 0x10
3938 12:47:48.907869 EX_ROW_EN[1] = 0x0
3939 12:47:48.907998 LP4Y_EN = 0x0
3940 12:47:48.910527 WORK_FSP = 0x0
3941 12:47:48.910651 WL = 0x2
3942 12:47:48.914004 RL = 0x2
3943 12:47:48.914137 BL = 0x2
3944 12:47:48.917140 RPST = 0x0
3945 12:47:48.917264 RD_PRE = 0x0
3946 12:47:48.920526 WR_PRE = 0x1
3947 12:47:48.920647 WR_PST = 0x0
3948 12:47:48.924004 DBI_WR = 0x0
3949 12:47:48.924124 DBI_RD = 0x0
3950 12:47:48.927423 OTF = 0x1
3951 12:47:48.931115 ===================================
3952 12:47:48.937430 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3953 12:47:48.940802 nWR fixed to 30
3954 12:47:48.940926 [ModeRegInit_LP4] CH0 RK0
3955 12:47:48.943978 [ModeRegInit_LP4] CH0 RK1
3956 12:47:48.947168 [ModeRegInit_LP4] CH1 RK0
3957 12:47:48.950656 [ModeRegInit_LP4] CH1 RK1
3958 12:47:48.950779 match AC timing 17
3959 12:47:48.957619 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3960 12:47:48.960288 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3961 12:47:48.963907 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3962 12:47:48.970601 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3963 12:47:48.973588 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3964 12:47:48.973709 ==
3965 12:47:48.977031 Dram Type= 6, Freq= 0, CH_0, rank 0
3966 12:47:48.980615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3967 12:47:48.980738 ==
3968 12:47:48.987275 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3969 12:47:48.993494 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3970 12:47:48.997260 [CA 0] Center 36 (5~67) winsize 63
3971 12:47:49.000357 [CA 1] Center 36 (5~67) winsize 63
3972 12:47:49.003997 [CA 2] Center 34 (3~65) winsize 63
3973 12:47:49.007068 [CA 3] Center 33 (3~64) winsize 62
3974 12:47:49.010411 [CA 4] Center 33 (2~64) winsize 63
3975 12:47:49.013596 [CA 5] Center 32 (2~63) winsize 62
3976 12:47:49.013720
3977 12:47:49.016996 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3978 12:47:49.017130
3979 12:47:49.020435 [CATrainingPosCal] consider 1 rank data
3980 12:47:49.023493 u2DelayCellTimex100 = 270/100 ps
3981 12:47:49.026967 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3982 12:47:49.030391 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3983 12:47:49.033359 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3984 12:47:49.036854 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3985 12:47:49.040080 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3986 12:47:49.043642 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3987 12:47:49.043762
3988 12:47:49.050241 CA PerBit enable=1, Macro0, CA PI delay=32
3989 12:47:49.050368
3990 12:47:49.050481 [CBTSetCACLKResult] CA Dly = 32
3991 12:47:49.053357 CS Dly: 4 (0~35)
3992 12:47:49.053481 ==
3993 12:47:49.056634 Dram Type= 6, Freq= 0, CH_0, rank 1
3994 12:47:49.059965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3995 12:47:49.060090 ==
3996 12:47:49.066819 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3997 12:47:49.073200 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3998 12:47:49.076794 [CA 0] Center 35 (5~66) winsize 62
3999 12:47:49.080027 [CA 1] Center 35 (5~66) winsize 62
4000 12:47:49.083604 [CA 2] Center 34 (3~65) winsize 63
4001 12:47:49.086761 [CA 3] Center 33 (3~64) winsize 62
4002 12:47:49.090133 [CA 4] Center 33 (2~64) winsize 63
4003 12:47:49.093217 [CA 5] Center 32 (2~63) winsize 62
4004 12:47:49.093340
4005 12:47:49.096560 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4006 12:47:49.096696
4007 12:47:49.099907 [CATrainingPosCal] consider 2 rank data
4008 12:47:49.103443 u2DelayCellTimex100 = 270/100 ps
4009 12:47:49.106502 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4010 12:47:49.110038 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4011 12:47:49.113423 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
4012 12:47:49.116680 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4013 12:47:49.120232 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4014 12:47:49.126458 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4015 12:47:49.126591
4016 12:47:49.129953 CA PerBit enable=1, Macro0, CA PI delay=32
4017 12:47:49.130080
4018 12:47:49.133082 [CBTSetCACLKResult] CA Dly = 32
4019 12:47:49.133204 CS Dly: 4 (0~36)
4020 12:47:49.133324
4021 12:47:49.136477 ----->DramcWriteLeveling(PI) begin...
4022 12:47:49.136598 ==
4023 12:47:49.139377 Dram Type= 6, Freq= 0, CH_0, rank 0
4024 12:47:49.146198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4025 12:47:49.146337 ==
4026 12:47:49.149792 Write leveling (Byte 0): 33 => 33
4027 12:47:49.149920 Write leveling (Byte 1): 33 => 33
4028 12:47:49.152690 DramcWriteLeveling(PI) end<-----
4029 12:47:49.152810
4030 12:47:49.156376 ==
4031 12:47:49.156509 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 12:47:49.162823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 12:47:49.162947 ==
4034 12:47:49.166215 [Gating] SW mode calibration
4035 12:47:49.172638 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4036 12:47:49.176387 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4037 12:47:49.182593 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 12:47:49.186021 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4039 12:47:49.189618 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4040 12:47:49.195904 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
4041 12:47:49.199245 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
4042 12:47:49.202546 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 12:47:49.209336 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 12:47:49.212641 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 12:47:49.215937 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 12:47:49.219317 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 12:47:49.226001 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 12:47:49.229253 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
4049 12:47:49.232375 0 10 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
4050 12:47:49.239179 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 12:47:49.242564 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 12:47:49.245869 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 12:47:49.252767 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 12:47:49.255808 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 12:47:49.259276 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 12:47:49.265732 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4057 12:47:49.269707 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4058 12:47:49.272718 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 12:47:49.279071 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 12:47:49.282752 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 12:47:49.285611 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 12:47:49.292437 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 12:47:49.296139 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 12:47:49.298832 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 12:47:49.305682 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 12:47:49.309024 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 12:47:49.312410 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 12:47:49.319205 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 12:47:49.322525 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 12:47:49.325899 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 12:47:49.332410 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 12:47:49.335868 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4073 12:47:49.339071 Total UI for P1: 0, mck2ui 16
4074 12:47:49.342048 best dqsien dly found for B0: ( 0, 13, 10)
4075 12:47:49.345533 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 12:47:49.348780 Total UI for P1: 0, mck2ui 16
4077 12:47:49.352125 best dqsien dly found for B1: ( 0, 13, 12)
4078 12:47:49.355445 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4079 12:47:49.358829 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4080 12:47:49.358918
4081 12:47:49.361994 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4082 12:47:49.368847 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4083 12:47:49.368931 [Gating] SW calibration Done
4084 12:47:49.369022 ==
4085 12:47:49.372202 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 12:47:49.378538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 12:47:49.378636 ==
4088 12:47:49.378721 RX Vref Scan: 0
4089 12:47:49.378805
4090 12:47:49.381974 RX Vref 0 -> 0, step: 1
4091 12:47:49.382056
4092 12:47:49.385409 RX Delay -230 -> 252, step: 16
4093 12:47:49.388666 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4094 12:47:49.392091 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4095 12:47:49.398990 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4096 12:47:49.401970 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4097 12:47:49.405339 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4098 12:47:49.408674 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4099 12:47:49.412033 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4100 12:47:49.418958 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4101 12:47:49.422339 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4102 12:47:49.425650 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4103 12:47:49.428874 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4104 12:47:49.432445 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4105 12:47:49.438662 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4106 12:47:49.442419 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4107 12:47:49.445588 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4108 12:47:49.449099 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4109 12:47:49.451966 ==
4110 12:47:49.452093 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 12:47:49.458822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 12:47:49.458945 ==
4113 12:47:49.459067 DQS Delay:
4114 12:47:49.462214 DQS0 = 0, DQS1 = 0
4115 12:47:49.462333 DQM Delay:
4116 12:47:49.465505 DQM0 = 50, DQM1 = 45
4117 12:47:49.465622 DQ Delay:
4118 12:47:49.469137 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4119 12:47:49.472562 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4120 12:47:49.475370 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =41
4121 12:47:49.478881 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4122 12:47:49.479001
4123 12:47:49.479109
4124 12:47:49.479214 ==
4125 12:47:49.482388 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 12:47:49.485819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 12:47:49.485940 ==
4128 12:47:49.486048
4129 12:47:49.486154
4130 12:47:49.488861 TX Vref Scan disable
4131 12:47:49.491965 == TX Byte 0 ==
4132 12:47:49.495649 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4133 12:47:49.498689 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4134 12:47:49.502212 == TX Byte 1 ==
4135 12:47:49.505640 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4136 12:47:49.508802 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4137 12:47:49.508897 ==
4138 12:47:49.511967 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 12:47:49.515545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 12:47:49.518460 ==
4141 12:47:49.518537
4142 12:47:49.518602
4143 12:47:49.518668 TX Vref Scan disable
4144 12:47:49.522381 == TX Byte 0 ==
4145 12:47:49.526119 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4146 12:47:49.532693 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4147 12:47:49.532810 == TX Byte 1 ==
4148 12:47:49.535862 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4149 12:47:49.542061 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4150 12:47:49.542176
4151 12:47:49.542270 [DATLAT]
4152 12:47:49.542371 Freq=600, CH0 RK0
4153 12:47:49.542465
4154 12:47:49.545574 DATLAT Default: 0x9
4155 12:47:49.545675 0, 0xFFFF, sum = 0
4156 12:47:49.549160 1, 0xFFFF, sum = 0
4157 12:47:49.549271 2, 0xFFFF, sum = 0
4158 12:47:49.552445 3, 0xFFFF, sum = 0
4159 12:47:49.556049 4, 0xFFFF, sum = 0
4160 12:47:49.556146 5, 0xFFFF, sum = 0
4161 12:47:49.559254 6, 0xFFFF, sum = 0
4162 12:47:49.559330 7, 0xFFFF, sum = 0
4163 12:47:49.559395 8, 0x0, sum = 1
4164 12:47:49.562687 9, 0x0, sum = 2
4165 12:47:49.562798 10, 0x0, sum = 3
4166 12:47:49.565786 11, 0x0, sum = 4
4167 12:47:49.565886 best_step = 9
4168 12:47:49.565951
4169 12:47:49.566031 ==
4170 12:47:49.568963 Dram Type= 6, Freq= 0, CH_0, rank 0
4171 12:47:49.575921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4172 12:47:49.576035 ==
4173 12:47:49.576129 RX Vref Scan: 1
4174 12:47:49.576219
4175 12:47:49.579583 RX Vref 0 -> 0, step: 1
4176 12:47:49.579683
4177 12:47:49.582412 RX Delay -179 -> 252, step: 8
4178 12:47:49.582520
4179 12:47:49.585724 Set Vref, RX VrefLevel [Byte0]: 56
4180 12:47:49.588779 [Byte1]: 49
4181 12:47:49.588904
4182 12:47:49.592148 Final RX Vref Byte 0 = 56 to rank0
4183 12:47:49.595688 Final RX Vref Byte 1 = 49 to rank0
4184 12:47:49.599145 Final RX Vref Byte 0 = 56 to rank1
4185 12:47:49.602668 Final RX Vref Byte 1 = 49 to rank1==
4186 12:47:49.605457 Dram Type= 6, Freq= 0, CH_0, rank 0
4187 12:47:49.608788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 12:47:49.608889 ==
4189 12:47:49.612151 DQS Delay:
4190 12:47:49.612230 DQS0 = 0, DQS1 = 0
4191 12:47:49.612294 DQM Delay:
4192 12:47:49.615599 DQM0 = 52, DQM1 = 46
4193 12:47:49.615702 DQ Delay:
4194 12:47:49.619249 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4195 12:47:49.622389 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4196 12:47:49.625798 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4197 12:47:49.628869 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4198 12:47:49.628984
4199 12:47:49.629090
4200 12:47:49.638915 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4201 12:47:49.639023 CH0 RK0: MR19=808, MR18=6D60
4202 12:47:49.645527 CH0_RK0: MR19=0x808, MR18=0x6D60, DQSOSC=389, MR23=63, INC=173, DEC=115
4203 12:47:49.645646
4204 12:47:49.649020 ----->DramcWriteLeveling(PI) begin...
4205 12:47:49.649134 ==
4206 12:47:49.652581 Dram Type= 6, Freq= 0, CH_0, rank 1
4207 12:47:49.658874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4208 12:47:49.658994 ==
4209 12:47:49.662171 Write leveling (Byte 0): 34 => 34
4210 12:47:49.665811 Write leveling (Byte 1): 31 => 31
4211 12:47:49.668920 DramcWriteLeveling(PI) end<-----
4212 12:47:49.669022
4213 12:47:49.669114 ==
4214 12:47:49.672428 Dram Type= 6, Freq= 0, CH_0, rank 1
4215 12:47:49.675738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 12:47:49.675844 ==
4217 12:47:49.678716 [Gating] SW mode calibration
4218 12:47:49.685518 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4219 12:47:49.688520 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4220 12:47:49.695711 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4221 12:47:49.698968 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 12:47:49.701938 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4223 12:47:49.708419 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
4224 12:47:49.711923 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
4225 12:47:49.715201 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 12:47:49.721800 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 12:47:49.725513 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 12:47:49.728838 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 12:47:49.734987 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 12:47:49.738454 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 12:47:49.741764 0 10 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4232 12:47:49.748656 0 10 16 | B1->B0 | 3d3d 3b3b | 0 0 | (0 0) (0 0)
4233 12:47:49.751892 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 12:47:49.755036 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 12:47:49.761460 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 12:47:49.764802 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 12:47:49.768274 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 12:47:49.775052 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 12:47:49.778917 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 12:47:49.781987 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4241 12:47:49.788242 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 12:47:49.791776 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 12:47:49.795398 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 12:47:49.801734 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 12:47:49.805105 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 12:47:49.808755 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 12:47:49.814889 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 12:47:49.818182 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 12:47:49.821678 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 12:47:49.828546 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 12:47:49.831378 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 12:47:49.835077 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 12:47:49.838326 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 12:47:49.844901 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 12:47:49.848183 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4256 12:47:49.851293 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 12:47:49.854664 Total UI for P1: 0, mck2ui 16
4258 12:47:49.858125 best dqsien dly found for B0: ( 0, 13, 12)
4259 12:47:49.861155 Total UI for P1: 0, mck2ui 16
4260 12:47:49.864700 best dqsien dly found for B1: ( 0, 13, 14)
4261 12:47:49.868165 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4262 12:47:49.874927 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4263 12:47:49.875050
4264 12:47:49.878167 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4265 12:47:49.880895 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4266 12:47:49.884831 [Gating] SW calibration Done
4267 12:47:49.884935 ==
4268 12:47:49.888035 Dram Type= 6, Freq= 0, CH_0, rank 1
4269 12:47:49.891046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4270 12:47:49.891170 ==
4271 12:47:49.891278 RX Vref Scan: 0
4272 12:47:49.894815
4273 12:47:49.894968 RX Vref 0 -> 0, step: 1
4274 12:47:49.895078
4275 12:47:49.898004 RX Delay -230 -> 252, step: 16
4276 12:47:49.901143 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4277 12:47:49.907793 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4278 12:47:49.911275 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4279 12:47:49.914698 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4280 12:47:49.917591 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4281 12:47:49.921092 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4282 12:47:49.927806 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4283 12:47:49.931164 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4284 12:47:49.934099 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4285 12:47:49.937514 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4286 12:47:49.944413 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4287 12:47:49.947762 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4288 12:47:49.950843 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4289 12:47:49.954388 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4290 12:47:49.960918 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4291 12:47:49.964405 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4292 12:47:49.964526 ==
4293 12:47:49.967526 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 12:47:49.970999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 12:47:49.971084 ==
4296 12:47:49.973787 DQS Delay:
4297 12:47:49.973862 DQS0 = 0, DQS1 = 0
4298 12:47:49.973925 DQM Delay:
4299 12:47:49.977469 DQM0 = 51, DQM1 = 43
4300 12:47:49.977551 DQ Delay:
4301 12:47:49.980896 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4302 12:47:49.984323 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4303 12:47:49.987263 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4304 12:47:49.990666 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4305 12:47:49.990746
4306 12:47:49.990810
4307 12:47:49.990870 ==
4308 12:47:49.993678 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 12:47:50.000439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 12:47:50.000558 ==
4311 12:47:50.000652
4312 12:47:50.000749
4313 12:47:50.000842 TX Vref Scan disable
4314 12:47:50.004240 == TX Byte 0 ==
4315 12:47:50.007732 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4316 12:47:50.010922 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4317 12:47:50.014070 == TX Byte 1 ==
4318 12:47:50.018082 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4319 12:47:50.024109 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4320 12:47:50.024198 ==
4321 12:47:50.027542 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 12:47:50.030879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 12:47:50.030991 ==
4324 12:47:50.031079
4325 12:47:50.031183
4326 12:47:50.034164 TX Vref Scan disable
4327 12:47:50.037644 == TX Byte 0 ==
4328 12:47:50.040620 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4329 12:47:50.044144 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4330 12:47:50.047399 == TX Byte 1 ==
4331 12:47:50.050784 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4332 12:47:50.054205 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4333 12:47:50.054287
4334 12:47:50.054352 [DATLAT]
4335 12:47:50.057635 Freq=600, CH0 RK1
4336 12:47:50.057714
4337 12:47:50.057783 DATLAT Default: 0x9
4338 12:47:50.060671 0, 0xFFFF, sum = 0
4339 12:47:50.064161 1, 0xFFFF, sum = 0
4340 12:47:50.064240 2, 0xFFFF, sum = 0
4341 12:47:50.067236 3, 0xFFFF, sum = 0
4342 12:47:50.067345 4, 0xFFFF, sum = 0
4343 12:47:50.070870 5, 0xFFFF, sum = 0
4344 12:47:50.070946 6, 0xFFFF, sum = 0
4345 12:47:50.073790 7, 0xFFFF, sum = 0
4346 12:47:50.073876 8, 0x0, sum = 1
4347 12:47:50.073941 9, 0x0, sum = 2
4348 12:47:50.077289 10, 0x0, sum = 3
4349 12:47:50.077376 11, 0x0, sum = 4
4350 12:47:50.080502 best_step = 9
4351 12:47:50.080612
4352 12:47:50.080704 ==
4353 12:47:50.083807 Dram Type= 6, Freq= 0, CH_0, rank 1
4354 12:47:50.087425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 12:47:50.087538 ==
4356 12:47:50.090645 RX Vref Scan: 0
4357 12:47:50.090725
4358 12:47:50.090788 RX Vref 0 -> 0, step: 1
4359 12:47:50.090846
4360 12:47:50.093578 RX Delay -163 -> 252, step: 8
4361 12:47:50.101332 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4362 12:47:50.105056 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4363 12:47:50.107917 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4364 12:47:50.111319 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4365 12:47:50.114711 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4366 12:47:50.121035 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4367 12:47:50.124719 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4368 12:47:50.127963 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4369 12:47:50.131218 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4370 12:47:50.134579 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4371 12:47:50.141247 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4372 12:47:50.144597 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4373 12:47:50.147672 iDelay=205, Bit 12, Center 48 (-91 ~ 188) 280
4374 12:47:50.151092 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4375 12:47:50.157984 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4376 12:47:50.161248 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4377 12:47:50.161378 ==
4378 12:47:50.164426 Dram Type= 6, Freq= 0, CH_0, rank 1
4379 12:47:50.167742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 12:47:50.167869 ==
4381 12:47:50.171395 DQS Delay:
4382 12:47:50.171539 DQS0 = 0, DQS1 = 0
4383 12:47:50.171652 DQM Delay:
4384 12:47:50.174199 DQM0 = 53, DQM1 = 46
4385 12:47:50.174319 DQ Delay:
4386 12:47:50.177596 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4387 12:47:50.180705 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =60
4388 12:47:50.184109 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4389 12:47:50.187395 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4390 12:47:50.187537
4391 12:47:50.187657
4392 12:47:50.197527 [DQSOSCAuto] RK1, (LSB)MR18= 0x6121, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4393 12:47:50.197689 CH0 RK1: MR19=808, MR18=6121
4394 12:47:50.204268 CH0_RK1: MR19=0x808, MR18=0x6121, DQSOSC=391, MR23=63, INC=171, DEC=114
4395 12:47:50.207436 [RxdqsGatingPostProcess] freq 600
4396 12:47:50.214304 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4397 12:47:50.217640 Pre-setting of DQS Precalculation
4398 12:47:50.221020 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4399 12:47:50.221151 ==
4400 12:47:50.223921 Dram Type= 6, Freq= 0, CH_1, rank 0
4401 12:47:50.230820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 12:47:50.231008 ==
4403 12:47:50.234303 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4404 12:47:50.240696 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4405 12:47:50.243898 [CA 0] Center 35 (5~66) winsize 62
4406 12:47:50.247717 [CA 1] Center 35 (5~66) winsize 62
4407 12:47:50.250887 [CA 2] Center 34 (4~65) winsize 62
4408 12:47:50.254197 [CA 3] Center 34 (4~65) winsize 62
4409 12:47:50.257168 [CA 4] Center 34 (4~65) winsize 62
4410 12:47:50.260660 [CA 5] Center 34 (4~64) winsize 61
4411 12:47:50.260811
4412 12:47:50.264376 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4413 12:47:50.264512
4414 12:47:50.267116 [CATrainingPosCal] consider 1 rank data
4415 12:47:50.270754 u2DelayCellTimex100 = 270/100 ps
4416 12:47:50.274024 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4417 12:47:50.277331 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4418 12:47:50.280398 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4419 12:47:50.287020 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4420 12:47:50.290303 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4421 12:47:50.293636 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4422 12:47:50.293786
4423 12:47:50.297599 CA PerBit enable=1, Macro0, CA PI delay=34
4424 12:47:50.297739
4425 12:47:50.300637 [CBTSetCACLKResult] CA Dly = 34
4426 12:47:50.300772 CS Dly: 5 (0~36)
4427 12:47:50.300883 ==
4428 12:47:50.303486 Dram Type= 6, Freq= 0, CH_1, rank 1
4429 12:47:50.310292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 12:47:50.310417 ==
4431 12:47:50.313532 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4432 12:47:50.320363 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4433 12:47:50.323933 [CA 0] Center 36 (5~67) winsize 63
4434 12:47:50.327386 [CA 1] Center 36 (5~67) winsize 63
4435 12:47:50.330225 [CA 2] Center 34 (4~65) winsize 62
4436 12:47:50.334055 [CA 3] Center 34 (4~65) winsize 62
4437 12:47:50.337050 [CA 4] Center 35 (4~66) winsize 63
4438 12:47:50.340542 [CA 5] Center 34 (3~65) winsize 63
4439 12:47:50.340644
4440 12:47:50.343721 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4441 12:47:50.343815
4442 12:47:50.346990 [CATrainingPosCal] consider 2 rank data
4443 12:47:50.350222 u2DelayCellTimex100 = 270/100 ps
4444 12:47:50.353534 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4445 12:47:50.357150 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4446 12:47:50.360097 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4447 12:47:50.367023 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4448 12:47:50.370196 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4449 12:47:50.373333 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4450 12:47:50.373413
4451 12:47:50.376842 CA PerBit enable=1, Macro0, CA PI delay=34
4452 12:47:50.376921
4453 12:47:50.380253 [CBTSetCACLKResult] CA Dly = 34
4454 12:47:50.380331 CS Dly: 6 (0~38)
4455 12:47:50.380413
4456 12:47:50.383424 ----->DramcWriteLeveling(PI) begin...
4457 12:47:50.383513 ==
4458 12:47:50.386858 Dram Type= 6, Freq= 0, CH_1, rank 0
4459 12:47:50.393703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 12:47:50.393863 ==
4461 12:47:50.396650 Write leveling (Byte 0): 32 => 32
4462 12:47:50.399843 Write leveling (Byte 1): 32 => 32
4463 12:47:50.403579 DramcWriteLeveling(PI) end<-----
4464 12:47:50.403720
4465 12:47:50.403842 ==
4466 12:47:50.406892 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 12:47:50.409828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 12:47:50.409916 ==
4469 12:47:50.413261 [Gating] SW mode calibration
4470 12:47:50.420032 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4471 12:47:50.423035 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4472 12:47:50.430097 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4473 12:47:50.433017 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 12:47:50.436670 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4475 12:47:50.443316 0 9 12 | B1->B0 | 2f2f 2c2c | 1 0 | (1 0) (0 0)
4476 12:47:50.446855 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 12:47:50.450357 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 12:47:50.456670 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 12:47:50.459842 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 12:47:50.463676 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 12:47:50.470212 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 12:47:50.473333 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4483 12:47:50.476875 0 10 12 | B1->B0 | 3737 3939 | 0 0 | (0 0) (0 0)
4484 12:47:50.482976 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 12:47:50.486537 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 12:47:50.489905 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 12:47:50.496750 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 12:47:50.499868 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 12:47:50.502973 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 12:47:50.509840 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 12:47:50.513093 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4492 12:47:50.516348 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 12:47:50.523221 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 12:47:50.526647 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 12:47:50.529581 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 12:47:50.533149 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 12:47:50.539499 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 12:47:50.543130 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 12:47:50.546348 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 12:47:50.553201 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 12:47:50.556239 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 12:47:50.559703 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 12:47:50.566061 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 12:47:50.569793 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 12:47:50.573137 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 12:47:50.579790 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4507 12:47:50.583365 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4508 12:47:50.586010 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 12:47:50.589289 Total UI for P1: 0, mck2ui 16
4510 12:47:50.593077 best dqsien dly found for B0: ( 0, 13, 10)
4511 12:47:50.596385 Total UI for P1: 0, mck2ui 16
4512 12:47:50.599784 best dqsien dly found for B1: ( 0, 13, 14)
4513 12:47:50.602896 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4514 12:47:50.606137 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4515 12:47:50.606274
4516 12:47:50.612989 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4517 12:47:50.616080 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4518 12:47:50.619638 [Gating] SW calibration Done
4519 12:47:50.619767 ==
4520 12:47:50.623027 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 12:47:50.625991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 12:47:50.626109 ==
4523 12:47:50.626186 RX Vref Scan: 0
4524 12:47:50.626255
4525 12:47:50.629541 RX Vref 0 -> 0, step: 1
4526 12:47:50.629661
4527 12:47:50.632904 RX Delay -230 -> 252, step: 16
4528 12:47:50.635983 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4529 12:47:50.639855 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4530 12:47:50.645984 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4531 12:47:50.649418 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4532 12:47:50.652878 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4533 12:47:50.656451 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4534 12:47:50.659372 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4535 12:47:50.666129 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4536 12:47:50.669583 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4537 12:47:50.672947 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4538 12:47:50.676004 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4539 12:47:50.683058 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4540 12:47:50.686330 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4541 12:47:50.689296 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4542 12:47:50.692766 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4543 12:47:50.696120 iDelay=218, Bit 15, Center 57 (-86 ~ 201) 288
4544 12:47:50.699546 ==
4545 12:47:50.699696 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 12:47:50.705980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 12:47:50.706088 ==
4548 12:47:50.706161 DQS Delay:
4549 12:47:50.709208 DQS0 = 0, DQS1 = 0
4550 12:47:50.709297 DQM Delay:
4551 12:47:50.712966 DQM0 = 51, DQM1 = 49
4552 12:47:50.713072 DQ Delay:
4553 12:47:50.715801 DQ0 =65, DQ1 =41, DQ2 =41, DQ3 =41
4554 12:47:50.719213 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =41
4555 12:47:50.722539 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4556 12:47:50.726173 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =57
4557 12:47:50.726297
4558 12:47:50.726395
4559 12:47:50.726477 ==
4560 12:47:50.729151 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 12:47:50.732567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 12:47:50.732779 ==
4563 12:47:50.732916
4564 12:47:50.733042
4565 12:47:50.736047 TX Vref Scan disable
4566 12:47:50.738924 == TX Byte 0 ==
4567 12:47:50.742671 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4568 12:47:50.745865 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4569 12:47:50.749273 == TX Byte 1 ==
4570 12:47:50.752619 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4571 12:47:50.755612 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4572 12:47:50.755893 ==
4573 12:47:50.758953 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 12:47:50.762481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 12:47:50.765795 ==
4576 12:47:50.765968
4577 12:47:50.766103
4578 12:47:50.766225 TX Vref Scan disable
4579 12:47:50.769890 == TX Byte 0 ==
4580 12:47:50.772695 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4581 12:47:50.779463 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4582 12:47:50.779683 == TX Byte 1 ==
4583 12:47:50.783144 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4584 12:47:50.789749 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4585 12:47:50.789976
4586 12:47:50.790124 [DATLAT]
4587 12:47:50.790255 Freq=600, CH1 RK0
4588 12:47:50.790389
4589 12:47:50.793064 DATLAT Default: 0x9
4590 12:47:50.793221 0, 0xFFFF, sum = 0
4591 12:47:50.796395 1, 0xFFFF, sum = 0
4592 12:47:50.796573 2, 0xFFFF, sum = 0
4593 12:47:50.799702 3, 0xFFFF, sum = 0
4594 12:47:50.802750 4, 0xFFFF, sum = 0
4595 12:47:50.802932 5, 0xFFFF, sum = 0
4596 12:47:50.806514 6, 0xFFFF, sum = 0
4597 12:47:50.806691 7, 0xFFFF, sum = 0
4598 12:47:50.806834 8, 0x0, sum = 1
4599 12:47:50.809373 9, 0x0, sum = 2
4600 12:47:50.809530 10, 0x0, sum = 3
4601 12:47:50.812854 11, 0x0, sum = 4
4602 12:47:50.813023 best_step = 9
4603 12:47:50.813156
4604 12:47:50.813322 ==
4605 12:47:50.816058 Dram Type= 6, Freq= 0, CH_1, rank 0
4606 12:47:50.822904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 12:47:50.823125 ==
4608 12:47:50.823271 RX Vref Scan: 1
4609 12:47:50.823400
4610 12:47:50.826309 RX Vref 0 -> 0, step: 1
4611 12:47:50.826479
4612 12:47:50.829593 RX Delay -163 -> 252, step: 8
4613 12:47:50.829771
4614 12:47:50.832558 Set Vref, RX VrefLevel [Byte0]: 51
4615 12:47:50.836378 [Byte1]: 48
4616 12:47:50.836580
4617 12:47:50.839394 Final RX Vref Byte 0 = 51 to rank0
4618 12:47:50.842505 Final RX Vref Byte 1 = 48 to rank0
4619 12:47:50.846209 Final RX Vref Byte 0 = 51 to rank1
4620 12:47:50.849433 Final RX Vref Byte 1 = 48 to rank1==
4621 12:47:50.852731 Dram Type= 6, Freq= 0, CH_1, rank 0
4622 12:47:50.856216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 12:47:50.856400 ==
4624 12:47:50.859547 DQS Delay:
4625 12:47:50.859706 DQS0 = 0, DQS1 = 0
4626 12:47:50.859834 DQM Delay:
4627 12:47:50.862366 DQM0 = 48, DQM1 = 45
4628 12:47:50.862514 DQ Delay:
4629 12:47:50.865791 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4630 12:47:50.869223 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4631 12:47:50.872675 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4632 12:47:50.876197 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4633 12:47:50.876405
4634 12:47:50.876542
4635 12:47:50.885807 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a6f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
4636 12:47:50.889153 CH1 RK0: MR19=808, MR18=4A6F
4637 12:47:50.892329 CH1_RK0: MR19=0x808, MR18=0x4A6F, DQSOSC=389, MR23=63, INC=173, DEC=115
4638 12:47:50.892534
4639 12:47:50.895833 ----->DramcWriteLeveling(PI) begin...
4640 12:47:50.899022 ==
4641 12:47:50.902342 Dram Type= 6, Freq= 0, CH_1, rank 1
4642 12:47:50.905850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 12:47:50.906046 ==
4644 12:47:50.909044 Write leveling (Byte 0): 30 => 30
4645 12:47:50.912490 Write leveling (Byte 1): 32 => 32
4646 12:47:50.915429 DramcWriteLeveling(PI) end<-----
4647 12:47:50.915611
4648 12:47:50.915753 ==
4649 12:47:50.918875 Dram Type= 6, Freq= 0, CH_1, rank 1
4650 12:47:50.922377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 12:47:50.922566 ==
4652 12:47:50.925516 [Gating] SW mode calibration
4653 12:47:50.932236 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4654 12:47:50.939117 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4655 12:47:50.942284 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4656 12:47:50.945322 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4657 12:47:50.948944 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4658 12:47:50.955791 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (1 1) (1 1)
4659 12:47:50.958837 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 12:47:50.962478 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 12:47:51.062625 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 12:47:51.062809 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 12:47:51.062929 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 12:47:51.062999 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 12:47:51.063089 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 12:47:51.063162 0 10 12 | B1->B0 | 3b3b 3a3a | 0 0 | (1 1) (0 0)
4667 12:47:51.063236 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 12:47:51.063326 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 12:47:51.063382 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 12:47:51.063437 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 12:47:51.063496 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 12:47:51.063563 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 12:47:51.063620 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 12:47:51.063675 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4675 12:47:51.063730 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 12:47:51.063788 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 12:47:51.063842 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 12:47:51.063896 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 12:47:51.063950 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 12:47:51.064007 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 12:47:51.064062 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 12:47:51.064116 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 12:47:51.065016 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 12:47:51.068806 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 12:47:51.075291 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 12:47:51.078474 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 12:47:51.081890 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 12:47:51.085374 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 12:47:51.091647 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4690 12:47:51.094993 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4691 12:47:51.098464 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 12:47:51.101829 Total UI for P1: 0, mck2ui 16
4693 12:47:51.104884 best dqsien dly found for B0: ( 0, 13, 12)
4694 12:47:51.108172 Total UI for P1: 0, mck2ui 16
4695 12:47:51.111816 best dqsien dly found for B1: ( 0, 13, 10)
4696 12:47:51.115060 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4697 12:47:51.121438 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4698 12:47:51.121634
4699 12:47:51.124703 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4700 12:47:51.128233 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4701 12:47:51.131617 [Gating] SW calibration Done
4702 12:47:51.131768 ==
4703 12:47:51.134600 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 12:47:51.138115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 12:47:51.138261 ==
4706 12:47:51.141439 RX Vref Scan: 0
4707 12:47:51.141551
4708 12:47:51.141619 RX Vref 0 -> 0, step: 1
4709 12:47:51.141680
4710 12:47:51.144674 RX Delay -230 -> 252, step: 16
4711 12:47:51.148181 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4712 12:47:51.154704 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4713 12:47:51.158115 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4714 12:47:51.161462 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4715 12:47:51.164541 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4716 12:47:51.168234 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4717 12:47:51.175036 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4718 12:47:51.178084 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4719 12:47:51.181336 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4720 12:47:51.184789 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4721 12:47:51.191247 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4722 12:47:51.194805 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4723 12:47:51.198030 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4724 12:47:51.201407 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4725 12:47:51.207773 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4726 12:47:51.211071 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4727 12:47:51.211188 ==
4728 12:47:51.214476 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 12:47:51.217514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 12:47:51.217654 ==
4731 12:47:51.220957 DQS Delay:
4732 12:47:51.221096 DQS0 = 0, DQS1 = 0
4733 12:47:51.221197 DQM Delay:
4734 12:47:51.224417 DQM0 = 50, DQM1 = 47
4735 12:47:51.224522 DQ Delay:
4736 12:47:51.227546 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4737 12:47:51.230953 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4738 12:47:51.234585 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4739 12:47:51.238017 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4740 12:47:51.238219
4741 12:47:51.238367
4742 12:47:51.238487 ==
4743 12:47:51.240922 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 12:47:51.247794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 12:47:51.247967 ==
4746 12:47:51.248068
4747 12:47:51.248159
4748 12:47:51.248247 TX Vref Scan disable
4749 12:47:51.251263 == TX Byte 0 ==
4750 12:47:51.254670 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4751 12:47:51.261262 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4752 12:47:51.261425 == TX Byte 1 ==
4753 12:47:51.264615 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4754 12:47:51.271075 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4755 12:47:51.271233 ==
4756 12:47:51.274242 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 12:47:51.277886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 12:47:51.278027 ==
4759 12:47:51.278135
4760 12:47:51.278227
4761 12:47:51.281032 TX Vref Scan disable
4762 12:47:51.284178 == TX Byte 0 ==
4763 12:47:51.287452 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4764 12:47:51.290807 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4765 12:47:51.294402 == TX Byte 1 ==
4766 12:47:51.297426 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4767 12:47:51.301118 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4768 12:47:51.301278
4769 12:47:51.301421 [DATLAT]
4770 12:47:51.304024 Freq=600, CH1 RK1
4771 12:47:51.304187
4772 12:47:51.304319 DATLAT Default: 0x9
4773 12:47:51.307467 0, 0xFFFF, sum = 0
4774 12:47:51.311101 1, 0xFFFF, sum = 0
4775 12:47:51.311282 2, 0xFFFF, sum = 0
4776 12:47:51.314147 3, 0xFFFF, sum = 0
4777 12:47:51.314247 4, 0xFFFF, sum = 0
4778 12:47:51.317753 5, 0xFFFF, sum = 0
4779 12:47:51.317850 6, 0xFFFF, sum = 0
4780 12:47:51.320789 7, 0xFFFF, sum = 0
4781 12:47:51.320909 8, 0x0, sum = 1
4782 12:47:51.321013 9, 0x0, sum = 2
4783 12:47:51.324128 10, 0x0, sum = 3
4784 12:47:51.324237 11, 0x0, sum = 4
4785 12:47:51.327475 best_step = 9
4786 12:47:51.327601
4787 12:47:51.327707 ==
4788 12:47:51.331227 Dram Type= 6, Freq= 0, CH_1, rank 1
4789 12:47:51.334258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4790 12:47:51.334392 ==
4791 12:47:51.337715 RX Vref Scan: 0
4792 12:47:51.337829
4793 12:47:51.337936 RX Vref 0 -> 0, step: 1
4794 12:47:51.338035
4795 12:47:51.340725 RX Delay -163 -> 252, step: 8
4796 12:47:51.347827 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4797 12:47:51.351673 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4798 12:47:51.355224 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4799 12:47:51.358104 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4800 12:47:51.361472 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4801 12:47:51.368630 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4802 12:47:51.371437 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4803 12:47:51.374872 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4804 12:47:51.378360 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4805 12:47:51.381452 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4806 12:47:51.388051 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4807 12:47:51.391450 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4808 12:47:51.394617 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4809 12:47:51.398126 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4810 12:47:51.404787 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4811 12:47:51.408282 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4812 12:47:51.408424 ==
4813 12:47:51.411404 Dram Type= 6, Freq= 0, CH_1, rank 1
4814 12:47:51.414771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4815 12:47:51.414932 ==
4816 12:47:51.417968 DQS Delay:
4817 12:47:51.418112 DQS0 = 0, DQS1 = 0
4818 12:47:51.418255 DQM Delay:
4819 12:47:51.421326 DQM0 = 48, DQM1 = 44
4820 12:47:51.421480 DQ Delay:
4821 12:47:51.424796 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4822 12:47:51.428335 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4823 12:47:51.431652 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4824 12:47:51.435086 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4825 12:47:51.435306
4826 12:47:51.435419
4827 12:47:51.444509 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d25, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 389 ps
4828 12:47:51.444680 CH1 RK1: MR19=808, MR18=6D25
4829 12:47:51.451247 CH1_RK1: MR19=0x808, MR18=0x6D25, DQSOSC=389, MR23=63, INC=173, DEC=115
4830 12:47:51.454531 [RxdqsGatingPostProcess] freq 600
4831 12:47:51.461749 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4832 12:47:51.465024 Pre-setting of DQS Precalculation
4833 12:47:51.468167 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4834 12:47:51.474940 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4835 12:47:51.481321 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4836 12:47:51.484840
4837 12:47:51.485005
4838 12:47:51.485105 [Calibration Summary] 1200 Mbps
4839 12:47:51.488020 CH 0, Rank 0
4840 12:47:51.488131 SW Impedance : PASS
4841 12:47:51.491714 DUTY Scan : NO K
4842 12:47:51.494897 ZQ Calibration : PASS
4843 12:47:51.495039 Jitter Meter : NO K
4844 12:47:51.498038 CBT Training : PASS
4845 12:47:51.501409 Write leveling : PASS
4846 12:47:51.501564 RX DQS gating : PASS
4847 12:47:51.504334 RX DQ/DQS(RDDQC) : PASS
4848 12:47:51.508014 TX DQ/DQS : PASS
4849 12:47:51.508141 RX DATLAT : PASS
4850 12:47:51.511398 RX DQ/DQS(Engine): PASS
4851 12:47:51.514356 TX OE : NO K
4852 12:47:51.514498 All Pass.
4853 12:47:51.514604
4854 12:47:51.514705 CH 0, Rank 1
4855 12:47:51.517940 SW Impedance : PASS
4856 12:47:51.521117 DUTY Scan : NO K
4857 12:47:51.521234 ZQ Calibration : PASS
4858 12:47:51.524278 Jitter Meter : NO K
4859 12:47:51.527927 CBT Training : PASS
4860 12:47:51.528126 Write leveling : PASS
4861 12:47:51.531352 RX DQS gating : PASS
4862 12:47:51.534554 RX DQ/DQS(RDDQC) : PASS
4863 12:47:51.534699 TX DQ/DQS : PASS
4864 12:47:51.537530 RX DATLAT : PASS
4865 12:47:51.537660 RX DQ/DQS(Engine): PASS
4866 12:47:51.541387 TX OE : NO K
4867 12:47:51.541532 All Pass.
4868 12:47:51.541638
4869 12:47:51.544601 CH 1, Rank 0
4870 12:47:51.544776 SW Impedance : PASS
4871 12:47:51.547921 DUTY Scan : NO K
4872 12:47:51.551043 ZQ Calibration : PASS
4873 12:47:51.551235 Jitter Meter : NO K
4874 12:47:51.554304 CBT Training : PASS
4875 12:47:51.557748 Write leveling : PASS
4876 12:47:51.557935 RX DQS gating : PASS
4877 12:47:51.561021 RX DQ/DQS(RDDQC) : PASS
4878 12:47:51.564197 TX DQ/DQS : PASS
4879 12:47:51.564337 RX DATLAT : PASS
4880 12:47:51.567772 RX DQ/DQS(Engine): PASS
4881 12:47:51.571271 TX OE : NO K
4882 12:47:51.571436 All Pass.
4883 12:47:51.571560
4884 12:47:51.571628 CH 1, Rank 1
4885 12:47:51.574864 SW Impedance : PASS
4886 12:47:51.577637 DUTY Scan : NO K
4887 12:47:51.577802 ZQ Calibration : PASS
4888 12:47:51.581085 Jitter Meter : NO K
4889 12:47:51.584324 CBT Training : PASS
4890 12:47:51.584507 Write leveling : PASS
4891 12:47:51.587590 RX DQS gating : PASS
4892 12:47:51.587737 RX DQ/DQS(RDDQC) : PASS
4893 12:47:51.591000 TX DQ/DQS : PASS
4894 12:47:51.594752 RX DATLAT : PASS
4895 12:47:51.594862 RX DQ/DQS(Engine): PASS
4896 12:47:51.597824 TX OE : NO K
4897 12:47:51.597918 All Pass.
4898 12:47:51.598006
4899 12:47:51.600664 DramC Write-DBI off
4900 12:47:51.604061 PER_BANK_REFRESH: Hybrid Mode
4901 12:47:51.604221 TX_TRACKING: ON
4902 12:47:51.614061 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4903 12:47:51.617496 [FAST_K] Save calibration result to emmc
4904 12:47:51.621114 dramc_set_vcore_voltage set vcore to 662500
4905 12:47:51.624269 Read voltage for 933, 3
4906 12:47:51.624371 Vio18 = 0
4907 12:47:51.624464 Vcore = 662500
4908 12:47:51.628087 Vdram = 0
4909 12:47:51.628206 Vddq = 0
4910 12:47:51.628297 Vmddr = 0
4911 12:47:51.634094 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4912 12:47:51.637564 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4913 12:47:51.640963 MEM_TYPE=3, freq_sel=17
4914 12:47:51.644075 sv_algorithm_assistance_LP4_1600
4915 12:47:51.647661 ============ PULL DRAM RESETB DOWN ============
4916 12:47:51.650955 ========== PULL DRAM RESETB DOWN end =========
4917 12:47:51.657493 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4918 12:47:51.660874 ===================================
4919 12:47:51.664299 LPDDR4 DRAM CONFIGURATION
4920 12:47:51.667603 ===================================
4921 12:47:51.667728 EX_ROW_EN[0] = 0x0
4922 12:47:51.670914 EX_ROW_EN[1] = 0x0
4923 12:47:51.671028 LP4Y_EN = 0x0
4924 12:47:51.674453 WORK_FSP = 0x0
4925 12:47:51.674559 WL = 0x3
4926 12:47:51.677286 RL = 0x3
4927 12:47:51.677388 BL = 0x2
4928 12:47:51.680752 RPST = 0x0
4929 12:47:51.680865 RD_PRE = 0x0
4930 12:47:51.684335 WR_PRE = 0x1
4931 12:47:51.684447 WR_PST = 0x0
4932 12:47:51.687168 DBI_WR = 0x0
4933 12:47:51.687270 DBI_RD = 0x0
4934 12:47:51.690700 OTF = 0x1
4935 12:47:51.694055 ===================================
4936 12:47:51.697412 ===================================
4937 12:47:51.697522 ANA top config
4938 12:47:51.701068 ===================================
4939 12:47:51.703959 DLL_ASYNC_EN = 0
4940 12:47:51.707228 ALL_SLAVE_EN = 1
4941 12:47:51.710751 NEW_RANK_MODE = 1
4942 12:47:51.710925 DLL_IDLE_MODE = 1
4943 12:47:51.714178 LP45_APHY_COMB_EN = 1
4944 12:47:51.717056 TX_ODT_DIS = 1
4945 12:47:51.720233 NEW_8X_MODE = 1
4946 12:47:51.723999 ===================================
4947 12:47:51.727049 ===================================
4948 12:47:51.730678 data_rate = 1866
4949 12:47:51.730880 CKR = 1
4950 12:47:51.733818 DQ_P2S_RATIO = 8
4951 12:47:51.737431 ===================================
4952 12:47:51.740174 CA_P2S_RATIO = 8
4953 12:47:51.743440 DQ_CA_OPEN = 0
4954 12:47:51.746744 DQ_SEMI_OPEN = 0
4955 12:47:51.750192 CA_SEMI_OPEN = 0
4956 12:47:51.753760 CA_FULL_RATE = 0
4957 12:47:51.753948 DQ_CKDIV4_EN = 1
4958 12:47:51.756623 CA_CKDIV4_EN = 1
4959 12:47:51.759991 CA_PREDIV_EN = 0
4960 12:47:51.763761 PH8_DLY = 0
4961 12:47:51.766792 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4962 12:47:51.766925 DQ_AAMCK_DIV = 4
4963 12:47:51.770315 CA_AAMCK_DIV = 4
4964 12:47:51.773435 CA_ADMCK_DIV = 4
4965 12:47:51.776657 DQ_TRACK_CA_EN = 0
4966 12:47:51.780352 CA_PICK = 933
4967 12:47:51.783684 CA_MCKIO = 933
4968 12:47:51.786588 MCKIO_SEMI = 0
4969 12:47:51.786726 PLL_FREQ = 3732
4970 12:47:51.790044 DQ_UI_PI_RATIO = 32
4971 12:47:51.793548 CA_UI_PI_RATIO = 0
4972 12:47:51.797019 ===================================
4973 12:47:51.799963 ===================================
4974 12:47:51.803299 memory_type:LPDDR4
4975 12:47:51.803454 GP_NUM : 10
4976 12:47:51.806758 SRAM_EN : 1
4977 12:47:51.810506 MD32_EN : 0
4978 12:47:51.813651 ===================================
4979 12:47:51.813831 [ANA_INIT] >>>>>>>>>>>>>>
4980 12:47:51.816665 <<<<<< [CONFIGURE PHASE]: ANA_TX
4981 12:47:51.819900 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4982 12:47:51.823451 ===================================
4983 12:47:51.827023 data_rate = 1866,PCW = 0X8f00
4984 12:47:51.829861 ===================================
4985 12:47:51.833627 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4986 12:47:51.840025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4987 12:47:51.843367 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4988 12:47:51.850009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4989 12:47:51.853626 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4990 12:47:51.856445 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4991 12:47:51.859810 [ANA_INIT] flow start
4992 12:47:51.859977 [ANA_INIT] PLL >>>>>>>>
4993 12:47:51.863235 [ANA_INIT] PLL <<<<<<<<
4994 12:47:51.866588 [ANA_INIT] MIDPI >>>>>>>>
4995 12:47:51.866819 [ANA_INIT] MIDPI <<<<<<<<
4996 12:47:51.870211 [ANA_INIT] DLL >>>>>>>>
4997 12:47:51.873229 [ANA_INIT] flow end
4998 12:47:51.876502 ============ LP4 DIFF to SE enter ============
4999 12:47:51.880098 ============ LP4 DIFF to SE exit ============
5000 12:47:51.883427 [ANA_INIT] <<<<<<<<<<<<<
5001 12:47:51.887014 [Flow] Enable top DCM control >>>>>
5002 12:47:51.890172 [Flow] Enable top DCM control <<<<<
5003 12:47:51.893092 Enable DLL master slave shuffle
5004 12:47:51.896591 ==============================================================
5005 12:47:51.900129 Gating Mode config
5006 12:47:51.903012 ==============================================================
5007 12:47:51.906726 Config description:
5008 12:47:51.916634 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5009 12:47:51.923385 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5010 12:47:51.926415 SELPH_MODE 0: By rank 1: By Phase
5011 12:47:51.933197 ==============================================================
5012 12:47:51.936605 GAT_TRACK_EN = 1
5013 12:47:51.939974 RX_GATING_MODE = 2
5014 12:47:51.943065 RX_GATING_TRACK_MODE = 2
5015 12:47:51.946637 SELPH_MODE = 1
5016 12:47:51.949808 PICG_EARLY_EN = 1
5017 12:47:51.950051 VALID_LAT_VALUE = 1
5018 12:47:51.956610 ==============================================================
5019 12:47:51.959634 Enter into Gating configuration >>>>
5020 12:47:51.963307 Exit from Gating configuration <<<<
5021 12:47:51.966775 Enter into DVFS_PRE_config >>>>>
5022 12:47:51.976742 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5023 12:47:51.980008 Exit from DVFS_PRE_config <<<<<
5024 12:47:51.983202 Enter into PICG configuration >>>>
5025 12:47:51.986642 Exit from PICG configuration <<<<
5026 12:47:51.989915 [RX_INPUT] configuration >>>>>
5027 12:47:51.992994 [RX_INPUT] configuration <<<<<
5028 12:47:51.996436 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5029 12:47:52.003245 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5030 12:47:52.009711 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5031 12:47:52.016107 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5032 12:47:52.022873 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5033 12:47:52.029713 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5034 12:47:52.033147 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5035 12:47:52.036264 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5036 12:47:52.039738 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5037 12:47:52.042914 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5038 12:47:52.049848 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5039 12:47:52.052738 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5040 12:47:52.056518 ===================================
5041 12:47:52.059703 LPDDR4 DRAM CONFIGURATION
5042 12:47:52.062455 ===================================
5043 12:47:52.062644 EX_ROW_EN[0] = 0x0
5044 12:47:52.066255 EX_ROW_EN[1] = 0x0
5045 12:47:52.066449 LP4Y_EN = 0x0
5046 12:47:52.069216 WORK_FSP = 0x0
5047 12:47:52.069390 WL = 0x3
5048 12:47:52.072560 RL = 0x3
5049 12:47:52.072742 BL = 0x2
5050 12:47:52.076137 RPST = 0x0
5051 12:47:52.079498 RD_PRE = 0x0
5052 12:47:52.079675 WR_PRE = 0x1
5053 12:47:52.082475 WR_PST = 0x0
5054 12:47:52.082610 DBI_WR = 0x0
5055 12:47:52.086165 DBI_RD = 0x0
5056 12:47:52.086305 OTF = 0x1
5057 12:47:52.089460 ===================================
5058 12:47:52.092788 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5059 12:47:52.099090 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5060 12:47:52.102462 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5061 12:47:52.105959 ===================================
5062 12:47:52.109179 LPDDR4 DRAM CONFIGURATION
5063 12:47:52.112220 ===================================
5064 12:47:52.112366 EX_ROW_EN[0] = 0x10
5065 12:47:52.115825 EX_ROW_EN[1] = 0x0
5066 12:47:52.116003 LP4Y_EN = 0x0
5067 12:47:52.119022 WORK_FSP = 0x0
5068 12:47:52.119164 WL = 0x3
5069 12:47:52.122370 RL = 0x3
5070 12:47:52.122526 BL = 0x2
5071 12:47:52.125582 RPST = 0x0
5072 12:47:52.125726 RD_PRE = 0x0
5073 12:47:52.128878 WR_PRE = 0x1
5074 12:47:52.132543 WR_PST = 0x0
5075 12:47:52.132700 DBI_WR = 0x0
5076 12:47:52.135463 DBI_RD = 0x0
5077 12:47:52.135628 OTF = 0x1
5078 12:47:52.138865 ===================================
5079 12:47:52.145918 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5080 12:47:52.148996 nWR fixed to 30
5081 12:47:52.152556 [ModeRegInit_LP4] CH0 RK0
5082 12:47:52.152682 [ModeRegInit_LP4] CH0 RK1
5083 12:47:52.156215 [ModeRegInit_LP4] CH1 RK0
5084 12:47:52.159300 [ModeRegInit_LP4] CH1 RK1
5085 12:47:52.159436 match AC timing 9
5086 12:47:52.165790 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5087 12:47:52.169196 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5088 12:47:52.172780 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5089 12:47:52.179372 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5090 12:47:52.182395 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5091 12:47:52.182524 ==
5092 12:47:52.185802 Dram Type= 6, Freq= 0, CH_0, rank 0
5093 12:47:52.189473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 12:47:52.189668 ==
5095 12:47:52.195820 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5096 12:47:52.202423 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5097 12:47:52.205805 [CA 0] Center 37 (6~68) winsize 63
5098 12:47:52.208875 [CA 1] Center 37 (6~68) winsize 63
5099 12:47:52.212443 [CA 2] Center 34 (4~65) winsize 62
5100 12:47:52.215852 [CA 3] Center 34 (3~65) winsize 63
5101 12:47:52.218768 [CA 4] Center 33 (3~64) winsize 62
5102 12:47:52.222423 [CA 5] Center 32 (2~62) winsize 61
5103 12:47:52.222633
5104 12:47:52.225428 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5105 12:47:52.225611
5106 12:47:52.229130 [CATrainingPosCal] consider 1 rank data
5107 12:47:52.233226 u2DelayCellTimex100 = 270/100 ps
5108 12:47:52.235268 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5109 12:47:52.238854 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5110 12:47:52.242311 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5111 12:47:52.245786 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5112 12:47:52.248644 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5113 12:47:52.251927 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5114 12:47:52.255309
5115 12:47:52.258817 CA PerBit enable=1, Macro0, CA PI delay=32
5116 12:47:52.259026
5117 12:47:52.262155 [CBTSetCACLKResult] CA Dly = 32
5118 12:47:52.262360 CS Dly: 5 (0~36)
5119 12:47:52.262502 ==
5120 12:47:52.265417 Dram Type= 6, Freq= 0, CH_0, rank 1
5121 12:47:52.268960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 12:47:52.269140 ==
5123 12:47:52.275750 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5124 12:47:52.282061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5125 12:47:52.285578 [CA 0] Center 37 (6~68) winsize 63
5126 12:47:52.288760 [CA 1] Center 37 (7~68) winsize 62
5127 12:47:52.291834 [CA 2] Center 34 (4~65) winsize 62
5128 12:47:52.295275 [CA 3] Center 34 (3~65) winsize 63
5129 12:47:52.298833 [CA 4] Center 33 (3~64) winsize 62
5130 12:47:52.302166 [CA 5] Center 32 (2~62) winsize 61
5131 12:47:52.302307
5132 12:47:52.305566 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5133 12:47:52.305695
5134 12:47:52.308876 [CATrainingPosCal] consider 2 rank data
5135 12:47:52.311981 u2DelayCellTimex100 = 270/100 ps
5136 12:47:52.315303 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5137 12:47:52.318836 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5138 12:47:52.322043 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5139 12:47:52.325511 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5140 12:47:52.328949 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5141 12:47:52.335139 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5142 12:47:52.335314
5143 12:47:52.338641 CA PerBit enable=1, Macro0, CA PI delay=32
5144 12:47:52.338770
5145 12:47:52.341833 [CBTSetCACLKResult] CA Dly = 32
5146 12:47:52.341975 CS Dly: 5 (0~37)
5147 12:47:52.342081
5148 12:47:52.345026 ----->DramcWriteLeveling(PI) begin...
5149 12:47:52.345166 ==
5150 12:47:52.349065 Dram Type= 6, Freq= 0, CH_0, rank 0
5151 12:47:52.355099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5152 12:47:52.355280 ==
5153 12:47:52.358694 Write leveling (Byte 0): 31 => 31
5154 12:47:52.358915 Write leveling (Byte 1): 29 => 29
5155 12:47:52.361539 DramcWriteLeveling(PI) end<-----
5156 12:47:52.361737
5157 12:47:52.361874 ==
5158 12:47:52.364916 Dram Type= 6, Freq= 0, CH_0, rank 0
5159 12:47:52.371765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 12:47:52.371993 ==
5161 12:47:52.375449 [Gating] SW mode calibration
5162 12:47:52.381447 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5163 12:47:52.385057 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5164 12:47:52.391601 0 14 0 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
5165 12:47:52.395044 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 12:47:52.398794 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 12:47:52.404682 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 12:47:52.408199 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 12:47:52.411397 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 12:47:52.418108 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5171 12:47:52.421556 0 14 28 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
5172 12:47:52.424753 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5173 12:47:52.431302 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 12:47:52.434832 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 12:47:52.438221 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 12:47:52.445282 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 12:47:52.448370 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 12:47:52.451615 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5179 12:47:52.454627 0 15 28 | B1->B0 | 2727 4040 | 0 1 | (0 0) (0 0)
5180 12:47:52.461417 1 0 0 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
5181 12:47:52.464790 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 12:47:52.468110 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 12:47:52.474931 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 12:47:52.478136 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 12:47:52.481451 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 12:47:52.487928 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5187 12:47:52.491374 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5188 12:47:52.495078 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5189 12:47:52.501723 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 12:47:52.504897 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 12:47:52.508256 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 12:47:52.514828 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 12:47:52.518349 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 12:47:52.521820 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 12:47:52.528352 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 12:47:52.531973 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 12:47:52.534807 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 12:47:52.538367 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 12:47:52.545184 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 12:47:52.548031 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 12:47:52.551758 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 12:47:52.558482 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5203 12:47:52.561706 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5204 12:47:52.565274 Total UI for P1: 0, mck2ui 16
5205 12:47:52.568521 best dqsien dly found for B0: ( 1, 2, 24)
5206 12:47:52.572012 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 12:47:52.575081 Total UI for P1: 0, mck2ui 16
5208 12:47:52.578124 best dqsien dly found for B1: ( 1, 2, 28)
5209 12:47:52.581483 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5210 12:47:52.585393 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5211 12:47:52.585553
5212 12:47:52.591562 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5213 12:47:52.594904 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5214 12:47:52.595132 [Gating] SW calibration Done
5215 12:47:52.598170 ==
5216 12:47:52.601401 Dram Type= 6, Freq= 0, CH_0, rank 0
5217 12:47:52.604953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5218 12:47:52.605220 ==
5219 12:47:52.605362 RX Vref Scan: 0
5220 12:47:52.605501
5221 12:47:52.608248 RX Vref 0 -> 0, step: 1
5222 12:47:52.608439
5223 12:47:52.611447 RX Delay -80 -> 252, step: 8
5224 12:47:52.614577 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5225 12:47:52.618260 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5226 12:47:52.621088 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5227 12:47:52.628070 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5228 12:47:52.631442 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5229 12:47:52.634761 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5230 12:47:52.638045 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5231 12:47:52.641076 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5232 12:47:52.644677 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5233 12:47:52.651094 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5234 12:47:52.654532 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5235 12:47:52.658076 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5236 12:47:52.661432 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5237 12:47:52.664356 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5238 12:47:52.671405 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5239 12:47:52.674618 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5240 12:47:52.674837 ==
5241 12:47:52.677908 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 12:47:52.681366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 12:47:52.681599 ==
5244 12:47:52.681740 DQS Delay:
5245 12:47:52.684837 DQS0 = 0, DQS1 = 0
5246 12:47:52.685028 DQM Delay:
5247 12:47:52.687664 DQM0 = 105, DQM1 = 95
5248 12:47:52.687849 DQ Delay:
5249 12:47:52.691065 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5250 12:47:52.694658 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5251 12:47:52.697955 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5252 12:47:52.701438 DQ12 =99, DQ13 =103, DQ14 =107, DQ15 =99
5253 12:47:52.701668
5254 12:47:52.701813
5255 12:47:52.701944 ==
5256 12:47:52.704720 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 12:47:52.711244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 12:47:52.711449 ==
5259 12:47:52.711569
5260 12:47:52.711672
5261 12:47:52.711772 TX Vref Scan disable
5262 12:47:52.714942 == TX Byte 0 ==
5263 12:47:52.718063 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5264 12:47:52.725064 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5265 12:47:52.725299 == TX Byte 1 ==
5266 12:47:52.728024 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5267 12:47:52.734841 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5268 12:47:52.735091 ==
5269 12:47:52.737813 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 12:47:52.741190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 12:47:52.741338 ==
5272 12:47:52.741420
5273 12:47:52.741483
5274 12:47:52.744871 TX Vref Scan disable
5275 12:47:52.745088 == TX Byte 0 ==
5276 12:47:52.751544 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5277 12:47:52.754580 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5278 12:47:52.754774 == TX Byte 1 ==
5279 12:47:52.761278 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5280 12:47:52.765006 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5281 12:47:52.765251
5282 12:47:52.765396 [DATLAT]
5283 12:47:52.768348 Freq=933, CH0 RK0
5284 12:47:52.768555
5285 12:47:52.768698 DATLAT Default: 0xd
5286 12:47:52.771448 0, 0xFFFF, sum = 0
5287 12:47:52.771653 1, 0xFFFF, sum = 0
5288 12:47:52.775152 2, 0xFFFF, sum = 0
5289 12:47:52.775351 3, 0xFFFF, sum = 0
5290 12:47:52.777963 4, 0xFFFF, sum = 0
5291 12:47:52.778109 5, 0xFFFF, sum = 0
5292 12:47:52.781362 6, 0xFFFF, sum = 0
5293 12:47:52.781596 7, 0xFFFF, sum = 0
5294 12:47:52.784913 8, 0xFFFF, sum = 0
5295 12:47:52.785165 9, 0xFFFF, sum = 0
5296 12:47:52.788383 10, 0x0, sum = 1
5297 12:47:52.788631 11, 0x0, sum = 2
5298 12:47:52.791897 12, 0x0, sum = 3
5299 12:47:52.792122 13, 0x0, sum = 4
5300 12:47:52.794932 best_step = 11
5301 12:47:52.795132
5302 12:47:52.795262 ==
5303 12:47:52.797881 Dram Type= 6, Freq= 0, CH_0, rank 0
5304 12:47:52.801512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 12:47:52.801730 ==
5306 12:47:52.805106 RX Vref Scan: 1
5307 12:47:52.805326
5308 12:47:52.805469 RX Vref 0 -> 0, step: 1
5309 12:47:52.805592
5310 12:47:52.807794 RX Delay -53 -> 252, step: 4
5311 12:47:52.807970
5312 12:47:52.811260 Set Vref, RX VrefLevel [Byte0]: 56
5313 12:47:52.814583 [Byte1]: 49
5314 12:47:52.819075
5315 12:47:52.819296 Final RX Vref Byte 0 = 56 to rank0
5316 12:47:52.822061 Final RX Vref Byte 1 = 49 to rank0
5317 12:47:52.826006 Final RX Vref Byte 0 = 56 to rank1
5318 12:47:52.828529 Final RX Vref Byte 1 = 49 to rank1==
5319 12:47:52.831981 Dram Type= 6, Freq= 0, CH_0, rank 0
5320 12:47:52.838784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 12:47:52.838995 ==
5322 12:47:52.839128 DQS Delay:
5323 12:47:52.839248 DQS0 = 0, DQS1 = 0
5324 12:47:52.842025 DQM Delay:
5325 12:47:52.842202 DQM0 = 105, DQM1 = 96
5326 12:47:52.845586 DQ Delay:
5327 12:47:52.848851 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5328 12:47:52.851988 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =112
5329 12:47:52.855040 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =90
5330 12:47:52.858831 DQ12 =102, DQ13 =102, DQ14 =106, DQ15 =104
5331 12:47:52.859050
5332 12:47:52.859179
5333 12:47:52.865044 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
5334 12:47:52.868638 CH0 RK0: MR19=505, MR18=2E26
5335 12:47:52.875042 CH0_RK0: MR19=0x505, MR18=0x2E26, DQSOSC=407, MR23=63, INC=65, DEC=43
5336 12:47:52.875256
5337 12:47:52.878516 ----->DramcWriteLeveling(PI) begin...
5338 12:47:52.878674 ==
5339 12:47:52.881640 Dram Type= 6, Freq= 0, CH_0, rank 1
5340 12:47:52.885437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5341 12:47:52.885589 ==
5342 12:47:52.888452 Write leveling (Byte 0): 34 => 34
5343 12:47:52.891716 Write leveling (Byte 1): 32 => 32
5344 12:47:52.895260 DramcWriteLeveling(PI) end<-----
5345 12:47:52.895419
5346 12:47:52.895543 ==
5347 12:47:52.898727 Dram Type= 6, Freq= 0, CH_0, rank 1
5348 12:47:52.905088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 12:47:52.905308 ==
5350 12:47:52.905406 [Gating] SW mode calibration
5351 12:47:52.915042 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5352 12:47:52.918776 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5353 12:47:52.922211 0 14 0 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5354 12:47:52.928736 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 12:47:52.931573 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 12:47:52.935250 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 12:47:52.941918 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 12:47:52.945189 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 12:47:52.948423 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5360 12:47:52.955267 0 14 28 | B1->B0 | 2d2d 2e2e | 1 1 | (1 1) (1 0)
5361 12:47:52.958277 0 15 0 | B1->B0 | 2424 2929 | 0 0 | (0 0) (1 0)
5362 12:47:52.962221 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 12:47:52.968903 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 12:47:52.971734 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 12:47:52.975126 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 12:47:52.982073 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 12:47:52.985047 0 15 24 | B1->B0 | 2929 2626 | 0 0 | (0 0) (0 0)
5368 12:47:52.988381 0 15 28 | B1->B0 | 3c3c 3d3d | 0 0 | (0 0) (0 0)
5369 12:47:52.994826 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5370 12:47:52.998542 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 12:47:53.002179 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 12:47:53.005310 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 12:47:53.011833 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 12:47:53.015432 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 12:47:53.018827 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 12:47:53.025365 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5377 12:47:53.028587 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 12:47:53.031944 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 12:47:53.038240 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 12:47:53.041939 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 12:47:53.044958 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 12:47:53.051436 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 12:47:53.055149 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 12:47:53.058188 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 12:47:53.064931 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 12:47:53.068685 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 12:47:53.071603 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 12:47:53.078205 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 12:47:53.081620 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 12:47:53.085141 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 12:47:53.091795 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 12:47:53.095005 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5393 12:47:53.098352 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 12:47:53.101660 Total UI for P1: 0, mck2ui 16
5395 12:47:53.104866 best dqsien dly found for B0: ( 1, 2, 28)
5396 12:47:53.108164 Total UI for P1: 0, mck2ui 16
5397 12:47:53.111197 best dqsien dly found for B1: ( 1, 2, 28)
5398 12:47:53.114905 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5399 12:47:53.117783 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5400 12:47:53.117909
5401 12:47:53.121327 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5402 12:47:53.128384 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5403 12:47:53.128600 [Gating] SW calibration Done
5404 12:47:53.128709 ==
5405 12:47:53.131287 Dram Type= 6, Freq= 0, CH_0, rank 1
5406 12:47:53.138073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5407 12:47:53.138228 ==
5408 12:47:53.138299 RX Vref Scan: 0
5409 12:47:53.138362
5410 12:47:53.141131 RX Vref 0 -> 0, step: 1
5411 12:47:53.141233
5412 12:47:53.144392 RX Delay -80 -> 252, step: 8
5413 12:47:53.147875 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5414 12:47:53.151083 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5415 12:47:53.154866 iDelay=208, Bit 2, Center 107 (16 ~ 199) 184
5416 12:47:53.160809 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5417 12:47:53.164287 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5418 12:47:53.167718 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5419 12:47:53.170923 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5420 12:47:53.174649 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5421 12:47:53.177818 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5422 12:47:53.184314 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5423 12:47:53.187689 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5424 12:47:53.191191 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5425 12:47:53.194161 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5426 12:47:53.197599 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5427 12:47:53.204030 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5428 12:47:53.207277 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5429 12:47:53.207459 ==
5430 12:47:53.211119 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 12:47:53.213927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 12:47:53.214134 ==
5433 12:47:53.217118 DQS Delay:
5434 12:47:53.217348 DQS0 = 0, DQS1 = 0
5435 12:47:53.217492 DQM Delay:
5436 12:47:53.220581 DQM0 = 105, DQM1 = 95
5437 12:47:53.220789 DQ Delay:
5438 12:47:53.223943 DQ0 =107, DQ1 =107, DQ2 =107, DQ3 =99
5439 12:47:53.227265 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5440 12:47:53.230818 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5441 12:47:53.234462 DQ12 =103, DQ13 =99, DQ14 =103, DQ15 =103
5442 12:47:53.234678
5443 12:47:53.237054
5444 12:47:53.237263 ==
5445 12:47:53.240742 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 12:47:53.243871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 12:47:53.244096 ==
5448 12:47:53.244240
5449 12:47:53.244369
5450 12:47:53.247164 TX Vref Scan disable
5451 12:47:53.247376 == TX Byte 0 ==
5452 12:47:53.254037 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5453 12:47:53.257655 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5454 12:47:53.257883 == TX Byte 1 ==
5455 12:47:53.263667 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5456 12:47:53.267593 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5457 12:47:53.267827 ==
5458 12:47:53.270664 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 12:47:53.274157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 12:47:53.274384 ==
5461 12:47:53.274529
5462 12:47:53.274658
5463 12:47:53.277026 TX Vref Scan disable
5464 12:47:53.280479 == TX Byte 0 ==
5465 12:47:53.283831 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5466 12:47:53.287605 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5467 12:47:53.290811 == TX Byte 1 ==
5468 12:47:53.294415 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5469 12:47:53.297113 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5470 12:47:53.297320
5471 12:47:53.297461 [DATLAT]
5472 12:47:53.300572 Freq=933, CH0 RK1
5473 12:47:53.300791
5474 12:47:53.304002 DATLAT Default: 0xb
5475 12:47:53.304232 0, 0xFFFF, sum = 0
5476 12:47:53.307584 1, 0xFFFF, sum = 0
5477 12:47:53.307813 2, 0xFFFF, sum = 0
5478 12:47:53.310703 3, 0xFFFF, sum = 0
5479 12:47:53.310925 4, 0xFFFF, sum = 0
5480 12:47:53.314216 5, 0xFFFF, sum = 0
5481 12:47:53.314444 6, 0xFFFF, sum = 0
5482 12:47:53.317573 7, 0xFFFF, sum = 0
5483 12:47:53.317789 8, 0xFFFF, sum = 0
5484 12:47:53.320948 9, 0xFFFF, sum = 0
5485 12:47:53.321146 10, 0x0, sum = 1
5486 12:47:53.324293 11, 0x0, sum = 2
5487 12:47:53.324512 12, 0x0, sum = 3
5488 12:47:53.327296 13, 0x0, sum = 4
5489 12:47:53.327495 best_step = 11
5490 12:47:53.327637
5491 12:47:53.327760 ==
5492 12:47:53.330542 Dram Type= 6, Freq= 0, CH_0, rank 1
5493 12:47:53.333838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5494 12:47:53.334055 ==
5495 12:47:53.337234 RX Vref Scan: 0
5496 12:47:53.337446
5497 12:47:53.340728 RX Vref 0 -> 0, step: 1
5498 12:47:53.340937
5499 12:47:53.341076 RX Delay -45 -> 252, step: 4
5500 12:47:53.348384 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5501 12:47:53.351684 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5502 12:47:53.355373 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5503 12:47:53.358986 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5504 12:47:53.361671 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5505 12:47:53.368951 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5506 12:47:53.372115 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5507 12:47:53.375442 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5508 12:47:53.378434 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5509 12:47:53.381691 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5510 12:47:53.385300 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5511 12:47:53.391942 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5512 12:47:53.394878 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5513 12:47:53.398336 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5514 12:47:53.401753 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5515 12:47:53.408578 iDelay=199, Bit 15, Center 100 (15 ~ 186) 172
5516 12:47:53.408807 ==
5517 12:47:53.412083 Dram Type= 6, Freq= 0, CH_0, rank 1
5518 12:47:53.415278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5519 12:47:53.415495 ==
5520 12:47:53.415643 DQS Delay:
5521 12:47:53.418487 DQS0 = 0, DQS1 = 0
5522 12:47:53.418675 DQM Delay:
5523 12:47:53.421677 DQM0 = 104, DQM1 = 93
5524 12:47:53.421886 DQ Delay:
5525 12:47:53.425139 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5526 12:47:53.428566 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5527 12:47:53.431998 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =88
5528 12:47:53.435232 DQ12 =98, DQ13 =98, DQ14 =104, DQ15 =100
5529 12:47:53.435449
5530 12:47:53.435598
5531 12:47:53.445155 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5532 12:47:53.445388 CH0 RK1: MR19=505, MR18=2C04
5533 12:47:53.451918 CH0_RK1: MR19=0x505, MR18=0x2C04, DQSOSC=408, MR23=63, INC=65, DEC=43
5534 12:47:53.454830 [RxdqsGatingPostProcess] freq 933
5535 12:47:53.461571 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5536 12:47:53.464931 best DQS0 dly(2T, 0.5T) = (0, 10)
5537 12:47:53.468379 best DQS1 dly(2T, 0.5T) = (0, 10)
5538 12:47:53.471621 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5539 12:47:53.474527 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5540 12:47:53.477949 best DQS0 dly(2T, 0.5T) = (0, 10)
5541 12:47:53.478161 best DQS1 dly(2T, 0.5T) = (0, 10)
5542 12:47:53.481300 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5543 12:47:53.484696 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5544 12:47:53.488478 Pre-setting of DQS Precalculation
5545 12:47:53.494620 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5546 12:47:53.494778 ==
5547 12:47:53.498138 Dram Type= 6, Freq= 0, CH_1, rank 0
5548 12:47:53.501015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5549 12:47:53.501127 ==
5550 12:47:53.507981 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5551 12:47:53.514607 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5552 12:47:53.517699 [CA 0] Center 36 (6~67) winsize 62
5553 12:47:53.521347 [CA 1] Center 36 (6~67) winsize 62
5554 12:47:53.524764 [CA 2] Center 34 (4~65) winsize 62
5555 12:47:53.527853 [CA 3] Center 34 (4~65) winsize 62
5556 12:47:53.531141 [CA 4] Center 34 (4~64) winsize 61
5557 12:47:53.534272 [CA 5] Center 33 (3~64) winsize 62
5558 12:47:53.534483
5559 12:47:53.537775 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5560 12:47:53.537960
5561 12:47:53.541152 [CATrainingPosCal] consider 1 rank data
5562 12:47:53.544514 u2DelayCellTimex100 = 270/100 ps
5563 12:47:53.548096 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5564 12:47:53.551053 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5565 12:47:53.554752 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5566 12:47:53.557635 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5567 12:47:53.561316 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5568 12:47:53.564586 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5569 12:47:53.564776
5570 12:47:53.568151 CA PerBit enable=1, Macro0, CA PI delay=33
5571 12:47:53.571381
5572 12:47:53.571576 [CBTSetCACLKResult] CA Dly = 33
5573 12:47:53.574074 CS Dly: 7 (0~38)
5574 12:47:53.574226 ==
5575 12:47:53.577967 Dram Type= 6, Freq= 0, CH_1, rank 1
5576 12:47:53.580843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5577 12:47:53.581065 ==
5578 12:47:53.587570 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5579 12:47:53.594620 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5580 12:47:53.597577 [CA 0] Center 36 (6~67) winsize 62
5581 12:47:53.600956 [CA 1] Center 36 (6~67) winsize 62
5582 12:47:53.604418 [CA 2] Center 35 (4~66) winsize 63
5583 12:47:53.607868 [CA 3] Center 34 (4~65) winsize 62
5584 12:47:53.611342 [CA 4] Center 34 (4~65) winsize 62
5585 12:47:53.614595 [CA 5] Center 33 (3~64) winsize 62
5586 12:47:53.614807
5587 12:47:53.617565 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5588 12:47:53.617766
5589 12:47:53.621072 [CATrainingPosCal] consider 2 rank data
5590 12:47:53.624336 u2DelayCellTimex100 = 270/100 ps
5591 12:47:53.627711 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5592 12:47:53.630942 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5593 12:47:53.634196 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5594 12:47:53.637804 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5595 12:47:53.640820 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5596 12:47:53.644352 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5597 12:47:53.644530
5598 12:47:53.650751 CA PerBit enable=1, Macro0, CA PI delay=33
5599 12:47:53.650929
5600 12:47:53.651002 [CBTSetCACLKResult] CA Dly = 33
5601 12:47:53.654404 CS Dly: 7 (0~39)
5602 12:47:53.654540
5603 12:47:53.657488 ----->DramcWriteLeveling(PI) begin...
5604 12:47:53.657702 ==
5605 12:47:53.660879 Dram Type= 6, Freq= 0, CH_1, rank 0
5606 12:47:53.664582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5607 12:47:53.664803 ==
5608 12:47:53.667718 Write leveling (Byte 0): 24 => 24
5609 12:47:53.670824 Write leveling (Byte 1): 26 => 26
5610 12:47:53.674166 DramcWriteLeveling(PI) end<-----
5611 12:47:53.674346
5612 12:47:53.674446 ==
5613 12:47:53.677496 Dram Type= 6, Freq= 0, CH_1, rank 0
5614 12:47:53.680755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5615 12:47:53.680947 ==
5616 12:47:53.684097 [Gating] SW mode calibration
5617 12:47:53.690993 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5618 12:47:53.697674 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5619 12:47:53.700697 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 12:47:53.707569 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 12:47:53.710446 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 12:47:53.713961 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5623 12:47:53.720416 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 12:47:53.723867 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 12:47:53.727426 0 14 24 | B1->B0 | 3333 2e2e | 0 0 | (0 1) (0 1)
5626 12:47:53.734092 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (1 0)
5627 12:47:53.736966 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 12:47:53.740373 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 12:47:53.747493 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 12:47:53.750756 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 12:47:53.754454 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 12:47:53.760520 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 12:47:53.764131 0 15 24 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
5634 12:47:53.767512 0 15 28 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
5635 12:47:53.770443 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 12:47:53.777267 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 12:47:53.780784 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 12:47:53.784047 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 12:47:53.790588 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 12:47:53.794061 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 12:47:53.797545 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5642 12:47:53.804163 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5643 12:47:53.807508 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 12:47:53.810684 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 12:47:53.817637 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 12:47:53.820438 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 12:47:53.823655 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 12:47:53.830445 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 12:47:53.834007 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 12:47:53.837079 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 12:47:53.843931 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 12:47:53.847198 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 12:47:53.850448 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 12:47:53.857501 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 12:47:53.860444 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 12:47:53.863649 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 12:47:53.870735 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5658 12:47:53.873593 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 12:47:53.877335 Total UI for P1: 0, mck2ui 16
5660 12:47:53.880605 best dqsien dly found for B0: ( 1, 2, 24)
5661 12:47:53.883956 Total UI for P1: 0, mck2ui 16
5662 12:47:53.887331 best dqsien dly found for B1: ( 1, 2, 24)
5663 12:47:53.890558 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5664 12:47:53.893650 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5665 12:47:53.893826
5666 12:47:53.897089 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5667 12:47:53.900583 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5668 12:47:53.903415 [Gating] SW calibration Done
5669 12:47:53.903601 ==
5670 12:47:53.907214 Dram Type= 6, Freq= 0, CH_1, rank 0
5671 12:47:53.910239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5672 12:47:53.910389 ==
5673 12:47:53.913613 RX Vref Scan: 0
5674 12:47:53.913754
5675 12:47:53.916539 RX Vref 0 -> 0, step: 1
5676 12:47:53.916680
5677 12:47:53.916755 RX Delay -80 -> 252, step: 8
5678 12:47:53.923281 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5679 12:47:53.926988 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5680 12:47:53.929805 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5681 12:47:53.933653 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5682 12:47:53.936902 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5683 12:47:53.940011 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5684 12:47:53.946512 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5685 12:47:53.950239 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5686 12:47:53.953280 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5687 12:47:53.956771 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5688 12:47:53.960142 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5689 12:47:53.963191 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5690 12:47:53.970107 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5691 12:47:53.973306 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5692 12:47:53.977109 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5693 12:47:53.980159 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5694 12:47:53.980380 ==
5695 12:47:53.983806 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 12:47:53.990260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 12:47:53.990503 ==
5698 12:47:53.990651 DQS Delay:
5699 12:47:53.990773 DQS0 = 0, DQS1 = 0
5700 12:47:53.993783 DQM Delay:
5701 12:47:53.994011 DQM0 = 103, DQM1 = 98
5702 12:47:53.996662 DQ Delay:
5703 12:47:54.000189 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5704 12:47:54.003344 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5705 12:47:54.006652 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5706 12:47:54.010071 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5707 12:47:54.010310
5708 12:47:54.010457
5709 12:47:54.010588 ==
5710 12:47:54.013496 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 12:47:54.016856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 12:47:54.017075 ==
5713 12:47:54.017216
5714 12:47:54.017341
5715 12:47:54.019827 TX Vref Scan disable
5716 12:47:54.023336 == TX Byte 0 ==
5717 12:47:54.026731 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5718 12:47:54.030176 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5719 12:47:54.033868 == TX Byte 1 ==
5720 12:47:54.036475 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5721 12:47:54.040080 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5722 12:47:54.040276 ==
5723 12:47:54.043772 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 12:47:54.046758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 12:47:54.050038 ==
5726 12:47:54.050220
5727 12:47:54.050325
5728 12:47:54.050415 TX Vref Scan disable
5729 12:47:54.053339 == TX Byte 0 ==
5730 12:47:54.056599 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5731 12:47:54.063787 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5732 12:47:54.064088 == TX Byte 1 ==
5733 12:47:54.066628 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5734 12:47:54.073464 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5735 12:47:54.073651
5736 12:47:54.073754 [DATLAT]
5737 12:47:54.073846 Freq=933, CH1 RK0
5738 12:47:54.073935
5739 12:47:54.076797 DATLAT Default: 0xd
5740 12:47:54.076968 0, 0xFFFF, sum = 0
5741 12:47:54.080302 1, 0xFFFF, sum = 0
5742 12:47:54.080556 2, 0xFFFF, sum = 0
5743 12:47:54.083449 3, 0xFFFF, sum = 0
5744 12:47:54.083702 4, 0xFFFF, sum = 0
5745 12:47:54.086654 5, 0xFFFF, sum = 0
5746 12:47:54.090024 6, 0xFFFF, sum = 0
5747 12:47:54.090201 7, 0xFFFF, sum = 0
5748 12:47:54.093256 8, 0xFFFF, sum = 0
5749 12:47:54.093427 9, 0xFFFF, sum = 0
5750 12:47:54.097064 10, 0x0, sum = 1
5751 12:47:54.097251 11, 0x0, sum = 2
5752 12:47:54.097352 12, 0x0, sum = 3
5753 12:47:54.100019 13, 0x0, sum = 4
5754 12:47:54.100184 best_step = 11
5755 12:47:54.100283
5756 12:47:54.103248 ==
5757 12:47:54.103414 Dram Type= 6, Freq= 0, CH_1, rank 0
5758 12:47:54.109812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 12:47:54.110062 ==
5760 12:47:54.110206 RX Vref Scan: 1
5761 12:47:54.110344
5762 12:47:54.113233 RX Vref 0 -> 0, step: 1
5763 12:47:54.113451
5764 12:47:54.116648 RX Delay -45 -> 252, step: 4
5765 12:47:54.116839
5766 12:47:54.119933 Set Vref, RX VrefLevel [Byte0]: 51
5767 12:47:54.122925 [Byte1]: 48
5768 12:47:54.123168
5769 12:47:54.126477 Final RX Vref Byte 0 = 51 to rank0
5770 12:47:54.130032 Final RX Vref Byte 1 = 48 to rank0
5771 12:47:54.133156 Final RX Vref Byte 0 = 51 to rank1
5772 12:47:54.136348 Final RX Vref Byte 1 = 48 to rank1==
5773 12:47:54.139692 Dram Type= 6, Freq= 0, CH_1, rank 0
5774 12:47:54.143113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5775 12:47:54.143267 ==
5776 12:47:54.146529 DQS Delay:
5777 12:47:54.146703 DQS0 = 0, DQS1 = 0
5778 12:47:54.149825 DQM Delay:
5779 12:47:54.150013 DQM0 = 103, DQM1 = 98
5780 12:47:54.150117 DQ Delay:
5781 12:47:54.153218 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5782 12:47:54.156683 DQ4 =104, DQ5 =114, DQ6 =112, DQ7 =102
5783 12:47:54.159599 DQ8 =88, DQ9 =88, DQ10 =100, DQ11 =96
5784 12:47:54.166737 DQ12 =102, DQ13 =102, DQ14 =104, DQ15 =106
5785 12:47:54.166921
5786 12:47:54.167027
5787 12:47:54.173142 [DQSOSCAuto] RK0, (LSB)MR18= 0x172e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5788 12:47:54.176380 CH1 RK0: MR19=505, MR18=172E
5789 12:47:54.182869 CH1_RK0: MR19=0x505, MR18=0x172E, DQSOSC=407, MR23=63, INC=65, DEC=43
5790 12:47:54.183067
5791 12:47:54.186372 ----->DramcWriteLeveling(PI) begin...
5792 12:47:54.186561 ==
5793 12:47:54.189659 Dram Type= 6, Freq= 0, CH_1, rank 1
5794 12:47:54.192894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5795 12:47:54.193070 ==
5796 12:47:54.196191 Write leveling (Byte 0): 28 => 28
5797 12:47:54.199466 Write leveling (Byte 1): 29 => 29
5798 12:47:54.202821 DramcWriteLeveling(PI) end<-----
5799 12:47:54.203029
5800 12:47:54.203130 ==
5801 12:47:54.206133 Dram Type= 6, Freq= 0, CH_1, rank 1
5802 12:47:54.209801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 12:47:54.209958 ==
5804 12:47:54.213160 [Gating] SW mode calibration
5805 12:47:54.219569 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5806 12:47:54.226181 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5807 12:47:54.229744 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 12:47:54.236100 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 12:47:54.239585 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 12:47:54.242473 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 12:47:54.249445 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 12:47:54.252754 0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5813 12:47:54.255730 0 14 24 | B1->B0 | 2f2f 3333 | 0 0 | (0 1) (0 0)
5814 12:47:54.262489 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5815 12:47:54.266604 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 12:47:54.269497 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 12:47:54.272707 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 12:47:54.279367 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 12:47:54.282369 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 12:47:54.285840 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 12:47:54.292354 0 15 24 | B1->B0 | 3737 2b2b | 0 0 | (1 1) (0 0)
5822 12:47:54.295645 0 15 28 | B1->B0 | 4646 3b3b | 0 0 | (0 0) (0 0)
5823 12:47:54.299017 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 12:47:54.305901 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 12:47:54.309148 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 12:47:54.312074 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 12:47:54.318838 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 12:47:54.322596 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 12:47:54.325693 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5830 12:47:54.332118 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5831 12:47:54.335848 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 12:47:54.339091 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 12:47:54.345717 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 12:47:54.349169 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 12:47:54.352081 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 12:47:54.358857 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 12:47:54.362315 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 12:47:54.365812 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 12:47:54.372134 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 12:47:54.375740 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 12:47:54.378824 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 12:47:54.382211 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 12:47:54.389036 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 12:47:54.392447 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 12:47:54.395713 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 12:47:54.402369 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5847 12:47:54.405928 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 12:47:54.408786 Total UI for P1: 0, mck2ui 16
5849 12:47:54.412087 best dqsien dly found for B0: ( 1, 2, 28)
5850 12:47:54.415317 Total UI for P1: 0, mck2ui 16
5851 12:47:54.418653 best dqsien dly found for B1: ( 1, 2, 28)
5852 12:47:54.422361 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5853 12:47:54.425395 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5854 12:47:54.425569
5855 12:47:54.428555 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5856 12:47:54.435291 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5857 12:47:54.435477 [Gating] SW calibration Done
5858 12:47:54.435589 ==
5859 12:47:54.438704 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 12:47:54.445601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 12:47:54.445768 ==
5862 12:47:54.445842 RX Vref Scan: 0
5863 12:47:54.445927
5864 12:47:54.448821 RX Vref 0 -> 0, step: 1
5865 12:47:54.448955
5866 12:47:54.451836 RX Delay -80 -> 252, step: 8
5867 12:47:54.455194 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5868 12:47:54.458645 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5869 12:47:54.461825 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5870 12:47:54.465366 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5871 12:47:54.471690 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5872 12:47:54.475299 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5873 12:47:54.478634 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5874 12:47:54.481871 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5875 12:47:54.485067 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5876 12:47:54.488458 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5877 12:47:54.492166 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5878 12:47:54.498405 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5879 12:47:54.501831 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5880 12:47:54.505185 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5881 12:47:54.508287 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5882 12:47:54.515197 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5883 12:47:54.515391 ==
5884 12:47:54.518195 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 12:47:54.522000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 12:47:54.522154 ==
5887 12:47:54.522234 DQS Delay:
5888 12:47:54.524815 DQS0 = 0, DQS1 = 0
5889 12:47:54.524953 DQM Delay:
5890 12:47:54.528516 DQM0 = 102, DQM1 = 98
5891 12:47:54.528697 DQ Delay:
5892 12:47:54.531683 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =99
5893 12:47:54.534668 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5894 12:47:54.537957 DQ8 =91, DQ9 =91, DQ10 =99, DQ11 =91
5895 12:47:54.541560 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107
5896 12:47:54.541768
5897 12:47:54.541879
5898 12:47:54.541973 ==
5899 12:47:54.544776 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 12:47:54.547945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 12:47:54.551591 ==
5902 12:47:54.551779
5903 12:47:54.551885
5904 12:47:54.551986 TX Vref Scan disable
5905 12:47:54.555134 == TX Byte 0 ==
5906 12:47:54.558054 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5907 12:47:54.561389 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5908 12:47:54.564728 == TX Byte 1 ==
5909 12:47:54.568050 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5910 12:47:54.571715 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5911 12:47:54.574698 ==
5912 12:47:54.577932 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 12:47:54.581412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 12:47:54.581583 ==
5915 12:47:54.581700
5916 12:47:54.581794
5917 12:47:54.584813 TX Vref Scan disable
5918 12:47:54.584970 == TX Byte 0 ==
5919 12:47:54.591239 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5920 12:47:54.594802 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5921 12:47:54.594959 == TX Byte 1 ==
5922 12:47:54.601205 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5923 12:47:54.604637 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5924 12:47:54.604820
5925 12:47:54.604922 [DATLAT]
5926 12:47:54.608217 Freq=933, CH1 RK1
5927 12:47:54.608361
5928 12:47:54.608432 DATLAT Default: 0xb
5929 12:47:54.611603 0, 0xFFFF, sum = 0
5930 12:47:54.611767 1, 0xFFFF, sum = 0
5931 12:47:54.614522 2, 0xFFFF, sum = 0
5932 12:47:54.614667 3, 0xFFFF, sum = 0
5933 12:47:54.617913 4, 0xFFFF, sum = 0
5934 12:47:54.618129 5, 0xFFFF, sum = 0
5935 12:47:54.621430 6, 0xFFFF, sum = 0
5936 12:47:54.621567 7, 0xFFFF, sum = 0
5937 12:47:54.624703 8, 0xFFFF, sum = 0
5938 12:47:54.624848 9, 0xFFFF, sum = 0
5939 12:47:54.628024 10, 0x0, sum = 1
5940 12:47:54.628194 11, 0x0, sum = 2
5941 12:47:54.631658 12, 0x0, sum = 3
5942 12:47:54.631913 13, 0x0, sum = 4
5943 12:47:54.634865 best_step = 11
5944 12:47:54.635076
5945 12:47:54.635233 ==
5946 12:47:54.637777 Dram Type= 6, Freq= 0, CH_1, rank 1
5947 12:47:54.641164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5948 12:47:54.641323 ==
5949 12:47:54.644666 RX Vref Scan: 0
5950 12:47:54.644809
5951 12:47:54.644879 RX Vref 0 -> 0, step: 1
5952 12:47:54.644965
5953 12:47:54.647860 RX Delay -45 -> 252, step: 4
5954 12:47:54.654789 iDelay=199, Bit 0, Center 108 (27 ~ 190) 164
5955 12:47:54.658299 iDelay=199, Bit 1, Center 100 (19 ~ 182) 164
5956 12:47:54.661614 iDelay=199, Bit 2, Center 94 (11 ~ 178) 168
5957 12:47:54.664685 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5958 12:47:54.668078 iDelay=199, Bit 4, Center 100 (19 ~ 182) 164
5959 12:47:54.675056 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5960 12:47:54.678039 iDelay=199, Bit 6, Center 114 (31 ~ 198) 168
5961 12:47:54.681579 iDelay=199, Bit 7, Center 102 (19 ~ 186) 168
5962 12:47:54.684700 iDelay=199, Bit 8, Center 86 (-1 ~ 174) 176
5963 12:47:54.688222 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5964 12:47:54.695142 iDelay=199, Bit 10, Center 102 (19 ~ 186) 168
5965 12:47:54.698124 iDelay=199, Bit 11, Center 94 (11 ~ 178) 168
5966 12:47:54.701436 iDelay=199, Bit 12, Center 110 (23 ~ 198) 176
5967 12:47:54.704993 iDelay=199, Bit 13, Center 104 (23 ~ 186) 164
5968 12:47:54.708275 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5969 12:47:54.714911 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5970 12:47:54.715158 ==
5971 12:47:54.718232 Dram Type= 6, Freq= 0, CH_1, rank 1
5972 12:47:54.721288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5973 12:47:54.721516 ==
5974 12:47:54.721653 DQS Delay:
5975 12:47:54.725223 DQS0 = 0, DQS1 = 0
5976 12:47:54.725453 DQM Delay:
5977 12:47:54.728424 DQM0 = 104, DQM1 = 99
5978 12:47:54.728644 DQ Delay:
5979 12:47:54.731649 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5980 12:47:54.734893 DQ4 =100, DQ5 =116, DQ6 =114, DQ7 =102
5981 12:47:54.737963 DQ8 =86, DQ9 =88, DQ10 =102, DQ11 =94
5982 12:47:54.741284 DQ12 =110, DQ13 =104, DQ14 =104, DQ15 =108
5983 12:47:54.741447
5984 12:47:54.741547
5985 12:47:54.751184 [DQSOSCAuto] RK1, (LSB)MR18= 0x3104, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 406 ps
5986 12:47:54.754684 CH1 RK1: MR19=505, MR18=3104
5987 12:47:54.757824 CH1_RK1: MR19=0x505, MR18=0x3104, DQSOSC=406, MR23=63, INC=65, DEC=43
5988 12:47:54.761135 [RxdqsGatingPostProcess] freq 933
5989 12:47:54.767879 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5990 12:47:54.771182 best DQS0 dly(2T, 0.5T) = (0, 10)
5991 12:47:54.775155 best DQS1 dly(2T, 0.5T) = (0, 10)
5992 12:47:54.777822 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5993 12:47:54.781449 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5994 12:47:54.784633 best DQS0 dly(2T, 0.5T) = (0, 10)
5995 12:47:54.788125 best DQS1 dly(2T, 0.5T) = (0, 10)
5996 12:47:54.788262 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5997 12:47:54.791160 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5998 12:47:54.794570 Pre-setting of DQS Precalculation
5999 12:47:54.801700 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6000 12:47:54.808079 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6001 12:47:54.814655 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6002 12:47:54.814809
6003 12:47:54.814906
6004 12:47:54.818129 [Calibration Summary] 1866 Mbps
6005 12:47:54.821284 CH 0, Rank 0
6006 12:47:54.821443 SW Impedance : PASS
6007 12:47:54.824456 DUTY Scan : NO K
6008 12:47:54.827998 ZQ Calibration : PASS
6009 12:47:54.828176 Jitter Meter : NO K
6010 12:47:54.831083 CBT Training : PASS
6011 12:47:54.831311 Write leveling : PASS
6012 12:47:54.834843 RX DQS gating : PASS
6013 12:47:54.837803 RX DQ/DQS(RDDQC) : PASS
6014 12:47:54.837927 TX DQ/DQS : PASS
6015 12:47:54.840988 RX DATLAT : PASS
6016 12:47:54.844518 RX DQ/DQS(Engine): PASS
6017 12:47:54.844667 TX OE : NO K
6018 12:47:54.847731 All Pass.
6019 12:47:54.847862
6020 12:47:54.847932 CH 0, Rank 1
6021 12:47:54.851233 SW Impedance : PASS
6022 12:47:54.851422 DUTY Scan : NO K
6023 12:47:54.854384 ZQ Calibration : PASS
6024 12:47:54.857785 Jitter Meter : NO K
6025 12:47:54.857995 CBT Training : PASS
6026 12:47:54.861173 Write leveling : PASS
6027 12:47:54.864473 RX DQS gating : PASS
6028 12:47:54.864681 RX DQ/DQS(RDDQC) : PASS
6029 12:47:54.867834 TX DQ/DQS : PASS
6030 12:47:54.871044 RX DATLAT : PASS
6031 12:47:54.871192 RX DQ/DQS(Engine): PASS
6032 12:47:54.874470 TX OE : NO K
6033 12:47:54.874611 All Pass.
6034 12:47:54.874712
6035 12:47:54.874783 CH 1, Rank 0
6036 12:47:54.877889 SW Impedance : PASS
6037 12:47:54.881046 DUTY Scan : NO K
6038 12:47:54.881262 ZQ Calibration : PASS
6039 12:47:54.884399 Jitter Meter : NO K
6040 12:47:54.887839 CBT Training : PASS
6041 12:47:54.888023 Write leveling : PASS
6042 12:47:54.891056 RX DQS gating : PASS
6043 12:47:54.894465 RX DQ/DQS(RDDQC) : PASS
6044 12:47:54.894593 TX DQ/DQS : PASS
6045 12:47:54.897939 RX DATLAT : PASS
6046 12:47:54.900841 RX DQ/DQS(Engine): PASS
6047 12:47:54.900974 TX OE : NO K
6048 12:47:54.904434 All Pass.
6049 12:47:54.904521
6050 12:47:54.904586 CH 1, Rank 1
6051 12:47:54.907863 SW Impedance : PASS
6052 12:47:54.907950 DUTY Scan : NO K
6053 12:47:54.911221 ZQ Calibration : PASS
6054 12:47:54.914337 Jitter Meter : NO K
6055 12:47:54.914464 CBT Training : PASS
6056 12:47:54.917505 Write leveling : PASS
6057 12:47:54.920917 RX DQS gating : PASS
6058 12:47:54.921046 RX DQ/DQS(RDDQC) : PASS
6059 12:47:54.924416 TX DQ/DQS : PASS
6060 12:47:54.924537 RX DATLAT : PASS
6061 12:47:54.927867 RX DQ/DQS(Engine): PASS
6062 12:47:54.930905 TX OE : NO K
6063 12:47:54.931158 All Pass.
6064 12:47:54.931331
6065 12:47:54.934148 DramC Write-DBI off
6066 12:47:54.934343 PER_BANK_REFRESH: Hybrid Mode
6067 12:47:54.937701 TX_TRACKING: ON
6068 12:47:54.947779 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6069 12:47:54.950880 [FAST_K] Save calibration result to emmc
6070 12:47:54.954502 dramc_set_vcore_voltage set vcore to 650000
6071 12:47:54.954650 Read voltage for 400, 6
6072 12:47:54.957583 Vio18 = 0
6073 12:47:54.957669 Vcore = 650000
6074 12:47:54.957738 Vdram = 0
6075 12:47:54.961106 Vddq = 0
6076 12:47:54.961186 Vmddr = 0
6077 12:47:54.964512 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6078 12:47:54.970589 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6079 12:47:54.974082 MEM_TYPE=3, freq_sel=20
6080 12:47:54.977534 sv_algorithm_assistance_LP4_800
6081 12:47:54.981050 ============ PULL DRAM RESETB DOWN ============
6082 12:47:54.984182 ========== PULL DRAM RESETB DOWN end =========
6083 12:47:54.990947 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6084 12:47:54.994242 ===================================
6085 12:47:54.994398 LPDDR4 DRAM CONFIGURATION
6086 12:47:54.997165 ===================================
6087 12:47:55.000959 EX_ROW_EN[0] = 0x0
6088 12:47:55.001161 EX_ROW_EN[1] = 0x0
6089 12:47:55.003848 LP4Y_EN = 0x0
6090 12:47:55.004026 WORK_FSP = 0x0
6091 12:47:55.007307 WL = 0x2
6092 12:47:55.010567 RL = 0x2
6093 12:47:55.010796 BL = 0x2
6094 12:47:55.014162 RPST = 0x0
6095 12:47:55.014390 RD_PRE = 0x0
6096 12:47:55.017534 WR_PRE = 0x1
6097 12:47:55.017691 WR_PST = 0x0
6098 12:47:55.020821 DBI_WR = 0x0
6099 12:47:55.020957 DBI_RD = 0x0
6100 12:47:55.024301 OTF = 0x1
6101 12:47:55.027406 ===================================
6102 12:47:55.030825 ===================================
6103 12:47:55.030999 ANA top config
6104 12:47:55.033666 ===================================
6105 12:47:55.037045 DLL_ASYNC_EN = 0
6106 12:47:55.040198 ALL_SLAVE_EN = 1
6107 12:47:55.040383 NEW_RANK_MODE = 1
6108 12:47:55.044150 DLL_IDLE_MODE = 1
6109 12:47:55.047236 LP45_APHY_COMB_EN = 1
6110 12:47:55.050358 TX_ODT_DIS = 1
6111 12:47:55.053866 NEW_8X_MODE = 1
6112 12:47:55.053983 ===================================
6113 12:47:55.057300 ===================================
6114 12:47:55.060425 data_rate = 800
6115 12:47:55.063990 CKR = 1
6116 12:47:55.067318 DQ_P2S_RATIO = 4
6117 12:47:55.070253 ===================================
6118 12:47:55.073570 CA_P2S_RATIO = 4
6119 12:47:55.077106 DQ_CA_OPEN = 0
6120 12:47:55.077235 DQ_SEMI_OPEN = 1
6121 12:47:55.080540 CA_SEMI_OPEN = 1
6122 12:47:55.083742 CA_FULL_RATE = 0
6123 12:47:55.086966 DQ_CKDIV4_EN = 0
6124 12:47:55.090817 CA_CKDIV4_EN = 1
6125 12:47:55.093721 CA_PREDIV_EN = 0
6126 12:47:55.093845 PH8_DLY = 0
6127 12:47:55.096982 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6128 12:47:55.100702 DQ_AAMCK_DIV = 0
6129 12:47:55.103334 CA_AAMCK_DIV = 0
6130 12:47:55.107013 CA_ADMCK_DIV = 4
6131 12:47:55.110372 DQ_TRACK_CA_EN = 0
6132 12:47:55.113507 CA_PICK = 800
6133 12:47:55.113656 CA_MCKIO = 400
6134 12:47:55.116981 MCKIO_SEMI = 400
6135 12:47:55.120030 PLL_FREQ = 3016
6136 12:47:55.123260 DQ_UI_PI_RATIO = 32
6137 12:47:55.126846 CA_UI_PI_RATIO = 32
6138 12:47:55.130083 ===================================
6139 12:47:55.133172 ===================================
6140 12:47:55.136720 memory_type:LPDDR4
6141 12:47:55.136945 GP_NUM : 10
6142 12:47:55.139944 SRAM_EN : 1
6143 12:47:55.140163 MD32_EN : 0
6144 12:47:55.143269 ===================================
6145 12:47:55.146724 [ANA_INIT] >>>>>>>>>>>>>>
6146 12:47:55.149799 <<<<<< [CONFIGURE PHASE]: ANA_TX
6147 12:47:55.153675 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6148 12:47:55.156850 ===================================
6149 12:47:55.160142 data_rate = 800,PCW = 0X7400
6150 12:47:55.163564 ===================================
6151 12:47:55.166698 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6152 12:47:55.173270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6153 12:47:55.183106 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6154 12:47:55.186490 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6155 12:47:55.190167 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6156 12:47:55.193559 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6157 12:47:55.196440 [ANA_INIT] flow start
6158 12:47:55.200026 [ANA_INIT] PLL >>>>>>>>
6159 12:47:55.200185 [ANA_INIT] PLL <<<<<<<<
6160 12:47:55.203004 [ANA_INIT] MIDPI >>>>>>>>
6161 12:47:55.206445 [ANA_INIT] MIDPI <<<<<<<<
6162 12:47:55.209930 [ANA_INIT] DLL >>>>>>>>
6163 12:47:55.210134 [ANA_INIT] flow end
6164 12:47:55.213375 ============ LP4 DIFF to SE enter ============
6165 12:47:55.219658 ============ LP4 DIFF to SE exit ============
6166 12:47:55.219831 [ANA_INIT] <<<<<<<<<<<<<
6167 12:47:55.223589 [Flow] Enable top DCM control >>>>>
6168 12:47:55.226579 [Flow] Enable top DCM control <<<<<
6169 12:47:55.230071 Enable DLL master slave shuffle
6170 12:47:55.236426 ==============================================================
6171 12:47:55.236590 Gating Mode config
6172 12:47:55.243378 ==============================================================
6173 12:47:55.246727 Config description:
6174 12:47:55.252936 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6175 12:47:55.259486 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6176 12:47:55.266311 SELPH_MODE 0: By rank 1: By Phase
6177 12:47:55.273213 ==============================================================
6178 12:47:55.273389 GAT_TRACK_EN = 0
6179 12:47:55.276226 RX_GATING_MODE = 2
6180 12:47:55.279504 RX_GATING_TRACK_MODE = 2
6181 12:47:55.282982 SELPH_MODE = 1
6182 12:47:55.286226 PICG_EARLY_EN = 1
6183 12:47:55.289834 VALID_LAT_VALUE = 1
6184 12:47:55.296856 ==============================================================
6185 12:47:55.299725 Enter into Gating configuration >>>>
6186 12:47:55.303089 Exit from Gating configuration <<<<
6187 12:47:55.306672 Enter into DVFS_PRE_config >>>>>
6188 12:47:55.316440 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6189 12:47:55.320014 Exit from DVFS_PRE_config <<<<<
6190 12:47:55.322886 Enter into PICG configuration >>>>
6191 12:47:55.326107 Exit from PICG configuration <<<<
6192 12:47:55.329639 [RX_INPUT] configuration >>>>>
6193 12:47:55.329839 [RX_INPUT] configuration <<<<<
6194 12:47:55.336110 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6195 12:47:55.343007 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6196 12:47:55.345889 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6197 12:47:55.353081 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6198 12:47:55.359578 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6199 12:47:55.366468 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6200 12:47:55.369369 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6201 12:47:55.372796 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6202 12:47:55.379324 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6203 12:47:55.382978 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6204 12:47:55.386088 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6205 12:47:55.392529 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6206 12:47:55.395958 ===================================
6207 12:47:55.396065 LPDDR4 DRAM CONFIGURATION
6208 12:47:55.399103 ===================================
6209 12:47:55.402871 EX_ROW_EN[0] = 0x0
6210 12:47:55.403103 EX_ROW_EN[1] = 0x0
6211 12:47:55.406047 LP4Y_EN = 0x0
6212 12:47:55.406247 WORK_FSP = 0x0
6213 12:47:55.409400 WL = 0x2
6214 12:47:55.412725 RL = 0x2
6215 12:47:55.412954 BL = 0x2
6216 12:47:55.415683 RPST = 0x0
6217 12:47:55.415892 RD_PRE = 0x0
6218 12:47:55.419148 WR_PRE = 0x1
6219 12:47:55.419390 WR_PST = 0x0
6220 12:47:55.422846 DBI_WR = 0x0
6221 12:47:55.423058 DBI_RD = 0x0
6222 12:47:55.426042 OTF = 0x1
6223 12:47:55.429498 ===================================
6224 12:47:55.432664 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6225 12:47:55.435779 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6226 12:47:55.439546 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6227 12:47:55.442590 ===================================
6228 12:47:55.445849 LPDDR4 DRAM CONFIGURATION
6229 12:47:55.449416 ===================================
6230 12:47:55.452639 EX_ROW_EN[0] = 0x10
6231 12:47:55.452803 EX_ROW_EN[1] = 0x0
6232 12:47:55.456052 LP4Y_EN = 0x0
6233 12:47:55.456241 WORK_FSP = 0x0
6234 12:47:55.459769 WL = 0x2
6235 12:47:55.459924 RL = 0x2
6236 12:47:55.462493 BL = 0x2
6237 12:47:55.462634 RPST = 0x0
6238 12:47:55.465778 RD_PRE = 0x0
6239 12:47:55.465943 WR_PRE = 0x1
6240 12:47:55.469247 WR_PST = 0x0
6241 12:47:55.472984 DBI_WR = 0x0
6242 12:47:55.473168 DBI_RD = 0x0
6243 12:47:55.476335 OTF = 0x1
6244 12:47:55.479324 ===================================
6245 12:47:55.482426 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6246 12:47:55.487591 nWR fixed to 30
6247 12:47:55.490997 [ModeRegInit_LP4] CH0 RK0
6248 12:47:55.491221 [ModeRegInit_LP4] CH0 RK1
6249 12:47:55.494518 [ModeRegInit_LP4] CH1 RK0
6250 12:47:55.497408 [ModeRegInit_LP4] CH1 RK1
6251 12:47:55.497580 match AC timing 19
6252 12:47:55.504405 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6253 12:47:55.507765 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6254 12:47:55.510551 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6255 12:47:55.517411 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6256 12:47:55.520723 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6257 12:47:55.520932 ==
6258 12:47:55.524104 Dram Type= 6, Freq= 0, CH_0, rank 0
6259 12:47:55.527843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6260 12:47:55.528061 ==
6261 12:47:55.534100 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6262 12:47:55.540903 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6263 12:47:55.544598 [CA 0] Center 36 (8~64) winsize 57
6264 12:47:55.547806 [CA 1] Center 36 (8~64) winsize 57
6265 12:47:55.550760 [CA 2] Center 36 (8~64) winsize 57
6266 12:47:55.550905 [CA 3] Center 36 (8~64) winsize 57
6267 12:47:55.554266 [CA 4] Center 36 (8~64) winsize 57
6268 12:47:55.557557 [CA 5] Center 36 (8~64) winsize 57
6269 12:47:55.557778
6270 12:47:55.561029 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6271 12:47:55.563892
6272 12:47:55.567359 [CATrainingPosCal] consider 1 rank data
6273 12:47:55.570673 u2DelayCellTimex100 = 270/100 ps
6274 12:47:55.574042 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 12:47:55.577536 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 12:47:55.580556 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 12:47:55.583962 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 12:47:55.587331 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 12:47:55.590663 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 12:47:55.590827
6281 12:47:55.593803 CA PerBit enable=1, Macro0, CA PI delay=36
6282 12:47:55.593936
6283 12:47:55.597327 [CBTSetCACLKResult] CA Dly = 36
6284 12:47:55.600932 CS Dly: 1 (0~32)
6285 12:47:55.601075 ==
6286 12:47:55.603804 Dram Type= 6, Freq= 0, CH_0, rank 1
6287 12:47:55.607104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 12:47:55.607257 ==
6289 12:47:55.613869 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6290 12:47:55.617170 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6291 12:47:55.620628 [CA 0] Center 36 (8~64) winsize 57
6292 12:47:55.623956 [CA 1] Center 36 (8~64) winsize 57
6293 12:47:55.626764 [CA 2] Center 36 (8~64) winsize 57
6294 12:47:55.630129 [CA 3] Center 36 (8~64) winsize 57
6295 12:47:55.633647 [CA 4] Center 36 (8~64) winsize 57
6296 12:47:55.636765 [CA 5] Center 36 (8~64) winsize 57
6297 12:47:55.636937
6298 12:47:55.640119 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6299 12:47:55.640319
6300 12:47:55.643780 [CATrainingPosCal] consider 2 rank data
6301 12:47:55.646484 u2DelayCellTimex100 = 270/100 ps
6302 12:47:55.649969 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 12:47:55.656473 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 12:47:55.660059 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 12:47:55.663119 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 12:47:55.666412 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 12:47:55.669642 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 12:47:55.669772
6309 12:47:55.672995 CA PerBit enable=1, Macro0, CA PI delay=36
6310 12:47:55.673156
6311 12:47:55.676362 [CBTSetCACLKResult] CA Dly = 36
6312 12:47:55.676558 CS Dly: 1 (0~32)
6313 12:47:55.679859
6314 12:47:55.683237 ----->DramcWriteLeveling(PI) begin...
6315 12:47:55.683444 ==
6316 12:47:55.686120 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 12:47:55.689661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 12:47:55.689872 ==
6319 12:47:55.693134 Write leveling (Byte 0): 40 => 8
6320 12:47:55.696000 Write leveling (Byte 1): 40 => 8
6321 12:47:55.699383 DramcWriteLeveling(PI) end<-----
6322 12:47:55.699612
6323 12:47:55.699751 ==
6324 12:47:55.703027 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 12:47:55.706360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 12:47:55.706596 ==
6327 12:47:55.709848 [Gating] SW mode calibration
6328 12:47:55.716052 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6329 12:47:55.723122 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6330 12:47:55.726066 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6331 12:47:55.729256 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6332 12:47:55.735693 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6333 12:47:55.739005 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6334 12:47:55.742591 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6335 12:47:55.749546 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6336 12:47:55.752526 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6337 12:47:55.756325 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6338 12:47:55.762541 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6339 12:47:55.762773 Total UI for P1: 0, mck2ui 16
6340 12:47:55.766096 best dqsien dly found for B0: ( 0, 14, 24)
6341 12:47:55.769209 Total UI for P1: 0, mck2ui 16
6342 12:47:55.772664 best dqsien dly found for B1: ( 0, 14, 24)
6343 12:47:55.778974 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6344 12:47:55.782319 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6345 12:47:55.782505
6346 12:47:55.785916 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6347 12:47:55.789560 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6348 12:47:55.792523 [Gating] SW calibration Done
6349 12:47:55.792726 ==
6350 12:47:55.795924 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 12:47:55.799357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 12:47:55.799480 ==
6353 12:47:55.802355 RX Vref Scan: 0
6354 12:47:55.802468
6355 12:47:55.802537 RX Vref 0 -> 0, step: 1
6356 12:47:55.802599
6357 12:47:55.805685 RX Delay -410 -> 252, step: 16
6358 12:47:55.812067 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6359 12:47:55.815461 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6360 12:47:55.818938 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6361 12:47:55.822247 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6362 12:47:55.825640 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6363 12:47:55.832009 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6364 12:47:55.835368 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6365 12:47:55.838683 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6366 12:47:55.842149 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6367 12:47:55.848554 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6368 12:47:55.852037 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6369 12:47:55.855532 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6370 12:47:55.858503 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6371 12:47:55.865296 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6372 12:47:55.869352 iDelay=230, Bit 14, Center -3 (-234 ~ 229) 464
6373 12:47:55.872024 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6374 12:47:55.872149 ==
6375 12:47:55.875818 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 12:47:55.881809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 12:47:55.881994 ==
6378 12:47:55.882101 DQS Delay:
6379 12:47:55.885335 DQS0 = 27, DQS1 = 35
6380 12:47:55.885491 DQM Delay:
6381 12:47:55.885596 DQM0 = 12, DQM1 = 13
6382 12:47:55.888516 DQ Delay:
6383 12:47:55.892061 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6384 12:47:55.895682 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6385 12:47:55.895847 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6386 12:47:55.898408 DQ12 =16, DQ13 =16, DQ14 =32, DQ15 =16
6387 12:47:55.898553
6388 12:47:55.901915
6389 12:47:55.902068 ==
6390 12:47:55.905298 Dram Type= 6, Freq= 0, CH_0, rank 0
6391 12:47:55.908607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6392 12:47:55.908774 ==
6393 12:47:55.908888
6394 12:47:55.908988
6395 12:47:55.912095 TX Vref Scan disable
6396 12:47:55.912214 == TX Byte 0 ==
6397 12:47:55.915128 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6398 12:47:55.921848 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6399 12:47:55.922057 == TX Byte 1 ==
6400 12:47:55.925481 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6401 12:47:55.932043 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6402 12:47:55.932253 ==
6403 12:47:55.935273 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 12:47:55.938381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 12:47:55.938527 ==
6406 12:47:55.938634
6407 12:47:55.938726
6408 12:47:55.941782 TX Vref Scan disable
6409 12:47:55.941896 == TX Byte 0 ==
6410 12:47:55.945283 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6411 12:47:55.951931 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6412 12:47:55.952101 == TX Byte 1 ==
6413 12:47:55.955013 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6414 12:47:55.961996 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6415 12:47:55.962145
6416 12:47:55.962246 [DATLAT]
6417 12:47:55.962332 Freq=400, CH0 RK0
6418 12:47:55.962414
6419 12:47:55.964947 DATLAT Default: 0xf
6420 12:47:55.968294 0, 0xFFFF, sum = 0
6421 12:47:55.968391 1, 0xFFFF, sum = 0
6422 12:47:55.971834 2, 0xFFFF, sum = 0
6423 12:47:55.971988 3, 0xFFFF, sum = 0
6424 12:47:55.975308 4, 0xFFFF, sum = 0
6425 12:47:55.975432 5, 0xFFFF, sum = 0
6426 12:47:55.978187 6, 0xFFFF, sum = 0
6427 12:47:55.978312 7, 0xFFFF, sum = 0
6428 12:47:55.981499 8, 0xFFFF, sum = 0
6429 12:47:55.981678 9, 0xFFFF, sum = 0
6430 12:47:55.984907 10, 0xFFFF, sum = 0
6431 12:47:55.985093 11, 0xFFFF, sum = 0
6432 12:47:55.988869 12, 0xFFFF, sum = 0
6433 12:47:55.989067 13, 0x0, sum = 1
6434 12:47:55.991782 14, 0x0, sum = 2
6435 12:47:55.991939 15, 0x0, sum = 3
6436 12:47:55.994940 16, 0x0, sum = 4
6437 12:47:55.995066 best_step = 14
6438 12:47:55.995161
6439 12:47:55.995254 ==
6440 12:47:55.998379 Dram Type= 6, Freq= 0, CH_0, rank 0
6441 12:47:56.005112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 12:47:56.005226 ==
6443 12:47:56.005309 RX Vref Scan: 1
6444 12:47:56.005404
6445 12:47:56.008073 RX Vref 0 -> 0, step: 1
6446 12:47:56.008207
6447 12:47:56.011826 RX Delay -311 -> 252, step: 8
6448 12:47:56.012008
6449 12:47:56.014962 Set Vref, RX VrefLevel [Byte0]: 56
6450 12:47:56.018167 [Byte1]: 49
6451 12:47:56.018333
6452 12:47:56.021618 Final RX Vref Byte 0 = 56 to rank0
6453 12:47:56.024967 Final RX Vref Byte 1 = 49 to rank0
6454 12:47:56.028370 Final RX Vref Byte 0 = 56 to rank1
6455 12:47:56.031386 Final RX Vref Byte 1 = 49 to rank1==
6456 12:47:56.034776 Dram Type= 6, Freq= 0, CH_0, rank 0
6457 12:47:56.038243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 12:47:56.038390 ==
6459 12:47:56.041487 DQS Delay:
6460 12:47:56.041653 DQS0 = 28, DQS1 = 36
6461 12:47:56.045314 DQM Delay:
6462 12:47:56.045483 DQM0 = 10, DQM1 = 12
6463 12:47:56.045583 DQ Delay:
6464 12:47:56.048207 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6465 12:47:56.051805 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6466 12:47:56.054551 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6467 12:47:56.057870 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6468 12:47:56.058031
6469 12:47:56.058138
6470 12:47:56.067787 [DQSOSCAuto] RK0, (LSB)MR18= 0xc9b7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 384 ps
6471 12:47:56.071349 CH0 RK0: MR19=C0C, MR18=C9B7
6472 12:47:56.074746 CH0_RK0: MR19=0xC0C, MR18=0xC9B7, DQSOSC=384, MR23=63, INC=400, DEC=267
6473 12:47:56.078242 ==
6474 12:47:56.078452 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 12:47:56.084782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 12:47:56.085015 ==
6477 12:47:56.088368 [Gating] SW mode calibration
6478 12:47:56.095084 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6479 12:47:56.098295 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6480 12:47:56.104625 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6481 12:47:56.107952 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6482 12:47:56.111439 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6483 12:47:56.117987 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6484 12:47:56.120938 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6485 12:47:56.124381 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6486 12:47:56.131094 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6487 12:47:56.134640 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 12:47:56.137659 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6489 12:47:56.141420 Total UI for P1: 0, mck2ui 16
6490 12:47:56.144401 best dqsien dly found for B0: ( 0, 14, 24)
6491 12:47:56.147778 Total UI for P1: 0, mck2ui 16
6492 12:47:56.151141 best dqsien dly found for B1: ( 0, 14, 24)
6493 12:47:56.154690 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6494 12:47:56.157431 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6495 12:47:56.157567
6496 12:47:56.160921 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6497 12:47:56.167431 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6498 12:47:56.167621 [Gating] SW calibration Done
6499 12:47:56.171150 ==
6500 12:47:56.171285 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 12:47:56.177759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 12:47:56.177920 ==
6503 12:47:56.178028 RX Vref Scan: 0
6504 12:47:56.178130
6505 12:47:56.181133 RX Vref 0 -> 0, step: 1
6506 12:47:56.181251
6507 12:47:56.184515 RX Delay -410 -> 252, step: 16
6508 12:47:56.187553 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6509 12:47:56.190982 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6510 12:47:56.197201 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6511 12:47:56.200485 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6512 12:47:56.204273 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6513 12:47:56.207131 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6514 12:47:56.214066 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6515 12:47:56.217172 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6516 12:47:56.220615 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6517 12:47:56.223964 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6518 12:47:56.230642 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6519 12:47:56.233646 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6520 12:47:56.237089 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6521 12:47:56.240517 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6522 12:47:56.247199 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6523 12:47:56.250266 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6524 12:47:56.250437 ==
6525 12:47:56.253723 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 12:47:56.256895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 12:47:56.257027 ==
6528 12:47:56.260290 DQS Delay:
6529 12:47:56.260397 DQS0 = 27, DQS1 = 35
6530 12:47:56.263916 DQM Delay:
6531 12:47:56.264011 DQM0 = 12, DQM1 = 12
6532 12:47:56.267163 DQ Delay:
6533 12:47:56.267275 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6534 12:47:56.270031 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6535 12:47:56.273353 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6536 12:47:56.276960 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6537 12:47:56.277092
6538 12:47:56.277190
6539 12:47:56.277281 ==
6540 12:47:56.280290 Dram Type= 6, Freq= 0, CH_0, rank 1
6541 12:47:56.286548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6542 12:47:56.286719 ==
6543 12:47:56.286825
6544 12:47:56.286917
6545 12:47:56.287006 TX Vref Scan disable
6546 12:47:56.289976 == TX Byte 0 ==
6547 12:47:56.293400 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6548 12:47:56.296922 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6549 12:47:56.299818 == TX Byte 1 ==
6550 12:47:56.303287 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6551 12:47:56.306579 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6552 12:47:56.306691 ==
6553 12:47:56.310037 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 12:47:56.316642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 12:47:56.316833 ==
6556 12:47:56.316962
6557 12:47:56.317080
6558 12:47:56.319945 TX Vref Scan disable
6559 12:47:56.320097 == TX Byte 0 ==
6560 12:47:56.323486 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6561 12:47:56.326314 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6562 12:47:56.329834 == TX Byte 1 ==
6563 12:47:56.333258 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6564 12:47:56.336713 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6565 12:47:56.336818
6566 12:47:56.339442 [DATLAT]
6567 12:47:56.339558 Freq=400, CH0 RK1
6568 12:47:56.339649
6569 12:47:56.343006 DATLAT Default: 0xe
6570 12:47:56.343113 0, 0xFFFF, sum = 0
6571 12:47:56.346515 1, 0xFFFF, sum = 0
6572 12:47:56.346621 2, 0xFFFF, sum = 0
6573 12:47:56.349581 3, 0xFFFF, sum = 0
6574 12:47:56.349688 4, 0xFFFF, sum = 0
6575 12:47:56.353154 5, 0xFFFF, sum = 0
6576 12:47:56.353275 6, 0xFFFF, sum = 0
6577 12:47:56.356472 7, 0xFFFF, sum = 0
6578 12:47:56.359595 8, 0xFFFF, sum = 0
6579 12:47:56.359779 9, 0xFFFF, sum = 0
6580 12:47:56.363052 10, 0xFFFF, sum = 0
6581 12:47:56.363215 11, 0xFFFF, sum = 0
6582 12:47:56.366837 12, 0xFFFF, sum = 0
6583 12:47:56.366979 13, 0x0, sum = 1
6584 12:47:56.369714 14, 0x0, sum = 2
6585 12:47:56.369844 15, 0x0, sum = 3
6586 12:47:56.373037 16, 0x0, sum = 4
6587 12:47:56.373191 best_step = 14
6588 12:47:56.373294
6589 12:47:56.373392 ==
6590 12:47:56.376427 Dram Type= 6, Freq= 0, CH_0, rank 1
6591 12:47:56.379847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 12:47:56.379952 ==
6593 12:47:56.383059 RX Vref Scan: 0
6594 12:47:56.383199
6595 12:47:56.385997 RX Vref 0 -> 0, step: 1
6596 12:47:56.386124
6597 12:47:56.386229 RX Delay -311 -> 252, step: 8
6598 12:47:56.394747 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6599 12:47:56.398010 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6600 12:47:56.401592 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6601 12:47:56.405076 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6602 12:47:56.411826 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6603 12:47:56.414969 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6604 12:47:56.417817 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6605 12:47:56.421279 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6606 12:47:56.427790 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6607 12:47:56.431424 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6608 12:47:56.434998 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6609 12:47:56.438396 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6610 12:47:56.444795 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6611 12:47:56.448219 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6612 12:47:56.451971 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6613 12:47:56.455111 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6614 12:47:56.457995 ==
6615 12:47:56.461435 Dram Type= 6, Freq= 0, CH_0, rank 1
6616 12:47:56.464574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 12:47:56.464662 ==
6618 12:47:56.464763 DQS Delay:
6619 12:47:56.468578 DQS0 = 24, DQS1 = 32
6620 12:47:56.468728 DQM Delay:
6621 12:47:56.471673 DQM0 = 8, DQM1 = 9
6622 12:47:56.471818 DQ Delay:
6623 12:47:56.475158 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6624 12:47:56.478185 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6625 12:47:56.478325 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6626 12:47:56.484861 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6627 12:47:56.484969
6628 12:47:56.485038
6629 12:47:56.491742 [DQSOSCAuto] RK1, (LSB)MR18= 0xbc5b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6630 12:47:56.494898 CH0 RK1: MR19=C0C, MR18=BC5B
6631 12:47:56.501132 CH0_RK1: MR19=0xC0C, MR18=0xBC5B, DQSOSC=386, MR23=63, INC=396, DEC=264
6632 12:47:56.504508 [RxdqsGatingPostProcess] freq 400
6633 12:47:56.507849 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6634 12:47:56.511432 best DQS0 dly(2T, 0.5T) = (0, 10)
6635 12:47:56.514835 best DQS1 dly(2T, 0.5T) = (0, 10)
6636 12:47:56.518327 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6637 12:47:56.521074 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6638 12:47:56.524617 best DQS0 dly(2T, 0.5T) = (0, 10)
6639 12:47:56.528045 best DQS1 dly(2T, 0.5T) = (0, 10)
6640 12:47:56.530948 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6641 12:47:56.534423 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6642 12:47:56.538165 Pre-setting of DQS Precalculation
6643 12:47:56.541331 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6644 12:47:56.541420 ==
6645 12:47:56.544710 Dram Type= 6, Freq= 0, CH_1, rank 0
6646 12:47:56.551169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 12:47:56.551350 ==
6648 12:47:56.554892 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6649 12:47:56.560973 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6650 12:47:56.564540 [CA 0] Center 36 (8~64) winsize 57
6651 12:47:56.567916 [CA 1] Center 36 (8~64) winsize 57
6652 12:47:56.571042 [CA 2] Center 36 (8~64) winsize 57
6653 12:47:56.574833 [CA 3] Center 36 (8~64) winsize 57
6654 12:47:56.577861 [CA 4] Center 36 (8~64) winsize 57
6655 12:47:56.581070 [CA 5] Center 36 (8~64) winsize 57
6656 12:47:56.581211
6657 12:47:56.584432 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6658 12:47:56.584572
6659 12:47:56.587471 [CATrainingPosCal] consider 1 rank data
6660 12:47:56.591402 u2DelayCellTimex100 = 270/100 ps
6661 12:47:56.595103 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 12:47:56.598024 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 12:47:56.601253 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 12:47:56.604229 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 12:47:56.607875 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 12:47:56.610961 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 12:47:56.611048
6668 12:47:56.617941 CA PerBit enable=1, Macro0, CA PI delay=36
6669 12:47:56.618103
6670 12:47:56.621297 [CBTSetCACLKResult] CA Dly = 36
6671 12:47:56.621407 CS Dly: 1 (0~32)
6672 12:47:56.621494 ==
6673 12:47:56.624598 Dram Type= 6, Freq= 0, CH_1, rank 1
6674 12:47:56.627920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 12:47:56.628011 ==
6676 12:47:56.634312 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6677 12:47:56.640992 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6678 12:47:56.644347 [CA 0] Center 36 (8~64) winsize 57
6679 12:47:56.647883 [CA 1] Center 36 (8~64) winsize 57
6680 12:47:56.650974 [CA 2] Center 36 (8~64) winsize 57
6681 12:47:56.654607 [CA 3] Center 36 (8~64) winsize 57
6682 12:47:56.657412 [CA 4] Center 36 (8~64) winsize 57
6683 12:47:56.657489 [CA 5] Center 36 (8~64) winsize 57
6684 12:47:56.657552
6685 12:47:56.664434 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6686 12:47:56.664595
6687 12:47:56.667687 [CATrainingPosCal] consider 2 rank data
6688 12:47:56.670801 u2DelayCellTimex100 = 270/100 ps
6689 12:47:56.673827 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 12:47:56.677735 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 12:47:56.680820 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 12:47:56.684015 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 12:47:56.687665 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 12:47:56.690451 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 12:47:56.690608
6696 12:47:56.693859 CA PerBit enable=1, Macro0, CA PI delay=36
6697 12:47:56.693950
6698 12:47:56.697426 [CBTSetCACLKResult] CA Dly = 36
6699 12:47:56.700606 CS Dly: 1 (0~32)
6700 12:47:56.700767
6701 12:47:56.704279 ----->DramcWriteLeveling(PI) begin...
6702 12:47:56.704446 ==
6703 12:47:56.707477 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 12:47:56.710882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 12:47:56.711031 ==
6706 12:47:56.713835 Write leveling (Byte 0): 40 => 8
6707 12:47:56.717252 Write leveling (Byte 1): 40 => 8
6708 12:47:56.721029 DramcWriteLeveling(PI) end<-----
6709 12:47:56.721131
6710 12:47:56.721200 ==
6711 12:47:56.723885 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 12:47:56.727666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 12:47:56.727768 ==
6714 12:47:56.730508 [Gating] SW mode calibration
6715 12:47:56.737223 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6716 12:47:56.744451 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6717 12:47:56.747356 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6718 12:47:56.750812 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6719 12:47:56.757389 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6720 12:47:56.760900 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6721 12:47:56.763734 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6722 12:47:56.770703 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6723 12:47:56.774111 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6724 12:47:56.777033 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6725 12:47:56.783727 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6726 12:47:56.783870 Total UI for P1: 0, mck2ui 16
6727 12:47:56.790462 best dqsien dly found for B0: ( 0, 14, 24)
6728 12:47:56.790630 Total UI for P1: 0, mck2ui 16
6729 12:47:56.797014 best dqsien dly found for B1: ( 0, 14, 24)
6730 12:47:56.800681 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6731 12:47:56.803710 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6732 12:47:56.803856
6733 12:47:56.806975 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6734 12:47:56.810523 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6735 12:47:56.813831 [Gating] SW calibration Done
6736 12:47:56.813962 ==
6737 12:47:56.816708 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 12:47:56.820211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 12:47:56.820308 ==
6740 12:47:56.823674 RX Vref Scan: 0
6741 12:47:56.823792
6742 12:47:56.823882 RX Vref 0 -> 0, step: 1
6743 12:47:56.823984
6744 12:47:56.827096 RX Delay -410 -> 252, step: 16
6745 12:47:56.833567 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6746 12:47:56.837085 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6747 12:47:56.840341 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6748 12:47:56.843935 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6749 12:47:56.850346 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6750 12:47:56.853674 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6751 12:47:56.857255 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6752 12:47:56.860501 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6753 12:47:56.863907 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6754 12:47:56.870162 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6755 12:47:56.873706 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6756 12:47:56.877167 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6757 12:47:56.883639 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6758 12:47:56.887000 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6759 12:47:56.890585 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6760 12:47:56.893947 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6761 12:47:56.894066 ==
6762 12:47:56.896950 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 12:47:56.904031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 12:47:56.904199 ==
6765 12:47:56.904300 DQS Delay:
6766 12:47:56.907333 DQS0 = 27, DQS1 = 35
6767 12:47:56.907465 DQM Delay:
6768 12:47:56.907584 DQM0 = 10, DQM1 = 12
6769 12:47:56.910427 DQ Delay:
6770 12:47:56.913757 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6771 12:47:56.913915 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6772 12:47:56.916963 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6773 12:47:56.920619 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =16
6774 12:47:56.920750
6775 12:47:56.923959
6776 12:47:56.924064 ==
6777 12:47:56.926884 Dram Type= 6, Freq= 0, CH_1, rank 0
6778 12:47:56.930218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6779 12:47:56.930338 ==
6780 12:47:56.930433
6781 12:47:56.930522
6782 12:47:56.933728 TX Vref Scan disable
6783 12:47:56.933829 == TX Byte 0 ==
6784 12:47:56.936972 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6785 12:47:56.943719 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6786 12:47:56.943898 == TX Byte 1 ==
6787 12:47:56.946716 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6788 12:47:56.953558 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6789 12:47:56.953717 ==
6790 12:47:56.957376 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 12:47:56.960558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 12:47:56.960671 ==
6793 12:47:56.960767
6794 12:47:56.960861
6795 12:47:56.963796 TX Vref Scan disable
6796 12:47:56.963940 == TX Byte 0 ==
6797 12:47:56.967082 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6798 12:47:56.973843 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6799 12:47:56.973963 == TX Byte 1 ==
6800 12:47:56.976928 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6801 12:47:56.983869 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6802 12:47:56.984008
6803 12:47:56.984104 [DATLAT]
6804 12:47:56.984192 Freq=400, CH1 RK0
6805 12:47:56.984255
6806 12:47:56.987178 DATLAT Default: 0xf
6807 12:47:56.987259 0, 0xFFFF, sum = 0
6808 12:47:56.990526 1, 0xFFFF, sum = 0
6809 12:47:56.993594 2, 0xFFFF, sum = 0
6810 12:47:56.993688 3, 0xFFFF, sum = 0
6811 12:47:56.997034 4, 0xFFFF, sum = 0
6812 12:47:56.997145 5, 0xFFFF, sum = 0
6813 12:47:57.000244 6, 0xFFFF, sum = 0
6814 12:47:57.000337 7, 0xFFFF, sum = 0
6815 12:47:57.003641 8, 0xFFFF, sum = 0
6816 12:47:57.003804 9, 0xFFFF, sum = 0
6817 12:47:57.007116 10, 0xFFFF, sum = 0
6818 12:47:57.007256 11, 0xFFFF, sum = 0
6819 12:47:57.010458 12, 0xFFFF, sum = 0
6820 12:47:57.010620 13, 0x0, sum = 1
6821 12:47:57.013368 14, 0x0, sum = 2
6822 12:47:57.013478 15, 0x0, sum = 3
6823 12:47:57.016921 16, 0x0, sum = 4
6824 12:47:57.017071 best_step = 14
6825 12:47:57.017202
6826 12:47:57.017345 ==
6827 12:47:57.020510 Dram Type= 6, Freq= 0, CH_1, rank 0
6828 12:47:57.023663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 12:47:57.026882 ==
6830 12:47:57.026997 RX Vref Scan: 1
6831 12:47:57.027093
6832 12:47:57.030003 RX Vref 0 -> 0, step: 1
6833 12:47:57.030104
6834 12:47:57.033511 RX Delay -311 -> 252, step: 8
6835 12:47:57.033657
6836 12:47:57.036979 Set Vref, RX VrefLevel [Byte0]: 51
6837 12:47:57.039916 [Byte1]: 48
6838 12:47:57.040056
6839 12:47:57.043442 Final RX Vref Byte 0 = 51 to rank0
6840 12:47:57.046533 Final RX Vref Byte 1 = 48 to rank0
6841 12:47:57.050109 Final RX Vref Byte 0 = 51 to rank1
6842 12:47:57.053596 Final RX Vref Byte 1 = 48 to rank1==
6843 12:47:57.056766 Dram Type= 6, Freq= 0, CH_1, rank 0
6844 12:47:57.060093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 12:47:57.060249 ==
6846 12:47:57.063151 DQS Delay:
6847 12:47:57.063293 DQS0 = 32, DQS1 = 32
6848 12:47:57.066521 DQM Delay:
6849 12:47:57.066636 DQM0 = 14, DQM1 = 10
6850 12:47:57.066730 DQ Delay:
6851 12:47:57.069896 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6852 12:47:57.073232 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =12
6853 12:47:57.076911 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6854 12:47:57.080102 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6855 12:47:57.080215
6856 12:47:57.080285
6857 12:47:57.090298 [DQSOSCAuto] RK0, (LSB)MR18= 0x93cb, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6858 12:47:57.090459 CH1 RK0: MR19=C0C, MR18=93CB
6859 12:47:57.096858 CH1_RK0: MR19=0xC0C, MR18=0x93CB, DQSOSC=384, MR23=63, INC=400, DEC=267
6860 12:47:57.097016 ==
6861 12:47:57.100405 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 12:47:57.107005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 12:47:57.107102 ==
6864 12:47:57.107169 [Gating] SW mode calibration
6865 12:47:57.117277 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6866 12:47:57.120277 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6867 12:47:57.126845 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6868 12:47:57.130087 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6869 12:47:57.133142 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6870 12:47:57.136618 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6871 12:47:57.143164 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6872 12:47:57.146527 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6873 12:47:57.150184 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6874 12:47:57.156660 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6875 12:47:57.159935 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6876 12:47:57.163209 Total UI for P1: 0, mck2ui 16
6877 12:47:57.166651 best dqsien dly found for B0: ( 0, 14, 24)
6878 12:47:57.169960 Total UI for P1: 0, mck2ui 16
6879 12:47:57.173425 best dqsien dly found for B1: ( 0, 14, 24)
6880 12:47:57.176476 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6881 12:47:57.179780 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6882 12:47:57.179914
6883 12:47:57.183021 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6884 12:47:57.186466 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6885 12:47:57.190017 [Gating] SW calibration Done
6886 12:47:57.190167 ==
6887 12:47:57.193088 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 12:47:57.199700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 12:47:57.199788 ==
6890 12:47:57.199855 RX Vref Scan: 0
6891 12:47:57.199917
6892 12:47:57.202882 RX Vref 0 -> 0, step: 1
6893 12:47:57.202962
6894 12:47:57.206418 RX Delay -410 -> 252, step: 16
6895 12:47:57.209641 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6896 12:47:57.213161 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6897 12:47:57.219432 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6898 12:47:57.223171 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6899 12:47:57.226429 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6900 12:47:57.229711 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6901 12:47:57.232716 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6902 12:47:57.239352 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6903 12:47:57.242962 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6904 12:47:57.246391 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6905 12:47:57.249315 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6906 12:47:57.256317 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6907 12:47:57.259719 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6908 12:47:57.263069 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6909 12:47:57.269344 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6910 12:47:57.272959 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6911 12:47:57.273118 ==
6912 12:47:57.276272 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 12:47:57.279199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 12:47:57.279354 ==
6915 12:47:57.282717 DQS Delay:
6916 12:47:57.282875 DQS0 = 35, DQS1 = 35
6917 12:47:57.283003 DQM Delay:
6918 12:47:57.286043 DQM0 = 19, DQM1 = 13
6919 12:47:57.286183 DQ Delay:
6920 12:47:57.289452 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6921 12:47:57.292908 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6922 12:47:57.296323 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6923 12:47:57.299402 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6924 12:47:57.299580
6925 12:47:57.299723
6926 12:47:57.299847 ==
6927 12:47:57.302566 Dram Type= 6, Freq= 0, CH_1, rank 1
6928 12:47:57.309482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6929 12:47:57.309689 ==
6930 12:47:57.309824
6931 12:47:57.309959
6932 12:47:57.310080 TX Vref Scan disable
6933 12:47:57.312838 == TX Byte 0 ==
6934 12:47:57.315857 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6935 12:47:57.319254 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6936 12:47:57.322869 == TX Byte 1 ==
6937 12:47:57.326017 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6938 12:47:57.329448 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6939 12:47:57.329544 ==
6940 12:47:57.332854 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 12:47:57.339473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 12:47:57.339607 ==
6943 12:47:57.339678
6944 12:47:57.339740
6945 12:47:57.339801 TX Vref Scan disable
6946 12:47:57.342531 == TX Byte 0 ==
6947 12:47:57.345877 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6948 12:47:57.349208 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6949 12:47:57.352505 == TX Byte 1 ==
6950 12:47:57.355468 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6951 12:47:57.359091 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6952 12:47:57.359240
6953 12:47:57.362351 [DATLAT]
6954 12:47:57.362506 Freq=400, CH1 RK1
6955 12:47:57.362637
6956 12:47:57.365839 DATLAT Default: 0xe
6957 12:47:57.365994 0, 0xFFFF, sum = 0
6958 12:47:57.369264 1, 0xFFFF, sum = 0
6959 12:47:57.369351 2, 0xFFFF, sum = 0
6960 12:47:57.372517 3, 0xFFFF, sum = 0
6961 12:47:57.372602 4, 0xFFFF, sum = 0
6962 12:47:57.376024 5, 0xFFFF, sum = 0
6963 12:47:57.376109 6, 0xFFFF, sum = 0
6964 12:47:57.379436 7, 0xFFFF, sum = 0
6965 12:47:57.379514 8, 0xFFFF, sum = 0
6966 12:47:57.382223 9, 0xFFFF, sum = 0
6967 12:47:57.382302 10, 0xFFFF, sum = 0
6968 12:47:57.385915 11, 0xFFFF, sum = 0
6969 12:47:57.385986 12, 0xFFFF, sum = 0
6970 12:47:57.389264 13, 0x0, sum = 1
6971 12:47:57.389349 14, 0x0, sum = 2
6972 12:47:57.392190 15, 0x0, sum = 3
6973 12:47:57.392261 16, 0x0, sum = 4
6974 12:47:57.395831 best_step = 14
6975 12:47:57.395901
6976 12:47:57.395962 ==
6977 12:47:57.399132 Dram Type= 6, Freq= 0, CH_1, rank 1
6978 12:47:57.401993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6979 12:47:57.402163 ==
6980 12:47:57.405849 RX Vref Scan: 0
6981 12:47:57.406035
6982 12:47:57.406163 RX Vref 0 -> 0, step: 1
6983 12:47:57.406292
6984 12:47:57.408943 RX Delay -311 -> 252, step: 8
6985 12:47:57.417115 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6986 12:47:57.420400 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6987 12:47:57.423554 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6988 12:47:57.427011 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6989 12:47:57.433544 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6990 12:47:57.437409 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6991 12:47:57.440393 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6992 12:47:57.443279 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6993 12:47:57.450112 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6994 12:47:57.453580 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6995 12:47:57.457163 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6996 12:47:57.460483 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6997 12:47:57.467082 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6998 12:47:57.470404 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6999 12:47:57.473832 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7000 12:47:57.476905 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7001 12:47:57.479955 ==
7002 12:47:57.483532 Dram Type= 6, Freq= 0, CH_1, rank 1
7003 12:47:57.487077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7004 12:47:57.487173 ==
7005 12:47:57.487246 DQS Delay:
7006 12:47:57.490025 DQS0 = 28, DQS1 = 32
7007 12:47:57.490176 DQM Delay:
7008 12:47:57.493561 DQM0 = 11, DQM1 = 12
7009 12:47:57.493715 DQ Delay:
7010 12:47:57.497030 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =4
7011 12:47:57.500422 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
7012 12:47:57.503357 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
7013 12:47:57.506570 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7014 12:47:57.506711
7015 12:47:57.506835
7016 12:47:57.513491 [DQSOSCAuto] RK1, (LSB)MR18= 0xc456, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
7017 12:47:57.516757 CH1 RK1: MR19=C0C, MR18=C456
7018 12:47:57.523825 CH1_RK1: MR19=0xC0C, MR18=0xC456, DQSOSC=385, MR23=63, INC=398, DEC=265
7019 12:47:57.526463 [RxdqsGatingPostProcess] freq 400
7020 12:47:57.530081 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7021 12:47:57.533693 best DQS0 dly(2T, 0.5T) = (0, 10)
7022 12:47:57.536887 best DQS1 dly(2T, 0.5T) = (0, 10)
7023 12:47:57.540182 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7024 12:47:57.543544 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7025 12:47:57.546695 best DQS0 dly(2T, 0.5T) = (0, 10)
7026 12:47:57.549800 best DQS1 dly(2T, 0.5T) = (0, 10)
7027 12:47:57.553004 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7028 12:47:57.556925 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7029 12:47:57.560210 Pre-setting of DQS Precalculation
7030 12:47:57.563513 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7031 12:47:57.573299 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7032 12:47:57.579935 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7033 12:47:57.580108
7034 12:47:57.580235
7035 12:47:57.583261 [Calibration Summary] 800 Mbps
7036 12:47:57.583374 CH 0, Rank 0
7037 12:47:57.586821 SW Impedance : PASS
7038 12:47:57.586919 DUTY Scan : NO K
7039 12:47:57.589929 ZQ Calibration : PASS
7040 12:47:57.593080 Jitter Meter : NO K
7041 12:47:57.593180 CBT Training : PASS
7042 12:47:57.596242 Write leveling : PASS
7043 12:47:57.599637 RX DQS gating : PASS
7044 12:47:57.599723 RX DQ/DQS(RDDQC) : PASS
7045 12:47:57.603345 TX DQ/DQS : PASS
7046 12:47:57.603426 RX DATLAT : PASS
7047 12:47:57.606559 RX DQ/DQS(Engine): PASS
7048 12:47:57.609494 TX OE : NO K
7049 12:47:57.609599 All Pass.
7050 12:47:57.609691
7051 12:47:57.609799 CH 0, Rank 1
7052 12:47:57.612913 SW Impedance : PASS
7053 12:47:57.616329 DUTY Scan : NO K
7054 12:47:57.616413 ZQ Calibration : PASS
7055 12:47:57.619563 Jitter Meter : NO K
7056 12:47:57.623158 CBT Training : PASS
7057 12:47:57.623246 Write leveling : NO K
7058 12:47:57.626528 RX DQS gating : PASS
7059 12:47:57.630118 RX DQ/DQS(RDDQC) : PASS
7060 12:47:57.630211 TX DQ/DQS : PASS
7061 12:47:57.633493 RX DATLAT : PASS
7062 12:47:57.636598 RX DQ/DQS(Engine): PASS
7063 12:47:57.636700 TX OE : NO K
7064 12:47:57.639607 All Pass.
7065 12:47:57.639718
7066 12:47:57.639822 CH 1, Rank 0
7067 12:47:57.643240 SW Impedance : PASS
7068 12:47:57.643355 DUTY Scan : NO K
7069 12:47:57.646731 ZQ Calibration : PASS
7070 12:47:57.649940 Jitter Meter : NO K
7071 12:47:57.650104 CBT Training : PASS
7072 12:47:57.652908 Write leveling : PASS
7073 12:47:57.653048 RX DQS gating : PASS
7074 12:47:57.656380 RX DQ/DQS(RDDQC) : PASS
7075 12:47:57.659978 TX DQ/DQS : PASS
7076 12:47:57.660122 RX DATLAT : PASS
7077 12:47:57.662877 RX DQ/DQS(Engine): PASS
7078 12:47:57.666314 TX OE : NO K
7079 12:47:57.666423 All Pass.
7080 12:47:57.666528
7081 12:47:57.666620 CH 1, Rank 1
7082 12:47:57.669767 SW Impedance : PASS
7083 12:47:57.673366 DUTY Scan : NO K
7084 12:47:57.673485 ZQ Calibration : PASS
7085 12:47:57.676026 Jitter Meter : NO K
7086 12:47:57.679650 CBT Training : PASS
7087 12:47:57.679763 Write leveling : NO K
7088 12:47:57.682969 RX DQS gating : PASS
7089 12:47:57.686007 RX DQ/DQS(RDDQC) : PASS
7090 12:47:57.686127 TX DQ/DQS : PASS
7091 12:47:57.689614 RX DATLAT : PASS
7092 12:47:57.692928 RX DQ/DQS(Engine): PASS
7093 12:47:57.693081 TX OE : NO K
7094 12:47:57.693208 All Pass.
7095 12:47:57.696632
7096 12:47:57.696760 DramC Write-DBI off
7097 12:47:57.699430 PER_BANK_REFRESH: Hybrid Mode
7098 12:47:57.699545 TX_TRACKING: ON
7099 12:47:57.709474 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7100 12:47:57.712922 [FAST_K] Save calibration result to emmc
7101 12:47:57.716147 dramc_set_vcore_voltage set vcore to 725000
7102 12:47:57.719599 Read voltage for 1600, 0
7103 12:47:57.719720 Vio18 = 0
7104 12:47:57.722960 Vcore = 725000
7105 12:47:57.723093 Vdram = 0
7106 12:47:57.723216 Vddq = 0
7107 12:47:57.723337 Vmddr = 0
7108 12:47:57.729587 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7109 12:47:57.736232 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7110 12:47:57.736411 MEM_TYPE=3, freq_sel=13
7111 12:47:57.739542 sv_algorithm_assistance_LP4_3733
7112 12:47:57.743138 ============ PULL DRAM RESETB DOWN ============
7113 12:47:57.749707 ========== PULL DRAM RESETB DOWN end =========
7114 12:47:57.752577 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7115 12:47:57.756214 ===================================
7116 12:47:57.759731 LPDDR4 DRAM CONFIGURATION
7117 12:47:57.762613 ===================================
7118 12:47:57.762734 EX_ROW_EN[0] = 0x0
7119 12:47:57.766238 EX_ROW_EN[1] = 0x0
7120 12:47:57.766355 LP4Y_EN = 0x0
7121 12:47:57.769495 WORK_FSP = 0x1
7122 12:47:57.769645 WL = 0x5
7123 12:47:57.772413 RL = 0x5
7124 12:47:57.775826 BL = 0x2
7125 12:47:57.775948 RPST = 0x0
7126 12:47:57.779117 RD_PRE = 0x0
7127 12:47:57.779237 WR_PRE = 0x1
7128 12:47:57.782167 WR_PST = 0x1
7129 12:47:57.782285 DBI_WR = 0x0
7130 12:47:57.785685 DBI_RD = 0x0
7131 12:47:57.785806 OTF = 0x1
7132 12:47:57.789013 ===================================
7133 12:47:57.792430 ===================================
7134 12:47:57.795628 ANA top config
7135 12:47:57.798936 ===================================
7136 12:47:57.799050 DLL_ASYNC_EN = 0
7137 12:47:57.802275 ALL_SLAVE_EN = 0
7138 12:47:57.805500 NEW_RANK_MODE = 1
7139 12:47:57.808747 DLL_IDLE_MODE = 1
7140 12:47:57.808851 LP45_APHY_COMB_EN = 1
7141 12:47:57.812145 TX_ODT_DIS = 0
7142 12:47:57.815606 NEW_8X_MODE = 1
7143 12:47:57.819182 ===================================
7144 12:47:57.822648 ===================================
7145 12:47:57.826077 data_rate = 3200
7146 12:47:57.828707 CKR = 1
7147 12:47:57.832124 DQ_P2S_RATIO = 8
7148 12:47:57.835220 ===================================
7149 12:47:57.835347 CA_P2S_RATIO = 8
7150 12:47:57.838451 DQ_CA_OPEN = 0
7151 12:47:57.842054 DQ_SEMI_OPEN = 0
7152 12:47:57.845557 CA_SEMI_OPEN = 0
7153 12:47:57.848825 CA_FULL_RATE = 0
7154 12:47:57.852007 DQ_CKDIV4_EN = 0
7155 12:47:57.852146 CA_CKDIV4_EN = 0
7156 12:47:57.855442 CA_PREDIV_EN = 0
7157 12:47:57.858536 PH8_DLY = 12
7158 12:47:57.861917 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7159 12:47:57.864928 DQ_AAMCK_DIV = 4
7160 12:47:57.868416 CA_AAMCK_DIV = 4
7161 12:47:57.868570 CA_ADMCK_DIV = 4
7162 12:47:57.871930 DQ_TRACK_CA_EN = 0
7163 12:47:57.874854 CA_PICK = 1600
7164 12:47:57.878149 CA_MCKIO = 1600
7165 12:47:57.881620 MCKIO_SEMI = 0
7166 12:47:57.885129 PLL_FREQ = 3068
7167 12:47:57.888187 DQ_UI_PI_RATIO = 32
7168 12:47:57.891560 CA_UI_PI_RATIO = 0
7169 12:47:57.894582 ===================================
7170 12:47:57.898352 ===================================
7171 12:47:57.898513 memory_type:LPDDR4
7172 12:47:57.901319 GP_NUM : 10
7173 12:47:57.904929 SRAM_EN : 1
7174 12:47:57.905088 MD32_EN : 0
7175 12:47:57.908163 ===================================
7176 12:47:57.911487 [ANA_INIT] >>>>>>>>>>>>>>
7177 12:47:57.914728 <<<<<< [CONFIGURE PHASE]: ANA_TX
7178 12:47:57.918020 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7179 12:47:57.921587 ===================================
7180 12:47:57.924595 data_rate = 3200,PCW = 0X7600
7181 12:47:57.928049 ===================================
7182 12:47:57.931301 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7183 12:47:57.935028 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7184 12:47:57.941248 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7185 12:47:57.944873 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7186 12:47:57.947909 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7187 12:47:57.951175 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7188 12:47:57.954325 [ANA_INIT] flow start
7189 12:47:57.958206 [ANA_INIT] PLL >>>>>>>>
7190 12:47:57.958339 [ANA_INIT] PLL <<<<<<<<
7191 12:47:57.961287 [ANA_INIT] MIDPI >>>>>>>>
7192 12:47:57.964595 [ANA_INIT] MIDPI <<<<<<<<
7193 12:47:57.964700 [ANA_INIT] DLL >>>>>>>>
7194 12:47:57.968233 [ANA_INIT] DLL <<<<<<<<
7195 12:47:57.970872 [ANA_INIT] flow end
7196 12:47:57.974406 ============ LP4 DIFF to SE enter ============
7197 12:47:57.977842 ============ LP4 DIFF to SE exit ============
7198 12:47:57.981236 [ANA_INIT] <<<<<<<<<<<<<
7199 12:47:57.984611 [Flow] Enable top DCM control >>>>>
7200 12:47:57.987704 [Flow] Enable top DCM control <<<<<
7201 12:47:57.991094 Enable DLL master slave shuffle
7202 12:47:57.994485 ==============================================================
7203 12:47:57.998072 Gating Mode config
7204 12:47:58.004232 ==============================================================
7205 12:47:58.004341 Config description:
7206 12:47:58.014136 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7207 12:47:58.021264 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7208 12:47:58.024227 SELPH_MODE 0: By rank 1: By Phase
7209 12:47:58.031226 ==============================================================
7210 12:47:58.034305 GAT_TRACK_EN = 1
7211 12:47:58.037875 RX_GATING_MODE = 2
7212 12:47:58.041113 RX_GATING_TRACK_MODE = 2
7213 12:47:58.044435 SELPH_MODE = 1
7214 12:47:58.047659 PICG_EARLY_EN = 1
7215 12:47:58.051171 VALID_LAT_VALUE = 1
7216 12:47:58.054618 ==============================================================
7217 12:47:58.057801 Enter into Gating configuration >>>>
7218 12:47:58.060822 Exit from Gating configuration <<<<
7219 12:47:58.064558 Enter into DVFS_PRE_config >>>>>
7220 12:47:58.077806 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7221 12:47:58.078062 Exit from DVFS_PRE_config <<<<<
7222 12:47:58.081238 Enter into PICG configuration >>>>
7223 12:47:58.083985 Exit from PICG configuration <<<<
7224 12:47:58.087397 [RX_INPUT] configuration >>>>>
7225 12:47:58.090883 [RX_INPUT] configuration <<<<<
7226 12:47:58.097300 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7227 12:47:58.100834 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7228 12:47:58.107732 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7229 12:47:58.114360 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7230 12:47:58.120922 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7231 12:47:58.127452 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7232 12:47:58.130918 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7233 12:47:58.134125 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7234 12:47:58.137526 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7235 12:47:58.144387 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7236 12:47:58.147319 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7237 12:47:58.150797 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7238 12:47:58.153903 ===================================
7239 12:47:58.157364 LPDDR4 DRAM CONFIGURATION
7240 12:47:58.160890 ===================================
7241 12:47:58.161030 EX_ROW_EN[0] = 0x0
7242 12:47:58.164083 EX_ROW_EN[1] = 0x0
7243 12:47:58.167180 LP4Y_EN = 0x0
7244 12:47:58.167323 WORK_FSP = 0x1
7245 12:47:58.170717 WL = 0x5
7246 12:47:58.170809 RL = 0x5
7247 12:47:58.173561 BL = 0x2
7248 12:47:58.173670 RPST = 0x0
7249 12:47:58.177141 RD_PRE = 0x0
7250 12:47:58.177246 WR_PRE = 0x1
7251 12:47:58.180520 WR_PST = 0x1
7252 12:47:58.180623 DBI_WR = 0x0
7253 12:47:58.183891 DBI_RD = 0x0
7254 12:47:58.184019 OTF = 0x1
7255 12:47:58.187317 ===================================
7256 12:47:58.190230 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7257 12:47:58.197206 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7258 12:47:58.200611 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7259 12:47:58.203657 ===================================
7260 12:47:58.207049 LPDDR4 DRAM CONFIGURATION
7261 12:47:58.210285 ===================================
7262 12:47:58.210408 EX_ROW_EN[0] = 0x10
7263 12:47:58.213869 EX_ROW_EN[1] = 0x0
7264 12:47:58.217093 LP4Y_EN = 0x0
7265 12:47:58.217186 WORK_FSP = 0x1
7266 12:47:58.220529 WL = 0x5
7267 12:47:58.220618 RL = 0x5
7268 12:47:58.223398 BL = 0x2
7269 12:47:58.223497 RPST = 0x0
7270 12:47:58.226829 RD_PRE = 0x0
7271 12:47:58.226921 WR_PRE = 0x1
7272 12:47:58.230289 WR_PST = 0x1
7273 12:47:58.230424 DBI_WR = 0x0
7274 12:47:58.233780 DBI_RD = 0x0
7275 12:47:58.233911 OTF = 0x1
7276 12:47:58.237402 ===================================
7277 12:47:58.243968 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7278 12:47:58.244125 ==
7279 12:47:58.247112 Dram Type= 6, Freq= 0, CH_0, rank 0
7280 12:47:58.250676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7281 12:47:58.250793 ==
7282 12:47:58.253988 [Duty_Offset_Calibration]
7283 12:47:58.256771 B0:2 B1:1 CA:1
7284 12:47:58.256933
7285 12:47:58.260113 [DutyScan_Calibration_Flow] k_type=0
7286 12:47:58.268889
7287 12:47:58.269000 ==CLK 0==
7288 12:47:58.272336 Final CLK duty delay cell = 0
7289 12:47:58.275348 [0] MAX Duty = 5156%(X100), DQS PI = 22
7290 12:47:58.278719 [0] MIN Duty = 4907%(X100), DQS PI = 0
7291 12:47:58.278806 [0] AVG Duty = 5031%(X100)
7292 12:47:58.282030
7293 12:47:58.285513 CH0 CLK Duty spec in!! Max-Min= 249%
7294 12:47:58.288443 [DutyScan_Calibration_Flow] ====Done====
7295 12:47:58.288584
7296 12:47:58.291830 [DutyScan_Calibration_Flow] k_type=1
7297 12:47:58.307681
7298 12:47:58.307830 ==DQS 0 ==
7299 12:47:58.311265 Final DQS duty delay cell = -4
7300 12:47:58.314390 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7301 12:47:58.317773 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7302 12:47:58.321250 [-4] AVG Duty = 4891%(X100)
7303 12:47:58.321336
7304 12:47:58.321401 ==DQS 1 ==
7305 12:47:58.324764 Final DQS duty delay cell = 0
7306 12:47:58.328155 [0] MAX Duty = 5187%(X100), DQS PI = 4
7307 12:47:58.331389 [0] MIN Duty = 5062%(X100), DQS PI = 32
7308 12:47:58.334683 [0] AVG Duty = 5124%(X100)
7309 12:47:58.334767
7310 12:47:58.338117 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7311 12:47:58.338201
7312 12:47:58.341170 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7313 12:47:58.344340 [DutyScan_Calibration_Flow] ====Done====
7314 12:47:58.344478
7315 12:47:58.347572 [DutyScan_Calibration_Flow] k_type=3
7316 12:47:58.364838
7317 12:47:58.364989 ==DQM 0 ==
7318 12:47:58.368013 Final DQM duty delay cell = 0
7319 12:47:58.371163 [0] MAX Duty = 5218%(X100), DQS PI = 34
7320 12:47:58.374486 [0] MIN Duty = 4876%(X100), DQS PI = 60
7321 12:47:58.377717 [0] AVG Duty = 5047%(X100)
7322 12:47:58.377815
7323 12:47:58.377902 ==DQM 1 ==
7324 12:47:58.380897 Final DQM duty delay cell = -4
7325 12:47:58.384526 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7326 12:47:58.387589 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7327 12:47:58.390865 [-4] AVG Duty = 4906%(X100)
7328 12:47:58.390968
7329 12:47:58.394331 CH0 DQM 0 Duty spec in!! Max-Min= 342%
7330 12:47:58.394422
7331 12:47:58.397562 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7332 12:47:58.401285 [DutyScan_Calibration_Flow] ====Done====
7333 12:47:58.401397
7334 12:47:58.404344 [DutyScan_Calibration_Flow] k_type=2
7335 12:47:58.422090
7336 12:47:58.422236 ==DQ 0 ==
7337 12:47:58.425680 Final DQ duty delay cell = 0
7338 12:47:58.429035 [0] MAX Duty = 5062%(X100), DQS PI = 26
7339 12:47:58.432104 [0] MIN Duty = 4907%(X100), DQS PI = 0
7340 12:47:58.432181 [0] AVG Duty = 4984%(X100)
7341 12:47:58.432270
7342 12:47:58.435662 ==DQ 1 ==
7343 12:47:58.438796 Final DQ duty delay cell = 0
7344 12:47:58.442243 [0] MAX Duty = 5156%(X100), DQS PI = 22
7345 12:47:58.445141 [0] MIN Duty = 4938%(X100), DQS PI = 34
7346 12:47:58.445294 [0] AVG Duty = 5047%(X100)
7347 12:47:58.445395
7348 12:47:58.448759 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7349 12:47:58.451963
7350 12:47:58.455613 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7351 12:47:58.458862 [DutyScan_Calibration_Flow] ====Done====
7352 12:47:58.458983 ==
7353 12:47:58.461896 Dram Type= 6, Freq= 0, CH_1, rank 0
7354 12:47:58.465445 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7355 12:47:58.465542 ==
7356 12:47:58.468705 [Duty_Offset_Calibration]
7357 12:47:58.468784 B0:1 B1:0 CA:0
7358 12:47:58.468846
7359 12:47:58.472103 [DutyScan_Calibration_Flow] k_type=0
7360 12:47:58.481530
7361 12:47:58.481690 ==CLK 0==
7362 12:47:58.484643 Final CLK duty delay cell = -4
7363 12:47:58.488239 [-4] MAX Duty = 4969%(X100), DQS PI = 30
7364 12:47:58.491634 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7365 12:47:58.494925 [-4] AVG Duty = 4906%(X100)
7366 12:47:58.495041
7367 12:47:58.498108 CH1 CLK Duty spec in!! Max-Min= 125%
7368 12:47:58.501259 [DutyScan_Calibration_Flow] ====Done====
7369 12:47:58.501348
7370 12:47:58.504122 [DutyScan_Calibration_Flow] k_type=1
7371 12:47:58.521571
7372 12:47:58.521727 ==DQS 0 ==
7373 12:47:58.524560 Final DQS duty delay cell = 0
7374 12:47:58.527761 [0] MAX Duty = 5094%(X100), DQS PI = 46
7375 12:47:58.531419 [0] MIN Duty = 4844%(X100), DQS PI = 14
7376 12:47:58.534665 [0] AVG Duty = 4969%(X100)
7377 12:47:58.534797
7378 12:47:58.534870 ==DQS 1 ==
7379 12:47:58.538186 Final DQS duty delay cell = 0
7380 12:47:58.541691 [0] MAX Duty = 5249%(X100), DQS PI = 48
7381 12:47:58.544333 [0] MIN Duty = 4938%(X100), DQS PI = 40
7382 12:47:58.547778 [0] AVG Duty = 5093%(X100)
7383 12:47:58.547862
7384 12:47:58.551052 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7385 12:47:58.551134
7386 12:47:58.554482 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7387 12:47:58.557812 [DutyScan_Calibration_Flow] ====Done====
7388 12:47:58.557964
7389 12:47:58.561391 [DutyScan_Calibration_Flow] k_type=3
7390 12:47:58.578491
7391 12:47:58.578720 ==DQM 0 ==
7392 12:47:58.581648 Final DQM duty delay cell = 0
7393 12:47:58.584840 [0] MAX Duty = 5187%(X100), DQS PI = 38
7394 12:47:58.588202 [0] MIN Duty = 5031%(X100), DQS PI = 16
7395 12:47:58.588353 [0] AVG Duty = 5109%(X100)
7396 12:47:58.591817
7397 12:47:58.591977 ==DQM 1 ==
7398 12:47:58.594956 Final DQM duty delay cell = 0
7399 12:47:58.598433 [0] MAX Duty = 5093%(X100), DQS PI = 8
7400 12:47:58.601628 [0] MIN Duty = 4907%(X100), DQS PI = 2
7401 12:47:58.601800 [0] AVG Duty = 5000%(X100)
7402 12:47:58.601938
7403 12:47:58.608211 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7404 12:47:58.608300
7405 12:47:58.611535 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7406 12:47:58.615006 [DutyScan_Calibration_Flow] ====Done====
7407 12:47:58.615158
7408 12:47:58.618272 [DutyScan_Calibration_Flow] k_type=2
7409 12:47:58.634232
7410 12:47:58.634382 ==DQ 0 ==
7411 12:47:58.637918 Final DQ duty delay cell = -4
7412 12:47:58.640814 [-4] MAX Duty = 5062%(X100), DQS PI = 26
7413 12:47:58.644210 [-4] MIN Duty = 4875%(X100), DQS PI = 14
7414 12:47:58.647594 [-4] AVG Duty = 4968%(X100)
7415 12:47:58.647758
7416 12:47:58.647888 ==DQ 1 ==
7417 12:47:58.651084 Final DQ duty delay cell = 0
7418 12:47:58.654701 [0] MAX Duty = 5093%(X100), DQS PI = 8
7419 12:47:58.657961 [0] MIN Duty = 4938%(X100), DQS PI = 0
7420 12:47:58.658148 [0] AVG Duty = 5015%(X100)
7421 12:47:58.658280
7422 12:47:58.664157 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7423 12:47:58.664347
7424 12:47:58.667646 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7425 12:47:58.670792 [DutyScan_Calibration_Flow] ====Done====
7426 12:47:58.674231 nWR fixed to 30
7427 12:47:58.674400 [ModeRegInit_LP4] CH0 RK0
7428 12:47:58.677543 [ModeRegInit_LP4] CH0 RK1
7429 12:47:58.680965 [ModeRegInit_LP4] CH1 RK0
7430 12:47:58.684433 [ModeRegInit_LP4] CH1 RK1
7431 12:47:58.684587 match AC timing 5
7432 12:47:58.691064 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7433 12:47:58.694202 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7434 12:47:58.697432 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7435 12:47:58.704202 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7436 12:47:58.707645 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7437 12:47:58.707785 [MiockJmeterHQA]
7438 12:47:58.707883
7439 12:47:58.710937 [DramcMiockJmeter] u1RxGatingPI = 0
7440 12:47:58.714111 0 : 4252, 4027
7441 12:47:58.714247 4 : 4252, 4027
7442 12:47:58.714340 8 : 4252, 4027
7443 12:47:58.717473 12 : 4252, 4027
7444 12:47:58.717589 16 : 4253, 4026
7445 12:47:58.720910 20 : 4252, 4027
7446 12:47:58.721038 24 : 4255, 4029
7447 12:47:58.724274 28 : 4363, 4137
7448 12:47:58.724368 32 : 4252, 4027
7449 12:47:58.727419 36 : 4252, 4027
7450 12:47:58.727577 40 : 4255, 4029
7451 12:47:58.727704 44 : 4255, 4029
7452 12:47:58.730936 48 : 4252, 4027
7453 12:47:58.731053 52 : 4366, 4140
7454 12:47:58.733888 56 : 4363, 4138
7455 12:47:58.734046 60 : 4252, 4026
7456 12:47:58.737571 64 : 4252, 4027
7457 12:47:58.737710 68 : 4252, 4027
7458 12:47:58.740980 72 : 4250, 4027
7459 12:47:58.741122 76 : 4252, 4029
7460 12:47:58.741251 80 : 4360, 4138
7461 12:47:58.744128 84 : 4249, 4027
7462 12:47:58.744241 88 : 4250, 92
7463 12:47:58.747452 92 : 4249, 0
7464 12:47:58.747585 96 : 4253, 0
7465 12:47:58.747685 100 : 4250, 0
7466 12:47:58.751149 104 : 4250, 0
7467 12:47:58.751268 108 : 4252, 0
7468 12:47:58.751366 112 : 4250, 0
7469 12:47:58.754261 116 : 4250, 0
7470 12:47:58.754424 120 : 4252, 0
7471 12:47:58.757199 124 : 4361, 0
7472 12:47:58.757359 128 : 4361, 0
7473 12:47:58.757501 132 : 4363, 0
7474 12:47:58.761092 136 : 4250, 0
7475 12:47:58.761219 140 : 4252, 0
7476 12:47:58.764021 144 : 4250, 0
7477 12:47:58.764144 148 : 4250, 0
7478 12:47:58.764243 152 : 4250, 0
7479 12:47:58.767608 156 : 4250, 0
7480 12:47:58.767741 160 : 4252, 0
7481 12:47:58.771084 164 : 4250, 0
7482 12:47:58.771177 168 : 4250, 0
7483 12:47:58.771246 172 : 4252, 0
7484 12:47:58.774196 176 : 4361, 0
7485 12:47:58.774315 180 : 4361, 0
7486 12:47:58.774412 184 : 4363, 0
7487 12:47:58.777814 188 : 4250, 0
7488 12:47:58.777929 192 : 4250, 0
7489 12:47:58.780991 196 : 4250, 0
7490 12:47:58.781080 200 : 4249, 0
7491 12:47:58.781148 204 : 4250, 1203
7492 12:47:58.784516 208 : 4250, 4009
7493 12:47:58.784615 212 : 4250, 4027
7494 12:47:58.787592 216 : 4250, 4026
7495 12:47:58.787681 220 : 4250, 4027
7496 12:47:58.791125 224 : 4361, 4138
7497 12:47:58.791241 228 : 4250, 4027
7498 12:47:58.793928 232 : 4252, 4029
7499 12:47:58.794049 236 : 4361, 4137
7500 12:47:58.797454 240 : 4250, 4027
7501 12:47:58.797568 244 : 4249, 4027
7502 12:47:58.800844 248 : 4360, 4138
7503 12:47:58.800995 252 : 4250, 4027
7504 12:47:58.804012 256 : 4250, 4026
7505 12:47:58.804163 260 : 4250, 4027
7506 12:47:58.804294 264 : 4252, 4029
7507 12:47:58.807288 268 : 4250, 4027
7508 12:47:58.807431 272 : 4250, 4027
7509 12:47:58.810706 276 : 4361, 4138
7510 12:47:58.810852 280 : 4250, 4027
7511 12:47:58.814057 284 : 4250, 4027
7512 12:47:58.814217 288 : 4361, 4137
7513 12:47:58.817604 292 : 4250, 4027
7514 12:47:58.817715 296 : 4249, 4027
7515 12:47:58.820922 300 : 4363, 4140
7516 12:47:58.821030 304 : 4250, 4027
7517 12:47:58.824651 308 : 4250, 3979
7518 12:47:58.824778 312 : 4249, 2021
7519 12:47:58.824874
7520 12:47:58.827347 MIOCK jitter meter ch=0
7521 12:47:58.827450
7522 12:47:58.830726 1T = (312-88) = 224 dly cells
7523 12:47:58.834061 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7524 12:47:58.834155 ==
7525 12:47:58.837217 Dram Type= 6, Freq= 0, CH_0, rank 0
7526 12:47:58.843984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 12:47:58.844133 ==
7528 12:47:58.846953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7529 12:47:58.854059 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7530 12:47:58.857713 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7531 12:47:58.864141 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7532 12:47:58.871795 [CA 0] Center 43 (12~74) winsize 63
7533 12:47:58.875311 [CA 1] Center 43 (13~74) winsize 62
7534 12:47:58.878406 [CA 2] Center 38 (9~68) winsize 60
7535 12:47:58.881762 [CA 3] Center 38 (8~68) winsize 61
7536 12:47:58.885012 [CA 4] Center 36 (7~66) winsize 60
7537 12:47:58.888170 [CA 5] Center 36 (7~65) winsize 59
7538 12:47:58.888312
7539 12:47:58.891593 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7540 12:47:58.891729
7541 12:47:58.894755 [CATrainingPosCal] consider 1 rank data
7542 12:47:58.898514 u2DelayCellTimex100 = 290/100 ps
7543 12:47:58.901885 CA0 delay=43 (12~74),Diff = 7 PI (23 cell)
7544 12:47:58.908383 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7545 12:47:58.911725 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7546 12:47:58.915135 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7547 12:47:58.918485 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7548 12:47:58.921284 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7549 12:47:58.921384
7550 12:47:58.925054 CA PerBit enable=1, Macro0, CA PI delay=36
7551 12:47:58.925156
7552 12:47:58.928101 [CBTSetCACLKResult] CA Dly = 36
7553 12:47:58.931537 CS Dly: 9 (0~40)
7554 12:47:58.935102 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7555 12:47:58.938242 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7556 12:47:58.938331 ==
7557 12:47:58.941520 Dram Type= 6, Freq= 0, CH_0, rank 1
7558 12:47:58.945037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7559 12:47:58.945147 ==
7560 12:47:58.951481 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7561 12:47:58.954980 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7562 12:47:58.961602 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7563 12:47:58.964550 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7564 12:47:58.975044 [CA 0] Center 42 (12~73) winsize 62
7565 12:47:58.978463 [CA 1] Center 42 (12~73) winsize 62
7566 12:47:58.981379 [CA 2] Center 37 (8~67) winsize 60
7567 12:47:58.985011 [CA 3] Center 37 (7~68) winsize 62
7568 12:47:58.988385 [CA 4] Center 35 (6~65) winsize 60
7569 12:47:58.991661 [CA 5] Center 35 (5~65) winsize 61
7570 12:47:58.991740
7571 12:47:58.994918 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7572 12:47:58.995034
7573 12:47:58.998268 [CATrainingPosCal] consider 2 rank data
7574 12:47:59.001573 u2DelayCellTimex100 = 290/100 ps
7575 12:47:59.005329 CA0 delay=42 (12~73),Diff = 6 PI (20 cell)
7576 12:47:59.011543 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7577 12:47:59.015073 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
7578 12:47:59.018072 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7579 12:47:59.021280 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7580 12:47:59.025052 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7581 12:47:59.025206
7582 12:47:59.028537 CA PerBit enable=1, Macro0, CA PI delay=36
7583 12:47:59.028670
7584 12:47:59.031850 [CBTSetCACLKResult] CA Dly = 36
7585 12:47:59.034722 CS Dly: 10 (0~42)
7586 12:47:59.037981 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7587 12:47:59.041385 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7588 12:47:59.041551
7589 12:47:59.045161 ----->DramcWriteLeveling(PI) begin...
7590 12:47:59.045308 ==
7591 12:47:59.048094 Dram Type= 6, Freq= 0, CH_0, rank 0
7592 12:47:59.051668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7593 12:47:59.054794 ==
7594 12:47:59.054945 Write leveling (Byte 0): 33 => 33
7595 12:47:59.057890 Write leveling (Byte 1): 27 => 27
7596 12:47:59.061433 DramcWriteLeveling(PI) end<-----
7597 12:47:59.061541
7598 12:47:59.061630 ==
7599 12:47:59.064916 Dram Type= 6, Freq= 0, CH_0, rank 0
7600 12:47:59.071432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7601 12:47:59.071621 ==
7602 12:47:59.071734 [Gating] SW mode calibration
7603 12:47:59.081150 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7604 12:47:59.084843 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7605 12:47:59.087853 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
7606 12:47:59.094496 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 12:47:59.098001 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7608 12:47:59.104619 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7609 12:47:59.108025 1 4 16 | B1->B0 | 2323 3535 | 0 0 | (1 1) (0 0)
7610 12:47:59.111184 1 4 20 | B1->B0 | 3333 3535 | 1 0 | (1 1) (0 0)
7611 12:47:59.114879 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7612 12:47:59.120892 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7613 12:47:59.124502 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7614 12:47:59.128107 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7615 12:47:59.134231 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
7616 12:47:59.137766 1 5 12 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 0)
7617 12:47:59.141042 1 5 16 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
7618 12:47:59.147492 1 5 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7619 12:47:59.151073 1 5 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7620 12:47:59.154284 1 5 28 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7621 12:47:59.161049 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7622 12:47:59.164045 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7623 12:47:59.167529 1 6 8 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7624 12:47:59.174175 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7625 12:47:59.177805 1 6 16 | B1->B0 | 2929 4645 | 0 1 | (0 0) (0 0)
7626 12:47:59.180790 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 12:47:59.187683 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 12:47:59.190450 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 12:47:59.194204 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 12:47:59.201052 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 12:47:59.203963 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 12:47:59.207556 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7633 12:47:59.214173 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7634 12:47:59.217216 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7635 12:47:59.220874 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 12:47:59.226957 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 12:47:59.230591 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 12:47:59.233926 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 12:47:59.240615 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 12:47:59.244327 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 12:47:59.247155 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 12:47:59.250563 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 12:47:59.257343 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 12:47:59.260538 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 12:47:59.264216 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 12:47:59.270747 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 12:47:59.274242 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7648 12:47:59.277131 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7649 12:47:59.284347 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7650 12:47:59.287221 Total UI for P1: 0, mck2ui 16
7651 12:47:59.290796 best dqsien dly found for B0: ( 1, 9, 10)
7652 12:47:59.294136 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 12:47:59.297525 Total UI for P1: 0, mck2ui 16
7654 12:47:59.301009 best dqsien dly found for B1: ( 1, 9, 16)
7655 12:47:59.304099 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7656 12:47:59.307420 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
7657 12:47:59.307543
7658 12:47:59.310873 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7659 12:47:59.313852 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
7660 12:47:59.317370 [Gating] SW calibration Done
7661 12:47:59.317456 ==
7662 12:47:59.320788 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 12:47:59.327300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 12:47:59.327391 ==
7665 12:47:59.327459 RX Vref Scan: 0
7666 12:47:59.327530
7667 12:47:59.330429 RX Vref 0 -> 0, step: 1
7668 12:47:59.330514
7669 12:47:59.333972 RX Delay 0 -> 252, step: 8
7670 12:47:59.336939 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7671 12:47:59.340589 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7672 12:47:59.343813 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7673 12:47:59.346964 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7674 12:47:59.353657 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7675 12:47:59.357262 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7676 12:47:59.360962 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7677 12:47:59.363660 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7678 12:47:59.367109 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7679 12:47:59.370526 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7680 12:47:59.377262 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7681 12:47:59.380241 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7682 12:47:59.383866 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7683 12:47:59.386751 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7684 12:47:59.393482 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7685 12:47:59.397122 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7686 12:47:59.397242 ==
7687 12:47:59.400157 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 12:47:59.403558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 12:47:59.403645 ==
7690 12:47:59.403712 DQS Delay:
7691 12:47:59.407061 DQS0 = 0, DQS1 = 0
7692 12:47:59.407217 DQM Delay:
7693 12:47:59.410154 DQM0 = 136, DQM1 = 130
7694 12:47:59.410296 DQ Delay:
7695 12:47:59.413765 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7696 12:47:59.416953 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7697 12:47:59.420417 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7698 12:47:59.424071 DQ12 =131, DQ13 =139, DQ14 =139, DQ15 =135
7699 12:47:59.426991
7700 12:47:59.427130
7701 12:47:59.427269 ==
7702 12:47:59.430536 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 12:47:59.433963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 12:47:59.434102 ==
7705 12:47:59.434225
7706 12:47:59.434362
7707 12:47:59.436920 TX Vref Scan disable
7708 12:47:59.437065 == TX Byte 0 ==
7709 12:47:59.443792 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7710 12:47:59.447311 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7711 12:47:59.447450 == TX Byte 1 ==
7712 12:47:59.453864 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7713 12:47:59.457169 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7714 12:47:59.457284 ==
7715 12:47:59.460855 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 12:47:59.463891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 12:47:59.463978 ==
7718 12:47:59.476397
7719 12:47:59.479699 TX Vref early break, caculate TX vref
7720 12:47:59.482971 TX Vref=16, minBit 7, minWin=22, winSum=379
7721 12:47:59.486315 TX Vref=18, minBit 0, minWin=24, winSum=392
7722 12:47:59.489790 TX Vref=20, minBit 4, minWin=24, winSum=400
7723 12:47:59.493299 TX Vref=22, minBit 2, minWin=25, winSum=413
7724 12:47:59.496296 TX Vref=24, minBit 6, minWin=25, winSum=418
7725 12:47:59.503395 TX Vref=26, minBit 2, minWin=26, winSum=424
7726 12:47:59.506409 TX Vref=28, minBit 6, minWin=25, winSum=429
7727 12:47:59.509923 TX Vref=30, minBit 1, minWin=25, winSum=417
7728 12:47:59.512919 TX Vref=32, minBit 6, minWin=24, winSum=406
7729 12:47:59.519969 [TxChooseVref] Worse bit 2, Min win 26, Win sum 424, Final Vref 26
7730 12:47:59.520072
7731 12:47:59.522984 Final TX Range 0 Vref 26
7732 12:47:59.523066
7733 12:47:59.523131 ==
7734 12:47:59.526448 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 12:47:59.529527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 12:47:59.529650 ==
7737 12:47:59.529739
7738 12:47:59.529802
7739 12:47:59.533025 TX Vref Scan disable
7740 12:47:59.536577 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7741 12:47:59.540024 == TX Byte 0 ==
7742 12:47:59.543064 u2DelayCellOfst[0]=13 cells (4 PI)
7743 12:47:59.546656 u2DelayCellOfst[1]=16 cells (5 PI)
7744 12:47:59.549615 u2DelayCellOfst[2]=10 cells (3 PI)
7745 12:47:59.553477 u2DelayCellOfst[3]=10 cells (3 PI)
7746 12:47:59.553571 u2DelayCellOfst[4]=6 cells (2 PI)
7747 12:47:59.556290 u2DelayCellOfst[5]=0 cells (0 PI)
7748 12:47:59.559892 u2DelayCellOfst[6]=16 cells (5 PI)
7749 12:47:59.563085 u2DelayCellOfst[7]=16 cells (5 PI)
7750 12:47:59.569575 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7751 12:47:59.573390 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7752 12:47:59.573518 == TX Byte 1 ==
7753 12:47:59.576303 u2DelayCellOfst[8]=3 cells (1 PI)
7754 12:47:59.579791 u2DelayCellOfst[9]=0 cells (0 PI)
7755 12:47:59.583359 u2DelayCellOfst[10]=6 cells (2 PI)
7756 12:47:59.586189 u2DelayCellOfst[11]=3 cells (1 PI)
7757 12:47:59.589650 u2DelayCellOfst[12]=13 cells (4 PI)
7758 12:47:59.592786 u2DelayCellOfst[13]=10 cells (3 PI)
7759 12:47:59.596108 u2DelayCellOfst[14]=13 cells (4 PI)
7760 12:47:59.599611 u2DelayCellOfst[15]=10 cells (3 PI)
7761 12:47:59.603413 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7762 12:47:59.606386 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7763 12:47:59.609362 DramC Write-DBI on
7764 12:47:59.609444 ==
7765 12:47:59.612911 Dram Type= 6, Freq= 0, CH_0, rank 0
7766 12:47:59.616418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7767 12:47:59.616525 ==
7768 12:47:59.616617
7769 12:47:59.616713
7770 12:47:59.619417 TX Vref Scan disable
7771 12:47:59.623102 == TX Byte 0 ==
7772 12:47:59.626100 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7773 12:47:59.626180 == TX Byte 1 ==
7774 12:47:59.632491 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7775 12:47:59.632579 DramC Write-DBI off
7776 12:47:59.632645
7777 12:47:59.635894 [DATLAT]
7778 12:47:59.635999 Freq=1600, CH0 RK0
7779 12:47:59.636097
7780 12:47:59.639556 DATLAT Default: 0xf
7781 12:47:59.639649 0, 0xFFFF, sum = 0
7782 12:47:59.642638 1, 0xFFFF, sum = 0
7783 12:47:59.642721 2, 0xFFFF, sum = 0
7784 12:47:59.646087 3, 0xFFFF, sum = 0
7785 12:47:59.646204 4, 0xFFFF, sum = 0
7786 12:47:59.649190 5, 0xFFFF, sum = 0
7787 12:47:59.649283 6, 0xFFFF, sum = 0
7788 12:47:59.652707 7, 0xFFFF, sum = 0
7789 12:47:59.652798 8, 0xFFFF, sum = 0
7790 12:47:59.655869 9, 0xFFFF, sum = 0
7791 12:47:59.655956 10, 0xFFFF, sum = 0
7792 12:47:59.659413 11, 0xFFFF, sum = 0
7793 12:47:59.662502 12, 0xFFFF, sum = 0
7794 12:47:59.662616 13, 0xFFFF, sum = 0
7795 12:47:59.665993 14, 0x0, sum = 1
7796 12:47:59.666106 15, 0x0, sum = 2
7797 12:47:59.666202 16, 0x0, sum = 3
7798 12:47:59.669389 17, 0x0, sum = 4
7799 12:47:59.669507 best_step = 15
7800 12:47:59.669612
7801 12:47:59.672827 ==
7802 12:47:59.672920 Dram Type= 6, Freq= 0, CH_0, rank 0
7803 12:47:59.679140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7804 12:47:59.679258 ==
7805 12:47:59.679325 RX Vref Scan: 1
7806 12:47:59.679387
7807 12:47:59.682694 Set Vref Range= 24 -> 127
7808 12:47:59.682776
7809 12:47:59.686370 RX Vref 24 -> 127, step: 1
7810 12:47:59.686445
7811 12:47:59.689346 RX Delay 27 -> 252, step: 4
7812 12:47:59.689438
7813 12:47:59.692488 Set Vref, RX VrefLevel [Byte0]: 24
7814 12:47:59.695961 [Byte1]: 24
7815 12:47:59.696047
7816 12:47:59.699318 Set Vref, RX VrefLevel [Byte0]: 25
7817 12:47:59.702559 [Byte1]: 25
7818 12:47:59.702681
7819 12:47:59.705828 Set Vref, RX VrefLevel [Byte0]: 26
7820 12:47:59.709231 [Byte1]: 26
7821 12:47:59.709346
7822 12:47:59.712669 Set Vref, RX VrefLevel [Byte0]: 27
7823 12:47:59.715668 [Byte1]: 27
7824 12:47:59.719985
7825 12:47:59.720099 Set Vref, RX VrefLevel [Byte0]: 28
7826 12:47:59.722992 [Byte1]: 28
7827 12:47:59.727037
7828 12:47:59.727127 Set Vref, RX VrefLevel [Byte0]: 29
7829 12:47:59.730694 [Byte1]: 29
7830 12:47:59.735033
7831 12:47:59.735153 Set Vref, RX VrefLevel [Byte0]: 30
7832 12:47:59.738017 [Byte1]: 30
7833 12:47:59.742534
7834 12:47:59.742649 Set Vref, RX VrefLevel [Byte0]: 31
7835 12:47:59.745445 [Byte1]: 31
7836 12:47:59.750107
7837 12:47:59.750199 Set Vref, RX VrefLevel [Byte0]: 32
7838 12:47:59.752954 [Byte1]: 32
7839 12:47:59.757320
7840 12:47:59.757405 Set Vref, RX VrefLevel [Byte0]: 33
7841 12:47:59.761011 [Byte1]: 33
7842 12:47:59.765127
7843 12:47:59.765212 Set Vref, RX VrefLevel [Byte0]: 34
7844 12:47:59.768314 [Byte1]: 34
7845 12:47:59.772464
7846 12:47:59.772548 Set Vref, RX VrefLevel [Byte0]: 35
7847 12:47:59.775815 [Byte1]: 35
7848 12:47:59.779984
7849 12:47:59.780061 Set Vref, RX VrefLevel [Byte0]: 36
7850 12:47:59.783444 [Byte1]: 36
7851 12:47:59.787582
7852 12:47:59.787661 Set Vref, RX VrefLevel [Byte0]: 37
7853 12:47:59.790919 [Byte1]: 37
7854 12:47:59.795111
7855 12:47:59.795192 Set Vref, RX VrefLevel [Byte0]: 38
7856 12:47:59.798170 [Byte1]: 38
7857 12:47:59.802845
7858 12:47:59.802937 Set Vref, RX VrefLevel [Byte0]: 39
7859 12:47:59.805780 [Byte1]: 39
7860 12:47:59.810371
7861 12:47:59.810487 Set Vref, RX VrefLevel [Byte0]: 40
7862 12:47:59.813178 [Byte1]: 40
7863 12:47:59.817550
7864 12:47:59.817642 Set Vref, RX VrefLevel [Byte0]: 41
7865 12:47:59.820839 [Byte1]: 41
7866 12:47:59.824997
7867 12:47:59.825141 Set Vref, RX VrefLevel [Byte0]: 42
7868 12:47:59.828513 [Byte1]: 42
7869 12:47:59.832626
7870 12:47:59.832745 Set Vref, RX VrefLevel [Byte0]: 43
7871 12:47:59.835829 [Byte1]: 43
7872 12:47:59.840628
7873 12:47:59.840727 Set Vref, RX VrefLevel [Byte0]: 44
7874 12:47:59.843532 [Byte1]: 44
7875 12:47:59.847883
7876 12:47:59.847971 Set Vref, RX VrefLevel [Byte0]: 45
7877 12:47:59.851284 [Byte1]: 45
7878 12:47:59.855331
7879 12:47:59.855420 Set Vref, RX VrefLevel [Byte0]: 46
7880 12:47:59.858933 [Byte1]: 46
7881 12:47:59.862989
7882 12:47:59.863081 Set Vref, RX VrefLevel [Byte0]: 47
7883 12:47:59.865983 [Byte1]: 47
7884 12:47:59.870422
7885 12:47:59.870508 Set Vref, RX VrefLevel [Byte0]: 48
7886 12:47:59.874128 [Byte1]: 48
7887 12:47:59.878186
7888 12:47:59.878275 Set Vref, RX VrefLevel [Byte0]: 49
7889 12:47:59.881352 [Byte1]: 49
7890 12:47:59.885436
7891 12:47:59.885528 Set Vref, RX VrefLevel [Byte0]: 50
7892 12:47:59.888874 [Byte1]: 50
7893 12:47:59.893143
7894 12:47:59.893241 Set Vref, RX VrefLevel [Byte0]: 51
7895 12:47:59.896436 [Byte1]: 51
7896 12:47:59.900293
7897 12:47:59.900425 Set Vref, RX VrefLevel [Byte0]: 52
7898 12:47:59.903959 [Byte1]: 52
7899 12:47:59.908126
7900 12:47:59.908230 Set Vref, RX VrefLevel [Byte0]: 53
7901 12:47:59.911232 [Byte1]: 53
7902 12:47:59.915566
7903 12:47:59.915675 Set Vref, RX VrefLevel [Byte0]: 54
7904 12:47:59.918623 [Byte1]: 54
7905 12:47:59.923246
7906 12:47:59.923370 Set Vref, RX VrefLevel [Byte0]: 55
7907 12:47:59.926659 [Byte1]: 55
7908 12:47:59.930447
7909 12:47:59.930578 Set Vref, RX VrefLevel [Byte0]: 56
7910 12:47:59.933666 [Byte1]: 56
7911 12:47:59.938319
7912 12:47:59.938414 Set Vref, RX VrefLevel [Byte0]: 57
7913 12:47:59.941369 [Byte1]: 57
7914 12:47:59.945696
7915 12:47:59.945787 Set Vref, RX VrefLevel [Byte0]: 58
7916 12:47:59.949246 [Byte1]: 58
7917 12:47:59.952973
7918 12:47:59.953070 Set Vref, RX VrefLevel [Byte0]: 59
7919 12:47:59.956708 [Byte1]: 59
7920 12:47:59.960933
7921 12:47:59.961021 Set Vref, RX VrefLevel [Byte0]: 60
7922 12:47:59.963841 [Byte1]: 60
7923 12:47:59.968496
7924 12:47:59.968589 Set Vref, RX VrefLevel [Byte0]: 61
7925 12:47:59.971593 [Byte1]: 61
7926 12:47:59.975914
7927 12:47:59.976024 Set Vref, RX VrefLevel [Byte0]: 62
7928 12:47:59.979092 [Byte1]: 62
7929 12:47:59.983548
7930 12:47:59.983661 Set Vref, RX VrefLevel [Byte0]: 63
7931 12:47:59.986612 [Byte1]: 63
7932 12:47:59.991036
7933 12:47:59.991173 Set Vref, RX VrefLevel [Byte0]: 64
7934 12:47:59.994243 [Byte1]: 64
7935 12:47:59.998516
7936 12:47:59.998657 Set Vref, RX VrefLevel [Byte0]: 65
7937 12:48:00.001510 [Byte1]: 65
7938 12:48:00.006166
7939 12:48:00.006298 Set Vref, RX VrefLevel [Byte0]: 66
7940 12:48:00.008989 [Byte1]: 66
7941 12:48:00.013372
7942 12:48:00.013517 Set Vref, RX VrefLevel [Byte0]: 67
7943 12:48:00.017090 [Byte1]: 67
7944 12:48:00.020851
7945 12:48:00.020993 Set Vref, RX VrefLevel [Byte0]: 68
7946 12:48:00.024264 [Byte1]: 68
7947 12:48:00.028541
7948 12:48:00.028680 Set Vref, RX VrefLevel [Byte0]: 69
7949 12:48:00.031529 [Byte1]: 69
7950 12:48:00.035780
7951 12:48:00.035897 Set Vref, RX VrefLevel [Byte0]: 70
7952 12:48:00.039211 [Byte1]: 70
7953 12:48:00.043463
7954 12:48:00.043592 Set Vref, RX VrefLevel [Byte0]: 71
7955 12:48:00.046836 [Byte1]: 71
7956 12:48:00.051445
7957 12:48:00.051570 Set Vref, RX VrefLevel [Byte0]: 72
7958 12:48:00.054852 [Byte1]: 72
7959 12:48:00.058554
7960 12:48:00.058670 Final RX Vref Byte 0 = 56 to rank0
7961 12:48:00.062191 Final RX Vref Byte 1 = 65 to rank0
7962 12:48:00.065339 Final RX Vref Byte 0 = 56 to rank1
7963 12:48:00.068942 Final RX Vref Byte 1 = 65 to rank1==
7964 12:48:00.072039 Dram Type= 6, Freq= 0, CH_0, rank 0
7965 12:48:00.078763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7966 12:48:00.078893 ==
7967 12:48:00.078995 DQS Delay:
7968 12:48:00.079061 DQS0 = 0, DQS1 = 0
7969 12:48:00.081931 DQM Delay:
7970 12:48:00.082036 DQM0 = 133, DQM1 = 128
7971 12:48:00.085609 DQ Delay:
7972 12:48:00.088885 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7973 12:48:00.091930 DQ4 =132, DQ5 =124, DQ6 =138, DQ7 =138
7974 12:48:00.095601 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
7975 12:48:00.098783 DQ12 =132, DQ13 =132, DQ14 =140, DQ15 =136
7976 12:48:00.098903
7977 12:48:00.098999
7978 12:48:00.099089
7979 12:48:00.101788 [DramC_TX_OE_Calibration] TA2
7980 12:48:00.105462 Original DQ_B0 (3 6) =30, OEN = 27
7981 12:48:00.108625 Original DQ_B1 (3 6) =30, OEN = 27
7982 12:48:00.111682 24, 0x0, End_B0=24 End_B1=24
7983 12:48:00.111797 25, 0x0, End_B0=25 End_B1=25
7984 12:48:00.115458 26, 0x0, End_B0=26 End_B1=26
7985 12:48:00.118655 27, 0x0, End_B0=27 End_B1=27
7986 12:48:00.121942 28, 0x0, End_B0=28 End_B1=28
7987 12:48:00.122053 29, 0x0, End_B0=29 End_B1=29
7988 12:48:00.125306 30, 0x0, End_B0=30 End_B1=30
7989 12:48:00.128990 31, 0x5151, End_B0=30 End_B1=30
7990 12:48:00.132065 Byte0 end_step=30 best_step=27
7991 12:48:00.135134 Byte1 end_step=30 best_step=27
7992 12:48:00.138801 Byte0 TX OE(2T, 0.5T) = (3, 3)
7993 12:48:00.138907 Byte1 TX OE(2T, 0.5T) = (3, 3)
7994 12:48:00.138999
7995 12:48:00.141855
7996 12:48:00.148847 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7997 12:48:00.152170 CH0 RK0: MR19=303, MR18=2723
7998 12:48:00.158583 CH0_RK0: MR19=0x303, MR18=0x2723, DQSOSC=390, MR23=63, INC=24, DEC=16
7999 12:48:00.158665
8000 12:48:00.161653 ----->DramcWriteLeveling(PI) begin...
8001 12:48:00.161744 ==
8002 12:48:00.165241 Dram Type= 6, Freq= 0, CH_0, rank 1
8003 12:48:00.168351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8004 12:48:00.168426 ==
8005 12:48:00.172056 Write leveling (Byte 0): 35 => 35
8006 12:48:00.175237 Write leveling (Byte 1): 27 => 27
8007 12:48:00.178902 DramcWriteLeveling(PI) end<-----
8008 12:48:00.178978
8009 12:48:00.179041 ==
8010 12:48:00.181883 Dram Type= 6, Freq= 0, CH_0, rank 1
8011 12:48:00.185365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8012 12:48:00.185484 ==
8013 12:48:00.188942 [Gating] SW mode calibration
8014 12:48:00.195131 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8015 12:48:00.201959 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8016 12:48:00.205138 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 12:48:00.208262 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 12:48:00.214989 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 12:48:00.218097 1 4 12 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
8020 12:48:00.221802 1 4 16 | B1->B0 | 2e2e 3434 | 0 1 | (1 1) (1 1)
8021 12:48:00.228421 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8022 12:48:00.231770 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8023 12:48:00.234892 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8024 12:48:00.241444 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
8025 12:48:00.245118 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 12:48:00.248132 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8027 12:48:00.254599 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
8028 12:48:00.258174 1 5 16 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 0)
8029 12:48:00.261570 1 5 20 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8030 12:48:00.268035 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8031 12:48:00.271453 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 12:48:00.275006 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
8033 12:48:00.281412 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 12:48:00.284893 1 6 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
8035 12:48:00.288078 1 6 12 | B1->B0 | 2727 3c3c | 0 0 | (0 0) (0 0)
8036 12:48:00.291215 1 6 16 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
8037 12:48:00.298405 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 12:48:00.301237 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 12:48:00.304934 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 12:48:00.311619 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 12:48:00.314779 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 12:48:00.317901 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 12:48:00.324777 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 12:48:00.328422 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8045 12:48:00.331598 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 12:48:00.338265 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 12:48:00.341267 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 12:48:00.344527 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 12:48:00.351629 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 12:48:00.354612 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 12:48:00.357773 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 12:48:00.364901 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 12:48:00.368215 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 12:48:00.371112 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 12:48:00.377631 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 12:48:00.381318 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 12:48:00.384463 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 12:48:00.391087 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 12:48:00.394823 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8060 12:48:00.397910 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8061 12:48:00.404510 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 12:48:00.404595 Total UI for P1: 0, mck2ui 16
8063 12:48:00.407795 best dqsien dly found for B0: ( 1, 9, 14)
8064 12:48:00.411311 Total UI for P1: 0, mck2ui 16
8065 12:48:00.414275 best dqsien dly found for B1: ( 1, 9, 14)
8066 12:48:00.417729 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8067 12:48:00.424662 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8068 12:48:00.424775
8069 12:48:00.427779 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8070 12:48:00.430978 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8071 12:48:00.434518 [Gating] SW calibration Done
8072 12:48:00.434652 ==
8073 12:48:00.437683 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 12:48:00.441319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 12:48:00.441428 ==
8076 12:48:00.444383 RX Vref Scan: 0
8077 12:48:00.444482
8078 12:48:00.444574 RX Vref 0 -> 0, step: 1
8079 12:48:00.444661
8080 12:48:00.447497 RX Delay 0 -> 252, step: 8
8081 12:48:00.450977 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8082 12:48:00.454424 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8083 12:48:00.461232 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8084 12:48:00.464337 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8085 12:48:00.467767 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8086 12:48:00.470667 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8087 12:48:00.474376 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8088 12:48:00.481108 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8089 12:48:00.484203 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8090 12:48:00.487795 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8091 12:48:00.490938 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8092 12:48:00.494171 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8093 12:48:00.500475 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8094 12:48:00.504225 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8095 12:48:00.507364 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8096 12:48:00.510468 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8097 12:48:00.514117 ==
8098 12:48:00.514187 Dram Type= 6, Freq= 0, CH_0, rank 1
8099 12:48:00.520396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8100 12:48:00.520485 ==
8101 12:48:00.520559 DQS Delay:
8102 12:48:00.524065 DQS0 = 0, DQS1 = 0
8103 12:48:00.524130 DQM Delay:
8104 12:48:00.527132 DQM0 = 137, DQM1 = 131
8105 12:48:00.527222 DQ Delay:
8106 12:48:00.530660 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8107 12:48:00.533546 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8108 12:48:00.536867 DQ8 =123, DQ9 =119, DQ10 =131, DQ11 =123
8109 12:48:00.540374 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8110 12:48:00.540463
8111 12:48:00.540542
8112 12:48:00.540620 ==
8113 12:48:00.543893 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 12:48:00.550249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 12:48:00.550342 ==
8116 12:48:00.550406
8117 12:48:00.550468
8118 12:48:00.550527 TX Vref Scan disable
8119 12:48:00.553914 == TX Byte 0 ==
8120 12:48:00.557451 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8121 12:48:00.560294 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8122 12:48:00.563703 == TX Byte 1 ==
8123 12:48:00.567132 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8124 12:48:00.573632 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8125 12:48:00.573711 ==
8126 12:48:00.577047 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 12:48:00.580321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 12:48:00.580445 ==
8129 12:48:00.593532
8130 12:48:00.597185 TX Vref early break, caculate TX vref
8131 12:48:00.600215 TX Vref=16, minBit 1, minWin=23, winSum=388
8132 12:48:00.603901 TX Vref=18, minBit 0, minWin=23, winSum=396
8133 12:48:00.606990 TX Vref=20, minBit 7, minWin=23, winSum=406
8134 12:48:00.610159 TX Vref=22, minBit 1, minWin=24, winSum=409
8135 12:48:00.613771 TX Vref=24, minBit 1, minWin=25, winSum=419
8136 12:48:00.620565 TX Vref=26, minBit 1, minWin=25, winSum=428
8137 12:48:00.623503 TX Vref=28, minBit 0, minWin=25, winSum=426
8138 12:48:00.626846 TX Vref=30, minBit 0, minWin=25, winSum=417
8139 12:48:00.630525 TX Vref=32, minBit 0, minWin=25, winSum=410
8140 12:48:00.633785 TX Vref=34, minBit 0, minWin=24, winSum=403
8141 12:48:00.640698 [TxChooseVref] Worse bit 1, Min win 25, Win sum 428, Final Vref 26
8142 12:48:00.640780
8143 12:48:00.643926 Final TX Range 0 Vref 26
8144 12:48:00.644047
8145 12:48:00.644157 ==
8146 12:48:00.646744 Dram Type= 6, Freq= 0, CH_0, rank 1
8147 12:48:00.650057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8148 12:48:00.650169 ==
8149 12:48:00.650274
8150 12:48:00.650377
8151 12:48:00.653487 TX Vref Scan disable
8152 12:48:00.660174 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8153 12:48:00.660285 == TX Byte 0 ==
8154 12:48:00.663276 u2DelayCellOfst[0]=13 cells (4 PI)
8155 12:48:00.666766 u2DelayCellOfst[1]=13 cells (4 PI)
8156 12:48:00.670088 u2DelayCellOfst[2]=10 cells (3 PI)
8157 12:48:00.673570 u2DelayCellOfst[3]=10 cells (3 PI)
8158 12:48:00.676870 u2DelayCellOfst[4]=6 cells (2 PI)
8159 12:48:00.679893 u2DelayCellOfst[5]=0 cells (0 PI)
8160 12:48:00.683624 u2DelayCellOfst[6]=16 cells (5 PI)
8161 12:48:00.683715 u2DelayCellOfst[7]=13 cells (4 PI)
8162 12:48:00.690062 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8163 12:48:00.693772 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8164 12:48:00.693863 == TX Byte 1 ==
8165 12:48:00.696666 u2DelayCellOfst[8]=3 cells (1 PI)
8166 12:48:00.700342 u2DelayCellOfst[9]=0 cells (0 PI)
8167 12:48:00.703459 u2DelayCellOfst[10]=6 cells (2 PI)
8168 12:48:00.706631 u2DelayCellOfst[11]=3 cells (1 PI)
8169 12:48:00.710304 u2DelayCellOfst[12]=10 cells (3 PI)
8170 12:48:00.713395 u2DelayCellOfst[13]=10 cells (3 PI)
8171 12:48:00.717090 u2DelayCellOfst[14]=16 cells (5 PI)
8172 12:48:00.720231 u2DelayCellOfst[15]=10 cells (3 PI)
8173 12:48:00.723306 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8174 12:48:00.730210 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8175 12:48:00.730289 DramC Write-DBI on
8176 12:48:00.730354 ==
8177 12:48:00.733349 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 12:48:00.736484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 12:48:00.736586 ==
8180 12:48:00.736676
8181 12:48:00.740251
8182 12:48:00.740324 TX Vref Scan disable
8183 12:48:00.743401 == TX Byte 0 ==
8184 12:48:00.747084 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8185 12:48:00.750109 == TX Byte 1 ==
8186 12:48:00.753120 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8187 12:48:00.753231 DramC Write-DBI off
8188 12:48:00.756852
8189 12:48:00.756962 [DATLAT]
8190 12:48:00.757057 Freq=1600, CH0 RK1
8191 12:48:00.757151
8192 12:48:00.760381 DATLAT Default: 0xf
8193 12:48:00.760490 0, 0xFFFF, sum = 0
8194 12:48:00.763263 1, 0xFFFF, sum = 0
8195 12:48:00.763365 2, 0xFFFF, sum = 0
8196 12:48:00.766389 3, 0xFFFF, sum = 0
8197 12:48:00.766500 4, 0xFFFF, sum = 0
8198 12:48:00.769730 5, 0xFFFF, sum = 0
8199 12:48:00.773415 6, 0xFFFF, sum = 0
8200 12:48:00.773508 7, 0xFFFF, sum = 0
8201 12:48:00.776369 8, 0xFFFF, sum = 0
8202 12:48:00.776453 9, 0xFFFF, sum = 0
8203 12:48:00.779620 10, 0xFFFF, sum = 0
8204 12:48:00.779704 11, 0xFFFF, sum = 0
8205 12:48:00.783009 12, 0xFFFF, sum = 0
8206 12:48:00.783093 13, 0xFFFF, sum = 0
8207 12:48:00.786227 14, 0x0, sum = 1
8208 12:48:00.786338 15, 0x0, sum = 2
8209 12:48:00.790005 16, 0x0, sum = 3
8210 12:48:00.790089 17, 0x0, sum = 4
8211 12:48:00.793194 best_step = 15
8212 12:48:00.793275
8213 12:48:00.793341 ==
8214 12:48:00.796560 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 12:48:00.799979 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 12:48:00.800057 ==
8217 12:48:00.800120 RX Vref Scan: 0
8218 12:48:00.802829
8219 12:48:00.802927 RX Vref 0 -> 0, step: 1
8220 12:48:00.803015
8221 12:48:00.806471 RX Delay 19 -> 252, step: 4
8222 12:48:00.809990 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8223 12:48:00.816631 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8224 12:48:00.819833 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8225 12:48:00.822951 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8226 12:48:00.826501 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8227 12:48:00.829685 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8228 12:48:00.836414 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8229 12:48:00.839330 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8230 12:48:00.843083 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8231 12:48:00.846133 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8232 12:48:00.849812 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8233 12:48:00.855931 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8234 12:48:00.859729 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8235 12:48:00.862619 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8236 12:48:00.866424 iDelay=191, Bit 14, Center 136 (87 ~ 186) 100
8237 12:48:00.869957 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8238 12:48:00.870054 ==
8239 12:48:00.872928 Dram Type= 6, Freq= 0, CH_0, rank 1
8240 12:48:00.879393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8241 12:48:00.879493 ==
8242 12:48:00.879610 DQS Delay:
8243 12:48:00.882747 DQS0 = 0, DQS1 = 0
8244 12:48:00.882827 DQM Delay:
8245 12:48:00.886172 DQM0 = 134, DQM1 = 126
8246 12:48:00.886242 DQ Delay:
8247 12:48:00.889796 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8248 12:48:00.892963 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8249 12:48:00.896271 DQ8 =118, DQ9 =116, DQ10 =126, DQ11 =118
8250 12:48:00.899626 DQ12 =134, DQ13 =132, DQ14 =136, DQ15 =134
8251 12:48:00.899710
8252 12:48:00.899784
8253 12:48:00.899842
8254 12:48:00.902807 [DramC_TX_OE_Calibration] TA2
8255 12:48:00.906392 Original DQ_B0 (3 6) =30, OEN = 27
8256 12:48:00.909522 Original DQ_B1 (3 6) =30, OEN = 27
8257 12:48:00.912838 24, 0x0, End_B0=24 End_B1=24
8258 12:48:00.915912 25, 0x0, End_B0=25 End_B1=25
8259 12:48:00.916012 26, 0x0, End_B0=26 End_B1=26
8260 12:48:00.919559 27, 0x0, End_B0=27 End_B1=27
8261 12:48:00.922737 28, 0x0, End_B0=28 End_B1=28
8262 12:48:00.926203 29, 0x0, End_B0=29 End_B1=29
8263 12:48:00.926281 30, 0x0, End_B0=30 End_B1=30
8264 12:48:00.929747 31, 0x4141, End_B0=30 End_B1=30
8265 12:48:00.932842 Byte0 end_step=30 best_step=27
8266 12:48:00.935963 Byte1 end_step=30 best_step=27
8267 12:48:00.939627 Byte0 TX OE(2T, 0.5T) = (3, 3)
8268 12:48:00.943077 Byte1 TX OE(2T, 0.5T) = (3, 3)
8269 12:48:00.943152
8270 12:48:00.943226
8271 12:48:00.949267 [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8272 12:48:00.952873 CH0 RK1: MR19=303, MR18=2008
8273 12:48:00.959501 CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15
8274 12:48:00.962593 [RxdqsGatingPostProcess] freq 1600
8275 12:48:00.966324 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8276 12:48:01.085347 best DQS0 dly(2T, 0.5T) = (1, 1)
8277 12:48:01.085713 best DQS1 dly(2T, 0.5T) = (1, 1)
8278 12:48:01.085834 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8279 12:48:01.085941 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8280 12:48:01.086042 best DQS0 dly(2T, 0.5T) = (1, 1)
8281 12:48:01.086139 best DQS1 dly(2T, 0.5T) = (1, 1)
8282 12:48:01.086227 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8283 12:48:01.086317 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8284 12:48:01.086432 Pre-setting of DQS Precalculation
8285 12:48:01.086520 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8286 12:48:01.086606 ==
8287 12:48:01.086695 Dram Type= 6, Freq= 0, CH_1, rank 0
8288 12:48:01.086786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8289 12:48:01.086869 ==
8290 12:48:01.086953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8291 12:48:01.087040 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8292 12:48:01.087124 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8293 12:48:01.087208 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8294 12:48:01.087297 [CA 0] Center 41 (12~71) winsize 60
8295 12:48:01.087382 [CA 1] Center 41 (12~71) winsize 60
8296 12:48:01.087470 [CA 2] Center 38 (9~68) winsize 60
8297 12:48:01.087586 [CA 3] Center 37 (9~66) winsize 58
8298 12:48:01.087668 [CA 4] Center 37 (8~67) winsize 60
8299 12:48:01.087781 [CA 5] Center 36 (7~66) winsize 60
8300 12:48:01.087865
8301 12:48:01.087938 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8302 12:48:01.088036
8303 12:48:01.088164 [CATrainingPosCal] consider 1 rank data
8304 12:48:01.088245 u2DelayCellTimex100 = 290/100 ps
8305 12:48:01.088359 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8306 12:48:01.088440 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8307 12:48:01.088523 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8308 12:48:01.088635 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8309 12:48:01.088690 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8310 12:48:01.088743 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8311 12:48:01.088795
8312 12:48:01.089328 CA PerBit enable=1, Macro0, CA PI delay=36
8313 12:48:01.089414
8314 12:48:01.092968 [CBTSetCACLKResult] CA Dly = 36
8315 12:48:01.096086 CS Dly: 10 (0~41)
8316 12:48:01.099190 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8317 12:48:01.102258 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8318 12:48:01.102366 ==
8319 12:48:01.106120 Dram Type= 6, Freq= 0, CH_1, rank 1
8320 12:48:01.109042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 12:48:01.112724 ==
8322 12:48:01.115858 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8323 12:48:01.119273 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8324 12:48:01.125508 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8325 12:48:01.128900 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8326 12:48:01.139103 [CA 0] Center 42 (13~72) winsize 60
8327 12:48:01.142403 [CA 1] Center 42 (12~72) winsize 61
8328 12:48:01.145933 [CA 2] Center 38 (9~68) winsize 60
8329 12:48:01.149103 [CA 3] Center 37 (8~67) winsize 60
8330 12:48:01.152503 [CA 4] Center 38 (8~68) winsize 61
8331 12:48:01.155810 [CA 5] Center 36 (7~66) winsize 60
8332 12:48:01.155885
8333 12:48:01.159478 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8334 12:48:01.159646
8335 12:48:01.162533 [CATrainingPosCal] consider 2 rank data
8336 12:48:01.165918 u2DelayCellTimex100 = 290/100 ps
8337 12:48:01.169017 CA0 delay=42 (13~71),Diff = 6 PI (20 cell)
8338 12:48:01.175952 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8339 12:48:01.179148 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8340 12:48:01.182807 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8341 12:48:01.185898 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8342 12:48:01.189493 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8343 12:48:01.189594
8344 12:48:01.192627 CA PerBit enable=1, Macro0, CA PI delay=36
8345 12:48:01.192736
8346 12:48:01.195718 [CBTSetCACLKResult] CA Dly = 36
8347 12:48:01.198856 CS Dly: 12 (0~45)
8348 12:48:01.202485 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8349 12:48:01.205615 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8350 12:48:01.205689
8351 12:48:01.209514 ----->DramcWriteLeveling(PI) begin...
8352 12:48:01.209589 ==
8353 12:48:01.212611 Dram Type= 6, Freq= 0, CH_1, rank 0
8354 12:48:01.215791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8355 12:48:01.218877 ==
8356 12:48:01.218957 Write leveling (Byte 0): 27 => 27
8357 12:48:01.222121 Write leveling (Byte 1): 28 => 28
8358 12:48:01.225793 DramcWriteLeveling(PI) end<-----
8359 12:48:01.225866
8360 12:48:01.225927 ==
8361 12:48:01.228799 Dram Type= 6, Freq= 0, CH_1, rank 0
8362 12:48:01.235480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8363 12:48:01.235574 ==
8364 12:48:01.239085 [Gating] SW mode calibration
8365 12:48:01.245387 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8366 12:48:01.248939 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8367 12:48:01.255503 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 12:48:01.259030 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 12:48:01.262022 1 4 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
8370 12:48:01.269158 1 4 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
8371 12:48:01.272530 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 12:48:01.275683 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 12:48:01.278819 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 12:48:01.285806 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 12:48:01.288910 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 12:48:01.292436 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 12:48:01.298769 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
8378 12:48:01.302575 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
8379 12:48:01.305648 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 12:48:01.312398 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 12:48:01.315473 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 12:48:01.319253 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 12:48:01.325557 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 12:48:01.329245 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 12:48:01.332376 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8386 12:48:01.339246 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8387 12:48:01.342344 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 12:48:01.345878 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 12:48:01.352572 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 12:48:01.355655 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 12:48:01.358653 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 12:48:01.365856 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 12:48:01.368757 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8394 12:48:01.372293 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8395 12:48:01.379015 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 12:48:01.382002 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 12:48:01.385532 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 12:48:01.388999 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 12:48:01.395278 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 12:48:01.398536 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 12:48:01.401764 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 12:48:01.408506 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 12:48:01.412193 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 12:48:01.415228 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 12:48:01.422024 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 12:48:01.425795 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 12:48:01.428963 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 12:48:01.435619 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 12:48:01.438629 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8410 12:48:01.442363 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8411 12:48:01.445479 Total UI for P1: 0, mck2ui 16
8412 12:48:01.449134 best dqsien dly found for B1: ( 1, 9, 8)
8413 12:48:01.455222 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 12:48:01.455347 Total UI for P1: 0, mck2ui 16
8415 12:48:01.458803 best dqsien dly found for B0: ( 1, 9, 10)
8416 12:48:01.465576 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8417 12:48:01.469092 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8418 12:48:01.469177
8419 12:48:01.472131 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8420 12:48:01.475229 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8421 12:48:01.478725 [Gating] SW calibration Done
8422 12:48:01.478807 ==
8423 12:48:01.482244 Dram Type= 6, Freq= 0, CH_1, rank 0
8424 12:48:01.485410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8425 12:48:01.485492 ==
8426 12:48:01.488963 RX Vref Scan: 0
8427 12:48:01.489044
8428 12:48:01.489108 RX Vref 0 -> 0, step: 1
8429 12:48:01.489169
8430 12:48:01.492061 RX Delay 0 -> 252, step: 8
8431 12:48:01.495549 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8432 12:48:01.498533 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8433 12:48:01.505136 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8434 12:48:01.508547 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8435 12:48:01.511916 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8436 12:48:01.515158 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8437 12:48:01.518600 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8438 12:48:01.525288 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8439 12:48:01.528405 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8440 12:48:01.532062 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8441 12:48:01.535064 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8442 12:48:01.538902 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8443 12:48:01.545099 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8444 12:48:01.548655 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8445 12:48:01.551940 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8446 12:48:01.555429 iDelay=200, Bit 15, Center 147 (96 ~ 199) 104
8447 12:48:01.555549 ==
8448 12:48:01.558449 Dram Type= 6, Freq= 0, CH_1, rank 0
8449 12:48:01.565074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8450 12:48:01.565157 ==
8451 12:48:01.565230 DQS Delay:
8452 12:48:01.565296 DQS0 = 0, DQS1 = 0
8453 12:48:01.568775 DQM Delay:
8454 12:48:01.568853 DQM0 = 136, DQM1 = 134
8455 12:48:01.571761 DQ Delay:
8456 12:48:01.575365 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8457 12:48:01.578408 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8458 12:48:01.581518 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8459 12:48:01.585087 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =147
8460 12:48:01.585162
8461 12:48:01.585228
8462 12:48:01.585290 ==
8463 12:48:01.588695 Dram Type= 6, Freq= 0, CH_1, rank 0
8464 12:48:01.591877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8465 12:48:01.591952 ==
8466 12:48:01.594939
8467 12:48:01.595021
8468 12:48:01.595095 TX Vref Scan disable
8469 12:48:01.598578 == TX Byte 0 ==
8470 12:48:01.601701 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8471 12:48:01.605309 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8472 12:48:01.608238 == TX Byte 1 ==
8473 12:48:01.611881 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8474 12:48:01.614914 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8475 12:48:01.615021 ==
8476 12:48:01.618602 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 12:48:01.625287 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 12:48:01.625371 ==
8479 12:48:01.636303
8480 12:48:01.639393 TX Vref early break, caculate TX vref
8481 12:48:01.643271 TX Vref=16, minBit 0, minWin=22, winSum=373
8482 12:48:01.646446 TX Vref=18, minBit 9, minWin=22, winSum=382
8483 12:48:01.649449 TX Vref=20, minBit 0, minWin=24, winSum=396
8484 12:48:01.653264 TX Vref=22, minBit 1, minWin=24, winSum=405
8485 12:48:01.656283 TX Vref=24, minBit 0, minWin=24, winSum=416
8486 12:48:01.662832 TX Vref=26, minBit 0, minWin=25, winSum=421
8487 12:48:01.665943 TX Vref=28, minBit 0, minWin=25, winSum=426
8488 12:48:01.669724 TX Vref=30, minBit 0, minWin=25, winSum=418
8489 12:48:01.672783 TX Vref=32, minBit 0, minWin=25, winSum=413
8490 12:48:01.676344 TX Vref=34, minBit 2, minWin=23, winSum=400
8491 12:48:01.683232 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 28
8492 12:48:01.683316
8493 12:48:01.686486 Final TX Range 0 Vref 28
8494 12:48:01.686570
8495 12:48:01.686654 ==
8496 12:48:01.689433 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 12:48:01.693032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8498 12:48:01.693116 ==
8499 12:48:01.693201
8500 12:48:01.693280
8501 12:48:01.696654 TX Vref Scan disable
8502 12:48:01.702950 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8503 12:48:01.703026 == TX Byte 0 ==
8504 12:48:01.706595 u2DelayCellOfst[0]=20 cells (6 PI)
8505 12:48:01.709508 u2DelayCellOfst[1]=13 cells (4 PI)
8506 12:48:01.712591 u2DelayCellOfst[2]=0 cells (0 PI)
8507 12:48:01.716419 u2DelayCellOfst[3]=10 cells (3 PI)
8508 12:48:01.719596 u2DelayCellOfst[4]=13 cells (4 PI)
8509 12:48:01.722713 u2DelayCellOfst[5]=20 cells (6 PI)
8510 12:48:01.726284 u2DelayCellOfst[6]=20 cells (6 PI)
8511 12:48:01.726382 u2DelayCellOfst[7]=10 cells (3 PI)
8512 12:48:01.733002 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8513 12:48:01.735984 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8514 12:48:01.736059 == TX Byte 1 ==
8515 12:48:01.739385 u2DelayCellOfst[8]=0 cells (0 PI)
8516 12:48:01.742753 u2DelayCellOfst[9]=3 cells (1 PI)
8517 12:48:01.746223 u2DelayCellOfst[10]=13 cells (4 PI)
8518 12:48:01.749320 u2DelayCellOfst[11]=3 cells (1 PI)
8519 12:48:01.753073 u2DelayCellOfst[12]=13 cells (4 PI)
8520 12:48:01.756187 u2DelayCellOfst[13]=16 cells (5 PI)
8521 12:48:01.759346 u2DelayCellOfst[14]=20 cells (6 PI)
8522 12:48:01.762921 u2DelayCellOfst[15]=16 cells (5 PI)
8523 12:48:01.766339 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8524 12:48:01.772592 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8525 12:48:01.772671 DramC Write-DBI on
8526 12:48:01.772739 ==
8527 12:48:01.776330 Dram Type= 6, Freq= 0, CH_1, rank 0
8528 12:48:01.779400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8529 12:48:01.779512 ==
8530 12:48:01.779600
8531 12:48:01.783188
8532 12:48:01.783285 TX Vref Scan disable
8533 12:48:01.786236 == TX Byte 0 ==
8534 12:48:01.789840 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8535 12:48:01.792591 == TX Byte 1 ==
8536 12:48:01.796203 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8537 12:48:01.796278 DramC Write-DBI off
8538 12:48:01.796346
8539 12:48:01.799768 [DATLAT]
8540 12:48:01.799840 Freq=1600, CH1 RK0
8541 12:48:01.799901
8542 12:48:01.802927 DATLAT Default: 0xf
8543 12:48:01.803033 0, 0xFFFF, sum = 0
8544 12:48:01.806096 1, 0xFFFF, sum = 0
8545 12:48:01.806205 2, 0xFFFF, sum = 0
8546 12:48:01.809175 3, 0xFFFF, sum = 0
8547 12:48:01.809288 4, 0xFFFF, sum = 0
8548 12:48:01.812917 5, 0xFFFF, sum = 0
8549 12:48:01.813029 6, 0xFFFF, sum = 0
8550 12:48:01.816009 7, 0xFFFF, sum = 0
8551 12:48:01.819251 8, 0xFFFF, sum = 0
8552 12:48:01.819337 9, 0xFFFF, sum = 0
8553 12:48:01.823013 10, 0xFFFF, sum = 0
8554 12:48:01.823097 11, 0xFFFF, sum = 0
8555 12:48:01.826184 12, 0xFFFF, sum = 0
8556 12:48:01.826294 13, 0xFFFF, sum = 0
8557 12:48:01.829165 14, 0x0, sum = 1
8558 12:48:01.829254 15, 0x0, sum = 2
8559 12:48:01.832872 16, 0x0, sum = 3
8560 12:48:01.832955 17, 0x0, sum = 4
8561 12:48:01.833021 best_step = 15
8562 12:48:01.835946
8563 12:48:01.836027 ==
8564 12:48:01.839675 Dram Type= 6, Freq= 0, CH_1, rank 0
8565 12:48:01.842577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8566 12:48:01.842689 ==
8567 12:48:01.842792 RX Vref Scan: 1
8568 12:48:01.842885
8569 12:48:01.846259 Set Vref Range= 24 -> 127
8570 12:48:01.846362
8571 12:48:01.849464 RX Vref 24 -> 127, step: 1
8572 12:48:01.849538
8573 12:48:01.852532 RX Delay 27 -> 252, step: 4
8574 12:48:01.852637
8575 12:48:01.855994 Set Vref, RX VrefLevel [Byte0]: 24
8576 12:48:01.859482 [Byte1]: 24
8577 12:48:01.859575
8578 12:48:01.862444 Set Vref, RX VrefLevel [Byte0]: 25
8579 12:48:01.866193 [Byte1]: 25
8580 12:48:01.866303
8581 12:48:01.868989 Set Vref, RX VrefLevel [Byte0]: 26
8582 12:48:01.872725 [Byte1]: 26
8583 12:48:01.875789
8584 12:48:01.875892 Set Vref, RX VrefLevel [Byte0]: 27
8585 12:48:01.879447 [Byte1]: 27
8586 12:48:01.883339
8587 12:48:01.883443 Set Vref, RX VrefLevel [Byte0]: 28
8588 12:48:01.887174 [Byte1]: 28
8589 12:48:01.891295
8590 12:48:01.891396 Set Vref, RX VrefLevel [Byte0]: 29
8591 12:48:01.894399 [Byte1]: 29
8592 12:48:01.898530
8593 12:48:01.898624 Set Vref, RX VrefLevel [Byte0]: 30
8594 12:48:01.902095 [Byte1]: 30
8595 12:48:01.905975
8596 12:48:01.906088 Set Vref, RX VrefLevel [Byte0]: 31
8597 12:48:01.909472 [Byte1]: 31
8598 12:48:01.913722
8599 12:48:01.913803 Set Vref, RX VrefLevel [Byte0]: 32
8600 12:48:01.917261 [Byte1]: 32
8601 12:48:01.921018
8602 12:48:01.921099 Set Vref, RX VrefLevel [Byte0]: 33
8603 12:48:01.924690 [Byte1]: 33
8604 12:48:01.929147
8605 12:48:01.929229 Set Vref, RX VrefLevel [Byte0]: 34
8606 12:48:01.932084 [Byte1]: 34
8607 12:48:01.936385
8608 12:48:01.936500 Set Vref, RX VrefLevel [Byte0]: 35
8609 12:48:01.939408 [Byte1]: 35
8610 12:48:01.943811
8611 12:48:01.943893 Set Vref, RX VrefLevel [Byte0]: 36
8612 12:48:01.947235 [Byte1]: 36
8613 12:48:01.951246
8614 12:48:01.951328 Set Vref, RX VrefLevel [Byte0]: 37
8615 12:48:01.954474 [Byte1]: 37
8616 12:48:01.958740
8617 12:48:01.962320 Set Vref, RX VrefLevel [Byte0]: 38
8618 12:48:01.965266 [Byte1]: 38
8619 12:48:01.965348
8620 12:48:01.968872 Set Vref, RX VrefLevel [Byte0]: 39
8621 12:48:01.971859 [Byte1]: 39
8622 12:48:01.971942
8623 12:48:01.975243 Set Vref, RX VrefLevel [Byte0]: 40
8624 12:48:01.978547 [Byte1]: 40
8625 12:48:01.978633
8626 12:48:01.981659 Set Vref, RX VrefLevel [Byte0]: 41
8627 12:48:01.985487 [Byte1]: 41
8628 12:48:01.989226
8629 12:48:01.989307 Set Vref, RX VrefLevel [Byte0]: 42
8630 12:48:01.992322 [Byte1]: 42
8631 12:48:01.996609
8632 12:48:01.996690 Set Vref, RX VrefLevel [Byte0]: 43
8633 12:48:01.999762 [Byte1]: 43
8634 12:48:02.003951
8635 12:48:02.004031 Set Vref, RX VrefLevel [Byte0]: 44
8636 12:48:02.007498 [Byte1]: 44
8637 12:48:02.011510
8638 12:48:02.011647 Set Vref, RX VrefLevel [Byte0]: 45
8639 12:48:02.014824 [Byte1]: 45
8640 12:48:02.019400
8641 12:48:02.019529 Set Vref, RX VrefLevel [Byte0]: 46
8642 12:48:02.022157 [Byte1]: 46
8643 12:48:02.026628
8644 12:48:02.026707 Set Vref, RX VrefLevel [Byte0]: 47
8645 12:48:02.030271 [Byte1]: 47
8646 12:48:02.033893
8647 12:48:02.033972 Set Vref, RX VrefLevel [Byte0]: 48
8648 12:48:02.037503 [Byte1]: 48
8649 12:48:02.041797
8650 12:48:02.041877 Set Vref, RX VrefLevel [Byte0]: 49
8651 12:48:02.044781 [Byte1]: 49
8652 12:48:02.049026
8653 12:48:02.049106 Set Vref, RX VrefLevel [Byte0]: 50
8654 12:48:02.052665 [Byte1]: 50
8655 12:48:02.056719
8656 12:48:02.056816 Set Vref, RX VrefLevel [Byte0]: 51
8657 12:48:02.060198 [Byte1]: 51
8658 12:48:02.064532
8659 12:48:02.064615 Set Vref, RX VrefLevel [Byte0]: 52
8660 12:48:02.067732 [Byte1]: 52
8661 12:48:02.071893
8662 12:48:02.072001 Set Vref, RX VrefLevel [Byte0]: 53
8663 12:48:02.075271 [Byte1]: 53
8664 12:48:02.079482
8665 12:48:02.079617 Set Vref, RX VrefLevel [Byte0]: 54
8666 12:48:02.082454 [Byte1]: 54
8667 12:48:02.087005
8668 12:48:02.087103 Set Vref, RX VrefLevel [Byte0]: 55
8669 12:48:02.089979 [Byte1]: 55
8670 12:48:02.094167
8671 12:48:02.094258 Set Vref, RX VrefLevel [Byte0]: 56
8672 12:48:02.097723 [Byte1]: 56
8673 12:48:02.102056
8674 12:48:02.102153 Set Vref, RX VrefLevel [Byte0]: 57
8675 12:48:02.105019 [Byte1]: 57
8676 12:48:02.109238
8677 12:48:02.109335 Set Vref, RX VrefLevel [Byte0]: 58
8678 12:48:02.112822 [Byte1]: 58
8679 12:48:02.117128
8680 12:48:02.117208 Set Vref, RX VrefLevel [Byte0]: 59
8681 12:48:02.120184 [Byte1]: 59
8682 12:48:02.124325
8683 12:48:02.124421 Set Vref, RX VrefLevel [Byte0]: 60
8684 12:48:02.127960 [Byte1]: 60
8685 12:48:02.131809
8686 12:48:02.131890 Set Vref, RX VrefLevel [Byte0]: 61
8687 12:48:02.135690 [Byte1]: 61
8688 12:48:02.139600
8689 12:48:02.139727 Set Vref, RX VrefLevel [Byte0]: 62
8690 12:48:02.142956 [Byte1]: 62
8691 12:48:02.147235
8692 12:48:02.147331 Set Vref, RX VrefLevel [Byte0]: 63
8693 12:48:02.150314 [Byte1]: 63
8694 12:48:02.154621
8695 12:48:02.154697 Set Vref, RX VrefLevel [Byte0]: 64
8696 12:48:02.158157 [Byte1]: 64
8697 12:48:02.162295
8698 12:48:02.162390 Set Vref, RX VrefLevel [Byte0]: 65
8699 12:48:02.165793 [Byte1]: 65
8700 12:48:02.169872
8701 12:48:02.169967 Set Vref, RX VrefLevel [Byte0]: 66
8702 12:48:02.173062 [Byte1]: 66
8703 12:48:02.177423
8704 12:48:02.177492 Set Vref, RX VrefLevel [Byte0]: 67
8705 12:48:02.180492 [Byte1]: 67
8706 12:48:02.184790
8707 12:48:02.184857 Set Vref, RX VrefLevel [Byte0]: 68
8708 12:48:02.188277 [Byte1]: 68
8709 12:48:02.192271
8710 12:48:02.192335 Set Vref, RX VrefLevel [Byte0]: 69
8711 12:48:02.195780 [Byte1]: 69
8712 12:48:02.199813
8713 12:48:02.199881 Set Vref, RX VrefLevel [Byte0]: 70
8714 12:48:02.203417 [Byte1]: 70
8715 12:48:02.207094
8716 12:48:02.207175 Set Vref, RX VrefLevel [Byte0]: 71
8717 12:48:02.210790 [Byte1]: 71
8718 12:48:02.214928
8719 12:48:02.215026 Set Vref, RX VrefLevel [Byte0]: 72
8720 12:48:02.218472 [Byte1]: 72
8721 12:48:02.222252
8722 12:48:02.222353 Set Vref, RX VrefLevel [Byte0]: 73
8723 12:48:02.225955 [Byte1]: 73
8724 12:48:02.230121
8725 12:48:02.230236 Set Vref, RX VrefLevel [Byte0]: 74
8726 12:48:02.233255 [Byte1]: 74
8727 12:48:02.237371
8728 12:48:02.237465 Final RX Vref Byte 0 = 59 to rank0
8729 12:48:02.240662 Final RX Vref Byte 1 = 55 to rank0
8730 12:48:02.244031 Final RX Vref Byte 0 = 59 to rank1
8731 12:48:02.247593 Final RX Vref Byte 1 = 55 to rank1==
8732 12:48:02.250577 Dram Type= 6, Freq= 0, CH_1, rank 0
8733 12:48:02.257568 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8734 12:48:02.257652 ==
8735 12:48:02.257760 DQS Delay:
8736 12:48:02.257826 DQS0 = 0, DQS1 = 0
8737 12:48:02.260524 DQM Delay:
8738 12:48:02.260604 DQM0 = 134, DQM1 = 131
8739 12:48:02.263782 DQ Delay:
8740 12:48:02.267356 DQ0 =140, DQ1 =130, DQ2 =124, DQ3 =130
8741 12:48:02.270810 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132
8742 12:48:02.274172 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =122
8743 12:48:02.277073 DQ12 =140, DQ13 =138, DQ14 =140, DQ15 =140
8744 12:48:02.277152
8745 12:48:02.277216
8746 12:48:02.277275
8747 12:48:02.280800 [DramC_TX_OE_Calibration] TA2
8748 12:48:02.283928 Original DQ_B0 (3 6) =30, OEN = 27
8749 12:48:02.287057 Original DQ_B1 (3 6) =30, OEN = 27
8750 12:48:02.290645 24, 0x0, End_B0=24 End_B1=24
8751 12:48:02.290729 25, 0x0, End_B0=25 End_B1=25
8752 12:48:02.293873 26, 0x0, End_B0=26 End_B1=26
8753 12:48:02.296948 27, 0x0, End_B0=27 End_B1=27
8754 12:48:02.300466 28, 0x0, End_B0=28 End_B1=28
8755 12:48:02.304008 29, 0x0, End_B0=29 End_B1=29
8756 12:48:02.304090 30, 0x0, End_B0=30 End_B1=30
8757 12:48:02.306852 31, 0x4545, End_B0=30 End_B1=30
8758 12:48:02.310486 Byte0 end_step=30 best_step=27
8759 12:48:02.313462 Byte1 end_step=30 best_step=27
8760 12:48:02.317107 Byte0 TX OE(2T, 0.5T) = (3, 3)
8761 12:48:02.320204 Byte1 TX OE(2T, 0.5T) = (3, 3)
8762 12:48:02.320284
8763 12:48:02.320348
8764 12:48:02.327362 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8765 12:48:02.330390 CH1 RK0: MR19=303, MR18=1826
8766 12:48:02.337012 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8767 12:48:02.337130
8768 12:48:02.340011 ----->DramcWriteLeveling(PI) begin...
8769 12:48:02.340109 ==
8770 12:48:02.343745 Dram Type= 6, Freq= 0, CH_1, rank 1
8771 12:48:02.346574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 12:48:02.346671 ==
8773 12:48:02.349891 Write leveling (Byte 0): 27 => 27
8774 12:48:02.353348 Write leveling (Byte 1): 28 => 28
8775 12:48:02.356649 DramcWriteLeveling(PI) end<-----
8776 12:48:02.356732
8777 12:48:02.356795 ==
8778 12:48:02.360196 Dram Type= 6, Freq= 0, CH_1, rank 1
8779 12:48:02.363656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8780 12:48:02.363741 ==
8781 12:48:02.366981 [Gating] SW mode calibration
8782 12:48:02.373532 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8783 12:48:02.380069 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8784 12:48:02.383407 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 12:48:02.386884 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 12:48:02.393552 1 4 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
8787 12:48:02.397288 1 4 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
8788 12:48:02.400198 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 12:48:02.406822 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 12:48:02.410384 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 12:48:02.413455 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 12:48:02.419975 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 12:48:02.423493 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8794 12:48:02.427113 1 5 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
8795 12:48:02.433269 1 5 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 0)
8796 12:48:02.437065 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 12:48:02.440024 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 12:48:02.446893 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 12:48:02.450523 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 12:48:02.453548 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 12:48:02.459995 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 12:48:02.463385 1 6 8 | B1->B0 | 3332 2323 | 1 0 | (0 0) (0 0)
8803 12:48:02.466846 1 6 12 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
8804 12:48:02.473126 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 12:48:02.476964 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 12:48:02.479797 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 12:48:02.486937 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 12:48:02.489795 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 12:48:02.493306 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8810 12:48:02.496747 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8811 12:48:02.503240 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8812 12:48:02.506843 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 12:48:02.509876 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 12:48:02.516942 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 12:48:02.519866 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 12:48:02.523366 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 12:48:02.530063 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 12:48:02.533168 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 12:48:02.536972 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 12:48:02.543644 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 12:48:02.546582 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 12:48:02.550267 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 12:48:02.556440 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 12:48:02.560129 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 12:48:02.563167 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8826 12:48:02.569703 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8827 12:48:02.573368 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8828 12:48:02.576403 Total UI for P1: 0, mck2ui 16
8829 12:48:02.579988 best dqsien dly found for B1: ( 1, 9, 6)
8830 12:48:02.583101 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 12:48:02.586425 Total UI for P1: 0, mck2ui 16
8832 12:48:02.590194 best dqsien dly found for B0: ( 1, 9, 12)
8833 12:48:02.593633 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8834 12:48:02.596474 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8835 12:48:02.596554
8836 12:48:02.599982 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8837 12:48:02.606786 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8838 12:48:02.606908 [Gating] SW calibration Done
8839 12:48:02.607023 ==
8840 12:48:02.609665 Dram Type= 6, Freq= 0, CH_1, rank 1
8841 12:48:02.616137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8842 12:48:02.616242 ==
8843 12:48:02.616335 RX Vref Scan: 0
8844 12:48:02.616398
8845 12:48:02.619727 RX Vref 0 -> 0, step: 1
8846 12:48:02.619824
8847 12:48:02.623305 RX Delay 0 -> 252, step: 8
8848 12:48:02.626334 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8849 12:48:02.629848 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8850 12:48:02.632875 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8851 12:48:02.639932 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8852 12:48:02.642969 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8853 12:48:02.646579 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8854 12:48:02.649575 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8855 12:48:02.652732 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8856 12:48:02.659462 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8857 12:48:02.662562 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8858 12:48:02.666154 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8859 12:48:02.669740 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8860 12:48:02.672720 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8861 12:48:02.679369 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8862 12:48:02.683218 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8863 12:48:02.686245 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8864 12:48:02.686352 ==
8865 12:48:02.689897 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 12:48:02.692897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 12:48:02.692968 ==
8868 12:48:02.696470 DQS Delay:
8869 12:48:02.696557 DQS0 = 0, DQS1 = 0
8870 12:48:02.699469 DQM Delay:
8871 12:48:02.699574 DQM0 = 135, DQM1 = 133
8872 12:48:02.699653 DQ Delay:
8873 12:48:02.703050 DQ0 =139, DQ1 =135, DQ2 =119, DQ3 =131
8874 12:48:02.706519 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8875 12:48:02.712980 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8876 12:48:02.716127 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8877 12:48:02.716228
8878 12:48:02.716331
8879 12:48:02.716437 ==
8880 12:48:02.719499 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 12:48:02.723078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 12:48:02.723151 ==
8883 12:48:02.723224
8884 12:48:02.723283
8885 12:48:02.725880 TX Vref Scan disable
8886 12:48:02.729100 == TX Byte 0 ==
8887 12:48:02.732871 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8888 12:48:02.735855 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8889 12:48:02.739177 == TX Byte 1 ==
8890 12:48:02.742706 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8891 12:48:02.746344 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8892 12:48:02.746443 ==
8893 12:48:02.749289 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 12:48:02.753073 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 12:48:02.756086 ==
8896 12:48:02.766499
8897 12:48:02.770174 TX Vref early break, caculate TX vref
8898 12:48:02.773289 TX Vref=16, minBit 0, minWin=23, winSum=385
8899 12:48:02.776840 TX Vref=18, minBit 0, minWin=23, winSum=390
8900 12:48:02.780297 TX Vref=20, minBit 0, minWin=24, winSum=400
8901 12:48:02.783439 TX Vref=22, minBit 0, minWin=25, winSum=413
8902 12:48:02.787103 TX Vref=24, minBit 0, minWin=25, winSum=418
8903 12:48:02.793140 TX Vref=26, minBit 0, minWin=25, winSum=423
8904 12:48:02.796658 TX Vref=28, minBit 1, minWin=25, winSum=426
8905 12:48:02.799769 TX Vref=30, minBit 1, minWin=25, winSum=421
8906 12:48:02.803402 TX Vref=32, minBit 0, minWin=25, winSum=413
8907 12:48:02.806513 TX Vref=34, minBit 0, minWin=24, winSum=402
8908 12:48:02.813282 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 28
8909 12:48:02.813358
8910 12:48:02.816869 Final TX Range 0 Vref 28
8911 12:48:02.816944
8912 12:48:02.817022 ==
8913 12:48:02.819814 Dram Type= 6, Freq= 0, CH_1, rank 1
8914 12:48:02.823294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8915 12:48:02.823403 ==
8916 12:48:02.823494
8917 12:48:02.823586
8918 12:48:02.826688 TX Vref Scan disable
8919 12:48:02.833330 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8920 12:48:02.833410 == TX Byte 0 ==
8921 12:48:02.836569 u2DelayCellOfst[0]=16 cells (5 PI)
8922 12:48:02.839808 u2DelayCellOfst[1]=10 cells (3 PI)
8923 12:48:02.843403 u2DelayCellOfst[2]=0 cells (0 PI)
8924 12:48:02.846288 u2DelayCellOfst[3]=6 cells (2 PI)
8925 12:48:02.849845 u2DelayCellOfst[4]=10 cells (3 PI)
8926 12:48:02.853307 u2DelayCellOfst[5]=16 cells (5 PI)
8927 12:48:02.853416 u2DelayCellOfst[6]=16 cells (5 PI)
8928 12:48:02.856549 u2DelayCellOfst[7]=6 cells (2 PI)
8929 12:48:02.863037 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8930 12:48:02.866741 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8931 12:48:02.866816 == TX Byte 1 ==
8932 12:48:02.869927 u2DelayCellOfst[8]=0 cells (0 PI)
8933 12:48:02.873015 u2DelayCellOfst[9]=6 cells (2 PI)
8934 12:48:02.876718 u2DelayCellOfst[10]=13 cells (4 PI)
8935 12:48:02.879853 u2DelayCellOfst[11]=10 cells (3 PI)
8936 12:48:02.883410 u2DelayCellOfst[12]=16 cells (5 PI)
8937 12:48:02.886421 u2DelayCellOfst[13]=20 cells (6 PI)
8938 12:48:02.890097 u2DelayCellOfst[14]=20 cells (6 PI)
8939 12:48:02.893143 u2DelayCellOfst[15]=20 cells (6 PI)
8940 12:48:02.896791 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8941 12:48:02.902895 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8942 12:48:02.902976 DramC Write-DBI on
8943 12:48:02.903040 ==
8944 12:48:02.906512 Dram Type= 6, Freq= 0, CH_1, rank 1
8945 12:48:02.909558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8946 12:48:02.909639 ==
8947 12:48:02.913240
8948 12:48:02.913321
8949 12:48:02.913385 TX Vref Scan disable
8950 12:48:02.916309 == TX Byte 0 ==
8951 12:48:02.919962 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8952 12:48:02.922939 == TX Byte 1 ==
8953 12:48:02.926503 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8954 12:48:02.926609 DramC Write-DBI off
8955 12:48:02.926700
8956 12:48:02.929547 [DATLAT]
8957 12:48:02.929617 Freq=1600, CH1 RK1
8958 12:48:02.929678
8959 12:48:02.933248 DATLAT Default: 0xf
8960 12:48:02.933317 0, 0xFFFF, sum = 0
8961 12:48:02.936237 1, 0xFFFF, sum = 0
8962 12:48:02.936319 2, 0xFFFF, sum = 0
8963 12:48:02.939838 3, 0xFFFF, sum = 0
8964 12:48:02.939960 4, 0xFFFF, sum = 0
8965 12:48:02.943295 5, 0xFFFF, sum = 0
8966 12:48:02.943408 6, 0xFFFF, sum = 0
8967 12:48:02.946472 7, 0xFFFF, sum = 0
8968 12:48:02.949454 8, 0xFFFF, sum = 0
8969 12:48:02.949567 9, 0xFFFF, sum = 0
8970 12:48:02.952963 10, 0xFFFF, sum = 0
8971 12:48:02.953076 11, 0xFFFF, sum = 0
8972 12:48:02.956187 12, 0xFFFF, sum = 0
8973 12:48:02.956310 13, 0xFFFF, sum = 0
8974 12:48:02.959394 14, 0x0, sum = 1
8975 12:48:02.959525 15, 0x0, sum = 2
8976 12:48:02.963032 16, 0x0, sum = 3
8977 12:48:02.963132 17, 0x0, sum = 4
8978 12:48:02.965996 best_step = 15
8979 12:48:02.966095
8980 12:48:02.966184 ==
8981 12:48:02.969721 Dram Type= 6, Freq= 0, CH_1, rank 1
8982 12:48:02.972769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8983 12:48:02.972865 ==
8984 12:48:02.972999 RX Vref Scan: 0
8985 12:48:02.973116
8986 12:48:02.976328 RX Vref 0 -> 0, step: 1
8987 12:48:02.976437
8988 12:48:02.979646 RX Delay 19 -> 252, step: 4
8989 12:48:02.983183 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8990 12:48:02.986188 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8991 12:48:02.992853 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8992 12:48:02.996503 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8993 12:48:02.999544 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8994 12:48:03.003055 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8995 12:48:03.006275 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8996 12:48:03.012747 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8997 12:48:03.016484 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8998 12:48:03.019652 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8999 12:48:03.023230 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9000 12:48:03.026397 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9001 12:48:03.033140 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9002 12:48:03.036247 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9003 12:48:03.039885 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9004 12:48:03.042745 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9005 12:48:03.042861 ==
9006 12:48:03.046230 Dram Type= 6, Freq= 0, CH_1, rank 1
9007 12:48:03.052966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9008 12:48:03.053063 ==
9009 12:48:03.053154 DQS Delay:
9010 12:48:03.053240 DQS0 = 0, DQS1 = 0
9011 12:48:03.056093 DQM Delay:
9012 12:48:03.056169 DQM0 = 134, DQM1 = 130
9013 12:48:03.059212 DQ Delay:
9014 12:48:03.062803 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9015 12:48:03.065903 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9016 12:48:03.069480 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9017 12:48:03.072959 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9018 12:48:03.073042
9019 12:48:03.073106
9020 12:48:03.073166
9021 12:48:03.076225 [DramC_TX_OE_Calibration] TA2
9022 12:48:03.078998 Original DQ_B0 (3 6) =30, OEN = 27
9023 12:48:03.082441 Original DQ_B1 (3 6) =30, OEN = 27
9024 12:48:03.085583 24, 0x0, End_B0=24 End_B1=24
9025 12:48:03.085666 25, 0x0, End_B0=25 End_B1=25
9026 12:48:03.089192 26, 0x0, End_B0=26 End_B1=26
9027 12:48:03.092372 27, 0x0, End_B0=27 End_B1=27
9028 12:48:03.096059 28, 0x0, End_B0=28 End_B1=28
9029 12:48:03.099023 29, 0x0, End_B0=29 End_B1=29
9030 12:48:03.099105 30, 0x0, End_B0=30 End_B1=30
9031 12:48:03.102231 31, 0x4141, End_B0=30 End_B1=30
9032 12:48:03.105899 Byte0 end_step=30 best_step=27
9033 12:48:03.108938 Byte1 end_step=30 best_step=27
9034 12:48:03.112479 Byte0 TX OE(2T, 0.5T) = (3, 3)
9035 12:48:03.115458 Byte1 TX OE(2T, 0.5T) = (3, 3)
9036 12:48:03.115573
9037 12:48:03.115637
9038 12:48:03.122196 [DQSOSCAuto] RK1, (LSB)MR18= 0x2408, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
9039 12:48:03.125865 CH1 RK1: MR19=303, MR18=2408
9040 12:48:03.132531 CH1_RK1: MR19=0x303, MR18=0x2408, DQSOSC=391, MR23=63, INC=24, DEC=16
9041 12:48:03.135457 [RxdqsGatingPostProcess] freq 1600
9042 12:48:03.138611 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9043 12:48:03.142341 best DQS0 dly(2T, 0.5T) = (1, 1)
9044 12:48:03.145343 best DQS1 dly(2T, 0.5T) = (1, 1)
9045 12:48:03.149000 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9046 12:48:03.152610 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9047 12:48:03.155452 best DQS0 dly(2T, 0.5T) = (1, 1)
9048 12:48:03.158588 best DQS1 dly(2T, 0.5T) = (1, 1)
9049 12:48:03.162403 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9050 12:48:03.165580 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9051 12:48:03.169194 Pre-setting of DQS Precalculation
9052 12:48:03.172303 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9053 12:48:03.178884 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9054 12:48:03.188998 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9055 12:48:03.189079
9056 12:48:03.189143
9057 12:48:03.189203 [Calibration Summary] 3200 Mbps
9058 12:48:03.191929 CH 0, Rank 0
9059 12:48:03.192008 SW Impedance : PASS
9060 12:48:03.195401 DUTY Scan : NO K
9061 12:48:03.198895 ZQ Calibration : PASS
9062 12:48:03.199010 Jitter Meter : NO K
9063 12:48:03.201713 CBT Training : PASS
9064 12:48:03.205063 Write leveling : PASS
9065 12:48:03.205143 RX DQS gating : PASS
9066 12:48:03.208416 RX DQ/DQS(RDDQC) : PASS
9067 12:48:03.212181 TX DQ/DQS : PASS
9068 12:48:03.212262 RX DATLAT : PASS
9069 12:48:03.215265 RX DQ/DQS(Engine): PASS
9070 12:48:03.218505 TX OE : PASS
9071 12:48:03.218587 All Pass.
9072 12:48:03.218651
9073 12:48:03.218710 CH 0, Rank 1
9074 12:48:03.221792 SW Impedance : PASS
9075 12:48:03.225128 DUTY Scan : NO K
9076 12:48:03.225210 ZQ Calibration : PASS
9077 12:48:03.228612 Jitter Meter : NO K
9078 12:48:03.232185 CBT Training : PASS
9079 12:48:03.232265 Write leveling : PASS
9080 12:48:03.235243 RX DQS gating : PASS
9081 12:48:03.235323 RX DQ/DQS(RDDQC) : PASS
9082 12:48:03.238809 TX DQ/DQS : PASS
9083 12:48:03.241953 RX DATLAT : PASS
9084 12:48:03.242034 RX DQ/DQS(Engine): PASS
9085 12:48:03.244965 TX OE : PASS
9086 12:48:03.245045 All Pass.
9087 12:48:03.245109
9088 12:48:03.248834 CH 1, Rank 0
9089 12:48:03.248914 SW Impedance : PASS
9090 12:48:03.251760 DUTY Scan : NO K
9091 12:48:03.255485 ZQ Calibration : PASS
9092 12:48:03.255587 Jitter Meter : NO K
9093 12:48:03.258529 CBT Training : PASS
9094 12:48:03.261974 Write leveling : PASS
9095 12:48:03.262060 RX DQS gating : PASS
9096 12:48:03.265113 RX DQ/DQS(RDDQC) : PASS
9097 12:48:03.268757 TX DQ/DQS : PASS
9098 12:48:03.268839 RX DATLAT : PASS
9099 12:48:03.271720 RX DQ/DQS(Engine): PASS
9100 12:48:03.275298 TX OE : PASS
9101 12:48:03.275394 All Pass.
9102 12:48:03.275460
9103 12:48:03.275529 CH 1, Rank 1
9104 12:48:03.278906 SW Impedance : PASS
9105 12:48:03.281964 DUTY Scan : NO K
9106 12:48:03.282062 ZQ Calibration : PASS
9107 12:48:03.284910 Jitter Meter : NO K
9108 12:48:03.285011 CBT Training : PASS
9109 12:48:03.288343 Write leveling : PASS
9110 12:48:03.291897 RX DQS gating : PASS
9111 12:48:03.291979 RX DQ/DQS(RDDQC) : PASS
9112 12:48:03.294912 TX DQ/DQS : PASS
9113 12:48:03.298489 RX DATLAT : PASS
9114 12:48:03.298599 RX DQ/DQS(Engine): PASS
9115 12:48:03.302208 TX OE : PASS
9116 12:48:03.302303 All Pass.
9117 12:48:03.302398
9118 12:48:03.305099 DramC Write-DBI on
9119 12:48:03.308662 PER_BANK_REFRESH: Hybrid Mode
9120 12:48:03.308741 TX_TRACKING: ON
9121 12:48:03.318364 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9122 12:48:03.325236 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9123 12:48:03.332151 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9124 12:48:03.335397 [FAST_K] Save calibration result to emmc
9125 12:48:03.338237 sync common calibartion params.
9126 12:48:03.342160 sync cbt_mode0:1, 1:1
9127 12:48:03.345021 dram_init: ddr_geometry: 2
9128 12:48:03.345105 dram_init: ddr_geometry: 2
9129 12:48:03.348378 dram_init: ddr_geometry: 2
9130 12:48:03.351573 0:dram_rank_size:100000000
9131 12:48:03.354808 1:dram_rank_size:100000000
9132 12:48:03.358408 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9133 12:48:03.361462 DFS_SHUFFLE_HW_MODE: ON
9134 12:48:03.365067 dramc_set_vcore_voltage set vcore to 725000
9135 12:48:03.368026 Read voltage for 1600, 0
9136 12:48:03.368141 Vio18 = 0
9137 12:48:03.368221 Vcore = 725000
9138 12:48:03.371666 Vdram = 0
9139 12:48:03.371784 Vddq = 0
9140 12:48:03.371886 Vmddr = 0
9141 12:48:03.374752 switch to 3200 Mbps bootup
9142 12:48:03.378376 [DramcRunTimeConfig]
9143 12:48:03.378484 PHYPLL
9144 12:48:03.378550 DPM_CONTROL_AFTERK: ON
9145 12:48:03.381429 PER_BANK_REFRESH: ON
9146 12:48:03.385157 REFRESH_OVERHEAD_REDUCTION: ON
9147 12:48:03.385237 CMD_PICG_NEW_MODE: OFF
9148 12:48:03.388171 XRTWTW_NEW_MODE: ON
9149 12:48:03.391246 XRTRTR_NEW_MODE: ON
9150 12:48:03.391343 TX_TRACKING: ON
9151 12:48:03.394715 RDSEL_TRACKING: OFF
9152 12:48:03.394796 DQS Precalculation for DVFS: ON
9153 12:48:03.398124 RX_TRACKING: OFF
9154 12:48:03.398221 HW_GATING DBG: ON
9155 12:48:03.401659 ZQCS_ENABLE_LP4: ON
9156 12:48:03.401756 RX_PICG_NEW_MODE: ON
9157 12:48:03.404768 TX_PICG_NEW_MODE: ON
9158 12:48:03.408186 ENABLE_RX_DCM_DPHY: ON
9159 12:48:03.411579 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9160 12:48:03.411693 DUMMY_READ_FOR_TRACKING: OFF
9161 12:48:03.414779 !!! SPM_CONTROL_AFTERK: OFF
9162 12:48:03.418218 !!! SPM could not control APHY
9163 12:48:03.421280 IMPEDANCE_TRACKING: ON
9164 12:48:03.421377 TEMP_SENSOR: ON
9165 12:48:03.424922 HW_SAVE_FOR_SR: OFF
9166 12:48:03.425021 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9167 12:48:03.431171 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9168 12:48:03.431289 Read ODT Tracking: ON
9169 12:48:03.434576 Refresh Rate DeBounce: ON
9170 12:48:03.434660 DFS_NO_QUEUE_FLUSH: ON
9171 12:48:03.438116 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9172 12:48:03.441446 ENABLE_DFS_RUNTIME_MRW: OFF
9173 12:48:03.445117 DDR_RESERVE_NEW_MODE: ON
9174 12:48:03.445200 MR_CBT_SWITCH_FREQ: ON
9175 12:48:03.448170 =========================
9176 12:48:03.467168 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9177 12:48:03.470779 dram_init: ddr_geometry: 2
9178 12:48:03.488842 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9179 12:48:03.491913 dram_init: dram init end (result: 0)
9180 12:48:03.499112 DRAM-K: Full calibration passed in 24419 msecs
9181 12:48:03.501992 MRC: failed to locate region type 0.
9182 12:48:03.502086 DRAM rank0 size:0x100000000,
9183 12:48:03.505458 DRAM rank1 size=0x100000000
9184 12:48:03.515258 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9185 12:48:03.521950 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9186 12:48:03.528629 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9187 12:48:03.535401 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9188 12:48:03.538894 DRAM rank0 size:0x100000000,
9189 12:48:03.541817 DRAM rank1 size=0x100000000
9190 12:48:03.541931 CBMEM:
9191 12:48:03.545310 IMD: root @ 0xfffff000 254 entries.
9192 12:48:03.548627 IMD: root @ 0xffffec00 62 entries.
9193 12:48:03.552307 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9194 12:48:03.555228 WARNING: RO_VPD is uninitialized or empty.
9195 12:48:03.561899 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9196 12:48:03.569031 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9197 12:48:03.581752 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9198 12:48:03.593320 BS: romstage times (exec / console): total (unknown) / 23958 ms
9199 12:48:03.593405
9200 12:48:03.593490
9201 12:48:03.602899 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9202 12:48:03.606513 ARM64: Exception handlers installed.
9203 12:48:03.609883 ARM64: Testing exception
9204 12:48:03.612975 ARM64: Done test exception
9205 12:48:03.613059 Enumerating buses...
9206 12:48:03.616521 Show all devs... Before device enumeration.
9207 12:48:03.619593 Root Device: enabled 1
9208 12:48:03.623096 CPU_CLUSTER: 0: enabled 1
9209 12:48:03.623193 CPU: 00: enabled 1
9210 12:48:03.626111 Compare with tree...
9211 12:48:03.626207 Root Device: enabled 1
9212 12:48:03.629854 CPU_CLUSTER: 0: enabled 1
9213 12:48:03.632940 CPU: 00: enabled 1
9214 12:48:03.633037 Root Device scanning...
9215 12:48:03.636655 scan_static_bus for Root Device
9216 12:48:03.639699 CPU_CLUSTER: 0 enabled
9217 12:48:03.642675 scan_static_bus for Root Device done
9218 12:48:03.646300 scan_bus: bus Root Device finished in 8 msecs
9219 12:48:03.646397 done
9220 12:48:03.653369 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9221 12:48:03.656496 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9222 12:48:03.662674 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9223 12:48:03.666200 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9224 12:48:03.669643 Allocating resources...
9225 12:48:03.669739 Reading resources...
9226 12:48:03.676290 Root Device read_resources bus 0 link: 0
9227 12:48:03.676371 DRAM rank0 size:0x100000000,
9228 12:48:03.679897 DRAM rank1 size=0x100000000
9229 12:48:03.682984 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9230 12:48:03.685981 CPU: 00 missing read_resources
9231 12:48:03.689490 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9232 12:48:03.696238 Root Device read_resources bus 0 link: 0 done
9233 12:48:03.696322 Done reading resources.
9234 12:48:03.702906 Show resources in subtree (Root Device)...After reading.
9235 12:48:03.705971 Root Device child on link 0 CPU_CLUSTER: 0
9236 12:48:03.709138 CPU_CLUSTER: 0 child on link 0 CPU: 00
9237 12:48:03.719155 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9238 12:48:03.719236 CPU: 00
9239 12:48:03.723015 Root Device assign_resources, bus 0 link: 0
9240 12:48:03.725932 CPU_CLUSTER: 0 missing set_resources
9241 12:48:03.729519 Root Device assign_resources, bus 0 link: 0 done
9242 12:48:03.732353 Done setting resources.
9243 12:48:03.739491 Show resources in subtree (Root Device)...After assigning values.
9244 12:48:03.742564 Root Device child on link 0 CPU_CLUSTER: 0
9245 12:48:03.746122 CPU_CLUSTER: 0 child on link 0 CPU: 00
9246 12:48:03.755953 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9247 12:48:03.756042 CPU: 00
9248 12:48:03.758969 Done allocating resources.
9249 12:48:03.762395 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9250 12:48:03.765667 Enabling resources...
9251 12:48:03.765779 done.
9252 12:48:03.772379 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9253 12:48:03.772462 Initializing devices...
9254 12:48:03.775681 Root Device init
9255 12:48:03.775761 init hardware done!
9256 12:48:03.779144 0x00000018: ctrlr->caps
9257 12:48:03.782053 52.000 MHz: ctrlr->f_max
9258 12:48:03.782136 0.400 MHz: ctrlr->f_min
9259 12:48:03.785493 0x40ff8080: ctrlr->voltages
9260 12:48:03.785576 sclk: 390625
9261 12:48:03.788720 Bus Width = 1
9262 12:48:03.788801 sclk: 390625
9263 12:48:03.792183 Bus Width = 1
9264 12:48:03.792264 Early init status = 3
9265 12:48:03.798920 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9266 12:48:03.801861 in-header: 03 fc 00 00 01 00 00 00
9267 12:48:03.805467 in-data: 00
9268 12:48:03.808590 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9269 12:48:03.813523 in-header: 03 fd 00 00 00 00 00 00
9270 12:48:03.816542 in-data:
9271 12:48:03.819963 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9272 12:48:03.824152 in-header: 03 fc 00 00 01 00 00 00
9273 12:48:03.827854 in-data: 00
9274 12:48:03.830825 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9275 12:48:03.836739 in-header: 03 fd 00 00 00 00 00 00
9276 12:48:03.839710 in-data:
9277 12:48:03.843361 [SSUSB] Setting up USB HOST controller...
9278 12:48:03.846398 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9279 12:48:03.849460 [SSUSB] phy power-on done.
9280 12:48:03.853101 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9281 12:48:03.859871 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9282 12:48:03.862947 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9283 12:48:03.869633 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9284 12:48:03.876062 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9285 12:48:03.883387 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9286 12:48:03.890063 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9287 12:48:03.896199 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9288 12:48:03.899691 SPM: binary array size = 0x9dc
9289 12:48:03.903186 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9290 12:48:03.909973 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9291 12:48:03.916624 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9292 12:48:03.919724 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9293 12:48:03.926367 configure_display: Starting display init
9294 12:48:03.959907 anx7625_power_on_init: Init interface.
9295 12:48:03.962914 anx7625_disable_pd_protocol: Disabled PD feature.
9296 12:48:03.966605 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9297 12:48:03.994020 anx7625_start_dp_work: Secure OCM version=00
9298 12:48:03.997784 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9299 12:48:04.012511 sp_tx_get_edid_block: EDID Block = 1
9300 12:48:04.114913 Extracted contents:
9301 12:48:04.117922 header: 00 ff ff ff ff ff ff 00
9302 12:48:04.121353 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9303 12:48:04.124569 version: 01 04
9304 12:48:04.128394 basic params: 95 1f 11 78 0a
9305 12:48:04.131427 chroma info: 76 90 94 55 54 90 27 21 50 54
9306 12:48:04.134430 established: 00 00 00
9307 12:48:04.141075 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9308 12:48:04.144642 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9309 12:48:04.151409 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9310 12:48:04.157949 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9311 12:48:04.164700 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9312 12:48:04.167669 extensions: 00
9313 12:48:04.167747 checksum: fb
9314 12:48:04.167825
9315 12:48:04.171411 Manufacturer: IVO Model 57d Serial Number 0
9316 12:48:04.174526 Made week 0 of 2020
9317 12:48:04.174638 EDID version: 1.4
9318 12:48:04.177665 Digital display
9319 12:48:04.180856 6 bits per primary color channel
9320 12:48:04.181028 DisplayPort interface
9321 12:48:04.184351 Maximum image size: 31 cm x 17 cm
9322 12:48:04.187960 Gamma: 220%
9323 12:48:04.188065 Check DPMS levels
9324 12:48:04.190884 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9325 12:48:04.197479 First detailed timing is preferred timing
9326 12:48:04.197558 Established timings supported:
9327 12:48:04.201090 Standard timings supported:
9328 12:48:04.204212 Detailed timings
9329 12:48:04.207919 Hex of detail: 383680a07038204018303c0035ae10000019
9330 12:48:04.210901 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9331 12:48:04.217588 0780 0798 07c8 0820 hborder 0
9332 12:48:04.220594 0438 043b 0447 0458 vborder 0
9333 12:48:04.224340 -hsync -vsync
9334 12:48:04.224417 Did detailed timing
9335 12:48:04.231034 Hex of detail: 000000000000000000000000000000000000
9336 12:48:04.231149 Manufacturer-specified data, tag 0
9337 12:48:04.237378 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9338 12:48:04.240382 ASCII string: InfoVision
9339 12:48:04.244120 Hex of detail: 000000fe00523134304e574635205248200a
9340 12:48:04.247290 ASCII string: R140NWF5 RH
9341 12:48:04.247400 Checksum
9342 12:48:04.250911 Checksum: 0xfb (valid)
9343 12:48:04.253842 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9344 12:48:04.257433 DSI data_rate: 832800000 bps
9345 12:48:04.264221 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9346 12:48:04.267223 anx7625_parse_edid: pixelclock(138800).
9347 12:48:04.270589 hactive(1920), hsync(48), hfp(24), hbp(88)
9348 12:48:04.274290 vactive(1080), vsync(12), vfp(3), vbp(17)
9349 12:48:04.277115 anx7625_dsi_config: config dsi.
9350 12:48:04.284061 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9351 12:48:04.296638 anx7625_dsi_config: success to config DSI
9352 12:48:04.300237 anx7625_dp_start: MIPI phy setup OK.
9353 12:48:04.303402 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9354 12:48:04.307084 mtk_ddp_mode_set invalid vrefresh 60
9355 12:48:04.310256 main_disp_path_setup
9356 12:48:04.310386 ovl_layer_smi_id_en
9357 12:48:04.313211 ovl_layer_smi_id_en
9358 12:48:04.313285 ccorr_config
9359 12:48:04.313353 aal_config
9360 12:48:04.316888 gamma_config
9361 12:48:04.316974 postmask_config
9362 12:48:04.319923 dither_config
9363 12:48:04.323528 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9364 12:48:04.329811 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9365 12:48:04.333348 Root Device init finished in 554 msecs
9366 12:48:04.333428 CPU_CLUSTER: 0 init
9367 12:48:04.343369 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9368 12:48:04.346864 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9369 12:48:04.349855 APU_MBOX 0x190000b0 = 0x10001
9370 12:48:04.353511 APU_MBOX 0x190001b0 = 0x10001
9371 12:48:04.356512 APU_MBOX 0x190005b0 = 0x10001
9372 12:48:04.360041 APU_MBOX 0x190006b0 = 0x10001
9373 12:48:04.362983 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9374 12:48:04.375999 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9375 12:48:04.387896 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9376 12:48:04.394451 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9377 12:48:04.406328 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9378 12:48:04.415668 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9379 12:48:04.418637 CPU_CLUSTER: 0 init finished in 81 msecs
9380 12:48:04.422227 Devices initialized
9381 12:48:04.425327 Show all devs... After init.
9382 12:48:04.425432 Root Device: enabled 1
9383 12:48:04.428486 CPU_CLUSTER: 0: enabled 1
9384 12:48:04.432067 CPU: 00: enabled 1
9385 12:48:04.435651 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9386 12:48:04.438756 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9387 12:48:04.441834 ELOG: NV offset 0x57f000 size 0x1000
9388 12:48:04.449092 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9389 12:48:04.455509 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9390 12:48:04.458540 ELOG: Event(17) added with size 13 at 2023-07-20 12:47:34 UTC
9391 12:48:04.465399 out: cmd=0x121: 03 db 21 01 00 00 00 00
9392 12:48:04.468365 in-header: 03 fe 00 00 2c 00 00 00
9393 12:48:04.478406 in-data: 61 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9394 12:48:04.485061 ELOG: Event(A1) added with size 10 at 2023-07-20 12:47:34 UTC
9395 12:48:04.492093 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9396 12:48:04.498316 ELOG: Event(A0) added with size 9 at 2023-07-20 12:47:34 UTC
9397 12:48:04.501804 elog_add_boot_reason: Logged dev mode boot
9398 12:48:04.505341 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9399 12:48:04.508346 Finalize devices...
9400 12:48:04.511547 Devices finalized
9401 12:48:04.515225 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9402 12:48:04.518323 Writing coreboot table at 0xffe64000
9403 12:48:04.521392 0. 000000000010a000-0000000000113fff: RAMSTAGE
9404 12:48:04.524853 1. 0000000040000000-00000000400fffff: RAM
9405 12:48:04.531642 2. 0000000040100000-000000004032afff: RAMSTAGE
9406 12:48:04.534788 3. 000000004032b000-00000000545fffff: RAM
9407 12:48:04.538486 4. 0000000054600000-000000005465ffff: BL31
9408 12:48:04.541462 5. 0000000054660000-00000000ffe63fff: RAM
9409 12:48:04.548320 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9410 12:48:04.551268 7. 0000000100000000-000000023fffffff: RAM
9411 12:48:04.554830 Passing 5 GPIOs to payload:
9412 12:48:04.558207 NAME | PORT | POLARITY | VALUE
9413 12:48:04.561492 EC in RW | 0x000000aa | low | undefined
9414 12:48:04.568158 EC interrupt | 0x00000005 | low | undefined
9415 12:48:04.571639 TPM interrupt | 0x000000ab | high | undefined
9416 12:48:04.578100 SD card detect | 0x00000011 | high | undefined
9417 12:48:04.581573 speaker enable | 0x00000093 | high | undefined
9418 12:48:04.584723 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9419 12:48:04.587796 in-header: 03 f9 00 00 02 00 00 00
9420 12:48:04.591433 in-data: 02 00
9421 12:48:04.591584 ADC[4]: Raw value=904357 ID=7
9422 12:48:04.594564 ADC[3]: Raw value=213441 ID=1
9423 12:48:04.598173 RAM Code: 0x71
9424 12:48:04.598278 ADC[6]: Raw value=75332 ID=0
9425 12:48:04.601118 ADC[5]: Raw value=213072 ID=1
9426 12:48:04.604624 SKU Code: 0x1
9427 12:48:04.607860 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5298
9428 12:48:04.611235 coreboot table: 964 bytes.
9429 12:48:04.614409 IMD ROOT 0. 0xfffff000 0x00001000
9430 12:48:04.617778 IMD SMALL 1. 0xffffe000 0x00001000
9431 12:48:04.621356 RO MCACHE 2. 0xffffc000 0x00001104
9432 12:48:04.624502 CONSOLE 3. 0xfff7c000 0x00080000
9433 12:48:04.627992 FMAP 4. 0xfff7b000 0x00000452
9434 12:48:04.630953 TIME STAMP 5. 0xfff7a000 0x00000910
9435 12:48:04.634675 VBOOT WORK 6. 0xfff66000 0x00014000
9436 12:48:04.637608 RAMOOPS 7. 0xffe66000 0x00100000
9437 12:48:04.641266 COREBOOT 8. 0xffe64000 0x00002000
9438 12:48:04.641372 IMD small region:
9439 12:48:04.644349 IMD ROOT 0. 0xffffec00 0x00000400
9440 12:48:04.647980 VPD 1. 0xffffeba0 0x0000004c
9441 12:48:04.654806 MMC STATUS 2. 0xffffeb80 0x00000004
9442 12:48:04.657957 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9443 12:48:04.661066 Probing TPM: done!
9444 12:48:04.664601 Connected to device vid:did:rid of 1ae0:0028:00
9445 12:48:04.674566 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9446 12:48:04.677975 Initialized TPM device CR50 revision 0
9447 12:48:04.682442 Checking cr50 for pending updates
9448 12:48:04.685236 Reading cr50 TPM mode
9449 12:48:04.693902 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9450 12:48:04.700538 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9451 12:48:04.740803 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9452 12:48:04.743886 Checking segment from ROM address 0x40100000
9453 12:48:04.747453 Checking segment from ROM address 0x4010001c
9454 12:48:04.753758 Loading segment from ROM address 0x40100000
9455 12:48:04.753874 code (compression=0)
9456 12:48:04.763699 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9457 12:48:04.770493 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9458 12:48:04.770598 it's not compressed!
9459 12:48:04.777275 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9460 12:48:04.780782 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9461 12:48:04.801375 Loading segment from ROM address 0x4010001c
9462 12:48:04.801463 Entry Point 0x80000000
9463 12:48:04.804436 Loaded segments
9464 12:48:04.807504 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9465 12:48:04.814273 Jumping to boot code at 0x80000000(0xffe64000)
9466 12:48:04.821011 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9467 12:48:04.827805 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9468 12:48:04.835372 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9469 12:48:04.838651 Checking segment from ROM address 0x40100000
9470 12:48:04.842047 Checking segment from ROM address 0x4010001c
9471 12:48:04.848891 Loading segment from ROM address 0x40100000
9472 12:48:04.848992 code (compression=1)
9473 12:48:04.855655 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9474 12:48:04.864882 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9475 12:48:04.864976 using LZMA
9476 12:48:04.873731 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9477 12:48:04.880737 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9478 12:48:04.883761 Loading segment from ROM address 0x4010001c
9479 12:48:04.883851 Entry Point 0x54601000
9480 12:48:04.887201 Loaded segments
9481 12:48:04.890248 NOTICE: MT8192 bl31_setup
9482 12:48:04.897576 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9483 12:48:04.900914 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9484 12:48:04.904414 WARNING: region 0:
9485 12:48:04.907536 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9486 12:48:04.907626 WARNING: region 1:
9487 12:48:04.913997 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9488 12:48:04.917614 WARNING: region 2:
9489 12:48:04.920608 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9490 12:48:04.924253 WARNING: region 3:
9491 12:48:04.927340 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9492 12:48:04.931072 WARNING: region 4:
9493 12:48:04.934111 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9494 12:48:04.937704 WARNING: region 5:
9495 12:48:04.941189 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 12:48:04.944222 WARNING: region 6:
9497 12:48:04.947823 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9498 12:48:04.947919 WARNING: region 7:
9499 12:48:04.954505 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9500 12:48:04.960883 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9501 12:48:04.964408 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9502 12:48:04.967958 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9503 12:48:04.974779 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9504 12:48:04.977880 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9505 12:48:04.980951 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9506 12:48:04.987868 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9507 12:48:04.991227 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9508 12:48:04.994679 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9509 12:48:05.001435 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9510 12:48:05.004496 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9511 12:48:05.008041 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9512 12:48:05.014417 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9513 12:48:05.017784 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9514 12:48:05.024618 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9515 12:48:05.028278 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9516 12:48:05.031401 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9517 12:48:05.038107 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9518 12:48:05.041219 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9519 12:48:05.044853 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9520 12:48:05.051483 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9521 12:48:05.054530 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9522 12:48:05.061436 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9523 12:48:05.064436 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9524 12:48:05.068235 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9525 12:48:05.074425 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9526 12:48:05.078144 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9527 12:48:05.084967 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9528 12:48:05.088053 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9529 12:48:05.091126 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9530 12:48:05.097853 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9531 12:48:05.101242 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9532 12:48:05.105000 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9533 12:48:05.111099 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9534 12:48:05.114809 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9535 12:48:05.118264 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9536 12:48:05.121616 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9537 12:48:05.128073 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9538 12:48:05.131426 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9539 12:48:05.134720 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9540 12:48:05.138133 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9541 12:48:05.141204 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9542 12:48:05.147943 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9543 12:48:05.151468 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9544 12:48:05.155075 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9545 12:48:05.161226 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9546 12:48:05.164908 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9547 12:48:05.168401 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9548 12:48:05.171483 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9549 12:48:05.178362 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9550 12:48:05.181368 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9551 12:48:05.188093 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9552 12:48:05.191734 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9553 12:48:05.198369 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9554 12:48:05.201903 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9555 12:48:05.204941 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9556 12:48:05.211463 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9557 12:48:05.215188 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9558 12:48:05.221968 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9559 12:48:05.224856 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9560 12:48:05.231852 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9561 12:48:05.235418 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9562 12:48:05.238429 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9563 12:48:05.244992 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9564 12:48:05.248526 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9565 12:48:05.255090 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9566 12:48:05.258604 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9567 12:48:05.265249 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9568 12:48:05.268378 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9569 12:48:05.271884 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9570 12:48:05.278562 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9571 12:48:05.281531 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9572 12:48:05.288408 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9573 12:48:05.292207 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9574 12:48:05.298361 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9575 12:48:05.302077 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9576 12:48:05.305218 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9577 12:48:05.311843 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9578 12:48:05.315585 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9579 12:48:05.322283 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9580 12:48:05.325344 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9581 12:48:05.331750 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9582 12:48:05.335263 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9583 12:48:05.338575 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9584 12:48:05.345535 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9585 12:48:05.348586 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9586 12:48:05.355730 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9587 12:48:05.358604 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9588 12:48:05.362222 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9589 12:48:05.368973 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9590 12:48:05.372047 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9591 12:48:05.378623 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9592 12:48:05.382358 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9593 12:48:05.389063 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9594 12:48:05.392535 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9595 12:48:05.398841 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9596 12:48:05.402502 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9597 12:48:05.405415 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9598 12:48:05.409219 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9599 12:48:05.412255 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9600 12:48:05.419036 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9601 12:48:05.422117 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9602 12:48:05.428946 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9603 12:48:05.432772 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9604 12:48:05.435754 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9605 12:48:05.442336 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9606 12:48:05.445843 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9607 12:48:05.452294 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9608 12:48:05.455837 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9609 12:48:05.459356 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9610 12:48:05.465756 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9611 12:48:05.469105 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9612 12:48:05.472599 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9613 12:48:05.479051 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9614 12:48:05.482661 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9615 12:48:05.489493 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9616 12:48:05.492574 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9617 12:48:05.495535 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9618 12:48:05.502534 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9619 12:48:05.506082 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9620 12:48:05.509062 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9621 12:48:05.512571 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9622 12:48:05.515610 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9623 12:48:05.522457 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9624 12:48:05.526048 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9625 12:48:05.532944 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9626 12:48:05.535941 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9627 12:48:05.539036 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9628 12:48:05.545776 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9629 12:48:05.549326 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9630 12:48:05.552544 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9631 12:48:05.559083 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9632 12:48:05.562536 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9633 12:48:05.569145 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9634 12:48:05.572612 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9635 12:48:05.576122 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9636 12:48:05.582891 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9637 12:48:05.585877 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9638 12:48:05.589594 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9639 12:48:05.595804 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9640 12:48:05.599512 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9641 12:48:05.606536 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9642 12:48:05.609487 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9643 12:48:05.612673 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9644 12:48:05.619361 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9645 12:48:05.623172 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9646 12:48:05.626318 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9647 12:48:05.632703 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9648 12:48:05.636517 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9649 12:48:05.643207 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9650 12:48:05.646406 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9651 12:48:05.649297 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9652 12:48:05.656234 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9653 12:48:05.659293 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9654 12:48:05.666034 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9655 12:48:05.669771 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9656 12:48:05.673110 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9657 12:48:05.679446 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9658 12:48:05.682671 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9659 12:48:05.689482 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9660 12:48:05.693069 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9661 12:48:05.696388 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9662 12:48:05.702852 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9663 12:48:05.705960 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9664 12:48:05.712749 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9665 12:48:05.715853 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9666 12:48:05.718917 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9667 12:48:05.725986 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9668 12:48:05.729387 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9669 12:48:05.735915 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9670 12:48:05.739444 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9671 12:48:05.742428 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9672 12:48:05.749211 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9673 12:48:05.752244 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9674 12:48:05.755653 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9675 12:48:05.762330 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9676 12:48:05.765513 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9677 12:48:05.772394 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9678 12:48:05.775437 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9679 12:48:05.778453 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9680 12:48:05.785237 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9681 12:48:05.788337 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9682 12:48:05.795036 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9683 12:48:05.798452 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9684 12:48:05.801823 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9685 12:48:05.808438 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9686 12:48:05.811899 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9687 12:48:05.818368 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9688 12:48:05.822115 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9689 12:48:05.825144 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9690 12:48:05.831936 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9691 12:48:05.835104 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9692 12:48:05.841871 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9693 12:48:05.845253 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9694 12:48:05.851871 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9695 12:48:05.854931 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9696 12:48:05.858602 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9697 12:48:05.864929 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9698 12:48:05.868219 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9699 12:48:05.875079 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9700 12:48:05.877906 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9701 12:48:05.881620 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9702 12:48:05.888561 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9703 12:48:05.891362 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9704 12:48:05.898127 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9705 12:48:05.901336 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9706 12:48:05.908073 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9707 12:48:05.911504 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9708 12:48:05.914322 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9709 12:48:05.921177 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9710 12:48:05.924379 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9711 12:48:05.931394 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9712 12:48:05.934741 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9713 12:48:05.937829 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9714 12:48:05.944351 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9715 12:48:05.947754 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9716 12:48:05.954678 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9717 12:48:05.957813 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9718 12:48:05.964547 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9719 12:48:05.967968 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9720 12:48:05.971005 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9721 12:48:05.977951 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9722 12:48:05.981041 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9723 12:48:05.987716 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9724 12:48:05.991393 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9725 12:48:05.994439 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9726 12:48:06.001384 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9727 12:48:06.004358 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9728 12:48:06.011124 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9729 12:48:06.014287 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9730 12:48:06.018014 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9731 12:48:06.021022 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9732 12:48:06.024797 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9733 12:48:06.031170 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9734 12:48:06.034505 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9735 12:48:06.041175 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9736 12:48:06.044359 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9737 12:48:06.047884 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9738 12:48:06.050968 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9739 12:48:06.057973 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9740 12:48:06.061261 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9741 12:48:06.067545 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9742 12:48:06.071106 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9743 12:48:06.074595 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9744 12:48:06.081486 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9745 12:48:06.084335 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9746 12:48:06.091144 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9747 12:48:06.094285 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9748 12:48:06.097679 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9749 12:48:06.104584 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9750 12:48:06.107632 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9751 12:48:06.111278 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9752 12:48:06.117503 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9753 12:48:06.121303 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9754 12:48:06.124462 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9755 12:48:06.131047 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9756 12:48:06.134512 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9757 12:48:06.141134 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9758 12:48:06.144316 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9759 12:48:06.147337 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9760 12:48:06.153877 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9761 12:48:06.157656 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9762 12:48:06.160641 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9763 12:48:06.167289 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9764 12:48:06.170712 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9765 12:48:06.174020 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9766 12:48:06.180715 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9767 12:48:06.184466 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9768 12:48:06.187460 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9769 12:48:06.194318 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9770 12:48:06.197356 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9771 12:48:06.200901 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9772 12:48:06.204021 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9773 12:48:06.207295 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9774 12:48:06.214151 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9775 12:48:06.217206 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9776 12:48:06.220929 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9777 12:48:06.227758 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9778 12:48:06.230767 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9779 12:48:06.234381 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9780 12:48:06.237492 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9781 12:48:06.244041 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9782 12:48:06.247223 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9783 12:48:06.253962 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9784 12:48:06.257638 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9785 12:48:06.260868 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9786 12:48:06.267111 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9787 12:48:06.270822 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9788 12:48:06.277105 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9789 12:48:06.280895 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9790 12:48:06.283760 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9791 12:48:06.290716 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9792 12:48:06.293791 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9793 12:48:06.300800 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9794 12:48:06.303912 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9795 12:48:06.307399 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9796 12:48:06.313440 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9797 12:48:06.317200 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9798 12:48:06.323778 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9799 12:48:06.326742 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9800 12:48:06.330455 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9801 12:48:06.337015 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9802 12:48:06.340276 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9803 12:48:06.346621 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9804 12:48:06.350327 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9805 12:48:06.353459 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9806 12:48:06.359947 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9807 12:48:06.363597 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9808 12:48:06.370068 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9809 12:48:06.373028 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9810 12:48:06.379752 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9811 12:48:06.383231 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9812 12:48:06.386355 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9813 12:48:06.393168 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9814 12:48:06.396704 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9815 12:48:06.403101 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9816 12:48:06.406317 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9817 12:48:06.409673 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9818 12:48:06.416578 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9819 12:48:06.420175 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9820 12:48:06.426899 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9821 12:48:06.430069 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9822 12:48:06.433701 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9823 12:48:06.439827 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9824 12:48:06.443492 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9825 12:48:06.450056 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9826 12:48:06.453683 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9827 12:48:06.456592 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9828 12:48:06.463560 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9829 12:48:06.466641 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9830 12:48:06.473356 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9831 12:48:06.476416 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9832 12:48:06.480133 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9833 12:48:06.486612 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9834 12:48:06.490182 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9835 12:48:06.496738 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9836 12:48:06.500047 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9837 12:48:06.503258 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9838 12:48:06.510200 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9839 12:48:06.513288 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9840 12:48:06.519686 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9841 12:48:06.523078 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9842 12:48:06.529975 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9843 12:48:06.532951 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9844 12:48:06.536774 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9845 12:48:06.543499 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9846 12:48:06.546551 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9847 12:48:06.550194 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9848 12:48:06.557072 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9849 12:48:06.559752 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9850 12:48:06.566337 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9851 12:48:06.569922 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9852 12:48:06.576818 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9853 12:48:06.579793 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9854 12:48:06.583425 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9855 12:48:06.590107 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9856 12:48:06.593117 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9857 12:48:06.599903 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9858 12:48:06.603234 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9859 12:48:06.609803 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9860 12:48:06.613485 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9861 12:48:06.616622 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9862 12:48:06.623212 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9863 12:48:06.626647 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9864 12:48:06.633172 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9865 12:48:06.636548 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9866 12:48:06.642918 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9867 12:48:06.646033 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9868 12:48:06.652635 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9869 12:48:06.656392 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9870 12:48:06.659421 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9871 12:48:06.665842 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9872 12:48:06.669388 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9873 12:48:06.675793 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9874 12:48:06.679413 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9875 12:48:06.686221 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9876 12:48:06.689249 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9877 12:48:06.693021 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9878 12:48:06.699557 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9879 12:48:06.702782 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9880 12:48:06.709490 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9881 12:48:06.712584 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9882 12:48:06.715528 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9883 12:48:06.722342 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9884 12:48:06.726202 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9885 12:48:06.732449 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9886 12:48:06.735795 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9887 12:48:06.742718 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9888 12:48:06.745895 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9889 12:48:06.752509 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9890 12:48:06.756180 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9891 12:48:06.759143 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9892 12:48:06.765882 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9893 12:48:06.769337 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9894 12:48:06.776001 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9895 12:48:06.779597 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9896 12:48:06.785663 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9897 12:48:06.789305 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9898 12:48:06.792422 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9899 12:48:06.799197 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9900 12:48:06.802366 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9901 12:48:06.808917 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9902 12:48:06.812692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9903 12:48:06.815972 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9904 12:48:06.822674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9905 12:48:06.825812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9906 12:48:06.832315 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9907 12:48:06.835715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9908 12:48:06.842619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9909 12:48:06.845904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9910 12:48:06.852588 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9911 12:48:06.855915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9912 12:48:06.862271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9913 12:48:06.865527 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9914 12:48:06.872645 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9915 12:48:06.875948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9916 12:48:06.882563 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9917 12:48:06.885655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9918 12:48:06.889232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9919 12:48:06.895950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9920 12:48:06.899033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9921 12:48:06.905803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9922 12:48:06.909478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9923 12:48:06.915683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9924 12:48:06.919345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9925 12:48:06.926000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9926 12:48:06.928994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9927 12:48:06.935932 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9928 12:48:06.938929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9929 12:48:06.946074 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9930 12:48:06.949254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9931 12:48:06.955733 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9932 12:48:06.959130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9933 12:48:06.965903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9934 12:48:06.968897 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9935 12:48:06.972439 INFO: [APUAPC] vio 0
9936 12:48:06.975649 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9937 12:48:06.982316 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9938 12:48:06.985558 INFO: [APUAPC] D0_APC_0: 0x400510
9939 12:48:06.988872 INFO: [APUAPC] D0_APC_1: 0x0
9940 12:48:06.991971 INFO: [APUAPC] D0_APC_2: 0x1540
9941 12:48:06.992390 INFO: [APUAPC] D0_APC_3: 0x0
9942 12:48:06.995684 INFO: [APUAPC] D1_APC_0: 0xffffffff
9943 12:48:06.998951 INFO: [APUAPC] D1_APC_1: 0xffffffff
9944 12:48:07.001833 INFO: [APUAPC] D1_APC_2: 0x3fffff
9945 12:48:07.005422 INFO: [APUAPC] D1_APC_3: 0x0
9946 12:48:07.008396 INFO: [APUAPC] D2_APC_0: 0xffffffff
9947 12:48:07.012074 INFO: [APUAPC] D2_APC_1: 0xffffffff
9948 12:48:07.015037 INFO: [APUAPC] D2_APC_2: 0x3fffff
9949 12:48:07.018171 INFO: [APUAPC] D2_APC_3: 0x0
9950 12:48:07.021935 INFO: [APUAPC] D3_APC_0: 0xffffffff
9951 12:48:07.024792 INFO: [APUAPC] D3_APC_1: 0xffffffff
9952 12:48:07.028566 INFO: [APUAPC] D3_APC_2: 0x3fffff
9953 12:48:07.031509 INFO: [APUAPC] D3_APC_3: 0x0
9954 12:48:07.035261 INFO: [APUAPC] D4_APC_0: 0xffffffff
9955 12:48:07.038475 INFO: [APUAPC] D4_APC_1: 0xffffffff
9956 12:48:07.042139 INFO: [APUAPC] D4_APC_2: 0x3fffff
9957 12:48:07.045061 INFO: [APUAPC] D4_APC_3: 0x0
9958 12:48:07.048571 INFO: [APUAPC] D5_APC_0: 0xffffffff
9959 12:48:07.051569 INFO: [APUAPC] D5_APC_1: 0xffffffff
9960 12:48:07.054993 INFO: [APUAPC] D5_APC_2: 0x3fffff
9961 12:48:07.058376 INFO: [APUAPC] D5_APC_3: 0x0
9962 12:48:07.061427 INFO: [APUAPC] D6_APC_0: 0xffffffff
9963 12:48:07.065024 INFO: [APUAPC] D6_APC_1: 0xffffffff
9964 12:48:07.067996 INFO: [APUAPC] D6_APC_2: 0x3fffff
9965 12:48:07.071760 INFO: [APUAPC] D6_APC_3: 0x0
9966 12:48:07.074616 INFO: [APUAPC] D7_APC_0: 0xffffffff
9967 12:48:07.078262 INFO: [APUAPC] D7_APC_1: 0xffffffff
9968 12:48:07.081738 INFO: [APUAPC] D7_APC_2: 0x3fffff
9969 12:48:07.084759 INFO: [APUAPC] D7_APC_3: 0x0
9970 12:48:07.088471 INFO: [APUAPC] D8_APC_0: 0xffffffff
9971 12:48:07.091451 INFO: [APUAPC] D8_APC_1: 0xffffffff
9972 12:48:07.094862 INFO: [APUAPC] D8_APC_2: 0x3fffff
9973 12:48:07.098467 INFO: [APUAPC] D8_APC_3: 0x0
9974 12:48:07.101740 INFO: [APUAPC] D9_APC_0: 0xffffffff
9975 12:48:07.104985 INFO: [APUAPC] D9_APC_1: 0xffffffff
9976 12:48:07.108507 INFO: [APUAPC] D9_APC_2: 0x3fffff
9977 12:48:07.111551 INFO: [APUAPC] D9_APC_3: 0x0
9978 12:48:07.114801 INFO: [APUAPC] D10_APC_0: 0xffffffff
9979 12:48:07.118660 INFO: [APUAPC] D10_APC_1: 0xffffffff
9980 12:48:07.121620 INFO: [APUAPC] D10_APC_2: 0x3fffff
9981 12:48:07.124768 INFO: [APUAPC] D10_APC_3: 0x0
9982 12:48:07.128439 INFO: [APUAPC] D11_APC_0: 0xffffffff
9983 12:48:07.131472 INFO: [APUAPC] D11_APC_1: 0xffffffff
9984 12:48:07.135245 INFO: [APUAPC] D11_APC_2: 0x3fffff
9985 12:48:07.138207 INFO: [APUAPC] D11_APC_3: 0x0
9986 12:48:07.141778 INFO: [APUAPC] D12_APC_0: 0xffffffff
9987 12:48:07.144856 INFO: [APUAPC] D12_APC_1: 0xffffffff
9988 12:48:07.148647 INFO: [APUAPC] D12_APC_2: 0x3fffff
9989 12:48:07.151691 INFO: [APUAPC] D12_APC_3: 0x0
9990 12:48:07.155111 INFO: [APUAPC] D13_APC_0: 0xffffffff
9991 12:48:07.158170 INFO: [APUAPC] D13_APC_1: 0xffffffff
9992 12:48:07.161931 INFO: [APUAPC] D13_APC_2: 0x3fffff
9993 12:48:07.164918 INFO: [APUAPC] D13_APC_3: 0x0
9994 12:48:07.168592 INFO: [APUAPC] D14_APC_0: 0xffffffff
9995 12:48:07.171724 INFO: [APUAPC] D14_APC_1: 0xffffffff
9996 12:48:07.174676 INFO: [APUAPC] D14_APC_2: 0x3fffff
9997 12:48:07.178268 INFO: [APUAPC] D14_APC_3: 0x0
9998 12:48:07.181663 INFO: [APUAPC] D15_APC_0: 0xffffffff
9999 12:48:07.184944 INFO: [APUAPC] D15_APC_1: 0xffffffff
10000 12:48:07.188222 INFO: [APUAPC] D15_APC_2: 0x3fffff
10001 12:48:07.191420 INFO: [APUAPC] D15_APC_3: 0x0
10002 12:48:07.194728 INFO: [APUAPC] APC_CON: 0x4
10003 12:48:07.195244 INFO: [NOCDAPC] D0_APC_0: 0x0
10004 12:48:07.198283 INFO: [NOCDAPC] D0_APC_1: 0x0
10005 12:48:07.201301 INFO: [NOCDAPC] D1_APC_0: 0x0
10006 12:48:07.204430 INFO: [NOCDAPC] D1_APC_1: 0xfff
10007 12:48:07.208070 INFO: [NOCDAPC] D2_APC_0: 0x0
10008 12:48:07.211020 INFO: [NOCDAPC] D2_APC_1: 0xfff
10009 12:48:07.214415 INFO: [NOCDAPC] D3_APC_0: 0x0
10010 12:48:07.217624 INFO: [NOCDAPC] D3_APC_1: 0xfff
10011 12:48:07.221058 INFO: [NOCDAPC] D4_APC_0: 0x0
10012 12:48:07.224541 INFO: [NOCDAPC] D4_APC_1: 0xfff
10013 12:48:07.228026 INFO: [NOCDAPC] D5_APC_0: 0x0
10014 12:48:07.228572 INFO: [NOCDAPC] D5_APC_1: 0xfff
10015 12:48:07.231381 INFO: [NOCDAPC] D6_APC_0: 0x0
10016 12:48:07.234565 INFO: [NOCDAPC] D6_APC_1: 0xfff
10017 12:48:07.238298 INFO: [NOCDAPC] D7_APC_0: 0x0
10018 12:48:07.241247 INFO: [NOCDAPC] D7_APC_1: 0xfff
10019 12:48:07.244242 INFO: [NOCDAPC] D8_APC_0: 0x0
10020 12:48:07.248024 INFO: [NOCDAPC] D8_APC_1: 0xfff
10021 12:48:07.251089 INFO: [NOCDAPC] D9_APC_0: 0x0
10022 12:48:07.254594 INFO: [NOCDAPC] D9_APC_1: 0xfff
10023 12:48:07.257522 INFO: [NOCDAPC] D10_APC_0: 0x0
10024 12:48:07.261049 INFO: [NOCDAPC] D10_APC_1: 0xfff
10025 12:48:07.261496 INFO: [NOCDAPC] D11_APC_0: 0x0
10026 12:48:07.264609 INFO: [NOCDAPC] D11_APC_1: 0xfff
10027 12:48:07.267829 INFO: [NOCDAPC] D12_APC_0: 0x0
10028 12:48:07.270979 INFO: [NOCDAPC] D12_APC_1: 0xfff
10029 12:48:07.274672 INFO: [NOCDAPC] D13_APC_0: 0x0
10030 12:48:07.277731 INFO: [NOCDAPC] D13_APC_1: 0xfff
10031 12:48:07.281451 INFO: [NOCDAPC] D14_APC_0: 0x0
10032 12:48:07.284400 INFO: [NOCDAPC] D14_APC_1: 0xfff
10033 12:48:07.287716 INFO: [NOCDAPC] D15_APC_0: 0x0
10034 12:48:07.290911 INFO: [NOCDAPC] D15_APC_1: 0xfff
10035 12:48:07.294378 INFO: [NOCDAPC] APC_CON: 0x4
10036 12:48:07.297732 INFO: [APUAPC] set_apusys_apc done
10037 12:48:07.301336 INFO: [DEVAPC] devapc_init done
10038 12:48:07.304579 INFO: GICv3 without legacy support detected.
10039 12:48:07.307891 INFO: ARM GICv3 driver initialized in EL3
10040 12:48:07.311063 INFO: Maximum SPI INTID supported: 639
10041 12:48:07.314680 INFO: BL31: Initializing runtime services
10042 12:48:07.320774 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10043 12:48:07.324204 INFO: SPM: enable CPC mode
10044 12:48:07.330783 INFO: mcdi ready for mcusys-off-idle and system suspend
10045 12:48:07.334263 INFO: BL31: Preparing for EL3 exit to normal world
10046 12:48:07.337510 INFO: Entry point address = 0x80000000
10047 12:48:07.340553 INFO: SPSR = 0x8
10048 12:48:07.345413
10049 12:48:07.345567
10050 12:48:07.345689
10051 12:48:07.348513 Starting depthcharge on Spherion...
10052 12:48:07.348644
10053 12:48:07.348787 Wipe memory regions:
10054 12:48:07.348889
10055 12:48:07.350037 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10056 12:48:07.350242 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10057 12:48:07.350440 Setting prompt string to ['asurada:']
10058 12:48:07.351017 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10059 12:48:07.352132 [0x00000040000000, 0x00000054600000)
10060 12:48:07.474236
10061 12:48:07.474785 [0x00000054660000, 0x00000080000000)
10062 12:48:07.734527
10063 12:48:07.734680 [0x000000821a7280, 0x000000ffe64000)
10064 12:48:08.478470
10065 12:48:08.478600 [0x00000100000000, 0x00000240000000)
10066 12:48:10.364661
10067 12:48:10.368213 Initializing XHCI USB controller at 0x11200000.
10068 12:48:11.405292
10069 12:48:11.408436 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10070 12:48:11.408523
10071 12:48:11.408595
10072 12:48:11.408656
10073 12:48:11.408934 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10075 12:48:11.509250 asurada: tftpboot 192.168.201.1 11118924/tftp-deploy-pu23uz5a/kernel/image.itb 11118924/tftp-deploy-pu23uz5a/kernel/cmdline
10076 12:48:11.509425 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10077 12:48:11.509539 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10078 12:48:11.513881 tftpboot 192.168.201.1 11118924/tftp-deploy-pu23uz5a/kernel/image.ittp-deploy-pu23uz5a/kernel/cmdline
10079 12:48:11.513989
10080 12:48:11.514082 Waiting for link
10081 12:48:11.674521
10082 12:48:11.674680 R8152: Initializing
10083 12:48:11.674776
10084 12:48:11.677535 Version 9 (ocp_data = 6010)
10085 12:48:11.677611
10086 12:48:11.681237 R8152: Done initializing
10087 12:48:11.681334
10088 12:48:11.681429 Adding net device
10089 12:48:13.627417
10090 12:48:13.627649 done.
10091 12:48:13.627802
10092 12:48:13.627963 MAC: 00:e0:4c:78:7a:aa
10093 12:48:13.628104
10094 12:48:13.630696 Sending DHCP discover... done.
10095 12:48:13.630865
10096 12:48:13.633992 Waiting for reply... done.
10097 12:48:13.634116
10098 12:48:13.637216 Sending DHCP request... done.
10099 12:48:13.637349
10100 12:48:13.926911 Waiting for reply... done.
10101 12:48:13.927157
10102 12:48:13.927346 My ip is 192.168.201.12
10103 12:48:13.927486
10104 12:48:13.930461 The DHCP server ip is 192.168.201.1
10105 12:48:13.930682
10106 12:48:13.936493 TFTP server IP predefined by user: 192.168.201.1
10107 12:48:13.936716
10108 12:48:13.943737 Bootfile predefined by user: 11118924/tftp-deploy-pu23uz5a/kernel/image.itb
10109 12:48:13.943862
10110 12:48:13.943954 Sending tftp read request... done.
10111 12:48:13.946846
10112 12:48:13.950459 Waiting for the transfer...
10113 12:48:13.950582
10114 12:48:14.206395 00000000 ################################################################
10115 12:48:14.206545
10116 12:48:14.458625 00080000 ################################################################
10117 12:48:14.458753
10118 12:48:14.706978 00100000 ################################################################
10119 12:48:14.707110
10120 12:48:14.953436 00180000 ################################################################
10121 12:48:14.953575
10122 12:48:15.201338 00200000 ################################################################
10123 12:48:15.201477
10124 12:48:15.445545 00280000 ################################################################
10125 12:48:15.445684
10126 12:48:15.692916 00300000 ################################################################
10127 12:48:15.693050
10128 12:48:15.941437 00380000 ################################################################
10129 12:48:15.941608
10130 12:48:16.193075 00400000 ################################################################
10131 12:48:16.193214
10132 12:48:16.449091 00480000 ################################################################
10133 12:48:16.449230
10134 12:48:16.709705 00500000 ################################################################
10135 12:48:16.709843
10136 12:48:16.967127 00580000 ################################################################
10137 12:48:16.967288
10138 12:48:17.220125 00600000 ################################################################
10139 12:48:17.220260
10140 12:48:17.471117 00680000 ################################################################
10141 12:48:17.471282
10142 12:48:17.733559 00700000 ################################################################
10143 12:48:17.733726
10144 12:48:18.007637 00780000 ################################################################
10145 12:48:18.007772
10146 12:48:18.279434 00800000 ################################################################
10147 12:48:18.279621
10148 12:48:18.554632 00880000 ################################################################
10149 12:48:18.554767
10150 12:48:18.818530 00900000 ################################################################
10151 12:48:18.818693
10152 12:48:19.080751 00980000 ################################################################
10153 12:48:19.080905
10154 12:48:19.337791 00a00000 ################################################################
10155 12:48:19.337928
10156 12:48:19.598415 00a80000 ################################################################
10157 12:48:19.598552
10158 12:48:19.855858 00b00000 ################################################################
10159 12:48:19.855991
10160 12:48:20.120296 00b80000 ################################################################
10161 12:48:20.120441
10162 12:48:20.379183 00c00000 ################################################################
10163 12:48:20.379317
10164 12:48:20.635849 00c80000 ################################################################
10165 12:48:20.635980
10166 12:48:20.895145 00d00000 ################################################################
10167 12:48:20.895277
10168 12:48:21.162027 00d80000 ################################################################
10169 12:48:21.162161
10170 12:48:21.416359 00e00000 ################################################################
10171 12:48:21.416528
10172 12:48:21.668138 00e80000 ################################################################
10173 12:48:21.668286
10174 12:48:21.920376 00f00000 ################################################################
10175 12:48:21.920511
10176 12:48:22.170239 00f80000 ################################################################
10177 12:48:22.170373
10178 12:48:22.423432 01000000 ################################################################
10179 12:48:22.423592
10180 12:48:22.680911 01080000 ################################################################
10181 12:48:22.681055
10182 12:48:22.940971 01100000 ################################################################
10183 12:48:22.941111
10184 12:48:23.193536 01180000 ################################################################
10185 12:48:23.193681
10186 12:48:23.454105 01200000 ################################################################
10187 12:48:23.454241
10188 12:48:23.715904 01280000 ################################################################
10189 12:48:23.716080
10190 12:48:23.970993 01300000 ################################################################
10191 12:48:23.971134
10192 12:48:24.224205 01380000 ################################################################
10193 12:48:24.224344
10194 12:48:24.485215 01400000 ################################################################
10195 12:48:24.485380
10196 12:48:24.735237 01480000 ################################################################
10197 12:48:24.735404
10198 12:48:24.984436 01500000 ################################################################
10199 12:48:24.984575
10200 12:48:25.235923 01580000 ################################################################
10201 12:48:25.236068
10202 12:48:25.490292 01600000 ################################################################
10203 12:48:25.490452
10204 12:48:25.737754 01680000 ################################################################
10205 12:48:25.737890
10206 12:48:25.983851 01700000 ################################################################
10207 12:48:25.983990
10208 12:48:26.238279 01780000 ################################################################
10209 12:48:26.238424
10210 12:48:26.489223 01800000 ################################################################
10211 12:48:26.489357
10212 12:48:26.737183 01880000 ################################################################
10213 12:48:26.737320
10214 12:48:26.986626 01900000 ################################################################
10215 12:48:26.986760
10216 12:48:27.238563 01980000 ################################################################
10217 12:48:27.238701
10218 12:48:27.501701 01a00000 ################################################################
10219 12:48:27.501840
10220 12:48:27.773963 01a80000 ################################################################
10221 12:48:27.774104
10222 12:48:27.869421 01b00000 ######################## done.
10223 12:48:27.869545
10224 12:48:27.872288 The bootfile was 28501434 bytes long.
10225 12:48:27.872404
10226 12:48:27.875696 Sending tftp read request... done.
10227 12:48:27.875822
10228 12:48:27.879281 Waiting for the transfer...
10229 12:48:27.879366
10230 12:48:27.879467 00000000 # done.
10231 12:48:27.879597
10232 12:48:27.885702 Command line loaded dynamically from TFTP file: 11118924/tftp-deploy-pu23uz5a/kernel/cmdline
10233 12:48:27.889474
10234 12:48:27.909239 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11118924/extract-nfsrootfs-0csouspo,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10235 12:48:27.909337
10236 12:48:27.909424 Loading FIT.
10237 12:48:27.909505
10238 12:48:27.912278 Image ramdisk-1 has 17644299 bytes.
10239 12:48:27.912364
10240 12:48:27.916066 Image fdt-1 has 46924 bytes.
10241 12:48:27.916152
10242 12:48:27.918981 Image kernel-1 has 10808178 bytes.
10243 12:48:27.919066
10244 12:48:27.929191 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10245 12:48:27.929301
10246 12:48:27.945947 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10247 12:48:27.946073
10248 12:48:27.952003 Choosing best match conf-1 for compat google,spherion-rev2.
10249 12:48:27.952086
10250 12:48:27.959840 Connected to device vid:did:rid of 1ae0:0028:00
10251 12:48:27.967990
10252 12:48:27.971565 tpm_get_response: command 0x17b, return code 0x0
10253 12:48:27.971661
10254 12:48:27.974833 ec_init: CrosEC protocol v3 supported (256, 248)
10255 12:48:27.978994
10256 12:48:27.982000 tpm_cleanup: add release locality here.
10257 12:48:27.982081
10258 12:48:27.982145 Shutting down all USB controllers.
10259 12:48:27.985499
10260 12:48:27.985579 Removing current net device
10261 12:48:27.985643
10262 12:48:27.992194 Exiting depthcharge with code 4 at timestamp: 49886278
10263 12:48:27.992276
10264 12:48:27.995667 LZMA decompressing kernel-1 to 0x821a6718
10265 12:48:27.995749
10266 12:48:27.998736 LZMA decompressing kernel-1 to 0x40000000
10267 12:48:29.350423
10268 12:48:29.350554 jumping to kernel
10269 12:48:29.350960 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10270 12:48:29.351056 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10271 12:48:29.351132 Setting prompt string to ['Linux version [0-9]']
10272 12:48:29.351201 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10273 12:48:29.351269 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10274 12:48:29.432149
10275 12:48:29.435696 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10276 12:48:29.439451 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10277 12:48:29.439597 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10278 12:48:29.439716 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10279 12:48:29.439820 Using line separator: #'\n'#
10280 12:48:29.439906 No login prompt set.
10281 12:48:29.440003 Parsing kernel messages
10282 12:48:29.440089 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10283 12:48:29.440302 [login-action] Waiting for messages, (timeout 00:04:03)
10284 12:48:29.458862 [ 0.000000] Linux version 6.1.38-cip1 (KernelCI@build-j6766-arm64-gcc-10-defconfig-arm64-chromebook-9w8v6) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Jul 20 12:35:57 UTC 2023
10285 12:48:29.462650 [ 0.000000] random: crng init done
10286 12:48:29.465713 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10287 12:48:29.469020 [ 0.000000] efi: UEFI not found.
10288 12:48:29.478927 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10289 12:48:29.485775 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10290 12:48:29.495477 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10291 12:48:29.505388 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10292 12:48:29.511951 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10293 12:48:29.515503 [ 0.000000] printk: bootconsole [mtk8250] enabled
10294 12:48:29.523877 [ 0.000000] NUMA: No NUMA configuration found
10295 12:48:29.530585 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10296 12:48:29.537247 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10297 12:48:29.537385 [ 0.000000] Zone ranges:
10298 12:48:29.543842 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10299 12:48:29.547148 [ 0.000000] DMA32 empty
10300 12:48:29.554333 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10301 12:48:29.557414 [ 0.000000] Movable zone start for each node
10302 12:48:29.560424 [ 0.000000] Early memory node ranges
10303 12:48:29.567379 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10304 12:48:29.573565 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10305 12:48:29.580406 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10306 12:48:29.586822 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10307 12:48:29.593725 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10308 12:48:29.600410 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10309 12:48:29.657167 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10310 12:48:29.663438 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10311 12:48:29.669974 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10312 12:48:29.672964 [ 0.000000] psci: probing for conduit method from DT.
10313 12:48:29.679857 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10314 12:48:29.682931 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10315 12:48:29.689877 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10316 12:48:29.692876 [ 0.000000] psci: SMC Calling Convention v1.2
10317 12:48:29.699457 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10318 12:48:29.703135 [ 0.000000] Detected VIPT I-cache on CPU0
10319 12:48:29.710061 [ 0.000000] CPU features: detected: GIC system register CPU interface
10320 12:48:29.716152 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10321 12:48:29.723029 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10322 12:48:29.730073 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10323 12:48:29.736696 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10324 12:48:29.742866 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10325 12:48:29.749947 [ 0.000000] alternatives: applying boot alternatives
10326 12:48:29.753061 [ 0.000000] Fallback order for Node 0: 0
10327 12:48:29.759992 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10328 12:48:29.762935 [ 0.000000] Policy zone: Normal
10329 12:48:29.785865 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11118924/extract-nfsrootfs-0csouspo,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10330 12:48:29.795951 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10331 12:48:29.809034 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10332 12:48:29.819511 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10333 12:48:29.826294 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10334 12:48:29.829325 <6>[ 0.000000] software IO TLB: area num 8.
10335 12:48:29.886661 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10336 12:48:30.035975 <6>[ 0.000000] Memory: 7952972K/8385536K available (17984K kernel code, 4098K rwdata, 16796K rodata, 8384K init, 615K bss, 399796K reserved, 32768K cma-reserved)
10337 12:48:30.042618 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10338 12:48:30.048997 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10339 12:48:30.052798 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10340 12:48:30.059094 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10341 12:48:30.065899 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10342 12:48:30.069031 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10343 12:48:30.079201 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10344 12:48:30.085643 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10345 12:48:30.092442 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10346 12:48:30.099150 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10347 12:48:30.102126 <6>[ 0.000000] GICv3: 608 SPIs implemented
10348 12:48:30.105831 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10349 12:48:30.111990 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10350 12:48:30.115710 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10351 12:48:30.122143 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10352 12:48:30.135350 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10353 12:48:30.148212 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10354 12:48:30.154679 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10355 12:48:30.163068 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10356 12:48:30.176024 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10357 12:48:30.182873 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10358 12:48:30.189460 <6>[ 0.009183] Console: colour dummy device 80x25
10359 12:48:30.199209 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10360 12:48:30.206050 <6>[ 0.024415] pid_max: default: 32768 minimum: 301
10361 12:48:30.208952 <6>[ 0.029319] LSM: Security Framework initializing
10362 12:48:30.215644 <6>[ 0.034255] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10363 12:48:30.225630 <6>[ 0.042069] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10364 12:48:30.235495 <6>[ 0.051493] cblist_init_generic: Setting adjustable number of callback queues.
10365 12:48:30.238957 <6>[ 0.058947] cblist_init_generic: Setting shift to 3 and lim to 1.
10366 12:48:30.245245 <6>[ 0.065285] cblist_init_generic: Setting shift to 3 and lim to 1.
10367 12:48:30.251811 <6>[ 0.071691] rcu: Hierarchical SRCU implementation.
10368 12:48:30.258904 <6>[ 0.076705] rcu: Max phase no-delay instances is 1000.
10369 12:48:30.265334 <6>[ 0.083760] EFI services will not be available.
10370 12:48:30.268465 <6>[ 0.088762] smp: Bringing up secondary CPUs ...
10371 12:48:30.276323 <6>[ 0.093816] Detected VIPT I-cache on CPU1
10372 12:48:30.283180 <6>[ 0.093886] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10373 12:48:30.290015 <6>[ 0.093918] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10374 12:48:30.292758 <6>[ 0.094253] Detected VIPT I-cache on CPU2
10375 12:48:30.299559 <6>[ 0.094305] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10376 12:48:30.309379 <6>[ 0.094324] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10377 12:48:30.312606 <6>[ 0.094584] Detected VIPT I-cache on CPU3
10378 12:48:30.319087 <6>[ 0.094630] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10379 12:48:30.326072 <6>[ 0.094645] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10380 12:48:30.329380 <6>[ 0.094950] CPU features: detected: Spectre-v4
10381 12:48:30.336001 <6>[ 0.094957] CPU features: detected: Spectre-BHB
10382 12:48:30.339435 <6>[ 0.094963] Detected PIPT I-cache on CPU4
10383 12:48:30.345721 <6>[ 0.095022] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10384 12:48:30.352536 <6>[ 0.095040] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10385 12:48:30.359065 <6>[ 0.095336] Detected PIPT I-cache on CPU5
10386 12:48:30.365278 <6>[ 0.095401] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10387 12:48:30.372093 <6>[ 0.095418] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10388 12:48:30.375671 <6>[ 0.095702] Detected PIPT I-cache on CPU6
10389 12:48:30.381825 <6>[ 0.095770] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10390 12:48:30.388973 <6>[ 0.095787] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10391 12:48:30.395314 <6>[ 0.096084] Detected PIPT I-cache on CPU7
10392 12:48:30.401752 <6>[ 0.096150] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10393 12:48:30.408480 <6>[ 0.096167] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10394 12:48:30.411752 <6>[ 0.096213] smp: Brought up 1 node, 8 CPUs
10395 12:48:30.418161 <6>[ 0.237626] SMP: Total of 8 processors activated.
10396 12:48:30.421762 <6>[ 0.242547] CPU features: detected: 32-bit EL0 Support
10397 12:48:30.431564 <6>[ 0.247910] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10398 12:48:30.438247 <6>[ 0.256710] CPU features: detected: Common not Private translations
10399 12:48:30.444920 <6>[ 0.263186] CPU features: detected: CRC32 instructions
10400 12:48:30.448241 <6>[ 0.268537] CPU features: detected: RCpc load-acquire (LDAPR)
10401 12:48:30.454864 <6>[ 0.274497] CPU features: detected: LSE atomic instructions
10402 12:48:30.461188 <6>[ 0.280278] CPU features: detected: Privileged Access Never
10403 12:48:30.468258 <6>[ 0.286058] CPU features: detected: RAS Extension Support
10404 12:48:30.474709 <6>[ 0.291701] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10405 12:48:30.477706 <6>[ 0.298921] CPU: All CPU(s) started at EL2
10406 12:48:30.484455 <6>[ 0.303264] alternatives: applying system-wide alternatives
10407 12:48:30.494330 <6>[ 0.313938] devtmpfs: initialized
10408 12:48:30.506308 <6>[ 0.322968] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10409 12:48:30.516441 <6>[ 0.332933] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10410 12:48:30.523015 <6>[ 0.340831] pinctrl core: initialized pinctrl subsystem
10411 12:48:30.526260 <6>[ 0.347489] DMI not present or invalid.
10412 12:48:30.532686 <6>[ 0.351896] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10413 12:48:30.542744 <6>[ 0.358769] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10414 12:48:30.549400 <6>[ 0.366349] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10415 12:48:30.559312 <6>[ 0.374555] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10416 12:48:30.562791 <6>[ 0.382799] audit: initializing netlink subsys (disabled)
10417 12:48:30.572283 <5>[ 0.388498] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10418 12:48:30.579623 <6>[ 0.389203] thermal_sys: Registered thermal governor 'step_wise'
10419 12:48:30.586075 <6>[ 0.396466] thermal_sys: Registered thermal governor 'power_allocator'
10420 12:48:30.589022 <6>[ 0.402720] cpuidle: using governor menu
10421 12:48:30.595823 <6>[ 0.413683] NET: Registered PF_QIPCRTR protocol family
10422 12:48:30.602755 <6>[ 0.419180] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10423 12:48:30.605536 <6>[ 0.426285] ASID allocator initialised with 32768 entries
10424 12:48:30.613167 <6>[ 0.432848] Serial: AMBA PL011 UART driver
10425 12:48:30.621397 <4>[ 0.441500] Trying to register duplicate clock ID: 134
10426 12:48:30.675598 <6>[ 0.498737] KASLR enabled
10427 12:48:30.689851 <6>[ 0.506438] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10428 12:48:30.696552 <6>[ 0.513454] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10429 12:48:30.702996 <6>[ 0.519945] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10430 12:48:30.709857 <6>[ 0.526951] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10431 12:48:30.716820 <6>[ 0.533440] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10432 12:48:30.722831 <6>[ 0.540446] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10433 12:48:30.729758 <6>[ 0.546934] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10434 12:48:30.736534 <6>[ 0.553941] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10435 12:48:30.739414 <6>[ 0.561403] ACPI: Interpreter disabled.
10436 12:48:30.747852 <6>[ 0.567856] iommu: Default domain type: Translated
10437 12:48:30.754453 <6>[ 0.572972] iommu: DMA domain TLB invalidation policy: strict mode
10438 12:48:30.758156 <5>[ 0.579646] SCSI subsystem initialized
10439 12:48:30.764348 <6>[ 0.583898] usbcore: registered new interface driver usbfs
10440 12:48:30.771118 <6>[ 0.589632] usbcore: registered new interface driver hub
10441 12:48:30.774307 <6>[ 0.595188] usbcore: registered new device driver usb
10442 12:48:30.781278 <6>[ 0.601297] pps_core: LinuxPPS API ver. 1 registered
10443 12:48:30.791217 <6>[ 0.606490] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10444 12:48:30.794952 <6>[ 0.615837] PTP clock support registered
10445 12:48:30.797896 <6>[ 0.620077] EDAC MC: Ver: 3.0.0
10446 12:48:30.805628 <6>[ 0.625231] FPGA manager framework
10447 12:48:30.811759 <6>[ 0.628911] Advanced Linux Sound Architecture Driver Initialized.
10448 12:48:30.815420 <6>[ 0.635682] vgaarb: loaded
10449 12:48:30.821504 <6>[ 0.638869] clocksource: Switched to clocksource arch_sys_counter
10450 12:48:30.825140 <5>[ 0.645324] VFS: Disk quotas dquot_6.6.0
10451 12:48:30.831397 <6>[ 0.649512] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10452 12:48:30.835175 <6>[ 0.656705] pnp: PnP ACPI: disabled
10453 12:48:30.843701 <6>[ 0.663354] NET: Registered PF_INET protocol family
10454 12:48:30.853302 <6>[ 0.668943] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10455 12:48:30.864909 <6>[ 0.681255] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10456 12:48:30.874594 <6>[ 0.690070] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10457 12:48:30.881248 <6>[ 0.698042] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10458 12:48:30.887962 <6>[ 0.706745] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10459 12:48:30.900214 <6>[ 0.716495] TCP: Hash tables configured (established 65536 bind 65536)
10460 12:48:30.906833 <6>[ 0.723360] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10461 12:48:30.913194 <6>[ 0.730559] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10462 12:48:30.919694 <6>[ 0.738267] NET: Registered PF_UNIX/PF_LOCAL protocol family
10463 12:48:30.926028 <6>[ 0.744413] RPC: Registered named UNIX socket transport module.
10464 12:48:30.929895 <6>[ 0.750567] RPC: Registered udp transport module.
10465 12:48:30.936399 <6>[ 0.755502] RPC: Registered tcp transport module.
10466 12:48:30.942666 <6>[ 0.760436] RPC: Registered tcp NFSv4.1 backchannel transport module.
10467 12:48:30.946130 <6>[ 0.767103] PCI: CLS 0 bytes, default 64
10468 12:48:30.949370 <6>[ 0.771441] Unpacking initramfs...
10469 12:48:30.959163 <6>[ 0.775251] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10470 12:48:30.965799 <6>[ 0.783887] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10471 12:48:30.973012 <6>[ 0.792677] kvm [1]: IPA Size Limit: 40 bits
10472 12:48:30.976084 <6>[ 0.797202] kvm [1]: GICv3: no GICV resource entry
10473 12:48:30.982898 <6>[ 0.802223] kvm [1]: disabling GICv2 emulation
10474 12:48:30.989629 <6>[ 0.806908] kvm [1]: GIC system register CPU interface enabled
10475 12:48:30.992665 <6>[ 0.813074] kvm [1]: vgic interrupt IRQ18
10476 12:48:30.998675 <6>[ 0.817434] kvm [1]: VHE mode initialized successfully
10477 12:48:31.002482 <5>[ 0.823892] Initialise system trusted keyrings
10478 12:48:31.009218 <6>[ 0.828691] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10479 12:48:31.018818 <6>[ 0.838649] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10480 12:48:31.025271 <5>[ 0.845033] NFS: Registering the id_resolver key type
10481 12:48:31.028857 <5>[ 0.850332] Key type id_resolver registered
10482 12:48:31.035632 <5>[ 0.854749] Key type id_legacy registered
10483 12:48:31.042366 <6>[ 0.859029] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10484 12:48:31.048960 <6>[ 0.865954] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10485 12:48:31.055630 <6>[ 0.873670] 9p: Installing v9fs 9p2000 file system support
10486 12:48:31.091103 <5>[ 0.911590] Key type asymmetric registered
10487 12:48:31.094675 <5>[ 0.915919] Asymmetric key parser 'x509' registered
10488 12:48:31.104413 <6>[ 0.921055] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10489 12:48:31.108058 <6>[ 0.928670] io scheduler mq-deadline registered
10490 12:48:31.110967 <6>[ 0.933430] io scheduler kyber registered
10491 12:48:31.129658 <6>[ 0.950180] EINJ: ACPI disabled.
10492 12:48:31.162031 <4>[ 0.975410] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10493 12:48:31.171741 <4>[ 0.986047] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10494 12:48:31.187047 <6>[ 1.006889] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10495 12:48:31.194178 <6>[ 1.014869] printk: console [ttyS0] disabled
10496 12:48:31.222678 <6>[ 1.039512] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10497 12:48:31.229464 <6>[ 1.048985] printk: console [ttyS0] enabled
10498 12:48:31.232465 <6>[ 1.048985] printk: console [ttyS0] enabled
10499 12:48:31.239675 <6>[ 1.057878] printk: bootconsole [mtk8250] disabled
10500 12:48:31.242710 <6>[ 1.057878] printk: bootconsole [mtk8250] disabled
10501 12:48:31.248865 <6>[ 1.069175] SuperH (H)SCI(F) driver initialized
10502 12:48:31.252103 <6>[ 1.074450] msm_serial: driver initialized
10503 12:48:31.266279 <6>[ 1.083419] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10504 12:48:31.276701 <6>[ 1.091969] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10505 12:48:31.282822 <6>[ 1.100510] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10506 12:48:31.293255 <6>[ 1.109138] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10507 12:48:31.299470 <6>[ 1.117849] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10508 12:48:31.309699 <6>[ 1.126563] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10509 12:48:31.319657 <6>[ 1.135105] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10510 12:48:31.326303 <6>[ 1.143910] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10511 12:48:31.336259 <6>[ 1.152453] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10512 12:48:31.347814 <6>[ 1.168176] loop: module loaded
10513 12:48:31.354405 <6>[ 1.174189] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10514 12:48:31.377463 <4>[ 1.197509] mtk-pmic-keys: Failed to locate of_node [id: -1]
10515 12:48:31.384418 <6>[ 1.204322] megasas: 07.719.03.00-rc1
10516 12:48:31.393646 <6>[ 1.213820] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10517 12:48:31.402259 <6>[ 1.222268] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10518 12:48:31.419433 <6>[ 1.239137] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10519 12:48:31.476549 <6>[ 1.289824] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10520 12:48:31.686500 <6>[ 1.506576] Freeing initrd memory: 17228K
10521 12:48:31.696563 <6>[ 1.516767] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10522 12:48:31.707688 <6>[ 1.527648] tun: Universal TUN/TAP device driver, 1.6
10523 12:48:31.711488 <6>[ 1.533697] thunder_xcv, ver 1.0
10524 12:48:31.714623 <6>[ 1.537201] thunder_bgx, ver 1.0
10525 12:48:31.717782 <6>[ 1.540697] nicpf, ver 1.0
10526 12:48:31.728128 <6>[ 1.544695] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10527 12:48:31.731654 <6>[ 1.552172] hns3: Copyright (c) 2017 Huawei Corporation.
10528 12:48:31.734686 <6>[ 1.557759] hclge is initializing
10529 12:48:31.741752 <6>[ 1.561339] e1000: Intel(R) PRO/1000 Network Driver
10530 12:48:31.748610 <6>[ 1.566470] e1000: Copyright (c) 1999-2006 Intel Corporation.
10531 12:48:31.751560 <6>[ 1.572483] e1000e: Intel(R) PRO/1000 Network Driver
10532 12:48:31.758277 <6>[ 1.577699] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10533 12:48:31.765147 <6>[ 1.583888] igb: Intel(R) Gigabit Ethernet Network Driver
10534 12:48:31.771847 <6>[ 1.589540] igb: Copyright (c) 2007-2014 Intel Corporation.
10535 12:48:31.778511 <6>[ 1.595376] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10536 12:48:31.781443 <6>[ 1.601894] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10537 12:48:31.788752 <6>[ 1.608353] sky2: driver version 1.30
10538 12:48:31.794634 <6>[ 1.613326] VFIO - User Level meta-driver version: 0.3
10539 12:48:31.801775 <6>[ 1.621537] usbcore: registered new interface driver usb-storage
10540 12:48:31.808006 <6>[ 1.627979] usbcore: registered new device driver onboard-usb-hub
10541 12:48:31.817192 <6>[ 1.637028] mt6397-rtc mt6359-rtc: registered as rtc0
10542 12:48:31.827298 <6>[ 1.642486] mt6397-rtc mt6359-rtc: setting system clock to 2023-07-20T12:48:01 UTC (1689857281)
10543 12:48:31.830440 <6>[ 1.652040] i2c_dev: i2c /dev entries driver
10544 12:48:31.847261 <6>[ 1.663727] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10545 12:48:31.853900 <6>[ 1.673906] sdhci: Secure Digital Host Controller Interface driver
10546 12:48:31.860920 <6>[ 1.680344] sdhci: Copyright(c) Pierre Ossman
10547 12:48:31.867616 <6>[ 1.685732] Synopsys Designware Multimedia Card Interface Driver
10548 12:48:31.870911 <6>[ 1.692363] mmc0: CQHCI version 5.10
10549 12:48:31.877062 <6>[ 1.692880] sdhci-pltfm: SDHCI platform and OF driver helper
10550 12:48:31.884584 <6>[ 1.704294] ledtrig-cpu: registered to indicate activity on CPUs
10551 12:48:31.894838 <6>[ 1.711636] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10552 12:48:31.898286 <6>[ 1.719020] usbcore: registered new interface driver usbhid
10553 12:48:31.904746 <6>[ 1.724846] usbhid: USB HID core driver
10554 12:48:31.911707 <6>[ 1.729081] spi_master spi0: will run message pump with realtime priority
10555 12:48:31.955147 <6>[ 1.768290] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10556 12:48:31.973428 <6>[ 1.783307] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10557 12:48:31.977156 <6>[ 1.796883] mmc0: Command Queue Engine enabled
10558 12:48:31.984455 <6>[ 1.798759] cros-ec-spi spi0.0: Chrome EC device registered
10559 12:48:31.987653 <6>[ 1.801620] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10560 12:48:31.994754 <6>[ 1.814815] mmcblk0: mmc0:0001 DA4128 116 GiB
10561 12:48:32.007930 <6>[ 1.824340] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10562 12:48:32.014232 <6>[ 1.824379] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10563 12:48:32.020612 <6>[ 1.835716] NET: Registered PF_PACKET protocol family
10564 12:48:32.024467 <6>[ 1.841026] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10565 12:48:32.031113 <6>[ 1.844989] 9pnet: Installing 9P2000 support
10566 12:48:32.034462 <6>[ 1.850712] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10567 12:48:32.040684 <5>[ 1.854672] Key type dns_resolver registered
10568 12:48:32.043892 <6>[ 1.860478] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10569 12:48:32.051331 <6>[ 1.864922] registered taskstats version 1
10570 12:48:32.054286 <5>[ 1.875308] Loading compiled-in X.509 certificates
10571 12:48:32.089795 <4>[ 1.903219] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10572 12:48:32.099632 <4>[ 1.913904] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10573 12:48:32.109729 <3>[ 1.926528] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10574 12:48:32.121659 <6>[ 1.941957] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10575 12:48:32.128944 <6>[ 1.948806] xhci-mtk 11200000.usb: xHCI Host Controller
10576 12:48:32.135363 <6>[ 1.954315] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10577 12:48:32.145790 <6>[ 1.962254] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10578 12:48:32.152202 <6>[ 1.971698] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10579 12:48:32.158997 <6>[ 1.977790] xhci-mtk 11200000.usb: xHCI Host Controller
10580 12:48:32.165640 <6>[ 1.983273] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10581 12:48:32.172178 <6>[ 1.990924] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10582 12:48:32.178935 <6>[ 1.998811] hub 1-0:1.0: USB hub found
10583 12:48:32.182094 <6>[ 2.002850] hub 1-0:1.0: 1 port detected
10584 12:48:32.188929 <6>[ 2.007197] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10585 12:48:32.196216 <6>[ 2.016000] hub 2-0:1.0: USB hub found
10586 12:48:32.199331 <6>[ 2.020053] hub 2-0:1.0: 1 port detected
10587 12:48:32.207256 <6>[ 2.027377] mtk-msdc 11f70000.mmc: Got CD GPIO
10588 12:48:32.224247 <6>[ 2.040557] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10589 12:48:32.230351 <6>[ 2.048586] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10590 12:48:32.241522 <4>[ 2.056553] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10591 12:48:32.250773 <6>[ 2.066222] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10592 12:48:32.257357 <6>[ 2.074304] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10593 12:48:32.263856 <6>[ 2.082316] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10594 12:48:32.273964 <6>[ 2.090238] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10595 12:48:32.280788 <6>[ 2.098059] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10596 12:48:32.290498 <6>[ 2.105881] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10597 12:48:32.300702 <6>[ 2.116597] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10598 12:48:32.307007 <6>[ 2.124967] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10599 12:48:32.317288 <6>[ 2.133322] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10600 12:48:32.323963 <6>[ 2.141672] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10601 12:48:32.333820 <6>[ 2.150016] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10602 12:48:32.341010 <6>[ 2.158360] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10603 12:48:32.350936 <6>[ 2.166704] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10604 12:48:32.357274 <6>[ 2.175048] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10605 12:48:32.366999 <6>[ 2.183392] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10606 12:48:32.373947 <6>[ 2.191735] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10607 12:48:32.383740 <6>[ 2.200084] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10608 12:48:32.390450 <6>[ 2.208428] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10609 12:48:32.400647 <6>[ 2.216771] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10610 12:48:32.407370 <6>[ 2.225114] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10611 12:48:32.417231 <6>[ 2.233460] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10612 12:48:32.424199 <6>[ 2.242363] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10613 12:48:32.430504 <6>[ 2.249823] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10614 12:48:32.437053 <6>[ 2.256841] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10615 12:48:32.446812 <6>[ 2.263947] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10616 12:48:32.453264 <6>[ 2.271226] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10617 12:48:32.463203 <6>[ 2.278142] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10618 12:48:32.470371 <6>[ 2.287283] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10619 12:48:32.480428 <6>[ 2.296411] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10620 12:48:32.490137 <6>[ 2.305713] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10621 12:48:32.500076 <6>[ 2.315189] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10622 12:48:32.506752 <6>[ 2.324665] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10623 12:48:32.517305 <6>[ 2.333793] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10624 12:48:32.527425 <6>[ 2.343274] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10625 12:48:32.537333 <6>[ 2.352405] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10626 12:48:32.546972 <6>[ 2.361708] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10627 12:48:32.557135 <6>[ 2.371873] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10628 12:48:32.566852 <6>[ 2.383208] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10629 12:48:32.573736 <6>[ 2.393127] Trying to probe devices needed for running init ...
10630 12:48:32.590450 <6>[ 2.407140] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10631 12:48:32.617349 <6>[ 2.437719] hub 2-1:1.0: USB hub found
10632 12:48:32.621052 <6>[ 2.442122] hub 2-1:1.0: 3 ports detected
10633 12:48:32.742342 <6>[ 2.559143] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10634 12:48:32.896848 <6>[ 2.716885] hub 1-1:1.0: USB hub found
10635 12:48:32.900175 <6>[ 2.721333] hub 1-1:1.0: 4 ports detected
10636 12:48:32.978650 <6>[ 2.795401] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10637 12:48:33.221963 <6>[ 3.039071] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10638 12:48:33.353215 <6>[ 3.173628] hub 1-1.4:1.0: USB hub found
10639 12:48:33.356514 <6>[ 3.178160] hub 1-1.4:1.0: 2 ports detected
10640 12:48:33.654183 <6>[ 3.471115] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10641 12:48:33.838379 <6>[ 3.655116] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10642 12:48:44.874870 <6>[ 14.699709] ALSA device list:
10643 12:48:44.880917 <6>[ 14.702965] No soundcards found.
10644 12:48:44.893278 <6>[ 14.715342] Freeing unused kernel memory: 8384K
10645 12:48:44.896697 <6>[ 14.720219] Run /init as init process
10646 12:48:44.907043 Loading, please wait...
10647 12:48:44.926423 Starting version 247.3-7+deb11u2
10648 12:48:45.246295 <6>[ 15.065169] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10649 12:48:45.262278 <6>[ 15.084287] remoteproc remoteproc0: scp is available
10650 12:48:45.268788 <6>[ 15.089623] remoteproc remoteproc0: powering up scp
10651 12:48:45.276033 <6>[ 15.094775] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10652 12:48:45.282683 <6>[ 15.103251] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10653 12:48:45.289124 <6>[ 15.104531] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10654 12:48:45.295461 <6>[ 15.110473] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10655 12:48:45.305647 <3>[ 15.115847] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10656 12:48:45.312241 <3>[ 15.115863] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10657 12:48:45.322200 <3>[ 15.115871] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10658 12:48:45.328483 <3>[ 15.115995] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10659 12:48:45.338721 <3>[ 15.116006] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10660 12:48:45.345021 <3>[ 15.116013] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10661 12:48:45.354938 <3>[ 15.116022] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10662 12:48:45.362008 <3>[ 15.116029] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10663 12:48:45.368818 <3>[ 15.116063] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10664 12:48:45.379279 <3>[ 15.116105] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10665 12:48:45.385973 <3>[ 15.116113] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10666 12:48:45.395924 <3>[ 15.116119] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10667 12:48:45.402742 <3>[ 15.116171] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10668 12:48:45.409496 <3>[ 15.116178] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10669 12:48:45.419353 <3>[ 15.116190] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10670 12:48:45.426358 <3>[ 15.116197] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10671 12:48:45.433320 <3>[ 15.116204] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10672 12:48:45.443445 <3>[ 15.116232] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10673 12:48:45.452898 <6>[ 15.116522] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10674 12:48:45.456504 <6>[ 15.141111] mc: Linux media interface: v0.10
10675 12:48:45.463047 <4>[ 15.142277] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10676 12:48:45.469494 <4>[ 15.142486] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10677 12:48:45.476161 <6>[ 15.142593] usbcore: registered new interface driver r8152
10678 12:48:45.486219 <6>[ 15.148442] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10679 12:48:45.492682 <4>[ 15.156402] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10680 12:48:45.499818 <4>[ 15.156402] Fallback method does not support PEC.
10681 12:48:45.505798 <6>[ 15.175854] videodev: Linux video capture interface: v2.00
10682 12:48:45.512956 <3>[ 15.199973] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10683 12:48:45.519211 <6>[ 15.227197] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10684 12:48:45.529138 <6>[ 15.234376] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10685 12:48:45.535823 <6>[ 15.234390] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10686 12:48:45.545676 <3>[ 15.251545] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10687 12:48:45.552645 <6>[ 15.253733] remoteproc remoteproc0: remote processor scp is now up
10688 12:48:45.559021 <6>[ 15.254849] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10689 12:48:45.569160 <6>[ 15.256638] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10690 12:48:45.575674 <6>[ 15.259557] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10691 12:48:45.585671 <6>[ 15.263312] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10692 12:48:45.595544 <4>[ 15.266369] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10693 12:48:45.605623 <4>[ 15.266379] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10694 12:48:45.612378 <6>[ 15.276315] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10695 12:48:45.618958 <6>[ 15.278978] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10696 12:48:45.625980 <6>[ 15.283100] pci_bus 0000:00: root bus resource [bus 00-ff]
10697 12:48:45.632391 <6>[ 15.312658] usbcore: registered new interface driver cdc_ether
10698 12:48:45.638945 <6>[ 15.325798] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10699 12:48:45.642060 <6>[ 15.331766] r8152 2-1.3:1.0 eth0: v1.12.13
10700 12:48:45.648964 <6>[ 15.332533] Bluetooth: Core ver 2.22
10701 12:48:45.652176 <6>[ 15.332658] NET: Registered PF_BLUETOOTH protocol family
10702 12:48:45.658854 <6>[ 15.332661] Bluetooth: HCI device and connection manager initialized
10703 12:48:45.665164 <6>[ 15.332682] Bluetooth: HCI socket layer initialized
10704 12:48:45.668737 <6>[ 15.332691] Bluetooth: L2CAP socket layer initialized
10705 12:48:45.675367 <6>[ 15.332706] Bluetooth: SCO socket layer initialized
10706 12:48:45.684744 <6>[ 15.340364] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10707 12:48:45.691418 <6>[ 15.340423] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10708 12:48:45.698471 <6>[ 15.340845] usbcore: registered new interface driver r8153_ecm
10709 12:48:45.704813 <6>[ 15.342065] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10710 12:48:45.718006 <6>[ 15.343426] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10711 12:48:45.721950 <6>[ 15.343675] usbcore: registered new interface driver uvcvideo
10712 12:48:45.728331 <6>[ 15.355477] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10713 12:48:45.738246 <6>[ 15.356052] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10714 12:48:45.741233 <6>[ 15.387278] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10715 12:48:45.748380 <6>[ 15.394893] pci 0000:00:00.0: supports D1 D2
10716 12:48:45.754618 <6>[ 15.395498] usbcore: registered new interface driver btusb
10717 12:48:45.764506 <4>[ 15.396666] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10718 12:48:45.771094 <3>[ 15.396675] Bluetooth: hci0: Failed to load firmware file (-2)
10719 12:48:45.774693 <3>[ 15.396679] Bluetooth: hci0: Failed to set up firmware (-2)
10720 12:48:45.787206 <4>[ 15.396683] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10721 12:48:45.794415 <6>[ 15.612862] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10722 12:48:45.804057 <6>[ 15.621509] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10723 12:48:45.810647 <6>[ 15.629906] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10724 12:48:45.817771 <6>[ 15.636196] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10725 12:48:45.823985 <6>[ 15.643686] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10726 12:48:45.830222 <6>[ 15.651175] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10727 12:48:45.837098 <6>[ 15.658756] pci 0000:01:00.0: supports D1 D2
10728 12:48:45.843382 <6>[ 15.663281] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10729 12:48:45.864642 <6>[ 15.683082] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10730 12:48:45.871059 <6>[ 15.690000] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10731 12:48:45.877506 <6>[ 15.698090] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10732 12:48:45.887685 <6>[ 15.706096] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10733 12:48:45.894132 <6>[ 15.714104] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10734 12:48:45.904261 <6>[ 15.722112] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10735 12:48:45.907250 <6>[ 15.730118] pci 0000:00:00.0: PCI bridge to [bus 01]
10736 12:48:45.917178 <6>[ 15.735340] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10737 12:48:45.923722 <6>[ 15.743483] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10738 12:48:45.930471 <6>[ 15.750706] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10739 12:48:45.937090 <6>[ 15.757512] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10740 12:48:45.954842 <5>[ 15.773549] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10741 12:48:45.974335 <5>[ 15.793112] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10742 12:48:45.981392 <4>[ 15.800074] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10743 12:48:45.987477 <6>[ 15.808959] cfg80211: failed to load regulatory.db
10744 12:48:46.032753 <6>[ 15.851477] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10745 12:48:46.039583 <6>[ 15.859126] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10746 12:48:46.063394 <6>[ 15.885804] mt7921e 0000:01:00.0: ASIC revision: 79610010
10747 12:48:46.171215 <4>[ 15.986592] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10748 12:48:46.174747 Begin: Loading essential drivers ... done.
10749 12:48:46.181384 Begin: Running /scripts/init-premount ... done.
10750 12:48:46.187968 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10751 12:48:46.194491 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10752 12:48:46.198016 Device /sys/class/net/enx00e04c787aaa found
10753 12:48:46.201018 done.
10754 12:48:46.237230 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10755 12:48:46.289722 <4>[ 16.105379] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10756 12:48:46.409361 <4>[ 16.224778] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10757 12:48:46.525505 <4>[ 16.340697] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10758 12:48:46.641151 <4>[ 16.456631] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10759 12:48:46.757038 <4>[ 16.572572] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10760 12:48:46.873388 <4>[ 16.688630] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10761 12:48:46.988942 <4>[ 16.804486] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10762 12:48:47.104728 <4>[ 16.920454] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10763 12:48:47.141337 <6>[ 16.963546] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10764 12:48:47.220895 <4>[ 17.036473] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10765 12:48:47.320580 IP-Config: no response after 2 secs - giving up
10766 12:48:47.328226 <3>[ 17.150613] mt7921e 0000:01:00.0: hardware init failed
10767 12:48:47.372158 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10768 12:48:47.375328 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10769 12:48:47.382333 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10770 12:48:47.391823 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10771 12:48:47.398349 host : mt8192-asurada-spherion-r0-cbg-0
10772 12:48:47.404986 domain : lava-rack
10773 12:48:47.408617 rootserver: 192.168.201.1 rootpath:
10774 12:48:47.408700 filename :
10775 12:48:47.462862 done.
10776 12:48:47.469942 Begin: Running /scripts/nfs-bottom ... done.
10777 12:48:47.487447 Begin: Running /scripts/init-bottom ... done.
10778 12:48:48.585724 <6>[ 18.407902] NET: Registered PF_INET6 protocol family
10779 12:48:48.592632 <6>[ 18.414675] Segment Routing with IPv6
10780 12:48:48.595853 <6>[ 18.418683] In-situ OAM (IOAM) with IPv6
10781 12:48:48.703975 <30>[ 18.509195] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10782 12:48:48.710977 <30>[ 18.532957] systemd[1]: Detected architecture arm64.
10783 12:48:48.730440
10784 12:48:48.733174 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10785 12:48:48.733768
10786 12:48:48.751632 <30>[ 18.573505] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10787 12:48:49.253734 <30>[ 19.072723] systemd[1]: Queued start job for default target Graphical Interface.
10788 12:48:49.290071 <30>[ 19.112237] systemd[1]: Created slice system-getty.slice.
10789 12:48:49.297016 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10790 12:48:49.313861 <30>[ 19.135737] systemd[1]: Created slice system-modprobe.slice.
10791 12:48:49.320232 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10792 12:48:49.337929 <30>[ 19.160295] systemd[1]: Created slice system-serial\x2dgetty.slice.
10793 12:48:49.348151 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10794 12:48:49.361542 <30>[ 19.183653] systemd[1]: Created slice User and Session Slice.
10795 12:48:49.367848 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10796 12:48:49.388874 <30>[ 19.207713] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10797 12:48:49.398483 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10798 12:48:49.416213 <30>[ 19.235271] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10799 12:48:49.422705 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10800 12:48:49.443890 <30>[ 19.259261] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10801 12:48:49.449894 <30>[ 19.271292] systemd[1]: Reached target Local Encrypted Volumes.
10802 12:48:49.456609 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10803 12:48:49.472731 <30>[ 19.295174] systemd[1]: Reached target Paths.
10804 12:48:49.476372 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10805 12:48:49.493096 <30>[ 19.315181] systemd[1]: Reached target Remote File Systems.
10806 12:48:49.499403 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10807 12:48:49.512850 <30>[ 19.335167] systemd[1]: Reached target Slices.
10808 12:48:49.516309 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10809 12:48:49.532824 <30>[ 19.355191] systemd[1]: Reached target Swap.
10810 12:48:49.536286 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10811 12:48:49.556290 <30>[ 19.375434] systemd[1]: Listening on initctl Compatibility Named Pipe.
10812 12:48:49.562934 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10813 12:48:49.569521 <30>[ 19.390839] systemd[1]: Listening on Journal Audit Socket.
10814 12:48:49.575766 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10815 12:48:49.590080 <30>[ 19.412031] systemd[1]: Listening on Journal Socket (/dev/log).
10816 12:48:49.596068 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10817 12:48:49.613439 <30>[ 19.435972] systemd[1]: Listening on Journal Socket.
10818 12:48:49.620259 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10819 12:48:49.633971 <30>[ 19.456478] systemd[1]: Listening on Network Service Netlink Socket.
10820 12:48:49.643915 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10821 12:48:49.659054 <30>[ 19.481520] systemd[1]: Listening on udev Control Socket.
10822 12:48:49.666094 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10823 12:48:49.680937 <30>[ 19.503457] systemd[1]: Listening on udev Kernel Socket.
10824 12:48:49.687486 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10825 12:48:49.729168 <30>[ 19.551377] systemd[1]: Mounting Huge Pages File System...
10826 12:48:49.735467 Mounting [0;1;39mHuge Pages File System[0m...
10827 12:48:49.750781 <30>[ 19.573427] systemd[1]: Mounting POSIX Message Queue File System...
10828 12:48:49.757901 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10829 12:48:49.775387 <30>[ 19.597611] systemd[1]: Mounting Kernel Debug File System...
10830 12:48:49.782041 Mounting [0;1;39mKernel Debug File System[0m...
10831 12:48:49.800479 <30>[ 19.619544] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10832 12:48:49.817093 <30>[ 19.636162] systemd[1]: Starting Create list of static device nodes for the current kernel...
10833 12:48:49.823721 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10834 12:48:49.842974 <30>[ 19.665732] systemd[1]: Starting Load Kernel Module configfs...
10835 12:48:49.849621 Starting [0;1;39mLoad Kernel Module configfs[0m...
10836 12:48:49.867186 <30>[ 19.689473] systemd[1]: Starting Load Kernel Module drm...
10837 12:48:49.873426 Starting [0;1;39mLoad Kernel Module drm[0m...
10838 12:48:49.891225 <30>[ 19.713625] systemd[1]: Starting Load Kernel Module fuse...
10839 12:48:49.897719 Starting [0;1;39mLoad Kernel Module fuse[0m...
10840 12:48:49.925120 <6>[ 19.747549] fuse: init (API version 7.37)
10841 12:48:49.935086 <30>[ 19.748829] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10842 12:48:49.960875 <30>[ 19.783592] systemd[1]: Starting Journal Service...
10843 12:48:49.964345 Starting [0;1;39mJournal Service[0m...
10844 12:48:49.986630 <30>[ 19.809154] systemd[1]: Starting Load Kernel Modules...
10845 12:48:49.993289 Starting [0;1;39mLoad Kernel Modules[0m...
10846 12:48:50.019282 <30>[ 19.838340] systemd[1]: Starting Remount Root and Kernel File Systems...
10847 12:48:50.025795 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10848 12:48:50.043888 <30>[ 19.866023] systemd[1]: Starting Coldplug All udev Devices...
10849 12:48:50.050331 Starting [0;1;39mColdplug All udev Devices[0m...
10850 12:48:50.067895 <30>[ 19.890234] systemd[1]: Mounted Huge Pages File System.
10851 12:48:50.074219 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10852 12:48:50.088961 <30>[ 19.911567] systemd[1]: Mounted POSIX Message Queue File System.
10853 12:48:50.095530 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10854 12:48:50.111214 <3>[ 19.930494] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10855 12:48:50.118385 <30>[ 19.939841] systemd[1]: Mounted Kernel Debug File System.
10856 12:48:50.124526 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10857 12:48:50.142887 <3>[ 19.961666] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10858 12:48:50.152737 <30>[ 19.971543] systemd[1]: Finished Create list of static device nodes for the current kernel.
10859 12:48:50.162201 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10860 12:48:50.177974 <30>[ 20.000280] systemd[1]: modprobe@configfs.service: Succeeded.
10861 12:48:50.185000 <30>[ 20.006985] systemd[1]: Finished Load Kernel Module configfs.
10862 12:48:50.195049 <3>[ 20.009029] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10863 12:48:50.201583 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10864 12:48:50.217826 <30>[ 20.040029] systemd[1]: modprobe@drm.service: Succeeded.
10865 12:48:50.227768 <3>[ 20.043424] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10866 12:48:50.231361 <30>[ 20.046310] systemd[1]: Finished Load Kernel Module drm.
10867 12:48:50.237669 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10868 12:48:50.256916 <3>[ 20.075895] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10869 12:48:50.263720 <30>[ 20.076367] systemd[1]: modprobe@fuse.service: Succeeded.
10870 12:48:50.270402 <30>[ 20.091088] systemd[1]: Finished Load Kernel Module fuse.
10871 12:48:50.276956 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10872 12:48:50.288136 <3>[ 20.106850] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10873 12:48:50.295345 <30>[ 20.117265] systemd[1]: Finished Load Kernel Modules.
10874 12:48:50.301813 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10875 12:48:50.319263 <3>[ 20.137734] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10876 12:48:50.330374 <30>[ 20.148719] systemd[1]: Finished Remount Root and Kernel File Systems.
10877 12:48:50.337030 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10878 12:48:50.351222 <3>[ 20.169461] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10879 12:48:50.364901 <30>[ 20.187070] systemd[1]: Mounting FUSE Control File System...
10880 12:48:50.371287 Mounting [0;1;39mFUSE Control File System[0m...
10881 12:48:50.387183 <30>[ 20.209663] systemd[1]: Mounting Kernel Configuration File System...
10882 12:48:50.398371 Mounting [0;1;39mKernel Configuration <4>[ 20.220033] power_supply_show_property: 1 callbacks suppressed
10883 12:48:50.407950 File System[0m.<3>[ 20.220045] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10884 12:48:50.411740 ..
10885 12:48:50.434834 <30>[ 20.252882] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10886 12:48:50.444588 <3>[ 20.259061] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10887 12:48:50.451089 <30>[ 20.261938] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10888 12:48:50.474170 <3>[ 20.292816] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 12:48:50.481331 <30>[ 20.303570] systemd[1]: Starting Load/Save Random Seed...
10890 12:48:50.487934 Starting [0;1;39mLoad/Save Random Seed[0m...
10891 12:48:50.504500 <30>[ 20.326104] systemd[1]: Starting Apply Kernel Variables...
10892 12:48:50.514372 <3>[ 20.326686] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 12:48:50.517602 Starting [0;1;39mApply Kernel Variables[0m...
10894 12:48:50.535146 <3>[ 20.353978] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 12:48:50.545211 <30>[ 20.366408] systemd[1]: Starting Create System Users...
10896 12:48:50.555296 Starting [0;1;39mCreat<3>[ 20.374645] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 12:48:50.558379 e System Users[0m...
10898 12:48:50.575163 <30>[ 20.397367] systemd[1]: Mounted FUSE Control File System.
10899 12:48:50.582231 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10900 12:48:50.596889 <3>[ 20.415048] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10901 12:48:50.606199 <3>[ 20.415791] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10902 12:48:50.620597 <4>[ 20.432156] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10903 12:48:50.626968 <30>[ 20.432639] systemd[1]: Mounted Kernel Configuration File System.
10904 12:48:50.638169 <3>[ 20.444324] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 12:48:50.644584 <3>[ 20.447798] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10906 12:48:50.650865 <3>[ 20.465940] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 12:48:50.657923 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10908 12:48:50.677060 <29>[ 20.495817] systemd[1]: systemd-udev-trigger.service: Main process exited, code=exited, status=1/FAILURE
10909 12:48:50.687262 <28>[ 20.506013] systemd[1]: systemd-udev-trigger.service: Failed with result 'exit-code'.
10910 12:48:50.694401 <27>[ 20.514766] systemd[1]: Failed to start Coldplug All udev Devices.
10911 12:48:50.701214 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10912 12:48:50.717251 See 'systemctl status systemd-udev-trigger.service' for details.
10913 12:48:50.734578 <30>[ 20.556051] systemd[1]: Finished Load/Save Random Seed.
10914 12:48:50.740775 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10915 12:48:50.756682 <30>[ 20.579476] systemd[1]: Started Journal Service.
10916 12:48:50.763246 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10917 12:48:50.778710 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10918 12:48:50.797573 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10919 12:48:50.829498 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10920 12:48:50.851778 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10921 12:48:50.869908 <46>[ 20.688687] systemd-journald[301]: Received client request to flush runtime journal.
10922 12:48:51.624949 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10923 12:48:51.637244 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10924 12:48:51.653375 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10925 12:48:51.708889 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10926 12:48:52.259282 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10927 12:48:52.297401 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10928 12:48:52.320948 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10929 12:48:52.345004 Starting [0;1;39mNetwork Service[0m...
10930 12:48:52.664805 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10931 12:48:52.690075 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10932 12:48:52.728792 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10933 12:48:53.040105 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10934 12:48:53.057510 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10935 12:48:53.073404 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10936 12:48:53.094494 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10937 12:48:53.112300 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10938 12:48:53.157448 Starting [0;1;39mNetwork Name Resolution[0m...
10939 12:48:53.181734 Starting [0;1;39mNetwork Time Synchronization[0m...
10940 12:48:53.199888 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10941 12:48:53.221107 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10942 12:48:53.251129 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10943 12:48:53.304096 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10944 12:48:53.441298 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10945 12:48:53.456460 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10946 12:48:53.475628 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10947 12:48:53.488633 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10948 12:48:53.504455 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10949 12:48:53.618766 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10950 12:48:53.670050 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10951 12:48:53.703974 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10952 12:48:54.343496 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10953 12:48:54.356569 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10954 12:48:54.433397 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10955 12:48:54.445764 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10956 12:48:54.460152 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10957 12:48:54.496550 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10958 12:48:54.812140 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10959 12:48:54.888794 Starting [0;1;39mUser Login Management[0m...
10960 12:48:54.905236 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10961 12:48:54.921420 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10962 12:48:54.939615 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10963 12:48:54.977141 Starting [0;1;39mPermit User Sessions[0m...
10964 12:48:55.063512 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10965 12:48:55.085098 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10966 12:48:55.121666 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10967 12:48:55.181089 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10968 12:48:55.200778 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10969 12:48:55.217719 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10970 12:48:55.237191 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10971 12:48:55.252243 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10972 12:48:55.308984 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10973 12:48:55.345420 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10974 12:48:55.445262
10975 12:48:55.445408
10976 12:48:55.448381 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10977 12:48:55.448464
10978 12:48:55.451467 debian-bullseye-arm64 login: root (automatic login)
10979 12:48:55.451570
10980 12:48:55.451636
10981 12:48:55.706542 Linux debian-bullseye-arm64 6.1.38-cip1 #1 SMP PREEMPT Thu Jul 20 12:35:57 UTC 2023 aarch64
10982 12:48:55.706728
10983 12:48:55.712996 The programs included with the Debian GNU/Linux system are free software;
10984 12:48:55.720178 the exact distribution terms for each program are described in the
10985 12:48:55.723334 individual files in /usr/share/doc/*/copyright.
10986 12:48:55.723416
10987 12:48:55.729759 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10988 12:48:55.733136 permitted by applicable law.
10989 12:48:55.776809 Matched prompt #10: / #
10991 12:48:55.777050 Setting prompt string to ['/ #']
10992 12:48:55.777145 end: 2.2.5.1 login-action (duration 00:00:26) [common]
10994 12:48:55.777342 end: 2.2.5 auto-login-action (duration 00:00:26) [common]
10995 12:48:55.777428 start: 2.2.6 expect-shell-connection (timeout 00:03:37) [common]
10996 12:48:55.777501 Setting prompt string to ['/ #']
10997 12:48:55.777562 Forcing a shell prompt, looking for ['/ #']
10999 12:48:55.827753 / #
11000 12:48:55.827880 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11001 12:48:55.827959 Waiting using forced prompt support (timeout 00:02:30)
11002 12:48:55.832430
11003 12:48:55.832712 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11004 12:48:55.832812 start: 2.2.7 export-device-env (timeout 00:03:37) [common]
11006 12:48:55.933170 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11118924/extract-nfsrootfs-0csouspo'
11007 12:48:55.938233 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11118924/extract-nfsrootfs-0csouspo'
11009 12:48:56.038769 / # export NFS_SERVER_IP='192.168.201.1'
11010 12:48:56.043835 export NFS_SERVER_IP='192.168.201.1'
11011 12:48:56.044137 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11012 12:48:56.044239 end: 2.2 depthcharge-retry (duration 00:01:23) [common]
11013 12:48:56.044326 end: 2 depthcharge-action (duration 00:01:23) [common]
11014 12:48:56.044417 start: 3 lava-test-retry (timeout 00:01:00) [common]
11015 12:48:56.044506 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11016 12:48:56.044584 Using namespace: common
11018 12:48:56.144939 / # #
11019 12:48:56.145110 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11020 12:48:56.149779 #
11021 12:48:56.150044 Using /lava-11118924
11023 12:48:56.250368 / # export SHELL=/bin/sh
11024 12:48:56.254982 export SHELL=/bin/sh
11026 12:48:56.355575 / # . /lava-11118924/environment
11027 12:48:56.360231 . /lava-11118924/environment
11029 12:48:56.465964 / # /lava-11118924/bin/lava-test-runner /lava-11118924/0
11030 12:48:56.466192 Test shell timeout: 10s (minimum of the action and connection timeout)
11031 12:48:56.471424 /lava-11118924/bin/lava-test-runner /lava-11118924/0
11032 12:48:56.669899 + export TESTRUN_ID=0_dmesg
11033 12:48:56.673212 + cd /lava-11118924/0/tests/0_dmesg
11034 12:48:56.676672 + cat uuid
11035 12:48:56.683256 + UUID=11118924_1.<8>[ 26.505566] <LAVA_SIGNAL_STARTRUN 0_dmesg 11118924_1.6.2.3.1>
11036 12:48:56.683548 Received signal: <STARTRUN> 0_dmesg 11118924_1.6.2.3.1
11037 12:48:56.683704 Starting test lava.0_dmesg (11118924_1.6.2.3.1)
11038 12:48:56.683820 Skipping test definition patterns.
11039 12:48:56.686694 6.2.3.1
11040 12:48:56.686807 + set +x
11041 12:48:56.689669 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11042 12:48:56.765661 <8>[ 26.585396] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11043 12:48:56.765994 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11045 12:48:56.825413 <8>[ 26.645345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11046 12:48:56.825743 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11048 12:48:56.889165 <8>[ 26.709096] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11049 12:48:56.889499 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11051 12:48:56.892470 + set +x
11052 12:48:56.895511 <8>[ 26.718501] <LAVA_SIGNAL_ENDRUN 0_dmesg 11118924_1.6.2.3.1>
11053 12:48:56.895792 Received signal: <ENDRUN> 0_dmesg 11118924_1.6.2.3.1
11054 12:48:56.895886 Ending use of test pattern.
11055 12:48:56.895951 Ending test lava.0_dmesg (11118924_1.6.2.3.1), duration 0.21
11057 12:48:56.901903 <LAVA_TEST_RUNNER EXIT>
11058 12:48:56.902215 ok: lava_test_shell seems to have completed
11059 12:48:56.902325 alert: pass
crit: pass
emerg: pass
11060 12:48:56.902419 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11061 12:48:56.902505 end: 3 lava-test-retry (duration 00:00:01) [common]
11062 12:48:56.902594 start: 4 lava-test-retry (timeout 00:01:00) [common]
11063 12:48:56.902693 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11064 12:48:56.902758 Using namespace: common
11066 12:48:57.003137 / # #
11067 12:48:57.003313 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11068 12:48:57.003466 Using /lava-11118924
11070 12:48:57.103849 export SHELL=/bin/sh
11071 12:48:57.104070 #
11073 12:48:57.204652 / # export SHELL=/bin/sh. /lava-11118924/environment
11074 12:48:57.204869
11076 12:48:57.305401 / # . /lava-11118924/environment/lava-11118924/bin/lava-test-runner /lava-11118924/1
11077 12:48:57.305560 Test shell timeout: 10s (minimum of the action and connection timeout)
11078 12:48:57.305716
11079 12:48:57.310088 / # /lava-11118924/bin/lava-test-runner /lava-11118924/1
11080 12:48:57.408960 + export TESTRUN_ID=1_bootrr
11081 12:48:57.412481 + cd /lava-11118924/1/tests/1_bootrr
11082 12:48:57.415229 + cat uuid
11083 12:48:57.428510 + UUID=11118924_1.<8>[ 27.248498] <LAVA_SIGNAL_STARTRUN 1_bootrr 11118924_1.6.2.3.5>
11084 12:48:57.428659 6.2.3.5
11085 12:48:57.428730 + set +x
11086 12:48:57.428973 Received signal: <STARTRUN> 1_bootrr 11118924_1.6.2.3.5
11087 12:48:57.429044 Starting test lava.1_bootrr (11118924_1.6.2.3.5)
11088 12:48:57.429124 Skipping test definition patterns.
11089 12:48:57.441548 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11118924/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11090 12:48:57.444827 + cd /opt/bootrr/libexec/bootrr
11091 12:48:57.444934 + sh helpers/bootrr-auto
11092 12:48:57.498137 /lava-11118924/1/../bin/lava-test-case
11093 12:48:57.526371 <8>[ 27.346666] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11094 12:48:57.526731 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11096 12:48:57.563908 /lava-11118924/1/../bin/lava-test-case
11097 12:48:57.589092 <8>[ 27.408935] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11098 12:48:57.589422 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11100 12:48:57.610635 /lava-11118924/1/../bin/lava-test-case
11101 12:48:57.631708 <8>[ 27.451503] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11102 12:48:57.632034 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11104 12:48:57.676716 /lava-11118924/1/../bin/lava-test-case
11105 12:48:57.698096 <8>[ 27.518112] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11106 12:48:57.698485 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11108 12:48:57.730682 /lava-11118924/1/../bin/lava-test-case
11109 12:48:57.751167 <8>[ 27.571012] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11110 12:48:57.751501 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11112 12:48:57.778091 /lava-11118924/1/../bin/lava-test-case
11113 12:48:57.799192 <8>[ 27.619068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11114 12:48:57.799549 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11116 12:48:57.825687 /lava-11118924/1/../bin/lava-test-case
11117 12:48:57.846888 <8>[ 27.667203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11118 12:48:57.847211 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11120 12:48:57.878304 /lava-11118924/1/../bin/lava-test-case
11121 12:48:57.900438 <8>[ 27.720699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11122 12:48:57.900768 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11124 12:48:57.919779 /lava-11118924/1/../bin/lava-test-case
11125 12:48:57.942593 <8>[ 27.762453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11126 12:48:57.942922 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11128 12:48:57.970615 /lava-11118924/1/../bin/lava-test-case
11129 12:48:57.995143 <8>[ 27.815364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11130 12:48:57.995469 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11132 12:48:58.013862 /lava-11118924/1/../bin/lava-test-case
11133 12:48:58.034156 <8>[ 27.854415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11134 12:48:58.034526 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11136 12:48:58.073034 /lava-11118924/1/../bin/lava-test-case
11137 12:48:58.093125 <8>[ 27.913248] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11138 12:48:58.093504 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11140 12:48:58.128902 /lava-11118924/1/../bin/lava-test-case
11141 12:48:58.154724 <8>[ 27.974703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11142 12:48:58.155121 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11144 12:48:58.182381 /lava-11118924/1/../bin/lava-test-case
11145 12:48:58.203390 <8>[ 28.023789] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11146 12:48:58.203811 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11148 12:48:58.235053 /lava-11118924/1/../bin/lava-test-case
11149 12:48:58.254853 <8>[ 28.074973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11150 12:48:58.255242 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11152 12:48:58.271631 /lava-11118924/1/../bin/lava-test-case
11153 12:48:58.294921 <8>[ 28.115109] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11154 12:48:58.295324 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11156 12:48:58.323804 /lava-11118924/1/../bin/lava-test-case
11157 12:48:58.346633 <8>[ 28.166767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11158 12:48:58.347030 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11160 12:48:58.374282 /lava-11118924/1/../bin/lava-test-case
11161 12:48:58.394839 <8>[ 28.215044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11162 12:48:58.395230 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11164 12:48:58.422133 /lava-11118924/1/../bin/lava-test-case
11165 12:48:58.442035 <8>[ 28.262392] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11166 12:48:58.442431 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11168 12:48:58.459246 /lava-11118924/1/../bin/lava-test-case
11169 12:48:58.478671 <8>[ 28.299078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11170 12:48:58.479052 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11172 12:48:58.504909 /lava-11118924/1/../bin/lava-test-case
11173 12:48:58.527082 <8>[ 28.347308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11174 12:48:58.527486 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11176 12:48:58.546670 /lava-11118924/1/../bin/lava-test-case
11177 12:48:58.568851 <8>[ 28.388966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11178 12:48:58.569239 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11180 12:48:58.598934 /lava-11118924/1/../bin/lava-test-case
11181 12:48:58.618790 <8>[ 28.439002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11182 12:48:58.619176 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11184 12:48:58.637851 /lava-11118924/1/../bin/lava-test-case
11185 12:48:58.659777 <8>[ 28.479782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11186 12:48:58.660143 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11188 12:48:58.693351 /lava-11118924/1/../bin/lava-test-case
11189 12:48:58.716389 <8>[ 28.536656] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11190 12:48:58.716762 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11192 12:48:58.746394 /lava-11118924/1/../bin/lava-test-case
11193 12:48:58.770793 <8>[ 28.591091] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11194 12:48:58.771163 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11196 12:48:58.788743 /lava-11118924/1/../bin/lava-test-case
11197 12:48:58.810570 <8>[ 28.630556] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11198 12:48:58.810901 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11200 12:48:58.840088 /lava-11118924/1/../bin/lava-test-case
11201 12:48:58.864127 <8>[ 28.684456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11202 12:48:58.864457 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11204 12:48:58.883463 /lava-11118924/1/../bin/lava-test-case
11205 12:48:58.906094 <8>[ 28.726151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11206 12:48:58.906419 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11208 12:48:58.935685 /lava-11118924/1/../bin/lava-test-case
11209 12:48:58.958700 <8>[ 28.778629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11210 12:48:58.959044 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11212 12:48:58.986100 /lava-11118924/1/../bin/lava-test-case
11213 12:48:59.007537 <8>[ 28.827850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11214 12:48:59.007863 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11216 12:48:59.043159 /lava-11118924/1/../bin/lava-test-case
11217 12:48:59.067713 <8>[ 28.887830] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11218 12:48:59.068041 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11220 12:48:59.096996 /lava-11118924/1/../bin/lava-test-case
11221 12:48:59.117370 <8>[ 28.937364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11222 12:48:59.117716 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11224 12:48:59.136983 /lava-11118924/1/../bin/lava-test-case
11225 12:48:59.158057 <8>[ 28.978148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11226 12:48:59.158406 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11228 12:48:59.190333 /lava-11118924/1/../bin/lava-test-case
11229 12:48:59.217353 <8>[ 29.037654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11230 12:48:59.217704 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11232 12:48:59.247499 /lava-11118924/1/../bin/lava-test-case
11233 12:48:59.270242 <8>[ 29.090638] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11234 12:48:59.270566 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11236 12:48:59.290264 /lava-11118924/1/../bin/lava-test-case
11237 12:48:59.315831 <8>[ 29.135746] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11238 12:48:59.316158 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11240 12:48:59.342924 /lava-11118924/1/../bin/lava-test-case
11241 12:48:59.366045 <8>[ 29.186467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11242 12:48:59.366370 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11244 12:48:59.391897 /lava-11118924/1/../bin/lava-test-case
11245 12:48:59.414348 <8>[ 29.234439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11246 12:48:59.414681 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11248 12:48:59.440134 /lava-11118924/1/../bin/lava-test-case
11249 12:48:59.464803 <8>[ 29.284890] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11250 12:48:59.465158 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11252 12:48:59.484892 /lava-11118924/1/../bin/lava-test-case
11253 12:48:59.506181 <8>[ 29.326281] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11254 12:48:59.506535 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11256 12:48:59.535940 /lava-11118924/1/../bin/lava-test-case
11257 12:48:59.558109 <8>[ 29.378679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11258 12:48:59.558438 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11260 12:48:59.577452 /lava-11118924/1/../bin/lava-test-case
11261 12:48:59.599131 <8>[ 29.419463] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11262 12:48:59.599477 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11264 12:48:59.629556 /lava-11118924/1/../bin/lava-test-case
11265 12:48:59.651487 <8>[ 29.471779] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11266 12:48:59.651906 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11268 12:48:59.671304 /lava-11118924/1/../bin/lava-test-case
11269 12:48:59.691446 <8>[ 29.511480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11270 12:48:59.691810 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11272 12:48:59.725648 /lava-11118924/1/../bin/lava-test-case
11273 12:48:59.748387 <8>[ 29.568492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11274 12:48:59.748734 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11276 12:48:59.763410 /lava-11118924/1/../bin/lava-test-case
11277 12:48:59.784100 <8>[ 29.604287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11278 12:48:59.784430 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11280 12:48:59.811957 /lava-11118924/1/../bin/lava-test-case
11281 12:48:59.834297 <8>[ 29.654440] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11282 12:48:59.834674 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11284 12:48:59.853855 /lava-11118924/1/../bin/lava-test-case
11285 12:48:59.874887 <8>[ 29.695205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11286 12:48:59.875199 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11288 12:48:59.902644 /lava-11118924/1/../bin/lava-test-case
11289 12:48:59.926632 <8>[ 29.746989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11290 12:48:59.926911 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11292 12:48:59.954226 /lava-11118924/1/../bin/lava-test-case
11293 12:48:59.977942 <8>[ 29.798011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11294 12:48:59.978219 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11296 12:48:59.994897 /lava-11118924/1/../bin/lava-test-case
11297 12:49:00.018789 <8>[ 29.838828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11298 12:49:00.019076 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11300 12:49:00.053987 /lava-11118924/1/../bin/lava-test-case
11301 12:49:00.074923 <8>[ 29.895332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11302 12:49:00.075238 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11304 12:49:00.093123 /lava-11118924/1/../bin/lava-test-case
11305 12:49:00.117799 <8>[ 29.938016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11306 12:49:00.118092 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11308 12:49:00.150223 /lava-11118924/1/../bin/lava-test-case
11309 12:49:00.173774 <8>[ 29.993988] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11310 12:49:00.174055 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11312 12:49:00.209189 /lava-11118924/1/../bin/lava-test-case
11313 12:49:00.234256 <8>[ 30.054431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11314 12:49:00.234544 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11316 12:49:00.260910 /lava-11118924/1/../bin/lava-test-case
11317 12:49:00.285555 <8>[ 30.105991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11318 12:49:00.285824 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11320 12:49:00.313405 /lava-11118924/1/../bin/lava-test-case
11321 12:49:00.337816 <8>[ 30.158398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11322 12:49:00.338166 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11324 12:49:00.369972 /lava-11118924/1/../bin/lava-test-case
11325 12:49:00.389882 <8>[ 30.210595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11326 12:49:00.390174 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11328 12:49:00.407661 /lava-11118924/1/../bin/lava-test-case
11329 12:49:00.426908 <8>[ 30.247315] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11330 12:49:00.427175 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11332 12:49:00.452511 /lava-11118924/1/../bin/lava-test-case
11333 12:49:00.471951 <8>[ 30.292511] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11334 12:49:00.472253 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11336 12:49:00.502669 /lava-11118924/1/../bin/lava-test-case
11337 12:49:00.523888 <8>[ 30.344392] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11338 12:49:00.524169 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11340 12:49:00.539455 /lava-11118924/1/../bin/lava-test-case
11341 12:49:00.563046 <8>[ 30.383259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11342 12:49:00.563310 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11344 12:49:00.588527 /lava-11118924/1/../bin/lava-test-case
11345 12:49:00.609323 <8>[ 30.429665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11346 12:49:00.609628 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11348 12:49:00.627326 /lava-11118924/1/../bin/lava-test-case
11349 12:49:00.650186 <8>[ 30.470604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11350 12:49:00.650454 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11352 12:49:00.687327 /lava-11118924/1/../bin/lava-test-case
11353 12:49:00.710780 <8>[ 30.531263] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11354 12:49:00.711057 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11356 12:49:00.731178 /lava-11118924/1/../bin/lava-test-case
11357 12:49:00.755795 <8>[ 30.576139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11358 12:49:00.756109 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11360 12:49:00.786898 /lava-11118924/1/../bin/lava-test-case
11361 12:49:00.809322 <8>[ 30.629986] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11362 12:49:00.809631 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11364 12:49:00.839923 /lava-11118924/1/../bin/lava-test-case
11365 12:49:00.866406 <8>[ 30.686581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11366 12:49:00.866747 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11368 12:49:00.894384 /lava-11118924/1/../bin/lava-test-case
11369 12:49:00.916876 <8>[ 30.737288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11370 12:49:00.917179 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11372 12:49:00.946475 /lava-11118924/1/../bin/lava-test-case
11373 12:49:00.967775 <8>[ 30.787847] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11374 12:49:00.968043 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11376 12:49:01.005441 /lava-11118924/1/../bin/lava-test-case
11377 12:49:01.025771 <8>[ 30.846260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11378 12:49:01.026049 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11380 12:49:01.057617 /lava-11118924/1/../bin/lava-test-case
11381 12:49:01.078899 <8>[ 30.899716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11382 12:49:01.079178 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11384 12:49:01.107348 /lava-11118924/1/../bin/lava-test-case
11385 12:49:01.130091 <8>[ 30.950814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11386 12:49:01.130411 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11388 12:49:01.158624 /lava-11118924/1/../bin/lava-test-case
11389 12:49:01.181634 <8>[ 31.002008] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11390 12:49:01.181920 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11392 12:49:01.213292 /lava-11118924/1/../bin/lava-test-case
11393 12:49:01.235129 <8>[ 31.055585] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11394 12:49:01.235411 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11396 12:49:01.268410 /lava-11118924/1/../bin/lava-test-case
11397 12:49:01.294831 <8>[ 31.115266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11398 12:49:01.295109 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11400 12:49:01.330055 /lava-11118924/1/../bin/lava-test-case
11401 12:49:01.354916 <8>[ 31.175306] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11402 12:49:01.355256 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11404 12:49:01.390550 /lava-11118924/1/../bin/lava-test-case
11405 12:49:01.417806 <8>[ 31.238038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11406 12:49:01.418105 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11408 12:49:01.447215 /lava-11118924/1/../bin/lava-test-case
11409 12:49:01.468119 <8>[ 31.288560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11410 12:49:01.468387 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11412 12:49:01.499121 /lava-11118924/1/../bin/lava-test-case
11413 12:49:01.520064 <8>[ 31.340446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11414 12:49:01.520353 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11416 12:49:01.549118 /lava-11118924/1/../bin/lava-test-case
11417 12:49:01.572627 <8>[ 31.392973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11418 12:49:01.572891 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11420 12:49:01.593837 /lava-11118924/1/../bin/lava-test-case
11421 12:49:01.616813 <8>[ 31.437187] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11422 12:49:01.617095 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11424 12:49:01.653384 /lava-11118924/1/../bin/lava-test-case
11425 12:49:01.674639 <8>[ 31.495465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11426 12:49:01.674908 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11428 12:49:01.694524 /lava-11118924/1/../bin/lava-test-case
11429 12:49:01.721048 <8>[ 31.541896] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11430 12:49:01.721323 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11432 12:49:01.751779 /lava-11118924/1/../bin/lava-test-case
11433 12:49:01.777642 <8>[ 31.598377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11434 12:49:01.777914 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11436 12:49:01.797148 /lava-11118924/1/../bin/lava-test-case
11437 12:49:01.821513 <8>[ 31.641916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11438 12:49:01.821790 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11440 12:49:01.850822 /lava-11118924/1/../bin/lava-test-case
11441 12:49:01.872574 <8>[ 31.693017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11442 12:49:01.872836 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11444 12:49:01.892211 /lava-11118924/1/../bin/lava-test-case
11445 12:49:01.913800 <8>[ 31.734229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11446 12:49:01.914068 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11448 12:49:01.942928 /lava-11118924/1/../bin/lava-test-case
11449 12:49:01.966631 <8>[ 31.787053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11450 12:49:01.966900 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11452 12:49:01.994177 /lava-11118924/1/../bin/lava-test-case
11453 12:49:02.016742 <8>[ 31.837135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11454 12:49:02.017012 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11456 12:49:02.047250 /lava-11118924/1/../bin/lava-test-case
11457 12:49:02.069699 <8>[ 31.890178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11458 12:49:02.069965 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11460 12:49:02.087437 /lava-11118924/1/../bin/lava-test-case
11461 12:49:02.111315 <8>[ 31.931974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11462 12:49:02.111630 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11464 12:49:02.142588 /lava-11118924/1/../bin/lava-test-case
11465 12:49:02.166362 <8>[ 31.986504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11466 12:49:02.166625 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11468 12:49:02.191209 /lava-11118924/1/../bin/lava-test-case
11469 12:49:02.215877 <8>[ 32.036689] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11470 12:49:02.216149 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11472 12:49:02.235764 /lava-11118924/1/../bin/lava-test-case
11473 12:49:02.257388 <8>[ 32.078101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11474 12:49:02.257651 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11476 12:49:02.288979 /lava-11118924/1/../bin/lava-test-case
11477 12:49:02.310682 <8>[ 32.131521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11478 12:49:02.310956 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11480 12:49:02.337255 /lava-11118924/1/../bin/lava-test-case
11481 12:49:02.358062 <8>[ 32.178834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11482 12:49:02.358379 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11484 12:49:02.385588 /lava-11118924/1/../bin/lava-test-case
11485 12:49:02.409407 <8>[ 32.230145] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11486 12:49:02.409710 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11488 12:49:02.429661 /lava-11118924/1/../bin/lava-test-case
11489 12:49:02.450325 <8>[ 32.270794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11490 12:49:02.450587 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11492 12:49:03.495731 /lava-11118924/1/../bin/lava-test-case
11493 12:49:03.521322 <8>[ 33.342153] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11494 12:49:03.521638 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11496 12:49:03.541253 /lava-11118924/1/../bin/lava-test-case
11497 12:49:03.564436 <8>[ 33.385457] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11498 12:49:03.564709 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11500 12:49:04.604118 /lava-11118924/1/../bin/lava-test-case
11501 12:49:04.629153 <8>[ 34.450240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11502 12:49:04.629479 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11504 12:49:04.649377 /lava-11118924/1/../bin/lava-test-case
11505 12:49:04.676320 <8>[ 34.497365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11506 12:49:04.676689 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11508 12:49:05.712368 /lava-11118924/1/../bin/lava-test-case
11509 12:49:05.732572 <8>[ 35.553725] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11510 12:49:05.732918 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11512 12:49:05.751417 /lava-11118924/1/../bin/lava-test-case
11513 12:49:05.769497 <8>[ 35.590223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11514 12:49:05.769821 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11516 12:49:06.798923 /lava-11118924/1/../bin/lava-test-case
11517 12:49:06.821131 <8>[ 36.642440] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11518 12:49:06.821467 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11520 12:49:06.838621 /lava-11118924/1/../bin/lava-test-case
11521 12:49:06.860815 <8>[ 36.682166] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11522 12:49:06.861132 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11524 12:49:07.895441 /lava-11118924/1/../bin/lava-test-case
11525 12:49:07.917282 <8>[ 37.738372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11526 12:49:07.917630 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11528 12:49:07.937230 /lava-11118924/1/../bin/lava-test-case
11529 12:49:07.961204 <8>[ 37.782626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11530 12:49:07.961554 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11532 12:49:09.000055 /lava-11118924/1/../bin/lava-test-case
11533 12:49:09.025808 <8>[ 38.847069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11534 12:49:09.026125 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11536 12:49:09.045284 /lava-11118924/1/../bin/lava-test-case
11537 12:49:09.067417 <8>[ 38.889049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11538 12:49:09.067742 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11540 12:49:10.104134 /lava-11118924/1/../bin/lava-test-case
11541 12:49:10.131764 <8>[ 39.952945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11542 12:49:10.132128 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11544 12:49:10.150407 /lava-11118924/1/../bin/lava-test-case
11545 12:49:10.176828 <8>[ 39.998483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11546 12:49:10.177194 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11548 12:49:10.201114 /lava-11118924/1/../bin/lava-test-case
11549 12:49:10.222661 <8>[ 40.043773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11550 12:49:10.222983 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11552 12:49:11.262165 /lava-11118924/1/../bin/lava-test-case
11553 12:49:11.290915 <8>[ 41.112661] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11554 12:49:11.291300 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11556 12:49:11.312573 /lava-11118924/1/../bin/lava-test-case
11557 12:49:11.334373 <8>[ 41.155959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11558 12:49:11.334706 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11560 12:49:11.364993 /lava-11118924/1/../bin/lava-test-case
11561 12:49:11.387283 <8>[ 41.208638] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11562 12:49:11.387643 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11564 12:49:11.406599 /lava-11118924/1/../bin/lava-test-case
11565 12:49:11.430129 <8>[ 41.251446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11566 12:49:11.430489 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11568 12:49:11.459185 /lava-11118924/1/../bin/lava-test-case
11569 12:49:11.481957 <8>[ 41.303596] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11570 12:49:11.482322 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11572 12:49:11.510607 /lava-11118924/1/../bin/lava-test-case
11573 12:49:11.533913 <8>[ 41.355751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11574 12:49:11.534272 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11576 12:49:11.564801 /lava-11118924/1/../bin/lava-test-case
11577 12:49:11.586841 <8>[ 41.408796] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11578 12:49:11.587219 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11580 12:49:11.614115 /lava-11118924/1/../bin/lava-test-case
11581 12:49:11.637330 <8>[ 41.459172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11582 12:49:11.637676 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11584 12:49:11.669378 /lava-11118924/1/../bin/lava-test-case
11585 12:49:11.693192 <8>[ 41.515216] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11586 12:49:11.693531 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11588 12:49:11.726145 /lava-11118924/1/../bin/lava-test-case
11589 12:49:11.747159 <8>[ 41.569262] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11590 12:49:11.747493 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11592 12:49:11.765451 /lava-11118924/1/../bin/lava-test-case
11593 12:49:11.787696 <8>[ 41.609164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11594 12:49:11.788029 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11596 12:49:11.815763 /lava-11118924/1/../bin/lava-test-case
11597 12:49:11.836386 <8>[ 41.658364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11598 12:49:11.836714 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11600 12:49:11.855325 /lava-11118924/1/../bin/lava-test-case
11601 12:49:11.877366 <8>[ 41.699155] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11602 12:49:11.877701 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11604 12:49:11.904967 /lava-11118924/1/../bin/lava-test-case
11605 12:49:11.928259 <8>[ 41.750268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11606 12:49:11.928617 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11608 12:49:11.957365 /lava-11118924/1/../bin/lava-test-case
11609 12:49:11.978271 <8>[ 41.800136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11610 12:49:11.978607 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11612 12:49:12.005596 /lava-11118924/1/../bin/lava-test-case
11613 12:49:12.025167 <8>[ 41.846783] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11614 12:49:12.025533 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11616 12:49:12.044024 /lava-11118924/1/../bin/lava-test-case
11617 12:49:12.071377 <8>[ 41.892957] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11618 12:49:12.071773 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11620 12:49:12.099284 /lava-11118924/1/../bin/lava-test-case
11621 12:49:12.120543 <8>[ 41.942545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11622 12:49:12.120911 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11624 12:49:12.139344 /lava-11118924/1/../bin/lava-test-case
11625 12:49:12.162518 <8>[ 41.984070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11626 12:49:12.162846 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11628 12:49:12.189089 /lava-11118924/1/../bin/lava-test-case
11629 12:49:12.210993 <8>[ 42.032514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11630 12:49:12.211368 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11632 12:49:12.227492 /lava-11118924/1/../bin/lava-test-case
11633 12:49:12.247660 <8>[ 42.069271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11634 12:49:12.248002 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11636 12:49:13.290564 /lava-11118924/1/../bin/lava-test-case
11637 12:49:13.314864 <8>[ 43.136641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11638 12:49:13.315236 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11640 12:49:14.353431 /lava-11118924/1/../bin/lava-test-case
11641 12:49:14.378347 <8>[ 44.200542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11642 12:49:14.378730 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11644 12:49:14.398010 /lava-11118924/1/../bin/lava-test-case
11645 12:49:14.416250 <8>[ 44.238128] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11646 12:49:14.416590 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11648 12:49:14.442913 /lava-11118924/1/../bin/lava-test-case
11649 12:49:14.466498 <8>[ 44.288420] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11650 12:49:14.466837 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11652 12:49:14.484540 /lava-11118924/1/../bin/lava-test-case
11653 12:49:14.507752 <8>[ 44.329644] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11654 12:49:14.508103 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11656 12:49:14.536554 /lava-11118924/1/../bin/lava-test-case
11657 12:49:14.557575 <8>[ 44.379318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11658 12:49:14.557940 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11660 12:49:14.576780 /lava-11118924/1/../bin/lava-test-case
11661 12:49:14.598738 <8>[ 44.420611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11662 12:49:14.599071 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11664 12:49:14.623720 /lava-11118924/1/../bin/lava-test-case
11665 12:49:14.644454 <8>[ 44.466739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11666 12:49:14.644786 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11668 12:49:14.672137 /lava-11118924/1/../bin/lava-test-case
11669 12:49:14.695646 <8>[ 44.517755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11670 12:49:14.695973 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11672 12:49:14.722620 /lava-11118924/1/../bin/lava-test-case
11673 12:49:14.745818 <8>[ 44.567892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11674 12:49:14.746179 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11676 12:49:14.765514 /lava-11118924/1/../bin/lava-test-case
11677 12:49:14.786777 <8>[ 44.609040] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11678 12:49:14.787106 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11680 12:49:14.816824 /lava-11118924/1/../bin/lava-test-case
11681 12:49:14.837867 <8>[ 44.659749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11682 12:49:14.838224 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11684 12:49:14.857262 /lava-11118924/1/../bin/lava-test-case
11685 12:49:14.883543 <8>[ 44.705447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11686 12:49:14.883884 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11688 12:49:14.911972 /lava-11118924/1/../bin/lava-test-case
11689 12:49:14.932941 <8>[ 44.755195] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11690 12:49:14.933313 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11692 12:49:14.950712 /lava-11118924/1/../bin/lava-test-case
11693 12:49:14.968270 <8>[ 44.790126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11694 12:49:14.968640 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11696 12:49:15.001794 /lava-11118924/1/../bin/lava-test-case
11697 12:49:15.020386 <8>[ 44.842758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11698 12:49:15.020750 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11700 12:49:15.036562 /lava-11118924/1/../bin/lava-test-case
11701 12:49:15.056501 <8>[ 44.878716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11702 12:49:15.056899 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11704 12:49:15.078736 /lava-11118924/1/../bin/lava-test-case
11705 12:49:15.094379 <8>[ 44.916477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11706 12:49:15.094727 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11708 12:49:15.111556 /lava-11118924/1/../bin/lava-test-case
11709 12:49:15.131113 <8>[ 44.953431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11710 12:49:15.131467 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11712 12:49:15.158707 /lava-11118924/1/../bin/lava-test-case
11713 12:49:15.175219 <8>[ 44.997428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11714 12:49:15.175563 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11716 12:49:15.190772 /lava-11118924/1/../bin/lava-test-case
11717 12:49:15.207021 <8>[ 45.028931] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11718 12:49:15.207365 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11720 12:49:15.229506 /lava-11118924/1/../bin/lava-test-case
11721 12:49:15.249679 <8>[ 45.072007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11722 12:49:15.250020 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11724 12:49:16.270227 /lava-11118924/1/../bin/lava-test-case
11725 12:49:16.297835 <8>[ 46.119796] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11726 12:49:16.298154 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11728 12:49:16.326181 <6>[ 46.155141] vpu: disabling
11729 12:49:16.329446 <6>[ 46.158193] vproc2: disabling
11730 12:49:16.332869 <6>[ 46.161477] vproc1: disabling
11731 12:49:16.336173 <6>[ 46.164755] vaud18: disabling
11732 12:49:16.343123 <6>[ 46.168162] vsram_others: disabling
11733 12:49:16.343295 <6>[ 46.172040] va09: disabling
11734 12:49:16.349594 <6>[ 46.175142] vsram_md: disabling
11735 12:49:16.349734 <6>[ 46.178625] Vgpu: disabling
11736 12:49:17.329112 /lava-11118924/1/../bin/lava-test-case
11737 12:49:17.356547 <8>[ 47.178694] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11738 12:49:17.357001 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11739 12:49:17.357179 Bad test result: blocked
11740 12:49:17.375198 /lava-11118924/1/../bin/lava-test-case
11741 12:49:17.399514 <8>[ 47.221707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11742 12:49:17.399923 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11744 12:49:18.435484 /lava-11118924/1/../bin/lava-test-case
11745 12:49:18.463322 <8>[ 48.285781] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11746 12:49:18.463686 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11748 12:49:18.482818 /lava-11118924/1/../bin/lava-test-case
11749 12:49:18.507746 <8>[ 48.330443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11750 12:49:18.508125 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11752 12:49:18.536874 /lava-11118924/1/../bin/lava-test-case
11753 12:49:18.560055 <8>[ 48.382616] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11754 12:49:18.560456 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11756 12:49:18.588733 /lava-11118924/1/../bin/lava-test-case
11757 12:49:18.611117 <8>[ 48.433515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11758 12:49:18.611542 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11760 12:49:18.629698 /lava-11118924/1/../bin/lava-test-case
11761 12:49:18.651811 <8>[ 48.474005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11762 12:49:18.652198 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11764 12:49:18.678396 /lava-11118924/1/../bin/lava-test-case
11765 12:49:18.697807 <8>[ 48.520024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11766 12:49:18.698202 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11768 12:49:18.716017 /lava-11118924/1/../bin/lava-test-case
11769 12:49:18.739013 <8>[ 48.561308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11770 12:49:18.739351 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11772 12:49:19.779866 /lava-11118924/1/../bin/lava-test-case
11773 12:49:19.804375 <8>[ 49.626943] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11774 12:49:19.804745 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11776 12:49:19.819605 /lava-11118924/1/../bin/lava-test-case
11777 12:49:19.835976 <8>[ 49.658574] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11778 12:49:19.836343 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11780 12:49:20.870750 /lava-11118924/1/../bin/lava-test-case
11781 12:49:20.893748 <8>[ 50.716298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11782 12:49:20.894110 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11784 12:49:20.912393 /lava-11118924/1/../bin/lava-test-case
11785 12:49:20.932137 <8>[ 50.754648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11786 12:49:20.932490 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11788 12:49:21.961010 /lava-11118924/1/../bin/lava-test-case
11789 12:49:21.979376 <8>[ 51.802318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11790 12:49:21.979743 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11792 12:49:21.994877 /lava-11118924/1/../bin/lava-test-case
11793 12:49:22.012120 <8>[ 51.834844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11794 12:49:22.012411 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11796 12:49:23.042758 /lava-11118924/1/../bin/lava-test-case
11797 12:49:23.069416 <8>[ 52.892521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11798 12:49:23.069729 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11800 12:49:23.088392 /lava-11118924/1/../bin/lava-test-case
11801 12:49:23.111302 <8>[ 52.934360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11802 12:49:23.111561 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11804 12:49:23.141190 /lava-11118924/1/../bin/lava-test-case
11805 12:49:23.175071 <8>[ 52.998028] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11806 12:49:23.175410 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11808 12:49:23.200274 /lava-11118924/1/../bin/lava-test-case
11809 12:49:23.219626 <8>[ 53.042630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11810 12:49:23.219902 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11812 12:49:23.235436 /lava-11118924/1/../bin/lava-test-case
11813 12:49:23.258061 <8>[ 53.081303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11814 12:49:23.258350 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11816 12:49:23.286613 /lava-11118924/1/../bin/lava-test-case
11817 12:49:23.309228 <8>[ 53.132099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11818 12:49:23.309493 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11820 12:49:23.327637 /lava-11118924/1/../bin/lava-test-case
11821 12:49:23.346827 <8>[ 53.169849] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11822 12:49:23.347117 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11824 12:49:23.381548 /lava-11118924/1/../bin/lava-test-case
11825 12:49:23.400415 <8>[ 53.223446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11826 12:49:23.400696 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11828 12:49:23.417775 /lava-11118924/1/../bin/lava-test-case
11829 12:49:23.439786 <8>[ 53.262532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11830 12:49:23.440071 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11832 12:49:24.477259 /lava-11118924/1/../bin/lava-test-case
11833 12:49:24.499892 <8>[ 54.323384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>
11834 12:49:24.500234 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11836 12:49:24.507858 + <8>[ 54.334436] <LAVA_SIGNAL_ENDRUN 1_bootrr 11118924_1.6.2.3.5>
11837 12:49:24.508155 Received signal: <ENDRUN> 1_bootrr 11118924_1.6.2.3.5
11838 12:49:24.508262 Ending use of test pattern.
11839 12:49:24.508368 Ending test lava.1_bootrr (11118924_1.6.2.3.5), duration 27.08
11841 12:49:24.510837 set +x
11842 12:49:24.514175 <LAVA_TEST_RUNNER EXIT>
11843 12:49:24.514453 ok: lava_test_shell seems to have completed
11844 12:49:24.515574 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11845 12:49:24.515754 end: 4.1 lava-test-shell (duration 00:00:28) [common]
11846 12:49:24.515854 end: 4 lava-test-retry (duration 00:00:28) [common]
11847 12:49:24.515944 start: 5 finalize (timeout 00:07:41) [common]
11848 12:49:24.516061 start: 5.1 power-off (timeout 00:00:30) [common]
11849 12:49:24.516235 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11850 12:49:24.592941 >> Command sent successfully.
11851 12:49:24.595437 Returned 0 in 0 seconds
11852 12:49:24.695889 end: 5.1 power-off (duration 00:00:00) [common]
11854 12:49:24.696237 start: 5.2 read-feedback (timeout 00:07:41) [common]
11855 12:49:24.696515 Listened to connection for namespace 'common' for up to 1s
11856 12:49:25.697438 Finalising connection for namespace 'common'
11857 12:49:25.697649 Disconnecting from shell: Finalise
11858 12:49:25.697760 / #
11859 12:49:25.798128 end: 5.2 read-feedback (duration 00:00:01) [common]
11860 12:49:25.798327 end: 5 finalize (duration 00:00:01) [common]
11861 12:49:25.798467 Cleaning after the job
11862 12:49:25.798585 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11118924/tftp-deploy-pu23uz5a/ramdisk
11863 12:49:25.799169 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11118924/tftp-deploy-pu23uz5a/kernel
11864 12:49:25.804280 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11118924/tftp-deploy-pu23uz5a/dtb
11865 12:49:25.804455 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11118924/tftp-deploy-pu23uz5a/nfsrootfs
11866 12:49:25.820792 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11118924/tftp-deploy-pu23uz5a/modules
11867 12:49:25.828115 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11118924
11868 12:49:26.130328 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11118924
11869 12:49:26.130518 Job finished correctly