Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 131
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 23
- Warnings: 1
1 12:46:03.230909 lava-dispatcher, installed at version: 2023.05.1
2 12:46:03.231151 start: 0 validate
3 12:46:03.231287 Start time: 2023-07-20 12:46:03.231279+00:00 (UTC)
4 12:46:03.231415 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:46:03.231551 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:46:03.501685 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:46:03.502452 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.38-cip1-7-g5cff59cac977b%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:46:39.334462 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:46:39.334680 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.38-cip1-7-g5cff59cac977b%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:46:39.601241 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:46:39.601413 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.38-cip1-7-g5cff59cac977b%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:46:43.308935 validate duration: 40.08
14 12:46:43.309233 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:46:43.309352 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:46:43.309459 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:46:43.309597 Not decompressing ramdisk as can be used compressed.
18 12:46:43.309703 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 12:46:43.309781 saving as /var/lib/lava/dispatcher/tmp/11118892/tftp-deploy-rgu9yvwm/ramdisk/rootfs.cpio.gz
20 12:46:43.309853 total size: 84918747 (80MB)
21 12:46:43.674056 progress 0% (0MB)
22 12:46:43.754597 progress 5% (4MB)
23 12:46:44.100967 progress 10% (8MB)
24 12:46:44.265098 progress 15% (12MB)
25 12:46:44.434716 progress 20% (16MB)
26 12:46:44.559933 progress 25% (20MB)
27 12:46:44.628216 progress 30% (24MB)
28 12:46:44.698669 progress 35% (28MB)
29 12:46:44.807100 progress 40% (32MB)
30 12:46:44.927337 progress 45% (36MB)
31 12:46:45.023648 progress 50% (40MB)
32 12:46:45.110201 progress 55% (44MB)
33 12:46:45.172084 progress 60% (48MB)
34 12:46:45.254108 progress 65% (52MB)
35 12:46:45.383877 progress 70% (56MB)
36 12:46:45.456870 progress 75% (60MB)
37 12:46:45.555335 progress 80% (64MB)
38 12:46:45.650185 progress 85% (68MB)
39 12:46:45.724142 progress 90% (72MB)
40 12:46:45.764010 progress 95% (76MB)
41 12:46:45.803666 progress 100% (80MB)
42 12:46:45.803928 80MB downloaded in 2.49s (32.47MB/s)
43 12:46:45.804131 end: 1.1.1 http-download (duration 00:00:02) [common]
45 12:46:45.804505 end: 1.1 download-retry (duration 00:00:02) [common]
46 12:46:45.804620 start: 1.2 download-retry (timeout 00:09:58) [common]
47 12:46:45.804779 start: 1.2.1 http-download (timeout 00:09:58) [common]
48 12:46:45.804955 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.38-cip1-7-g5cff59cac977b/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:46:45.805056 saving as /var/lib/lava/dispatcher/tmp/11118892/tftp-deploy-rgu9yvwm/kernel/Image
50 12:46:45.805160 total size: 48564736 (46MB)
51 12:46:45.805249 No compression specified
52 12:46:45.806425 progress 0% (0MB)
53 12:46:45.819289 progress 5% (2MB)
54 12:46:45.832231 progress 10% (4MB)
55 12:46:45.845329 progress 15% (6MB)
56 12:46:45.858588 progress 20% (9MB)
57 12:46:45.871763 progress 25% (11MB)
58 12:46:45.885035 progress 30% (13MB)
59 12:46:45.897962 progress 35% (16MB)
60 12:46:45.911697 progress 40% (18MB)
61 12:46:45.924726 progress 45% (20MB)
62 12:46:45.937787 progress 50% (23MB)
63 12:46:45.950765 progress 55% (25MB)
64 12:46:45.964051 progress 60% (27MB)
65 12:46:45.976892 progress 65% (30MB)
66 12:46:45.989639 progress 70% (32MB)
67 12:46:46.002344 progress 75% (34MB)
68 12:46:46.015255 progress 80% (37MB)
69 12:46:46.027991 progress 85% (39MB)
70 12:46:46.040476 progress 90% (41MB)
71 12:46:46.053061 progress 95% (44MB)
72 12:46:46.065945 progress 100% (46MB)
73 12:46:46.066112 46MB downloaded in 0.26s (177.49MB/s)
74 12:46:46.066270 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:46:46.066537 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:46:46.066622 start: 1.3 download-retry (timeout 00:09:57) [common]
78 12:46:46.066706 start: 1.3.1 http-download (timeout 00:09:57) [common]
79 12:46:46.066843 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.38-cip1-7-g5cff59cac977b/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:46:46.066915 saving as /var/lib/lava/dispatcher/tmp/11118892/tftp-deploy-rgu9yvwm/dtb/mt8192-asurada-spherion-r0.dtb
81 12:46:46.066976 total size: 46924 (0MB)
82 12:46:46.067034 No compression specified
83 12:46:48.702142 progress 69% (0MB)
84 12:46:48.702849 progress 100% (0MB)
85 12:46:48.703226 0MB downloaded in 2.64s (0.02MB/s)
86 12:46:48.703523 end: 1.3.1 http-download (duration 00:00:03) [common]
88 12:46:48.704052 end: 1.3 download-retry (duration 00:00:03) [common]
89 12:46:48.704247 start: 1.4 download-retry (timeout 00:09:55) [common]
90 12:46:48.704438 start: 1.4.1 http-download (timeout 00:09:55) [common]
91 12:46:48.745013 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.38-cip1-7-g5cff59cac977b/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:46:48.745164 saving as /var/lib/lava/dispatcher/tmp/11118892/tftp-deploy-rgu9yvwm/modules/modules.tar
93 12:46:48.745237 total size: 8543056 (8MB)
94 12:46:48.745303 Using unxz to decompress xz
95 12:46:51.173622 progress 0% (0MB)
96 12:46:51.204164 progress 5% (0MB)
97 12:46:51.237404 progress 10% (0MB)
98 12:46:51.262820 progress 15% (1MB)
99 12:46:51.291040 progress 20% (1MB)
100 12:46:51.317748 progress 25% (2MB)
101 12:46:51.344776 progress 30% (2MB)
102 12:46:51.371562 progress 35% (2MB)
103 12:46:51.398377 progress 40% (3MB)
104 12:46:51.425589 progress 45% (3MB)
105 12:46:51.450867 progress 50% (4MB)
106 12:46:51.477641 progress 55% (4MB)
107 12:46:51.504102 progress 60% (4MB)
108 12:46:51.530984 progress 65% (5MB)
109 12:46:51.561094 progress 70% (5MB)
110 12:46:51.591839 progress 75% (6MB)
111 12:46:51.617650 progress 80% (6MB)
112 12:46:51.642071 progress 85% (6MB)
113 12:46:51.667358 progress 90% (7MB)
114 12:46:51.693226 progress 95% (7MB)
115 12:46:51.720248 progress 100% (8MB)
116 12:46:51.726693 8MB downloaded in 2.98s (2.73MB/s)
117 12:46:51.727031 end: 1.4.1 http-download (duration 00:00:03) [common]
119 12:46:51.727321 end: 1.4 download-retry (duration 00:00:03) [common]
120 12:46:51.727419 start: 1.5 prepare-tftp-overlay (timeout 00:09:52) [common]
121 12:46:51.727516 start: 1.5.1 extract-nfsrootfs (timeout 00:09:52) [common]
122 12:46:51.727611 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:46:51.727723 start: 1.5.2 lava-overlay (timeout 00:09:52) [common]
124 12:46:51.727976 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm
125 12:46:51.728146 makedir: /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin
126 12:46:51.728301 makedir: /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/tests
127 12:46:51.728448 makedir: /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/results
128 12:46:51.728607 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-add-keys
129 12:46:51.728814 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-add-sources
130 12:46:51.728971 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-background-process-start
131 12:46:51.729129 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-background-process-stop
132 12:46:51.729305 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-common-functions
133 12:46:51.729459 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-echo-ipv4
134 12:46:51.729639 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-install-packages
135 12:46:51.729816 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-installed-packages
136 12:46:51.729994 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-os-build
137 12:46:51.730172 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-probe-channel
138 12:46:51.730355 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-probe-ip
139 12:46:51.730496 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-target-ip
140 12:46:51.730629 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-target-mac
141 12:46:51.730760 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-target-storage
142 12:46:51.730929 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-test-case
143 12:46:51.731149 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-test-event
144 12:46:51.731346 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-test-feedback
145 12:46:51.731515 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-test-raise
146 12:46:51.731683 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-test-reference
147 12:46:51.731848 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-test-runner
148 12:46:51.732036 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-test-set
149 12:46:51.732242 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-test-shell
150 12:46:51.732414 Updating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-install-packages (oe)
151 12:46:51.733540 Updating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/bin/lava-installed-packages (oe)
152 12:46:51.734934 Creating /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/environment
153 12:46:51.735125 LAVA metadata
154 12:46:51.735262 - LAVA_JOB_ID=11118892
155 12:46:51.735333 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:46:51.735450 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:52) [common]
157 12:46:51.735520 skipped lava-vland-overlay
158 12:46:51.735597 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:46:51.735684 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:52) [common]
160 12:46:51.735749 skipped lava-multinode-overlay
161 12:46:51.735827 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:46:51.735912 start: 1.5.2.3 test-definition (timeout 00:09:52) [common]
163 12:46:51.735990 Loading test definitions
164 12:46:51.736085 start: 1.5.2.3.1 git-repo-action (timeout 00:09:52) [common]
165 12:46:51.736164 Using /lava-11118892 at stage 0
166 12:46:51.736282 Fetching tests from https://github.com/kernelci/kernelci-core
167 12:46:51.736437 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/0/tests/0_sleep'
168 12:46:52.749479 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/0/tests/0_sleep
169 12:46:52.751156 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 12:46:52.751703 uuid=11118892_1.5.2.3.1 testdef=None
171 12:46:52.751899 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 12:46:52.752273 start: 1.5.2.3.2 test-overlay (timeout 00:09:51) [common]
174 12:46:52.753126 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 12:46:52.753486 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:51) [common]
177 12:46:52.825832 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 12:46:52.826243 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
180 12:46:52.898051 runner path: /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/0/tests/0_sleep test_uuid 11118892_1.5.2.3.1
181 12:46:52.898234 sleep_params='mem freeze'
182 12:46:52.898470 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 12:46:52.898809 Creating lava-test-runner.conf files
185 12:46:52.898907 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11118892/lava-overlay-x4bfrvpm/lava-11118892/0 for stage 0
186 12:46:52.899043 - 0_sleep
187 12:46:52.899197 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 12:46:52.899331 start: 1.5.2.4 compress-overlay (timeout 00:09:50) [common]
189 12:46:53.038206 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 12:46:53.038374 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
191 12:46:53.038499 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 12:46:53.038639 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 12:46:53.038731 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
194 12:46:55.964743 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:03) [common]
195 12:46:55.965278 start: 1.5.4 extract-modules (timeout 00:09:47) [common]
196 12:46:55.965465 extracting modules file /var/lib/lava/dispatcher/tmp/11118892/tftp-deploy-rgu9yvwm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11118892/extract-overlay-ramdisk-sq4wuvlw/ramdisk
197 12:46:56.216563 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 12:46:56.216769 start: 1.5.5 apply-overlay-tftp (timeout 00:09:47) [common]
199 12:46:56.216869 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11118892/compress-overlay-wgip7zoy/overlay-1.5.2.4.tar.gz to ramdisk
200 12:46:56.216940 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11118892/compress-overlay-wgip7zoy/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11118892/extract-overlay-ramdisk-sq4wuvlw/ramdisk
201 12:46:56.315597 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 12:46:56.315755 start: 1.5.6 configure-preseed-file (timeout 00:09:47) [common]
203 12:46:56.315848 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 12:46:56.315942 start: 1.5.7 compress-ramdisk (timeout 00:09:47) [common]
205 12:46:56.316029 Building ramdisk /var/lib/lava/dispatcher/tmp/11118892/extract-overlay-ramdisk-sq4wuvlw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11118892/extract-overlay-ramdisk-sq4wuvlw/ramdisk
206 12:46:58.970759 >> 561900 blocks
207 12:47:08.896526 rename /var/lib/lava/dispatcher/tmp/11118892/extract-overlay-ramdisk-sq4wuvlw/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11118892/tftp-deploy-rgu9yvwm/ramdisk/ramdisk.cpio.gz
208 12:47:08.897016 end: 1.5.7 compress-ramdisk (duration 00:00:13) [common]
209 12:47:08.897153 start: 1.5.8 prepare-kernel (timeout 00:09:34) [common]
210 12:47:08.897264 start: 1.5.8.1 prepare-fit (timeout 00:09:34) [common]
211 12:47:08.897399 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11118892/tftp-deploy-rgu9yvwm/kernel/Image'
212 12:47:22.212542 Returned 0 in 13 seconds
213 12:47:22.313200 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11118892/tftp-deploy-rgu9yvwm/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11118892/tftp-deploy-rgu9yvwm/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11118892/tftp-deploy-rgu9yvwm/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11118892/tftp-deploy-rgu9yvwm/kernel/image.itb
214 12:47:24.256109 output: FIT description: Kernel Image image with one or more FDT blobs
215 12:47:24.256481 output: Created: Thu Jul 20 13:47:23 2023
216 12:47:24.256563 output: Image 0 (kernel-1)
217 12:47:24.256632 output: Description:
218 12:47:24.256718 output: Created: Thu Jul 20 13:47:23 2023
219 12:47:24.256785 output: Type: Kernel Image
220 12:47:24.256846 output: Compression: lzma compressed
221 12:47:24.256909 output: Data Size: 10808178 Bytes = 10554.86 KiB = 10.31 MiB
222 12:47:24.256973 output: Architecture: AArch64
223 12:47:24.257035 output: OS: Linux
224 12:47:24.257116 output: Load Address: 0x00000000
225 12:47:24.257208 output: Entry Point: 0x00000000
226 12:47:24.257301 output: Hash algo: crc32
227 12:47:24.257389 output: Hash value: 96f4d49d
228 12:47:24.257487 output: Image 1 (fdt-1)
229 12:47:24.257555 output: Description: mt8192-asurada-spherion-r0
230 12:47:24.257612 output: Created: Thu Jul 20 13:47:23 2023
231 12:47:24.257668 output: Type: Flat Device Tree
232 12:47:24.257724 output: Compression: uncompressed
233 12:47:24.257779 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
234 12:47:24.257834 output: Architecture: AArch64
235 12:47:24.257898 output: Hash algo: crc32
236 12:47:24.257955 output: Hash value: 1df858fa
237 12:47:24.258010 output: Image 2 (ramdisk-1)
238 12:47:24.258065 output: Description: unavailable
239 12:47:24.258119 output: Created: Thu Jul 20 13:47:23 2023
240 12:47:24.258173 output: Type: RAMDisk Image
241 12:47:24.258227 output: Compression: Unknown Compression
242 12:47:24.258281 output: Data Size: 98185983 Bytes = 95884.75 KiB = 93.64 MiB
243 12:47:24.258335 output: Architecture: AArch64
244 12:47:24.258389 output: OS: Linux
245 12:47:24.258442 output: Load Address: unavailable
246 12:47:24.258496 output: Entry Point: unavailable
247 12:47:24.258549 output: Hash algo: crc32
248 12:47:24.258603 output: Hash value: 8731975e
249 12:47:24.258656 output: Default Configuration: 'conf-1'
250 12:47:24.258710 output: Configuration 0 (conf-1)
251 12:47:24.258765 output: Description: mt8192-asurada-spherion-r0
252 12:47:24.258818 output: Kernel: kernel-1
253 12:47:24.258872 output: Init Ramdisk: ramdisk-1
254 12:47:24.258925 output: FDT: fdt-1
255 12:47:24.258999 output: Loadables: kernel-1
256 12:47:24.259055 output:
257 12:47:24.259281 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
258 12:47:24.259413 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
259 12:47:24.259568 end: 1.5 prepare-tftp-overlay (duration 00:00:33) [common]
260 12:47:24.259699 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:19) [common]
261 12:47:24.259793 No LXC device requested
262 12:47:24.259879 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 12:47:24.259981 start: 1.7 deploy-device-env (timeout 00:09:19) [common]
264 12:47:24.260092 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 12:47:24.260167 Checking files for TFTP limit of 4294967296 bytes.
266 12:47:24.261053 end: 1 tftp-deploy (duration 00:00:41) [common]
267 12:47:24.261220 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 12:47:24.261356 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 12:47:24.261546 substitutions:
270 12:47:24.261644 - {DTB}: 11118892/tftp-deploy-rgu9yvwm/dtb/mt8192-asurada-spherion-r0.dtb
271 12:47:24.261752 - {INITRD}: 11118892/tftp-deploy-rgu9yvwm/ramdisk/ramdisk.cpio.gz
272 12:47:24.261845 - {KERNEL}: 11118892/tftp-deploy-rgu9yvwm/kernel/Image
273 12:47:24.261944 - {LAVA_MAC}: None
274 12:47:24.262035 - {PRESEED_CONFIG}: None
275 12:47:24.262122 - {PRESEED_LOCAL}: None
276 12:47:24.262221 - {RAMDISK}: 11118892/tftp-deploy-rgu9yvwm/ramdisk/ramdisk.cpio.gz
277 12:47:24.262285 - {ROOT_PART}: None
278 12:47:24.262342 - {ROOT}: None
279 12:47:24.262399 - {SERVER_IP}: 192.168.201.1
280 12:47:24.262465 - {TEE}: None
281 12:47:24.262557 Parsed boot commands:
282 12:47:24.262647 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 12:47:24.262903 Parsed boot commands: tftpboot 192.168.201.1 11118892/tftp-deploy-rgu9yvwm/kernel/image.itb 11118892/tftp-deploy-rgu9yvwm/kernel/cmdline
284 12:47:24.263048 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 12:47:24.263188 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 12:47:24.263359 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 12:47:24.263505 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 12:47:24.263636 Not connected, no need to disconnect.
289 12:47:24.263782 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 12:47:24.263938 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 12:47:24.264077 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
292 12:47:24.268785 Setting prompt string to ['lava-test: # ']
293 12:47:24.269409 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 12:47:24.269609 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 12:47:24.269768 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 12:47:24.269911 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 12:47:24.270256 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
298 12:47:32.649498 >> Command sent successfully.
299 12:47:32.652969 Returned 0 in 8 seconds
300 12:47:32.753470 end: 2.2.2.1 pdu-reboot (duration 00:00:08) [common]
302 12:47:32.753915 end: 2.2.2 reset-device (duration 00:00:08) [common]
303 12:47:32.754047 start: 2.2.3 depthcharge-start (timeout 00:04:52) [common]
304 12:47:32.754175 Setting prompt string to 'Starting depthcharge on Spherion...'
305 12:47:32.754274 Changing prompt to 'Starting depthcharge on Spherion...'
306 12:47:32.754374 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 12:47:32.754796 [Enter `^Ec?' for help]
308 12:47:32.929237
309 12:47:32.929417
310 12:47:32.929491 F0: 102B 0000
311 12:47:32.929555
312 12:47:32.929670 F3: 1001 0000 [0200]
313 12:47:32.929759
314 12:47:32.932878 F3: 1001 0000
315 12:47:32.932997
316 12:47:32.933081 F7: 102D 0000
317 12:47:32.933145
318 12:47:32.933204 F1: 0000 0000
319 12:47:32.933264
320 12:47:32.935764 V0: 0000 0000 [0001]
321 12:47:32.935848
322 12:47:32.935916 00: 0007 8000
323 12:47:32.935984
324 12:47:32.939488 01: 0000 0000
325 12:47:32.939603
326 12:47:32.939701 BP: 0C00 0209 [0000]
327 12:47:32.939793
328 12:47:32.942968 G0: 1182 0000
329 12:47:32.943090
330 12:47:32.943188 EC: 0000 0021 [4000]
331 12:47:32.943282
332 12:47:32.946537 S7: 0000 0000 [0000]
333 12:47:32.946626
334 12:47:32.946695 CC: 0000 0000 [0001]
335 12:47:32.946759
336 12:47:32.949249 T0: 0000 0040 [010F]
337 12:47:32.949337
338 12:47:32.949406 Jump to BL
339 12:47:32.949469
340 12:47:32.976138
341 12:47:32.976320
342 12:47:32.976423
343 12:47:32.983493 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 12:47:32.987251 ARM64: Exception handlers installed.
345 12:47:32.990794 ARM64: Testing exception
346 12:47:32.990924 ARM64: Done test exception
347 12:47:33.000998 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 12:47:33.011559 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 12:47:33.018409 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 12:47:33.028195 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 12:47:33.035015 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 12:47:33.041747 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 12:47:33.052371 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 12:47:33.059266 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 12:47:33.078617 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 12:47:33.082070 WDT: Last reset was cold boot
357 12:47:33.085100 SPI1(PAD0) initialized at 2873684 Hz
358 12:47:33.089017 SPI5(PAD0) initialized at 992727 Hz
359 12:47:33.091965 VBOOT: Loading verstage.
360 12:47:33.098556 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 12:47:33.102218 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 12:47:33.105408 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 12:47:33.108362 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 12:47:33.116198 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 12:47:33.122539 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 12:47:33.133695 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 12:47:33.133846
368 12:47:33.133922
369 12:47:33.143460 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 12:47:33.147235 ARM64: Exception handlers installed.
371 12:47:33.150287 ARM64: Testing exception
372 12:47:33.150461 ARM64: Done test exception
373 12:47:33.156823 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 12:47:33.160108 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 12:47:33.174613 Probing TPM: . done!
376 12:47:33.174805 TPM ready after 0 ms
377 12:47:33.182322 Connected to device vid:did:rid of 1ae0:0028:00
378 12:47:33.189044 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 12:47:33.248396 Initialized TPM device CR50 revision 0
380 12:47:33.258020 tlcl_send_startup: Startup return code is 0
381 12:47:33.258191 TPM: setup succeeded
382 12:47:33.270004 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 12:47:33.278527 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 12:47:33.290767 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 12:47:33.301140 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 12:47:33.304160 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 12:47:33.310259 in-header: 03 07 00 00 08 00 00 00
388 12:47:33.313526 in-data: aa e4 47 04 13 02 00 00
389 12:47:33.317182 Chrome EC: UHEPI supported
390 12:47:33.324799 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 12:47:33.328468 in-header: 03 ad 00 00 08 00 00 00
392 12:47:33.328616 in-data: 00 20 20 08 00 00 00 00
393 12:47:33.332686 Phase 1
394 12:47:33.336409 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 12:47:33.340130 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 12:47:33.347790 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 12:47:33.347927 Recovery requested (1009000e)
398 12:47:33.358781 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 12:47:33.364421 tlcl_extend: response is 0
400 12:47:33.373838 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 12:47:33.379334 tlcl_extend: response is 0
402 12:47:33.386272 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 12:47:33.405874 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
404 12:47:33.413008 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 12:47:33.413172
406 12:47:33.413278
407 12:47:33.423577 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 12:47:33.427376 ARM64: Exception handlers installed.
409 12:47:33.427508 ARM64: Testing exception
410 12:47:33.431015 ARM64: Done test exception
411 12:47:33.451291 pmic_efuse_setting: Set efuses in 11 msecs
412 12:47:33.455222 pmwrap_interface_init: Select PMIF_VLD_RDY
413 12:47:33.462043 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 12:47:33.465468 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 12:47:33.468513 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 12:47:33.475707 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 12:47:33.479463 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 12:47:33.483122 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 12:47:33.490523 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 12:47:33.494227 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 12:47:33.497962 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 12:47:33.505355 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 12:47:33.509131 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 12:47:33.513422 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 12:47:33.517017 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 12:47:33.524405 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 12:47:33.527907 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 12:47:33.534846 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 12:47:33.539052 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 12:47:33.546611 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 12:47:33.554044 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 12:47:33.557792 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 12:47:33.564829 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 12:47:33.568692 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 12:47:33.576176 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 12:47:33.580358 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 12:47:33.583911 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 12:47:33.591881 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 12:47:33.595526 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 12:47:33.599222 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 12:47:33.606913 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 12:47:33.610321 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 12:47:33.614055 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 12:47:33.621234 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 12:47:33.624970 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 12:47:33.629395 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 12:47:33.636177 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 12:47:33.640267 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 12:47:33.647451 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 12:47:33.650798 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 12:47:33.655206 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 12:47:33.658830 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 12:47:33.662431 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 12:47:33.669666 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 12:47:33.673203 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 12:47:33.676674 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 12:47:33.680580 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 12:47:33.684371 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 12:47:33.688215 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 12:47:33.695353 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 12:47:33.699227 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 12:47:33.702900 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 12:47:33.706677 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 12:47:33.713978 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 12:47:33.721347 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 12:47:33.728440 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 12:47:33.735911 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 12:47:33.743289 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 12:47:33.746817 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 12:47:33.754153 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 12:47:33.757759 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 12:47:33.765668 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x9
473 12:47:33.768986 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 12:47:33.777054 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
475 12:47:33.780459 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 12:47:33.788871 [RTC]rtc_get_frequency_meter,154: input=15, output=791
477 12:47:33.798357 [RTC]rtc_get_frequency_meter,154: input=23, output=978
478 12:47:33.808149 [RTC]rtc_get_frequency_meter,154: input=19, output=884
479 12:47:33.817321 [RTC]rtc_get_frequency_meter,154: input=17, output=836
480 12:47:33.827055 [RTC]rtc_get_frequency_meter,154: input=16, output=813
481 12:47:33.836130 [RTC]rtc_get_frequency_meter,154: input=15, output=791
482 12:47:33.846597 [RTC]rtc_get_frequency_meter,154: input=16, output=814
483 12:47:33.850531 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
484 12:47:33.853858 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
485 12:47:33.857469 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 12:47:33.865549 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 12:47:33.868574 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 12:47:33.872590 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 12:47:33.876052 ADC[4]: Raw value=901328 ID=7
490 12:47:33.876142 ADC[3]: Raw value=213336 ID=1
491 12:47:33.880205 RAM Code: 0x71
492 12:47:33.883904 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 12:47:33.887403 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 12:47:33.899014 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 12:47:33.903028 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 12:47:33.906159 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 12:47:33.909839 in-header: 03 07 00 00 08 00 00 00
498 12:47:33.913780 in-data: aa e4 47 04 13 02 00 00
499 12:47:33.917598 Chrome EC: UHEPI supported
500 12:47:33.924360 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 12:47:33.928124 in-header: 03 ed 00 00 08 00 00 00
502 12:47:33.928259 in-data: 80 20 60 08 00 00 00 00
503 12:47:33.932254 MRC: failed to locate region type 0.
504 12:47:33.939537 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 12:47:33.943272 DRAM-K: Running full calibration
506 12:47:33.950191 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 12:47:33.950350 header.status = 0x0
508 12:47:33.953793 header.version = 0x6 (expected: 0x6)
509 12:47:33.957889 header.size = 0xd00 (expected: 0xd00)
510 12:47:33.958011 header.flags = 0x0
511 12:47:33.964517 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 12:47:33.983586 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
513 12:47:33.990985 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 12:47:33.991126 dram_init: ddr_geometry: 2
515 12:47:33.994749 [EMI] MDL number = 2
516 12:47:33.994860 [EMI] Get MDL freq = 0
517 12:47:33.998468 dram_init: ddr_type: 0
518 12:47:34.002208 is_discrete_lpddr4: 1
519 12:47:34.002332 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 12:47:34.002434
521 12:47:34.005906
522 12:47:34.006013 [Bian_co] ETT version 0.0.0.1
523 12:47:34.010129 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 12:47:34.010251
525 12:47:34.013766 dramc_set_vcore_voltage set vcore to 650000
526 12:47:34.017546 Read voltage for 800, 4
527 12:47:34.017666 Vio18 = 0
528 12:47:34.021244 Vcore = 650000
529 12:47:34.021362 Vdram = 0
530 12:47:34.021459 Vddq = 0
531 12:47:34.021560 Vmddr = 0
532 12:47:34.024443 dram_init: config_dvfs: 1
533 12:47:34.031468 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 12:47:34.034440 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 12:47:34.038082 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
536 12:47:34.041716 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
537 12:47:34.048431 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
538 12:47:34.051415 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
539 12:47:34.051537 MEM_TYPE=3, freq_sel=18
540 12:47:34.055093 sv_algorithm_assistance_LP4_1600
541 12:47:34.061284 ============ PULL DRAM RESETB DOWN ============
542 12:47:34.064879 ========== PULL DRAM RESETB DOWN end =========
543 12:47:34.068338 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 12:47:34.071377 ===================================
545 12:47:34.074906 LPDDR4 DRAM CONFIGURATION
546 12:47:34.078011 ===================================
547 12:47:34.078122 EX_ROW_EN[0] = 0x0
548 12:47:34.081540 EX_ROW_EN[1] = 0x0
549 12:47:34.085147 LP4Y_EN = 0x0
550 12:47:34.085255 WORK_FSP = 0x0
551 12:47:34.088327 WL = 0x2
552 12:47:34.088441 RL = 0x2
553 12:47:34.091909 BL = 0x2
554 12:47:34.092026 RPST = 0x0
555 12:47:34.095000 RD_PRE = 0x0
556 12:47:34.095105 WR_PRE = 0x1
557 12:47:34.098506 WR_PST = 0x0
558 12:47:34.098624 DBI_WR = 0x0
559 12:47:34.101884 DBI_RD = 0x0
560 12:47:34.102007 OTF = 0x1
561 12:47:34.105132 ===================================
562 12:47:34.108438 ===================================
563 12:47:34.111756 ANA top config
564 12:47:34.115344 ===================================
565 12:47:34.115458 DLL_ASYNC_EN = 0
566 12:47:34.118741 ALL_SLAVE_EN = 1
567 12:47:34.122226 NEW_RANK_MODE = 1
568 12:47:34.125147 DLL_IDLE_MODE = 1
569 12:47:34.125239 LP45_APHY_COMB_EN = 1
570 12:47:34.128608 TX_ODT_DIS = 1
571 12:47:34.132215 NEW_8X_MODE = 1
572 12:47:34.135262 ===================================
573 12:47:34.138474 ===================================
574 12:47:34.141786 data_rate = 1600
575 12:47:34.145392 CKR = 1
576 12:47:34.145529 DQ_P2S_RATIO = 8
577 12:47:34.148523 ===================================
578 12:47:34.152142 CA_P2S_RATIO = 8
579 12:47:34.155263 DQ_CA_OPEN = 0
580 12:47:34.158885 DQ_SEMI_OPEN = 0
581 12:47:34.161895 CA_SEMI_OPEN = 0
582 12:47:34.165721 CA_FULL_RATE = 0
583 12:47:34.165838 DQ_CKDIV4_EN = 1
584 12:47:34.168706 CA_CKDIV4_EN = 1
585 12:47:34.172370 CA_PREDIV_EN = 0
586 12:47:34.175848 PH8_DLY = 0
587 12:47:34.179307 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 12:47:34.179428 DQ_AAMCK_DIV = 4
589 12:47:34.182599 CA_AAMCK_DIV = 4
590 12:47:34.185767 CA_ADMCK_DIV = 4
591 12:47:34.189292 DQ_TRACK_CA_EN = 0
592 12:47:34.192334 CA_PICK = 800
593 12:47:34.195927 CA_MCKIO = 800
594 12:47:34.196044 MCKIO_SEMI = 0
595 12:47:34.199059 PLL_FREQ = 3068
596 12:47:34.202692 DQ_UI_PI_RATIO = 32
597 12:47:34.206437 CA_UI_PI_RATIO = 0
598 12:47:34.210002 ===================================
599 12:47:34.213985 ===================================
600 12:47:34.214079 memory_type:LPDDR4
601 12:47:34.217720 GP_NUM : 10
602 12:47:34.217818 SRAM_EN : 1
603 12:47:34.221488 MD32_EN : 0
604 12:47:34.225006 ===================================
605 12:47:34.225098 [ANA_INIT] >>>>>>>>>>>>>>
606 12:47:34.228525 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 12:47:34.232229 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 12:47:34.236536 ===================================
609 12:47:34.239916 data_rate = 1600,PCW = 0X7600
610 12:47:34.242789 ===================================
611 12:47:34.246634 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 12:47:34.249926 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 12:47:34.256577 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 12:47:34.259698 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 12:47:34.263367 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 12:47:34.266449 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 12:47:34.270099 [ANA_INIT] flow start
618 12:47:34.273213 [ANA_INIT] PLL >>>>>>>>
619 12:47:34.273328 [ANA_INIT] PLL <<<<<<<<
620 12:47:34.276812 [ANA_INIT] MIDPI >>>>>>>>
621 12:47:34.279854 [ANA_INIT] MIDPI <<<<<<<<
622 12:47:34.283500 [ANA_INIT] DLL >>>>>>>>
623 12:47:34.283612 [ANA_INIT] flow end
624 12:47:34.286891 ============ LP4 DIFF to SE enter ============
625 12:47:34.293283 ============ LP4 DIFF to SE exit ============
626 12:47:34.293412 [ANA_INIT] <<<<<<<<<<<<<
627 12:47:34.297002 [Flow] Enable top DCM control >>>>>
628 12:47:34.299983 [Flow] Enable top DCM control <<<<<
629 12:47:34.303658 Enable DLL master slave shuffle
630 12:47:34.310412 ==============================================================
631 12:47:34.310526 Gating Mode config
632 12:47:34.317286 ==============================================================
633 12:47:34.317372 Config description:
634 12:47:34.327208 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 12:47:34.333748 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 12:47:34.340404 SELPH_MODE 0: By rank 1: By Phase
637 12:47:34.343745 ==============================================================
638 12:47:34.347177 GAT_TRACK_EN = 1
639 12:47:34.350705 RX_GATING_MODE = 2
640 12:47:34.353973 RX_GATING_TRACK_MODE = 2
641 12:47:34.357279 SELPH_MODE = 1
642 12:47:34.360454 PICG_EARLY_EN = 1
643 12:47:34.364159 VALID_LAT_VALUE = 1
644 12:47:34.367104 ==============================================================
645 12:47:34.370859 Enter into Gating configuration >>>>
646 12:47:34.373821 Exit from Gating configuration <<<<
647 12:47:34.377684 Enter into DVFS_PRE_config >>>>>
648 12:47:34.390723 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 12:47:34.394317 Exit from DVFS_PRE_config <<<<<
650 12:47:34.397821 Enter into PICG configuration >>>>
651 12:47:34.397943 Exit from PICG configuration <<<<
652 12:47:34.400865 [RX_INPUT] configuration >>>>>
653 12:47:34.404512 [RX_INPUT] configuration <<<<<
654 12:47:34.410641 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 12:47:34.414279 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 12:47:34.421001 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 12:47:34.428406 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 12:47:34.435102 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 12:47:34.438535 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 12:47:34.445264 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 12:47:34.448398 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 12:47:34.451504 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 12:47:34.455406 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 12:47:34.458716 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 12:47:34.465412 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 12:47:34.468615 ===================================
667 12:47:34.468918 LPDDR4 DRAM CONFIGURATION
668 12:47:34.471860 ===================================
669 12:47:34.475298 EX_ROW_EN[0] = 0x0
670 12:47:34.478988 EX_ROW_EN[1] = 0x0
671 12:47:34.479239 LP4Y_EN = 0x0
672 12:47:34.482194 WORK_FSP = 0x0
673 12:47:34.482450 WL = 0x2
674 12:47:34.485800 RL = 0x2
675 12:47:34.486015 BL = 0x2
676 12:47:34.488970 RPST = 0x0
677 12:47:34.489165 RD_PRE = 0x0
678 12:47:34.492506 WR_PRE = 0x1
679 12:47:34.492719 WR_PST = 0x0
680 12:47:34.496011 DBI_WR = 0x0
681 12:47:34.496214 DBI_RD = 0x0
682 12:47:34.499470 OTF = 0x1
683 12:47:34.502301 ===================================
684 12:47:34.506022 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 12:47:34.509131 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 12:47:34.515959 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 12:47:34.518873 ===================================
688 12:47:34.519087 LPDDR4 DRAM CONFIGURATION
689 12:47:34.522602 ===================================
690 12:47:34.525713 EX_ROW_EN[0] = 0x10
691 12:47:34.525906 EX_ROW_EN[1] = 0x0
692 12:47:34.529435 LP4Y_EN = 0x0
693 12:47:34.529651 WORK_FSP = 0x0
694 12:47:34.532522 WL = 0x2
695 12:47:34.532752 RL = 0x2
696 12:47:34.536060 BL = 0x2
697 12:47:34.536254 RPST = 0x0
698 12:47:34.539153 RD_PRE = 0x0
699 12:47:34.539382 WR_PRE = 0x1
700 12:47:34.542716 WR_PST = 0x0
701 12:47:34.546353 DBI_WR = 0x0
702 12:47:34.546576 DBI_RD = 0x0
703 12:47:34.549878 OTF = 0x1
704 12:47:34.550106 ===================================
705 12:47:34.556277 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 12:47:34.561265 nWR fixed to 40
707 12:47:34.564742 [ModeRegInit_LP4] CH0 RK0
708 12:47:34.564964 [ModeRegInit_LP4] CH0 RK1
709 12:47:34.568116 [ModeRegInit_LP4] CH1 RK0
710 12:47:34.571537 [ModeRegInit_LP4] CH1 RK1
711 12:47:34.571752 match AC timing 13
712 12:47:34.577987 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 12:47:34.581202 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 12:47:34.584871 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 12:47:34.591358 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 12:47:34.595146 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 12:47:34.595378 [EMI DOE] emi_dcm 0
718 12:47:34.601849 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 12:47:34.602147 ==
720 12:47:34.605200 Dram Type= 6, Freq= 0, CH_0, rank 0
721 12:47:34.608546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 12:47:34.608822 ==
723 12:47:34.615368 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 12:47:34.618539 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 12:47:34.628734 [CA 0] Center 37 (7~68) winsize 62
726 12:47:34.632176 [CA 1] Center 37 (6~68) winsize 63
727 12:47:34.635947 [CA 2] Center 35 (4~66) winsize 63
728 12:47:34.638755 [CA 3] Center 34 (4~65) winsize 62
729 12:47:34.641966 [CA 4] Center 34 (4~65) winsize 62
730 12:47:34.645552 [CA 5] Center 34 (4~64) winsize 61
731 12:47:34.645753
732 12:47:34.649073 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 12:47:34.649353
734 12:47:34.652161 [CATrainingPosCal] consider 1 rank data
735 12:47:34.655485 u2DelayCellTimex100 = 270/100 ps
736 12:47:34.658967 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
737 12:47:34.662493 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
738 12:47:34.665672 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
739 12:47:34.672246 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
740 12:47:34.675590 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
741 12:47:34.679295 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
742 12:47:34.679589
743 12:47:34.682527 CA PerBit enable=1, Macro0, CA PI delay=34
744 12:47:34.682821
745 12:47:34.685752 [CBTSetCACLKResult] CA Dly = 34
746 12:47:34.686057 CS Dly: 5 (0~36)
747 12:47:34.686330 ==
748 12:47:34.689134 Dram Type= 6, Freq= 0, CH_0, rank 1
749 12:47:34.692896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 12:47:34.696085 ==
751 12:47:34.699433 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 12:47:34.706298 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 12:47:34.714556 [CA 0] Center 37 (7~68) winsize 62
754 12:47:34.718274 [CA 1] Center 37 (7~68) winsize 62
755 12:47:34.721380 [CA 2] Center 35 (5~66) winsize 62
756 12:47:34.725087 [CA 3] Center 35 (4~66) winsize 63
757 12:47:34.728082 [CA 4] Center 34 (4~65) winsize 62
758 12:47:34.731880 [CA 5] Center 33 (3~64) winsize 62
759 12:47:34.731965
760 12:47:34.734799 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 12:47:34.734886
762 12:47:34.738452 [CATrainingPosCal] consider 2 rank data
763 12:47:34.741522 u2DelayCellTimex100 = 270/100 ps
764 12:47:34.745002 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
765 12:47:34.748647 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
766 12:47:34.751732 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
767 12:47:34.758684 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
768 12:47:34.761966 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
769 12:47:34.764848 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
770 12:47:34.764935
771 12:47:34.768488 CA PerBit enable=1, Macro0, CA PI delay=34
772 12:47:34.768573
773 12:47:34.771738 [CBTSetCACLKResult] CA Dly = 34
774 12:47:34.771823 CS Dly: 6 (0~38)
775 12:47:34.771891
776 12:47:34.775166 ----->DramcWriteLeveling(PI) begin...
777 12:47:34.775290 ==
778 12:47:34.778092 Dram Type= 6, Freq= 0, CH_0, rank 0
779 12:47:34.785259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 12:47:34.785351 ==
781 12:47:34.788953 Write leveling (Byte 0): 31 => 31
782 12:47:34.789038 Write leveling (Byte 1): 30 => 30
783 12:47:34.792745 DramcWriteLeveling(PI) end<-----
784 12:47:34.792823
785 12:47:34.792888 ==
786 12:47:34.796345 Dram Type= 6, Freq= 0, CH_0, rank 0
787 12:47:34.800613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 12:47:34.800728 ==
789 12:47:34.803667 [Gating] SW mode calibration
790 12:47:34.810942 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 12:47:34.815181 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 12:47:34.821539 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 12:47:34.824892 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
794 12:47:34.828066 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
795 12:47:34.834818 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:47:34.837974 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:47:34.841906 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:47:34.848029 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:47:34.851792 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:47:34.854962 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:47:34.861796 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:47:34.864744 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:47:34.868661 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:47:34.871689 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:47:34.878530 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:47:34.882063 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:47:34.885058 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:47:34.892291 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:47:34.895394 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
810 12:47:34.898555 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
811 12:47:34.905715 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:47:34.908718 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 12:47:34.912399 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 12:47:34.915513 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 12:47:34.922202 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 12:47:34.925560 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 12:47:34.928841 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 12:47:34.935997 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
819 12:47:34.939056 0 9 12 | B1->B0 | 2828 3232 | 0 0 | (0 0) (0 0)
820 12:47:34.942328 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 12:47:34.949272 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 12:47:34.952603 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 12:47:34.955690 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 12:47:34.962358 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 12:47:34.966031 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
826 12:47:34.969056 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 1)
827 12:47:34.972395 0 10 12 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
828 12:47:34.979522 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 12:47:34.982651 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 12:47:34.986376 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 12:47:34.993070 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 12:47:34.996148 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 12:47:34.999194 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 12:47:35.006280 0 11 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
835 12:47:35.009359 0 11 12 | B1->B0 | 3737 4343 | 1 0 | (0 0) (0 0)
836 12:47:35.013043 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 12:47:35.019775 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 12:47:35.022808 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 12:47:35.026367 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 12:47:35.033141 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 12:47:35.036555 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 12:47:35.039667 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
843 12:47:35.043210 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
844 12:47:35.049499 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:47:35.053080 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:47:35.056195 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:47:35.063197 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:47:35.066775 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:47:35.069948 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:47:35.076438 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:47:35.079881 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 12:47:35.083255 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 12:47:35.090112 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 12:47:35.093088 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 12:47:35.096774 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 12:47:35.099813 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 12:47:35.106560 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 12:47:35.110018 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
859 12:47:35.113625 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
860 12:47:35.116780 Total UI for P1: 0, mck2ui 16
861 12:47:35.120643 best dqsien dly found for B0: ( 0, 14, 8)
862 12:47:35.123679 Total UI for P1: 0, mck2ui 16
863 12:47:35.126721 best dqsien dly found for B1: ( 0, 14, 8)
864 12:47:35.130488 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
865 12:47:35.133410 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
866 12:47:35.133495
867 12:47:35.140536 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
868 12:47:35.143655 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 12:47:35.143740 [Gating] SW calibration Done
870 12:47:35.147121 ==
871 12:47:35.147206 Dram Type= 6, Freq= 0, CH_0, rank 0
872 12:47:35.153714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
873 12:47:35.153817 ==
874 12:47:35.153909 RX Vref Scan: 0
875 12:47:35.153999
876 12:47:35.157295 RX Vref 0 -> 0, step: 1
877 12:47:35.157380
878 12:47:35.160287 RX Delay -130 -> 252, step: 16
879 12:47:35.163826 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
880 12:47:35.167433 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
881 12:47:35.170669 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
882 12:47:35.177193 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
883 12:47:35.180768 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
884 12:47:35.183989 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
885 12:47:35.187491 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
886 12:47:35.191048 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
887 12:47:35.194222 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
888 12:47:35.200947 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
889 12:47:35.204042 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
890 12:47:35.207861 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
891 12:47:35.210924 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
892 12:47:35.214467 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
893 12:47:35.221276 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
894 12:47:35.224369 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
895 12:47:35.224444 ==
896 12:47:35.227535 Dram Type= 6, Freq= 0, CH_0, rank 0
897 12:47:35.231207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 12:47:35.231282 ==
899 12:47:35.234325 DQS Delay:
900 12:47:35.234399 DQS0 = 0, DQS1 = 0
901 12:47:35.234463 DQM Delay:
902 12:47:35.238058 DQM0 = 84, DQM1 = 78
903 12:47:35.238151 DQ Delay:
904 12:47:35.241033 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
905 12:47:35.244887 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
906 12:47:35.247733 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =77
907 12:47:35.251310 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
908 12:47:35.251394
909 12:47:35.251462
910 12:47:35.251533 ==
911 12:47:35.254974 Dram Type= 6, Freq= 0, CH_0, rank 0
912 12:47:35.258182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 12:47:35.261797 ==
914 12:47:35.261869
915 12:47:35.261940
916 12:47:35.262001 TX Vref Scan disable
917 12:47:35.264931 == TX Byte 0 ==
918 12:47:35.268382 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
919 12:47:35.271463 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
920 12:47:35.275155 == TX Byte 1 ==
921 12:47:35.278149 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
922 12:47:35.281455 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
923 12:47:35.281529 ==
924 12:47:35.284929 Dram Type= 6, Freq= 0, CH_0, rank 0
925 12:47:35.291482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 12:47:35.291572 ==
927 12:47:35.303549 TX Vref=22, minBit 5, minWin=27, winSum=440
928 12:47:35.307140 TX Vref=24, minBit 7, minWin=27, winSum=445
929 12:47:35.310233 TX Vref=26, minBit 5, minWin=27, winSum=448
930 12:47:35.313602 TX Vref=28, minBit 9, minWin=27, winSum=451
931 12:47:35.316955 TX Vref=30, minBit 2, minWin=28, winSum=457
932 12:47:35.320531 TX Vref=32, minBit 5, minWin=27, winSum=455
933 12:47:35.327232 [TxChooseVref] Worse bit 2, Min win 28, Win sum 457, Final Vref 30
934 12:47:35.327345
935 12:47:35.330823 Final TX Range 1 Vref 30
936 12:47:35.330934
937 12:47:35.331038 ==
938 12:47:35.333936 Dram Type= 6, Freq= 0, CH_0, rank 0
939 12:47:35.337702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 12:47:35.337789 ==
941 12:47:35.337859
942 12:47:35.337922
943 12:47:35.340786 TX Vref Scan disable
944 12:47:35.343810 == TX Byte 0 ==
945 12:47:35.347343 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
946 12:47:35.351003 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
947 12:47:35.353977 == TX Byte 1 ==
948 12:47:35.357474 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
949 12:47:35.361162 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
950 12:47:35.361275
951 12:47:35.364539 [DATLAT]
952 12:47:35.364662 Freq=800, CH0 RK0
953 12:47:35.364778
954 12:47:35.367657 DATLAT Default: 0xa
955 12:47:35.367784 0, 0xFFFF, sum = 0
956 12:47:35.371195 1, 0xFFFF, sum = 0
957 12:47:35.371315 2, 0xFFFF, sum = 0
958 12:47:35.374148 3, 0xFFFF, sum = 0
959 12:47:35.374271 4, 0xFFFF, sum = 0
960 12:47:35.377856 5, 0xFFFF, sum = 0
961 12:47:35.377970 6, 0xFFFF, sum = 0
962 12:47:35.380990 7, 0xFFFF, sum = 0
963 12:47:35.381102 8, 0xFFFF, sum = 0
964 12:47:35.384396 9, 0x0, sum = 1
965 12:47:35.384526 10, 0x0, sum = 2
966 12:47:35.387995 11, 0x0, sum = 3
967 12:47:35.388119 12, 0x0, sum = 4
968 12:47:35.388215 best_step = 10
969 12:47:35.391343
970 12:47:35.391444 ==
971 12:47:35.394233 Dram Type= 6, Freq= 0, CH_0, rank 0
972 12:47:35.397862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 12:47:35.397964 ==
974 12:47:35.398075 RX Vref Scan: 1
975 12:47:35.398168
976 12:47:35.400997 Set Vref Range= 32 -> 127
977 12:47:35.401096
978 12:47:35.404634 RX Vref 32 -> 127, step: 1
979 12:47:35.404754
980 12:47:35.407716 RX Delay -111 -> 252, step: 8
981 12:47:35.407818
982 12:47:35.411266 Set Vref, RX VrefLevel [Byte0]: 32
983 12:47:35.414677 [Byte1]: 32
984 12:47:35.414788
985 12:47:35.418193 Set Vref, RX VrefLevel [Byte0]: 33
986 12:47:35.421609 [Byte1]: 33
987 12:47:35.421693
988 12:47:35.424778 Set Vref, RX VrefLevel [Byte0]: 34
989 12:47:35.428312 [Byte1]: 34
990 12:47:35.431399
991 12:47:35.431482 Set Vref, RX VrefLevel [Byte0]: 35
992 12:47:35.434880 [Byte1]: 35
993 12:47:35.439229
994 12:47:35.439313 Set Vref, RX VrefLevel [Byte0]: 36
995 12:47:35.442182 [Byte1]: 36
996 12:47:35.447092
997 12:47:35.447179 Set Vref, RX VrefLevel [Byte0]: 37
998 12:47:35.450165 [Byte1]: 37
999 12:47:35.455070
1000 12:47:35.455153 Set Vref, RX VrefLevel [Byte0]: 38
1001 12:47:35.458141 [Byte1]: 38
1002 12:47:35.462873
1003 12:47:35.462955 Set Vref, RX VrefLevel [Byte0]: 39
1004 12:47:35.465919 [Byte1]: 39
1005 12:47:35.470668
1006 12:47:35.470779 Set Vref, RX VrefLevel [Byte0]: 40
1007 12:47:35.473677 [Byte1]: 40
1008 12:47:35.477958
1009 12:47:35.478064 Set Vref, RX VrefLevel [Byte0]: 41
1010 12:47:35.480964 [Byte1]: 41
1011 12:47:35.485351
1012 12:47:35.485465 Set Vref, RX VrefLevel [Byte0]: 42
1013 12:47:35.488367 [Byte1]: 42
1014 12:47:35.492800
1015 12:47:35.492884 Set Vref, RX VrefLevel [Byte0]: 43
1016 12:47:35.496018 [Byte1]: 43
1017 12:47:35.500603
1018 12:47:35.500713 Set Vref, RX VrefLevel [Byte0]: 44
1019 12:47:35.503734 [Byte1]: 44
1020 12:47:35.507906
1021 12:47:35.507988 Set Vref, RX VrefLevel [Byte0]: 45
1022 12:47:35.511139 [Byte1]: 45
1023 12:47:35.516079
1024 12:47:35.516163 Set Vref, RX VrefLevel [Byte0]: 46
1025 12:47:35.519087 [Byte1]: 46
1026 12:47:35.523203
1027 12:47:35.523283 Set Vref, RX VrefLevel [Byte0]: 47
1028 12:47:35.526807 [Byte1]: 47
1029 12:47:35.530969
1030 12:47:35.531052 Set Vref, RX VrefLevel [Byte0]: 48
1031 12:47:35.534426 [Byte1]: 48
1032 12:47:35.538640
1033 12:47:35.538721 Set Vref, RX VrefLevel [Byte0]: 49
1034 12:47:35.541905 [Byte1]: 49
1035 12:47:35.546353
1036 12:47:35.546450 Set Vref, RX VrefLevel [Byte0]: 50
1037 12:47:35.549551 [Byte1]: 50
1038 12:47:35.553924
1039 12:47:35.554005 Set Vref, RX VrefLevel [Byte0]: 51
1040 12:47:35.557363 [Byte1]: 51
1041 12:47:35.561792
1042 12:47:35.561875 Set Vref, RX VrefLevel [Byte0]: 52
1043 12:47:35.565214 [Byte1]: 52
1044 12:47:35.569409
1045 12:47:35.569492 Set Vref, RX VrefLevel [Byte0]: 53
1046 12:47:35.572489 [Byte1]: 53
1047 12:47:35.576930
1048 12:47:35.577042 Set Vref, RX VrefLevel [Byte0]: 54
1049 12:47:35.580372 [Byte1]: 54
1050 12:47:35.584720
1051 12:47:35.584835 Set Vref, RX VrefLevel [Byte0]: 55
1052 12:47:35.587741 [Byte1]: 55
1053 12:47:35.592110
1054 12:47:35.592221 Set Vref, RX VrefLevel [Byte0]: 56
1055 12:47:35.595736 [Byte1]: 56
1056 12:47:35.599750
1057 12:47:35.599854 Set Vref, RX VrefLevel [Byte0]: 57
1058 12:47:35.602801 [Byte1]: 57
1059 12:47:35.607404
1060 12:47:35.607493 Set Vref, RX VrefLevel [Byte0]: 58
1061 12:47:35.610730 [Byte1]: 58
1062 12:47:35.615090
1063 12:47:35.615166 Set Vref, RX VrefLevel [Byte0]: 59
1064 12:47:35.618280 [Byte1]: 59
1065 12:47:35.622477
1066 12:47:35.622545 Set Vref, RX VrefLevel [Byte0]: 60
1067 12:47:35.626059 [Byte1]: 60
1068 12:47:35.630348
1069 12:47:35.630422 Set Vref, RX VrefLevel [Byte0]: 61
1070 12:47:35.633340 [Byte1]: 61
1071 12:47:35.638213
1072 12:47:35.638288 Set Vref, RX VrefLevel [Byte0]: 62
1073 12:47:35.641072 [Byte1]: 62
1074 12:47:35.645750
1075 12:47:35.645828 Set Vref, RX VrefLevel [Byte0]: 63
1076 12:47:35.649119 [Byte1]: 63
1077 12:47:35.653340
1078 12:47:35.653415 Set Vref, RX VrefLevel [Byte0]: 64
1079 12:47:35.656651 [Byte1]: 64
1080 12:47:35.660736
1081 12:47:35.660815 Set Vref, RX VrefLevel [Byte0]: 65
1082 12:47:35.664377 [Byte1]: 65
1083 12:47:35.668457
1084 12:47:35.668563 Set Vref, RX VrefLevel [Byte0]: 66
1085 12:47:35.672034 [Byte1]: 66
1086 12:47:35.676387
1087 12:47:35.676490 Set Vref, RX VrefLevel [Byte0]: 67
1088 12:47:35.679838 [Byte1]: 67
1089 12:47:35.683784
1090 12:47:35.683866 Set Vref, RX VrefLevel [Byte0]: 68
1091 12:47:35.686865 [Byte1]: 68
1092 12:47:35.691202
1093 12:47:35.691278 Set Vref, RX VrefLevel [Byte0]: 69
1094 12:47:35.694796 [Byte1]: 69
1095 12:47:35.699108
1096 12:47:35.699209 Set Vref, RX VrefLevel [Byte0]: 70
1097 12:47:35.702127 [Byte1]: 70
1098 12:47:35.706843
1099 12:47:35.706919 Set Vref, RX VrefLevel [Byte0]: 71
1100 12:47:35.709896 [Byte1]: 71
1101 12:47:35.714361
1102 12:47:35.714434 Set Vref, RX VrefLevel [Byte0]: 72
1103 12:47:35.717552 [Byte1]: 72
1104 12:47:35.722199
1105 12:47:35.722272 Set Vref, RX VrefLevel [Byte0]: 73
1106 12:47:35.725368 [Byte1]: 73
1107 12:47:35.729946
1108 12:47:35.730030 Set Vref, RX VrefLevel [Byte0]: 74
1109 12:47:35.733059 [Byte1]: 74
1110 12:47:35.737377
1111 12:47:35.737482 Set Vref, RX VrefLevel [Byte0]: 75
1112 12:47:35.740989 [Byte1]: 75
1113 12:47:35.745178
1114 12:47:35.745270 Set Vref, RX VrefLevel [Byte0]: 76
1115 12:47:35.748377 [Byte1]: 76
1116 12:47:35.752597
1117 12:47:35.752689 Final RX Vref Byte 0 = 59 to rank0
1118 12:47:35.756320 Final RX Vref Byte 1 = 62 to rank0
1119 12:47:35.759323 Final RX Vref Byte 0 = 59 to rank1
1120 12:47:35.762561 Final RX Vref Byte 1 = 62 to rank1==
1121 12:47:35.766119 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 12:47:35.769623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 12:47:35.772943 ==
1124 12:47:35.773047 DQS Delay:
1125 12:47:35.773157 DQS0 = 0, DQS1 = 0
1126 12:47:35.776497 DQM Delay:
1127 12:47:35.776599 DQM0 = 86, DQM1 = 78
1128 12:47:35.779495 DQ Delay:
1129 12:47:35.779594 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1130 12:47:35.783156 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1131 12:47:35.786291 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1132 12:47:35.789673 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1133 12:47:35.789781
1134 12:47:35.789874
1135 12:47:35.799852 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
1136 12:47:35.803469 CH0 RK0: MR19=606, MR18=2C13
1137 12:47:35.806430 CH0_RK0: MR19=0x606, MR18=0x2C13, DQSOSC=398, MR23=63, INC=93, DEC=62
1138 12:47:35.806536
1139 12:47:35.810030 ----->DramcWriteLeveling(PI) begin...
1140 12:47:35.813673 ==
1141 12:47:35.816580 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 12:47:35.820133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 12:47:35.820205 ==
1144 12:47:35.823743 Write leveling (Byte 0): 29 => 29
1145 12:47:35.826665 Write leveling (Byte 1): 29 => 29
1146 12:47:35.830122 DramcWriteLeveling(PI) end<-----
1147 12:47:35.830194
1148 12:47:35.830256 ==
1149 12:47:35.833572 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 12:47:35.836606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 12:47:35.836700 ==
1152 12:47:35.840217 [Gating] SW mode calibration
1153 12:47:35.846973 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 12:47:35.850573 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 12:47:35.857266 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1156 12:47:35.860357 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1157 12:47:35.863958 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1158 12:47:35.907909 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:47:35.908211 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:47:35.908285 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:47:35.908360 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:47:35.908422 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:47:35.908493 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:47:35.908572 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:47:35.908834 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:47:35.909078 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:47:35.909142 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:47:35.941502 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:47:35.942168 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:47:35.942758 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:47:35.943024 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:47:35.943096 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1173 12:47:35.943349 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1174 12:47:35.943443 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:47:35.946467 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:47:35.949670 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:47:35.953402 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:47:35.956950 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:47:35.959974 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:47:35.966682 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:47:35.970368 0 9 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
1182 12:47:35.973465 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1183 12:47:35.980358 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 12:47:35.983401 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 12:47:35.987045 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 12:47:35.993410 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 12:47:35.996764 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1188 12:47:36.000511 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1189 12:47:36.003441 0 10 8 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 1)
1190 12:47:36.010195 0 10 12 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
1191 12:47:36.013875 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:47:36.017020 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:47:36.023763 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:47:36.027181 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 12:47:36.030293 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 12:47:36.037768 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
1197 12:47:36.041632 0 11 8 | B1->B0 | 2525 3f3f | 0 0 | (0 0) (0 0)
1198 12:47:36.045640 0 11 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1199 12:47:36.049334 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 12:47:36.052461 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 12:47:36.059217 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 12:47:36.062780 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 12:47:36.066356 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 12:47:36.070109 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1205 12:47:36.076856 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1206 12:47:36.079911 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:47:36.082955 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:47:36.089648 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:47:36.093302 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:47:36.096841 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:47:36.103354 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:47:36.106769 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:47:36.109861 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:47:36.117109 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:47:36.120009 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:47:36.123520 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:47:36.126843 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:47:36.133504 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 12:47:36.136928 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 12:47:36.140366 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1221 12:47:36.146976 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1222 12:47:36.147073 Total UI for P1: 0, mck2ui 16
1223 12:47:36.154107 best dqsien dly found for B0: ( 0, 14, 4)
1224 12:47:36.157585 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 12:47:36.160656 Total UI for P1: 0, mck2ui 16
1226 12:47:36.164245 best dqsien dly found for B1: ( 0, 14, 8)
1227 12:47:36.167803 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1228 12:47:36.170742 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1229 12:47:36.170825
1230 12:47:36.174416 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1231 12:47:36.177387 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 12:47:36.180534 [Gating] SW calibration Done
1233 12:47:36.180676 ==
1234 12:47:36.184049 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 12:47:36.187769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 12:47:36.187853 ==
1237 12:47:36.190822 RX Vref Scan: 0
1238 12:47:36.190905
1239 12:47:36.190971 RX Vref 0 -> 0, step: 1
1240 12:47:36.194538
1241 12:47:36.194647 RX Delay -130 -> 252, step: 16
1242 12:47:36.200704 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1243 12:47:36.204185 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1244 12:47:36.207750 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1245 12:47:36.211132 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1246 12:47:36.214766 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1247 12:47:36.217590 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1248 12:47:36.224340 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1249 12:47:36.227974 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1250 12:47:36.231021 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1251 12:47:36.234510 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1252 12:47:36.237922 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1253 12:47:36.244717 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1254 12:47:36.248356 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1255 12:47:36.251219 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1256 12:47:36.255023 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1257 12:47:36.257831 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1258 12:47:36.257929 ==
1259 12:47:36.261392 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 12:47:36.268428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 12:47:36.268540 ==
1262 12:47:36.268635 DQS Delay:
1263 12:47:36.271918 DQS0 = 0, DQS1 = 0
1264 12:47:36.271994 DQM Delay:
1265 12:47:36.272057 DQM0 = 86, DQM1 = 73
1266 12:47:36.274897 DQ Delay:
1267 12:47:36.278561 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1268 12:47:36.281653 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1269 12:47:36.285147 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1270 12:47:36.288240 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =85
1271 12:47:36.288328
1272 12:47:36.288398
1273 12:47:36.288460 ==
1274 12:47:36.291838 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 12:47:36.295147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 12:47:36.295225 ==
1277 12:47:36.295288
1278 12:47:36.295350
1279 12:47:36.298253 TX Vref Scan disable
1280 12:47:36.301882 == TX Byte 0 ==
1281 12:47:36.304837 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1282 12:47:36.308537 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1283 12:47:36.308607 == TX Byte 1 ==
1284 12:47:36.315289 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1285 12:47:36.318573 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1286 12:47:36.318646 ==
1287 12:47:36.321813 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 12:47:36.324744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 12:47:36.324822 ==
1290 12:47:36.339154 TX Vref=22, minBit 1, minWin=27, winSum=441
1291 12:47:36.342883 TX Vref=24, minBit 3, minWin=27, winSum=442
1292 12:47:36.345716 TX Vref=26, minBit 3, minWin=27, winSum=451
1293 12:47:36.349108 TX Vref=28, minBit 0, minWin=28, winSum=452
1294 12:47:36.352737 TX Vref=30, minBit 0, minWin=28, winSum=454
1295 12:47:36.356167 TX Vref=32, minBit 12, minWin=27, winSum=451
1296 12:47:36.362798 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
1297 12:47:36.362880
1298 12:47:36.365953 Final TX Range 1 Vref 30
1299 12:47:36.366035
1300 12:47:36.366100 ==
1301 12:47:36.369674 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 12:47:36.372540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 12:47:36.372647 ==
1304 12:47:36.372726
1305 12:47:36.372787
1306 12:47:36.375903 TX Vref Scan disable
1307 12:47:36.379784 == TX Byte 0 ==
1308 12:47:36.382703 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1309 12:47:36.386409 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1310 12:47:36.389454 == TX Byte 1 ==
1311 12:47:36.393065 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1312 12:47:36.396660 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1313 12:47:36.396743
1314 12:47:36.399753 [DATLAT]
1315 12:47:36.399829 Freq=800, CH0 RK1
1316 12:47:36.399890
1317 12:47:36.402803 DATLAT Default: 0xa
1318 12:47:36.402878 0, 0xFFFF, sum = 0
1319 12:47:36.406512 1, 0xFFFF, sum = 0
1320 12:47:36.406587 2, 0xFFFF, sum = 0
1321 12:47:36.409953 3, 0xFFFF, sum = 0
1322 12:47:36.410027 4, 0xFFFF, sum = 0
1323 12:47:36.413030 5, 0xFFFF, sum = 0
1324 12:47:36.413098 6, 0xFFFF, sum = 0
1325 12:47:36.416658 7, 0xFFFF, sum = 0
1326 12:47:36.416734 8, 0xFFFF, sum = 0
1327 12:47:36.419677 9, 0x0, sum = 1
1328 12:47:36.419747 10, 0x0, sum = 2
1329 12:47:36.423140 11, 0x0, sum = 3
1330 12:47:36.423208 12, 0x0, sum = 4
1331 12:47:36.426439 best_step = 10
1332 12:47:36.426513
1333 12:47:36.426574 ==
1334 12:47:36.429847 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 12:47:36.433202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 12:47:36.433274 ==
1337 12:47:36.433335 RX Vref Scan: 0
1338 12:47:36.433397
1339 12:47:36.436551 RX Vref 0 -> 0, step: 1
1340 12:47:36.436615
1341 12:47:36.439580 RX Delay -95 -> 252, step: 8
1342 12:47:36.443250 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1343 12:47:36.449953 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1344 12:47:36.453210 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1345 12:47:36.456866 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1346 12:47:36.459707 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1347 12:47:36.463244 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1348 12:47:36.470120 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1349 12:47:36.473170 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1350 12:47:36.476835 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1351 12:47:36.479882 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1352 12:47:36.483692 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1353 12:47:36.487234 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1354 12:47:36.493347 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1355 12:47:36.497139 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1356 12:47:36.500072 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1357 12:47:36.503287 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1358 12:47:36.503371 ==
1359 12:47:36.507056 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 12:47:36.513461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 12:47:36.513545 ==
1362 12:47:36.513612 DQS Delay:
1363 12:47:36.517164 DQS0 = 0, DQS1 = 0
1364 12:47:36.517259 DQM Delay:
1365 12:47:36.517356 DQM0 = 87, DQM1 = 79
1366 12:47:36.520247 DQ Delay:
1367 12:47:36.523359 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1368 12:47:36.527197 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1369 12:47:36.530162 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1370 12:47:36.533702 DQ12 =84, DQ13 =88, DQ14 =88, DQ15 =88
1371 12:47:36.533801
1372 12:47:36.533896
1373 12:47:36.540342 [DQSOSCAuto] RK1, (LSB)MR18= 0x301a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1374 12:47:36.544122 CH0 RK1: MR19=606, MR18=301A
1375 12:47:36.550665 CH0_RK1: MR19=0x606, MR18=0x301A, DQSOSC=397, MR23=63, INC=93, DEC=62
1376 12:47:36.553651 [RxdqsGatingPostProcess] freq 800
1377 12:47:36.557167 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 12:47:36.560356 Pre-setting of DQS Precalculation
1379 12:47:36.567284 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 12:47:36.567368 ==
1381 12:47:36.570343 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 12:47:36.574096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 12:47:36.574184 ==
1384 12:47:36.580344 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 12:47:36.584149 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 12:47:36.594021 [CA 0] Center 36 (6~66) winsize 61
1387 12:47:36.597560 [CA 1] Center 36 (6~66) winsize 61
1388 12:47:36.600731 [CA 2] Center 34 (4~64) winsize 61
1389 12:47:36.603891 [CA 3] Center 33 (3~64) winsize 62
1390 12:47:36.607345 [CA 4] Center 34 (4~65) winsize 62
1391 12:47:36.610693 [CA 5] Center 34 (4~64) winsize 61
1392 12:47:36.610776
1393 12:47:36.613876 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1394 12:47:36.613959
1395 12:47:36.617286 [CATrainingPosCal] consider 1 rank data
1396 12:47:36.620801 u2DelayCellTimex100 = 270/100 ps
1397 12:47:36.624098 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1398 12:47:36.627769 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1399 12:47:36.630824 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1400 12:47:36.637368 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1401 12:47:36.641160 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1402 12:47:36.644163 CA5 delay=34 (4~64),Diff = 1 PI (7 cell)
1403 12:47:36.644245
1404 12:47:36.647390 CA PerBit enable=1, Macro0, CA PI delay=33
1405 12:47:36.647473
1406 12:47:36.650721 [CBTSetCACLKResult] CA Dly = 33
1407 12:47:36.650803 CS Dly: 4 (0~35)
1408 12:47:36.650869 ==
1409 12:47:36.654028 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 12:47:36.660808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 12:47:36.660908 ==
1412 12:47:36.664184 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 12:47:36.670701 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 12:47:36.680110 [CA 0] Center 36 (6~66) winsize 61
1415 12:47:36.683241 [CA 1] Center 36 (6~66) winsize 61
1416 12:47:36.686353 [CA 2] Center 33 (3~64) winsize 62
1417 12:47:36.690051 [CA 3] Center 34 (3~65) winsize 63
1418 12:47:36.693059 [CA 4] Center 34 (3~65) winsize 63
1419 12:47:36.696818 [CA 5] Center 33 (3~64) winsize 62
1420 12:47:36.696894
1421 12:47:36.699720 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1422 12:47:36.699793
1423 12:47:36.704124 [CATrainingPosCal] consider 2 rank data
1424 12:47:36.708430 u2DelayCellTimex100 = 270/100 ps
1425 12:47:36.712283 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1426 12:47:36.715426 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1427 12:47:36.718978 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1428 12:47:36.722738 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1429 12:47:36.726586 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1430 12:47:36.730015 CA5 delay=34 (4~64),Diff = 1 PI (7 cell)
1431 12:47:36.730094
1432 12:47:36.733518 CA PerBit enable=1, Macro0, CA PI delay=33
1433 12:47:36.733596
1434 12:47:36.737819 [CBTSetCACLKResult] CA Dly = 33
1435 12:47:36.737897 CS Dly: 5 (0~37)
1436 12:47:36.737966
1437 12:47:36.741487 ----->DramcWriteLeveling(PI) begin...
1438 12:47:36.741563 ==
1439 12:47:36.744537 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 12:47:36.748207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 12:47:36.748302 ==
1442 12:47:36.751341 Write leveling (Byte 0): 28 => 28
1443 12:47:36.755020 Write leveling (Byte 1): 29 => 29
1444 12:47:36.757790 DramcWriteLeveling(PI) end<-----
1445 12:47:36.757872
1446 12:47:36.757935 ==
1447 12:47:36.761129 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 12:47:36.764887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 12:47:36.768342 ==
1450 12:47:36.768449 [Gating] SW mode calibration
1451 12:47:36.775001 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 12:47:36.781681 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 12:47:36.784795 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 12:47:36.791482 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1455 12:47:36.795142 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1456 12:47:36.798197 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:47:36.801979 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:47:36.808624 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:47:36.811675 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:47:36.815387 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:47:36.822078 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:47:36.825094 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:47:36.828820 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:47:36.835624 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:47:36.838796 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:47:36.842542 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:47:36.845591 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:47:36.852118 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:47:36.855710 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:47:36.858808 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:47:36.866037 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1472 12:47:36.869199 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:47:36.872537 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:47:36.878903 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:47:36.882702 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:47:36.885747 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:47:36.892523 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:47:36.896097 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:47:36.899196 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 12:47:36.905988 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 12:47:36.909089 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 12:47:36.912811 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1483 12:47:36.915841 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 12:47:36.922700 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 12:47:36.926357 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 12:47:36.929431 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
1487 12:47:36.936298 0 10 8 | B1->B0 | 2e2e 2f2f | 1 0 | (1 0) (1 1)
1488 12:47:36.939877 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:47:36.942973 0 10 16 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1490 12:47:36.950257 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1491 12:47:36.953312 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 12:47:36.957061 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 12:47:36.959901 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 12:47:36.966844 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1495 12:47:36.970360 0 11 8 | B1->B0 | 3434 3636 | 0 0 | (0 0) (0 0)
1496 12:47:36.973970 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 12:47:36.980559 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 12:47:36.983447 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 12:47:36.986937 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 12:47:36.993721 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 12:47:36.997281 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 12:47:37.000825 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 12:47:37.003654 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1504 12:47:37.010476 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1505 12:47:37.013920 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:47:37.017545 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:47:37.023737 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:47:37.027551 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:47:37.030628 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:47:37.037411 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:47:37.041151 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:47:37.044286 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:47:37.050987 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:47:37.054126 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:47:37.057781 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:47:37.060898 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:47:37.067664 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 12:47:37.071169 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 12:47:37.074668 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1520 12:47:37.077900 Total UI for P1: 0, mck2ui 16
1521 12:47:37.081581 best dqsien dly found for B0: ( 0, 14, 6)
1522 12:47:37.088066 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 12:47:37.088162 Total UI for P1: 0, mck2ui 16
1524 12:47:37.091681 best dqsien dly found for B1: ( 0, 14, 8)
1525 12:47:37.097872 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1526 12:47:37.101292 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1527 12:47:37.101421
1528 12:47:37.104924 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1529 12:47:37.107860 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1530 12:47:37.111180 [Gating] SW calibration Done
1531 12:47:37.111282 ==
1532 12:47:37.114805 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 12:47:37.118307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1534 12:47:37.118409 ==
1535 12:47:37.118502 RX Vref Scan: 0
1536 12:47:37.121634
1537 12:47:37.121751 RX Vref 0 -> 0, step: 1
1538 12:47:37.121842
1539 12:47:37.124729 RX Delay -130 -> 252, step: 16
1540 12:47:37.128327 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1541 12:47:37.131438 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1542 12:47:37.138262 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1543 12:47:37.141934 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1544 12:47:37.145588 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1545 12:47:37.148492 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1546 12:47:37.151523 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1547 12:47:37.155227 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1548 12:47:37.162180 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1549 12:47:37.165022 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1550 12:47:37.168663 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1551 12:47:37.171784 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1552 12:47:37.178931 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1553 12:47:37.181906 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1554 12:47:37.185615 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1555 12:47:37.188543 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1556 12:47:37.188661 ==
1557 12:47:37.192210 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 12:47:37.195287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 12:47:37.195394 ==
1560 12:47:37.198854 DQS Delay:
1561 12:47:37.198975 DQS0 = 0, DQS1 = 0
1562 12:47:37.201985 DQM Delay:
1563 12:47:37.202114 DQM0 = 82, DQM1 = 76
1564 12:47:37.202225 DQ Delay:
1565 12:47:37.205359 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1566 12:47:37.208990 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =77
1567 12:47:37.212294 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1568 12:47:37.215651 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1569 12:47:37.215802
1570 12:47:37.215933
1571 12:47:37.219242 ==
1572 12:47:37.219370 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 12:47:37.225658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 12:47:37.225829 ==
1575 12:47:37.225946
1576 12:47:37.226049
1577 12:47:37.228962 TX Vref Scan disable
1578 12:47:37.229120 == TX Byte 0 ==
1579 12:47:37.232202 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1580 12:47:37.239251 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1581 12:47:37.239334 == TX Byte 1 ==
1582 12:47:37.242500 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1583 12:47:37.249181 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1584 12:47:37.249268 ==
1585 12:47:37.252824 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 12:47:37.255866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 12:47:37.255968 ==
1588 12:47:37.268890 TX Vref=22, minBit 1, minWin=27, winSum=441
1589 12:47:37.271823 TX Vref=24, minBit 1, minWin=27, winSum=444
1590 12:47:37.275517 TX Vref=26, minBit 0, minWin=27, winSum=447
1591 12:47:37.278550 TX Vref=28, minBit 0, minWin=28, winSum=451
1592 12:47:37.282150 TX Vref=30, minBit 0, minWin=28, winSum=452
1593 12:47:37.285784 TX Vref=32, minBit 11, minWin=27, winSum=453
1594 12:47:37.292415 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 30
1595 12:47:37.292575
1596 12:47:37.296120 Final TX Range 1 Vref 30
1597 12:47:37.296266
1598 12:47:37.296370 ==
1599 12:47:37.299678 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 12:47:37.302843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 12:47:37.302970 ==
1602 12:47:37.303071
1603 12:47:37.303164
1604 12:47:37.305945 TX Vref Scan disable
1605 12:47:37.309435 == TX Byte 0 ==
1606 12:47:37.313045 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1607 12:47:37.316237 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1608 12:47:37.319585 == TX Byte 1 ==
1609 12:47:37.322795 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1610 12:47:37.326501 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1611 12:47:37.326661
1612 12:47:37.326785 [DATLAT]
1613 12:47:37.329618 Freq=800, CH1 RK0
1614 12:47:37.329776
1615 12:47:37.333318 DATLAT Default: 0xa
1616 12:47:37.333474 0, 0xFFFF, sum = 0
1617 12:47:37.336554 1, 0xFFFF, sum = 0
1618 12:47:37.336752 2, 0xFFFF, sum = 0
1619 12:47:37.339536 3, 0xFFFF, sum = 0
1620 12:47:37.339694 4, 0xFFFF, sum = 0
1621 12:47:37.343030 5, 0xFFFF, sum = 0
1622 12:47:37.343187 6, 0xFFFF, sum = 0
1623 12:47:37.346547 7, 0xFFFF, sum = 0
1624 12:47:37.346705 8, 0xFFFF, sum = 0
1625 12:47:37.349720 9, 0x0, sum = 1
1626 12:47:37.349944 10, 0x0, sum = 2
1627 12:47:37.353049 11, 0x0, sum = 3
1628 12:47:37.353223 12, 0x0, sum = 4
1629 12:47:37.353355 best_step = 10
1630 12:47:37.353472
1631 12:47:37.356867 ==
1632 12:47:37.357014 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 12:47:37.363524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 12:47:37.363667 ==
1635 12:47:37.363776 RX Vref Scan: 1
1636 12:47:37.363875
1637 12:47:37.366509 Set Vref Range= 32 -> 127
1638 12:47:37.366643
1639 12:47:37.370220 RX Vref 32 -> 127, step: 1
1640 12:47:37.370354
1641 12:47:37.373211 RX Delay -111 -> 252, step: 8
1642 12:47:37.373345
1643 12:47:37.377017 Set Vref, RX VrefLevel [Byte0]: 32
1644 12:47:37.380186 [Byte1]: 32
1645 12:47:37.380320
1646 12:47:37.383257 Set Vref, RX VrefLevel [Byte0]: 33
1647 12:47:37.386837 [Byte1]: 33
1648 12:47:37.387003
1649 12:47:37.389827 Set Vref, RX VrefLevel [Byte0]: 34
1650 12:47:37.393433 [Byte1]: 34
1651 12:47:37.396884
1652 12:47:37.397047 Set Vref, RX VrefLevel [Byte0]: 35
1653 12:47:37.399952 [Byte1]: 35
1654 12:47:37.404192
1655 12:47:37.404326 Set Vref, RX VrefLevel [Byte0]: 36
1656 12:47:37.407846 [Byte1]: 36
1657 12:47:37.411952
1658 12:47:37.412085 Set Vref, RX VrefLevel [Byte0]: 37
1659 12:47:37.415536 [Byte1]: 37
1660 12:47:37.419841
1661 12:47:37.419990 Set Vref, RX VrefLevel [Byte0]: 38
1662 12:47:37.422861 [Byte1]: 38
1663 12:47:37.427458
1664 12:47:37.427637 Set Vref, RX VrefLevel [Byte0]: 39
1665 12:47:37.430761 [Byte1]: 39
1666 12:47:37.434938
1667 12:47:37.435138 Set Vref, RX VrefLevel [Byte0]: 40
1668 12:47:37.438564 [Byte1]: 40
1669 12:47:37.442317
1670 12:47:37.442486 Set Vref, RX VrefLevel [Byte0]: 41
1671 12:47:37.446044 [Byte1]: 41
1672 12:47:37.450251
1673 12:47:37.450421 Set Vref, RX VrefLevel [Byte0]: 42
1674 12:47:37.453321 [Byte1]: 42
1675 12:47:37.457561
1676 12:47:37.457834 Set Vref, RX VrefLevel [Byte0]: 43
1677 12:47:37.461113 [Byte1]: 43
1678 12:47:37.465540
1679 12:47:37.465833 Set Vref, RX VrefLevel [Byte0]: 44
1680 12:47:37.468988 [Byte1]: 44
1681 12:47:37.473242
1682 12:47:37.473510 Set Vref, RX VrefLevel [Byte0]: 45
1683 12:47:37.476283 [Byte1]: 45
1684 12:47:37.480690
1685 12:47:37.480976 Set Vref, RX VrefLevel [Byte0]: 46
1686 12:47:37.484127 [Byte1]: 46
1687 12:47:37.488418
1688 12:47:37.488693 Set Vref, RX VrefLevel [Byte0]: 47
1689 12:47:37.491419 [Byte1]: 47
1690 12:47:37.495842
1691 12:47:37.496133 Set Vref, RX VrefLevel [Byte0]: 48
1692 12:47:37.499443 [Byte1]: 48
1693 12:47:37.503751
1694 12:47:37.503954 Set Vref, RX VrefLevel [Byte0]: 49
1695 12:47:37.506816 [Byte1]: 49
1696 12:47:37.511400
1697 12:47:37.511596 Set Vref, RX VrefLevel [Byte0]: 50
1698 12:47:37.515055 [Byte1]: 50
1699 12:47:37.519042
1700 12:47:37.519245 Set Vref, RX VrefLevel [Byte0]: 51
1701 12:47:37.522143 [Byte1]: 51
1702 12:47:37.526820
1703 12:47:37.527017 Set Vref, RX VrefLevel [Byte0]: 52
1704 12:47:37.530051 [Byte1]: 52
1705 12:47:37.534148
1706 12:47:37.534352 Set Vref, RX VrefLevel [Byte0]: 53
1707 12:47:37.537574 [Byte1]: 53
1708 12:47:37.542231
1709 12:47:37.542485 Set Vref, RX VrefLevel [Byte0]: 54
1710 12:47:37.545049 [Byte1]: 54
1711 12:47:37.549766
1712 12:47:37.549964 Set Vref, RX VrefLevel [Byte0]: 55
1713 12:47:37.552658 [Byte1]: 55
1714 12:47:37.557380
1715 12:47:37.557622 Set Vref, RX VrefLevel [Byte0]: 56
1716 12:47:37.560306 [Byte1]: 56
1717 12:47:37.565084
1718 12:47:37.565296 Set Vref, RX VrefLevel [Byte0]: 57
1719 12:47:37.568046 [Byte1]: 57
1720 12:47:37.572740
1721 12:47:37.572870 Set Vref, RX VrefLevel [Byte0]: 58
1722 12:47:37.575882 [Byte1]: 58
1723 12:47:37.580226
1724 12:47:37.580320 Set Vref, RX VrefLevel [Byte0]: 59
1725 12:47:37.583236 [Byte1]: 59
1726 12:47:37.587444
1727 12:47:37.587531 Set Vref, RX VrefLevel [Byte0]: 60
1728 12:47:37.591246 [Byte1]: 60
1729 12:47:37.595308
1730 12:47:37.595393 Set Vref, RX VrefLevel [Byte0]: 61
1731 12:47:37.598982 [Byte1]: 61
1732 12:47:37.603254
1733 12:47:37.603373 Set Vref, RX VrefLevel [Byte0]: 62
1734 12:47:37.606334 [Byte1]: 62
1735 12:47:37.610532
1736 12:47:37.610651 Set Vref, RX VrefLevel [Byte0]: 63
1737 12:47:37.614174 [Byte1]: 63
1738 12:47:37.618758
1739 12:47:37.618955 Set Vref, RX VrefLevel [Byte0]: 64
1740 12:47:37.649034 [Byte1]: 64
1741 12:47:37.649281
1742 12:47:37.649491 Set Vref, RX VrefLevel [Byte0]: 65
1743 12:47:37.649677 [Byte1]: 65
1744 12:47:37.649878
1745 12:47:37.650067 Set Vref, RX VrefLevel [Byte0]: 66
1746 12:47:37.650234 [Byte1]: 66
1747 12:47:37.650414
1748 12:47:37.650588 Set Vref, RX VrefLevel [Byte0]: 67
1749 12:47:37.650753 [Byte1]: 67
1750 12:47:37.651149
1751 12:47:37.651352 Set Vref, RX VrefLevel [Byte0]: 68
1752 12:47:37.651985 [Byte1]: 68
1753 12:47:37.656887
1754 12:47:37.657117 Set Vref, RX VrefLevel [Byte0]: 69
1755 12:47:37.659622 [Byte1]: 69
1756 12:47:37.664342
1757 12:47:37.664495 Set Vref, RX VrefLevel [Byte0]: 70
1758 12:47:37.667346 [Byte1]: 70
1759 12:47:37.671715
1760 12:47:37.671851 Set Vref, RX VrefLevel [Byte0]: 71
1761 12:47:37.675288 [Byte1]: 71
1762 12:47:37.679290
1763 12:47:37.679400 Set Vref, RX VrefLevel [Byte0]: 72
1764 12:47:37.682891 [Byte1]: 72
1765 12:47:37.687610
1766 12:47:37.687713 Set Vref, RX VrefLevel [Byte0]: 73
1767 12:47:37.690600 [Byte1]: 73
1768 12:47:37.694767
1769 12:47:37.694879 Set Vref, RX VrefLevel [Byte0]: 74
1770 12:47:37.698299 [Byte1]: 74
1771 12:47:37.702449
1772 12:47:37.702543 Set Vref, RX VrefLevel [Byte0]: 75
1773 12:47:37.706044 [Byte1]: 75
1774 12:47:37.710466
1775 12:47:37.710543 Set Vref, RX VrefLevel [Byte0]: 76
1776 12:47:37.713468 [Byte1]: 76
1777 12:47:37.717565
1778 12:47:37.717638 Set Vref, RX VrefLevel [Byte0]: 77
1779 12:47:37.721110 [Byte1]: 77
1780 12:47:37.725243
1781 12:47:37.725325 Set Vref, RX VrefLevel [Byte0]: 78
1782 12:47:37.728663 [Byte1]: 78
1783 12:47:37.733144
1784 12:47:37.733236 Final RX Vref Byte 0 = 63 to rank0
1785 12:47:37.736275 Final RX Vref Byte 1 = 58 to rank0
1786 12:47:37.740027 Final RX Vref Byte 0 = 63 to rank1
1787 12:47:37.743072 Final RX Vref Byte 1 = 58 to rank1==
1788 12:47:37.746691 Dram Type= 6, Freq= 0, CH_1, rank 0
1789 12:47:37.750132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 12:47:37.753108 ==
1791 12:47:37.753204 DQS Delay:
1792 12:47:37.753280 DQS0 = 0, DQS1 = 0
1793 12:47:37.756901 DQM Delay:
1794 12:47:37.757004 DQM0 = 84, DQM1 = 74
1795 12:47:37.757086 DQ Delay:
1796 12:47:37.759818 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1797 12:47:37.763751 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1798 12:47:37.767034 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1799 12:47:37.770381 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1800 12:47:37.770509
1801 12:47:37.770607
1802 12:47:37.780289 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b00, (MSB)MR19= 0x606, tDQSOscB0 = 410 ps tDQSOscB1 = 398 ps
1803 12:47:37.783920 CH1 RK0: MR19=606, MR18=2B00
1804 12:47:37.786984 CH1_RK0: MR19=0x606, MR18=0x2B00, DQSOSC=398, MR23=63, INC=93, DEC=62
1805 12:47:37.787124
1806 12:47:37.790588 ----->DramcWriteLeveling(PI) begin...
1807 12:47:37.794098 ==
1808 12:47:37.797519 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 12:47:37.800491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 12:47:37.800691 ==
1811 12:47:37.803855 Write leveling (Byte 0): 28 => 28
1812 12:47:37.807347 Write leveling (Byte 1): 28 => 28
1813 12:47:37.810915 DramcWriteLeveling(PI) end<-----
1814 12:47:37.811165
1815 12:47:37.811364 ==
1816 12:47:37.814501 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 12:47:37.817614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1818 12:47:37.817945 ==
1819 12:47:37.820723 [Gating] SW mode calibration
1820 12:47:37.828165 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1821 12:47:37.831166 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1822 12:47:37.837830 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1823 12:47:37.841277 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1824 12:47:37.844188 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1825 12:47:37.851056 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:47:37.854165 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:47:37.857713 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:47:37.864233 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:47:37.867999 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:47:37.871187 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:47:37.877766 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:47:37.881141 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:47:37.884635 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:47:37.888047 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:47:37.894782 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 12:47:37.897862 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 12:47:37.901455 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 12:47:37.908087 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1839 12:47:37.911353 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1840 12:47:37.914689 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 12:47:37.921712 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:47:37.924792 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:47:37.928400 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:47:37.935255 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:47:37.938643 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 12:47:37.941909 0 9 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1847 12:47:37.944740 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1848 12:47:37.951759 0 9 8 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
1849 12:47:37.954849 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 12:47:37.958417 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 12:47:37.965372 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1852 12:47:37.968406 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 12:47:37.971968 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 12:47:37.978266 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 12:47:37.982152 0 10 4 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (1 0)
1856 12:47:37.985376 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
1857 12:47:37.988710 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 12:47:37.995569 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 12:47:37.999283 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 12:47:38.002411 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 12:47:38.009364 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 12:47:38.013105 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 12:47:38.015720 0 11 4 | B1->B0 | 2a2a 3939 | 0 1 | (0 0) (0 0)
1864 12:47:38.022563 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1865 12:47:38.025844 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 12:47:38.028914 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 12:47:38.035657 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 12:47:38.039266 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 12:47:38.042751 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 12:47:38.045865 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 12:47:38.052550 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1872 12:47:38.055904 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1873 12:47:38.059326 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 12:47:38.066157 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 12:47:38.069149 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 12:47:38.072832 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 12:47:38.079445 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 12:47:38.083110 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 12:47:38.086399 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 12:47:38.092811 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 12:47:38.096400 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 12:47:38.099753 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 12:47:38.103074 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 12:47:38.109263 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 12:47:38.112934 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 12:47:38.116585 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 12:47:38.122805 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1888 12:47:38.126512 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 12:47:38.129504 Total UI for P1: 0, mck2ui 16
1890 12:47:38.133042 best dqsien dly found for B0: ( 0, 14, 4)
1891 12:47:38.136234 Total UI for P1: 0, mck2ui 16
1892 12:47:38.139376 best dqsien dly found for B1: ( 0, 14, 4)
1893 12:47:38.143205 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1894 12:47:38.146067 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1895 12:47:38.146165
1896 12:47:38.149763 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1897 12:47:38.152799 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1898 12:47:38.156469 [Gating] SW calibration Done
1899 12:47:38.156592 ==
1900 12:47:38.159482 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 12:47:38.163152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1902 12:47:38.163251 ==
1903 12:47:38.166470 RX Vref Scan: 0
1904 12:47:38.166552
1905 12:47:38.169477 RX Vref 0 -> 0, step: 1
1906 12:47:38.169585
1907 12:47:38.169688 RX Delay -130 -> 252, step: 16
1908 12:47:38.176352 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1909 12:47:38.179429 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1910 12:47:38.183143 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1911 12:47:38.186320 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1912 12:47:38.189793 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1913 12:47:38.196437 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1914 12:47:38.199964 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1915 12:47:38.203005 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1916 12:47:38.206541 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1917 12:47:38.209936 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1918 12:47:38.213348 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1919 12:47:38.220137 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1920 12:47:38.223518 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1921 12:47:38.226655 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1922 12:47:38.230432 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1923 12:47:38.236623 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1924 12:47:38.236788 ==
1925 12:47:38.240253 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 12:47:38.243969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 12:47:38.244055 ==
1928 12:47:38.244123 DQS Delay:
1929 12:47:38.247155 DQS0 = 0, DQS1 = 0
1930 12:47:38.247247 DQM Delay:
1931 12:47:38.250614 DQM0 = 81, DQM1 = 77
1932 12:47:38.250699 DQ Delay:
1933 12:47:38.253767 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1934 12:47:38.256839 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1935 12:47:38.260544 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1936 12:47:38.263671 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1937 12:47:38.263773
1938 12:47:38.263865
1939 12:47:38.263960 ==
1940 12:47:38.267102 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 12:47:38.270678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 12:47:38.270822 ==
1943 12:47:38.270926
1944 12:47:38.271020
1945 12:47:38.273515 TX Vref Scan disable
1946 12:47:38.277178 == TX Byte 0 ==
1947 12:47:38.280299 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1948 12:47:38.284014 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1949 12:47:38.287214 == TX Byte 1 ==
1950 12:47:38.290384 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1951 12:47:38.293681 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1952 12:47:38.293785 ==
1953 12:47:38.297394 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 12:47:38.300755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 12:47:38.300840 ==
1956 12:47:38.314528 TX Vref=22, minBit 1, minWin=27, winSum=442
1957 12:47:38.317994 TX Vref=24, minBit 10, minWin=27, winSum=444
1958 12:47:38.321269 TX Vref=26, minBit 1, minWin=27, winSum=445
1959 12:47:38.324709 TX Vref=28, minBit 1, minWin=27, winSum=447
1960 12:47:38.328236 TX Vref=30, minBit 0, minWin=28, winSum=451
1961 12:47:38.331184 TX Vref=32, minBit 0, minWin=28, winSum=450
1962 12:47:38.338093 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 30
1963 12:47:38.338222
1964 12:47:38.341184 Final TX Range 1 Vref 30
1965 12:47:38.341269
1966 12:47:38.341335 ==
1967 12:47:38.344576 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 12:47:38.348522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 12:47:38.348634 ==
1970 12:47:38.348724
1971 12:47:38.348789
1972 12:47:38.351427 TX Vref Scan disable
1973 12:47:38.354486 == TX Byte 0 ==
1974 12:47:38.358134 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1975 12:47:38.361161 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1976 12:47:38.364878 == TX Byte 1 ==
1977 12:47:38.367940 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1978 12:47:38.371769 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1979 12:47:38.371875
1980 12:47:38.374756 [DATLAT]
1981 12:47:38.374860 Freq=800, CH1 RK1
1982 12:47:38.374965
1983 12:47:38.378271 DATLAT Default: 0xa
1984 12:47:38.378371 0, 0xFFFF, sum = 0
1985 12:47:38.381666 1, 0xFFFF, sum = 0
1986 12:47:38.381774 2, 0xFFFF, sum = 0
1987 12:47:38.384622 3, 0xFFFF, sum = 0
1988 12:47:38.384732 4, 0xFFFF, sum = 0
1989 12:47:38.388365 5, 0xFFFF, sum = 0
1990 12:47:38.388470 6, 0xFFFF, sum = 0
1991 12:47:38.391507 7, 0xFFFF, sum = 0
1992 12:47:38.391607 8, 0xFFFF, sum = 0
1993 12:47:38.394655 9, 0x0, sum = 1
1994 12:47:38.394784 10, 0x0, sum = 2
1995 12:47:38.398496 11, 0x0, sum = 3
1996 12:47:38.398600 12, 0x0, sum = 4
1997 12:47:38.401609 best_step = 10
1998 12:47:38.401725
1999 12:47:38.401826 ==
2000 12:47:38.404727 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 12:47:38.408553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 12:47:38.408640 ==
2003 12:47:38.411438 RX Vref Scan: 0
2004 12:47:38.411522
2005 12:47:38.411590 RX Vref 0 -> 0, step: 1
2006 12:47:38.411652
2007 12:47:38.414866 RX Delay -111 -> 252, step: 8
2008 12:47:38.421860 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2009 12:47:38.424971 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2010 12:47:38.428313 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2011 12:47:38.432154 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2012 12:47:38.435116 iDelay=209, Bit 4, Center 80 (-31 ~ 192) 224
2013 12:47:38.438613 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
2014 12:47:38.445592 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2015 12:47:38.448591 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2016 12:47:38.452294 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2017 12:47:38.455486 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2018 12:47:38.459217 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2019 12:47:38.465366 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2020 12:47:38.468948 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2021 12:47:38.472035 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2022 12:47:38.475876 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2023 12:47:38.478886 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2024 12:47:38.479010 ==
2025 12:47:38.482567 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 12:47:38.489390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 12:47:38.489500 ==
2028 12:47:38.489584 DQS Delay:
2029 12:47:38.492627 DQS0 = 0, DQS1 = 0
2030 12:47:38.492751 DQM Delay:
2031 12:47:38.492842 DQM0 = 80, DQM1 = 75
2032 12:47:38.495775 DQ Delay:
2033 12:47:38.499460 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2034 12:47:38.502585 DQ4 =80, DQ5 =88, DQ6 =92, DQ7 =76
2035 12:47:38.506275 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2036 12:47:38.509474 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2037 12:47:38.509560
2038 12:47:38.509626
2039 12:47:38.516239 [DQSOSCAuto] RK1, (LSB)MR18= 0x232f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 401 ps
2040 12:47:38.519382 CH1 RK1: MR19=606, MR18=232F
2041 12:47:38.525959 CH1_RK1: MR19=0x606, MR18=0x232F, DQSOSC=397, MR23=63, INC=93, DEC=62
2042 12:47:38.529328 [RxdqsGatingPostProcess] freq 800
2043 12:47:38.532516 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2044 12:47:38.536046 Pre-setting of DQS Precalculation
2045 12:47:38.542948 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2046 12:47:38.549601 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2047 12:47:38.556204 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2048 12:47:38.556375
2049 12:47:38.556530
2050 12:47:38.560096 [Calibration Summary] 1600 Mbps
2051 12:47:38.560220 CH 0, Rank 0
2052 12:47:38.563522 SW Impedance : PASS
2053 12:47:38.563658 DUTY Scan : NO K
2054 12:47:38.566334 ZQ Calibration : PASS
2055 12:47:38.570032 Jitter Meter : NO K
2056 12:47:38.570186 CBT Training : PASS
2057 12:47:38.573193 Write leveling : PASS
2058 12:47:38.576847 RX DQS gating : PASS
2059 12:47:38.577080 RX DQ/DQS(RDDQC) : PASS
2060 12:47:38.580023 TX DQ/DQS : PASS
2061 12:47:38.583146 RX DATLAT : PASS
2062 12:47:38.583376 RX DQ/DQS(Engine): PASS
2063 12:47:38.586870 TX OE : NO K
2064 12:47:38.587102 All Pass.
2065 12:47:38.587322
2066 12:47:38.590022 CH 0, Rank 1
2067 12:47:38.590247 SW Impedance : PASS
2068 12:47:38.593784 DUTY Scan : NO K
2069 12:47:38.594004 ZQ Calibration : PASS
2070 12:47:38.596608 Jitter Meter : NO K
2071 12:47:38.599987 CBT Training : PASS
2072 12:47:38.600227 Write leveling : PASS
2073 12:47:38.603660 RX DQS gating : PASS
2074 12:47:38.606784 RX DQ/DQS(RDDQC) : PASS
2075 12:47:38.607111 TX DQ/DQS : PASS
2076 12:47:38.610587 RX DATLAT : PASS
2077 12:47:38.613634 RX DQ/DQS(Engine): PASS
2078 12:47:38.613877 TX OE : NO K
2079 12:47:38.614078 All Pass.
2080 12:47:38.616887
2081 12:47:38.617072 CH 1, Rank 0
2082 12:47:38.620514 SW Impedance : PASS
2083 12:47:38.620759 DUTY Scan : NO K
2084 12:47:38.623698 ZQ Calibration : PASS
2085 12:47:38.623871 Jitter Meter : NO K
2086 12:47:38.626903 CBT Training : PASS
2087 12:47:38.630507 Write leveling : PASS
2088 12:47:38.630680 RX DQS gating : PASS
2089 12:47:38.634126 RX DQ/DQS(RDDQC) : PASS
2090 12:47:38.636947 TX DQ/DQS : PASS
2091 12:47:38.637124 RX DATLAT : PASS
2092 12:47:38.640500 RX DQ/DQS(Engine): PASS
2093 12:47:38.643913 TX OE : NO K
2094 12:47:38.644116 All Pass.
2095 12:47:38.644270
2096 12:47:38.644400 CH 1, Rank 1
2097 12:47:38.647424 SW Impedance : PASS
2098 12:47:38.650608 DUTY Scan : NO K
2099 12:47:38.650782 ZQ Calibration : PASS
2100 12:47:38.653617 Jitter Meter : NO K
2101 12:47:38.657184 CBT Training : PASS
2102 12:47:38.657357 Write leveling : PASS
2103 12:47:38.660494 RX DQS gating : PASS
2104 12:47:38.660743 RX DQ/DQS(RDDQC) : PASS
2105 12:47:38.663883 TX DQ/DQS : PASS
2106 12:47:38.667216 RX DATLAT : PASS
2107 12:47:38.667397 RX DQ/DQS(Engine): PASS
2108 12:47:38.670625 TX OE : NO K
2109 12:47:38.670804 All Pass.
2110 12:47:38.670944
2111 12:47:38.673894 DramC Write-DBI off
2112 12:47:38.677384 PER_BANK_REFRESH: Hybrid Mode
2113 12:47:38.677547 TX_TRACKING: ON
2114 12:47:38.680859 [GetDramInforAfterCalByMRR] Vendor 6.
2115 12:47:38.684495 [GetDramInforAfterCalByMRR] Revision 606.
2116 12:47:38.687680 [GetDramInforAfterCalByMRR] Revision 2 0.
2117 12:47:38.690757 MR0 0x3b3b
2118 12:47:38.690996 MR8 0x5151
2119 12:47:38.694557 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2120 12:47:38.694783
2121 12:47:38.694979 MR0 0x3b3b
2122 12:47:38.697676 MR8 0x5151
2123 12:47:38.700854 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2124 12:47:38.701036
2125 12:47:38.707854 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2126 12:47:38.714728 [FAST_K] Save calibration result to emmc
2127 12:47:38.717971 [FAST_K] Save calibration result to emmc
2128 12:47:38.718213 dram_init: config_dvfs: 1
2129 12:47:38.724642 dramc_set_vcore_voltage set vcore to 662500
2130 12:47:38.724975 Read voltage for 1200, 2
2131 12:47:38.725210 Vio18 = 0
2132 12:47:38.727921 Vcore = 662500
2133 12:47:38.728268 Vdram = 0
2134 12:47:38.728575 Vddq = 0
2135 12:47:38.731048 Vmddr = 0
2136 12:47:38.734933 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2137 12:47:38.741189 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2138 12:47:38.741521 MEM_TYPE=3, freq_sel=15
2139 12:47:38.744813 sv_algorithm_assistance_LP4_1600
2140 12:47:38.751115 ============ PULL DRAM RESETB DOWN ============
2141 12:47:38.754864 ========== PULL DRAM RESETB DOWN end =========
2142 12:47:38.757885 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2143 12:47:38.761361 ===================================
2144 12:47:38.764692 LPDDR4 DRAM CONFIGURATION
2145 12:47:38.767975 ===================================
2146 12:47:38.768077 EX_ROW_EN[0] = 0x0
2147 12:47:38.771490 EX_ROW_EN[1] = 0x0
2148 12:47:38.774835 LP4Y_EN = 0x0
2149 12:47:38.774939 WORK_FSP = 0x0
2150 12:47:38.778103 WL = 0x4
2151 12:47:38.778210 RL = 0x4
2152 12:47:38.781808 BL = 0x2
2153 12:47:38.781914 RPST = 0x0
2154 12:47:38.784575 RD_PRE = 0x0
2155 12:47:38.784705 WR_PRE = 0x1
2156 12:47:38.788091 WR_PST = 0x0
2157 12:47:38.788200 DBI_WR = 0x0
2158 12:47:38.791493 DBI_RD = 0x0
2159 12:47:38.791601 OTF = 0x1
2160 12:47:38.795112 ===================================
2161 12:47:38.798278 ===================================
2162 12:47:38.801362 ANA top config
2163 12:47:38.805166 ===================================
2164 12:47:38.805279 DLL_ASYNC_EN = 0
2165 12:47:38.808349 ALL_SLAVE_EN = 0
2166 12:47:38.811541 NEW_RANK_MODE = 1
2167 12:47:38.814988 DLL_IDLE_MODE = 1
2168 12:47:38.815117 LP45_APHY_COMB_EN = 1
2169 12:47:38.818625 TX_ODT_DIS = 1
2170 12:47:38.821729 NEW_8X_MODE = 1
2171 12:47:38.824857 ===================================
2172 12:47:38.828560 ===================================
2173 12:47:38.831796 data_rate = 2400
2174 12:47:38.834805 CKR = 1
2175 12:47:38.834910 DQ_P2S_RATIO = 8
2176 12:47:38.838522 ===================================
2177 12:47:38.841984 CA_P2S_RATIO = 8
2178 12:47:38.845349 DQ_CA_OPEN = 0
2179 12:47:38.848348 DQ_SEMI_OPEN = 0
2180 12:47:38.852135 CA_SEMI_OPEN = 0
2181 12:47:38.852242 CA_FULL_RATE = 0
2182 12:47:38.855047 DQ_CKDIV4_EN = 0
2183 12:47:38.858574 CA_CKDIV4_EN = 0
2184 12:47:38.861962 CA_PREDIV_EN = 0
2185 12:47:38.865245 PH8_DLY = 17
2186 12:47:38.869084 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2187 12:47:38.869196 DQ_AAMCK_DIV = 4
2188 12:47:38.872346 CA_AAMCK_DIV = 4
2189 12:47:38.875249 CA_ADMCK_DIV = 4
2190 12:47:38.878497 DQ_TRACK_CA_EN = 0
2191 12:47:38.882307 CA_PICK = 1200
2192 12:47:38.885651 CA_MCKIO = 1200
2193 12:47:38.888637 MCKIO_SEMI = 0
2194 12:47:38.888764 PLL_FREQ = 2366
2195 12:47:38.892383 DQ_UI_PI_RATIO = 32
2196 12:47:38.895402 CA_UI_PI_RATIO = 0
2197 12:47:38.898987 ===================================
2198 12:47:38.902509 ===================================
2199 12:47:38.905476 memory_type:LPDDR4
2200 12:47:38.905599 GP_NUM : 10
2201 12:47:38.909365 SRAM_EN : 1
2202 12:47:38.912426 MD32_EN : 0
2203 12:47:38.915637 ===================================
2204 12:47:38.915742 [ANA_INIT] >>>>>>>>>>>>>>
2205 12:47:38.919299 <<<<<< [CONFIGURE PHASE]: ANA_TX
2206 12:47:38.922804 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2207 12:47:38.925757 ===================================
2208 12:47:38.929451 data_rate = 2400,PCW = 0X5b00
2209 12:47:38.932485 ===================================
2210 12:47:38.935609 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2211 12:47:38.942571 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 12:47:38.946177 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2213 12:47:38.952687 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2214 12:47:38.955852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2215 12:47:38.959634 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2216 12:47:38.959750 [ANA_INIT] flow start
2217 12:47:38.962558 [ANA_INIT] PLL >>>>>>>>
2218 12:47:38.966061 [ANA_INIT] PLL <<<<<<<<
2219 12:47:38.966170 [ANA_INIT] MIDPI >>>>>>>>
2220 12:47:38.969518 [ANA_INIT] MIDPI <<<<<<<<
2221 12:47:38.973055 [ANA_INIT] DLL >>>>>>>>
2222 12:47:38.973162 [ANA_INIT] DLL <<<<<<<<
2223 12:47:38.976123 [ANA_INIT] flow end
2224 12:47:38.979236 ============ LP4 DIFF to SE enter ============
2225 12:47:38.982988 ============ LP4 DIFF to SE exit ============
2226 12:47:38.985891 [ANA_INIT] <<<<<<<<<<<<<
2227 12:47:38.989761 [Flow] Enable top DCM control >>>>>
2228 12:47:38.992630 [Flow] Enable top DCM control <<<<<
2229 12:47:38.996060 Enable DLL master slave shuffle
2230 12:47:39.003050 ==============================================================
2231 12:47:39.003169 Gating Mode config
2232 12:47:39.010201 ==============================================================
2233 12:47:39.010321 Config description:
2234 12:47:39.020006 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2235 12:47:39.026253 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2236 12:47:39.033261 SELPH_MODE 0: By rank 1: By Phase
2237 12:47:39.036373 ==============================================================
2238 12:47:39.040214 GAT_TRACK_EN = 1
2239 12:47:39.043451 RX_GATING_MODE = 2
2240 12:47:39.046507 RX_GATING_TRACK_MODE = 2
2241 12:47:39.050288 SELPH_MODE = 1
2242 12:47:39.053220 PICG_EARLY_EN = 1
2243 12:47:39.057036 VALID_LAT_VALUE = 1
2244 12:47:39.060071 ==============================================================
2245 12:47:39.063205 Enter into Gating configuration >>>>
2246 12:47:39.066964 Exit from Gating configuration <<<<
2247 12:47:39.070123 Enter into DVFS_PRE_config >>>>>
2248 12:47:39.080435 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2249 12:47:39.083546 Exit from DVFS_PRE_config <<<<<
2250 12:47:39.086823 Enter into PICG configuration >>>>
2251 12:47:39.090453 Exit from PICG configuration <<<<
2252 12:47:39.093536 [RX_INPUT] configuration >>>>>
2253 12:47:39.097195 [RX_INPUT] configuration <<<<<
2254 12:47:39.100590 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2255 12:47:39.107229 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2256 12:47:39.113962 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2257 12:47:39.120880 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2258 12:47:39.127511 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2259 12:47:39.130681 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2260 12:47:39.137390 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2261 12:47:39.140775 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2262 12:47:39.143861 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2263 12:47:39.147558 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2264 12:47:39.150739 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2265 12:47:39.157476 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2266 12:47:39.160872 ===================================
2267 12:47:39.164067 LPDDR4 DRAM CONFIGURATION
2268 12:47:39.164170 ===================================
2269 12:47:39.167750 EX_ROW_EN[0] = 0x0
2270 12:47:39.170815 EX_ROW_EN[1] = 0x0
2271 12:47:39.170915 LP4Y_EN = 0x0
2272 12:47:39.174624 WORK_FSP = 0x0
2273 12:47:39.174742 WL = 0x4
2274 12:47:39.177779 RL = 0x4
2275 12:47:39.177882 BL = 0x2
2276 12:47:39.180776 RPST = 0x0
2277 12:47:39.180895 RD_PRE = 0x0
2278 12:47:39.184442 WR_PRE = 0x1
2279 12:47:39.184538 WR_PST = 0x0
2280 12:47:39.187728 DBI_WR = 0x0
2281 12:47:39.187837 DBI_RD = 0x0
2282 12:47:39.190847 OTF = 0x1
2283 12:47:39.194626 ===================================
2284 12:47:39.197650 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2285 12:47:39.201254 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2286 12:47:39.207867 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2287 12:47:39.210974 ===================================
2288 12:47:39.211088 LPDDR4 DRAM CONFIGURATION
2289 12:47:39.214604 ===================================
2290 12:47:39.217793 EX_ROW_EN[0] = 0x10
2291 12:47:39.217899 EX_ROW_EN[1] = 0x0
2292 12:47:39.221293 LP4Y_EN = 0x0
2293 12:47:39.221396 WORK_FSP = 0x0
2294 12:47:39.224686 WL = 0x4
2295 12:47:39.224811 RL = 0x4
2296 12:47:39.228299 BL = 0x2
2297 12:47:39.228410 RPST = 0x0
2298 12:47:39.231325 RD_PRE = 0x0
2299 12:47:39.235093 WR_PRE = 0x1
2300 12:47:39.235220 WR_PST = 0x0
2301 12:47:39.238231 DBI_WR = 0x0
2302 12:47:39.238348 DBI_RD = 0x0
2303 12:47:39.241284 OTF = 0x1
2304 12:47:39.245064 ===================================
2305 12:47:39.247912 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2306 12:47:39.248024 ==
2307 12:47:39.251426 Dram Type= 6, Freq= 0, CH_0, rank 0
2308 12:47:39.258275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2309 12:47:39.258387 ==
2310 12:47:39.258483 [Duty_Offset_Calibration]
2311 12:47:39.261511 B0:3 B1:-1 CA:1
2312 12:47:39.261621
2313 12:47:39.265106 [DutyScan_Calibration_Flow] k_type=0
2314 12:47:39.273556
2315 12:47:39.273676 ==CLK 0==
2316 12:47:39.276647 Final CLK duty delay cell = -4
2317 12:47:39.279883 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2318 12:47:39.283695 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2319 12:47:39.286866 [-4] AVG Duty = 4953%(X100)
2320 12:47:39.286976
2321 12:47:39.289864 CH0 CLK Duty spec in!! Max-Min= 156%
2322 12:47:39.293378 [DutyScan_Calibration_Flow] ====Done====
2323 12:47:39.293490
2324 12:47:39.296848 [DutyScan_Calibration_Flow] k_type=1
2325 12:47:39.311966
2326 12:47:39.312080 ==DQS 0 ==
2327 12:47:39.315607 Final DQS duty delay cell = 0
2328 12:47:39.318727 [0] MAX Duty = 5125%(X100), DQS PI = 42
2329 12:47:39.322192 [0] MIN Duty = 5000%(X100), DQS PI = 12
2330 12:47:39.322276 [0] AVG Duty = 5062%(X100)
2331 12:47:39.325810
2332 12:47:39.325893 ==DQS 1 ==
2333 12:47:39.329170 Final DQS duty delay cell = -4
2334 12:47:39.332094 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2335 12:47:39.335728 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2336 12:47:39.338771 [-4] AVG Duty = 5062%(X100)
2337 12:47:39.338876
2338 12:47:39.342512 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2339 12:47:39.342621
2340 12:47:39.345577 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2341 12:47:39.349282 [DutyScan_Calibration_Flow] ====Done====
2342 12:47:39.349381
2343 12:47:39.352326 [DutyScan_Calibration_Flow] k_type=3
2344 12:47:39.369264
2345 12:47:39.369392 ==DQM 0 ==
2346 12:47:39.372220 Final DQM duty delay cell = 0
2347 12:47:39.375792 [0] MAX Duty = 5000%(X100), DQS PI = 54
2348 12:47:39.378922 [0] MIN Duty = 4906%(X100), DQS PI = 2
2349 12:47:39.379027 [0] AVG Duty = 4953%(X100)
2350 12:47:39.382780
2351 12:47:39.382885 ==DQM 1 ==
2352 12:47:39.385794 Final DQM duty delay cell = 0
2353 12:47:39.389530 [0] MAX Duty = 5124%(X100), DQS PI = 32
2354 12:47:39.392600 [0] MIN Duty = 4969%(X100), DQS PI = 10
2355 12:47:39.392748 [0] AVG Duty = 5046%(X100)
2356 12:47:39.392839
2357 12:47:39.395646 CH0 DQM 0 Duty spec in!! Max-Min= 94%
2358 12:47:39.399170
2359 12:47:39.402762 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2360 12:47:39.406113 [DutyScan_Calibration_Flow] ====Done====
2361 12:47:39.406234
2362 12:47:39.409197 [DutyScan_Calibration_Flow] k_type=2
2363 12:47:39.424930
2364 12:47:39.425036 ==DQ 0 ==
2365 12:47:39.428009 Final DQ duty delay cell = -4
2366 12:47:39.431102 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2367 12:47:39.435093 [-4] MIN Duty = 4875%(X100), DQS PI = 12
2368 12:47:39.438321 [-4] AVG Duty = 4968%(X100)
2369 12:47:39.438447
2370 12:47:39.438541 ==DQ 1 ==
2371 12:47:39.441329 Final DQ duty delay cell = 0
2372 12:47:39.444910 [0] MAX Duty = 5031%(X100), DQS PI = 18
2373 12:47:39.447996 [0] MIN Duty = 4907%(X100), DQS PI = 46
2374 12:47:39.448078 [0] AVG Duty = 4969%(X100)
2375 12:47:39.451822
2376 12:47:39.454869 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2377 12:47:39.454952
2378 12:47:39.458612 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2379 12:47:39.461620 [DutyScan_Calibration_Flow] ====Done====
2380 12:47:39.461739 ==
2381 12:47:39.465093 Dram Type= 6, Freq= 0, CH_1, rank 0
2382 12:47:39.468552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2383 12:47:39.468662 ==
2384 12:47:39.471737 [Duty_Offset_Calibration]
2385 12:47:39.471855 B0:1 B1:1 CA:2
2386 12:47:39.472007
2387 12:47:39.475401 [DutyScan_Calibration_Flow] k_type=0
2388 12:47:39.485021
2389 12:47:39.485116 ==CLK 0==
2390 12:47:39.488171 Final CLK duty delay cell = 0
2391 12:47:39.491925 [0] MAX Duty = 5156%(X100), DQS PI = 24
2392 12:47:39.495023 [0] MIN Duty = 4969%(X100), DQS PI = 40
2393 12:47:39.495125 [0] AVG Duty = 5062%(X100)
2394 12:47:39.498175
2395 12:47:39.498282 CH1 CLK Duty spec in!! Max-Min= 187%
2396 12:47:39.505055 [DutyScan_Calibration_Flow] ====Done====
2397 12:47:39.505160
2398 12:47:39.508124 [DutyScan_Calibration_Flow] k_type=1
2399 12:47:39.524158
2400 12:47:39.524259 ==DQS 0 ==
2401 12:47:39.527566 Final DQS duty delay cell = 0
2402 12:47:39.530974 [0] MAX Duty = 5031%(X100), DQS PI = 18
2403 12:47:39.534461 [0] MIN Duty = 4844%(X100), DQS PI = 48
2404 12:47:39.534569 [0] AVG Duty = 4937%(X100)
2405 12:47:39.537507
2406 12:47:39.537629 ==DQS 1 ==
2407 12:47:39.541181 Final DQS duty delay cell = 0
2408 12:47:39.544344 [0] MAX Duty = 5062%(X100), DQS PI = 36
2409 12:47:39.547862 [0] MIN Duty = 4938%(X100), DQS PI = 0
2410 12:47:39.547974 [0] AVG Duty = 5000%(X100)
2411 12:47:39.548074
2412 12:47:39.551018 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2413 12:47:39.554748
2414 12:47:39.557844 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2415 12:47:39.561511 [DutyScan_Calibration_Flow] ====Done====
2416 12:47:39.561616
2417 12:47:39.564538 [DutyScan_Calibration_Flow] k_type=3
2418 12:47:39.581246
2419 12:47:39.581390 ==DQM 0 ==
2420 12:47:39.584068 Final DQM duty delay cell = 0
2421 12:47:39.587243 [0] MAX Duty = 5093%(X100), DQS PI = 18
2422 12:47:39.590835 [0] MIN Duty = 4875%(X100), DQS PI = 50
2423 12:47:39.590946 [0] AVG Duty = 4984%(X100)
2424 12:47:39.593910
2425 12:47:39.594013 ==DQM 1 ==
2426 12:47:39.597689 Final DQM duty delay cell = 0
2427 12:47:39.600889 [0] MAX Duty = 5156%(X100), DQS PI = 62
2428 12:47:39.603875 [0] MIN Duty = 4938%(X100), DQS PI = 22
2429 12:47:39.603986 [0] AVG Duty = 5047%(X100)
2430 12:47:39.607665
2431 12:47:39.610744 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2432 12:47:39.610945
2433 12:47:39.614405 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2434 12:47:39.617548 [DutyScan_Calibration_Flow] ====Done====
2435 12:47:39.617656
2436 12:47:39.621113 [DutyScan_Calibration_Flow] k_type=2
2437 12:47:41.041433
2438 12:47:41.042462 ==DQ 0 ==
2439 12:47:41.043054 Final DQ duty delay cell = 0
2440 12:47:41.043600 [0] MAX Duty = 5125%(X100), DQS PI = 18
2441 12:47:41.044112 [0] MIN Duty = 4969%(X100), DQS PI = 14
2442 12:47:41.044763 [0] AVG Duty = 5047%(X100)
2443 12:47:41.044865
2444 12:47:41.044982 ==DQ 1 ==
2445 12:47:41.045115 Final DQ duty delay cell = 0
2446 12:47:41.045243 [0] MAX Duty = 5124%(X100), DQS PI = 58
2447 12:47:41.045372 [0] MIN Duty = 5031%(X100), DQS PI = 4
2448 12:47:41.045497 [0] AVG Duty = 5077%(X100)
2449 12:47:41.045628
2450 12:47:41.045755 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2451 12:47:41.045841
2452 12:47:41.045912 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2453 12:47:41.045973 [DutyScan_Calibration_Flow] ====Done====
2454 12:47:41.046063 nWR fixed to 30
2455 12:47:41.046157 [ModeRegInit_LP4] CH0 RK0
2456 12:47:41.046239 [ModeRegInit_LP4] CH0 RK1
2457 12:47:41.046334 [ModeRegInit_LP4] CH1 RK0
2458 12:47:41.046444 [ModeRegInit_LP4] CH1 RK1
2459 12:47:41.046546 match AC timing 7
2460 12:47:41.046651 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2461 12:47:41.046765 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2462 12:47:41.046857 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2463 12:47:41.046963 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2464 12:47:41.047070 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2465 12:47:41.047174 ==
2466 12:47:41.047280 Dram Type= 6, Freq= 0, CH_0, rank 0
2467 12:47:41.047368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2468 12:47:41.047455 ==
2469 12:47:41.047556 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2470 12:47:41.047644 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2471 12:47:41.047737 [CA 0] Center 40 (10~71) winsize 62
2472 12:47:41.047835 [CA 1] Center 39 (9~70) winsize 62
2473 12:47:41.047921 [CA 2] Center 36 (6~67) winsize 62
2474 12:47:41.048004 [CA 3] Center 35 (5~66) winsize 62
2475 12:47:41.048101 [CA 4] Center 34 (4~65) winsize 62
2476 12:47:41.048186 [CA 5] Center 34 (4~64) winsize 61
2477 12:47:41.048269
2478 12:47:41.048377 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2479 12:47:41.048463
2480 12:47:41.048546 [CATrainingPosCal] consider 1 rank data
2481 12:47:41.048643 u2DelayCellTimex100 = 270/100 ps
2482 12:47:41.048746 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2483 12:47:41.048838 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2484 12:47:41.048936 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2485 12:47:41.049023 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2486 12:47:41.049114 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2487 12:47:41.049211 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2488 12:47:41.049296
2489 12:47:41.049381 CA PerBit enable=1, Macro0, CA PI delay=34
2490 12:47:41.049486
2491 12:47:41.049573 [CBTSetCACLKResult] CA Dly = 34
2492 12:47:41.049657 CS Dly: 7 (0~38)
2493 12:47:41.049755 ==
2494 12:47:41.049845 Dram Type= 6, Freq= 0, CH_0, rank 1
2495 12:47:41.049927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2496 12:47:41.050020 ==
2497 12:47:41.050115 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2498 12:47:41.050207 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2499 12:47:41.050299 [CA 0] Center 39 (9~70) winsize 62
2500 12:47:41.050387 [CA 1] Center 39 (9~70) winsize 62
2501 12:47:41.050482 [CA 2] Center 36 (6~67) winsize 62
2502 12:47:41.050575 [CA 3] Center 35 (5~66) winsize 62
2503 12:47:41.050668 [CA 4] Center 34 (4~65) winsize 62
2504 12:47:41.050755 [CA 5] Center 34 (4~64) winsize 61
2505 12:47:41.050840
2506 12:47:41.050939 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2507 12:47:41.051029
2508 12:47:41.051122 [CATrainingPosCal] consider 2 rank data
2509 12:47:41.051211 u2DelayCellTimex100 = 270/100 ps
2510 12:47:41.051299 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2511 12:47:41.051389 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2512 12:47:41.051477 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2513 12:47:41.051566 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2514 12:47:41.051653 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2515 12:47:41.051742 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2516 12:47:41.051828
2517 12:47:41.051913 CA PerBit enable=1, Macro0, CA PI delay=34
2518 12:47:41.051997
2519 12:47:41.052060 [CBTSetCACLKResult] CA Dly = 34
2520 12:47:41.052120 CS Dly: 8 (0~41)
2521 12:47:41.052176
2522 12:47:41.052266 ----->DramcWriteLeveling(PI) begin...
2523 12:47:41.052352 ==
2524 12:47:41.052441 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 12:47:41.052530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 12:47:41.052617 ==
2527 12:47:41.052716 Write leveling (Byte 0): 31 => 31
2528 12:47:41.052805 Write leveling (Byte 1): 29 => 29
2529 12:47:41.052892 DramcWriteLeveling(PI) end<-----
2530 12:47:41.052979
2531 12:47:41.053066 ==
2532 12:47:41.053154 Dram Type= 6, Freq= 0, CH_0, rank 0
2533 12:47:41.053239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 12:47:41.053326 ==
2535 12:47:41.053416 [Gating] SW mode calibration
2536 12:47:41.053503 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2537 12:47:41.053590 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2538 12:47:41.053676 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 12:47:41.053765 0 15 4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
2540 12:47:41.053851 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2541 12:47:41.053937 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 12:47:41.054024 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 12:47:41.054110 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 12:47:41.054197 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 12:47:41.054282 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 12:47:41.054367 1 0 0 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
2547 12:47:41.054454 1 0 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
2548 12:47:41.054540 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 12:47:41.054625 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 12:47:41.054712 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 12:47:41.054797 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 12:47:41.054882 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 12:47:41.054967 1 0 28 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
2554 12:47:41.055062 1 1 0 | B1->B0 | 2424 2a2a | 0 1 | (0 0) (0 0)
2555 12:47:41.055152 1 1 4 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
2556 12:47:41.055439 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 12:47:41.055543 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 12:47:41.055633 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 12:47:41.055719 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 12:47:41.055781 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 12:47:41.055867 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 12:47:41.055955 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2563 12:47:41.056044 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2564 12:47:41.056132 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 12:47:41.056219 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 12:47:41.056308 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 12:47:41.056396 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 12:47:41.056481 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 12:47:41.056568 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 12:47:41.056653 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 12:47:41.056727 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 12:47:41.056792 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 12:47:41.056879 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 12:47:41.056964 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 12:47:41.057054 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 12:47:41.057141 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 12:47:41.057225 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 12:47:41.057314 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2579 12:47:41.057401 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2580 12:47:41.057487 Total UI for P1: 0, mck2ui 16
2581 12:47:41.057573 best dqsien dly found for B0: ( 1, 4, 0)
2582 12:47:41.057658 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 12:47:41.057742 Total UI for P1: 0, mck2ui 16
2584 12:47:41.057831 best dqsien dly found for B1: ( 1, 4, 2)
2585 12:47:41.057917 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2586 12:47:41.058005 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2587 12:47:41.058089
2588 12:47:41.058173 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2589 12:47:41.058264 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2590 12:47:41.058352 [Gating] SW calibration Done
2591 12:47:41.058439 ==
2592 12:47:41.058526 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 12:47:41.058611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 12:47:41.058698 ==
2595 12:47:41.058786 RX Vref Scan: 0
2596 12:47:41.058874
2597 12:47:41.058959 RX Vref 0 -> 0, step: 1
2598 12:47:41.059043
2599 12:47:41.059128 RX Delay -40 -> 252, step: 8
2600 12:47:41.059215 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2601 12:47:41.059302 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2602 12:47:41.059389 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2603 12:47:41.059476 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2604 12:47:41.059566 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2605 12:47:41.059652 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2606 12:47:41.059739 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2607 12:47:41.059826 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2608 12:47:41.059916 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2609 12:47:41.060007 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2610 12:47:41.060094 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2611 12:47:41.060185 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2612 12:47:41.060269 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2613 12:47:41.060365 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2614 12:47:41.060456 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2615 12:47:41.060544 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2616 12:47:41.060630 ==
2617 12:47:41.060735 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 12:47:41.060827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 12:47:41.060913 ==
2620 12:47:41.060999 DQS Delay:
2621 12:47:41.061086 DQS0 = 0, DQS1 = 0
2622 12:47:41.061172 DQM Delay:
2623 12:47:41.061257 DQM0 = 115, DQM1 = 106
2624 12:47:41.061341 DQ Delay:
2625 12:47:41.061417 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2626 12:47:41.061505 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2627 12:47:41.061592 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2628 12:47:41.061678 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =111
2629 12:47:41.061764
2630 12:47:41.061850
2631 12:47:41.061934 ==
2632 12:47:41.062021 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 12:47:41.062109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 12:47:41.062195 ==
2635 12:47:41.062281
2636 12:47:41.062366
2637 12:47:41.062451 TX Vref Scan disable
2638 12:47:41.062536 == TX Byte 0 ==
2639 12:47:41.062626 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2640 12:47:41.062711 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2641 12:47:41.062798 == TX Byte 1 ==
2642 12:47:41.062883 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2643 12:47:41.062970 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2644 12:47:41.063055 ==
2645 12:47:41.063139 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 12:47:41.063229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 12:47:41.063315 ==
2648 12:47:41.063402 TX Vref=22, minBit 1, minWin=25, winSum=416
2649 12:47:41.063494 TX Vref=24, minBit 5, minWin=25, winSum=425
2650 12:47:41.063583 TX Vref=26, minBit 1, minWin=26, winSum=432
2651 12:47:41.063671 TX Vref=28, minBit 0, minWin=26, winSum=429
2652 12:47:41.063757 TX Vref=30, minBit 4, minWin=26, winSum=437
2653 12:47:41.063846 TX Vref=32, minBit 0, minWin=26, winSum=433
2654 12:47:41.063935 [TxChooseVref] Worse bit 4, Min win 26, Win sum 437, Final Vref 30
2655 12:47:41.064021
2656 12:47:41.064106 Final TX Range 1 Vref 30
2657 12:47:41.064190
2658 12:47:41.064273 ==
2659 12:47:41.064360 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 12:47:41.064450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 12:47:41.064541 ==
2662 12:47:41.064629
2663 12:47:41.064722
2664 12:47:41.064809 TX Vref Scan disable
2665 12:47:41.064895 == TX Byte 0 ==
2666 12:47:41.064990 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2667 12:47:41.065081 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2668 12:47:41.065170 == TX Byte 1 ==
2669 12:47:41.065254 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2670 12:47:41.065349 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2671 12:47:41.065437
2672 12:47:41.065524 [DATLAT]
2673 12:47:41.065610 Freq=1200, CH0 RK0
2674 12:47:41.065699
2675 12:47:41.065786 DATLAT Default: 0xd
2676 12:47:41.066060 0, 0xFFFF, sum = 0
2677 12:47:41.066157 1, 0xFFFF, sum = 0
2678 12:47:41.066249 2, 0xFFFF, sum = 0
2679 12:47:41.066339 3, 0xFFFF, sum = 0
2680 12:47:41.066426 4, 0xFFFF, sum = 0
2681 12:47:41.066514 5, 0xFFFF, sum = 0
2682 12:47:41.066602 6, 0xFFFF, sum = 0
2683 12:47:41.066687 7, 0xFFFF, sum = 0
2684 12:47:41.066774 8, 0xFFFF, sum = 0
2685 12:47:41.066866 9, 0xFFFF, sum = 0
2686 12:47:41.066952 10, 0xFFFF, sum = 0
2687 12:47:41.067041 11, 0xFFFF, sum = 0
2688 12:47:41.067128 12, 0x0, sum = 1
2689 12:47:41.067214 13, 0x0, sum = 2
2690 12:47:41.067301 14, 0x0, sum = 3
2691 12:47:41.067389 15, 0x0, sum = 4
2692 12:47:41.067479 best_step = 13
2693 12:47:41.067567
2694 12:47:41.067653 ==
2695 12:47:41.067738 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 12:47:41.067825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 12:47:41.067909 ==
2698 12:47:41.067995 RX Vref Scan: 1
2699 12:47:41.068080
2700 12:47:41.068168 Set Vref Range= 32 -> 127
2701 12:47:41.068255
2702 12:47:41.068340 RX Vref 32 -> 127, step: 1
2703 12:47:41.068425
2704 12:47:41.068510 RX Delay -21 -> 252, step: 4
2705 12:47:41.068596
2706 12:47:41.068690 Set Vref, RX VrefLevel [Byte0]: 32
2707 12:47:41.068781 [Byte1]: 32
2708 12:47:41.068865
2709 12:47:41.068952 Set Vref, RX VrefLevel [Byte0]: 33
2710 12:47:41.069040 [Byte1]: 33
2711 12:47:41.069127
2712 12:47:41.069213 Set Vref, RX VrefLevel [Byte0]: 34
2713 12:47:41.069297 [Byte1]: 34
2714 12:47:41.069386
2715 12:47:41.069472 Set Vref, RX VrefLevel [Byte0]: 35
2716 12:47:41.069556 [Byte1]: 35
2717 12:47:41.069641
2718 12:47:41.069728 Set Vref, RX VrefLevel [Byte0]: 36
2719 12:47:41.069812 [Byte1]: 36
2720 12:47:41.069897
2721 12:47:41.069985 Set Vref, RX VrefLevel [Byte0]: 37
2722 12:47:41.070071 [Byte1]: 37
2723 12:47:41.070157
2724 12:47:41.070240 Set Vref, RX VrefLevel [Byte0]: 38
2725 12:47:41.070330 [Byte1]: 38
2726 12:47:41.070421
2727 12:47:41.070510 Set Vref, RX VrefLevel [Byte0]: 39
2728 12:47:41.070599 [Byte1]: 39
2729 12:47:41.070683
2730 12:47:41.070779 Set Vref, RX VrefLevel [Byte0]: 40
2731 12:47:41.070866 [Byte1]: 40
2732 12:47:41.070952
2733 12:47:41.071040 Set Vref, RX VrefLevel [Byte0]: 41
2734 12:47:41.071125 [Byte1]: 41
2735 12:47:41.071213
2736 12:47:41.071301 Set Vref, RX VrefLevel [Byte0]: 42
2737 12:47:41.071386 [Byte1]: 42
2738 12:47:41.071469
2739 12:47:41.071555 Set Vref, RX VrefLevel [Byte0]: 43
2740 12:47:41.071641 [Byte1]: 43
2741 12:47:41.071725
2742 12:47:41.071785 Set Vref, RX VrefLevel [Byte0]: 44
2743 12:47:41.071844 [Byte1]: 44
2744 12:47:41.071904
2745 12:47:41.071991 Set Vref, RX VrefLevel [Byte0]: 45
2746 12:47:41.072079 [Byte1]: 45
2747 12:47:41.072163
2748 12:47:41.072247 Set Vref, RX VrefLevel [Byte0]: 46
2749 12:47:41.072335 [Byte1]: 46
2750 12:47:41.072420
2751 12:47:41.072503 Set Vref, RX VrefLevel [Byte0]: 47
2752 12:47:41.072594 [Byte1]: 47
2753 12:47:41.072691
2754 12:47:41.072778 Set Vref, RX VrefLevel [Byte0]: 48
2755 12:47:41.072864 [Byte1]: 48
2756 12:47:41.072951
2757 12:47:41.073035 Set Vref, RX VrefLevel [Byte0]: 49
2758 12:47:41.073121 [Byte1]: 49
2759 12:47:41.073207
2760 12:47:41.073296 Set Vref, RX VrefLevel [Byte0]: 50
2761 12:47:41.073385 [Byte1]: 50
2762 12:47:41.073468
2763 12:47:41.073552 Set Vref, RX VrefLevel [Byte0]: 51
2764 12:47:41.073638 [Byte1]: 51
2765 12:47:41.073721
2766 12:47:41.073808 Set Vref, RX VrefLevel [Byte0]: 52
2767 12:47:41.073897 [Byte1]: 52
2768 12:47:41.073984
2769 12:47:41.074070 Set Vref, RX VrefLevel [Byte0]: 53
2770 12:47:41.074155 [Byte1]: 53
2771 12:47:41.074239
2772 12:47:41.074325 Set Vref, RX VrefLevel [Byte0]: 54
2773 12:47:41.074410 [Byte1]: 54
2774 12:47:41.074495
2775 12:47:41.074583 Set Vref, RX VrefLevel [Byte0]: 55
2776 12:47:41.074668 [Byte1]: 55
2777 12:47:41.074753
2778 12:47:41.074847 Set Vref, RX VrefLevel [Byte0]: 56
2779 12:47:41.074933 [Byte1]: 56
2780 12:47:41.075019
2781 12:47:41.075101 Set Vref, RX VrefLevel [Byte0]: 57
2782 12:47:41.075191 [Byte1]: 57
2783 12:47:41.075285
2784 12:47:41.075382 Set Vref, RX VrefLevel [Byte0]: 58
2785 12:47:41.075475 [Byte1]: 58
2786 12:47:41.075564
2787 12:47:41.075656 Set Vref, RX VrefLevel [Byte0]: 59
2788 12:47:41.075744 [Byte1]: 59
2789 12:47:41.075829
2790 12:47:41.075916 Set Vref, RX VrefLevel [Byte0]: 60
2791 12:47:41.076007 [Byte1]: 60
2792 12:47:41.076110
2793 12:47:41.076206 Set Vref, RX VrefLevel [Byte0]: 61
2794 12:47:41.076298 [Byte1]: 61
2795 12:47:41.076384
2796 12:47:41.076471 Set Vref, RX VrefLevel [Byte0]: 62
2797 12:47:41.076557 [Byte1]: 62
2798 12:47:41.076641
2799 12:47:41.076749 Set Vref, RX VrefLevel [Byte0]: 63
2800 12:47:41.076835 [Byte1]: 63
2801 12:47:41.076921
2802 12:47:41.077007 Set Vref, RX VrefLevel [Byte0]: 64
2803 12:47:41.077092 [Byte1]: 64
2804 12:47:41.077179
2805 12:47:41.077264 Set Vref, RX VrefLevel [Byte0]: 65
2806 12:47:41.077352 [Byte1]: 65
2807 12:47:41.077440
2808 12:47:41.077526 Set Vref, RX VrefLevel [Byte0]: 66
2809 12:47:41.077612 [Byte1]: 66
2810 12:47:41.077699
2811 12:47:41.077783 Set Vref, RX VrefLevel [Byte0]: 67
2812 12:47:41.077869 [Byte1]: 67
2813 12:47:41.077953
2814 12:47:41.078036 Set Vref, RX VrefLevel [Byte0]: 68
2815 12:47:41.078124 [Byte1]: 68
2816 12:47:41.078207
2817 12:47:41.078292 Set Vref, RX VrefLevel [Byte0]: 69
2818 12:47:41.078378 [Byte1]: 69
2819 12:47:41.078465
2820 12:47:41.078551 Final RX Vref Byte 0 = 53 to rank0
2821 12:47:41.078635 Final RX Vref Byte 1 = 51 to rank0
2822 12:47:41.078720 Final RX Vref Byte 0 = 53 to rank1
2823 12:47:41.078806 Final RX Vref Byte 1 = 51 to rank1==
2824 12:47:41.078894 Dram Type= 6, Freq= 0, CH_0, rank 0
2825 12:47:41.078981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 12:47:41.079065 ==
2827 12:47:41.079149 DQS Delay:
2828 12:47:41.079235 DQS0 = 0, DQS1 = 0
2829 12:47:41.079321 DQM Delay:
2830 12:47:41.079405 DQM0 = 115, DQM1 = 105
2831 12:47:41.079491 DQ Delay:
2832 12:47:41.079578 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
2833 12:47:41.079665 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =122
2834 12:47:41.079748 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2835 12:47:41.079805 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2836 12:47:41.079861
2837 12:47:41.079915
2838 12:47:41.079996 [DQSOSCAuto] RK0, (LSB)MR18= 0xffee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2839 12:47:41.080084 CH0 RK0: MR19=303, MR18=FFEE
2840 12:47:41.080372 CH0_RK0: MR19=0x303, MR18=0xFFEE, DQSOSC=410, MR23=63, INC=39, DEC=26
2841 12:47:41.080477
2842 12:47:41.080568 ----->DramcWriteLeveling(PI) begin...
2843 12:47:41.080660 ==
2844 12:47:41.080758 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 12:47:41.080847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 12:47:41.080941 ==
2847 12:47:41.081027 Write leveling (Byte 0): 31 => 31
2848 12:47:41.081116 Write leveling (Byte 1): 28 => 28
2849 12:47:41.081203 DramcWriteLeveling(PI) end<-----
2850 12:47:41.081300
2851 12:47:41.081416 ==
2852 12:47:41.081501 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 12:47:41.081586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 12:47:41.081668 ==
2855 12:47:41.081767 [Gating] SW mode calibration
2856 12:47:41.081866 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2857 12:47:41.081955 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2858 12:47:41.082039 0 15 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
2859 12:47:41.082156 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2860 12:47:41.082241 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 12:47:41.082326 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 12:47:41.082412 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 12:47:41.082518 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 12:47:41.082619 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2865 12:47:41.082751 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
2866 12:47:41.082851 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2867 12:47:41.082935 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 12:47:41.083014 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 12:47:41.083089 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 12:47:41.083164 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 12:47:41.083247 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 12:47:41.083331 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2873 12:47:41.083432 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2874 12:47:41.083516 1 1 0 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
2875 12:47:41.083605 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 12:47:41.083691 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 12:47:41.083776 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 12:47:41.083863 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 12:47:41.083951 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 12:47:41.084042 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2881 12:47:41.084127 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2882 12:47:41.084211 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2883 12:47:41.084299 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2884 12:47:41.084383 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 12:47:41.084468 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 12:47:41.084555 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 12:47:41.084642 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 12:47:41.084749 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 12:47:41.084834 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 12:47:41.084917 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 12:47:41.085001 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 12:47:41.085086 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 12:47:41.085169 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 12:47:41.085258 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 12:47:41.085342 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 12:47:41.085441 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 12:47:41.085561 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2898 12:47:41.085659 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2899 12:47:41.085745 Total UI for P1: 0, mck2ui 16
2900 12:47:41.085857 best dqsien dly found for B0: ( 1, 3, 28)
2901 12:47:41.085966 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2902 12:47:41.086053 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 12:47:41.086138 Total UI for P1: 0, mck2ui 16
2904 12:47:41.086227 best dqsien dly found for B1: ( 1, 4, 0)
2905 12:47:41.086315 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2906 12:47:41.086402 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2907 12:47:41.086489
2908 12:47:41.086577 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2909 12:47:41.086662 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2910 12:47:41.086748 [Gating] SW calibration Done
2911 12:47:41.086833 ==
2912 12:47:41.086919 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 12:47:41.087004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 12:47:41.087088 ==
2915 12:47:41.087171 RX Vref Scan: 0
2916 12:47:41.087258
2917 12:47:41.087342 RX Vref 0 -> 0, step: 1
2918 12:47:41.087429
2919 12:47:41.087515 RX Delay -40 -> 252, step: 8
2920 12:47:41.087604 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2921 12:47:41.087688 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2922 12:47:41.087767 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2923 12:47:41.087832 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2924 12:47:41.087916 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2925 12:47:41.087987 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2926 12:47:41.088060 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2927 12:47:41.088146 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2928 12:47:41.088249 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2929 12:47:41.088338 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2930 12:47:41.092617 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2931 12:47:41.095635 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2932 12:47:41.099001 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2933 12:47:41.102301 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2934 12:47:41.105637 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2935 12:47:41.112695 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2936 12:47:41.112838 ==
2937 12:47:41.115745 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 12:47:41.119485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 12:47:41.119620 ==
2940 12:47:41.119730 DQS Delay:
2941 12:47:41.122542 DQS0 = 0, DQS1 = 0
2942 12:47:41.122675 DQM Delay:
2943 12:47:41.126251 DQM0 = 115, DQM1 = 105
2944 12:47:41.126388 DQ Delay:
2945 12:47:41.129390 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2946 12:47:41.132585 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
2947 12:47:41.136269 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =95
2948 12:47:41.139298 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2949 12:47:41.139461
2950 12:47:41.139565
2951 12:47:41.139658 ==
2952 12:47:41.143175 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 12:47:41.146101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 12:47:41.149838 ==
2955 12:47:41.149992
2956 12:47:41.150091
2957 12:47:41.150156 TX Vref Scan disable
2958 12:47:41.152906 == TX Byte 0 ==
2959 12:47:41.156588 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2960 12:47:41.159741 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2961 12:47:41.163153 == TX Byte 1 ==
2962 12:47:41.166775 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2963 12:47:41.169545 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2964 12:47:41.169752 ==
2965 12:47:41.173209 Dram Type= 6, Freq= 0, CH_0, rank 1
2966 12:47:41.179885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2967 12:47:41.180087 ==
2968 12:47:41.191034 TX Vref=22, minBit 0, minWin=26, winSum=424
2969 12:47:41.194291 TX Vref=24, minBit 0, minWin=26, winSum=428
2970 12:47:41.197424 TX Vref=26, minBit 7, minWin=26, winSum=438
2971 12:47:41.201092 TX Vref=28, minBit 0, minWin=27, winSum=437
2972 12:47:41.203968 TX Vref=30, minBit 0, minWin=27, winSum=437
2973 12:47:41.207465 TX Vref=32, minBit 3, minWin=26, winSum=436
2974 12:47:41.214179 [TxChooseVref] Worse bit 0, Min win 27, Win sum 437, Final Vref 28
2975 12:47:41.214293
2976 12:47:41.217727 Final TX Range 1 Vref 28
2977 12:47:41.217867
2978 12:47:41.217985 ==
2979 12:47:41.220983 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 12:47:41.224491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 12:47:41.224626 ==
2982 12:47:41.224761
2983 12:47:41.224875
2984 12:47:41.227986 TX Vref Scan disable
2985 12:47:41.231121 == TX Byte 0 ==
2986 12:47:41.234372 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2987 12:47:41.238134 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2988 12:47:41.241207 == TX Byte 1 ==
2989 12:47:41.244356 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2990 12:47:41.248230 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2991 12:47:41.248393
2992 12:47:41.251153 [DATLAT]
2993 12:47:41.251311 Freq=1200, CH0 RK1
2994 12:47:41.251437
2995 12:47:41.254949 DATLAT Default: 0xd
2996 12:47:41.255158 0, 0xFFFF, sum = 0
2997 12:47:41.257950 1, 0xFFFF, sum = 0
2998 12:47:41.258132 2, 0xFFFF, sum = 0
2999 12:47:41.261802 3, 0xFFFF, sum = 0
3000 12:47:41.262013 4, 0xFFFF, sum = 0
3001 12:47:41.265138 5, 0xFFFF, sum = 0
3002 12:47:41.265348 6, 0xFFFF, sum = 0
3003 12:47:41.268507 7, 0xFFFF, sum = 0
3004 12:47:41.268861 8, 0xFFFF, sum = 0
3005 12:47:41.271555 9, 0xFFFF, sum = 0
3006 12:47:41.271892 10, 0xFFFF, sum = 0
3007 12:47:41.275055 11, 0xFFFF, sum = 0
3008 12:47:41.275366 12, 0x0, sum = 1
3009 12:47:41.278376 13, 0x0, sum = 2
3010 12:47:41.278744 14, 0x0, sum = 3
3011 12:47:41.281968 15, 0x0, sum = 4
3012 12:47:41.282296 best_step = 13
3013 12:47:41.282502
3014 12:47:41.282690 ==
3015 12:47:41.284961 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 12:47:41.288482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 12:47:41.292003 ==
3018 12:47:41.292325 RX Vref Scan: 0
3019 12:47:41.292636
3020 12:47:41.295035 RX Vref 0 -> 0, step: 1
3021 12:47:41.295290
3022 12:47:41.298595 RX Delay -21 -> 252, step: 4
3023 12:47:41.301716 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3024 12:47:41.305420 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3025 12:47:41.308420 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3026 12:47:41.315124 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3027 12:47:41.318819 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3028 12:47:41.321868 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3029 12:47:41.325356 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3030 12:47:41.328834 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3031 12:47:41.332301 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3032 12:47:41.338638 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3033 12:47:41.341786 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3034 12:47:41.345533 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3035 12:47:41.348711 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3036 12:47:41.352406 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3037 12:47:41.359164 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3038 12:47:41.362177 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3039 12:47:41.362555 ==
3040 12:47:41.365870 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 12:47:41.368941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 12:47:41.369267 ==
3043 12:47:41.371987 DQS Delay:
3044 12:47:41.372297 DQS0 = 0, DQS1 = 0
3045 12:47:41.372624 DQM Delay:
3046 12:47:41.375673 DQM0 = 114, DQM1 = 104
3047 12:47:41.376028 DQ Delay:
3048 12:47:41.379431 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3049 12:47:41.382340 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3050 12:47:41.385701 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3051 12:47:41.388989 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3052 12:47:41.389373
3053 12:47:41.392555
3054 12:47:41.399053 [DQSOSCAuto] RK1, (LSB)MR18= 0x4f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3055 12:47:41.402643 CH0 RK1: MR19=403, MR18=4F6
3056 12:47:41.405689 CH0_RK1: MR19=0x403, MR18=0x4F6, DQSOSC=408, MR23=63, INC=39, DEC=26
3057 12:47:41.408772 [RxdqsGatingPostProcess] freq 1200
3058 12:47:41.415418 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3059 12:47:41.418957 best DQS0 dly(2T, 0.5T) = (0, 12)
3060 12:47:41.422127 best DQS1 dly(2T, 0.5T) = (0, 12)
3061 12:47:41.425866 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3062 12:47:41.428993 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3063 12:47:41.432493 best DQS0 dly(2T, 0.5T) = (0, 11)
3064 12:47:41.435610 best DQS1 dly(2T, 0.5T) = (0, 12)
3065 12:47:41.439170 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3066 12:47:41.442260 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3067 12:47:41.442677 Pre-setting of DQS Precalculation
3068 12:47:41.449006 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3069 12:47:41.449361 ==
3070 12:47:41.452752 Dram Type= 6, Freq= 0, CH_1, rank 0
3071 12:47:41.455927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 12:47:41.456302 ==
3073 12:47:41.462871 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3074 12:47:41.468984 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3075 12:47:41.476494 [CA 0] Center 38 (9~68) winsize 60
3076 12:47:41.479856 [CA 1] Center 38 (8~68) winsize 61
3077 12:47:41.483501 [CA 2] Center 35 (5~65) winsize 61
3078 12:47:41.486565 [CA 3] Center 34 (4~65) winsize 62
3079 12:47:41.490234 [CA 4] Center 34 (4~65) winsize 62
3080 12:47:41.493197 [CA 5] Center 33 (3~64) winsize 62
3081 12:47:41.493521
3082 12:47:41.496572 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3083 12:47:41.496937
3084 12:47:41.500183 [CATrainingPosCal] consider 1 rank data
3085 12:47:41.503400 u2DelayCellTimex100 = 270/100 ps
3086 12:47:41.506823 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3087 12:47:41.510382 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3088 12:47:41.513566 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3089 12:47:41.516518 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3090 12:47:41.523616 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3091 12:47:41.526863 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3092 12:47:41.527175
3093 12:47:41.530468 CA PerBit enable=1, Macro0, CA PI delay=33
3094 12:47:41.530789
3095 12:47:41.533611 [CBTSetCACLKResult] CA Dly = 33
3096 12:47:41.533935 CS Dly: 6 (0~37)
3097 12:47:41.534253 ==
3098 12:47:41.537283 Dram Type= 6, Freq= 0, CH_1, rank 1
3099 12:47:41.540322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3100 12:47:41.543455 ==
3101 12:47:41.547259 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3102 12:47:41.553844 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3103 12:47:41.562078 [CA 0] Center 38 (8~68) winsize 61
3104 12:47:41.565264 [CA 1] Center 38 (8~68) winsize 61
3105 12:47:41.568957 [CA 2] Center 34 (4~65) winsize 62
3106 12:47:41.571874 [CA 3] Center 34 (4~65) winsize 62
3107 12:47:41.575539 [CA 4] Center 34 (4~65) winsize 62
3108 12:47:41.578705 [CA 5] Center 33 (3~64) winsize 62
3109 12:47:41.579040
3110 12:47:41.582258 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3111 12:47:41.582622
3112 12:47:41.585368 [CATrainingPosCal] consider 2 rank data
3113 12:47:41.589123 u2DelayCellTimex100 = 270/100 ps
3114 12:47:41.592183 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3115 12:47:41.595310 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3116 12:47:41.599068 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3117 12:47:41.605470 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3118 12:47:41.608791 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3119 12:47:41.612736 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3120 12:47:41.613083
3121 12:47:41.615681 CA PerBit enable=1, Macro0, CA PI delay=33
3122 12:47:41.616030
3123 12:47:41.619179 [CBTSetCACLKResult] CA Dly = 33
3124 12:47:41.619562 CS Dly: 7 (0~40)
3125 12:47:41.619916
3126 12:47:41.622572 ----->DramcWriteLeveling(PI) begin...
3127 12:47:41.622963 ==
3128 12:47:41.625598 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 12:47:41.632912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 12:47:41.633255 ==
3131 12:47:41.635986 Write leveling (Byte 0): 26 => 26
3132 12:47:41.636311 Write leveling (Byte 1): 29 => 29
3133 12:47:41.639020 DramcWriteLeveling(PI) end<-----
3134 12:47:41.639334
3135 12:47:41.639636 ==
3136 12:47:41.642563 Dram Type= 6, Freq= 0, CH_1, rank 0
3137 12:47:41.649622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 12:47:41.650023 ==
3139 12:47:41.652807 [Gating] SW mode calibration
3140 12:47:41.659440 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3141 12:47:41.663062 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3142 12:47:41.666508 0 15 0 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
3143 12:47:41.673102 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 12:47:41.676272 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 12:47:41.679514 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 12:47:41.686485 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3147 12:47:41.689834 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 12:47:41.693043 0 15 24 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
3149 12:47:41.699807 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3150 12:47:41.703003 1 0 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 0)
3151 12:47:41.706732 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 12:47:41.713390 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 12:47:41.716635 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 12:47:41.720079 1 0 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3155 12:47:41.723175 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 12:47:41.730084 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 12:47:41.733288 1 0 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
3158 12:47:41.736949 1 1 0 | B1->B0 | 4343 2f2f | 0 0 | (0 0) (0 0)
3159 12:47:41.743397 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 12:47:41.746858 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 12:47:41.750328 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 12:47:41.757261 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 12:47:41.760453 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 12:47:41.763510 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 12:47:41.770212 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3166 12:47:41.773611 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3167 12:47:41.777116 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 12:47:41.780452 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 12:47:41.787227 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 12:47:41.790534 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 12:47:41.793956 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 12:47:41.800821 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 12:47:41.803841 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 12:47:41.807532 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 12:47:41.814386 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 12:47:41.817428 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 12:47:41.821023 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 12:47:41.827517 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 12:47:41.830594 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 12:47:41.834274 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 12:47:41.837594 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3182 12:47:41.844542 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3183 12:47:41.847612 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 12:47:41.850801 Total UI for P1: 0, mck2ui 16
3185 12:47:41.854347 best dqsien dly found for B0: ( 1, 3, 30)
3186 12:47:41.857960 Total UI for P1: 0, mck2ui 16
3187 12:47:41.861164 best dqsien dly found for B1: ( 1, 4, 0)
3188 12:47:41.864697 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3189 12:47:41.867927 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3190 12:47:41.868189
3191 12:47:41.871018 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3192 12:47:41.874633 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3193 12:47:41.878243 [Gating] SW calibration Done
3194 12:47:41.878636 ==
3195 12:47:41.881319 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 12:47:41.885032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 12:47:41.885290 ==
3198 12:47:41.887756 RX Vref Scan: 0
3199 12:47:41.888067
3200 12:47:41.891029 RX Vref 0 -> 0, step: 1
3201 12:47:41.891356
3202 12:47:41.891641 RX Delay -40 -> 252, step: 8
3203 12:47:41.898233 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3204 12:47:41.901286 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3205 12:47:41.904412 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3206 12:47:41.908192 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3207 12:47:41.911249 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3208 12:47:41.918033 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3209 12:47:41.921201 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3210 12:47:41.924856 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3211 12:47:41.928230 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3212 12:47:41.931442 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3213 12:47:41.935069 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3214 12:47:41.941395 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3215 12:47:41.944638 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3216 12:47:41.948058 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3217 12:47:41.951763 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3218 12:47:41.955267 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3219 12:47:41.958415 ==
3220 12:47:41.962002 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 12:47:41.965088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 12:47:41.965460 ==
3223 12:47:41.965779 DQS Delay:
3224 12:47:41.968573 DQS0 = 0, DQS1 = 0
3225 12:47:41.968888 DQM Delay:
3226 12:47:41.971737 DQM0 = 116, DQM1 = 108
3227 12:47:41.972071 DQ Delay:
3228 12:47:41.974916 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3229 12:47:41.978524 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3230 12:47:41.982079 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3231 12:47:41.985288 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =115
3232 12:47:41.985631
3233 12:47:41.985957
3234 12:47:41.986240 ==
3235 12:47:41.988920 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 12:47:41.991966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 12:47:41.995619 ==
3238 12:47:41.995896
3239 12:47:41.996107
3240 12:47:41.996298 TX Vref Scan disable
3241 12:47:41.998494 == TX Byte 0 ==
3242 12:47:42.002106 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3243 12:47:42.005697 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3244 12:47:42.008916 == TX Byte 1 ==
3245 12:47:42.012066 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3246 12:47:42.015933 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3247 12:47:42.016287 ==
3248 12:47:42.018968 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 12:47:42.025720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 12:47:42.026062 ==
3251 12:47:42.036639 TX Vref=22, minBit 0, minWin=25, winSum=412
3252 12:47:42.039506 TX Vref=24, minBit 1, minWin=25, winSum=415
3253 12:47:42.042732 TX Vref=26, minBit 1, minWin=25, winSum=423
3254 12:47:42.046417 TX Vref=28, minBit 0, minWin=26, winSum=425
3255 12:47:42.050170 TX Vref=30, minBit 1, minWin=26, winSum=427
3256 12:47:42.053100 TX Vref=32, minBit 0, minWin=26, winSum=427
3257 12:47:42.059778 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 30
3258 12:47:42.060065
3259 12:47:42.063107 Final TX Range 1 Vref 30
3260 12:47:42.063365
3261 12:47:42.063569 ==
3262 12:47:42.066877 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 12:47:42.070225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 12:47:42.070575 ==
3265 12:47:42.070885
3266 12:47:42.071191
3267 12:47:42.073303 TX Vref Scan disable
3268 12:47:42.076395 == TX Byte 0 ==
3269 12:47:42.080160 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3270 12:47:42.083642 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3271 12:47:42.086795 == TX Byte 1 ==
3272 12:47:42.089893 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3273 12:47:42.093717 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3274 12:47:42.094072
3275 12:47:42.096891 [DATLAT]
3276 12:47:42.097222 Freq=1200, CH1 RK0
3277 12:47:42.097516
3278 12:47:42.100442 DATLAT Default: 0xd
3279 12:47:42.100761 0, 0xFFFF, sum = 0
3280 12:47:42.103438 1, 0xFFFF, sum = 0
3281 12:47:42.103702 2, 0xFFFF, sum = 0
3282 12:47:42.107185 3, 0xFFFF, sum = 0
3283 12:47:42.107534 4, 0xFFFF, sum = 0
3284 12:47:42.110176 5, 0xFFFF, sum = 0
3285 12:47:42.110491 6, 0xFFFF, sum = 0
3286 12:47:42.113807 7, 0xFFFF, sum = 0
3287 12:47:42.114133 8, 0xFFFF, sum = 0
3288 12:47:42.117123 9, 0xFFFF, sum = 0
3289 12:47:42.117450 10, 0xFFFF, sum = 0
3290 12:47:42.120418 11, 0xFFFF, sum = 0
3291 12:47:42.120793 12, 0x0, sum = 1
3292 12:47:42.124181 13, 0x0, sum = 2
3293 12:47:42.124505 14, 0x0, sum = 3
3294 12:47:42.127346 15, 0x0, sum = 4
3295 12:47:42.127805 best_step = 13
3296 12:47:42.128119
3297 12:47:42.128524 ==
3298 12:47:42.130492 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 12:47:42.134124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 12:47:42.137038 ==
3301 12:47:42.137366 RX Vref Scan: 1
3302 12:47:42.137657
3303 12:47:42.140617 Set Vref Range= 32 -> 127
3304 12:47:42.140954
3305 12:47:42.141244 RX Vref 32 -> 127, step: 1
3306 12:47:42.143863
3307 12:47:42.144170 RX Delay -21 -> 252, step: 4
3308 12:47:42.144446
3309 12:47:42.147481 Set Vref, RX VrefLevel [Byte0]: 32
3310 12:47:42.150513 [Byte1]: 32
3311 12:47:42.154257
3312 12:47:42.154600 Set Vref, RX VrefLevel [Byte0]: 33
3313 12:47:42.158132 [Byte1]: 33
3314 12:47:42.162502
3315 12:47:42.162763 Set Vref, RX VrefLevel [Byte0]: 34
3316 12:47:42.165968 [Byte1]: 34
3317 12:47:42.170524
3318 12:47:42.170787 Set Vref, RX VrefLevel [Byte0]: 35
3319 12:47:42.173970 [Byte1]: 35
3320 12:47:42.178311
3321 12:47:42.178647 Set Vref, RX VrefLevel [Byte0]: 36
3322 12:47:42.181695 [Byte1]: 36
3323 12:47:42.186133
3324 12:47:42.186478 Set Vref, RX VrefLevel [Byte0]: 37
3325 12:47:42.189753 [Byte1]: 37
3326 12:47:42.194042
3327 12:47:42.194319 Set Vref, RX VrefLevel [Byte0]: 38
3328 12:47:42.197873 [Byte1]: 38
3329 12:47:42.202246
3330 12:47:42.202587 Set Vref, RX VrefLevel [Byte0]: 39
3331 12:47:42.205162 [Byte1]: 39
3332 12:47:42.209991
3333 12:47:42.210266 Set Vref, RX VrefLevel [Byte0]: 40
3334 12:47:42.213038 [Byte1]: 40
3335 12:47:42.217893
3336 12:47:42.218127 Set Vref, RX VrefLevel [Byte0]: 41
3337 12:47:42.220973 [Byte1]: 41
3338 12:47:42.225600
3339 12:47:42.225756 Set Vref, RX VrefLevel [Byte0]: 42
3340 12:47:42.229083 [Byte1]: 42
3341 12:47:42.233951
3342 12:47:42.234152 Set Vref, RX VrefLevel [Byte0]: 43
3343 12:47:42.236861 [Byte1]: 43
3344 12:47:42.241708
3345 12:47:42.241811 Set Vref, RX VrefLevel [Byte0]: 44
3346 12:47:42.244866 [Byte1]: 44
3347 12:47:42.249673
3348 12:47:42.249766 Set Vref, RX VrefLevel [Byte0]: 45
3349 12:47:42.252768 [Byte1]: 45
3350 12:47:42.257178
3351 12:47:42.257276 Set Vref, RX VrefLevel [Byte0]: 46
3352 12:47:42.260972 [Byte1]: 46
3353 12:47:42.265610
3354 12:47:42.265737 Set Vref, RX VrefLevel [Byte0]: 47
3355 12:47:42.268526 [Byte1]: 47
3356 12:47:42.273547
3357 12:47:42.273683 Set Vref, RX VrefLevel [Byte0]: 48
3358 12:47:42.276638 [Byte1]: 48
3359 12:47:42.280982
3360 12:47:42.281193 Set Vref, RX VrefLevel [Byte0]: 49
3361 12:47:42.284487 [Byte1]: 49
3362 12:47:42.289203
3363 12:47:42.289411 Set Vref, RX VrefLevel [Byte0]: 50
3364 12:47:42.292399 [Byte1]: 50
3365 12:47:42.297107
3366 12:47:42.297322 Set Vref, RX VrefLevel [Byte0]: 51
3367 12:47:42.300182 [Byte1]: 51
3368 12:47:42.305211
3369 12:47:42.305423 Set Vref, RX VrefLevel [Byte0]: 52
3370 12:47:42.308257 [Byte1]: 52
3371 12:47:42.313207
3372 12:47:42.313570 Set Vref, RX VrefLevel [Byte0]: 53
3373 12:47:42.316275 [Byte1]: 53
3374 12:47:42.320590
3375 12:47:42.320833 Set Vref, RX VrefLevel [Byte0]: 54
3376 12:47:42.324481 [Byte1]: 54
3377 12:47:42.328921
3378 12:47:42.329137 Set Vref, RX VrefLevel [Byte0]: 55
3379 12:47:42.331867 [Byte1]: 55
3380 12:47:42.336574
3381 12:47:42.336841 Set Vref, RX VrefLevel [Byte0]: 56
3382 12:47:42.340104 [Byte1]: 56
3383 12:47:42.344522
3384 12:47:42.344816 Set Vref, RX VrefLevel [Byte0]: 57
3385 12:47:42.348052 [Byte1]: 57
3386 12:47:42.352851
3387 12:47:42.353068 Set Vref, RX VrefLevel [Byte0]: 58
3388 12:47:42.355962 [Byte1]: 58
3389 12:47:42.360407
3390 12:47:42.360619 Set Vref, RX VrefLevel [Byte0]: 59
3391 12:47:42.364089 [Byte1]: 59
3392 12:47:42.368330
3393 12:47:42.368614 Set Vref, RX VrefLevel [Byte0]: 60
3394 12:47:42.371436 [Byte1]: 60
3395 12:47:42.376139
3396 12:47:42.376267 Set Vref, RX VrefLevel [Byte0]: 61
3397 12:47:42.379868 [Byte1]: 61
3398 12:47:42.384171
3399 12:47:42.384256 Set Vref, RX VrefLevel [Byte0]: 62
3400 12:47:42.387342 [Byte1]: 62
3401 12:47:42.392191
3402 12:47:42.392274 Set Vref, RX VrefLevel [Byte0]: 63
3403 12:47:42.395567 [Byte1]: 63
3404 12:47:42.399915
3405 12:47:42.400024 Set Vref, RX VrefLevel [Byte0]: 64
3406 12:47:42.403278 [Byte1]: 64
3407 12:47:42.408084
3408 12:47:42.408223 Set Vref, RX VrefLevel [Byte0]: 65
3409 12:47:42.411201 [Byte1]: 65
3410 12:47:42.415555
3411 12:47:42.415665 Set Vref, RX VrefLevel [Byte0]: 66
3412 12:47:42.419304 [Byte1]: 66
3413 12:47:42.423627
3414 12:47:42.423726 Set Vref, RX VrefLevel [Byte0]: 67
3415 12:47:42.427384 [Byte1]: 67
3416 12:47:42.431890
3417 12:47:42.431972 Set Vref, RX VrefLevel [Byte0]: 68
3418 12:47:42.434758 [Byte1]: 68
3419 12:47:42.439783
3420 12:47:42.439865 Set Vref, RX VrefLevel [Byte0]: 69
3421 12:47:42.442706 [Byte1]: 69
3422 12:47:42.447416
3423 12:47:42.447524 Set Vref, RX VrefLevel [Byte0]: 70
3424 12:47:42.450603 [Byte1]: 70
3425 12:47:42.455705
3426 12:47:42.455887 Final RX Vref Byte 0 = 56 to rank0
3427 12:47:42.458655 Final RX Vref Byte 1 = 54 to rank0
3428 12:47:42.462311 Final RX Vref Byte 0 = 56 to rank1
3429 12:47:42.465345 Final RX Vref Byte 1 = 54 to rank1==
3430 12:47:42.469159 Dram Type= 6, Freq= 0, CH_1, rank 0
3431 12:47:42.472175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3432 12:47:42.475904 ==
3433 12:47:42.475987 DQS Delay:
3434 12:47:42.476093 DQS0 = 0, DQS1 = 0
3435 12:47:42.479012 DQM Delay:
3436 12:47:42.479123 DQM0 = 116, DQM1 = 109
3437 12:47:42.482682 DQ Delay:
3438 12:47:42.485897 DQ0 =118, DQ1 =110, DQ2 =108, DQ3 =114
3439 12:47:42.488950 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3440 12:47:42.492742 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =106
3441 12:47:42.495854 DQ12 =120, DQ13 =114, DQ14 =116, DQ15 =114
3442 12:47:42.495955
3443 12:47:42.496045
3444 12:47:42.502587 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e5, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps
3445 12:47:42.505670 CH1 RK0: MR19=403, MR18=1E5
3446 12:47:42.512493 CH1_RK0: MR19=0x403, MR18=0x1E5, DQSOSC=409, MR23=63, INC=39, DEC=26
3447 12:47:42.512618
3448 12:47:42.515957 ----->DramcWriteLeveling(PI) begin...
3449 12:47:42.516043 ==
3450 12:47:42.519167 Dram Type= 6, Freq= 0, CH_1, rank 1
3451 12:47:42.522746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3452 12:47:42.522867 ==
3453 12:47:42.525959 Write leveling (Byte 0): 27 => 27
3454 12:47:42.529238 Write leveling (Byte 1): 28 => 28
3455 12:47:42.532780 DramcWriteLeveling(PI) end<-----
3456 12:47:42.532862
3457 12:47:42.532927 ==
3458 12:47:42.535860 Dram Type= 6, Freq= 0, CH_1, rank 1
3459 12:47:42.539658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 12:47:42.539756 ==
3461 12:47:42.542996 [Gating] SW mode calibration
3462 12:47:42.549378 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3463 12:47:42.556062 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3464 12:47:42.559376 0 15 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
3465 12:47:42.562605 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 12:47:42.569368 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 12:47:42.572958 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3468 12:47:42.576691 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 12:47:42.582761 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 12:47:42.586544 0 15 24 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (0 1)
3471 12:47:42.590120 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3472 12:47:42.596937 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 12:47:42.600052 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 12:47:42.603104 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 12:47:42.606604 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 12:47:42.613244 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 12:47:42.617156 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3478 12:47:42.620007 1 0 24 | B1->B0 | 2424 3e3e | 0 0 | (0 0) (0 0)
3479 12:47:42.626786 1 0 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3480 12:47:42.630132 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 12:47:42.633761 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 12:47:42.639945 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 12:47:42.643589 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 12:47:42.646800 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 12:47:42.653493 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3486 12:47:42.657190 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3487 12:47:42.660293 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3488 12:47:42.667115 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 12:47:42.670062 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 12:47:42.673505 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 12:47:42.677103 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 12:47:42.683682 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 12:47:42.686799 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 12:47:42.690656 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 12:47:42.697135 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 12:47:42.700229 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 12:47:42.703879 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 12:47:42.710530 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 12:47:42.713699 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 12:47:42.717251 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 12:47:42.724127 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3502 12:47:42.727229 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3503 12:47:42.730764 Total UI for P1: 0, mck2ui 16
3504 12:47:42.733690 best dqsien dly found for B0: ( 1, 3, 20)
3505 12:47:42.737017 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3506 12:47:42.740280 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 12:47:42.743850 Total UI for P1: 0, mck2ui 16
3508 12:47:42.747527 best dqsien dly found for B1: ( 1, 3, 26)
3509 12:47:42.750556 best DQS0 dly(MCK, UI, PI) = (1, 3, 20)
3510 12:47:42.757226 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3511 12:47:42.757311
3512 12:47:42.760400 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 20)
3513 12:47:42.764164 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3514 12:47:42.767301 [Gating] SW calibration Done
3515 12:47:42.767410 ==
3516 12:47:42.770395 Dram Type= 6, Freq= 0, CH_1, rank 1
3517 12:47:42.774022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3518 12:47:42.774131 ==
3519 12:47:42.777169 RX Vref Scan: 0
3520 12:47:42.777269
3521 12:47:42.777360 RX Vref 0 -> 0, step: 1
3522 12:47:42.777448
3523 12:47:42.780272 RX Delay -40 -> 252, step: 8
3524 12:47:42.783867 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3525 12:47:42.787411 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3526 12:47:42.793846 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3527 12:47:42.797249 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3528 12:47:42.800612 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3529 12:47:42.803731 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3530 12:47:42.807014 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3531 12:47:42.813593 iDelay=200, Bit 7, Center 111 (48 ~ 175) 128
3532 12:47:42.817292 iDelay=200, Bit 8, Center 103 (32 ~ 175) 144
3533 12:47:42.820963 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3534 12:47:42.823867 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3535 12:47:42.827041 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3536 12:47:42.833976 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3537 12:47:42.837101 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3538 12:47:42.840759 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3539 12:47:42.843728 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3540 12:47:42.843844 ==
3541 12:47:42.847028 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 12:47:42.853884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 12:47:42.854032 ==
3544 12:47:42.854134 DQS Delay:
3545 12:47:42.854264 DQS0 = 0, DQS1 = 0
3546 12:47:42.857031 DQM Delay:
3547 12:47:42.857140 DQM0 = 114, DQM1 = 111
3548 12:47:42.860627 DQ Delay:
3549 12:47:42.863807 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3550 12:47:42.866887 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =111
3551 12:47:42.870659 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3552 12:47:42.873756 DQ12 =115, DQ13 =123, DQ14 =119, DQ15 =119
3553 12:47:42.873944
3554 12:47:42.874101
3555 12:47:42.874232 ==
3556 12:47:42.877471 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 12:47:42.880478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 12:47:42.880590 ==
3559 12:47:42.884105
3560 12:47:42.884187
3561 12:47:42.884252 TX Vref Scan disable
3562 12:47:42.887132 == TX Byte 0 ==
3563 12:47:42.890138 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3564 12:47:42.893929 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3565 12:47:42.896882 == TX Byte 1 ==
3566 12:47:42.900544 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3567 12:47:42.903773 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3568 12:47:42.903873 ==
3569 12:47:42.906860 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 12:47:42.913935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 12:47:42.914018 ==
3572 12:47:42.924120 TX Vref=22, minBit 2, minWin=25, winSum=419
3573 12:47:42.927368 TX Vref=24, minBit 3, minWin=25, winSum=423
3574 12:47:42.931112 TX Vref=26, minBit 1, minWin=26, winSum=429
3575 12:47:42.934719 TX Vref=28, minBit 0, minWin=26, winSum=432
3576 12:47:42.937549 TX Vref=30, minBit 2, minWin=26, winSum=433
3577 12:47:42.940608 TX Vref=32, minBit 1, minWin=26, winSum=433
3578 12:47:42.947719 [TxChooseVref] Worse bit 2, Min win 26, Win sum 433, Final Vref 30
3579 12:47:42.947827
3580 12:47:42.950738 Final TX Range 1 Vref 30
3581 12:47:42.950822
3582 12:47:42.950887 ==
3583 12:47:42.954136 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 12:47:42.957715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 12:47:42.957803 ==
3586 12:47:42.957911
3587 12:47:42.961068
3588 12:47:42.961151 TX Vref Scan disable
3589 12:47:42.964495 == TX Byte 0 ==
3590 12:47:42.968022 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3591 12:47:42.971069 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3592 12:47:42.974208 == TX Byte 1 ==
3593 12:47:42.977985 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3594 12:47:42.981209 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3595 12:47:42.981297
3596 12:47:42.984378 [DATLAT]
3597 12:47:42.984464 Freq=1200, CH1 RK1
3598 12:47:42.984531
3599 12:47:42.988169 DATLAT Default: 0xd
3600 12:47:42.988256 0, 0xFFFF, sum = 0
3601 12:47:42.991446 1, 0xFFFF, sum = 0
3602 12:47:42.991564 2, 0xFFFF, sum = 0
3603 12:47:42.994299 3, 0xFFFF, sum = 0
3604 12:47:42.994412 4, 0xFFFF, sum = 0
3605 12:47:42.997497 5, 0xFFFF, sum = 0
3606 12:47:42.997602 6, 0xFFFF, sum = 0
3607 12:47:43.001153 7, 0xFFFF, sum = 0
3608 12:47:43.001242 8, 0xFFFF, sum = 0
3609 12:47:43.004253 9, 0xFFFF, sum = 0
3610 12:47:43.004405 10, 0xFFFF, sum = 0
3611 12:47:43.008006 11, 0xFFFF, sum = 0
3612 12:47:43.008095 12, 0x0, sum = 1
3613 12:47:43.011266 13, 0x0, sum = 2
3614 12:47:43.011351 14, 0x0, sum = 3
3615 12:47:43.014298 15, 0x0, sum = 4
3616 12:47:43.014449 best_step = 13
3617 12:47:43.014581
3618 12:47:43.014709 ==
3619 12:47:43.018059 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 12:47:43.024614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 12:47:43.024725 ==
3622 12:47:43.024794 RX Vref Scan: 0
3623 12:47:43.024857
3624 12:47:43.028005 RX Vref 0 -> 0, step: 1
3625 12:47:43.028115
3626 12:47:43.031437 RX Delay -21 -> 252, step: 4
3627 12:47:43.034499 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3628 12:47:43.038051 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3629 12:47:43.044466 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3630 12:47:43.047656 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3631 12:47:43.051560 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3632 12:47:43.054666 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3633 12:47:43.057807 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3634 12:47:43.061320 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3635 12:47:43.068037 iDelay=191, Bit 8, Center 100 (35 ~ 166) 132
3636 12:47:43.071425 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3637 12:47:43.074793 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3638 12:47:43.078167 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3639 12:47:43.081231 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3640 12:47:43.088087 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3641 12:47:43.091050 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3642 12:47:43.094905 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3643 12:47:43.095008 ==
3644 12:47:43.097841 Dram Type= 6, Freq= 0, CH_1, rank 1
3645 12:47:43.101569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3646 12:47:43.101665 ==
3647 12:47:43.104567 DQS Delay:
3648 12:47:43.104651 DQS0 = 0, DQS1 = 0
3649 12:47:43.108053 DQM Delay:
3650 12:47:43.108139 DQM0 = 113, DQM1 = 110
3651 12:47:43.111169 DQ Delay:
3652 12:47:43.114974 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3653 12:47:43.118107 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =110
3654 12:47:43.121198 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3655 12:47:43.124403 DQ12 =114, DQ13 =118, DQ14 =118, DQ15 =120
3656 12:47:43.124518
3657 12:47:43.124613
3658 12:47:43.131127 [DQSOSCAuto] RK1, (LSB)MR18= 0xfc04, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 411 ps
3659 12:47:43.134814 CH1 RK1: MR19=304, MR18=FC04
3660 12:47:43.141695 CH1_RK1: MR19=0x304, MR18=0xFC04, DQSOSC=408, MR23=63, INC=39, DEC=26
3661 12:47:43.144678 [RxdqsGatingPostProcess] freq 1200
3662 12:47:43.151229 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3663 12:47:43.151335 best DQS0 dly(2T, 0.5T) = (0, 11)
3664 12:47:43.154753 best DQS1 dly(2T, 0.5T) = (0, 12)
3665 12:47:43.157960 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3666 12:47:43.161389 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3667 12:47:43.164739 best DQS0 dly(2T, 0.5T) = (0, 11)
3668 12:47:43.167916 best DQS1 dly(2T, 0.5T) = (0, 11)
3669 12:47:43.171568 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3670 12:47:43.174494 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3671 12:47:43.178026 Pre-setting of DQS Precalculation
3672 12:47:43.181805 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3673 12:47:43.191636 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3674 12:47:43.197816 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3675 12:47:43.197913
3676 12:47:43.197978
3677 12:47:43.201544 [Calibration Summary] 2400 Mbps
3678 12:47:43.201661 CH 0, Rank 0
3679 12:47:43.204706 SW Impedance : PASS
3680 12:47:43.204813 DUTY Scan : NO K
3681 12:47:43.208310 ZQ Calibration : PASS
3682 12:47:43.211392 Jitter Meter : NO K
3683 12:47:43.211497 CBT Training : PASS
3684 12:47:43.214808 Write leveling : PASS
3685 12:47:43.218403 RX DQS gating : PASS
3686 12:47:43.218507 RX DQ/DQS(RDDQC) : PASS
3687 12:47:43.221433 TX DQ/DQS : PASS
3688 12:47:43.224454 RX DATLAT : PASS
3689 12:47:43.224557 RX DQ/DQS(Engine): PASS
3690 12:47:43.228182 TX OE : NO K
3691 12:47:43.228308 All Pass.
3692 12:47:43.228399
3693 12:47:43.231323 CH 0, Rank 1
3694 12:47:43.231406 SW Impedance : PASS
3695 12:47:43.234491 DUTY Scan : NO K
3696 12:47:43.238047 ZQ Calibration : PASS
3697 12:47:43.238130 Jitter Meter : NO K
3698 12:47:43.241161 CBT Training : PASS
3699 12:47:43.241243 Write leveling : PASS
3700 12:47:43.244940 RX DQS gating : PASS
3701 12:47:43.248455 RX DQ/DQS(RDDQC) : PASS
3702 12:47:43.248562 TX DQ/DQS : PASS
3703 12:47:43.251326 RX DATLAT : PASS
3704 12:47:43.255075 RX DQ/DQS(Engine): PASS
3705 12:47:43.255159 TX OE : NO K
3706 12:47:43.258161 All Pass.
3707 12:47:43.258244
3708 12:47:43.258312 CH 1, Rank 0
3709 12:47:43.261769 SW Impedance : PASS
3710 12:47:43.261852 DUTY Scan : NO K
3711 12:47:43.265196 ZQ Calibration : PASS
3712 12:47:43.265280 Jitter Meter : NO K
3713 12:47:43.268545 CBT Training : PASS
3714 12:47:43.271607 Write leveling : PASS
3715 12:47:43.271689 RX DQS gating : PASS
3716 12:47:43.274972 RX DQ/DQS(RDDQC) : PASS
3717 12:47:43.278430 TX DQ/DQS : PASS
3718 12:47:43.278516 RX DATLAT : PASS
3719 12:47:43.281594 RX DQ/DQS(Engine): PASS
3720 12:47:43.285518 TX OE : NO K
3721 12:47:43.285603 All Pass.
3722 12:47:43.285668
3723 12:47:43.285728 CH 1, Rank 1
3724 12:47:43.288328 SW Impedance : PASS
3725 12:47:43.291789 DUTY Scan : NO K
3726 12:47:43.291906 ZQ Calibration : PASS
3727 12:47:43.295204 Jitter Meter : NO K
3728 12:47:43.298300 CBT Training : PASS
3729 12:47:43.298388 Write leveling : PASS
3730 12:47:43.301588 RX DQS gating : PASS
3731 12:47:43.305162 RX DQ/DQS(RDDQC) : PASS
3732 12:47:43.305251 TX DQ/DQS : PASS
3733 12:47:43.308457 RX DATLAT : PASS
3734 12:47:43.308558 RX DQ/DQS(Engine): PASS
3735 12:47:43.312348 TX OE : NO K
3736 12:47:43.312498 All Pass.
3737 12:47:43.312600
3738 12:47:43.315285 DramC Write-DBI off
3739 12:47:43.318440 PER_BANK_REFRESH: Hybrid Mode
3740 12:47:43.318549 TX_TRACKING: ON
3741 12:47:43.328949 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3742 12:47:43.331856 [FAST_K] Save calibration result to emmc
3743 12:47:43.335099 dramc_set_vcore_voltage set vcore to 650000
3744 12:47:43.338320 Read voltage for 600, 5
3745 12:47:43.338405 Vio18 = 0
3746 12:47:43.338471 Vcore = 650000
3747 12:47:43.341894 Vdram = 0
3748 12:47:43.342055 Vddq = 0
3749 12:47:43.342248 Vmddr = 0
3750 12:47:43.348891 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3751 12:47:43.352013 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3752 12:47:43.355107 MEM_TYPE=3, freq_sel=19
3753 12:47:43.358562 sv_algorithm_assistance_LP4_1600
3754 12:47:43.361661 ============ PULL DRAM RESETB DOWN ============
3755 12:47:43.365299 ========== PULL DRAM RESETB DOWN end =========
3756 12:47:43.371802 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3757 12:47:43.375406 ===================================
3758 12:47:43.378471 LPDDR4 DRAM CONFIGURATION
3759 12:47:43.378588 ===================================
3760 12:47:43.381911 EX_ROW_EN[0] = 0x0
3761 12:47:43.385492 EX_ROW_EN[1] = 0x0
3762 12:47:43.385617 LP4Y_EN = 0x0
3763 12:47:43.388474 WORK_FSP = 0x0
3764 12:47:43.388586 WL = 0x2
3765 12:47:43.392122 RL = 0x2
3766 12:47:43.392232 BL = 0x2
3767 12:47:43.395444 RPST = 0x0
3768 12:47:43.395561 RD_PRE = 0x0
3769 12:47:43.398496 WR_PRE = 0x1
3770 12:47:43.398601 WR_PST = 0x0
3771 12:47:43.402280 DBI_WR = 0x0
3772 12:47:43.402389 DBI_RD = 0x0
3773 12:47:43.405239 OTF = 0x1
3774 12:47:43.409036 ===================================
3775 12:47:43.412154 ===================================
3776 12:47:43.412270 ANA top config
3777 12:47:43.415328 ===================================
3778 12:47:43.419023 DLL_ASYNC_EN = 0
3779 12:47:43.422159 ALL_SLAVE_EN = 1
3780 12:47:43.425774 NEW_RANK_MODE = 1
3781 12:47:43.425857 DLL_IDLE_MODE = 1
3782 12:47:43.428793 LP45_APHY_COMB_EN = 1
3783 12:47:43.432561 TX_ODT_DIS = 1
3784 12:47:43.435698 NEW_8X_MODE = 1
3785 12:47:43.438775 ===================================
3786 12:47:43.442530 ===================================
3787 12:47:43.442645 data_rate = 1200
3788 12:47:43.445494 CKR = 1
3789 12:47:43.448595 DQ_P2S_RATIO = 8
3790 12:47:43.452513 ===================================
3791 12:47:43.455510 CA_P2S_RATIO = 8
3792 12:47:43.458762 DQ_CA_OPEN = 0
3793 12:47:43.462532 DQ_SEMI_OPEN = 0
3794 12:47:43.462645 CA_SEMI_OPEN = 0
3795 12:47:43.465936 CA_FULL_RATE = 0
3796 12:47:43.469007 DQ_CKDIV4_EN = 1
3797 12:47:43.472615 CA_CKDIV4_EN = 1
3798 12:47:43.475928 CA_PREDIV_EN = 0
3799 12:47:43.478835 PH8_DLY = 0
3800 12:47:43.478921 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3801 12:47:43.482049 DQ_AAMCK_DIV = 4
3802 12:47:43.485628 CA_AAMCK_DIV = 4
3803 12:47:43.488743 CA_ADMCK_DIV = 4
3804 12:47:43.492485 DQ_TRACK_CA_EN = 0
3805 12:47:43.495474 CA_PICK = 600
3806 12:47:43.495566 CA_MCKIO = 600
3807 12:47:43.498825 MCKIO_SEMI = 0
3808 12:47:43.502443 PLL_FREQ = 2288
3809 12:47:43.505507 DQ_UI_PI_RATIO = 32
3810 12:47:43.508883 CA_UI_PI_RATIO = 0
3811 12:47:43.512202 ===================================
3812 12:47:43.515544 ===================================
3813 12:47:43.518751 memory_type:LPDDR4
3814 12:47:43.518859 GP_NUM : 10
3815 12:47:43.522550 SRAM_EN : 1
3816 12:47:43.522658 MD32_EN : 0
3817 12:47:43.525551 ===================================
3818 12:47:43.529229 [ANA_INIT] >>>>>>>>>>>>>>
3819 12:47:43.532832 <<<<<< [CONFIGURE PHASE]: ANA_TX
3820 12:47:43.535982 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3821 12:47:43.539006 ===================================
3822 12:47:43.542927 data_rate = 1200,PCW = 0X5800
3823 12:47:43.545934 ===================================
3824 12:47:43.549026 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3825 12:47:43.552366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3826 12:47:43.559125 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3827 12:47:43.562320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3828 12:47:43.566052 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3829 12:47:43.569263 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3830 12:47:43.572642 [ANA_INIT] flow start
3831 12:47:43.576080 [ANA_INIT] PLL >>>>>>>>
3832 12:47:43.576184 [ANA_INIT] PLL <<<<<<<<
3833 12:47:43.579104 [ANA_INIT] MIDPI >>>>>>>>
3834 12:47:43.582514 [ANA_INIT] MIDPI <<<<<<<<
3835 12:47:43.585759 [ANA_INIT] DLL >>>>>>>>
3836 12:47:43.585874 [ANA_INIT] flow end
3837 12:47:43.589146 ============ LP4 DIFF to SE enter ============
3838 12:47:43.596263 ============ LP4 DIFF to SE exit ============
3839 12:47:43.596348 [ANA_INIT] <<<<<<<<<<<<<
3840 12:47:43.599188 [Flow] Enable top DCM control >>>>>
3841 12:47:43.602824 [Flow] Enable top DCM control <<<<<
3842 12:47:43.605867 Enable DLL master slave shuffle
3843 12:47:43.612543 ==============================================================
3844 12:47:43.612657 Gating Mode config
3845 12:47:43.619122 ==============================================================
3846 12:47:43.619234 Config description:
3847 12:47:43.629481 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3848 12:47:43.636303 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3849 12:47:43.642622 SELPH_MODE 0: By rank 1: By Phase
3850 12:47:43.646405 ==============================================================
3851 12:47:43.649487 GAT_TRACK_EN = 1
3852 12:47:43.653299 RX_GATING_MODE = 2
3853 12:47:43.656231 RX_GATING_TRACK_MODE = 2
3854 12:47:43.659780 SELPH_MODE = 1
3855 12:47:43.662923 PICG_EARLY_EN = 1
3856 12:47:43.666669 VALID_LAT_VALUE = 1
3857 12:47:43.669866 ==============================================================
3858 12:47:43.676217 Enter into Gating configuration >>>>
3859 12:47:43.676336 Exit from Gating configuration <<<<
3860 12:47:43.679678 Enter into DVFS_PRE_config >>>>>
3861 12:47:43.693036 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3862 12:47:43.696658 Exit from DVFS_PRE_config <<<<<
3863 12:47:43.699473 Enter into PICG configuration >>>>
3864 12:47:43.699576 Exit from PICG configuration <<<<
3865 12:47:43.703072 [RX_INPUT] configuration >>>>>
3866 12:47:43.706867 [RX_INPUT] configuration <<<<<
3867 12:47:43.713067 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3868 12:47:43.716167 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3869 12:47:43.723018 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3870 12:47:43.730138 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3871 12:47:43.736289 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3872 12:47:43.743539 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3873 12:47:43.746680 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3874 12:47:43.749788 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3875 12:47:43.753514 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3876 12:47:43.759730 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3877 12:47:43.763195 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3878 12:47:43.766309 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3879 12:47:43.770095 ===================================
3880 12:47:43.773248 LPDDR4 DRAM CONFIGURATION
3881 12:47:43.776482 ===================================
3882 12:47:43.776592 EX_ROW_EN[0] = 0x0
3883 12:47:43.780141 EX_ROW_EN[1] = 0x0
3884 12:47:43.783437 LP4Y_EN = 0x0
3885 12:47:43.783549 WORK_FSP = 0x0
3886 12:47:43.786416 WL = 0x2
3887 12:47:43.786526 RL = 0x2
3888 12:47:43.789985 BL = 0x2
3889 12:47:43.790084 RPST = 0x0
3890 12:47:43.793343 RD_PRE = 0x0
3891 12:47:43.793445 WR_PRE = 0x1
3892 12:47:43.796325 WR_PST = 0x0
3893 12:47:43.796423 DBI_WR = 0x0
3894 12:47:43.799862 DBI_RD = 0x0
3895 12:47:43.799970 OTF = 0x1
3896 12:47:43.803191 ===================================
3897 12:47:43.806795 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3898 12:47:43.813426 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3899 12:47:43.816614 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3900 12:47:43.819810 ===================================
3901 12:47:43.823444 LPDDR4 DRAM CONFIGURATION
3902 12:47:43.827180 ===================================
3903 12:47:43.827285 EX_ROW_EN[0] = 0x10
3904 12:47:43.830141 EX_ROW_EN[1] = 0x0
3905 12:47:43.830244 LP4Y_EN = 0x0
3906 12:47:43.833692 WORK_FSP = 0x0
3907 12:47:43.833792 WL = 0x2
3908 12:47:43.836616 RL = 0x2
3909 12:47:43.836725 BL = 0x2
3910 12:47:43.840478 RPST = 0x0
3911 12:47:43.840577 RD_PRE = 0x0
3912 12:47:43.843630 WR_PRE = 0x1
3913 12:47:43.843731 WR_PST = 0x0
3914 12:47:43.846723 DBI_WR = 0x0
3915 12:47:43.850437 DBI_RD = 0x0
3916 12:47:43.850556 OTF = 0x1
3917 12:47:43.853694 ===================================
3918 12:47:43.859975 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3919 12:47:43.863614 nWR fixed to 30
3920 12:47:43.867151 [ModeRegInit_LP4] CH0 RK0
3921 12:47:43.867254 [ModeRegInit_LP4] CH0 RK1
3922 12:47:43.870310 [ModeRegInit_LP4] CH1 RK0
3923 12:47:43.873430 [ModeRegInit_LP4] CH1 RK1
3924 12:47:43.873534 match AC timing 17
3925 12:47:43.880299 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3926 12:47:43.884079 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3927 12:47:43.887144 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3928 12:47:43.893930 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3929 12:47:43.896931 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3930 12:47:43.897012 ==
3931 12:47:43.900379 Dram Type= 6, Freq= 0, CH_0, rank 0
3932 12:47:43.904185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3933 12:47:43.904263 ==
3934 12:47:43.910620 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3935 12:47:43.917068 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3936 12:47:43.920438 [CA 0] Center 36 (6~67) winsize 62
3937 12:47:43.924075 [CA 1] Center 36 (6~66) winsize 61
3938 12:47:43.926949 [CA 2] Center 34 (4~65) winsize 62
3939 12:47:43.930589 [CA 3] Center 34 (4~64) winsize 61
3940 12:47:43.933591 [CA 4] Center 33 (3~64) winsize 62
3941 12:47:43.937130 [CA 5] Center 33 (3~64) winsize 62
3942 12:47:43.937242
3943 12:47:43.940683 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3944 12:47:43.940765
3945 12:47:43.943697 [CATrainingPosCal] consider 1 rank data
3946 12:47:43.947383 u2DelayCellTimex100 = 270/100 ps
3947 12:47:43.950265 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3948 12:47:43.954018 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3949 12:47:43.957138 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3950 12:47:43.960784 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3951 12:47:43.963912 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3952 12:47:43.967068 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3953 12:47:43.967144
3954 12:47:43.970608 CA PerBit enable=1, Macro0, CA PI delay=33
3955 12:47:43.973759
3956 12:47:43.973841 [CBTSetCACLKResult] CA Dly = 33
3957 12:47:43.976989 CS Dly: 4 (0~35)
3958 12:47:43.977065 ==
3959 12:47:43.980648 Dram Type= 6, Freq= 0, CH_0, rank 1
3960 12:47:43.983745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 12:47:43.983831 ==
3962 12:47:43.990669 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3963 12:47:43.997335 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3964 12:47:44.000535 [CA 0] Center 36 (6~66) winsize 61
3965 12:47:44.004061 [CA 1] Center 35 (5~66) winsize 62
3966 12:47:44.007173 [CA 2] Center 34 (4~65) winsize 62
3967 12:47:44.010846 [CA 3] Center 34 (4~65) winsize 62
3968 12:47:44.013617 [CA 4] Center 33 (3~64) winsize 62
3969 12:47:44.017174 [CA 5] Center 33 (3~64) winsize 62
3970 12:47:44.017254
3971 12:47:44.020674 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3972 12:47:44.020785
3973 12:47:44.023789 [CATrainingPosCal] consider 2 rank data
3974 12:47:44.027152 u2DelayCellTimex100 = 270/100 ps
3975 12:47:44.030518 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3976 12:47:44.033660 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3977 12:47:44.037630 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3978 12:47:44.041035 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3979 12:47:44.044220 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3980 12:47:44.047518 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3981 12:47:44.047627
3982 12:47:44.050562 CA PerBit enable=1, Macro0, CA PI delay=33
3983 12:47:44.054185
3984 12:47:44.054265 [CBTSetCACLKResult] CA Dly = 33
3985 12:47:44.057502 CS Dly: 4 (0~36)
3986 12:47:44.057578
3987 12:47:44.060426 ----->DramcWriteLeveling(PI) begin...
3988 12:47:44.060500 ==
3989 12:47:44.064228 Dram Type= 6, Freq= 0, CH_0, rank 0
3990 12:47:44.067456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3991 12:47:44.067569 ==
3992 12:47:44.070696 Write leveling (Byte 0): 33 => 33
3993 12:47:44.074285 Write leveling (Byte 1): 30 => 30
3994 12:47:44.077770 DramcWriteLeveling(PI) end<-----
3995 12:47:44.077916
3996 12:47:44.078038 ==
3997 12:47:44.080748 Dram Type= 6, Freq= 0, CH_0, rank 0
3998 12:47:44.084312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3999 12:47:44.084466 ==
4000 12:47:44.087546 [Gating] SW mode calibration
4001 12:47:44.094348 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4002 12:47:44.101067 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4003 12:47:44.104403 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4004 12:47:44.107544 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4005 12:47:44.114220 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4006 12:47:44.117401 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4007 12:47:44.120995 0 9 16 | B1->B0 | 3131 2929 | 1 1 | (1 0) (0 0)
4008 12:47:44.127846 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 12:47:44.130986 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 12:47:44.134147 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 12:47:44.140509 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 12:47:44.144048 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 12:47:44.147338 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 12:47:44.154090 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4015 12:47:44.157549 0 10 16 | B1->B0 | 3333 3a3a | 0 1 | (0 0) (0 0)
4016 12:47:44.161089 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 12:47:44.167312 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 12:47:44.170999 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 12:47:44.174223 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 12:47:44.181006 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 12:47:44.184016 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 12:47:44.187520 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 12:47:44.194358 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4024 12:47:44.197495 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4025 12:47:44.200710 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 12:47:44.204383 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 12:47:44.210660 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 12:47:44.214409 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 12:47:44.217507 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 12:47:44.224430 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 12:47:44.227469 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 12:47:44.230964 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 12:47:44.237902 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 12:47:44.240918 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 12:47:44.244521 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 12:47:44.251398 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 12:47:44.254336 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 12:47:44.258085 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 12:47:44.264417 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4040 12:47:44.267784 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 12:47:44.271029 Total UI for P1: 0, mck2ui 16
4042 12:47:44.274266 best dqsien dly found for B0: ( 0, 13, 16)
4043 12:47:44.278240 Total UI for P1: 0, mck2ui 16
4044 12:47:44.281568 best dqsien dly found for B1: ( 0, 13, 16)
4045 12:47:44.284825 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4046 12:47:44.287917 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4047 12:47:44.288010
4048 12:47:44.291259 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4049 12:47:44.294355 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4050 12:47:44.298239 [Gating] SW calibration Done
4051 12:47:44.298342 ==
4052 12:47:44.301449 Dram Type= 6, Freq= 0, CH_0, rank 0
4053 12:47:44.304501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4054 12:47:44.304649 ==
4055 12:47:44.308234 RX Vref Scan: 0
4056 12:47:44.308393
4057 12:47:44.308546 RX Vref 0 -> 0, step: 1
4058 12:47:44.311394
4059 12:47:44.311524 RX Delay -230 -> 252, step: 16
4060 12:47:44.318288 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4061 12:47:44.321338 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4062 12:47:44.324482 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4063 12:47:44.328363 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4064 12:47:44.331581 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4065 12:47:44.338198 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4066 12:47:44.341553 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4067 12:47:44.345018 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4068 12:47:44.348427 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4069 12:47:44.355224 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4070 12:47:44.358168 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4071 12:47:44.361788 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4072 12:47:44.364776 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4073 12:47:44.368416 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4074 12:47:44.375276 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4075 12:47:44.378364 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4076 12:47:44.378610 ==
4077 12:47:44.381527 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 12:47:44.384708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 12:47:44.384899 ==
4080 12:47:44.388151 DQS Delay:
4081 12:47:44.388400 DQS0 = 0, DQS1 = 0
4082 12:47:44.388625 DQM Delay:
4083 12:47:44.391704 DQM0 = 43, DQM1 = 34
4084 12:47:44.391950 DQ Delay:
4085 12:47:44.394948 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4086 12:47:44.398429 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4087 12:47:44.402126 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4088 12:47:44.405172 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =49
4089 12:47:44.405407
4090 12:47:44.405611
4091 12:47:44.405805 ==
4092 12:47:44.408197 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 12:47:44.415050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 12:47:44.415246 ==
4095 12:47:44.415418
4096 12:47:44.415555
4097 12:47:44.415688 TX Vref Scan disable
4098 12:47:44.418797 == TX Byte 0 ==
4099 12:47:44.421993 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4100 12:47:44.425678 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4101 12:47:44.428890 == TX Byte 1 ==
4102 12:47:44.431933 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4103 12:47:44.435698 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4104 12:47:44.438847 ==
4105 12:47:44.442670 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 12:47:44.445495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 12:47:44.445749 ==
4108 12:47:44.446006
4109 12:47:44.446171
4110 12:47:44.449002 TX Vref Scan disable
4111 12:47:44.449195 == TX Byte 0 ==
4112 12:47:44.455699 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4113 12:47:44.459273 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4114 12:47:44.459530 == TX Byte 1 ==
4115 12:47:44.466120 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4116 12:47:44.469085 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4117 12:47:44.469327
4118 12:47:44.469555 [DATLAT]
4119 12:47:44.472153 Freq=600, CH0 RK0
4120 12:47:44.472409
4121 12:47:44.472712 DATLAT Default: 0x9
4122 12:47:44.475838 0, 0xFFFF, sum = 0
4123 12:47:44.476093 1, 0xFFFF, sum = 0
4124 12:47:44.478992 2, 0xFFFF, sum = 0
4125 12:47:44.479174 3, 0xFFFF, sum = 0
4126 12:47:44.482693 4, 0xFFFF, sum = 0
4127 12:47:44.483020 5, 0xFFFF, sum = 0
4128 12:47:44.485941 6, 0xFFFF, sum = 0
4129 12:47:44.486272 7, 0xFFFF, sum = 0
4130 12:47:44.489026 8, 0x0, sum = 1
4131 12:47:44.489343 9, 0x0, sum = 2
4132 12:47:44.492533 10, 0x0, sum = 3
4133 12:47:44.492862 11, 0x0, sum = 4
4134 12:47:44.495660 best_step = 9
4135 12:47:44.495970
4136 12:47:44.496254 ==
4137 12:47:44.498867 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 12:47:44.502397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 12:47:44.502652 ==
4140 12:47:44.505716 RX Vref Scan: 1
4141 12:47:44.505880
4142 12:47:44.506014 RX Vref 0 -> 0, step: 1
4143 12:47:44.506139
4144 12:47:44.508853 RX Delay -195 -> 252, step: 8
4145 12:47:44.509004
4146 12:47:44.511990 Set Vref, RX VrefLevel [Byte0]: 53
4147 12:47:44.515389 [Byte1]: 51
4148 12:47:44.518896
4149 12:47:44.519081 Final RX Vref Byte 0 = 53 to rank0
4150 12:47:44.522529 Final RX Vref Byte 1 = 51 to rank0
4151 12:47:44.526206 Final RX Vref Byte 0 = 53 to rank1
4152 12:47:44.529335 Final RX Vref Byte 1 = 51 to rank1==
4153 12:47:44.532515 Dram Type= 6, Freq= 0, CH_0, rank 0
4154 12:47:44.536218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 12:47:44.539476 ==
4156 12:47:44.539623 DQS Delay:
4157 12:47:44.539751 DQS0 = 0, DQS1 = 0
4158 12:47:44.542520 DQM Delay:
4159 12:47:44.542662 DQM0 = 42, DQM1 = 33
4160 12:47:44.546302 DQ Delay:
4161 12:47:44.546397 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4162 12:47:44.549427 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4163 12:47:44.552509 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4164 12:47:44.555982 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4165 12:47:44.556123
4166 12:47:44.559264
4167 12:47:44.565774 [DQSOSCAuto] RK0, (LSB)MR18= 0x4827, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4168 12:47:44.569656 CH0 RK0: MR19=808, MR18=4827
4169 12:47:44.575945 CH0_RK0: MR19=0x808, MR18=0x4827, DQSOSC=396, MR23=63, INC=167, DEC=111
4170 12:47:44.576047
4171 12:47:44.579132 ----->DramcWriteLeveling(PI) begin...
4172 12:47:44.579218 ==
4173 12:47:44.582843 Dram Type= 6, Freq= 0, CH_0, rank 1
4174 12:47:44.585969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 12:47:44.586056 ==
4176 12:47:44.589777 Write leveling (Byte 0): 31 => 31
4177 12:47:44.592951 Write leveling (Byte 1): 31 => 31
4178 12:47:44.595941 DramcWriteLeveling(PI) end<-----
4179 12:47:44.596024
4180 12:47:44.596089 ==
4181 12:47:44.599498 Dram Type= 6, Freq= 0, CH_0, rank 1
4182 12:47:44.602729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 12:47:44.602814 ==
4184 12:47:44.606425 [Gating] SW mode calibration
4185 12:47:44.612697 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4186 12:47:44.619525 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4187 12:47:44.622949 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4188 12:47:44.626513 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4189 12:47:44.633025 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4190 12:47:44.636025 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
4191 12:47:44.639492 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
4192 12:47:44.646310 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 12:47:44.649487 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 12:47:44.653156 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 12:47:44.659402 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 12:47:44.662574 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 12:47:44.666144 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 12:47:44.673045 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
4199 12:47:44.675773 0 10 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4200 12:47:44.679204 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 12:47:44.682640 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 12:47:44.689156 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 12:47:44.692261 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 12:47:44.696070 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 12:47:44.702300 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 12:47:44.705885 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4207 12:47:44.709107 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 12:47:44.715802 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 12:47:44.718940 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 12:47:44.722054 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 12:47:44.728871 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 12:47:44.732211 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 12:47:44.735809 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 12:47:44.742315 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 12:47:44.745445 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 12:47:44.749014 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 12:47:44.756084 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 12:47:44.759182 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 12:47:44.762345 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 12:47:44.768880 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 12:47:44.772295 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4222 12:47:44.775853 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4223 12:47:44.782568 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4224 12:47:44.782685 Total UI for P1: 0, mck2ui 16
4225 12:47:44.788939 best dqsien dly found for B0: ( 0, 13, 10)
4226 12:47:44.792462 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 12:47:44.795937 Total UI for P1: 0, mck2ui 16
4228 12:47:44.799063 best dqsien dly found for B1: ( 0, 13, 16)
4229 12:47:44.802119 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4230 12:47:44.805909 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4231 12:47:44.806002
4232 12:47:44.809027 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4233 12:47:44.812621 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4234 12:47:44.815624 [Gating] SW calibration Done
4235 12:47:44.815733 ==
4236 12:47:44.819439 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 12:47:44.822717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 12:47:44.822839 ==
4239 12:47:44.825893 RX Vref Scan: 0
4240 12:47:44.825999
4241 12:47:44.829052 RX Vref 0 -> 0, step: 1
4242 12:47:44.829164
4243 12:47:44.829261 RX Delay -230 -> 252, step: 16
4244 12:47:44.835935 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4245 12:47:44.839488 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4246 12:47:44.842754 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4247 12:47:44.846160 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4248 12:47:44.852917 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4249 12:47:44.855902 iDelay=218, Bit 5, Center 33 (-118 ~ 185) 304
4250 12:47:44.859405 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4251 12:47:44.862612 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4252 12:47:44.865770 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4253 12:47:44.872777 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4254 12:47:44.875816 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4255 12:47:44.879460 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4256 12:47:44.882646 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4257 12:47:44.889419 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4258 12:47:44.892708 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4259 12:47:44.896070 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4260 12:47:44.896186 ==
4261 12:47:44.899134 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 12:47:44.902680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 12:47:44.902795 ==
4264 12:47:44.906351 DQS Delay:
4265 12:47:44.906438 DQS0 = 0, DQS1 = 0
4266 12:47:44.909448 DQM Delay:
4267 12:47:44.909573 DQM0 = 43, DQM1 = 35
4268 12:47:44.909689 DQ Delay:
4269 12:47:44.912450 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4270 12:47:44.916090 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4271 12:47:44.919671 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4272 12:47:44.922821 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4273 12:47:44.922929
4274 12:47:44.923025
4275 12:47:44.923118 ==
4276 12:47:44.926001 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 12:47:44.932948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 12:47:44.933044 ==
4279 12:47:44.933115
4280 12:47:44.933177
4281 12:47:44.933236 TX Vref Scan disable
4282 12:47:44.936655 == TX Byte 0 ==
4283 12:47:44.939769 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4284 12:47:44.943650 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4285 12:47:44.946855 == TX Byte 1 ==
4286 12:47:44.949931 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4287 12:47:44.953544 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4288 12:47:44.956676 ==
4289 12:47:44.960384 Dram Type= 6, Freq= 0, CH_0, rank 1
4290 12:47:44.963607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4291 12:47:44.963699 ==
4292 12:47:44.963774
4293 12:47:44.963836
4294 12:47:44.966608 TX Vref Scan disable
4295 12:47:44.966684 == TX Byte 0 ==
4296 12:47:44.973425 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4297 12:47:44.976764 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4298 12:47:44.976886 == TX Byte 1 ==
4299 12:47:44.983549 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4300 12:47:44.986645 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4301 12:47:44.986764
4302 12:47:44.986832 [DATLAT]
4303 12:47:44.990412 Freq=600, CH0 RK1
4304 12:47:44.990499
4305 12:47:44.990583 DATLAT Default: 0x9
4306 12:47:44.993330 0, 0xFFFF, sum = 0
4307 12:47:44.993414 1, 0xFFFF, sum = 0
4308 12:47:44.996774 2, 0xFFFF, sum = 0
4309 12:47:44.996902 3, 0xFFFF, sum = 0
4310 12:47:45.000054 4, 0xFFFF, sum = 0
4311 12:47:45.000175 5, 0xFFFF, sum = 0
4312 12:47:45.003530 6, 0xFFFF, sum = 0
4313 12:47:45.003647 7, 0xFFFF, sum = 0
4314 12:47:45.006650 8, 0x0, sum = 1
4315 12:47:45.006777 9, 0x0, sum = 2
4316 12:47:45.009916 10, 0x0, sum = 3
4317 12:47:45.010030 11, 0x0, sum = 4
4318 12:47:45.013620 best_step = 9
4319 12:47:45.013742
4320 12:47:45.013866 ==
4321 12:47:45.016618 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 12:47:45.020375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 12:47:45.020497 ==
4324 12:47:45.023408 RX Vref Scan: 0
4325 12:47:45.023531
4326 12:47:45.023629 RX Vref 0 -> 0, step: 1
4327 12:47:45.023722
4328 12:47:45.026567 RX Delay -179 -> 252, step: 8
4329 12:47:45.033399 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4330 12:47:45.037258 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4331 12:47:45.040347 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4332 12:47:45.043411 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4333 12:47:45.050268 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4334 12:47:45.053293 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4335 12:47:45.057036 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4336 12:47:45.060122 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4337 12:47:45.063334 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4338 12:47:45.070106 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4339 12:47:45.073325 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4340 12:47:45.077070 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4341 12:47:45.080210 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4342 12:47:45.087143 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4343 12:47:45.090507 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4344 12:47:45.093885 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4345 12:47:45.093998 ==
4346 12:47:45.096913 Dram Type= 6, Freq= 0, CH_0, rank 1
4347 12:47:45.100549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 12:47:45.100679 ==
4349 12:47:45.103508 DQS Delay:
4350 12:47:45.103612 DQS0 = 0, DQS1 = 0
4351 12:47:45.106869 DQM Delay:
4352 12:47:45.106979 DQM0 = 40, DQM1 = 33
4353 12:47:45.107079 DQ Delay:
4354 12:47:45.110571 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4355 12:47:45.113901 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4356 12:47:45.116947 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4357 12:47:45.120311 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4358 12:47:45.120445
4359 12:47:45.120551
4360 12:47:45.130516 [DQSOSCAuto] RK1, (LSB)MR18= 0x492b, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4361 12:47:45.133789 CH0 RK1: MR19=808, MR18=492B
4362 12:47:45.137119 CH0_RK1: MR19=0x808, MR18=0x492B, DQSOSC=396, MR23=63, INC=167, DEC=111
4363 12:47:45.140635 [RxdqsGatingPostProcess] freq 600
4364 12:47:45.147421 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4365 12:47:45.150613 Pre-setting of DQS Precalculation
4366 12:47:45.153917 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4367 12:47:45.154033 ==
4368 12:47:45.157373 Dram Type= 6, Freq= 0, CH_1, rank 0
4369 12:47:45.163732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 12:47:45.163830 ==
4371 12:47:45.167479 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4372 12:47:45.173667 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4373 12:47:45.177393 [CA 0] Center 35 (5~66) winsize 62
4374 12:47:45.180511 [CA 1] Center 35 (5~66) winsize 62
4375 12:47:45.184235 [CA 2] Center 34 (3~65) winsize 63
4376 12:47:45.187187 [CA 3] Center 33 (3~64) winsize 62
4377 12:47:45.190956 [CA 4] Center 34 (3~65) winsize 63
4378 12:47:45.194074 [CA 5] Center 33 (3~64) winsize 62
4379 12:47:45.194186
4380 12:47:45.197179 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4381 12:47:45.197291
4382 12:47:45.200907 [CATrainingPosCal] consider 1 rank data
4383 12:47:45.204011 u2DelayCellTimex100 = 270/100 ps
4384 12:47:45.207655 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4385 12:47:45.210492 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4386 12:47:45.213899 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4387 12:47:45.220867 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4388 12:47:45.223975 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4389 12:47:45.227745 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4390 12:47:45.227824
4391 12:47:45.230807 CA PerBit enable=1, Macro0, CA PI delay=33
4392 12:47:45.230922
4393 12:47:45.234410 [CBTSetCACLKResult] CA Dly = 33
4394 12:47:45.234499 CS Dly: 3 (0~34)
4395 12:47:45.234566 ==
4396 12:47:45.237696 Dram Type= 6, Freq= 0, CH_1, rank 1
4397 12:47:45.244348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 12:47:45.244464 ==
4399 12:47:45.247297 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4400 12:47:45.253967 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4401 12:47:45.257615 [CA 0] Center 35 (5~66) winsize 62
4402 12:47:45.260819 [CA 1] Center 36 (6~66) winsize 61
4403 12:47:45.264481 [CA 2] Center 34 (3~65) winsize 63
4404 12:47:45.267494 [CA 3] Center 34 (3~65) winsize 63
4405 12:47:45.270647 [CA 4] Center 34 (3~65) winsize 63
4406 12:47:45.274346 [CA 5] Center 33 (3~64) winsize 62
4407 12:47:45.274455
4408 12:47:45.277439 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4409 12:47:45.277555
4410 12:47:45.281239 [CATrainingPosCal] consider 2 rank data
4411 12:47:45.284339 u2DelayCellTimex100 = 270/100 ps
4412 12:47:45.288061 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4413 12:47:45.291134 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4414 12:47:45.294060 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4415 12:47:45.300903 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4416 12:47:45.304074 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4417 12:47:45.307732 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4418 12:47:45.307826
4419 12:47:45.310811 CA PerBit enable=1, Macro0, CA PI delay=33
4420 12:47:45.310945
4421 12:47:45.314427 [CBTSetCACLKResult] CA Dly = 33
4422 12:47:45.314504 CS Dly: 4 (0~36)
4423 12:47:45.314576
4424 12:47:45.317558 ----->DramcWriteLeveling(PI) begin...
4425 12:47:45.317672 ==
4426 12:47:45.321056 Dram Type= 6, Freq= 0, CH_1, rank 0
4427 12:47:45.327637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4428 12:47:45.327770 ==
4429 12:47:45.331375 Write leveling (Byte 0): 30 => 30
4430 12:47:45.331493 Write leveling (Byte 1): 31 => 31
4431 12:47:45.334374 DramcWriteLeveling(PI) end<-----
4432 12:47:45.334491
4433 12:47:45.337797 ==
4434 12:47:45.337907 Dram Type= 6, Freq= 0, CH_1, rank 0
4435 12:47:45.344435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4436 12:47:45.344575 ==
4437 12:47:45.347983 [Gating] SW mode calibration
4438 12:47:45.354503 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4439 12:47:45.357883 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4440 12:47:45.364345 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4441 12:47:45.367899 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4442 12:47:45.371096 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4443 12:47:45.377932 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4444 12:47:45.380994 0 9 16 | B1->B0 | 2d2d 2626 | 1 0 | (1 0) (0 0)
4445 12:47:45.384676 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4446 12:47:45.387730 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 12:47:45.394462 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 12:47:45.397936 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 12:47:45.401010 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4450 12:47:45.407815 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 12:47:45.411497 0 10 12 | B1->B0 | 2828 2b2b | 1 1 | (0 0) (0 0)
4452 12:47:45.414654 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4453 12:47:45.421554 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 12:47:45.424511 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 12:47:45.427704 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 12:47:45.434642 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 12:47:45.437947 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 12:47:45.441442 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 12:47:45.447781 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4460 12:47:45.451002 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 12:47:45.454315 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 12:47:45.461698 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 12:47:45.464851 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 12:47:45.467750 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 12:47:45.471158 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 12:47:45.477881 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 12:47:45.481277 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 12:47:45.485039 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 12:47:45.491195 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 12:47:45.494397 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 12:47:45.498131 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 12:47:45.504517 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 12:47:45.507701 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 12:47:45.511461 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 12:47:45.517730 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4476 12:47:45.521263 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 12:47:45.524515 Total UI for P1: 0, mck2ui 16
4478 12:47:45.527640 best dqsien dly found for B0: ( 0, 13, 12)
4479 12:47:45.531303 Total UI for P1: 0, mck2ui 16
4480 12:47:45.534492 best dqsien dly found for B1: ( 0, 13, 14)
4481 12:47:45.538128 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4482 12:47:45.541180 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4483 12:47:45.541268
4484 12:47:45.544600 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4485 12:47:45.547998 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4486 12:47:45.550951 [Gating] SW calibration Done
4487 12:47:45.551042 ==
4488 12:47:45.554449 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 12:47:45.557848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 12:47:45.561033 ==
4491 12:47:45.561131 RX Vref Scan: 0
4492 12:47:45.561228
4493 12:47:45.564874 RX Vref 0 -> 0, step: 1
4494 12:47:45.564989
4495 12:47:45.567626 RX Delay -230 -> 252, step: 16
4496 12:47:45.571339 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4497 12:47:45.574467 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4498 12:47:45.578040 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4499 12:47:45.581644 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4500 12:47:45.587751 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4501 12:47:45.591182 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4502 12:47:45.594648 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4503 12:47:45.597685 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4504 12:47:45.604425 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4505 12:47:45.607928 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4506 12:47:45.611029 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4507 12:47:45.614192 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4508 12:47:45.620977 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4509 12:47:45.624634 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4510 12:47:45.627686 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4511 12:47:45.631305 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4512 12:47:45.631409 ==
4513 12:47:45.634418 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 12:47:45.641238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 12:47:45.641322 ==
4516 12:47:45.641387 DQS Delay:
4517 12:47:45.641451 DQS0 = 0, DQS1 = 0
4518 12:47:45.644705 DQM Delay:
4519 12:47:45.644818 DQM0 = 44, DQM1 = 34
4520 12:47:45.647809 DQ Delay:
4521 12:47:45.651427 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4522 12:47:45.651536 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4523 12:47:45.654381 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4524 12:47:45.657811 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =33
4525 12:47:45.661181
4526 12:47:45.661290
4527 12:47:45.661385 ==
4528 12:47:45.664887 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 12:47:45.667667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 12:47:45.667744 ==
4531 12:47:45.667807
4532 12:47:45.667866
4533 12:47:45.671103 TX Vref Scan disable
4534 12:47:45.671174 == TX Byte 0 ==
4535 12:47:45.677607 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4536 12:47:45.681108 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4537 12:47:45.681219 == TX Byte 1 ==
4538 12:47:45.687941 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4539 12:47:45.691009 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4540 12:47:45.691094 ==
4541 12:47:45.694802 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 12:47:45.698105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 12:47:45.698186 ==
4544 12:47:45.698251
4545 12:47:45.698313
4546 12:47:45.701531 TX Vref Scan disable
4547 12:47:45.704522 == TX Byte 0 ==
4548 12:47:45.707653 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4549 12:47:45.711344 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4550 12:47:45.714851 == TX Byte 1 ==
4551 12:47:45.717889 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4552 12:47:45.721003 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4553 12:47:45.721112
4554 12:47:45.724762 [DATLAT]
4555 12:47:45.724847 Freq=600, CH1 RK0
4556 12:47:45.724916
4557 12:47:45.727758 DATLAT Default: 0x9
4558 12:47:45.727879 0, 0xFFFF, sum = 0
4559 12:47:45.731487 1, 0xFFFF, sum = 0
4560 12:47:45.731599 2, 0xFFFF, sum = 0
4561 12:47:45.734649 3, 0xFFFF, sum = 0
4562 12:47:45.734734 4, 0xFFFF, sum = 0
4563 12:47:45.737756 5, 0xFFFF, sum = 0
4564 12:47:45.737867 6, 0xFFFF, sum = 0
4565 12:47:45.741496 7, 0xFFFF, sum = 0
4566 12:47:45.741583 8, 0x0, sum = 1
4567 12:47:45.744574 9, 0x0, sum = 2
4568 12:47:45.744685 10, 0x0, sum = 3
4569 12:47:45.748182 11, 0x0, sum = 4
4570 12:47:45.748270 best_step = 9
4571 12:47:45.748336
4572 12:47:45.748398 ==
4573 12:47:45.751400 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 12:47:45.754501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 12:47:45.758328 ==
4576 12:47:45.758422 RX Vref Scan: 1
4577 12:47:45.758491
4578 12:47:45.761279 RX Vref 0 -> 0, step: 1
4579 12:47:45.761364
4580 12:47:45.761431 RX Delay -195 -> 252, step: 8
4581 12:47:45.764758
4582 12:47:45.764832 Set Vref, RX VrefLevel [Byte0]: 56
4583 12:47:45.767751 [Byte1]: 54
4584 12:47:45.772842
4585 12:47:45.772955 Final RX Vref Byte 0 = 56 to rank0
4586 12:47:45.776512 Final RX Vref Byte 1 = 54 to rank0
4587 12:47:45.779553 Final RX Vref Byte 0 = 56 to rank1
4588 12:47:45.782857 Final RX Vref Byte 1 = 54 to rank1==
4589 12:47:45.785984 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 12:47:45.792888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 12:47:45.792986 ==
4592 12:47:45.793057 DQS Delay:
4593 12:47:45.796028 DQS0 = 0, DQS1 = 0
4594 12:47:45.796119 DQM Delay:
4595 12:47:45.796187 DQM0 = 41, DQM1 = 33
4596 12:47:45.799748 DQ Delay:
4597 12:47:45.802928 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =44
4598 12:47:45.806099 DQ4 =44, DQ5 =48, DQ6 =52, DQ7 =36
4599 12:47:45.809451 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4600 12:47:45.812786 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4601 12:47:45.812871
4602 12:47:45.812938
4603 12:47:45.819680 [DQSOSCAuto] RK0, (LSB)MR18= 0x490f, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4604 12:47:45.822646 CH1 RK0: MR19=808, MR18=490F
4605 12:47:45.829375 CH1_RK0: MR19=0x808, MR18=0x490F, DQSOSC=396, MR23=63, INC=167, DEC=111
4606 12:47:45.829484
4607 12:47:45.832631 ----->DramcWriteLeveling(PI) begin...
4608 12:47:45.832733 ==
4609 12:47:45.836492 Dram Type= 6, Freq= 0, CH_1, rank 1
4610 12:47:45.839546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 12:47:45.839664 ==
4612 12:47:45.842843 Write leveling (Byte 0): 31 => 31
4613 12:47:45.846435 Write leveling (Byte 1): 30 => 30
4614 12:47:45.849504 DramcWriteLeveling(PI) end<-----
4615 12:47:45.849626
4616 12:47:45.849726 ==
4617 12:47:45.853200 Dram Type= 6, Freq= 0, CH_1, rank 1
4618 12:47:45.856290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 12:47:45.856382 ==
4620 12:47:45.859426 [Gating] SW mode calibration
4621 12:47:45.866414 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4622 12:47:45.873235 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4623 12:47:45.876231 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4624 12:47:45.879575 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4625 12:47:45.886666 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4626 12:47:45.889840 0 9 12 | B1->B0 | 3030 2e2e | 1 0 | (1 1) (0 0)
4627 12:47:45.893383 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4628 12:47:45.900112 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 12:47:45.903010 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 12:47:45.906619 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 12:47:45.913501 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4632 12:47:45.916735 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4633 12:47:45.919730 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4634 12:47:45.923145 0 10 12 | B1->B0 | 2f2f 3939 | 0 0 | (0 0) (0 0)
4635 12:47:45.929834 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 12:47:45.933628 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 12:47:45.936555 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 12:47:45.943477 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 12:47:45.946546 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 12:47:45.950363 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 12:47:45.956365 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 12:47:45.960165 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4643 12:47:45.963267 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 12:47:45.970055 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 12:47:45.973256 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 12:47:45.976980 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 12:47:45.983746 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 12:47:45.986614 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 12:47:45.990019 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 12:47:45.996503 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 12:47:46.000210 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 12:47:46.003780 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 12:47:46.006741 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 12:47:46.013412 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 12:47:46.016621 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 12:47:46.020356 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 12:47:46.026553 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 12:47:46.030230 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 12:47:46.033828 Total UI for P1: 0, mck2ui 16
4660 12:47:47.107949 best dqsien dly found for B0: ( 0, 13, 10)
4661 12:47:47.108222 Total UI for P1: 0, mck2ui 16
4662 12:47:47.108428 best dqsien dly found for B1: ( 0, 13, 10)
4663 12:47:47.108593 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4664 12:47:47.108751 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4665 12:47:47.108895
4666 12:47:47.109039 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4667 12:47:47.109249 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4668 12:47:47.109395 [Gating] SW calibration Done
4669 12:47:47.109530 ==
4670 12:47:47.109672 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 12:47:47.109871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 12:47:47.110020 ==
4673 12:47:47.110167 RX Vref Scan: 0
4674 12:47:47.110312
4675 12:47:47.110455 RX Vref 0 -> 0, step: 1
4676 12:47:47.110647
4677 12:47:47.110795 RX Delay -230 -> 252, step: 16
4678 12:47:47.110954 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4679 12:47:47.111098 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4680 12:47:47.111205 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4681 12:47:47.111308 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4682 12:47:47.111477 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4683 12:47:47.111632 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4684 12:47:47.111785 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4685 12:47:47.111898 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4686 12:47:47.112006 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4687 12:47:47.112113 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4688 12:47:47.112262 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4689 12:47:47.112405 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4690 12:47:47.112601 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4691 12:47:47.112717 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4692 12:47:47.112845 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4693 12:47:47.112949 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4694 12:47:47.113053 ==
4695 12:47:47.113152 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 12:47:47.113249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 12:47:47.113381 ==
4698 12:47:47.113525 DQS Delay:
4699 12:47:47.113620 DQS0 = 0, DQS1 = 0
4700 12:47:47.113758 DQM Delay:
4701 12:47:47.113910 DQM0 = 42, DQM1 = 38
4702 12:47:47.114014 DQ Delay:
4703 12:47:47.114130 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4704 12:47:47.114220 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4705 12:47:47.114324 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =33
4706 12:47:47.114422 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4707 12:47:47.114528
4708 12:47:47.114620
4709 12:47:47.114717 ==
4710 12:47:47.114830 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 12:47:47.114922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 12:47:47.115029 ==
4713 12:47:47.115120
4714 12:47:47.115215
4715 12:47:47.115310 TX Vref Scan disable
4716 12:47:47.115405 == TX Byte 0 ==
4717 12:47:47.115501 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4718 12:47:47.115621 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4719 12:47:47.115715 == TX Byte 1 ==
4720 12:47:47.115805 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4721 12:47:47.115901 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4722 12:47:47.115997 ==
4723 12:47:47.116099 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 12:47:47.116195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 12:47:47.116299 ==
4726 12:47:47.116393
4727 12:47:47.116507
4728 12:47:47.116599 TX Vref Scan disable
4729 12:47:47.116731 == TX Byte 0 ==
4730 12:47:47.116822 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4731 12:47:47.116914 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4732 12:47:47.117016 == TX Byte 1 ==
4733 12:47:47.117109 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4734 12:47:47.117203 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4735 12:47:47.117296
4736 12:47:47.117407 [DATLAT]
4737 12:47:47.117524 Freq=600, CH1 RK1
4738 12:47:47.117633
4739 12:47:47.117718 DATLAT Default: 0x9
4740 12:47:47.117811 0, 0xFFFF, sum = 0
4741 12:47:47.117904 1, 0xFFFF, sum = 0
4742 12:47:47.118015 2, 0xFFFF, sum = 0
4743 12:47:47.118113 3, 0xFFFF, sum = 0
4744 12:47:47.118200 4, 0xFFFF, sum = 0
4745 12:47:47.118308 5, 0xFFFF, sum = 0
4746 12:47:47.118396 6, 0xFFFF, sum = 0
4747 12:47:47.118502 7, 0xFFFF, sum = 0
4748 12:47:47.118627 8, 0x0, sum = 1
4749 12:47:47.118740 9, 0x0, sum = 2
4750 12:47:47.118843 10, 0x0, sum = 3
4751 12:47:47.118934 11, 0x0, sum = 4
4752 12:47:47.119035 best_step = 9
4753 12:47:47.119125
4754 12:47:47.119220 ==
4755 12:47:47.119314 Dram Type= 6, Freq= 0, CH_1, rank 1
4756 12:47:47.119408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4757 12:47:47.119511 ==
4758 12:47:47.119600 RX Vref Scan: 0
4759 12:47:47.119694
4760 12:47:47.119786 RX Vref 0 -> 0, step: 1
4761 12:47:47.119879
4762 12:47:47.119972 RX Delay -195 -> 252, step: 8
4763 12:47:47.120080 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4764 12:47:47.120184 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4765 12:47:47.120284 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4766 12:47:47.120371 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4767 12:47:47.120471 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4768 12:47:47.120578 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4769 12:47:47.120681 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4770 12:47:47.120804 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4771 12:47:47.120899 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4772 12:47:47.121028 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4773 12:47:47.121129 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4774 12:47:47.121226 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4775 12:47:47.121320 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4776 12:47:47.121413 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4777 12:47:47.121513 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4778 12:47:47.121605 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4779 12:47:47.121698 ==
4780 12:47:47.121811 Dram Type= 6, Freq= 0, CH_1, rank 1
4781 12:47:47.121911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4782 12:47:47.122018 ==
4783 12:47:47.122109 DQS Delay:
4784 12:47:47.122208 DQS0 = 0, DQS1 = 0
4785 12:47:47.122305 DQM Delay:
4786 12:47:47.122403 DQM0 = 38, DQM1 = 33
4787 12:47:47.122493 DQ Delay:
4788 12:47:47.122578 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4789 12:47:47.122678 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =32
4790 12:47:47.122802 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4791 12:47:47.122912 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4792 12:47:47.123001
4793 12:47:47.123100
4794 12:47:47.123194 [DQSOSCAuto] RK1, (LSB)MR18= 0x3545, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4795 12:47:47.123288 CH1 RK1: MR19=808, MR18=3545
4796 12:47:47.123391 CH1_RK1: MR19=0x808, MR18=0x3545, DQSOSC=396, MR23=63, INC=167, DEC=111
4797 12:47:47.123481 [RxdqsGatingPostProcess] freq 600
4798 12:47:47.123799 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4799 12:47:47.123942 Pre-setting of DQS Precalculation
4800 12:47:47.124065 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4801 12:47:47.124176 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4802 12:47:47.124283 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4803 12:47:47.124390
4804 12:47:47.124484
4805 12:47:47.124577 [Calibration Summary] 1200 Mbps
4806 12:47:47.124697 CH 0, Rank 0
4807 12:47:47.124809 SW Impedance : PASS
4808 12:47:47.124908 DUTY Scan : NO K
4809 12:47:47.125003 ZQ Calibration : PASS
4810 12:47:47.125105 Jitter Meter : NO K
4811 12:47:47.125223 CBT Training : PASS
4812 12:47:47.125331 Write leveling : PASS
4813 12:47:47.125442 RX DQS gating : PASS
4814 12:47:47.125542 RX DQ/DQS(RDDQC) : PASS
4815 12:47:47.125653 TX DQ/DQS : PASS
4816 12:47:47.125758 RX DATLAT : PASS
4817 12:47:47.125839 RX DQ/DQS(Engine): PASS
4818 12:47:47.125908 TX OE : NO K
4819 12:47:47.125975 All Pass.
4820 12:47:47.126039
4821 12:47:47.126103 CH 0, Rank 1
4822 12:47:47.126167 SW Impedance : PASS
4823 12:47:47.126222 DUTY Scan : NO K
4824 12:47:47.126276 ZQ Calibration : PASS
4825 12:47:47.126344 Jitter Meter : NO K
4826 12:47:47.126400 CBT Training : PASS
4827 12:47:47.126453 Write leveling : PASS
4828 12:47:47.126507 RX DQS gating : PASS
4829 12:47:47.126560 RX DQ/DQS(RDDQC) : PASS
4830 12:47:47.126634 TX DQ/DQS : PASS
4831 12:47:47.126696 RX DATLAT : PASS
4832 12:47:47.126749 RX DQ/DQS(Engine): PASS
4833 12:47:47.126802 TX OE : NO K
4834 12:47:47.126864 All Pass.
4835 12:47:47.126917
4836 12:47:47.126978 CH 1, Rank 0
4837 12:47:47.127032 SW Impedance : PASS
4838 12:47:47.127095 DUTY Scan : NO K
4839 12:47:47.127157 ZQ Calibration : PASS
4840 12:47:47.127210 Jitter Meter : NO K
4841 12:47:47.127270 CBT Training : PASS
4842 12:47:47.127330 Write leveling : PASS
4843 12:47:47.127391 RX DQS gating : PASS
4844 12:47:47.127489 RX DQ/DQS(RDDQC) : PASS
4845 12:47:47.127555 TX DQ/DQS : PASS
4846 12:47:47.127608 RX DATLAT : PASS
4847 12:47:47.127687 RX DQ/DQS(Engine): PASS
4848 12:47:47.127774 TX OE : NO K
4849 12:47:47.127827 All Pass.
4850 12:47:47.127880
4851 12:47:47.127932 CH 1, Rank 1
4852 12:47:47.127985 SW Impedance : PASS
4853 12:47:47.128037 DUTY Scan : NO K
4854 12:47:47.128097 ZQ Calibration : PASS
4855 12:47:47.128159 Jitter Meter : NO K
4856 12:47:47.128212 CBT Training : PASS
4857 12:47:47.128273 Write leveling : PASS
4858 12:47:47.128334 RX DQS gating : PASS
4859 12:47:47.128401 RX DQ/DQS(RDDQC) : PASS
4860 12:47:47.128455 TX DQ/DQS : PASS
4861 12:47:47.128508 RX DATLAT : PASS
4862 12:47:47.128601 RX DQ/DQS(Engine): PASS
4863 12:47:47.128657 TX OE : NO K
4864 12:47:47.128745 All Pass.
4865 12:47:47.128860
4866 12:47:47.128929 DramC Write-DBI off
4867 12:47:47.128982 PER_BANK_REFRESH: Hybrid Mode
4868 12:47:47.129042 TX_TRACKING: ON
4869 12:47:47.129105 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4870 12:47:47.129189 [FAST_K] Save calibration result to emmc
4871 12:47:47.129256 dramc_set_vcore_voltage set vcore to 662500
4872 12:47:47.129311 Read voltage for 933, 3
4873 12:47:47.129371 Vio18 = 0
4874 12:47:47.129425 Vcore = 662500
4875 12:47:47.129477 Vdram = 0
4876 12:47:47.129530 Vddq = 0
4877 12:47:47.129598 Vmddr = 0
4878 12:47:47.129653 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4879 12:47:47.129713 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4880 12:47:47.129767 MEM_TYPE=3, freq_sel=17
4881 12:47:47.129821 sv_algorithm_assistance_LP4_1600
4882 12:47:47.129904 ============ PULL DRAM RESETB DOWN ============
4883 12:47:47.129971 ========== PULL DRAM RESETB DOWN end =========
4884 12:47:47.130024 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4885 12:47:47.130086 ===================================
4886 12:47:47.130156 LPDDR4 DRAM CONFIGURATION
4887 12:47:47.130217 ===================================
4888 12:47:47.130321 EX_ROW_EN[0] = 0x0
4889 12:47:47.130375 EX_ROW_EN[1] = 0x0
4890 12:47:47.130427 LP4Y_EN = 0x0
4891 12:47:47.130480 WORK_FSP = 0x0
4892 12:47:47.130541 WL = 0x3
4893 12:47:47.130594 RL = 0x3
4894 12:47:47.130646 BL = 0x2
4895 12:47:47.130699 RPST = 0x0
4896 12:47:47.130751 RD_PRE = 0x0
4897 12:47:47.130835 WR_PRE = 0x1
4898 12:47:47.130911 WR_PST = 0x0
4899 12:47:47.130963 DBI_WR = 0x0
4900 12:47:47.131022 DBI_RD = 0x0
4901 12:47:47.131091 OTF = 0x1
4902 12:47:47.131158 ===================================
4903 12:47:47.131211 ===================================
4904 12:47:47.131270 ANA top config
4905 12:47:47.131358 ===================================
4906 12:47:47.131412 DLL_ASYNC_EN = 0
4907 12:47:47.131464 ALL_SLAVE_EN = 1
4908 12:47:47.131525 NEW_RANK_MODE = 1
4909 12:47:47.131627 DLL_IDLE_MODE = 1
4910 12:47:47.131682 LP45_APHY_COMB_EN = 1
4911 12:47:47.131734 TX_ODT_DIS = 1
4912 12:47:47.131812 NEW_8X_MODE = 1
4913 12:47:47.131880 ===================================
4914 12:47:47.131933 ===================================
4915 12:47:47.131995 data_rate = 1866
4916 12:47:47.132057 CKR = 1
4917 12:47:47.132113 DQ_P2S_RATIO = 8
4918 12:47:47.132175 ===================================
4919 12:47:47.132229 CA_P2S_RATIO = 8
4920 12:47:47.132295 DQ_CA_OPEN = 0
4921 12:47:47.132391 DQ_SEMI_OPEN = 0
4922 12:47:47.132476 CA_SEMI_OPEN = 0
4923 12:47:47.132559 CA_FULL_RATE = 0
4924 12:47:47.132614 DQ_CKDIV4_EN = 1
4925 12:47:47.132685 CA_CKDIV4_EN = 1
4926 12:47:47.132792 CA_PREDIV_EN = 0
4927 12:47:47.132861 PH8_DLY = 0
4928 12:47:47.132922 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4929 12:47:47.132984 DQ_AAMCK_DIV = 4
4930 12:47:47.133046 CA_AAMCK_DIV = 4
4931 12:47:47.133100 CA_ADMCK_DIV = 4
4932 12:47:47.133153 DQ_TRACK_CA_EN = 0
4933 12:47:47.133213 CA_PICK = 933
4934 12:47:47.133289 CA_MCKIO = 933
4935 12:47:47.133365 MCKIO_SEMI = 0
4936 12:47:47.133420 PLL_FREQ = 3732
4937 12:47:47.133481 DQ_UI_PI_RATIO = 32
4938 12:47:47.133535 CA_UI_PI_RATIO = 0
4939 12:47:47.133594 ===================================
4940 12:47:47.133648 ===================================
4941 12:47:47.133701 memory_type:LPDDR4
4942 12:47:47.133763 GP_NUM : 10
4943 12:47:47.133832 SRAM_EN : 1
4944 12:47:47.133893 MD32_EN : 0
4945 12:47:47.133946 ===================================
4946 12:47:47.134248 [ANA_INIT] >>>>>>>>>>>>>>
4947 12:47:47.134320 <<<<<< [CONFIGURE PHASE]: ANA_TX
4948 12:47:47.134377 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4949 12:47:47.134431 ===================================
4950 12:47:47.134497 data_rate = 1866,PCW = 0X8f00
4951 12:47:47.134582 ===================================
4952 12:47:47.134644 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4953 12:47:47.134698 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4954 12:47:47.134767 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4955 12:47:47.134845 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4956 12:47:47.134913 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4957 12:47:47.134967 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4958 12:47:47.135037 [ANA_INIT] flow start
4959 12:47:47.135091 [ANA_INIT] PLL >>>>>>>>
4960 12:47:47.135171 [ANA_INIT] PLL <<<<<<<<
4961 12:47:47.135233 [ANA_INIT] MIDPI >>>>>>>>
4962 12:47:47.135286 [ANA_INIT] MIDPI <<<<<<<<
4963 12:47:47.135339 [ANA_INIT] DLL >>>>>>>>
4964 12:47:47.135401 [ANA_INIT] flow end
4965 12:47:47.135462 ============ LP4 DIFF to SE enter ============
4966 12:47:47.135517 ============ LP4 DIFF to SE exit ============
4967 12:47:47.135571 [ANA_INIT] <<<<<<<<<<<<<
4968 12:47:47.135624 [Flow] Enable top DCM control >>>>>
4969 12:47:47.135677 [Flow] Enable top DCM control <<<<<
4970 12:47:47.135738 Enable DLL master slave shuffle
4971 12:47:47.135791 ==============================================================
4972 12:47:47.135845 Gating Mode config
4973 12:47:47.135897 ==============================================================
4974 12:47:47.135959 Config description:
4975 12:47:47.136042 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4976 12:47:47.136111 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4977 12:47:47.136177 SELPH_MODE 0: By rank 1: By Phase
4978 12:47:47.136234 ==============================================================
4979 12:47:47.136288 GAT_TRACK_EN = 1
4980 12:47:47.136341 RX_GATING_MODE = 2
4981 12:47:47.136394 RX_GATING_TRACK_MODE = 2
4982 12:47:47.136454 SELPH_MODE = 1
4983 12:47:47.136509 PICG_EARLY_EN = 1
4984 12:47:47.136562 VALID_LAT_VALUE = 1
4985 12:47:47.136615 ==============================================================
4986 12:47:47.136721 Enter into Gating configuration >>>>
4987 12:47:47.136778 Exit from Gating configuration <<<<
4988 12:47:47.136831 Enter into DVFS_PRE_config >>>>>
4989 12:47:47.136884 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4990 12:47:47.136949 Exit from DVFS_PRE_config <<<<<
4991 12:47:47.137003 Enter into PICG configuration >>>>
4992 12:47:47.137056 Exit from PICG configuration <<<<
4993 12:47:47.137136 [RX_INPUT] configuration >>>>>
4994 12:47:47.137204 [RX_INPUT] configuration <<<<<
4995 12:47:47.137268 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4996 12:47:47.137324 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4997 12:47:47.137377 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4998 12:47:47.137440 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4999 12:47:47.137494 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5000 12:47:47.137548 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5001 12:47:47.137601 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5002 12:47:47.137655 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5003 12:47:47.137715 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5004 12:47:47.137769 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5005 12:47:47.137823 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5006 12:47:47.137876 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5007 12:47:47.137946 ===================================
5008 12:47:47.138015 LPDDR4 DRAM CONFIGURATION
5009 12:47:47.138082 ===================================
5010 12:47:47.138134 EX_ROW_EN[0] = 0x0
5011 12:47:47.138195 EX_ROW_EN[1] = 0x0
5012 12:47:47.138249 LP4Y_EN = 0x0
5013 12:47:47.138301 WORK_FSP = 0x0
5014 12:47:47.138353 WL = 0x3
5015 12:47:47.138438 RL = 0x3
5016 12:47:47.138493 BL = 0x2
5017 12:47:47.138547 RPST = 0x0
5018 12:47:47.138599 RD_PRE = 0x0
5019 12:47:47.138659 WR_PRE = 0x1
5020 12:47:47.138713 WR_PST = 0x0
5021 12:47:47.138765 DBI_WR = 0x0
5022 12:47:47.138818 DBI_RD = 0x0
5023 12:47:47.138869 OTF = 0x1
5024 12:47:47.138932 ===================================
5025 12:47:47.138985 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5026 12:47:47.139039 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5027 12:47:47.139091 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5028 12:47:47.139152 ===================================
5029 12:47:47.139207 LPDDR4 DRAM CONFIGURATION
5030 12:47:47.139259 ===================================
5031 12:47:47.139312 EX_ROW_EN[0] = 0x10
5032 12:47:47.139364 EX_ROW_EN[1] = 0x0
5033 12:47:47.139425 LP4Y_EN = 0x0
5034 12:47:47.139478 WORK_FSP = 0x0
5035 12:47:47.139531 WL = 0x3
5036 12:47:47.139584 RL = 0x3
5037 12:47:47.139636 BL = 0x2
5038 12:47:47.139688 RPST = 0x0
5039 12:47:47.139741 RD_PRE = 0x0
5040 12:47:47.139792 WR_PRE = 0x1
5041 12:47:47.139844 WR_PST = 0x0
5042 12:47:47.139897 DBI_WR = 0x0
5043 12:47:47.139965 DBI_RD = 0x0
5044 12:47:47.140019 OTF = 0x1
5045 12:47:47.140072 ===================================
5046 12:47:47.140133 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5047 12:47:47.140188 nWR fixed to 30
5048 12:47:47.140242 [ModeRegInit_LP4] CH0 RK0
5049 12:47:47.140294 [ModeRegInit_LP4] CH0 RK1
5050 12:47:47.140346 [ModeRegInit_LP4] CH1 RK0
5051 12:47:47.140407 [ModeRegInit_LP4] CH1 RK1
5052 12:47:47.140460 match AC timing 9
5053 12:47:47.140513 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5054 12:47:47.140799 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5055 12:47:47.140883 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5056 12:47:47.140954 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5057 12:47:47.141008 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5058 12:47:47.141063 ==
5059 12:47:47.141166 Dram Type= 6, Freq= 0, CH_0, rank 0
5060 12:47:47.141220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5061 12:47:47.141275 ==
5062 12:47:47.141328 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5063 12:47:47.141391 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5064 12:47:47.141473 [CA 0] Center 38 (8~69) winsize 62
5065 12:47:47.141526 [CA 1] Center 38 (7~69) winsize 63
5066 12:47:47.144358 [CA 2] Center 35 (5~66) winsize 62
5067 12:47:47.147517 [CA 3] Center 35 (5~65) winsize 61
5068 12:47:47.150706 [CA 4] Center 34 (4~64) winsize 61
5069 12:47:47.154473 [CA 5] Center 34 (4~64) winsize 61
5070 12:47:47.154554
5071 12:47:47.157504 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5072 12:47:47.157593
5073 12:47:47.160767 [CATrainingPosCal] consider 1 rank data
5074 12:47:47.164130 u2DelayCellTimex100 = 270/100 ps
5075 12:47:47.167243 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5076 12:47:47.171001 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5077 12:47:47.174099 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5078 12:47:47.177661 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5079 12:47:47.180474 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5080 12:47:47.184170 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5081 12:47:47.184285
5082 12:47:47.187380 CA PerBit enable=1, Macro0, CA PI delay=34
5083 12:47:47.190787
5084 12:47:47.190944 [CBTSetCACLKResult] CA Dly = 34
5085 12:47:47.194114 CS Dly: 6 (0~37)
5086 12:47:47.194206 ==
5087 12:47:47.197466 Dram Type= 6, Freq= 0, CH_0, rank 1
5088 12:47:47.200888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 12:47:47.201016 ==
5090 12:47:47.207607 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5091 12:47:47.214091 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5092 12:47:47.217282 [CA 0] Center 38 (7~69) winsize 63
5093 12:47:47.220871 [CA 1] Center 38 (7~69) winsize 63
5094 12:47:47.224521 [CA 2] Center 35 (5~66) winsize 62
5095 12:47:47.227623 [CA 3] Center 35 (4~66) winsize 63
5096 12:47:47.231373 [CA 4] Center 34 (3~65) winsize 63
5097 12:47:47.231477 [CA 5] Center 33 (3~64) winsize 62
5098 12:47:47.234273
5099 12:47:47.237932 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5100 12:47:47.238036
5101 12:47:47.241040 [CATrainingPosCal] consider 2 rank data
5102 12:47:47.243994 u2DelayCellTimex100 = 270/100 ps
5103 12:47:47.247495 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5104 12:47:47.250633 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5105 12:47:47.254341 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5106 12:47:47.257259 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5107 12:47:47.261121 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5108 12:47:47.264347 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5109 12:47:47.264466
5110 12:47:47.267453 CA PerBit enable=1, Macro0, CA PI delay=34
5111 12:47:47.267552
5112 12:47:47.271100 [CBTSetCACLKResult] CA Dly = 34
5113 12:47:47.274248 CS Dly: 7 (0~39)
5114 12:47:47.274339
5115 12:47:47.277353 ----->DramcWriteLeveling(PI) begin...
5116 12:47:47.277440 ==
5117 12:47:47.281062 Dram Type= 6, Freq= 0, CH_0, rank 0
5118 12:47:47.284194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5119 12:47:47.284306 ==
5120 12:47:47.287613 Write leveling (Byte 0): 31 => 31
5121 12:47:47.290676 Write leveling (Byte 1): 30 => 30
5122 12:47:47.294016 DramcWriteLeveling(PI) end<-----
5123 12:47:47.294117
5124 12:47:47.294183 ==
5125 12:47:47.297389 Dram Type= 6, Freq= 0, CH_0, rank 0
5126 12:47:47.300742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5127 12:47:47.300828 ==
5128 12:47:47.304000 [Gating] SW mode calibration
5129 12:47:47.310619 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5130 12:47:47.317538 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5131 12:47:47.321171 0 14 0 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5132 12:47:47.327171 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5133 12:47:47.331099 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 12:47:47.334016 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 12:47:47.340877 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 12:47:47.344299 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 12:47:47.347674 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 12:47:47.350680 0 14 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5139 12:47:47.357562 0 15 0 | B1->B0 | 3232 2b2b | 1 1 | (1 1) (1 1)
5140 12:47:47.360691 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
5141 12:47:47.364464 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 12:47:47.370749 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 12:47:47.374497 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 12:47:47.377625 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 12:47:47.384414 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 12:47:47.387677 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5147 12:47:47.390834 1 0 0 | B1->B0 | 3131 3c3c | 0 0 | (0 0) (0 0)
5148 12:47:47.397687 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5149 12:47:47.400804 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 12:47:47.404398 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 12:47:47.411055 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 12:47:47.414162 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 12:47:47.417815 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 12:47:47.421029 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 12:47:47.427572 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5156 12:47:47.431203 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5157 12:47:47.434727 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 12:47:47.441016 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 12:47:47.444775 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 12:47:47.447791 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 12:47:47.454145 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 12:47:47.457918 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 12:47:47.461045 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 12:47:47.467903 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 12:47:47.471114 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 12:47:47.474801 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 12:47:47.480922 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 12:47:47.484688 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 12:47:47.487817 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 12:47:47.494808 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 12:47:47.497725 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5172 12:47:47.501427 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5173 12:47:47.504427 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 12:47:47.507873 Total UI for P1: 0, mck2ui 16
5175 12:47:47.511062 best dqsien dly found for B0: ( 1, 3, 2)
5176 12:47:47.514770 Total UI for P1: 0, mck2ui 16
5177 12:47:47.517847 best dqsien dly found for B1: ( 1, 3, 2)
5178 12:47:47.520971 best DQS0 dly(MCK, UI, PI) = (1, 3, 2)
5179 12:47:47.524445 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5180 12:47:47.524582
5181 12:47:47.531442 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 2)
5182 12:47:47.534721 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5183 12:47:47.534811 [Gating] SW calibration Done
5184 12:47:47.538012 ==
5185 12:47:47.538091 Dram Type= 6, Freq= 0, CH_0, rank 0
5186 12:47:47.544715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5187 12:47:47.544836 ==
5188 12:47:47.544927 RX Vref Scan: 0
5189 12:47:47.545041
5190 12:47:47.547777 RX Vref 0 -> 0, step: 1
5191 12:47:47.547854
5192 12:47:47.551323 RX Delay -80 -> 252, step: 8
5193 12:47:47.554532 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5194 12:47:47.558225 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5195 12:47:47.561296 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5196 12:47:47.564719 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5197 12:47:47.571262 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5198 12:47:47.574973 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5199 12:47:47.578150 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5200 12:47:47.581775 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5201 12:47:47.584944 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5202 12:47:47.588111 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5203 12:47:47.594917 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5204 12:47:47.598003 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5205 12:47:47.601801 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5206 12:47:47.604874 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5207 12:47:47.608037 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5208 12:47:47.611625 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5209 12:47:47.614976 ==
5210 12:47:47.618074 Dram Type= 6, Freq= 0, CH_0, rank 0
5211 12:47:47.621747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5212 12:47:47.621873 ==
5213 12:47:47.621988 DQS Delay:
5214 12:47:47.624872 DQS0 = 0, DQS1 = 0
5215 12:47:47.624989 DQM Delay:
5216 12:47:47.628617 DQM0 = 96, DQM1 = 87
5217 12:47:47.628741 DQ Delay:
5218 12:47:47.631634 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5219 12:47:47.634714 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5220 12:47:47.638048 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5221 12:47:47.641580 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5222 12:47:47.641692
5223 12:47:47.641792
5224 12:47:47.641886 ==
5225 12:47:47.645256 Dram Type= 6, Freq= 0, CH_0, rank 0
5226 12:47:47.648251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5227 12:47:47.648353 ==
5228 12:47:47.648445
5229 12:47:47.648539
5230 12:47:47.651863 TX Vref Scan disable
5231 12:47:47.655416 == TX Byte 0 ==
5232 12:47:47.658571 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5233 12:47:47.662113 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5234 12:47:47.665178 == TX Byte 1 ==
5235 12:47:47.668401 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5236 12:47:47.671860 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5237 12:47:47.671973 ==
5238 12:47:47.675263 Dram Type= 6, Freq= 0, CH_0, rank 0
5239 12:47:47.678645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5240 12:47:47.678753 ==
5241 12:47:47.681883
5242 12:47:47.681996
5243 12:47:47.682065 TX Vref Scan disable
5244 12:47:47.685312 == TX Byte 0 ==
5245 12:47:47.688392 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5246 12:47:47.692184 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5247 12:47:47.695164 == TX Byte 1 ==
5248 12:47:47.698806 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5249 12:47:47.701926 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5250 12:47:47.705488
5251 12:47:47.705604 [DATLAT]
5252 12:47:47.705702 Freq=933, CH0 RK0
5253 12:47:47.705795
5254 12:47:47.708568 DATLAT Default: 0xd
5255 12:47:47.708673 0, 0xFFFF, sum = 0
5256 12:47:47.711807 1, 0xFFFF, sum = 0
5257 12:47:47.711910 2, 0xFFFF, sum = 0
5258 12:47:47.715637 3, 0xFFFF, sum = 0
5259 12:47:47.715749 4, 0xFFFF, sum = 0
5260 12:47:47.718763 5, 0xFFFF, sum = 0
5261 12:47:47.718868 6, 0xFFFF, sum = 0
5262 12:47:47.722268 7, 0xFFFF, sum = 0
5263 12:47:47.722376 8, 0xFFFF, sum = 0
5264 12:47:47.725691 9, 0xFFFF, sum = 0
5265 12:47:47.725800 10, 0x0, sum = 1
5266 12:47:47.728927 11, 0x0, sum = 2
5267 12:47:47.729045 12, 0x0, sum = 3
5268 12:47:47.731820 13, 0x0, sum = 4
5269 12:47:47.731935 best_step = 11
5270 12:47:47.732035
5271 12:47:47.732131 ==
5272 12:47:47.735598 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 12:47:47.741783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 12:47:47.741898 ==
5275 12:47:47.741998 RX Vref Scan: 1
5276 12:47:47.742104
5277 12:47:47.745343 RX Vref 0 -> 0, step: 1
5278 12:47:47.745462
5279 12:47:47.748626 RX Delay -61 -> 252, step: 4
5280 12:47:47.748752
5281 12:47:47.752021 Set Vref, RX VrefLevel [Byte0]: 53
5282 12:47:47.755583 [Byte1]: 51
5283 12:47:47.755709
5284 12:47:47.758688 Final RX Vref Byte 0 = 53 to rank0
5285 12:47:47.762213 Final RX Vref Byte 1 = 51 to rank0
5286 12:47:47.765274 Final RX Vref Byte 0 = 53 to rank1
5287 12:47:47.768833 Final RX Vref Byte 1 = 51 to rank1==
5288 12:47:47.771859 Dram Type= 6, Freq= 0, CH_0, rank 0
5289 12:47:47.775649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 12:47:47.775770 ==
5291 12:47:47.778801 DQS Delay:
5292 12:47:47.778927 DQS0 = 0, DQS1 = 0
5293 12:47:47.779027 DQM Delay:
5294 12:47:47.781744 DQM0 = 96, DQM1 = 88
5295 12:47:47.781850 DQ Delay:
5296 12:47:47.785301 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5297 12:47:47.788660 DQ4 =98, DQ5 =84, DQ6 =106, DQ7 =104
5298 12:47:47.791893 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =80
5299 12:47:47.795569 DQ12 =96, DQ13 =90, DQ14 =100, DQ15 =100
5300 12:47:47.795695
5301 12:47:47.795802
5302 12:47:47.805758 [DQSOSCAuto] RK0, (LSB)MR18= 0x1601, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5303 12:47:47.808689 CH0 RK0: MR19=505, MR18=1601
5304 12:47:47.811912 CH0_RK0: MR19=0x505, MR18=0x1601, DQSOSC=414, MR23=63, INC=63, DEC=42
5305 12:47:47.812022
5306 12:47:47.815680 ----->DramcWriteLeveling(PI) begin...
5307 12:47:47.818822 ==
5308 12:47:47.821903 Dram Type= 6, Freq= 0, CH_0, rank 1
5309 12:47:47.825624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 12:47:47.825752 ==
5311 12:47:47.828575 Write leveling (Byte 0): 30 => 30
5312 12:47:47.832057 Write leveling (Byte 1): 29 => 29
5313 12:47:47.835512 DramcWriteLeveling(PI) end<-----
5314 12:47:47.835626
5315 12:47:47.835729 ==
5316 12:47:47.838590 Dram Type= 6, Freq= 0, CH_0, rank 1
5317 12:47:47.841850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 12:47:47.841972 ==
5319 12:47:47.845555 [Gating] SW mode calibration
5320 12:47:47.852267 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5321 12:47:47.855657 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5322 12:47:47.862074 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5323 12:47:47.865316 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
5324 12:47:47.868642 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 12:47:47.875533 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 12:47:47.878982 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 12:47:47.882016 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 12:47:47.888783 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5329 12:47:47.892039 0 14 28 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
5330 12:47:47.895733 0 15 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
5331 12:47:47.902045 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5332 12:47:47.905504 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 12:47:47.908500 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 12:47:47.915486 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 12:47:47.918627 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 12:47:47.922357 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 12:47:47.928662 0 15 28 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
5338 12:47:47.932447 1 0 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5339 12:47:47.935685 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 12:47:47.942080 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 12:47:47.945484 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 12:47:47.948650 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 12:47:47.952361 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 12:47:47.959188 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 12:47:47.962232 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5346 12:47:47.965840 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5347 12:47:47.972433 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5348 12:47:47.975740 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 12:47:47.979064 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 12:47:47.986139 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 12:47:47.989613 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 12:47:47.992578 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 12:47:47.999439 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 12:47:48.002494 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 12:47:48.005614 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 12:47:48.012413 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 12:47:48.016034 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 12:47:48.019126 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 12:47:48.022948 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 12:47:48.029471 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 12:47:48.032673 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5362 12:47:48.035841 Total UI for P1: 0, mck2ui 16
5363 12:47:48.039477 best dqsien dly found for B0: ( 1, 2, 26)
5364 12:47:48.042624 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5365 12:47:48.049624 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5366 12:47:48.052477 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 12:47:48.056182 Total UI for P1: 0, mck2ui 16
5368 12:47:48.059333 best dqsien dly found for B1: ( 1, 3, 2)
5369 12:47:48.062949 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5370 12:47:48.066045 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5371 12:47:48.066146
5372 12:47:48.069163 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5373 12:47:48.072704 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5374 12:47:48.075707 [Gating] SW calibration Done
5375 12:47:48.075786 ==
5376 12:47:48.079311 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 12:47:48.082763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 12:47:48.082850 ==
5379 12:47:48.086209 RX Vref Scan: 0
5380 12:47:48.086289
5381 12:47:48.089349 RX Vref 0 -> 0, step: 1
5382 12:47:48.089455
5383 12:47:48.089525 RX Delay -80 -> 252, step: 8
5384 12:47:48.095813 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5385 12:47:48.099668 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5386 12:47:48.102787 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5387 12:47:48.105845 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5388 12:47:48.109290 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5389 12:47:48.113068 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5390 12:47:48.119191 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5391 12:47:48.122857 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5392 12:47:48.125876 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5393 12:47:48.129428 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5394 12:47:48.132690 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5395 12:47:48.139434 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5396 12:47:48.142714 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5397 12:47:48.145811 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5398 12:47:48.149415 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5399 12:47:48.152599 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5400 12:47:48.152710 ==
5401 12:47:48.156218 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 12:47:48.159463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 12:47:48.162621 ==
5404 12:47:48.162752 DQS Delay:
5405 12:47:48.162860 DQS0 = 0, DQS1 = 0
5406 12:47:48.166281 DQM Delay:
5407 12:47:48.166395 DQM0 = 97, DQM1 = 88
5408 12:47:48.169473 DQ Delay:
5409 12:47:48.169579 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5410 12:47:48.172607 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5411 12:47:48.176204 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5412 12:47:48.179259 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5413 12:47:48.182875
5414 12:47:48.183001
5415 12:47:48.183107 ==
5416 12:47:48.185950 Dram Type= 6, Freq= 0, CH_0, rank 1
5417 12:47:48.189511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5418 12:47:48.189646 ==
5419 12:47:48.189762
5420 12:47:48.189873
5421 12:47:48.192888 TX Vref Scan disable
5422 12:47:48.193037 == TX Byte 0 ==
5423 12:47:48.199644 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5424 12:47:48.202920 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5425 12:47:48.203079 == TX Byte 1 ==
5426 12:47:48.209635 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5427 12:47:48.212820 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5428 12:47:48.212970 ==
5429 12:47:48.216027 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 12:47:48.219269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 12:47:48.219425 ==
5432 12:47:48.219552
5433 12:47:48.219670
5434 12:47:48.222913 TX Vref Scan disable
5435 12:47:48.226018 == TX Byte 0 ==
5436 12:47:48.229859 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5437 12:47:48.232894 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5438 12:47:48.236513 == TX Byte 1 ==
5439 12:47:48.239482 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5440 12:47:48.242787 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5441 12:47:48.242997
5442 12:47:48.243190 [DATLAT]
5443 12:47:48.246151 Freq=933, CH0 RK1
5444 12:47:48.246380
5445 12:47:48.249365 DATLAT Default: 0xb
5446 12:47:48.249585 0, 0xFFFF, sum = 0
5447 12:47:48.253029 1, 0xFFFF, sum = 0
5448 12:47:48.253216 2, 0xFFFF, sum = 0
5449 12:47:48.256117 3, 0xFFFF, sum = 0
5450 12:47:48.256268 4, 0xFFFF, sum = 0
5451 12:47:48.259346 5, 0xFFFF, sum = 0
5452 12:47:48.259625 6, 0xFFFF, sum = 0
5453 12:47:48.262956 7, 0xFFFF, sum = 0
5454 12:47:48.263170 8, 0xFFFF, sum = 0
5455 12:47:48.266395 9, 0xFFFF, sum = 0
5456 12:47:48.266606 10, 0x0, sum = 1
5457 12:47:48.269945 11, 0x0, sum = 2
5458 12:47:48.270162 12, 0x0, sum = 3
5459 12:47:48.273238 13, 0x0, sum = 4
5460 12:47:48.273408 best_step = 11
5461 12:47:48.273561
5462 12:47:48.273680 ==
5463 12:47:48.276268 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 12:47:48.279972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 12:47:48.280189 ==
5466 12:47:48.283003 RX Vref Scan: 0
5467 12:47:48.283221
5468 12:47:48.286233 RX Vref 0 -> 0, step: 1
5469 12:47:48.286484
5470 12:47:48.286678 RX Delay -61 -> 252, step: 4
5471 12:47:48.294175 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5472 12:47:48.297556 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5473 12:47:48.301084 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5474 12:47:48.304165 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5475 12:47:48.308039 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5476 12:47:48.311204 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5477 12:47:48.317901 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5478 12:47:48.320865 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5479 12:47:48.324522 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5480 12:47:48.327802 iDelay=199, Bit 9, Center 76 (-13 ~ 166) 180
5481 12:47:48.331186 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5482 12:47:48.334081 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5483 12:47:48.340904 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5484 12:47:48.344557 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5485 12:47:48.347653 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5486 12:47:48.351268 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5487 12:47:48.351385 ==
5488 12:47:48.354547 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 12:47:48.357588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 12:47:48.360757 ==
5491 12:47:48.360830 DQS Delay:
5492 12:47:48.360892 DQS0 = 0, DQS1 = 0
5493 12:47:48.364583 DQM Delay:
5494 12:47:48.364691 DQM0 = 95, DQM1 = 87
5495 12:47:48.364762 DQ Delay:
5496 12:47:48.367753 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5497 12:47:48.370845 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =102
5498 12:47:48.374291 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =78
5499 12:47:48.377874 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =94
5500 12:47:48.377971
5501 12:47:48.381096
5502 12:47:48.387691 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5503 12:47:48.391372 CH0 RK1: MR19=505, MR18=1F0D
5504 12:47:48.398117 CH0_RK1: MR19=0x505, MR18=0x1F0D, DQSOSC=412, MR23=63, INC=63, DEC=42
5505 12:47:48.398272 [RxdqsGatingPostProcess] freq 933
5506 12:47:48.404366 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5507 12:47:48.407923 best DQS0 dly(2T, 0.5T) = (0, 11)
5508 12:47:48.411130 best DQS1 dly(2T, 0.5T) = (0, 11)
5509 12:47:48.414910 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5510 12:47:48.418083 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5511 12:47:48.421230 best DQS0 dly(2T, 0.5T) = (0, 10)
5512 12:47:48.424732 best DQS1 dly(2T, 0.5T) = (0, 11)
5513 12:47:48.427800 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5514 12:47:48.431074 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5515 12:47:48.434620 Pre-setting of DQS Precalculation
5516 12:47:48.437998 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5517 12:47:48.438194 ==
5518 12:47:48.441630 Dram Type= 6, Freq= 0, CH_1, rank 0
5519 12:47:48.444604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 12:47:48.444779 ==
5521 12:47:48.451387 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5522 12:47:48.458283 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5523 12:47:48.461320 [CA 0] Center 36 (6~67) winsize 62
5524 12:47:48.464433 [CA 1] Center 36 (6~67) winsize 62
5525 12:47:48.468053 [CA 2] Center 34 (4~64) winsize 61
5526 12:47:48.471401 [CA 3] Center 33 (3~64) winsize 62
5527 12:47:48.474679 [CA 4] Center 33 (3~64) winsize 62
5528 12:47:48.477879 [CA 5] Center 33 (3~63) winsize 61
5529 12:47:48.478039
5530 12:47:48.481164 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5531 12:47:48.481337
5532 12:47:48.484578 [CATrainingPosCal] consider 1 rank data
5533 12:47:48.488006 u2DelayCellTimex100 = 270/100 ps
5534 12:47:48.491569 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5535 12:47:48.494639 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5536 12:47:48.498307 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5537 12:47:48.501431 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5538 12:47:48.505182 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5539 12:47:48.508277 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5540 12:47:48.508493
5541 12:47:48.514834 CA PerBit enable=1, Macro0, CA PI delay=33
5542 12:47:48.515016
5543 12:47:48.515180 [CBTSetCACLKResult] CA Dly = 33
5544 12:47:48.518011 CS Dly: 5 (0~36)
5545 12:47:48.518153 ==
5546 12:47:48.521186 Dram Type= 6, Freq= 0, CH_1, rank 1
5547 12:47:48.525017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5548 12:47:48.525168 ==
5549 12:47:48.531731 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5550 12:47:48.537929 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5551 12:47:48.541647 [CA 0] Center 36 (6~67) winsize 62
5552 12:47:48.544533 [CA 1] Center 36 (6~67) winsize 62
5553 12:47:48.548091 [CA 2] Center 33 (3~64) winsize 62
5554 12:47:48.551776 [CA 3] Center 33 (3~64) winsize 62
5555 12:47:48.554937 [CA 4] Center 34 (4~64) winsize 61
5556 12:47:48.558021 [CA 5] Center 32 (2~63) winsize 62
5557 12:47:48.558157
5558 12:47:48.561919 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5559 12:47:48.562059
5560 12:47:48.564932 [CATrainingPosCal] consider 2 rank data
5561 12:47:48.568019 u2DelayCellTimex100 = 270/100 ps
5562 12:47:48.571863 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5563 12:47:48.574908 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5564 12:47:48.577881 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5565 12:47:48.581519 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5566 12:47:48.584924 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5567 12:47:48.588088 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5568 12:47:48.588223
5569 12:47:48.591506 CA PerBit enable=1, Macro0, CA PI delay=33
5570 12:47:48.594833
5571 12:47:48.595081 [CBTSetCACLKResult] CA Dly = 33
5572 12:47:48.598159 CS Dly: 6 (0~38)
5573 12:47:48.598376
5574 12:47:48.601880 ----->DramcWriteLeveling(PI) begin...
5575 12:47:48.602102 ==
5576 12:47:48.605154 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 12:47:48.608233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 12:47:48.608437 ==
5579 12:47:48.611837 Write leveling (Byte 0): 26 => 26
5580 12:47:48.614937 Write leveling (Byte 1): 27 => 27
5581 12:47:48.618388 DramcWriteLeveling(PI) end<-----
5582 12:47:48.618546
5583 12:47:48.618658 ==
5584 12:47:48.621729 Dram Type= 6, Freq= 0, CH_1, rank 0
5585 12:47:48.625276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5586 12:47:48.625476 ==
5587 12:47:48.628417 [Gating] SW mode calibration
5588 12:47:48.635036 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5589 12:47:48.641748 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5590 12:47:48.645347 0 14 0 | B1->B0 | 2f2f 3333 | 0 0 | (0 0) (0 0)
5591 12:47:48.651846 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5592 12:47:48.655339 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 12:47:48.658538 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5594 12:47:48.661602 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 12:47:48.668645 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 12:47:48.671722 0 14 24 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
5597 12:47:48.675433 0 14 28 | B1->B0 | 2f2f 3030 | 1 0 | (1 1) (0 0)
5598 12:47:48.681661 0 15 0 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
5599 12:47:48.685236 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 12:47:48.688385 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 12:47:48.695105 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 12:47:48.698705 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 12:47:48.702311 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 12:47:48.708876 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 12:47:48.712206 0 15 28 | B1->B0 | 3030 3030 | 0 0 | (1 1) (1 1)
5606 12:47:48.715465 1 0 0 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
5607 12:47:48.722245 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 12:47:48.725275 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 12:47:48.728941 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 12:47:48.735225 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 12:47:48.738298 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 12:47:48.742140 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 12:47:48.745120 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5614 12:47:48.751902 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5615 12:47:48.755606 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 12:47:48.758656 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 12:47:48.765378 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 12:47:48.768685 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 12:47:48.771708 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 12:47:48.778600 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 12:47:48.782278 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 12:47:48.785354 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 12:47:48.792128 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 12:47:48.796034 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 12:47:48.798862 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 12:47:48.805897 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 12:47:48.809035 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 12:47:48.812094 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5629 12:47:48.815652 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5630 12:47:48.822715 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5631 12:47:48.825578 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 12:47:48.829172 Total UI for P1: 0, mck2ui 16
5633 12:47:48.832231 best dqsien dly found for B0: ( 1, 2, 28)
5634 12:47:48.835672 Total UI for P1: 0, mck2ui 16
5635 12:47:48.839062 best dqsien dly found for B1: ( 1, 2, 28)
5636 12:47:48.842507 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5637 12:47:48.845601 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5638 12:47:48.845727
5639 12:47:48.849493 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5640 12:47:48.852303 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5641 12:47:48.855846 [Gating] SW calibration Done
5642 12:47:48.855968 ==
5643 12:47:48.858994 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 12:47:48.862667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 12:47:48.865652 ==
5646 12:47:48.865743 RX Vref Scan: 0
5647 12:47:48.865812
5648 12:47:48.869296 RX Vref 0 -> 0, step: 1
5649 12:47:48.869377
5650 12:47:48.869441 RX Delay -80 -> 252, step: 8
5651 12:47:48.876010 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5652 12:47:48.879170 iDelay=200, Bit 1, Center 91 (0 ~ 183) 184
5653 12:47:48.882872 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5654 12:47:48.885971 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5655 12:47:48.889661 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5656 12:47:48.892611 iDelay=200, Bit 5, Center 107 (16 ~ 199) 184
5657 12:47:48.899473 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5658 12:47:48.902931 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5659 12:47:48.906516 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5660 12:47:48.909531 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5661 12:47:48.913197 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5662 12:47:48.916362 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5663 12:47:48.923272 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5664 12:47:48.926276 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5665 12:47:48.929894 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5666 12:47:48.932799 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5667 12:47:48.932929 ==
5668 12:47:48.936046 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 12:47:48.939699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 12:47:48.943170 ==
5671 12:47:48.943316 DQS Delay:
5672 12:47:48.943427 DQS0 = 0, DQS1 = 0
5673 12:47:48.946568 DQM Delay:
5674 12:47:48.946703 DQM0 = 96, DQM1 = 89
5675 12:47:48.949385 DQ Delay:
5676 12:47:48.949513 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =99
5677 12:47:48.953284 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5678 12:47:48.956340 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5679 12:47:48.959801 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5680 12:47:48.959935
5681 12:47:48.962943
5682 12:47:48.963082 ==
5683 12:47:48.966067 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 12:47:48.969823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 12:47:48.969990 ==
5686 12:47:48.970125
5687 12:47:48.970288
5688 12:47:48.972802 TX Vref Scan disable
5689 12:47:48.972953 == TX Byte 0 ==
5690 12:47:48.979761 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5691 12:47:48.982823 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5692 12:47:48.983022 == TX Byte 1 ==
5693 12:47:48.989694 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5694 12:47:48.992776 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5695 12:47:48.992946 ==
5696 12:47:48.996313 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 12:47:48.999382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 12:47:48.999589 ==
5699 12:47:48.999723
5700 12:47:48.999871
5701 12:47:49.003069 TX Vref Scan disable
5702 12:47:49.006048 == TX Byte 0 ==
5703 12:47:49.009585 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5704 12:47:49.013386 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5705 12:47:49.016403 == TX Byte 1 ==
5706 12:47:49.020156 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5707 12:47:49.023277 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5708 12:47:49.023428
5709 12:47:49.023571 [DATLAT]
5710 12:47:49.026387 Freq=933, CH1 RK0
5711 12:47:49.026502
5712 12:47:49.030112 DATLAT Default: 0xd
5713 12:47:49.030224 0, 0xFFFF, sum = 0
5714 12:47:49.033015 1, 0xFFFF, sum = 0
5715 12:47:49.033118 2, 0xFFFF, sum = 0
5716 12:47:49.036815 3, 0xFFFF, sum = 0
5717 12:47:49.036969 4, 0xFFFF, sum = 0
5718 12:47:49.039626 5, 0xFFFF, sum = 0
5719 12:47:49.039778 6, 0xFFFF, sum = 0
5720 12:47:49.043307 7, 0xFFFF, sum = 0
5721 12:47:49.043486 8, 0xFFFF, sum = 0
5722 12:47:49.046425 9, 0xFFFF, sum = 0
5723 12:47:49.046570 10, 0x0, sum = 1
5724 12:47:49.050002 11, 0x0, sum = 2
5725 12:47:49.050123 12, 0x0, sum = 3
5726 12:47:49.053003 13, 0x0, sum = 4
5727 12:47:49.053126 best_step = 11
5728 12:47:49.053267
5729 12:47:49.053365 ==
5730 12:47:49.056364 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 12:47:49.059745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 12:47:49.059864 ==
5733 12:47:49.063156 RX Vref Scan: 1
5734 12:47:49.063322
5735 12:47:49.066698 RX Vref 0 -> 0, step: 1
5736 12:47:49.066854
5737 12:47:49.066985 RX Delay -61 -> 252, step: 4
5738 12:47:49.067118
5739 12:47:49.070149 Set Vref, RX VrefLevel [Byte0]: 56
5740 12:47:49.073256 [Byte1]: 54
5741 12:47:49.078122
5742 12:47:49.078239 Final RX Vref Byte 0 = 56 to rank0
5743 12:47:49.081106 Final RX Vref Byte 1 = 54 to rank0
5744 12:47:49.084843 Final RX Vref Byte 0 = 56 to rank1
5745 12:47:49.087873 Final RX Vref Byte 1 = 54 to rank1==
5746 12:47:49.091000 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 12:47:49.094641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 12:47:49.097702 ==
5749 12:47:49.097861 DQS Delay:
5750 12:47:49.097990 DQS0 = 0, DQS1 = 0
5751 12:47:49.101365 DQM Delay:
5752 12:47:49.101485 DQM0 = 98, DQM1 = 90
5753 12:47:49.104750 DQ Delay:
5754 12:47:49.107665 DQ0 =102, DQ1 =92, DQ2 =84, DQ3 =98
5755 12:47:49.111129 DQ4 =98, DQ5 =108, DQ6 =108, DQ7 =94
5756 12:47:49.111312 DQ8 =78, DQ9 =78, DQ10 =90, DQ11 =86
5757 12:47:49.118210 DQ12 =98, DQ13 =96, DQ14 =100, DQ15 =98
5758 12:47:49.118386
5759 12:47:49.118519
5760 12:47:49.124532 [DQSOSCAuto] RK0, (LSB)MR18= 0x14f0, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps
5761 12:47:49.128247 CH1 RK0: MR19=504, MR18=14F0
5762 12:47:49.135091 CH1_RK0: MR19=0x504, MR18=0x14F0, DQSOSC=415, MR23=63, INC=62, DEC=41
5763 12:47:49.135272
5764 12:47:49.138136 ----->DramcWriteLeveling(PI) begin...
5765 12:47:49.138289 ==
5766 12:47:49.141211 Dram Type= 6, Freq= 0, CH_1, rank 1
5767 12:47:49.144940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 12:47:49.145064 ==
5769 12:47:49.148374 Write leveling (Byte 0): 28 => 28
5770 12:47:49.151640 Write leveling (Byte 1): 28 => 28
5771 12:47:49.154866 DramcWriteLeveling(PI) end<-----
5772 12:47:49.154979
5773 12:47:49.155078 ==
5774 12:47:49.158224 Dram Type= 6, Freq= 0, CH_1, rank 1
5775 12:47:49.161407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 12:47:49.161526 ==
5777 12:47:49.165105 [Gating] SW mode calibration
5778 12:47:49.171716 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5779 12:47:49.178170 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5780 12:47:49.181833 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 12:47:49.184860 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 12:47:49.191410 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 12:47:49.194672 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5784 12:47:49.198327 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 12:47:49.205043 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 12:47:49.208182 0 14 24 | B1->B0 | 3434 2d2d | 0 0 | (0 1) (1 0)
5787 12:47:49.211291 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5788 12:47:49.218303 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 12:47:49.221784 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5790 12:47:49.224725 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 12:47:49.228467 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 12:47:49.234697 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5793 12:47:49.238452 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 12:47:49.241615 0 15 24 | B1->B0 | 2c2c 3434 | 0 0 | (1 1) (0 0)
5795 12:47:49.248572 0 15 28 | B1->B0 | 3838 4141 | 0 0 | (0 0) (0 0)
5796 12:47:49.251608 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 12:47:49.255036 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 12:47:49.261729 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 12:47:49.265299 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 12:47:49.268297 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 12:47:49.275522 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5802 12:47:49.278656 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5803 12:47:49.282281 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 12:47:49.288580 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5805 12:47:49.292144 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 12:47:49.295205 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 12:47:49.298348 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 12:47:49.305234 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 12:47:49.308940 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 12:47:49.311975 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 12:47:49.318754 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 12:47:49.321833 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 12:47:49.325277 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 12:47:49.331823 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 12:47:49.335574 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 12:47:49.338752 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 12:47:49.344921 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 12:47:49.348766 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5819 12:47:49.351799 Total UI for P1: 0, mck2ui 16
5820 12:47:49.355539 best dqsien dly found for B0: ( 1, 2, 22)
5821 12:47:49.358721 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5822 12:47:49.365191 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 12:47:49.365305 Total UI for P1: 0, mck2ui 16
5824 12:47:49.368489 best dqsien dly found for B1: ( 1, 2, 26)
5825 12:47:49.375475 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5826 12:47:49.378952 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5827 12:47:49.379054
5828 12:47:49.382217 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5829 12:47:49.385370 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5830 12:47:49.388440 [Gating] SW calibration Done
5831 12:47:49.388576 ==
5832 12:47:49.391978 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 12:47:49.395394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 12:47:49.395490 ==
5835 12:47:49.398952 RX Vref Scan: 0
5836 12:47:49.399072
5837 12:47:49.399173 RX Vref 0 -> 0, step: 1
5838 12:47:49.399281
5839 12:47:49.401958 RX Delay -80 -> 252, step: 8
5840 12:47:49.405749 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5841 12:47:49.408984 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5842 12:47:49.415499 iDelay=200, Bit 2, Center 83 (-16 ~ 183) 200
5843 12:47:49.418523 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5844 12:47:49.422329 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5845 12:47:49.425487 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5846 12:47:49.429021 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5847 12:47:49.431945 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5848 12:47:49.438969 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5849 12:47:49.442066 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5850 12:47:49.445809 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5851 12:47:49.448797 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5852 12:47:49.451915 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5853 12:47:49.456404 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5854 12:47:49.461907 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5855 12:47:49.465559 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5856 12:47:49.465643 ==
5857 12:47:49.468579 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 12:47:49.472132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 12:47:49.472231 ==
5860 12:47:49.472303 DQS Delay:
5861 12:47:49.475593 DQS0 = 0, DQS1 = 0
5862 12:47:49.475704 DQM Delay:
5863 12:47:49.478986 DQM0 = 94, DQM1 = 88
5864 12:47:49.479064 DQ Delay:
5865 12:47:49.482742 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =95
5866 12:47:49.485527 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5867 12:47:49.488943 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5868 12:47:49.492415 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5869 12:47:49.492533
5870 12:47:49.492653
5871 12:47:49.492800 ==
5872 12:47:49.495428 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 12:47:49.499116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 12:47:49.502380 ==
5875 12:47:49.502459
5876 12:47:49.502532
5877 12:47:49.502598 TX Vref Scan disable
5878 12:47:49.505337 == TX Byte 0 ==
5879 12:47:49.509101 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5880 12:47:49.512217 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5881 12:47:49.515312 == TX Byte 1 ==
5882 12:47:49.518942 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5883 12:47:49.522043 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5884 12:47:49.525682 ==
5885 12:47:49.525770 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 12:47:49.532317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 12:47:49.532405 ==
5888 12:47:49.532470
5889 12:47:49.532551
5890 12:47:49.535428 TX Vref Scan disable
5891 12:47:49.535524 == TX Byte 0 ==
5892 12:47:49.541982 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5893 12:47:49.545371 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5894 12:47:49.545455 == TX Byte 1 ==
5895 12:47:49.551957 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5896 12:47:49.555578 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5897 12:47:49.555662
5898 12:47:49.555741 [DATLAT]
5899 12:47:49.558683 Freq=933, CH1 RK1
5900 12:47:49.558770
5901 12:47:49.558839 DATLAT Default: 0xb
5902 12:47:49.562375 0, 0xFFFF, sum = 0
5903 12:47:49.562479 1, 0xFFFF, sum = 0
5904 12:47:49.565487 2, 0xFFFF, sum = 0
5905 12:47:49.565572 3, 0xFFFF, sum = 0
5906 12:47:49.568592 4, 0xFFFF, sum = 0
5907 12:47:49.568681 5, 0xFFFF, sum = 0
5908 12:47:49.572274 6, 0xFFFF, sum = 0
5909 12:47:49.572369 7, 0xFFFF, sum = 0
5910 12:47:49.575812 8, 0xFFFF, sum = 0
5911 12:47:49.575912 9, 0xFFFF, sum = 0
5912 12:47:49.578910 10, 0x0, sum = 1
5913 12:47:49.579000 11, 0x0, sum = 2
5914 12:47:49.582000 12, 0x0, sum = 3
5915 12:47:49.582085 13, 0x0, sum = 4
5916 12:47:49.585660 best_step = 11
5917 12:47:49.585733
5918 12:47:49.585796 ==
5919 12:47:49.589090 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 12:47:49.592821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 12:47:49.592964 ==
5922 12:47:49.593067 RX Vref Scan: 0
5923 12:47:49.595667
5924 12:47:49.595768 RX Vref 0 -> 0, step: 1
5925 12:47:49.595870
5926 12:47:49.598988 RX Delay -61 -> 252, step: 4
5927 12:47:49.605899 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5928 12:47:49.609378 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5929 12:47:49.612721 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5930 12:47:49.615794 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5931 12:47:49.619419 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5932 12:47:49.622471 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5933 12:47:49.629493 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5934 12:47:49.632549 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5935 12:47:49.636189 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5936 12:47:49.639335 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5937 12:47:49.642361 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
5938 12:47:49.646233 iDelay=199, Bit 11, Center 84 (-9 ~ 178) 188
5939 12:47:49.652804 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5940 12:47:49.656180 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5941 12:47:49.658997 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5942 12:47:49.662775 iDelay=199, Bit 15, Center 100 (11 ~ 190) 180
5943 12:47:49.662879 ==
5944 12:47:49.665928 Dram Type= 6, Freq= 0, CH_1, rank 1
5945 12:47:49.672746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5946 12:47:49.672825 ==
5947 12:47:49.672904 DQS Delay:
5948 12:47:49.672966 DQS0 = 0, DQS1 = 0
5949 12:47:49.675825 DQM Delay:
5950 12:47:49.675896 DQM0 = 95, DQM1 = 91
5951 12:47:49.679412 DQ Delay:
5952 12:47:49.683113 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =92
5953 12:47:49.686125 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =90
5954 12:47:49.686199 DQ8 =80, DQ9 =78, DQ10 =94, DQ11 =84
5955 12:47:49.692746 DQ12 =98, DQ13 =100, DQ14 =100, DQ15 =100
5956 12:47:49.692868
5957 12:47:49.692961
5958 12:47:49.699508 [DQSOSCAuto] RK1, (LSB)MR18= 0xe18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5959 12:47:49.702954 CH1 RK1: MR19=505, MR18=E18
5960 12:47:49.709310 CH1_RK1: MR19=0x505, MR18=0xE18, DQSOSC=414, MR23=63, INC=63, DEC=42
5961 12:47:49.712941 [RxdqsGatingPostProcess] freq 933
5962 12:47:49.716037 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5963 12:47:49.719568 best DQS0 dly(2T, 0.5T) = (0, 10)
5964 12:47:49.722786 best DQS1 dly(2T, 0.5T) = (0, 10)
5965 12:47:49.726160 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5966 12:47:49.729660 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5967 12:47:49.732734 best DQS0 dly(2T, 0.5T) = (0, 10)
5968 12:47:49.736405 best DQS1 dly(2T, 0.5T) = (0, 10)
5969 12:47:49.739441 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5970 12:47:49.743120 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5971 12:47:49.746238 Pre-setting of DQS Precalculation
5972 12:47:49.749856 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5973 12:47:49.756077 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5974 12:47:49.763227 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5975 12:47:49.766004
5976 12:47:49.766111
5977 12:47:49.766203 [Calibration Summary] 1866 Mbps
5978 12:47:49.769693 CH 0, Rank 0
5979 12:47:49.769801 SW Impedance : PASS
5980 12:47:49.772945 DUTY Scan : NO K
5981 12:47:49.776844 ZQ Calibration : PASS
5982 12:47:49.776943 Jitter Meter : NO K
5983 12:47:49.779785 CBT Training : PASS
5984 12:47:49.782779 Write leveling : PASS
5985 12:47:49.782883 RX DQS gating : PASS
5986 12:47:49.786245 RX DQ/DQS(RDDQC) : PASS
5987 12:47:49.789842 TX DQ/DQS : PASS
5988 12:47:49.789945 RX DATLAT : PASS
5989 12:47:49.793347 RX DQ/DQS(Engine): PASS
5990 12:47:49.793449 TX OE : NO K
5991 12:47:49.796497 All Pass.
5992 12:47:49.796601
5993 12:47:49.796733 CH 0, Rank 1
5994 12:47:49.800060 SW Impedance : PASS
5995 12:47:49.800165 DUTY Scan : NO K
5996 12:47:49.803063 ZQ Calibration : PASS
5997 12:47:49.806371 Jitter Meter : NO K
5998 12:47:49.806476 CBT Training : PASS
5999 12:47:49.809878 Write leveling : PASS
6000 12:47:49.813247 RX DQS gating : PASS
6001 12:47:49.813345 RX DQ/DQS(RDDQC) : PASS
6002 12:47:49.816965 TX DQ/DQS : PASS
6003 12:47:49.820105 RX DATLAT : PASS
6004 12:47:49.820202 RX DQ/DQS(Engine): PASS
6005 12:47:49.823226 TX OE : NO K
6006 12:47:49.823310 All Pass.
6007 12:47:49.823374
6008 12:47:49.826926 CH 1, Rank 0
6009 12:47:49.827034 SW Impedance : PASS
6010 12:47:49.830355 DUTY Scan : NO K
6011 12:47:49.833199 ZQ Calibration : PASS
6012 12:47:49.833284 Jitter Meter : NO K
6013 12:47:49.836488 CBT Training : PASS
6014 12:47:49.836601 Write leveling : PASS
6015 12:47:49.839916 RX DQS gating : PASS
6016 12:47:49.843484 RX DQ/DQS(RDDQC) : PASS
6017 12:47:49.843590 TX DQ/DQS : PASS
6018 12:47:49.846581 RX DATLAT : PASS
6019 12:47:49.850248 RX DQ/DQS(Engine): PASS
6020 12:47:49.850351 TX OE : NO K
6021 12:47:49.853323 All Pass.
6022 12:47:49.853420
6023 12:47:49.853510 CH 1, Rank 1
6024 12:47:49.856407 SW Impedance : PASS
6025 12:47:49.856504 DUTY Scan : NO K
6026 12:47:49.860175 ZQ Calibration : PASS
6027 12:47:49.863256 Jitter Meter : NO K
6028 12:47:49.863373 CBT Training : PASS
6029 12:47:49.866997 Write leveling : PASS
6030 12:47:49.869941 RX DQS gating : PASS
6031 12:47:49.870014 RX DQ/DQS(RDDQC) : PASS
6032 12:47:49.873392 TX DQ/DQS : PASS
6033 12:47:49.873471 RX DATLAT : PASS
6034 12:47:49.876759 RX DQ/DQS(Engine): PASS
6035 12:47:49.880429 TX OE : NO K
6036 12:47:49.880503 All Pass.
6037 12:47:49.880564
6038 12:47:49.883667 DramC Write-DBI off
6039 12:47:49.883739 PER_BANK_REFRESH: Hybrid Mode
6040 12:47:49.886783 TX_TRACKING: ON
6041 12:47:49.897019 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6042 12:47:49.900237 [FAST_K] Save calibration result to emmc
6043 12:47:49.903712 dramc_set_vcore_voltage set vcore to 650000
6044 12:47:49.903825 Read voltage for 400, 6
6045 12:47:49.906780 Vio18 = 0
6046 12:47:49.906859 Vcore = 650000
6047 12:47:49.906921 Vdram = 0
6048 12:47:49.910010 Vddq = 0
6049 12:47:49.910092 Vmddr = 0
6050 12:47:49.913773 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6051 12:47:49.920232 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6052 12:47:49.923733 MEM_TYPE=3, freq_sel=20
6053 12:47:49.926893 sv_algorithm_assistance_LP4_800
6054 12:47:49.930040 ============ PULL DRAM RESETB DOWN ============
6055 12:47:49.933639 ========== PULL DRAM RESETB DOWN end =========
6056 12:47:49.940286 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6057 12:47:49.943261 ===================================
6058 12:47:49.943365 LPDDR4 DRAM CONFIGURATION
6059 12:47:49.946483 ===================================
6060 12:47:49.950138 EX_ROW_EN[0] = 0x0
6061 12:47:49.950210 EX_ROW_EN[1] = 0x0
6062 12:47:49.953194 LP4Y_EN = 0x0
6063 12:47:49.953282 WORK_FSP = 0x0
6064 12:47:49.956814 WL = 0x2
6065 12:47:49.956889 RL = 0x2
6066 12:47:49.960070 BL = 0x2
6067 12:47:49.960168 RPST = 0x0
6068 12:47:49.963112 RD_PRE = 0x0
6069 12:47:49.966884 WR_PRE = 0x1
6070 12:47:49.966966 WR_PST = 0x0
6071 12:47:49.969931 DBI_WR = 0x0
6072 12:47:49.970001 DBI_RD = 0x0
6073 12:47:49.973702 OTF = 0x1
6074 12:47:49.976777 ===================================
6075 12:47:49.980316 ===================================
6076 12:47:49.980386 ANA top config
6077 12:47:49.983701 ===================================
6078 12:47:49.986928 DLL_ASYNC_EN = 0
6079 12:47:49.986999 ALL_SLAVE_EN = 1
6080 12:47:49.989940 NEW_RANK_MODE = 1
6081 12:47:49.993600 DLL_IDLE_MODE = 1
6082 12:47:49.996970 LP45_APHY_COMB_EN = 1
6083 12:47:49.999998 TX_ODT_DIS = 1
6084 12:47:50.000095 NEW_8X_MODE = 1
6085 12:47:50.003624 ===================================
6086 12:47:50.006601 ===================================
6087 12:47:50.010144 data_rate = 800
6088 12:47:50.013224 CKR = 1
6089 12:47:50.016995 DQ_P2S_RATIO = 4
6090 12:47:50.020081 ===================================
6091 12:47:50.023928 CA_P2S_RATIO = 4
6092 12:47:50.024010 DQ_CA_OPEN = 0
6093 12:47:50.026853 DQ_SEMI_OPEN = 1
6094 12:47:50.030282 CA_SEMI_OPEN = 1
6095 12:47:50.034026 CA_FULL_RATE = 0
6096 12:47:50.037142 DQ_CKDIV4_EN = 0
6097 12:47:50.040172 CA_CKDIV4_EN = 1
6098 12:47:50.040248 CA_PREDIV_EN = 0
6099 12:47:50.043919 PH8_DLY = 0
6100 12:47:50.047063 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6101 12:47:50.050176 DQ_AAMCK_DIV = 0
6102 12:47:50.053829 CA_AAMCK_DIV = 0
6103 12:47:50.057351 CA_ADMCK_DIV = 4
6104 12:47:50.057425 DQ_TRACK_CA_EN = 0
6105 12:47:50.060152 CA_PICK = 800
6106 12:47:50.063850 CA_MCKIO = 400
6107 12:47:50.067030 MCKIO_SEMI = 400
6108 12:47:50.070592 PLL_FREQ = 3016
6109 12:47:50.073406 DQ_UI_PI_RATIO = 32
6110 12:47:50.077131 CA_UI_PI_RATIO = 32
6111 12:47:50.080250 ===================================
6112 12:47:50.083392 ===================================
6113 12:47:50.083508 memory_type:LPDDR4
6114 12:47:50.087065 GP_NUM : 10
6115 12:47:50.089941 SRAM_EN : 1
6116 12:47:50.090063 MD32_EN : 0
6117 12:47:50.093389 ===================================
6118 12:47:50.096834 [ANA_INIT] >>>>>>>>>>>>>>
6119 12:47:50.099846 <<<<<< [CONFIGURE PHASE]: ANA_TX
6120 12:47:50.103257 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6121 12:47:50.106759 ===================================
6122 12:47:50.110374 data_rate = 800,PCW = 0X7400
6123 12:47:50.113284 ===================================
6124 12:47:50.116954 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6125 12:47:50.120089 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6126 12:47:50.133815 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6127 12:47:50.136719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6128 12:47:50.139971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6129 12:47:50.143631 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6130 12:47:50.146726 [ANA_INIT] flow start
6131 12:47:50.146809 [ANA_INIT] PLL >>>>>>>>
6132 12:47:50.150507 [ANA_INIT] PLL <<<<<<<<
6133 12:47:50.153620 [ANA_INIT] MIDPI >>>>>>>>
6134 12:47:50.153702 [ANA_INIT] MIDPI <<<<<<<<
6135 12:47:50.156743 [ANA_INIT] DLL >>>>>>>>
6136 12:47:50.160351 [ANA_INIT] flow end
6137 12:47:50.163343 ============ LP4 DIFF to SE enter ============
6138 12:47:50.166941 ============ LP4 DIFF to SE exit ============
6139 12:47:50.170567 [ANA_INIT] <<<<<<<<<<<<<
6140 12:47:50.173564 [Flow] Enable top DCM control >>>>>
6141 12:47:50.177067 [Flow] Enable top DCM control <<<<<
6142 12:47:50.180000 Enable DLL master slave shuffle
6143 12:47:50.183694 ==============================================================
6144 12:47:50.186810 Gating Mode config
6145 12:47:50.193408 ==============================================================
6146 12:47:50.193515 Config description:
6147 12:47:50.203612 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6148 12:47:50.210133 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6149 12:47:50.213905 SELPH_MODE 0: By rank 1: By Phase
6150 12:47:50.220484 ==============================================================
6151 12:47:50.223607 GAT_TRACK_EN = 0
6152 12:47:50.226779 RX_GATING_MODE = 2
6153 12:47:50.230614 RX_GATING_TRACK_MODE = 2
6154 12:47:50.233678 SELPH_MODE = 1
6155 12:47:50.236850 PICG_EARLY_EN = 1
6156 12:47:50.240323 VALID_LAT_VALUE = 1
6157 12:47:50.243846 ==============================================================
6158 12:47:50.246766 Enter into Gating configuration >>>>
6159 12:47:50.250671 Exit from Gating configuration <<<<
6160 12:47:50.253754 Enter into DVFS_PRE_config >>>>>
6161 12:47:50.263668 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6162 12:47:50.267045 Exit from DVFS_PRE_config <<<<<
6163 12:47:50.270737 Enter into PICG configuration >>>>
6164 12:47:50.273892 Exit from PICG configuration <<<<
6165 12:47:50.277015 [RX_INPUT] configuration >>>>>
6166 12:47:50.280576 [RX_INPUT] configuration <<<<<
6167 12:47:50.287079 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6168 12:47:50.290741 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6169 12:47:50.296769 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6170 12:47:50.303602 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6171 12:47:50.310383 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6172 12:47:50.317178 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6173 12:47:50.320628 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6174 12:47:50.323976 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6175 12:47:50.327216 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6176 12:47:50.330330 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6177 12:47:50.337268 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6178 12:47:50.340403 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6179 12:47:50.344123 ===================================
6180 12:47:50.347285 LPDDR4 DRAM CONFIGURATION
6181 12:47:50.350369 ===================================
6182 12:47:50.350476 EX_ROW_EN[0] = 0x0
6183 12:47:50.353826 EX_ROW_EN[1] = 0x0
6184 12:47:50.353936 LP4Y_EN = 0x0
6185 12:47:50.357196 WORK_FSP = 0x0
6186 12:47:50.357305 WL = 0x2
6187 12:47:50.360615 RL = 0x2
6188 12:47:50.360744 BL = 0x2
6189 12:47:50.364289 RPST = 0x0
6190 12:47:50.364384 RD_PRE = 0x0
6191 12:47:50.367460 WR_PRE = 0x1
6192 12:47:50.367562 WR_PST = 0x0
6193 12:47:50.371193 DBI_WR = 0x0
6194 12:47:50.371307 DBI_RD = 0x0
6195 12:47:50.374151 OTF = 0x1
6196 12:47:50.377696 ===================================
6197 12:47:50.380685 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6198 12:47:50.384282 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6199 12:47:50.390885 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6200 12:47:50.394594 ===================================
6201 12:47:50.394697 LPDDR4 DRAM CONFIGURATION
6202 12:47:50.397641 ===================================
6203 12:47:50.401123 EX_ROW_EN[0] = 0x10
6204 12:47:50.404266 EX_ROW_EN[1] = 0x0
6205 12:47:50.404363 LP4Y_EN = 0x0
6206 12:47:50.407379 WORK_FSP = 0x0
6207 12:47:50.407483 WL = 0x2
6208 12:47:50.411033 RL = 0x2
6209 12:47:50.411130 BL = 0x2
6210 12:47:50.414157 RPST = 0x0
6211 12:47:50.414262 RD_PRE = 0x0
6212 12:47:50.417397 WR_PRE = 0x1
6213 12:47:50.417493 WR_PST = 0x0
6214 12:47:50.421129 DBI_WR = 0x0
6215 12:47:50.421231 DBI_RD = 0x0
6216 12:47:50.424089 OTF = 0x1
6217 12:47:50.427922 ===================================
6218 12:47:50.434361 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6219 12:47:50.437682 nWR fixed to 30
6220 12:47:50.437791 [ModeRegInit_LP4] CH0 RK0
6221 12:47:50.440849 [ModeRegInit_LP4] CH0 RK1
6222 12:47:50.444426 [ModeRegInit_LP4] CH1 RK0
6223 12:47:50.444566 [ModeRegInit_LP4] CH1 RK1
6224 12:47:50.447971 match AC timing 19
6225 12:47:50.451079 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6226 12:47:50.454246 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6227 12:47:50.460891 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6228 12:47:50.464212 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6229 12:47:50.471280 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6230 12:47:50.471397 ==
6231 12:47:50.474367 Dram Type= 6, Freq= 0, CH_0, rank 0
6232 12:47:50.477912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6233 12:47:50.478017 ==
6234 12:47:50.484629 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6235 12:47:50.487839 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6236 12:47:50.491446 [CA 0] Center 36 (8~64) winsize 57
6237 12:47:50.494364 [CA 1] Center 36 (8~64) winsize 57
6238 12:47:50.497893 [CA 2] Center 36 (8~64) winsize 57
6239 12:47:50.501524 [CA 3] Center 36 (8~64) winsize 57
6240 12:47:50.504515 [CA 4] Center 36 (8~64) winsize 57
6241 12:47:50.508131 [CA 5] Center 36 (8~64) winsize 57
6242 12:47:50.508240
6243 12:47:50.511121 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6244 12:47:50.511226
6245 12:47:50.514902 [CATrainingPosCal] consider 1 rank data
6246 12:47:50.517976 u2DelayCellTimex100 = 270/100 ps
6247 12:47:50.521684 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 12:47:50.524732 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 12:47:50.527922 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 12:47:50.531665 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 12:47:50.538243 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 12:47:50.541237 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 12:47:50.541321
6254 12:47:50.544855 CA PerBit enable=1, Macro0, CA PI delay=36
6255 12:47:50.544939
6256 12:47:50.548399 [CBTSetCACLKResult] CA Dly = 36
6257 12:47:50.548483 CS Dly: 1 (0~32)
6258 12:47:50.548548 ==
6259 12:47:50.551745 Dram Type= 6, Freq= 0, CH_0, rank 1
6260 12:47:50.554749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 12:47:50.557943 ==
6262 12:47:50.561745 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6263 12:47:50.567936 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6264 12:47:50.571433 [CA 0] Center 36 (8~64) winsize 57
6265 12:47:50.575105 [CA 1] Center 36 (8~64) winsize 57
6266 12:47:50.578054 [CA 2] Center 36 (8~64) winsize 57
6267 12:47:50.581362 [CA 3] Center 36 (8~64) winsize 57
6268 12:47:50.584821 [CA 4] Center 36 (8~64) winsize 57
6269 12:47:50.587791 [CA 5] Center 36 (8~64) winsize 57
6270 12:47:50.587874
6271 12:47:50.591408 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6272 12:47:50.591518
6273 12:47:50.594556 [CATrainingPosCal] consider 2 rank data
6274 12:47:50.598311 u2DelayCellTimex100 = 270/100 ps
6275 12:47:50.601326 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 12:47:50.604967 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 12:47:50.608280 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 12:47:50.611315 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 12:47:50.615162 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 12:47:50.618292 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 12:47:50.618375
6282 12:47:50.621496 CA PerBit enable=1, Macro0, CA PI delay=36
6283 12:47:50.621585
6284 12:47:50.624540 [CBTSetCACLKResult] CA Dly = 36
6285 12:47:50.628187 CS Dly: 1 (0~32)
6286 12:47:50.628270
6287 12:47:50.631285 ----->DramcWriteLeveling(PI) begin...
6288 12:47:50.631370 ==
6289 12:47:50.635143 Dram Type= 6, Freq= 0, CH_0, rank 0
6290 12:47:50.638129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 12:47:50.638214 ==
6292 12:47:50.641866 Write leveling (Byte 0): 40 => 8
6293 12:47:50.645066 Write leveling (Byte 1): 32 => 0
6294 12:47:50.647944 DramcWriteLeveling(PI) end<-----
6295 12:47:50.648031
6296 12:47:50.648097 ==
6297 12:47:50.651721 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 12:47:50.654755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 12:47:50.654839 ==
6300 12:47:50.658462 [Gating] SW mode calibration
6301 12:47:50.664607 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6302 12:47:50.671858 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6303 12:47:50.674943 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6304 12:47:50.678469 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6305 12:47:50.684979 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6306 12:47:50.688348 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6307 12:47:50.691241 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6308 12:47:50.698314 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 12:47:50.701545 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 12:47:50.705307 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 12:47:50.711729 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6312 12:47:50.711834 Total UI for P1: 0, mck2ui 16
6313 12:47:50.718139 best dqsien dly found for B0: ( 0, 14, 24)
6314 12:47:50.718244 Total UI for P1: 0, mck2ui 16
6315 12:47:50.721669 best dqsien dly found for B1: ( 0, 14, 24)
6316 12:47:50.728520 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6317 12:47:50.731651 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6318 12:47:50.731735
6319 12:47:50.735428 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6320 12:47:50.738431 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6321 12:47:50.741649 [Gating] SW calibration Done
6322 12:47:50.741733 ==
6323 12:47:50.745336 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 12:47:50.748343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 12:47:50.748445 ==
6326 12:47:50.752062 RX Vref Scan: 0
6327 12:47:50.752145
6328 12:47:50.752211 RX Vref 0 -> 0, step: 1
6329 12:47:50.752272
6330 12:47:50.754977 RX Delay -410 -> 252, step: 16
6331 12:47:50.758700 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6332 12:47:50.764973 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6333 12:47:50.768724 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6334 12:47:50.771828 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6335 12:47:50.775047 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6336 12:47:50.781990 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6337 12:47:50.785219 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6338 12:47:50.788353 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6339 12:47:50.792068 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6340 12:47:50.798631 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6341 12:47:50.802000 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6342 12:47:50.804991 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6343 12:47:50.808841 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6344 12:47:50.815261 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6345 12:47:50.818570 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6346 12:47:50.821948 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6347 12:47:50.822035 ==
6348 12:47:50.825113 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 12:47:50.828848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 12:47:50.831929 ==
6351 12:47:50.831999 DQS Delay:
6352 12:47:50.832066 DQS0 = 35, DQS1 = 51
6353 12:47:50.835735 DQM Delay:
6354 12:47:50.835804 DQM0 = 6, DQM1 = 10
6355 12:47:50.838828 DQ Delay:
6356 12:47:50.838902 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6357 12:47:50.841932 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6358 12:47:50.845678 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6359 12:47:50.848641 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6360 12:47:50.848755
6361 12:47:50.848817
6362 12:47:50.848874 ==
6363 12:47:50.851932 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 12:47:50.859059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 12:47:50.859135 ==
6366 12:47:50.859209
6367 12:47:50.859269
6368 12:47:50.859326 TX Vref Scan disable
6369 12:47:50.862200 == TX Byte 0 ==
6370 12:47:50.865318 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6371 12:47:50.868967 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6372 12:47:50.872085 == TX Byte 1 ==
6373 12:47:50.875719 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6374 12:47:50.878770 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6375 12:47:50.878837 ==
6376 12:47:50.881904 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 12:47:50.888731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 12:47:50.888839 ==
6379 12:47:50.888904
6380 12:47:50.888967
6381 12:47:50.889023 TX Vref Scan disable
6382 12:47:50.891990 == TX Byte 0 ==
6383 12:47:50.895652 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6384 12:47:50.898612 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6385 12:47:50.902312 == TX Byte 1 ==
6386 12:47:50.905587 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6387 12:47:50.909140 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6388 12:47:50.909221
6389 12:47:50.912152 [DATLAT]
6390 12:47:50.912233 Freq=400, CH0 RK0
6391 12:47:50.912298
6392 12:47:50.915533 DATLAT Default: 0xf
6393 12:47:50.915614 0, 0xFFFF, sum = 0
6394 12:47:50.919091 1, 0xFFFF, sum = 0
6395 12:47:50.919175 2, 0xFFFF, sum = 0
6396 12:47:50.922161 3, 0xFFFF, sum = 0
6397 12:47:50.922274 4, 0xFFFF, sum = 0
6398 12:47:50.925803 5, 0xFFFF, sum = 0
6399 12:47:50.925887 6, 0xFFFF, sum = 0
6400 12:47:50.929197 7, 0xFFFF, sum = 0
6401 12:47:50.929283 8, 0xFFFF, sum = 0
6402 12:47:50.932260 9, 0xFFFF, sum = 0
6403 12:47:50.932342 10, 0xFFFF, sum = 0
6404 12:47:50.936051 11, 0xFFFF, sum = 0
6405 12:47:50.939168 12, 0xFFFF, sum = 0
6406 12:47:50.939251 13, 0x0, sum = 1
6407 12:47:50.939317 14, 0x0, sum = 2
6408 12:47:50.942338 15, 0x0, sum = 3
6409 12:47:50.942421 16, 0x0, sum = 4
6410 12:47:50.945560 best_step = 14
6411 12:47:50.945641
6412 12:47:50.945706 ==
6413 12:47:50.949375 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 12:47:50.952392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 12:47:50.952474 ==
6416 12:47:50.955615 RX Vref Scan: 1
6417 12:47:50.955696
6418 12:47:50.955760 RX Vref 0 -> 0, step: 1
6419 12:47:50.955820
6420 12:47:50.958779 RX Delay -343 -> 252, step: 8
6421 12:47:50.958860
6422 12:47:50.962459 Set Vref, RX VrefLevel [Byte0]: 53
6423 12:47:50.965906 [Byte1]: 51
6424 12:47:50.970795
6425 12:47:50.970876 Final RX Vref Byte 0 = 53 to rank0
6426 12:47:50.974030 Final RX Vref Byte 1 = 51 to rank0
6427 12:47:50.977044 Final RX Vref Byte 0 = 53 to rank1
6428 12:47:50.980852 Final RX Vref Byte 1 = 51 to rank1==
6429 12:47:50.983840 Dram Type= 6, Freq= 0, CH_0, rank 0
6430 12:47:50.990683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 12:47:50.990765 ==
6432 12:47:50.990830 DQS Delay:
6433 12:47:50.990890 DQS0 = 44, DQS1 = 60
6434 12:47:50.993623 DQM Delay:
6435 12:47:50.993731 DQM0 = 11, DQM1 = 15
6436 12:47:50.997252 DQ Delay:
6437 12:47:51.000899 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6438 12:47:51.000980 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6439 12:47:51.003664 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =12
6440 12:47:51.007436 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6441 12:47:51.007518
6442 12:47:51.007583
6443 12:47:51.017167 [DQSOSCAuto] RK0, (LSB)MR18= 0x8b59, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6444 12:47:51.020582 CH0 RK0: MR19=C0C, MR18=8B59
6445 12:47:51.027370 CH0_RK0: MR19=0xC0C, MR18=0x8B59, DQSOSC=392, MR23=63, INC=384, DEC=256
6446 12:47:51.027453 ==
6447 12:47:51.030546 Dram Type= 6, Freq= 0, CH_0, rank 1
6448 12:47:51.034685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 12:47:51.034768 ==
6450 12:47:51.037543 [Gating] SW mode calibration
6451 12:47:51.044026 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6452 12:47:51.047156 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6453 12:47:51.054072 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6454 12:47:51.057182 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6455 12:47:51.060931 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6456 12:47:51.067145 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 12:47:51.070610 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 12:47:51.074285 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 12:47:51.080599 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 12:47:51.084357 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 12:47:51.087496 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6462 12:47:51.090623 Total UI for P1: 0, mck2ui 16
6463 12:47:51.094228 best dqsien dly found for B0: ( 0, 14, 24)
6464 12:47:51.097350 Total UI for P1: 0, mck2ui 16
6465 12:47:51.101000 best dqsien dly found for B1: ( 0, 14, 24)
6466 12:47:51.104057 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6467 12:47:51.107762 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6468 12:47:51.107843
6469 12:47:51.113942 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6470 12:47:51.117363 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6471 12:47:51.117445 [Gating] SW calibration Done
6472 12:47:51.120621 ==
6473 12:47:51.120756 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 12:47:51.128043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 12:47:51.128125 ==
6476 12:47:51.128190 RX Vref Scan: 0
6477 12:47:51.128250
6478 12:47:51.130955 RX Vref 0 -> 0, step: 1
6479 12:47:51.131037
6480 12:47:51.134217 RX Delay -410 -> 252, step: 16
6481 12:47:51.137663 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6482 12:47:51.141266 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6483 12:47:51.147480 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6484 12:47:51.150713 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6485 12:47:51.154084 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6486 12:47:51.157740 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6487 12:47:51.164150 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6488 12:47:51.167984 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6489 12:47:51.171154 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6490 12:47:51.174246 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6491 12:47:51.180727 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6492 12:47:51.184412 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6493 12:47:51.187536 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6494 12:47:51.191340 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6495 12:47:51.197594 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6496 12:47:51.201273 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6497 12:47:51.201355 ==
6498 12:47:51.204121 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 12:47:51.207813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 12:47:51.207894 ==
6501 12:47:51.210959 DQS Delay:
6502 12:47:51.211040 DQS0 = 43, DQS1 = 51
6503 12:47:51.211105 DQM Delay:
6504 12:47:51.214643 DQM0 = 11, DQM1 = 10
6505 12:47:51.214729 DQ Delay:
6506 12:47:51.217681 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6507 12:47:51.221378 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6508 12:47:51.224196 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6509 12:47:51.227781 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6510 12:47:51.227861
6511 12:47:51.227926
6512 12:47:51.227986 ==
6513 12:47:51.231351 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 12:47:51.234276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 12:47:51.234358 ==
6516 12:47:51.234422
6517 12:47:51.237689
6518 12:47:51.237771 TX Vref Scan disable
6519 12:47:51.241247 == TX Byte 0 ==
6520 12:47:51.244468 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6521 12:47:51.247459 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6522 12:47:51.251100 == TX Byte 1 ==
6523 12:47:51.254625 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6524 12:47:51.257610 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6525 12:47:51.257692 ==
6526 12:47:51.261000 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 12:47:51.264257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 12:47:51.264339 ==
6529 12:47:51.264404
6530 12:47:51.267935
6531 12:47:51.268017 TX Vref Scan disable
6532 12:47:51.271011 == TX Byte 0 ==
6533 12:47:51.274127 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6534 12:47:51.277881 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6535 12:47:51.280876 == TX Byte 1 ==
6536 12:47:51.284115 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6537 12:47:51.287492 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6538 12:47:51.287636
6539 12:47:51.287721 [DATLAT]
6540 12:47:51.291243 Freq=400, CH0 RK1
6541 12:47:51.291325
6542 12:47:51.291390 DATLAT Default: 0xe
6543 12:47:51.294327 0, 0xFFFF, sum = 0
6544 12:47:51.297370 1, 0xFFFF, sum = 0
6545 12:47:51.297453 2, 0xFFFF, sum = 0
6546 12:47:51.301138 3, 0xFFFF, sum = 0
6547 12:47:51.301221 4, 0xFFFF, sum = 0
6548 12:47:51.304151 5, 0xFFFF, sum = 0
6549 12:47:51.304234 6, 0xFFFF, sum = 0
6550 12:47:51.307737 7, 0xFFFF, sum = 0
6551 12:47:51.307820 8, 0xFFFF, sum = 0
6552 12:47:51.310827 9, 0xFFFF, sum = 0
6553 12:47:51.310911 10, 0xFFFF, sum = 0
6554 12:47:51.314497 11, 0xFFFF, sum = 0
6555 12:47:51.314579 12, 0xFFFF, sum = 0
6556 12:47:51.317741 13, 0x0, sum = 1
6557 12:47:51.317824 14, 0x0, sum = 2
6558 12:47:51.320974 15, 0x0, sum = 3
6559 12:47:51.321056 16, 0x0, sum = 4
6560 12:47:51.324003 best_step = 14
6561 12:47:51.324084
6562 12:47:51.324148 ==
6563 12:47:51.327722 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 12:47:51.331170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 12:47:51.331252 ==
6566 12:47:51.331318 RX Vref Scan: 0
6567 12:47:51.331378
6568 12:47:51.334490 RX Vref 0 -> 0, step: 1
6569 12:47:51.334572
6570 12:47:51.337347 RX Delay -343 -> 252, step: 8
6571 12:47:51.344677 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6572 12:47:51.348355 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6573 12:47:51.351846 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6574 12:47:51.354789 iDelay=217, Bit 3, Center -32 (-271 ~ 208) 480
6575 12:47:51.361499 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6576 12:47:51.364897 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6577 12:47:51.368243 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6578 12:47:51.371604 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6579 12:47:51.378270 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6580 12:47:51.381367 iDelay=217, Bit 9, Center -56 (-295 ~ 184) 480
6581 12:47:51.385139 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6582 12:47:51.388275 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6583 12:47:51.394754 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6584 12:47:51.398387 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6585 12:47:51.401644 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6586 12:47:51.405317 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6587 12:47:51.408407 ==
6588 12:47:51.412030 Dram Type= 6, Freq= 0, CH_0, rank 1
6589 12:47:51.415366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 12:47:51.415448 ==
6591 12:47:51.415513 DQS Delay:
6592 12:47:51.418248 DQS0 = 48, DQS1 = 56
6593 12:47:51.418329 DQM Delay:
6594 12:47:51.422050 DQM0 = 14, DQM1 = 10
6595 12:47:51.422133 DQ Delay:
6596 12:47:51.425099 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =16
6597 12:47:51.428362 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6598 12:47:51.431564 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6599 12:47:51.435137 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =20
6600 12:47:51.435219
6601 12:47:51.435283
6602 12:47:51.441997 [DQSOSCAuto] RK1, (LSB)MR18= 0x9b6f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6603 12:47:51.444959 CH0 RK1: MR19=C0C, MR18=9B6F
6604 12:47:51.451498 CH0_RK1: MR19=0xC0C, MR18=0x9B6F, DQSOSC=390, MR23=63, INC=388, DEC=258
6605 12:47:51.455118 [RxdqsGatingPostProcess] freq 400
6606 12:47:51.458825 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6607 12:47:51.461796 best DQS0 dly(2T, 0.5T) = (0, 10)
6608 12:47:51.465140 best DQS1 dly(2T, 0.5T) = (0, 10)
6609 12:47:51.468833 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6610 12:47:51.472113 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6611 12:47:51.475051 best DQS0 dly(2T, 0.5T) = (0, 10)
6612 12:47:51.478309 best DQS1 dly(2T, 0.5T) = (0, 10)
6613 12:47:51.481805 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6614 12:47:51.484978 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6615 12:47:51.488811 Pre-setting of DQS Precalculation
6616 12:47:51.492007 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6617 12:47:51.492113 ==
6618 12:47:51.495163 Dram Type= 6, Freq= 0, CH_1, rank 0
6619 12:47:51.501758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 12:47:51.501853 ==
6621 12:47:51.505197 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6622 12:47:51.512065 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6623 12:47:51.515220 [CA 0] Center 36 (8~64) winsize 57
6624 12:47:51.518809 [CA 1] Center 36 (8~64) winsize 57
6625 12:47:51.522063 [CA 2] Center 36 (8~64) winsize 57
6626 12:47:51.525095 [CA 3] Center 36 (8~64) winsize 57
6627 12:47:51.528781 [CA 4] Center 36 (8~64) winsize 57
6628 12:47:51.531848 [CA 5] Center 36 (8~64) winsize 57
6629 12:47:51.531944
6630 12:47:51.535631 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6631 12:47:51.535727
6632 12:47:51.538653 [CATrainingPosCal] consider 1 rank data
6633 12:47:51.542265 u2DelayCellTimex100 = 270/100 ps
6634 12:47:51.545634 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 12:47:51.548842 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 12:47:51.552323 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 12:47:51.555680 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 12:47:51.558648 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 12:47:51.562313 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 12:47:51.562442
6641 12:47:51.565486 CA PerBit enable=1, Macro0, CA PI delay=36
6642 12:47:51.568568
6643 12:47:51.568703 [CBTSetCACLKResult] CA Dly = 36
6644 12:47:51.572106 CS Dly: 1 (0~32)
6645 12:47:51.572215 ==
6646 12:47:51.575551 Dram Type= 6, Freq= 0, CH_1, rank 1
6647 12:47:51.578993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 12:47:51.579139 ==
6649 12:47:51.585393 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6650 12:47:51.592001 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6651 12:47:51.595690 [CA 0] Center 36 (8~64) winsize 57
6652 12:47:51.595824 [CA 1] Center 36 (8~64) winsize 57
6653 12:47:51.598752 [CA 2] Center 36 (8~64) winsize 57
6654 12:47:51.602566 [CA 3] Center 36 (8~64) winsize 57
6655 12:47:51.605639 [CA 4] Center 36 (8~64) winsize 57
6656 12:47:51.608693 [CA 5] Center 36 (8~64) winsize 57
6657 12:47:51.608802
6658 12:47:51.612106 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6659 12:47:51.612216
6660 12:47:51.615723 [CATrainingPosCal] consider 2 rank data
6661 12:47:51.619211 u2DelayCellTimex100 = 270/100 ps
6662 12:47:51.622212 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 12:47:51.629171 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 12:47:51.632042 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 12:47:51.635792 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 12:47:51.638893 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 12:47:51.642627 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 12:47:51.642796
6669 12:47:51.645690 CA PerBit enable=1, Macro0, CA PI delay=36
6670 12:47:51.645830
6671 12:47:51.649200 [CBTSetCACLKResult] CA Dly = 36
6672 12:47:51.649291 CS Dly: 1 (0~32)
6673 12:47:51.649368
6674 12:47:51.652357 ----->DramcWriteLeveling(PI) begin...
6675 12:47:51.655957 ==
6676 12:47:51.658933 Dram Type= 6, Freq= 0, CH_1, rank 0
6677 12:47:51.662577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 12:47:51.662672 ==
6679 12:47:51.665797 Write leveling (Byte 0): 40 => 8
6680 12:47:51.668931 Write leveling (Byte 1): 40 => 8
6681 12:47:51.669015 DramcWriteLeveling(PI) end<-----
6682 12:47:51.672682
6683 12:47:51.672787 ==
6684 12:47:51.675749 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 12:47:51.678877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 12:47:51.678998 ==
6687 12:47:51.682383 [Gating] SW mode calibration
6688 12:47:51.689144 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6689 12:47:51.692690 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6690 12:47:51.699118 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6691 12:47:51.702583 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6692 12:47:51.705637 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6693 12:47:51.712426 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6694 12:47:51.715646 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6695 12:47:51.719099 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 12:47:51.726327 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 12:47:51.729343 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 12:47:51.732528 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6699 12:47:51.736219 Total UI for P1: 0, mck2ui 16
6700 12:47:51.739370 best dqsien dly found for B0: ( 0, 14, 24)
6701 12:47:51.742523 Total UI for P1: 0, mck2ui 16
6702 12:47:51.746306 best dqsien dly found for B1: ( 0, 14, 24)
6703 12:47:51.749451 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6704 12:47:51.752595 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6705 12:47:51.752898
6706 12:47:51.756115 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6707 12:47:51.763014 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6708 12:47:51.763312 [Gating] SW calibration Done
6709 12:47:51.763554 ==
6710 12:47:51.765981 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 12:47:51.773038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 12:47:51.773392 ==
6713 12:47:51.773688 RX Vref Scan: 0
6714 12:47:51.773933
6715 12:47:51.776261 RX Vref 0 -> 0, step: 1
6716 12:47:51.776550
6717 12:47:51.779835 RX Delay -410 -> 252, step: 16
6718 12:47:51.782969 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6719 12:47:51.786023 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6720 12:47:51.792583 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6721 12:47:51.796203 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6722 12:47:51.799184 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6723 12:47:51.802792 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6724 12:47:51.809194 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6725 12:47:51.812791 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6726 12:47:51.815877 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6727 12:47:51.819000 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6728 12:47:51.825753 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6729 12:47:51.829139 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6730 12:47:51.832425 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6731 12:47:51.836135 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6732 12:47:51.842389 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6733 12:47:51.846058 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6734 12:47:51.846443 ==
6735 12:47:51.849107 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 12:47:51.852173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 12:47:51.852277 ==
6738 12:47:51.855849 DQS Delay:
6739 12:47:51.855938 DQS0 = 51, DQS1 = 59
6740 12:47:51.858964 DQM Delay:
6741 12:47:51.859066 DQM0 = 19, DQM1 = 16
6742 12:47:51.859158 DQ Delay:
6743 12:47:51.862173 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6744 12:47:51.865771 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6745 12:47:51.868997 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6746 12:47:51.872579 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6747 12:47:51.872703
6748 12:47:51.872775
6749 12:47:51.872843 ==
6750 12:47:51.876061 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 12:47:51.882376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 12:47:51.882455 ==
6753 12:47:51.882521
6754 12:47:51.882581
6755 12:47:51.882644 TX Vref Scan disable
6756 12:47:51.885552 == TX Byte 0 ==
6757 12:47:51.889219 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6758 12:47:51.892994 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6759 12:47:51.895654 == TX Byte 1 ==
6760 12:47:51.899214 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6761 12:47:51.902416 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6762 12:47:51.902531 ==
6763 12:47:51.905974 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 12:47:51.912575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 12:47:51.912717 ==
6766 12:47:51.912794
6767 12:47:51.912863
6768 12:47:51.912928 TX Vref Scan disable
6769 12:47:51.916037 == TX Byte 0 ==
6770 12:47:51.918943 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6771 12:47:51.922680 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6772 12:47:51.925782 == TX Byte 1 ==
6773 12:47:51.929073 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6774 12:47:51.932789 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6775 12:47:51.932897
6776 12:47:51.935824 [DATLAT]
6777 12:47:51.935932 Freq=400, CH1 RK0
6778 12:47:51.936017
6779 12:47:51.939255 DATLAT Default: 0xf
6780 12:47:51.939376 0, 0xFFFF, sum = 0
6781 12:47:51.942453 1, 0xFFFF, sum = 0
6782 12:47:51.942577 2, 0xFFFF, sum = 0
6783 12:47:51.945783 3, 0xFFFF, sum = 0
6784 12:47:51.945889 4, 0xFFFF, sum = 0
6785 12:47:51.949344 5, 0xFFFF, sum = 0
6786 12:47:51.949485 6, 0xFFFF, sum = 0
6787 12:47:51.952349 7, 0xFFFF, sum = 0
6788 12:47:51.952453 8, 0xFFFF, sum = 0
6789 12:47:51.956142 9, 0xFFFF, sum = 0
6790 12:47:51.956244 10, 0xFFFF, sum = 0
6791 12:47:51.959232 11, 0xFFFF, sum = 0
6792 12:47:51.959343 12, 0xFFFF, sum = 0
6793 12:47:51.962311 13, 0x0, sum = 1
6794 12:47:51.962427 14, 0x0, sum = 2
6795 12:47:51.966128 15, 0x0, sum = 3
6796 12:47:51.966245 16, 0x0, sum = 4
6797 12:47:51.969354 best_step = 14
6798 12:47:51.969457
6799 12:47:51.969554 ==
6800 12:47:51.972476 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 12:47:51.976113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 12:47:51.976214 ==
6803 12:47:51.979535 RX Vref Scan: 1
6804 12:47:51.979636
6805 12:47:51.979727 RX Vref 0 -> 0, step: 1
6806 12:47:51.979816
6807 12:47:51.982362 RX Delay -359 -> 252, step: 8
6808 12:47:51.982462
6809 12:47:51.985757 Set Vref, RX VrefLevel [Byte0]: 56
6810 12:47:51.989094 [Byte1]: 54
6811 12:47:51.994210
6812 12:47:51.994328 Final RX Vref Byte 0 = 56 to rank0
6813 12:47:51.997297 Final RX Vref Byte 1 = 54 to rank0
6814 12:47:52.000800 Final RX Vref Byte 0 = 56 to rank1
6815 12:47:52.004049 Final RX Vref Byte 1 = 54 to rank1==
6816 12:47:52.007467 Dram Type= 6, Freq= 0, CH_1, rank 0
6817 12:47:52.014073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 12:47:52.014204 ==
6819 12:47:52.014275 DQS Delay:
6820 12:47:52.014338 DQS0 = 48, DQS1 = 60
6821 12:47:52.017103 DQM Delay:
6822 12:47:52.017201 DQM0 = 13, DQM1 = 13
6823 12:47:52.020742 DQ Delay:
6824 12:47:52.024177 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6825 12:47:52.024262 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6826 12:47:52.027685 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6827 12:47:52.030688 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6828 12:47:52.030795
6829 12:47:52.030862
6830 12:47:52.040770 [DQSOSCAuto] RK0, (LSB)MR18= 0x8d35, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6831 12:47:52.044389 CH1 RK0: MR19=C0C, MR18=8D35
6832 12:47:52.050916 CH1_RK0: MR19=0xC0C, MR18=0x8D35, DQSOSC=392, MR23=63, INC=384, DEC=256
6833 12:47:52.050997 ==
6834 12:47:52.054298 Dram Type= 6, Freq= 0, CH_1, rank 1
6835 12:47:52.057564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 12:47:52.057652 ==
6837 12:47:52.061116 [Gating] SW mode calibration
6838 12:47:52.067325 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6839 12:47:52.071119 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6840 12:47:52.077400 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6841 12:47:52.080674 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6842 12:47:52.084140 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6843 12:47:52.090925 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6844 12:47:52.094440 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6845 12:47:52.097781 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 12:47:52.104362 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 12:47:52.108036 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 12:47:52.111023 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6849 12:47:52.114298 Total UI for P1: 0, mck2ui 16
6850 12:47:52.117607 best dqsien dly found for B0: ( 0, 14, 24)
6851 12:47:52.121041 Total UI for P1: 0, mck2ui 16
6852 12:47:52.124585 best dqsien dly found for B1: ( 0, 14, 24)
6853 12:47:52.127654 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6854 12:47:52.131210 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6855 12:47:52.131336
6856 12:47:52.134563 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6857 12:47:52.141396 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6858 12:47:52.141550 [Gating] SW calibration Done
6859 12:47:52.141682 ==
6860 12:47:52.144438 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 12:47:52.151282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 12:47:52.151413 ==
6863 12:47:52.151508 RX Vref Scan: 0
6864 12:47:52.151593
6865 12:47:52.154338 RX Vref 0 -> 0, step: 1
6866 12:47:52.154460
6867 12:47:52.158061 RX Delay -410 -> 252, step: 16
6868 12:47:52.161027 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6869 12:47:52.164549 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6870 12:47:52.171433 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6871 12:47:52.174560 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6872 12:47:52.177578 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6873 12:47:52.181357 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6874 12:47:52.187574 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6875 12:47:52.191156 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6876 12:47:52.194706 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6877 12:47:52.197687 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6878 12:47:52.201255 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6879 12:47:52.208200 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6880 12:47:52.211286 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6881 12:47:52.214390 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6882 12:47:52.218188 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6883 12:47:52.224585 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6884 12:47:52.224711 ==
6885 12:47:52.228092 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 12:47:52.231507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 12:47:52.231612 ==
6888 12:47:52.231709 DQS Delay:
6889 12:47:52.234925 DQS0 = 43, DQS1 = 59
6890 12:47:52.235009 DQM Delay:
6891 12:47:52.237978 DQM0 = 9, DQM1 = 19
6892 12:47:52.238061 DQ Delay:
6893 12:47:52.241302 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6894 12:47:52.244891 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6895 12:47:52.248019 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6896 12:47:52.251168 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6897 12:47:52.251275
6898 12:47:52.251368
6899 12:47:52.251458 ==
6900 12:47:52.254884 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 12:47:52.257998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 12:47:52.258104 ==
6903 12:47:52.258198
6904 12:47:52.258287
6905 12:47:52.261720 TX Vref Scan disable
6906 12:47:52.261830 == TX Byte 0 ==
6907 12:47:52.268412 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6908 12:47:52.271578 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6909 12:47:52.271695 == TX Byte 1 ==
6910 12:47:52.278312 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6911 12:47:52.281477 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6912 12:47:52.281595 ==
6913 12:47:52.285283 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 12:47:52.288224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 12:47:52.288329 ==
6916 12:47:52.288442
6917 12:47:52.288544
6918 12:47:52.291908 TX Vref Scan disable
6919 12:47:52.292018 == TX Byte 0 ==
6920 12:47:52.298644 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6921 12:47:52.301542 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6922 12:47:52.301669 == TX Byte 1 ==
6923 12:47:52.308280 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6924 12:47:52.311874 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6925 12:47:52.311983
6926 12:47:52.312076 [DATLAT]
6927 12:47:52.315229 Freq=400, CH1 RK1
6928 12:47:52.315336
6929 12:47:52.315430 DATLAT Default: 0xe
6930 12:47:52.318409 0, 0xFFFF, sum = 0
6931 12:47:52.318525 1, 0xFFFF, sum = 0
6932 12:47:52.321527 2, 0xFFFF, sum = 0
6933 12:47:52.321634 3, 0xFFFF, sum = 0
6934 12:47:52.325321 4, 0xFFFF, sum = 0
6935 12:47:52.325452 5, 0xFFFF, sum = 0
6936 12:47:52.328353 6, 0xFFFF, sum = 0
6937 12:47:52.328465 7, 0xFFFF, sum = 0
6938 12:47:52.331398 8, 0xFFFF, sum = 0
6939 12:47:52.331508 9, 0xFFFF, sum = 0
6940 12:47:52.335000 10, 0xFFFF, sum = 0
6941 12:47:52.338504 11, 0xFFFF, sum = 0
6942 12:47:52.338611 12, 0xFFFF, sum = 0
6943 12:47:52.342041 13, 0x0, sum = 1
6944 12:47:52.342151 14, 0x0, sum = 2
6945 12:47:52.342257 15, 0x0, sum = 3
6946 12:47:52.345162 16, 0x0, sum = 4
6947 12:47:52.345274 best_step = 14
6948 12:47:52.345379
6949 12:47:52.345479 ==
6950 12:47:52.348634 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 12:47:52.355376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 12:47:52.355515 ==
6953 12:47:52.355615 RX Vref Scan: 0
6954 12:47:52.355713
6955 12:47:52.358447 RX Vref 0 -> 0, step: 1
6956 12:47:52.358548
6957 12:47:52.362163 RX Delay -359 -> 252, step: 8
6958 12:47:52.368471 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6959 12:47:52.372274 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6960 12:47:52.375360 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6961 12:47:52.378829 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6962 12:47:52.385273 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6963 12:47:52.388364 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6964 12:47:52.392104 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6965 12:47:52.395163 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6966 12:47:52.402221 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6967 12:47:52.405253 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6968 12:47:52.409032 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6969 12:47:52.412116 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6970 12:47:52.418798 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6971 12:47:52.422197 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6972 12:47:52.425157 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6973 12:47:52.429080 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6974 12:47:52.429217 ==
6975 12:47:52.432193 Dram Type= 6, Freq= 0, CH_1, rank 1
6976 12:47:52.438889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6977 12:47:52.439003 ==
6978 12:47:52.439097 DQS Delay:
6979 12:47:52.442034 DQS0 = 52, DQS1 = 56
6980 12:47:52.442136 DQM Delay:
6981 12:47:52.445523 DQM0 = 12, DQM1 = 9
6982 12:47:52.445623 DQ Delay:
6983 12:47:52.448553 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6984 12:47:52.452181 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6985 12:47:52.452292 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6986 12:47:52.455275 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6987 12:47:52.458725
6988 12:47:52.458833
6989 12:47:52.465639 [DQSOSCAuto] RK1, (LSB)MR18= 0x7d93, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 394 ps
6990 12:47:52.468883 CH1 RK1: MR19=C0C, MR18=7D93
6991 12:47:52.475662 CH1_RK1: MR19=0xC0C, MR18=0x7D93, DQSOSC=391, MR23=63, INC=386, DEC=257
6992 12:47:52.478727 [RxdqsGatingPostProcess] freq 400
6993 12:47:52.482354 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6994 12:47:52.485490 best DQS0 dly(2T, 0.5T) = (0, 10)
6995 12:47:52.489081 best DQS1 dly(2T, 0.5T) = (0, 10)
6996 12:47:52.491950 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6997 12:47:52.495404 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6998 12:47:52.498531 best DQS0 dly(2T, 0.5T) = (0, 10)
6999 12:47:52.502286 best DQS1 dly(2T, 0.5T) = (0, 10)
7000 12:47:52.505279 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7001 12:47:52.508788 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7002 12:47:52.512328 Pre-setting of DQS Precalculation
7003 12:47:52.515416 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7004 12:47:52.522165 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7005 12:47:52.531922 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7006 12:47:52.532051
7007 12:47:52.532133
7008 12:47:52.532206 [Calibration Summary] 800 Mbps
7009 12:47:52.535204 CH 0, Rank 0
7010 12:47:52.535327 SW Impedance : PASS
7011 12:47:52.538785 DUTY Scan : NO K
7012 12:47:52.541834 ZQ Calibration : PASS
7013 12:47:52.542005 Jitter Meter : NO K
7014 12:47:52.545645 CBT Training : PASS
7015 12:47:52.548626 Write leveling : PASS
7016 12:47:52.548746 RX DQS gating : PASS
7017 12:47:52.552440 RX DQ/DQS(RDDQC) : PASS
7018 12:47:52.555484 TX DQ/DQS : PASS
7019 12:47:52.555622 RX DATLAT : PASS
7020 12:47:52.558885 RX DQ/DQS(Engine): PASS
7021 12:47:52.561979 TX OE : NO K
7022 12:47:52.562124 All Pass.
7023 12:47:52.562244
7024 12:47:52.562369 CH 0, Rank 1
7025 12:47:52.565682 SW Impedance : PASS
7026 12:47:52.568649 DUTY Scan : NO K
7027 12:47:52.568768 ZQ Calibration : PASS
7028 12:47:52.572320 Jitter Meter : NO K
7029 12:47:52.572471 CBT Training : PASS
7030 12:47:52.575377 Write leveling : NO K
7031 12:47:52.578999 RX DQS gating : PASS
7032 12:47:52.579113 RX DQ/DQS(RDDQC) : PASS
7033 12:47:52.581993 TX DQ/DQS : PASS
7034 12:47:52.585691 RX DATLAT : PASS
7035 12:47:52.585799 RX DQ/DQS(Engine): PASS
7036 12:47:52.588801 TX OE : NO K
7037 12:47:52.588910 All Pass.
7038 12:47:52.589038
7039 12:47:52.591924 CH 1, Rank 0
7040 12:47:52.592035 SW Impedance : PASS
7041 12:47:52.595661 DUTY Scan : NO K
7042 12:47:52.599203 ZQ Calibration : PASS
7043 12:47:52.599293 Jitter Meter : NO K
7044 12:47:52.602449 CBT Training : PASS
7045 12:47:52.605673 Write leveling : PASS
7046 12:47:52.605779 RX DQS gating : PASS
7047 12:47:52.608987 RX DQ/DQS(RDDQC) : PASS
7048 12:47:52.609096 TX DQ/DQS : PASS
7049 12:47:52.612389 RX DATLAT : PASS
7050 12:47:52.615432 RX DQ/DQS(Engine): PASS
7051 12:47:52.615553 TX OE : NO K
7052 12:47:52.619168 All Pass.
7053 12:47:52.619269
7054 12:47:52.619347 CH 1, Rank 1
7055 12:47:52.622183 SW Impedance : PASS
7056 12:47:52.622311 DUTY Scan : NO K
7057 12:47:52.625870 ZQ Calibration : PASS
7058 12:47:52.628968 Jitter Meter : NO K
7059 12:47:52.629097 CBT Training : PASS
7060 12:47:52.632645 Write leveling : NO K
7061 12:47:52.635586 RX DQS gating : PASS
7062 12:47:52.635727 RX DQ/DQS(RDDQC) : PASS
7063 12:47:52.639072 TX DQ/DQS : PASS
7064 12:47:52.642460 RX DATLAT : PASS
7065 12:47:52.642611 RX DQ/DQS(Engine): PASS
7066 12:47:52.645723 TX OE : NO K
7067 12:47:52.645879 All Pass.
7068 12:47:52.646024
7069 12:47:52.649223 DramC Write-DBI off
7070 12:47:52.652784 PER_BANK_REFRESH: Hybrid Mode
7071 12:47:52.652961 TX_TRACKING: ON
7072 12:47:52.662541 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7073 12:47:52.666058 [FAST_K] Save calibration result to emmc
7074 12:47:52.669009 dramc_set_vcore_voltage set vcore to 725000
7075 12:47:52.669154 Read voltage for 1600, 0
7076 12:47:52.672840 Vio18 = 0
7077 12:47:52.673030 Vcore = 725000
7078 12:47:52.673191 Vdram = 0
7079 12:47:52.676226 Vddq = 0
7080 12:47:52.676392 Vmddr = 0
7081 12:47:52.679621 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7082 12:47:52.686413 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7083 12:47:52.689394 MEM_TYPE=3, freq_sel=13
7084 12:47:52.692523 sv_algorithm_assistance_LP4_3733
7085 12:47:52.696345 ============ PULL DRAM RESETB DOWN ============
7086 12:47:52.699421 ========== PULL DRAM RESETB DOWN end =========
7087 12:47:52.706139 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7088 12:47:52.706257 ===================================
7089 12:47:52.709613 LPDDR4 DRAM CONFIGURATION
7090 12:47:52.712986 ===================================
7091 12:47:52.716413 EX_ROW_EN[0] = 0x0
7092 12:47:52.716538 EX_ROW_EN[1] = 0x0
7093 12:47:52.719681 LP4Y_EN = 0x0
7094 12:47:52.719785 WORK_FSP = 0x1
7095 12:47:52.722899 WL = 0x5
7096 12:47:52.723004 RL = 0x5
7097 12:47:52.726074 BL = 0x2
7098 12:47:52.726183 RPST = 0x0
7099 12:47:52.729695 RD_PRE = 0x0
7100 12:47:52.729779 WR_PRE = 0x1
7101 12:47:52.732923 WR_PST = 0x1
7102 12:47:52.733034 DBI_WR = 0x0
7103 12:47:52.736056 DBI_RD = 0x0
7104 12:47:52.739882 OTF = 0x1
7105 12:47:52.740015 ===================================
7106 12:47:52.742889 ===================================
7107 12:47:52.746545 ANA top config
7108 12:47:52.749506 ===================================
7109 12:47:52.753046 DLL_ASYNC_EN = 0
7110 12:47:52.753137 ALL_SLAVE_EN = 0
7111 12:47:52.756510 NEW_RANK_MODE = 1
7112 12:47:52.759850 DLL_IDLE_MODE = 1
7113 12:47:52.762966 LP45_APHY_COMB_EN = 1
7114 12:47:52.766121 TX_ODT_DIS = 0
7115 12:47:52.766246 NEW_8X_MODE = 1
7116 12:47:52.769653 ===================================
7117 12:47:52.772690 ===================================
7118 12:47:52.776344 data_rate = 3200
7119 12:47:52.779455 CKR = 1
7120 12:47:52.783090 DQ_P2S_RATIO = 8
7121 12:47:52.786429 ===================================
7122 12:47:52.789463 CA_P2S_RATIO = 8
7123 12:47:52.789557 DQ_CA_OPEN = 0
7124 12:47:52.792971 DQ_SEMI_OPEN = 0
7125 12:47:52.796115 CA_SEMI_OPEN = 0
7126 12:47:52.799950 CA_FULL_RATE = 0
7127 12:47:52.803095 DQ_CKDIV4_EN = 0
7128 12:47:52.806328 CA_CKDIV4_EN = 0
7129 12:47:52.806492 CA_PREDIV_EN = 0
7130 12:47:52.809981 PH8_DLY = 12
7131 12:47:52.813122 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7132 12:47:52.816215 DQ_AAMCK_DIV = 4
7133 12:47:52.819610 CA_AAMCK_DIV = 4
7134 12:47:52.823075 CA_ADMCK_DIV = 4
7135 12:47:52.823209 DQ_TRACK_CA_EN = 0
7136 12:47:52.826367 CA_PICK = 1600
7137 12:47:52.829825 CA_MCKIO = 1600
7138 12:47:52.832964 MCKIO_SEMI = 0
7139 12:47:52.836623 PLL_FREQ = 3068
7140 12:47:52.839735 DQ_UI_PI_RATIO = 32
7141 12:47:52.843572 CA_UI_PI_RATIO = 0
7142 12:47:52.846668 ===================================
7143 12:47:52.850208 ===================================
7144 12:47:52.850313 memory_type:LPDDR4
7145 12:47:52.853290 GP_NUM : 10
7146 12:47:52.853409 SRAM_EN : 1
7147 12:47:52.856857 MD32_EN : 0
7148 12:47:52.859924 ===================================
7149 12:47:52.863522 [ANA_INIT] >>>>>>>>>>>>>>
7150 12:47:52.866580 <<<<<< [CONFIGURE PHASE]: ANA_TX
7151 12:47:52.869877 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7152 12:47:52.873274 ===================================
7153 12:47:52.876731 data_rate = 3200,PCW = 0X7600
7154 12:47:52.876814 ===================================
7155 12:47:52.883262 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7156 12:47:52.886470 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7157 12:47:52.893191 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7158 12:47:52.896689 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7159 12:47:52.899674 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7160 12:47:52.903338 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7161 12:47:52.906566 [ANA_INIT] flow start
7162 12:47:52.909789 [ANA_INIT] PLL >>>>>>>>
7163 12:47:52.909915 [ANA_INIT] PLL <<<<<<<<
7164 12:47:52.912832 [ANA_INIT] MIDPI >>>>>>>>
7165 12:47:52.916573 [ANA_INIT] MIDPI <<<<<<<<
7166 12:47:52.916713 [ANA_INIT] DLL >>>>>>>>
7167 12:47:52.919624 [ANA_INIT] DLL <<<<<<<<
7168 12:47:52.923168 [ANA_INIT] flow end
7169 12:47:52.926595 ============ LP4 DIFF to SE enter ============
7170 12:47:52.929588 ============ LP4 DIFF to SE exit ============
7171 12:47:52.933073 [ANA_INIT] <<<<<<<<<<<<<
7172 12:47:52.936235 [Flow] Enable top DCM control >>>>>
7173 12:47:52.940013 [Flow] Enable top DCM control <<<<<
7174 12:47:52.943084 Enable DLL master slave shuffle
7175 12:47:52.946128 ==============================================================
7176 12:47:52.949809 Gating Mode config
7177 12:47:52.956512 ==============================================================
7178 12:47:52.956681 Config description:
7179 12:47:52.966776 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7180 12:47:52.972988 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7181 12:47:52.976551 SELPH_MODE 0: By rank 1: By Phase
7182 12:47:52.983596 ==============================================================
7183 12:47:52.986208 GAT_TRACK_EN = 1
7184 12:47:52.989539 RX_GATING_MODE = 2
7185 12:47:52.993190 RX_GATING_TRACK_MODE = 2
7186 12:47:52.996309 SELPH_MODE = 1
7187 12:47:52.999935 PICG_EARLY_EN = 1
7188 12:47:53.000052 VALID_LAT_VALUE = 1
7189 12:47:53.006821 ==============================================================
7190 12:47:53.009978 Enter into Gating configuration >>>>
7191 12:47:53.013076 Exit from Gating configuration <<<<
7192 12:47:53.016896 Enter into DVFS_PRE_config >>>>>
7193 12:47:53.026811 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7194 12:47:53.029841 Exit from DVFS_PRE_config <<<<<
7195 12:47:53.033386 Enter into PICG configuration >>>>
7196 12:47:53.036717 Exit from PICG configuration <<<<
7197 12:47:53.040130 [RX_INPUT] configuration >>>>>
7198 12:47:53.043380 [RX_INPUT] configuration <<<<<
7199 12:47:53.047007 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7200 12:47:53.053175 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7201 12:47:53.060094 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7202 12:47:53.066753 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7203 12:47:53.073491 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7204 12:47:53.076546 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7205 12:47:53.083320 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7206 12:47:53.087026 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7207 12:47:53.090057 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7208 12:47:53.093557 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7209 12:47:53.097031 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7210 12:47:53.103667 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7211 12:47:53.106600 ===================================
7212 12:47:53.109970 LPDDR4 DRAM CONFIGURATION
7213 12:47:53.110065 ===================================
7214 12:47:53.113408 EX_ROW_EN[0] = 0x0
7215 12:47:53.116934 EX_ROW_EN[1] = 0x0
7216 12:47:53.117023 LP4Y_EN = 0x0
7217 12:47:53.119879 WORK_FSP = 0x1
7218 12:47:53.119993 WL = 0x5
7219 12:47:53.123608 RL = 0x5
7220 12:47:53.123713 BL = 0x2
7221 12:47:53.126743 RPST = 0x0
7222 12:47:53.126855 RD_PRE = 0x0
7223 12:47:53.129870 WR_PRE = 0x1
7224 12:47:53.129993 WR_PST = 0x1
7225 12:47:53.133632 DBI_WR = 0x0
7226 12:47:53.133719 DBI_RD = 0x0
7227 12:47:53.136622 OTF = 0x1
7228 12:47:53.140189 ===================================
7229 12:47:53.143622 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7230 12:47:53.146706 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7231 12:47:53.153651 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7232 12:47:53.156533 ===================================
7233 12:47:53.156663 LPDDR4 DRAM CONFIGURATION
7234 12:47:53.160291 ===================================
7235 12:47:53.163262 EX_ROW_EN[0] = 0x10
7236 12:47:53.166901 EX_ROW_EN[1] = 0x0
7237 12:47:53.167015 LP4Y_EN = 0x0
7238 12:47:53.170412 WORK_FSP = 0x1
7239 12:47:53.170528 WL = 0x5
7240 12:47:53.173412 RL = 0x5
7241 12:47:53.173526 BL = 0x2
7242 12:47:53.177072 RPST = 0x0
7243 12:47:53.177192 RD_PRE = 0x0
7244 12:47:53.180255 WR_PRE = 0x1
7245 12:47:53.180365 WR_PST = 0x1
7246 12:47:53.183358 DBI_WR = 0x0
7247 12:47:53.183461 DBI_RD = 0x0
7248 12:47:53.187083 OTF = 0x1
7249 12:47:53.190112 ===================================
7250 12:47:53.196995 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7251 12:47:53.197112 ==
7252 12:47:53.200010 Dram Type= 6, Freq= 0, CH_0, rank 0
7253 12:47:53.203563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7254 12:47:53.203680 ==
7255 12:47:53.207129 [Duty_Offset_Calibration]
7256 12:47:53.207246 B0:2 B1:-1 CA:1
7257 12:47:53.207344
7258 12:47:53.210155 [DutyScan_Calibration_Flow] k_type=0
7259 12:47:53.219497
7260 12:47:53.219641 ==CLK 0==
7261 12:47:53.222880 Final CLK duty delay cell = -4
7262 12:47:53.226442 [-4] MAX Duty = 5031%(X100), DQS PI = 6
7263 12:47:53.229462 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7264 12:47:53.233111 [-4] AVG Duty = 4937%(X100)
7265 12:47:53.233212
7266 12:47:53.236291 CH0 CLK Duty spec in!! Max-Min= 187%
7267 12:47:53.239892 [DutyScan_Calibration_Flow] ====Done====
7268 12:47:53.240003
7269 12:47:53.243081 [DutyScan_Calibration_Flow] k_type=1
7270 12:47:53.259279
7271 12:47:53.259439 ==DQS 0 ==
7272 12:47:53.262469 Final DQS duty delay cell = 0
7273 12:47:53.266028 [0] MAX Duty = 5125%(X100), DQS PI = 20
7274 12:47:53.269087 [0] MIN Duty = 5000%(X100), DQS PI = 14
7275 12:47:53.269177 [0] AVG Duty = 5062%(X100)
7276 12:47:53.272562
7277 12:47:53.272685 ==DQS 1 ==
7278 12:47:53.275722 Final DQS duty delay cell = -4
7279 12:47:53.279424 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7280 12:47:53.282507 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7281 12:47:53.285658 [-4] AVG Duty = 5046%(X100)
7282 12:47:53.285772
7283 12:47:53.289345 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7284 12:47:53.289453
7285 12:47:53.292407 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7286 12:47:53.295787 [DutyScan_Calibration_Flow] ====Done====
7287 12:47:53.295880
7288 12:47:53.298846 [DutyScan_Calibration_Flow] k_type=3
7289 12:47:53.316387
7290 12:47:53.316558 ==DQM 0 ==
7291 12:47:53.319996 Final DQM duty delay cell = 0
7292 12:47:53.322928 [0] MAX Duty = 5000%(X100), DQS PI = 40
7293 12:47:53.326657 [0] MIN Duty = 4875%(X100), DQS PI = 6
7294 12:47:53.326768 [0] AVG Duty = 4937%(X100)
7295 12:47:53.329784
7296 12:47:53.329904 ==DQM 1 ==
7297 12:47:53.333201 Final DQM duty delay cell = 0
7298 12:47:53.336942 [0] MAX Duty = 5218%(X100), DQS PI = 58
7299 12:47:53.340137 [0] MIN Duty = 4969%(X100), DQS PI = 20
7300 12:47:53.340260 [0] AVG Duty = 5093%(X100)
7301 12:47:53.343237
7302 12:47:53.346384 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7303 12:47:53.346463
7304 12:47:53.350088 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7305 12:47:53.353285 [DutyScan_Calibration_Flow] ====Done====
7306 12:47:53.353407
7307 12:47:53.356290 [DutyScan_Calibration_Flow] k_type=2
7308 12:47:53.372769
7309 12:47:53.372919 ==DQ 0 ==
7310 12:47:53.376040 Final DQ duty delay cell = -4
7311 12:47:53.379725 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7312 12:47:53.382970 [-4] MIN Duty = 4844%(X100), DQS PI = 28
7313 12:47:53.386059 [-4] AVG Duty = 4922%(X100)
7314 12:47:53.386181
7315 12:47:53.386277 ==DQ 1 ==
7316 12:47:53.389198 Final DQ duty delay cell = 0
7317 12:47:53.392915 [0] MAX Duty = 5000%(X100), DQS PI = 0
7318 12:47:53.395991 [0] MIN Duty = 4907%(X100), DQS PI = 18
7319 12:47:53.396096 [0] AVG Duty = 4953%(X100)
7320 12:47:53.396193
7321 12:47:53.399779 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7322 12:47:53.402844
7323 12:47:53.406680 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7324 12:47:53.409792 [DutyScan_Calibration_Flow] ====Done====
7325 12:47:53.409884 ==
7326 12:47:53.412954 Dram Type= 6, Freq= 0, CH_1, rank 0
7327 12:47:53.416234 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7328 12:47:53.416354 ==
7329 12:47:53.419898 [Duty_Offset_Calibration]
7330 12:47:53.420002 B0:1 B1:1 CA:2
7331 12:47:53.420094
7332 12:47:53.423048 [DutyScan_Calibration_Flow] k_type=0
7333 12:47:53.433424
7334 12:47:53.433553 ==CLK 0==
7335 12:47:53.436375 Final CLK duty delay cell = 0
7336 12:47:53.439966 [0] MAX Duty = 5187%(X100), DQS PI = 24
7337 12:47:53.443455 [0] MIN Duty = 4938%(X100), DQS PI = 56
7338 12:47:53.443543 [0] AVG Duty = 5062%(X100)
7339 12:47:53.446660
7340 12:47:53.449755 CH1 CLK Duty spec in!! Max-Min= 249%
7341 12:47:53.453510 [DutyScan_Calibration_Flow] ====Done====
7342 12:47:53.453613
7343 12:47:53.456603 [DutyScan_Calibration_Flow] k_type=1
7344 12:47:53.473039
7345 12:47:53.473208 ==DQS 0 ==
7346 12:47:53.475988 Final DQS duty delay cell = 0
7347 12:47:53.479672 [0] MAX Duty = 5062%(X100), DQS PI = 20
7348 12:47:53.483053 [0] MIN Duty = 4813%(X100), DQS PI = 50
7349 12:47:53.483178 [0] AVG Duty = 4937%(X100)
7350 12:47:53.486126
7351 12:47:53.486244 ==DQS 1 ==
7352 12:47:53.489783 Final DQS duty delay cell = 0
7353 12:47:53.493078 [0] MAX Duty = 5031%(X100), DQS PI = 34
7354 12:47:53.496010 [0] MIN Duty = 4938%(X100), DQS PI = 30
7355 12:47:53.496118 [0] AVG Duty = 4984%(X100)
7356 12:47:53.499753
7357 12:47:53.502745 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7358 12:47:53.502859
7359 12:47:53.505952 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7360 12:47:53.509694 [DutyScan_Calibration_Flow] ====Done====
7361 12:47:53.509810
7362 12:47:53.512617 [DutyScan_Calibration_Flow] k_type=3
7363 12:47:53.529828
7364 12:47:53.530003 ==DQM 0 ==
7365 12:47:53.533175 Final DQM duty delay cell = 0
7366 12:47:53.536156 [0] MAX Duty = 5187%(X100), DQS PI = 20
7367 12:47:53.539909 [0] MIN Duty = 4813%(X100), DQS PI = 50
7368 12:47:53.543063 [0] AVG Duty = 5000%(X100)
7369 12:47:53.543189
7370 12:47:53.543294 ==DQM 1 ==
7371 12:47:53.546743 Final DQM duty delay cell = 0
7372 12:47:53.549696 [0] MAX Duty = 5125%(X100), DQS PI = 8
7373 12:47:53.553339 [0] MIN Duty = 4875%(X100), DQS PI = 20
7374 12:47:53.553427 [0] AVG Duty = 5000%(X100)
7375 12:47:53.556352
7376 12:47:53.559983 CH1 DQM 0 Duty spec in!! Max-Min= 374%
7377 12:47:53.560072
7378 12:47:53.563178 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7379 12:47:53.566324 [DutyScan_Calibration_Flow] ====Done====
7380 12:47:53.566449
7381 12:47:53.569863 [DutyScan_Calibration_Flow] k_type=2
7382 12:47:53.586424
7383 12:47:53.586598 ==DQ 0 ==
7384 12:47:53.590009 Final DQ duty delay cell = 0
7385 12:47:53.593595 [0] MAX Duty = 5156%(X100), DQS PI = 20
7386 12:47:53.597026 [0] MIN Duty = 4907%(X100), DQS PI = 52
7387 12:47:53.597193 [0] AVG Duty = 5031%(X100)
7388 12:47:53.597334
7389 12:47:53.600432 ==DQ 1 ==
7390 12:47:53.603599 Final DQ duty delay cell = 0
7391 12:47:53.606514 [0] MAX Duty = 5124%(X100), DQS PI = 40
7392 12:47:53.610350 [0] MIN Duty = 5031%(X100), DQS PI = 0
7393 12:47:53.610488 [0] AVG Duty = 5077%(X100)
7394 12:47:53.610644
7395 12:47:53.613143 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7396 12:47:53.613318
7397 12:47:53.616747 CH1 DQ 1 Duty spec in!! Max-Min= 93%
7398 12:47:53.623680 [DutyScan_Calibration_Flow] ====Done====
7399 12:47:53.626645 nWR fixed to 30
7400 12:47:53.626815 [ModeRegInit_LP4] CH0 RK0
7401 12:47:53.630098 [ModeRegInit_LP4] CH0 RK1
7402 12:47:53.633218 [ModeRegInit_LP4] CH1 RK0
7403 12:47:53.633379 [ModeRegInit_LP4] CH1 RK1
7404 12:47:53.636676 match AC timing 5
7405 12:47:53.640176 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7406 12:47:53.643129 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7407 12:47:53.649777 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7408 12:47:53.653353 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7409 12:47:53.659823 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7410 12:47:53.659918 [MiockJmeterHQA]
7411 12:47:53.659986
7412 12:47:53.663620 [DramcMiockJmeter] u1RxGatingPI = 0
7413 12:47:53.663743 0 : 4366, 4140
7414 12:47:53.666792 4 : 4363, 4137
7415 12:47:53.666916 8 : 4253, 4026
7416 12:47:53.669777 12 : 4253, 4026
7417 12:47:53.669891 16 : 4252, 4026
7418 12:47:53.673413 20 : 4253, 4027
7419 12:47:53.673526 24 : 4363, 4138
7420 12:47:53.676998 28 : 4253, 4026
7421 12:47:53.677087 32 : 4365, 4140
7422 12:47:53.677155 36 : 4252, 4027
7423 12:47:53.679982 40 : 4253, 4027
7424 12:47:53.680067 44 : 4252, 4027
7425 12:47:53.683191 48 : 4363, 4137
7426 12:47:53.683279 52 : 4253, 4027
7427 12:47:53.686300 56 : 4363, 4137
7428 12:47:53.686392 60 : 4253, 4029
7429 12:47:53.686462 64 : 4250, 4027
7430 12:47:53.690066 68 : 4249, 4027
7431 12:47:53.690152 72 : 4250, 4027
7432 12:47:53.693143 76 : 4361, 4138
7433 12:47:53.693255 80 : 4250, 4027
7434 12:47:53.696281 84 : 4361, 4137
7435 12:47:53.696391 88 : 4250, 4027
7436 12:47:53.699924 92 : 4250, 4027
7437 12:47:53.700045 96 : 4250, 3469
7438 12:47:53.700141 100 : 4360, 0
7439 12:47:53.703704 104 : 4250, 0
7440 12:47:53.703789 108 : 4250, 0
7441 12:47:53.706635 112 : 4363, 0
7442 12:47:53.706730 116 : 4360, 0
7443 12:47:53.706803 120 : 4361, 0
7444 12:47:53.709638 124 : 4250, 0
7445 12:47:53.709741 128 : 4250, 0
7446 12:47:53.709816 132 : 4250, 0
7447 12:47:53.713098 136 : 4250, 0
7448 12:47:53.713190 140 : 4250, 0
7449 12:47:53.716437 144 : 4250, 0
7450 12:47:53.716563 148 : 4250, 0
7451 12:47:53.716691 152 : 4250, 0
7452 12:47:53.719622 156 : 4250, 0
7453 12:47:53.719739 160 : 4250, 0
7454 12:47:53.723302 164 : 4361, 0
7455 12:47:53.723426 168 : 4361, 0
7456 12:47:53.723545 172 : 4361, 0
7457 12:47:53.726427 176 : 4250, 0
7458 12:47:53.726544 180 : 4250, 0
7459 12:47:53.730084 184 : 4250, 0
7460 12:47:53.730168 188 : 4250, 0
7461 12:47:53.730235 192 : 4253, 0
7462 12:47:53.733026 196 : 4250, 0
7463 12:47:53.733122 200 : 4250, 0
7464 12:47:53.733191 204 : 4253, 0
7465 12:47:53.736574 208 : 4250, 0
7466 12:47:53.736710 212 : 4250, 168
7467 12:47:53.739860 216 : 4361, 3740
7468 12:47:53.739981 220 : 4363, 4138
7469 12:47:53.743263 224 : 4250, 4027
7470 12:47:53.743386 228 : 4363, 4140
7471 12:47:53.746631 232 : 4361, 4137
7472 12:47:53.746721 236 : 4250, 4027
7473 12:47:53.749676 240 : 4250, 4026
7474 12:47:53.749768 244 : 4250, 4027
7475 12:47:53.749854 248 : 4250, 4027
7476 12:47:53.753619 252 : 4252, 4029
7477 12:47:53.753733 256 : 4250, 4026
7478 12:47:53.756638 260 : 4250, 4027
7479 12:47:53.756751 264 : 4250, 4027
7480 12:47:53.759781 268 : 4361, 4138
7481 12:47:53.759892 272 : 4360, 4137
7482 12:47:53.763327 276 : 4248, 4024
7483 12:47:53.763443 280 : 4361, 4137
7484 12:47:53.766977 284 : 4361, 4138
7485 12:47:53.767095 288 : 4250, 4027
7486 12:47:53.769953 292 : 4250, 4026
7487 12:47:53.770062 296 : 4250, 4027
7488 12:47:53.770164 300 : 4250, 4027
7489 12:47:53.773092 304 : 4250, 4027
7490 12:47:53.773195 308 : 4250, 4026
7491 12:47:53.776861 312 : 4250, 4027
7492 12:47:53.776984 316 : 4250, 4027
7493 12:47:53.779865 320 : 4361, 4138
7494 12:47:53.779980 324 : 4360, 4137
7495 12:47:53.783520 328 : 4250, 4027
7496 12:47:53.783643 332 : 4361, 3061
7497 12:47:53.786593 336 : 4361, 66
7498 12:47:53.786712
7499 12:47:53.786809 MIOCK jitter meter ch=0
7500 12:47:53.786901
7501 12:47:53.790384 1T = (336-100) = 236 dly cells
7502 12:47:53.796621 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7503 12:47:53.796750 ==
7504 12:47:53.800339 Dram Type= 6, Freq= 0, CH_0, rank 0
7505 12:47:53.803332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7506 12:47:53.803448 ==
7507 12:47:53.809986 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7508 12:47:53.813590 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7509 12:47:53.816678 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7510 12:47:53.823573 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7511 12:47:53.832885 [CA 0] Center 44 (14~75) winsize 62
7512 12:47:53.836321 [CA 1] Center 44 (14~74) winsize 61
7513 12:47:53.839763 [CA 2] Center 39 (10~68) winsize 59
7514 12:47:53.843231 [CA 3] Center 39 (10~68) winsize 59
7515 12:47:53.846857 [CA 4] Center 37 (7~67) winsize 61
7516 12:47:53.849559 [CA 5] Center 37 (7~67) winsize 61
7517 12:47:53.849649
7518 12:47:53.853048 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7519 12:47:53.853131
7520 12:47:53.856353 [CATrainingPosCal] consider 1 rank data
7521 12:47:53.859995 u2DelayCellTimex100 = 275/100 ps
7522 12:47:53.863041 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7523 12:47:53.869962 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7524 12:47:53.873603 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7525 12:47:53.876494 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7526 12:47:53.880252 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7527 12:47:53.883227 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7528 12:47:53.883346
7529 12:47:53.886903 CA PerBit enable=1, Macro0, CA PI delay=37
7530 12:47:53.887037
7531 12:47:53.889803 [CBTSetCACLKResult] CA Dly = 37
7532 12:47:53.893680 CS Dly: 10 (0~41)
7533 12:47:53.896733 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7534 12:47:53.899766 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7535 12:47:53.899851 ==
7536 12:47:53.903633 Dram Type= 6, Freq= 0, CH_0, rank 1
7537 12:47:53.906651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 12:47:53.906766 ==
7539 12:47:53.913251 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7540 12:47:53.916833 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7541 12:47:53.923506 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7542 12:47:53.926626 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7543 12:47:53.937134 [CA 0] Center 43 (13~74) winsize 62
7544 12:47:53.940052 [CA 1] Center 43 (13~74) winsize 62
7545 12:47:53.943822 [CA 2] Center 39 (10~69) winsize 60
7546 12:47:53.947028 [CA 3] Center 38 (9~68) winsize 60
7547 12:47:53.950206 [CA 4] Center 37 (7~67) winsize 61
7548 12:47:53.953738 [CA 5] Center 37 (7~67) winsize 61
7549 12:47:53.953852
7550 12:47:53.957138 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7551 12:47:53.957246
7552 12:47:53.960500 [CATrainingPosCal] consider 2 rank data
7553 12:47:53.963778 u2DelayCellTimex100 = 275/100 ps
7554 12:47:53.967169 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7555 12:47:53.974047 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7556 12:47:53.977137 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7557 12:47:53.980614 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7558 12:47:53.984107 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7559 12:47:53.987061 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7560 12:47:53.987147
7561 12:47:53.990540 CA PerBit enable=1, Macro0, CA PI delay=37
7562 12:47:53.990657
7563 12:47:53.993625 [CBTSetCACLKResult] CA Dly = 37
7564 12:47:53.997340 CS Dly: 11 (0~44)
7565 12:47:54.000588 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7566 12:47:54.003711 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7567 12:47:54.003834
7568 12:47:54.007513 ----->DramcWriteLeveling(PI) begin...
7569 12:47:54.007612 ==
7570 12:47:54.010578 Dram Type= 6, Freq= 0, CH_0, rank 0
7571 12:47:54.014096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7572 12:47:54.014198 ==
7573 12:47:54.017574 Write leveling (Byte 0): 32 => 32
7574 12:47:54.020540 Write leveling (Byte 1): 29 => 29
7575 12:47:54.024152 DramcWriteLeveling(PI) end<-----
7576 12:47:54.024299
7577 12:47:54.024428 ==
7578 12:47:54.027362 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 12:47:54.030661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 12:47:54.034276 ==
7581 12:47:54.034408 [Gating] SW mode calibration
7582 12:47:54.044167 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7583 12:47:54.047355 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7584 12:47:54.050461 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 12:47:54.057219 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 12:47:54.060917 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 12:47:54.063969 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 12:47:54.070554 1 4 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 12:47:54.074054 1 4 20 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7590 12:47:54.077127 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7591 12:47:54.084369 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 12:47:54.087352 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 12:47:54.090905 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 12:47:54.097399 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 12:47:54.100435 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 12:47:54.104275 1 5 16 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7597 12:47:54.107280 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7598 12:47:54.114268 1 5 24 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
7599 12:47:54.117360 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 12:47:54.120802 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 12:47:54.127270 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 12:47:54.130979 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 12:47:54.134138 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7604 12:47:54.140870 1 6 16 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (1 1)
7605 12:47:54.144011 1 6 20 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7606 12:47:54.147804 1 6 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7607 12:47:54.154009 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 12:47:54.157739 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 12:47:54.160861 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 12:47:54.167656 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 12:47:54.170734 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 12:47:54.174404 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7613 12:47:54.180893 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7614 12:47:54.184439 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7615 12:47:54.187845 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 12:47:54.190550 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 12:47:54.197611 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 12:47:54.200964 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 12:47:54.204598 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 12:47:54.210651 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 12:47:54.214462 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 12:47:54.217632 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 12:47:54.224217 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 12:47:54.227874 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 12:47:54.230766 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 12:47:54.237588 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 12:47:54.241335 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 12:47:54.244417 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7629 12:47:54.251259 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7630 12:47:54.254485 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7631 12:47:54.257598 Total UI for P1: 0, mck2ui 16
7632 12:47:54.261225 best dqsien dly found for B0: ( 1, 9, 18)
7633 12:47:54.264377 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 12:47:54.267531 Total UI for P1: 0, mck2ui 16
7635 12:47:54.271371 best dqsien dly found for B1: ( 1, 9, 22)
7636 12:47:54.274288 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7637 12:47:54.277863 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7638 12:47:54.277999
7639 12:47:54.281083 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7640 12:47:54.287412 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7641 12:47:54.287564 [Gating] SW calibration Done
7642 12:47:54.287701 ==
7643 12:47:54.291135 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 12:47:54.297774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 12:47:54.297893 ==
7646 12:47:54.297991 RX Vref Scan: 0
7647 12:47:54.298083
7648 12:47:54.301301 RX Vref 0 -> 0, step: 1
7649 12:47:54.301434
7650 12:47:54.304563 RX Delay 0 -> 252, step: 8
7651 12:47:54.307571 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7652 12:47:54.311102 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7653 12:47:54.314516 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7654 12:47:54.317735 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7655 12:47:54.324480 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7656 12:47:54.327728 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7657 12:47:54.331236 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7658 12:47:54.334070 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7659 12:47:54.337891 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7660 12:47:54.344239 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7661 12:47:54.347981 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7662 12:47:54.351017 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7663 12:47:54.354225 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7664 12:47:54.357935 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
7665 12:47:54.364242 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7666 12:47:54.367397 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7667 12:47:54.367484 ==
7668 12:47:54.370524 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 12:47:54.374358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 12:47:54.374442 ==
7671 12:47:54.377620 DQS Delay:
7672 12:47:54.377752 DQS0 = 0, DQS1 = 0
7673 12:47:54.377851 DQM Delay:
7674 12:47:54.381299 DQM0 = 132, DQM1 = 123
7675 12:47:54.381415 DQ Delay:
7676 12:47:54.384084 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7677 12:47:54.387690 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7678 12:47:54.391110 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7679 12:47:54.398003 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =135
7680 12:47:54.398131
7681 12:47:54.398224
7682 12:47:54.398307 ==
7683 12:47:54.401107 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 12:47:54.404304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 12:47:54.404465 ==
7686 12:47:54.404603
7687 12:47:54.404788
7688 12:47:54.407659 TX Vref Scan disable
7689 12:47:54.407860 == TX Byte 0 ==
7690 12:47:54.414249 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7691 12:47:54.417892 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7692 12:47:54.418016 == TX Byte 1 ==
7693 12:47:54.424333 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7694 12:47:54.427478 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7695 12:47:54.427661 ==
7696 12:47:54.430950 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 12:47:54.434236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 12:47:54.434463 ==
7699 12:47:54.449520
7700 12:47:54.453207 TX Vref early break, caculate TX vref
7701 12:47:54.456328 TX Vref=16, minBit 4, minWin=20, winSum=355
7702 12:47:54.459441 TX Vref=18, minBit 2, minWin=21, winSum=366
7703 12:47:54.463192 TX Vref=20, minBit 0, minWin=22, winSum=381
7704 12:47:54.466259 TX Vref=22, minBit 7, minWin=22, winSum=391
7705 12:47:54.469448 TX Vref=24, minBit 0, minWin=23, winSum=399
7706 12:47:54.473306 TX Vref=26, minBit 1, minWin=24, winSum=410
7707 12:47:54.479999 TX Vref=28, minBit 1, minWin=24, winSum=420
7708 12:47:54.483015 TX Vref=30, minBit 0, minWin=25, winSum=420
7709 12:47:54.486730 TX Vref=32, minBit 0, minWin=24, winSum=411
7710 12:47:54.489815 TX Vref=34, minBit 4, minWin=23, winSum=404
7711 12:47:54.492889 TX Vref=36, minBit 0, minWin=23, winSum=391
7712 12:47:54.499771 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 30
7713 12:47:54.499885
7714 12:47:54.502865 Final TX Range 0 Vref 30
7715 12:47:54.502982
7716 12:47:54.503081 ==
7717 12:47:54.506604 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 12:47:54.509786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 12:47:54.509896 ==
7720 12:47:54.509993
7721 12:47:54.510087
7722 12:47:54.512888 TX Vref Scan disable
7723 12:47:54.519515 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7724 12:47:54.519641 == TX Byte 0 ==
7725 12:47:54.522930 u2DelayCellOfst[0]=14 cells (4 PI)
7726 12:47:54.526739 u2DelayCellOfst[1]=17 cells (5 PI)
7727 12:47:54.529855 u2DelayCellOfst[2]=10 cells (3 PI)
7728 12:47:54.532818 u2DelayCellOfst[3]=14 cells (4 PI)
7729 12:47:54.536346 u2DelayCellOfst[4]=10 cells (3 PI)
7730 12:47:54.539646 u2DelayCellOfst[5]=0 cells (0 PI)
7731 12:47:54.543078 u2DelayCellOfst[6]=17 cells (5 PI)
7732 12:47:54.546448 u2DelayCellOfst[7]=17 cells (5 PI)
7733 12:47:54.549868 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7734 12:47:54.552854 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7735 12:47:54.556316 == TX Byte 1 ==
7736 12:47:54.556427 u2DelayCellOfst[8]=0 cells (0 PI)
7737 12:47:54.559852 u2DelayCellOfst[9]=0 cells (0 PI)
7738 12:47:54.563002 u2DelayCellOfst[10]=7 cells (2 PI)
7739 12:47:54.566047 u2DelayCellOfst[11]=0 cells (0 PI)
7740 12:47:54.569818 u2DelayCellOfst[12]=10 cells (3 PI)
7741 12:47:54.572973 u2DelayCellOfst[13]=10 cells (3 PI)
7742 12:47:54.576863 u2DelayCellOfst[14]=14 cells (4 PI)
7743 12:47:54.579859 u2DelayCellOfst[15]=10 cells (3 PI)
7744 12:47:54.583075 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7745 12:47:54.590083 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7746 12:47:54.590183 DramC Write-DBI on
7747 12:47:54.590252 ==
7748 12:47:54.592914 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 12:47:54.596683 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 12:47:54.596761 ==
7751 12:47:54.596826
7752 12:47:54.599726
7753 12:47:54.599829 TX Vref Scan disable
7754 12:47:54.603461 == TX Byte 0 ==
7755 12:47:54.606267 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7756 12:47:54.609838 == TX Byte 1 ==
7757 12:47:54.613470 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7758 12:47:54.613601 DramC Write-DBI off
7759 12:47:54.613699
7760 12:47:54.616582 [DATLAT]
7761 12:47:54.616694 Freq=1600, CH0 RK0
7762 12:47:54.616763
7763 12:47:54.619785 DATLAT Default: 0xf
7764 12:47:54.619874 0, 0xFFFF, sum = 0
7765 12:47:54.623215 1, 0xFFFF, sum = 0
7766 12:47:54.623337 2, 0xFFFF, sum = 0
7767 12:47:54.626392 3, 0xFFFF, sum = 0
7768 12:47:54.626498 4, 0xFFFF, sum = 0
7769 12:47:54.629701 5, 0xFFFF, sum = 0
7770 12:47:54.629778 6, 0xFFFF, sum = 0
7771 12:47:54.633473 7, 0xFFFF, sum = 0
7772 12:47:54.633568 8, 0xFFFF, sum = 0
7773 12:47:54.636626 9, 0xFFFF, sum = 0
7774 12:47:54.639638 10, 0xFFFF, sum = 0
7775 12:47:54.639715 11, 0xFFFF, sum = 0
7776 12:47:54.643276 12, 0xFFFF, sum = 0
7777 12:47:54.643387 13, 0xFFFF, sum = 0
7778 12:47:54.646841 14, 0x0, sum = 1
7779 12:47:54.646941 15, 0x0, sum = 2
7780 12:47:54.649872 16, 0x0, sum = 3
7781 12:47:54.649997 17, 0x0, sum = 4
7782 12:47:54.650114 best_step = 15
7783 12:47:54.650214
7784 12:47:54.653612 ==
7785 12:47:54.656590 Dram Type= 6, Freq= 0, CH_0, rank 0
7786 12:47:54.660258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7787 12:47:54.660366 ==
7788 12:47:54.660473 RX Vref Scan: 1
7789 12:47:54.660569
7790 12:47:54.663181 Set Vref Range= 24 -> 127
7791 12:47:54.663292
7792 12:47:54.666854 RX Vref 24 -> 127, step: 1
7793 12:47:54.666964
7794 12:47:54.669979 RX Delay 11 -> 252, step: 4
7795 12:47:54.670089
7796 12:47:54.673293 Set Vref, RX VrefLevel [Byte0]: 24
7797 12:47:54.676902 [Byte1]: 24
7798 12:47:54.677024
7799 12:47:54.680020 Set Vref, RX VrefLevel [Byte0]: 25
7800 12:47:54.683221 [Byte1]: 25
7801 12:47:54.683331
7802 12:47:54.686949 Set Vref, RX VrefLevel [Byte0]: 26
7803 12:47:54.690201 [Byte1]: 26
7804 12:47:54.693354
7805 12:47:54.693466 Set Vref, RX VrefLevel [Byte0]: 27
7806 12:47:54.696420 [Byte1]: 27
7807 12:47:54.700590
7808 12:47:54.700729 Set Vref, RX VrefLevel [Byte0]: 28
7809 12:47:54.704268 [Byte1]: 28
7810 12:47:54.708653
7811 12:47:54.708789 Set Vref, RX VrefLevel [Byte0]: 29
7812 12:47:54.711623 [Byte1]: 29
7813 12:47:54.716070
7814 12:47:54.716188 Set Vref, RX VrefLevel [Byte0]: 30
7815 12:47:54.719088 [Byte1]: 30
7816 12:47:54.724068
7817 12:47:54.724176 Set Vref, RX VrefLevel [Byte0]: 31
7818 12:47:54.727179 [Byte1]: 31
7819 12:47:54.731391
7820 12:47:54.731502 Set Vref, RX VrefLevel [Byte0]: 32
7821 12:47:54.734338 [Byte1]: 32
7822 12:47:54.738890
7823 12:47:54.739000 Set Vref, RX VrefLevel [Byte0]: 33
7824 12:47:54.742551 [Byte1]: 33
7825 12:47:54.746919
7826 12:47:54.747027 Set Vref, RX VrefLevel [Byte0]: 34
7827 12:47:54.750053 [Byte1]: 34
7828 12:47:54.754243
7829 12:47:54.754352 Set Vref, RX VrefLevel [Byte0]: 35
7830 12:47:54.757589 [Byte1]: 35
7831 12:47:54.761617
7832 12:47:54.761729 Set Vref, RX VrefLevel [Byte0]: 36
7833 12:47:54.765348 [Byte1]: 36
7834 12:47:54.769146
7835 12:47:54.769259 Set Vref, RX VrefLevel [Byte0]: 37
7836 12:47:54.772744 [Byte1]: 37
7837 12:47:54.776806
7838 12:47:54.776912 Set Vref, RX VrefLevel [Byte0]: 38
7839 12:47:54.780081 [Byte1]: 38
7840 12:47:54.784656
7841 12:47:54.784775 Set Vref, RX VrefLevel [Byte0]: 39
7842 12:47:54.787685 [Byte1]: 39
7843 12:47:54.791975
7844 12:47:54.792089 Set Vref, RX VrefLevel [Byte0]: 40
7845 12:47:54.795787 [Byte1]: 40
7846 12:47:54.800166
7847 12:47:54.800280 Set Vref, RX VrefLevel [Byte0]: 41
7848 12:47:54.803083 [Byte1]: 41
7849 12:47:54.807489
7850 12:47:54.807602 Set Vref, RX VrefLevel [Byte0]: 42
7851 12:47:54.810665 [Byte1]: 42
7852 12:47:54.814992
7853 12:47:54.815106 Set Vref, RX VrefLevel [Byte0]: 43
7854 12:47:54.818155 [Byte1]: 43
7855 12:47:54.822748
7856 12:47:54.822860 Set Vref, RX VrefLevel [Byte0]: 44
7857 12:47:54.826169 [Byte1]: 44
7858 12:47:54.830529
7859 12:47:54.830651 Set Vref, RX VrefLevel [Byte0]: 45
7860 12:47:54.833566 [Byte1]: 45
7861 12:47:54.837959
7862 12:47:54.838077 Set Vref, RX VrefLevel [Byte0]: 46
7863 12:47:54.841445 [Byte1]: 46
7864 12:47:54.845474
7865 12:47:54.845558 Set Vref, RX VrefLevel [Byte0]: 47
7866 12:47:54.848830 [Byte1]: 47
7867 12:47:54.853173
7868 12:47:54.853300 Set Vref, RX VrefLevel [Byte0]: 48
7869 12:47:54.856181 [Byte1]: 48
7870 12:47:54.860487
7871 12:47:54.860593 Set Vref, RX VrefLevel [Byte0]: 49
7872 12:47:54.864152 [Byte1]: 49
7873 12:47:54.868201
7874 12:47:54.868309 Set Vref, RX VrefLevel [Byte0]: 50
7875 12:47:54.871852 [Byte1]: 50
7876 12:47:54.876094
7877 12:47:54.876211 Set Vref, RX VrefLevel [Byte0]: 51
7878 12:47:54.879117 [Byte1]: 51
7879 12:47:54.883475
7880 12:47:54.883583 Set Vref, RX VrefLevel [Byte0]: 52
7881 12:47:54.887104 [Byte1]: 52
7882 12:47:54.891087
7883 12:47:54.891202 Set Vref, RX VrefLevel [Byte0]: 53
7884 12:47:54.894322 [Byte1]: 53
7885 12:47:54.899007
7886 12:47:54.899116 Set Vref, RX VrefLevel [Byte0]: 54
7887 12:47:54.901944 [Byte1]: 54
7888 12:47:54.906132
7889 12:47:54.906252 Set Vref, RX VrefLevel [Byte0]: 55
7890 12:47:54.909952 [Byte1]: 55
7891 12:47:54.914297
7892 12:47:54.914431 Set Vref, RX VrefLevel [Byte0]: 56
7893 12:47:54.917398 [Byte1]: 56
7894 12:47:54.921732
7895 12:47:54.921848 Set Vref, RX VrefLevel [Byte0]: 57
7896 12:47:54.924972 [Byte1]: 57
7897 12:47:54.929022
7898 12:47:54.929123 Set Vref, RX VrefLevel [Byte0]: 58
7899 12:47:54.932408 [Byte1]: 58
7900 12:47:54.936898
7901 12:47:54.936984 Set Vref, RX VrefLevel [Byte0]: 59
7902 12:47:54.939935 [Byte1]: 59
7903 12:47:54.944382
7904 12:47:54.944473 Set Vref, RX VrefLevel [Byte0]: 60
7905 12:47:54.948022 [Byte1]: 60
7906 12:47:54.952032
7907 12:47:54.952154 Set Vref, RX VrefLevel [Byte0]: 61
7908 12:47:54.955450 [Byte1]: 61
7909 12:47:54.959582
7910 12:47:54.959686 Set Vref, RX VrefLevel [Byte0]: 62
7911 12:47:54.963333 [Byte1]: 62
7912 12:47:54.967033
7913 12:47:54.967144 Set Vref, RX VrefLevel [Byte0]: 63
7914 12:47:54.970676 [Byte1]: 63
7915 12:47:54.974870
7916 12:47:54.974986 Set Vref, RX VrefLevel [Byte0]: 64
7917 12:47:54.978445 [Byte1]: 64
7918 12:47:54.982371
7919 12:47:54.982483 Set Vref, RX VrefLevel [Byte0]: 65
7920 12:47:54.986187 [Byte1]: 65
7921 12:47:54.990499
7922 12:47:54.990605 Set Vref, RX VrefLevel [Byte0]: 66
7923 12:47:54.993576 [Byte1]: 66
7924 12:47:54.997792
7925 12:47:54.997870 Set Vref, RX VrefLevel [Byte0]: 67
7926 12:47:55.001378 [Byte1]: 67
7927 12:47:55.005308
7928 12:47:55.005392 Set Vref, RX VrefLevel [Byte0]: 68
7929 12:47:55.008585 [Byte1]: 68
7930 12:47:55.012798
7931 12:47:55.012921 Set Vref, RX VrefLevel [Byte0]: 69
7932 12:47:55.016548 [Byte1]: 69
7933 12:47:55.020851
7934 12:47:55.020977 Set Vref, RX VrefLevel [Byte0]: 70
7935 12:47:55.024020 [Byte1]: 70
7936 12:47:55.028445
7937 12:47:55.028558 Set Vref, RX VrefLevel [Byte0]: 71
7938 12:47:55.031626 [Byte1]: 71
7939 12:47:55.035697
7940 12:47:55.035802 Set Vref, RX VrefLevel [Byte0]: 72
7941 12:47:55.039182 [Byte1]: 72
7942 12:47:55.043216
7943 12:47:55.043323 Set Vref, RX VrefLevel [Byte0]: 73
7944 12:47:55.046809 [Byte1]: 73
7945 12:47:55.051102
7946 12:47:55.051216 Set Vref, RX VrefLevel [Byte0]: 74
7947 12:47:55.054244 [Byte1]: 74
7948 12:47:55.058674
7949 12:47:55.058781 Set Vref, RX VrefLevel [Byte0]: 75
7950 12:47:55.061950 [Byte1]: 75
7951 12:47:55.066002
7952 12:47:55.066109 Set Vref, RX VrefLevel [Byte0]: 76
7953 12:47:55.069830 [Byte1]: 76
7954 12:47:55.073557
7955 12:47:55.073667 Set Vref, RX VrefLevel [Byte0]: 77
7956 12:47:55.077250 [Byte1]: 77
7957 12:47:55.081575
7958 12:47:55.081693 Final RX Vref Byte 0 = 62 to rank0
7959 12:47:55.084644 Final RX Vref Byte 1 = 62 to rank0
7960 12:47:55.088002 Final RX Vref Byte 0 = 62 to rank1
7961 12:47:55.091555 Final RX Vref Byte 1 = 62 to rank1==
7962 12:47:55.094590 Dram Type= 6, Freq= 0, CH_0, rank 0
7963 12:47:55.101523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7964 12:47:55.101640 ==
7965 12:47:55.101747 DQS Delay:
7966 12:47:55.101838 DQS0 = 0, DQS1 = 0
7967 12:47:55.104557 DQM Delay:
7968 12:47:55.104690 DQM0 = 129, DQM1 = 121
7969 12:47:55.108280 DQ Delay:
7970 12:47:55.111390 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7971 12:47:55.114898 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7972 12:47:55.117886 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7973 12:47:55.121356 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
7974 12:47:55.121483
7975 12:47:55.121579
7976 12:47:55.121673
7977 12:47:55.124601 [DramC_TX_OE_Calibration] TA2
7978 12:47:55.128004 Original DQ_B0 (3 6) =30, OEN = 27
7979 12:47:55.131719 Original DQ_B1 (3 6) =30, OEN = 27
7980 12:47:55.134823 24, 0x0, End_B0=24 End_B1=24
7981 12:47:55.134937 25, 0x0, End_B0=25 End_B1=25
7982 12:47:55.138072 26, 0x0, End_B0=26 End_B1=26
7983 12:47:55.141760 27, 0x0, End_B0=27 End_B1=27
7984 12:47:55.145247 28, 0x0, End_B0=28 End_B1=28
7985 12:47:55.145351 29, 0x0, End_B0=29 End_B1=29
7986 12:47:55.148009 30, 0x0, End_B0=30 End_B1=30
7987 12:47:55.151352 31, 0x4141, End_B0=30 End_B1=30
7988 12:47:55.154884 Byte0 end_step=30 best_step=27
7989 12:47:55.158677 Byte1 end_step=30 best_step=27
7990 12:47:55.158806 Byte0 TX OE(2T, 0.5T) = (3, 3)
7991 12:47:55.161706 Byte1 TX OE(2T, 0.5T) = (3, 3)
7992 12:47:55.161815
7993 12:47:55.161908
7994 12:47:55.172197 [DQSOSCAuto] RK0, (LSB)MR18= 0x160b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
7995 12:47:55.174989 CH0 RK0: MR19=303, MR18=160B
7996 12:47:55.178609 CH0_RK0: MR19=0x303, MR18=0x160B, DQSOSC=398, MR23=63, INC=23, DEC=15
7997 12:47:55.178719
7998 12:47:55.181640 ----->DramcWriteLeveling(PI) begin...
7999 12:47:55.185368 ==
8000 12:47:55.188497 Dram Type= 6, Freq= 0, CH_0, rank 1
8001 12:47:55.192227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8002 12:47:55.192321 ==
8003 12:47:55.195185 Write leveling (Byte 0): 33 => 33
8004 12:47:55.198594 Write leveling (Byte 1): 27 => 27
8005 12:47:55.202170 DramcWriteLeveling(PI) end<-----
8006 12:47:55.202257
8007 12:47:55.202325 ==
8008 12:47:55.205197 Dram Type= 6, Freq= 0, CH_0, rank 1
8009 12:47:55.208784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8010 12:47:55.208870 ==
8011 12:47:55.211901 [Gating] SW mode calibration
8012 12:47:55.218550 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8013 12:47:55.222266 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8014 12:47:55.229221 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 12:47:55.232113 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 12:47:55.235760 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 12:47:55.242367 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8018 12:47:55.245576 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8019 12:47:55.248731 1 4 20 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
8020 12:47:55.255731 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 12:47:55.258577 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8022 12:47:55.262386 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8023 12:47:55.269227 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8024 12:47:55.272420 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8025 12:47:55.275346 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8026 12:47:55.282106 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8027 12:47:55.285684 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
8028 12:47:55.289236 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 12:47:55.292366 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 12:47:55.299474 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 12:47:55.302309 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 12:47:55.305444 1 6 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8033 12:47:55.312647 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8034 12:47:55.315802 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8035 12:47:55.319015 1 6 20 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
8036 12:47:55.325596 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8037 12:47:55.329325 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 12:47:55.332369 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 12:47:55.339240 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 12:47:55.342437 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 12:47:55.345941 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8042 12:47:55.352589 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8043 12:47:55.355658 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8044 12:47:55.359222 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 12:47:55.362270 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 12:47:55.369512 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 12:47:55.372451 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 12:47:55.376176 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 12:47:55.383029 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 12:47:55.386041 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 12:47:55.389615 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 12:47:55.395803 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 12:47:55.399529 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 12:47:55.402604 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 12:47:55.409348 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 12:47:55.413013 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8057 12:47:55.416147 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8058 12:47:55.419698 Total UI for P1: 0, mck2ui 16
8059 12:47:55.422671 best dqsien dly found for B0: ( 1, 9, 8)
8060 12:47:55.426117 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8061 12:47:55.432755 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8062 12:47:55.435881 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 12:47:55.439654 Total UI for P1: 0, mck2ui 16
8064 12:47:55.442699 best dqsien dly found for B1: ( 1, 9, 18)
8065 12:47:55.446344 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8066 12:47:55.449430 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8067 12:47:55.449548
8068 12:47:55.453026 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8069 12:47:55.456408 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8070 12:47:55.459534 [Gating] SW calibration Done
8071 12:47:55.459646 ==
8072 12:47:55.462999 Dram Type= 6, Freq= 0, CH_0, rank 1
8073 12:47:55.469853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8074 12:47:55.469980 ==
8075 12:47:55.470113 RX Vref Scan: 0
8076 12:47:55.470212
8077 12:47:55.473070 RX Vref 0 -> 0, step: 1
8078 12:47:55.473182
8079 12:47:55.476439 RX Delay 0 -> 252, step: 8
8080 12:47:55.479932 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8081 12:47:55.483007 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8082 12:47:55.486171 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8083 12:47:55.489930 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8084 12:47:55.493028 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8085 12:47:55.499796 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8086 12:47:55.502829 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8087 12:47:55.506773 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8088 12:47:55.509777 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8089 12:47:55.513343 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8090 12:47:55.519584 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8091 12:47:55.523241 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8092 12:47:55.526219 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8093 12:47:55.529844 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8094 12:47:55.536485 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8095 12:47:55.539676 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8096 12:47:55.539845 ==
8097 12:47:55.542771 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 12:47:55.546592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 12:47:55.546770 ==
8100 12:47:55.546932 DQS Delay:
8101 12:47:55.549738 DQS0 = 0, DQS1 = 0
8102 12:47:55.549916 DQM Delay:
8103 12:47:55.553281 DQM0 = 130, DQM1 = 123
8104 12:47:55.553450 DQ Delay:
8105 12:47:55.556343 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8106 12:47:55.560005 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8107 12:47:55.563315 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =115
8108 12:47:55.566301 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8109 12:47:55.566486
8110 12:47:55.569846
8111 12:47:55.570016 ==
8112 12:47:55.573595 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 12:47:55.576617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 12:47:55.576776 ==
8115 12:47:55.576885
8116 12:47:55.576980
8117 12:47:55.579852 TX Vref Scan disable
8118 12:47:55.580023 == TX Byte 0 ==
8119 12:47:55.583431 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8120 12:47:55.590026 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8121 12:47:55.590142 == TX Byte 1 ==
8122 12:47:55.593236 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8123 12:47:55.600140 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8124 12:47:55.600255 ==
8125 12:47:55.603602 Dram Type= 6, Freq= 0, CH_0, rank 1
8126 12:47:55.606405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8127 12:47:55.606535 ==
8128 12:47:55.621473
8129 12:47:55.624631 TX Vref early break, caculate TX vref
8130 12:47:55.628211 TX Vref=16, minBit 1, minWin=22, winSum=367
8131 12:47:55.631697 TX Vref=18, minBit 0, minWin=23, winSum=382
8132 12:47:55.634998 TX Vref=20, minBit 8, minWin=23, winSum=389
8133 12:47:55.638098 TX Vref=22, minBit 0, minWin=23, winSum=390
8134 12:47:55.641273 TX Vref=24, minBit 1, minWin=24, winSum=403
8135 12:47:55.648204 TX Vref=26, minBit 4, minWin=24, winSum=415
8136 12:47:55.651271 TX Vref=28, minBit 0, minWin=25, winSum=419
8137 12:47:55.654933 TX Vref=30, minBit 1, minWin=24, winSum=414
8138 12:47:55.657877 TX Vref=32, minBit 4, minWin=24, winSum=407
8139 12:47:55.661630 TX Vref=34, minBit 0, minWin=24, winSum=401
8140 12:47:55.665283 TX Vref=36, minBit 4, minWin=23, winSum=394
8141 12:47:55.671774 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
8142 12:47:55.671900
8143 12:47:55.674999 Final TX Range 0 Vref 28
8144 12:47:55.675103
8145 12:47:55.675195 ==
8146 12:47:55.678109 Dram Type= 6, Freq= 0, CH_0, rank 1
8147 12:47:55.681764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8148 12:47:55.681867 ==
8149 12:47:55.681960
8150 12:47:55.682050
8151 12:47:55.684900 TX Vref Scan disable
8152 12:47:55.691561 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8153 12:47:55.691683 == TX Byte 0 ==
8154 12:47:55.695092 u2DelayCellOfst[0]=14 cells (4 PI)
8155 12:47:55.698584 u2DelayCellOfst[1]=17 cells (5 PI)
8156 12:47:55.701662 u2DelayCellOfst[2]=10 cells (3 PI)
8157 12:47:55.704866 u2DelayCellOfst[3]=10 cells (3 PI)
8158 12:47:55.708570 u2DelayCellOfst[4]=10 cells (3 PI)
8159 12:47:55.711563 u2DelayCellOfst[5]=0 cells (0 PI)
8160 12:47:55.714947 u2DelayCellOfst[6]=17 cells (5 PI)
8161 12:47:55.718476 u2DelayCellOfst[7]=17 cells (5 PI)
8162 12:47:55.721881 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8163 12:47:55.725533 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8164 12:47:55.725724 == TX Byte 1 ==
8165 12:47:55.728565 u2DelayCellOfst[8]=0 cells (0 PI)
8166 12:47:55.731758 u2DelayCellOfst[9]=0 cells (0 PI)
8167 12:47:55.735515 u2DelayCellOfst[10]=7 cells (2 PI)
8168 12:47:55.738397 u2DelayCellOfst[11]=0 cells (0 PI)
8169 12:47:55.741890 u2DelayCellOfst[12]=10 cells (3 PI)
8170 12:47:55.745342 u2DelayCellOfst[13]=10 cells (3 PI)
8171 12:47:55.748519 u2DelayCellOfst[14]=14 cells (4 PI)
8172 12:47:55.751729 u2DelayCellOfst[15]=10 cells (3 PI)
8173 12:47:55.754882 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8174 12:47:55.761550 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8175 12:47:55.761762 DramC Write-DBI on
8176 12:47:55.761944 ==
8177 12:47:55.765259 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 12:47:55.768344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 12:47:55.768539 ==
8180 12:47:55.772058
8181 12:47:55.772270
8182 12:47:55.772459 TX Vref Scan disable
8183 12:47:55.775106 == TX Byte 0 ==
8184 12:47:55.778190 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8185 12:47:55.781612 == TX Byte 1 ==
8186 12:47:55.785151 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8187 12:47:55.785356 DramC Write-DBI off
8188 12:47:55.788359
8189 12:47:55.788606 [DATLAT]
8190 12:47:55.788790 Freq=1600, CH0 RK1
8191 12:47:55.789023
8192 12:47:55.791669 DATLAT Default: 0xf
8193 12:47:55.791875 0, 0xFFFF, sum = 0
8194 12:47:55.794770 1, 0xFFFF, sum = 0
8195 12:47:55.794977 2, 0xFFFF, sum = 0
8196 12:47:55.798469 3, 0xFFFF, sum = 0
8197 12:47:55.802082 4, 0xFFFF, sum = 0
8198 12:47:55.802286 5, 0xFFFF, sum = 0
8199 12:47:55.804794 6, 0xFFFF, sum = 0
8200 12:47:55.804971 7, 0xFFFF, sum = 0
8201 12:47:55.808208 8, 0xFFFF, sum = 0
8202 12:47:55.808476 9, 0xFFFF, sum = 0
8203 12:47:55.812068 10, 0xFFFF, sum = 0
8204 12:47:55.812324 11, 0xFFFF, sum = 0
8205 12:47:55.815141 12, 0xFFFF, sum = 0
8206 12:47:55.815396 13, 0xFFFF, sum = 0
8207 12:47:55.818220 14, 0x0, sum = 1
8208 12:47:55.818463 15, 0x0, sum = 2
8209 12:47:55.821799 16, 0x0, sum = 3
8210 12:47:55.822008 17, 0x0, sum = 4
8211 12:47:55.824685 best_step = 15
8212 12:47:55.824895
8213 12:47:55.825075 ==
8214 12:47:55.828576 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 12:47:55.831632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 12:47:55.831839 ==
8217 12:47:55.832033 RX Vref Scan: 0
8218 12:47:55.835104
8219 12:47:55.835319 RX Vref 0 -> 0, step: 1
8220 12:47:55.835533
8221 12:47:55.838126 RX Delay 11 -> 252, step: 4
8222 12:47:55.841859 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8223 12:47:55.847932 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8224 12:47:55.851898 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8225 12:47:55.854977 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8226 12:47:55.858033 iDelay=191, Bit 4, Center 126 (71 ~ 182) 112
8227 12:47:55.861789 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8228 12:47:55.868404 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8229 12:47:55.871702 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8230 12:47:55.874761 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8231 12:47:55.878072 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8232 12:47:55.881887 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8233 12:47:55.884879 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8234 12:47:55.891657 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8235 12:47:55.894971 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8236 12:47:55.898416 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8237 12:47:55.901724 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8238 12:47:55.901882 ==
8239 12:47:55.904841 Dram Type= 6, Freq= 0, CH_0, rank 1
8240 12:47:55.911982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8241 12:47:55.912239 ==
8242 12:47:55.912465 DQS Delay:
8243 12:47:55.914861 DQS0 = 0, DQS1 = 0
8244 12:47:55.915067 DQM Delay:
8245 12:47:55.915256 DQM0 = 127, DQM1 = 122
8246 12:47:55.918704 DQ Delay:
8247 12:47:55.922081 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8248 12:47:55.925053 DQ4 =126, DQ5 =116, DQ6 =136, DQ7 =136
8249 12:47:55.928655 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8250 12:47:55.932103 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8251 12:47:55.932319
8252 12:47:55.932535
8253 12:47:55.932727
8254 12:47:55.935403 [DramC_TX_OE_Calibration] TA2
8255 12:47:55.938733 Original DQ_B0 (3 6) =30, OEN = 27
8256 12:47:55.942186 Original DQ_B1 (3 6) =30, OEN = 27
8257 12:47:55.945623 24, 0x0, End_B0=24 End_B1=24
8258 12:47:55.945836 25, 0x0, End_B0=25 End_B1=25
8259 12:47:55.948609 26, 0x0, End_B0=26 End_B1=26
8260 12:47:55.951705 27, 0x0, End_B0=27 End_B1=27
8261 12:47:55.955344 28, 0x0, End_B0=28 End_B1=28
8262 12:47:55.955575 29, 0x0, End_B0=29 End_B1=29
8263 12:47:55.958815 30, 0x0, End_B0=30 End_B1=30
8264 12:47:55.961810 31, 0x4141, End_B0=30 End_B1=30
8265 12:47:55.965462 Byte0 end_step=30 best_step=27
8266 12:47:55.969022 Byte1 end_step=30 best_step=27
8267 12:47:55.972146 Byte0 TX OE(2T, 0.5T) = (3, 3)
8268 12:47:55.972368 Byte1 TX OE(2T, 0.5T) = (3, 3)
8269 12:47:55.972574
8270 12:47:55.975290
8271 12:47:55.982333 [DQSOSCAuto] RK1, (LSB)MR18= 0x180d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8272 12:47:55.985484 CH0 RK1: MR19=303, MR18=180D
8273 12:47:55.992204 CH0_RK1: MR19=0x303, MR18=0x180D, DQSOSC=397, MR23=63, INC=23, DEC=15
8274 12:47:55.992442 [RxdqsGatingPostProcess] freq 1600
8275 12:47:55.998948 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8276 12:47:56.002427 best DQS0 dly(2T, 0.5T) = (1, 1)
8277 12:47:56.005427 best DQS1 dly(2T, 0.5T) = (1, 1)
8278 12:47:56.008866 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8279 12:47:56.012533 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8280 12:47:56.015637 best DQS0 dly(2T, 0.5T) = (1, 1)
8281 12:47:56.019368 best DQS1 dly(2T, 0.5T) = (1, 1)
8282 12:47:56.019581 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8283 12:47:56.022759 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8284 12:47:56.025852 Pre-setting of DQS Precalculation
8285 12:47:56.032196 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8286 12:47:56.032416 ==
8287 12:47:56.035844 Dram Type= 6, Freq= 0, CH_1, rank 0
8288 12:47:56.039039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8289 12:47:56.039273 ==
8290 12:47:56.045585 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8291 12:47:56.048990 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8292 12:47:56.052236 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8293 12:47:56.059082 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8294 12:47:56.068129 [CA 0] Center 42 (14~70) winsize 57
8295 12:47:56.071588 [CA 1] Center 42 (13~71) winsize 59
8296 12:47:56.074767 [CA 2] Center 37 (8~66) winsize 59
8297 12:47:56.077963 [CA 3] Center 36 (7~66) winsize 60
8298 12:47:56.081718 [CA 4] Center 37 (8~66) winsize 59
8299 12:47:56.084709 [CA 5] Center 36 (7~66) winsize 60
8300 12:47:56.084870
8301 12:47:56.087938 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8302 12:47:56.088148
8303 12:47:56.091663 [CATrainingPosCal] consider 1 rank data
8304 12:47:56.094866 u2DelayCellTimex100 = 275/100 ps
8305 12:47:56.098269 CA0 delay=42 (14~70),Diff = 6 PI (21 cell)
8306 12:47:56.105111 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8307 12:47:56.108315 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8308 12:47:56.111422 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8309 12:47:56.114924 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8310 12:47:56.118211 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8311 12:47:56.118380
8312 12:47:56.121351 CA PerBit enable=1, Macro0, CA PI delay=36
8313 12:47:56.121511
8314 12:47:56.124994 [CBTSetCACLKResult] CA Dly = 36
8315 12:47:56.125207 CS Dly: 8 (0~39)
8316 12:47:56.131431 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8317 12:47:56.135207 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8318 12:47:56.135361 ==
8319 12:47:56.138382 Dram Type= 6, Freq= 0, CH_1, rank 1
8320 12:47:56.141514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 12:47:56.141704 ==
8322 12:47:56.148328 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8323 12:47:56.151556 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8324 12:47:56.154850 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8325 12:47:56.161714 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8326 12:47:56.171066 [CA 0] Center 43 (14~72) winsize 59
8327 12:47:56.174351 [CA 1] Center 43 (14~72) winsize 59
8328 12:47:56.177632 [CA 2] Center 38 (9~67) winsize 59
8329 12:47:56.181003 [CA 3] Center 37 (8~67) winsize 60
8330 12:47:56.184496 [CA 4] Center 38 (8~68) winsize 61
8331 12:47:56.187693 [CA 5] Center 37 (8~66) winsize 59
8332 12:47:56.187862
8333 12:47:56.191491 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8334 12:47:56.191648
8335 12:47:56.194613 [CATrainingPosCal] consider 2 rank data
8336 12:47:56.197770 u2DelayCellTimex100 = 275/100 ps
8337 12:47:56.201538 CA0 delay=42 (14~70),Diff = 5 PI (17 cell)
8338 12:47:56.207636 CA1 delay=42 (14~71),Diff = 5 PI (17 cell)
8339 12:47:56.211383 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8340 12:47:56.214611 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8341 12:47:56.218364 CA4 delay=37 (8~66),Diff = 0 PI (0 cell)
8342 12:47:56.221428 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8343 12:47:56.221660
8344 12:47:56.224650 CA PerBit enable=1, Macro0, CA PI delay=37
8345 12:47:56.224881
8346 12:47:56.228105 [CBTSetCACLKResult] CA Dly = 37
8347 12:47:56.228319 CS Dly: 10 (0~44)
8348 12:47:56.234730 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8349 12:47:56.237716 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8350 12:47:56.237923
8351 12:47:56.241371 ----->DramcWriteLeveling(PI) begin...
8352 12:47:56.241601 ==
8353 12:47:56.244955 Dram Type= 6, Freq= 0, CH_1, rank 0
8354 12:47:56.248012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8355 12:47:56.248243 ==
8356 12:47:56.251135 Write leveling (Byte 0): 25 => 25
8357 12:47:56.254734 Write leveling (Byte 1): 28 => 28
8358 12:47:56.257890 DramcWriteLeveling(PI) end<-----
8359 12:47:56.258147
8360 12:47:56.258368 ==
8361 12:47:56.261489 Dram Type= 6, Freq= 0, CH_1, rank 0
8362 12:47:56.265027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8363 12:47:56.268264 ==
8364 12:47:56.268552 [Gating] SW mode calibration
8365 12:47:56.278327 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8366 12:47:56.281134 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8367 12:47:56.284490 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 12:47:56.291230 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 12:47:56.294594 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 12:47:56.298323 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 12:47:56.304628 1 4 16 | B1->B0 | 2e2e 2525 | 0 0 | (0 0) (0 0)
8372 12:47:56.308094 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 12:47:56.311141 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 12:47:56.317987 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 12:47:56.321784 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 12:47:56.324986 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 12:47:56.331707 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 12:47:56.335088 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8379 12:47:56.338171 1 5 16 | B1->B0 | 3333 3333 | 1 1 | (1 0) (1 0)
8380 12:47:56.341892 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 12:47:56.348265 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 12:47:56.351316 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 12:47:56.355113 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 12:47:56.361733 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 12:47:56.364907 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 12:47:56.368401 1 6 12 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
8387 12:47:56.375170 1 6 16 | B1->B0 | 3e3e 3535 | 0 0 | (0 0) (0 0)
8388 12:47:56.378099 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 12:47:56.381625 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 12:47:56.388263 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 12:47:56.391733 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 12:47:56.394658 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 12:47:56.401663 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 12:47:56.405091 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8395 12:47:56.408103 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8396 12:47:56.415162 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8397 12:47:56.418439 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 12:47:56.421545 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 12:47:56.425216 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 12:47:56.431458 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 12:47:56.435067 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 12:47:56.438031 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 12:47:56.445145 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 12:47:56.448269 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 12:47:56.451579 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 12:47:56.458024 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 12:47:56.461700 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 12:47:56.464889 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 12:47:56.471550 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 12:47:56.475113 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8411 12:47:56.478246 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8412 12:47:56.485076 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8413 12:47:56.485236 Total UI for P1: 0, mck2ui 16
8414 12:47:56.491612 best dqsien dly found for B0: ( 1, 9, 14)
8415 12:47:56.494620 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 12:47:56.498217 Total UI for P1: 0, mck2ui 16
8417 12:47:56.501418 best dqsien dly found for B1: ( 1, 9, 18)
8418 12:47:56.504962 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8419 12:47:56.508377 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8420 12:47:56.508467
8421 12:47:56.511970 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8422 12:47:56.515122 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8423 12:47:56.518054 [Gating] SW calibration Done
8424 12:47:56.518149 ==
8425 12:47:56.521543 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 12:47:56.524686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 12:47:56.524785 ==
8428 12:47:56.528375 RX Vref Scan: 0
8429 12:47:56.528479
8430 12:47:56.531460 RX Vref 0 -> 0, step: 1
8431 12:47:56.531580
8432 12:47:56.531674 RX Delay 0 -> 252, step: 8
8433 12:47:56.538403 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8434 12:47:56.541506 iDelay=208, Bit 1, Center 127 (72 ~ 183) 112
8435 12:47:56.545057 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8436 12:47:56.548613 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8437 12:47:56.552006 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8438 12:47:56.558732 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8439 12:47:56.561690 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8440 12:47:56.565183 iDelay=208, Bit 7, Center 127 (72 ~ 183) 112
8441 12:47:56.568220 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8442 12:47:56.571979 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8443 12:47:56.575050 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8444 12:47:56.581849 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8445 12:47:56.585468 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8446 12:47:56.588532 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8447 12:47:56.591661 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8448 12:47:56.598530 iDelay=208, Bit 15, Center 131 (80 ~ 183) 104
8449 12:47:56.598637 ==
8450 12:47:56.601654 Dram Type= 6, Freq= 0, CH_1, rank 0
8451 12:47:56.605099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8452 12:47:56.605235 ==
8453 12:47:56.605341 DQS Delay:
8454 12:47:56.608541 DQS0 = 0, DQS1 = 0
8455 12:47:56.608642 DQM Delay:
8456 12:47:56.611522 DQM0 = 134, DQM1 = 126
8457 12:47:56.611627 DQ Delay:
8458 12:47:56.615025 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8459 12:47:56.618588 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =127
8460 12:47:56.621610 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8461 12:47:56.625152 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8462 12:47:56.625269
8463 12:47:56.625382
8464 12:47:56.625488 ==
8465 12:47:56.628880 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 12:47:56.635397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8467 12:47:56.635526 ==
8468 12:47:56.635622
8469 12:47:56.635716
8470 12:47:56.635804 TX Vref Scan disable
8471 12:47:56.638569 == TX Byte 0 ==
8472 12:47:56.642263 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8473 12:47:56.645462 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8474 12:47:56.648527 == TX Byte 1 ==
8475 12:47:56.652264 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8476 12:47:56.655285 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8477 12:47:56.659138 ==
8478 12:47:56.662020 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 12:47:56.665718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 12:47:56.665836 ==
8481 12:47:56.678809
8482 12:47:56.682168 TX Vref early break, caculate TX vref
8483 12:47:56.685277 TX Vref=16, minBit 8, minWin=21, winSum=361
8484 12:47:56.689078 TX Vref=18, minBit 5, minWin=22, winSum=373
8485 12:47:56.692156 TX Vref=20, minBit 8, minWin=22, winSum=384
8486 12:47:56.695877 TX Vref=22, minBit 11, minWin=22, winSum=390
8487 12:47:56.698899 TX Vref=24, minBit 8, minWin=22, winSum=401
8488 12:47:56.705636 TX Vref=26, minBit 8, minWin=24, winSum=411
8489 12:47:56.708658 TX Vref=28, minBit 8, minWin=25, winSum=414
8490 12:47:56.712146 TX Vref=30, minBit 1, minWin=25, winSum=415
8491 12:47:56.715667 TX Vref=32, minBit 0, minWin=25, winSum=412
8492 12:47:56.719230 TX Vref=34, minBit 11, minWin=23, winSum=399
8493 12:47:56.722300 TX Vref=36, minBit 0, minWin=23, winSum=387
8494 12:47:56.729008 [TxChooseVref] Worse bit 1, Min win 25, Win sum 415, Final Vref 30
8495 12:47:56.729141
8496 12:47:56.732662 Final TX Range 0 Vref 30
8497 12:47:56.732816
8498 12:47:56.732919 ==
8499 12:47:56.735587 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 12:47:56.739211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 12:47:56.739325 ==
8502 12:47:56.739428
8503 12:47:56.739533
8504 12:47:56.742301 TX Vref Scan disable
8505 12:47:56.749164 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8506 12:47:56.749292 == TX Byte 0 ==
8507 12:47:56.752181 u2DelayCellOfst[0]=17 cells (5 PI)
8508 12:47:56.756103 u2DelayCellOfst[1]=10 cells (3 PI)
8509 12:47:56.759065 u2DelayCellOfst[2]=0 cells (0 PI)
8510 12:47:56.762749 u2DelayCellOfst[3]=7 cells (2 PI)
8511 12:47:56.765907 u2DelayCellOfst[4]=7 cells (2 PI)
8512 12:47:56.769558 u2DelayCellOfst[5]=17 cells (5 PI)
8513 12:47:56.772587 u2DelayCellOfst[6]=17 cells (5 PI)
8514 12:47:56.772719 u2DelayCellOfst[7]=7 cells (2 PI)
8515 12:47:56.779038 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8516 12:47:56.782497 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8517 12:47:56.782583 == TX Byte 1 ==
8518 12:47:56.786037 u2DelayCellOfst[8]=0 cells (0 PI)
8519 12:47:56.789152 u2DelayCellOfst[9]=7 cells (2 PI)
8520 12:47:56.792192 u2DelayCellOfst[10]=10 cells (3 PI)
8521 12:47:56.795829 u2DelayCellOfst[11]=7 cells (2 PI)
8522 12:47:56.798990 u2DelayCellOfst[12]=14 cells (4 PI)
8523 12:47:56.802686 u2DelayCellOfst[13]=17 cells (5 PI)
8524 12:47:56.805707 u2DelayCellOfst[14]=17 cells (5 PI)
8525 12:47:56.808916 u2DelayCellOfst[15]=17 cells (5 PI)
8526 12:47:56.812673 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8527 12:47:56.819165 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8528 12:47:56.819369 DramC Write-DBI on
8529 12:47:56.819541 ==
8530 12:47:56.822537 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 12:47:56.825502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 12:47:56.825705 ==
8533 12:47:56.828958
8534 12:47:56.829180
8535 12:47:56.829418 TX Vref Scan disable
8536 12:47:56.832449 == TX Byte 0 ==
8537 12:47:56.835505 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8538 12:47:56.839262 == TX Byte 1 ==
8539 12:47:56.842215 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8540 12:47:56.842447 DramC Write-DBI off
8541 12:47:56.842643
8542 12:47:56.845974 [DATLAT]
8543 12:47:56.846205 Freq=1600, CH1 RK0
8544 12:47:56.846406
8545 12:47:56.848971 DATLAT Default: 0xf
8546 12:47:56.849173 0, 0xFFFF, sum = 0
8547 12:47:56.852571 1, 0xFFFF, sum = 0
8548 12:47:56.852789 2, 0xFFFF, sum = 0
8549 12:47:56.855800 3, 0xFFFF, sum = 0
8550 12:47:56.856036 4, 0xFFFF, sum = 0
8551 12:47:56.859580 5, 0xFFFF, sum = 0
8552 12:47:56.859791 6, 0xFFFF, sum = 0
8553 12:47:56.862715 7, 0xFFFF, sum = 0
8554 12:47:56.863018 8, 0xFFFF, sum = 0
8555 12:47:56.865824 9, 0xFFFF, sum = 0
8556 12:47:56.868988 10, 0xFFFF, sum = 0
8557 12:47:56.869222 11, 0xFFFF, sum = 0
8558 12:47:56.872525 12, 0xFFFF, sum = 0
8559 12:47:56.872802 13, 0xFFFF, sum = 0
8560 12:47:56.876160 14, 0x0, sum = 1
8561 12:47:56.876403 15, 0x0, sum = 2
8562 12:47:56.876612 16, 0x0, sum = 3
8563 12:47:56.879704 17, 0x0, sum = 4
8564 12:47:56.879936 best_step = 15
8565 12:47:56.880119
8566 12:47:56.882865 ==
8567 12:47:56.883102 Dram Type= 6, Freq= 0, CH_1, rank 0
8568 12:47:56.889576 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8569 12:47:56.889802 ==
8570 12:47:56.890026 RX Vref Scan: 1
8571 12:47:56.890225
8572 12:47:56.892979 Set Vref Range= 24 -> 127
8573 12:47:56.893236
8574 12:47:56.896130 RX Vref 24 -> 127, step: 1
8575 12:47:56.896335
8576 12:47:56.899189 RX Delay 11 -> 252, step: 4
8577 12:47:56.899426
8578 12:47:56.902839 Set Vref, RX VrefLevel [Byte0]: 24
8579 12:47:56.906063 [Byte1]: 24
8580 12:47:56.906243
8581 12:47:56.909161 Set Vref, RX VrefLevel [Byte0]: 25
8582 12:47:56.912854 [Byte1]: 25
8583 12:47:56.913003
8584 12:47:56.915852 Set Vref, RX VrefLevel [Byte0]: 26
8585 12:47:56.919623 [Byte1]: 26
8586 12:47:56.922386
8587 12:47:56.922500 Set Vref, RX VrefLevel [Byte0]: 27
8588 12:47:56.925939 [Byte1]: 27
8589 12:47:56.930039
8590 12:47:56.930147 Set Vref, RX VrefLevel [Byte0]: 28
8591 12:47:56.933542 [Byte1]: 28
8592 12:47:56.937795
8593 12:47:56.937907 Set Vref, RX VrefLevel [Byte0]: 29
8594 12:47:56.940760 [Byte1]: 29
8595 12:47:56.945431
8596 12:47:56.945568 Set Vref, RX VrefLevel [Byte0]: 30
8597 12:47:56.948422 [Byte1]: 30
8598 12:47:56.952803
8599 12:47:56.952911 Set Vref, RX VrefLevel [Byte0]: 31
8600 12:47:56.955938 [Byte1]: 31
8601 12:47:56.960275
8602 12:47:56.960391 Set Vref, RX VrefLevel [Byte0]: 32
8603 12:47:56.963940 [Byte1]: 32
8604 12:47:56.968314
8605 12:47:56.968428 Set Vref, RX VrefLevel [Byte0]: 33
8606 12:47:56.971502 [Byte1]: 33
8607 12:47:56.975826
8608 12:47:56.975942 Set Vref, RX VrefLevel [Byte0]: 34
8609 12:47:56.979132 [Byte1]: 34
8610 12:47:56.983686
8611 12:47:56.983804 Set Vref, RX VrefLevel [Byte0]: 35
8612 12:47:56.986514 [Byte1]: 35
8613 12:47:56.990844
8614 12:47:56.990957 Set Vref, RX VrefLevel [Byte0]: 36
8615 12:47:56.994428 [Byte1]: 36
8616 12:47:56.998339
8617 12:47:56.998460 Set Vref, RX VrefLevel [Byte0]: 37
8618 12:47:57.001759 [Byte1]: 37
8619 12:47:57.006299
8620 12:47:57.006444 Set Vref, RX VrefLevel [Byte0]: 38
8621 12:47:57.009559 [Byte1]: 38
8622 12:47:57.013957
8623 12:47:57.014044 Set Vref, RX VrefLevel [Byte0]: 39
8624 12:47:57.017527 [Byte1]: 39
8625 12:47:57.021135
8626 12:47:57.021260 Set Vref, RX VrefLevel [Byte0]: 40
8627 12:47:57.024945 [Byte1]: 40
8628 12:47:57.029093
8629 12:47:57.029232 Set Vref, RX VrefLevel [Byte0]: 41
8630 12:47:57.032093 [Byte1]: 41
8631 12:47:57.036588
8632 12:47:57.036702 Set Vref, RX VrefLevel [Byte0]: 42
8633 12:47:57.039994 [Byte1]: 42
8634 12:47:57.044466
8635 12:47:57.044591 Set Vref, RX VrefLevel [Byte0]: 43
8636 12:47:57.047347 [Byte1]: 43
8637 12:47:57.051921
8638 12:47:57.052034 Set Vref, RX VrefLevel [Byte0]: 44
8639 12:47:57.055345 [Byte1]: 44
8640 12:47:57.059573
8641 12:47:57.059683 Set Vref, RX VrefLevel [Byte0]: 45
8642 12:47:57.062698 [Byte1]: 45
8643 12:47:57.067228
8644 12:47:57.067339 Set Vref, RX VrefLevel [Byte0]: 46
8645 12:47:57.070348 [Byte1]: 46
8646 12:47:57.074689
8647 12:47:57.074793 Set Vref, RX VrefLevel [Byte0]: 47
8648 12:47:57.077792 [Byte1]: 47
8649 12:47:57.082142
8650 12:47:57.082274 Set Vref, RX VrefLevel [Byte0]: 48
8651 12:47:57.085791 [Byte1]: 48
8652 12:47:57.090175
8653 12:47:57.090292 Set Vref, RX VrefLevel [Byte0]: 49
8654 12:47:57.093437 [Byte1]: 49
8655 12:47:57.097216
8656 12:47:57.097326 Set Vref, RX VrefLevel [Byte0]: 50
8657 12:47:57.100812 [Byte1]: 50
8658 12:47:57.105035
8659 12:47:57.105145 Set Vref, RX VrefLevel [Byte0]: 51
8660 12:47:57.108534 [Byte1]: 51
8661 12:47:57.112999
8662 12:47:57.113119 Set Vref, RX VrefLevel [Byte0]: 52
8663 12:47:57.116014 [Byte1]: 52
8664 12:47:57.120395
8665 12:47:57.120508 Set Vref, RX VrefLevel [Byte0]: 53
8666 12:47:57.123428 [Byte1]: 53
8667 12:47:57.127744
8668 12:47:57.127852 Set Vref, RX VrefLevel [Byte0]: 54
8669 12:47:57.131340 [Byte1]: 54
8670 12:47:57.135627
8671 12:47:57.135732 Set Vref, RX VrefLevel [Byte0]: 55
8672 12:47:57.138657 [Byte1]: 55
8673 12:47:57.143115
8674 12:47:57.143238 Set Vref, RX VrefLevel [Byte0]: 56
8675 12:47:57.146507 [Byte1]: 56
8676 12:47:57.150669
8677 12:47:57.150793 Set Vref, RX VrefLevel [Byte0]: 57
8678 12:47:57.154404 [Byte1]: 57
8679 12:47:57.158627
8680 12:47:57.158740 Set Vref, RX VrefLevel [Byte0]: 58
8681 12:47:57.161625 [Byte1]: 58
8682 12:47:57.165784
8683 12:47:57.165898 Set Vref, RX VrefLevel [Byte0]: 59
8684 12:47:57.169418 [Byte1]: 59
8685 12:47:57.173902
8686 12:47:57.174005 Set Vref, RX VrefLevel [Byte0]: 60
8687 12:47:57.177053 [Byte1]: 60
8688 12:47:57.181450
8689 12:47:57.181580 Set Vref, RX VrefLevel [Byte0]: 61
8690 12:47:57.184534 [Byte1]: 61
8691 12:47:57.189029
8692 12:47:57.189142 Set Vref, RX VrefLevel [Byte0]: 62
8693 12:47:57.192104 [Byte1]: 62
8694 12:47:57.196363
8695 12:47:57.196465 Set Vref, RX VrefLevel [Byte0]: 63
8696 12:47:57.199825 [Byte1]: 63
8697 12:47:57.204337
8698 12:47:57.204449 Set Vref, RX VrefLevel [Byte0]: 64
8699 12:47:57.207445 [Byte1]: 64
8700 12:47:57.211888
8701 12:47:57.211999 Set Vref, RX VrefLevel [Byte0]: 65
8702 12:47:57.214804 [Byte1]: 65
8703 12:47:57.219134
8704 12:47:57.219252 Set Vref, RX VrefLevel [Byte0]: 66
8705 12:47:57.222736 [Byte1]: 66
8706 12:47:57.226990
8707 12:47:57.227103 Set Vref, RX VrefLevel [Byte0]: 67
8708 12:47:57.230061 [Byte1]: 67
8709 12:47:57.234319
8710 12:47:57.234428 Set Vref, RX VrefLevel [Byte0]: 68
8711 12:47:57.237908 [Byte1]: 68
8712 12:47:57.242306
8713 12:47:57.242408 Set Vref, RX VrefLevel [Byte0]: 69
8714 12:47:57.245406 [Byte1]: 69
8715 12:47:57.249574
8716 12:47:57.249653 Set Vref, RX VrefLevel [Byte0]: 70
8717 12:47:57.252900 [Byte1]: 70
8718 12:47:57.257544
8719 12:47:57.257640 Set Vref, RX VrefLevel [Byte0]: 71
8720 12:47:57.260600 [Byte1]: 71
8721 12:47:57.264872
8722 12:47:57.265007 Set Vref, RX VrefLevel [Byte0]: 72
8723 12:47:57.268542 [Byte1]: 72
8724 12:47:57.272472
8725 12:47:57.272615 Set Vref, RX VrefLevel [Byte0]: 73
8726 12:47:57.276246 [Byte1]: 73
8727 12:47:57.280568
8728 12:47:57.280717 Final RX Vref Byte 0 = 62 to rank0
8729 12:47:57.283522 Final RX Vref Byte 1 = 55 to rank0
8730 12:47:57.286770 Final RX Vref Byte 0 = 62 to rank1
8731 12:47:57.290487 Final RX Vref Byte 1 = 55 to rank1==
8732 12:47:57.293604 Dram Type= 6, Freq= 0, CH_1, rank 0
8733 12:47:57.300367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8734 12:47:57.300486 ==
8735 12:47:57.300582 DQS Delay:
8736 12:47:57.300698 DQS0 = 0, DQS1 = 0
8737 12:47:57.303644 DQM Delay:
8738 12:47:57.303753 DQM0 = 131, DQM1 = 124
8739 12:47:57.307099 DQ Delay:
8740 12:47:57.310312 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =132
8741 12:47:57.313784 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8742 12:47:57.316873 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8743 12:47:57.320590 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8744 12:47:57.320742
8745 12:47:57.320814
8746 12:47:57.320882
8747 12:47:57.324020 [DramC_TX_OE_Calibration] TA2
8748 12:47:57.326715 Original DQ_B0 (3 6) =30, OEN = 27
8749 12:47:57.330195 Original DQ_B1 (3 6) =30, OEN = 27
8750 12:47:57.333774 24, 0x0, End_B0=24 End_B1=24
8751 12:47:57.333857 25, 0x0, End_B0=25 End_B1=25
8752 12:47:57.336958 26, 0x0, End_B0=26 End_B1=26
8753 12:47:57.340165 27, 0x0, End_B0=27 End_B1=27
8754 12:47:57.343687 28, 0x0, End_B0=28 End_B1=28
8755 12:47:57.343814 29, 0x0, End_B0=29 End_B1=29
8756 12:47:57.346819 30, 0x0, End_B0=30 End_B1=30
8757 12:47:57.350625 31, 0x4545, End_B0=30 End_B1=30
8758 12:47:57.353715 Byte0 end_step=30 best_step=27
8759 12:47:57.357284 Byte1 end_step=30 best_step=27
8760 12:47:57.360274 Byte0 TX OE(2T, 0.5T) = (3, 3)
8761 12:47:57.360385 Byte1 TX OE(2T, 0.5T) = (3, 3)
8762 12:47:57.360483
8763 12:47:57.360573
8764 12:47:57.370346 [DQSOSCAuto] RK0, (LSB)MR18= 0x1600, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 398 ps
8765 12:47:57.374088 CH1 RK0: MR19=303, MR18=1600
8766 12:47:57.377040 CH1_RK0: MR19=0x303, MR18=0x1600, DQSOSC=398, MR23=63, INC=23, DEC=15
8767 12:47:57.380577
8768 12:47:57.384188 ----->DramcWriteLeveling(PI) begin...
8769 12:47:57.384300 ==
8770 12:47:57.387314 Dram Type= 6, Freq= 0, CH_1, rank 1
8771 12:47:57.390416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 12:47:57.390516 ==
8773 12:47:57.394103 Write leveling (Byte 0): 26 => 26
8774 12:47:57.397258 Write leveling (Byte 1): 28 => 28
8775 12:47:57.400317 DramcWriteLeveling(PI) end<-----
8776 12:47:57.400425
8777 12:47:57.400524 ==
8778 12:47:57.404060 Dram Type= 6, Freq= 0, CH_1, rank 1
8779 12:47:57.407254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8780 12:47:57.407366 ==
8781 12:47:57.411038 [Gating] SW mode calibration
8782 12:47:57.417365 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8783 12:47:57.420600 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8784 12:47:57.427512 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 12:47:57.430868 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 12:47:57.434092 1 4 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8787 12:47:57.440967 1 4 12 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
8788 12:47:57.443969 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8789 12:47:57.447692 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 12:47:57.454372 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 12:47:57.457394 1 4 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
8792 12:47:57.461139 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 12:47:57.467620 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 12:47:57.471124 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
8795 12:47:57.474423 1 5 12 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
8796 12:47:57.481056 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 12:47:57.484110 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 12:47:57.487840 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 12:47:57.490998 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 12:47:57.498021 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 12:47:57.501049 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 12:47:57.504170 1 6 8 | B1->B0 | 2424 3d3d | 0 0 | (0 0) (0 0)
8803 12:47:57.511041 1 6 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
8804 12:47:57.514775 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 12:47:57.517657 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 12:47:57.524335 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 12:47:57.527700 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 12:47:57.531373 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 12:47:57.538096 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8810 12:47:57.541089 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8811 12:47:57.544432 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8812 12:47:57.551273 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8813 12:47:57.554800 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 12:47:57.557863 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 12:47:57.561666 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 12:47:57.567945 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 12:47:57.571793 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 12:47:57.574855 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 12:47:57.581750 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 12:47:57.584963 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 12:47:57.588055 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 12:47:57.594620 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 12:47:57.598333 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 12:47:57.601377 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 12:47:57.608288 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8826 12:47:57.611400 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8827 12:47:57.614544 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8828 12:47:57.618299 Total UI for P1: 0, mck2ui 16
8829 12:47:57.621352 best dqsien dly found for B0: ( 1, 9, 6)
8830 12:47:57.628191 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8831 12:47:57.631607 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 12:47:57.634970 Total UI for P1: 0, mck2ui 16
8833 12:47:57.638227 best dqsien dly found for B1: ( 1, 9, 12)
8834 12:47:57.641820 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8835 12:47:57.644702 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8836 12:47:57.644866
8837 12:47:57.648423 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8838 12:47:57.651329 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8839 12:47:57.654908 [Gating] SW calibration Done
8840 12:47:57.655109 ==
8841 12:47:57.658733 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 12:47:57.661804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 12:47:57.662463 ==
8844 12:47:57.665196 RX Vref Scan: 0
8845 12:47:57.665788
8846 12:47:57.668266 RX Vref 0 -> 0, step: 1
8847 12:47:57.668924
8848 12:47:57.669514 RX Delay 0 -> 252, step: 8
8849 12:47:57.675066 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8850 12:47:57.678204 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8851 12:47:57.681892 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8852 12:47:57.685083 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8853 12:47:57.688528 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8854 12:47:57.691886 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8855 12:47:57.698326 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8856 12:47:57.702058 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8857 12:47:57.705157 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8858 12:47:57.708085 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8859 12:47:57.711785 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8860 12:47:57.718104 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8861 12:47:57.721829 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8862 12:47:57.724956 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8863 12:47:57.728161 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8864 12:47:57.734998 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8865 12:47:57.735204 ==
8866 12:47:57.738174 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 12:47:57.741510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 12:47:57.741670 ==
8869 12:47:57.741870 DQS Delay:
8870 12:47:57.744795 DQS0 = 0, DQS1 = 0
8871 12:47:57.744961 DQM Delay:
8872 12:47:57.748313 DQM0 = 132, DQM1 = 127
8873 12:47:57.748422 DQ Delay:
8874 12:47:57.751159 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =135
8875 12:47:57.754750 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8876 12:47:57.758253 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8877 12:47:57.761171 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8878 12:47:57.761290
8879 12:47:57.761390
8880 12:47:57.761477 ==
8881 12:47:57.764755 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 12:47:57.771321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 12:47:57.771431 ==
8884 12:47:57.771531
8885 12:47:57.771623
8886 12:47:57.771715 TX Vref Scan disable
8887 12:47:57.774981 == TX Byte 0 ==
8888 12:47:57.778729 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8889 12:47:57.781829 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8890 12:47:57.785056 == TX Byte 1 ==
8891 12:47:57.788114 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8892 12:47:57.795073 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8893 12:47:57.795182 ==
8894 12:47:57.798777 Dram Type= 6, Freq= 0, CH_1, rank 1
8895 12:47:57.801669 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8896 12:47:57.801783 ==
8897 12:47:57.814696
8898 12:47:57.818289 TX Vref early break, caculate TX vref
8899 12:47:57.821498 TX Vref=16, minBit 8, minWin=22, winSum=379
8900 12:47:57.825207 TX Vref=18, minBit 6, minWin=23, winSum=385
8901 12:47:57.828263 TX Vref=20, minBit 8, minWin=23, winSum=395
8902 12:47:57.831381 TX Vref=22, minBit 8, minWin=23, winSum=399
8903 12:47:57.835104 TX Vref=24, minBit 8, minWin=24, winSum=410
8904 12:47:57.842019 TX Vref=26, minBit 8, minWin=24, winSum=414
8905 12:47:57.845067 TX Vref=28, minBit 5, minWin=25, winSum=423
8906 12:47:57.848433 TX Vref=30, minBit 5, minWin=25, winSum=418
8907 12:47:57.852039 TX Vref=32, minBit 4, minWin=25, winSum=413
8908 12:47:57.854988 TX Vref=34, minBit 8, minWin=24, winSum=403
8909 12:47:57.858623 TX Vref=36, minBit 0, minWin=24, winSum=396
8910 12:47:57.865056 [TxChooseVref] Worse bit 5, Min win 25, Win sum 423, Final Vref 28
8911 12:47:57.865165
8912 12:47:57.868564 Final TX Range 0 Vref 28
8913 12:47:57.868648
8914 12:47:57.868728 ==
8915 12:47:57.872074 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 12:47:57.874980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 12:47:57.875064 ==
8918 12:47:57.875131
8919 12:47:57.875193
8920 12:47:57.878618 TX Vref Scan disable
8921 12:47:57.884968 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8922 12:47:57.885079 == TX Byte 0 ==
8923 12:47:57.888633 u2DelayCellOfst[0]=17 cells (5 PI)
8924 12:47:57.891716 u2DelayCellOfst[1]=14 cells (4 PI)
8925 12:47:57.894790 u2DelayCellOfst[2]=0 cells (0 PI)
8926 12:47:57.898443 u2DelayCellOfst[3]=10 cells (3 PI)
8927 12:47:57.901568 u2DelayCellOfst[4]=14 cells (4 PI)
8928 12:47:57.905390 u2DelayCellOfst[5]=24 cells (7 PI)
8929 12:47:57.908457 u2DelayCellOfst[6]=21 cells (6 PI)
8930 12:47:57.911448 u2DelayCellOfst[7]=10 cells (3 PI)
8931 12:47:57.914949 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8932 12:47:57.918572 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8933 12:47:57.921376 == TX Byte 1 ==
8934 12:47:57.921492 u2DelayCellOfst[8]=0 cells (0 PI)
8935 12:47:57.925058 u2DelayCellOfst[9]=3 cells (1 PI)
8936 12:47:57.928430 u2DelayCellOfst[10]=10 cells (3 PI)
8937 12:47:57.931612 u2DelayCellOfst[11]=7 cells (2 PI)
8938 12:47:57.935359 u2DelayCellOfst[12]=14 cells (4 PI)
8939 12:47:57.938431 u2DelayCellOfst[13]=14 cells (4 PI)
8940 12:47:57.941612 u2DelayCellOfst[14]=17 cells (5 PI)
8941 12:47:57.945266 u2DelayCellOfst[15]=14 cells (4 PI)
8942 12:47:57.948644 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8943 12:47:57.955364 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8944 12:47:57.955491 DramC Write-DBI on
8945 12:47:57.955598 ==
8946 12:47:57.958361 Dram Type= 6, Freq= 0, CH_1, rank 1
8947 12:47:57.961524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8948 12:47:57.964913 ==
8949 12:47:57.965028
8950 12:47:57.965121
8951 12:47:57.965208 TX Vref Scan disable
8952 12:47:57.968277 == TX Byte 0 ==
8953 12:47:57.971802 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8954 12:47:57.975262 == TX Byte 1 ==
8955 12:47:57.978581 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8956 12:47:57.978699 DramC Write-DBI off
8957 12:47:57.981552
8958 12:47:57.981656 [DATLAT]
8959 12:47:57.981795 Freq=1600, CH1 RK1
8960 12:47:57.981913
8961 12:47:57.985008 DATLAT Default: 0xf
8962 12:47:57.985123 0, 0xFFFF, sum = 0
8963 12:47:57.988685 1, 0xFFFF, sum = 0
8964 12:47:57.988803 2, 0xFFFF, sum = 0
8965 12:47:57.991818 3, 0xFFFF, sum = 0
8966 12:47:57.991916 4, 0xFFFF, sum = 0
8967 12:47:57.995505 5, 0xFFFF, sum = 0
8968 12:47:57.995625 6, 0xFFFF, sum = 0
8969 12:47:57.998699 7, 0xFFFF, sum = 0
8970 12:47:58.001859 8, 0xFFFF, sum = 0
8971 12:47:58.001950 9, 0xFFFF, sum = 0
8972 12:47:58.005558 10, 0xFFFF, sum = 0
8973 12:47:58.005674 11, 0xFFFF, sum = 0
8974 12:47:58.008617 12, 0xFFFF, sum = 0
8975 12:47:58.008743 13, 0xFFFF, sum = 0
8976 12:47:58.011729 14, 0x0, sum = 1
8977 12:47:58.011857 15, 0x0, sum = 2
8978 12:47:58.015434 16, 0x0, sum = 3
8979 12:47:58.015550 17, 0x0, sum = 4
8980 12:47:58.015645 best_step = 15
8981 12:47:58.018499
8982 12:47:58.018613 ==
8983 12:47:58.022231 Dram Type= 6, Freq= 0, CH_1, rank 1
8984 12:47:58.025249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8985 12:47:58.025349 ==
8986 12:47:58.025443 RX Vref Scan: 0
8987 12:47:58.025532
8988 12:47:58.028838 RX Vref 0 -> 0, step: 1
8989 12:47:58.028935
8990 12:47:58.032185 RX Delay 11 -> 252, step: 4
8991 12:47:58.035422 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8992 12:47:58.038608 iDelay=191, Bit 1, Center 126 (75 ~ 178) 104
8993 12:47:58.045195 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
8994 12:47:58.048891 iDelay=191, Bit 3, Center 128 (75 ~ 182) 108
8995 12:47:58.051954 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8996 12:47:58.055753 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
8997 12:47:58.058692 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8998 12:47:58.065866 iDelay=191, Bit 7, Center 126 (75 ~ 178) 104
8999 12:47:58.068929 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
9000 12:47:58.072402 iDelay=191, Bit 9, Center 114 (59 ~ 170) 112
9001 12:47:58.075389 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
9002 12:47:58.078736 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
9003 12:47:58.085669 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
9004 12:47:58.089243 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
9005 12:47:58.092195 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
9006 12:47:58.095779 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
9007 12:47:58.095895 ==
9008 12:47:58.098825 Dram Type= 6, Freq= 0, CH_1, rank 1
9009 12:47:58.102141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9010 12:47:58.105837 ==
9011 12:47:58.105958 DQS Delay:
9012 12:47:58.106081 DQS0 = 0, DQS1 = 0
9013 12:47:58.108868 DQM Delay:
9014 12:47:58.108979 DQM0 = 130, DQM1 = 126
9015 12:47:58.111876 DQ Delay:
9016 12:47:58.115590 DQ0 =134, DQ1 =126, DQ2 =118, DQ3 =128
9017 12:47:58.119190 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
9018 12:47:58.122324 DQ8 =114, DQ9 =114, DQ10 =126, DQ11 =118
9019 12:47:58.125468 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
9020 12:47:58.125579
9021 12:47:58.125675
9022 12:47:58.125772
9023 12:47:58.129147 [DramC_TX_OE_Calibration] TA2
9024 12:47:58.132190 Original DQ_B0 (3 6) =30, OEN = 27
9025 12:47:58.135830 Original DQ_B1 (3 6) =30, OEN = 27
9026 12:47:58.135939 24, 0x0, End_B0=24 End_B1=24
9027 12:47:58.138909 25, 0x0, End_B0=25 End_B1=25
9028 12:47:58.142431 26, 0x0, End_B0=26 End_B1=26
9029 12:47:58.145854 27, 0x0, End_B0=27 End_B1=27
9030 12:47:58.149159 28, 0x0, End_B0=28 End_B1=28
9031 12:47:58.149277 29, 0x0, End_B0=29 End_B1=29
9032 12:47:58.152546 30, 0x0, End_B0=30 End_B1=30
9033 12:47:58.155747 31, 0x4141, End_B0=30 End_B1=30
9034 12:47:58.158871 Byte0 end_step=30 best_step=27
9035 12:47:58.162401 Byte1 end_step=30 best_step=27
9036 12:47:58.162485 Byte0 TX OE(2T, 0.5T) = (3, 3)
9037 12:47:58.166085 Byte1 TX OE(2T, 0.5T) = (3, 3)
9038 12:47:58.166166
9039 12:47:58.166231
9040 12:47:58.175784 [DQSOSCAuto] RK1, (LSB)MR18= 0x1219, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
9041 12:47:58.179400 CH1 RK1: MR19=303, MR18=1219
9042 12:47:58.182433 CH1_RK1: MR19=0x303, MR18=0x1219, DQSOSC=397, MR23=63, INC=23, DEC=15
9043 12:47:58.185859 [RxdqsGatingPostProcess] freq 1600
9044 12:47:58.192344 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9045 12:47:58.195982 best DQS0 dly(2T, 0.5T) = (1, 1)
9046 12:47:58.198830 best DQS1 dly(2T, 0.5T) = (1, 1)
9047 12:47:58.202468 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9048 12:47:58.205527 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9049 12:47:58.208895 best DQS0 dly(2T, 0.5T) = (1, 1)
9050 12:47:58.209001 best DQS1 dly(2T, 0.5T) = (1, 1)
9051 12:47:58.212413 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9052 12:47:58.215606 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9053 12:47:58.219431 Pre-setting of DQS Precalculation
9054 12:47:58.226014 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9055 12:47:58.232286 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9056 12:47:58.239125 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9057 12:47:58.239248
9058 12:47:58.239341
9059 12:47:58.242266 [Calibration Summary] 3200 Mbps
9060 12:47:58.242366 CH 0, Rank 0
9061 12:47:58.246020 SW Impedance : PASS
9062 12:47:58.249094 DUTY Scan : NO K
9063 12:47:58.249192 ZQ Calibration : PASS
9064 12:47:58.252685 Jitter Meter : NO K
9065 12:47:58.256006 CBT Training : PASS
9066 12:47:58.256147 Write leveling : PASS
9067 12:47:58.259234 RX DQS gating : PASS
9068 12:47:58.262880 RX DQ/DQS(RDDQC) : PASS
9069 12:47:58.262991 TX DQ/DQS : PASS
9070 12:47:58.265964 RX DATLAT : PASS
9071 12:47:58.269143 RX DQ/DQS(Engine): PASS
9072 12:47:58.269247 TX OE : PASS
9073 12:47:58.269338 All Pass.
9074 12:47:58.269425
9075 12:47:58.272637 CH 0, Rank 1
9076 12:47:58.276024 SW Impedance : PASS
9077 12:47:58.276129 DUTY Scan : NO K
9078 12:47:58.279153 ZQ Calibration : PASS
9079 12:47:58.279255 Jitter Meter : NO K
9080 12:47:58.283001 CBT Training : PASS
9081 12:47:58.285953 Write leveling : PASS
9082 12:47:58.286078 RX DQS gating : PASS
9083 12:47:58.289197 RX DQ/DQS(RDDQC) : PASS
9084 12:47:58.292720 TX DQ/DQS : PASS
9085 12:47:58.292835 RX DATLAT : PASS
9086 12:47:58.295599 RX DQ/DQS(Engine): PASS
9087 12:47:58.299200 TX OE : PASS
9088 12:47:58.299305 All Pass.
9089 12:47:58.299399
9090 12:47:58.299494 CH 1, Rank 0
9091 12:47:58.302248 SW Impedance : PASS
9092 12:47:58.305716 DUTY Scan : NO K
9093 12:47:58.305802 ZQ Calibration : PASS
9094 12:47:58.309360 Jitter Meter : NO K
9095 12:47:58.312377 CBT Training : PASS
9096 12:47:58.312482 Write leveling : PASS
9097 12:47:58.315551 RX DQS gating : PASS
9098 12:47:58.318802 RX DQ/DQS(RDDQC) : PASS
9099 12:47:58.318947 TX DQ/DQS : PASS
9100 12:47:58.322388 RX DATLAT : PASS
9101 12:47:58.322492 RX DQ/DQS(Engine): PASS
9102 12:47:58.325551 TX OE : PASS
9103 12:47:58.325651 All Pass.
9104 12:47:58.325753
9105 12:47:58.329122 CH 1, Rank 1
9106 12:47:58.329222 SW Impedance : PASS
9107 12:47:58.332225 DUTY Scan : NO K
9108 12:47:58.335876 ZQ Calibration : PASS
9109 12:47:58.335982 Jitter Meter : NO K
9110 12:47:58.339031 CBT Training : PASS
9111 12:47:58.342094 Write leveling : PASS
9112 12:47:58.342201 RX DQS gating : PASS
9113 12:47:58.345882 RX DQ/DQS(RDDQC) : PASS
9114 12:47:58.349061 TX DQ/DQS : PASS
9115 12:47:58.349169 RX DATLAT : PASS
9116 12:47:58.352827 RX DQ/DQS(Engine): PASS
9117 12:47:58.355931 TX OE : PASS
9118 12:47:58.356033 All Pass.
9119 12:47:58.356125
9120 12:47:58.356213 DramC Write-DBI on
9121 12:47:58.358940 PER_BANK_REFRESH: Hybrid Mode
9122 12:47:58.362397 TX_TRACKING: ON
9123 12:47:58.369434 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9124 12:47:58.379083 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9125 12:47:58.385878 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9126 12:47:58.388917 [FAST_K] Save calibration result to emmc
9127 12:47:58.392622 sync common calibartion params.
9128 12:47:58.392762 sync cbt_mode0:1, 1:1
9129 12:47:58.396099 dram_init: ddr_geometry: 2
9130 12:47:58.399618 dram_init: ddr_geometry: 2
9131 12:47:58.402404 dram_init: ddr_geometry: 2
9132 12:47:58.402510 0:dram_rank_size:100000000
9133 12:47:58.405808 1:dram_rank_size:100000000
9134 12:47:58.412859 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9135 12:47:58.412990 DFS_SHUFFLE_HW_MODE: ON
9136 12:47:58.419538 dramc_set_vcore_voltage set vcore to 725000
9137 12:47:58.419653 Read voltage for 1600, 0
9138 12:47:58.419723 Vio18 = 0
9139 12:47:58.422572 Vcore = 725000
9140 12:47:58.422655 Vdram = 0
9141 12:47:58.422720 Vddq = 0
9142 12:47:58.425641 Vmddr = 0
9143 12:47:58.425763 switch to 3200 Mbps bootup
9144 12:47:58.429214 [DramcRunTimeConfig]
9145 12:47:58.429337 PHYPLL
9146 12:47:58.432927 DPM_CONTROL_AFTERK: ON
9147 12:47:58.433012 PER_BANK_REFRESH: ON
9148 12:47:58.435942 REFRESH_OVERHEAD_REDUCTION: ON
9149 12:47:58.439068 CMD_PICG_NEW_MODE: OFF
9150 12:47:58.439179 XRTWTW_NEW_MODE: ON
9151 12:47:58.442831 XRTRTR_NEW_MODE: ON
9152 12:47:58.442936 TX_TRACKING: ON
9153 12:47:58.446006 RDSEL_TRACKING: OFF
9154 12:47:58.449206 DQS Precalculation for DVFS: ON
9155 12:47:58.449358 RX_TRACKING: OFF
9156 12:47:58.452935 HW_GATING DBG: ON
9157 12:47:58.453060 ZQCS_ENABLE_LP4: ON
9158 12:47:58.456209 RX_PICG_NEW_MODE: ON
9159 12:47:58.456356 TX_PICG_NEW_MODE: ON
9160 12:47:58.459802 ENABLE_RX_DCM_DPHY: ON
9161 12:47:58.462841 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9162 12:47:58.465792 DUMMY_READ_FOR_TRACKING: OFF
9163 12:47:58.465901 !!! SPM_CONTROL_AFTERK: OFF
9164 12:47:58.469900 !!! SPM could not control APHY
9165 12:47:58.472655 IMPEDANCE_TRACKING: ON
9166 12:47:58.472783 TEMP_SENSOR: ON
9167 12:47:58.476337 HW_SAVE_FOR_SR: OFF
9168 12:47:58.479276 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9169 12:47:58.482505 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9170 12:47:58.482612 Read ODT Tracking: ON
9171 12:47:58.486071 Refresh Rate DeBounce: ON
9172 12:47:58.489629 DFS_NO_QUEUE_FLUSH: ON
9173 12:47:58.492993 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9174 12:47:58.493108 ENABLE_DFS_RUNTIME_MRW: OFF
9175 12:47:58.496244 DDR_RESERVE_NEW_MODE: ON
9176 12:47:58.499122 MR_CBT_SWITCH_FREQ: ON
9177 12:47:58.499235 =========================
9178 12:47:58.519803 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9179 12:47:58.523231 dram_init: ddr_geometry: 2
9180 12:47:58.541176 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9181 12:47:58.544949 dram_init: dram init end (result: 0)
9182 12:47:58.551188 DRAM-K: Full calibration passed in 24597 msecs
9183 12:47:58.554265 MRC: failed to locate region type 0.
9184 12:47:58.554378 DRAM rank0 size:0x100000000,
9185 12:47:58.558115 DRAM rank1 size=0x100000000
9186 12:47:58.568017 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9187 12:47:58.574499 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9188 12:47:58.580582 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9189 12:47:58.587407 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9190 12:47:58.591192 DRAM rank0 size:0x100000000,
9191 12:47:58.594332 DRAM rank1 size=0x100000000
9192 12:47:58.594437 CBMEM:
9193 12:47:58.598103 IMD: root @ 0xfffff000 254 entries.
9194 12:47:58.600882 IMD: root @ 0xffffec00 62 entries.
9195 12:47:58.604191 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9196 12:47:58.607624 WARNING: RO_VPD is uninitialized or empty.
9197 12:47:58.613980 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9198 12:47:58.621307 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9199 12:47:58.634079 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9200 12:47:58.645515 BS: romstage times (exec / console): total (unknown) / 24099 ms
9201 12:47:58.645661
9202 12:47:58.645734
9203 12:47:58.655379 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9204 12:47:58.659173 ARM64: Exception handlers installed.
9205 12:47:58.662385 ARM64: Testing exception
9206 12:47:58.665700 ARM64: Done test exception
9207 12:47:58.665788 Enumerating buses...
9208 12:47:58.668864 Show all devs... Before device enumeration.
9209 12:47:58.671992 Root Device: enabled 1
9210 12:47:58.675714 CPU_CLUSTER: 0: enabled 1
9211 12:47:58.675803 CPU: 00: enabled 1
9212 12:47:58.678778 Compare with tree...
9213 12:47:58.678873 Root Device: enabled 1
9214 12:47:58.682247 CPU_CLUSTER: 0: enabled 1
9215 12:47:58.685545 CPU: 00: enabled 1
9216 12:47:58.685620 Root Device scanning...
9217 12:47:58.688829 scan_static_bus for Root Device
9218 12:47:58.692455 CPU_CLUSTER: 0 enabled
9219 12:47:58.695552 scan_static_bus for Root Device done
9220 12:47:58.699246 scan_bus: bus Root Device finished in 8 msecs
9221 12:47:58.699321 done
9222 12:47:58.705555 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9223 12:47:58.709106 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9224 12:47:58.715384 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9225 12:47:58.719028 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9226 12:47:58.722551 Allocating resources...
9227 12:47:58.722649 Reading resources...
9228 12:47:58.728883 Root Device read_resources bus 0 link: 0
9229 12:47:58.728986 DRAM rank0 size:0x100000000,
9230 12:47:58.732073 DRAM rank1 size=0x100000000
9231 12:47:58.735799 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9232 12:47:58.739241 CPU: 00 missing read_resources
9233 12:47:58.742128 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9234 12:47:58.745606 Root Device read_resources bus 0 link: 0 done
9235 12:47:58.748874 Done reading resources.
9236 12:47:58.755687 Show resources in subtree (Root Device)...After reading.
9237 12:47:58.758836 Root Device child on link 0 CPU_CLUSTER: 0
9238 12:47:58.762559 CPU_CLUSTER: 0 child on link 0 CPU: 00
9239 12:47:58.769400 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9240 12:47:58.772532 CPU: 00
9241 12:47:58.775725 Root Device assign_resources, bus 0 link: 0
9242 12:47:58.779499 CPU_CLUSTER: 0 missing set_resources
9243 12:47:58.782534 Root Device assign_resources, bus 0 link: 0 done
9244 12:47:58.785688 Done setting resources.
9245 12:47:58.792449 Show resources in subtree (Root Device)...After assigning values.
9246 12:47:58.795732 Root Device child on link 0 CPU_CLUSTER: 0
9247 12:47:58.799362 CPU_CLUSTER: 0 child on link 0 CPU: 00
9248 12:47:58.809132 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9249 12:47:58.809231 CPU: 00
9250 12:47:58.812312 Done allocating resources.
9251 12:47:58.815744 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9252 12:47:58.819141 Enabling resources...
9253 12:47:58.819269 done.
9254 12:47:58.822377 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9255 12:47:58.825791 Initializing devices...
9256 12:47:58.825922 Root Device init
9257 12:47:58.829403 init hardware done!
9258 12:47:58.832516 0x00000018: ctrlr->caps
9259 12:47:58.832638 52.000 MHz: ctrlr->f_max
9260 12:47:58.835549 0.400 MHz: ctrlr->f_min
9261 12:47:58.839171 0x40ff8080: ctrlr->voltages
9262 12:47:58.839294 sclk: 390625
9263 12:47:58.842147 Bus Width = 1
9264 12:47:58.842255 sclk: 390625
9265 12:47:58.842351 Bus Width = 1
9266 12:47:58.845456 Early init status = 3
9267 12:47:58.848838 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9268 12:47:58.853738 in-header: 03 fc 00 00 01 00 00 00
9269 12:47:58.856511 in-data: 00
9270 12:47:58.859774 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9271 12:47:58.865130 in-header: 03 fd 00 00 00 00 00 00
9272 12:47:58.869051 in-data:
9273 12:47:58.872161 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9274 12:47:58.876526 in-header: 03 fc 00 00 01 00 00 00
9275 12:47:58.879599 in-data: 00
9276 12:47:58.883376 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9277 12:47:58.888420 in-header: 03 fd 00 00 00 00 00 00
9278 12:47:58.892134 in-data:
9279 12:47:58.895330 [SSUSB] Setting up USB HOST controller...
9280 12:47:58.899115 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9281 12:47:58.902294 [SSUSB] phy power-on done.
9282 12:47:58.905202 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9283 12:47:58.911844 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9284 12:47:58.915337 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9285 12:47:58.922361 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9286 12:47:58.928624 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9287 12:47:58.935146 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9288 12:47:58.941804 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9289 12:47:58.948883 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9290 12:47:58.951901 SPM: binary array size = 0x9dc
9291 12:47:58.955343 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9292 12:47:58.961828 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9293 12:47:58.968880 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9294 12:47:58.971529 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9295 12:47:58.978526 configure_display: Starting display init
9296 12:47:59.012363 anx7625_power_on_init: Init interface.
9297 12:47:59.015202 anx7625_disable_pd_protocol: Disabled PD feature.
9298 12:47:59.018487 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9299 12:47:59.046470 anx7625_start_dp_work: Secure OCM version=00
9300 12:47:59.049608 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9301 12:47:59.064281 sp_tx_get_edid_block: EDID Block = 1
9302 12:48:00.657827 Extracted contents:
9303 12:48:00.659783 header: 00 ff ff ff ff ff ff 00
9304 12:48:00.660328 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9305 12:48:00.661085 version: 01 04
9306 12:48:00.661543 basic params: 95 1f 11 78 0a
9307 12:48:00.661642 chroma info: 76 90 94 55 54 90 27 21 50 54
9308 12:48:00.661782 established: 00 00 00
9309 12:48:00.661891 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9310 12:48:00.661984 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9311 12:48:00.662108 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9312 12:48:00.662199 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9313 12:48:00.662322 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9314 12:48:00.662412 extensions: 00
9315 12:48:00.662501 checksum: fb
9316 12:48:00.662585
9317 12:48:00.662673 Manufacturer: IVO Model 57d Serial Number 0
9318 12:48:00.662764 Made week 0 of 2020
9319 12:48:00.662889 EDID version: 1.4
9320 12:48:00.662979 Digital display
9321 12:48:00.663070 6 bits per primary color channel
9322 12:48:00.663162 DisplayPort interface
9323 12:48:00.663253 Maximum image size: 31 cm x 17 cm
9324 12:48:00.663358 Gamma: 220%
9325 12:48:00.663463 Check DPMS levels
9326 12:48:00.663554 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9327 12:48:00.663644 First detailed timing is preferred timing
9328 12:48:00.663736 Established timings supported:
9329 12:48:00.663827 Standard timings supported:
9330 12:48:00.663934 Detailed timings
9331 12:48:00.664027 Hex of detail: 383680a07038204018303c0035ae10000019
9332 12:48:00.664122 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9333 12:48:00.664216 0780 0798 07c8 0820 hborder 0
9334 12:48:00.664309 0438 043b 0447 0458 vborder 0
9335 12:48:00.664401 -hsync -vsync
9336 12:48:00.664496 Did detailed timing
9337 12:48:00.664589 Hex of detail: 000000000000000000000000000000000000
9338 12:48:00.664691 Manufacturer-specified data, tag 0
9339 12:48:00.664796 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9340 12:48:00.664887 ASCII string: InfoVision
9341 12:48:00.665010 Hex of detail: 000000fe00523134304e574635205248200a
9342 12:48:00.665118 ASCII string: R140NWF5 RH
9343 12:48:00.665221 Checksum
9344 12:48:00.665311 Checksum: 0xfb (valid)
9345 12:48:00.665401 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9346 12:48:00.665506 DSI data_rate: 832800000 bps
9347 12:48:00.665612 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9348 12:48:00.665702 anx7625_parse_edid: pixelclock(138800).
9349 12:48:00.665792 hactive(1920), hsync(48), hfp(24), hbp(88)
9350 12:48:00.665898 vactive(1080), vsync(12), vfp(3), vbp(17)
9351 12:48:00.666045 anx7625_dsi_config: config dsi.
9352 12:48:00.666140 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9353 12:48:00.666232 anx7625_dsi_config: success to config DSI
9354 12:48:00.666324 anx7625_dp_start: MIPI phy setup OK.
9355 12:48:00.666416 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9356 12:48:00.666508 mtk_ddp_mode_set invalid vrefresh 60
9357 12:48:00.666601 main_disp_path_setup
9358 12:48:00.666693 ovl_layer_smi_id_en
9359 12:48:00.666786 ovl_layer_smi_id_en
9360 12:48:00.666877 ccorr_config
9361 12:48:00.666969 aal_config
9362 12:48:00.667061 gamma_config
9363 12:48:00.667154 postmask_config
9364 12:48:00.667248 dither_config
9365 12:48:00.667343 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9366 12:48:00.667435 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9367 12:48:00.667534 Root Device init finished in 554 msecs
9368 12:48:00.667632 CPU_CLUSTER: 0 init
9369 12:48:00.667735 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9370 12:48:00.667836 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9371 12:48:00.667928 APU_MBOX 0x190000b0 = 0x10001
9372 12:48:00.668027 APU_MBOX 0x190001b0 = 0x10001
9373 12:48:00.668125 APU_MBOX 0x190005b0 = 0x10001
9374 12:48:00.668221 APU_MBOX 0x190006b0 = 0x10001
9375 12:48:00.668321 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9376 12:48:00.668419 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9377 12:48:00.668515 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9378 12:48:00.668615 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9379 12:48:00.668726 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9380 12:48:00.668821 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9381 12:48:00.668922 CPU_CLUSTER: 0 init finished in 81 msecs
9382 12:48:00.669019 Devices initialized
9383 12:48:00.669111 Show all devs... After init.
9384 12:48:00.669210 Root Device: enabled 1
9385 12:48:00.669306 CPU_CLUSTER: 0: enabled 1
9386 12:48:00.669403 CPU: 00: enabled 1
9387 12:48:00.669501 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9388 12:48:00.669598 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9389 12:48:00.669692 ELOG: NV offset 0x57f000 size 0x1000
9390 12:48:00.669791 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9391 12:48:00.669888 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9392 12:48:00.669983 ELOG: Event(17) added with size 13 at 2023-07-20 12:48:02 UTC
9393 12:48:00.670082 out: cmd=0x121: 03 db 21 01 00 00 00 00
9394 12:48:00.670179 in-header: 03 c5 00 00 2c 00 00 00
9395 12:48:00.670273 in-data: 9a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9396 12:48:00.670378 ELOG: Event(A1) added with size 10 at 2023-07-20 12:48:02 UTC
9397 12:48:00.670479 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9398 12:48:00.670569 ELOG: Event(A0) added with size 9 at 2023-07-20 12:48:02 UTC
9399 12:48:00.670668 elog_add_boot_reason: Logged dev mode boot
9400 12:48:00.703608 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9401 12:48:00.703966 Finalize devices...
9402 12:48:00.704210 Devices finalized
9403 12:48:00.704410 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9404 12:48:00.704610 Writing coreboot table at 0xffe64000
9405 12:48:00.704797 0. 000000000010a000-0000000000113fff: RAMSTAGE
9406 12:48:00.704965 1. 0000000040000000-00000000400fffff: RAM
9407 12:48:00.705173 2. 0000000040100000-000000004032afff: RAMSTAGE
9408 12:48:00.705371 3. 000000004032b000-00000000545fffff: RAM
9409 12:48:00.705603 4. 0000000054600000-000000005465ffff: BL31
9410 12:48:00.705785 5. 0000000054660000-00000000ffe63fff: RAM
9411 12:48:00.705954 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9412 12:48:00.706138 7. 0000000100000000-000000023fffffff: RAM
9413 12:48:00.706324 Passing 5 GPIOs to payload:
9414 12:48:00.706507 NAME | PORT | POLARITY | VALUE
9415 12:48:00.706696 EC in RW | 0x000000aa | low | undefined
9416 12:48:00.706888 EC interrupt | 0x00000005 | low | undefined
9417 12:48:00.707071 TPM interrupt | 0x000000ab | high | undefined
9418 12:48:00.707297 SD card detect | 0x00000011 | high | undefined
9419 12:48:00.707449 speaker enable | 0x00000093 | high | undefined
9420 12:48:00.707631 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9421 12:48:00.707765 in-header: 03 f9 00 00 02 00 00 00
9422 12:48:00.707911 in-data: 02 00
9423 12:48:00.708061 ADC[4]: Raw value=900959 ID=7
9424 12:48:00.708176 ADC[3]: Raw value=213336 ID=1
9425 12:48:00.708263 RAM Code: 0x71
9426 12:48:00.708402 ADC[6]: Raw value=74557 ID=0
9427 12:48:00.708542 ADC[5]: Raw value=212229 ID=1
9428 12:48:00.708721 SKU Code: 0x1
9429 12:48:00.708857 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ce41
9430 12:48:00.709005 coreboot table: 964 bytes.
9431 12:48:00.709156 IMD ROOT 0. 0xfffff000 0x00001000
9432 12:48:00.709302 IMD SMALL 1. 0xffffe000 0x00001000
9433 12:48:00.709429 RO MCACHE 2. 0xffffc000 0x00001104
9434 12:48:00.709565 CONSOLE 3. 0xfff7c000 0x00080000
9435 12:48:00.709697 FMAP 4. 0xfff7b000 0x00000452
9436 12:48:00.709835 TIME STAMP 5. 0xfff7a000 0x00000910
9437 12:48:00.709955 VBOOT WORK 6. 0xfff66000 0x00014000
9438 12:48:00.710152 RAMOOPS 7. 0xffe66000 0x00100000
9439 12:48:00.710292 COREBOOT 8. 0xffe64000 0x00002000
9440 12:48:00.710424 IMD small region:
9441 12:48:00.710573 IMD ROOT 0. 0xffffec00 0x00000400
9442 12:48:00.710711 VPD 1. 0xffffeba0 0x0000004c
9443 12:48:00.710844 MMC STATUS 2. 0xffffeb80 0x00000004
9444 12:48:00.710975 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9445 12:48:00.711105 Probing TPM: done!
9446 12:48:00.711236 Connected to device vid:did:rid of 1ae0:0028:00
9447 12:48:00.711368 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9448 12:48:00.711502 Initialized TPM device CR50 revision 0
9449 12:48:00.711633 Checking cr50 for pending updates
9450 12:48:00.711740 Reading cr50 TPM mode
9451 12:48:00.711844 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9452 12:48:00.711947 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9453 12:48:00.712063 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9454 12:48:00.712198 Checking segment from ROM address 0x40100000
9455 12:48:00.712329 Checking segment from ROM address 0x4010001c
9456 12:48:00.712474 Loading segment from ROM address 0x40100000
9457 12:48:00.712607 code (compression=0)
9458 12:48:00.712753 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9459 12:48:00.712911 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9460 12:48:00.713050 it's not compressed!
9461 12:48:00.713183 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9462 12:48:00.713320 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9463 12:48:00.713451 Loading segment from ROM address 0x4010001c
9464 12:48:00.713584 Entry Point 0x80000000
9465 12:48:00.713714 Loaded segments
9466 12:48:00.713848 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9467 12:48:00.713979 Jumping to boot code at 0x80000000(0xffe64000)
9468 12:48:00.714135 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9469 12:48:00.714276 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9470 12:48:00.714426 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9471 12:48:00.714561 Checking segment from ROM address 0x40100000
9472 12:48:00.714691 Checking segment from ROM address 0x4010001c
9473 12:48:00.714826 Loading segment from ROM address 0x40100000
9474 12:48:00.714976 code (compression=1)
9475 12:48:00.715113 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9476 12:48:00.715245 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9477 12:48:00.715377 using LZMA
9478 12:48:00.715510 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9479 12:48:00.715666 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9480 12:48:00.715801 Loading segment from ROM address 0x4010001c
9481 12:48:00.715932 Entry Point 0x54601000
9482 12:48:00.716085 Loaded segments
9483 12:48:00.716274 NOTICE: MT8192 bl31_setup
9484 12:48:00.716424 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9485 12:48:00.716568 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9486 12:48:00.716713 WARNING: region 0:
9487 12:48:00.716848 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9488 12:48:00.716979 WARNING: region 1:
9489 12:48:00.717131 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9490 12:48:00.717264 WARNING: region 2:
9491 12:48:00.717433 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9492 12:48:00.717577 WARNING: region 3:
9493 12:48:00.717928 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9494 12:48:00.718072 WARNING: region 4:
9495 12:48:00.718219 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9496 12:48:00.718354 WARNING: region 5:
9497 12:48:00.718487 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9498 12:48:00.718619 WARNING: region 6:
9499 12:48:00.718767 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9500 12:48:00.718905 WARNING: region 7:
9501 12:48:00.719037 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9502 12:48:00.719197 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9503 12:48:00.719339 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9504 12:48:00.719472 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9505 12:48:00.719607 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9506 12:48:00.719742 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9507 12:48:00.719877 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9508 12:48:00.720007 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9509 12:48:00.720135 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9510 12:48:00.720270 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9511 12:48:00.720399 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9512 12:48:00.720551 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9513 12:48:00.720683 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9514 12:48:00.720808 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9515 12:48:00.720942 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9516 12:48:00.721076 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9517 12:48:00.721204 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9518 12:48:00.721335 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9519 12:48:00.721470 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9520 12:48:00.721598 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9521 12:48:00.721730 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9522 12:48:00.721862 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9523 12:48:00.721995 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9524 12:48:00.722123 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9525 12:48:00.722284 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9526 12:48:00.722433 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9527 12:48:00.722565 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9528 12:48:00.722699 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9529 12:48:00.722830 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9530 12:48:00.722957 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9531 12:48:00.723095 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9532 12:48:00.723228 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9533 12:48:00.723356 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9534 12:48:00.723485 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9535 12:48:00.723621 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9536 12:48:00.723748 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9537 12:48:00.723875 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9538 12:48:00.724009 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9539 12:48:00.724156 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9540 12:48:00.724286 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9541 12:48:00.724418 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9542 12:48:00.724544 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9543 12:48:00.724694 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9544 12:48:00.724830 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9545 12:48:00.724961 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9546 12:48:00.725076 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9547 12:48:00.725193 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9548 12:48:00.725321 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9549 12:48:00.725433 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9550 12:48:00.725545 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9551 12:48:00.725680 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9552 12:48:00.725794 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9553 12:48:00.725930 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9554 12:48:00.726058 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9555 12:48:00.726168 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9556 12:48:00.726304 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9557 12:48:00.726426 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9558 12:48:00.726538 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9559 12:48:00.726659 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9560 12:48:00.726781 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9561 12:48:00.726890 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9562 12:48:00.727005 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9563 12:48:00.727122 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9564 12:48:00.727246 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9565 12:48:00.727363 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9566 12:48:00.727492 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9567 12:48:00.727608 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9568 12:48:00.727722 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9569 12:48:00.727837 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9570 12:48:00.727957 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9571 12:48:00.728072 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9572 12:48:00.728186 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9573 12:48:00.728511 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9574 12:48:00.728634 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9575 12:48:00.728748 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9576 12:48:00.728825 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9577 12:48:00.728908 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9578 12:48:00.728984 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9579 12:48:00.729071 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9580 12:48:00.729171 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9581 12:48:00.729248 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9582 12:48:00.729322 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9583 12:48:00.729397 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9584 12:48:00.729470 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9585 12:48:00.729556 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9586 12:48:00.729631 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9587 12:48:00.729706 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9588 12:48:00.729779 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9589 12:48:00.729852 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9590 12:48:00.729926 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9591 12:48:00.729999 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9592 12:48:00.730116 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9593 12:48:00.730232 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9594 12:48:00.730346 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9595 12:48:00.730461 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9596 12:48:00.730626 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9597 12:48:00.730745 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9598 12:48:00.730859 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9599 12:48:00.730975 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9600 12:48:00.731093 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9601 12:48:00.731210 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9602 12:48:00.731324 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9603 12:48:00.731452 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9604 12:48:00.731564 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9605 12:48:00.731673 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9606 12:48:00.731777 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9607 12:48:00.731889 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9608 12:48:00.731991 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9609 12:48:00.732093 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9610 12:48:00.732215 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9611 12:48:00.732326 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9612 12:48:00.732440 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9613 12:48:00.732543 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9614 12:48:00.732649 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9615 12:48:00.732739 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9616 12:48:00.732814 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9617 12:48:00.732880 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9618 12:48:00.732946 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9619 12:48:00.733011 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9620 12:48:00.733076 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9621 12:48:00.733141 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9622 12:48:00.733206 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9623 12:48:00.733270 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9624 12:48:00.733342 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9625 12:48:00.733407 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9626 12:48:00.733472 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9627 12:48:00.733537 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9628 12:48:00.733601 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9629 12:48:00.733696 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9630 12:48:00.733773 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9631 12:48:00.733848 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9632 12:48:00.733914 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9633 12:48:00.733978 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9634 12:48:00.734043 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9635 12:48:00.734107 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9636 12:48:00.734171 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9637 12:48:00.734235 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9638 12:48:00.734299 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9639 12:48:00.734378 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9640 12:48:00.734452 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9641 12:48:00.734559 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9642 12:48:00.734661 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9643 12:48:00.734762 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9644 12:48:00.734875 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9645 12:48:00.734981 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9646 12:48:00.735083 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9647 12:48:00.735184 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9648 12:48:00.735284 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9649 12:48:00.735586 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9650 12:48:00.735693 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9651 12:48:00.735813 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9652 12:48:00.735883 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9653 12:48:00.735954 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9654 12:48:00.736021 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9655 12:48:00.736088 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9656 12:48:00.736153 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9657 12:48:00.736218 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9658 12:48:00.736282 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9659 12:48:00.736348 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9660 12:48:00.736494 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9661 12:48:00.739290 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9662 12:48:00.745781 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9663 12:48:00.749428 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9664 12:48:00.755567 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9665 12:48:00.759363 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9666 12:48:00.762980 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9667 12:48:00.769137 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9668 12:48:00.772891 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9669 12:48:00.776057 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9670 12:48:00.782923 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9671 12:48:00.786139 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9672 12:48:00.792695 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9673 12:48:00.796065 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9674 12:48:00.799129 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9675 12:48:00.806112 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9676 12:48:00.809186 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9677 12:48:00.815917 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9678 12:48:00.819726 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9679 12:48:00.822591 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9680 12:48:00.829408 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9681 12:48:00.832427 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9682 12:48:00.836238 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9683 12:48:00.842591 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9684 12:48:00.846087 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9685 12:48:00.852756 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9686 12:48:00.856567 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9687 12:48:00.859723 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9688 12:48:00.866227 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9689 12:48:00.869919 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9690 12:48:00.876017 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9691 12:48:00.879874 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9692 12:48:00.882882 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9693 12:48:00.889855 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9694 12:48:00.893045 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9695 12:48:00.899932 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9696 12:48:00.902932 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9697 12:48:00.906603 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9698 12:48:00.912783 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9699 12:48:00.916326 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9700 12:48:00.923183 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9701 12:48:00.926322 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9702 12:48:00.929378 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9703 12:48:00.936615 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9704 12:48:00.939340 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9705 12:48:00.946483 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9706 12:48:00.949490 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9707 12:48:00.956354 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9708 12:48:00.959455 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9709 12:48:00.963156 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9710 12:48:00.969980 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9711 12:48:00.973107 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9712 12:48:00.976813 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9713 12:48:00.983032 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9714 12:48:00.986791 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9715 12:48:00.993017 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9716 12:48:00.996768 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9717 12:48:01.003018 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9718 12:48:01.006913 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9719 12:48:01.009925 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9720 12:48:01.016797 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9721 12:48:01.019743 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9722 12:48:01.026714 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9723 12:48:01.030121 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9724 12:48:01.033196 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9725 12:48:01.039805 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9726 12:48:01.043598 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9727 12:48:01.049682 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9728 12:48:01.053224 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9729 12:48:01.056839 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9730 12:48:01.063683 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9731 12:48:01.066705 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9732 12:48:01.070672 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9733 12:48:01.073487 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9734 12:48:01.080038 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9735 12:48:01.083384 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9736 12:48:01.086621 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9737 12:48:01.093918 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9738 12:48:01.097039 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9739 12:48:01.100020 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9740 12:48:01.106891 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9741 12:48:01.110054 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9742 12:48:01.113927 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9743 12:48:01.120660 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9744 12:48:01.123597 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9745 12:48:01.127273 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9746 12:48:01.133914 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9747 12:48:01.137101 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9748 12:48:01.144033 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9749 12:48:01.146752 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9750 12:48:01.150370 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9751 12:48:01.157152 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9752 12:48:01.160224 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9753 12:48:01.163778 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9754 12:48:01.170055 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9755 12:48:01.173650 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9756 12:48:01.176861 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9757 12:48:01.183704 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9758 12:48:01.187483 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9759 12:48:01.193566 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9760 12:48:01.196982 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9761 12:48:01.200368 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9762 12:48:01.206876 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9763 12:48:01.210430 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9764 12:48:01.214119 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9765 12:48:01.220472 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9766 12:48:01.224146 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9767 12:48:01.226963 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9768 12:48:01.234187 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9769 12:48:01.237426 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9770 12:48:01.240488 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9771 12:48:01.244212 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9772 12:48:01.250513 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9773 12:48:01.253778 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9774 12:48:01.257191 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9775 12:48:01.260502 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9776 12:48:01.267607 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9777 12:48:01.270680 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9778 12:48:01.273979 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9779 12:48:01.277099 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9780 12:48:01.283725 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9781 12:48:01.287060 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9782 12:48:01.290378 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9783 12:48:01.294134 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9784 12:48:01.300370 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9785 12:48:01.303959 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9786 12:48:01.310310 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9787 12:48:01.313712 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9788 12:48:01.320364 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9789 12:48:01.323649 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9790 12:48:01.327485 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9791 12:48:01.334246 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9792 12:48:01.337377 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9793 12:48:01.340373 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9794 12:48:01.347394 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9795 12:48:01.350554 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9796 12:48:01.357416 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9797 12:48:01.360511 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9798 12:48:01.367312 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9799 12:48:01.370950 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9800 12:48:01.374097 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9801 12:48:01.380625 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9802 12:48:01.383997 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9803 12:48:01.387311 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9804 12:48:01.394134 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9805 12:48:01.397660 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9806 12:48:01.404554 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9807 12:48:01.407842 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9808 12:48:01.410869 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9809 12:48:01.417598 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9810 12:48:01.420780 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9811 12:48:01.427883 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9812 12:48:01.431143 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9813 12:48:01.437412 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9814 12:48:01.441156 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9815 12:48:01.444216 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9816 12:48:01.451159 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9817 12:48:01.454333 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9818 12:48:01.457637 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9819 12:48:01.464689 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9820 12:48:01.467835 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9821 12:48:01.474769 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9822 12:48:01.478206 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9823 12:48:01.481049 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9824 12:48:01.487900 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9825 12:48:01.491273 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9826 12:48:01.498367 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9827 12:48:01.501431 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9828 12:48:01.505113 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9829 12:48:01.511300 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9830 12:48:01.514942 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9831 12:48:01.521421 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9832 12:48:01.524653 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9833 12:48:01.527792 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9834 12:48:01.534670 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9835 12:48:01.538311 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9836 12:48:01.544760 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9837 12:48:01.548102 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9838 12:48:01.551643 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9839 12:48:01.557900 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9840 12:48:01.561119 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9841 12:48:01.568113 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9842 12:48:01.571152 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9843 12:48:01.574959 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9844 12:48:01.581132 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9845 12:48:01.584988 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9846 12:48:01.591545 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9847 12:48:01.594897 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9848 12:48:01.598112 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9849 12:48:01.604813 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9850 12:48:01.608403 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9851 12:48:01.614997 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9852 12:48:01.618317 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9853 12:48:01.621785 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9854 12:48:01.627851 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9855 12:48:01.631459 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9856 12:48:01.637886 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9857 12:48:01.641644 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9858 12:48:01.647885 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9859 12:48:01.651419 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9860 12:48:01.654203 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9861 12:48:01.661038 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9862 12:48:01.664353 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9863 12:48:01.671195 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9864 12:48:01.674323 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9865 12:48:01.681093 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9866 12:48:01.684208 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9867 12:48:01.688049 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9868 12:48:01.694339 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9869 12:48:01.697719 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9870 12:48:01.704819 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9871 12:48:01.707709 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9872 12:48:01.711169 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9873 12:48:01.717991 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9874 12:48:01.720994 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9875 12:48:01.727923 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9876 12:48:01.731411 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9877 12:48:01.738113 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9878 12:48:01.741276 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9879 12:48:01.744357 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9880 12:48:01.751265 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9881 12:48:01.754947 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9882 12:48:01.761242 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9883 12:48:01.764965 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9884 12:48:01.771295 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9885 12:48:01.774597 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9886 12:48:01.781223 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9887 12:48:01.784959 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9888 12:48:01.788111 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9889 12:48:01.794983 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9890 12:48:01.798079 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9891 12:48:01.804933 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9892 12:48:01.807833 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9893 12:48:01.814693 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9894 12:48:01.818142 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9895 12:48:01.821373 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9896 12:48:01.828027 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9897 12:48:01.831519 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9898 12:48:01.837943 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9899 12:48:01.841299 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9900 12:48:01.848224 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9901 12:48:01.851309 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9902 12:48:01.854465 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9903 12:48:01.861433 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9904 12:48:01.864473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9905 12:48:01.868334 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9906 12:48:01.874529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9907 12:48:01.878332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9908 12:48:01.884638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9909 12:48:01.887863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9910 12:48:01.894799 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9911 12:48:01.898180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9912 12:48:01.904573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9913 12:48:01.907795 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9914 12:48:01.914820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9915 12:48:01.917738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9916 12:48:01.924774 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9917 12:48:01.928145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9918 12:48:01.934631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9919 12:48:01.937915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9920 12:48:01.944567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9921 12:48:01.948099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9922 12:48:01.951584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9923 12:48:01.958405 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9924 12:48:01.961665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9925 12:48:01.968022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9926 12:48:01.971773 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9927 12:48:01.978088 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9928 12:48:01.981881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9929 12:48:01.988160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9930 12:48:01.991292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9931 12:48:01.998362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9932 12:48:02.001420 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9933 12:48:02.008340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9934 12:48:02.011301 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9935 12:48:02.018100 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9936 12:48:02.021828 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9937 12:48:02.025003 INFO: [APUAPC] vio 0
9938 12:48:02.028128 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9939 12:48:02.034870 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9940 12:48:02.038521 INFO: [APUAPC] D0_APC_0: 0x400510
9941 12:48:02.041527 INFO: [APUAPC] D0_APC_1: 0x0
9942 12:48:02.041638 INFO: [APUAPC] D0_APC_2: 0x1540
9943 12:48:02.044596 INFO: [APUAPC] D0_APC_3: 0x0
9944 12:48:02.048264 INFO: [APUAPC] D1_APC_0: 0xffffffff
9945 12:48:02.051516 INFO: [APUAPC] D1_APC_1: 0xffffffff
9946 12:48:02.055105 INFO: [APUAPC] D1_APC_2: 0x3fffff
9947 12:48:02.058485 INFO: [APUAPC] D1_APC_3: 0x0
9948 12:48:02.061475 INFO: [APUAPC] D2_APC_0: 0xffffffff
9949 12:48:02.065070 INFO: [APUAPC] D2_APC_1: 0xffffffff
9950 12:48:02.068264 INFO: [APUAPC] D2_APC_2: 0x3fffff
9951 12:48:02.071987 INFO: [APUAPC] D2_APC_3: 0x0
9952 12:48:02.075144 INFO: [APUAPC] D3_APC_0: 0xffffffff
9953 12:48:02.078185 INFO: [APUAPC] D3_APC_1: 0xffffffff
9954 12:48:02.081990 INFO: [APUAPC] D3_APC_2: 0x3fffff
9955 12:48:02.085179 INFO: [APUAPC] D3_APC_3: 0x0
9956 12:48:02.088425 INFO: [APUAPC] D4_APC_0: 0xffffffff
9957 12:48:02.091631 INFO: [APUAPC] D4_APC_1: 0xffffffff
9958 12:48:02.095394 INFO: [APUAPC] D4_APC_2: 0x3fffff
9959 12:48:02.098620 INFO: [APUAPC] D4_APC_3: 0x0
9960 12:48:02.101818 INFO: [APUAPC] D5_APC_0: 0xffffffff
9961 12:48:02.105725 INFO: [APUAPC] D5_APC_1: 0xffffffff
9962 12:48:02.108818 INFO: [APUAPC] D5_APC_2: 0x3fffff
9963 12:48:02.112037 INFO: [APUAPC] D5_APC_3: 0x0
9964 12:48:02.115492 INFO: [APUAPC] D6_APC_0: 0xffffffff
9965 12:48:02.119020 INFO: [APUAPC] D6_APC_1: 0xffffffff
9966 12:48:02.122537 INFO: [APUAPC] D6_APC_2: 0x3fffff
9967 12:48:02.125632 INFO: [APUAPC] D6_APC_3: 0x0
9968 12:48:02.128828 INFO: [APUAPC] D7_APC_0: 0xffffffff
9969 12:48:02.132278 INFO: [APUAPC] D7_APC_1: 0xffffffff
9970 12:48:02.135501 INFO: [APUAPC] D7_APC_2: 0x3fffff
9971 12:48:02.135912 INFO: [APUAPC] D7_APC_3: 0x0
9972 12:48:02.141952 INFO: [APUAPC] D8_APC_0: 0xffffffff
9973 12:48:02.145386 INFO: [APUAPC] D8_APC_1: 0xffffffff
9974 12:48:02.148839 INFO: [APUAPC] D8_APC_2: 0x3fffff
9975 12:48:02.149205 INFO: [APUAPC] D8_APC_3: 0x0
9976 12:48:02.152303 INFO: [APUAPC] D9_APC_0: 0xffffffff
9977 12:48:02.155270 INFO: [APUAPC] D9_APC_1: 0xffffffff
9978 12:48:02.158820 INFO: [APUAPC] D9_APC_2: 0x3fffff
9979 12:48:02.162341 INFO: [APUAPC] D9_APC_3: 0x0
9980 12:48:02.165299 INFO: [APUAPC] D10_APC_0: 0xffffffff
9981 12:48:02.168762 INFO: [APUAPC] D10_APC_1: 0xffffffff
9982 12:48:02.171904 INFO: [APUAPC] D10_APC_2: 0x3fffff
9983 12:48:02.175755 INFO: [APUAPC] D10_APC_3: 0x0
9984 12:48:02.179056 INFO: [APUAPC] D11_APC_0: 0xffffffff
9985 12:48:02.182142 INFO: [APUAPC] D11_APC_1: 0xffffffff
9986 12:48:02.185773 INFO: [APUAPC] D11_APC_2: 0x3fffff
9987 12:48:02.188973 INFO: [APUAPC] D11_APC_3: 0x0
9988 12:48:02.192303 INFO: [APUAPC] D12_APC_0: 0xffffffff
9989 12:48:02.195391 INFO: [APUAPC] D12_APC_1: 0xffffffff
9990 12:48:02.199278 INFO: [APUAPC] D12_APC_2: 0x3fffff
9991 12:48:02.202528 INFO: [APUAPC] D12_APC_3: 0x0
9992 12:48:02.205713 INFO: [APUAPC] D13_APC_0: 0xffffffff
9993 12:48:02.208953 INFO: [APUAPC] D13_APC_1: 0xffffffff
9994 12:48:02.212108 INFO: [APUAPC] D13_APC_2: 0x3fffff
9995 12:48:02.216141 INFO: [APUAPC] D13_APC_3: 0x0
9996 12:48:02.219197 INFO: [APUAPC] D14_APC_0: 0xffffffff
9997 12:48:02.222370 INFO: [APUAPC] D14_APC_1: 0xffffffff
9998 12:48:02.226115 INFO: [APUAPC] D14_APC_2: 0x3fffff
9999 12:48:02.229198 INFO: [APUAPC] D14_APC_3: 0x0
10000 12:48:02.232376 INFO: [APUAPC] D15_APC_0: 0xffffffff
10001 12:48:02.235844 INFO: [APUAPC] D15_APC_1: 0xffffffff
10002 12:48:02.239435 INFO: [APUAPC] D15_APC_2: 0x3fffff
10003 12:48:02.242268 INFO: [APUAPC] D15_APC_3: 0x0
10004 12:48:02.245680 INFO: [APUAPC] APC_CON: 0x4
10005 12:48:02.248967 INFO: [NOCDAPC] D0_APC_0: 0x0
10006 12:48:02.252686 INFO: [NOCDAPC] D0_APC_1: 0x0
10007 12:48:02.256072 INFO: [NOCDAPC] D1_APC_0: 0x0
10008 12:48:02.259273 INFO: [NOCDAPC] D1_APC_1: 0xfff
10009 12:48:02.259362 INFO: [NOCDAPC] D2_APC_0: 0x0
10010 12:48:02.262636 INFO: [NOCDAPC] D2_APC_1: 0xfff
10011 12:48:02.265863 INFO: [NOCDAPC] D3_APC_0: 0x0
10012 12:48:02.269229 INFO: [NOCDAPC] D3_APC_1: 0xfff
10013 12:48:02.272280 INFO: [NOCDAPC] D4_APC_0: 0x0
10014 12:48:02.276181 INFO: [NOCDAPC] D4_APC_1: 0xfff
10015 12:48:02.279061 INFO: [NOCDAPC] D5_APC_0: 0x0
10016 12:48:02.282788 INFO: [NOCDAPC] D5_APC_1: 0xfff
10017 12:48:02.285960 INFO: [NOCDAPC] D6_APC_0: 0x0
10018 12:48:02.289145 INFO: [NOCDAPC] D6_APC_1: 0xfff
10019 12:48:02.289242 INFO: [NOCDAPC] D7_APC_0: 0x0
10020 12:48:02.292221 INFO: [NOCDAPC] D7_APC_1: 0xfff
10021 12:48:02.295972 INFO: [NOCDAPC] D8_APC_0: 0x0
10022 12:48:02.299136 INFO: [NOCDAPC] D8_APC_1: 0xfff
10023 12:48:02.302866 INFO: [NOCDAPC] D9_APC_0: 0x0
10024 12:48:02.305982 INFO: [NOCDAPC] D9_APC_1: 0xfff
10025 12:48:02.309226 INFO: [NOCDAPC] D10_APC_0: 0x0
10026 12:48:02.312812 INFO: [NOCDAPC] D10_APC_1: 0xfff
10027 12:48:02.316053 INFO: [NOCDAPC] D11_APC_0: 0x0
10028 12:48:02.319050 INFO: [NOCDAPC] D11_APC_1: 0xfff
10029 12:48:02.322931 INFO: [NOCDAPC] D12_APC_0: 0x0
10030 12:48:02.326022 INFO: [NOCDAPC] D12_APC_1: 0xfff
10031 12:48:02.329084 INFO: [NOCDAPC] D13_APC_0: 0x0
10032 12:48:02.329201 INFO: [NOCDAPC] D13_APC_1: 0xfff
10033 12:48:02.332879 INFO: [NOCDAPC] D14_APC_0: 0x0
10034 12:48:02.335985 INFO: [NOCDAPC] D14_APC_1: 0xfff
10035 12:48:02.339097 INFO: [NOCDAPC] D15_APC_0: 0x0
10036 12:48:02.342875 INFO: [NOCDAPC] D15_APC_1: 0xfff
10037 12:48:02.346044 INFO: [NOCDAPC] APC_CON: 0x4
10038 12:48:02.349572 INFO: [APUAPC] set_apusys_apc done
10039 12:48:02.352629 INFO: [DEVAPC] devapc_init done
10040 12:48:02.356321 INFO: GICv3 without legacy support detected.
10041 12:48:02.359311 INFO: ARM GICv3 driver initialized in EL3
10042 12:48:02.365718 INFO: Maximum SPI INTID supported: 639
10043 12:48:02.369727 INFO: BL31: Initializing runtime services
10044 12:48:02.372839 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10045 12:48:02.376028 INFO: SPM: enable CPC mode
10046 12:48:02.382767 INFO: mcdi ready for mcusys-off-idle and system suspend
10047 12:48:02.386420 INFO: BL31: Preparing for EL3 exit to normal world
10048 12:48:02.389434 INFO: Entry point address = 0x80000000
10049 12:48:02.392547 INFO: SPSR = 0x8
10050 12:48:02.398304
10051 12:48:02.398592
10052 12:48:02.398835
10053 12:48:02.401706 Starting depthcharge on Spherion...
10054 12:48:02.401985
10055 12:48:02.402225 Wipe memory regions:
10056 12:48:02.402493
10057 12:48:02.404176 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10058 12:48:02.404535 start: 2.2.4 bootloader-commands (timeout 00:04:22) [common]
10059 12:48:02.404907 Setting prompt string to ['asurada:']
10060 12:48:02.405212 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:22)
10061 12:48:02.405769 [0x00000040000000, 0x00000054600000)
10062 12:48:02.526999
10063 12:48:02.527240 [0x00000054660000, 0x00000080000000)
10064 12:48:02.788144
10065 12:48:02.788421 [0x000000821a7280, 0x000000ffe64000)
10066 12:48:03.533232
10067 12:48:03.533715 [0x00000100000000, 0x00000240000000)
10068 12:48:05.423419
10069 12:48:05.426440 Initializing XHCI USB controller at 0x11200000.
10070 12:48:06.464150
10071 12:48:06.467821 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10072 12:48:06.467974
10073 12:48:06.468070
10074 12:48:06.468169
10075 12:48:06.468505 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10077 12:48:06.569004 asurada: tftpboot 192.168.201.1 11118892/tftp-deploy-rgu9yvwm/kernel/image.itb 11118892/tftp-deploy-rgu9yvwm/kernel/cmdline
10078 12:48:06.569339 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10079 12:48:06.569562 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:18)
10080 12:48:06.573860 tftpboot 192.168.201.1 11118892/tftp-deploy-rgu9yvwm/kernel/image.ittp-deploy-rgu9yvwm/kernel/cmdline
10081 12:48:06.574152
10082 12:48:06.574404 Waiting for link
10083 12:48:06.734158
10084 12:48:06.734360 R8152: Initializing
10085 12:48:06.734497
10086 12:48:06.737982 Version 6 (ocp_data = 5c30)
10087 12:48:06.738164
10088 12:48:06.741132 R8152: Done initializing
10089 12:48:06.741273
10090 12:48:06.741378 Adding net device
10091 12:48:08.705820
10092 12:48:08.705979 done.
10093 12:48:08.706091
10094 12:48:08.706193 MAC: 00:24:32:30:78:52
10095 12:48:08.706343
10096 12:48:08.708972 Sending DHCP discover... done.
10097 12:48:08.709069
10098 12:48:12.290672 Waiting for reply... done.
10099 12:48:12.290866
10100 12:48:12.290987 Sending DHCP request... done.
10101 12:48:12.293550
10102 12:48:13.254445 Waiting for reply... done.
10103 12:48:13.254668
10104 12:48:13.254787 My ip is 192.168.201.14
10105 12:48:13.254890
10106 12:48:13.257977 The DHCP server ip is 192.168.201.1
10107 12:48:13.258099
10108 12:48:13.264901 TFTP server IP predefined by user: 192.168.201.1
10109 12:48:13.265053
10110 12:48:13.271266 Bootfile predefined by user: 11118892/tftp-deploy-rgu9yvwm/kernel/image.itb
10111 12:48:13.271384
10112 12:48:13.271491 Sending tftp read request... done.
10113 12:48:13.271592
10114 12:48:13.278162 Waiting for the transfer...
10115 12:48:13.278293
10116 12:48:13.834336 00000000 ################################################################
10117 12:48:13.834486
10118 12:48:14.370801 00080000 ################################################################
10119 12:48:14.371022
10120 12:48:14.930218 00100000 ################################################################
10121 12:48:14.930450
10122 12:48:15.465017 00180000 ################################################################
10123 12:48:15.465182
10124 12:48:16.002329 00200000 ################################################################
10125 12:48:16.002538
10126 12:48:16.549763 00280000 ################################################################
10127 12:48:16.549939
10128 12:48:17.090944 00300000 ################################################################
10129 12:48:17.091197
10130 12:48:17.634727 00380000 ################################################################
10131 12:48:17.634903
10132 12:48:18.169082 00400000 ################################################################
10133 12:48:18.169325
10134 12:48:18.709694 00480000 ################################################################
10135 12:48:18.709855
10136 12:48:19.279565 00500000 ################################################################
10137 12:48:19.279752
10138 12:48:19.853786 00580000 ################################################################
10139 12:48:19.853980
10140 12:48:20.402357 00600000 ################################################################
10141 12:48:20.402505
10142 12:48:20.954553 00680000 ################################################################
10143 12:48:20.954693
10144 12:48:21.545769 00700000 ################################################################
10145 12:48:21.545952
10146 12:48:22.100828 00780000 ################################################################
10147 12:48:22.100974
10148 12:48:22.681445 00800000 ################################################################
10149 12:48:22.681819
10150 12:48:23.264375 00880000 ################################################################
10151 12:48:23.264549
10152 12:48:23.819928 00900000 ################################################################
10153 12:48:23.820068
10154 12:48:24.372781 00980000 ################################################################
10155 12:48:24.372952
10156 12:48:24.919448 00a00000 ################################################################
10157 12:48:24.919595
10158 12:48:25.583364 00a80000 ################################################################
10159 12:48:25.583741
10160 12:48:26.274666 00b00000 ################################################################
10161 12:48:26.274835
10162 12:48:26.869866 00b80000 ################################################################
10163 12:48:26.870154
10164 12:48:27.452365 00c00000 ################################################################
10165 12:48:27.452574
10166 12:48:28.079813 00c80000 ################################################################
10167 12:48:28.080541
10168 12:48:28.728636 00d00000 ################################################################
10169 12:48:28.729487
10170 12:48:29.367366 00d80000 ################################################################
10171 12:48:29.367583
10172 12:48:30.221346 00e00000 ################################################################
10173 12:48:30.221521
10174 12:48:30.638614 00e80000 ################################################################
10175 12:48:30.639126
10176 12:48:31.257300 00f00000 ################################################################
10177 12:48:31.257809
10178 12:48:31.846709 00f80000 ################################################################
10179 12:48:31.846857
10180 12:48:32.392760 01000000 ################################################################
10181 12:48:32.393432
10182 12:48:32.961260 01080000 ################################################################
10183 12:48:32.961418
10184 12:48:33.573913 01100000 ################################################################
10185 12:48:33.574327
10186 12:48:34.194919 01180000 ################################################################
10187 12:48:34.195071
10188 12:48:34.826065 01200000 ################################################################
10189 12:48:34.826673
10190 12:48:35.445078 01280000 ################################################################
10191 12:48:35.445581
10192 12:48:36.090037 01300000 ################################################################
10193 12:48:36.090261
10194 12:48:36.723328 01380000 ################################################################
10195 12:48:36.723746
10196 12:48:37.357489 01400000 ################################################################
10197 12:48:37.358002
10198 12:48:37.975973 01480000 ################################################################
10199 12:48:37.976357
10200 12:48:38.593777 01500000 ################################################################
10201 12:48:38.594606
10202 12:48:39.212584 01580000 ################################################################
10203 12:48:39.212899
10204 12:48:39.831814 01600000 ################################################################
10205 12:48:39.832767
10206 12:48:40.492480 01680000 ################################################################
10207 12:48:40.493080
10208 12:48:41.165467 01700000 ################################################################
10209 12:48:41.166009
10210 12:48:41.833152 01780000 ################################################################
10211 12:48:41.833540
10212 12:48:42.483585 01800000 ################################################################
10213 12:48:42.484099
10214 12:48:43.142737 01880000 ################################################################
10215 12:48:43.143483
10216 12:48:43.774250 01900000 ################################################################
10217 12:48:43.774482
10218 12:48:44.404141 01980000 ################################################################
10219 12:48:44.404549
10220 12:48:45.016634 01a00000 ################################################################
10221 12:48:45.016833
10222 12:48:45.629420 01a80000 ################################################################
10223 12:48:45.630299
10224 12:48:46.236054 01b00000 ################################################################
10225 12:48:46.236590
10226 12:48:46.888808 01b80000 ################################################################
10227 12:48:46.888956
10228 12:48:47.557533 01c00000 ################################################################
10229 12:48:47.558058
10230 12:48:48.183628 01c80000 ################################################################
10231 12:48:48.183924
10232 12:48:48.805470 01d00000 ################################################################
10233 12:48:48.805695
10234 12:48:49.442099 01d80000 ################################################################
10235 12:48:49.442567
10236 12:48:50.080331 01e00000 ################################################################
10237 12:48:50.080695
10238 12:48:50.726755 01e80000 ################################################################
10239 12:48:50.727025
10240 12:48:51.364989 01f00000 ################################################################
10241 12:48:51.365564
10242 12:48:51.989116 01f80000 ################################################################
10243 12:48:51.989618
10244 12:48:52.607918 02000000 ################################################################
10245 12:48:52.608418
10246 12:48:53.191715 02080000 ################################################################
10247 12:48:53.191864
10248 12:48:53.770086 02100000 ################################################################
10249 12:48:53.770235
10250 12:48:54.360306 02180000 ################################################################
10251 12:48:54.360492
10252 12:48:54.902628 02200000 ################################################################
10253 12:48:54.903291
10254 12:48:55.474710 02280000 ################################################################
10255 12:48:55.475246
10256 12:48:56.062161 02300000 ################################################################
10257 12:48:56.062333
10258 12:48:56.674741 02380000 ################################################################
10259 12:48:56.675338
10260 12:48:57.255008 02400000 ################################################################
10261 12:48:57.255520
10262 12:48:57.876781 02480000 ################################################################
10263 12:48:57.877171
10264 12:48:58.501544 02500000 ################################################################
10265 12:48:58.502069
10266 12:48:59.103320 02580000 ################################################################
10267 12:48:59.103467
10268 12:48:59.673166 02600000 ################################################################
10269 12:48:59.673320
10270 12:49:00.237134 02680000 ################################################################
10271 12:49:00.237278
10272 12:49:00.803773 02700000 ################################################################
10273 12:49:00.803947
10274 12:49:01.374404 02780000 ################################################################
10275 12:49:01.374564
10276 12:49:01.957267 02800000 ################################################################
10277 12:49:01.957430
10278 12:49:02.526067 02880000 ################################################################
10279 12:49:02.526625
10280 12:49:03.118885 02900000 ################################################################
10281 12:49:03.119157
10282 12:49:03.694652 02980000 ################################################################
10283 12:49:03.694835
10284 12:49:04.247463 02a00000 ################################################################
10285 12:49:04.247724
10286 12:49:04.803258 02a80000 ################################################################
10287 12:49:04.803593
10288 12:49:05.387479 02b00000 ################################################################
10289 12:49:05.387658
10290 12:49:06.004714 02b80000 ################################################################
10291 12:49:06.005269
10292 12:49:06.643881 02c00000 ################################################################
10293 12:49:06.644216
10294 12:49:07.265120 02c80000 ################################################################
10295 12:49:07.265588
10296 12:49:07.899959 02d00000 ################################################################
10297 12:49:07.900119
10298 12:49:08.498540 02d80000 ################################################################
10299 12:49:08.499014
10300 12:49:09.098742 02e00000 ################################################################
10301 12:49:09.098995
10302 12:49:09.725593 02e80000 ################################################################
10303 12:49:09.726273
10304 12:49:10.314573 02f00000 ################################################################
10305 12:49:10.315393
10306 12:49:10.929823 02f80000 ################################################################
10307 12:49:10.930363
10308 12:49:11.510580 03000000 ################################################################
10309 12:49:11.511379
10310 12:49:12.102862 03080000 ################################################################
10311 12:49:12.103208
10312 12:49:12.704231 03100000 ################################################################
10313 12:49:12.704418
10314 12:49:13.319581 03180000 ################################################################
10315 12:49:13.319760
10316 12:49:13.923195 03200000 ################################################################
10317 12:49:13.923507
10318 12:49:14.479269 03280000 ################################################################
10319 12:49:14.479462
10320 12:49:15.023313 03300000 ################################################################
10321 12:49:15.023475
10322 12:49:15.572410 03380000 ################################################################
10323 12:49:15.572599
10324 12:49:16.125435 03400000 ################################################################
10325 12:49:16.125898
10326 12:49:16.697601 03480000 ################################################################
10327 12:49:16.697739
10328 12:49:17.265428 03500000 ################################################################
10329 12:49:17.265564
10330 12:49:17.825993 03580000 ################################################################
10331 12:49:17.826651
10332 12:49:18.405606 03600000 ################################################################
10333 12:49:18.405850
10334 12:49:19.033606 03680000 ################################################################
10335 12:49:19.034101
10336 12:49:19.663578 03700000 ################################################################
10337 12:49:19.664128
10338 12:49:20.292005 03780000 ################################################################
10339 12:49:20.292166
10340 12:49:20.883365 03800000 ################################################################
10341 12:49:20.883805
10342 12:49:21.520199 03880000 ################################################################
10343 12:49:21.520585
10344 12:49:22.131694 03900000 ################################################################
10345 12:49:22.132047
10346 12:49:22.762690 03980000 ################################################################
10347 12:49:22.763223
10348 12:49:23.349370 03a00000 ################################################################
10349 12:49:23.349669
10350 12:49:23.917183 03a80000 ################################################################
10351 12:49:23.917329
10352 12:49:24.502102 03b00000 ################################################################
10353 12:49:24.502739
10354 12:49:25.060809 03b80000 ################################################################
10355 12:49:25.060960
10356 12:49:25.626372 03c00000 ################################################################
10357 12:49:25.626535
10358 12:49:26.221899 03c80000 ################################################################
10359 12:49:26.222211
10360 12:49:26.821334 03d00000 ################################################################
10361 12:49:26.821480
10362 12:49:27.378010 03d80000 ################################################################
10363 12:49:27.378184
10364 12:49:27.979464 03e00000 ################################################################
10365 12:49:27.979605
10366 12:49:28.520745 03e80000 ################################################################
10367 12:49:28.520986
10368 12:49:29.081026 03f00000 ################################################################
10369 12:49:29.081159
10370 12:49:29.618612 03f80000 ################################################################
10371 12:49:29.618761
10372 12:49:30.155027 04000000 ################################################################
10373 12:49:30.155190
10374 12:49:30.688359 04080000 ################################################################
10375 12:49:30.688528
10376 12:49:31.212379 04100000 ################################################################
10377 12:49:31.212522
10378 12:49:31.747836 04180000 ################################################################
10379 12:49:31.748015
10380 12:49:32.293507 04200000 ################################################################
10381 12:49:32.293674
10382 12:49:32.832965 04280000 ################################################################
10383 12:49:32.833102
10384 12:49:33.357389 04300000 ################################################################
10385 12:49:33.357522
10386 12:49:33.899697 04380000 ################################################################
10387 12:49:33.899835
10388 12:49:34.443130 04400000 ################################################################
10389 12:49:34.443270
10390 12:49:34.979850 04480000 ################################################################
10391 12:49:34.979986
10392 12:49:35.530141 04500000 ################################################################
10393 12:49:35.530323
10394 12:49:36.062628 04580000 ################################################################
10395 12:49:36.062767
10396 12:49:36.585427 04600000 ################################################################
10397 12:49:36.585573
10398 12:49:37.111216 04680000 ################################################################
10399 12:49:37.111381
10400 12:49:37.651279 04700000 ################################################################
10401 12:49:37.651447
10402 12:49:38.177503 04780000 ################################################################
10403 12:49:38.177643
10404 12:49:38.699981 04800000 ################################################################
10405 12:49:38.700201
10406 12:49:39.229919 04880000 ################################################################
10407 12:49:39.230067
10408 12:49:39.746403 04900000 ################################################################
10409 12:49:39.746566
10410 12:49:40.261555 04980000 ################################################################
10411 12:49:40.261784
10412 12:49:40.814082 04a00000 ################################################################
10413 12:49:40.814317
10414 12:49:41.305980 04a80000 ################################################################
10415 12:49:41.306151
10416 12:49:41.838340 04b00000 ################################################################
10417 12:49:41.838501
10418 12:49:42.368564 04b80000 ################################################################
10419 12:49:42.368733
10420 12:49:42.914178 04c00000 ################################################################
10421 12:49:42.914317
10422 12:49:43.448925 04c80000 ################################################################
10423 12:49:43.449067
10424 12:49:43.979627 04d00000 ################################################################
10425 12:49:43.979766
10426 12:49:44.508250 04d80000 ################################################################
10427 12:49:44.508417
10428 12:49:45.036061 04e00000 ################################################################
10429 12:49:45.036195
10430 12:49:45.580725 04e80000 ################################################################
10431 12:49:45.580864
10432 12:49:46.105136 04f00000 ################################################################
10433 12:49:46.105313
10434 12:49:46.643307 04f80000 ################################################################
10435 12:49:46.643471
10436 12:49:47.203823 05000000 ################################################################
10437 12:49:47.203989
10438 12:49:47.766429 05080000 ################################################################
10439 12:49:47.766587
10440 12:49:48.310632 05100000 ################################################################
10441 12:49:48.310787
10442 12:49:48.839867 05180000 ################################################################
10443 12:49:48.840023
10444 12:49:49.385271 05200000 ################################################################
10445 12:49:49.385426
10446 12:49:49.940133 05280000 ################################################################
10447 12:49:49.940302
10448 12:49:50.470818 05300000 ################################################################
10449 12:49:50.470986
10450 12:49:50.998373 05380000 ################################################################
10451 12:49:50.998519
10452 12:49:51.533710 05400000 ################################################################
10453 12:49:51.533848
10454 12:49:52.059943 05480000 ################################################################
10455 12:49:52.060090
10456 12:49:52.598171 05500000 ################################################################
10457 12:49:52.598313
10458 12:49:53.137843 05580000 ################################################################
10459 12:49:53.138004
10460 12:49:53.681506 05600000 ################################################################
10461 12:49:53.681642
10462 12:49:54.227608 05680000 ################################################################
10463 12:49:54.227747
10464 12:49:54.774710 05700000 ################################################################
10465 12:49:54.774902
10466 12:49:55.313488 05780000 ################################################################
10467 12:49:55.313722
10468 12:49:55.954022 05800000 ################################################################
10469 12:49:55.954185
10470 12:49:56.573277 05880000 ################################################################
10471 12:49:56.573607
10472 12:49:57.219965 05900000 ################################################################
10473 12:49:57.220140
10474 12:49:57.892464 05980000 ################################################################
10475 12:49:57.893167
10476 12:49:58.582845 05a00000 ################################################################
10477 12:49:58.583344
10478 12:49:59.214429 05a80000 ################################################################
10479 12:49:59.214594
10480 12:49:59.848819 05b00000 ################################################################
10481 12:49:59.849325
10482 12:50:00.504935 05b80000 ################################################################
10483 12:50:00.505586
10484 12:50:01.169236 05c00000 ################################################################
10485 12:50:01.169857
10486 12:50:01.824196 05c80000 ################################################################
10487 12:50:01.824341
10488 12:50:02.397963 05d00000 ################################################################
10489 12:50:02.398124
10490 12:50:03.061585 05d80000 ################################################################
10491 12:50:03.062113
10492 12:50:05.844283 05e00000 ################################################################
10493 12:50:05.844833
10494 12:50:05.845191 05e80000 ################################################################
10495 12:50:05.845519
10496 12:50:05.845826 05f00000 ################################################################
10497 12:50:05.846130
10498 12:50:05.846421 05f80000 ################################################################
10499 12:50:05.846716
10500 12:50:06.287464 06000000 ################################################################
10501 12:50:06.287692
10502 12:50:06.834859 06080000 ################################################################
10503 12:50:06.835006
10504 12:50:07.374602 06100000 ################################################################
10505 12:50:07.375164
10506 12:50:07.923797 06180000 ################################################################
10507 12:50:07.923962
10508 12:50:08.464997 06200000 ################################################################
10509 12:50:08.465152
10510 12:50:09.000194 06280000 ################################################################
10511 12:50:09.000346
10512 12:50:09.530890 06300000 ################################################################
10513 12:50:09.531023
10514 12:50:10.066016 06380000 ################################################################
10515 12:50:10.066149
10516 12:50:10.613077 06400000 ################################################################
10517 12:50:10.613214
10518 12:50:11.160106 06480000 ################################################################
10519 12:50:11.160619
10520 12:50:11.854923 06500000 ################################################################
10521 12:50:11.855445
10522 12:50:12.518325 06580000 ################################################################
10523 12:50:12.518851
10524 12:50:13.171562 06600000 ################################################################
10525 12:50:13.172049
10526 12:50:13.809256 06680000 ################################################################
10527 12:50:13.809766
10528 12:50:14.440306 06700000 ################################################################
10529 12:50:14.440507
10530 12:50:14.992104 06780000 ############################################################### done.
10531 12:50:14.992244
10532 12:50:14.994947 The bootfile was 109043118 bytes long.
10533 12:50:14.995073
10534 12:50:14.998358 Sending tftp read request... done.
10535 12:50:14.998462
10536 12:50:14.998576 Waiting for the transfer...
10537 12:50:14.998695
10538 12:50:15.002239 00000000 # done.
10539 12:50:15.002369
10540 12:50:15.008537 Command line loaded dynamically from TFTP file: 11118892/tftp-deploy-rgu9yvwm/kernel/cmdline
10541 12:50:15.008689
10542 12:50:15.022109 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10543 12:50:15.022265
10544 12:50:15.025441 Loading FIT.
10545 12:50:15.025612
10546 12:50:15.028860 Image ramdisk-1 has 98185983 bytes.
10547 12:50:15.029060
10548 12:50:15.029220 Image fdt-1 has 46924 bytes.
10549 12:50:15.029369
10550 12:50:15.032115 Image kernel-1 has 10808178 bytes.
10551 12:50:15.032313
10552 12:50:15.042232 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10553 12:50:15.042531
10554 12:50:15.058929 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10555 12:50:15.059338
10556 12:50:15.066416 Choosing best match conf-1 for compat google,spherion-rev2.
10557 12:50:15.069476
10558 12:50:15.074344 Connected to device vid:did:rid of 1ae0:0028:00
10559 12:50:15.082199
10560 12:50:15.085829 tpm_get_response: command 0x17b, return code 0x0
10561 12:50:15.086383
10562 12:50:15.089109 ec_init: CrosEC protocol v3 supported (256, 248)
10563 12:50:15.092351
10564 12:50:15.095804 tpm_cleanup: add release locality here.
10565 12:50:15.096305
10566 12:50:15.096842 Shutting down all USB controllers.
10567 12:50:15.099717
10568 12:50:15.100222 Removing current net device
10569 12:50:15.100745
10570 12:50:15.106229 Exiting depthcharge with code 4 at timestamp: 162126834
10571 12:50:15.106719
10572 12:50:15.109694 LZMA decompressing kernel-1 to 0x821a6718
10573 12:50:15.110099
10574 12:50:15.112902 LZMA decompressing kernel-1 to 0x40000000
10575 12:50:16.464271
10576 12:50:16.464427 jumping to kernel
10577 12:50:16.464968 end: 2.2.4 bootloader-commands (duration 00:02:14) [common]
10578 12:50:16.465091 start: 2.2.5 auto-login-action (timeout 00:02:08) [common]
10579 12:50:16.465186 Setting prompt string to ['Linux version [0-9]']
10580 12:50:16.465272 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10581 12:50:16.465359 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10582 12:50:16.547477
10583 12:50:16.550367 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10584 12:50:16.554497 start: 2.2.5.1 login-action (timeout 00:02:08) [common]
10585 12:50:16.554833 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10586 12:50:16.555184 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10587 12:50:16.555519 Using line separator: #'\n'#
10588 12:50:16.555787 No login prompt set.
10589 12:50:16.556044 Parsing kernel messages
10590 12:50:16.556318 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10591 12:50:16.556819 [login-action] Waiting for messages, (timeout 00:02:08)
10592 12:50:16.573894 [ 0.000000] Linux version 6.1.38-cip1 (KernelCI@build-j6766-arm64-gcc-10-defconfig-arm64-chromebook-9w8v6) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Jul 20 12:35:57 UTC 2023
10593 12:50:16.577255 [ 0.000000] random: crng init done
10594 12:50:16.580560 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10595 12:50:16.583870 [ 0.000000] efi: UEFI not found.
10596 12:50:16.594087 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10597 12:50:16.600437 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10598 12:50:16.610570 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10599 12:50:16.620858 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10600 12:50:16.627586 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10601 12:50:16.630866 [ 0.000000] printk: bootconsole [mtk8250] enabled
10602 12:50:16.638685 [ 0.000000] NUMA: No NUMA configuration found
10603 12:50:16.645661 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10604 12:50:16.651989 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10605 12:50:16.652078 [ 0.000000] Zone ranges:
10606 12:50:16.658636 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10607 12:50:16.662364 [ 0.000000] DMA32 empty
10608 12:50:16.668455 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10609 12:50:16.671999 [ 0.000000] Movable zone start for each node
10610 12:50:16.675390 [ 0.000000] Early memory node ranges
10611 12:50:16.682068 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10612 12:50:16.688789 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10613 12:50:16.695602 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10614 12:50:16.702411 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10615 12:50:16.705337 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10616 12:50:16.715746 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10617 12:50:16.770931 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10618 12:50:16.777462 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10619 12:50:16.783921 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10620 12:50:16.787387 [ 0.000000] psci: probing for conduit method from DT.
10621 12:50:16.794097 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10622 12:50:16.797727 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10623 12:50:16.803778 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10624 12:50:16.807129 [ 0.000000] psci: SMC Calling Convention v1.2
10625 12:50:16.814145 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10626 12:50:16.817796 [ 0.000000] Detected VIPT I-cache on CPU0
10627 12:50:16.824169 [ 0.000000] CPU features: detected: GIC system register CPU interface
10628 12:50:16.830729 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10629 12:50:16.837439 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10630 12:50:16.844496 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10631 12:50:16.851293 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10632 12:50:16.857379 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10633 12:50:16.864151 [ 0.000000] alternatives: applying boot alternatives
10634 12:50:16.867490 [ 0.000000] Fallback order for Node 0: 0
10635 12:50:16.874175 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10636 12:50:16.877368 [ 0.000000] Policy zone: Normal
10637 12:50:16.894240 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10638 12:50:16.904555 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10639 12:50:16.915321 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10640 12:50:16.925021 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10641 12:50:16.931783 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10642 12:50:16.935103 <6>[ 0.000000] software IO TLB: area num 8.
10643 12:50:16.991715 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10644 12:50:17.140148 <6>[ 0.000000] Memory: 7874316K/8385536K available (17984K kernel code, 4098K rwdata, 16796K rodata, 8384K init, 615K bss, 478452K reserved, 32768K cma-reserved)
10645 12:50:17.146791 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10646 12:50:17.153391 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10647 12:50:17.156850 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10648 12:50:17.163775 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10649 12:50:17.170633 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10650 12:50:17.173816 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10651 12:50:17.184050 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10652 12:50:17.190836 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10653 12:50:17.194226 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10654 12:50:17.201294 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10655 12:50:17.205033 <6>[ 0.000000] GICv3: 608 SPIs implemented
10656 12:50:17.211729 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10657 12:50:17.215244 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10658 12:50:17.218491 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10659 12:50:17.227825 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10660 12:50:17.237985 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10661 12:50:17.251219 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10662 12:50:17.257759 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10663 12:50:17.266717 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10664 12:50:17.280346 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10665 12:50:17.287070 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10666 12:50:17.293982 <6>[ 0.009180] Console: colour dummy device 80x25
10667 12:50:17.304328 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10668 12:50:17.307435 <6>[ 0.024348] pid_max: default: 32768 minimum: 301
10669 12:50:17.314233 <6>[ 0.029221] LSM: Security Framework initializing
10670 12:50:17.320274 <6>[ 0.034187] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10671 12:50:17.330558 <6>[ 0.042049] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10672 12:50:17.337165 <6>[ 0.051480] cblist_init_generic: Setting adjustable number of callback queues.
10673 12:50:17.343957 <6>[ 0.058934] cblist_init_generic: Setting shift to 3 and lim to 1.
10674 12:50:17.350625 <6>[ 0.065313] cblist_init_generic: Setting shift to 3 and lim to 1.
10675 12:50:17.357523 <6>[ 0.071718] rcu: Hierarchical SRCU implementation.
10676 12:50:17.360449 <6>[ 0.076731] rcu: Max phase no-delay instances is 1000.
10677 12:50:17.367737 <6>[ 0.083762] EFI services will not be available.
10678 12:50:17.371654 <6>[ 0.088765] smp: Bringing up secondary CPUs ...
10679 12:50:17.380658 <6>[ 0.093821] Detected VIPT I-cache on CPU1
10680 12:50:17.387129 <6>[ 0.093890] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10681 12:50:17.393943 <6>[ 0.093920] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10682 12:50:17.397356 <6>[ 0.094258] Detected VIPT I-cache on CPU2
10683 12:50:17.404071 <6>[ 0.094309] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10684 12:50:17.410199 <6>[ 0.094326] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10685 12:50:17.417418 <6>[ 0.094585] Detected VIPT I-cache on CPU3
10686 12:50:17.423438 <6>[ 0.094632] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10687 12:50:17.430721 <6>[ 0.094646] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10688 12:50:17.434205 <6>[ 0.094953] CPU features: detected: Spectre-v4
10689 12:50:17.440489 <6>[ 0.094959] CPU features: detected: Spectre-BHB
10690 12:50:17.443882 <6>[ 0.094965] Detected PIPT I-cache on CPU4
10691 12:50:17.450461 <6>[ 0.095023] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10692 12:50:17.457062 <6>[ 0.095040] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10693 12:50:17.463575 <6>[ 0.095334] Detected PIPT I-cache on CPU5
10694 12:50:17.470070 <6>[ 0.095399] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10695 12:50:17.476932 <6>[ 0.095415] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10696 12:50:17.480422 <6>[ 0.095698] Detected PIPT I-cache on CPU6
10697 12:50:17.487393 <6>[ 0.095766] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10698 12:50:17.493543 <6>[ 0.095782] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10699 12:50:17.496662 <6>[ 0.096081] Detected PIPT I-cache on CPU7
10700 12:50:17.506822 <6>[ 0.096147] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10701 12:50:17.514200 <6>[ 0.096164] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10702 12:50:17.516999 <6>[ 0.096211] smp: Brought up 1 node, 8 CPUs
10703 12:50:17.520312 <6>[ 0.237554] SMP: Total of 8 processors activated.
10704 12:50:17.526676 <6>[ 0.242475] CPU features: detected: 32-bit EL0 Support
10705 12:50:17.536718 <6>[ 0.247837] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10706 12:50:17.543895 <6>[ 0.256637] CPU features: detected: Common not Private translations
10707 12:50:17.547282 <6>[ 0.263112] CPU features: detected: CRC32 instructions
10708 12:50:17.553421 <6>[ 0.268464] CPU features: detected: RCpc load-acquire (LDAPR)
10709 12:50:17.560117 <6>[ 0.274423] CPU features: detected: LSE atomic instructions
10710 12:50:17.566572 <6>[ 0.280239] CPU features: detected: Privileged Access Never
10711 12:50:17.569930 <6>[ 0.286018] CPU features: detected: RAS Extension Support
10712 12:50:17.576644 <6>[ 0.291662] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10713 12:50:17.583187 <6>[ 0.298882] CPU: All CPU(s) started at EL2
10714 12:50:17.586511 <6>[ 0.303199] alternatives: applying system-wide alternatives
10715 12:50:17.598265 <6>[ 0.313876] devtmpfs: initialized
10716 12:50:17.610123 <6>[ 0.322673] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10717 12:50:17.620200 <6>[ 0.332634] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10718 12:50:17.627027 <6>[ 0.340677] pinctrl core: initialized pinctrl subsystem
10719 12:50:17.630471 <6>[ 0.347338] DMI not present or invalid.
10720 12:50:17.636882 <6>[ 0.351739] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10721 12:50:17.646902 <6>[ 0.358612] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10722 12:50:17.653043 <6>[ 0.366193] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10723 12:50:17.663102 <6>[ 0.374409] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10724 12:50:17.666529 <6>[ 0.382652] audit: initializing netlink subsys (disabled)
10725 12:50:17.676350 <5>[ 0.388347] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10726 12:50:17.683211 <6>[ 0.389041] thermal_sys: Registered thermal governor 'step_wise'
10727 12:50:17.689721 <6>[ 0.396316] thermal_sys: Registered thermal governor 'power_allocator'
10728 12:50:17.692924 <6>[ 0.402571] cpuidle: using governor menu
10729 12:50:17.696380 <6>[ 0.413532] NET: Registered PF_QIPCRTR protocol family
10730 12:50:17.706431 <6>[ 0.419012] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10731 12:50:17.709481 <6>[ 0.426115] ASID allocator initialised with 32768 entries
10732 12:50:17.716604 <6>[ 0.432680] Serial: AMBA PL011 UART driver
10733 12:50:17.725097 <4>[ 0.441359] Trying to register duplicate clock ID: 134
10734 12:50:17.779029 <6>[ 0.498660] KASLR enabled
10735 12:50:17.793928 <6>[ 0.506335] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10736 12:50:17.800809 <6>[ 0.513351] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10737 12:50:17.806831 <6>[ 0.519841] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10738 12:50:17.814246 <6>[ 0.526846] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10739 12:50:17.820846 <6>[ 0.533333] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10740 12:50:17.827395 <6>[ 0.540337] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10741 12:50:17.834333 <6>[ 0.546827] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10742 12:50:17.840998 <6>[ 0.553834] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10743 12:50:17.843927 <6>[ 0.561294] ACPI: Interpreter disabled.
10744 12:50:17.852235 <6>[ 0.567707] iommu: Default domain type: Translated
10745 12:50:17.858348 <6>[ 0.572821] iommu: DMA domain TLB invalidation policy: strict mode
10746 12:50:17.861628 <5>[ 0.579480] SCSI subsystem initialized
10747 12:50:17.868265 <6>[ 0.583713] usbcore: registered new interface driver usbfs
10748 12:50:17.874791 <6>[ 0.589442] usbcore: registered new interface driver hub
10749 12:50:17.878180 <6>[ 0.594995] usbcore: registered new device driver usb
10750 12:50:17.885447 <6>[ 0.601093] pps_core: LinuxPPS API ver. 1 registered
10751 12:50:17.895444 <6>[ 0.606288] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10752 12:50:17.898697 <6>[ 0.615629] PTP clock support registered
10753 12:50:17.902070 <6>[ 0.619871] EDAC MC: Ver: 3.0.0
10754 12:50:17.909462 <6>[ 0.625048] FPGA manager framework
10755 12:50:17.916035 <6>[ 0.628724] Advanced Linux Sound Architecture Driver Initialized.
10756 12:50:17.919225 <6>[ 0.635487] vgaarb: loaded
10757 12:50:17.925788 <6>[ 0.638645] clocksource: Switched to clocksource arch_sys_counter
10758 12:50:17.928947 <5>[ 0.645093] VFS: Disk quotas dquot_6.6.0
10759 12:50:17.935619 <6>[ 0.649279] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10760 12:50:17.938871 <6>[ 0.656470] pnp: PnP ACPI: disabled
10761 12:50:17.947298 <6>[ 0.663147] NET: Registered PF_INET protocol family
10762 12:50:17.956865 <6>[ 0.668746] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10763 12:50:17.968300 <6>[ 0.681053] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10764 12:50:17.978491 <6>[ 0.689868] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10765 12:50:17.985088 <6>[ 0.697840] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10766 12:50:17.991778 <6>[ 0.706539] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10767 12:50:18.003448 <6>[ 0.716281] TCP: Hash tables configured (established 65536 bind 65536)
10768 12:50:18.010107 <6>[ 0.723142] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10769 12:50:18.016807 <6>[ 0.730341] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10770 12:50:18.023353 <6>[ 0.738044] NET: Registered PF_UNIX/PF_LOCAL protocol family
10771 12:50:18.030667 <6>[ 0.744211] RPC: Registered named UNIX socket transport module.
10772 12:50:18.033460 <6>[ 0.750368] RPC: Registered udp transport module.
10773 12:50:18.040072 <6>[ 0.755302] RPC: Registered tcp transport module.
10774 12:50:18.046760 <6>[ 0.760234] RPC: Registered tcp NFSv4.1 backchannel transport module.
10775 12:50:18.050562 <6>[ 0.766903] PCI: CLS 0 bytes, default 64
10776 12:50:18.053387 <6>[ 0.771297] Unpacking initramfs...
10777 12:50:18.078291 <6>[ 0.790875] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10778 12:50:18.088283 <6>[ 0.799551] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10779 12:50:18.091238 <6>[ 0.808407] kvm [1]: IPA Size Limit: 40 bits
10780 12:50:18.098296 <6>[ 0.812935] kvm [1]: GICv3: no GICV resource entry
10781 12:50:18.101611 <6>[ 0.817957] kvm [1]: disabling GICv2 emulation
10782 12:50:18.107682 <6>[ 0.822657] kvm [1]: GIC system register CPU interface enabled
10783 12:50:18.111539 <6>[ 0.828828] kvm [1]: vgic interrupt IRQ18
10784 12:50:18.118187 <6>[ 0.833188] kvm [1]: VHE mode initialized successfully
10785 12:50:18.124836 <5>[ 0.839562] Initialise system trusted keyrings
10786 12:50:18.131297 <6>[ 0.844349] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10787 12:50:18.138484 <6>[ 0.854322] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10788 12:50:18.145286 <5>[ 0.860669] NFS: Registering the id_resolver key type
10789 12:50:18.148554 <5>[ 0.865970] Key type id_resolver registered
10790 12:50:18.155246 <5>[ 0.870384] Key type id_legacy registered
10791 12:50:18.161902 <6>[ 0.874665] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10792 12:50:18.168285 <6>[ 0.881589] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10793 12:50:18.175008 <6>[ 0.889289] 9p: Installing v9fs 9p2000 file system support
10794 12:50:18.211215 <5>[ 0.927322] Key type asymmetric registered
10795 12:50:18.214233 <5>[ 0.931655] Asymmetric key parser 'x509' registered
10796 12:50:18.224188 <6>[ 0.936804] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10797 12:50:18.227536 <6>[ 0.944421] io scheduler mq-deadline registered
10798 12:50:18.231345 <6>[ 0.949202] io scheduler kyber registered
10799 12:50:18.249866 <6>[ 0.966009] EINJ: ACPI disabled.
10800 12:50:18.282247 <4>[ 0.991621] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10801 12:50:18.292067 <4>[ 1.002257] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10802 12:50:18.306728 <6>[ 1.023155] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10803 12:50:18.314724 <6>[ 1.031097] printk: console [ttyS0] disabled
10804 12:50:18.343196 <6>[ 1.055744] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10805 12:50:18.349815 <6>[ 1.065239] printk: console [ttyS0] enabled
10806 12:50:18.353318 <6>[ 1.065239] printk: console [ttyS0] enabled
10807 12:50:18.356691 <6>[ 1.074132] printk: bootconsole [mtk8250] disabled
10808 12:50:18.363380 <6>[ 1.074132] printk: bootconsole [mtk8250] disabled
10809 12:50:18.370010 <6>[ 1.085371] SuperH (H)SCI(F) driver initialized
10810 12:50:18.373330 <6>[ 1.090660] msm_serial: driver initialized
10811 12:50:18.387363 <6>[ 1.099573] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10812 12:50:18.397156 <6>[ 1.108120] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10813 12:50:18.403564 <6>[ 1.116665] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10814 12:50:18.413603 <6>[ 1.125294] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10815 12:50:18.423826 <6>[ 1.134006] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10816 12:50:18.430064 <6>[ 1.142727] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10817 12:50:18.440545 <6>[ 1.151270] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10818 12:50:18.446562 <6>[ 1.160081] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10819 12:50:18.456440 <6>[ 1.168626] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10820 12:50:18.468380 <6>[ 1.184132] loop: module loaded
10821 12:50:18.474944 <6>[ 1.190107] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10822 12:50:18.497131 <4>[ 1.212712] mtk-pmic-keys: Failed to locate of_node [id: -1]
10823 12:50:18.503630 <6>[ 1.219446] megasas: 07.719.03.00-rc1
10824 12:50:18.512982 <6>[ 1.228854] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10825 12:50:18.522349 <6>[ 1.238055] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10826 12:50:18.539134 <6>[ 1.254964] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10827 12:50:18.596185 <6>[ 1.305580] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10828 12:50:22.099142 <6>[ 4.815620] Freeing initrd memory: 95880K
10829 12:50:22.109380 <6>[ 4.825827] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10830 12:50:22.120202 <6>[ 4.836605] tun: Universal TUN/TAP device driver, 1.6
10831 12:50:22.123532 <6>[ 4.842662] thunder_xcv, ver 1.0
10832 12:50:22.126871 <6>[ 4.846155] thunder_bgx, ver 1.0
10833 12:50:22.130019 <6>[ 4.849651] nicpf, ver 1.0
10834 12:50:22.140284 <6>[ 4.853665] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10835 12:50:22.143952 <6>[ 4.861140] hns3: Copyright (c) 2017 Huawei Corporation.
10836 12:50:22.147199 <6>[ 4.866725] hclge is initializing
10837 12:50:22.153617 <6>[ 4.870304] e1000: Intel(R) PRO/1000 Network Driver
10838 12:50:22.160533 <6>[ 4.875434] e1000: Copyright (c) 1999-2006 Intel Corporation.
10839 12:50:22.163826 <6>[ 4.881449] e1000e: Intel(R) PRO/1000 Network Driver
10840 12:50:22.169966 <6>[ 4.886664] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10841 12:50:22.176574 <6>[ 4.892848] igb: Intel(R) Gigabit Ethernet Network Driver
10842 12:50:22.183115 <6>[ 4.898498] igb: Copyright (c) 2007-2014 Intel Corporation.
10843 12:50:22.190074 <6>[ 4.904333] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10844 12:50:22.196550 <6>[ 4.910851] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10845 12:50:22.200106 <6>[ 4.917312] sky2: driver version 1.30
10846 12:50:22.206718 <6>[ 4.922275] VFIO - User Level meta-driver version: 0.3
10847 12:50:22.213824 <6>[ 4.930472] usbcore: registered new interface driver usb-storage
10848 12:50:22.220581 <6>[ 4.936920] usbcore: registered new device driver onboard-usb-hub
10849 12:50:22.229273 <6>[ 4.945965] mt6397-rtc mt6359-rtc: registered as rtc0
10850 12:50:22.239048 <6>[ 4.951421] mt6397-rtc mt6359-rtc: setting system clock to 2023-07-20T12:50:25 UTC (1689857425)
10851 12:50:22.242321 <6>[ 4.960977] i2c_dev: i2c /dev entries driver
10852 12:50:22.259174 <6>[ 4.972544] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10853 12:50:22.266099 <6>[ 4.982774] sdhci: Secure Digital Host Controller Interface driver
10854 12:50:22.272746 <6>[ 4.989209] sdhci: Copyright(c) Pierre Ossman
10855 12:50:22.279338 <6>[ 4.994593] Synopsys Designware Multimedia Card Interface Driver
10856 12:50:22.282647 <6>[ 5.001217] mmc0: CQHCI version 5.10
10857 12:50:22.289211 <6>[ 5.001748] sdhci-pltfm: SDHCI platform and OF driver helper
10858 12:50:22.296557 <6>[ 5.013150] ledtrig-cpu: registered to indicate activity on CPUs
10859 12:50:22.307369 <6>[ 5.020488] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10860 12:50:22.310634 <6>[ 5.027872] usbcore: registered new interface driver usbhid
10861 12:50:22.317077 <6>[ 5.033699] usbhid: USB HID core driver
10862 12:50:22.323947 <6>[ 5.037937] spi_master spi0: will run message pump with realtime priority
10863 12:50:22.368401 <6>[ 5.078665] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10864 12:50:22.387829 <6>[ 5.094244] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10865 12:50:22.391146 <6>[ 5.107861] mmc0: Command Queue Engine enabled
10866 12:50:22.398663 <6>[ 5.109399] cros-ec-spi spi0.0: Chrome EC device registered
10867 12:50:22.402033 <6>[ 5.112603] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10868 12:50:22.408693 <6>[ 5.125737] mmcblk0: mmc0:0001 DA4128 116 GiB
10869 12:50:22.424454 <6>[ 5.137650] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10870 12:50:22.430944 <6>[ 5.140437] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10871 12:50:22.437659 <6>[ 5.149094] NET: Registered PF_PACKET protocol family
10872 12:50:22.440995 <6>[ 5.154551] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10873 12:50:22.447427 <6>[ 5.158320] 9pnet: Installing 9P2000 support
10874 12:50:22.450773 <6>[ 5.164187] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10875 12:50:22.457384 <5>[ 5.168017] Key type dns_resolver registered
10876 12:50:22.460938 <6>[ 5.174018] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10877 12:50:22.467768 <6>[ 5.178347] registered taskstats version 1
10878 12:50:22.470912 <5>[ 5.188614] Loading compiled-in X.509 certificates
10879 12:50:22.506980 <4>[ 5.216853] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10880 12:50:22.516815 <4>[ 5.227524] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10881 12:50:22.527019 <3>[ 5.240184] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10882 12:50:22.538638 <6>[ 5.255660] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10883 12:50:22.546048 <6>[ 5.262482] xhci-mtk 11200000.usb: xHCI Host Controller
10884 12:50:22.552213 <6>[ 5.267985] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10885 12:50:22.562742 <6>[ 5.275832] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10886 12:50:22.569371 <6>[ 5.285261] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10887 12:50:22.575684 <6>[ 5.291348] xhci-mtk 11200000.usb: xHCI Host Controller
10888 12:50:22.582833 <6>[ 5.296831] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10889 12:50:22.589144 <6>[ 5.304483] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10890 12:50:22.595910 <6>[ 5.312218] hub 1-0:1.0: USB hub found
10891 12:50:22.599102 <6>[ 5.316248] hub 1-0:1.0: 1 port detected
10892 12:50:22.605743 <6>[ 5.320588] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10893 12:50:22.612905 <6>[ 5.329494] hub 2-0:1.0: USB hub found
10894 12:50:22.616088 <6>[ 5.333543] hub 2-0:1.0: 1 port detected
10895 12:50:22.624159 <6>[ 5.340878] mtk-msdc 11f70000.mmc: Got CD GPIO
10896 12:50:22.641351 <6>[ 5.354762] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10897 12:50:22.648066 <6>[ 5.362800] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10898 12:50:22.658258 <4>[ 5.370797] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10899 12:50:22.668227 <6>[ 5.380467] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10900 12:50:22.674311 <6>[ 5.388549] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10901 12:50:22.681597 <6>[ 5.396575] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10902 12:50:22.691309 <6>[ 5.404496] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10903 12:50:22.697895 <6>[ 5.412316] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10904 12:50:22.707864 <6>[ 5.420138] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10905 12:50:22.717982 <6>[ 5.430871] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10906 12:50:22.724725 <6>[ 5.439246] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10907 12:50:22.734555 <6>[ 5.447592] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10908 12:50:22.741053 <6>[ 5.455936] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10909 12:50:22.750953 <6>[ 5.464280] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10910 12:50:22.757494 <6>[ 5.472629] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10911 12:50:22.767400 <6>[ 5.480973] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10912 12:50:22.777229 <6>[ 5.489317] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10913 12:50:22.784110 <6>[ 5.497662] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10914 12:50:22.793970 <6>[ 5.506006] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10915 12:50:22.800523 <6>[ 5.514357] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10916 12:50:22.810813 <6>[ 5.522701] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10917 12:50:22.817143 <6>[ 5.531045] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10918 12:50:22.827102 <6>[ 5.539391] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10919 12:50:22.833685 <6>[ 5.547739] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10920 12:50:22.840179 <6>[ 5.556665] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10921 12:50:22.847451 <6>[ 5.564099] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10922 12:50:22.854252 <6>[ 5.571140] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10923 12:50:22.864897 <6>[ 5.578214] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10924 12:50:22.871477 <6>[ 5.585475] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10925 12:50:22.878255 <6>[ 5.592374] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10926 12:50:22.888362 <6>[ 5.601517] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10927 12:50:22.898422 <6>[ 5.610646] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10928 12:50:22.908433 <6>[ 5.619949] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10929 12:50:22.918027 <6>[ 5.629424] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10930 12:50:22.924703 <6>[ 5.638899] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10931 12:50:22.934759 <6>[ 5.648027] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10932 12:50:22.944551 <6>[ 5.657502] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10933 12:50:22.954912 <6>[ 5.666629] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10934 12:50:22.964936 <6>[ 5.675935] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10935 12:50:22.974760 <6>[ 5.686101] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10936 12:50:22.984491 <6>[ 5.698078] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10937 12:50:23.005475 <6>[ 5.718959] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10938 12:50:23.033222 <6>[ 5.749631] hub 2-1:1.0: USB hub found
10939 12:50:23.036578 <6>[ 5.754030] hub 2-1:1.0: 3 ports detected
10940 12:50:23.157631 <6>[ 5.870902] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10941 12:50:23.311937 <6>[ 6.028610] hub 1-1:1.0: USB hub found
10942 12:50:23.315204 <6>[ 6.033041] hub 1-1:1.0: 4 ports detected
10943 12:50:23.393411 <6>[ 6.107005] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10944 12:50:23.637135 <6>[ 6.350894] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10945 12:50:23.769367 <6>[ 6.485911] hub 1-1.4:1.0: USB hub found
10946 12:50:23.772348 <6>[ 6.490439] hub 1-1.4:1.0: 2 ports detected
10947 12:50:24.069338 <6>[ 6.782893] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10948 12:50:24.257141 <6>[ 6.970925] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10949 12:50:35.273863 <6>[ 17.995477] ALSA device list:
10950 12:50:35.280490 <6>[ 17.998735] No soundcards found.
10951 12:50:35.292952 <6>[ 18.011167] Freeing unused kernel memory: 8384K
10952 12:50:35.296243 <6>[ 18.016046] Run /init as init process
10953 12:50:35.326102 <6>[ 18.043944] NET: Registered PF_INET6 protocol family
10954 12:50:35.332722 <6>[ 18.050131] Segment Routing with IPv6
10955 12:50:35.335946 <6>[ 18.054091] In-situ OAM (IOAM) with IPv6
10956 12:50:35.370268 <30>[ 18.068338] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10957 12:50:35.373767 <30>[ 18.092110] systemd[1]: Detected architecture arm64.
10958 12:50:35.374080
10959 12:50:35.380478 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10960 12:50:35.380775
10961 12:50:35.393202 <30>[ 18.111089] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10962 12:50:35.534988 <30>[ 18.249412] systemd[1]: Queued start job for default target Graphical Interface.
10963 12:50:35.578246 <30>[ 18.296255] systemd[1]: Created slice system-getty.slice.
10964 12:50:35.584915 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10965 12:50:35.601577 <30>[ 18.319487] systemd[1]: Created slice system-modprobe.slice.
10966 12:50:35.607499 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10967 12:50:35.625013 <30>[ 18.343424] systemd[1]: Created slice system-serial\x2dgetty.slice.
10968 12:50:35.635262 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10969 12:50:35.650020 <30>[ 18.367926] systemd[1]: Created slice User and Session Slice.
10970 12:50:35.656554 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10971 12:50:35.676909 <30>[ 18.391461] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10972 12:50:35.686643 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10973 12:50:35.704535 <30>[ 18.419440] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10974 12:50:35.711237 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10975 12:50:35.731730 <30>[ 18.443064] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10976 12:50:35.738393 <30>[ 18.455100] systemd[1]: Reached target Local Encrypted Volumes.
10977 12:50:35.744523 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10978 12:50:35.760974 <30>[ 18.479274] systemd[1]: Reached target Paths.
10979 12:50:35.764202 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10980 12:50:35.780952 <30>[ 18.498960] systemd[1]: Reached target Remote File Systems.
10981 12:50:35.787041 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10982 12:50:35.800613 <30>[ 18.518952] systemd[1]: Reached target Slices.
10983 12:50:35.803924 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10984 12:50:35.820786 <30>[ 18.538975] systemd[1]: Reached target Swap.
10985 12:50:35.824087 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10986 12:50:35.844259 <30>[ 18.559255] systemd[1]: Listening on initctl Compatibility Named Pipe.
10987 12:50:35.850993 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10988 12:50:35.857597 <30>[ 18.573999] systemd[1]: Listening on Journal Audit Socket.
10989 12:50:35.864052 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10990 12:50:35.877142 <30>[ 18.595228] systemd[1]: Listening on Journal Socket (/dev/log).
10991 12:50:35.883496 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10992 12:50:35.900780 <30>[ 18.619233] systemd[1]: Listening on Journal Socket.
10993 12:50:35.907585 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10994 12:50:35.921181 <30>[ 18.639236] systemd[1]: Listening on udev Control Socket.
10995 12:50:35.927836 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10996 12:50:35.945425 <30>[ 18.663578] systemd[1]: Listening on udev Kernel Socket.
10997 12:50:35.951903 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10998 12:50:35.984714 <30>[ 18.703103] systemd[1]: Mounting Huge Pages File System...
10999 12:50:35.991433 Mounting [0;1;39mHuge Pages File System[0m...
11000 12:50:36.007361 <30>[ 18.725179] systemd[1]: Mounting POSIX Message Queue File System...
11001 12:50:36.013855 Mounting [0;1;39mPOSIX Message Queue File System[0m...
11002 12:50:36.031260 <30>[ 18.749131] systemd[1]: Mounting Kernel Debug File System...
11003 12:50:36.037862 Mounting [0;1;39mKernel Debug File System[0m...
11004 12:50:36.056559 <30>[ 18.771200] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
11005 12:50:36.067966 <30>[ 18.782224] systemd[1]: Starting Create list of static device nodes for the current kernel...
11006 12:50:36.074343 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
11007 12:50:36.121693 <30>[ 18.839366] systemd[1]: Starting Load Kernel Module configfs...
11008 12:50:36.128399 Starting [0;1;39mLoad Kernel Module configfs[0m...
11009 12:50:36.143539 <30>[ 18.861384] systemd[1]: Starting Load Kernel Module drm...
11010 12:50:36.150125 Starting [0;1;39mLoad Kernel Module drm[0m...
11011 12:50:36.168490 <30>[ 18.883204] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
11012 12:50:36.197813 <30>[ 18.915516] systemd[1]: Starting Journal Service...
11013 12:50:36.201251 Starting [0;1;39mJournal Service[0m...
11014 12:50:36.219712 <30>[ 18.937818] systemd[1]: Starting Load Kernel Modules...
11015 12:50:36.226576 Starting [0;1;39mLoad Kernel Modules[0m...
11016 12:50:36.246658 <30>[ 18.961529] systemd[1]: Starting Remount Root and Kernel File Systems...
11017 12:50:36.253425 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
11018 12:50:36.267213 <30>[ 18.985601] systemd[1]: Starting Coldplug All udev Devices...
11019 12:50:36.274222 Starting [0;1;39mColdplug All udev Devices[0m...
11020 12:50:36.291584 <30>[ 19.009659] systemd[1]: Mounted Huge Pages File System.
11021 12:50:36.297741 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
11022 12:50:36.313019 <30>[ 19.031381] systemd[1]: Started Journal Service.
11023 12:50:36.319743 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11024 12:50:36.334375 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11025 12:50:36.349453 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11026 12:50:36.369282 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11027 12:50:36.387327 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11028 12:50:36.402573 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11029 12:50:36.418373 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11030 12:50:36.438085 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11031 12:50:36.453267 See 'systemctl status systemd-remount-fs.service' for details.
11032 12:50:36.505699 Mounting [0;1;39mKernel Configuration File System[0m...
11033 12:50:36.523993 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11034 12:50:36.541120 <46>[ 19.255473] systemd-journald[181]: Received client request to flush runtime journal.
11035 12:50:36.549886 Starting [0;1;39mLoad/Save Random Seed[0m...
11036 12:50:36.568398 Starting [0;1;39mApply Kernel Variables[0m...
11037 12:50:36.588250 Starting [0;1;39mCreate System Users[0m...
11038 12:50:36.607600 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11039 12:50:36.633618 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11040 12:50:36.650220 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11041 12:50:36.666800 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11042 12:50:36.682045 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11043 12:50:36.697943 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11044 12:50:36.734090 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11045 12:50:36.755651 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11046 12:50:36.773144 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11047 12:50:36.793050 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11048 12:50:36.825282 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11049 12:50:36.848629 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11050 12:50:36.865985 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11051 12:50:36.886637 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11052 12:50:36.943169 Starting [0;1;39mNetwork Time Synchronization[0m...
11053 12:50:36.964122 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11054 12:50:36.995942 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11055 12:50:37.042785 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11056 12:50:37.063975 <6>[ 19.778319] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11057 12:50:37.075227 <6>[ 19.793357] remoteproc remoteproc0: scp is available
11058 12:50:37.081974 <6>[ 19.799372] remoteproc remoteproc0: powering up scp
11059 12:50:37.092085 <6>[ 19.805939] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11060 12:50:37.098491 <6>[ 19.815548] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11061 12:50:37.105401 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11062 12:50:37.128066 [[0;32m OK [<6>[ 19.843138] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11063 12:50:37.137418 0m] Started [0;<6>[ 19.851736] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11064 12:50:37.147289 1;39mNetwork Tim<6>[ 19.861664] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11065 12:50:37.157275 e Synchronizatio<3>[ 19.872467] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11066 12:50:37.157391 n[0m.
11067 12:50:37.167099 <3>[ 19.881256] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11068 12:50:37.173668 <3>[ 19.890097] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11069 12:50:37.184325 <3>[ 19.899244] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11070 12:50:37.190888 <3>[ 19.907391] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11071 12:50:37.197320 <6>[ 19.908515] usbcore: registered new interface driver r8152
11072 12:50:37.207822 <3>[ 19.915571] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11073 12:50:37.214365 <3>[ 19.915589] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11074 12:50:37.220654 <3>[ 19.915599] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11075 12:50:37.230589 <3>[ 19.921861] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11076 12:50:37.237273 <4>[ 19.939178] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11077 12:50:37.247295 <6>[ 19.942568] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11078 12:50:37.253959 <6>[ 19.942577] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11079 12:50:37.260890 <6>[ 19.942581] remoteproc remoteproc0: remote processor scp is now up
11080 12:50:37.267574 <6>[ 19.947028] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11081 12:50:37.274127 <4>[ 19.960056] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11082 12:50:37.284068 <3>[ 19.961384] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11083 12:50:37.287353 <6>[ 19.991878] mc: Linux media interface: v0.10
11084 12:50:37.297347 <3>[ 19.998254] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11085 12:50:37.303820 <3>[ 19.998265] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11086 12:50:37.310701 <3>[ 20.003772] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11087 12:50:37.317398 <6>[ 20.007946] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11088 12:50:37.327414 <3>[ 20.012260] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11089 12:50:37.337363 <4>[ 20.017253] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11090 12:50:37.341155 <4>[ 20.017253] Fallback method does not support PEC.
11091 12:50:37.348383 <6>[ 20.019517] pci_bus 0000:00: root bus resource [bus 00-ff]
11092 12:50:37.355140 <6>[ 20.023030] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11093 12:50:37.361862 <3>[ 20.027626] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11094 12:50:37.368682 <6>[ 20.035703] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11095 12:50:37.378723 <6>[ 20.035714] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11096 12:50:37.388734 <3>[ 20.036786] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11097 12:50:37.395940 <3>[ 20.042587] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11098 12:50:37.405467 <4>[ 20.047305] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11099 12:50:37.412146 <4>[ 20.047320] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11100 12:50:37.418693 <6>[ 20.050724] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11101 12:50:37.428741 <6>[ 20.063342] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11102 12:50:37.438818 <6>[ 20.063826] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11103 12:50:37.445413 <3>[ 20.064301] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11104 12:50:37.456106 <3>[ 20.064533] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11105 12:50:37.462258 <6>[ 20.070077] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11106 12:50:37.472489 <3>[ 20.077002] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11107 12:50:37.479806 <3>[ 20.077831] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11108 12:50:37.483540 <6>[ 20.085610] pci 0000:00:00.0: supports D1 D2
11109 12:50:37.494210 <6>[ 20.089489] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11110 12:50:37.497554 <6>[ 20.103010] r8152 2-1.3:1.0 eth0: v1.12.13
11111 12:50:37.507654 <3>[ 20.109312] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11112 12:50:37.515019 <6>[ 20.111249] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11113 12:50:37.518445 <6>[ 20.113120] videodev: Linux video capture interface: v2.00
11114 12:50:37.525568 <6>[ 20.120483] usbcore: registered new interface driver cdc_ether
11115 12:50:37.535006 <6>[ 20.132675] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11116 12:50:37.542232 <6>[ 20.132962] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11117 12:50:37.549692 <6>[ 20.139479] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11118 12:50:37.552989 <6>[ 20.142336] Bluetooth: Core ver 2.22
11119 12:50:37.556319 <6>[ 20.142411] NET: Registered PF_BLUETOOTH protocol family
11120 12:50:37.562949 <6>[ 20.142413] Bluetooth: HCI device and connection manager initialized
11121 12:50:37.569800 <6>[ 20.142437] Bluetooth: HCI socket layer initialized
11122 12:50:37.573719 <6>[ 20.142444] Bluetooth: L2CAP socket layer initialized
11123 12:50:37.580442 <6>[ 20.142459] Bluetooth: SCO socket layer initialized
11124 12:50:37.586951 <6>[ 20.145036] usbcore: registered new interface driver r8153_ecm
11125 12:50:37.594072 <6>[ 20.146427] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11126 12:50:37.600236 <6>[ 20.154396] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11127 12:50:37.607361 <6>[ 20.178802] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
11128 12:50:37.614075 <6>[ 20.179880] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11129 12:50:37.627920 <6>[ 20.181457] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11130 12:50:37.634936 <6>[ 20.181622] usbcore: registered new interface driver uvcvideo
11131 12:50:37.641437 <6>[ 20.185792] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11132 12:50:37.648718 <6>[ 20.185816] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11133 12:50:37.652684 <6>[ 20.204123] usbcore: registered new interface driver btusb
11134 12:50:37.659288 <6>[ 20.204582] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11135 12:50:37.670607 <4>[ 20.204810] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11136 12:50:37.676625 <3>[ 20.204821] Bluetooth: hci0: Failed to load firmware file (-2)
11137 12:50:37.683447 <3>[ 20.204827] Bluetooth: hci0: Failed to set up firmware (-2)
11138 12:50:37.693229 <4>[ 20.204831] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11139 12:50:37.696519 <6>[ 20.208010] pci 0000:01:00.0: supports D1 D2
11140 12:50:37.706938 <3>[ 20.211371] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11141 12:50:37.716741 <3>[ 20.217889] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11142 12:50:37.722946 <3>[ 20.218746] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11143 12:50:37.730152 <6>[ 20.221538] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11144 12:50:37.736606 <6>[ 20.234845] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11145 12:50:37.746816 <3>[ 20.241573] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11146 12:50:37.753667 <6>[ 20.242981] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11147 12:50:37.763049 <3>[ 20.274155] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11148 12:50:37.769764 <6>[ 20.275637] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11149 12:50:37.779929 <6>[ 20.275650] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11150 12:50:37.786687 <6>[ 20.275666] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11151 12:50:37.796703 <3>[ 20.301326] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11152 12:50:37.803270 <6>[ 20.303389] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11153 12:50:37.809955 <6>[ 20.303405] pci 0000:00:00.0: PCI bridge to [bus 01]
11154 12:50:37.816544 <6>[ 20.532889] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11155 12:50:37.823270 <6>[ 20.533076] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11156 12:50:37.832661 [[0;32m OK [<6>[ 20.548375] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11157 12:50:37.839392 0m] Finished [0<6>[ 20.556477] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11158 12:50:37.846216 ;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11159 12:50:37.859797 <5>[ 20.575000] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11160 12:50:37.871023 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11161 12:50:37.877110 <5>[ 20.594842] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11162 12:50:37.886991 <4>[ 20.601736] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11163 12:50:37.890337 <6>[ 20.610626] cfg80211: failed to load regulatory.db
11164 12:50:37.937885 <6>[ 20.652765] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11165 12:50:37.944613 <6>[ 20.660374] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11166 12:50:37.968759 <6>[ 20.687165] mt7921e 0000:01:00.0: ASIC revision: 79610010
11167 12:50:38.057300 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11168 12:50:38.075747 <4>[ 20.787274] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11169 12:50:38.082258 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11170 12:50:38.101315 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11171 12:50:38.117319 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11172 12:50:38.133226 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11173 12:50:38.149219 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11174 12:50:38.168427 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11175 12:50:38.198480 [[0;32m OK [0m] Listening on [0;1;39mD-Bus <4>[ 20.909678] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11176 12:50:38.201320 System Message Bus Socket[0m.
11177 12:50:38.217431 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11178 12:50:38.236546 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11179 12:50:38.256126 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11180 12:50:38.297723 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11181 12:50:38.320169 <4>[ 21.031465] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11182 12:50:38.331823 Starting [0;1;39mUser Login Management[0m...
11183 12:50:38.346833 Starting [0;1;39mPermit User Sessions[0m...
11184 12:50:38.363628 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11185 12:50:38.384144 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11186 12:50:38.400449 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11187 12:50:38.419417 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11188 12:50:38.442171 <4>[ 21.153773] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11189 12:50:38.448774 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11190 12:50:38.465428 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11191 12:50:38.482133 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11192 12:50:38.497062 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11193 12:50:38.512983 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11194 12:50:38.561705 <4>[ 21.273329] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11195 12:50:38.586553 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11196 12:50:38.612839 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11197 12:50:38.627201
11198 12:50:38.627618
11199 12:50:38.630698 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11200 12:50:38.631130
11201 12:50:38.633609 debian-bullseye-arm64 login: root (automatic login)
11202 12:50:38.634042
11203 12:50:38.634466
11204 12:50:38.650293 Linux debian-bullseye-arm64 6.1.38-cip1 #1 SMP PREEMPT Thu Jul 20 12:35:57 UTC 2023 aarch64
11205 12:50:38.650737
11206 12:50:38.657099 The programs included with the Debian GNU/Linux system are free software;
11207 12:50:38.663659 the exact distribution terms for each program are described in the
11208 12:50:38.666874 individual files in /usr/share/doc/*/copyright.
11209 12:50:38.667291
11210 12:50:38.683976 Debian GNU/Linux comes with ABSOLUTELY NO WARRA<4>[ 21.393421] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11211 12:50:38.684520 NTY, to the extent
11212 12:50:38.687115 permitted by applicable law.
11213 12:50:38.688415 Matched prompt #10: / #
11215 12:50:38.689600 Setting prompt string to ['/ #']
11216 12:50:38.690040 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11218 12:50:38.691066 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11219 12:50:38.691521 start: 2.2.6 expect-shell-connection (timeout 00:01:46) [common]
11220 12:50:38.691882 Setting prompt string to ['/ #']
11221 12:50:38.692194 Forcing a shell prompt, looking for ['/ #']
11223 12:50:38.743087 / #
11224 12:50:38.743585 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11225 12:50:38.743973 Waiting using forced prompt support (timeout 00:02:30)
11226 12:50:38.749565
11227 12:50:38.750470 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11228 12:50:38.750955 start: 2.2.7 export-device-env (timeout 00:01:46) [common]
11229 12:50:38.751457 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11230 12:50:38.751951 end: 2.2 depthcharge-retry (duration 00:03:14) [common]
11231 12:50:38.752420 end: 2 depthcharge-action (duration 00:03:14) [common]
11232 12:50:38.753051 start: 3 lava-test-retry (timeout 00:05:00) [common]
11233 12:50:38.753810 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11234 12:50:38.754480 Using namespace: common
11236 12:50:38.855531 / # #
11237 12:50:38.856048 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11238 12:50:38.856553 <4>[ 21.513088] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11239 12:50:38.861945 #
11240 12:50:38.862654 Using /lava-11118892
11242 12:50:38.963808 / # export SHELL=/bin/sh
11243 12:50:38.964585 <4>[ 21.632898] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11244 12:50:38.969993 export SHELL=/bin/sh
11246 12:50:39.071326 / # . /lava-11118892/environment
11247 12:50:39.072042 . /lava-11118892/environment<4>[ 21.753262] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11248 12:50:39.077472
11250 12:50:39.178843 / # /lava-11118892/bin/lava-test-runner /lava-11118892/0
11251 12:50:39.179453 Test shell timeout: 10s (minimum of the action and connection timeout)
11252 12:50:39.179953 /lava-11118892/bin/lava-test-runner /lava-11118892/0<4>[ 21.872978] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11253 12:50:39.184912
11254 12:50:39.232843 + export TESTRUN_ID=0_sleep
11255 12:50:39.233058 + cd /lava-11118892/0/tests/0_sleep
11256 12:50:39.233203 + cat uuid
11257 12:50:39.233332 + UUID=11118892_1.5.2.3.1
11258 12:50:39.233457 + set +x
11259 12:50:39.233580 <LAVA_SIGNAL_STARTRUN 0_sleep 11118892_1.5.2.3.1>
11260 12:50:39.233701 + ./config/lava/sleep/sleep.sh mem freeze
11261 12:50:39.233821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11262 12:50:39.233938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11263 12:50:39.234287 Received signal: <STARTRUN> 0_sleep 11118892_1.5.2.3.1
11264 12:50:39.234453 Starting test lava.0_sleep (11118892_1.5.2.3.1)
11265 12:50:39.234642 Skipping test definition patterns.
11266 12:50:39.234869 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11268 12:50:39.235372 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11270 12:50:39.235843 rtcwake: assuming RTC uses UTC ...
11271 12:50:39.241053 rtcwake: wakeup from "mem" u<6>[ 21.960905] PM: suspend entry (deep)
11272 12:50:39.247617 sing rtc0 at Thu<6>[ 21.964881] Filesystems sync: 0.000 seconds
11273 12:50:39.247917 Jul 20 12:50:48 2023
11274 12:50:39.254405 <6>[ 21.972818] Freezing user space processes
11275 12:50:39.261104 <6>[ 21.978749] Freezing user space processes completed (elapsed 0.001 seconds)
11276 12:50:39.267557 <6>[ 21.986015] OOM killer disabled.
11277 12:50:39.271091 <6>[ 21.989561] Freezing remaining freezable tasks
11278 12:50:39.277765 <3>[ 21.990977] mt7921e 0000:01:00.0: hardware init failed
11279 12:50:39.284226 <6>[ 21.995567] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11280 12:50:39.290916 <6>[ 22.007316] printk: Suspending console(s) (use no_console_suspend to debug)
11281 12:50:42.677135 <3>[ 25.162957] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11282 12:50:42.687165 <3>[ 25.162995] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11283 12:50:42.696930 <3>[ 25.163031] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11284 12:50:42.704037 <3>[ 25.163053] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11285 12:50:42.710432 <3>[ 25.163220] PM: Some devices failed to suspend, or early wake event detected
11286 12:50:42.717580 <4>[ 25.179478] typec port0-partner: PM: parent port0 should not be sleeping
11287 12:50:42.723532 <6>[ 25.442956] OOM killer enabled.
11288 12:50:42.726950 <6>[ 25.446351] Restarting tasks ... done.
11289 12:50:42.734137 <5>[ 25.452162] random: crng reseeded on system resumption
11290 12:50:42.737349 <6>[ 25.458484] PM: suspend exit
11291 12:50:42.740632 rtcwake: write error
11292 12:50:42.747114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11293 12:50:42.747372 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11295 12:50:42.750926 rtcwake: assuming RTC uses UTC ...
11296 12:50:42.757343 rtcwake: wakeup from "mem" using rtc0 at Thu Jul 20 12:50:51 2023
11297 12:50:42.769832 <6>[ 25.488974] PM: suspend entry (deep)
11298 12:50:42.773169 <6>[ 25.492860] Filesystems sync: 0.000 seconds
11299 12:50:42.777066 <6>[ 25.498127] Freezing user space processes
11300 12:50:42.788571 <6>[ 25.504327] Freezing user space processes completed (elapsed 0.001 seconds)
11301 12:50:42.791954 <6>[ 25.511555] OOM killer disabled.
11302 12:50:42.795413 <6>[ 25.515067] Freezing remaining freezable tasks
11303 12:50:42.805027 <6>[ 25.520956] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11304 12:50:42.811548 <6>[ 25.528618] printk: Suspending console(s) (use no_console_suspend to debug)
11305 12:50:46.261105 <3>[ 28.746924] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11306 12:50:46.270954 <3>[ 28.746949] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11307 12:50:46.281186 <3>[ 28.746983] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11308 12:50:46.287830 <3>[ 28.747003] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11309 12:50:46.294419 <3>[ 28.747396] PM: Some devices failed to suspend, or early wake event detected
11310 12:50:46.298068 <6>[ 29.020096] OOM killer enabled.
11311 12:50:46.306253 <6>[ 29.023498] Restarting tasks ... done.
11312 12:50:46.309375 <5>[ 29.029570] random: crng reseeded on system resumption
11313 12:50:46.313841 <6>[ 29.036467] PM: suspend exit
11314 12:50:46.317061 rtcwake: write error
11315 12:50:46.324889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11316 12:50:46.325194 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11318 12:50:46.328573 rtcwake: assuming RTC uses UTC ...
11319 12:50:46.334990 rtcwake: wakeup from "mem" using rtc0 at Thu Jul 20 12:50:55 2023
11320 12:50:46.347749 <6>[ 29.066962] PM: suspend entry (deep)
11321 12:50:46.350877 <6>[ 29.070864] Filesystems sync: 0.000 seconds
11322 12:50:46.354533 <6>[ 29.076093] Freezing user space processes
11323 12:50:46.366023 <6>[ 29.082129] Freezing user space processes completed (elapsed 0.001 seconds)
11324 12:50:46.369628 <6>[ 29.089364] OOM killer disabled.
11325 12:50:46.372983 <6>[ 29.092847] Freezing remaining freezable tasks
11326 12:50:46.382932 <6>[ 29.098695] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11327 12:50:46.389497 <6>[ 29.106350] printk: Suspending console(s) (use no_console_suspend to debug)
11328 12:50:49.845323 <3>[ 32.330896] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11329 12:50:49.855474 <3>[ 32.330921] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11330 12:50:49.865596 <3>[ 32.330947] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11331 12:50:49.872307 <3>[ 32.330969] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11332 12:50:49.878611 <3>[ 32.331329] PM: Some devices failed to suspend, or early wake event detected
11333 12:50:49.882067 <6>[ 32.604577] OOM killer enabled.
11334 12:50:49.890214 <6>[ 32.607976] Restarting tasks ... done.
11335 12:50:49.893288 <5>[ 32.613660] random: crng reseeded on system resumption
11336 12:50:49.897347 <6>[ 32.620331] PM: suspend exit
11337 12:50:49.900848 rtcwake: write error
11338 12:50:49.915877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11339 12:50:49.916597 rtcwake: assuming RTC uses UTC ...
11340 12:50:49.917484 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11342 12:50:49.919164 rtcwake: wakeup from "mem" using rtc0 at Thu Jul 20 12:50:58 2023
11343 12:50:49.931266 <6>[ 32.650908] PM: suspend entry (deep)
11344 12:50:49.935054 <6>[ 32.654839] Filesystems sync: 0.000 seconds
11345 12:50:49.938003 <6>[ 32.660003] Freezing user space processes
11346 12:50:49.950201 <6>[ 32.666125] Freezing user space processes completed (elapsed 0.001 seconds)
11347 12:50:49.953291 <6>[ 32.673492] OOM killer disabled.
11348 12:50:49.956465 <6>[ 32.676979] Freezing remaining freezable tasks
11349 12:50:49.966729 <6>[ 32.682732] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11350 12:50:49.973181 <6>[ 32.690388] printk: Suspending console(s) (use no_console_suspend to debug)
11351 12:50:53.428692 <3>[ 35.914904] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11352 12:50:53.438670 <3>[ 35.914928] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11353 12:50:53.448584 <3>[ 35.914954] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11354 12:50:53.455352 <3>[ 35.914976] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11355 12:50:53.462530 <3>[ 35.915342] PM: Some devices failed to suspend, or early wake event detected
11356 12:50:53.465706 <6>[ 36.188538] OOM killer enabled.
11357 12:50:53.473640 <6>[ 36.191937] Restarting tasks ... done.
11358 12:50:53.476526 <5>[ 36.197527] random: crng reseeded on system resumption
11359 12:50:53.480483 <6>[ 36.204030] PM: suspend exit
11360 12:50:53.484372 rtcwake: write error
11361 12:50:53.492711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11362 12:50:53.493427 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11364 12:50:53.495949 rtcwake: assuming RTC uses UTC ...
11365 12:50:53.502327 rtcwake: wakeup from "mem" using rtc0 at Thu Jul 20 12:51:02 2023
11366 12:50:53.515262 <6>[ 36.235072] PM: suspend entry (deep)
11367 12:50:53.518392 <6>[ 36.238971] Filesystems sync: 0.000 seconds
11368 12:50:53.525487 <6>[ 36.244178] Freezing user space processes
11369 12:50:53.531458 <6>[ 36.250346] Freezing user space processes completed (elapsed 0.001 seconds)
11370 12:50:53.535302 <6>[ 36.257650] OOM killer disabled.
11371 12:50:53.542106 <6>[ 36.261144] Freezing remaining freezable tasks
11372 12:50:53.548661 <6>[ 36.266694] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11373 12:50:53.555222 <6>[ 36.274351] printk: Suspending console(s) (use no_console_suspend to debug)
11374 12:50:57.011954 <3>[ 39.498921] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11375 12:50:57.022291 <3>[ 39.498946] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11376 12:50:57.031848 <3>[ 39.498980] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11377 12:50:57.038909 <3>[ 39.499001] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11378 12:50:57.046039 <3>[ 39.499293] PM: Some devices failed to suspend, or early wake event detected
11379 12:50:57.048572 <6>[ 39.772106] OOM killer enabled.
11380 12:50:57.057193 <6>[ 39.775505] Restarting tasks ... done.
11381 12:50:57.060443 <5>[ 39.781275] random: crng reseeded on system resumption
11382 12:50:57.064802 <6>[ 39.788190] PM: suspend exit
11383 12:50:57.068180 rtcwake: write error
11384 12:50:57.076404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11385 12:50:57.077330 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11387 12:50:57.079769 rtcwake: assuming RTC uses UTC ...
11388 12:50:57.086181 rtcwake: wakeup from "mem" using rtc0 at Thu Jul 20 12:51:06 2023
11389 12:50:57.099595 <6>[ 39.819269] PM: suspend entry (deep)
11390 12:50:57.102975 <6>[ 39.823174] Filesystems sync: 0.000 seconds
11391 12:50:57.106256 <6>[ 39.828337] Freezing user space processes
11392 12:50:57.117906 <6>[ 39.834499] Freezing user space processes completed (elapsed 0.001 seconds)
11393 12:50:57.121181 <6>[ 39.841822] OOM killer disabled.
11394 12:50:57.124350 <6>[ 39.845314] Freezing remaining freezable tasks
11395 12:50:57.134484 <6>[ 39.851310] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11396 12:50:57.141080 <6>[ 39.858969] printk: Suspending console(s) (use no_console_suspend to debug)
11397 12:51:00.596159 <3>[ 43.082897] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11398 12:51:00.606283 <3>[ 43.082921] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11399 12:51:00.615920 <3>[ 43.082947] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11400 12:51:00.623040 <3>[ 43.082969] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11401 12:51:00.629662 <3>[ 43.083442] PM: Some devices failed to suspend, or early wake event detected
11402 12:51:00.633193 <6>[ 43.356649] OOM killer enabled.
11403 12:51:00.640858 <6>[ 43.360047] Restarting tasks ... done.
11404 12:51:00.644144 <5>[ 43.365707] random: crng reseeded on system resumption
11405 12:51:00.648244 <6>[ 43.372436] PM: suspend exit
11406 12:51:00.651429 rtcwake: write error
11407 12:51:00.659156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11408 12:51:00.659842 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11410 12:51:00.663030 rtcwake: assuming RTC uses UTC ...
11411 12:51:00.669720 rtcwake: wakeup from "mem" using rtc0 at Thu Jul 20 12:51:09 2023
11412 12:51:00.682319 <6>[ 43.402877] PM: suspend entry (deep)
11413 12:51:00.685522 <6>[ 43.406785] Filesystems sync: 0.000 seconds
11414 12:51:00.689116 <6>[ 43.411959] Freezing user space processes
11415 12:51:00.700519 <6>[ 43.418052] Freezing user space processes completed (elapsed 0.001 seconds)
11416 12:51:00.704361 <6>[ 43.425292] OOM killer disabled.
11417 12:51:00.707324 <6>[ 43.428780] Freezing remaining freezable tasks
11418 12:51:00.717439 <6>[ 43.434677] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11419 12:51:00.723824 <6>[ 43.442334] printk: Suspending console(s) (use no_console_suspend to debug)
11420 12:51:05.116180 <3>[ 46.666925] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11421 12:51:05.116439 <3>[ 46.666950] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11422 12:51:05.116582 <3>[ 46.666983] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11423 12:51:05.116731 <3>[ 46.667004] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11424 12:51:05.116857 <3>[ 46.667439] PM: Some devices failed to suspend, or early wake event detected
11425 12:51:05.116978 <6>[ 46.940651] OOM killer enabled.
11426 12:51:05.117121 <6>[ 46.944050] Restarting tasks ... done.
11427 12:51:05.117258 <5>[ 46.949661] random: crng reseeded on system resumption
11428 12:51:05.117381 <6>[ 46.956235] PM: suspend exit
11429 12:51:05.117496 rtcwake: write error
11430 12:51:05.117609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11431 12:51:05.117777 rtcwake: assuming RTC uses UTC ...
11432 12:51:05.117905 rtcwake: wakeup from "mem" using rtc0 at Thu Jul 20 12:51:13 2023
11433 12:51:05.118030 <6>[ 46.987110] PM: suspend entry (deep)
11434 12:51:05.118144 <6>[ 46.991016] Filesystems sync: 0.000 seconds
11435 12:51:05.118257 <6>[ 46.996197] Freezing user space processes
11436 12:51:05.118370 <6>[ 47.002182] Freezing user space processes completed (elapsed 0.001 seconds)
11437 12:51:05.118483 <6>[ 47.009466] OOM killer disabled.
11438 12:51:05.118595 <6>[ 47.012957] Freezing remaining freezable tasks
11439 12:51:05.118706 <6>[ 47.018696] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11440 12:51:05.118819 <6>[ 47.026351] printk: Suspending console(s) (use no_console_suspend to debug)
11441 12:51:05.119142 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11443 12:51:07.759241 <6>[ 48.203021] vpu: disabling
11444 12:51:07.762664 <6>[ 48.203118] vproc2: disabling
11445 12:51:07.766400 <6>[ 48.203156] vproc1: disabling
11446 12:51:07.769827 <6>[ 48.203194] vaud18: disabling
11447 12:51:07.772946 <6>[ 48.203378] vsram_others: disabling
11448 12:51:07.776427 <6>[ 48.203525] va09: disabling
11449 12:51:07.779637 <6>[ 48.203580] vsram_md: disabling
11450 12:51:07.782583 <6>[ 48.203678] Vgpu: disabling
11451 12:51:07.789941 <3>[ 50.250893] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11452 12:51:07.799482 <3>[ 50.250919] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11453 12:51:07.809360 <3>[ 50.250945] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11454 12:51:07.816276 <3>[ 50.250968] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11455 12:51:07.823114 <3>[ 50.251331] PM: Some devices failed to suspend, or early wake event detected
11456 12:51:07.826231 <6>[ 50.549826] OOM killer enabled.
11457 12:51:07.833242 <6>[ 50.553224] Restarting tasks ... done.
11458 12:51:07.836640 <5>[ 50.558819] random: crng reseeded on system resumption
11459 12:51:07.840539 <6>[ 50.565234] PM: suspend exit
11460 12:51:07.843788 rtcwake: write error
11461 12:51:07.851933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11462 12:51:07.852795 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11464 12:51:07.855404 rtcwake: assuming RTC uses UTC ...
11465 12:51:07.861870 rtcwake: wakeup from "mem" using rtc0 at Thu Jul 20 12:51:16 2023
11466 12:51:07.874861 <6>[ 50.596061] PM: suspend entry (deep)
11467 12:51:07.878124 <6>[ 50.599953] Filesystems sync: 0.000 seconds
11468 12:51:07.884644 <6>[ 50.605255] Freezing user space processes
11469 12:51:07.891388 <6>[ 50.611286] Freezing user space processes completed (elapsed 0.001 seconds)
11470 12:51:07.894623 <6>[ 50.618509] OOM killer disabled.
11471 12:51:07.901315 <6>[ 50.621992] Freezing remaining freezable tasks
11472 12:51:07.907657 <6>[ 50.628045] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11473 12:51:07.917636 <6>[ 50.635716] printk: Suspending console(s) (use no_console_suspend to debug)
11474 12:51:12.159617 <3>[ 53.834933] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11475 12:51:12.160384 <3>[ 53.834964] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11476 12:51:12.161024 <3>[ 53.834996] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11477 12:51:12.161514 <3>[ 53.835021] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11478 12:51:12.161977 <3>[ 53.835432] PM: Some devices failed to suspend, or early wake event detected
11479 12:51:12.162425 <6>[ 54.108837] OOM killer enabled.
11480 12:51:12.162869 <6>[ 54.112238] Restarting tasks ... done.
11481 12:51:12.163395 <5>[ 54.118474] random: crng reseeded on system resumption
11482 12:51:12.163842 <6>[ 54.125122] PM: suspend exit
11483 12:51:12.164274 rtcwake: write error
11484 12:51:12.164745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11485 12:51:12.164922 rtcwake: assuming RTC uses UTC ...
11486 12:51:12.164977 rtcwake: wakeup from "mem" using rtc0 at Thu Jul 20 12:51:20 2023
11487 12:51:12.165032 <6>[ 54.155661] PM: suspend entry (deep)
11488 12:51:12.165108 <6>[ 54.159572] Filesystems sync: 0.000 seconds
11489 12:51:12.165164 <6>[ 54.164786] Freezing user space processes
11490 12:51:12.165250 <6>[ 54.170793] Freezing user space processes completed (elapsed 0.001 seconds)
11491 12:51:12.165319 <6>[ 54.178017] OOM killer disabled.
11492 12:51:12.165373 <6>[ 54.181503] Freezing remaining freezable tasks
11493 12:51:12.165449 <6>[ 54.187521] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11494 12:51:12.165564 <6>[ 54.195179] printk: Suspending console(s) (use no_console_suspend to debug)
11495 12:51:12.165852 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11497 12:51:14.930469 <3>[ 57.418924] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11498 12:51:14.940428 <3>[ 57.418948] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11499 12:51:14.950545 <3>[ 57.418982] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11500 12:51:14.956599 <3>[ 57.419004] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11501 12:51:14.963628 <3>[ 57.419505] PM: Some devices failed to suspend, or early wake event detected
11502 12:51:14.967121 <6>[ 57.692662] OOM killer enabled.
11503 12:51:14.975063 <6>[ 57.696061] Restarting tasks ... done.
11504 12:51:14.978230 <5>[ 57.701657] random: crng reseeded on system resumption
11505 12:51:14.982690 <6>[ 57.708320] PM: suspend exit
11506 12:51:14.985918 rtcwake: write error
11507 12:51:14.993865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11508 12:51:14.994771 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11510 12:51:14.997232 rtcwake: assuming RTC uses UTC ...
11511 12:51:15.003792 rtcwake: wakeup from "freeze" using rtc0 at Thu Jul 20 12:51:24 2023
11512 12:51:15.018433 <6>[ 57.740738] PM: suspend entry (s2idle)
11513 12:51:15.021662 <6>[ 57.744809] Filesystems sync: 0.000 seconds
11514 12:51:15.024869 <6>[ 57.750036] Freezing user space processes
11515 12:51:15.036908 <6>[ 57.756262] Freezing user space processes completed (elapsed 0.001 seconds)
11516 12:51:15.040577 <6>[ 57.763498] OOM killer disabled.
11517 12:51:15.043738 <6>[ 57.766984] Freezing remaining freezable tasks
11518 12:51:15.054009 <6>[ 57.772878] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11519 12:51:15.060462 <6>[ 57.780550] printk: Suspending console(s) (use no_console_suspend to debug)
11520 12:51:18.509817 <3>[ 61.002922] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11521 12:51:18.520112 <3>[ 61.002947] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11522 12:51:18.530233 <3>[ 61.002980] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11523 12:51:18.536688 <3>[ 61.003005] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11524 12:51:18.543531 <3>[ 61.003393] PM: Some devices failed to suspend, or early wake event detected
11525 12:51:18.546442 <6>[ 61.272765] OOM killer enabled.
11526 12:51:18.554883 <6>[ 61.276166] Restarting tasks ... done.
11527 12:51:18.558355 <5>[ 61.282258] random: crng reseeded on system resumption
11528 12:51:18.562799 <6>[ 61.289069] PM: suspend exit
11529 12:51:18.565438 rtcwake: write error
11530 12:51:18.573860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11531 12:51:18.574118 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11533 12:51:18.577268 rtcwake: assuming RTC uses UTC ...
11534 12:51:18.583692 rtcwake: wakeup from "freeze" using rtc0 at Thu Jul 20 12:51:27 2023
11535 12:51:18.596014 <6>[ 61.319342] PM: suspend entry (s2idle)
11536 12:51:18.599361 <6>[ 61.323398] Filesystems sync: 0.000 seconds
11537 12:51:18.606113 <6>[ 61.328666] Freezing user space processes
11538 12:51:18.612865 <6>[ 61.334793] Freezing user space processes completed (elapsed 0.001 seconds)
11539 12:51:18.616604 <6>[ 61.342014] OOM killer disabled.
11540 12:51:18.623138 <6>[ 61.345500] Freezing remaining freezable tasks
11541 12:51:18.629661 <6>[ 61.351508] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11542 12:51:18.639258 <6>[ 61.359169] printk: Suspending console(s) (use no_console_suspend to debug)
11543 12:51:22.097107 <3>[ 64.586928] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11544 12:51:22.106749 <3>[ 64.586953] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11545 12:51:22.117022 <3>[ 64.586986] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11546 12:51:22.123493 <3>[ 64.587008] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11547 12:51:22.130355 <3>[ 64.587513] PM: Some devices failed to suspend, or early wake event detected
11548 12:51:22.134004 <6>[ 64.860534] OOM killer enabled.
11549 12:51:22.142110 <6>[ 64.863933] Restarting tasks ... done.
11550 12:51:22.145304 <5>[ 64.869822] random: crng reseeded on system resumption
11551 12:51:22.149158 <6>[ 64.876390] PM: suspend exit
11552 12:51:22.152960 rtcwake: write error
11553 12:51:22.160485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11554 12:51:22.160798 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11556 12:51:22.164069 rtcwake: assuming RTC uses UTC ...
11557 12:51:22.170255 rtcwake: wakeup from "freeze" using rtc0 at Thu Jul 20 12:51:31 2023
11558 12:51:22.183108 <6>[ 64.906889] PM: suspend entry (s2idle)
11559 12:51:22.186232 <6>[ 64.910957] Filesystems sync: 0.000 seconds
11560 12:51:22.193420 <6>[ 64.916102] Freezing user space processes
11561 12:51:22.200030 <6>[ 64.922159] Freezing user space processes completed (elapsed 0.001 seconds)
11562 12:51:22.203286 <6>[ 64.929394] OOM killer disabled.
11563 12:51:22.210100 <6>[ 64.932877] Freezing remaining freezable tasks
11564 12:51:22.217034 <6>[ 64.938686] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11565 12:51:22.223812 <6>[ 64.946354] printk: Suspending console(s) (use no_console_suspend to debug)
11566 12:51:25.681063 <3>[ 68.170945] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11567 12:51:25.691109 <3>[ 68.170970] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11568 12:51:25.700978 <3>[ 68.171004] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11569 12:51:25.707998 <3>[ 68.171025] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11570 12:51:25.714446 <3>[ 68.171441] PM: Some devices failed to suspend, or early wake event detected
11571 12:51:25.717949 <6>[ 68.444714] OOM killer enabled.
11572 12:51:25.726357 <6>[ 68.448115] Restarting tasks ... done.
11573 12:51:25.729140 <5>[ 68.454276] random: crng reseeded on system resumption
11574 12:51:25.733653 <6>[ 68.461261] PM: suspend exit
11575 12:51:25.737405 rtcwake: write error
11576 12:51:25.745290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11577 12:51:25.745547 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11579 12:51:25.748523 rtcwake: assuming RTC uses UTC ...
11580 12:51:25.755611 rtcwake: wakeup from "freeze" using rtc0 at Thu Jul 20 12:51:34 2023
11581 12:51:25.768448 <6>[ 68.492331] PM: suspend entry (s2idle)
11582 12:51:25.771674 <6>[ 68.496423] Filesystems sync: 0.000 seconds
11583 12:51:25.778146 <6>[ 68.501611] Freezing user space processes
11584 12:51:25.784543 <6>[ 68.507528] Freezing user space processes completed (elapsed 0.001 seconds)
11585 12:51:25.788511 <6>[ 68.514753] OOM killer disabled.
11586 12:51:25.794947 <6>[ 68.518231] Freezing remaining freezable tasks
11587 12:51:25.801445 <6>[ 68.524169] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11588 12:51:25.811573 <6>[ 68.531828] printk: Suspending console(s) (use no_console_suspend to debug)
11589 12:51:29.264102 <3>[ 71.754946] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11590 12:51:29.274464 <3>[ 71.754972] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11591 12:51:29.284716 <3>[ 71.755009] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11592 12:51:29.291330 <3>[ 71.755042] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11593 12:51:29.297885 <3>[ 71.755529] PM: Some devices failed to suspend, or early wake event detected
11594 12:51:29.301114 <6>[ 72.028710] OOM killer enabled.
11595 12:51:29.309495 <6>[ 72.032111] Restarting tasks ... done.
11596 12:51:29.312818 <5>[ 72.038350] random: crng reseeded on system resumption
11597 12:51:29.317371 <6>[ 72.045173] PM: suspend exit
11598 12:51:29.320634 rtcwake: write error
11599 12:51:29.328426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11600 12:51:29.328713 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11602 12:51:29.331974 rtcwake: assuming RTC uses UTC ...
11603 12:51:29.338513 rtcwake: wakeup from "freeze" using rtc0 at Thu Jul 20 12:51:38 2023
11604 12:51:29.351374 <6>[ 72.075669] PM: suspend entry (s2idle)
11605 12:51:29.354543 <6>[ 72.079735] Filesystems sync: 0.000 seconds
11606 12:51:29.358053 <6>[ 72.084920] Freezing user space processes
11607 12:51:29.369772 <6>[ 72.090802] Freezing user space processes completed (elapsed 0.001 seconds)
11608 12:51:29.372974 <6>[ 72.098023] OOM killer disabled.
11609 12:51:29.376308 <6>[ 72.101508] Freezing remaining freezable tasks
11610 12:51:29.386538 <6>[ 72.107513] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11611 12:51:29.392929 <6>[ 72.115180] printk: Suspending console(s) (use no_console_suspend to debug)
11612 12:51:32.843371 <3>[ 75.338920] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11613 12:51:32.853044 <3>[ 75.338945] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11614 12:51:32.863438 <3>[ 75.338979] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11615 12:51:32.869926 <3>[ 75.339000] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11616 12:51:32.876593 <3>[ 75.339395] PM: Some devices failed to suspend, or early wake event detected
11617 12:51:32.880289 <6>[ 75.608039] OOM killer enabled.
11618 12:51:32.888121 <6>[ 75.611438] Restarting tasks ... done.
11619 12:51:32.891383 <5>[ 75.617175] random: crng reseeded on system resumption
11620 12:51:32.895964 <6>[ 75.623931] PM: suspend exit
11621 12:51:32.899228 rtcwake: write error
11622 12:51:32.906961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11623 12:51:32.907235 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11625 12:51:32.910150 rtcwake: assuming RTC uses UTC ...
11626 12:51:32.917056 rtcwake: wakeup from "freeze" using rtc0 at Thu Jul 20 12:51:41 2023
11627 12:51:32.929680 <6>[ 75.654613] PM: suspend entry (s2idle)
11628 12:51:32.932793 <6>[ 75.658668] Filesystems sync: 0.000 seconds
11629 12:51:32.936385 <6>[ 75.663833] Freezing user space processes
11630 12:51:32.948116 <6>[ 75.670020] Freezing user space processes completed (elapsed 0.001 seconds)
11631 12:51:32.951975 <6>[ 75.677285] OOM killer disabled.
11632 12:51:32.955117 <6>[ 75.680769] Freezing remaining freezable tasks
11633 12:51:32.965350 <6>[ 75.686729] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11634 12:51:32.971800 <6>[ 75.694382] printk: Suspending console(s) (use no_console_suspend to debug)
11635 12:51:36.427385 <3>[ 78.922925] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11636 12:51:36.436987 <3>[ 78.922949] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11637 12:51:36.447041 <3>[ 78.922977] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11638 12:51:36.454230 <3>[ 78.922998] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11639 12:51:36.460594 <3>[ 78.923384] PM: Some devices failed to suspend, or early wake event detected
11640 12:51:36.463918 <6>[ 79.192528] OOM killer enabled.
11641 12:51:36.472286 <6>[ 79.195928] Restarting tasks ... done.
11642 12:51:36.475399 <5>[ 79.201703] random: crng reseeded on system resumption
11643 12:51:36.479410 <6>[ 79.208030] PM: suspend exit
11644 12:51:36.482470 rtcwake: write error
11645 12:51:36.490851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11646 12:51:36.491112 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11648 12:51:36.493937 rtcwake: assuming RTC uses UTC ...
11649 12:51:36.500581 rtcwake: wakeup from "freeze" using rtc0 at Thu Jul 20 12:51:45 2023
11650 12:51:36.513124 <6>[ 79.238725] PM: suspend entry (s2idle)
11651 12:51:36.516436 <6>[ 79.242809] Filesystems sync: 0.000 seconds
11652 12:51:36.523359 <6>[ 79.247985] Freezing user space processes
11653 12:51:36.529905 <6>[ 79.254211] Freezing user space processes completed (elapsed 0.001 seconds)
11654 12:51:36.533062 <6>[ 79.261440] OOM killer disabled.
11655 12:51:36.540249 <6>[ 79.264929] Freezing remaining freezable tasks
11656 12:51:36.546579 <6>[ 79.270750] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11657 12:51:36.556173 <6>[ 79.278414] printk: Suspending console(s) (use no_console_suspend to debug)
11658 12:51:40.014401 <3>[ 82.506948] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11659 12:51:40.024469 <3>[ 82.506972] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11660 12:51:40.034514 <3>[ 82.507006] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11661 12:51:40.040929 <3>[ 82.507027] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11662 12:51:40.047761 <3>[ 82.507442] PM: Some devices failed to suspend, or early wake event detected
11663 12:51:40.050940 <6>[ 82.780032] OOM killer enabled.
11664 12:51:40.059527 <6>[ 82.783431] Restarting tasks ... done.
11665 12:51:40.062788 <5>[ 82.789357] random: crng reseeded on system resumption
11666 12:51:40.067317 <6>[ 82.796654] PM: suspend exit
11667 12:51:40.070471 rtcwake: write error
11668 12:51:40.078783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11669 12:51:40.079046 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11671 12:51:40.082446 rtcwake: assuming RTC uses UTC ...
11672 12:51:40.088831 rtcwake: wakeup from "freeze" using rtc0 at Thu Jul 20 12:51:49 2023
11673 12:51:40.101735 <6>[ 82.827407] PM: suspend entry (s2idle)
11674 12:51:40.104791 <6>[ 82.831495] Filesystems sync: 0.000 seconds
11675 12:51:40.111410 <6>[ 82.836721] Freezing user space processes
11676 12:51:40.117998 <6>[ 82.842798] Freezing user space processes completed (elapsed 0.001 seconds)
11677 12:51:40.121842 <6>[ 82.850027] OOM killer disabled.
11678 12:51:40.128018 <6>[ 82.853509] Freezing remaining freezable tasks
11679 12:51:40.134923 <6>[ 82.859401] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11680 12:51:40.144541 <6>[ 82.867059] printk: Suspending console(s) (use no_console_suspend to debug)
11681 12:51:43.598408 <3>[ 86.090937] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11682 12:51:43.608836 <3>[ 86.090961] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11683 12:51:43.618852 <3>[ 86.090987] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11684 12:51:43.625239 <3>[ 86.091009] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11685 12:51:43.632097 <3>[ 86.091382] PM: Some devices failed to suspend, or early wake event detected
11686 12:51:43.635470 <6>[ 86.364545] OOM killer enabled.
11687 12:51:43.643672 <6>[ 86.367943] Restarting tasks ... done.
11688 12:51:43.647027 <5>[ 86.373772] random: crng reseeded on system resumption
11689 12:51:43.650991 <6>[ 86.380324] PM: suspend exit
11690 12:51:43.654329 rtcwake: write error
11691 12:51:43.662186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11692 12:51:43.662513 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11694 12:51:43.665339 rtcwake: assuming RTC uses UTC ...
11695 12:51:43.671582 rtcwake: wakeup from "freeze" using rtc0 at Thu Jul 20 12:51:52 2023
11696 12:51:43.684777 <6>[ 86.410955] PM: suspend entry (s2idle)
11697 12:51:43.687789 <6>[ 86.415030] Filesystems sync: 0.000 seconds
11698 12:51:43.694619 <6>[ 86.420208] Freezing user space processes
11699 12:51:43.701643 <6>[ 86.426366] Freezing user space processes completed (elapsed 0.001 seconds)
11700 12:51:43.704594 <6>[ 86.433717] OOM killer disabled.
11701 12:51:43.711689 <6>[ 86.437213] Freezing remaining freezable tasks
11702 12:51:43.718121 <6>[ 86.442703] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11703 12:51:43.724593 <6>[ 86.450360] printk: Suspending console(s) (use no_console_suspend to debug)
11704 12:51:47.182333 <3>[ 89.674921] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11705 12:51:47.192030 <3>[ 89.674946] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11706 12:51:47.202267 <3>[ 89.674979] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11707 12:51:47.208794 <3>[ 89.675001] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11708 12:51:47.215824 <3>[ 89.675570] PM: Some devices failed to suspend, or early wake event detected
11709 12:51:47.219101 <6>[ 89.948734] OOM killer enabled.
11710 12:51:47.227439 <6>[ 89.952134] Restarting tasks ... done.
11711 12:51:47.231139 <5>[ 89.958428] random: crng reseeded on system resumption
11712 12:51:47.234992 <6>[ 89.965123] PM: suspend exit
11713 12:51:47.238741 rtcwake: write error
11714 12:51:47.246146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11715 12:51:47.246455 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11717 12:51:47.250060 rtcwake: assuming RTC uses UTC ...
11718 12:51:47.256105 rtcwake: wakeup from "freeze" using rtc0 at Thu Jul 20 12:51:56 2023
11719 12:51:47.268602 <6>[ 89.995475] PM: suspend entry (s2idle)
11720 12:51:47.272332 <6>[ 89.999565] Filesystems sync: 0.000 seconds
11721 12:51:47.278734 <6>[ 90.004735] Freezing user space processes
11722 12:51:47.285507 <6>[ 90.010745] Freezing user space processes completed (elapsed 0.001 seconds)
11723 12:51:47.288911 <6>[ 90.017969] OOM killer disabled.
11724 12:51:47.295565 <6>[ 90.021453] Freezing remaining freezable tasks
11725 12:51:47.302252 <6>[ 90.027337] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11726 12:51:47.317845 <6>[ 90.035000] printk: Suspending console(s) (use no_console_suspend to debug)
11727 12:51:50.761128 <3>[ 93.258921] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11728 12:51:50.771379 <3>[ 93.258947] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11729 12:51:50.781392 <3>[ 93.258979] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11730 12:51:50.788311 <3>[ 93.259000] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11731 12:51:50.794607 <3>[ 93.259431] PM: Some devices failed to suspend, or early wake event detected
11732 12:51:50.797729 <6>[ 93.528127] OOM killer enabled.
11733 12:51:50.805814 <6>[ 93.531525] Restarting tasks ... done.
11734 12:51:50.809148 <5>[ 93.537144] random: crng reseeded on system resumption
11735 12:51:50.813113 <6>[ 93.543804] PM: suspend exit
11736 12:51:50.816616 rtcwake: write error
11737 12:51:50.824866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11738 12:51:50.824955 + set +x
11739 12:51:50.825221 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11741 12:51:50.831248 <LAVA_SIGNAL_ENDRUN 0_sleep 11118892_1.5.2.3.1>
11742 12:51:50.831343 <LAVA_TEST_RUNNER EXIT>
11743 12:51:50.831611 Received signal: <ENDRUN> 0_sleep 11118892_1.5.2.3.1
11744 12:51:50.831716 Ending use of test pattern.
11745 12:51:50.831789 Ending test lava.0_sleep (11118892_1.5.2.3.1), duration 71.60
11747 12:51:50.832249 ok: lava_test_shell seems to have completed
11748 12:51:50.832611 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
11749 12:51:50.832816 end: 3.1 lava-test-shell (duration 00:01:12) [common]
11750 12:51:50.832939 end: 3 lava-test-retry (duration 00:01:12) [common]
11751 12:51:50.833067 start: 4 finalize (timeout 00:04:52) [common]
11752 12:51:50.833191 start: 4.1 power-off (timeout 00:00:30) [common]
11753 12:51:50.833406 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11754 12:51:50.944212 >> Command sent successfully.
11755 12:51:50.946663 Returned 0 in 0 seconds
11756 12:51:51.047130 end: 4.1 power-off (duration 00:00:00) [common]
11758 12:51:51.047472 start: 4.2 read-feedback (timeout 00:04:52) [common]
11759 12:51:51.047744 Listened to connection for namespace 'common' for up to 1s
11760 12:51:52.048663 Finalising connection for namespace 'common'
11761 12:51:52.048882 Disconnecting from shell: Finalise
11762 12:51:52.048959 / #
11763 12:51:52.149296 end: 4.2 read-feedback (duration 00:00:01) [common]
11764 12:51:52.149507 end: 4 finalize (duration 00:00:01) [common]
11765 12:51:52.149643 Cleaning after the job
11766 12:51:52.149773 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11118892/tftp-deploy-rgu9yvwm/ramdisk
11767 12:51:52.162432 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11118892/tftp-deploy-rgu9yvwm/kernel
11768 12:51:52.184274 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11118892/tftp-deploy-rgu9yvwm/dtb
11769 12:51:52.184493 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11118892/tftp-deploy-rgu9yvwm/modules
11770 12:51:52.191323 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11118892
11771 12:51:52.361928 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11118892
11772 12:51:52.362104 Job finished correctly