Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 31
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 66
- Warnings: 1
1 12:45:56.344022 lava-dispatcher, installed at version: 2023.05.1
2 12:45:56.344248 start: 0 validate
3 12:45:56.344377 Start time: 2023-07-20 12:45:56.344369+00:00 (UTC)
4 12:45:56.344505 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:45:56.344635 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:45:56.617698 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:45:56.618490 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.38-cip1-7-g5cff59cac977b%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:46:33.962912 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:46:33.963723 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.38-cip1-7-g5cff59cac977b%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:46:34.235084 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:46:34.235852 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.38-cip1-7-g5cff59cac977b%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:46:38.519826 validate duration: 42.18
14 12:46:38.520165 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:46:38.520309 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:46:38.520425 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:46:38.520591 Not decompressing ramdisk as can be used compressed.
18 12:46:38.520711 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 12:46:38.520807 saving as /var/lib/lava/dispatcher/tmp/11118918/tftp-deploy-4z2yt1i4/ramdisk/rootfs.cpio.gz
20 12:46:38.520891 total size: 26246609 (25MB)
21 12:46:38.789474 progress 0% (0MB)
22 12:46:38.797107 progress 5% (1MB)
23 12:46:38.804468 progress 10% (2MB)
24 12:46:38.811830 progress 15% (3MB)
25 12:46:38.819224 progress 20% (5MB)
26 12:46:38.826776 progress 25% (6MB)
27 12:46:38.834102 progress 30% (7MB)
28 12:46:38.841441 progress 35% (8MB)
29 12:46:38.848934 progress 40% (10MB)
30 12:46:38.856254 progress 45% (11MB)
31 12:46:38.863608 progress 50% (12MB)
32 12:46:38.870851 progress 55% (13MB)
33 12:46:38.878262 progress 60% (15MB)
34 12:46:38.885814 progress 65% (16MB)
35 12:46:38.893230 progress 70% (17MB)
36 12:46:38.900634 progress 75% (18MB)
37 12:46:38.907849 progress 80% (20MB)
38 12:46:38.914907 progress 85% (21MB)
39 12:46:38.922129 progress 90% (22MB)
40 12:46:38.929291 progress 95% (23MB)
41 12:46:38.936299 progress 100% (25MB)
42 12:46:38.936560 25MB downloaded in 0.42s (60.22MB/s)
43 12:46:38.936719 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:46:38.936955 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:46:38.937038 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:46:38.937119 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:46:38.937261 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.38-cip1-7-g5cff59cac977b/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:46:38.937333 saving as /var/lib/lava/dispatcher/tmp/11118918/tftp-deploy-4z2yt1i4/kernel/Image
50 12:46:38.937397 total size: 48564736 (46MB)
51 12:46:38.937457 No compression specified
52 12:46:38.938564 progress 0% (0MB)
53 12:46:38.952093 progress 5% (2MB)
54 12:46:38.965797 progress 10% (4MB)
55 12:46:38.979302 progress 15% (6MB)
56 12:46:38.992994 progress 20% (9MB)
57 12:46:39.005910 progress 25% (11MB)
58 12:46:39.018431 progress 30% (13MB)
59 12:46:39.031157 progress 35% (16MB)
60 12:46:39.043689 progress 40% (18MB)
61 12:46:39.056333 progress 45% (20MB)
62 12:46:39.069225 progress 50% (23MB)
63 12:46:39.081989 progress 55% (25MB)
64 12:46:39.094815 progress 60% (27MB)
65 12:46:39.107404 progress 65% (30MB)
66 12:46:39.120143 progress 70% (32MB)
67 12:46:39.132880 progress 75% (34MB)
68 12:46:39.145462 progress 80% (37MB)
69 12:46:39.157934 progress 85% (39MB)
70 12:46:39.170452 progress 90% (41MB)
71 12:46:39.182978 progress 95% (44MB)
72 12:46:39.195670 progress 100% (46MB)
73 12:46:39.195830 46MB downloaded in 0.26s (179.22MB/s)
74 12:46:39.195979 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:46:39.196204 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:46:39.196288 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:46:39.196413 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:46:39.196551 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.38-cip1-7-g5cff59cac977b/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:46:39.196619 saving as /var/lib/lava/dispatcher/tmp/11118918/tftp-deploy-4z2yt1i4/dtb/mt8192-asurada-spherion-r0.dtb
81 12:46:39.196678 total size: 46924 (0MB)
82 12:46:39.196736 No compression specified
83 12:46:39.197869 progress 69% (0MB)
84 12:46:39.198140 progress 100% (0MB)
85 12:46:39.198292 0MB downloaded in 0.00s (27.77MB/s)
86 12:46:39.198476 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:46:39.198693 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:46:39.198776 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:46:39.198857 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:46:39.198968 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.38-cip1-7-g5cff59cac977b/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:46:39.199034 saving as /var/lib/lava/dispatcher/tmp/11118918/tftp-deploy-4z2yt1i4/modules/modules.tar
93 12:46:39.199093 total size: 8543056 (8MB)
94 12:46:39.199150 Using unxz to decompress xz
95 12:46:39.203519 progress 0% (0MB)
96 12:46:39.225064 progress 5% (0MB)
97 12:46:39.250040 progress 10% (0MB)
98 12:46:39.274021 progress 15% (1MB)
99 12:46:39.301138 progress 20% (1MB)
100 12:46:39.326657 progress 25% (2MB)
101 12:46:39.351976 progress 30% (2MB)
102 12:46:39.377384 progress 35% (2MB)
103 12:46:39.402497 progress 40% (3MB)
104 12:46:39.428087 progress 45% (3MB)
105 12:46:39.452508 progress 50% (4MB)
106 12:46:39.477664 progress 55% (4MB)
107 12:46:39.502506 progress 60% (4MB)
108 12:46:39.527298 progress 65% (5MB)
109 12:46:39.556341 progress 70% (5MB)
110 12:46:39.587156 progress 75% (6MB)
111 12:46:39.611552 progress 80% (6MB)
112 12:46:39.635104 progress 85% (6MB)
113 12:46:39.658203 progress 90% (7MB)
114 12:46:39.682709 progress 95% (7MB)
115 12:46:39.707803 progress 100% (8MB)
116 12:46:39.713809 8MB downloaded in 0.51s (15.83MB/s)
117 12:46:39.714128 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:46:39.714389 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:46:39.714483 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:46:39.714576 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:46:39.714658 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:46:39.714743 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:46:39.714964 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v
125 12:46:39.715098 makedir: /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin
126 12:46:39.715202 makedir: /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/tests
127 12:46:39.715300 makedir: /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/results
128 12:46:39.715451 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-add-keys
129 12:46:39.715603 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-add-sources
130 12:46:39.715737 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-background-process-start
131 12:46:39.715867 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-background-process-stop
132 12:46:39.715996 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-common-functions
133 12:46:39.716122 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-echo-ipv4
134 12:46:39.716249 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-install-packages
135 12:46:39.716373 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-installed-packages
136 12:46:39.716496 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-os-build
137 12:46:39.716623 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-probe-channel
138 12:46:39.716747 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-probe-ip
139 12:46:39.716871 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-target-ip
140 12:46:39.716994 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-target-mac
141 12:46:39.717117 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-target-storage
142 12:46:39.717245 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-test-case
143 12:46:39.717371 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-test-event
144 12:46:39.717494 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-test-feedback
145 12:46:39.717617 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-test-raise
146 12:46:39.717744 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-test-reference
147 12:46:39.717868 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-test-runner
148 12:46:39.717994 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-test-set
149 12:46:39.718122 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-test-shell
150 12:46:39.718249 Updating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-install-packages (oe)
151 12:46:39.718405 Updating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/bin/lava-installed-packages (oe)
152 12:46:39.718527 Creating /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/environment
153 12:46:39.718629 LAVA metadata
154 12:46:39.718704 - LAVA_JOB_ID=11118918
155 12:46:39.718766 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:46:39.718869 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:46:39.718936 skipped lava-vland-overlay
158 12:46:39.719010 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:46:39.719089 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:46:39.719149 skipped lava-multinode-overlay
161 12:46:39.719223 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:46:39.719305 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:46:39.719404 Loading test definitions
164 12:46:39.719510 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:46:39.719582 Using /lava-11118918 at stage 0
166 12:46:39.719895 uuid=11118918_1.5.2.3.1 testdef=None
167 12:46:39.719982 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:46:39.720066 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:46:39.720574 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:46:39.720795 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:46:39.721509 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:46:39.721741 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:46:39.722342 runner path: /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 11118918_1.5.2.3.1
176 12:46:39.722499 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:46:39.722764 Creating lava-test-runner.conf files
179 12:46:39.722868 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11118918/lava-overlay-854lw75v/lava-11118918/0 for stage 0
180 12:46:39.722963 - 0_v4l2-compliance-mtk-vcodec-enc
181 12:46:39.723067 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:46:39.723151 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:46:39.729754 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:46:39.729859 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:46:39.729946 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:46:39.730032 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:46:39.730124 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:46:40.470598 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:46:40.471073 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:46:40.471238 extracting modules file /var/lib/lava/dispatcher/tmp/11118918/tftp-deploy-4z2yt1i4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11118918/extract-overlay-ramdisk-xy2fkmd0/ramdisk
191 12:46:40.719891 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:46:40.720061 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 12:46:40.720161 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11118918/compress-overlay-10wk8_e3/overlay-1.5.2.4.tar.gz to ramdisk
194 12:46:40.720230 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11118918/compress-overlay-10wk8_e3/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11118918/extract-overlay-ramdisk-xy2fkmd0/ramdisk
195 12:46:40.727541 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:46:40.727656 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 12:46:40.727746 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:46:40.727836 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 12:46:40.727916 Building ramdisk /var/lib/lava/dispatcher/tmp/11118918/extract-overlay-ramdisk-xy2fkmd0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11118918/extract-overlay-ramdisk-xy2fkmd0/ramdisk
200 12:46:41.364309 >> 226881 blocks
201 12:46:45.272693 rename /var/lib/lava/dispatcher/tmp/11118918/extract-overlay-ramdisk-xy2fkmd0/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11118918/tftp-deploy-4z2yt1i4/ramdisk/ramdisk.cpio.gz
202 12:46:45.273150 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 12:46:45.273270 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 12:46:45.273373 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 12:46:45.273483 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11118918/tftp-deploy-4z2yt1i4/kernel/Image'
206 12:46:58.186222 Returned 0 in 12 seconds
207 12:46:58.286883 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11118918/tftp-deploy-4z2yt1i4/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11118918/tftp-deploy-4z2yt1i4/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11118918/tftp-deploy-4z2yt1i4/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11118918/tftp-deploy-4z2yt1i4/kernel/image.itb
208 12:46:58.903124 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:46:58.903553 output: Created: Thu Jul 20 13:46:58 2023
210 12:46:58.903627 output: Image 0 (kernel-1)
211 12:46:58.903693 output: Description:
212 12:46:58.903757 output: Created: Thu Jul 20 13:46:58 2023
213 12:46:58.903822 output: Type: Kernel Image
214 12:46:58.903883 output: Compression: lzma compressed
215 12:46:58.903944 output: Data Size: 10808178 Bytes = 10554.86 KiB = 10.31 MiB
216 12:46:58.904002 output: Architecture: AArch64
217 12:46:58.904064 output: OS: Linux
218 12:46:58.904123 output: Load Address: 0x00000000
219 12:46:58.904181 output: Entry Point: 0x00000000
220 12:46:58.904239 output: Hash algo: crc32
221 12:46:58.904294 output: Hash value: 96f4d49d
222 12:46:58.904347 output: Image 1 (fdt-1)
223 12:46:58.904400 output: Description: mt8192-asurada-spherion-r0
224 12:46:58.904453 output: Created: Thu Jul 20 13:46:58 2023
225 12:46:58.904506 output: Type: Flat Device Tree
226 12:46:58.904559 output: Compression: uncompressed
227 12:46:58.904611 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 12:46:58.904664 output: Architecture: AArch64
229 12:46:58.904717 output: Hash algo: crc32
230 12:46:58.904771 output: Hash value: 1df858fa
231 12:46:58.904824 output: Image 2 (ramdisk-1)
232 12:46:58.904877 output: Description: unavailable
233 12:46:58.904932 output: Created: Thu Jul 20 13:46:58 2023
234 12:46:58.904986 output: Type: RAMDisk Image
235 12:46:58.905039 output: Compression: Unknown Compression
236 12:46:58.905092 output: Data Size: 39212006 Bytes = 38292.97 KiB = 37.40 MiB
237 12:46:58.905144 output: Architecture: AArch64
238 12:46:58.905197 output: OS: Linux
239 12:46:58.905249 output: Load Address: unavailable
240 12:46:58.905302 output: Entry Point: unavailable
241 12:46:58.905355 output: Hash algo: crc32
242 12:46:58.905407 output: Hash value: 9cf7a521
243 12:46:58.905459 output: Default Configuration: 'conf-1'
244 12:46:58.905512 output: Configuration 0 (conf-1)
245 12:46:58.905564 output: Description: mt8192-asurada-spherion-r0
246 12:46:58.905616 output: Kernel: kernel-1
247 12:46:58.905668 output: Init Ramdisk: ramdisk-1
248 12:46:58.905721 output: FDT: fdt-1
249 12:46:58.905772 output: Loadables: kernel-1
250 12:46:58.905824 output:
251 12:46:58.906026 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 12:46:58.906129 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 12:46:58.906235 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 12:46:58.906328 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 12:46:58.906406 No LXC device requested
256 12:46:58.906484 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:46:58.906572 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 12:46:58.906649 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:46:58.906715 Checking files for TFTP limit of 4294967296 bytes.
260 12:46:58.907238 end: 1 tftp-deploy (duration 00:00:20) [common]
261 12:46:58.907341 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:46:58.907480 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:46:58.907605 substitutions:
264 12:46:58.907671 - {DTB}: 11118918/tftp-deploy-4z2yt1i4/dtb/mt8192-asurada-spherion-r0.dtb
265 12:46:58.907735 - {INITRD}: 11118918/tftp-deploy-4z2yt1i4/ramdisk/ramdisk.cpio.gz
266 12:46:58.907804 - {KERNEL}: 11118918/tftp-deploy-4z2yt1i4/kernel/Image
267 12:46:58.907866 - {LAVA_MAC}: None
268 12:46:58.907922 - {PRESEED_CONFIG}: None
269 12:46:58.907978 - {PRESEED_LOCAL}: None
270 12:46:58.908033 - {RAMDISK}: 11118918/tftp-deploy-4z2yt1i4/ramdisk/ramdisk.cpio.gz
271 12:46:58.908087 - {ROOT_PART}: None
272 12:46:58.908141 - {ROOT}: None
273 12:46:58.908195 - {SERVER_IP}: 192.168.201.1
274 12:46:58.908249 - {TEE}: None
275 12:46:58.908302 Parsed boot commands:
276 12:46:58.908356 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:46:58.908538 Parsed boot commands: tftpboot 192.168.201.1 11118918/tftp-deploy-4z2yt1i4/kernel/image.itb 11118918/tftp-deploy-4z2yt1i4/kernel/cmdline
278 12:46:58.908630 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:46:58.908716 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:46:58.908810 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:46:58.908897 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:46:58.908969 Not connected, no need to disconnect.
283 12:46:58.909042 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:46:58.909122 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:46:58.909187 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
286 12:46:58.913188 Setting prompt string to ['lava-test: # ']
287 12:46:58.913552 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:46:58.913665 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:46:58.913762 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:46:58.913857 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:46:58.914056 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 12:47:04.060379 >> Command sent successfully.
293 12:47:04.070815 Returned 0 in 5 seconds
294 12:47:04.172099 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:47:04.174664 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:47:04.175192 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:47:04.175766 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:47:04.176130 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:47:04.176494 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:47:04.177689 [Enter `^Ec?' for help]
302 12:47:04.334548
303 12:47:04.335083
304 12:47:04.335462 F0: 102B 0000
305 12:47:04.335792
306 12:47:04.336100 F3: 1001 0000 [0200]
307 12:47:04.337096
308 12:47:04.337520 F3: 1001 0000
309 12:47:04.337896
310 12:47:04.338436 F7: 102D 0000
311 12:47:04.338774
312 12:47:04.341200 F1: 0000 0000
313 12:47:04.341737
314 12:47:04.342083 V0: 0000 0000 [0001]
315 12:47:04.342423
316 12:47:04.344372 00: 0007 8000
317 12:47:04.344821
318 12:47:04.345161 01: 0000 0000
319 12:47:04.345488
320 12:47:04.347441 BP: 0C00 0209 [0000]
321 12:47:04.347873
322 12:47:04.348213 G0: 1182 0000
323 12:47:04.348533
324 12:47:04.350778 EC: 0000 0021 [4000]
325 12:47:04.351207
326 12:47:04.351610 S7: 0000 0000 [0000]
327 12:47:04.351935
328 12:47:04.354516 CC: 0000 0000 [0001]
329 12:47:04.354948
330 12:47:04.355358 T0: 0000 0040 [010F]
331 12:47:04.355749
332 12:47:04.356070 Jump to BL
333 12:47:04.356370
334 12:47:04.381260
335 12:47:04.381802
336 12:47:04.382153
337 12:47:04.388576 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:47:04.392142 ARM64: Exception handlers installed.
339 12:47:04.396134 ARM64: Testing exception
340 12:47:04.398870 ARM64: Done test exception
341 12:47:04.406246 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:47:04.415972 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:47:04.422990 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:47:04.432652 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:47:04.439855 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:47:04.446478 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:47:04.458159 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:47:04.464866 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:47:04.483953 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:47:04.487499 WDT: Last reset was cold boot
351 12:47:04.491216 SPI1(PAD0) initialized at 2873684 Hz
352 12:47:04.494206 SPI5(PAD0) initialized at 992727 Hz
353 12:47:04.497420 VBOOT: Loading verstage.
354 12:47:04.503914 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:47:04.507441 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:47:04.511071 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:47:04.513775 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:47:04.521523 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:47:04.528423 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:47:04.539430 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 12:47:04.540028
362 12:47:04.540405
363 12:47:04.549214 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:47:04.552147 ARM64: Exception handlers installed.
365 12:47:04.556056 ARM64: Testing exception
366 12:47:04.556640 ARM64: Done test exception
367 12:47:04.562342 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:47:04.566255 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:47:04.580046 Probing TPM: . done!
370 12:47:04.580609 TPM ready after 0 ms
371 12:47:04.586623 Connected to device vid:did:rid of 1ae0:0028:00
372 12:47:04.635939 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 12:47:04.636517 Initialized TPM device CR50 revision 0
374 12:47:04.647508 tlcl_send_startup: Startup return code is 0
375 12:47:04.647984 TPM: setup succeeded
376 12:47:04.659043 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:47:04.668355 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:47:04.680576 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:47:04.689301 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:47:04.692608 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:47:04.696312 in-header: 03 07 00 00 08 00 00 00
382 12:47:04.699541 in-data: aa e4 47 04 13 02 00 00
383 12:47:04.703509 Chrome EC: UHEPI supported
384 12:47:04.709998 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:47:04.714290 in-header: 03 9d 00 00 08 00 00 00
386 12:47:04.717596 in-data: 10 20 20 08 00 00 00 00
387 12:47:04.718071 Phase 1
388 12:47:04.721002 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:47:04.728607 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:47:04.736087 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:47:04.736647 Recovery requested (1009000e)
392 12:47:04.744153 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:47:04.749824 tlcl_extend: response is 0
394 12:47:04.757484 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:47:04.763224 tlcl_extend: response is 0
396 12:47:04.769646 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:47:04.790610 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 12:47:04.798384 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:47:04.798912
400 12:47:04.799252
401 12:47:04.808910 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:47:04.809426 ARM64: Exception handlers installed.
403 12:47:04.812718 ARM64: Testing exception
404 12:47:04.815929 ARM64: Done test exception
405 12:47:04.836515 pmic_efuse_setting: Set efuses in 11 msecs
406 12:47:04.840744 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:47:04.843940 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:47:04.851239 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:47:04.855117 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:47:04.858786 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:47:04.866338 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:47:04.870399 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:47:04.873640 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:47:04.877771 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:47:04.884352 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:47:04.887833 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:47:04.894224 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:47:04.897764 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:47:04.901271 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:47:04.907539 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:47:04.914485 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:47:04.921005 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:47:04.924795 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:47:04.930991 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:47:04.938414 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:47:04.941800 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:47:04.949197 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:47:04.952967 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:47:04.959702 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:47:04.963108 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:47:04.970233 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:47:04.976796 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:47:04.980094 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:47:04.984049 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:47:04.990899 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:47:04.994402 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:47:05.001661 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:47:05.005081 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:47:05.008489 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:47:05.015824 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:47:05.020024 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:47:05.024363 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:47:05.030342 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:47:05.033818 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:47:05.040618 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:47:05.043452 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:47:05.046685 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:47:05.053686 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:47:05.056823 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:47:05.060568 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:47:05.066972 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:47:05.070448 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:47:05.073926 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:47:05.077415 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:47:05.083943 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:47:05.087073 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:47:05.090543 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:47:05.097492 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:47:05.107479 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:47:05.110642 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:47:05.120453 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:47:05.127194 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:47:05.133950 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:47:05.137443 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:47:05.140182 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:47:05.148512 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x29
467 12:47:05.155073 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:47:05.158210 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 12:47:05.162183 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:47:05.173282 [RTC]rtc_get_frequency_meter,154: input=15, output=794
471 12:47:05.176272 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 12:47:05.183313 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 12:47:05.186811 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 12:47:05.189899 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 12:47:05.192945 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 12:47:05.196445 ADC[4]: Raw value=897780 ID=7
477 12:47:05.199955 ADC[3]: Raw value=212700 ID=1
478 12:47:05.203208 RAM Code: 0x71
479 12:47:05.207413 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 12:47:05.210796 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 12:47:05.218031 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 12:47:05.225395 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 12:47:05.229368 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 12:47:05.233233 in-header: 03 07 00 00 08 00 00 00
485 12:47:05.237398 in-data: aa e4 47 04 13 02 00 00
486 12:47:05.240876 Chrome EC: UHEPI supported
487 12:47:05.248022 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 12:47:05.251627 in-header: 03 95 00 00 08 00 00 00
489 12:47:05.252062 in-data: 18 20 20 08 00 00 00 00
490 12:47:05.255283 MRC: failed to locate region type 0.
491 12:47:05.262957 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 12:47:05.266324 DRAM-K: Running full calibration
493 12:47:05.274185 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 12:47:05.274717 header.status = 0x0
495 12:47:05.277659 header.version = 0x6 (expected: 0x6)
496 12:47:05.281567 header.size = 0xd00 (expected: 0xd00)
497 12:47:05.281999 header.flags = 0x0
498 12:47:05.288240 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 12:47:05.306788 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
500 12:47:05.313739 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 12:47:05.316781 dram_init: ddr_geometry: 2
502 12:47:05.317206 [EMI] MDL number = 2
503 12:47:05.320187 [EMI] Get MDL freq = 0
504 12:47:05.323888 dram_init: ddr_type: 0
505 12:47:05.324309 is_discrete_lpddr4: 1
506 12:47:05.327796 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 12:47:05.328400
508 12:47:05.328762
509 12:47:05.331324 [Bian_co] ETT version 0.0.0.1
510 12:47:05.335013 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 12:47:05.335498
512 12:47:05.338575 dramc_set_vcore_voltage set vcore to 650000
513 12:47:05.342503 Read voltage for 800, 4
514 12:47:05.342937 Vio18 = 0
515 12:47:05.343286 Vcore = 650000
516 12:47:05.346060 Vdram = 0
517 12:47:05.346596 Vddq = 0
518 12:47:05.346947 Vmddr = 0
519 12:47:05.349462 dram_init: config_dvfs: 1
520 12:47:05.352773 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 12:47:05.359554 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 12:47:05.362382 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 12:47:05.365712 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 12:47:05.369493 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 12:47:05.372429 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 12:47:05.376513 MEM_TYPE=3, freq_sel=18
527 12:47:05.379095 sv_algorithm_assistance_LP4_1600
528 12:47:05.382609 ============ PULL DRAM RESETB DOWN ============
529 12:47:05.389576 ========== PULL DRAM RESETB DOWN end =========
530 12:47:05.392435 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 12:47:05.395939 ===================================
532 12:47:05.399355 LPDDR4 DRAM CONFIGURATION
533 12:47:05.402558 ===================================
534 12:47:05.403063 EX_ROW_EN[0] = 0x0
535 12:47:05.405911 EX_ROW_EN[1] = 0x0
536 12:47:05.406347 LP4Y_EN = 0x0
537 12:47:05.409226 WORK_FSP = 0x0
538 12:47:05.409662 WL = 0x2
539 12:47:05.412422 RL = 0x2
540 12:47:05.412856 BL = 0x2
541 12:47:05.416041 RPST = 0x0
542 12:47:05.416552 RD_PRE = 0x0
543 12:47:05.419435 WR_PRE = 0x1
544 12:47:05.419864 WR_PST = 0x0
545 12:47:05.422520 DBI_WR = 0x0
546 12:47:05.422942 DBI_RD = 0x0
547 12:47:05.426090 OTF = 0x1
548 12:47:05.429414 ===================================
549 12:47:05.432521 ===================================
550 12:47:05.432941 ANA top config
551 12:47:05.436029 ===================================
552 12:47:05.439329 DLL_ASYNC_EN = 0
553 12:47:05.442633 ALL_SLAVE_EN = 1
554 12:47:05.445793 NEW_RANK_MODE = 1
555 12:47:05.446268 DLL_IDLE_MODE = 1
556 12:47:05.449062 LP45_APHY_COMB_EN = 1
557 12:47:05.452827 TX_ODT_DIS = 1
558 12:47:05.455737 NEW_8X_MODE = 1
559 12:47:05.459496 ===================================
560 12:47:05.462872 ===================================
561 12:47:05.465701 data_rate = 1600
562 12:47:05.466121 CKR = 1
563 12:47:05.469243 DQ_P2S_RATIO = 8
564 12:47:05.472539 ===================================
565 12:47:05.475865 CA_P2S_RATIO = 8
566 12:47:05.479125 DQ_CA_OPEN = 0
567 12:47:05.482536 DQ_SEMI_OPEN = 0
568 12:47:05.486004 CA_SEMI_OPEN = 0
569 12:47:05.486422 CA_FULL_RATE = 0
570 12:47:05.489648 DQ_CKDIV4_EN = 1
571 12:47:05.493039 CA_CKDIV4_EN = 1
572 12:47:05.495930 CA_PREDIV_EN = 0
573 12:47:05.499238 PH8_DLY = 0
574 12:47:05.502835 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 12:47:05.503314 DQ_AAMCK_DIV = 4
576 12:47:05.505956 CA_AAMCK_DIV = 4
577 12:47:05.509525 CA_ADMCK_DIV = 4
578 12:47:05.512780 DQ_TRACK_CA_EN = 0
579 12:47:05.516297 CA_PICK = 800
580 12:47:05.519150 CA_MCKIO = 800
581 12:47:05.519624 MCKIO_SEMI = 0
582 12:47:05.522996 PLL_FREQ = 3068
583 12:47:05.525855 DQ_UI_PI_RATIO = 32
584 12:47:05.529236 CA_UI_PI_RATIO = 0
585 12:47:05.532686 ===================================
586 12:47:05.536157 ===================================
587 12:47:05.539511 memory_type:LPDDR4
588 12:47:05.539932 GP_NUM : 10
589 12:47:05.543235 SRAM_EN : 1
590 12:47:05.546612 MD32_EN : 0
591 12:47:05.547033 ===================================
592 12:47:05.549848 [ANA_INIT] >>>>>>>>>>>>>>
593 12:47:05.552637 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 12:47:05.556107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 12:47:05.559732 ===================================
596 12:47:05.562906 data_rate = 1600,PCW = 0X7600
597 12:47:05.565833 ===================================
598 12:47:05.569658 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 12:47:05.576212 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 12:47:05.579814 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 12:47:05.586328 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 12:47:05.590197 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 12:47:05.593783 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 12:47:05.594207 [ANA_INIT] flow start
605 12:47:05.597214 [ANA_INIT] PLL >>>>>>>>
606 12:47:05.597719 [ANA_INIT] PLL <<<<<<<<
607 12:47:05.600463 [ANA_INIT] MIDPI >>>>>>>>
608 12:47:05.604753 [ANA_INIT] MIDPI <<<<<<<<
609 12:47:05.605177 [ANA_INIT] DLL >>>>>>>>
610 12:47:05.607942 [ANA_INIT] flow end
611 12:47:05.611825 ============ LP4 DIFF to SE enter ============
612 12:47:05.615540 ============ LP4 DIFF to SE exit ============
613 12:47:05.619688 [ANA_INIT] <<<<<<<<<<<<<
614 12:47:05.620110 [Flow] Enable top DCM control >>>>>
615 12:47:05.623179 [Flow] Enable top DCM control <<<<<
616 12:47:05.626819 Enable DLL master slave shuffle
617 12:47:05.633958 ==============================================================
618 12:47:05.634386 Gating Mode config
619 12:47:05.641479 ==============================================================
620 12:47:05.641908 Config description:
621 12:47:05.652261 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 12:47:05.660152 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 12:47:05.664199 SELPH_MODE 0: By rank 1: By Phase
624 12:47:05.667715 ==============================================================
625 12:47:05.671815 GAT_TRACK_EN = 1
626 12:47:05.675254 RX_GATING_MODE = 2
627 12:47:05.678896 RX_GATING_TRACK_MODE = 2
628 12:47:05.682343 SELPH_MODE = 1
629 12:47:05.682769 PICG_EARLY_EN = 1
630 12:47:05.686088 VALID_LAT_VALUE = 1
631 12:47:05.693729 ==============================================================
632 12:47:05.698037 Enter into Gating configuration >>>>
633 12:47:05.698461 Exit from Gating configuration <<<<
634 12:47:05.701347 Enter into DVFS_PRE_config >>>>>
635 12:47:05.712793 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 12:47:05.716397 Exit from DVFS_PRE_config <<<<<
637 12:47:05.720398 Enter into PICG configuration >>>>
638 12:47:05.724043 Exit from PICG configuration <<<<
639 12:47:05.724489 [RX_INPUT] configuration >>>>>
640 12:47:05.728033 [RX_INPUT] configuration <<<<<
641 12:47:05.735456 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 12:47:05.739013 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 12:47:05.746262 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 12:47:05.749685 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 12:47:05.757097 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 12:47:05.764826 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 12:47:05.768783 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 12:47:05.772941 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 12:47:05.776418 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 12:47:05.779791 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 12:47:05.783857 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 12:47:05.787143 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 12:47:05.790639 ===================================
654 12:47:05.794492 LPDDR4 DRAM CONFIGURATION
655 12:47:05.798627 ===================================
656 12:47:05.799052 EX_ROW_EN[0] = 0x0
657 12:47:05.801834 EX_ROW_EN[1] = 0x0
658 12:47:05.802291 LP4Y_EN = 0x0
659 12:47:05.805590 WORK_FSP = 0x0
660 12:47:05.805992 WL = 0x2
661 12:47:05.809485 RL = 0x2
662 12:47:05.809935 BL = 0x2
663 12:47:05.813153 RPST = 0x0
664 12:47:05.813969 RD_PRE = 0x0
665 12:47:05.814470 WR_PRE = 0x1
666 12:47:05.816931 WR_PST = 0x0
667 12:47:05.817351 DBI_WR = 0x0
668 12:47:05.820805 DBI_RD = 0x0
669 12:47:05.821279 OTF = 0x1
670 12:47:05.824546 ===================================
671 12:47:05.827963 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 12:47:05.832237 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 12:47:05.839262 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 12:47:05.843262 ===================================
675 12:47:05.843739 LPDDR4 DRAM CONFIGURATION
676 12:47:05.846887 ===================================
677 12:47:05.850180 EX_ROW_EN[0] = 0x10
678 12:47:05.850601 EX_ROW_EN[1] = 0x0
679 12:47:05.854015 LP4Y_EN = 0x0
680 12:47:05.854439 WORK_FSP = 0x0
681 12:47:05.857322 WL = 0x2
682 12:47:05.857744 RL = 0x2
683 12:47:05.861645 BL = 0x2
684 12:47:05.862068 RPST = 0x0
685 12:47:05.862491 RD_PRE = 0x0
686 12:47:05.864639 WR_PRE = 0x1
687 12:47:05.865062 WR_PST = 0x0
688 12:47:05.868860 DBI_WR = 0x0
689 12:47:05.869282 DBI_RD = 0x0
690 12:47:05.872161 OTF = 0x1
691 12:47:05.876218 ===================================
692 12:47:05.879099 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 12:47:05.885319 nWR fixed to 40
694 12:47:05.888739 [ModeRegInit_LP4] CH0 RK0
695 12:47:05.889158 [ModeRegInit_LP4] CH0 RK1
696 12:47:05.892426 [ModeRegInit_LP4] CH1 RK0
697 12:47:05.892849 [ModeRegInit_LP4] CH1 RK1
698 12:47:05.896367 match AC timing 13
699 12:47:05.900124 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 12:47:05.903431 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 12:47:05.907131 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 12:47:05.914634 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 12:47:05.918070 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 12:47:05.918496 [EMI DOE] emi_dcm 0
705 12:47:05.925937 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 12:47:05.926427 ==
707 12:47:05.929033 Dram Type= 6, Freq= 0, CH_0, rank 0
708 12:47:05.933354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 12:47:05.933780 ==
710 12:47:05.937432 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 12:47:05.943363 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 12:47:05.952016 [CA 0] Center 38 (7~69) winsize 63
713 12:47:05.955521 [CA 1] Center 37 (7~68) winsize 62
714 12:47:05.958604 [CA 2] Center 35 (5~66) winsize 62
715 12:47:05.961955 [CA 3] Center 35 (4~66) winsize 63
716 12:47:05.965337 [CA 4] Center 34 (4~65) winsize 62
717 12:47:05.968648 [CA 5] Center 34 (4~64) winsize 61
718 12:47:05.969091
719 12:47:05.971694 [CmdBusTrainingLP45] Vref(ca) range 1: 30
720 12:47:05.972141
721 12:47:05.975693 [CATrainingPosCal] consider 1 rank data
722 12:47:05.978421 u2DelayCellTimex100 = 270/100 ps
723 12:47:05.981838 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 12:47:05.985401 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 12:47:05.991677 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 12:47:05.995262 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
727 12:47:05.998562 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 12:47:06.001906 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
729 12:47:06.002354
730 12:47:06.005091 CA PerBit enable=1, Macro0, CA PI delay=34
731 12:47:06.005537
732 12:47:06.008910 [CBTSetCACLKResult] CA Dly = 34
733 12:47:06.009379 CS Dly: 6 (0~37)
734 12:47:06.009835 ==
735 12:47:06.011934 Dram Type= 6, Freq= 0, CH_0, rank 1
736 12:47:06.019040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 12:47:06.019536 ==
738 12:47:06.021883 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 12:47:06.028652 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 12:47:06.038558 [CA 0] Center 38 (7~69) winsize 63
741 12:47:06.042146 [CA 1] Center 37 (7~68) winsize 62
742 12:47:06.045058 [CA 2] Center 35 (5~66) winsize 62
743 12:47:06.048602 [CA 3] Center 35 (5~66) winsize 62
744 12:47:06.051841 [CA 4] Center 34 (4~65) winsize 62
745 12:47:06.055293 [CA 5] Center 34 (3~65) winsize 63
746 12:47:06.055770
747 12:47:06.058739 [CmdBusTrainingLP45] Vref(ca) range 1: 34
748 12:47:06.059185
749 12:47:06.061543 [CATrainingPosCal] consider 2 rank data
750 12:47:06.064911 u2DelayCellTimex100 = 270/100 ps
751 12:47:06.069449 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 12:47:06.072227 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 12:47:06.078611 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 12:47:06.081795 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 12:47:06.084900 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 12:47:06.088264 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
757 12:47:06.088711
758 12:47:06.091615 CA PerBit enable=1, Macro0, CA PI delay=34
759 12:47:06.092103
760 12:47:06.095187 [CBTSetCACLKResult] CA Dly = 34
761 12:47:06.095827 CS Dly: 6 (0~38)
762 12:47:06.096368
763 12:47:06.098512 ----->DramcWriteLeveling(PI) begin...
764 12:47:06.102013 ==
765 12:47:06.102573 Dram Type= 6, Freq= 0, CH_0, rank 0
766 12:47:06.108423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 12:47:06.108956 ==
768 12:47:06.111652 Write leveling (Byte 0): 35 => 35
769 12:47:06.114825 Write leveling (Byte 1): 30 => 30
770 12:47:06.118298 DramcWriteLeveling(PI) end<-----
771 12:47:06.118793
772 12:47:06.119241 ==
773 12:47:06.121927 Dram Type= 6, Freq= 0, CH_0, rank 0
774 12:47:06.124828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 12:47:06.125358 ==
776 12:47:06.128553 [Gating] SW mode calibration
777 12:47:06.134977 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 12:47:06.138619 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 12:47:06.145002 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 12:47:06.148862 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 12:47:06.151913 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
782 12:47:06.158423 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
783 12:47:06.161831 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 12:47:06.165122 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 12:47:06.171611 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 12:47:06.175554 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 12:47:06.179846 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 12:47:06.182683 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 12:47:06.189970 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:47:06.193226 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:47:06.196621 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:47:06.200148 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:47:06.207166 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:47:06.210775 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:47:06.214201 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:47:06.217654 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:47:06.224364 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
798 12:47:06.227311 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:47:06.230658 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:47:06.237463 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:47:06.240757 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:47:06.244182 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:47:06.250822 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:47:06.253674 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:47:06.257308 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:47:06.263922 0 9 12 | B1->B0 | 2626 2e2e | 0 0 | (0 0) (0 0)
807 12:47:06.266988 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 12:47:06.270755 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 12:47:06.277685 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 12:47:06.280533 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 12:47:06.284166 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 12:47:06.291042 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 12:47:06.294283 0 10 8 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
814 12:47:06.297222 0 10 12 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (1 1)
815 12:47:06.301066 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 12:47:06.307299 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 12:47:06.310626 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 12:47:06.314178 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 12:47:06.321081 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 12:47:06.323861 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 12:47:06.327307 0 11 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
822 12:47:06.334232 0 11 12 | B1->B0 | 3737 3d3d | 1 0 | (0 0) (0 0)
823 12:47:06.337591 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 12:47:06.340901 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 12:47:06.347546 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 12:47:06.350432 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 12:47:06.354271 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 12:47:06.360479 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 12:47:06.363683 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 12:47:06.367297 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 12:47:06.373666 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 12:47:06.377693 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 12:47:06.380546 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 12:47:06.387473 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 12:47:06.390407 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 12:47:06.393919 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 12:47:06.400115 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:47:06.403598 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:47:06.406947 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:47:06.413316 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:47:06.417095 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:47:06.420434 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:47:06.426748 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:47:06.430244 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:47:06.433434 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
846 12:47:06.436955 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
847 12:47:06.440256 Total UI for P1: 0, mck2ui 16
848 12:47:06.443826 best dqsien dly found for B0: ( 0, 14, 8)
849 12:47:06.450623 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 12:47:06.453537 Total UI for P1: 0, mck2ui 16
851 12:47:06.457244 best dqsien dly found for B1: ( 0, 14, 12)
852 12:47:06.460511 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
853 12:47:06.463368 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
854 12:47:06.463844
855 12:47:06.467276 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
856 12:47:06.470725 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
857 12:47:06.473525 [Gating] SW calibration Done
858 12:47:06.473951 ==
859 12:47:06.476902 Dram Type= 6, Freq= 0, CH_0, rank 0
860 12:47:06.480184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 12:47:06.480808 ==
862 12:47:06.483304 RX Vref Scan: 0
863 12:47:06.483881
864 12:47:06.484346 RX Vref 0 -> 0, step: 1
865 12:47:06.486965
866 12:47:06.487641 RX Delay -130 -> 252, step: 16
867 12:47:06.493797 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
868 12:47:06.496708 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
869 12:47:06.500265 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 12:47:06.503503 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
871 12:47:06.507090 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
872 12:47:06.513404 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
873 12:47:06.516770 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 12:47:06.519999 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 12:47:06.523561 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
876 12:47:06.526986 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
877 12:47:06.533667 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 12:47:06.536846 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 12:47:06.539954 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 12:47:06.543497 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 12:47:06.546752 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
882 12:47:06.553707 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 12:47:06.554162 ==
884 12:47:06.556732 Dram Type= 6, Freq= 0, CH_0, rank 0
885 12:47:06.560362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 12:47:06.560851 ==
887 12:47:06.561314 DQS Delay:
888 12:47:06.563518 DQS0 = 0, DQS1 = 0
889 12:47:06.564055 DQM Delay:
890 12:47:06.566846 DQM0 = 81, DQM1 = 70
891 12:47:06.567310 DQ Delay:
892 12:47:06.570235 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
893 12:47:06.573389 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
894 12:47:06.576648 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
895 12:47:06.580077 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
896 12:47:06.580548
897 12:47:06.581011
898 12:47:06.581463 ==
899 12:47:06.584081 Dram Type= 6, Freq= 0, CH_0, rank 0
900 12:47:06.587351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 12:47:06.587847 ==
902 12:47:06.588314
903 12:47:06.588754
904 12:47:06.590627 TX Vref Scan disable
905 12:47:06.594221 == TX Byte 0 ==
906 12:47:06.597774 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
907 12:47:06.601008 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
908 12:47:06.604587 == TX Byte 1 ==
909 12:47:06.607326 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
910 12:47:06.610665 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
911 12:47:06.611132 ==
912 12:47:06.613887 Dram Type= 6, Freq= 0, CH_0, rank 0
913 12:47:06.617514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 12:47:06.617976 ==
915 12:47:06.632568 TX Vref=22, minBit 5, minWin=26, winSum=432
916 12:47:06.635267 TX Vref=24, minBit 5, minWin=26, winSum=439
917 12:47:06.638749 TX Vref=26, minBit 3, minWin=27, winSum=441
918 12:47:06.642050 TX Vref=28, minBit 11, minWin=27, winSum=445
919 12:47:06.645618 TX Vref=30, minBit 10, minWin=27, winSum=442
920 12:47:06.651998 TX Vref=32, minBit 10, minWin=26, winSum=440
921 12:47:06.655433 [TxChooseVref] Worse bit 11, Min win 27, Win sum 445, Final Vref 28
922 12:47:06.655899
923 12:47:06.658847 Final TX Range 1 Vref 28
924 12:47:06.659325
925 12:47:06.659839 ==
926 12:47:06.662149 Dram Type= 6, Freq= 0, CH_0, rank 0
927 12:47:06.665739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 12:47:06.668936 ==
929 12:47:06.669505
930 12:47:06.670064
931 12:47:06.670443 TX Vref Scan disable
932 12:47:06.672624 == TX Byte 0 ==
933 12:47:06.675733 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
934 12:47:06.679436 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
935 12:47:06.682480 == TX Byte 1 ==
936 12:47:06.685905 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
937 12:47:06.689005 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
938 12:47:06.692574
939 12:47:06.693023 [DATLAT]
940 12:47:06.693389 Freq=800, CH0 RK0
941 12:47:06.693724
942 12:47:06.695857 DATLAT Default: 0xa
943 12:47:06.696318 0, 0xFFFF, sum = 0
944 12:47:06.699065 1, 0xFFFF, sum = 0
945 12:47:06.699634 2, 0xFFFF, sum = 0
946 12:47:06.702393 3, 0xFFFF, sum = 0
947 12:47:06.702920 4, 0xFFFF, sum = 0
948 12:47:06.705809 5, 0xFFFF, sum = 0
949 12:47:06.706261 6, 0xFFFF, sum = 0
950 12:47:06.709212 7, 0xFFFF, sum = 0
951 12:47:06.712276 8, 0xFFFF, sum = 0
952 12:47:06.712745 9, 0x0, sum = 1
953 12:47:06.713237 10, 0x0, sum = 2
954 12:47:06.716032 11, 0x0, sum = 3
955 12:47:06.716497 12, 0x0, sum = 4
956 12:47:06.719197 best_step = 10
957 12:47:06.719696
958 12:47:06.720261 ==
959 12:47:06.722561 Dram Type= 6, Freq= 0, CH_0, rank 0
960 12:47:06.726166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 12:47:06.726631 ==
962 12:47:06.729449 RX Vref Scan: 1
963 12:47:06.729909
964 12:47:06.730371 Set Vref Range= 32 -> 127
965 12:47:06.730811
966 12:47:06.732360 RX Vref 32 -> 127, step: 1
967 12:47:06.732813
968 12:47:06.735839 RX Delay -111 -> 252, step: 8
969 12:47:06.736300
970 12:47:06.739306 Set Vref, RX VrefLevel [Byte0]: 32
971 12:47:06.742587 [Byte1]: 32
972 12:47:06.743048
973 12:47:06.746021 Set Vref, RX VrefLevel [Byte0]: 33
974 12:47:06.749192 [Byte1]: 33
975 12:47:06.752852
976 12:47:06.753308 Set Vref, RX VrefLevel [Byte0]: 34
977 12:47:06.756297 [Byte1]: 34
978 12:47:06.760984
979 12:47:06.761441 Set Vref, RX VrefLevel [Byte0]: 35
980 12:47:06.763974 [Byte1]: 35
981 12:47:06.768495
982 12:47:06.768950 Set Vref, RX VrefLevel [Byte0]: 36
983 12:47:06.771478 [Byte1]: 36
984 12:47:06.775835
985 12:47:06.776290 Set Vref, RX VrefLevel [Byte0]: 37
986 12:47:06.779167 [Byte1]: 37
987 12:47:06.783633
988 12:47:06.784116 Set Vref, RX VrefLevel [Byte0]: 38
989 12:47:06.786729 [Byte1]: 38
990 12:47:06.791329
991 12:47:06.791842 Set Vref, RX VrefLevel [Byte0]: 39
992 12:47:06.794821 [Byte1]: 39
993 12:47:06.798711
994 12:47:06.799187 Set Vref, RX VrefLevel [Byte0]: 40
995 12:47:06.802061 [Byte1]: 40
996 12:47:06.806816
997 12:47:06.807275 Set Vref, RX VrefLevel [Byte0]: 41
998 12:47:06.809785 [Byte1]: 41
999 12:47:06.814130
1000 12:47:06.814604 Set Vref, RX VrefLevel [Byte0]: 42
1001 12:47:06.817383 [Byte1]: 42
1002 12:47:06.821874
1003 12:47:06.822416 Set Vref, RX VrefLevel [Byte0]: 43
1004 12:47:06.826030 [Byte1]: 43
1005 12:47:06.829490
1006 12:47:06.829964 Set Vref, RX VrefLevel [Byte0]: 44
1007 12:47:06.833576 [Byte1]: 44
1008 12:47:06.837293
1009 12:47:06.837922 Set Vref, RX VrefLevel [Byte0]: 45
1010 12:47:06.840806 [Byte1]: 45
1011 12:47:06.844850
1012 12:47:06.845513 Set Vref, RX VrefLevel [Byte0]: 46
1013 12:47:06.848743 [Byte1]: 46
1014 12:47:06.852826
1015 12:47:06.853444 Set Vref, RX VrefLevel [Byte0]: 47
1016 12:47:06.856252 [Byte1]: 47
1017 12:47:06.860297
1018 12:47:06.860815 Set Vref, RX VrefLevel [Byte0]: 48
1019 12:47:06.863958 [Byte1]: 48
1020 12:47:06.868051
1021 12:47:06.868565 Set Vref, RX VrefLevel [Byte0]: 49
1022 12:47:06.871231 [Byte1]: 49
1023 12:47:06.875327
1024 12:47:06.875938 Set Vref, RX VrefLevel [Byte0]: 50
1025 12:47:06.878842 [Byte1]: 50
1026 12:47:06.882988
1027 12:47:06.883519 Set Vref, RX VrefLevel [Byte0]: 51
1028 12:47:06.886368 [Byte1]: 51
1029 12:47:06.890377
1030 12:47:06.890841 Set Vref, RX VrefLevel [Byte0]: 52
1031 12:47:06.893997 [Byte1]: 52
1032 12:47:06.898224
1033 12:47:06.898740 Set Vref, RX VrefLevel [Byte0]: 53
1034 12:47:06.901870 [Byte1]: 53
1035 12:47:06.905693
1036 12:47:06.906205 Set Vref, RX VrefLevel [Byte0]: 54
1037 12:47:06.909400 [Byte1]: 54
1038 12:47:06.913844
1039 12:47:06.914330 Set Vref, RX VrefLevel [Byte0]: 55
1040 12:47:06.917047 [Byte1]: 55
1041 12:47:06.921428
1042 12:47:06.922053 Set Vref, RX VrefLevel [Byte0]: 56
1043 12:47:06.924235 [Byte1]: 56
1044 12:47:06.928811
1045 12:47:06.929315 Set Vref, RX VrefLevel [Byte0]: 57
1046 12:47:06.932232 [Byte1]: 57
1047 12:47:06.936620
1048 12:47:06.937114 Set Vref, RX VrefLevel [Byte0]: 58
1049 12:47:06.939686 [Byte1]: 58
1050 12:47:06.944191
1051 12:47:06.944628 Set Vref, RX VrefLevel [Byte0]: 59
1052 12:47:06.947563 [Byte1]: 59
1053 12:47:06.952006
1054 12:47:06.952451 Set Vref, RX VrefLevel [Byte0]: 60
1055 12:47:06.958132 [Byte1]: 60
1056 12:47:06.958577
1057 12:47:06.961333 Set Vref, RX VrefLevel [Byte0]: 61
1058 12:47:06.965066 [Byte1]: 61
1059 12:47:06.965548
1060 12:47:06.968344 Set Vref, RX VrefLevel [Byte0]: 62
1061 12:47:06.971744 [Byte1]: 62
1062 12:47:06.972234
1063 12:47:06.975233 Set Vref, RX VrefLevel [Byte0]: 63
1064 12:47:06.978129 [Byte1]: 63
1065 12:47:06.982489
1066 12:47:06.982994 Set Vref, RX VrefLevel [Byte0]: 64
1067 12:47:06.985540 [Byte1]: 64
1068 12:47:06.990255
1069 12:47:06.990871 Set Vref, RX VrefLevel [Byte0]: 65
1070 12:47:06.992956 [Byte1]: 65
1071 12:47:06.997391
1072 12:47:06.998002 Set Vref, RX VrefLevel [Byte0]: 66
1073 12:47:07.001064 [Byte1]: 66
1074 12:47:07.005302
1075 12:47:07.005858 Set Vref, RX VrefLevel [Byte0]: 67
1076 12:47:07.008691 [Byte1]: 67
1077 12:47:07.013166
1078 12:47:07.013603 Set Vref, RX VrefLevel [Byte0]: 68
1079 12:47:07.016556 [Byte1]: 68
1080 12:47:07.020404
1081 12:47:07.020517 Set Vref, RX VrefLevel [Byte0]: 69
1082 12:47:07.023721 [Byte1]: 69
1083 12:47:07.027721
1084 12:47:07.027803 Set Vref, RX VrefLevel [Byte0]: 70
1085 12:47:07.030993 [Byte1]: 70
1086 12:47:07.035352
1087 12:47:07.035459 Set Vref, RX VrefLevel [Byte0]: 71
1088 12:47:07.038947 [Byte1]: 71
1089 12:47:07.042934
1090 12:47:07.043004 Set Vref, RX VrefLevel [Byte0]: 72
1091 12:47:07.046263 [Byte1]: 72
1092 12:47:07.050760
1093 12:47:07.050856 Set Vref, RX VrefLevel [Byte0]: 73
1094 12:47:07.053733 [Byte1]: 73
1095 12:47:07.058509
1096 12:47:07.058614 Set Vref, RX VrefLevel [Byte0]: 74
1097 12:47:07.061505 [Byte1]: 74
1098 12:47:07.066051
1099 12:47:07.066136 Set Vref, RX VrefLevel [Byte0]: 75
1100 12:47:07.069619 [Byte1]: 75
1101 12:47:07.073582
1102 12:47:07.073779 Set Vref, RX VrefLevel [Byte0]: 76
1103 12:47:07.077355 [Byte1]: 76
1104 12:47:07.081109
1105 12:47:07.081246 Set Vref, RX VrefLevel [Byte0]: 77
1106 12:47:07.084664 [Byte1]: 77
1107 12:47:07.088715
1108 12:47:07.088799 Set Vref, RX VrefLevel [Byte0]: 78
1109 12:47:07.092315 [Byte1]: 78
1110 12:47:07.096274
1111 12:47:07.096356 Final RX Vref Byte 0 = 59 to rank0
1112 12:47:07.099845 Final RX Vref Byte 1 = 59 to rank0
1113 12:47:07.103476 Final RX Vref Byte 0 = 59 to rank1
1114 12:47:07.106378 Final RX Vref Byte 1 = 59 to rank1==
1115 12:47:07.109814 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 12:47:07.116572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 12:47:07.116680 ==
1118 12:47:07.116787 DQS Delay:
1119 12:47:07.116868 DQS0 = 0, DQS1 = 0
1120 12:47:07.119682 DQM Delay:
1121 12:47:07.119782 DQM0 = 81, DQM1 = 68
1122 12:47:07.123173 DQ Delay:
1123 12:47:07.126318 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1124 12:47:07.126425 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1125 12:47:07.129503 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1126 12:47:07.136327 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1127 12:47:07.136421
1128 12:47:07.136488
1129 12:47:07.143233 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b2a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1130 12:47:07.146312 CH0 RK0: MR19=606, MR18=2B2A
1131 12:47:07.152882 CH0_RK0: MR19=0x606, MR18=0x2B2A, DQSOSC=398, MR23=63, INC=93, DEC=62
1132 12:47:07.152969
1133 12:47:07.156469 ----->DramcWriteLeveling(PI) begin...
1134 12:47:07.156554 ==
1135 12:47:07.159932 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 12:47:07.163301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 12:47:07.163422 ==
1138 12:47:07.166374 Write leveling (Byte 0): 31 => 31
1139 12:47:07.170037 Write leveling (Byte 1): 31 => 31
1140 12:47:07.173470 DramcWriteLeveling(PI) end<-----
1141 12:47:07.173553
1142 12:47:07.173618 ==
1143 12:47:07.176326 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 12:47:07.179930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 12:47:07.180014 ==
1146 12:47:07.183069 [Gating] SW mode calibration
1147 12:47:07.189729 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 12:47:07.196585 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 12:47:07.200122 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 12:47:07.203602 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1151 12:47:07.209930 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 12:47:07.213429 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1153 12:47:07.216772 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 12:47:07.223310 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 12:47:07.227032 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 12:47:07.230259 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:47:07.236631 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:47:07.239807 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:47:07.243028 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:47:07.246518 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:47:07.253309 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:47:07.256782 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:47:07.300814 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:47:07.301087 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:47:07.301396 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1166 12:47:07.301477 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1167 12:47:07.301724 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1168 12:47:07.301855 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:47:07.301948 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:47:07.302438 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:47:07.302520 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:47:07.303152 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:47:07.344565 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:47:07.344854 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:47:07.344924 0 9 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1176 12:47:07.345000 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 12:47:07.345072 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 12:47:07.345144 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 12:47:07.345526 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 12:47:07.346448 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 12:47:07.346576 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 12:47:07.346881 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
1183 12:47:07.375111 0 10 8 | B1->B0 | 3030 2a2a | 0 0 | (0 1) (0 0)
1184 12:47:07.375426 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 12:47:07.375530 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 12:47:07.375597 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 12:47:07.375671 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 12:47:07.376224 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 12:47:07.378721 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:47:07.382487 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:47:07.385761 0 11 8 | B1->B0 | 2e2e 3939 | 1 1 | (0 0) (0 0)
1192 12:47:07.388932 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1193 12:47:07.392521 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 12:47:07.399039 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 12:47:07.402081 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 12:47:07.405602 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 12:47:07.412484 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 12:47:07.415952 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 12:47:07.419379 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1200 12:47:07.423484 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1201 12:47:07.427171 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 12:47:07.433692 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 12:47:07.437239 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 12:47:07.440536 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 12:47:07.444563 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:47:07.451295 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:47:07.454779 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:47:07.457680 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:47:07.464483 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:47:07.468059 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:47:07.471102 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:47:07.477734 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:47:07.481049 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:47:07.484491 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:47:07.491247 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1216 12:47:07.494386 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 12:47:07.497898 Total UI for P1: 0, mck2ui 16
1218 12:47:07.500935 best dqsien dly found for B0: ( 0, 14, 8)
1219 12:47:07.504250 Total UI for P1: 0, mck2ui 16
1220 12:47:07.507876 best dqsien dly found for B1: ( 0, 14, 8)
1221 12:47:07.511050 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1222 12:47:07.514685 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1223 12:47:07.514767
1224 12:47:07.517463 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1225 12:47:07.520921 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1226 12:47:07.524337 [Gating] SW calibration Done
1227 12:47:07.524418 ==
1228 12:47:07.527657 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 12:47:07.530823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 12:47:07.530932 ==
1231 12:47:07.534312 RX Vref Scan: 0
1232 12:47:07.534393
1233 12:47:07.538103 RX Vref 0 -> 0, step: 1
1234 12:47:07.538185
1235 12:47:07.538248 RX Delay -130 -> 252, step: 16
1236 12:47:07.544402 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1237 12:47:07.547580 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1238 12:47:07.550936 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1239 12:47:07.554189 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1240 12:47:07.557902 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1241 12:47:07.564723 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1242 12:47:07.567745 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1243 12:47:07.571102 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1244 12:47:07.574644 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1245 12:47:07.577754 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1246 12:47:07.584218 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1247 12:47:07.587579 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1248 12:47:07.591147 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1249 12:47:07.594880 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1250 12:47:07.597596 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1251 12:47:07.604228 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1252 12:47:07.604310 ==
1253 12:47:07.607695 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 12:47:07.611058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 12:47:07.611140 ==
1256 12:47:07.611204 DQS Delay:
1257 12:47:07.614138 DQS0 = 0, DQS1 = 0
1258 12:47:07.614220 DQM Delay:
1259 12:47:07.617358 DQM0 = 75, DQM1 = 69
1260 12:47:07.617440 DQ Delay:
1261 12:47:07.620691 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1262 12:47:07.623986 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =85
1263 12:47:07.627575 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1264 12:47:07.631027 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1265 12:47:07.631109
1266 12:47:07.631173
1267 12:47:07.631232 ==
1268 12:47:07.634002 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 12:47:07.637436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 12:47:07.637518 ==
1271 12:47:07.640847
1272 12:47:07.640928
1273 12:47:07.640992 TX Vref Scan disable
1274 12:47:07.644186 == TX Byte 0 ==
1275 12:47:07.647528 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1276 12:47:07.650958 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1277 12:47:07.654668 == TX Byte 1 ==
1278 12:47:07.657482 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1279 12:47:07.660939 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1280 12:47:07.661021 ==
1281 12:47:07.664020 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 12:47:07.670709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 12:47:07.670792 ==
1284 12:47:07.682239 TX Vref=22, minBit 9, minWin=26, winSum=435
1285 12:47:07.685721 TX Vref=24, minBit 11, minWin=26, winSum=435
1286 12:47:07.688996 TX Vref=26, minBit 2, minWin=27, winSum=443
1287 12:47:07.692750 TX Vref=28, minBit 1, minWin=27, winSum=443
1288 12:47:07.696017 TX Vref=30, minBit 1, minWin=27, winSum=443
1289 12:47:07.702683 TX Vref=32, minBit 11, minWin=26, winSum=444
1290 12:47:07.705805 [TxChooseVref] Worse bit 2, Min win 27, Win sum 443, Final Vref 26
1291 12:47:07.705887
1292 12:47:07.709045 Final TX Range 1 Vref 26
1293 12:47:07.709142
1294 12:47:07.709207 ==
1295 12:47:07.712530 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 12:47:07.715871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 12:47:07.715951 ==
1298 12:47:07.719238
1299 12:47:07.719316
1300 12:47:07.719405 TX Vref Scan disable
1301 12:47:07.722353 == TX Byte 0 ==
1302 12:47:07.725726 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1303 12:47:07.729828 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1304 12:47:07.732651 == TX Byte 1 ==
1305 12:47:07.736279 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1306 12:47:07.739090 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1307 12:47:07.742476
1308 12:47:07.742547 [DATLAT]
1309 12:47:07.742605 Freq=800, CH0 RK1
1310 12:47:07.742662
1311 12:47:07.745917 DATLAT Default: 0xa
1312 12:47:07.745996 0, 0xFFFF, sum = 0
1313 12:47:07.749291 1, 0xFFFF, sum = 0
1314 12:47:07.749399 2, 0xFFFF, sum = 0
1315 12:47:07.752723 3, 0xFFFF, sum = 0
1316 12:47:07.752803 4, 0xFFFF, sum = 0
1317 12:47:07.756069 5, 0xFFFF, sum = 0
1318 12:47:07.759447 6, 0xFFFF, sum = 0
1319 12:47:07.759527 7, 0xFFFF, sum = 0
1320 12:47:07.762559 8, 0xFFFF, sum = 0
1321 12:47:07.762639 9, 0x0, sum = 1
1322 12:47:07.762702 10, 0x0, sum = 2
1323 12:47:07.766045 11, 0x0, sum = 3
1324 12:47:07.766126 12, 0x0, sum = 4
1325 12:47:07.769056 best_step = 10
1326 12:47:07.769164
1327 12:47:07.769258 ==
1328 12:47:07.772454 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 12:47:07.775923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 12:47:07.776003 ==
1331 12:47:07.779364 RX Vref Scan: 0
1332 12:47:07.779482
1333 12:47:07.779544 RX Vref 0 -> 0, step: 1
1334 12:47:07.779602
1335 12:47:07.782293 RX Delay -111 -> 252, step: 8
1336 12:47:07.789104 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1337 12:47:07.792422 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1338 12:47:07.795962 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1339 12:47:07.799285 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1340 12:47:07.802348 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1341 12:47:07.809371 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1342 12:47:07.812817 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1343 12:47:07.816501 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1344 12:47:07.819228 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1345 12:47:07.822807 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1346 12:47:07.829427 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1347 12:47:07.833111 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1348 12:47:07.836189 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1349 12:47:07.839999 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1350 12:47:07.842854 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1351 12:47:07.849230 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1352 12:47:07.849311 ==
1353 12:47:07.852624 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 12:47:07.855992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 12:47:07.856106 ==
1356 12:47:07.856180 DQS Delay:
1357 12:47:07.859115 DQS0 = 0, DQS1 = 0
1358 12:47:07.859221 DQM Delay:
1359 12:47:07.862346 DQM0 = 78, DQM1 = 70
1360 12:47:07.862427 DQ Delay:
1361 12:47:07.866193 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1362 12:47:07.869483 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =88
1363 12:47:07.872963 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1364 12:47:07.875720 DQ12 =76, DQ13 =72, DQ14 =80, DQ15 =80
1365 12:47:07.875829
1366 12:47:07.875920
1367 12:47:07.882586 [DQSOSCAuto] RK1, (LSB)MR18= 0x4621, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1368 12:47:07.886038 CH0 RK1: MR19=606, MR18=4621
1369 12:47:07.892715 CH0_RK1: MR19=0x606, MR18=0x4621, DQSOSC=392, MR23=63, INC=96, DEC=64
1370 12:47:07.896569 [RxdqsGatingPostProcess] freq 800
1371 12:47:07.902562 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 12:47:07.906003 Pre-setting of DQS Precalculation
1373 12:47:07.909648 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 12:47:07.909730 ==
1375 12:47:07.912733 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 12:47:07.916005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 12:47:07.916087 ==
1378 12:47:07.923204 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 12:47:07.929271 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 12:47:07.937617 [CA 0] Center 36 (6~66) winsize 61
1381 12:47:07.940878 [CA 1] Center 36 (6~67) winsize 62
1382 12:47:07.944067 [CA 2] Center 34 (5~64) winsize 60
1383 12:47:07.947925 [CA 3] Center 34 (4~64) winsize 61
1384 12:47:07.950854 [CA 4] Center 35 (5~65) winsize 61
1385 12:47:07.954367 [CA 5] Center 34 (4~64) winsize 61
1386 12:47:07.954448
1387 12:47:07.957631 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1388 12:47:07.957712
1389 12:47:07.960706 [CATrainingPosCal] consider 1 rank data
1390 12:47:07.963994 u2DelayCellTimex100 = 270/100 ps
1391 12:47:07.967264 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1392 12:47:07.970993 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1393 12:47:07.977662 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1394 12:47:07.980806 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1395 12:47:07.984267 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1396 12:47:07.987589 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1397 12:47:07.987670
1398 12:47:07.990641 CA PerBit enable=1, Macro0, CA PI delay=34
1399 12:47:07.990722
1400 12:47:07.994010 [CBTSetCACLKResult] CA Dly = 34
1401 12:47:07.994092 CS Dly: 4 (0~35)
1402 12:47:07.997726 ==
1403 12:47:07.997808 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 12:47:08.004058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 12:47:08.004138 ==
1406 12:47:08.007687 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 12:47:08.013715 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 12:47:08.023565 [CA 0] Center 37 (7~67) winsize 61
1409 12:47:08.027080 [CA 1] Center 36 (6~67) winsize 62
1410 12:47:08.030388 [CA 2] Center 35 (5~65) winsize 61
1411 12:47:08.033877 [CA 3] Center 34 (4~64) winsize 61
1412 12:47:08.037215 [CA 4] Center 35 (5~65) winsize 61
1413 12:47:08.040510 [CA 5] Center 33 (3~64) winsize 62
1414 12:47:08.040589
1415 12:47:08.043944 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1416 12:47:08.044023
1417 12:47:08.047397 [CATrainingPosCal] consider 2 rank data
1418 12:47:08.050349 u2DelayCellTimex100 = 270/100 ps
1419 12:47:08.053627 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1420 12:47:08.056761 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1421 12:47:08.063768 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1422 12:47:08.067001 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1423 12:47:08.070569 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1424 12:47:08.073416 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1425 12:47:08.073516
1426 12:47:08.077349 CA PerBit enable=1, Macro0, CA PI delay=34
1427 12:47:08.077445
1428 12:47:08.081215 [CBTSetCACLKResult] CA Dly = 34
1429 12:47:08.081313 CS Dly: 5 (0~37)
1430 12:47:08.081399
1431 12:47:08.085136 ----->DramcWriteLeveling(PI) begin...
1432 12:47:08.085236 ==
1433 12:47:08.089152 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 12:47:08.092659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 12:47:08.092757 ==
1436 12:47:08.096388 Write leveling (Byte 0): 27 => 27
1437 12:47:08.100093 Write leveling (Byte 1): 28 => 28
1438 12:47:08.103520 DramcWriteLeveling(PI) end<-----
1439 12:47:08.103593
1440 12:47:08.103653 ==
1441 12:47:08.106936 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 12:47:08.110854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 12:47:08.110950 ==
1444 12:47:08.114375 [Gating] SW mode calibration
1445 12:47:08.121091 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 12:47:08.124226 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 12:47:08.130685 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 12:47:08.134154 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 12:47:08.137645 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 12:47:08.144280 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 12:47:08.147363 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 12:47:08.150774 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 12:47:08.154465 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 12:47:08.161065 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 12:47:08.164164 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:47:08.167579 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:47:08.174088 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:47:08.177343 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:47:08.180845 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:47:08.187404 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:47:08.190719 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:47:08.193779 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:47:08.200751 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:47:08.204057 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1465 12:47:08.207328 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1466 12:47:08.214074 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:47:08.217602 0 8 16 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1468 12:47:08.220475 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:47:08.227145 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:47:08.230743 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:47:08.233760 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:47:08.240838 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:47:08.244316 0 9 8 | B1->B0 | 2c2c 2c2c | 1 1 | (1 1) (1 1)
1474 12:47:08.247155 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 12:47:08.253629 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 12:47:08.257049 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 12:47:08.260640 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 12:47:08.267099 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 12:47:08.270243 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 12:47:08.273678 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1481 12:47:08.280656 0 10 8 | B1->B0 | 2929 2727 | 0 0 | (1 1) (0 0)
1482 12:47:08.283943 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 12:47:08.286913 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 12:47:08.290388 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 12:47:08.297357 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:47:08.300820 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:47:08.303563 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:47:08.310347 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1489 12:47:08.313894 0 11 8 | B1->B0 | 3a3a 3939 | 0 0 | (0 0) (0 0)
1490 12:47:08.317539 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 12:47:08.323629 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 12:47:08.327178 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 12:47:08.330651 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 12:47:08.337453 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 12:47:08.340622 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 12:47:08.343941 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 12:47:08.350173 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1498 12:47:08.353782 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 12:47:08.356976 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 12:47:08.363948 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 12:47:08.367165 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 12:47:08.370856 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:47:08.377066 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:47:08.380676 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:47:08.383677 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:47:08.386849 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:47:08.393982 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:47:08.397303 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:47:08.400279 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:47:08.407117 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:47:08.410857 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:47:08.413700 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:47:08.420441 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1514 12:47:08.423879 Total UI for P1: 0, mck2ui 16
1515 12:47:08.426845 best dqsien dly found for B0: ( 0, 14, 6)
1516 12:47:08.430686 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 12:47:08.433835 Total UI for P1: 0, mck2ui 16
1518 12:47:08.436726 best dqsien dly found for B1: ( 0, 14, 8)
1519 12:47:08.440271 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1520 12:47:08.443698 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1521 12:47:08.443808
1522 12:47:08.447113 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1523 12:47:08.450285 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1524 12:47:08.453453 [Gating] SW calibration Done
1525 12:47:08.453549 ==
1526 12:47:08.457006 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 12:47:08.460393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 12:47:08.463885 ==
1529 12:47:08.463966 RX Vref Scan: 0
1530 12:47:08.464029
1531 12:47:08.467149 RX Vref 0 -> 0, step: 1
1532 12:47:08.467254
1533 12:47:08.470297 RX Delay -130 -> 252, step: 16
1534 12:47:08.473570 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1535 12:47:08.476765 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1536 12:47:08.480082 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1537 12:47:08.483318 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1538 12:47:08.490161 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1539 12:47:08.493734 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1540 12:47:08.496718 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1541 12:47:08.500291 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1542 12:47:08.503755 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1543 12:47:08.507420 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1544 12:47:08.513631 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1545 12:47:08.516945 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1546 12:47:08.520295 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1547 12:47:08.523689 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1548 12:47:08.530242 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1549 12:47:08.533787 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1550 12:47:08.533867 ==
1551 12:47:08.537264 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 12:47:08.540645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 12:47:08.540765 ==
1554 12:47:08.540857 DQS Delay:
1555 12:47:08.544017 DQS0 = 0, DQS1 = 0
1556 12:47:08.544089 DQM Delay:
1557 12:47:08.547027 DQM0 = 81, DQM1 = 71
1558 12:47:08.547122 DQ Delay:
1559 12:47:08.550548 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1560 12:47:08.553910 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1561 12:47:08.557044 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1562 12:47:08.560541 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1563 12:47:08.560617
1564 12:47:08.560679
1565 12:47:08.560737 ==
1566 12:47:08.563992 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 12:47:08.566881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 12:47:08.570474 ==
1569 12:47:08.570559
1570 12:47:08.570626
1571 12:47:08.570689 TX Vref Scan disable
1572 12:47:08.573724 == TX Byte 0 ==
1573 12:47:08.577027 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1574 12:47:08.580271 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1575 12:47:08.583621 == TX Byte 1 ==
1576 12:47:08.586897 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1577 12:47:08.590689 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1578 12:47:08.594052 ==
1579 12:47:08.594171 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 12:47:08.600293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 12:47:08.600443 ==
1582 12:47:08.612708 TX Vref=22, minBit 1, minWin=27, winSum=441
1583 12:47:08.615697 TX Vref=24, minBit 1, minWin=27, winSum=440
1584 12:47:08.619198 TX Vref=26, minBit 1, minWin=27, winSum=447
1585 12:47:08.622590 TX Vref=28, minBit 5, minWin=27, winSum=448
1586 12:47:08.626162 TX Vref=30, minBit 4, minWin=27, winSum=446
1587 12:47:08.629138 TX Vref=32, minBit 5, minWin=27, winSum=446
1588 12:47:08.635814 [TxChooseVref] Worse bit 5, Min win 27, Win sum 448, Final Vref 28
1589 12:47:08.636230
1590 12:47:08.639262 Final TX Range 1 Vref 28
1591 12:47:08.639733
1592 12:47:08.640061 ==
1593 12:47:08.642575 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 12:47:08.645856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 12:47:08.646270 ==
1596 12:47:08.646593
1597 12:47:08.649107
1598 12:47:08.649517 TX Vref Scan disable
1599 12:47:08.652666 == TX Byte 0 ==
1600 12:47:08.656182 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1601 12:47:08.659738 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1602 12:47:08.663106 == TX Byte 1 ==
1603 12:47:08.666107 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1604 12:47:08.669814 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1605 12:47:08.670283
1606 12:47:08.673253 [DATLAT]
1607 12:47:08.673891 Freq=800, CH1 RK0
1608 12:47:08.674278
1609 12:47:08.676582 DATLAT Default: 0xa
1610 12:47:08.677033 0, 0xFFFF, sum = 0
1611 12:47:08.680068 1, 0xFFFF, sum = 0
1612 12:47:08.680549 2, 0xFFFF, sum = 0
1613 12:47:08.682914 3, 0xFFFF, sum = 0
1614 12:47:08.683442 4, 0xFFFF, sum = 0
1615 12:47:08.686522 5, 0xFFFF, sum = 0
1616 12:47:08.686893 6, 0xFFFF, sum = 0
1617 12:47:08.689691 7, 0xFFFF, sum = 0
1618 12:47:08.690124 8, 0xFFFF, sum = 0
1619 12:47:08.693283 9, 0x0, sum = 1
1620 12:47:08.693844 10, 0x0, sum = 2
1621 12:47:08.696600 11, 0x0, sum = 3
1622 12:47:08.697029 12, 0x0, sum = 4
1623 12:47:08.700183 best_step = 10
1624 12:47:08.700759
1625 12:47:08.701107 ==
1626 12:47:08.702860 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 12:47:08.706372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 12:47:08.706826 ==
1629 12:47:08.709955 RX Vref Scan: 1
1630 12:47:08.710498
1631 12:47:08.710833 Set Vref Range= 32 -> 127
1632 12:47:08.711171
1633 12:47:08.712968 RX Vref 32 -> 127, step: 1
1634 12:47:08.713389
1635 12:47:08.716650 RX Delay -111 -> 252, step: 8
1636 12:47:08.717075
1637 12:47:08.719464 Set Vref, RX VrefLevel [Byte0]: 32
1638 12:47:08.723048 [Byte1]: 32
1639 12:47:08.723534
1640 12:47:08.726397 Set Vref, RX VrefLevel [Byte0]: 33
1641 12:47:08.729825 [Byte1]: 33
1642 12:47:08.733198
1643 12:47:08.733638 Set Vref, RX VrefLevel [Byte0]: 34
1644 12:47:08.736103 [Byte1]: 34
1645 12:47:08.740632
1646 12:47:08.741066 Set Vref, RX VrefLevel [Byte0]: 35
1647 12:47:08.744117 [Byte1]: 35
1648 12:47:08.748473
1649 12:47:08.748899 Set Vref, RX VrefLevel [Byte0]: 36
1650 12:47:08.751483 [Byte1]: 36
1651 12:47:08.755940
1652 12:47:08.756456 Set Vref, RX VrefLevel [Byte0]: 37
1653 12:47:08.758946 [Byte1]: 37
1654 12:47:08.763499
1655 12:47:08.764053 Set Vref, RX VrefLevel [Byte0]: 38
1656 12:47:08.767031 [Byte1]: 38
1657 12:47:08.771628
1658 12:47:08.772052 Set Vref, RX VrefLevel [Byte0]: 39
1659 12:47:08.774674 [Byte1]: 39
1660 12:47:08.779188
1661 12:47:08.779715 Set Vref, RX VrefLevel [Byte0]: 40
1662 12:47:08.782156 [Byte1]: 40
1663 12:47:08.786619
1664 12:47:08.787067 Set Vref, RX VrefLevel [Byte0]: 41
1665 12:47:08.790040 [Byte1]: 41
1666 12:47:08.794267
1667 12:47:08.794697 Set Vref, RX VrefLevel [Byte0]: 42
1668 12:47:08.797325 [Byte1]: 42
1669 12:47:08.801935
1670 12:47:08.802478 Set Vref, RX VrefLevel [Byte0]: 43
1671 12:47:08.805659 [Byte1]: 43
1672 12:47:08.809445
1673 12:47:08.809998 Set Vref, RX VrefLevel [Byte0]: 44
1674 12:47:08.812868 [Byte1]: 44
1675 12:47:08.817500
1676 12:47:08.817944 Set Vref, RX VrefLevel [Byte0]: 45
1677 12:47:08.820392 [Byte1]: 45
1678 12:47:08.824746
1679 12:47:08.825291 Set Vref, RX VrefLevel [Byte0]: 46
1680 12:47:08.828217 [Byte1]: 46
1681 12:47:08.832456
1682 12:47:08.832882 Set Vref, RX VrefLevel [Byte0]: 47
1683 12:47:08.835446 [Byte1]: 47
1684 12:47:08.839994
1685 12:47:08.840581 Set Vref, RX VrefLevel [Byte0]: 48
1686 12:47:08.843273 [Byte1]: 48
1687 12:47:08.847525
1688 12:47:08.847944 Set Vref, RX VrefLevel [Byte0]: 49
1689 12:47:08.850837 [Byte1]: 49
1690 12:47:08.855284
1691 12:47:08.855746 Set Vref, RX VrefLevel [Byte0]: 50
1692 12:47:08.858694 [Byte1]: 50
1693 12:47:08.863147
1694 12:47:08.863684 Set Vref, RX VrefLevel [Byte0]: 51
1695 12:47:08.866390 [Byte1]: 51
1696 12:47:08.870612
1697 12:47:08.871065 Set Vref, RX VrefLevel [Byte0]: 52
1698 12:47:08.873584 [Byte1]: 52
1699 12:47:08.877948
1700 12:47:08.878493 Set Vref, RX VrefLevel [Byte0]: 53
1701 12:47:08.881560 [Byte1]: 53
1702 12:47:08.886094
1703 12:47:08.886695 Set Vref, RX VrefLevel [Byte0]: 54
1704 12:47:08.889376 [Byte1]: 54
1705 12:47:08.893398
1706 12:47:08.893936 Set Vref, RX VrefLevel [Byte0]: 55
1707 12:47:08.896947 [Byte1]: 55
1708 12:47:08.901437
1709 12:47:08.902010 Set Vref, RX VrefLevel [Byte0]: 56
1710 12:47:08.904494 [Byte1]: 56
1711 12:47:08.908610
1712 12:47:08.908695 Set Vref, RX VrefLevel [Byte0]: 57
1713 12:47:08.911529 [Byte1]: 57
1714 12:47:08.916154
1715 12:47:08.916232 Set Vref, RX VrefLevel [Byte0]: 58
1716 12:47:08.919644 [Byte1]: 58
1717 12:47:08.923982
1718 12:47:08.924083 Set Vref, RX VrefLevel [Byte0]: 59
1719 12:47:08.927086 [Byte1]: 59
1720 12:47:08.931552
1721 12:47:08.931626 Set Vref, RX VrefLevel [Byte0]: 60
1722 12:47:08.934888 [Byte1]: 60
1723 12:47:08.939088
1724 12:47:08.939197 Set Vref, RX VrefLevel [Byte0]: 61
1725 12:47:08.942195 [Byte1]: 61
1726 12:47:08.946822
1727 12:47:08.946924 Set Vref, RX VrefLevel [Byte0]: 62
1728 12:47:08.950247 [Byte1]: 62
1729 12:47:08.954354
1730 12:47:08.954444 Set Vref, RX VrefLevel [Byte0]: 63
1731 12:47:08.957886 [Byte1]: 63
1732 12:47:08.962174
1733 12:47:08.962275 Set Vref, RX VrefLevel [Byte0]: 64
1734 12:47:08.965120 [Byte1]: 64
1735 12:47:08.969557
1736 12:47:08.969634 Set Vref, RX VrefLevel [Byte0]: 65
1737 12:47:08.972647 [Byte1]: 65
1738 12:47:08.977145
1739 12:47:08.977225 Set Vref, RX VrefLevel [Byte0]: 66
1740 12:47:08.980891 [Byte1]: 66
1741 12:47:08.985142
1742 12:47:08.985264 Set Vref, RX VrefLevel [Byte0]: 67
1743 12:47:08.988094 [Byte1]: 67
1744 12:47:08.992342
1745 12:47:08.992416 Set Vref, RX VrefLevel [Byte0]: 68
1746 12:47:08.995619 [Byte1]: 68
1747 12:47:09.000235
1748 12:47:09.000337 Set Vref, RX VrefLevel [Byte0]: 69
1749 12:47:09.003273 [Byte1]: 69
1750 12:47:09.007769
1751 12:47:09.007842 Set Vref, RX VrefLevel [Byte0]: 70
1752 12:47:09.010946 [Byte1]: 70
1753 12:47:09.015185
1754 12:47:09.015300 Set Vref, RX VrefLevel [Byte0]: 71
1755 12:47:09.018754 [Byte1]: 71
1756 12:47:09.023297
1757 12:47:09.023449 Set Vref, RX VrefLevel [Byte0]: 72
1758 12:47:09.026192 [Byte1]: 72
1759 12:47:09.030750
1760 12:47:09.030820 Final RX Vref Byte 0 = 57 to rank0
1761 12:47:09.034324 Final RX Vref Byte 1 = 54 to rank0
1762 12:47:09.037269 Final RX Vref Byte 0 = 57 to rank1
1763 12:47:09.041050 Final RX Vref Byte 1 = 54 to rank1==
1764 12:47:09.044158 Dram Type= 6, Freq= 0, CH_1, rank 0
1765 12:47:09.050696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1766 12:47:09.050787 ==
1767 12:47:09.050871 DQS Delay:
1768 12:47:09.050931 DQS0 = 0, DQS1 = 0
1769 12:47:09.053772 DQM Delay:
1770 12:47:09.053840 DQM0 = 80, DQM1 = 72
1771 12:47:09.057906 DQ Delay:
1772 12:47:09.060677 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1773 12:47:09.060751 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1774 12:47:09.064027 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1775 12:47:09.067561 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =76
1776 12:47:09.070732
1777 12:47:09.070805
1778 12:47:09.077552 [DQSOSCAuto] RK0, (LSB)MR18= 0x101a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
1779 12:47:09.080689 CH1 RK0: MR19=606, MR18=101A
1780 12:47:09.087424 CH1_RK0: MR19=0x606, MR18=0x101A, DQSOSC=403, MR23=63, INC=90, DEC=60
1781 12:47:09.087515
1782 12:47:09.090789 ----->DramcWriteLeveling(PI) begin...
1783 12:47:09.090898 ==
1784 12:47:09.094211 Dram Type= 6, Freq= 0, CH_1, rank 1
1785 12:47:09.097143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1786 12:47:09.097234 ==
1787 12:47:09.100828 Write leveling (Byte 0): 28 => 28
1788 12:47:09.104022 Write leveling (Byte 1): 29 => 29
1789 12:47:09.107489 DramcWriteLeveling(PI) end<-----
1790 12:47:09.107569
1791 12:47:09.107640 ==
1792 12:47:09.110396 Dram Type= 6, Freq= 0, CH_1, rank 1
1793 12:47:09.113884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1794 12:47:09.113981 ==
1795 12:47:09.117178 [Gating] SW mode calibration
1796 12:47:09.123897 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1797 12:47:09.130935 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1798 12:47:09.134271 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1799 12:47:09.137248 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1800 12:47:09.143770 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 12:47:09.147700 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 12:47:09.150482 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 12:47:09.157552 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 12:47:09.160639 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 12:47:09.164034 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 12:47:09.170469 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 12:47:09.173701 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 12:47:09.177072 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 12:47:09.183635 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 12:47:09.187167 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 12:47:09.190556 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 12:47:09.193824 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 12:47:09.200781 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 12:47:09.204183 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 12:47:09.206988 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1816 12:47:09.214032 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1817 12:47:09.217450 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:47:09.220401 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:47:09.227010 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:47:09.230611 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:47:09.233798 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:47:09.240414 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:47:09.243891 0 9 4 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
1824 12:47:09.247149 0 9 8 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1825 12:47:09.253948 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 12:47:09.256946 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 12:47:09.260021 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 12:47:09.266840 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 12:47:09.270354 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 12:47:09.273457 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1831 12:47:09.280751 0 10 4 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (1 1)
1832 12:47:09.283525 0 10 8 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
1833 12:47:09.286944 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:47:09.293526 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:47:09.297131 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 12:47:09.299910 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 12:47:09.307065 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 12:47:09.310160 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 12:47:09.313294 0 11 4 | B1->B0 | 2b2b 3636 | 0 1 | (0 0) (0 0)
1840 12:47:09.320301 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1841 12:47:09.323879 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 12:47:09.326815 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 12:47:09.330266 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 12:47:09.337148 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 12:47:09.340204 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 12:47:09.343561 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 12:47:09.350620 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1848 12:47:09.353536 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1849 12:47:09.356987 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 12:47:09.363416 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 12:47:09.366896 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 12:47:09.370294 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 12:47:09.376822 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 12:47:09.380065 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 12:47:09.383583 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 12:47:09.390295 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 12:47:09.393590 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 12:47:09.396980 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 12:47:09.403234 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 12:47:09.407128 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 12:47:09.410459 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 12:47:09.416890 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 12:47:09.419906 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1864 12:47:09.423447 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 12:47:09.426661 Total UI for P1: 0, mck2ui 16
1866 12:47:09.430088 best dqsien dly found for B0: ( 0, 14, 4)
1867 12:47:09.433398 Total UI for P1: 0, mck2ui 16
1868 12:47:09.436814 best dqsien dly found for B1: ( 0, 14, 4)
1869 12:47:09.440417 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1870 12:47:09.443503 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1871 12:47:09.443575
1872 12:47:09.446915 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1873 12:47:09.450128 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1874 12:47:09.453807 [Gating] SW calibration Done
1875 12:47:09.453882 ==
1876 12:47:09.456925 Dram Type= 6, Freq= 0, CH_1, rank 1
1877 12:47:09.460036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1878 12:47:09.463353 ==
1879 12:47:09.463495 RX Vref Scan: 0
1880 12:47:09.463587
1881 12:47:09.466896 RX Vref 0 -> 0, step: 1
1882 12:47:09.466971
1883 12:47:09.470450 RX Delay -130 -> 252, step: 16
1884 12:47:09.473697 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1885 12:47:09.476652 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1886 12:47:09.480139 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1887 12:47:09.483607 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1888 12:47:09.490294 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1889 12:47:09.493311 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1890 12:47:09.496734 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1891 12:47:09.499861 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1892 12:47:09.503577 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1893 12:47:09.509803 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1894 12:47:09.513523 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1895 12:47:09.516661 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1896 12:47:09.519976 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1897 12:47:09.523580 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1898 12:47:09.529709 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1899 12:47:09.533361 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1900 12:47:09.533435 ==
1901 12:47:09.536747 Dram Type= 6, Freq= 0, CH_1, rank 1
1902 12:47:09.540196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1903 12:47:09.540267 ==
1904 12:47:09.543577 DQS Delay:
1905 12:47:09.543645 DQS0 = 0, DQS1 = 0
1906 12:47:09.543719 DQM Delay:
1907 12:47:09.546445 DQM0 = 79, DQM1 = 71
1908 12:47:09.546511 DQ Delay:
1909 12:47:09.549732 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1910 12:47:09.553036 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1911 12:47:09.556654 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1912 12:47:09.560144 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1913 12:47:09.560219
1914 12:47:09.560281
1915 12:47:09.560361 ==
1916 12:47:09.563405 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 12:47:09.570115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 12:47:09.570216 ==
1919 12:47:09.570311
1920 12:47:09.570404
1921 12:47:09.570490 TX Vref Scan disable
1922 12:47:09.573471 == TX Byte 0 ==
1923 12:47:09.577147 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1924 12:47:09.580162 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1925 12:47:09.583725 == TX Byte 1 ==
1926 12:47:09.586666 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1927 12:47:09.590219 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1928 12:47:09.593460 ==
1929 12:47:09.596897 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 12:47:09.600387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 12:47:09.600476 ==
1932 12:47:09.612510 TX Vref=22, minBit 1, minWin=27, winSum=448
1933 12:47:09.615984 TX Vref=24, minBit 0, minWin=28, winSum=453
1934 12:47:09.619080 TX Vref=26, minBit 1, minWin=27, winSum=453
1935 12:47:09.622614 TX Vref=28, minBit 0, minWin=28, winSum=458
1936 12:47:09.625565 TX Vref=30, minBit 1, minWin=27, winSum=461
1937 12:47:09.629443 TX Vref=32, minBit 1, minWin=27, winSum=456
1938 12:47:09.635910 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1939 12:47:09.635996
1940 12:47:09.639337 Final TX Range 1 Vref 28
1941 12:47:09.639436
1942 12:47:09.639501 ==
1943 12:47:09.642426 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 12:47:09.645791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 12:47:09.645873 ==
1946 12:47:09.645937
1947 12:47:09.649209
1948 12:47:09.649290 TX Vref Scan disable
1949 12:47:09.652609 == TX Byte 0 ==
1950 12:47:09.656215 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1951 12:47:09.658899 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1952 12:47:09.663037 == TX Byte 1 ==
1953 12:47:09.665585 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1954 12:47:09.669631 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1955 12:47:09.672597
1956 12:47:09.672678 [DATLAT]
1957 12:47:09.672743 Freq=800, CH1 RK1
1958 12:47:09.672803
1959 12:47:09.675912 DATLAT Default: 0xa
1960 12:47:09.675994 0, 0xFFFF, sum = 0
1961 12:47:09.679333 1, 0xFFFF, sum = 0
1962 12:47:09.679453 2, 0xFFFF, sum = 0
1963 12:47:09.682474 3, 0xFFFF, sum = 0
1964 12:47:09.682556 4, 0xFFFF, sum = 0
1965 12:47:09.686043 5, 0xFFFF, sum = 0
1966 12:47:09.686125 6, 0xFFFF, sum = 0
1967 12:47:09.689054 7, 0xFFFF, sum = 0
1968 12:47:09.689136 8, 0xFFFF, sum = 0
1969 12:47:09.692353 9, 0x0, sum = 1
1970 12:47:09.692435 10, 0x0, sum = 2
1971 12:47:09.695917 11, 0x0, sum = 3
1972 12:47:09.695999 12, 0x0, sum = 4
1973 12:47:09.699347 best_step = 10
1974 12:47:09.699457
1975 12:47:09.699522 ==
1976 12:47:09.702607 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 12:47:09.706369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 12:47:09.706451 ==
1979 12:47:09.709341 RX Vref Scan: 0
1980 12:47:09.709423
1981 12:47:09.709486 RX Vref 0 -> 0, step: 1
1982 12:47:09.709546
1983 12:47:09.712435 RX Delay -111 -> 252, step: 8
1984 12:47:09.718937 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1985 12:47:09.721978 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1986 12:47:09.725717 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
1987 12:47:09.728806 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1988 12:47:09.735226 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
1989 12:47:09.738952 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
1990 12:47:09.742254 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1991 12:47:09.745516 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
1992 12:47:09.748602 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
1993 12:47:09.755822 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
1994 12:47:09.758783 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1995 12:47:09.761971 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1996 12:47:09.765391 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1997 12:47:09.768533 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
1998 12:47:09.775191 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1999 12:47:09.778717 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2000 12:47:09.778798 ==
2001 12:47:09.782480 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 12:47:09.785276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 12:47:09.785359 ==
2004 12:47:09.788739 DQS Delay:
2005 12:47:09.788821 DQS0 = 0, DQS1 = 0
2006 12:47:09.788885 DQM Delay:
2007 12:47:09.791902 DQM0 = 77, DQM1 = 74
2008 12:47:09.791983 DQ Delay:
2009 12:47:09.795306 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2010 12:47:09.799176 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2011 12:47:09.802320 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =68
2012 12:47:09.805212 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
2013 12:47:09.805293
2014 12:47:09.805357
2015 12:47:09.815489 [DQSOSCAuto] RK1, (LSB)MR18= 0x263d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2016 12:47:09.815572 CH1 RK1: MR19=606, MR18=263D
2017 12:47:09.822257 CH1_RK1: MR19=0x606, MR18=0x263D, DQSOSC=394, MR23=63, INC=95, DEC=63
2018 12:47:09.825685 [RxdqsGatingPostProcess] freq 800
2019 12:47:09.832108 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2020 12:47:09.835268 Pre-setting of DQS Precalculation
2021 12:47:09.838431 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2022 12:47:09.845440 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2023 12:47:09.855332 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2024 12:47:09.855452
2025 12:47:09.855516
2026 12:47:09.855577 [Calibration Summary] 1600 Mbps
2027 12:47:09.859002 CH 0, Rank 0
2028 12:47:09.859083 SW Impedance : PASS
2029 12:47:09.861825 DUTY Scan : NO K
2030 12:47:09.865597 ZQ Calibration : PASS
2031 12:47:09.865678 Jitter Meter : NO K
2032 12:47:09.868965 CBT Training : PASS
2033 12:47:09.872056 Write leveling : PASS
2034 12:47:09.872141 RX DQS gating : PASS
2035 12:47:09.875337 RX DQ/DQS(RDDQC) : PASS
2036 12:47:09.878527 TX DQ/DQS : PASS
2037 12:47:09.878609 RX DATLAT : PASS
2038 12:47:09.883638 RX DQ/DQS(Engine): PASS
2039 12:47:09.885470 TX OE : NO K
2040 12:47:09.885552 All Pass.
2041 12:47:09.885615
2042 12:47:09.885674 CH 0, Rank 1
2043 12:47:09.888712 SW Impedance : PASS
2044 12:47:09.892016 DUTY Scan : NO K
2045 12:47:09.892098 ZQ Calibration : PASS
2046 12:47:09.895481 Jitter Meter : NO K
2047 12:47:09.898906 CBT Training : PASS
2048 12:47:09.898987 Write leveling : PASS
2049 12:47:09.901782 RX DQS gating : PASS
2050 12:47:09.901864 RX DQ/DQS(RDDQC) : PASS
2051 12:47:09.905333 TX DQ/DQS : PASS
2052 12:47:09.908833 RX DATLAT : PASS
2053 12:47:09.908915 RX DQ/DQS(Engine): PASS
2054 12:47:09.912263 TX OE : NO K
2055 12:47:09.912345 All Pass.
2056 12:47:09.912408
2057 12:47:09.915740 CH 1, Rank 0
2058 12:47:09.915821 SW Impedance : PASS
2059 12:47:09.919102 DUTY Scan : NO K
2060 12:47:09.922041 ZQ Calibration : PASS
2061 12:47:09.922122 Jitter Meter : NO K
2062 12:47:09.925534 CBT Training : PASS
2063 12:47:09.928779 Write leveling : PASS
2064 12:47:09.928860 RX DQS gating : PASS
2065 12:47:09.932111 RX DQ/DQS(RDDQC) : PASS
2066 12:47:09.935326 TX DQ/DQS : PASS
2067 12:47:09.935459 RX DATLAT : PASS
2068 12:47:09.938738 RX DQ/DQS(Engine): PASS
2069 12:47:09.938829 TX OE : NO K
2070 12:47:09.942127 All Pass.
2071 12:47:09.942234
2072 12:47:09.942326 CH 1, Rank 1
2073 12:47:09.945167 SW Impedance : PASS
2074 12:47:09.945248 DUTY Scan : NO K
2075 12:47:09.948555 ZQ Calibration : PASS
2076 12:47:09.952219 Jitter Meter : NO K
2077 12:47:09.952300 CBT Training : PASS
2078 12:47:09.955637 Write leveling : PASS
2079 12:47:09.958499 RX DQS gating : PASS
2080 12:47:09.958580 RX DQ/DQS(RDDQC) : PASS
2081 12:47:09.962269 TX DQ/DQS : PASS
2082 12:47:09.965434 RX DATLAT : PASS
2083 12:47:09.965515 RX DQ/DQS(Engine): PASS
2084 12:47:09.968500 TX OE : NO K
2085 12:47:09.968581 All Pass.
2086 12:47:09.968645
2087 12:47:09.972207 DramC Write-DBI off
2088 12:47:09.975290 PER_BANK_REFRESH: Hybrid Mode
2089 12:47:09.975377 TX_TRACKING: ON
2090 12:47:09.978648 [GetDramInforAfterCalByMRR] Vendor 6.
2091 12:47:09.982390 [GetDramInforAfterCalByMRR] Revision 606.
2092 12:47:09.985688 [GetDramInforAfterCalByMRR] Revision 2 0.
2093 12:47:09.988710 MR0 0x3b3b
2094 12:47:09.988792 MR8 0x5151
2095 12:47:09.991860 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2096 12:47:09.991942
2097 12:47:09.992006 MR0 0x3b3b
2098 12:47:09.995543 MR8 0x5151
2099 12:47:09.998830 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2100 12:47:09.998911
2101 12:47:10.008771 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2102 12:47:10.012118 [FAST_K] Save calibration result to emmc
2103 12:47:10.015547 [FAST_K] Save calibration result to emmc
2104 12:47:10.015628 dram_init: config_dvfs: 1
2105 12:47:10.021883 dramc_set_vcore_voltage set vcore to 662500
2106 12:47:10.021964 Read voltage for 1200, 2
2107 12:47:10.025432 Vio18 = 0
2108 12:47:10.025513 Vcore = 662500
2109 12:47:10.025577 Vdram = 0
2110 12:47:10.025637 Vddq = 0
2111 12:47:10.028597 Vmddr = 0
2112 12:47:10.032057 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2113 12:47:10.038739 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2114 12:47:10.042013 MEM_TYPE=3, freq_sel=15
2115 12:47:10.042094 sv_algorithm_assistance_LP4_1600
2116 12:47:10.048986 ============ PULL DRAM RESETB DOWN ============
2117 12:47:10.052268 ========== PULL DRAM RESETB DOWN end =========
2118 12:47:10.055276 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2119 12:47:10.058837 ===================================
2120 12:47:10.061797 LPDDR4 DRAM CONFIGURATION
2121 12:47:10.065491 ===================================
2122 12:47:10.068813 EX_ROW_EN[0] = 0x0
2123 12:47:10.068894 EX_ROW_EN[1] = 0x0
2124 12:47:10.072201 LP4Y_EN = 0x0
2125 12:47:10.072283 WORK_FSP = 0x0
2126 12:47:10.075321 WL = 0x4
2127 12:47:10.075424 RL = 0x4
2128 12:47:10.078653 BL = 0x2
2129 12:47:10.078734 RPST = 0x0
2130 12:47:10.082363 RD_PRE = 0x0
2131 12:47:10.082444 WR_PRE = 0x1
2132 12:47:10.085586 WR_PST = 0x0
2133 12:47:10.085668 DBI_WR = 0x0
2134 12:47:10.089154 DBI_RD = 0x0
2135 12:47:10.089236 OTF = 0x1
2136 12:47:10.092190 ===================================
2137 12:47:10.095208 ===================================
2138 12:47:10.098726 ANA top config
2139 12:47:10.102090 ===================================
2140 12:47:10.105411 DLL_ASYNC_EN = 0
2141 12:47:10.105493 ALL_SLAVE_EN = 0
2142 12:47:10.108955 NEW_RANK_MODE = 1
2143 12:47:10.112317 DLL_IDLE_MODE = 1
2144 12:47:10.115149 LP45_APHY_COMB_EN = 1
2145 12:47:10.115230 TX_ODT_DIS = 1
2146 12:47:10.118427 NEW_8X_MODE = 1
2147 12:47:10.121837 ===================================
2148 12:47:10.125205 ===================================
2149 12:47:10.128538 data_rate = 2400
2150 12:47:10.132033 CKR = 1
2151 12:47:10.134928 DQ_P2S_RATIO = 8
2152 12:47:10.138280 ===================================
2153 12:47:10.141640 CA_P2S_RATIO = 8
2154 12:47:10.141721 DQ_CA_OPEN = 0
2155 12:47:10.145143 DQ_SEMI_OPEN = 0
2156 12:47:10.147975 CA_SEMI_OPEN = 0
2157 12:47:10.151664 CA_FULL_RATE = 0
2158 12:47:10.154828 DQ_CKDIV4_EN = 0
2159 12:47:10.158065 CA_CKDIV4_EN = 0
2160 12:47:10.158147 CA_PREDIV_EN = 0
2161 12:47:10.161501 PH8_DLY = 17
2162 12:47:10.164924 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2163 12:47:10.168154 DQ_AAMCK_DIV = 4
2164 12:47:10.171646 CA_AAMCK_DIV = 4
2165 12:47:10.174855 CA_ADMCK_DIV = 4
2166 12:47:10.174936 DQ_TRACK_CA_EN = 0
2167 12:47:10.178404 CA_PICK = 1200
2168 12:47:10.181671 CA_MCKIO = 1200
2169 12:47:10.184854 MCKIO_SEMI = 0
2170 12:47:10.188520 PLL_FREQ = 2366
2171 12:47:10.191733 DQ_UI_PI_RATIO = 32
2172 12:47:10.194842 CA_UI_PI_RATIO = 0
2173 12:47:10.198281 ===================================
2174 12:47:10.201400 ===================================
2175 12:47:10.201482 memory_type:LPDDR4
2176 12:47:10.205256 GP_NUM : 10
2177 12:47:10.208149 SRAM_EN : 1
2178 12:47:10.208229 MD32_EN : 0
2179 12:47:10.211665 ===================================
2180 12:47:10.214930 [ANA_INIT] >>>>>>>>>>>>>>
2181 12:47:10.218970 <<<<<< [CONFIGURE PHASE]: ANA_TX
2182 12:47:10.221540 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2183 12:47:10.225273 ===================================
2184 12:47:10.228531 data_rate = 2400,PCW = 0X5b00
2185 12:47:10.231341 ===================================
2186 12:47:10.234877 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2187 12:47:10.238218 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2188 12:47:10.245188 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2189 12:47:10.248308 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2190 12:47:10.251703 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2191 12:47:10.255197 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2192 12:47:10.258501 [ANA_INIT] flow start
2193 12:47:10.261534 [ANA_INIT] PLL >>>>>>>>
2194 12:47:10.261607 [ANA_INIT] PLL <<<<<<<<
2195 12:47:10.264945 [ANA_INIT] MIDPI >>>>>>>>
2196 12:47:10.268444 [ANA_INIT] MIDPI <<<<<<<<
2197 12:47:10.268516 [ANA_INIT] DLL >>>>>>>>
2198 12:47:10.271937 [ANA_INIT] DLL <<<<<<<<
2199 12:47:10.275183 [ANA_INIT] flow end
2200 12:47:10.278153 ============ LP4 DIFF to SE enter ============
2201 12:47:10.282003 ============ LP4 DIFF to SE exit ============
2202 12:47:10.284982 [ANA_INIT] <<<<<<<<<<<<<
2203 12:47:10.288370 [Flow] Enable top DCM control >>>>>
2204 12:47:10.291579 [Flow] Enable top DCM control <<<<<
2205 12:47:10.295328 Enable DLL master slave shuffle
2206 12:47:10.298128 ==============================================================
2207 12:47:10.301625 Gating Mode config
2208 12:47:10.308117 ==============================================================
2209 12:47:10.308216 Config description:
2210 12:47:10.318287 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2211 12:47:10.324860 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2212 12:47:10.328266 SELPH_MODE 0: By rank 1: By Phase
2213 12:47:10.335316 ==============================================================
2214 12:47:10.338392 GAT_TRACK_EN = 1
2215 12:47:10.341743 RX_GATING_MODE = 2
2216 12:47:10.344935 RX_GATING_TRACK_MODE = 2
2217 12:47:10.348261 SELPH_MODE = 1
2218 12:47:10.351538 PICG_EARLY_EN = 1
2219 12:47:10.351609 VALID_LAT_VALUE = 1
2220 12:47:10.358434 ==============================================================
2221 12:47:10.361732 Enter into Gating configuration >>>>
2222 12:47:10.365052 Exit from Gating configuration <<<<
2223 12:47:10.368186 Enter into DVFS_PRE_config >>>>>
2224 12:47:10.378058 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2225 12:47:10.381434 Exit from DVFS_PRE_config <<<<<
2226 12:47:10.385280 Enter into PICG configuration >>>>
2227 12:47:10.388171 Exit from PICG configuration <<<<
2228 12:47:10.391512 [RX_INPUT] configuration >>>>>
2229 12:47:10.395010 [RX_INPUT] configuration <<<<<
2230 12:47:10.398409 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2231 12:47:10.404774 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2232 12:47:10.411633 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2233 12:47:10.418065 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2234 12:47:10.424858 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2235 12:47:10.431645 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2236 12:47:10.434921 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2237 12:47:10.438553 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2238 12:47:10.441267 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2239 12:47:10.445510 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2240 12:47:10.451282 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2241 12:47:10.455107 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2242 12:47:10.458363 ===================================
2243 12:47:10.461340 LPDDR4 DRAM CONFIGURATION
2244 12:47:10.464561 ===================================
2245 12:47:10.464643 EX_ROW_EN[0] = 0x0
2246 12:47:10.468047 EX_ROW_EN[1] = 0x0
2247 12:47:10.468129 LP4Y_EN = 0x0
2248 12:47:10.471422 WORK_FSP = 0x0
2249 12:47:10.471504 WL = 0x4
2250 12:47:10.474700 RL = 0x4
2251 12:47:10.474781 BL = 0x2
2252 12:47:10.478219 RPST = 0x0
2253 12:47:10.478301 RD_PRE = 0x0
2254 12:47:10.481556 WR_PRE = 0x1
2255 12:47:10.485367 WR_PST = 0x0
2256 12:47:10.485448 DBI_WR = 0x0
2257 12:47:10.487998 DBI_RD = 0x0
2258 12:47:10.488079 OTF = 0x1
2259 12:47:10.491480 ===================================
2260 12:47:10.495011 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2261 12:47:10.498251 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2262 12:47:10.504573 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2263 12:47:10.507870 ===================================
2264 12:47:10.511649 LPDDR4 DRAM CONFIGURATION
2265 12:47:10.514815 ===================================
2266 12:47:10.514889 EX_ROW_EN[0] = 0x10
2267 12:47:10.518245 EX_ROW_EN[1] = 0x0
2268 12:47:10.518347 LP4Y_EN = 0x0
2269 12:47:10.521429 WORK_FSP = 0x0
2270 12:47:10.521504 WL = 0x4
2271 12:47:10.524808 RL = 0x4
2272 12:47:10.524909 BL = 0x2
2273 12:47:10.527991 RPST = 0x0
2274 12:47:10.528061 RD_PRE = 0x0
2275 12:47:10.531543 WR_PRE = 0x1
2276 12:47:10.531612 WR_PST = 0x0
2277 12:47:10.534935 DBI_WR = 0x0
2278 12:47:10.535031 DBI_RD = 0x0
2279 12:47:10.538297 OTF = 0x1
2280 12:47:10.541201 ===================================
2281 12:47:10.547963 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2282 12:47:10.548039 ==
2283 12:47:10.551563 Dram Type= 6, Freq= 0, CH_0, rank 0
2284 12:47:10.554452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2285 12:47:10.554557 ==
2286 12:47:10.558239 [Duty_Offset_Calibration]
2287 12:47:10.558328 B0:2 B1:0 CA:3
2288 12:47:10.558390
2289 12:47:10.561482 [DutyScan_Calibration_Flow] k_type=0
2290 12:47:10.572206
2291 12:47:10.572281 ==CLK 0==
2292 12:47:10.575062 Final CLK duty delay cell = 0
2293 12:47:10.578486 [0] MAX Duty = 5031%(X100), DQS PI = 12
2294 12:47:10.581787 [0] MIN Duty = 4906%(X100), DQS PI = 54
2295 12:47:10.581861 [0] AVG Duty = 4968%(X100)
2296 12:47:10.585188
2297 12:47:10.588600 CH0 CLK Duty spec in!! Max-Min= 125%
2298 12:47:10.591976 [DutyScan_Calibration_Flow] ====Done====
2299 12:47:10.592052
2300 12:47:10.595168 [DutyScan_Calibration_Flow] k_type=1
2301 12:47:10.611071
2302 12:47:10.611160 ==DQS 0 ==
2303 12:47:10.614463 Final DQS duty delay cell = 0
2304 12:47:10.617977 [0] MAX Duty = 5062%(X100), DQS PI = 14
2305 12:47:10.620979 [0] MIN Duty = 4907%(X100), DQS PI = 46
2306 12:47:10.621068 [0] AVG Duty = 4984%(X100)
2307 12:47:10.624499
2308 12:47:10.624587 ==DQS 1 ==
2309 12:47:10.628095 Final DQS duty delay cell = 0
2310 12:47:10.631328 [0] MAX Duty = 5125%(X100), DQS PI = 34
2311 12:47:10.634824 [0] MIN Duty = 5031%(X100), DQS PI = 0
2312 12:47:10.634895 [0] AVG Duty = 5078%(X100)
2313 12:47:10.638236
2314 12:47:10.641081 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2315 12:47:10.641151
2316 12:47:10.644449 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2317 12:47:10.648082 [DutyScan_Calibration_Flow] ====Done====
2318 12:47:10.648151
2319 12:47:10.651231 [DutyScan_Calibration_Flow] k_type=3
2320 12:47:10.668433
2321 12:47:10.668504 ==DQM 0 ==
2322 12:47:10.671796 Final DQM duty delay cell = 0
2323 12:47:10.675189 [0] MAX Duty = 5124%(X100), DQS PI = 28
2324 12:47:10.678584 [0] MIN Duty = 4907%(X100), DQS PI = 0
2325 12:47:10.678656 [0] AVG Duty = 5015%(X100)
2326 12:47:10.682012
2327 12:47:10.682095 ==DQM 1 ==
2328 12:47:10.684965 Final DQM duty delay cell = 4
2329 12:47:10.688423 [4] MAX Duty = 5124%(X100), DQS PI = 50
2330 12:47:10.691702 [4] MIN Duty = 5000%(X100), DQS PI = 30
2331 12:47:10.691806 [4] AVG Duty = 5062%(X100)
2332 12:47:10.695007
2333 12:47:10.698269 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2334 12:47:10.698342
2335 12:47:10.701439 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2336 12:47:10.705001 [DutyScan_Calibration_Flow] ====Done====
2337 12:47:10.705096
2338 12:47:10.708582 [DutyScan_Calibration_Flow] k_type=2
2339 12:47:10.723494
2340 12:47:10.723595 ==DQ 0 ==
2341 12:47:10.726629 Final DQ duty delay cell = -4
2342 12:47:10.729958 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2343 12:47:10.733501 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2344 12:47:10.737002 [-4] AVG Duty = 4969%(X100)
2345 12:47:10.737099
2346 12:47:10.737187 ==DQ 1 ==
2347 12:47:10.739979 Final DQ duty delay cell = -4
2348 12:47:10.743138 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2349 12:47:10.746559 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2350 12:47:10.750148 [-4] AVG Duty = 4938%(X100)
2351 12:47:10.750218
2352 12:47:10.753440 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2353 12:47:10.753509
2354 12:47:10.757083 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2355 12:47:10.760092 [DutyScan_Calibration_Flow] ====Done====
2356 12:47:10.760166 ==
2357 12:47:10.763360 Dram Type= 6, Freq= 0, CH_1, rank 0
2358 12:47:10.766266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2359 12:47:10.766338 ==
2360 12:47:10.769902 [Duty_Offset_Calibration]
2361 12:47:10.769971 B0:1 B1:-2 CA:0
2362 12:47:10.770034
2363 12:47:10.773110 [DutyScan_Calibration_Flow] k_type=0
2364 12:47:10.783625
2365 12:47:10.783694 ==CLK 0==
2366 12:47:10.787186 Final CLK duty delay cell = 0
2367 12:47:10.790481 [0] MAX Duty = 5062%(X100), DQS PI = 30
2368 12:47:10.793723 [0] MIN Duty = 4876%(X100), DQS PI = 0
2369 12:47:10.793798 [0] AVG Duty = 4969%(X100)
2370 12:47:10.793858
2371 12:47:10.796925 CH1 CLK Duty spec in!! Max-Min= 186%
2372 12:47:10.803868 [DutyScan_Calibration_Flow] ====Done====
2373 12:47:10.803948
2374 12:47:10.807389 [DutyScan_Calibration_Flow] k_type=1
2375 12:47:10.821981
2376 12:47:10.822078 ==DQS 0 ==
2377 12:47:10.825314 Final DQS duty delay cell = -4
2378 12:47:10.829082 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2379 12:47:10.832045 [-4] MIN Duty = 4907%(X100), DQS PI = 4
2380 12:47:10.835607 [-4] AVG Duty = 4953%(X100)
2381 12:47:10.835697
2382 12:47:10.835759 ==DQS 1 ==
2383 12:47:10.838727 Final DQS duty delay cell = 0
2384 12:47:10.841955 [0] MAX Duty = 5093%(X100), DQS PI = 0
2385 12:47:10.845294 [0] MIN Duty = 4875%(X100), DQS PI = 26
2386 12:47:10.848908 [0] AVG Duty = 4984%(X100)
2387 12:47:10.848982
2388 12:47:10.852359 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2389 12:47:10.852435
2390 12:47:10.855319 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2391 12:47:10.859220 [DutyScan_Calibration_Flow] ====Done====
2392 12:47:10.859291
2393 12:47:10.861988 [DutyScan_Calibration_Flow] k_type=3
2394 12:47:10.878571
2395 12:47:10.878668 ==DQM 0 ==
2396 12:47:10.882382 Final DQM duty delay cell = 0
2397 12:47:10.885597 [0] MAX Duty = 5031%(X100), DQS PI = 24
2398 12:47:10.888975 [0] MIN Duty = 4844%(X100), DQS PI = 52
2399 12:47:10.892321 [0] AVG Duty = 4937%(X100)
2400 12:47:10.892391
2401 12:47:10.892451 ==DQM 1 ==
2402 12:47:10.895605 Final DQM duty delay cell = 0
2403 12:47:10.898468 [0] MAX Duty = 5031%(X100), DQS PI = 36
2404 12:47:10.902327 [0] MIN Duty = 4907%(X100), DQS PI = 2
2405 12:47:10.905444 [0] AVG Duty = 4969%(X100)
2406 12:47:10.905540
2407 12:47:10.908700 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2408 12:47:10.908770
2409 12:47:10.912279 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2410 12:47:10.915232 [DutyScan_Calibration_Flow] ====Done====
2411 12:47:10.915302
2412 12:47:10.918453 [DutyScan_Calibration_Flow] k_type=2
2413 12:47:10.934915
2414 12:47:10.935016 ==DQ 0 ==
2415 12:47:10.938352 Final DQ duty delay cell = 0
2416 12:47:10.941816 [0] MAX Duty = 5093%(X100), DQS PI = 20
2417 12:47:10.944995 [0] MIN Duty = 4938%(X100), DQS PI = 54
2418 12:47:10.945110 [0] AVG Duty = 5015%(X100)
2419 12:47:10.948578
2420 12:47:10.948653 ==DQ 1 ==
2421 12:47:10.952079 Final DQ duty delay cell = 0
2422 12:47:10.955365 [0] MAX Duty = 5125%(X100), DQS PI = 36
2423 12:47:10.958658 [0] MIN Duty = 4969%(X100), DQS PI = 26
2424 12:47:10.958731 [0] AVG Duty = 5047%(X100)
2425 12:47:10.958812
2426 12:47:10.962079 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2427 12:47:10.965153
2428 12:47:10.968325 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2429 12:47:10.971655 [DutyScan_Calibration_Flow] ====Done====
2430 12:47:10.975118 nWR fixed to 30
2431 12:47:10.975264 [ModeRegInit_LP4] CH0 RK0
2432 12:47:10.978795 [ModeRegInit_LP4] CH0 RK1
2433 12:47:10.981738 [ModeRegInit_LP4] CH1 RK0
2434 12:47:10.981845 [ModeRegInit_LP4] CH1 RK1
2435 12:47:10.985074 match AC timing 7
2436 12:47:10.988320 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2437 12:47:10.992084 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2438 12:47:10.998377 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2439 12:47:11.001910 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2440 12:47:11.008476 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2441 12:47:11.008687 ==
2442 12:47:11.012348 Dram Type= 6, Freq= 0, CH_0, rank 0
2443 12:47:11.015364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2444 12:47:11.015768 ==
2445 12:47:11.022082 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2446 12:47:11.025671 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2447 12:47:11.035261 [CA 0] Center 40 (10~71) winsize 62
2448 12:47:11.038711 [CA 1] Center 39 (9~70) winsize 62
2449 12:47:11.042047 [CA 2] Center 36 (6~66) winsize 61
2450 12:47:11.045707 [CA 3] Center 35 (5~66) winsize 62
2451 12:47:11.049042 [CA 4] Center 34 (4~65) winsize 62
2452 12:47:11.052014 [CA 5] Center 33 (3~63) winsize 61
2453 12:47:11.052562
2454 12:47:11.055281 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2455 12:47:11.055846
2456 12:47:11.058805 [CATrainingPosCal] consider 1 rank data
2457 12:47:11.062082 u2DelayCellTimex100 = 270/100 ps
2458 12:47:11.065375 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2459 12:47:11.072065 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2460 12:47:11.075530 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2461 12:47:11.079000 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2462 12:47:11.082730 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2463 12:47:11.085618 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2464 12:47:11.086041
2465 12:47:11.088764 CA PerBit enable=1, Macro0, CA PI delay=33
2466 12:47:11.089181
2467 12:47:11.092476 [CBTSetCACLKResult] CA Dly = 33
2468 12:47:11.092896 CS Dly: 7 (0~38)
2469 12:47:11.095738 ==
2470 12:47:11.096156 Dram Type= 6, Freq= 0, CH_0, rank 1
2471 12:47:11.102559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2472 12:47:11.102980 ==
2473 12:47:11.105455 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2474 12:47:11.112478 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2475 12:47:11.121430 [CA 0] Center 40 (10~70) winsize 61
2476 12:47:11.124879 [CA 1] Center 39 (9~70) winsize 62
2477 12:47:11.128060 [CA 2] Center 36 (6~66) winsize 61
2478 12:47:11.131453 [CA 3] Center 35 (5~66) winsize 62
2479 12:47:11.135294 [CA 4] Center 34 (3~65) winsize 63
2480 12:47:11.138690 [CA 5] Center 33 (3~64) winsize 62
2481 12:47:11.139318
2482 12:47:11.141976 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2483 12:47:11.142598
2484 12:47:11.144774 [CATrainingPosCal] consider 2 rank data
2485 12:47:11.148231 u2DelayCellTimex100 = 270/100 ps
2486 12:47:11.151534 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2487 12:47:11.158697 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2488 12:47:11.161815 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2489 12:47:11.165153 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2490 12:47:11.168536 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2491 12:47:11.171828 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2492 12:47:11.172283
2493 12:47:11.174764 CA PerBit enable=1, Macro0, CA PI delay=33
2494 12:47:11.175235
2495 12:47:11.178096 [CBTSetCACLKResult] CA Dly = 33
2496 12:47:11.178547 CS Dly: 8 (0~40)
2497 12:47:11.179026
2498 12:47:11.181496 ----->DramcWriteLeveling(PI) begin...
2499 12:47:11.184960 ==
2500 12:47:11.188499 Dram Type= 6, Freq= 0, CH_0, rank 0
2501 12:47:11.191869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2502 12:47:11.192334 ==
2503 12:47:11.195267 Write leveling (Byte 0): 33 => 33
2504 12:47:11.198032 Write leveling (Byte 1): 30 => 30
2505 12:47:11.201582 DramcWriteLeveling(PI) end<-----
2506 12:47:11.202019
2507 12:47:11.202485 ==
2508 12:47:11.205433 Dram Type= 6, Freq= 0, CH_0, rank 0
2509 12:47:11.208903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 12:47:11.209441 ==
2511 12:47:11.211950 [Gating] SW mode calibration
2512 12:47:11.218418 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2513 12:47:11.225416 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2514 12:47:11.228519 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2515 12:47:11.231256 0 15 4 | B1->B0 | 2525 3232 | 1 1 | (0 0) (1 1)
2516 12:47:11.235034 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 12:47:11.241530 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 12:47:11.244737 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 12:47:11.248389 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 12:47:11.254603 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 12:47:11.258046 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2522 12:47:11.261617 1 0 0 | B1->B0 | 2f2f 2525 | 0 0 | (1 0) (0 0)
2523 12:47:11.268018 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 12:47:11.271418 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 12:47:11.274681 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 12:47:11.281548 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 12:47:11.284899 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 12:47:11.287959 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 12:47:11.294285 1 0 28 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
2530 12:47:11.297647 1 1 0 | B1->B0 | 2828 3434 | 1 0 | (1 1) (0 0)
2531 12:47:11.301009 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2532 12:47:11.307913 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 12:47:11.311258 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 12:47:11.314614 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 12:47:11.320765 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 12:47:11.324286 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 12:47:11.327617 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2538 12:47:11.334263 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2539 12:47:11.338028 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2540 12:47:11.340961 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 12:47:11.344350 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 12:47:11.351330 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 12:47:11.354540 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 12:47:11.357580 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 12:47:11.364340 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 12:47:11.367805 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 12:47:11.371313 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 12:47:11.377958 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 12:47:11.381338 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 12:47:11.384293 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 12:47:11.391061 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 12:47:11.394334 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 12:47:11.397786 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2554 12:47:11.404299 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2555 12:47:11.404375 Total UI for P1: 0, mck2ui 16
2556 12:47:11.411236 best dqsien dly found for B0: ( 1, 3, 28)
2557 12:47:11.414771 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2558 12:47:11.417507 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 12:47:11.421417 Total UI for P1: 0, mck2ui 16
2560 12:47:11.424093 best dqsien dly found for B1: ( 1, 4, 2)
2561 12:47:11.427721 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2562 12:47:11.431145 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2563 12:47:11.431227
2564 12:47:11.434079 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2565 12:47:11.441100 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2566 12:47:11.441182 [Gating] SW calibration Done
2567 12:47:11.441247 ==
2568 12:47:11.444328 Dram Type= 6, Freq= 0, CH_0, rank 0
2569 12:47:11.451128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2570 12:47:11.451210 ==
2571 12:47:11.451275 RX Vref Scan: 0
2572 12:47:11.451335
2573 12:47:11.454585 RX Vref 0 -> 0, step: 1
2574 12:47:11.454666
2575 12:47:11.457384 RX Delay -40 -> 252, step: 8
2576 12:47:11.461034 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2577 12:47:11.464195 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2578 12:47:11.467584 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2579 12:47:11.474276 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2580 12:47:11.477685 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2581 12:47:11.481077 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2582 12:47:11.484442 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2583 12:47:11.487854 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2584 12:47:11.491356 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2585 12:47:11.497758 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2586 12:47:11.500922 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2587 12:47:11.504144 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2588 12:47:11.507659 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2589 12:47:11.510979 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2590 12:47:11.517861 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2591 12:47:11.520959 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2592 12:47:11.521033 ==
2593 12:47:11.524228 Dram Type= 6, Freq= 0, CH_0, rank 0
2594 12:47:11.527755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2595 12:47:11.527829 ==
2596 12:47:11.527894 DQS Delay:
2597 12:47:11.531232 DQS0 = 0, DQS1 = 0
2598 12:47:11.531303 DQM Delay:
2599 12:47:11.534304 DQM0 = 112, DQM1 = 102
2600 12:47:11.534374 DQ Delay:
2601 12:47:11.538146 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2602 12:47:11.541275 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2603 12:47:11.544435 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2604 12:47:11.548016 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2605 12:47:11.548092
2606 12:47:11.551261
2607 12:47:11.551359 ==
2608 12:47:11.554888 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 12:47:11.557498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 12:47:11.557571 ==
2611 12:47:11.557632
2612 12:47:11.557696
2613 12:47:11.561003 TX Vref Scan disable
2614 12:47:11.561073 == TX Byte 0 ==
2615 12:47:11.567267 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2616 12:47:11.571091 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2617 12:47:11.571170 == TX Byte 1 ==
2618 12:47:11.577324 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2619 12:47:11.581111 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2620 12:47:11.581202 ==
2621 12:47:11.583883 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 12:47:11.587507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 12:47:11.587585 ==
2624 12:47:11.599744 TX Vref=22, minBit 6, minWin=25, winSum=419
2625 12:47:11.603217 TX Vref=24, minBit 0, minWin=26, winSum=425
2626 12:47:11.606917 TX Vref=26, minBit 1, minWin=26, winSum=432
2627 12:47:11.609917 TX Vref=28, minBit 0, minWin=27, winSum=440
2628 12:47:11.613086 TX Vref=30, minBit 5, minWin=27, winSum=440
2629 12:47:11.619758 TX Vref=32, minBit 10, minWin=26, winSum=435
2630 12:47:11.623254 [TxChooseVref] Worse bit 0, Min win 27, Win sum 440, Final Vref 28
2631 12:47:11.623353
2632 12:47:11.626415 Final TX Range 1 Vref 28
2633 12:47:11.626486
2634 12:47:11.626554 ==
2635 12:47:11.630012 Dram Type= 6, Freq= 0, CH_0, rank 0
2636 12:47:11.633603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2637 12:47:11.633700 ==
2638 12:47:11.633792
2639 12:47:11.636499
2640 12:47:11.636569 TX Vref Scan disable
2641 12:47:11.639759 == TX Byte 0 ==
2642 12:47:11.643463 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2643 12:47:11.646543 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2644 12:47:11.649908 == TX Byte 1 ==
2645 12:47:11.653097 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2646 12:47:11.656589 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2647 12:47:11.656662
2648 12:47:11.659806 [DATLAT]
2649 12:47:11.659886 Freq=1200, CH0 RK0
2650 12:47:11.659951
2651 12:47:11.663447 DATLAT Default: 0xd
2652 12:47:11.663521 0, 0xFFFF, sum = 0
2653 12:47:11.666442 1, 0xFFFF, sum = 0
2654 12:47:11.666520 2, 0xFFFF, sum = 0
2655 12:47:11.670067 3, 0xFFFF, sum = 0
2656 12:47:11.670140 4, 0xFFFF, sum = 0
2657 12:47:11.673368 5, 0xFFFF, sum = 0
2658 12:47:11.673444 6, 0xFFFF, sum = 0
2659 12:47:11.676643 7, 0xFFFF, sum = 0
2660 12:47:11.680075 8, 0xFFFF, sum = 0
2661 12:47:11.680152 9, 0xFFFF, sum = 0
2662 12:47:11.682874 10, 0xFFFF, sum = 0
2663 12:47:11.682973 11, 0xFFFF, sum = 0
2664 12:47:11.686449 12, 0x0, sum = 1
2665 12:47:11.686525 13, 0x0, sum = 2
2666 12:47:11.689562 14, 0x0, sum = 3
2667 12:47:11.689638 15, 0x0, sum = 4
2668 12:47:11.689699 best_step = 13
2669 12:47:11.689757
2670 12:47:11.692933 ==
2671 12:47:11.696678 Dram Type= 6, Freq= 0, CH_0, rank 0
2672 12:47:11.699897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2673 12:47:11.699976 ==
2674 12:47:11.700066 RX Vref Scan: 1
2675 12:47:11.700154
2676 12:47:11.703131 Set Vref Range= 32 -> 127
2677 12:47:11.703226
2678 12:47:11.706577 RX Vref 32 -> 127, step: 1
2679 12:47:11.706672
2680 12:47:11.709878 RX Delay -37 -> 252, step: 4
2681 12:47:11.709975
2682 12:47:11.713221 Set Vref, RX VrefLevel [Byte0]: 32
2683 12:47:11.716588 [Byte1]: 32
2684 12:47:11.716664
2685 12:47:11.719981 Set Vref, RX VrefLevel [Byte0]: 33
2686 12:47:11.723440 [Byte1]: 33
2687 12:47:11.726303
2688 12:47:11.726375 Set Vref, RX VrefLevel [Byte0]: 34
2689 12:47:11.729597 [Byte1]: 34
2690 12:47:11.734609
2691 12:47:11.734685 Set Vref, RX VrefLevel [Byte0]: 35
2692 12:47:11.737786 [Byte1]: 35
2693 12:47:11.742408
2694 12:47:11.742478 Set Vref, RX VrefLevel [Byte0]: 36
2695 12:47:11.745741 [Byte1]: 36
2696 12:47:11.750742
2697 12:47:11.750814 Set Vref, RX VrefLevel [Byte0]: 37
2698 12:47:11.753785 [Byte1]: 37
2699 12:47:11.758403
2700 12:47:11.758478 Set Vref, RX VrefLevel [Byte0]: 38
2701 12:47:11.761877 [Byte1]: 38
2702 12:47:11.766638
2703 12:47:11.766714 Set Vref, RX VrefLevel [Byte0]: 39
2704 12:47:11.769442 [Byte1]: 39
2705 12:47:11.774884
2706 12:47:11.774983 Set Vref, RX VrefLevel [Byte0]: 40
2707 12:47:11.777447 [Byte1]: 40
2708 12:47:11.782487
2709 12:47:11.782559 Set Vref, RX VrefLevel [Byte0]: 41
2710 12:47:11.785886 [Byte1]: 41
2711 12:47:11.790343
2712 12:47:11.790433 Set Vref, RX VrefLevel [Byte0]: 42
2713 12:47:11.793760 [Byte1]: 42
2714 12:47:11.798303
2715 12:47:11.798376 Set Vref, RX VrefLevel [Byte0]: 43
2716 12:47:11.801687 [Byte1]: 43
2717 12:47:11.806575
2718 12:47:11.806651 Set Vref, RX VrefLevel [Byte0]: 44
2719 12:47:11.809663 [Byte1]: 44
2720 12:47:11.814575
2721 12:47:11.814650 Set Vref, RX VrefLevel [Byte0]: 45
2722 12:47:11.817409 [Byte1]: 45
2723 12:47:11.822290
2724 12:47:11.822374 Set Vref, RX VrefLevel [Byte0]: 46
2725 12:47:11.825570 [Byte1]: 46
2726 12:47:11.830633
2727 12:47:11.830707 Set Vref, RX VrefLevel [Byte0]: 47
2728 12:47:11.833759 [Byte1]: 47
2729 12:47:11.838538
2730 12:47:11.838609 Set Vref, RX VrefLevel [Byte0]: 48
2731 12:47:11.841864 [Byte1]: 48
2732 12:47:11.846360
2733 12:47:11.846440 Set Vref, RX VrefLevel [Byte0]: 49
2734 12:47:11.849869 [Byte1]: 49
2735 12:47:11.854213
2736 12:47:11.854312 Set Vref, RX VrefLevel [Byte0]: 50
2737 12:47:11.857487 [Byte1]: 50
2738 12:47:11.862395
2739 12:47:11.862467 Set Vref, RX VrefLevel [Byte0]: 51
2740 12:47:11.865848 [Byte1]: 51
2741 12:47:11.870322
2742 12:47:11.870408 Set Vref, RX VrefLevel [Byte0]: 52
2743 12:47:11.873888 [Byte1]: 52
2744 12:47:11.878536
2745 12:47:11.878609 Set Vref, RX VrefLevel [Byte0]: 53
2746 12:47:11.881992 [Byte1]: 53
2747 12:47:11.886379
2748 12:47:11.886476 Set Vref, RX VrefLevel [Byte0]: 54
2749 12:47:11.889853 [Byte1]: 54
2750 12:47:11.894338
2751 12:47:11.894413 Set Vref, RX VrefLevel [Byte0]: 55
2752 12:47:11.897736 [Byte1]: 55
2753 12:47:11.902387
2754 12:47:11.902457 Set Vref, RX VrefLevel [Byte0]: 56
2755 12:47:11.905704 [Byte1]: 56
2756 12:47:11.910567
2757 12:47:11.910663 Set Vref, RX VrefLevel [Byte0]: 57
2758 12:47:11.913801 [Byte1]: 57
2759 12:47:11.918287
2760 12:47:11.918356 Set Vref, RX VrefLevel [Byte0]: 58
2761 12:47:11.921944 [Byte1]: 58
2762 12:47:11.926260
2763 12:47:11.926331 Set Vref, RX VrefLevel [Byte0]: 59
2764 12:47:11.929581 [Byte1]: 59
2765 12:47:11.934393
2766 12:47:11.934461 Set Vref, RX VrefLevel [Byte0]: 60
2767 12:47:11.937424 [Byte1]: 60
2768 12:47:11.942527
2769 12:47:11.942608 Set Vref, RX VrefLevel [Byte0]: 61
2770 12:47:11.945876 [Byte1]: 61
2771 12:47:11.950267
2772 12:47:11.950348 Set Vref, RX VrefLevel [Byte0]: 62
2773 12:47:11.953627 [Byte1]: 62
2774 12:47:11.958198
2775 12:47:11.958279 Set Vref, RX VrefLevel [Byte0]: 63
2776 12:47:11.961483 [Byte1]: 63
2777 12:47:11.966466
2778 12:47:11.966547 Set Vref, RX VrefLevel [Byte0]: 64
2779 12:47:11.969571 [Byte1]: 64
2780 12:47:11.974599
2781 12:47:11.974681 Set Vref, RX VrefLevel [Byte0]: 65
2782 12:47:11.977920 [Byte1]: 65
2783 12:47:11.982251
2784 12:47:11.982358 Set Vref, RX VrefLevel [Byte0]: 66
2785 12:47:11.985600 [Byte1]: 66
2786 12:47:11.990099
2787 12:47:11.990178 Set Vref, RX VrefLevel [Byte0]: 67
2788 12:47:11.993652 [Byte1]: 67
2789 12:47:11.998529
2790 12:47:11.998605 Set Vref, RX VrefLevel [Byte0]: 68
2791 12:47:12.001977 [Byte1]: 68
2792 12:47:12.006697
2793 12:47:12.006774 Set Vref, RX VrefLevel [Byte0]: 69
2794 12:47:12.009418 [Byte1]: 69
2795 12:47:12.014307
2796 12:47:12.014405 Set Vref, RX VrefLevel [Byte0]: 70
2797 12:47:12.017763 [Byte1]: 70
2798 12:47:12.022478
2799 12:47:12.022589 Set Vref, RX VrefLevel [Byte0]: 71
2800 12:47:12.025883 [Byte1]: 71
2801 12:47:12.030299
2802 12:47:12.030397 Set Vref, RX VrefLevel [Byte0]: 72
2803 12:47:12.033642 [Byte1]: 72
2804 12:47:12.038284
2805 12:47:12.038389 Set Vref, RX VrefLevel [Byte0]: 73
2806 12:47:12.041422 [Byte1]: 73
2807 12:47:12.046802
2808 12:47:12.046899 Set Vref, RX VrefLevel [Byte0]: 74
2809 12:47:12.049899 [Byte1]: 74
2810 12:47:12.054515
2811 12:47:12.054611 Set Vref, RX VrefLevel [Byte0]: 75
2812 12:47:12.057978 [Byte1]: 75
2813 12:47:12.062196
2814 12:47:12.062271 Set Vref, RX VrefLevel [Byte0]: 76
2815 12:47:12.065686 [Byte1]: 76
2816 12:47:12.070240
2817 12:47:12.070315 Final RX Vref Byte 0 = 62 to rank0
2818 12:47:12.073622 Final RX Vref Byte 1 = 56 to rank0
2819 12:47:12.076964 Final RX Vref Byte 0 = 62 to rank1
2820 12:47:12.080574 Final RX Vref Byte 1 = 56 to rank1==
2821 12:47:12.083612 Dram Type= 6, Freq= 0, CH_0, rank 0
2822 12:47:12.090335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 12:47:12.090416 ==
2824 12:47:12.090479 DQS Delay:
2825 12:47:12.090538 DQS0 = 0, DQS1 = 0
2826 12:47:12.093987 DQM Delay:
2827 12:47:12.094057 DQM0 = 112, DQM1 = 102
2828 12:47:12.096764 DQ Delay:
2829 12:47:12.100163 DQ0 =110, DQ1 =114, DQ2 =110, DQ3 =108
2830 12:47:12.103607 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2831 12:47:12.107021 DQ8 =94, DQ9 =86, DQ10 =104, DQ11 =94
2832 12:47:12.110392 DQ12 =108, DQ13 =108, DQ14 =116, DQ15 =110
2833 12:47:12.110465
2834 12:47:12.110526
2835 12:47:12.117209 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2836 12:47:12.120175 CH0 RK0: MR19=303, MR18=FBFB
2837 12:47:12.127033 CH0_RK0: MR19=0x303, MR18=0xFBFB, DQSOSC=412, MR23=63, INC=38, DEC=25
2838 12:47:12.127108
2839 12:47:12.130452 ----->DramcWriteLeveling(PI) begin...
2840 12:47:12.130524 ==
2841 12:47:12.133847 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 12:47:12.137077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 12:47:12.140558 ==
2844 12:47:12.140633 Write leveling (Byte 0): 33 => 33
2845 12:47:12.143585 Write leveling (Byte 1): 31 => 31
2846 12:47:12.147041 DramcWriteLeveling(PI) end<-----
2847 12:47:12.147113
2848 12:47:12.147173 ==
2849 12:47:12.150425 Dram Type= 6, Freq= 0, CH_0, rank 1
2850 12:47:12.157001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2851 12:47:12.157084 ==
2852 12:47:12.157148 [Gating] SW mode calibration
2853 12:47:12.166857 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2854 12:47:12.170189 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2855 12:47:12.173533 0 15 0 | B1->B0 | 2727 3333 | 1 1 | (1 1) (1 1)
2856 12:47:12.180608 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 12:47:12.183704 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 12:47:12.187083 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 12:47:12.193885 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 12:47:12.197017 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 12:47:12.200122 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2862 12:47:12.206773 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
2863 12:47:12.210483 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 12:47:12.213399 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 12:47:12.220241 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 12:47:12.223727 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 12:47:12.227188 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 12:47:12.233531 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 12:47:12.236918 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2870 12:47:12.240271 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2871 12:47:12.247064 1 1 0 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
2872 12:47:12.250540 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 12:47:12.253325 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 12:47:12.256585 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 12:47:12.263304 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 12:47:12.266640 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 12:47:12.270233 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2878 12:47:12.276678 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2879 12:47:12.280022 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 12:47:12.283384 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 12:47:12.290253 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 12:47:12.294592 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 12:47:12.297009 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 12:47:12.303687 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 12:47:12.307099 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 12:47:12.310246 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 12:47:12.317012 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 12:47:12.320541 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 12:47:12.323950 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 12:47:12.330350 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 12:47:12.333724 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 12:47:12.336626 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 12:47:12.343490 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 12:47:12.346795 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2895 12:47:12.350069 Total UI for P1: 0, mck2ui 16
2896 12:47:12.353660 best dqsien dly found for B0: ( 1, 3, 26)
2897 12:47:12.357035 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2898 12:47:12.359962 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 12:47:12.363313 Total UI for P1: 0, mck2ui 16
2900 12:47:12.366633 best dqsien dly found for B1: ( 1, 4, 0)
2901 12:47:12.370102 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2902 12:47:12.373441 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2903 12:47:12.376949
2904 12:47:12.379849 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2905 12:47:12.383280 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2906 12:47:12.386764 [Gating] SW calibration Done
2907 12:47:12.386836 ==
2908 12:47:12.390258 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 12:47:12.393150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 12:47:12.393239 ==
2911 12:47:12.393303 RX Vref Scan: 0
2912 12:47:12.396887
2913 12:47:12.396957 RX Vref 0 -> 0, step: 1
2914 12:47:12.397023
2915 12:47:12.399857 RX Delay -40 -> 252, step: 8
2916 12:47:12.403231 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2917 12:47:12.406635 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2918 12:47:12.413208 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2919 12:47:12.416484 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2920 12:47:12.419787 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2921 12:47:12.423549 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2922 12:47:12.426628 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2923 12:47:12.430062 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2924 12:47:12.437196 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2925 12:47:12.440081 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2926 12:47:12.443360 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2927 12:47:12.446851 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2928 12:47:12.450143 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2929 12:47:12.456965 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2930 12:47:12.460345 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2931 12:47:12.463197 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2932 12:47:12.463278 ==
2933 12:47:12.467116 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 12:47:12.470448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 12:47:12.470531 ==
2936 12:47:12.473183 DQS Delay:
2937 12:47:12.473265 DQS0 = 0, DQS1 = 0
2938 12:47:12.476723 DQM Delay:
2939 12:47:12.476805 DQM0 = 111, DQM1 = 101
2940 12:47:12.476870 DQ Delay:
2941 12:47:12.483542 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2942 12:47:12.486841 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2943 12:47:12.490549 DQ8 =91, DQ9 =83, DQ10 =107, DQ11 =95
2944 12:47:12.493887 DQ12 =107, DQ13 =111, DQ14 =111, DQ15 =107
2945 12:47:12.493969
2946 12:47:12.494032
2947 12:47:12.494091 ==
2948 12:47:12.496707 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 12:47:12.500080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 12:47:12.500162 ==
2951 12:47:12.500226
2952 12:47:12.500286
2953 12:47:12.503407 TX Vref Scan disable
2954 12:47:12.503523 == TX Byte 0 ==
2955 12:47:12.510331 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2956 12:47:12.513627 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2957 12:47:12.513709 == TX Byte 1 ==
2958 12:47:12.520394 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2959 12:47:12.523535 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2960 12:47:12.523617 ==
2961 12:47:12.526894 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 12:47:12.530395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 12:47:12.530477 ==
2964 12:47:12.543244 TX Vref=22, minBit 0, minWin=26, winSum=429
2965 12:47:12.546584 TX Vref=24, minBit 0, minWin=26, winSum=429
2966 12:47:12.550145 TX Vref=26, minBit 3, minWin=26, winSum=437
2967 12:47:12.553014 TX Vref=28, minBit 1, minWin=26, winSum=442
2968 12:47:12.556477 TX Vref=30, minBit 1, minWin=27, winSum=444
2969 12:47:12.562991 TX Vref=32, minBit 13, minWin=26, winSum=442
2970 12:47:12.566812 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 30
2971 12:47:12.566893
2972 12:47:12.569828 Final TX Range 1 Vref 30
2973 12:47:12.569910
2974 12:47:12.569997 ==
2975 12:47:12.573233 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 12:47:12.576295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 12:47:12.576370 ==
2978 12:47:12.579661
2979 12:47:12.579743
2980 12:47:12.579806 TX Vref Scan disable
2981 12:47:12.583177 == TX Byte 0 ==
2982 12:47:12.586558 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2983 12:47:12.589950 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2984 12:47:12.593445 == TX Byte 1 ==
2985 12:47:12.596356 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2986 12:47:12.599606 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2987 12:47:12.602873
2988 12:47:12.602953 [DATLAT]
2989 12:47:12.603018 Freq=1200, CH0 RK1
2990 12:47:12.603078
2991 12:47:12.606197 DATLAT Default: 0xd
2992 12:47:12.606312 0, 0xFFFF, sum = 0
2993 12:47:12.609798 1, 0xFFFF, sum = 0
2994 12:47:12.609898 2, 0xFFFF, sum = 0
2995 12:47:12.613127 3, 0xFFFF, sum = 0
2996 12:47:12.613200 4, 0xFFFF, sum = 0
2997 12:47:12.616540 5, 0xFFFF, sum = 0
2998 12:47:12.619848 6, 0xFFFF, sum = 0
2999 12:47:12.619919 7, 0xFFFF, sum = 0
3000 12:47:12.623104 8, 0xFFFF, sum = 0
3001 12:47:12.623202 9, 0xFFFF, sum = 0
3002 12:47:12.626512 10, 0xFFFF, sum = 0
3003 12:47:12.626611 11, 0xFFFF, sum = 0
3004 12:47:12.629989 12, 0x0, sum = 1
3005 12:47:12.630063 13, 0x0, sum = 2
3006 12:47:12.633134 14, 0x0, sum = 3
3007 12:47:12.633205 15, 0x0, sum = 4
3008 12:47:12.633267 best_step = 13
3009 12:47:12.633324
3010 12:47:12.636277 ==
3011 12:47:12.639663 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 12:47:12.643141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 12:47:12.643215 ==
3014 12:47:12.643311 RX Vref Scan: 0
3015 12:47:12.643419
3016 12:47:12.646683 RX Vref 0 -> 0, step: 1
3017 12:47:12.646779
3018 12:47:12.650050 RX Delay -37 -> 252, step: 4
3019 12:47:12.653402 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3020 12:47:12.659893 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3021 12:47:12.663532 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3022 12:47:12.666684 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3023 12:47:12.669648 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3024 12:47:12.673106 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3025 12:47:12.676529 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3026 12:47:12.683549 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3027 12:47:12.686746 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3028 12:47:12.690001 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3029 12:47:12.693508 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3030 12:47:12.696552 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3031 12:47:12.703613 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3032 12:47:12.706893 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3033 12:47:12.710342 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3034 12:47:12.713200 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3035 12:47:12.713278 ==
3036 12:47:12.716576 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 12:47:12.719844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 12:47:12.723202 ==
3039 12:47:12.723304 DQS Delay:
3040 12:47:12.723424 DQS0 = 0, DQS1 = 0
3041 12:47:12.727000 DQM Delay:
3042 12:47:12.727102 DQM0 = 111, DQM1 = 102
3043 12:47:12.729919 DQ Delay:
3044 12:47:12.733342 DQ0 =108, DQ1 =112, DQ2 =110, DQ3 =108
3045 12:47:12.736841 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3046 12:47:12.739783 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3047 12:47:12.743073 DQ12 =110, DQ13 =108, DQ14 =116, DQ15 =110
3048 12:47:12.743186
3049 12:47:12.743294
3050 12:47:12.750107 [DQSOSCAuto] RK1, (LSB)MR18= 0x15fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 401 ps
3051 12:47:12.753184 CH0 RK1: MR19=403, MR18=15FC
3052 12:47:12.759934 CH0_RK1: MR19=0x403, MR18=0x15FC, DQSOSC=401, MR23=63, INC=40, DEC=27
3053 12:47:12.763342 [RxdqsGatingPostProcess] freq 1200
3054 12:47:12.769580 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3055 12:47:12.773402 best DQS0 dly(2T, 0.5T) = (0, 11)
3056 12:47:12.773517 best DQS1 dly(2T, 0.5T) = (0, 12)
3057 12:47:12.776842 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3058 12:47:12.780083 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3059 12:47:12.783191 best DQS0 dly(2T, 0.5T) = (0, 11)
3060 12:47:12.786575 best DQS1 dly(2T, 0.5T) = (0, 12)
3061 12:47:12.790005 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3062 12:47:12.793377 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3063 12:47:12.796511 Pre-setting of DQS Precalculation
3064 12:47:12.803167 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3065 12:47:12.803248 ==
3066 12:47:12.806552 Dram Type= 6, Freq= 0, CH_1, rank 0
3067 12:47:12.809810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 12:47:12.809897 ==
3069 12:47:12.812987 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3070 12:47:12.819885 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3071 12:47:12.828972 [CA 0] Center 37 (7~67) winsize 61
3072 12:47:12.832696 [CA 1] Center 38 (8~68) winsize 61
3073 12:47:12.835595 [CA 2] Center 34 (4~64) winsize 61
3074 12:47:12.839160 [CA 3] Center 33 (3~64) winsize 62
3075 12:47:12.842576 [CA 4] Center 34 (4~64) winsize 61
3076 12:47:12.845964 [CA 5] Center 33 (3~63) winsize 61
3077 12:47:12.846045
3078 12:47:12.849210 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3079 12:47:12.849291
3080 12:47:12.852568 [CATrainingPosCal] consider 1 rank data
3081 12:47:12.855703 u2DelayCellTimex100 = 270/100 ps
3082 12:47:12.859350 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3083 12:47:12.862664 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3084 12:47:12.869176 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3085 12:47:12.872517 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3086 12:47:12.875823 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3087 12:47:12.879224 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3088 12:47:12.879327
3089 12:47:12.882473 CA PerBit enable=1, Macro0, CA PI delay=33
3090 12:47:12.882550
3091 12:47:12.886072 [CBTSetCACLKResult] CA Dly = 33
3092 12:47:12.886148 CS Dly: 5 (0~36)
3093 12:47:12.886229 ==
3094 12:47:12.889229 Dram Type= 6, Freq= 0, CH_1, rank 1
3095 12:47:12.896005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 12:47:12.896108 ==
3097 12:47:12.899315 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3098 12:47:12.905617 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3099 12:47:12.915461 [CA 0] Center 37 (7~68) winsize 62
3100 12:47:12.918194 [CA 1] Center 37 (7~68) winsize 62
3101 12:47:12.921679 [CA 2] Center 35 (5~65) winsize 61
3102 12:47:12.924540 [CA 3] Center 33 (3~64) winsize 62
3103 12:47:12.928258 [CA 4] Center 34 (4~65) winsize 62
3104 12:47:12.931079 [CA 5] Center 32 (2~63) winsize 62
3105 12:47:12.931155
3106 12:47:12.934565 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3107 12:47:12.934637
3108 12:47:12.937758 [CATrainingPosCal] consider 2 rank data
3109 12:47:12.941247 u2DelayCellTimex100 = 270/100 ps
3110 12:47:12.944752 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3111 12:47:12.951104 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3112 12:47:12.954558 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3113 12:47:12.957842 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3114 12:47:12.960937 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3115 12:47:12.964699 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3116 12:47:12.964777
3117 12:47:12.967516 CA PerBit enable=1, Macro0, CA PI delay=33
3118 12:47:12.967612
3119 12:47:12.971043 [CBTSetCACLKResult] CA Dly = 33
3120 12:47:12.971116 CS Dly: 7 (0~40)
3121 12:47:12.974373
3122 12:47:12.977609 ----->DramcWriteLeveling(PI) begin...
3123 12:47:12.977719 ==
3124 12:47:12.980862 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 12:47:12.984221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 12:47:12.984298 ==
3127 12:47:12.987702 Write leveling (Byte 0): 26 => 26
3128 12:47:12.990883 Write leveling (Byte 1): 29 => 29
3129 12:47:12.994174 DramcWriteLeveling(PI) end<-----
3130 12:47:12.994275
3131 12:47:12.994373 ==
3132 12:47:12.997625 Dram Type= 6, Freq= 0, CH_1, rank 0
3133 12:47:13.000915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 12:47:13.001019 ==
3135 12:47:13.004440 [Gating] SW mode calibration
3136 12:47:13.010795 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3137 12:47:13.018159 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3138 12:47:13.021215 0 15 0 | B1->B0 | 2a2a 2525 | 1 1 | (1 1) (0 0)
3139 12:47:13.024613 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 12:47:13.031088 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 12:47:13.034759 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 12:47:13.037706 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 12:47:13.040900 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 12:47:13.047678 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
3145 12:47:13.051465 0 15 28 | B1->B0 | 2f2f 3131 | 0 0 | (0 1) (0 1)
3146 12:47:13.054152 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3147 12:47:13.060870 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 12:47:13.064305 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 12:47:13.067492 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 12:47:13.074382 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 12:47:13.077679 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 12:47:13.080776 1 0 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3153 12:47:13.087497 1 0 28 | B1->B0 | 4040 3636 | 0 0 | (0 0) (0 0)
3154 12:47:13.091139 1 1 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3155 12:47:13.094351 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 12:47:13.101063 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 12:47:13.104495 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 12:47:13.107807 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 12:47:13.114051 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 12:47:13.117380 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 12:47:13.120626 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 12:47:13.127545 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 12:47:13.131167 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 12:47:13.134322 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 12:47:13.137412 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 12:47:13.144601 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 12:47:13.147813 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 12:47:13.150977 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 12:47:13.157398 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 12:47:13.160737 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 12:47:13.164674 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 12:47:13.170713 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 12:47:13.173995 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 12:47:13.177645 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 12:47:13.184482 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 12:47:13.187886 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 12:47:13.191138 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3178 12:47:13.197466 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 12:47:13.197569 Total UI for P1: 0, mck2ui 16
3180 12:47:13.204403 best dqsien dly found for B0: ( 1, 3, 28)
3181 12:47:13.204480 Total UI for P1: 0, mck2ui 16
3182 12:47:13.207568 best dqsien dly found for B1: ( 1, 3, 28)
3183 12:47:13.214276 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3184 12:47:13.217884 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3185 12:47:13.217955
3186 12:47:13.221202 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3187 12:47:13.224630 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3188 12:47:13.227555 [Gating] SW calibration Done
3189 12:47:13.227654 ==
3190 12:47:13.230985 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 12:47:13.234506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 12:47:13.234603 ==
3193 12:47:13.237386 RX Vref Scan: 0
3194 12:47:13.237480
3195 12:47:13.237567 RX Vref 0 -> 0, step: 1
3196 12:47:13.237651
3197 12:47:13.240796 RX Delay -40 -> 252, step: 8
3198 12:47:13.244437 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3199 12:47:13.250756 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3200 12:47:13.254172 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3201 12:47:13.257421 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3202 12:47:13.261117 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3203 12:47:13.264402 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3204 12:47:13.267841 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3205 12:47:13.274353 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3206 12:47:13.277722 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3207 12:47:13.280625 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3208 12:47:13.284218 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3209 12:47:13.287539 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3210 12:47:13.294490 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3211 12:47:13.297776 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3212 12:47:13.301204 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3213 12:47:13.304583 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3214 12:47:13.304669 ==
3215 12:47:13.307849 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 12:47:13.314276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 12:47:13.314382 ==
3218 12:47:13.314474 DQS Delay:
3219 12:47:13.314561 DQS0 = 0, DQS1 = 0
3220 12:47:13.317786 DQM Delay:
3221 12:47:13.317882 DQM0 = 114, DQM1 = 106
3222 12:47:13.321004 DQ Delay:
3223 12:47:13.324558 DQ0 =123, DQ1 =107, DQ2 =103, DQ3 =111
3224 12:47:13.327440 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3225 12:47:13.331082 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3226 12:47:13.334031 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3227 12:47:13.334112
3228 12:47:13.334195
3229 12:47:13.334274 ==
3230 12:47:13.337315 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 12:47:13.340826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 12:47:13.340926 ==
3233 12:47:13.344350
3234 12:47:13.344426
3235 12:47:13.344523 TX Vref Scan disable
3236 12:47:13.347790 == TX Byte 0 ==
3237 12:47:13.350789 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3238 12:47:13.354378 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3239 12:47:13.357650 == TX Byte 1 ==
3240 12:47:13.360925 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3241 12:47:13.364150 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3242 12:47:13.364225 ==
3243 12:47:13.367498 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 12:47:13.374218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 12:47:13.374321 ==
3246 12:47:13.384575 TX Vref=22, minBit 8, minWin=24, winSum=410
3247 12:47:13.388019 TX Vref=24, minBit 11, minWin=24, winSum=420
3248 12:47:13.391498 TX Vref=26, minBit 1, minWin=26, winSum=423
3249 12:47:13.394892 TX Vref=28, minBit 1, minWin=26, winSum=427
3250 12:47:13.398314 TX Vref=30, minBit 9, minWin=25, winSum=425
3251 12:47:13.405065 TX Vref=32, minBit 9, minWin=25, winSum=425
3252 12:47:13.407950 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
3253 12:47:13.408051
3254 12:47:13.411389 Final TX Range 1 Vref 28
3255 12:47:13.411478
3256 12:47:13.411557 ==
3257 12:47:13.414532 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 12:47:13.418348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 12:47:13.418451 ==
3260 12:47:13.418553
3261 12:47:13.421622
3262 12:47:13.421719 TX Vref Scan disable
3263 12:47:13.424948 == TX Byte 0 ==
3264 12:47:13.428508 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3265 12:47:13.431321 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3266 12:47:13.434954 == TX Byte 1 ==
3267 12:47:13.438380 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3268 12:47:13.441658 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3269 12:47:13.441761
3270 12:47:13.445113 [DATLAT]
3271 12:47:13.445185 Freq=1200, CH1 RK0
3272 12:47:13.445263
3273 12:47:13.448072 DATLAT Default: 0xd
3274 12:47:13.448170 0, 0xFFFF, sum = 0
3275 12:47:13.451508 1, 0xFFFF, sum = 0
3276 12:47:13.451607 2, 0xFFFF, sum = 0
3277 12:47:13.454905 3, 0xFFFF, sum = 0
3278 12:47:13.454980 4, 0xFFFF, sum = 0
3279 12:47:13.458036 5, 0xFFFF, sum = 0
3280 12:47:13.458140 6, 0xFFFF, sum = 0
3281 12:47:13.461680 7, 0xFFFF, sum = 0
3282 12:47:13.461782 8, 0xFFFF, sum = 0
3283 12:47:13.464762 9, 0xFFFF, sum = 0
3284 12:47:13.468086 10, 0xFFFF, sum = 0
3285 12:47:13.468186 11, 0xFFFF, sum = 0
3286 12:47:13.471265 12, 0x0, sum = 1
3287 12:47:13.471368 13, 0x0, sum = 2
3288 12:47:13.475045 14, 0x0, sum = 3
3289 12:47:13.475144 15, 0x0, sum = 4
3290 12:47:13.475232 best_step = 13
3291 12:47:13.475319
3292 12:47:13.477913 ==
3293 12:47:13.481372 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 12:47:13.485206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 12:47:13.485287 ==
3296 12:47:13.485351 RX Vref Scan: 1
3297 12:47:13.485410
3298 12:47:13.488816 Set Vref Range= 32 -> 127
3299 12:47:13.488897
3300 12:47:13.491704 RX Vref 32 -> 127, step: 1
3301 12:47:13.491785
3302 12:47:13.495244 RX Delay -21 -> 252, step: 4
3303 12:47:13.495325
3304 12:47:13.498094 Set Vref, RX VrefLevel [Byte0]: 32
3305 12:47:13.501693 [Byte1]: 32
3306 12:47:13.501774
3307 12:47:13.504969 Set Vref, RX VrefLevel [Byte0]: 33
3308 12:47:13.508242 [Byte1]: 33
3309 12:47:13.508323
3310 12:47:13.511666 Set Vref, RX VrefLevel [Byte0]: 34
3311 12:47:13.515157 [Byte1]: 34
3312 12:47:13.519121
3313 12:47:13.519201 Set Vref, RX VrefLevel [Byte0]: 35
3314 12:47:13.522226 [Byte1]: 35
3315 12:47:13.527185
3316 12:47:13.527265 Set Vref, RX VrefLevel [Byte0]: 36
3317 12:47:13.530062 [Byte1]: 36
3318 12:47:13.535033
3319 12:47:13.535114 Set Vref, RX VrefLevel [Byte0]: 37
3320 12:47:13.538255 [Byte1]: 37
3321 12:47:13.542981
3322 12:47:13.543061 Set Vref, RX VrefLevel [Byte0]: 38
3323 12:47:13.546142 [Byte1]: 38
3324 12:47:13.550895
3325 12:47:13.550975 Set Vref, RX VrefLevel [Byte0]: 39
3326 12:47:13.554425 [Byte1]: 39
3327 12:47:13.558821
3328 12:47:13.558901 Set Vref, RX VrefLevel [Byte0]: 40
3329 12:47:13.562267 [Byte1]: 40
3330 12:47:13.566473
3331 12:47:13.566553 Set Vref, RX VrefLevel [Byte0]: 41
3332 12:47:13.569695 [Byte1]: 41
3333 12:47:13.574724
3334 12:47:13.574804 Set Vref, RX VrefLevel [Byte0]: 42
3335 12:47:13.577958 [Byte1]: 42
3336 12:47:13.582532
3337 12:47:13.582612 Set Vref, RX VrefLevel [Byte0]: 43
3338 12:47:13.585897 [Byte1]: 43
3339 12:47:13.590109
3340 12:47:13.590189 Set Vref, RX VrefLevel [Byte0]: 44
3341 12:47:13.593992 [Byte1]: 44
3342 12:47:13.597977
3343 12:47:13.598082 Set Vref, RX VrefLevel [Byte0]: 45
3344 12:47:13.601475 [Byte1]: 45
3345 12:47:13.606099
3346 12:47:13.606171 Set Vref, RX VrefLevel [Byte0]: 46
3347 12:47:13.609503 [Byte1]: 46
3348 12:47:13.614050
3349 12:47:13.614145 Set Vref, RX VrefLevel [Byte0]: 47
3350 12:47:13.617346 [Byte1]: 47
3351 12:47:13.621911
3352 12:47:13.621981 Set Vref, RX VrefLevel [Byte0]: 48
3353 12:47:13.625255 [Byte1]: 48
3354 12:47:13.629904
3355 12:47:13.629993 Set Vref, RX VrefLevel [Byte0]: 49
3356 12:47:13.633128 [Byte1]: 49
3357 12:47:13.637851
3358 12:47:13.637925 Set Vref, RX VrefLevel [Byte0]: 50
3359 12:47:13.641128 [Byte1]: 50
3360 12:47:13.645663
3361 12:47:13.645757 Set Vref, RX VrefLevel [Byte0]: 51
3362 12:47:13.648951 [Byte1]: 51
3363 12:47:13.653506
3364 12:47:13.653602 Set Vref, RX VrefLevel [Byte0]: 52
3365 12:47:13.657000 [Byte1]: 52
3366 12:47:13.661513
3367 12:47:13.661608 Set Vref, RX VrefLevel [Byte0]: 53
3368 12:47:13.664845 [Byte1]: 53
3369 12:47:13.669397
3370 12:47:13.669497 Set Vref, RX VrefLevel [Byte0]: 54
3371 12:47:13.672866 [Byte1]: 54
3372 12:47:13.677137
3373 12:47:13.677231 Set Vref, RX VrefLevel [Byte0]: 55
3374 12:47:13.680489 [Byte1]: 55
3375 12:47:13.685672
3376 12:47:13.685772 Set Vref, RX VrefLevel [Byte0]: 56
3377 12:47:13.688509 [Byte1]: 56
3378 12:47:13.693564
3379 12:47:13.693637 Set Vref, RX VrefLevel [Byte0]: 57
3380 12:47:13.696933 [Byte1]: 57
3381 12:47:13.701505
3382 12:47:13.701604 Set Vref, RX VrefLevel [Byte0]: 58
3383 12:47:13.704702 [Byte1]: 58
3384 12:47:13.708880
3385 12:47:13.708951 Set Vref, RX VrefLevel [Byte0]: 59
3386 12:47:13.712361 [Byte1]: 59
3387 12:47:13.717232
3388 12:47:13.717316 Set Vref, RX VrefLevel [Byte0]: 60
3389 12:47:13.720657 [Byte1]: 60
3390 12:47:13.725264
3391 12:47:13.725361 Set Vref, RX VrefLevel [Byte0]: 61
3392 12:47:13.728135 [Byte1]: 61
3393 12:47:13.732789
3394 12:47:13.732888 Set Vref, RX VrefLevel [Byte0]: 62
3395 12:47:13.736336 [Byte1]: 62
3396 12:47:13.740787
3397 12:47:13.740869 Set Vref, RX VrefLevel [Byte0]: 63
3398 12:47:13.743872 [Byte1]: 63
3399 12:47:13.749157
3400 12:47:13.749238 Set Vref, RX VrefLevel [Byte0]: 64
3401 12:47:13.751892 [Byte1]: 64
3402 12:47:13.756911
3403 12:47:13.756992 Set Vref, RX VrefLevel [Byte0]: 65
3404 12:47:13.760136 [Byte1]: 65
3405 12:47:13.764619
3406 12:47:13.764700 Set Vref, RX VrefLevel [Byte0]: 66
3407 12:47:13.767880 [Byte1]: 66
3408 12:47:13.772314
3409 12:47:13.772396 Final RX Vref Byte 0 = 56 to rank0
3410 12:47:13.775841 Final RX Vref Byte 1 = 48 to rank0
3411 12:47:13.779183 Final RX Vref Byte 0 = 56 to rank1
3412 12:47:13.782656 Final RX Vref Byte 1 = 48 to rank1==
3413 12:47:13.786036 Dram Type= 6, Freq= 0, CH_1, rank 0
3414 12:47:13.792428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3415 12:47:13.792504 ==
3416 12:47:13.792568 DQS Delay:
3417 12:47:13.792626 DQS0 = 0, DQS1 = 0
3418 12:47:13.795672 DQM Delay:
3419 12:47:13.795753 DQM0 = 114, DQM1 = 104
3420 12:47:13.799042 DQ Delay:
3421 12:47:13.802495 DQ0 =116, DQ1 =110, DQ2 =104, DQ3 =112
3422 12:47:13.805559 DQ4 =112, DQ5 =122, DQ6 =126, DQ7 =112
3423 12:47:13.809041 DQ8 =92, DQ9 =100, DQ10 =104, DQ11 =100
3424 12:47:13.812402 DQ12 =110, DQ13 =110, DQ14 =112, DQ15 =110
3425 12:47:13.812484
3426 12:47:13.812547
3427 12:47:13.819115 [DQSOSCAuto] RK0, (LSB)MR18= 0xf2f9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 415 ps
3428 12:47:13.822449 CH1 RK0: MR19=303, MR18=F2F9
3429 12:47:13.829336 CH1_RK0: MR19=0x303, MR18=0xF2F9, DQSOSC=412, MR23=63, INC=38, DEC=25
3430 12:47:13.829418
3431 12:47:13.832935 ----->DramcWriteLeveling(PI) begin...
3432 12:47:13.833019 ==
3433 12:47:13.835624 Dram Type= 6, Freq= 0, CH_1, rank 1
3434 12:47:13.839377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3435 12:47:13.842870 ==
3436 12:47:13.842951 Write leveling (Byte 0): 25 => 25
3437 12:47:13.845735 Write leveling (Byte 1): 29 => 29
3438 12:47:13.849062 DramcWriteLeveling(PI) end<-----
3439 12:47:13.849144
3440 12:47:13.849207 ==
3441 12:47:13.852409 Dram Type= 6, Freq= 0, CH_1, rank 1
3442 12:47:13.859483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3443 12:47:13.859564 ==
3444 12:47:13.859628 [Gating] SW mode calibration
3445 12:47:13.869101 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3446 12:47:13.872481 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3447 12:47:13.875801 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 12:47:13.882065 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 12:47:13.885556 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 12:47:13.892528 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 12:47:13.895759 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 12:47:13.899287 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3453 12:47:13.902490 0 15 24 | B1->B0 | 3232 2424 | 0 0 | (0 0) (0 0)
3454 12:47:13.908777 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3455 12:47:13.912006 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 12:47:13.915761 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 12:47:13.922272 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 12:47:13.925916 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 12:47:13.928787 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 12:47:13.935861 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3461 12:47:13.938701 1 0 24 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
3462 12:47:13.942110 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3463 12:47:13.949198 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 12:47:13.952327 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 12:47:13.955439 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 12:47:13.962429 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 12:47:13.965848 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 12:47:13.968881 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 12:47:13.975567 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3470 12:47:13.978691 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3471 12:47:13.982102 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 12:47:13.989005 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 12:47:13.992424 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 12:47:13.995305 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 12:47:14.002264 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 12:47:14.005752 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 12:47:14.008636 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 12:47:14.011943 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 12:47:14.018749 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 12:47:14.022097 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 12:47:14.025492 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 12:47:14.032339 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 12:47:14.035345 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 12:47:14.038781 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3485 12:47:14.045167 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3486 12:47:14.048450 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3487 12:47:14.052296 Total UI for P1: 0, mck2ui 16
3488 12:47:14.055103 best dqsien dly found for B0: ( 1, 3, 22)
3489 12:47:14.058529 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 12:47:14.061979 Total UI for P1: 0, mck2ui 16
3491 12:47:14.064897 best dqsien dly found for B1: ( 1, 3, 26)
3492 12:47:14.068312 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3493 12:47:14.071705 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3494 12:47:14.071789
3495 12:47:14.078657 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3496 12:47:14.081782 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3497 12:47:14.085274 [Gating] SW calibration Done
3498 12:47:14.085355 ==
3499 12:47:14.088363 Dram Type= 6, Freq= 0, CH_1, rank 1
3500 12:47:14.091922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3501 12:47:14.092004 ==
3502 12:47:14.092069 RX Vref Scan: 0
3503 12:47:14.092129
3504 12:47:14.094731 RX Vref 0 -> 0, step: 1
3505 12:47:14.094812
3506 12:47:14.098211 RX Delay -40 -> 252, step: 8
3507 12:47:14.101740 iDelay=200, Bit 0, Center 119 (40 ~ 199) 160
3508 12:47:14.105412 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3509 12:47:14.111528 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3510 12:47:14.115080 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3511 12:47:14.118438 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3512 12:47:14.121286 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3513 12:47:14.124588 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3514 12:47:14.131519 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3515 12:47:14.134875 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3516 12:47:14.138135 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3517 12:47:14.141296 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3518 12:47:14.144664 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3519 12:47:14.151549 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3520 12:47:14.154737 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3521 12:47:14.157731 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3522 12:47:14.161453 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3523 12:47:14.161544 ==
3524 12:47:14.164215 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 12:47:14.171076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 12:47:14.171159 ==
3527 12:47:14.171224 DQS Delay:
3528 12:47:14.171284 DQS0 = 0, DQS1 = 0
3529 12:47:14.174588 DQM Delay:
3530 12:47:14.174668 DQM0 = 111, DQM1 = 108
3531 12:47:14.177612 DQ Delay:
3532 12:47:14.181222 DQ0 =119, DQ1 =107, DQ2 =99, DQ3 =107
3533 12:47:14.184154 DQ4 =107, DQ5 =123, DQ6 =119, DQ7 =111
3534 12:47:14.187561 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3535 12:47:14.190740 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3536 12:47:14.190823
3537 12:47:14.190887
3538 12:47:14.190946 ==
3539 12:47:14.193897 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 12:47:14.197712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 12:47:14.197789 ==
3542 12:47:14.197851
3543 12:47:14.200561
3544 12:47:14.200633 TX Vref Scan disable
3545 12:47:14.204086 == TX Byte 0 ==
3546 12:47:14.207434 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3547 12:47:14.210749 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3548 12:47:14.214137 == TX Byte 1 ==
3549 12:47:14.217630 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3550 12:47:14.220443 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3551 12:47:14.220515 ==
3552 12:47:14.223976 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 12:47:14.230317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 12:47:14.230399 ==
3555 12:47:14.241775 TX Vref=22, minBit 9, minWin=25, winSum=425
3556 12:47:14.244538 TX Vref=24, minBit 9, minWin=25, winSum=428
3557 12:47:14.248059 TX Vref=26, minBit 9, minWin=25, winSum=432
3558 12:47:14.251553 TX Vref=28, minBit 9, minWin=26, winSum=436
3559 12:47:14.254551 TX Vref=30, minBit 8, minWin=26, winSum=433
3560 12:47:14.260966 TX Vref=32, minBit 1, minWin=26, winSum=432
3561 12:47:14.264809 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 28
3562 12:47:14.264885
3563 12:47:14.267993 Final TX Range 1 Vref 28
3564 12:47:14.268073
3565 12:47:14.268233 ==
3566 12:47:14.270983 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 12:47:14.274557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 12:47:14.277837 ==
3569 12:47:14.277910
3570 12:47:14.277971
3571 12:47:14.278029 TX Vref Scan disable
3572 12:47:14.281178 == TX Byte 0 ==
3573 12:47:14.284518 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3574 12:47:14.291271 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3575 12:47:14.291417 == TX Byte 1 ==
3576 12:47:14.294381 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3577 12:47:14.301209 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3578 12:47:14.301291
3579 12:47:14.301354 [DATLAT]
3580 12:47:14.301413 Freq=1200, CH1 RK1
3581 12:47:14.301476
3582 12:47:14.304199 DATLAT Default: 0xd
3583 12:47:14.304272 0, 0xFFFF, sum = 0
3584 12:47:14.308011 1, 0xFFFF, sum = 0
3585 12:47:14.308089 2, 0xFFFF, sum = 0
3586 12:47:14.310900 3, 0xFFFF, sum = 0
3587 12:47:14.314269 4, 0xFFFF, sum = 0
3588 12:47:14.314343 5, 0xFFFF, sum = 0
3589 12:47:14.317921 6, 0xFFFF, sum = 0
3590 12:47:14.317994 7, 0xFFFF, sum = 0
3591 12:47:14.321030 8, 0xFFFF, sum = 0
3592 12:47:14.321112 9, 0xFFFF, sum = 0
3593 12:47:14.324647 10, 0xFFFF, sum = 0
3594 12:47:14.324755 11, 0xFFFF, sum = 0
3595 12:47:14.327600 12, 0x0, sum = 1
3596 12:47:14.327675 13, 0x0, sum = 2
3597 12:47:14.330935 14, 0x0, sum = 3
3598 12:47:14.331010 15, 0x0, sum = 4
3599 12:47:14.331072 best_step = 13
3600 12:47:14.334362
3601 12:47:14.334435 ==
3602 12:47:14.337724 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 12:47:14.341147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 12:47:14.341245 ==
3605 12:47:14.341309 RX Vref Scan: 0
3606 12:47:14.341367
3607 12:47:14.343964 RX Vref 0 -> 0, step: 1
3608 12:47:14.344035
3609 12:47:14.347616 RX Delay -21 -> 252, step: 4
3610 12:47:14.350832 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3611 12:47:14.357568 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3612 12:47:14.360854 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3613 12:47:14.363865 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3614 12:47:14.367509 iDelay=195, Bit 4, Center 110 (39 ~ 182) 144
3615 12:47:14.371090 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3616 12:47:14.377291 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3617 12:47:14.380826 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3618 12:47:14.383896 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3619 12:47:14.387613 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3620 12:47:14.390279 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3621 12:47:14.397441 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3622 12:47:14.400958 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3623 12:47:14.403652 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3624 12:47:14.406882 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3625 12:47:14.413845 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3626 12:47:14.413927 ==
3627 12:47:14.417178 Dram Type= 6, Freq= 0, CH_1, rank 1
3628 12:47:14.420031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3629 12:47:14.420114 ==
3630 12:47:14.420178 DQS Delay:
3631 12:47:14.423563 DQS0 = 0, DQS1 = 0
3632 12:47:14.423643 DQM Delay:
3633 12:47:14.427094 DQM0 = 111, DQM1 = 110
3634 12:47:14.427175 DQ Delay:
3635 12:47:14.430439 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3636 12:47:14.433754 DQ4 =110, DQ5 =120, DQ6 =122, DQ7 =110
3637 12:47:14.436680 DQ8 =96, DQ9 =102, DQ10 =110, DQ11 =104
3638 12:47:14.440140 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =118
3639 12:47:14.440222
3640 12:47:14.440285
3641 12:47:14.449908 [DQSOSCAuto] RK1, (LSB)MR18= 0xfc0c, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 411 ps
3642 12:47:14.453560 CH1 RK1: MR19=304, MR18=FC0C
3643 12:47:14.460134 CH1_RK1: MR19=0x304, MR18=0xFC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3644 12:47:14.460216 [RxdqsGatingPostProcess] freq 1200
3645 12:47:14.467072 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3646 12:47:14.470023 best DQS0 dly(2T, 0.5T) = (0, 11)
3647 12:47:14.473342 best DQS1 dly(2T, 0.5T) = (0, 11)
3648 12:47:14.476872 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3649 12:47:14.479731 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3650 12:47:14.483050 best DQS0 dly(2T, 0.5T) = (0, 11)
3651 12:47:14.486722 best DQS1 dly(2T, 0.5T) = (0, 11)
3652 12:47:14.489518 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3653 12:47:14.493195 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3654 12:47:14.496392 Pre-setting of DQS Precalculation
3655 12:47:14.499522 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3656 12:47:14.506545 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3657 12:47:14.516266 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3658 12:47:14.516349
3659 12:47:14.516413
3660 12:47:14.519839 [Calibration Summary] 2400 Mbps
3661 12:47:14.519921 CH 0, Rank 0
3662 12:47:14.523105 SW Impedance : PASS
3663 12:47:14.523186 DUTY Scan : NO K
3664 12:47:14.525877 ZQ Calibration : PASS
3665 12:47:14.529328 Jitter Meter : NO K
3666 12:47:14.529410 CBT Training : PASS
3667 12:47:14.532839 Write leveling : PASS
3668 12:47:14.532920 RX DQS gating : PASS
3669 12:47:14.536283 RX DQ/DQS(RDDQC) : PASS
3670 12:47:14.539153 TX DQ/DQS : PASS
3671 12:47:14.539235 RX DATLAT : PASS
3672 12:47:14.542496 RX DQ/DQS(Engine): PASS
3673 12:47:14.546051 TX OE : NO K
3674 12:47:14.546133 All Pass.
3675 12:47:14.546196
3676 12:47:14.548908 CH 0, Rank 1
3677 12:47:14.548989 SW Impedance : PASS
3678 12:47:14.552403 DUTY Scan : NO K
3679 12:47:14.552485 ZQ Calibration : PASS
3680 12:47:14.555844 Jitter Meter : NO K
3681 12:47:14.558773 CBT Training : PASS
3682 12:47:14.558854 Write leveling : PASS
3683 12:47:14.562714 RX DQS gating : PASS
3684 12:47:14.565780 RX DQ/DQS(RDDQC) : PASS
3685 12:47:14.565861 TX DQ/DQS : PASS
3686 12:47:14.569137 RX DATLAT : PASS
3687 12:47:14.572035 RX DQ/DQS(Engine): PASS
3688 12:47:14.572134 TX OE : NO K
3689 12:47:14.575635 All Pass.
3690 12:47:14.575715
3691 12:47:14.575778 CH 1, Rank 0
3692 12:47:14.578578 SW Impedance : PASS
3693 12:47:14.578658 DUTY Scan : NO K
3694 12:47:14.581934 ZQ Calibration : PASS
3695 12:47:14.585413 Jitter Meter : NO K
3696 12:47:14.585494 CBT Training : PASS
3697 12:47:14.589041 Write leveling : PASS
3698 12:47:14.592294 RX DQS gating : PASS
3699 12:47:14.592376 RX DQ/DQS(RDDQC) : PASS
3700 12:47:14.595669 TX DQ/DQS : PASS
3701 12:47:14.595776 RX DATLAT : PASS
3702 12:47:14.599029 RX DQ/DQS(Engine): PASS
3703 12:47:14.602413 TX OE : NO K
3704 12:47:14.602497 All Pass.
3705 12:47:14.602560
3706 12:47:14.602623 CH 1, Rank 1
3707 12:47:14.605137 SW Impedance : PASS
3708 12:47:14.608749 DUTY Scan : NO K
3709 12:47:14.608830 ZQ Calibration : PASS
3710 12:47:14.612521 Jitter Meter : NO K
3711 12:47:14.615059 CBT Training : PASS
3712 12:47:14.615139 Write leveling : PASS
3713 12:47:14.618686 RX DQS gating : PASS
3714 12:47:14.621906 RX DQ/DQS(RDDQC) : PASS
3715 12:47:14.621987 TX DQ/DQS : PASS
3716 12:47:14.625264 RX DATLAT : PASS
3717 12:47:14.628529 RX DQ/DQS(Engine): PASS
3718 12:47:14.628610 TX OE : NO K
3719 12:47:14.632113 All Pass.
3720 12:47:14.632194
3721 12:47:14.632257 DramC Write-DBI off
3722 12:47:14.635160 PER_BANK_REFRESH: Hybrid Mode
3723 12:47:14.635240 TX_TRACKING: ON
3724 12:47:14.644844 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3725 12:47:14.648254 [FAST_K] Save calibration result to emmc
3726 12:47:14.651725 dramc_set_vcore_voltage set vcore to 650000
3727 12:47:14.655292 Read voltage for 600, 5
3728 12:47:14.655435 Vio18 = 0
3729 12:47:14.658060 Vcore = 650000
3730 12:47:14.658141 Vdram = 0
3731 12:47:14.658205 Vddq = 0
3732 12:47:14.661453 Vmddr = 0
3733 12:47:14.664898 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3734 12:47:14.671225 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3735 12:47:14.671332 MEM_TYPE=3, freq_sel=19
3736 12:47:14.674451 sv_algorithm_assistance_LP4_1600
3737 12:47:14.681277 ============ PULL DRAM RESETB DOWN ============
3738 12:47:14.684812 ========== PULL DRAM RESETB DOWN end =========
3739 12:47:14.687916 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3740 12:47:14.691173 ===================================
3741 12:47:14.694420 LPDDR4 DRAM CONFIGURATION
3742 12:47:14.698003 ===================================
3743 12:47:14.701562 EX_ROW_EN[0] = 0x0
3744 12:47:14.701642 EX_ROW_EN[1] = 0x0
3745 12:47:14.704363 LP4Y_EN = 0x0
3746 12:47:14.704444 WORK_FSP = 0x0
3747 12:47:14.707798 WL = 0x2
3748 12:47:14.707879 RL = 0x2
3749 12:47:14.711071 BL = 0x2
3750 12:47:14.711152 RPST = 0x0
3751 12:47:14.714491 RD_PRE = 0x0
3752 12:47:14.714572 WR_PRE = 0x1
3753 12:47:14.717379 WR_PST = 0x0
3754 12:47:14.717460 DBI_WR = 0x0
3755 12:47:14.720878 DBI_RD = 0x0
3756 12:47:14.720959 OTF = 0x1
3757 12:47:14.724315 ===================================
3758 12:47:14.727645 ===================================
3759 12:47:14.731210 ANA top config
3760 12:47:14.734310 ===================================
3761 12:47:14.737392 DLL_ASYNC_EN = 0
3762 12:47:14.737473 ALL_SLAVE_EN = 1
3763 12:47:14.740574 NEW_RANK_MODE = 1
3764 12:47:14.744164 DLL_IDLE_MODE = 1
3765 12:47:14.747051 LP45_APHY_COMB_EN = 1
3766 12:47:14.750415 TX_ODT_DIS = 1
3767 12:47:14.750497 NEW_8X_MODE = 1
3768 12:47:14.753904 ===================================
3769 12:47:14.757301 ===================================
3770 12:47:14.760772 data_rate = 1200
3771 12:47:14.763798 CKR = 1
3772 12:47:14.767009 DQ_P2S_RATIO = 8
3773 12:47:14.770500 ===================================
3774 12:47:14.773840 CA_P2S_RATIO = 8
3775 12:47:14.776755 DQ_CA_OPEN = 0
3776 12:47:14.776836 DQ_SEMI_OPEN = 0
3777 12:47:14.780224 CA_SEMI_OPEN = 0
3778 12:47:14.783558 CA_FULL_RATE = 0
3779 12:47:14.786981 DQ_CKDIV4_EN = 1
3780 12:47:14.790183 CA_CKDIV4_EN = 1
3781 12:47:14.793786 CA_PREDIV_EN = 0
3782 12:47:14.793867 PH8_DLY = 0
3783 12:47:14.796883 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3784 12:47:14.800046 DQ_AAMCK_DIV = 4
3785 12:47:14.803326 CA_AAMCK_DIV = 4
3786 12:47:14.807088 CA_ADMCK_DIV = 4
3787 12:47:14.810028 DQ_TRACK_CA_EN = 0
3788 12:47:14.810110 CA_PICK = 600
3789 12:47:14.813641 CA_MCKIO = 600
3790 12:47:14.817015 MCKIO_SEMI = 0
3791 12:47:14.819947 PLL_FREQ = 2288
3792 12:47:14.823478 DQ_UI_PI_RATIO = 32
3793 12:47:14.826742 CA_UI_PI_RATIO = 0
3794 12:47:14.830618 ===================================
3795 12:47:14.833089 ===================================
3796 12:47:14.833170 memory_type:LPDDR4
3797 12:47:14.836416 GP_NUM : 10
3798 12:47:14.840131 SRAM_EN : 1
3799 12:47:14.840213 MD32_EN : 0
3800 12:47:14.843336 ===================================
3801 12:47:14.846770 [ANA_INIT] >>>>>>>>>>>>>>
3802 12:47:14.849783 <<<<<< [CONFIGURE PHASE]: ANA_TX
3803 12:47:14.853168 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3804 12:47:14.856669 ===================================
3805 12:47:14.859638 data_rate = 1200,PCW = 0X5800
3806 12:47:14.862924 ===================================
3807 12:47:14.866574 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3808 12:47:14.869836 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3809 12:47:14.876145 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3810 12:47:14.879588 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3811 12:47:14.882971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3812 12:47:14.889556 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3813 12:47:14.889638 [ANA_INIT] flow start
3814 12:47:14.893067 [ANA_INIT] PLL >>>>>>>>
3815 12:47:14.896411 [ANA_INIT] PLL <<<<<<<<
3816 12:47:14.896492 [ANA_INIT] MIDPI >>>>>>>>
3817 12:47:14.900016 [ANA_INIT] MIDPI <<<<<<<<
3818 12:47:14.903011 [ANA_INIT] DLL >>>>>>>>
3819 12:47:14.903092 [ANA_INIT] flow end
3820 12:47:14.906172 ============ LP4 DIFF to SE enter ============
3821 12:47:14.913072 ============ LP4 DIFF to SE exit ============
3822 12:47:14.913178 [ANA_INIT] <<<<<<<<<<<<<
3823 12:47:14.915957 [Flow] Enable top DCM control >>>>>
3824 12:47:14.919383 [Flow] Enable top DCM control <<<<<
3825 12:47:14.922447 Enable DLL master slave shuffle
3826 12:47:14.929370 ==============================================================
3827 12:47:14.932803 Gating Mode config
3828 12:47:14.935723 ==============================================================
3829 12:47:14.939093 Config description:
3830 12:47:14.949294 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3831 12:47:14.955656 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3832 12:47:14.958939 SELPH_MODE 0: By rank 1: By Phase
3833 12:47:14.965897 ==============================================================
3834 12:47:14.969219 GAT_TRACK_EN = 1
3835 12:47:14.972546 RX_GATING_MODE = 2
3836 12:47:14.976336 RX_GATING_TRACK_MODE = 2
3837 12:47:14.976418 SELPH_MODE = 1
3838 12:47:14.979265 PICG_EARLY_EN = 1
3839 12:47:14.982615 VALID_LAT_VALUE = 1
3840 12:47:14.989367 ==============================================================
3841 12:47:14.992141 Enter into Gating configuration >>>>
3842 12:47:14.995537 Exit from Gating configuration <<<<
3843 12:47:14.999080 Enter into DVFS_PRE_config >>>>>
3844 12:47:15.008712 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3845 12:47:15.012145 Exit from DVFS_PRE_config <<<<<
3846 12:47:15.015520 Enter into PICG configuration >>>>
3847 12:47:15.019012 Exit from PICG configuration <<<<
3848 12:47:15.022146 [RX_INPUT] configuration >>>>>
3849 12:47:15.025331 [RX_INPUT] configuration <<<<<
3850 12:47:15.029044 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3851 12:47:15.035304 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3852 12:47:15.041889 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3853 12:47:15.048485 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3854 12:47:15.051901 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3855 12:47:15.058692 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3856 12:47:15.065528 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3857 12:47:15.068767 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3858 12:47:15.071851 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3859 12:47:15.075213 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3860 12:47:15.078814 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3861 12:47:15.085035 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3862 12:47:15.088536 ===================================
3863 12:47:15.091878 LPDDR4 DRAM CONFIGURATION
3864 12:47:15.095087 ===================================
3865 12:47:15.095219 EX_ROW_EN[0] = 0x0
3866 12:47:15.098358 EX_ROW_EN[1] = 0x0
3867 12:47:15.098434 LP4Y_EN = 0x0
3868 12:47:15.101739 WORK_FSP = 0x0
3869 12:47:15.101811 WL = 0x2
3870 12:47:15.104823 RL = 0x2
3871 12:47:15.104903 BL = 0x2
3872 12:47:15.108514 RPST = 0x0
3873 12:47:15.108595 RD_PRE = 0x0
3874 12:47:15.111759 WR_PRE = 0x1
3875 12:47:15.111856 WR_PST = 0x0
3876 12:47:15.114639 DBI_WR = 0x0
3877 12:47:15.114736 DBI_RD = 0x0
3878 12:47:15.118046 OTF = 0x1
3879 12:47:15.121476 ===================================
3880 12:47:15.124878 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3881 12:47:15.127900 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3882 12:47:15.134514 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3883 12:47:15.138220 ===================================
3884 12:47:15.140998 LPDDR4 DRAM CONFIGURATION
3885 12:47:15.144862 ===================================
3886 12:47:15.144958 EX_ROW_EN[0] = 0x10
3887 12:47:15.148056 EX_ROW_EN[1] = 0x0
3888 12:47:15.148173 LP4Y_EN = 0x0
3889 12:47:15.151304 WORK_FSP = 0x0
3890 12:47:15.151429 WL = 0x2
3891 12:47:15.154810 RL = 0x2
3892 12:47:15.154891 BL = 0x2
3893 12:47:15.158109 RPST = 0x0
3894 12:47:15.158191 RD_PRE = 0x0
3895 12:47:15.161209 WR_PRE = 0x1
3896 12:47:15.161290 WR_PST = 0x0
3897 12:47:15.164362 DBI_WR = 0x0
3898 12:47:15.164443 DBI_RD = 0x0
3899 12:47:15.168005 OTF = 0x1
3900 12:47:15.171282 ===================================
3901 12:47:15.177628 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3902 12:47:15.181507 nWR fixed to 30
3903 12:47:15.184229 [ModeRegInit_LP4] CH0 RK0
3904 12:47:15.184311 [ModeRegInit_LP4] CH0 RK1
3905 12:47:15.187687 [ModeRegInit_LP4] CH1 RK0
3906 12:47:15.191164 [ModeRegInit_LP4] CH1 RK1
3907 12:47:15.191245 match AC timing 17
3908 12:47:15.197950 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3909 12:47:15.200781 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3910 12:47:15.204274 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3911 12:47:15.211187 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3912 12:47:15.214370 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3913 12:47:15.214452 ==
3914 12:47:15.217519 Dram Type= 6, Freq= 0, CH_0, rank 0
3915 12:47:15.220826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3916 12:47:15.220908 ==
3917 12:47:15.227740 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3918 12:47:15.233937 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3919 12:47:15.237284 [CA 0] Center 37 (7~67) winsize 61
3920 12:47:15.240599 [CA 1] Center 36 (6~67) winsize 62
3921 12:47:15.244012 [CA 2] Center 35 (5~65) winsize 61
3922 12:47:15.247094 [CA 3] Center 35 (5~65) winsize 61
3923 12:47:15.250960 [CA 4] Center 34 (4~64) winsize 61
3924 12:47:15.253762 [CA 5] Center 34 (4~64) winsize 61
3925 12:47:15.253843
3926 12:47:15.256985 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3927 12:47:15.257066
3928 12:47:15.261034 [CATrainingPosCal] consider 1 rank data
3929 12:47:15.263624 u2DelayCellTimex100 = 270/100 ps
3930 12:47:15.267553 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3931 12:47:15.271062 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3932 12:47:15.273769 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3933 12:47:15.277079 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3934 12:47:15.283940 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3935 12:47:15.287195 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3936 12:47:15.287275
3937 12:47:15.290546 CA PerBit enable=1, Macro0, CA PI delay=34
3938 12:47:15.290627
3939 12:47:15.293966 [CBTSetCACLKResult] CA Dly = 34
3940 12:47:15.294047 CS Dly: 5 (0~36)
3941 12:47:15.294111 ==
3942 12:47:15.296879 Dram Type= 6, Freq= 0, CH_0, rank 1
3943 12:47:15.300347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3944 12:47:15.303300 ==
3945 12:47:15.306992 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3946 12:47:15.313404 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3947 12:47:15.316820 [CA 0] Center 37 (7~67) winsize 61
3948 12:47:15.320091 [CA 1] Center 36 (6~67) winsize 62
3949 12:47:15.323518 [CA 2] Center 35 (5~65) winsize 61
3950 12:47:15.326468 [CA 3] Center 34 (4~65) winsize 62
3951 12:47:15.329907 [CA 4] Center 34 (4~65) winsize 62
3952 12:47:15.333267 [CA 5] Center 33 (3~64) winsize 62
3953 12:47:15.333348
3954 12:47:15.336730 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3955 12:47:15.336811
3956 12:47:15.340077 [CATrainingPosCal] consider 2 rank data
3957 12:47:15.343312 u2DelayCellTimex100 = 270/100 ps
3958 12:47:15.346524 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3959 12:47:15.350164 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3960 12:47:15.356475 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3961 12:47:15.359664 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3962 12:47:15.363186 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3963 12:47:15.366514 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3964 12:47:15.366595
3965 12:47:15.369800 CA PerBit enable=1, Macro0, CA PI delay=34
3966 12:47:15.369882
3967 12:47:15.373290 [CBTSetCACLKResult] CA Dly = 34
3968 12:47:15.373371 CS Dly: 5 (0~37)
3969 12:47:15.373436
3970 12:47:15.376508 ----->DramcWriteLeveling(PI) begin...
3971 12:47:15.379885 ==
3972 12:47:15.383082 Dram Type= 6, Freq= 0, CH_0, rank 0
3973 12:47:15.386017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3974 12:47:15.386098 ==
3975 12:47:15.389713 Write leveling (Byte 0): 30 => 30
3976 12:47:15.392700 Write leveling (Byte 1): 31 => 31
3977 12:47:15.395910 DramcWriteLeveling(PI) end<-----
3978 12:47:15.395991
3979 12:47:15.396054 ==
3980 12:47:15.399258 Dram Type= 6, Freq= 0, CH_0, rank 0
3981 12:47:15.402643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 12:47:15.402724 ==
3983 12:47:15.406271 [Gating] SW mode calibration
3984 12:47:15.412572 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3985 12:47:15.419363 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3986 12:47:15.422385 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3987 12:47:15.426307 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3988 12:47:15.429504 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3989 12:47:15.436031 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
3990 12:47:15.439613 0 9 16 | B1->B0 | 3131 2828 | 0 0 | (0 1) (0 0)
3991 12:47:15.442849 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 12:47:15.449534 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 12:47:15.452825 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 12:47:15.455840 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 12:47:15.462569 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 12:47:15.465486 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 12:47:15.469593 0 10 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
3998 12:47:15.475554 0 10 16 | B1->B0 | 3535 3b3b | 0 1 | (0 0) (0 0)
3999 12:47:15.478717 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 12:47:15.482416 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 12:47:15.489000 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 12:47:15.492248 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 12:47:15.495282 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 12:47:15.501904 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 12:47:15.505503 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4006 12:47:15.508825 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4007 12:47:15.515113 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 12:47:15.518666 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 12:47:15.521665 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 12:47:15.528682 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 12:47:15.531890 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 12:47:15.534960 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 12:47:15.541790 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 12:47:15.544996 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 12:47:15.548794 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 12:47:15.555275 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 12:47:15.558668 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 12:47:15.561719 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 12:47:15.568203 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 12:47:15.571803 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 12:47:15.574950 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4022 12:47:15.578552 Total UI for P1: 0, mck2ui 16
4023 12:47:15.581319 best dqsien dly found for B0: ( 0, 13, 10)
4024 12:47:15.588087 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 12:47:15.588169 Total UI for P1: 0, mck2ui 16
4026 12:47:15.594766 best dqsien dly found for B1: ( 0, 13, 14)
4027 12:47:15.598507 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4028 12:47:15.601196 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4029 12:47:15.601301
4030 12:47:15.604469 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4031 12:47:15.607965 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4032 12:47:15.611435 [Gating] SW calibration Done
4033 12:47:15.611515 ==
4034 12:47:15.614723 Dram Type= 6, Freq= 0, CH_0, rank 0
4035 12:47:15.618131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 12:47:15.618212 ==
4037 12:47:15.621108 RX Vref Scan: 0
4038 12:47:15.621189
4039 12:47:15.621252 RX Vref 0 -> 0, step: 1
4040 12:47:15.621311
4041 12:47:15.624458 RX Delay -230 -> 252, step: 16
4042 12:47:15.631107 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4043 12:47:15.634757 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4044 12:47:15.638184 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4045 12:47:15.641376 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4046 12:47:15.644417 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4047 12:47:15.651189 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4048 12:47:15.654621 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4049 12:47:15.658123 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4050 12:47:15.661220 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4051 12:47:15.668053 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4052 12:47:15.671096 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4053 12:47:15.674407 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4054 12:47:15.677649 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4055 12:47:15.684252 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4056 12:47:15.687497 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4057 12:47:15.691013 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4058 12:47:15.691094 ==
4059 12:47:15.694591 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 12:47:15.697888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 12:47:15.697969 ==
4062 12:47:15.701050 DQS Delay:
4063 12:47:15.701130 DQS0 = 0, DQS1 = 0
4064 12:47:15.704525 DQM Delay:
4065 12:47:15.704605 DQM0 = 40, DQM1 = 28
4066 12:47:15.704669 DQ Delay:
4067 12:47:15.707918 DQ0 =33, DQ1 =41, DQ2 =41, DQ3 =41
4068 12:47:15.711305 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4069 12:47:15.714660 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4070 12:47:15.717620 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4071 12:47:15.717701
4072 12:47:15.717764
4073 12:47:15.720934 ==
4074 12:47:15.721014 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 12:47:15.727300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 12:47:15.727409 ==
4077 12:47:15.727475
4078 12:47:15.727534
4079 12:47:15.730721 TX Vref Scan disable
4080 12:47:15.730802 == TX Byte 0 ==
4081 12:47:15.737347 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4082 12:47:15.740850 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4083 12:47:15.740935 == TX Byte 1 ==
4084 12:47:15.747000 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4085 12:47:15.750386 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4086 12:47:15.750466 ==
4087 12:47:15.753852 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 12:47:15.757330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 12:47:15.757411 ==
4090 12:47:15.757474
4091 12:47:15.757532
4092 12:47:15.760485 TX Vref Scan disable
4093 12:47:15.763971 == TX Byte 0 ==
4094 12:47:15.767414 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4095 12:47:15.770644 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4096 12:47:15.773612 == TX Byte 1 ==
4097 12:47:15.777506 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4098 12:47:15.780513 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4099 12:47:15.780595
4100 12:47:15.783999 [DATLAT]
4101 12:47:15.784080 Freq=600, CH0 RK0
4102 12:47:15.784144
4103 12:47:15.786985 DATLAT Default: 0x9
4104 12:47:15.787065 0, 0xFFFF, sum = 0
4105 12:47:15.790668 1, 0xFFFF, sum = 0
4106 12:47:15.790750 2, 0xFFFF, sum = 0
4107 12:47:15.793611 3, 0xFFFF, sum = 0
4108 12:47:15.793693 4, 0xFFFF, sum = 0
4109 12:47:15.797097 5, 0xFFFF, sum = 0
4110 12:47:15.797179 6, 0xFFFF, sum = 0
4111 12:47:15.800336 7, 0xFFFF, sum = 0
4112 12:47:15.800418 8, 0x0, sum = 1
4113 12:47:15.803360 9, 0x0, sum = 2
4114 12:47:15.803461 10, 0x0, sum = 3
4115 12:47:15.807363 11, 0x0, sum = 4
4116 12:47:15.807468 best_step = 9
4117 12:47:15.807531
4118 12:47:15.807589 ==
4119 12:47:15.810172 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 12:47:15.813540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 12:47:15.817068 ==
4122 12:47:15.817148 RX Vref Scan: 1
4123 12:47:15.817211
4124 12:47:15.820575 RX Vref 0 -> 0, step: 1
4125 12:47:15.820655
4126 12:47:15.823414 RX Delay -195 -> 252, step: 8
4127 12:47:15.823494
4128 12:47:15.826866 Set Vref, RX VrefLevel [Byte0]: 62
4129 12:47:15.830454 [Byte1]: 56
4130 12:47:15.830535
4131 12:47:15.833908 Final RX Vref Byte 0 = 62 to rank0
4132 12:47:15.836831 Final RX Vref Byte 1 = 56 to rank0
4133 12:47:15.840454 Final RX Vref Byte 0 = 62 to rank1
4134 12:47:15.843273 Final RX Vref Byte 1 = 56 to rank1==
4135 12:47:15.846810 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 12:47:15.850017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 12:47:15.850098 ==
4138 12:47:15.853695 DQS Delay:
4139 12:47:15.853776 DQS0 = 0, DQS1 = 0
4140 12:47:15.853840 DQM Delay:
4141 12:47:15.856629 DQM0 = 35, DQM1 = 28
4142 12:47:15.856709 DQ Delay:
4143 12:47:15.859984 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =32
4144 12:47:15.863439 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4145 12:47:15.866612 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4146 12:47:15.869920 DQ12 =32, DQ13 =36, DQ14 =40, DQ15 =36
4147 12:47:15.870001
4148 12:47:15.870064
4149 12:47:15.879932 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c3b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4150 12:47:15.880015 CH0 RK0: MR19=808, MR18=3C3B
4151 12:47:15.886406 CH0_RK0: MR19=0x808, MR18=0x3C3B, DQSOSC=398, MR23=63, INC=165, DEC=110
4152 12:47:15.886487
4153 12:47:15.890024 ----->DramcWriteLeveling(PI) begin...
4154 12:47:15.893379 ==
4155 12:47:15.893460 Dram Type= 6, Freq= 0, CH_0, rank 1
4156 12:47:15.900059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 12:47:15.900141 ==
4158 12:47:15.903115 Write leveling (Byte 0): 32 => 32
4159 12:47:15.906489 Write leveling (Byte 1): 32 => 32
4160 12:47:15.906569 DramcWriteLeveling(PI) end<-----
4161 12:47:15.909895
4162 12:47:15.909979 ==
4163 12:47:15.913220 Dram Type= 6, Freq= 0, CH_0, rank 1
4164 12:47:15.916677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 12:47:15.916762 ==
4166 12:47:15.920170 [Gating] SW mode calibration
4167 12:47:15.926440 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4168 12:47:15.929866 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4169 12:47:15.936803 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4170 12:47:15.939600 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4171 12:47:15.942993 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4172 12:47:15.950122 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
4173 12:47:15.953263 0 9 16 | B1->B0 | 2f2f 2424 | 1 0 | (1 1) (0 0)
4174 12:47:15.956489 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 12:47:15.963340 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 12:47:15.966897 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 12:47:15.969586 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 12:47:15.976597 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 12:47:15.979470 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 12:47:15.982739 0 10 12 | B1->B0 | 2626 3434 | 0 0 | (0 0) (1 1)
4181 12:47:15.989780 0 10 16 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
4182 12:47:15.993122 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 12:47:15.996586 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 12:47:16.003473 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 12:47:16.006161 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 12:47:16.009531 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 12:47:16.015952 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4188 12:47:16.019083 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4189 12:47:16.022528 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 12:47:16.029491 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 12:47:16.032463 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 12:47:16.035952 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 12:47:16.042749 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 12:47:16.045669 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 12:47:16.049087 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 12:47:16.055527 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 12:47:16.058634 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 12:47:16.062190 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 12:47:16.068590 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 12:47:16.071982 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 12:47:16.075510 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 12:47:16.082042 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 12:47:16.085357 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 12:47:16.088647 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4205 12:47:16.091817 Total UI for P1: 0, mck2ui 16
4206 12:47:16.094904 best dqsien dly found for B0: ( 0, 13, 10)
4207 12:47:16.102068 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 12:47:16.102149 Total UI for P1: 0, mck2ui 16
4209 12:47:16.104864 best dqsien dly found for B1: ( 0, 13, 12)
4210 12:47:16.111623 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4211 12:47:16.115053 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4212 12:47:16.115159
4213 12:47:16.118370 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4214 12:47:16.123363 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4215 12:47:16.124945 [Gating] SW calibration Done
4216 12:47:16.125033 ==
4217 12:47:16.128459 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 12:47:16.131961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 12:47:16.132127 ==
4220 12:47:16.135028 RX Vref Scan: 0
4221 12:47:16.135116
4222 12:47:16.135183 RX Vref 0 -> 0, step: 1
4223 12:47:16.135244
4224 12:47:16.138487 RX Delay -230 -> 252, step: 16
4225 12:47:16.144871 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4226 12:47:16.148258 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4227 12:47:16.151788 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4228 12:47:16.154746 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4229 12:47:16.158322 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4230 12:47:16.164742 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4231 12:47:16.167915 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4232 12:47:16.171539 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4233 12:47:16.174570 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4234 12:47:16.181179 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4235 12:47:16.184819 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4236 12:47:16.188293 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4237 12:47:16.191159 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4238 12:47:16.197880 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4239 12:47:16.201235 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4240 12:47:16.204789 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4241 12:47:16.204880 ==
4242 12:47:16.207682 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 12:47:16.210908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 12:47:16.211028 ==
4245 12:47:16.214371 DQS Delay:
4246 12:47:16.214453 DQS0 = 0, DQS1 = 0
4247 12:47:16.217617 DQM Delay:
4248 12:47:16.217699 DQM0 = 40, DQM1 = 28
4249 12:47:16.217764 DQ Delay:
4250 12:47:16.221124 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4251 12:47:16.224512 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4252 12:47:16.227445 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4253 12:47:16.230909 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4254 12:47:16.230993
4255 12:47:16.231057
4256 12:47:16.234155 ==
4257 12:47:16.237301 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 12:47:16.240902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 12:47:16.240991 ==
4260 12:47:16.241056
4261 12:47:16.241115
4262 12:47:16.244217 TX Vref Scan disable
4263 12:47:16.244302 == TX Byte 0 ==
4264 12:47:16.250778 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4265 12:47:16.254198 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4266 12:47:16.254292 == TX Byte 1 ==
4267 12:47:16.260919 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4268 12:47:16.264367 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4269 12:47:16.264459 ==
4270 12:47:16.267728 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 12:47:16.271208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 12:47:16.271301 ==
4273 12:47:16.271417
4274 12:47:16.271482
4275 12:47:16.274239 TX Vref Scan disable
4276 12:47:16.277567 == TX Byte 0 ==
4277 12:47:16.280585 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4278 12:47:16.284197 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4279 12:47:16.287624 == TX Byte 1 ==
4280 12:47:16.290923 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4281 12:47:16.294295 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4282 12:47:16.294382
4283 12:47:16.298050 [DATLAT]
4284 12:47:16.298135 Freq=600, CH0 RK1
4285 12:47:16.298200
4286 12:47:16.300527 DATLAT Default: 0x9
4287 12:47:16.300625 0, 0xFFFF, sum = 0
4288 12:47:16.304023 1, 0xFFFF, sum = 0
4289 12:47:16.304116 2, 0xFFFF, sum = 0
4290 12:47:16.307461 3, 0xFFFF, sum = 0
4291 12:47:16.307549 4, 0xFFFF, sum = 0
4292 12:47:16.310745 5, 0xFFFF, sum = 0
4293 12:47:16.310829 6, 0xFFFF, sum = 0
4294 12:47:16.314179 7, 0xFFFF, sum = 0
4295 12:47:16.314263 8, 0x0, sum = 1
4296 12:47:16.317024 9, 0x0, sum = 2
4297 12:47:16.317107 10, 0x0, sum = 3
4298 12:47:16.320834 11, 0x0, sum = 4
4299 12:47:16.320916 best_step = 9
4300 12:47:16.320980
4301 12:47:16.321039 ==
4302 12:47:16.323632 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 12:47:16.326938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 12:47:16.330504 ==
4305 12:47:16.330591 RX Vref Scan: 0
4306 12:47:16.330655
4307 12:47:16.333814 RX Vref 0 -> 0, step: 1
4308 12:47:16.333898
4309 12:47:16.337287 RX Delay -195 -> 252, step: 8
4310 12:47:16.340117 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4311 12:47:16.346916 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4312 12:47:16.350181 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4313 12:47:16.353726 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4314 12:47:16.356769 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4315 12:47:16.360106 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4316 12:47:16.366685 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4317 12:47:16.370023 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4318 12:47:16.373482 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4319 12:47:16.377122 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4320 12:47:16.383902 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4321 12:47:16.386855 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4322 12:47:16.389991 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4323 12:47:16.393193 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4324 12:47:16.396556 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4325 12:47:16.403324 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4326 12:47:16.403449 ==
4327 12:47:16.406484 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 12:47:16.410031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 12:47:16.410102 ==
4330 12:47:16.410162 DQS Delay:
4331 12:47:16.413393 DQS0 = 0, DQS1 = 0
4332 12:47:16.413466 DQM Delay:
4333 12:47:16.416849 DQM0 = 33, DQM1 = 27
4334 12:47:16.416924 DQ Delay:
4335 12:47:16.420324 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4336 12:47:16.423004 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4337 12:47:16.426298 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4338 12:47:16.429919 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4339 12:47:16.429994
4340 12:47:16.430054
4341 12:47:16.439751 [DQSOSCAuto] RK1, (LSB)MR18= 0x6736, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4342 12:47:16.439828 CH0 RK1: MR19=808, MR18=6736
4343 12:47:16.446443 CH0_RK1: MR19=0x808, MR18=0x6736, DQSOSC=390, MR23=63, INC=172, DEC=114
4344 12:47:16.449760 [RxdqsGatingPostProcess] freq 600
4345 12:47:16.456064 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4346 12:47:16.459521 Pre-setting of DQS Precalculation
4347 12:47:16.462742 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4348 12:47:16.462814 ==
4349 12:47:16.466136 Dram Type= 6, Freq= 0, CH_1, rank 0
4350 12:47:16.472653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 12:47:16.472733 ==
4352 12:47:16.476035 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4353 12:47:16.482984 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4354 12:47:16.486205 [CA 0] Center 36 (6~66) winsize 61
4355 12:47:16.489322 [CA 1] Center 36 (6~66) winsize 61
4356 12:47:16.492514 [CA 2] Center 34 (4~65) winsize 62
4357 12:47:16.495801 [CA 3] Center 34 (4~65) winsize 62
4358 12:47:16.499458 [CA 4] Center 34 (4~65) winsize 62
4359 12:47:16.502540 [CA 5] Center 34 (4~64) winsize 61
4360 12:47:16.502612
4361 12:47:16.506064 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4362 12:47:16.506164
4363 12:47:16.509470 [CATrainingPosCal] consider 1 rank data
4364 12:47:16.512767 u2DelayCellTimex100 = 270/100 ps
4365 12:47:16.515722 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4366 12:47:16.519275 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4367 12:47:16.525593 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4368 12:47:16.529355 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4369 12:47:16.532921 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4370 12:47:16.536029 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4371 12:47:16.536105
4372 12:47:16.539091 CA PerBit enable=1, Macro0, CA PI delay=34
4373 12:47:16.539198
4374 12:47:16.542757 [CBTSetCACLKResult] CA Dly = 34
4375 12:47:16.542836 CS Dly: 4 (0~35)
4376 12:47:16.542899 ==
4377 12:47:16.545708 Dram Type= 6, Freq= 0, CH_1, rank 1
4378 12:47:16.552130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 12:47:16.552219 ==
4380 12:47:16.555821 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4381 12:47:16.562508 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4382 12:47:16.565940 [CA 0] Center 36 (6~66) winsize 61
4383 12:47:16.569592 [CA 1] Center 36 (6~66) winsize 61
4384 12:47:16.572421 [CA 2] Center 34 (4~65) winsize 62
4385 12:47:16.576060 [CA 3] Center 34 (3~65) winsize 63
4386 12:47:16.579130 [CA 4] Center 34 (4~65) winsize 62
4387 12:47:16.582623 [CA 5] Center 33 (3~64) winsize 62
4388 12:47:16.582701
4389 12:47:16.585608 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4390 12:47:16.585686
4391 12:47:16.589058 [CATrainingPosCal] consider 2 rank data
4392 12:47:16.592163 u2DelayCellTimex100 = 270/100 ps
4393 12:47:16.595338 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4394 12:47:16.602182 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4395 12:47:16.605274 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4396 12:47:16.608770 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4397 12:47:16.612297 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4398 12:47:16.615618 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4399 12:47:16.615732
4400 12:47:16.619017 CA PerBit enable=1, Macro0, CA PI delay=34
4401 12:47:16.619127
4402 12:47:16.622302 [CBTSetCACLKResult] CA Dly = 34
4403 12:47:16.622410 CS Dly: 5 (0~38)
4404 12:47:16.625629
4405 12:47:16.628896 ----->DramcWriteLeveling(PI) begin...
4406 12:47:16.629005 ==
4407 12:47:16.632087 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 12:47:16.635260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 12:47:16.635360 ==
4410 12:47:16.638823 Write leveling (Byte 0): 32 => 32
4411 12:47:16.641881 Write leveling (Byte 1): 32 => 32
4412 12:47:16.645551 DramcWriteLeveling(PI) end<-----
4413 12:47:16.645653
4414 12:47:16.645748 ==
4415 12:47:16.649052 Dram Type= 6, Freq= 0, CH_1, rank 0
4416 12:47:16.652575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 12:47:16.652692 ==
4418 12:47:16.655719 [Gating] SW mode calibration
4419 12:47:16.662113 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4420 12:47:16.669063 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4421 12:47:16.671961 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4422 12:47:16.675294 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4423 12:47:16.678611 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4424 12:47:16.685332 0 9 12 | B1->B0 | 3030 3030 | 1 1 | (1 0) (0 0)
4425 12:47:16.688393 0 9 16 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
4426 12:47:16.695656 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 12:47:16.698533 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 12:47:16.702096 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 12:47:16.705283 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 12:47:16.712076 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 12:47:16.715297 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 12:47:16.718595 0 10 12 | B1->B0 | 3131 3131 | 0 1 | (1 1) (0 0)
4433 12:47:16.724882 0 10 16 | B1->B0 | 4242 3e3e | 0 0 | (0 0) (0 0)
4434 12:47:16.728277 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 12:47:16.731699 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 12:47:16.738143 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 12:47:16.742067 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 12:47:16.745241 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 12:47:16.751309 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 12:47:16.754935 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4441 12:47:16.758218 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 12:47:16.765189 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 12:47:16.767997 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 12:47:16.771591 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 12:47:16.777964 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 12:47:16.781202 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 12:47:16.784664 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 12:47:16.791686 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 12:47:16.794510 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 12:47:16.798235 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 12:47:16.804379 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 12:47:16.808157 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 12:47:16.811541 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 12:47:16.817619 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 12:47:16.821017 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 12:47:16.824540 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 12:47:16.831138 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 12:47:16.831256 Total UI for P1: 0, mck2ui 16
4459 12:47:16.837339 best dqsien dly found for B0: ( 0, 13, 14)
4460 12:47:16.837477 Total UI for P1: 0, mck2ui 16
4461 12:47:16.844445 best dqsien dly found for B1: ( 0, 13, 14)
4462 12:47:16.847723 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4463 12:47:16.851125 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4464 12:47:16.851217
4465 12:47:16.854403 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4466 12:47:16.857490 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4467 12:47:16.860653 [Gating] SW calibration Done
4468 12:47:16.860736 ==
4469 12:47:16.863875 Dram Type= 6, Freq= 0, CH_1, rank 0
4470 12:47:16.867492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 12:47:16.867585 ==
4472 12:47:16.870722 RX Vref Scan: 0
4473 12:47:16.870828
4474 12:47:16.870917 RX Vref 0 -> 0, step: 1
4475 12:47:16.871005
4476 12:47:16.874328 RX Delay -230 -> 252, step: 16
4477 12:47:16.880617 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4478 12:47:16.883860 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4479 12:47:16.887240 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4480 12:47:16.890686 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4481 12:47:16.896961 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4482 12:47:16.900229 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4483 12:47:16.903320 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4484 12:47:16.906832 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4485 12:47:16.910337 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4486 12:47:16.917247 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4487 12:47:16.919922 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4488 12:47:16.923188 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4489 12:47:16.926696 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4490 12:47:16.933348 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4491 12:47:16.936783 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4492 12:47:16.939658 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4493 12:47:16.939774 ==
4494 12:47:16.943482 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 12:47:16.949982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 12:47:16.950095 ==
4497 12:47:16.950166 DQS Delay:
4498 12:47:16.950226 DQS0 = 0, DQS1 = 0
4499 12:47:16.952978 DQM Delay:
4500 12:47:16.953098 DQM0 = 37, DQM1 = 28
4501 12:47:16.956346 DQ Delay:
4502 12:47:16.959874 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4503 12:47:16.963085 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4504 12:47:16.966037 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4505 12:47:16.969346 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4506 12:47:16.969444
4507 12:47:16.969532
4508 12:47:16.969614 ==
4509 12:47:16.972711 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 12:47:16.976251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 12:47:16.976355 ==
4512 12:47:16.976421
4513 12:47:16.976527
4514 12:47:16.979623 TX Vref Scan disable
4515 12:47:16.979709 == TX Byte 0 ==
4516 12:47:16.985929 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4517 12:47:16.989318 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4518 12:47:16.989419 == TX Byte 1 ==
4519 12:47:16.996013 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4520 12:47:16.999266 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4521 12:47:16.999384 ==
4522 12:47:17.002746 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 12:47:17.005975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 12:47:17.006068 ==
4525 12:47:17.009103
4526 12:47:17.009192
4527 12:47:17.009273 TX Vref Scan disable
4528 12:47:17.013149 == TX Byte 0 ==
4529 12:47:17.016128 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4530 12:47:17.022463 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4531 12:47:17.022573 == TX Byte 1 ==
4532 12:47:17.026429 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4533 12:47:17.032485 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4534 12:47:17.032598
4535 12:47:17.032664 [DATLAT]
4536 12:47:17.032725 Freq=600, CH1 RK0
4537 12:47:17.032795
4538 12:47:17.036173 DATLAT Default: 0x9
4539 12:47:17.036263 0, 0xFFFF, sum = 0
4540 12:47:17.039285 1, 0xFFFF, sum = 0
4541 12:47:17.042565 2, 0xFFFF, sum = 0
4542 12:47:17.042649 3, 0xFFFF, sum = 0
4543 12:47:17.045585 4, 0xFFFF, sum = 0
4544 12:47:17.045668 5, 0xFFFF, sum = 0
4545 12:47:17.048852 6, 0xFFFF, sum = 0
4546 12:47:17.048948 7, 0xFFFF, sum = 0
4547 12:47:17.052529 8, 0x0, sum = 1
4548 12:47:17.052627 9, 0x0, sum = 2
4549 12:47:17.055492 10, 0x0, sum = 3
4550 12:47:17.055584 11, 0x0, sum = 4
4551 12:47:17.055671 best_step = 9
4552 12:47:17.055752
4553 12:47:17.059135 ==
4554 12:47:17.062061 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 12:47:17.065630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 12:47:17.065724 ==
4557 12:47:17.065812 RX Vref Scan: 1
4558 12:47:17.065894
4559 12:47:17.068810 RX Vref 0 -> 0, step: 1
4560 12:47:17.068897
4561 12:47:17.072218 RX Delay -195 -> 252, step: 8
4562 12:47:17.072307
4563 12:47:17.075367 Set Vref, RX VrefLevel [Byte0]: 56
4564 12:47:17.078583 [Byte1]: 48
4565 12:47:17.078676
4566 12:47:17.082118 Final RX Vref Byte 0 = 56 to rank0
4567 12:47:17.085386 Final RX Vref Byte 1 = 48 to rank0
4568 12:47:17.088692 Final RX Vref Byte 0 = 56 to rank1
4569 12:47:17.091634 Final RX Vref Byte 1 = 48 to rank1==
4570 12:47:17.095041 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 12:47:17.098507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 12:47:17.101892 ==
4573 12:47:17.101991 DQS Delay:
4574 12:47:17.102079 DQS0 = 0, DQS1 = 0
4575 12:47:17.105432 DQM Delay:
4576 12:47:17.105522 DQM0 = 39, DQM1 = 29
4577 12:47:17.108269 DQ Delay:
4578 12:47:17.111593 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4579 12:47:17.111687 DQ4 =36, DQ5 =52, DQ6 =48, DQ7 =36
4580 12:47:17.114753 DQ8 =12, DQ9 =16, DQ10 =32, DQ11 =20
4581 12:47:17.121711 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =36
4582 12:47:17.121824
4583 12:47:17.121916
4584 12:47:17.128232 [DQSOSCAuto] RK0, (LSB)MR18= 0x2835, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
4585 12:47:17.131350 CH1 RK0: MR19=808, MR18=2835
4586 12:47:17.138077 CH1_RK0: MR19=0x808, MR18=0x2835, DQSOSC=399, MR23=63, INC=164, DEC=109
4587 12:47:17.138197
4588 12:47:17.141431 ----->DramcWriteLeveling(PI) begin...
4589 12:47:17.141523 ==
4590 12:47:17.144441 Dram Type= 6, Freq= 0, CH_1, rank 1
4591 12:47:17.147722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 12:47:17.147842 ==
4593 12:47:17.151049 Write leveling (Byte 0): 29 => 29
4594 12:47:17.154473 Write leveling (Byte 1): 29 => 29
4595 12:47:17.157681 DramcWriteLeveling(PI) end<-----
4596 12:47:17.157778
4597 12:47:17.157881 ==
4598 12:47:17.161050 Dram Type= 6, Freq= 0, CH_1, rank 1
4599 12:47:17.164211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4600 12:47:17.164307 ==
4601 12:47:17.167926 [Gating] SW mode calibration
4602 12:47:17.174251 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4603 12:47:17.180884 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4604 12:47:17.184899 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4605 12:47:17.191144 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4606 12:47:17.194137 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4607 12:47:17.197488 0 9 12 | B1->B0 | 3131 2c2c | 0 0 | (1 1) (1 1)
4608 12:47:17.204515 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4609 12:47:17.207324 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 12:47:17.210951 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 12:47:17.217492 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 12:47:17.220844 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 12:47:17.223992 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 12:47:17.227362 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4615 12:47:17.234015 0 10 12 | B1->B0 | 2d2d 3e3e | 1 0 | (0 0) (0 0)
4616 12:47:17.237218 0 10 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
4617 12:47:17.240625 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 12:47:17.247271 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 12:47:17.250878 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 12:47:17.254038 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 12:47:17.260459 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 12:47:17.264113 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 12:47:17.267497 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 12:47:17.273894 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 12:47:17.277262 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 12:47:17.280636 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 12:47:17.286739 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 12:47:17.290631 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 12:47:17.293709 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 12:47:17.300106 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 12:47:17.303607 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 12:47:17.307003 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 12:47:17.313480 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 12:47:17.316874 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 12:47:17.319786 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 12:47:17.326646 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 12:47:17.329858 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 12:47:17.333266 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 12:47:17.339981 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 12:47:17.343166 Total UI for P1: 0, mck2ui 16
4641 12:47:17.346550 best dqsien dly found for B0: ( 0, 13, 10)
4642 12:47:17.346652 Total UI for P1: 0, mck2ui 16
4643 12:47:17.353341 best dqsien dly found for B1: ( 0, 13, 10)
4644 12:47:17.356259 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4645 12:47:17.359532 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4646 12:47:17.359631
4647 12:47:17.362987 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4648 12:47:17.366436 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4649 12:47:17.369612 [Gating] SW calibration Done
4650 12:47:17.369712 ==
4651 12:47:17.373016 Dram Type= 6, Freq= 0, CH_1, rank 1
4652 12:47:17.376422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4653 12:47:17.376521 ==
4654 12:47:17.379573 RX Vref Scan: 0
4655 12:47:17.379672
4656 12:47:17.382494 RX Vref 0 -> 0, step: 1
4657 12:47:17.382605
4658 12:47:17.382703 RX Delay -230 -> 252, step: 16
4659 12:47:17.389209 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4660 12:47:17.392833 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4661 12:47:17.395813 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4662 12:47:17.399267 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4663 12:47:17.406005 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4664 12:47:17.409055 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4665 12:47:17.412385 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4666 12:47:17.415851 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4667 12:47:17.422045 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4668 12:47:17.425572 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4669 12:47:17.429052 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4670 12:47:17.432120 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4671 12:47:17.438775 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4672 12:47:17.442447 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4673 12:47:17.445732 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4674 12:47:17.449008 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4675 12:47:17.449111 ==
4676 12:47:17.451929 Dram Type= 6, Freq= 0, CH_1, rank 1
4677 12:47:17.458889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4678 12:47:17.459016 ==
4679 12:47:17.459108 DQS Delay:
4680 12:47:17.461834 DQS0 = 0, DQS1 = 0
4681 12:47:17.461920 DQM Delay:
4682 12:47:17.462004 DQM0 = 35, DQM1 = 27
4683 12:47:17.465103 DQ Delay:
4684 12:47:17.468505 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4685 12:47:17.471860 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4686 12:47:17.475273 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4687 12:47:17.478466 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4688 12:47:17.478567
4689 12:47:17.478653
4690 12:47:17.478735 ==
4691 12:47:17.481420 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 12:47:17.484768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 12:47:17.484868 ==
4694 12:47:17.484957
4695 12:47:17.485034
4696 12:47:17.488578 TX Vref Scan disable
4697 12:47:17.491530 == TX Byte 0 ==
4698 12:47:17.495293 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4699 12:47:17.498393 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4700 12:47:17.501301 == TX Byte 1 ==
4701 12:47:17.504623 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4702 12:47:17.508438 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4703 12:47:17.508567 ==
4704 12:47:17.511567 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 12:47:17.515010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 12:47:17.518326 ==
4707 12:47:17.518438
4708 12:47:17.518526
4709 12:47:17.518603 TX Vref Scan disable
4710 12:47:17.521832 == TX Byte 0 ==
4711 12:47:17.525301 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4712 12:47:17.531622 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4713 12:47:17.531757 == TX Byte 1 ==
4714 12:47:17.535193 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4715 12:47:17.541595 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4716 12:47:17.541710
4717 12:47:17.541787 [DATLAT]
4718 12:47:17.541850 Freq=600, CH1 RK1
4719 12:47:17.541909
4720 12:47:17.544643 DATLAT Default: 0x9
4721 12:47:17.544721 0, 0xFFFF, sum = 0
4722 12:47:17.548340 1, 0xFFFF, sum = 0
4723 12:47:17.551526 2, 0xFFFF, sum = 0
4724 12:47:17.551618 3, 0xFFFF, sum = 0
4725 12:47:17.555014 4, 0xFFFF, sum = 0
4726 12:47:17.555101 5, 0xFFFF, sum = 0
4727 12:47:17.558345 6, 0xFFFF, sum = 0
4728 12:47:17.558441 7, 0xFFFF, sum = 0
4729 12:47:17.561813 8, 0x0, sum = 1
4730 12:47:17.561895 9, 0x0, sum = 2
4731 12:47:17.561961 10, 0x0, sum = 3
4732 12:47:17.564605 11, 0x0, sum = 4
4733 12:47:17.564688 best_step = 9
4734 12:47:17.564747
4735 12:47:17.568159 ==
4736 12:47:17.568237 Dram Type= 6, Freq= 0, CH_1, rank 1
4737 12:47:17.574912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4738 12:47:17.575019 ==
4739 12:47:17.575085 RX Vref Scan: 0
4740 12:47:17.575144
4741 12:47:17.577744 RX Vref 0 -> 0, step: 1
4742 12:47:17.577825
4743 12:47:17.581578 RX Delay -195 -> 252, step: 8
4744 12:47:17.587790 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4745 12:47:17.591218 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4746 12:47:17.594541 iDelay=205, Bit 2, Center 20 (-139 ~ 180) 320
4747 12:47:17.597735 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4748 12:47:17.601119 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4749 12:47:17.608146 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4750 12:47:17.611089 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4751 12:47:17.614555 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4752 12:47:17.618241 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4753 12:47:17.624111 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4754 12:47:17.627626 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4755 12:47:17.630786 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4756 12:47:17.634263 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4757 12:47:17.637689 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4758 12:47:17.644327 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4759 12:47:17.647516 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4760 12:47:17.647626 ==
4761 12:47:17.650709 Dram Type= 6, Freq= 0, CH_1, rank 1
4762 12:47:17.653910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4763 12:47:17.654009 ==
4764 12:47:17.657541 DQS Delay:
4765 12:47:17.657656 DQS0 = 0, DQS1 = 0
4766 12:47:17.660830 DQM Delay:
4767 12:47:17.660923 DQM0 = 35, DQM1 = 29
4768 12:47:17.660989 DQ Delay:
4769 12:47:17.663806 DQ0 =40, DQ1 =32, DQ2 =20, DQ3 =32
4770 12:47:17.667167 DQ4 =36, DQ5 =44, DQ6 =48, DQ7 =32
4771 12:47:17.670927 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =24
4772 12:47:17.673703 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4773 12:47:17.673796
4774 12:47:17.673861
4775 12:47:17.683841 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f5d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
4776 12:47:17.687115 CH1 RK1: MR19=808, MR18=3F5D
4777 12:47:17.694061 CH1_RK1: MR19=0x808, MR18=0x3F5D, DQSOSC=392, MR23=63, INC=170, DEC=113
4778 12:47:17.694224 [RxdqsGatingPostProcess] freq 600
4779 12:47:17.700337 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4780 12:47:17.704097 Pre-setting of DQS Precalculation
4781 12:47:17.706799 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4782 12:47:17.717432 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4783 12:47:17.723464 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4784 12:47:17.723615
4785 12:47:17.723714
4786 12:47:17.726955 [Calibration Summary] 1200 Mbps
4787 12:47:17.727069 CH 0, Rank 0
4788 12:47:17.730201 SW Impedance : PASS
4789 12:47:17.730336 DUTY Scan : NO K
4790 12:47:17.733542 ZQ Calibration : PASS
4791 12:47:17.737114 Jitter Meter : NO K
4792 12:47:17.737219 CBT Training : PASS
4793 12:47:17.740250 Write leveling : PASS
4794 12:47:17.744244 RX DQS gating : PASS
4795 12:47:17.744334 RX DQ/DQS(RDDQC) : PASS
4796 12:47:17.746667 TX DQ/DQS : PASS
4797 12:47:17.750129 RX DATLAT : PASS
4798 12:47:17.750210 RX DQ/DQS(Engine): PASS
4799 12:47:17.753583 TX OE : NO K
4800 12:47:17.753661 All Pass.
4801 12:47:17.753724
4802 12:47:17.756709 CH 0, Rank 1
4803 12:47:17.756800 SW Impedance : PASS
4804 12:47:17.760239 DUTY Scan : NO K
4805 12:47:17.762994 ZQ Calibration : PASS
4806 12:47:17.763105 Jitter Meter : NO K
4807 12:47:17.766610 CBT Training : PASS
4808 12:47:17.769965 Write leveling : PASS
4809 12:47:17.770046 RX DQS gating : PASS
4810 12:47:17.773407 RX DQ/DQS(RDDQC) : PASS
4811 12:47:17.776432 TX DQ/DQS : PASS
4812 12:47:17.776522 RX DATLAT : PASS
4813 12:47:17.780113 RX DQ/DQS(Engine): PASS
4814 12:47:17.780191 TX OE : NO K
4815 12:47:17.783365 All Pass.
4816 12:47:17.783471
4817 12:47:17.783555 CH 1, Rank 0
4818 12:47:17.786682 SW Impedance : PASS
4819 12:47:17.786762 DUTY Scan : NO K
4820 12:47:17.789903 ZQ Calibration : PASS
4821 12:47:17.793313 Jitter Meter : NO K
4822 12:47:17.793396 CBT Training : PASS
4823 12:47:17.796723 Write leveling : PASS
4824 12:47:17.799638 RX DQS gating : PASS
4825 12:47:17.799750 RX DQ/DQS(RDDQC) : PASS
4826 12:47:17.803005 TX DQ/DQS : PASS
4827 12:47:17.806360 RX DATLAT : PASS
4828 12:47:17.806447 RX DQ/DQS(Engine): PASS
4829 12:47:17.809549 TX OE : NO K
4830 12:47:17.809701 All Pass.
4831 12:47:17.809797
4832 12:47:17.812988 CH 1, Rank 1
4833 12:47:17.813104 SW Impedance : PASS
4834 12:47:17.816393 DUTY Scan : NO K
4835 12:47:17.820016 ZQ Calibration : PASS
4836 12:47:17.820146 Jitter Meter : NO K
4837 12:47:17.822831 CBT Training : PASS
4838 12:47:17.826319 Write leveling : PASS
4839 12:47:17.826446 RX DQS gating : PASS
4840 12:47:17.829477 RX DQ/DQS(RDDQC) : PASS
4841 12:47:17.833086 TX DQ/DQS : PASS
4842 12:47:17.833210 RX DATLAT : PASS
4843 12:47:17.836347 RX DQ/DQS(Engine): PASS
4844 12:47:17.836439 TX OE : NO K
4845 12:47:17.839207 All Pass.
4846 12:47:17.839321
4847 12:47:17.839427 DramC Write-DBI off
4848 12:47:17.842528 PER_BANK_REFRESH: Hybrid Mode
4849 12:47:17.846180 TX_TRACKING: ON
4850 12:47:17.852710 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4851 12:47:17.856009 [FAST_K] Save calibration result to emmc
4852 12:47:17.862900 dramc_set_vcore_voltage set vcore to 662500
4853 12:47:17.863050 Read voltage for 933, 3
4854 12:47:17.863154 Vio18 = 0
4855 12:47:17.866285 Vcore = 662500
4856 12:47:17.866391 Vdram = 0
4857 12:47:17.866485 Vddq = 0
4858 12:47:17.869114 Vmddr = 0
4859 12:47:17.872776 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4860 12:47:17.879307 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4861 12:47:17.882922 MEM_TYPE=3, freq_sel=17
4862 12:47:17.883020 sv_algorithm_assistance_LP4_1600
4863 12:47:17.889392 ============ PULL DRAM RESETB DOWN ============
4864 12:47:17.892816 ========== PULL DRAM RESETB DOWN end =========
4865 12:47:17.896005 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4866 12:47:17.899566 ===================================
4867 12:47:17.902899 LPDDR4 DRAM CONFIGURATION
4868 12:47:17.905674 ===================================
4869 12:47:17.909244 EX_ROW_EN[0] = 0x0
4870 12:47:17.909362 EX_ROW_EN[1] = 0x0
4871 12:47:17.912507 LP4Y_EN = 0x0
4872 12:47:17.912635 WORK_FSP = 0x0
4873 12:47:17.915744 WL = 0x3
4874 12:47:17.915861 RL = 0x3
4875 12:47:17.918790 BL = 0x2
4876 12:47:17.918913 RPST = 0x0
4877 12:47:17.922350 RD_PRE = 0x0
4878 12:47:17.922491 WR_PRE = 0x1
4879 12:47:17.925929 WR_PST = 0x0
4880 12:47:17.926066 DBI_WR = 0x0
4881 12:47:17.929175 DBI_RD = 0x0
4882 12:47:17.929321 OTF = 0x1
4883 12:47:17.932119 ===================================
4884 12:47:17.935607 ===================================
4885 12:47:17.938684 ANA top config
4886 12:47:17.942064 ===================================
4887 12:47:17.945542 DLL_ASYNC_EN = 0
4888 12:47:17.945672 ALL_SLAVE_EN = 1
4889 12:47:17.948919 NEW_RANK_MODE = 1
4890 12:47:17.952197 DLL_IDLE_MODE = 1
4891 12:47:17.955430 LP45_APHY_COMB_EN = 1
4892 12:47:17.958713 TX_ODT_DIS = 1
4893 12:47:17.958827 NEW_8X_MODE = 1
4894 12:47:17.962174 ===================================
4895 12:47:17.965268 ===================================
4896 12:47:17.968777 data_rate = 1866
4897 12:47:17.972151 CKR = 1
4898 12:47:17.975595 DQ_P2S_RATIO = 8
4899 12:47:17.979002 ===================================
4900 12:47:17.982228 CA_P2S_RATIO = 8
4901 12:47:17.982319 DQ_CA_OPEN = 0
4902 12:47:17.985297 DQ_SEMI_OPEN = 0
4903 12:47:17.988696 CA_SEMI_OPEN = 0
4904 12:47:17.991722 CA_FULL_RATE = 0
4905 12:47:17.995520 DQ_CKDIV4_EN = 1
4906 12:47:17.998877 CA_CKDIV4_EN = 1
4907 12:47:17.999025 CA_PREDIV_EN = 0
4908 12:47:18.001839 PH8_DLY = 0
4909 12:47:18.005232 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4910 12:47:18.008293 DQ_AAMCK_DIV = 4
4911 12:47:18.011641 CA_AAMCK_DIV = 4
4912 12:47:18.015201 CA_ADMCK_DIV = 4
4913 12:47:18.015315 DQ_TRACK_CA_EN = 0
4914 12:47:18.018530 CA_PICK = 933
4915 12:47:18.021531 CA_MCKIO = 933
4916 12:47:18.025292 MCKIO_SEMI = 0
4917 12:47:18.028591 PLL_FREQ = 3732
4918 12:47:18.032121 DQ_UI_PI_RATIO = 32
4919 12:47:18.034942 CA_UI_PI_RATIO = 0
4920 12:47:18.038496 ===================================
4921 12:47:18.041624 ===================================
4922 12:47:18.041753 memory_type:LPDDR4
4923 12:47:18.044922 GP_NUM : 10
4924 12:47:18.048131 SRAM_EN : 1
4925 12:47:18.048254 MD32_EN : 0
4926 12:47:18.052314 ===================================
4927 12:47:18.055231 [ANA_INIT] >>>>>>>>>>>>>>
4928 12:47:18.058226 <<<<<< [CONFIGURE PHASE]: ANA_TX
4929 12:47:18.061992 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4930 12:47:18.064984 ===================================
4931 12:47:18.068460 data_rate = 1866,PCW = 0X8f00
4932 12:47:18.071765 ===================================
4933 12:47:18.074929 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4934 12:47:18.078642 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4935 12:47:18.084846 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4936 12:47:18.088079 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4937 12:47:18.091552 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4938 12:47:18.094654 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4939 12:47:18.098003 [ANA_INIT] flow start
4940 12:47:18.101318 [ANA_INIT] PLL >>>>>>>>
4941 12:47:18.101475 [ANA_INIT] PLL <<<<<<<<
4942 12:47:18.104862 [ANA_INIT] MIDPI >>>>>>>>
4943 12:47:18.108116 [ANA_INIT] MIDPI <<<<<<<<
4944 12:47:18.111620 [ANA_INIT] DLL >>>>>>>>
4945 12:47:18.111745 [ANA_INIT] flow end
4946 12:47:18.114658 ============ LP4 DIFF to SE enter ============
4947 12:47:18.121381 ============ LP4 DIFF to SE exit ============
4948 12:47:18.121519 [ANA_INIT] <<<<<<<<<<<<<
4949 12:47:18.124926 [Flow] Enable top DCM control >>>>>
4950 12:47:18.127893 [Flow] Enable top DCM control <<<<<
4951 12:47:18.131599 Enable DLL master slave shuffle
4952 12:47:18.137804 ==============================================================
4953 12:47:18.137988 Gating Mode config
4954 12:47:18.144843 ==============================================================
4955 12:47:18.147802 Config description:
4956 12:47:18.158044 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4957 12:47:18.161387 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4958 12:47:18.168027 SELPH_MODE 0: By rank 1: By Phase
4959 12:47:18.174396 ==============================================================
4960 12:47:18.174614 GAT_TRACK_EN = 1
4961 12:47:18.177910 RX_GATING_MODE = 2
4962 12:47:18.181148 RX_GATING_TRACK_MODE = 2
4963 12:47:18.184573 SELPH_MODE = 1
4964 12:47:18.188390 PICG_EARLY_EN = 1
4965 12:47:18.191164 VALID_LAT_VALUE = 1
4966 12:47:18.198188 ==============================================================
4967 12:47:18.201401 Enter into Gating configuration >>>>
4968 12:47:18.204669 Exit from Gating configuration <<<<
4969 12:47:18.207985 Enter into DVFS_PRE_config >>>>>
4970 12:47:18.217982 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4971 12:47:18.220830 Exit from DVFS_PRE_config <<<<<
4972 12:47:18.224210 Enter into PICG configuration >>>>
4973 12:47:18.227602 Exit from PICG configuration <<<<
4974 12:47:18.231065 [RX_INPUT] configuration >>>>>
4975 12:47:18.234470 [RX_INPUT] configuration <<<<<
4976 12:47:18.237341 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4977 12:47:18.244104 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4978 12:47:18.250637 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4979 12:47:18.254136 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4980 12:47:18.260879 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4981 12:47:18.267834 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4982 12:47:18.270760 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4983 12:47:18.276996 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4984 12:47:18.280423 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4985 12:47:18.284153 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4986 12:47:18.287114 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4987 12:47:18.293765 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4988 12:47:18.297212 ===================================
4989 12:47:18.297342 LPDDR4 DRAM CONFIGURATION
4990 12:47:18.300635 ===================================
4991 12:47:18.303809 EX_ROW_EN[0] = 0x0
4992 12:47:18.306974 EX_ROW_EN[1] = 0x0
4993 12:47:18.307110 LP4Y_EN = 0x0
4994 12:47:18.310416 WORK_FSP = 0x0
4995 12:47:18.310538 WL = 0x3
4996 12:47:18.313757 RL = 0x3
4997 12:47:18.313872 BL = 0x2
4998 12:47:18.317240 RPST = 0x0
4999 12:47:18.317384 RD_PRE = 0x0
5000 12:47:18.320121 WR_PRE = 0x1
5001 12:47:18.320276 WR_PST = 0x0
5002 12:47:18.323711 DBI_WR = 0x0
5003 12:47:18.323880 DBI_RD = 0x0
5004 12:47:18.326978 OTF = 0x1
5005 12:47:18.330556 ===================================
5006 12:47:18.333607 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5007 12:47:18.337042 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5008 12:47:18.343591 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5009 12:47:18.346967 ===================================
5010 12:47:18.347062 LPDDR4 DRAM CONFIGURATION
5011 12:47:18.349871 ===================================
5012 12:47:18.353125 EX_ROW_EN[0] = 0x10
5013 12:47:18.356899 EX_ROW_EN[1] = 0x0
5014 12:47:18.357017 LP4Y_EN = 0x0
5015 12:47:18.360283 WORK_FSP = 0x0
5016 12:47:18.360426 WL = 0x3
5017 12:47:18.363641 RL = 0x3
5018 12:47:18.363737 BL = 0x2
5019 12:47:18.367265 RPST = 0x0
5020 12:47:18.367350 RD_PRE = 0x0
5021 12:47:18.369746 WR_PRE = 0x1
5022 12:47:18.369849 WR_PST = 0x0
5023 12:47:18.373110 DBI_WR = 0x0
5024 12:47:18.373215 DBI_RD = 0x0
5025 12:47:18.376949 OTF = 0x1
5026 12:47:18.379750 ===================================
5027 12:47:18.386820 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5028 12:47:18.389895 nWR fixed to 30
5029 12:47:18.390043 [ModeRegInit_LP4] CH0 RK0
5030 12:47:18.393201 [ModeRegInit_LP4] CH0 RK1
5031 12:47:18.396640 [ModeRegInit_LP4] CH1 RK0
5032 12:47:18.399728 [ModeRegInit_LP4] CH1 RK1
5033 12:47:18.399855 match AC timing 9
5034 12:47:18.402994 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5035 12:47:18.409675 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5036 12:47:18.412814 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5037 12:47:18.419490 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5038 12:47:18.423104 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5039 12:47:18.423300 ==
5040 12:47:18.426673 Dram Type= 6, Freq= 0, CH_0, rank 0
5041 12:47:18.429580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5042 12:47:18.429759 ==
5043 12:47:18.436443 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5044 12:47:18.442839 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5045 12:47:18.446190 [CA 0] Center 38 (8~69) winsize 62
5046 12:47:18.449591 [CA 1] Center 38 (7~69) winsize 63
5047 12:47:18.452991 [CA 2] Center 35 (5~66) winsize 62
5048 12:47:18.455885 [CA 3] Center 35 (4~66) winsize 63
5049 12:47:18.459294 [CA 4] Center 34 (4~65) winsize 62
5050 12:47:18.462957 [CA 5] Center 33 (3~64) winsize 62
5051 12:47:18.463076
5052 12:47:18.466245 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5053 12:47:18.466358
5054 12:47:18.469445 [CATrainingPosCal] consider 1 rank data
5055 12:47:18.472770 u2DelayCellTimex100 = 270/100 ps
5056 12:47:18.476152 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5057 12:47:18.479654 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5058 12:47:18.482736 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5059 12:47:18.485908 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5060 12:47:18.489527 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5061 12:47:18.492934 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5062 12:47:18.493025
5063 12:47:18.499528 CA PerBit enable=1, Macro0, CA PI delay=33
5064 12:47:18.499632
5065 12:47:18.499699 [CBTSetCACLKResult] CA Dly = 33
5066 12:47:18.502520 CS Dly: 6 (0~37)
5067 12:47:18.502637 ==
5068 12:47:18.505623 Dram Type= 6, Freq= 0, CH_0, rank 1
5069 12:47:18.509242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5070 12:47:18.509363 ==
5071 12:47:18.515903 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5072 12:47:18.522700 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5073 12:47:18.525715 [CA 0] Center 38 (8~69) winsize 62
5074 12:47:18.528818 [CA 1] Center 38 (8~69) winsize 62
5075 12:47:18.532266 [CA 2] Center 35 (5~66) winsize 62
5076 12:47:18.535678 [CA 3] Center 35 (5~66) winsize 62
5077 12:47:18.539085 [CA 4] Center 34 (4~65) winsize 62
5078 12:47:18.542468 [CA 5] Center 33 (3~64) winsize 62
5079 12:47:18.542575
5080 12:47:18.545915 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5081 12:47:18.546024
5082 12:47:18.548705 [CATrainingPosCal] consider 2 rank data
5083 12:47:18.552289 u2DelayCellTimex100 = 270/100 ps
5084 12:47:18.555762 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5085 12:47:18.559080 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5086 12:47:18.561985 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5087 12:47:18.565529 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5088 12:47:18.568633 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5089 12:47:18.575170 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5090 12:47:18.575286
5091 12:47:18.578847 CA PerBit enable=1, Macro0, CA PI delay=33
5092 12:47:18.578948
5093 12:47:18.582391 [CBTSetCACLKResult] CA Dly = 33
5094 12:47:18.582509 CS Dly: 6 (0~38)
5095 12:47:18.582614
5096 12:47:18.585184 ----->DramcWriteLeveling(PI) begin...
5097 12:47:18.585286 ==
5098 12:47:18.588532 Dram Type= 6, Freq= 0, CH_0, rank 0
5099 12:47:18.595109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5100 12:47:18.595228 ==
5101 12:47:18.598881 Write leveling (Byte 0): 31 => 31
5102 12:47:18.598972 Write leveling (Byte 1): 31 => 31
5103 12:47:18.601904 DramcWriteLeveling(PI) end<-----
5104 12:47:18.601985
5105 12:47:18.602047 ==
5106 12:47:18.605392 Dram Type= 6, Freq= 0, CH_0, rank 0
5107 12:47:18.611721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 12:47:18.611853 ==
5109 12:47:18.615250 [Gating] SW mode calibration
5110 12:47:18.622167 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5111 12:47:18.625366 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5112 12:47:18.631889 0 14 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5113 12:47:18.635120 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5114 12:47:18.638178 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 12:47:18.645011 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 12:47:18.648397 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 12:47:18.651769 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 12:47:18.658156 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 12:47:18.661631 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5120 12:47:18.665019 0 15 0 | B1->B0 | 3434 2c2c | 0 1 | (0 1) (1 0)
5121 12:47:18.671875 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5122 12:47:18.675224 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 12:47:18.678347 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 12:47:18.685171 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 12:47:18.688359 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 12:47:18.692030 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 12:47:18.698022 0 15 28 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
5128 12:47:18.701331 1 0 0 | B1->B0 | 2a2a 3939 | 0 1 | (1 1) (0 0)
5129 12:47:18.704763 1 0 4 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
5130 12:47:18.708134 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 12:47:18.714840 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 12:47:18.717938 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 12:47:18.721742 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 12:47:18.728017 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 12:47:18.731646 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5136 12:47:18.734748 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5137 12:47:18.741335 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5138 12:47:18.744734 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 12:47:18.748331 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 12:47:18.754666 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 12:47:18.757953 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 12:47:18.761588 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 12:47:18.767700 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 12:47:18.771150 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 12:47:18.774742 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 12:47:18.780854 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 12:47:18.784320 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 12:47:18.787364 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 12:47:18.794266 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 12:47:18.797469 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 12:47:18.801187 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5152 12:47:18.807571 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5153 12:47:18.810878 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 12:47:18.814525 Total UI for P1: 0, mck2ui 16
5155 12:47:18.817517 best dqsien dly found for B0: ( 1, 2, 30)
5156 12:47:18.821281 Total UI for P1: 0, mck2ui 16
5157 12:47:18.824494 best dqsien dly found for B1: ( 1, 3, 2)
5158 12:47:18.827567 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5159 12:47:18.831051 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5160 12:47:18.831149
5161 12:47:18.834061 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5162 12:47:18.837504 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5163 12:47:18.840672 [Gating] SW calibration Done
5164 12:47:18.840768 ==
5165 12:47:18.843982 Dram Type= 6, Freq= 0, CH_0, rank 0
5166 12:47:18.847191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5167 12:47:18.847311 ==
5168 12:47:18.851230 RX Vref Scan: 0
5169 12:47:18.851350
5170 12:47:18.854124 RX Vref 0 -> 0, step: 1
5171 12:47:18.854212
5172 12:47:18.854277 RX Delay -80 -> 252, step: 8
5173 12:47:18.860795 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5174 12:47:18.864306 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5175 12:47:18.867259 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5176 12:47:18.870656 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5177 12:47:18.873985 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5178 12:47:18.877393 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5179 12:47:18.883698 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5180 12:47:18.887219 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5181 12:47:18.890611 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5182 12:47:18.893662 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5183 12:47:18.896963 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5184 12:47:18.903841 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5185 12:47:18.906826 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5186 12:47:18.910163 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5187 12:47:18.913689 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5188 12:47:18.917026 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5189 12:47:18.920670 ==
5190 12:47:18.923549 Dram Type= 6, Freq= 0, CH_0, rank 0
5191 12:47:18.926785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5192 12:47:18.926899 ==
5193 12:47:18.926992 DQS Delay:
5194 12:47:18.930171 DQS0 = 0, DQS1 = 0
5195 12:47:18.930252 DQM Delay:
5196 12:47:18.933825 DQM0 = 94, DQM1 = 82
5197 12:47:18.933941 DQ Delay:
5198 12:47:18.937050 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5199 12:47:18.940538 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =107
5200 12:47:18.943454 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75
5201 12:47:18.946769 DQ12 =83, DQ13 =87, DQ14 =91, DQ15 =91
5202 12:47:18.946884
5203 12:47:18.946977
5204 12:47:18.947074 ==
5205 12:47:18.949809 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 12:47:18.953306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 12:47:18.953390 ==
5208 12:47:18.953466
5209 12:47:18.953525
5210 12:47:18.956763 TX Vref Scan disable
5211 12:47:18.960149 == TX Byte 0 ==
5212 12:47:18.963235 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5213 12:47:18.966863 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5214 12:47:18.969937 == TX Byte 1 ==
5215 12:47:18.973790 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5216 12:47:18.976969 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5217 12:47:18.977067 ==
5218 12:47:18.980215 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 12:47:18.987058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 12:47:18.987199 ==
5221 12:47:18.987295
5222 12:47:18.987394
5223 12:47:18.987468 TX Vref Scan disable
5224 12:47:18.990438 == TX Byte 0 ==
5225 12:47:18.993848 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5226 12:47:19.000665 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5227 12:47:19.000791 == TX Byte 1 ==
5228 12:47:19.004195 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5229 12:47:19.010357 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5230 12:47:19.010495
5231 12:47:19.010589 [DATLAT]
5232 12:47:19.010663 Freq=933, CH0 RK0
5233 12:47:19.010724
5234 12:47:19.013477 DATLAT Default: 0xd
5235 12:47:19.013585 0, 0xFFFF, sum = 0
5236 12:47:19.017128 1, 0xFFFF, sum = 0
5237 12:47:19.020540 2, 0xFFFF, sum = 0
5238 12:47:19.020650 3, 0xFFFF, sum = 0
5239 12:47:19.023403 4, 0xFFFF, sum = 0
5240 12:47:19.023507 5, 0xFFFF, sum = 0
5241 12:47:19.026822 6, 0xFFFF, sum = 0
5242 12:47:19.026934 7, 0xFFFF, sum = 0
5243 12:47:19.030169 8, 0xFFFF, sum = 0
5244 12:47:19.030249 9, 0xFFFF, sum = 0
5245 12:47:19.033613 10, 0x0, sum = 1
5246 12:47:19.033721 11, 0x0, sum = 2
5247 12:47:19.036809 12, 0x0, sum = 3
5248 12:47:19.036890 13, 0x0, sum = 4
5249 12:47:19.036953 best_step = 11
5250 12:47:19.037028
5251 12:47:19.040010 ==
5252 12:47:19.043869 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 12:47:19.046650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 12:47:19.046761 ==
5255 12:47:19.046852 RX Vref Scan: 1
5256 12:47:19.046949
5257 12:47:19.050340 RX Vref 0 -> 0, step: 1
5258 12:47:19.050448
5259 12:47:19.053523 RX Delay -69 -> 252, step: 4
5260 12:47:19.053623
5261 12:47:19.056627 Set Vref, RX VrefLevel [Byte0]: 62
5262 12:47:19.060211 [Byte1]: 56
5263 12:47:19.060310
5264 12:47:19.063431 Final RX Vref Byte 0 = 62 to rank0
5265 12:47:19.066920 Final RX Vref Byte 1 = 56 to rank0
5266 12:47:19.070429 Final RX Vref Byte 0 = 62 to rank1
5267 12:47:19.073430 Final RX Vref Byte 1 = 56 to rank1==
5268 12:47:19.076873 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 12:47:19.080194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 12:47:19.083029 ==
5271 12:47:19.083132 DQS Delay:
5272 12:47:19.083202 DQS0 = 0, DQS1 = 0
5273 12:47:19.086848 DQM Delay:
5274 12:47:19.086976 DQM0 = 95, DQM1 = 83
5275 12:47:19.090144 DQ Delay:
5276 12:47:19.093084 DQ0 =94, DQ1 =94, DQ2 =92, DQ3 =92
5277 12:47:19.096510 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5278 12:47:19.100065 DQ8 =78, DQ9 =72, DQ10 =82, DQ11 =80
5279 12:47:19.103272 DQ12 =86, DQ13 =88, DQ14 =96, DQ15 =88
5280 12:47:19.103394
5281 12:47:19.103489
5282 12:47:19.109669 [DQSOSCAuto] RK0, (LSB)MR18= 0x1413, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5283 12:47:19.113612 CH0 RK0: MR19=505, MR18=1413
5284 12:47:19.119593 CH0_RK0: MR19=0x505, MR18=0x1413, DQSOSC=415, MR23=63, INC=62, DEC=41
5285 12:47:19.119727
5286 12:47:19.123285 ----->DramcWriteLeveling(PI) begin...
5287 12:47:19.123422 ==
5288 12:47:19.126414 Dram Type= 6, Freq= 0, CH_0, rank 1
5289 12:47:19.129904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 12:47:19.130035 ==
5291 12:47:19.133006 Write leveling (Byte 0): 29 => 29
5292 12:47:19.136071 Write leveling (Byte 1): 29 => 29
5293 12:47:19.139827 DramcWriteLeveling(PI) end<-----
5294 12:47:19.139957
5295 12:47:19.140052 ==
5296 12:47:19.143307 Dram Type= 6, Freq= 0, CH_0, rank 1
5297 12:47:19.146344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 12:47:19.146457 ==
5299 12:47:19.149472 [Gating] SW mode calibration
5300 12:47:19.156051 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5301 12:47:19.163031 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5302 12:47:19.166361 0 14 0 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
5303 12:47:19.172685 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 12:47:19.175957 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 12:47:19.179288 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 12:47:19.182761 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 12:47:19.189280 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 12:47:19.192489 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 12:47:19.195856 0 14 28 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
5310 12:47:19.202475 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
5311 12:47:19.205940 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 12:47:19.209404 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 12:47:19.216078 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 12:47:19.219277 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 12:47:19.222168 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 12:47:19.229174 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 12:47:19.232491 0 15 28 | B1->B0 | 2424 3838 | 0 0 | (0 0) (0 0)
5318 12:47:19.235350 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5319 12:47:19.242191 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 12:47:19.245411 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 12:47:19.248816 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 12:47:19.255683 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 12:47:19.258763 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 12:47:19.262178 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 12:47:19.269106 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5326 12:47:19.272174 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5327 12:47:19.275790 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 12:47:19.282294 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 12:47:19.285772 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 12:47:19.289050 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 12:47:19.295411 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 12:47:19.298785 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 12:47:19.301936 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 12:47:19.308951 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 12:47:19.312238 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 12:47:19.315203 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 12:47:19.321763 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 12:47:19.325245 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 12:47:19.328621 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 12:47:19.335109 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5341 12:47:19.338776 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 12:47:19.342013 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 12:47:19.344939 Total UI for P1: 0, mck2ui 16
5344 12:47:19.348389 best dqsien dly found for B0: ( 1, 2, 30)
5345 12:47:19.351444 Total UI for P1: 0, mck2ui 16
5346 12:47:19.355015 best dqsien dly found for B1: ( 1, 2, 30)
5347 12:47:19.358414 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5348 12:47:19.361744 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5349 12:47:19.361868
5350 12:47:19.364896 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5351 12:47:19.371593 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5352 12:47:19.371716 [Gating] SW calibration Done
5353 12:47:19.371783 ==
5354 12:47:19.374787 Dram Type= 6, Freq= 0, CH_0, rank 1
5355 12:47:19.381605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5356 12:47:19.381760 ==
5357 12:47:19.381857 RX Vref Scan: 0
5358 12:47:19.381945
5359 12:47:19.384898 RX Vref 0 -> 0, step: 1
5360 12:47:19.384982
5361 12:47:19.388434 RX Delay -80 -> 252, step: 8
5362 12:47:19.391159 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5363 12:47:19.394746 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5364 12:47:19.398251 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5365 12:47:19.404489 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5366 12:47:19.408007 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5367 12:47:19.411254 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5368 12:47:19.414390 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5369 12:47:19.417656 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5370 12:47:19.421251 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5371 12:47:19.427620 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5372 12:47:19.431110 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5373 12:47:19.434576 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5374 12:47:19.438051 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5375 12:47:19.440925 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5376 12:47:19.447543 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5377 12:47:19.450949 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5378 12:47:19.451065 ==
5379 12:47:19.454267 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 12:47:19.457767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 12:47:19.457889 ==
5382 12:47:19.461194 DQS Delay:
5383 12:47:19.461299 DQS0 = 0, DQS1 = 0
5384 12:47:19.461365 DQM Delay:
5385 12:47:19.464784 DQM0 = 92, DQM1 = 83
5386 12:47:19.464880 DQ Delay:
5387 12:47:19.467826 DQ0 =91, DQ1 =95, DQ2 =87, DQ3 =91
5388 12:47:19.470648 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =103
5389 12:47:19.474054 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5390 12:47:19.477488 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5391 12:47:19.477596
5392 12:47:19.477662
5393 12:47:19.477721 ==
5394 12:47:19.480795 Dram Type= 6, Freq= 0, CH_0, rank 1
5395 12:47:19.487587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5396 12:47:19.487710 ==
5397 12:47:19.487794
5398 12:47:19.487855
5399 12:47:19.487912 TX Vref Scan disable
5400 12:47:19.490877 == TX Byte 0 ==
5401 12:47:19.494318 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5402 12:47:19.497873 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5403 12:47:19.500989 == TX Byte 1 ==
5404 12:47:19.504269 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5405 12:47:19.507613 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5406 12:47:19.511052 ==
5407 12:47:19.514340 Dram Type= 6, Freq= 0, CH_0, rank 1
5408 12:47:19.517548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5409 12:47:19.517642 ==
5410 12:47:19.517722
5411 12:47:19.517784
5412 12:47:19.521134 TX Vref Scan disable
5413 12:47:19.521244 == TX Byte 0 ==
5414 12:47:19.527674 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5415 12:47:19.531002 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5416 12:47:19.531098 == TX Byte 1 ==
5417 12:47:19.537286 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5418 12:47:19.540909 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5419 12:47:19.541027
5420 12:47:19.541109 [DATLAT]
5421 12:47:19.543987 Freq=933, CH0 RK1
5422 12:47:19.544066
5423 12:47:19.544125 DATLAT Default: 0xb
5424 12:47:19.547356 0, 0xFFFF, sum = 0
5425 12:47:19.547471 1, 0xFFFF, sum = 0
5426 12:47:19.550668 2, 0xFFFF, sum = 0
5427 12:47:19.550770 3, 0xFFFF, sum = 0
5428 12:47:19.553860 4, 0xFFFF, sum = 0
5429 12:47:19.557069 5, 0xFFFF, sum = 0
5430 12:47:19.557160 6, 0xFFFF, sum = 0
5431 12:47:19.560408 7, 0xFFFF, sum = 0
5432 12:47:19.560499 8, 0xFFFF, sum = 0
5433 12:47:19.563849 9, 0xFFFF, sum = 0
5434 12:47:19.563937 10, 0x0, sum = 1
5435 12:47:19.567006 11, 0x0, sum = 2
5436 12:47:19.567114 12, 0x0, sum = 3
5437 12:47:19.567206 13, 0x0, sum = 4
5438 12:47:19.570537 best_step = 11
5439 12:47:19.570614
5440 12:47:19.570676 ==
5441 12:47:19.573871 Dram Type= 6, Freq= 0, CH_0, rank 1
5442 12:47:19.577097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5443 12:47:19.577185 ==
5444 12:47:19.580555 RX Vref Scan: 0
5445 12:47:19.580636
5446 12:47:19.583415 RX Vref 0 -> 0, step: 1
5447 12:47:19.583532
5448 12:47:19.583621 RX Delay -77 -> 252, step: 4
5449 12:47:19.591424 iDelay=199, Bit 0, Center 90 (-1 ~ 182) 184
5450 12:47:19.594897 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5451 12:47:19.598131 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5452 12:47:19.601510 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5453 12:47:19.604663 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5454 12:47:19.611358 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5455 12:47:19.614708 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5456 12:47:19.617622 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5457 12:47:19.621248 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5458 12:47:19.624717 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5459 12:47:19.630904 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5460 12:47:19.634516 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5461 12:47:19.637944 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5462 12:47:19.641394 iDelay=199, Bit 13, Center 88 (-5 ~ 182) 188
5463 12:47:19.644517 iDelay=199, Bit 14, Center 92 (-1 ~ 186) 188
5464 12:47:19.651000 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5465 12:47:19.651105 ==
5466 12:47:19.654330 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 12:47:19.657886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 12:47:19.657995 ==
5469 12:47:19.658087 DQS Delay:
5470 12:47:19.661001 DQS0 = 0, DQS1 = 0
5471 12:47:19.661081 DQM Delay:
5472 12:47:19.664045 DQM0 = 92, DQM1 = 84
5473 12:47:19.664126 DQ Delay:
5474 12:47:19.667447 DQ0 =90, DQ1 =92, DQ2 =90, DQ3 =88
5475 12:47:19.670730 DQ4 =92, DQ5 =80, DQ6 =106, DQ7 =104
5476 12:47:19.674146 DQ8 =78, DQ9 =72, DQ10 =84, DQ11 =78
5477 12:47:19.677435 DQ12 =90, DQ13 =88, DQ14 =92, DQ15 =92
5478 12:47:19.677526
5479 12:47:19.677630
5480 12:47:19.687676 [DQSOSCAuto] RK1, (LSB)MR18= 0x3213, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5481 12:47:19.687808 CH0 RK1: MR19=505, MR18=3213
5482 12:47:19.693883 CH0_RK1: MR19=0x505, MR18=0x3213, DQSOSC=406, MR23=63, INC=65, DEC=43
5483 12:47:19.697421 [RxdqsGatingPostProcess] freq 933
5484 12:47:19.703901 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5485 12:47:19.707013 best DQS0 dly(2T, 0.5T) = (0, 10)
5486 12:47:19.710616 best DQS1 dly(2T, 0.5T) = (0, 11)
5487 12:47:19.713752 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5488 12:47:19.716876 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5489 12:47:19.716960 best DQS0 dly(2T, 0.5T) = (0, 10)
5490 12:47:19.720533 best DQS1 dly(2T, 0.5T) = (0, 10)
5491 12:47:19.724054 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5492 12:47:19.727288 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5493 12:47:19.730879 Pre-setting of DQS Precalculation
5494 12:47:19.737391 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5495 12:47:19.737523 ==
5496 12:47:19.740556 Dram Type= 6, Freq= 0, CH_1, rank 0
5497 12:47:19.743988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5498 12:47:19.744073 ==
5499 12:47:19.750408 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5500 12:47:19.756892 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5501 12:47:19.760348 [CA 0] Center 37 (7~67) winsize 61
5502 12:47:19.763319 [CA 1] Center 37 (7~68) winsize 62
5503 12:47:19.766693 [CA 2] Center 34 (5~64) winsize 60
5504 12:47:19.770197 [CA 3] Center 34 (4~64) winsize 61
5505 12:47:19.773244 [CA 4] Center 35 (5~65) winsize 61
5506 12:47:19.773331 [CA 5] Center 34 (4~64) winsize 61
5507 12:47:19.776640
5508 12:47:19.780041 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5509 12:47:19.780146
5510 12:47:19.783423 [CATrainingPosCal] consider 1 rank data
5511 12:47:19.786857 u2DelayCellTimex100 = 270/100 ps
5512 12:47:19.790186 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5513 12:47:19.793245 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5514 12:47:19.796509 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5515 12:47:19.799967 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5516 12:47:19.802947 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5517 12:47:19.806415 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5518 12:47:19.806509
5519 12:47:19.809705 CA PerBit enable=1, Macro0, CA PI delay=34
5520 12:47:19.813102
5521 12:47:19.813222 [CBTSetCACLKResult] CA Dly = 34
5522 12:47:19.816411 CS Dly: 5 (0~36)
5523 12:47:19.816526 ==
5524 12:47:19.819879 Dram Type= 6, Freq= 0, CH_1, rank 1
5525 12:47:19.823092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5526 12:47:19.823181 ==
5527 12:47:19.829799 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5528 12:47:19.836392 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5529 12:47:19.839572 [CA 0] Center 38 (8~68) winsize 61
5530 12:47:19.843149 [CA 1] Center 37 (7~68) winsize 62
5531 12:47:19.846084 [CA 2] Center 35 (6~65) winsize 60
5532 12:47:19.849556 [CA 3] Center 34 (4~64) winsize 61
5533 12:47:19.853079 [CA 4] Center 35 (5~65) winsize 61
5534 12:47:19.856162 [CA 5] Center 34 (4~64) winsize 61
5535 12:47:19.856266
5536 12:47:19.860095 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5537 12:47:19.860198
5538 12:47:19.863111 [CATrainingPosCal] consider 2 rank data
5539 12:47:19.866241 u2DelayCellTimex100 = 270/100 ps
5540 12:47:19.869499 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5541 12:47:19.872900 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5542 12:47:19.876297 CA2 delay=35 (6~64),Diff = 1 PI (6 cell)
5543 12:47:19.879456 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5544 12:47:19.882584 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5545 12:47:19.886047 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5546 12:47:19.886152
5547 12:47:19.893094 CA PerBit enable=1, Macro0, CA PI delay=34
5548 12:47:19.893225
5549 12:47:19.893292 [CBTSetCACLKResult] CA Dly = 34
5550 12:47:19.895862 CS Dly: 6 (0~38)
5551 12:47:19.895948
5552 12:47:19.899247 ----->DramcWriteLeveling(PI) begin...
5553 12:47:19.899368 ==
5554 12:47:19.902754 Dram Type= 6, Freq= 0, CH_1, rank 0
5555 12:47:19.906195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5556 12:47:19.906288 ==
5557 12:47:19.909106 Write leveling (Byte 0): 27 => 27
5558 12:47:19.912514 Write leveling (Byte 1): 29 => 29
5559 12:47:19.915927 DramcWriteLeveling(PI) end<-----
5560 12:47:19.916029
5561 12:47:19.916099 ==
5562 12:47:19.919196 Dram Type= 6, Freq= 0, CH_1, rank 0
5563 12:47:19.925957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5564 12:47:19.926103 ==
5565 12:47:19.926193 [Gating] SW mode calibration
5566 12:47:19.935587 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5567 12:47:19.939350 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5568 12:47:19.942789 0 14 0 | B1->B0 | 3131 3333 | 0 0 | (0 0) (0 0)
5569 12:47:19.949178 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 12:47:19.952235 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 12:47:19.956146 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 12:47:19.962225 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 12:47:19.965546 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 12:47:19.969266 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 12:47:19.975633 0 14 28 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (0 0)
5576 12:47:19.978999 0 15 0 | B1->B0 | 2626 2424 | 0 0 | (1 1) (0 0)
5577 12:47:19.982282 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 12:47:19.988945 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 12:47:19.992319 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 12:47:19.995789 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 12:47:20.002778 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 12:47:20.005471 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 12:47:20.008973 0 15 28 | B1->B0 | 3232 3434 | 0 0 | (0 0) (0 0)
5584 12:47:20.015760 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 12:47:20.018697 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 12:47:20.022551 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 12:47:20.028769 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 12:47:20.032343 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 12:47:20.035652 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 12:47:20.042206 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 12:47:20.045413 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5592 12:47:20.048537 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5593 12:47:20.055596 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 12:47:20.058503 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 12:47:20.062135 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 12:47:20.065450 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 12:47:20.071914 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 12:47:20.075263 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 12:47:20.078302 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 12:47:20.085204 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 12:47:20.088361 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 12:47:20.092090 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 12:47:20.098811 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 12:47:20.101659 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 12:47:20.104975 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 12:47:20.111791 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 12:47:20.115206 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5608 12:47:20.118071 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 12:47:20.122051 Total UI for P1: 0, mck2ui 16
5610 12:47:20.124888 best dqsien dly found for B0: ( 1, 2, 30)
5611 12:47:20.128599 Total UI for P1: 0, mck2ui 16
5612 12:47:20.131495 best dqsien dly found for B1: ( 1, 2, 28)
5613 12:47:20.135355 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5614 12:47:20.138366 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5615 12:47:20.138490
5616 12:47:20.145116 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5617 12:47:20.148504 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5618 12:47:20.151705 [Gating] SW calibration Done
5619 12:47:20.151836 ==
5620 12:47:20.155125 Dram Type= 6, Freq= 0, CH_1, rank 0
5621 12:47:20.158075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5622 12:47:20.158221 ==
5623 12:47:20.158320 RX Vref Scan: 0
5624 12:47:20.158422
5625 12:47:20.161666 RX Vref 0 -> 0, step: 1
5626 12:47:20.161803
5627 12:47:20.165123 RX Delay -80 -> 252, step: 8
5628 12:47:20.168264 iDelay=208, Bit 0, Center 103 (0 ~ 207) 208
5629 12:47:20.171739 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5630 12:47:20.178302 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5631 12:47:20.181466 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5632 12:47:20.184951 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5633 12:47:20.188455 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5634 12:47:20.191165 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5635 12:47:20.194703 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5636 12:47:20.201229 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5637 12:47:20.204861 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5638 12:47:20.207853 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5639 12:47:20.211023 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5640 12:47:20.214289 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5641 12:47:20.221197 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5642 12:47:20.224689 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5643 12:47:20.227970 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5644 12:47:20.228069 ==
5645 12:47:20.231237 Dram Type= 6, Freq= 0, CH_1, rank 0
5646 12:47:20.234739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5647 12:47:20.234815 ==
5648 12:47:20.237594 DQS Delay:
5649 12:47:20.237692 DQS0 = 0, DQS1 = 0
5650 12:47:20.240977 DQM Delay:
5651 12:47:20.241077 DQM0 = 94, DQM1 = 86
5652 12:47:20.241170 DQ Delay:
5653 12:47:20.244683 DQ0 =103, DQ1 =91, DQ2 =83, DQ3 =91
5654 12:47:20.247799 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5655 12:47:20.251046 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5656 12:47:20.254500 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5657 12:47:20.254597
5658 12:47:20.254678
5659 12:47:20.257669 ==
5660 12:47:20.261079 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 12:47:20.264468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 12:47:20.264549 ==
5663 12:47:20.264612
5664 12:47:20.264671
5665 12:47:20.267418 TX Vref Scan disable
5666 12:47:20.267498 == TX Byte 0 ==
5667 12:47:20.271123 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5668 12:47:20.277605 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5669 12:47:20.277687 == TX Byte 1 ==
5670 12:47:20.284293 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5671 12:47:20.287321 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5672 12:47:20.287428 ==
5673 12:47:20.290582 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 12:47:20.293927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 12:47:20.294009 ==
5676 12:47:20.294072
5677 12:47:20.294129
5678 12:47:20.297359 TX Vref Scan disable
5679 12:47:20.300595 == TX Byte 0 ==
5680 12:47:20.303886 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5681 12:47:20.307589 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5682 12:47:20.310522 == TX Byte 1 ==
5683 12:47:20.313810 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5684 12:47:20.317176 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5685 12:47:20.317257
5686 12:47:20.320409 [DATLAT]
5687 12:47:20.320507 Freq=933, CH1 RK0
5688 12:47:20.320615
5689 12:47:20.323724 DATLAT Default: 0xd
5690 12:47:20.323830 0, 0xFFFF, sum = 0
5691 12:47:20.327313 1, 0xFFFF, sum = 0
5692 12:47:20.327449 2, 0xFFFF, sum = 0
5693 12:47:20.330591 3, 0xFFFF, sum = 0
5694 12:47:20.330671 4, 0xFFFF, sum = 0
5695 12:47:20.334016 5, 0xFFFF, sum = 0
5696 12:47:20.334097 6, 0xFFFF, sum = 0
5697 12:47:20.337346 7, 0xFFFF, sum = 0
5698 12:47:20.337427 8, 0xFFFF, sum = 0
5699 12:47:20.340765 9, 0xFFFF, sum = 0
5700 12:47:20.340847 10, 0x0, sum = 1
5701 12:47:20.344008 11, 0x0, sum = 2
5702 12:47:20.344089 12, 0x0, sum = 3
5703 12:47:20.347368 13, 0x0, sum = 4
5704 12:47:20.347471 best_step = 11
5705 12:47:20.347534
5706 12:47:20.347592 ==
5707 12:47:20.350149 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 12:47:20.356900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 12:47:20.356982 ==
5710 12:47:20.357051 RX Vref Scan: 1
5711 12:47:20.357114
5712 12:47:20.360226 RX Vref 0 -> 0, step: 1
5713 12:47:20.360300
5714 12:47:20.363465 RX Delay -61 -> 252, step: 4
5715 12:47:20.363535
5716 12:47:20.366858 Set Vref, RX VrefLevel [Byte0]: 56
5717 12:47:20.370257 [Byte1]: 48
5718 12:47:20.370365
5719 12:47:20.373649 Final RX Vref Byte 0 = 56 to rank0
5720 12:47:20.376962 Final RX Vref Byte 1 = 48 to rank0
5721 12:47:20.380174 Final RX Vref Byte 0 = 56 to rank1
5722 12:47:20.383399 Final RX Vref Byte 1 = 48 to rank1==
5723 12:47:20.386627 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 12:47:20.389831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 12:47:20.389914 ==
5726 12:47:20.393274 DQS Delay:
5727 12:47:20.393361 DQS0 = 0, DQS1 = 0
5728 12:47:20.393427 DQM Delay:
5729 12:47:20.396892 DQM0 = 96, DQM1 = 87
5730 12:47:20.397016 DQ Delay:
5731 12:47:20.399740 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =92
5732 12:47:20.403070 DQ4 =94, DQ5 =106, DQ6 =106, DQ7 =94
5733 12:47:20.406306 DQ8 =76, DQ9 =78, DQ10 =86, DQ11 =82
5734 12:47:20.410117 DQ12 =98, DQ13 =94, DQ14 =92, DQ15 =94
5735 12:47:20.410200
5736 12:47:20.410263
5737 12:47:20.419609 [DQSOSCAuto] RK0, (LSB)MR18= 0x10a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5738 12:47:20.423012 CH1 RK0: MR19=505, MR18=10A
5739 12:47:20.426260 CH1_RK0: MR19=0x505, MR18=0x10A, DQSOSC=418, MR23=63, INC=62, DEC=41
5740 12:47:20.426343
5741 12:47:20.429645 ----->DramcWriteLeveling(PI) begin...
5742 12:47:20.432889 ==
5743 12:47:20.436173 Dram Type= 6, Freq= 0, CH_1, rank 1
5744 12:47:20.439358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 12:47:20.439495 ==
5746 12:47:20.443053 Write leveling (Byte 0): 26 => 26
5747 12:47:20.446332 Write leveling (Byte 1): 27 => 27
5748 12:47:20.449737 DramcWriteLeveling(PI) end<-----
5749 12:47:20.449818
5750 12:47:20.449881 ==
5751 12:47:20.452558 Dram Type= 6, Freq= 0, CH_1, rank 1
5752 12:47:20.456288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 12:47:20.456370 ==
5754 12:47:20.459509 [Gating] SW mode calibration
5755 12:47:20.466044 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5756 12:47:20.472688 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5757 12:47:20.476113 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5758 12:47:20.479044 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 12:47:20.485420 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 12:47:20.488872 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 12:47:20.492031 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 12:47:20.498871 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5763 12:47:20.502001 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (1 1) (0 1)
5764 12:47:20.505190 0 14 28 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
5765 12:47:20.511853 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 12:47:20.515207 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 12:47:20.518414 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 12:47:20.525560 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 12:47:20.528514 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 12:47:20.531932 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 12:47:20.538887 0 15 24 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
5772 12:47:20.541874 0 15 28 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
5773 12:47:20.544905 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 12:47:20.551885 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 12:47:20.554637 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 12:47:20.558266 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 12:47:20.564904 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 12:47:20.568289 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 12:47:20.571159 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5780 12:47:20.578204 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5781 12:47:20.581149 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 12:47:20.584641 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 12:47:20.591272 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 12:47:20.594495 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 12:47:20.597869 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 12:47:20.604433 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 12:47:20.607729 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 12:47:20.611159 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 12:47:20.617684 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 12:47:20.620902 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 12:47:20.624441 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 12:47:20.631185 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 12:47:20.634319 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 12:47:20.637785 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 12:47:20.643939 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5796 12:47:20.647367 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5797 12:47:20.650634 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 12:47:20.653973 Total UI for P1: 0, mck2ui 16
5799 12:47:20.657352 best dqsien dly found for B0: ( 1, 2, 26)
5800 12:47:20.660606 Total UI for P1: 0, mck2ui 16
5801 12:47:20.664045 best dqsien dly found for B1: ( 1, 2, 30)
5802 12:47:20.667333 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5803 12:47:20.670827 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5804 12:47:20.670907
5805 12:47:20.674023 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5806 12:47:20.680786 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5807 12:47:20.680869 [Gating] SW calibration Done
5808 12:47:20.683862 ==
5809 12:47:20.683963 Dram Type= 6, Freq= 0, CH_1, rank 1
5810 12:47:20.690523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 12:47:20.690606 ==
5812 12:47:20.690670 RX Vref Scan: 0
5813 12:47:20.690729
5814 12:47:20.693861 RX Vref 0 -> 0, step: 1
5815 12:47:20.693943
5816 12:47:20.697271 RX Delay -80 -> 252, step: 8
5817 12:47:20.700384 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5818 12:47:20.703833 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5819 12:47:20.707299 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5820 12:47:20.713866 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5821 12:47:20.717096 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5822 12:47:20.720149 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5823 12:47:20.723280 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5824 12:47:20.727051 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5825 12:47:20.730040 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5826 12:47:20.736670 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5827 12:47:20.740102 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5828 12:47:20.743462 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5829 12:47:20.746406 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5830 12:47:20.753215 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5831 12:47:20.756769 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5832 12:47:20.760381 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5833 12:47:20.760463 ==
5834 12:47:20.763178 Dram Type= 6, Freq= 0, CH_1, rank 1
5835 12:47:20.766548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 12:47:20.766630 ==
5837 12:47:20.770046 DQS Delay:
5838 12:47:20.770127 DQS0 = 0, DQS1 = 0
5839 12:47:20.770190 DQM Delay:
5840 12:47:20.773494 DQM0 = 93, DQM1 = 87
5841 12:47:20.773575 DQ Delay:
5842 12:47:20.776446 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5843 12:47:20.779818 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5844 12:47:20.783143 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5845 12:47:20.786677 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5846 12:47:20.786764
5847 12:47:20.786829
5848 12:47:20.786887 ==
5849 12:47:20.789654 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 12:47:20.796427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 12:47:20.796510 ==
5852 12:47:20.796573
5853 12:47:20.796632
5854 12:47:20.796687 TX Vref Scan disable
5855 12:47:20.799798 == TX Byte 0 ==
5856 12:47:20.803099 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5857 12:47:20.810270 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5858 12:47:20.810352 == TX Byte 1 ==
5859 12:47:20.813154 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5860 12:47:20.820051 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5861 12:47:20.820149 ==
5862 12:47:20.823103 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 12:47:20.826651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 12:47:20.826734 ==
5865 12:47:20.826799
5866 12:47:20.826862
5867 12:47:20.829883 TX Vref Scan disable
5868 12:47:20.829963 == TX Byte 0 ==
5869 12:47:20.836391 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5870 12:47:20.839635 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5871 12:47:20.839717 == TX Byte 1 ==
5872 12:47:20.846376 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5873 12:47:20.849676 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5874 12:47:20.849757
5875 12:47:20.849821 [DATLAT]
5876 12:47:20.853061 Freq=933, CH1 RK1
5877 12:47:20.853142
5878 12:47:20.853206 DATLAT Default: 0xb
5879 12:47:20.856568 0, 0xFFFF, sum = 0
5880 12:47:20.856650 1, 0xFFFF, sum = 0
5881 12:47:20.859739 2, 0xFFFF, sum = 0
5882 12:47:20.859821 3, 0xFFFF, sum = 0
5883 12:47:20.863484 4, 0xFFFF, sum = 0
5884 12:47:20.863565 5, 0xFFFF, sum = 0
5885 12:47:20.867023 6, 0xFFFF, sum = 0
5886 12:47:20.870041 7, 0xFFFF, sum = 0
5887 12:47:20.870124 8, 0xFFFF, sum = 0
5888 12:47:20.873075 9, 0xFFFF, sum = 0
5889 12:47:20.873204 10, 0x0, sum = 1
5890 12:47:20.876151 11, 0x0, sum = 2
5891 12:47:20.876234 12, 0x0, sum = 3
5892 12:47:20.876298 13, 0x0, sum = 4
5893 12:47:20.879597 best_step = 11
5894 12:47:20.879677
5895 12:47:20.879740 ==
5896 12:47:20.883069 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 12:47:20.886422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 12:47:20.886504 ==
5899 12:47:20.889772 RX Vref Scan: 0
5900 12:47:20.889885
5901 12:47:20.889948 RX Vref 0 -> 0, step: 1
5902 12:47:20.893024
5903 12:47:20.893104 RX Delay -69 -> 252, step: 4
5904 12:47:20.900150 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5905 12:47:20.903940 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5906 12:47:20.906867 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5907 12:47:20.910189 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5908 12:47:20.913751 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5909 12:47:20.920126 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5910 12:47:20.923658 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5911 12:47:20.926622 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5912 12:47:20.929944 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5913 12:47:20.933434 iDelay=203, Bit 9, Center 84 (-9 ~ 178) 188
5914 12:47:20.937084 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5915 12:47:20.943808 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5916 12:47:20.946977 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5917 12:47:20.949866 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5918 12:47:20.953335 iDelay=203, Bit 14, Center 98 (11 ~ 186) 176
5919 12:47:20.956733 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
5920 12:47:20.956808 ==
5921 12:47:20.960348 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 12:47:20.966604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 12:47:20.966685 ==
5924 12:47:20.966764 DQS Delay:
5925 12:47:20.970396 DQS0 = 0, DQS1 = 0
5926 12:47:20.970497 DQM Delay:
5927 12:47:20.972954 DQM0 = 91, DQM1 = 91
5928 12:47:20.973029 DQ Delay:
5929 12:47:20.976299 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
5930 12:47:20.979977 DQ4 =88, DQ5 =100, DQ6 =102, DQ7 =88
5931 12:47:20.982921 DQ8 =78, DQ9 =84, DQ10 =92, DQ11 =84
5932 12:47:20.986275 DQ12 =100, DQ13 =96, DQ14 =98, DQ15 =98
5933 12:47:20.986355
5934 12:47:20.986416
5935 12:47:20.993127 [DQSOSCAuto] RK1, (LSB)MR18= 0xc1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
5936 12:47:20.996506 CH1 RK1: MR19=505, MR18=C1F
5937 12:47:21.003121 CH1_RK1: MR19=0x505, MR18=0xC1F, DQSOSC=412, MR23=63, INC=63, DEC=42
5938 12:47:21.006610 [RxdqsGatingPostProcess] freq 933
5939 12:47:21.012876 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5940 12:47:21.012986 best DQS0 dly(2T, 0.5T) = (0, 10)
5941 12:47:21.016124 best DQS1 dly(2T, 0.5T) = (0, 10)
5942 12:47:21.019739 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5943 12:47:21.022707 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5944 12:47:21.026156 best DQS0 dly(2T, 0.5T) = (0, 10)
5945 12:47:21.029360 best DQS1 dly(2T, 0.5T) = (0, 10)
5946 12:47:21.032816 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5947 12:47:21.036079 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5948 12:47:21.039401 Pre-setting of DQS Precalculation
5949 12:47:21.045977 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5950 12:47:21.052582 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5951 12:47:21.059549 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5952 12:47:21.059649
5953 12:47:21.059714
5954 12:47:21.062808 [Calibration Summary] 1866 Mbps
5955 12:47:21.062889 CH 0, Rank 0
5956 12:47:21.065614 SW Impedance : PASS
5957 12:47:21.069095 DUTY Scan : NO K
5958 12:47:21.069177 ZQ Calibration : PASS
5959 12:47:21.072426 Jitter Meter : NO K
5960 12:47:21.072507 CBT Training : PASS
5961 12:47:21.075841 Write leveling : PASS
5962 12:47:21.079273 RX DQS gating : PASS
5963 12:47:21.079355 RX DQ/DQS(RDDQC) : PASS
5964 12:47:21.082293 TX DQ/DQS : PASS
5965 12:47:21.086007 RX DATLAT : PASS
5966 12:47:21.086088 RX DQ/DQS(Engine): PASS
5967 12:47:21.089523 TX OE : NO K
5968 12:47:21.089604 All Pass.
5969 12:47:21.089686
5970 12:47:21.092391 CH 0, Rank 1
5971 12:47:21.092473 SW Impedance : PASS
5972 12:47:21.095581 DUTY Scan : NO K
5973 12:47:21.098895 ZQ Calibration : PASS
5974 12:47:21.099002 Jitter Meter : NO K
5975 12:47:21.102244 CBT Training : PASS
5976 12:47:21.105605 Write leveling : PASS
5977 12:47:21.105687 RX DQS gating : PASS
5978 12:47:21.108975 RX DQ/DQS(RDDQC) : PASS
5979 12:47:21.112421 TX DQ/DQS : PASS
5980 12:47:21.112503 RX DATLAT : PASS
5981 12:47:21.116065 RX DQ/DQS(Engine): PASS
5982 12:47:21.116147 TX OE : NO K
5983 12:47:21.119313 All Pass.
5984 12:47:21.119432
5985 12:47:21.119498 CH 1, Rank 0
5986 12:47:21.122608 SW Impedance : PASS
5987 12:47:21.122693 DUTY Scan : NO K
5988 12:47:21.128012 ZQ Calibration : PASS
5989 12:47:21.128870 Jitter Meter : NO K
5990 12:47:21.128951 CBT Training : PASS
5991 12:47:21.132124 Write leveling : PASS
5992 12:47:21.135478 RX DQS gating : PASS
5993 12:47:21.135586 RX DQ/DQS(RDDQC) : PASS
5994 12:47:21.138883 TX DQ/DQS : PASS
5995 12:47:21.142214 RX DATLAT : PASS
5996 12:47:21.142297 RX DQ/DQS(Engine): PASS
5997 12:47:21.145477 TX OE : NO K
5998 12:47:21.145558 All Pass.
5999 12:47:21.145622
6000 12:47:21.148910 CH 1, Rank 1
6001 12:47:21.148997 SW Impedance : PASS
6002 12:47:21.152348 DUTY Scan : NO K
6003 12:47:21.155342 ZQ Calibration : PASS
6004 12:47:21.155462 Jitter Meter : NO K
6005 12:47:21.159085 CBT Training : PASS
6006 12:47:21.162353 Write leveling : PASS
6007 12:47:21.162431 RX DQS gating : PASS
6008 12:47:21.165549 RX DQ/DQS(RDDQC) : PASS
6009 12:47:21.168730 TX DQ/DQS : PASS
6010 12:47:21.168920 RX DATLAT : PASS
6011 12:47:21.172213 RX DQ/DQS(Engine): PASS
6012 12:47:21.174993 TX OE : NO K
6013 12:47:21.175099 All Pass.
6014 12:47:21.175167
6015 12:47:21.175227 DramC Write-DBI off
6016 12:47:21.178312 PER_BANK_REFRESH: Hybrid Mode
6017 12:47:21.181699 TX_TRACKING: ON
6018 12:47:21.188513 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6019 12:47:21.191849 [FAST_K] Save calibration result to emmc
6020 12:47:21.198292 dramc_set_vcore_voltage set vcore to 650000
6021 12:47:21.198375 Read voltage for 400, 6
6022 12:47:21.202006 Vio18 = 0
6023 12:47:21.202088 Vcore = 650000
6024 12:47:21.202152 Vdram = 0
6025 12:47:21.204842 Vddq = 0
6026 12:47:21.204924 Vmddr = 0
6027 12:47:21.208249 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6028 12:47:21.215141 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6029 12:47:21.218066 MEM_TYPE=3, freq_sel=20
6030 12:47:21.218147 sv_algorithm_assistance_LP4_800
6031 12:47:21.224954 ============ PULL DRAM RESETB DOWN ============
6032 12:47:21.228201 ========== PULL DRAM RESETB DOWN end =========
6033 12:47:21.231572 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6034 12:47:21.234660 ===================================
6035 12:47:21.238412 LPDDR4 DRAM CONFIGURATION
6036 12:47:21.241217 ===================================
6037 12:47:21.244595 EX_ROW_EN[0] = 0x0
6038 12:47:21.244676 EX_ROW_EN[1] = 0x0
6039 12:47:21.247893 LP4Y_EN = 0x0
6040 12:47:21.248000 WORK_FSP = 0x0
6041 12:47:21.251227 WL = 0x2
6042 12:47:21.251308 RL = 0x2
6043 12:47:21.254571 BL = 0x2
6044 12:47:21.254652 RPST = 0x0
6045 12:47:21.257838 RD_PRE = 0x0
6046 12:47:21.261303 WR_PRE = 0x1
6047 12:47:21.261386 WR_PST = 0x0
6048 12:47:21.264315 DBI_WR = 0x0
6049 12:47:21.264403 DBI_RD = 0x0
6050 12:47:21.267855 OTF = 0x1
6051 12:47:21.271213 ===================================
6052 12:47:21.274541 ===================================
6053 12:47:21.274616 ANA top config
6054 12:47:21.277664 ===================================
6055 12:47:21.280992 DLL_ASYNC_EN = 0
6056 12:47:21.284281 ALL_SLAVE_EN = 1
6057 12:47:21.284362 NEW_RANK_MODE = 1
6058 12:47:21.287314 DLL_IDLE_MODE = 1
6059 12:47:21.290786 LP45_APHY_COMB_EN = 1
6060 12:47:21.294484 TX_ODT_DIS = 1
6061 12:47:21.294560 NEW_8X_MODE = 1
6062 12:47:21.297333 ===================================
6063 12:47:21.300588 ===================================
6064 12:47:21.303796 data_rate = 800
6065 12:47:21.307161 CKR = 1
6066 12:47:21.310537 DQ_P2S_RATIO = 4
6067 12:47:21.313929 ===================================
6068 12:47:21.317315 CA_P2S_RATIO = 4
6069 12:47:21.320918 DQ_CA_OPEN = 0
6070 12:47:21.324311 DQ_SEMI_OPEN = 1
6071 12:47:21.324383 CA_SEMI_OPEN = 1
6072 12:47:21.327204 CA_FULL_RATE = 0
6073 12:47:21.330401 DQ_CKDIV4_EN = 0
6074 12:47:21.333823 CA_CKDIV4_EN = 1
6075 12:47:21.337139 CA_PREDIV_EN = 0
6076 12:47:21.340422 PH8_DLY = 0
6077 12:47:21.340499 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6078 12:47:21.343951 DQ_AAMCK_DIV = 0
6079 12:47:21.347217 CA_AAMCK_DIV = 0
6080 12:47:21.350719 CA_ADMCK_DIV = 4
6081 12:47:21.353587 DQ_TRACK_CA_EN = 0
6082 12:47:21.357043 CA_PICK = 800
6083 12:47:21.357117 CA_MCKIO = 400
6084 12:47:21.360162 MCKIO_SEMI = 400
6085 12:47:21.363584 PLL_FREQ = 3016
6086 12:47:21.366925 DQ_UI_PI_RATIO = 32
6087 12:47:21.370129 CA_UI_PI_RATIO = 32
6088 12:47:21.373486 ===================================
6089 12:47:21.376671 ===================================
6090 12:47:21.379845 memory_type:LPDDR4
6091 12:47:21.379916 GP_NUM : 10
6092 12:47:21.383144 SRAM_EN : 1
6093 12:47:21.386862 MD32_EN : 0
6094 12:47:21.389855 ===================================
6095 12:47:21.389937 [ANA_INIT] >>>>>>>>>>>>>>
6096 12:47:21.392973 <<<<<< [CONFIGURE PHASE]: ANA_TX
6097 12:47:21.396626 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6098 12:47:21.399938 ===================================
6099 12:47:21.403038 data_rate = 800,PCW = 0X7400
6100 12:47:21.406332 ===================================
6101 12:47:21.409950 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6102 12:47:21.416606 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6103 12:47:21.426348 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6104 12:47:21.432726 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6105 12:47:21.436845 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6106 12:47:21.439600 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6107 12:47:21.439676 [ANA_INIT] flow start
6108 12:47:21.442967 [ANA_INIT] PLL >>>>>>>>
6109 12:47:21.446177 [ANA_INIT] PLL <<<<<<<<
6110 12:47:21.446257 [ANA_INIT] MIDPI >>>>>>>>
6111 12:47:21.449366 [ANA_INIT] MIDPI <<<<<<<<
6112 12:47:21.452363 [ANA_INIT] DLL >>>>>>>>
6113 12:47:21.452438 [ANA_INIT] flow end
6114 12:47:21.459143 ============ LP4 DIFF to SE enter ============
6115 12:47:21.462629 ============ LP4 DIFF to SE exit ============
6116 12:47:21.465930 [ANA_INIT] <<<<<<<<<<<<<
6117 12:47:21.469054 [Flow] Enable top DCM control >>>>>
6118 12:47:21.472914 [Flow] Enable top DCM control <<<<<
6119 12:47:21.473021 Enable DLL master slave shuffle
6120 12:47:21.479174 ==============================================================
6121 12:47:21.482160 Gating Mode config
6122 12:47:21.485650 ==============================================================
6123 12:47:21.488982 Config description:
6124 12:47:21.498834 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6125 12:47:21.505470 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6126 12:47:21.508689 SELPH_MODE 0: By rank 1: By Phase
6127 12:47:21.515406 ==============================================================
6128 12:47:21.518654 GAT_TRACK_EN = 0
6129 12:47:21.522054 RX_GATING_MODE = 2
6130 12:47:21.525551 RX_GATING_TRACK_MODE = 2
6131 12:47:21.528527 SELPH_MODE = 1
6132 12:47:21.528609 PICG_EARLY_EN = 1
6133 12:47:21.532326 VALID_LAT_VALUE = 1
6134 12:47:21.538254 ==============================================================
6135 12:47:21.541685 Enter into Gating configuration >>>>
6136 12:47:21.545154 Exit from Gating configuration <<<<
6137 12:47:21.548703 Enter into DVFS_PRE_config >>>>>
6138 12:47:21.558471 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6139 12:47:21.561860 Exit from DVFS_PRE_config <<<<<
6140 12:47:21.564799 Enter into PICG configuration >>>>
6141 12:47:21.568221 Exit from PICG configuration <<<<
6142 12:47:21.571658 [RX_INPUT] configuration >>>>>
6143 12:47:21.575282 [RX_INPUT] configuration <<<<<
6144 12:47:21.581469 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6145 12:47:21.584880 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6146 12:47:21.591209 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6147 12:47:21.597949 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6148 12:47:21.604647 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6149 12:47:21.610938 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6150 12:47:21.614617 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6151 12:47:21.617944 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6152 12:47:21.621180 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6153 12:47:21.627624 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6154 12:47:21.631132 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6155 12:47:21.634416 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6156 12:47:21.637882 ===================================
6157 12:47:21.641170 LPDDR4 DRAM CONFIGURATION
6158 12:47:21.644084 ===================================
6159 12:47:21.644160 EX_ROW_EN[0] = 0x0
6160 12:47:21.647696 EX_ROW_EN[1] = 0x0
6161 12:47:21.650662 LP4Y_EN = 0x0
6162 12:47:21.650734 WORK_FSP = 0x0
6163 12:47:21.654198 WL = 0x2
6164 12:47:21.654280 RL = 0x2
6165 12:47:21.657454 BL = 0x2
6166 12:47:21.657535 RPST = 0x0
6167 12:47:21.660944 RD_PRE = 0x0
6168 12:47:21.661052 WR_PRE = 0x1
6169 12:47:21.663817 WR_PST = 0x0
6170 12:47:21.663917 DBI_WR = 0x0
6171 12:47:21.667478 DBI_RD = 0x0
6172 12:47:21.667554 OTF = 0x1
6173 12:47:21.671075 ===================================
6174 12:47:21.674037 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6175 12:47:21.680891 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6176 12:47:21.684028 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6177 12:47:21.687358 ===================================
6178 12:47:21.690676 LPDDR4 DRAM CONFIGURATION
6179 12:47:21.693796 ===================================
6180 12:47:21.693896 EX_ROW_EN[0] = 0x10
6181 12:47:21.697216 EX_ROW_EN[1] = 0x0
6182 12:47:21.700707 LP4Y_EN = 0x0
6183 12:47:21.700788 WORK_FSP = 0x0
6184 12:47:21.704037 WL = 0x2
6185 12:47:21.704118 RL = 0x2
6186 12:47:21.707278 BL = 0x2
6187 12:47:21.707384 RPST = 0x0
6188 12:47:21.710645 RD_PRE = 0x0
6189 12:47:21.710748 WR_PRE = 0x1
6190 12:47:21.714001 WR_PST = 0x0
6191 12:47:21.714100 DBI_WR = 0x0
6192 12:47:21.717315 DBI_RD = 0x0
6193 12:47:21.717415 OTF = 0x1
6194 12:47:21.720679 ===================================
6195 12:47:21.726859 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6196 12:47:21.731342 nWR fixed to 30
6197 12:47:21.734882 [ModeRegInit_LP4] CH0 RK0
6198 12:47:21.734979 [ModeRegInit_LP4] CH0 RK1
6199 12:47:21.738172 [ModeRegInit_LP4] CH1 RK0
6200 12:47:21.741059 [ModeRegInit_LP4] CH1 RK1
6201 12:47:21.741134 match AC timing 19
6202 12:47:21.747879 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6203 12:47:21.751521 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6204 12:47:21.754245 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6205 12:47:21.761505 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6206 12:47:21.764414 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6207 12:47:21.764497 ==
6208 12:47:21.768152 Dram Type= 6, Freq= 0, CH_0, rank 0
6209 12:47:21.771355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6210 12:47:21.771511 ==
6211 12:47:21.777753 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6212 12:47:21.784302 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6213 12:47:21.787634 [CA 0] Center 36 (8~64) winsize 57
6214 12:47:21.791237 [CA 1] Center 36 (8~64) winsize 57
6215 12:47:21.794744 [CA 2] Center 36 (8~64) winsize 57
6216 12:47:21.794825 [CA 3] Center 36 (8~64) winsize 57
6217 12:47:21.797463 [CA 4] Center 36 (8~64) winsize 57
6218 12:47:21.801200 [CA 5] Center 36 (8~64) winsize 57
6219 12:47:21.801282
6220 12:47:21.807798 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6221 12:47:21.807880
6222 12:47:21.810970 [CATrainingPosCal] consider 1 rank data
6223 12:47:21.814273 u2DelayCellTimex100 = 270/100 ps
6224 12:47:21.817183 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 12:47:21.821020 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 12:47:21.824268 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 12:47:21.827635 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 12:47:21.830848 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 12:47:21.834215 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 12:47:21.834297
6231 12:47:21.837170 CA PerBit enable=1, Macro0, CA PI delay=36
6232 12:47:21.837251
6233 12:47:21.840482 [CBTSetCACLKResult] CA Dly = 36
6234 12:47:21.844106 CS Dly: 1 (0~32)
6235 12:47:21.844234 ==
6236 12:47:21.847248 Dram Type= 6, Freq= 0, CH_0, rank 1
6237 12:47:21.850242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6238 12:47:21.850324 ==
6239 12:47:21.857001 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6240 12:47:21.863943 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6241 12:47:21.867284 [CA 0] Center 36 (8~64) winsize 57
6242 12:47:21.867365 [CA 1] Center 36 (8~64) winsize 57
6243 12:47:21.870815 [CA 2] Center 36 (8~64) winsize 57
6244 12:47:21.873749 [CA 3] Center 36 (8~64) winsize 57
6245 12:47:21.876913 [CA 4] Center 36 (8~64) winsize 57
6246 12:47:21.879988 [CA 5] Center 36 (8~64) winsize 57
6247 12:47:21.880070
6248 12:47:21.883685 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6249 12:47:21.883767
6250 12:47:21.886971 [CATrainingPosCal] consider 2 rank data
6251 12:47:21.890344 u2DelayCellTimex100 = 270/100 ps
6252 12:47:21.893720 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 12:47:21.899991 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 12:47:21.903288 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 12:47:21.906637 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 12:47:21.909855 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 12:47:21.913150 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 12:47:21.913226
6259 12:47:21.917004 CA PerBit enable=1, Macro0, CA PI delay=36
6260 12:47:21.917077
6261 12:47:21.919851 [CBTSetCACLKResult] CA Dly = 36
6262 12:47:21.923115 CS Dly: 1 (0~32)
6263 12:47:21.923210
6264 12:47:21.926446 ----->DramcWriteLeveling(PI) begin...
6265 12:47:21.926547 ==
6266 12:47:21.929730 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 12:47:21.933207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 12:47:21.933307 ==
6269 12:47:21.936493 Write leveling (Byte 0): 40 => 8
6270 12:47:21.940039 Write leveling (Byte 1): 32 => 0
6271 12:47:21.943027 DramcWriteLeveling(PI) end<-----
6272 12:47:21.943126
6273 12:47:21.943206 ==
6274 12:47:21.946200 Dram Type= 6, Freq= 0, CH_0, rank 0
6275 12:47:21.949646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 12:47:21.949731 ==
6277 12:47:21.952907 [Gating] SW mode calibration
6278 12:47:21.959914 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6279 12:47:21.966225 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6280 12:47:21.969619 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6281 12:47:21.973387 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6282 12:47:21.979721 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6283 12:47:21.983015 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6284 12:47:21.985978 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 12:47:21.992876 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6286 12:47:21.996130 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6287 12:47:21.999385 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6288 12:47:22.006306 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 12:47:22.006406 Total UI for P1: 0, mck2ui 16
6290 12:47:22.012686 best dqsien dly found for B0: ( 0, 14, 24)
6291 12:47:22.012767 Total UI for P1: 0, mck2ui 16
6292 12:47:22.016184 best dqsien dly found for B1: ( 0, 14, 24)
6293 12:47:22.022574 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6294 12:47:22.025839 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6295 12:47:22.025938
6296 12:47:22.029245 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6297 12:47:22.032319 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6298 12:47:22.035813 [Gating] SW calibration Done
6299 12:47:22.035913 ==
6300 12:47:22.039210 Dram Type= 6, Freq= 0, CH_0, rank 0
6301 12:47:22.042651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 12:47:22.042725 ==
6303 12:47:22.045762 RX Vref Scan: 0
6304 12:47:22.045874
6305 12:47:22.045966 RX Vref 0 -> 0, step: 1
6306 12:47:22.046028
6307 12:47:22.049094 RX Delay -410 -> 252, step: 16
6308 12:47:22.055718 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6309 12:47:22.059067 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6310 12:47:22.062521 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6311 12:47:22.065969 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6312 12:47:22.069525 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6313 12:47:22.075884 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6314 12:47:22.079405 iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496
6315 12:47:22.082732 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6316 12:47:22.086125 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6317 12:47:22.092475 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6318 12:47:22.095646 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6319 12:47:22.099020 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6320 12:47:22.105714 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6321 12:47:22.109244 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6322 12:47:22.112268 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6323 12:47:22.115548 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6324 12:47:22.115630 ==
6325 12:47:22.118815 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 12:47:22.125233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 12:47:22.125315 ==
6328 12:47:22.125379 DQS Delay:
6329 12:47:22.128699 DQS0 = 59, DQS1 = 59
6330 12:47:22.128808 DQM Delay:
6331 12:47:22.132006 DQM0 = 17, DQM1 = 10
6332 12:47:22.132110 DQ Delay:
6333 12:47:22.135183 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6334 12:47:22.138937 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6335 12:47:22.141855 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6336 12:47:22.145336 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6337 12:47:22.145417
6338 12:47:22.145481
6339 12:47:22.145540 ==
6340 12:47:22.148622 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 12:47:22.152130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 12:47:22.152210 ==
6343 12:47:22.152274
6344 12:47:22.152333
6345 12:47:22.155415 TX Vref Scan disable
6346 12:47:22.155522 == TX Byte 0 ==
6347 12:47:22.162132 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 12:47:22.165731 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 12:47:22.165845 == TX Byte 1 ==
6350 12:47:22.172128 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6351 12:47:22.175445 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6352 12:47:22.175541 ==
6353 12:47:22.179232 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 12:47:22.182156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 12:47:22.182238 ==
6356 12:47:22.182302
6357 12:47:22.182362
6358 12:47:22.185457 TX Vref Scan disable
6359 12:47:22.185537 == TX Byte 0 ==
6360 12:47:22.191685 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6361 12:47:22.195148 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6362 12:47:22.195229 == TX Byte 1 ==
6363 12:47:22.201865 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6364 12:47:22.205121 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6365 12:47:22.205236
6366 12:47:22.205333 [DATLAT]
6367 12:47:22.208411 Freq=400, CH0 RK0
6368 12:47:22.208512
6369 12:47:22.208605 DATLAT Default: 0xf
6370 12:47:22.211418 0, 0xFFFF, sum = 0
6371 12:47:22.211492 1, 0xFFFF, sum = 0
6372 12:47:22.214674 2, 0xFFFF, sum = 0
6373 12:47:22.214776 3, 0xFFFF, sum = 0
6374 12:47:22.218223 4, 0xFFFF, sum = 0
6375 12:47:22.221555 5, 0xFFFF, sum = 0
6376 12:47:22.221653 6, 0xFFFF, sum = 0
6377 12:47:22.224981 7, 0xFFFF, sum = 0
6378 12:47:22.225077 8, 0xFFFF, sum = 0
6379 12:47:22.228421 9, 0xFFFF, sum = 0
6380 12:47:22.228532 10, 0xFFFF, sum = 0
6381 12:47:22.231251 11, 0xFFFF, sum = 0
6382 12:47:22.231347 12, 0xFFFF, sum = 0
6383 12:47:22.234834 13, 0x0, sum = 1
6384 12:47:22.234931 14, 0x0, sum = 2
6385 12:47:22.238202 15, 0x0, sum = 3
6386 12:47:22.238300 16, 0x0, sum = 4
6387 12:47:22.241495 best_step = 14
6388 12:47:22.241603
6389 12:47:22.241711 ==
6390 12:47:22.244743 Dram Type= 6, Freq= 0, CH_0, rank 0
6391 12:47:22.248356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6392 12:47:22.248461 ==
6393 12:47:22.248552 RX Vref Scan: 1
6394 12:47:22.248651
6395 12:47:22.251468 RX Vref 0 -> 0, step: 1
6396 12:47:22.251563
6397 12:47:22.254923 RX Delay -359 -> 252, step: 8
6398 12:47:22.255020
6399 12:47:22.258257 Set Vref, RX VrefLevel [Byte0]: 62
6400 12:47:22.261685 [Byte1]: 56
6401 12:47:22.265637
6402 12:47:22.265714 Final RX Vref Byte 0 = 62 to rank0
6403 12:47:22.268587 Final RX Vref Byte 1 = 56 to rank0
6404 12:47:22.272170 Final RX Vref Byte 0 = 62 to rank1
6405 12:47:22.275110 Final RX Vref Byte 1 = 56 to rank1==
6406 12:47:22.278596 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 12:47:22.284987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 12:47:22.285082 ==
6409 12:47:22.285148 DQS Delay:
6410 12:47:22.288196 DQS0 = 60, DQS1 = 68
6411 12:47:22.288264 DQM Delay:
6412 12:47:22.288328 DQM0 = 13, DQM1 = 12
6413 12:47:22.291606 DQ Delay:
6414 12:47:22.294916 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6415 12:47:22.298195 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6416 12:47:22.298301 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6417 12:47:22.304769 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6418 12:47:22.304848
6419 12:47:22.304921
6420 12:47:22.311433 [DQSOSCAuto] RK0, (LSB)MR18= 0x8381, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6421 12:47:22.314854 CH0 RK0: MR19=C0C, MR18=8381
6422 12:47:22.321683 CH0_RK0: MR19=0xC0C, MR18=0x8381, DQSOSC=393, MR23=63, INC=382, DEC=254
6423 12:47:22.321759 ==
6424 12:47:22.324676 Dram Type= 6, Freq= 0, CH_0, rank 1
6425 12:47:22.328033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 12:47:22.328106 ==
6427 12:47:22.331605 [Gating] SW mode calibration
6428 12:47:22.337912 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6429 12:47:22.344745 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6430 12:47:22.347706 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6431 12:47:22.350960 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6432 12:47:22.357697 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6433 12:47:22.361243 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6434 12:47:22.364246 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 12:47:22.370796 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6436 12:47:22.374178 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6437 12:47:22.377441 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 12:47:22.384278 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 12:47:22.384385 Total UI for P1: 0, mck2ui 16
6440 12:47:22.390613 best dqsien dly found for B0: ( 0, 14, 24)
6441 12:47:22.390719 Total UI for P1: 0, mck2ui 16
6442 12:47:22.397860 best dqsien dly found for B1: ( 0, 14, 24)
6443 12:47:22.400886 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6444 12:47:22.404352 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6445 12:47:22.404442
6446 12:47:22.407629 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6447 12:47:22.410796 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6448 12:47:22.414165 [Gating] SW calibration Done
6449 12:47:22.414281 ==
6450 12:47:22.418054 Dram Type= 6, Freq= 0, CH_0, rank 1
6451 12:47:22.420625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 12:47:22.420726 ==
6453 12:47:22.424426 RX Vref Scan: 0
6454 12:47:22.424527
6455 12:47:22.424630 RX Vref 0 -> 0, step: 1
6456 12:47:22.424717
6457 12:47:22.427564 RX Delay -410 -> 252, step: 16
6458 12:47:22.433858 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6459 12:47:22.437399 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6460 12:47:22.440969 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6461 12:47:22.443850 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6462 12:47:22.450655 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6463 12:47:22.454160 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6464 12:47:22.457390 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6465 12:47:22.460624 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6466 12:47:22.467387 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6467 12:47:22.470752 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6468 12:47:22.474148 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6469 12:47:22.477450 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6470 12:47:22.484091 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6471 12:47:22.486996 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6472 12:47:22.490268 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6473 12:47:22.493652 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6474 12:47:22.497142 ==
6475 12:47:22.500366 Dram Type= 6, Freq= 0, CH_0, rank 1
6476 12:47:22.503875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 12:47:22.503949 ==
6478 12:47:22.504011 DQS Delay:
6479 12:47:22.507027 DQS0 = 59, DQS1 = 59
6480 12:47:22.507140 DQM Delay:
6481 12:47:22.510514 DQM0 = 16, DQM1 = 10
6482 12:47:22.510634 DQ Delay:
6483 12:47:22.514047 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6484 12:47:22.517349 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6485 12:47:22.520082 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6486 12:47:22.523786 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6487 12:47:22.523885
6488 12:47:22.523978
6489 12:47:22.524067 ==
6490 12:47:22.527123 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 12:47:22.530430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 12:47:22.530528 ==
6493 12:47:22.530618
6494 12:47:22.530703
6495 12:47:22.533645 TX Vref Scan disable
6496 12:47:22.533740 == TX Byte 0 ==
6497 12:47:22.540183 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6498 12:47:22.543328 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6499 12:47:22.543453 == TX Byte 1 ==
6500 12:47:22.550009 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6501 12:47:22.553480 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6502 12:47:22.553580 ==
6503 12:47:22.556997 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 12:47:22.559759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 12:47:22.559859 ==
6506 12:47:22.559950
6507 12:47:22.560036
6508 12:47:22.563168 TX Vref Scan disable
6509 12:47:22.563280 == TX Byte 0 ==
6510 12:47:22.570155 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6511 12:47:22.573106 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6512 12:47:22.573204 == TX Byte 1 ==
6513 12:47:22.579805 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6514 12:47:22.583086 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6515 12:47:22.583184
6516 12:47:22.583291 [DATLAT]
6517 12:47:22.586807 Freq=400, CH0 RK1
6518 12:47:22.586903
6519 12:47:22.586989 DATLAT Default: 0xe
6520 12:47:22.589803 0, 0xFFFF, sum = 0
6521 12:47:22.589898 1, 0xFFFF, sum = 0
6522 12:47:22.593425 2, 0xFFFF, sum = 0
6523 12:47:22.593529 3, 0xFFFF, sum = 0
6524 12:47:22.596752 4, 0xFFFF, sum = 0
6525 12:47:22.596848 5, 0xFFFF, sum = 0
6526 12:47:22.599642 6, 0xFFFF, sum = 0
6527 12:47:22.603276 7, 0xFFFF, sum = 0
6528 12:47:22.603397 8, 0xFFFF, sum = 0
6529 12:47:22.606498 9, 0xFFFF, sum = 0
6530 12:47:22.606598 10, 0xFFFF, sum = 0
6531 12:47:22.609916 11, 0xFFFF, sum = 0
6532 12:47:22.610014 12, 0xFFFF, sum = 0
6533 12:47:22.613232 13, 0x0, sum = 1
6534 12:47:22.613333 14, 0x0, sum = 2
6535 12:47:22.616802 15, 0x0, sum = 3
6536 12:47:22.616873 16, 0x0, sum = 4
6537 12:47:22.616933 best_step = 14
6538 12:47:22.616991
6539 12:47:22.619659 ==
6540 12:47:22.623109 Dram Type= 6, Freq= 0, CH_0, rank 1
6541 12:47:22.626421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6542 12:47:22.626515 ==
6543 12:47:22.626604 RX Vref Scan: 0
6544 12:47:22.626691
6545 12:47:22.629714 RX Vref 0 -> 0, step: 1
6546 12:47:22.629810
6547 12:47:22.633162 RX Delay -359 -> 252, step: 8
6548 12:47:22.640145 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6549 12:47:22.643450 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6550 12:47:22.646867 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6551 12:47:22.650470 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6552 12:47:22.656636 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6553 12:47:22.660275 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6554 12:47:22.663343 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6555 12:47:22.666673 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6556 12:47:22.673124 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6557 12:47:22.676374 iDelay=217, Bit 9, Center -68 (-319 ~ 184) 504
6558 12:47:22.679799 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6559 12:47:22.686620 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6560 12:47:22.689945 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6561 12:47:22.693255 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6562 12:47:22.696589 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6563 12:47:22.703545 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6564 12:47:22.703640 ==
6565 12:47:22.706265 Dram Type= 6, Freq= 0, CH_0, rank 1
6566 12:47:22.710234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6567 12:47:22.710340 ==
6568 12:47:22.710439 DQS Delay:
6569 12:47:22.713270 DQS0 = 60, DQS1 = 68
6570 12:47:22.713369 DQM Delay:
6571 12:47:22.716745 DQM0 = 12, DQM1 = 14
6572 12:47:22.716844 DQ Delay:
6573 12:47:22.719525 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6574 12:47:22.722926 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6575 12:47:22.726424 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6576 12:47:22.729518 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6577 12:47:22.729619
6578 12:47:22.729711
6579 12:47:22.736485 [DQSOSCAuto] RK1, (LSB)MR18= 0xc57a, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6580 12:47:22.739524 CH0 RK1: MR19=C0C, MR18=C57A
6581 12:47:22.746202 CH0_RK1: MR19=0xC0C, MR18=0xC57A, DQSOSC=385, MR23=63, INC=398, DEC=265
6582 12:47:22.749508 [RxdqsGatingPostProcess] freq 400
6583 12:47:22.756399 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6584 12:47:22.756514 best DQS0 dly(2T, 0.5T) = (0, 10)
6585 12:47:22.759602 best DQS1 dly(2T, 0.5T) = (0, 10)
6586 12:47:22.763265 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6587 12:47:22.766044 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6588 12:47:22.769401 best DQS0 dly(2T, 0.5T) = (0, 10)
6589 12:47:22.772658 best DQS1 dly(2T, 0.5T) = (0, 10)
6590 12:47:22.776044 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6591 12:47:22.779705 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6592 12:47:22.782787 Pre-setting of DQS Precalculation
6593 12:47:22.789328 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6594 12:47:22.789433 ==
6595 12:47:22.792768 Dram Type= 6, Freq= 0, CH_1, rank 0
6596 12:47:22.796112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 12:47:22.796221 ==
6598 12:47:22.802570 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6599 12:47:22.805869 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6600 12:47:22.809617 [CA 0] Center 36 (8~64) winsize 57
6601 12:47:22.812596 [CA 1] Center 36 (8~64) winsize 57
6602 12:47:22.815996 [CA 2] Center 36 (8~64) winsize 57
6603 12:47:22.819684 [CA 3] Center 36 (8~64) winsize 57
6604 12:47:22.822496 [CA 4] Center 36 (8~64) winsize 57
6605 12:47:22.825866 [CA 5] Center 36 (8~64) winsize 57
6606 12:47:22.825981
6607 12:47:22.829311 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6608 12:47:22.829417
6609 12:47:22.832669 [CATrainingPosCal] consider 1 rank data
6610 12:47:22.835512 u2DelayCellTimex100 = 270/100 ps
6611 12:47:22.838956 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 12:47:22.842337 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 12:47:22.849074 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 12:47:22.852283 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 12:47:22.855791 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 12:47:22.858640 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 12:47:22.858750
6618 12:47:22.862026 CA PerBit enable=1, Macro0, CA PI delay=36
6619 12:47:22.862099
6620 12:47:22.865268 [CBTSetCACLKResult] CA Dly = 36
6621 12:47:22.865366 CS Dly: 1 (0~32)
6622 12:47:22.868557 ==
6623 12:47:22.868631 Dram Type= 6, Freq= 0, CH_1, rank 1
6624 12:47:22.875183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 12:47:22.875284 ==
6626 12:47:22.878657 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6627 12:47:22.885144 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6628 12:47:22.888392 [CA 0] Center 36 (8~64) winsize 57
6629 12:47:22.891710 [CA 1] Center 36 (8~64) winsize 57
6630 12:47:22.895136 [CA 2] Center 36 (8~64) winsize 57
6631 12:47:22.898374 [CA 3] Center 36 (8~64) winsize 57
6632 12:47:22.901931 [CA 4] Center 36 (8~64) winsize 57
6633 12:47:22.905298 [CA 5] Center 36 (8~64) winsize 57
6634 12:47:22.905379
6635 12:47:22.908248 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6636 12:47:22.908330
6637 12:47:22.911553 [CATrainingPosCal] consider 2 rank data
6638 12:47:22.914705 u2DelayCellTimex100 = 270/100 ps
6639 12:47:22.918703 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 12:47:22.921805 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 12:47:22.925147 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 12:47:22.928187 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 12:47:22.934755 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 12:47:22.938000 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 12:47:22.938105
6646 12:47:22.941307 CA PerBit enable=1, Macro0, CA PI delay=36
6647 12:47:22.941388
6648 12:47:22.944666 [CBTSetCACLKResult] CA Dly = 36
6649 12:47:22.944748 CS Dly: 1 (0~32)
6650 12:47:22.944811
6651 12:47:22.948061 ----->DramcWriteLeveling(PI) begin...
6652 12:47:22.948144 ==
6653 12:47:22.951510 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 12:47:22.958194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 12:47:22.958276 ==
6656 12:47:22.961030 Write leveling (Byte 0): 40 => 8
6657 12:47:22.964437 Write leveling (Byte 1): 40 => 8
6658 12:47:22.964516 DramcWriteLeveling(PI) end<-----
6659 12:47:22.964581
6660 12:47:22.967850 ==
6661 12:47:22.967925 Dram Type= 6, Freq= 0, CH_1, rank 0
6662 12:47:22.974612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 12:47:22.974695 ==
6664 12:47:22.977576 [Gating] SW mode calibration
6665 12:47:22.984330 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6666 12:47:22.987462 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6667 12:47:22.994109 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6668 12:47:22.997309 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6669 12:47:23.001088 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6670 12:47:23.007470 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6671 12:47:23.010861 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 12:47:23.014110 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6673 12:47:23.020707 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6674 12:47:23.024058 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6675 12:47:23.027497 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6676 12:47:23.030294 Total UI for P1: 0, mck2ui 16
6677 12:47:23.034042 best dqsien dly found for B0: ( 0, 14, 24)
6678 12:47:23.037672 Total UI for P1: 0, mck2ui 16
6679 12:47:23.040422 best dqsien dly found for B1: ( 0, 14, 24)
6680 12:47:23.043728 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6681 12:47:23.046841 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6682 12:47:23.050229
6683 12:47:23.053756 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6684 12:47:23.057128 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6685 12:47:23.060345 [Gating] SW calibration Done
6686 12:47:23.060427 ==
6687 12:47:23.063857 Dram Type= 6, Freq= 0, CH_1, rank 0
6688 12:47:23.066737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 12:47:23.066820 ==
6690 12:47:23.066884 RX Vref Scan: 0
6691 12:47:23.070178
6692 12:47:23.070259 RX Vref 0 -> 0, step: 1
6693 12:47:23.070324
6694 12:47:23.073509 RX Delay -410 -> 252, step: 16
6695 12:47:23.076919 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6696 12:47:23.083174 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6697 12:47:23.086892 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6698 12:47:23.089805 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6699 12:47:23.093176 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6700 12:47:23.100034 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6701 12:47:23.103206 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6702 12:47:23.106412 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6703 12:47:23.109742 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6704 12:47:23.116469 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6705 12:47:23.119648 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6706 12:47:23.122867 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6707 12:47:23.129590 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6708 12:47:23.133084 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6709 12:47:23.136254 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6710 12:47:23.139628 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6711 12:47:23.139727 ==
6712 12:47:23.143022 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 12:47:23.149613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 12:47:23.149692 ==
6715 12:47:23.149755 DQS Delay:
6716 12:47:23.152722 DQS0 = 51, DQS1 = 67
6717 12:47:23.152796 DQM Delay:
6718 12:47:23.156068 DQM0 = 13, DQM1 = 18
6719 12:47:23.156146 DQ Delay:
6720 12:47:23.159167 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6721 12:47:23.162501 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6722 12:47:23.165839 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6723 12:47:23.168894 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6724 12:47:23.168994
6725 12:47:23.169083
6726 12:47:23.169171 ==
6727 12:47:23.172400 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 12:47:23.175680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 12:47:23.175768 ==
6730 12:47:23.175858
6731 12:47:23.175943
6732 12:47:23.179016 TX Vref Scan disable
6733 12:47:23.179114 == TX Byte 0 ==
6734 12:47:23.185542 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 12:47:23.189360 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 12:47:23.189459 == TX Byte 1 ==
6737 12:47:23.195554 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 12:47:23.198665 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 12:47:23.198764 ==
6740 12:47:23.202146 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 12:47:23.205455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 12:47:23.205554 ==
6743 12:47:23.205645
6744 12:47:23.205732
6745 12:47:23.209033 TX Vref Scan disable
6746 12:47:23.209129 == TX Byte 0 ==
6747 12:47:23.215315 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6748 12:47:23.218847 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6749 12:47:23.218929 == TX Byte 1 ==
6750 12:47:23.225274 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 12:47:23.228535 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 12:47:23.228640
6753 12:47:23.228706 [DATLAT]
6754 12:47:23.231936 Freq=400, CH1 RK0
6755 12:47:23.232034
6756 12:47:23.232131 DATLAT Default: 0xf
6757 12:47:23.235430 0, 0xFFFF, sum = 0
6758 12:47:23.235540 1, 0xFFFF, sum = 0
6759 12:47:23.238498 2, 0xFFFF, sum = 0
6760 12:47:23.238597 3, 0xFFFF, sum = 0
6761 12:47:23.241873 4, 0xFFFF, sum = 0
6762 12:47:23.241988 5, 0xFFFF, sum = 0
6763 12:47:23.244916 6, 0xFFFF, sum = 0
6764 12:47:23.245015 7, 0xFFFF, sum = 0
6765 12:47:23.248308 8, 0xFFFF, sum = 0
6766 12:47:23.251554 9, 0xFFFF, sum = 0
6767 12:47:23.251667 10, 0xFFFF, sum = 0
6768 12:47:23.255043 11, 0xFFFF, sum = 0
6769 12:47:23.255145 12, 0xFFFF, sum = 0
6770 12:47:23.258113 13, 0x0, sum = 1
6771 12:47:23.258195 14, 0x0, sum = 2
6772 12:47:23.261783 15, 0x0, sum = 3
6773 12:47:23.261866 16, 0x0, sum = 4
6774 12:47:23.261932 best_step = 14
6775 12:47:23.261991
6776 12:47:23.264901 ==
6777 12:47:23.268523 Dram Type= 6, Freq= 0, CH_1, rank 0
6778 12:47:23.271753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6779 12:47:23.271856 ==
6780 12:47:23.271947 RX Vref Scan: 1
6781 12:47:23.272036
6782 12:47:23.274724 RX Vref 0 -> 0, step: 1
6783 12:47:23.274805
6784 12:47:23.278791 RX Delay -375 -> 252, step: 8
6785 12:47:23.278893
6786 12:47:23.281398 Set Vref, RX VrefLevel [Byte0]: 56
6787 12:47:23.284713 [Byte1]: 48
6788 12:47:23.288891
6789 12:47:23.288972 Final RX Vref Byte 0 = 56 to rank0
6790 12:47:23.292195 Final RX Vref Byte 1 = 48 to rank0
6791 12:47:23.295551 Final RX Vref Byte 0 = 56 to rank1
6792 12:47:23.298556 Final RX Vref Byte 1 = 48 to rank1==
6793 12:47:23.302199 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 12:47:23.308533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 12:47:23.308628 ==
6796 12:47:23.308693 DQS Delay:
6797 12:47:23.311956 DQS0 = 56, DQS1 = 68
6798 12:47:23.312054 DQM Delay:
6799 12:47:23.312135 DQM0 = 13, DQM1 = 14
6800 12:47:23.315382 DQ Delay:
6801 12:47:23.319137 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6802 12:47:23.319234 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6803 12:47:23.321817 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6804 12:47:23.325290 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6805 12:47:23.325388
6806 12:47:23.328781
6807 12:47:23.334953 [DQSOSCAuto] RK0, (LSB)MR18= 0x5568, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
6808 12:47:23.338474 CH1 RK0: MR19=C0C, MR18=5568
6809 12:47:23.344901 CH1_RK0: MR19=0xC0C, MR18=0x5568, DQSOSC=396, MR23=63, INC=376, DEC=251
6810 12:47:23.345000 ==
6811 12:47:23.348438 Dram Type= 6, Freq= 0, CH_1, rank 1
6812 12:47:23.351650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 12:47:23.351796 ==
6814 12:47:23.355265 [Gating] SW mode calibration
6815 12:47:23.361878 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6816 12:47:23.368424 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6817 12:47:23.371742 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6818 12:47:23.374918 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6819 12:47:23.381717 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6820 12:47:23.385125 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6821 12:47:23.388171 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 12:47:23.394591 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6823 12:47:23.398191 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6824 12:47:23.401465 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6825 12:47:23.405014 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6826 12:47:23.408322 Total UI for P1: 0, mck2ui 16
6827 12:47:23.411467 best dqsien dly found for B0: ( 0, 14, 24)
6828 12:47:23.414817 Total UI for P1: 0, mck2ui 16
6829 12:47:23.418236 best dqsien dly found for B1: ( 0, 14, 24)
6830 12:47:23.421630 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6831 12:47:23.428050 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6832 12:47:23.428131
6833 12:47:23.431522 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6834 12:47:23.434922 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6835 12:47:23.437823 [Gating] SW calibration Done
6836 12:47:23.437905 ==
6837 12:47:23.441247 Dram Type= 6, Freq= 0, CH_1, rank 1
6838 12:47:23.444613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 12:47:23.444695 ==
6840 12:47:23.447864 RX Vref Scan: 0
6841 12:47:23.447945
6842 12:47:23.448009 RX Vref 0 -> 0, step: 1
6843 12:47:23.448069
6844 12:47:23.451243 RX Delay -410 -> 252, step: 16
6845 12:47:23.454827 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6846 12:47:23.461325 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6847 12:47:23.464385 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6848 12:47:23.468031 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6849 12:47:23.471310 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6850 12:47:23.477664 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6851 12:47:23.480971 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6852 12:47:23.484212 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6853 12:47:23.487868 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6854 12:47:23.494545 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6855 12:47:23.497940 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6856 12:47:23.500956 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6857 12:47:23.507788 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6858 12:47:23.510838 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6859 12:47:23.514038 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6860 12:47:23.517725 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6861 12:47:23.517808 ==
6862 12:47:23.520686 Dram Type= 6, Freq= 0, CH_1, rank 1
6863 12:47:23.527652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 12:47:23.527734 ==
6865 12:47:23.527798 DQS Delay:
6866 12:47:23.531026 DQS0 = 59, DQS1 = 59
6867 12:47:23.531108 DQM Delay:
6868 12:47:23.531172 DQM0 = 19, DQM1 = 12
6869 12:47:23.534574 DQ Delay:
6870 12:47:23.537379 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6871 12:47:23.540970 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6872 12:47:23.541051 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6873 12:47:23.547696 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6874 12:47:23.547805
6875 12:47:23.547896
6876 12:47:23.547970 ==
6877 12:47:23.551231 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 12:47:23.554013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 12:47:23.554129 ==
6880 12:47:23.554221
6881 12:47:23.554317
6882 12:47:23.557393 TX Vref Scan disable
6883 12:47:23.557498 == TX Byte 0 ==
6884 12:47:23.561043 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6885 12:47:23.567488 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6886 12:47:23.567592 == TX Byte 1 ==
6887 12:47:23.570646 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6888 12:47:23.577266 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6889 12:47:23.577352 ==
6890 12:47:23.580582 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 12:47:23.584382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 12:47:23.584464 ==
6893 12:47:23.584528
6894 12:47:23.584587
6895 12:47:23.587481 TX Vref Scan disable
6896 12:47:23.587562 == TX Byte 0 ==
6897 12:47:23.590848 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6898 12:47:23.597329 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6899 12:47:23.597435 == TX Byte 1 ==
6900 12:47:23.600653 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6901 12:47:23.607080 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6902 12:47:23.607187
6903 12:47:23.607283 [DATLAT]
6904 12:47:23.607393 Freq=400, CH1 RK1
6905 12:47:23.610738
6906 12:47:23.610818 DATLAT Default: 0xe
6907 12:47:23.613840 0, 0xFFFF, sum = 0
6908 12:47:23.613938 1, 0xFFFF, sum = 0
6909 12:47:23.617487 2, 0xFFFF, sum = 0
6910 12:47:23.617569 3, 0xFFFF, sum = 0
6911 12:47:23.620431 4, 0xFFFF, sum = 0
6912 12:47:23.620514 5, 0xFFFF, sum = 0
6913 12:47:23.623735 6, 0xFFFF, sum = 0
6914 12:47:23.623818 7, 0xFFFF, sum = 0
6915 12:47:23.627063 8, 0xFFFF, sum = 0
6916 12:47:23.627173 9, 0xFFFF, sum = 0
6917 12:47:23.630540 10, 0xFFFF, sum = 0
6918 12:47:23.630623 11, 0xFFFF, sum = 0
6919 12:47:23.634025 12, 0xFFFF, sum = 0
6920 12:47:23.634108 13, 0x0, sum = 1
6921 12:47:23.637383 14, 0x0, sum = 2
6922 12:47:23.637465 15, 0x0, sum = 3
6923 12:47:23.640384 16, 0x0, sum = 4
6924 12:47:23.640467 best_step = 14
6925 12:47:23.640530
6926 12:47:23.640590 ==
6927 12:47:23.643694 Dram Type= 6, Freq= 0, CH_1, rank 1
6928 12:47:23.650119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6929 12:47:23.650207 ==
6930 12:47:23.650271 RX Vref Scan: 0
6931 12:47:23.650331
6932 12:47:23.653992 RX Vref 0 -> 0, step: 1
6933 12:47:23.654099
6934 12:47:23.657253 RX Delay -359 -> 252, step: 8
6935 12:47:23.663544 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6936 12:47:23.666894 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6937 12:47:23.670233 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6938 12:47:23.673609 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6939 12:47:23.680325 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6940 12:47:23.683457 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6941 12:47:23.687407 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6942 12:47:23.690391 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6943 12:47:23.696670 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6944 12:47:23.699826 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6945 12:47:23.703572 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6946 12:47:23.706875 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6947 12:47:23.713048 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6948 12:47:23.717094 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6949 12:47:23.719724 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6950 12:47:23.726487 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6951 12:47:23.726563 ==
6952 12:47:23.730095 Dram Type= 6, Freq= 0, CH_1, rank 1
6953 12:47:23.732905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6954 12:47:23.732986 ==
6955 12:47:23.733052 DQS Delay:
6956 12:47:23.736519 DQS0 = 60, DQS1 = 64
6957 12:47:23.736594 DQM Delay:
6958 12:47:23.739983 DQM0 = 12, DQM1 = 10
6959 12:47:23.740054 DQ Delay:
6960 12:47:23.742832 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6961 12:47:23.746206 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6962 12:47:23.749716 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6963 12:47:23.752989 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6964 12:47:23.753067
6965 12:47:23.753128
6966 12:47:23.759294 [DQSOSCAuto] RK1, (LSB)MR18= 0x7cac, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6967 12:47:23.762756 CH1 RK1: MR19=C0C, MR18=7CAC
6968 12:47:23.769533 CH1_RK1: MR19=0xC0C, MR18=0x7CAC, DQSOSC=388, MR23=63, INC=392, DEC=261
6969 12:47:23.772864 [RxdqsGatingPostProcess] freq 400
6970 12:47:23.779307 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6971 12:47:23.782758 best DQS0 dly(2T, 0.5T) = (0, 10)
6972 12:47:23.782831 best DQS1 dly(2T, 0.5T) = (0, 10)
6973 12:47:23.786241 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6974 12:47:23.789496 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6975 12:47:23.792897 best DQS0 dly(2T, 0.5T) = (0, 10)
6976 12:47:23.796432 best DQS1 dly(2T, 0.5T) = (0, 10)
6977 12:47:23.799289 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6978 12:47:23.802868 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6979 12:47:23.806003 Pre-setting of DQS Precalculation
6980 12:47:23.812527 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6981 12:47:23.819486 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6982 12:47:23.825706 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6983 12:47:23.825793
6984 12:47:23.825856
6985 12:47:23.829145 [Calibration Summary] 800 Mbps
6986 12:47:23.829219 CH 0, Rank 0
6987 12:47:23.832503 SW Impedance : PASS
6988 12:47:23.836067 DUTY Scan : NO K
6989 12:47:23.836172 ZQ Calibration : PASS
6990 12:47:23.839557 Jitter Meter : NO K
6991 12:47:23.839632 CBT Training : PASS
6992 12:47:23.842655 Write leveling : PASS
6993 12:47:23.845987 RX DQS gating : PASS
6994 12:47:23.846068 RX DQ/DQS(RDDQC) : PASS
6995 12:47:23.848982 TX DQ/DQS : PASS
6996 12:47:23.852601 RX DATLAT : PASS
6997 12:47:23.852682 RX DQ/DQS(Engine): PASS
6998 12:47:23.855952 TX OE : NO K
6999 12:47:23.856034 All Pass.
7000 12:47:23.856098
7001 12:47:23.858887 CH 0, Rank 1
7002 12:47:23.858968 SW Impedance : PASS
7003 12:47:23.862275 DUTY Scan : NO K
7004 12:47:23.865523 ZQ Calibration : PASS
7005 12:47:23.865604 Jitter Meter : NO K
7006 12:47:23.869209 CBT Training : PASS
7007 12:47:23.872131 Write leveling : NO K
7008 12:47:23.872228 RX DQS gating : PASS
7009 12:47:23.875436 RX DQ/DQS(RDDQC) : PASS
7010 12:47:23.878688 TX DQ/DQS : PASS
7011 12:47:23.878770 RX DATLAT : PASS
7012 12:47:23.882104 RX DQ/DQS(Engine): PASS
7013 12:47:23.885557 TX OE : NO K
7014 12:47:23.885639 All Pass.
7015 12:47:23.885703
7016 12:47:23.885761 CH 1, Rank 0
7017 12:47:23.889037 SW Impedance : PASS
7018 12:47:23.892367 DUTY Scan : NO K
7019 12:47:23.892449 ZQ Calibration : PASS
7020 12:47:23.895549 Jitter Meter : NO K
7021 12:47:23.898941 CBT Training : PASS
7022 12:47:23.899022 Write leveling : PASS
7023 12:47:23.902355 RX DQS gating : PASS
7024 12:47:23.902436 RX DQ/DQS(RDDQC) : PASS
7025 12:47:23.905534 TX DQ/DQS : PASS
7026 12:47:23.908638 RX DATLAT : PASS
7027 12:47:23.908720 RX DQ/DQS(Engine): PASS
7028 12:47:23.911959 TX OE : NO K
7029 12:47:23.912041 All Pass.
7030 12:47:23.912131
7031 12:47:23.915532 CH 1, Rank 1
7032 12:47:23.915613 SW Impedance : PASS
7033 12:47:23.918510 DUTY Scan : NO K
7034 12:47:23.922137 ZQ Calibration : PASS
7035 12:47:23.922218 Jitter Meter : NO K
7036 12:47:23.925093 CBT Training : PASS
7037 12:47:23.928404 Write leveling : NO K
7038 12:47:23.928512 RX DQS gating : PASS
7039 12:47:23.931866 RX DQ/DQS(RDDQC) : PASS
7040 12:47:23.934870 TX DQ/DQS : PASS
7041 12:47:23.934950 RX DATLAT : PASS
7042 12:47:23.938348 RX DQ/DQS(Engine): PASS
7043 12:47:23.941802 TX OE : NO K
7044 12:47:23.941903 All Pass.
7045 12:47:23.942019
7046 12:47:23.942109 DramC Write-DBI off
7047 12:47:23.945436 PER_BANK_REFRESH: Hybrid Mode
7048 12:47:23.948327 TX_TRACKING: ON
7049 12:47:23.955015 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7050 12:47:23.958249 [FAST_K] Save calibration result to emmc
7051 12:47:23.965327 dramc_set_vcore_voltage set vcore to 725000
7052 12:47:23.965415 Read voltage for 1600, 0
7053 12:47:23.968544 Vio18 = 0
7054 12:47:23.968664 Vcore = 725000
7055 12:47:23.968755 Vdram = 0
7056 12:47:23.968857 Vddq = 0
7057 12:47:23.971957 Vmddr = 0
7058 12:47:23.974917 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7059 12:47:23.981726 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7060 12:47:23.985331 MEM_TYPE=3, freq_sel=13
7061 12:47:23.985436 sv_algorithm_assistance_LP4_3733
7062 12:47:23.991684 ============ PULL DRAM RESETB DOWN ============
7063 12:47:23.995026 ========== PULL DRAM RESETB DOWN end =========
7064 12:47:23.998531 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7065 12:47:24.001705 ===================================
7066 12:47:24.005175 LPDDR4 DRAM CONFIGURATION
7067 12:47:24.008772 ===================================
7068 12:47:24.012026 EX_ROW_EN[0] = 0x0
7069 12:47:24.012106 EX_ROW_EN[1] = 0x0
7070 12:47:24.015129 LP4Y_EN = 0x0
7071 12:47:24.015227 WORK_FSP = 0x1
7072 12:47:24.018430 WL = 0x5
7073 12:47:24.018534 RL = 0x5
7074 12:47:24.021781 BL = 0x2
7075 12:47:24.021877 RPST = 0x0
7076 12:47:24.025175 RD_PRE = 0x0
7077 12:47:24.025278 WR_PRE = 0x1
7078 12:47:24.028197 WR_PST = 0x1
7079 12:47:24.028276 DBI_WR = 0x0
7080 12:47:24.031864 DBI_RD = 0x0
7081 12:47:24.035026 OTF = 0x1
7082 12:47:24.038281 ===================================
7083 12:47:24.038365 ===================================
7084 12:47:24.041622 ANA top config
7085 12:47:24.045159 ===================================
7086 12:47:24.048058 DLL_ASYNC_EN = 0
7087 12:47:24.048140 ALL_SLAVE_EN = 0
7088 12:47:24.051297 NEW_RANK_MODE = 1
7089 12:47:24.054845 DLL_IDLE_MODE = 1
7090 12:47:24.058200 LP45_APHY_COMB_EN = 1
7091 12:47:24.061473 TX_ODT_DIS = 0
7092 12:47:24.061579 NEW_8X_MODE = 1
7093 12:47:24.064763 ===================================
7094 12:47:24.067852 ===================================
7095 12:47:24.070991 data_rate = 3200
7096 12:47:24.074412 CKR = 1
7097 12:47:24.077931 DQ_P2S_RATIO = 8
7098 12:47:24.081644 ===================================
7099 12:47:24.084981 CA_P2S_RATIO = 8
7100 12:47:24.088113 DQ_CA_OPEN = 0
7101 12:47:24.088192 DQ_SEMI_OPEN = 0
7102 12:47:24.091334 CA_SEMI_OPEN = 0
7103 12:47:24.094373 CA_FULL_RATE = 0
7104 12:47:24.097822 DQ_CKDIV4_EN = 0
7105 12:47:24.101252 CA_CKDIV4_EN = 0
7106 12:47:24.104667 CA_PREDIV_EN = 0
7107 12:47:24.104747 PH8_DLY = 12
7108 12:47:24.107514 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7109 12:47:24.110833 DQ_AAMCK_DIV = 4
7110 12:47:24.114348 CA_AAMCK_DIV = 4
7111 12:47:24.117741 CA_ADMCK_DIV = 4
7112 12:47:24.120780 DQ_TRACK_CA_EN = 0
7113 12:47:24.124075 CA_PICK = 1600
7114 12:47:24.124149 CA_MCKIO = 1600
7115 12:47:24.127940 MCKIO_SEMI = 0
7116 12:47:24.130530 PLL_FREQ = 3068
7117 12:47:24.133868 DQ_UI_PI_RATIO = 32
7118 12:47:24.137177 CA_UI_PI_RATIO = 0
7119 12:47:24.140879 ===================================
7120 12:47:24.144161 ===================================
7121 12:47:24.147600 memory_type:LPDDR4
7122 12:47:24.147701 GP_NUM : 10
7123 12:47:24.151061 SRAM_EN : 1
7124 12:47:24.151137 MD32_EN : 0
7125 12:47:24.153886 ===================================
7126 12:47:24.157256 [ANA_INIT] >>>>>>>>>>>>>>
7127 12:47:24.160612 <<<<<< [CONFIGURE PHASE]: ANA_TX
7128 12:47:24.163851 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7129 12:47:24.167509 ===================================
7130 12:47:24.170871 data_rate = 3200,PCW = 0X7600
7131 12:47:24.173777 ===================================
7132 12:47:24.177332 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7133 12:47:24.183835 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7134 12:47:24.187192 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7135 12:47:24.194026 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7136 12:47:24.197071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7137 12:47:24.200607 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7138 12:47:24.200686 [ANA_INIT] flow start
7139 12:47:24.203630 [ANA_INIT] PLL >>>>>>>>
7140 12:47:24.207046 [ANA_INIT] PLL <<<<<<<<
7141 12:47:24.207127 [ANA_INIT] MIDPI >>>>>>>>
7142 12:47:24.210536 [ANA_INIT] MIDPI <<<<<<<<
7143 12:47:24.213563 [ANA_INIT] DLL >>>>>>>>
7144 12:47:24.213644 [ANA_INIT] DLL <<<<<<<<
7145 12:47:24.217048 [ANA_INIT] flow end
7146 12:47:24.220526 ============ LP4 DIFF to SE enter ============
7147 12:47:24.223772 ============ LP4 DIFF to SE exit ============
7148 12:47:24.227026 [ANA_INIT] <<<<<<<<<<<<<
7149 12:47:24.230299 [Flow] Enable top DCM control >>>>>
7150 12:47:24.233553 [Flow] Enable top DCM control <<<<<
7151 12:47:24.237478 Enable DLL master slave shuffle
7152 12:47:24.243582 ==============================================================
7153 12:47:24.243663 Gating Mode config
7154 12:47:24.250019 ==============================================================
7155 12:47:24.253307 Config description:
7156 12:47:24.260108 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7157 12:47:24.266880 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7158 12:47:24.273421 SELPH_MODE 0: By rank 1: By Phase
7159 12:47:24.280253 ==============================================================
7160 12:47:24.280333 GAT_TRACK_EN = 1
7161 12:47:24.283142 RX_GATING_MODE = 2
7162 12:47:24.286719 RX_GATING_TRACK_MODE = 2
7163 12:47:24.290175 SELPH_MODE = 1
7164 12:47:24.293543 PICG_EARLY_EN = 1
7165 12:47:24.296427 VALID_LAT_VALUE = 1
7166 12:47:24.303781 ==============================================================
7167 12:47:24.306449 Enter into Gating configuration >>>>
7168 12:47:24.310151 Exit from Gating configuration <<<<
7169 12:47:24.313192 Enter into DVFS_PRE_config >>>>>
7170 12:47:24.322943 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7171 12:47:24.326587 Exit from DVFS_PRE_config <<<<<
7172 12:47:24.329826 Enter into PICG configuration >>>>
7173 12:47:24.332943 Exit from PICG configuration <<<<
7174 12:47:24.336257 [RX_INPUT] configuration >>>>>
7175 12:47:24.336337 [RX_INPUT] configuration <<<<<
7176 12:47:24.342855 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7177 12:47:24.349562 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7178 12:47:24.356064 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7179 12:47:24.359583 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7180 12:47:24.366578 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7181 12:47:24.373023 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7182 12:47:24.376293 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7183 12:47:24.379425 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7184 12:47:24.386235 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7185 12:47:24.389590 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7186 12:47:24.392570 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7187 12:47:24.399259 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7188 12:47:24.402855 ===================================
7189 12:47:24.402937 LPDDR4 DRAM CONFIGURATION
7190 12:47:24.405748 ===================================
7191 12:47:24.409097 EX_ROW_EN[0] = 0x0
7192 12:47:24.413075 EX_ROW_EN[1] = 0x0
7193 12:47:24.413156 LP4Y_EN = 0x0
7194 12:47:24.415650 WORK_FSP = 0x1
7195 12:47:24.415732 WL = 0x5
7196 12:47:24.418922 RL = 0x5
7197 12:47:24.419004 BL = 0x2
7198 12:47:24.422325 RPST = 0x0
7199 12:47:24.422406 RD_PRE = 0x0
7200 12:47:24.425723 WR_PRE = 0x1
7201 12:47:24.425804 WR_PST = 0x1
7202 12:47:24.429042 DBI_WR = 0x0
7203 12:47:24.429123 DBI_RD = 0x0
7204 12:47:24.432787 OTF = 0x1
7205 12:47:24.435553 ===================================
7206 12:47:24.439109 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7207 12:47:24.442623 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7208 12:47:24.448872 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7209 12:47:24.452704 ===================================
7210 12:47:24.452785 LPDDR4 DRAM CONFIGURATION
7211 12:47:24.455754 ===================================
7212 12:47:24.458861 EX_ROW_EN[0] = 0x10
7213 12:47:24.458943 EX_ROW_EN[1] = 0x0
7214 12:47:24.462329 LP4Y_EN = 0x0
7215 12:47:24.465556 WORK_FSP = 0x1
7216 12:47:24.465713 WL = 0x5
7217 12:47:24.469174 RL = 0x5
7218 12:47:24.469254 BL = 0x2
7219 12:47:24.472258 RPST = 0x0
7220 12:47:24.472339 RD_PRE = 0x0
7221 12:47:24.475419 WR_PRE = 0x1
7222 12:47:24.475500 WR_PST = 0x1
7223 12:47:24.478834 DBI_WR = 0x0
7224 12:47:24.478941 DBI_RD = 0x0
7225 12:47:24.482143 OTF = 0x1
7226 12:47:24.485560 ===================================
7227 12:47:24.492322 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7228 12:47:24.492404 ==
7229 12:47:24.495776 Dram Type= 6, Freq= 0, CH_0, rank 0
7230 12:47:24.498642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7231 12:47:24.498724 ==
7232 12:47:24.502171 [Duty_Offset_Calibration]
7233 12:47:24.502252 B0:2 B1:0 CA:3
7234 12:47:24.502315
7235 12:47:24.505572 [DutyScan_Calibration_Flow] k_type=0
7236 12:47:24.516011
7237 12:47:24.516092 ==CLK 0==
7238 12:47:24.518648 Final CLK duty delay cell = 0
7239 12:47:24.522236 [0] MAX Duty = 5031%(X100), DQS PI = 12
7240 12:47:24.525569 [0] MIN Duty = 4907%(X100), DQS PI = 6
7241 12:47:24.525651 [0] AVG Duty = 4969%(X100)
7242 12:47:24.529015
7243 12:47:24.531944 CH0 CLK Duty spec in!! Max-Min= 124%
7244 12:47:24.535397 [DutyScan_Calibration_Flow] ====Done====
7245 12:47:24.535493
7246 12:47:24.538701 [DutyScan_Calibration_Flow] k_type=1
7247 12:47:24.555671
7248 12:47:24.555751 ==DQS 0 ==
7249 12:47:24.558767 Final DQS duty delay cell = 0
7250 12:47:24.562366 [0] MAX Duty = 5094%(X100), DQS PI = 30
7251 12:47:24.565232 [0] MIN Duty = 4875%(X100), DQS PI = 0
7252 12:47:24.568595 [0] AVG Duty = 4984%(X100)
7253 12:47:24.568676
7254 12:47:24.568740 ==DQS 1 ==
7255 12:47:24.571886 Final DQS duty delay cell = 0
7256 12:47:24.575082 [0] MAX Duty = 5156%(X100), DQS PI = 32
7257 12:47:24.578476 [0] MIN Duty = 5031%(X100), DQS PI = 14
7258 12:47:24.581984 [0] AVG Duty = 5093%(X100)
7259 12:47:24.582065
7260 12:47:24.585134 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7261 12:47:24.585216
7262 12:47:24.588465 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7263 12:47:24.591561 [DutyScan_Calibration_Flow] ====Done====
7264 12:47:24.591681
7265 12:47:24.594813 [DutyScan_Calibration_Flow] k_type=3
7266 12:47:24.612486
7267 12:47:24.612607 ==DQM 0 ==
7268 12:47:24.615976 Final DQM duty delay cell = 0
7269 12:47:24.619630 [0] MAX Duty = 5187%(X100), DQS PI = 30
7270 12:47:24.622722 [0] MIN Duty = 4906%(X100), DQS PI = 0
7271 12:47:24.622840 [0] AVG Duty = 5046%(X100)
7272 12:47:24.626152
7273 12:47:24.626270 ==DQM 1 ==
7274 12:47:24.629317 Final DQM duty delay cell = 0
7275 12:47:24.632689 [0] MAX Duty = 4938%(X100), DQS PI = 60
7276 12:47:24.636162 [0] MIN Duty = 4813%(X100), DQS PI = 14
7277 12:47:24.639632 [0] AVG Duty = 4875%(X100)
7278 12:47:24.639749
7279 12:47:24.642317 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7280 12:47:24.642434
7281 12:47:24.645736 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7282 12:47:24.649136 [DutyScan_Calibration_Flow] ====Done====
7283 12:47:24.649253
7284 12:47:24.652347 [DutyScan_Calibration_Flow] k_type=2
7285 12:47:24.669037
7286 12:47:24.669156 ==DQ 0 ==
7287 12:47:24.672705 Final DQ duty delay cell = -4
7288 12:47:24.675668 [-4] MAX Duty = 5000%(X100), DQS PI = 12
7289 12:47:24.678865 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7290 12:47:24.681976 [-4] AVG Duty = 4938%(X100)
7291 12:47:24.682093
7292 12:47:24.682201 ==DQ 1 ==
7293 12:47:24.685997 Final DQ duty delay cell = 0
7294 12:47:24.688532 [0] MAX Duty = 5156%(X100), DQS PI = 58
7295 12:47:24.692343 [0] MIN Duty = 5000%(X100), DQS PI = 16
7296 12:47:24.695607 [0] AVG Duty = 5078%(X100)
7297 12:47:24.695724
7298 12:47:24.698538 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7299 12:47:24.698655
7300 12:47:24.702214 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7301 12:47:24.705145 [DutyScan_Calibration_Flow] ====Done====
7302 12:47:24.705261 ==
7303 12:47:24.708730 Dram Type= 6, Freq= 0, CH_1, rank 0
7304 12:47:24.711776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7305 12:47:24.711896 ==
7306 12:47:24.715273 [Duty_Offset_Calibration]
7307 12:47:24.715430 B0:1 B1:-2 CA:0
7308 12:47:24.715537
7309 12:47:24.718865 [DutyScan_Calibration_Flow] k_type=0
7310 12:47:24.729361
7311 12:47:24.729479 ==CLK 0==
7312 12:47:24.733120 Final CLK duty delay cell = 0
7313 12:47:24.736436 [0] MAX Duty = 5093%(X100), DQS PI = 20
7314 12:47:24.739771 [0] MIN Duty = 4813%(X100), DQS PI = 60
7315 12:47:24.739887 [0] AVG Duty = 4953%(X100)
7316 12:47:24.743255
7317 12:47:24.746139 CH1 CLK Duty spec in!! Max-Min= 280%
7318 12:47:24.749417 [DutyScan_Calibration_Flow] ====Done====
7319 12:47:24.749534
7320 12:47:24.752948 [DutyScan_Calibration_Flow] k_type=1
7321 12:47:24.769508
7322 12:47:24.769624 ==DQS 0 ==
7323 12:47:24.773124 Final DQS duty delay cell = 0
7324 12:47:24.775913 [0] MAX Duty = 5187%(X100), DQS PI = 26
7325 12:47:24.779308 [0] MIN Duty = 5031%(X100), DQS PI = 62
7326 12:47:24.782684 [0] AVG Duty = 5109%(X100)
7327 12:47:24.782800
7328 12:47:24.782905 ==DQS 1 ==
7329 12:47:24.786292 Final DQS duty delay cell = 0
7330 12:47:24.789924 [0] MAX Duty = 5093%(X100), DQS PI = 62
7331 12:47:24.792693 [0] MIN Duty = 4844%(X100), DQS PI = 24
7332 12:47:24.795985 [0] AVG Duty = 4968%(X100)
7333 12:47:24.796103
7334 12:47:24.799247 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7335 12:47:24.799363
7336 12:47:24.802674 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7337 12:47:24.805593 [DutyScan_Calibration_Flow] ====Done====
7338 12:47:24.805708
7339 12:47:24.808962 [DutyScan_Calibration_Flow] k_type=3
7340 12:47:24.826253
7341 12:47:24.826369 ==DQM 0 ==
7342 12:47:24.829282 Final DQM duty delay cell = 0
7343 12:47:24.832583 [0] MAX Duty = 5062%(X100), DQS PI = 26
7344 12:47:24.836335 [0] MIN Duty = 4813%(X100), DQS PI = 54
7345 12:47:24.840089 [0] AVG Duty = 4937%(X100)
7346 12:47:24.840207
7347 12:47:24.840314 ==DQM 1 ==
7348 12:47:24.842778 Final DQM duty delay cell = 0
7349 12:47:24.846178 [0] MAX Duty = 5062%(X100), DQS PI = 34
7350 12:47:24.849355 [0] MIN Duty = 4875%(X100), DQS PI = 24
7351 12:47:24.852555 [0] AVG Duty = 4968%(X100)
7352 12:47:24.852671
7353 12:47:24.856247 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7354 12:47:24.856364
7355 12:47:24.859695 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7356 12:47:24.862683 [DutyScan_Calibration_Flow] ====Done====
7357 12:47:24.862800
7358 12:47:24.866139 [DutyScan_Calibration_Flow] k_type=2
7359 12:47:24.883165
7360 12:47:24.883283 ==DQ 0 ==
7361 12:47:24.886613 Final DQ duty delay cell = 0
7362 12:47:24.889875 [0] MAX Duty = 5093%(X100), DQS PI = 22
7363 12:47:24.892880 [0] MIN Duty = 4907%(X100), DQS PI = 62
7364 12:47:24.892998 [0] AVG Duty = 5000%(X100)
7365 12:47:24.896342
7366 12:47:24.896461 ==DQ 1 ==
7367 12:47:24.900003 Final DQ duty delay cell = 0
7368 12:47:24.902785 [0] MAX Duty = 5125%(X100), DQS PI = 34
7369 12:47:24.906107 [0] MIN Duty = 4969%(X100), DQS PI = 24
7370 12:47:24.906227 [0] AVG Duty = 5047%(X100)
7371 12:47:24.909565
7372 12:47:24.913276 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7373 12:47:24.913394
7374 12:47:24.916481 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7375 12:47:24.919689 [DutyScan_Calibration_Flow] ====Done====
7376 12:47:24.923189 nWR fixed to 30
7377 12:47:24.923309 [ModeRegInit_LP4] CH0 RK0
7378 12:47:24.926565 [ModeRegInit_LP4] CH0 RK1
7379 12:47:24.929505 [ModeRegInit_LP4] CH1 RK0
7380 12:47:24.932832 [ModeRegInit_LP4] CH1 RK1
7381 12:47:24.932950 match AC timing 5
7382 12:47:24.936321 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7383 12:47:24.943006 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7384 12:47:24.946111 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7385 12:47:24.953225 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7386 12:47:24.956307 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7387 12:47:24.956424 [MiockJmeterHQA]
7388 12:47:24.956531
7389 12:47:24.959449 [DramcMiockJmeter] u1RxGatingPI = 0
7390 12:47:24.962655 0 : 4255, 4029
7391 12:47:24.962776 4 : 4252, 4027
7392 12:47:24.966150 8 : 4255, 4030
7393 12:47:24.966269 12 : 4253, 4027
7394 12:47:24.966410 16 : 4254, 4029
7395 12:47:24.969469 20 : 4252, 4027
7396 12:47:24.969588 24 : 4252, 4027
7397 12:47:24.972646 28 : 4363, 4138
7398 12:47:24.972766 32 : 4252, 4027
7399 12:47:24.976380 36 : 4252, 4027
7400 12:47:24.976499 40 : 4253, 4027
7401 12:47:24.976609 44 : 4363, 4138
7402 12:47:24.979251 48 : 4252, 4027
7403 12:47:24.979376 52 : 4363, 4140
7404 12:47:24.982847 56 : 4250, 4027
7405 12:47:24.982966 60 : 4250, 4027
7406 12:47:24.986140 64 : 4250, 4027
7407 12:47:24.986260 68 : 4250, 4027
7408 12:47:24.989612 72 : 4361, 4137
7409 12:47:24.989732 76 : 4250, 4027
7410 12:47:24.989843 80 : 4360, 4138
7411 12:47:24.992603 84 : 4250, 4027
7412 12:47:24.992722 88 : 4250, 4027
7413 12:47:24.995955 92 : 4250, 4027
7414 12:47:24.996075 96 : 4360, 4138
7415 12:47:24.999247 100 : 4250, 4027
7416 12:47:24.999367 104 : 4250, 3883
7417 12:47:25.002721 108 : 4250, 10
7418 12:47:25.002842 112 : 4252, 0
7419 12:47:25.002952 116 : 4361, 0
7420 12:47:25.005587 120 : 4361, 0
7421 12:47:25.005706 124 : 4363, 0
7422 12:47:25.008808 128 : 4253, 0
7423 12:47:25.008928 132 : 4252, 0
7424 12:47:25.009037 136 : 4250, 0
7425 12:47:25.012417 140 : 4253, 0
7426 12:47:25.012538 144 : 4252, 0
7427 12:47:25.015617 148 : 4250, 0
7428 12:47:25.015737 152 : 4253, 0
7429 12:47:25.015847 156 : 4250, 0
7430 12:47:25.019181 160 : 4250, 0
7431 12:47:25.019300 164 : 4253, 0
7432 12:47:25.022401 168 : 4360, 0
7433 12:47:25.022519 172 : 4361, 0
7434 12:47:25.022626 176 : 4362, 0
7435 12:47:25.025861 180 : 4250, 0
7436 12:47:25.025979 184 : 4250, 0
7437 12:47:25.026091 188 : 4250, 0
7438 12:47:25.028703 192 : 4253, 0
7439 12:47:25.028821 196 : 4250, 0
7440 12:47:25.032064 200 : 4250, 0
7441 12:47:25.032185 204 : 4253, 0
7442 12:47:25.032294 208 : 4252, 0
7443 12:47:25.035303 212 : 4250, 0
7444 12:47:25.035458 216 : 4253, 0
7445 12:47:25.038586 220 : 4363, 0
7446 12:47:25.038707 224 : 4361, 0
7447 12:47:25.038816 228 : 4362, 0
7448 12:47:25.041952 232 : 4250, 0
7449 12:47:25.042072 236 : 4250, 1138
7450 12:47:25.045321 240 : 4250, 4027
7451 12:47:25.045439 244 : 4253, 4029
7452 12:47:25.048474 248 : 4250, 4027
7453 12:47:25.048593 252 : 4360, 4138
7454 12:47:25.051945 256 : 4360, 4138
7455 12:47:25.052066 260 : 4247, 4025
7456 12:47:25.055016 264 : 4360, 4138
7457 12:47:25.055134 268 : 4361, 4137
7458 12:47:25.055244 272 : 4250, 4027
7459 12:47:25.058558 276 : 4250, 4027
7460 12:47:25.058678 280 : 4250, 4027
7461 12:47:25.061902 284 : 4250, 4027
7462 12:47:25.062020 288 : 4250, 4027
7463 12:47:25.065270 292 : 4249, 4027
7464 12:47:25.065388 296 : 4252, 4029
7465 12:47:25.068702 300 : 4250, 4027
7466 12:47:25.068822 304 : 4361, 4137
7467 12:47:25.071756 308 : 4360, 4138
7468 12:47:25.071875 312 : 4250, 4027
7469 12:47:25.075182 316 : 4360, 4138
7470 12:47:25.075301 320 : 4250, 4026
7471 12:47:25.078418 324 : 4250, 4027
7472 12:47:25.078535 328 : 4252, 4027
7473 12:47:25.078645 332 : 4250, 4027
7474 12:47:25.081999 336 : 4250, 4027
7475 12:47:25.082119 340 : 4250, 4027
7476 12:47:25.084986 344 : 4249, 4027
7477 12:47:25.085106 348 : 4250, 4027
7478 12:47:25.088336 352 : 4250, 4025
7479 12:47:25.088455 356 : 4361, 2910
7480 12:47:25.091690 360 : 4360, 1
7481 12:47:25.091809
7482 12:47:25.091917 MIOCK jitter meter ch=0
7483 12:47:25.092019
7484 12:47:25.095289 1T = (360-108) = 252 dly cells
7485 12:47:25.101576 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7486 12:47:25.101696 ==
7487 12:47:25.104910 Dram Type= 6, Freq= 0, CH_0, rank 0
7488 12:47:25.108124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7489 12:47:25.108244 ==
7490 12:47:25.114799 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7491 12:47:25.118022 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7492 12:47:25.124883 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7493 12:47:25.128297 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7494 12:47:25.138642 [CA 0] Center 44 (14~75) winsize 62
7495 12:47:25.141354 [CA 1] Center 43 (13~74) winsize 62
7496 12:47:25.145177 [CA 2] Center 39 (10~69) winsize 60
7497 12:47:25.147982 [CA 3] Center 39 (10~68) winsize 59
7498 12:47:25.151547 [CA 4] Center 37 (8~67) winsize 60
7499 12:47:25.154790 [CA 5] Center 37 (7~67) winsize 61
7500 12:47:25.154907
7501 12:47:25.158073 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7502 12:47:25.158190
7503 12:47:25.164451 [CATrainingPosCal] consider 1 rank data
7504 12:47:25.164578 u2DelayCellTimex100 = 258/100 ps
7505 12:47:25.171411 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7506 12:47:25.174820 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7507 12:47:25.178177 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7508 12:47:25.181453 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7509 12:47:25.184454 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7510 12:47:25.187739 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7511 12:47:25.187855
7512 12:47:25.191590 CA PerBit enable=1, Macro0, CA PI delay=37
7513 12:47:25.191709
7514 12:47:25.194636 [CBTSetCACLKResult] CA Dly = 37
7515 12:47:25.197808 CS Dly: 11 (0~42)
7516 12:47:25.201306 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7517 12:47:25.204621 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7518 12:47:25.204740 ==
7519 12:47:25.207960 Dram Type= 6, Freq= 0, CH_0, rank 1
7520 12:47:25.214257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7521 12:47:25.214378 ==
7522 12:47:25.217831 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7523 12:47:25.224849 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7524 12:47:25.227893 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7525 12:47:25.234030 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7526 12:47:25.241872 [CA 0] Center 44 (14~75) winsize 62
7527 12:47:25.245162 [CA 1] Center 43 (13~74) winsize 62
7528 12:47:25.248487 [CA 2] Center 39 (10~69) winsize 60
7529 12:47:25.251750 [CA 3] Center 39 (10~69) winsize 60
7530 12:47:25.255123 [CA 4] Center 37 (8~67) winsize 60
7531 12:47:25.258556 [CA 5] Center 37 (7~67) winsize 61
7532 12:47:25.258673
7533 12:47:25.261968 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7534 12:47:25.262087
7535 12:47:25.268028 [CATrainingPosCal] consider 2 rank data
7536 12:47:25.268146 u2DelayCellTimex100 = 258/100 ps
7537 12:47:25.274836 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7538 12:47:25.278241 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7539 12:47:25.281602 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7540 12:47:25.285014 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7541 12:47:25.287859 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7542 12:47:25.291206 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7543 12:47:25.291323
7544 12:47:25.295032 CA PerBit enable=1, Macro0, CA PI delay=37
7545 12:47:25.295150
7546 12:47:25.298148 [CBTSetCACLKResult] CA Dly = 37
7547 12:47:25.301668 CS Dly: 11 (0~43)
7548 12:47:25.304526 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7549 12:47:25.308236 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7550 12:47:25.308353
7551 12:47:25.311095 ----->DramcWriteLeveling(PI) begin...
7552 12:47:25.314375 ==
7553 12:47:25.314493 Dram Type= 6, Freq= 0, CH_0, rank 0
7554 12:47:25.321558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7555 12:47:25.321679 ==
7556 12:47:25.324464 Write leveling (Byte 0): 35 => 35
7557 12:47:25.328186 Write leveling (Byte 1): 28 => 28
7558 12:47:25.330953 DramcWriteLeveling(PI) end<-----
7559 12:47:25.331069
7560 12:47:25.331176 ==
7561 12:47:25.334515 Dram Type= 6, Freq= 0, CH_0, rank 0
7562 12:47:25.337757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7563 12:47:25.337877 ==
7564 12:47:25.341104 [Gating] SW mode calibration
7565 12:47:25.347538 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7566 12:47:25.354278 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7567 12:47:25.357527 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 12:47:25.361200 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 12:47:25.367241 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 12:47:25.370530 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 12:47:25.373745 1 4 16 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
7572 12:47:25.380396 1 4 20 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
7573 12:47:25.383959 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7574 12:47:25.387180 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7575 12:47:25.394235 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7576 12:47:25.397452 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7577 12:47:25.400345 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7578 12:47:25.403679 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7579 12:47:25.410405 1 5 16 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
7580 12:47:25.413464 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 0) (1 0)
7581 12:47:25.416805 1 5 24 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
7582 12:47:25.423918 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 12:47:25.427087 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 12:47:25.430251 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 12:47:25.436816 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 12:47:25.440022 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7587 12:47:25.443334 1 6 16 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7588 12:47:25.450131 1 6 20 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7589 12:47:25.453651 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7590 12:47:25.456444 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 12:47:25.463511 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 12:47:25.466352 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7593 12:47:25.469807 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7594 12:47:25.476351 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7595 12:47:25.479838 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7596 12:47:25.483119 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7597 12:47:25.489508 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7598 12:47:25.493420 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 12:47:25.496308 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 12:47:25.503214 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 12:47:25.506526 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 12:47:25.509530 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 12:47:25.516188 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 12:47:25.519672 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 12:47:25.522884 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 12:47:25.529557 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 12:47:25.533203 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 12:47:25.536054 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 12:47:25.542796 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 12:47:25.546054 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7611 12:47:25.549303 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7612 12:47:25.555882 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7613 12:47:25.555965 Total UI for P1: 0, mck2ui 16
7614 12:47:25.562791 best dqsien dly found for B0: ( 1, 9, 14)
7615 12:47:25.566452 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 12:47:25.569247 Total UI for P1: 0, mck2ui 16
7617 12:47:25.572777 best dqsien dly found for B1: ( 1, 9, 20)
7618 12:47:25.576033 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7619 12:47:25.579547 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7620 12:47:25.579629
7621 12:47:25.582635 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7622 12:47:25.585660 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7623 12:47:25.589074 [Gating] SW calibration Done
7624 12:47:25.589159 ==
7625 12:47:25.592554 Dram Type= 6, Freq= 0, CH_0, rank 0
7626 12:47:25.595605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7627 12:47:25.599096 ==
7628 12:47:25.599222 RX Vref Scan: 0
7629 12:47:25.599318
7630 12:47:25.602540 RX Vref 0 -> 0, step: 1
7631 12:47:25.602617
7632 12:47:25.606023 RX Delay 0 -> 252, step: 8
7633 12:47:25.608906 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7634 12:47:25.612299 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7635 12:47:25.615840 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7636 12:47:25.619604 iDelay=200, Bit 3, Center 119 (64 ~ 175) 112
7637 12:47:25.625472 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7638 12:47:25.629136 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7639 12:47:25.632102 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7640 12:47:25.635463 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7641 12:47:25.639008 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7642 12:47:25.645334 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7643 12:47:25.648775 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7644 12:47:25.652090 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7645 12:47:25.655453 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7646 12:47:25.658934 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
7647 12:47:25.665321 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7648 12:47:25.669077 iDelay=200, Bit 15, Center 127 (72 ~ 183) 112
7649 12:47:25.669163 ==
7650 12:47:25.671929 Dram Type= 6, Freq= 0, CH_0, rank 0
7651 12:47:25.675154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7652 12:47:25.675239 ==
7653 12:47:25.678546 DQS Delay:
7654 12:47:25.678630 DQS0 = 0, DQS1 = 0
7655 12:47:25.678715 DQM Delay:
7656 12:47:25.681842 DQM0 = 128, DQM1 = 123
7657 12:47:25.681926 DQ Delay:
7658 12:47:25.685266 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7659 12:47:25.688674 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =143
7660 12:47:25.695698 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7661 12:47:25.698372 DQ12 =127, DQ13 =127, DQ14 =135, DQ15 =127
7662 12:47:25.698457
7663 12:47:25.698542
7664 12:47:25.698622 ==
7665 12:47:25.701950 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 12:47:25.705024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 12:47:25.705108 ==
7668 12:47:25.705193
7669 12:47:25.705273
7670 12:47:25.708584 TX Vref Scan disable
7671 12:47:25.708668 == TX Byte 0 ==
7672 12:47:25.715131 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7673 12:47:25.718687 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7674 12:47:25.721479 == TX Byte 1 ==
7675 12:47:25.724932 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7676 12:47:25.728298 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7677 12:47:25.728383 ==
7678 12:47:25.731697 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 12:47:25.735133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7680 12:47:25.735219 ==
7681 12:47:25.749766
7682 12:47:25.753110 TX Vref early break, caculate TX vref
7683 12:47:25.756332 TX Vref=16, minBit 4, minWin=21, winSum=359
7684 12:47:25.759818 TX Vref=18, minBit 8, minWin=22, winSum=367
7685 12:47:25.763257 TX Vref=20, minBit 0, minWin=23, winSum=379
7686 12:47:25.766740 TX Vref=22, minBit 8, minWin=23, winSum=388
7687 12:47:25.770053 TX Vref=24, minBit 8, minWin=24, winSum=398
7688 12:47:25.776318 TX Vref=26, minBit 4, minWin=23, winSum=405
7689 12:47:25.779627 TX Vref=28, minBit 9, minWin=23, winSum=405
7690 12:47:25.783043 TX Vref=30, minBit 8, minWin=24, winSum=399
7691 12:47:25.786615 TX Vref=32, minBit 9, minWin=22, winSum=386
7692 12:47:25.790043 TX Vref=34, minBit 8, minWin=23, winSum=383
7693 12:47:25.796236 [TxChooseVref] Worse bit 8, Min win 24, Win sum 399, Final Vref 30
7694 12:47:25.796341
7695 12:47:25.799736 Final TX Range 0 Vref 30
7696 12:47:25.799829
7697 12:47:25.799914 ==
7698 12:47:25.803159 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 12:47:25.806279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 12:47:25.806370 ==
7701 12:47:25.806456
7702 12:47:25.806536
7703 12:47:25.809513 TX Vref Scan disable
7704 12:47:25.816509 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7705 12:47:25.816614 == TX Byte 0 ==
7706 12:47:25.819524 u2DelayCellOfst[0]=11 cells (3 PI)
7707 12:47:25.822988 u2DelayCellOfst[1]=15 cells (4 PI)
7708 12:47:25.826308 u2DelayCellOfst[2]=11 cells (3 PI)
7709 12:47:25.829938 u2DelayCellOfst[3]=7 cells (2 PI)
7710 12:47:25.832744 u2DelayCellOfst[4]=7 cells (2 PI)
7711 12:47:25.836075 u2DelayCellOfst[5]=0 cells (0 PI)
7712 12:47:25.839481 u2DelayCellOfst[6]=18 cells (5 PI)
7713 12:47:25.839597 u2DelayCellOfst[7]=15 cells (4 PI)
7714 12:47:25.845968 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7715 12:47:25.849610 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7716 12:47:25.853061 == TX Byte 1 ==
7717 12:47:25.853152 u2DelayCellOfst[8]=0 cells (0 PI)
7718 12:47:25.856257 u2DelayCellOfst[9]=0 cells (0 PI)
7719 12:47:25.859562 u2DelayCellOfst[10]=7 cells (2 PI)
7720 12:47:25.862338 u2DelayCellOfst[11]=3 cells (1 PI)
7721 12:47:25.865788 u2DelayCellOfst[12]=11 cells (3 PI)
7722 12:47:25.869138 u2DelayCellOfst[13]=11 cells (3 PI)
7723 12:47:25.872722 u2DelayCellOfst[14]=18 cells (5 PI)
7724 12:47:25.876062 u2DelayCellOfst[15]=11 cells (3 PI)
7725 12:47:25.878934 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7726 12:47:25.885707 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7727 12:47:25.885816 DramC Write-DBI on
7728 12:47:25.885907 ==
7729 12:47:25.889125 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 12:47:25.892383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7731 12:47:25.895678 ==
7732 12:47:25.895771
7733 12:47:25.895858
7734 12:47:25.895939 TX Vref Scan disable
7735 12:47:25.899609 == TX Byte 0 ==
7736 12:47:25.902882 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7737 12:47:25.905915 == TX Byte 1 ==
7738 12:47:25.909326 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7739 12:47:25.912643 DramC Write-DBI off
7740 12:47:25.912731
7741 12:47:25.912816 [DATLAT]
7742 12:47:25.912897 Freq=1600, CH0 RK0
7743 12:47:25.912976
7744 12:47:25.915810 DATLAT Default: 0xf
7745 12:47:25.915904 0, 0xFFFF, sum = 0
7746 12:47:25.919409 1, 0xFFFF, sum = 0
7747 12:47:25.919514 2, 0xFFFF, sum = 0
7748 12:47:25.922986 3, 0xFFFF, sum = 0
7749 12:47:25.926381 4, 0xFFFF, sum = 0
7750 12:47:25.926473 5, 0xFFFF, sum = 0
7751 12:47:25.929525 6, 0xFFFF, sum = 0
7752 12:47:25.929614 7, 0xFFFF, sum = 0
7753 12:47:25.932355 8, 0xFFFF, sum = 0
7754 12:47:25.932442 9, 0xFFFF, sum = 0
7755 12:47:25.935916 10, 0xFFFF, sum = 0
7756 12:47:25.936096 11, 0xFFFF, sum = 0
7757 12:47:25.939565 12, 0xFFFF, sum = 0
7758 12:47:25.939654 13, 0xEFFF, sum = 0
7759 12:47:25.942869 14, 0x0, sum = 1
7760 12:47:25.942956 15, 0x0, sum = 2
7761 12:47:25.945778 16, 0x0, sum = 3
7762 12:47:25.945870 17, 0x0, sum = 4
7763 12:47:25.949156 best_step = 15
7764 12:47:25.949246
7765 12:47:25.949331 ==
7766 12:47:25.952584 Dram Type= 6, Freq= 0, CH_0, rank 0
7767 12:47:25.955741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7768 12:47:25.955835 ==
7769 12:47:25.958916 RX Vref Scan: 1
7770 12:47:25.959002
7771 12:47:25.959087 Set Vref Range= 24 -> 127
7772 12:47:25.959168
7773 12:47:25.962414 RX Vref 24 -> 127, step: 1
7774 12:47:25.962502
7775 12:47:25.965705 RX Delay 11 -> 252, step: 4
7776 12:47:25.965792
7777 12:47:25.969016 Set Vref, RX VrefLevel [Byte0]: 24
7778 12:47:25.971997 [Byte1]: 24
7779 12:47:25.972089
7780 12:47:25.975501 Set Vref, RX VrefLevel [Byte0]: 25
7781 12:47:25.978825 [Byte1]: 25
7782 12:47:25.982300
7783 12:47:25.982391 Set Vref, RX VrefLevel [Byte0]: 26
7784 12:47:25.985616 [Byte1]: 26
7785 12:47:25.989615
7786 12:47:25.989704 Set Vref, RX VrefLevel [Byte0]: 27
7787 12:47:25.992992 [Byte1]: 27
7788 12:47:25.997506
7789 12:47:25.997603 Set Vref, RX VrefLevel [Byte0]: 28
7790 12:47:26.000869 [Byte1]: 28
7791 12:47:26.004903
7792 12:47:26.004997 Set Vref, RX VrefLevel [Byte0]: 29
7793 12:47:26.008542 [Byte1]: 29
7794 12:47:26.012315
7795 12:47:26.012408 Set Vref, RX VrefLevel [Byte0]: 30
7796 12:47:26.015749 [Byte1]: 30
7797 12:47:26.020159
7798 12:47:26.020258 Set Vref, RX VrefLevel [Byte0]: 31
7799 12:47:26.023467 [Byte1]: 31
7800 12:47:26.027918
7801 12:47:26.028020 Set Vref, RX VrefLevel [Byte0]: 32
7802 12:47:26.031624 [Byte1]: 32
7803 12:47:26.035455
7804 12:47:26.035549 Set Vref, RX VrefLevel [Byte0]: 33
7805 12:47:26.038785 [Byte1]: 33
7806 12:47:26.042854
7807 12:47:26.042948 Set Vref, RX VrefLevel [Byte0]: 34
7808 12:47:26.046403 [Byte1]: 34
7809 12:47:26.050324
7810 12:47:26.050416 Set Vref, RX VrefLevel [Byte0]: 35
7811 12:47:26.054033 [Byte1]: 35
7812 12:47:26.058149
7813 12:47:26.058248 Set Vref, RX VrefLevel [Byte0]: 36
7814 12:47:26.061466 [Byte1]: 36
7815 12:47:26.065659
7816 12:47:26.065755 Set Vref, RX VrefLevel [Byte0]: 37
7817 12:47:26.069463 [Byte1]: 37
7818 12:47:26.073623
7819 12:47:26.073726 Set Vref, RX VrefLevel [Byte0]: 38
7820 12:47:26.076655 [Byte1]: 38
7821 12:47:26.080886
7822 12:47:26.080988 Set Vref, RX VrefLevel [Byte0]: 39
7823 12:47:26.084303 [Byte1]: 39
7824 12:47:26.088708
7825 12:47:26.088812 Set Vref, RX VrefLevel [Byte0]: 40
7826 12:47:26.091999 [Byte1]: 40
7827 12:47:26.096017
7828 12:47:26.096115 Set Vref, RX VrefLevel [Byte0]: 41
7829 12:47:26.099441 [Byte1]: 41
7830 12:47:26.103864
7831 12:47:26.103964 Set Vref, RX VrefLevel [Byte0]: 42
7832 12:47:26.107219 [Byte1]: 42
7833 12:47:26.111201
7834 12:47:26.111293 Set Vref, RX VrefLevel [Byte0]: 43
7835 12:47:26.114529 [Byte1]: 43
7836 12:47:26.119107
7837 12:47:26.119197 Set Vref, RX VrefLevel [Byte0]: 44
7838 12:47:26.122636 [Byte1]: 44
7839 12:47:26.127289
7840 12:47:26.127381 Set Vref, RX VrefLevel [Byte0]: 45
7841 12:47:26.129867 [Byte1]: 45
7842 12:47:26.134078
7843 12:47:26.134166 Set Vref, RX VrefLevel [Byte0]: 46
7844 12:47:26.137786 [Byte1]: 46
7845 12:47:26.141927
7846 12:47:26.142016 Set Vref, RX VrefLevel [Byte0]: 47
7847 12:47:26.145402 [Byte1]: 47
7848 12:47:26.149504
7849 12:47:26.149601 Set Vref, RX VrefLevel [Byte0]: 48
7850 12:47:26.152885 [Byte1]: 48
7851 12:47:26.157356
7852 12:47:26.157451 Set Vref, RX VrefLevel [Byte0]: 49
7853 12:47:26.160552 [Byte1]: 49
7854 12:47:26.164828
7855 12:47:26.164917 Set Vref, RX VrefLevel [Byte0]: 50
7856 12:47:26.168415 [Byte1]: 50
7857 12:47:26.172242
7858 12:47:26.172331 Set Vref, RX VrefLevel [Byte0]: 51
7859 12:47:26.175873 [Byte1]: 51
7860 12:47:26.180053
7861 12:47:26.180140 Set Vref, RX VrefLevel [Byte0]: 52
7862 12:47:26.183125 [Byte1]: 52
7863 12:47:26.187624
7864 12:47:26.187717 Set Vref, RX VrefLevel [Byte0]: 53
7865 12:47:26.191081 [Byte1]: 53
7866 12:47:26.195411
7867 12:47:26.195494 Set Vref, RX VrefLevel [Byte0]: 54
7868 12:47:26.198612 [Byte1]: 54
7869 12:47:26.202841
7870 12:47:26.202924 Set Vref, RX VrefLevel [Byte0]: 55
7871 12:47:26.206097 [Byte1]: 55
7872 12:47:26.210413
7873 12:47:26.210494 Set Vref, RX VrefLevel [Byte0]: 56
7874 12:47:26.213785 [Byte1]: 56
7875 12:47:26.218064
7876 12:47:26.218149 Set Vref, RX VrefLevel [Byte0]: 57
7877 12:47:26.221286 [Byte1]: 57
7878 12:47:26.225699
7879 12:47:26.229018 Set Vref, RX VrefLevel [Byte0]: 58
7880 12:47:26.229103 [Byte1]: 58
7881 12:47:26.233018
7882 12:47:26.233100 Set Vref, RX VrefLevel [Byte0]: 59
7883 12:47:26.236357 [Byte1]: 59
7884 12:47:26.240668
7885 12:47:26.240750 Set Vref, RX VrefLevel [Byte0]: 60
7886 12:47:26.244323 [Byte1]: 60
7887 12:47:26.248270
7888 12:47:26.248365 Set Vref, RX VrefLevel [Byte0]: 61
7889 12:47:26.252091 [Byte1]: 61
7890 12:47:26.255884
7891 12:47:26.255969 Set Vref, RX VrefLevel [Byte0]: 62
7892 12:47:26.259164 [Byte1]: 62
7893 12:47:26.263318
7894 12:47:26.263432 Set Vref, RX VrefLevel [Byte0]: 63
7895 12:47:26.266852 [Byte1]: 63
7896 12:47:26.271067
7897 12:47:26.271169 Set Vref, RX VrefLevel [Byte0]: 64
7898 12:47:26.274536 [Byte1]: 64
7899 12:47:26.279069
7900 12:47:26.279171 Set Vref, RX VrefLevel [Byte0]: 65
7901 12:47:26.281854 [Byte1]: 65
7902 12:47:26.286372
7903 12:47:26.286499 Set Vref, RX VrefLevel [Byte0]: 66
7904 12:47:26.289831 [Byte1]: 66
7905 12:47:26.294081
7906 12:47:26.294167 Set Vref, RX VrefLevel [Byte0]: 67
7907 12:47:26.297133 [Byte1]: 67
7908 12:47:26.301642
7909 12:47:26.301727 Set Vref, RX VrefLevel [Byte0]: 68
7910 12:47:26.305125 [Byte1]: 68
7911 12:47:26.309205
7912 12:47:26.309311 Set Vref, RX VrefLevel [Byte0]: 69
7913 12:47:26.312778 [Byte1]: 69
7914 12:47:26.316697
7915 12:47:26.316798 Set Vref, RX VrefLevel [Byte0]: 70
7916 12:47:26.320221 [Byte1]: 70
7917 12:47:26.324837
7918 12:47:26.324924 Set Vref, RX VrefLevel [Byte0]: 71
7919 12:47:26.327988 [Byte1]: 71
7920 12:47:26.331893
7921 12:47:26.331996 Set Vref, RX VrefLevel [Byte0]: 72
7922 12:47:26.335723 [Byte1]: 72
7923 12:47:26.339671
7924 12:47:26.339748 Set Vref, RX VrefLevel [Byte0]: 73
7925 12:47:26.343233 [Byte1]: 73
7926 12:47:26.347746
7927 12:47:26.347835 Set Vref, RX VrefLevel [Byte0]: 74
7928 12:47:26.350855 [Byte1]: 74
7929 12:47:26.354848
7930 12:47:26.354935 Set Vref, RX VrefLevel [Byte0]: 75
7931 12:47:26.358259 [Byte1]: 75
7932 12:47:26.362770
7933 12:47:26.362854 Set Vref, RX VrefLevel [Byte0]: 76
7934 12:47:26.366228 [Byte1]: 76
7935 12:47:26.370356
7936 12:47:26.370440 Set Vref, RX VrefLevel [Byte0]: 77
7937 12:47:26.373667 [Byte1]: 77
7938 12:47:26.377894
7939 12:47:26.378001 Set Vref, RX VrefLevel [Byte0]: 78
7940 12:47:26.381699 [Byte1]: 78
7941 12:47:26.385243
7942 12:47:26.385332 Final RX Vref Byte 0 = 64 to rank0
7943 12:47:26.388638 Final RX Vref Byte 1 = 58 to rank0
7944 12:47:26.392235 Final RX Vref Byte 0 = 64 to rank1
7945 12:47:26.395658 Final RX Vref Byte 1 = 58 to rank1==
7946 12:47:26.398833 Dram Type= 6, Freq= 0, CH_0, rank 0
7947 12:47:26.405624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7948 12:47:26.405716 ==
7949 12:47:26.405802 DQS Delay:
7950 12:47:26.408498 DQS0 = 0, DQS1 = 0
7951 12:47:26.408582 DQM Delay:
7952 12:47:26.408664 DQM0 = 126, DQM1 = 120
7953 12:47:26.412094 DQ Delay:
7954 12:47:26.415317 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7955 12:47:26.418532 DQ4 =128, DQ5 =112, DQ6 =134, DQ7 =138
7956 12:47:26.421994 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
7957 12:47:26.424895 DQ12 =126, DQ13 =124, DQ14 =130, DQ15 =128
7958 12:47:26.424982
7959 12:47:26.425063
7960 12:47:26.425142
7961 12:47:26.428278 [DramC_TX_OE_Calibration] TA2
7962 12:47:26.431722 Original DQ_B0 (3 6) =30, OEN = 27
7963 12:47:26.435048 Original DQ_B1 (3 6) =30, OEN = 27
7964 12:47:26.438249 24, 0x0, End_B0=24 End_B1=24
7965 12:47:26.438353 25, 0x0, End_B0=25 End_B1=25
7966 12:47:26.441838 26, 0x0, End_B0=26 End_B1=26
7967 12:47:26.444903 27, 0x0, End_B0=27 End_B1=27
7968 12:47:26.448106 28, 0x0, End_B0=28 End_B1=28
7969 12:47:26.451842 29, 0x0, End_B0=29 End_B1=29
7970 12:47:26.451930 30, 0x0, End_B0=30 End_B1=30
7971 12:47:26.454788 31, 0x4141, End_B0=30 End_B1=30
7972 12:47:26.458087 Byte0 end_step=30 best_step=27
7973 12:47:26.461760 Byte1 end_step=30 best_step=27
7974 12:47:26.464836 Byte0 TX OE(2T, 0.5T) = (3, 3)
7975 12:47:26.468227 Byte1 TX OE(2T, 0.5T) = (3, 3)
7976 12:47:26.468308
7977 12:47:26.468391
7978 12:47:26.475245 [DQSOSCAuto] RK0, (LSB)MR18= 0x1211, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
7979 12:47:26.478176 CH0 RK0: MR19=303, MR18=1211
7980 12:47:26.485109 CH0_RK0: MR19=0x303, MR18=0x1211, DQSOSC=400, MR23=63, INC=23, DEC=15
7981 12:47:26.485193
7982 12:47:26.488231 ----->DramcWriteLeveling(PI) begin...
7983 12:47:26.488315 ==
7984 12:47:26.491617 Dram Type= 6, Freq= 0, CH_0, rank 1
7985 12:47:26.494704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7986 12:47:26.494782 ==
7987 12:47:26.497932 Write leveling (Byte 0): 34 => 34
7988 12:47:26.501476 Write leveling (Byte 1): 28 => 28
7989 12:47:26.504792 DramcWriteLeveling(PI) end<-----
7990 12:47:26.504883
7991 12:47:26.504971 ==
7992 12:47:26.507993 Dram Type= 6, Freq= 0, CH_0, rank 1
7993 12:47:26.510961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7994 12:47:26.511065 ==
7995 12:47:26.514877 [Gating] SW mode calibration
7996 12:47:26.521230 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7997 12:47:26.527796 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7998 12:47:26.531243 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7999 12:47:26.538040 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 12:47:26.541298 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 12:47:26.544664 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8002 12:47:26.551074 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8003 12:47:26.554399 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8004 12:47:26.557596 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8005 12:47:26.564399 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8006 12:47:26.567941 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8007 12:47:26.571165 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8008 12:47:26.574266 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8009 12:47:26.581124 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8010 12:47:26.584232 1 5 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
8011 12:47:26.587281 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 12:47:26.593940 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 12:47:26.597317 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 12:47:26.600886 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 12:47:26.607150 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 12:47:26.610571 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8017 12:47:26.613911 1 6 12 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8018 12:47:26.620862 1 6 16 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
8019 12:47:26.623929 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8020 12:47:26.627099 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 12:47:26.634056 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 12:47:26.637005 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8023 12:47:26.640574 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 12:47:26.646884 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8025 12:47:26.650310 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8026 12:47:26.653712 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8027 12:47:26.660181 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8028 12:47:26.663722 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 12:47:26.666998 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 12:47:26.673539 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 12:47:26.676646 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 12:47:26.680316 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 12:47:26.687077 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 12:47:26.690554 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 12:47:26.693682 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 12:47:26.700209 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 12:47:26.703523 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 12:47:26.706884 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 12:47:26.713725 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 12:47:26.717244 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8041 12:47:26.720422 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8042 12:47:26.723172 Total UI for P1: 0, mck2ui 16
8043 12:47:26.726902 best dqsien dly found for B0: ( 1, 9, 8)
8044 12:47:26.733294 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8045 12:47:26.736422 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 12:47:26.740053 Total UI for P1: 0, mck2ui 16
8047 12:47:26.743511 best dqsien dly found for B1: ( 1, 9, 18)
8048 12:47:26.746286 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8049 12:47:26.749756 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8050 12:47:26.749844
8051 12:47:26.753272 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8052 12:47:26.756255 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8053 12:47:26.760128 [Gating] SW calibration Done
8054 12:47:26.760210 ==
8055 12:47:26.763001 Dram Type= 6, Freq= 0, CH_0, rank 1
8056 12:47:26.766450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8057 12:47:26.766534 ==
8058 12:47:26.770062 RX Vref Scan: 0
8059 12:47:26.770144
8060 12:47:26.773350 RX Vref 0 -> 0, step: 1
8061 12:47:26.773437
8062 12:47:26.773501 RX Delay 0 -> 252, step: 8
8063 12:47:26.779577 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8064 12:47:26.783504 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8065 12:47:26.786372 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8066 12:47:26.789749 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8067 12:47:26.793095 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8068 12:47:26.799448 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8069 12:47:26.802834 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8070 12:47:26.806275 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8071 12:47:26.809649 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8072 12:47:26.812717 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8073 12:47:26.819384 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
8074 12:47:26.822492 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8075 12:47:26.825921 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8076 12:47:26.829185 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8077 12:47:26.835796 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8078 12:47:26.839363 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8079 12:47:26.839509 ==
8080 12:47:26.842514 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 12:47:26.845899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 12:47:26.845988 ==
8083 12:47:26.846053 DQS Delay:
8084 12:47:26.849182 DQS0 = 0, DQS1 = 0
8085 12:47:26.849268 DQM Delay:
8086 12:47:26.852359 DQM0 = 127, DQM1 = 121
8087 12:47:26.852443 DQ Delay:
8088 12:47:26.855785 DQ0 =127, DQ1 =127, DQ2 =123, DQ3 =123
8089 12:47:26.859297 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8090 12:47:26.862649 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
8091 12:47:26.868893 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8092 12:47:26.868998
8093 12:47:26.869062
8094 12:47:26.869121 ==
8095 12:47:26.872254 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 12:47:26.875518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 12:47:26.875633 ==
8098 12:47:26.875724
8099 12:47:26.875791
8100 12:47:26.879062 TX Vref Scan disable
8101 12:47:26.879170 == TX Byte 0 ==
8102 12:47:26.885498 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8103 12:47:26.888566 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8104 12:47:26.888660 == TX Byte 1 ==
8105 12:47:26.895169 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8106 12:47:26.898654 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8107 12:47:26.898757 ==
8108 12:47:26.902041 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 12:47:26.905010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 12:47:26.905127 ==
8111 12:47:26.921263
8112 12:47:26.924426 TX Vref early break, caculate TX vref
8113 12:47:26.927818 TX Vref=16, minBit 8, minWin=21, winSum=364
8114 12:47:26.930684 TX Vref=18, minBit 0, minWin=22, winSum=373
8115 12:47:26.934116 TX Vref=20, minBit 0, minWin=22, winSum=379
8116 12:47:26.937819 TX Vref=22, minBit 1, minWin=23, winSum=388
8117 12:47:26.940944 TX Vref=24, minBit 0, minWin=24, winSum=399
8118 12:47:26.947634 TX Vref=26, minBit 0, minWin=25, winSum=405
8119 12:47:26.950927 TX Vref=28, minBit 0, minWin=25, winSum=408
8120 12:47:26.954686 TX Vref=30, minBit 9, minWin=23, winSum=405
8121 12:47:26.957523 TX Vref=32, minBit 4, minWin=24, winSum=398
8122 12:47:26.960868 TX Vref=34, minBit 8, minWin=22, winSum=391
8123 12:47:26.964186 TX Vref=36, minBit 8, minWin=22, winSum=377
8124 12:47:26.970953 [TxChooseVref] Worse bit 0, Min win 25, Win sum 408, Final Vref 28
8125 12:47:26.971065
8126 12:47:26.973966 Final TX Range 0 Vref 28
8127 12:47:26.974053
8128 12:47:26.974117 ==
8129 12:47:26.977398 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 12:47:26.980873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 12:47:26.980963 ==
8132 12:47:26.981092
8133 12:47:26.981170
8134 12:47:26.984129 TX Vref Scan disable
8135 12:47:26.991138 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8136 12:47:26.991265 == TX Byte 0 ==
8137 12:47:26.994087 u2DelayCellOfst[0]=11 cells (3 PI)
8138 12:47:26.997584 u2DelayCellOfst[1]=18 cells (5 PI)
8139 12:47:27.000673 u2DelayCellOfst[2]=11 cells (3 PI)
8140 12:47:27.004527 u2DelayCellOfst[3]=11 cells (3 PI)
8141 12:47:27.007606 u2DelayCellOfst[4]=7 cells (2 PI)
8142 12:47:27.010690 u2DelayCellOfst[5]=0 cells (0 PI)
8143 12:47:27.014025 u2DelayCellOfst[6]=18 cells (5 PI)
8144 12:47:27.017172 u2DelayCellOfst[7]=18 cells (5 PI)
8145 12:47:27.020567 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8146 12:47:27.024161 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8147 12:47:27.027093 == TX Byte 1 ==
8148 12:47:27.030798 u2DelayCellOfst[8]=0 cells (0 PI)
8149 12:47:27.033905 u2DelayCellOfst[9]=3 cells (1 PI)
8150 12:47:27.033992 u2DelayCellOfst[10]=7 cells (2 PI)
8151 12:47:27.037511 u2DelayCellOfst[11]=7 cells (2 PI)
8152 12:47:27.040629 u2DelayCellOfst[12]=15 cells (4 PI)
8153 12:47:27.043987 u2DelayCellOfst[13]=11 cells (3 PI)
8154 12:47:27.047873 u2DelayCellOfst[14]=15 cells (4 PI)
8155 12:47:27.050514 u2DelayCellOfst[15]=15 cells (4 PI)
8156 12:47:27.057115 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8157 12:47:27.060634 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8158 12:47:27.060726 DramC Write-DBI on
8159 12:47:27.060792 ==
8160 12:47:27.063895 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 12:47:27.070097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 12:47:27.070203 ==
8163 12:47:27.070270
8164 12:47:27.070328
8165 12:47:27.070385 TX Vref Scan disable
8166 12:47:27.074555 == TX Byte 0 ==
8167 12:47:27.077995 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8168 12:47:27.080788 == TX Byte 1 ==
8169 12:47:27.084151 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8170 12:47:27.087608 DramC Write-DBI off
8171 12:47:27.087720
8172 12:47:27.087794 [DATLAT]
8173 12:47:27.087854 Freq=1600, CH0 RK1
8174 12:47:27.087912
8175 12:47:27.091244 DATLAT Default: 0xf
8176 12:47:27.091333 0, 0xFFFF, sum = 0
8177 12:47:27.094254 1, 0xFFFF, sum = 0
8178 12:47:27.097649 2, 0xFFFF, sum = 0
8179 12:47:27.097767 3, 0xFFFF, sum = 0
8180 12:47:27.101143 4, 0xFFFF, sum = 0
8181 12:47:27.101237 5, 0xFFFF, sum = 0
8182 12:47:27.104756 6, 0xFFFF, sum = 0
8183 12:47:27.104853 7, 0xFFFF, sum = 0
8184 12:47:27.107436 8, 0xFFFF, sum = 0
8185 12:47:27.107550 9, 0xFFFF, sum = 0
8186 12:47:27.110930 10, 0xFFFF, sum = 0
8187 12:47:27.111046 11, 0xFFFF, sum = 0
8188 12:47:27.114000 12, 0xFFFF, sum = 0
8189 12:47:27.114115 13, 0xCFFF, sum = 0
8190 12:47:27.117324 14, 0x0, sum = 1
8191 12:47:27.117442 15, 0x0, sum = 2
8192 12:47:27.120662 16, 0x0, sum = 3
8193 12:47:27.120777 17, 0x0, sum = 4
8194 12:47:27.124198 best_step = 15
8195 12:47:27.124308
8196 12:47:27.124402 ==
8197 12:47:27.127426 Dram Type= 6, Freq= 0, CH_0, rank 1
8198 12:47:27.130899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8199 12:47:27.130993 ==
8200 12:47:27.133881 RX Vref Scan: 0
8201 12:47:27.133968
8202 12:47:27.134033 RX Vref 0 -> 0, step: 1
8203 12:47:27.134095
8204 12:47:27.137341 RX Delay 3 -> 252, step: 4
8205 12:47:27.140620 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8206 12:47:27.147204 iDelay=191, Bit 1, Center 126 (75 ~ 178) 104
8207 12:47:27.150646 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8208 12:47:27.154111 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8209 12:47:27.157518 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8210 12:47:27.160526 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8211 12:47:27.167257 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8212 12:47:27.170710 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8213 12:47:27.174347 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8214 12:47:27.177139 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8215 12:47:27.180661 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8216 12:47:27.186820 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8217 12:47:27.190343 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8218 12:47:27.193688 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8219 12:47:27.196728 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8220 12:47:27.203900 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8221 12:47:27.204000 ==
8222 12:47:27.207066 Dram Type= 6, Freq= 0, CH_0, rank 1
8223 12:47:27.210587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 12:47:27.210671 ==
8225 12:47:27.210736 DQS Delay:
8226 12:47:27.213445 DQS0 = 0, DQS1 = 0
8227 12:47:27.213526 DQM Delay:
8228 12:47:27.216987 DQM0 = 124, DQM1 = 118
8229 12:47:27.217070 DQ Delay:
8230 12:47:27.220339 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8231 12:47:27.223218 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8232 12:47:27.226887 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8233 12:47:27.230228 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8234 12:47:27.230310
8235 12:47:27.230388
8236 12:47:27.230461
8237 12:47:27.233406 [DramC_TX_OE_Calibration] TA2
8238 12:47:27.237350 Original DQ_B0 (3 6) =30, OEN = 27
8239 12:47:27.239959 Original DQ_B1 (3 6) =30, OEN = 27
8240 12:47:27.243857 24, 0x0, End_B0=24 End_B1=24
8241 12:47:27.246505 25, 0x0, End_B0=25 End_B1=25
8242 12:47:27.250010 26, 0x0, End_B0=26 End_B1=26
8243 12:47:27.250096 27, 0x0, End_B0=27 End_B1=27
8244 12:47:27.253655 28, 0x0, End_B0=28 End_B1=28
8245 12:47:27.256495 29, 0x0, End_B0=29 End_B1=29
8246 12:47:27.259700 30, 0x0, End_B0=30 End_B1=30
8247 12:47:27.259792 31, 0x4141, End_B0=30 End_B1=30
8248 12:47:27.263259 Byte0 end_step=30 best_step=27
8249 12:47:27.266379 Byte1 end_step=30 best_step=27
8250 12:47:27.270394 Byte0 TX OE(2T, 0.5T) = (3, 3)
8251 12:47:27.273593 Byte1 TX OE(2T, 0.5T) = (3, 3)
8252 12:47:27.273677
8253 12:47:27.273740
8254 12:47:27.280106 [DQSOSCAuto] RK1, (LSB)MR18= 0x2513, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8255 12:47:27.283046 CH0 RK1: MR19=303, MR18=2513
8256 12:47:27.290061 CH0_RK1: MR19=0x303, MR18=0x2513, DQSOSC=391, MR23=63, INC=24, DEC=16
8257 12:47:27.293340 [RxdqsGatingPostProcess] freq 1600
8258 12:47:27.300365 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8259 12:47:27.300462 best DQS0 dly(2T, 0.5T) = (1, 1)
8260 12:47:27.303228 best DQS1 dly(2T, 0.5T) = (1, 1)
8261 12:47:27.306821 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8262 12:47:27.309981 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8263 12:47:27.313193 best DQS0 dly(2T, 0.5T) = (1, 1)
8264 12:47:27.316569 best DQS1 dly(2T, 0.5T) = (1, 1)
8265 12:47:27.319601 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8266 12:47:27.323066 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8267 12:47:27.326508 Pre-setting of DQS Precalculation
8268 12:47:27.329432 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8269 12:47:27.332866 ==
8270 12:47:27.332977 Dram Type= 6, Freq= 0, CH_1, rank 0
8271 12:47:27.340005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8272 12:47:27.340130 ==
8273 12:47:27.343242 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8274 12:47:27.349508 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8275 12:47:27.353594 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8276 12:47:27.359347 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8277 12:47:27.367510 [CA 0] Center 42 (13~71) winsize 59
8278 12:47:27.371052 [CA 1] Center 42 (13~72) winsize 60
8279 12:47:27.373926 [CA 2] Center 38 (9~67) winsize 59
8280 12:47:27.377406 [CA 3] Center 37 (8~66) winsize 59
8281 12:47:27.380738 [CA 4] Center 37 (8~67) winsize 60
8282 12:47:27.383855 [CA 5] Center 36 (7~66) winsize 60
8283 12:47:27.383939
8284 12:47:27.387225 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8285 12:47:27.387312
8286 12:47:27.390867 [CATrainingPosCal] consider 1 rank data
8287 12:47:27.394099 u2DelayCellTimex100 = 258/100 ps
8288 12:47:27.397496 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8289 12:47:27.403846 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8290 12:47:27.407480 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8291 12:47:27.411350 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8292 12:47:27.413959 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8293 12:47:27.417351 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8294 12:47:27.417461
8295 12:47:27.420703 CA PerBit enable=1, Macro0, CA PI delay=36
8296 12:47:27.420795
8297 12:47:27.423876 [CBTSetCACLKResult] CA Dly = 36
8298 12:47:27.427701 CS Dly: 9 (0~40)
8299 12:47:27.430659 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8300 12:47:27.434089 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8301 12:47:27.434170 ==
8302 12:47:27.437549 Dram Type= 6, Freq= 0, CH_1, rank 1
8303 12:47:27.440531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 12:47:27.440613 ==
8305 12:47:27.447298 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8306 12:47:27.450994 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8307 12:47:27.456872 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8308 12:47:27.460665 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8309 12:47:27.470611 [CA 0] Center 41 (12~71) winsize 60
8310 12:47:27.473963 [CA 1] Center 42 (12~72) winsize 61
8311 12:47:27.477265 [CA 2] Center 37 (8~67) winsize 60
8312 12:47:27.480648 [CA 3] Center 36 (7~66) winsize 60
8313 12:47:27.483624 [CA 4] Center 37 (8~67) winsize 60
8314 12:47:27.486911 [CA 5] Center 36 (6~66) winsize 61
8315 12:47:27.486990
8316 12:47:27.490063 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8317 12:47:27.490164
8318 12:47:27.493705 [CATrainingPosCal] consider 2 rank data
8319 12:47:27.497145 u2DelayCellTimex100 = 258/100 ps
8320 12:47:27.503762 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8321 12:47:27.507127 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8322 12:47:27.510041 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8323 12:47:27.513570 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8324 12:47:27.517048 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8325 12:47:27.520447 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8326 12:47:27.520528
8327 12:47:27.523958 CA PerBit enable=1, Macro0, CA PI delay=36
8328 12:47:27.524039
8329 12:47:27.526955 [CBTSetCACLKResult] CA Dly = 36
8330 12:47:27.529928 CS Dly: 10 (0~43)
8331 12:47:27.533511 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8332 12:47:27.536667 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8333 12:47:27.536776
8334 12:47:27.539927 ----->DramcWriteLeveling(PI) begin...
8335 12:47:27.540011 ==
8336 12:47:27.543320 Dram Type= 6, Freq= 0, CH_1, rank 0
8337 12:47:27.549947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 12:47:27.550030 ==
8339 12:47:27.553268 Write leveling (Byte 0): 24 => 24
8340 12:47:27.553350 Write leveling (Byte 1): 27 => 27
8341 12:47:27.556697 DramcWriteLeveling(PI) end<-----
8342 12:47:27.556777
8343 12:47:27.560448 ==
8344 12:47:27.560529 Dram Type= 6, Freq= 0, CH_1, rank 0
8345 12:47:27.566607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8346 12:47:27.566691 ==
8347 12:47:27.569882 [Gating] SW mode calibration
8348 12:47:27.576315 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8349 12:47:27.579807 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8350 12:47:27.586635 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 12:47:27.589758 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 12:47:27.592884 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 12:47:27.599977 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 12:47:27.603023 1 4 16 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8355 12:47:27.606235 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8356 12:47:27.613176 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8357 12:47:27.616275 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8358 12:47:27.619216 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8359 12:47:27.626452 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 12:47:27.629314 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 12:47:27.632840 1 5 12 | B1->B0 | 3434 3232 | 0 1 | (0 1) (1 0)
8362 12:47:27.639368 1 5 16 | B1->B0 | 2727 2525 | 0 0 | (1 0) (0 0)
8363 12:47:27.642829 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 12:47:27.645844 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 12:47:27.652811 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 12:47:27.656185 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 12:47:27.659461 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 12:47:27.666040 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 12:47:27.669656 1 6 12 | B1->B0 | 2929 2524 | 0 1 | (0 0) (0 0)
8370 12:47:27.672410 1 6 16 | B1->B0 | 4242 4141 | 0 0 | (0 0) (0 0)
8371 12:47:27.675787 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 12:47:27.682528 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 12:47:27.686303 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 12:47:27.689293 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 12:47:27.696235 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 12:47:27.698945 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 12:47:27.702623 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 12:47:27.709091 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8379 12:47:27.712287 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8380 12:47:27.715731 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 12:47:27.722610 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 12:47:27.725931 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 12:47:27.728820 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 12:47:27.735634 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 12:47:27.739195 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 12:47:27.742598 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 12:47:27.749164 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 12:47:27.752354 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 12:47:27.755773 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 12:47:27.762189 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 12:47:27.765429 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 12:47:27.768842 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 12:47:27.775401 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 12:47:27.778892 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8395 12:47:27.782297 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 12:47:27.785499 Total UI for P1: 0, mck2ui 16
8397 12:47:27.788617 best dqsien dly found for B0: ( 1, 9, 16)
8398 12:47:27.791806 Total UI for P1: 0, mck2ui 16
8399 12:47:27.795517 best dqsien dly found for B1: ( 1, 9, 16)
8400 12:47:27.798589 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8401 12:47:27.801798 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8402 12:47:27.801879
8403 12:47:27.808964 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8404 12:47:27.811911 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8405 12:47:27.814951 [Gating] SW calibration Done
8406 12:47:27.815050 ==
8407 12:47:27.818739 Dram Type= 6, Freq= 0, CH_1, rank 0
8408 12:47:27.821677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8409 12:47:27.821783 ==
8410 12:47:27.821872 RX Vref Scan: 0
8411 12:47:27.821959
8412 12:47:27.825116 RX Vref 0 -> 0, step: 1
8413 12:47:27.825220
8414 12:47:27.828617 RX Delay 0 -> 252, step: 8
8415 12:47:27.831867 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8416 12:47:27.834944 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8417 12:47:27.842127 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8418 12:47:27.845109 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8419 12:47:27.847942 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8420 12:47:27.851570 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8421 12:47:27.854815 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8422 12:47:27.861332 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8423 12:47:27.864635 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8424 12:47:27.867862 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8425 12:47:27.871160 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8426 12:47:27.874590 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8427 12:47:27.881612 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8428 12:47:27.884642 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8429 12:47:27.887981 iDelay=200, Bit 14, Center 131 (80 ~ 183) 104
8430 12:47:27.891064 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8431 12:47:27.891176 ==
8432 12:47:27.894328 Dram Type= 6, Freq= 0, CH_1, rank 0
8433 12:47:27.901079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8434 12:47:27.901258 ==
8435 12:47:27.901400 DQS Delay:
8436 12:47:27.901557 DQS0 = 0, DQS1 = 0
8437 12:47:27.904288 DQM Delay:
8438 12:47:27.904392 DQM0 = 132, DQM1 = 126
8439 12:47:27.907680 DQ Delay:
8440 12:47:27.910726 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8441 12:47:27.914153 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8442 12:47:27.917749 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119
8443 12:47:27.921016 DQ12 =135, DQ13 =135, DQ14 =131, DQ15 =135
8444 12:47:27.921136
8445 12:47:27.921242
8446 12:47:27.921341 ==
8447 12:47:27.924023 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 12:47:27.927781 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 12:47:27.930638 ==
8450 12:47:27.930789
8451 12:47:27.930889
8452 12:47:27.930985 TX Vref Scan disable
8453 12:47:27.933926 == TX Byte 0 ==
8454 12:47:27.937334 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8455 12:47:27.940711 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8456 12:47:27.943881 == TX Byte 1 ==
8457 12:47:27.947782 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8458 12:47:27.950577 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8459 12:47:27.953946 ==
8460 12:47:27.954045 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 12:47:27.960823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 12:47:27.960930 ==
8463 12:47:27.973643
8464 12:47:27.977042 TX Vref early break, caculate TX vref
8465 12:47:27.980439 TX Vref=16, minBit 11, minWin=21, winSum=363
8466 12:47:27.983591 TX Vref=18, minBit 1, minWin=22, winSum=374
8467 12:47:27.986839 TX Vref=20, minBit 8, minWin=23, winSum=386
8468 12:47:27.990431 TX Vref=22, minBit 10, minWin=23, winSum=393
8469 12:47:27.993386 TX Vref=24, minBit 13, minWin=24, winSum=405
8470 12:47:28.000189 TX Vref=26, minBit 1, minWin=25, winSum=413
8471 12:47:28.003100 TX Vref=28, minBit 1, minWin=25, winSum=418
8472 12:47:28.006888 TX Vref=30, minBit 1, minWin=25, winSum=417
8473 12:47:28.010338 TX Vref=32, minBit 0, minWin=24, winSum=412
8474 12:47:28.013490 TX Vref=34, minBit 0, minWin=24, winSum=400
8475 12:47:28.020207 TX Vref=36, minBit 0, minWin=23, winSum=384
8476 12:47:28.023485 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 28
8477 12:47:28.023591
8478 12:47:28.026821 Final TX Range 0 Vref 28
8479 12:47:28.026928
8480 12:47:28.026996 ==
8481 12:47:28.029971 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 12:47:28.033482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 12:47:28.033577 ==
8484 12:47:28.036788
8485 12:47:28.036911
8486 12:47:28.037014 TX Vref Scan disable
8487 12:47:28.043020 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8488 12:47:28.043130 == TX Byte 0 ==
8489 12:47:28.046847 u2DelayCellOfst[0]=18 cells (5 PI)
8490 12:47:28.050030 u2DelayCellOfst[1]=15 cells (4 PI)
8491 12:47:28.053164 u2DelayCellOfst[2]=0 cells (0 PI)
8492 12:47:28.056677 u2DelayCellOfst[3]=7 cells (2 PI)
8493 12:47:28.059624 u2DelayCellOfst[4]=7 cells (2 PI)
8494 12:47:28.063413 u2DelayCellOfst[5]=22 cells (6 PI)
8495 12:47:28.066389 u2DelayCellOfst[6]=18 cells (5 PI)
8496 12:47:28.069906 u2DelayCellOfst[7]=3 cells (1 PI)
8497 12:47:28.073080 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8498 12:47:28.076166 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8499 12:47:28.079801 == TX Byte 1 ==
8500 12:47:28.083088 u2DelayCellOfst[8]=0 cells (0 PI)
8501 12:47:28.086238 u2DelayCellOfst[9]=11 cells (3 PI)
8502 12:47:28.090020 u2DelayCellOfst[10]=15 cells (4 PI)
8503 12:47:28.090143 u2DelayCellOfst[11]=11 cells (3 PI)
8504 12:47:28.093086 u2DelayCellOfst[12]=18 cells (5 PI)
8505 12:47:28.096697 u2DelayCellOfst[13]=22 cells (6 PI)
8506 12:47:28.099894 u2DelayCellOfst[14]=22 cells (6 PI)
8507 12:47:28.102951 u2DelayCellOfst[15]=22 cells (6 PI)
8508 12:47:28.110015 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8509 12:47:28.113025 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8510 12:47:28.113146 DramC Write-DBI on
8511 12:47:28.113238 ==
8512 12:47:28.116673 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 12:47:28.122898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 12:47:28.123036 ==
8515 12:47:28.123134
8516 12:47:28.123233
8517 12:47:28.123328 TX Vref Scan disable
8518 12:47:28.127749 == TX Byte 0 ==
8519 12:47:28.130409 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8520 12:47:28.133599 == TX Byte 1 ==
8521 12:47:28.137286 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8522 12:47:28.140554 DramC Write-DBI off
8523 12:47:28.140676
8524 12:47:28.140747 [DATLAT]
8525 12:47:28.140809 Freq=1600, CH1 RK0
8526 12:47:28.140870
8527 12:47:28.144012 DATLAT Default: 0xf
8528 12:47:28.144128 0, 0xFFFF, sum = 0
8529 12:47:28.146807 1, 0xFFFF, sum = 0
8530 12:47:28.150241 2, 0xFFFF, sum = 0
8531 12:47:28.150366 3, 0xFFFF, sum = 0
8532 12:47:28.153659 4, 0xFFFF, sum = 0
8533 12:47:28.153774 5, 0xFFFF, sum = 0
8534 12:47:28.156841 6, 0xFFFF, sum = 0
8535 12:47:28.156958 7, 0xFFFF, sum = 0
8536 12:47:28.160073 8, 0xFFFF, sum = 0
8537 12:47:28.160160 9, 0xFFFF, sum = 0
8538 12:47:28.163620 10, 0xFFFF, sum = 0
8539 12:47:28.163741 11, 0xFFFF, sum = 0
8540 12:47:28.166766 12, 0xFFFF, sum = 0
8541 12:47:28.166875 13, 0x8FFF, sum = 0
8542 12:47:28.170334 14, 0x0, sum = 1
8543 12:47:28.170443 15, 0x0, sum = 2
8544 12:47:28.173412 16, 0x0, sum = 3
8545 12:47:28.173532 17, 0x0, sum = 4
8546 12:47:28.176823 best_step = 15
8547 12:47:28.176938
8548 12:47:28.177039 ==
8549 12:47:28.180263 Dram Type= 6, Freq= 0, CH_1, rank 0
8550 12:47:28.183754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8551 12:47:28.183858 ==
8552 12:47:28.186719 RX Vref Scan: 1
8553 12:47:28.186820
8554 12:47:28.186923 Set Vref Range= 24 -> 127
8555 12:47:28.187022
8556 12:47:28.190253 RX Vref 24 -> 127, step: 1
8557 12:47:28.190356
8558 12:47:28.193158 RX Delay 11 -> 252, step: 4
8559 12:47:28.193258
8560 12:47:28.196797 Set Vref, RX VrefLevel [Byte0]: 24
8561 12:47:28.200003 [Byte1]: 24
8562 12:47:28.200115
8563 12:47:28.203282 Set Vref, RX VrefLevel [Byte0]: 25
8564 12:47:28.206380 [Byte1]: 25
8565 12:47:28.210081
8566 12:47:28.210193 Set Vref, RX VrefLevel [Byte0]: 26
8567 12:47:28.213122 [Byte1]: 26
8568 12:47:28.217532
8569 12:47:28.217649 Set Vref, RX VrefLevel [Byte0]: 27
8570 12:47:28.221295 [Byte1]: 27
8571 12:47:28.225048
8572 12:47:28.225134 Set Vref, RX VrefLevel [Byte0]: 28
8573 12:47:28.228518 [Byte1]: 28
8574 12:47:28.232712
8575 12:47:28.232817 Set Vref, RX VrefLevel [Byte0]: 29
8576 12:47:28.235992 [Byte1]: 29
8577 12:47:28.240393
8578 12:47:28.240500 Set Vref, RX VrefLevel [Byte0]: 30
8579 12:47:28.244025 [Byte1]: 30
8580 12:47:28.247879
8581 12:47:28.247989 Set Vref, RX VrefLevel [Byte0]: 31
8582 12:47:28.251191 [Byte1]: 31
8583 12:47:28.255339
8584 12:47:28.255436 Set Vref, RX VrefLevel [Byte0]: 32
8585 12:47:28.258752 [Byte1]: 32
8586 12:47:28.263143
8587 12:47:28.263252 Set Vref, RX VrefLevel [Byte0]: 33
8588 12:47:28.266337 [Byte1]: 33
8589 12:47:28.270919
8590 12:47:28.271007 Set Vref, RX VrefLevel [Byte0]: 34
8591 12:47:28.274245 [Byte1]: 34
8592 12:47:28.278273
8593 12:47:28.278382 Set Vref, RX VrefLevel [Byte0]: 35
8594 12:47:28.281702 [Byte1]: 35
8595 12:47:28.285862
8596 12:47:28.285976 Set Vref, RX VrefLevel [Byte0]: 36
8597 12:47:28.289404 [Byte1]: 36
8598 12:47:28.293489
8599 12:47:28.293592 Set Vref, RX VrefLevel [Byte0]: 37
8600 12:47:28.296984 [Byte1]: 37
8601 12:47:28.301207
8602 12:47:28.301327 Set Vref, RX VrefLevel [Byte0]: 38
8603 12:47:28.308155 [Byte1]: 38
8604 12:47:28.308254
8605 12:47:28.310940 Set Vref, RX VrefLevel [Byte0]: 39
8606 12:47:28.314612 [Byte1]: 39
8607 12:47:28.314699
8608 12:47:28.317538 Set Vref, RX VrefLevel [Byte0]: 40
8609 12:47:28.320727 [Byte1]: 40
8610 12:47:28.324313
8611 12:47:28.324394 Set Vref, RX VrefLevel [Byte0]: 41
8612 12:47:28.327575 [Byte1]: 41
8613 12:47:28.331602
8614 12:47:28.331704 Set Vref, RX VrefLevel [Byte0]: 42
8615 12:47:28.335352 [Byte1]: 42
8616 12:47:28.339160
8617 12:47:28.339241 Set Vref, RX VrefLevel [Byte0]: 43
8618 12:47:28.342757 [Byte1]: 43
8619 12:47:28.346797
8620 12:47:28.346941 Set Vref, RX VrefLevel [Byte0]: 44
8621 12:47:28.350296 [Byte1]: 44
8622 12:47:28.354928
8623 12:47:28.355041 Set Vref, RX VrefLevel [Byte0]: 45
8624 12:47:28.357819 [Byte1]: 45
8625 12:47:28.362365
8626 12:47:28.362442 Set Vref, RX VrefLevel [Byte0]: 46
8627 12:47:28.365821 [Byte1]: 46
8628 12:47:28.369765
8629 12:47:28.369876 Set Vref, RX VrefLevel [Byte0]: 47
8630 12:47:28.372919 [Byte1]: 47
8631 12:47:28.377511
8632 12:47:28.377626 Set Vref, RX VrefLevel [Byte0]: 48
8633 12:47:28.380970 [Byte1]: 48
8634 12:47:28.384887
8635 12:47:28.384995 Set Vref, RX VrefLevel [Byte0]: 49
8636 12:47:28.388591 [Byte1]: 49
8637 12:47:28.392755
8638 12:47:28.392869 Set Vref, RX VrefLevel [Byte0]: 50
8639 12:47:28.395785 [Byte1]: 50
8640 12:47:28.400227
8641 12:47:28.400348 Set Vref, RX VrefLevel [Byte0]: 51
8642 12:47:28.406801 [Byte1]: 51
8643 12:47:28.406887
8644 12:47:28.410209 Set Vref, RX VrefLevel [Byte0]: 52
8645 12:47:28.413782 [Byte1]: 52
8646 12:47:28.413866
8647 12:47:28.416812 Set Vref, RX VrefLevel [Byte0]: 53
8648 12:47:28.420354 [Byte1]: 53
8649 12:47:28.420444
8650 12:47:28.423619 Set Vref, RX VrefLevel [Byte0]: 54
8651 12:47:28.426947 [Byte1]: 54
8652 12:47:28.430853
8653 12:47:28.430961 Set Vref, RX VrefLevel [Byte0]: 55
8654 12:47:28.433804 [Byte1]: 55
8655 12:47:28.438361
8656 12:47:28.438475 Set Vref, RX VrefLevel [Byte0]: 56
8657 12:47:28.441751 [Byte1]: 56
8658 12:47:28.446396
8659 12:47:28.446505 Set Vref, RX VrefLevel [Byte0]: 57
8660 12:47:28.449041 [Byte1]: 57
8661 12:47:28.453559
8662 12:47:28.453638 Set Vref, RX VrefLevel [Byte0]: 58
8663 12:47:28.456948 [Byte1]: 58
8664 12:47:28.461303
8665 12:47:28.461384 Set Vref, RX VrefLevel [Byte0]: 59
8666 12:47:28.464809 [Byte1]: 59
8667 12:47:28.468631
8668 12:47:28.468742 Set Vref, RX VrefLevel [Byte0]: 60
8669 12:47:28.472248 [Byte1]: 60
8670 12:47:28.476239
8671 12:47:28.476316 Set Vref, RX VrefLevel [Byte0]: 61
8672 12:47:28.479665 [Byte1]: 61
8673 12:47:28.484037
8674 12:47:28.484137 Set Vref, RX VrefLevel [Byte0]: 62
8675 12:47:28.487295 [Byte1]: 62
8676 12:47:28.491833
8677 12:47:28.491912 Set Vref, RX VrefLevel [Byte0]: 63
8678 12:47:28.495102 [Byte1]: 63
8679 12:47:28.499253
8680 12:47:28.499393 Set Vref, RX VrefLevel [Byte0]: 64
8681 12:47:28.502653 [Byte1]: 64
8682 12:47:28.506704
8683 12:47:28.506811 Set Vref, RX VrefLevel [Byte0]: 65
8684 12:47:28.510097 [Byte1]: 65
8685 12:47:28.514334
8686 12:47:28.514411 Set Vref, RX VrefLevel [Byte0]: 66
8687 12:47:28.517833 [Byte1]: 66
8688 12:47:28.521830
8689 12:47:28.521905 Set Vref, RX VrefLevel [Byte0]: 67
8690 12:47:28.525298 [Byte1]: 67
8691 12:47:28.529432
8692 12:47:28.529514 Set Vref, RX VrefLevel [Byte0]: 68
8693 12:47:28.532827 [Byte1]: 68
8694 12:47:28.537331
8695 12:47:28.537430 Set Vref, RX VrefLevel [Byte0]: 69
8696 12:47:28.540276 [Byte1]: 69
8697 12:47:28.545074
8698 12:47:28.545146 Set Vref, RX VrefLevel [Byte0]: 70
8699 12:47:28.548394 [Byte1]: 70
8700 12:47:28.552404
8701 12:47:28.552502 Set Vref, RX VrefLevel [Byte0]: 71
8702 12:47:28.555772 [Byte1]: 71
8703 12:47:28.560152
8704 12:47:28.560266 Set Vref, RX VrefLevel [Byte0]: 72
8705 12:47:28.563334 [Byte1]: 72
8706 12:47:28.567905
8707 12:47:28.567984 Final RX Vref Byte 0 = 56 to rank0
8708 12:47:28.571190 Final RX Vref Byte 1 = 53 to rank0
8709 12:47:28.574276 Final RX Vref Byte 0 = 56 to rank1
8710 12:47:28.577766 Final RX Vref Byte 1 = 53 to rank1==
8711 12:47:28.580828 Dram Type= 6, Freq= 0, CH_1, rank 0
8712 12:47:28.587796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8713 12:47:28.587880 ==
8714 12:47:28.587945 DQS Delay:
8715 12:47:28.588005 DQS0 = 0, DQS1 = 0
8716 12:47:28.590793 DQM Delay:
8717 12:47:28.590926 DQM0 = 131, DQM1 = 123
8718 12:47:28.594236 DQ Delay:
8719 12:47:28.597636 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8720 12:47:28.600991 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8721 12:47:28.604084 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8722 12:47:28.607923 DQ12 =134, DQ13 =132, DQ14 =132, DQ15 =132
8723 12:47:28.608056
8724 12:47:28.608240
8725 12:47:28.608375
8726 12:47:28.610713 [DramC_TX_OE_Calibration] TA2
8727 12:47:28.614120 Original DQ_B0 (3 6) =30, OEN = 27
8728 12:47:28.617532 Original DQ_B1 (3 6) =30, OEN = 27
8729 12:47:28.621011 24, 0x0, End_B0=24 End_B1=24
8730 12:47:28.621143 25, 0x0, End_B0=25 End_B1=25
8731 12:47:28.624519 26, 0x0, End_B0=26 End_B1=26
8732 12:47:28.627268 27, 0x0, End_B0=27 End_B1=27
8733 12:47:28.630778 28, 0x0, End_B0=28 End_B1=28
8734 12:47:28.634088 29, 0x0, End_B0=29 End_B1=29
8735 12:47:28.634225 30, 0x0, End_B0=30 End_B1=30
8736 12:47:28.637485 31, 0x4141, End_B0=30 End_B1=30
8737 12:47:28.641283 Byte0 end_step=30 best_step=27
8738 12:47:28.644482 Byte1 end_step=30 best_step=27
8739 12:47:28.647812 Byte0 TX OE(2T, 0.5T) = (3, 3)
8740 12:47:28.647912 Byte1 TX OE(2T, 0.5T) = (3, 3)
8741 12:47:28.650815
8742 12:47:28.650913
8743 12:47:28.657324 [DQSOSCAuto] RK0, (LSB)MR18= 0xb10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
8744 12:47:28.660820 CH1 RK0: MR19=303, MR18=B10
8745 12:47:28.667238 CH1_RK0: MR19=0x303, MR18=0xB10, DQSOSC=401, MR23=63, INC=22, DEC=15
8746 12:47:28.667367
8747 12:47:28.671267 ----->DramcWriteLeveling(PI) begin...
8748 12:47:28.671398 ==
8749 12:47:28.673770 Dram Type= 6, Freq= 0, CH_1, rank 1
8750 12:47:28.677438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8751 12:47:28.677517 ==
8752 12:47:28.680740 Write leveling (Byte 0): 24 => 24
8753 12:47:28.684043 Write leveling (Byte 1): 26 => 26
8754 12:47:28.687495 DramcWriteLeveling(PI) end<-----
8755 12:47:28.687599
8756 12:47:28.687690 ==
8757 12:47:28.690543 Dram Type= 6, Freq= 0, CH_1, rank 1
8758 12:47:28.693796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8759 12:47:28.693906 ==
8760 12:47:28.697510 [Gating] SW mode calibration
8761 12:47:28.703938 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8762 12:47:28.710262 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8763 12:47:28.714265 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 12:47:28.717049 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 12:47:28.723421 1 4 8 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
8766 12:47:28.727287 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 12:47:28.730770 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 12:47:28.737209 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 12:47:28.740438 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 12:47:28.744027 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 12:47:28.750438 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 12:47:28.753908 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 12:47:28.756847 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
8774 12:47:28.763536 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8775 12:47:28.766945 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 12:47:28.769909 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 12:47:28.776605 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 12:47:28.779789 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 12:47:28.783226 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 12:47:28.790153 1 6 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8781 12:47:28.793904 1 6 8 | B1->B0 | 2828 4444 | 1 0 | (0 0) (0 0)
8782 12:47:28.796793 1 6 12 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
8783 12:47:28.804136 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 12:47:28.806473 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 12:47:28.810175 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 12:47:28.816563 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 12:47:28.819961 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 12:47:28.823315 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 12:47:28.826535 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8790 12:47:28.833056 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8791 12:47:28.836571 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8792 12:47:28.839886 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 12:47:28.846532 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 12:47:28.849663 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 12:47:28.853000 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 12:47:28.859428 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 12:47:28.863081 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 12:47:28.866457 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 12:47:28.872868 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 12:47:28.876057 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 12:47:28.879464 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 12:47:28.885947 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 12:47:28.889386 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 12:47:28.892679 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8805 12:47:28.899448 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8806 12:47:28.903011 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8807 12:47:28.905890 Total UI for P1: 0, mck2ui 16
8808 12:47:28.909242 best dqsien dly found for B0: ( 1, 9, 6)
8809 12:47:28.912482 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 12:47:28.915917 Total UI for P1: 0, mck2ui 16
8811 12:47:28.919392 best dqsien dly found for B1: ( 1, 9, 10)
8812 12:47:28.922645 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8813 12:47:28.925591 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8814 12:47:28.925689
8815 12:47:28.932982 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8816 12:47:28.936085 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8817 12:47:28.939266 [Gating] SW calibration Done
8818 12:47:28.939387 ==
8819 12:47:28.942543 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 12:47:28.946256 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 12:47:28.946368 ==
8822 12:47:28.946469 RX Vref Scan: 0
8823 12:47:28.946564
8824 12:47:28.949100 RX Vref 0 -> 0, step: 1
8825 12:47:28.949203
8826 12:47:28.952782 RX Delay 0 -> 252, step: 8
8827 12:47:28.955876 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8828 12:47:28.959051 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8829 12:47:28.965571 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8830 12:47:28.969056 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8831 12:47:28.972290 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8832 12:47:28.976050 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8833 12:47:28.978809 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8834 12:47:28.982169 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8835 12:47:28.988762 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8836 12:47:28.992265 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8837 12:47:28.995996 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8838 12:47:28.999019 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8839 12:47:29.005630 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8840 12:47:29.008561 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8841 12:47:29.011895 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8842 12:47:29.015329 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8843 12:47:29.015432 ==
8844 12:47:29.018851 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 12:47:29.025166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 12:47:29.025279 ==
8847 12:47:29.025374 DQS Delay:
8848 12:47:29.025464 DQS0 = 0, DQS1 = 0
8849 12:47:29.028329 DQM Delay:
8850 12:47:29.028448 DQM0 = 128, DQM1 = 126
8851 12:47:29.032256 DQ Delay:
8852 12:47:29.035008 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =123
8853 12:47:29.038553 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8854 12:47:29.042213 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8855 12:47:29.045468 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =131
8856 12:47:29.045570
8857 12:47:29.045652
8858 12:47:29.045715 ==
8859 12:47:29.048389 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 12:47:29.051667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 12:47:29.055117 ==
8862 12:47:29.055231
8863 12:47:29.055332
8864 12:47:29.055435 TX Vref Scan disable
8865 12:47:29.058297 == TX Byte 0 ==
8866 12:47:29.061835 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8867 12:47:29.065009 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8868 12:47:29.068374 == TX Byte 1 ==
8869 12:47:29.071650 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8870 12:47:29.075213 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8871 12:47:29.078196 ==
8872 12:47:29.078281 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 12:47:29.084921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 12:47:29.085010 ==
8875 12:47:29.098232
8876 12:47:29.101110 TX Vref early break, caculate TX vref
8877 12:47:29.104645 TX Vref=16, minBit 0, minWin=23, winSum=386
8878 12:47:29.107539 TX Vref=18, minBit 0, minWin=23, winSum=393
8879 12:47:29.111173 TX Vref=20, minBit 0, minWin=25, winSum=405
8880 12:47:29.114497 TX Vref=22, minBit 0, minWin=25, winSum=413
8881 12:47:29.118131 TX Vref=24, minBit 0, minWin=25, winSum=420
8882 12:47:29.124421 TX Vref=26, minBit 0, minWin=25, winSum=428
8883 12:47:29.128254 TX Vref=28, minBit 5, minWin=25, winSum=427
8884 12:47:29.131144 TX Vref=30, minBit 5, minWin=25, winSum=421
8885 12:47:29.134522 TX Vref=32, minBit 6, minWin=24, winSum=418
8886 12:47:29.137577 TX Vref=34, minBit 1, minWin=24, winSum=409
8887 12:47:29.140817 TX Vref=36, minBit 5, minWin=23, winSum=401
8888 12:47:29.147660 [TxChooseVref] Worse bit 0, Min win 25, Win sum 428, Final Vref 26
8889 12:47:29.147751
8890 12:47:29.151207 Final TX Range 0 Vref 26
8891 12:47:29.151320
8892 12:47:29.151431 ==
8893 12:47:29.154518 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 12:47:29.157477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 12:47:29.157579 ==
8896 12:47:29.157681
8897 12:47:29.160920
8898 12:47:29.161027 TX Vref Scan disable
8899 12:47:29.167366 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8900 12:47:29.167460 == TX Byte 0 ==
8901 12:47:29.170964 u2DelayCellOfst[0]=18 cells (5 PI)
8902 12:47:29.174150 u2DelayCellOfst[1]=11 cells (3 PI)
8903 12:47:29.177717 u2DelayCellOfst[2]=0 cells (0 PI)
8904 12:47:29.180868 u2DelayCellOfst[3]=7 cells (2 PI)
8905 12:47:29.184111 u2DelayCellOfst[4]=7 cells (2 PI)
8906 12:47:29.187308 u2DelayCellOfst[5]=18 cells (5 PI)
8907 12:47:29.190386 u2DelayCellOfst[6]=18 cells (5 PI)
8908 12:47:29.193968 u2DelayCellOfst[7]=3 cells (1 PI)
8909 12:47:29.197190 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8910 12:47:29.200627 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8911 12:47:29.204067 == TX Byte 1 ==
8912 12:47:29.207055 u2DelayCellOfst[8]=0 cells (0 PI)
8913 12:47:29.210259 u2DelayCellOfst[9]=7 cells (2 PI)
8914 12:47:29.210369 u2DelayCellOfst[10]=11 cells (3 PI)
8915 12:47:29.213881 u2DelayCellOfst[11]=7 cells (2 PI)
8916 12:47:29.217007 u2DelayCellOfst[12]=15 cells (4 PI)
8917 12:47:29.220410 u2DelayCellOfst[13]=18 cells (5 PI)
8918 12:47:29.223976 u2DelayCellOfst[14]=22 cells (6 PI)
8919 12:47:29.227134 u2DelayCellOfst[15]=18 cells (5 PI)
8920 12:47:29.233556 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8921 12:47:29.237089 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8922 12:47:29.237170 DramC Write-DBI on
8923 12:47:29.237258 ==
8924 12:47:29.240565 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 12:47:29.247291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 12:47:29.247412 ==
8927 12:47:29.247521
8928 12:47:29.247620
8929 12:47:29.247722 TX Vref Scan disable
8930 12:47:29.251138 == TX Byte 0 ==
8931 12:47:29.253987 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8932 12:47:29.257404 == TX Byte 1 ==
8933 12:47:29.260922 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8934 12:47:29.263968 DramC Write-DBI off
8935 12:47:29.264071
8936 12:47:29.264173 [DATLAT]
8937 12:47:29.264255 Freq=1600, CH1 RK1
8938 12:47:29.264333
8939 12:47:29.267795 DATLAT Default: 0xf
8940 12:47:29.267875 0, 0xFFFF, sum = 0
8941 12:47:29.271036 1, 0xFFFF, sum = 0
8942 12:47:29.274154 2, 0xFFFF, sum = 0
8943 12:47:29.274257 3, 0xFFFF, sum = 0
8944 12:47:29.277422 4, 0xFFFF, sum = 0
8945 12:47:29.277501 5, 0xFFFF, sum = 0
8946 12:47:29.281087 6, 0xFFFF, sum = 0
8947 12:47:29.281174 7, 0xFFFF, sum = 0
8948 12:47:29.284557 8, 0xFFFF, sum = 0
8949 12:47:29.284652 9, 0xFFFF, sum = 0
8950 12:47:29.288145 10, 0xFFFF, sum = 0
8951 12:47:29.288233 11, 0xFFFF, sum = 0
8952 12:47:29.291110 12, 0xFFFF, sum = 0
8953 12:47:29.291223 13, 0x8FFF, sum = 0
8954 12:47:29.293868 14, 0x0, sum = 1
8955 12:47:29.293955 15, 0x0, sum = 2
8956 12:47:29.297588 16, 0x0, sum = 3
8957 12:47:29.297677 17, 0x0, sum = 4
8958 12:47:29.300607 best_step = 15
8959 12:47:29.300693
8960 12:47:29.300779 ==
8961 12:47:29.303862 Dram Type= 6, Freq= 0, CH_1, rank 1
8962 12:47:29.307342 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8963 12:47:29.307451 ==
8964 12:47:29.310873 RX Vref Scan: 0
8965 12:47:29.310985
8966 12:47:29.311087 RX Vref 0 -> 0, step: 1
8967 12:47:29.311190
8968 12:47:29.314033 RX Delay 3 -> 252, step: 4
8969 12:47:29.320494 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8970 12:47:29.323842 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8971 12:47:29.327008 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8972 12:47:29.330449 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8973 12:47:29.333891 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8974 12:47:29.337021 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8975 12:47:29.343391 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8976 12:47:29.346868 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
8977 12:47:29.350336 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8978 12:47:29.353462 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
8979 12:47:29.360657 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8980 12:47:29.363995 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
8981 12:47:29.366775 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8982 12:47:29.370227 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
8983 12:47:29.373823 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8984 12:47:29.380167 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8985 12:47:29.380258 ==
8986 12:47:29.383656 Dram Type= 6, Freq= 0, CH_1, rank 1
8987 12:47:29.386886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8988 12:47:29.386995 ==
8989 12:47:29.387102 DQS Delay:
8990 12:47:29.390245 DQS0 = 0, DQS1 = 0
8991 12:47:29.390386 DQM Delay:
8992 12:47:29.393122 DQM0 = 128, DQM1 = 125
8993 12:47:29.393256 DQ Delay:
8994 12:47:29.396698 DQ0 =132, DQ1 =126, DQ2 =116, DQ3 =126
8995 12:47:29.399905 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
8996 12:47:29.403220 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =118
8997 12:47:29.406511 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =132
8998 12:47:29.406655
8999 12:47:29.406787
9000 12:47:29.410271
9001 12:47:29.410386 [DramC_TX_OE_Calibration] TA2
9002 12:47:29.413339 Original DQ_B0 (3 6) =30, OEN = 27
9003 12:47:29.416798 Original DQ_B1 (3 6) =30, OEN = 27
9004 12:47:29.420039 24, 0x0, End_B0=24 End_B1=24
9005 12:47:29.423234 25, 0x0, End_B0=25 End_B1=25
9006 12:47:29.426551 26, 0x0, End_B0=26 End_B1=26
9007 12:47:29.426641 27, 0x0, End_B0=27 End_B1=27
9008 12:47:29.429779 28, 0x0, End_B0=28 End_B1=28
9009 12:47:29.433408 29, 0x0, End_B0=29 End_B1=29
9010 12:47:29.436287 30, 0x0, End_B0=30 End_B1=30
9011 12:47:29.439673 31, 0x4545, End_B0=30 End_B1=30
9012 12:47:29.439766 Byte0 end_step=30 best_step=27
9013 12:47:29.443121 Byte1 end_step=30 best_step=27
9014 12:47:29.446702 Byte0 TX OE(2T, 0.5T) = (3, 3)
9015 12:47:29.450016 Byte1 TX OE(2T, 0.5T) = (3, 3)
9016 12:47:29.450208
9017 12:47:29.450328
9018 12:47:29.456109 [DQSOSCAuto] RK1, (LSB)MR18= 0x131e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
9019 12:47:29.459502 CH1 RK1: MR19=303, MR18=131E
9020 12:47:29.466426 CH1_RK1: MR19=0x303, MR18=0x131E, DQSOSC=394, MR23=63, INC=23, DEC=15
9021 12:47:29.469293 [RxdqsGatingPostProcess] freq 1600
9022 12:47:29.476118 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9023 12:47:29.479387 best DQS0 dly(2T, 0.5T) = (1, 1)
9024 12:47:29.483153 best DQS1 dly(2T, 0.5T) = (1, 1)
9025 12:47:29.483237 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9026 12:47:29.486074 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9027 12:47:29.489257 best DQS0 dly(2T, 0.5T) = (1, 1)
9028 12:47:29.492337 best DQS1 dly(2T, 0.5T) = (1, 1)
9029 12:47:29.496063 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9030 12:47:29.499438 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9031 12:47:29.502889 Pre-setting of DQS Precalculation
9032 12:47:29.509171 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9033 12:47:29.515385 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9034 12:47:29.522231 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9035 12:47:29.522331
9036 12:47:29.522406
9037 12:47:29.525325 [Calibration Summary] 3200 Mbps
9038 12:47:29.525409 CH 0, Rank 0
9039 12:47:29.529240 SW Impedance : PASS
9040 12:47:29.532279 DUTY Scan : NO K
9041 12:47:29.532369 ZQ Calibration : PASS
9042 12:47:29.535614 Jitter Meter : NO K
9043 12:47:29.538740 CBT Training : PASS
9044 12:47:29.538852 Write leveling : PASS
9045 12:47:29.542089 RX DQS gating : PASS
9046 12:47:29.545652 RX DQ/DQS(RDDQC) : PASS
9047 12:47:29.545774 TX DQ/DQS : PASS
9048 12:47:29.548886 RX DATLAT : PASS
9049 12:47:29.548997 RX DQ/DQS(Engine): PASS
9050 12:47:29.552218 TX OE : PASS
9051 12:47:29.552303 All Pass.
9052 12:47:29.552384
9053 12:47:29.555779 CH 0, Rank 1
9054 12:47:29.555914 SW Impedance : PASS
9055 12:47:29.558529 DUTY Scan : NO K
9056 12:47:29.561998 ZQ Calibration : PASS
9057 12:47:29.562130 Jitter Meter : NO K
9058 12:47:29.565431 CBT Training : PASS
9059 12:47:29.568857 Write leveling : PASS
9060 12:47:29.568940 RX DQS gating : PASS
9061 12:47:29.572366 RX DQ/DQS(RDDQC) : PASS
9062 12:47:29.575256 TX DQ/DQS : PASS
9063 12:47:29.575339 RX DATLAT : PASS
9064 12:47:29.578529 RX DQ/DQS(Engine): PASS
9065 12:47:29.582240 TX OE : PASS
9066 12:47:29.582321 All Pass.
9067 12:47:29.582387
9068 12:47:29.582449 CH 1, Rank 0
9069 12:47:29.585357 SW Impedance : PASS
9070 12:47:29.588718 DUTY Scan : NO K
9071 12:47:29.588800 ZQ Calibration : PASS
9072 12:47:29.592210 Jitter Meter : NO K
9073 12:47:29.595053 CBT Training : PASS
9074 12:47:29.595136 Write leveling : PASS
9075 12:47:29.598993 RX DQS gating : PASS
9076 12:47:29.599076 RX DQ/DQS(RDDQC) : PASS
9077 12:47:29.601931 TX DQ/DQS : PASS
9078 12:47:29.605284 RX DATLAT : PASS
9079 12:47:29.605367 RX DQ/DQS(Engine): PASS
9080 12:47:29.608612 TX OE : PASS
9081 12:47:29.608695 All Pass.
9082 12:47:29.608759
9083 12:47:29.611941 CH 1, Rank 1
9084 12:47:29.612024 SW Impedance : PASS
9085 12:47:29.615236 DUTY Scan : NO K
9086 12:47:29.618495 ZQ Calibration : PASS
9087 12:47:29.618581 Jitter Meter : NO K
9088 12:47:29.621943 CBT Training : PASS
9089 12:47:29.625056 Write leveling : PASS
9090 12:47:29.625140 RX DQS gating : PASS
9091 12:47:29.628437 RX DQ/DQS(RDDQC) : PASS
9092 12:47:29.631953 TX DQ/DQS : PASS
9093 12:47:29.632037 RX DATLAT : PASS
9094 12:47:29.635336 RX DQ/DQS(Engine): PASS
9095 12:47:29.638623 TX OE : PASS
9096 12:47:29.638748 All Pass.
9097 12:47:29.638854
9098 12:47:29.638947 DramC Write-DBI on
9099 12:47:29.641899 PER_BANK_REFRESH: Hybrid Mode
9100 12:47:29.644885 TX_TRACKING: ON
9101 12:47:29.652225 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9102 12:47:29.661991 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9103 12:47:29.667991 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9104 12:47:29.671469 [FAST_K] Save calibration result to emmc
9105 12:47:29.675588 sync common calibartion params.
9106 12:47:29.678191 sync cbt_mode0:1, 1:1
9107 12:47:29.678275 dram_init: ddr_geometry: 2
9108 12:47:29.681776 dram_init: ddr_geometry: 2
9109 12:47:29.684915 dram_init: ddr_geometry: 2
9110 12:47:29.684996 0:dram_rank_size:100000000
9111 12:47:29.688456 1:dram_rank_size:100000000
9112 12:47:29.695182 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9113 12:47:29.695268 DFS_SHUFFLE_HW_MODE: ON
9114 12:47:29.701642 dramc_set_vcore_voltage set vcore to 725000
9115 12:47:29.701724 Read voltage for 1600, 0
9116 12:47:29.704885 Vio18 = 0
9117 12:47:29.704968 Vcore = 725000
9118 12:47:29.705031 Vdram = 0
9119 12:47:29.708299 Vddq = 0
9120 12:47:29.708380 Vmddr = 0
9121 12:47:29.711746 switch to 3200 Mbps bootup
9122 12:47:29.711826 [DramcRunTimeConfig]
9123 12:47:29.711917 PHYPLL
9124 12:47:29.714817 DPM_CONTROL_AFTERK: ON
9125 12:47:29.718230 PER_BANK_REFRESH: ON
9126 12:47:29.718311 REFRESH_OVERHEAD_REDUCTION: ON
9127 12:47:29.721487 CMD_PICG_NEW_MODE: OFF
9128 12:47:29.724997 XRTWTW_NEW_MODE: ON
9129 12:47:29.725079 XRTRTR_NEW_MODE: ON
9130 12:47:29.728407 TX_TRACKING: ON
9131 12:47:29.728488 RDSEL_TRACKING: OFF
9132 12:47:29.731664 DQS Precalculation for DVFS: ON
9133 12:47:29.731744 RX_TRACKING: OFF
9134 12:47:29.735200 HW_GATING DBG: ON
9135 12:47:29.735280 ZQCS_ENABLE_LP4: ON
9136 12:47:29.738368 RX_PICG_NEW_MODE: ON
9137 12:47:29.741590 TX_PICG_NEW_MODE: ON
9138 12:47:29.741673 ENABLE_RX_DCM_DPHY: ON
9139 12:47:29.744717 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9140 12:47:29.747930 DUMMY_READ_FOR_TRACKING: OFF
9141 12:47:29.751213 !!! SPM_CONTROL_AFTERK: OFF
9142 12:47:29.751305 !!! SPM could not control APHY
9143 12:47:29.754660 IMPEDANCE_TRACKING: ON
9144 12:47:29.757991 TEMP_SENSOR: ON
9145 12:47:29.758073 HW_SAVE_FOR_SR: OFF
9146 12:47:29.761312 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9147 12:47:29.764725 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9148 12:47:29.767905 Read ODT Tracking: ON
9149 12:47:29.767986 Refresh Rate DeBounce: ON
9150 12:47:29.771023 DFS_NO_QUEUE_FLUSH: ON
9151 12:47:29.774593 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9152 12:47:29.778175 ENABLE_DFS_RUNTIME_MRW: OFF
9153 12:47:29.778256 DDR_RESERVE_NEW_MODE: ON
9154 12:47:29.780993 MR_CBT_SWITCH_FREQ: ON
9155 12:47:29.784465 =========================
9156 12:47:29.802388 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9157 12:47:29.805670 dram_init: ddr_geometry: 2
9158 12:47:29.824047 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9159 12:47:29.827394 dram_init: dram init end (result: 0)
9160 12:47:29.833992 DRAM-K: Full calibration passed in 24556 msecs
9161 12:47:29.837429 MRC: failed to locate region type 0.
9162 12:47:29.837512 DRAM rank0 size:0x100000000,
9163 12:47:29.841066 DRAM rank1 size=0x100000000
9164 12:47:29.851058 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9165 12:47:29.857630 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9166 12:47:29.864332 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9167 12:47:29.870701 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9168 12:47:29.874056 DRAM rank0 size:0x100000000,
9169 12:47:29.877407 DRAM rank1 size=0x100000000
9170 12:47:29.877488 CBMEM:
9171 12:47:29.880484 IMD: root @ 0xfffff000 254 entries.
9172 12:47:29.883836 IMD: root @ 0xffffec00 62 entries.
9173 12:47:29.887209 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9174 12:47:29.890524 WARNING: RO_VPD is uninitialized or empty.
9175 12:47:29.897369 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9176 12:47:29.904129 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9177 12:47:29.917093 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9178 12:47:29.928279 BS: romstage times (exec / console): total (unknown) / 24019 ms
9179 12:47:29.928370
9180 12:47:29.928433
9181 12:47:29.938720 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9182 12:47:29.941486 ARM64: Exception handlers installed.
9183 12:47:29.945378 ARM64: Testing exception
9184 12:47:29.948599 ARM64: Done test exception
9185 12:47:29.948705 Enumerating buses...
9186 12:47:29.951572 Show all devs... Before device enumeration.
9187 12:47:29.955383 Root Device: enabled 1
9188 12:47:29.958136 CPU_CLUSTER: 0: enabled 1
9189 12:47:29.958216 CPU: 00: enabled 1
9190 12:47:29.961822 Compare with tree...
9191 12:47:29.961903 Root Device: enabled 1
9192 12:47:29.965376 CPU_CLUSTER: 0: enabled 1
9193 12:47:29.968301 CPU: 00: enabled 1
9194 12:47:29.968382 Root Device scanning...
9195 12:47:29.972147 scan_static_bus for Root Device
9196 12:47:29.974949 CPU_CLUSTER: 0 enabled
9197 12:47:29.978374 scan_static_bus for Root Device done
9198 12:47:29.981720 scan_bus: bus Root Device finished in 8 msecs
9199 12:47:29.981802 done
9200 12:47:29.987922 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9201 12:47:29.991304 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9202 12:47:29.997840 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9203 12:47:30.001395 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9204 12:47:30.004586 Allocating resources...
9205 12:47:30.007996 Reading resources...
9206 12:47:30.010892 Root Device read_resources bus 0 link: 0
9207 12:47:30.014236 DRAM rank0 size:0x100000000,
9208 12:47:30.014319 DRAM rank1 size=0x100000000
9209 12:47:30.017972 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9210 12:47:30.020765 CPU: 00 missing read_resources
9211 12:47:30.027410 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9212 12:47:30.031078 Root Device read_resources bus 0 link: 0 done
9213 12:47:30.031160 Done reading resources.
9214 12:47:30.037301 Show resources in subtree (Root Device)...After reading.
9215 12:47:30.040689 Root Device child on link 0 CPU_CLUSTER: 0
9216 12:47:30.044068 CPU_CLUSTER: 0 child on link 0 CPU: 00
9217 12:47:30.054198 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9218 12:47:30.054285 CPU: 00
9219 12:47:30.057176 Root Device assign_resources, bus 0 link: 0
9220 12:47:30.060540 CPU_CLUSTER: 0 missing set_resources
9221 12:47:30.067422 Root Device assign_resources, bus 0 link: 0 done
9222 12:47:30.067506 Done setting resources.
9223 12:47:30.073670 Show resources in subtree (Root Device)...After assigning values.
9224 12:47:30.077170 Root Device child on link 0 CPU_CLUSTER: 0
9225 12:47:30.080608 CPU_CLUSTER: 0 child on link 0 CPU: 00
9226 12:47:30.090515 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9227 12:47:30.090599 CPU: 00
9228 12:47:30.093406 Done allocating resources.
9229 12:47:30.100520 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9230 12:47:30.100631 Enabling resources...
9231 12:47:30.100729 done.
9232 12:47:30.106974 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9233 12:47:30.107093 Initializing devices...
9234 12:47:30.110461 Root Device init
9235 12:47:30.113447 init hardware done!
9236 12:47:30.113553 0x00000018: ctrlr->caps
9237 12:47:30.117038 52.000 MHz: ctrlr->f_max
9238 12:47:30.117151 0.400 MHz: ctrlr->f_min
9239 12:47:30.119906 0x40ff8080: ctrlr->voltages
9240 12:47:30.123149 sclk: 390625
9241 12:47:30.123257 Bus Width = 1
9242 12:47:30.123378 sclk: 390625
9243 12:47:30.126594 Bus Width = 1
9244 12:47:30.126698 Early init status = 3
9245 12:47:30.133195 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9246 12:47:30.136489 in-header: 03 fc 00 00 01 00 00 00
9247 12:47:30.140002 in-data: 00
9248 12:47:30.143278 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9249 12:47:30.146937 in-header: 03 fd 00 00 00 00 00 00
9250 12:47:30.150241 in-data:
9251 12:47:30.153183 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9252 12:47:30.156770 in-header: 03 fc 00 00 01 00 00 00
9253 12:47:30.160249 in-data: 00
9254 12:47:30.163712 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9255 12:47:30.168378 in-header: 03 fd 00 00 00 00 00 00
9256 12:47:30.172073 in-data:
9257 12:47:30.175221 [SSUSB] Setting up USB HOST controller...
9258 12:47:30.178724 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9259 12:47:30.181923 [SSUSB] phy power-on done.
9260 12:47:30.185363 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9261 12:47:30.191865 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9262 12:47:30.195202 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9263 12:47:30.201700 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9264 12:47:30.208399 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9265 12:47:30.214905 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9266 12:47:30.222017 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9267 12:47:30.228772 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9268 12:47:30.231708 SPM: binary array size = 0x9dc
9269 12:47:30.235075 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9270 12:47:30.241845 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9271 12:47:30.248756 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9272 12:47:30.251514 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9273 12:47:30.258335 configure_display: Starting display init
9274 12:47:30.292106 anx7625_power_on_init: Init interface.
9275 12:47:30.295059 anx7625_disable_pd_protocol: Disabled PD feature.
9276 12:47:30.298651 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9277 12:47:30.326430 anx7625_start_dp_work: Secure OCM version=00
9278 12:47:30.329708 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9279 12:47:30.344637 sp_tx_get_edid_block: EDID Block = 1
9280 12:47:30.446880 Extracted contents:
9281 12:47:30.450308 header: 00 ff ff ff ff ff ff 00
9282 12:47:30.453628 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9283 12:47:30.457080 version: 01 04
9284 12:47:30.460207 basic params: 95 1f 11 78 0a
9285 12:47:30.463547 chroma info: 76 90 94 55 54 90 27 21 50 54
9286 12:47:30.466987 established: 00 00 00
9287 12:47:30.473268 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9288 12:47:30.479944 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9289 12:47:30.483563 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9290 12:47:30.489428 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9291 12:47:30.496373 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9292 12:47:30.499715 extensions: 00
9293 12:47:30.499826 checksum: fb
9294 12:47:30.499917
9295 12:47:30.506123 Manufacturer: IVO Model 57d Serial Number 0
9296 12:47:30.506232 Made week 0 of 2020
9297 12:47:30.509665 EDID version: 1.4
9298 12:47:30.509749 Digital display
9299 12:47:30.513050 6 bits per primary color channel
9300 12:47:30.513148 DisplayPort interface
9301 12:47:30.516578 Maximum image size: 31 cm x 17 cm
9302 12:47:30.519471 Gamma: 220%
9303 12:47:30.519557 Check DPMS levels
9304 12:47:30.523054 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9305 12:47:30.529299 First detailed timing is preferred timing
9306 12:47:30.529420 Established timings supported:
9307 12:47:30.533298 Standard timings supported:
9308 12:47:30.536252 Detailed timings
9309 12:47:30.539993 Hex of detail: 383680a07038204018303c0035ae10000019
9310 12:47:30.545879 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9311 12:47:30.549491 0780 0798 07c8 0820 hborder 0
9312 12:47:30.553156 0438 043b 0447 0458 vborder 0
9313 12:47:30.555965 -hsync -vsync
9314 12:47:30.556078 Did detailed timing
9315 12:47:30.562600 Hex of detail: 000000000000000000000000000000000000
9316 12:47:30.565874 Manufacturer-specified data, tag 0
9317 12:47:30.569067 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9318 12:47:30.572736 ASCII string: InfoVision
9319 12:47:30.576422 Hex of detail: 000000fe00523134304e574635205248200a
9320 12:47:30.579167 ASCII string: R140NWF5 RH
9321 12:47:30.579284 Checksum
9322 12:47:30.582798 Checksum: 0xfb (valid)
9323 12:47:30.586296 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9324 12:47:30.589220 DSI data_rate: 832800000 bps
9325 12:47:30.595760 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9326 12:47:30.599299 anx7625_parse_edid: pixelclock(138800).
9327 12:47:30.602544 hactive(1920), hsync(48), hfp(24), hbp(88)
9328 12:47:30.605758 vactive(1080), vsync(12), vfp(3), vbp(17)
9329 12:47:30.609344 anx7625_dsi_config: config dsi.
9330 12:47:30.615720 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9331 12:47:30.629044 anx7625_dsi_config: success to config DSI
9332 12:47:30.632361 anx7625_dp_start: MIPI phy setup OK.
9333 12:47:30.635805 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9334 12:47:30.639306 mtk_ddp_mode_set invalid vrefresh 60
9335 12:47:30.642371 main_disp_path_setup
9336 12:47:30.642454 ovl_layer_smi_id_en
9337 12:47:30.645428 ovl_layer_smi_id_en
9338 12:47:30.645510 ccorr_config
9339 12:47:30.645574 aal_config
9340 12:47:30.649142 gamma_config
9341 12:47:30.649251 postmask_config
9342 12:47:30.652114 dither_config
9343 12:47:30.655390 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9344 12:47:30.661943 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9345 12:47:30.665675 Root Device init finished in 551 msecs
9346 12:47:30.668563 CPU_CLUSTER: 0 init
9347 12:47:30.675598 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9348 12:47:30.678597 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9349 12:47:30.682055 APU_MBOX 0x190000b0 = 0x10001
9350 12:47:30.685435 APU_MBOX 0x190001b0 = 0x10001
9351 12:47:30.688894 APU_MBOX 0x190005b0 = 0x10001
9352 12:47:30.691647 APU_MBOX 0x190006b0 = 0x10001
9353 12:47:30.695574 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9354 12:47:30.707901 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9355 12:47:30.720604 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9356 12:47:30.726803 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9357 12:47:30.738639 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9358 12:47:30.748370 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9359 12:47:30.751027 CPU_CLUSTER: 0 init finished in 81 msecs
9360 12:47:30.754493 Devices initialized
9361 12:47:30.758064 Show all devs... After init.
9362 12:47:30.758148 Root Device: enabled 1
9363 12:47:30.761211 CPU_CLUSTER: 0: enabled 1
9364 12:47:30.764401 CPU: 00: enabled 1
9365 12:47:30.768118 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9366 12:47:30.771269 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9367 12:47:30.774207 ELOG: NV offset 0x57f000 size 0x1000
9368 12:47:30.781557 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9369 12:47:30.787881 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9370 12:47:30.791126 ELOG: Event(17) added with size 13 at 2023-07-20 12:47:34 UTC
9371 12:47:30.794299 out: cmd=0x121: 03 db 21 01 00 00 00 00
9372 12:47:30.798250 in-header: 03 6d 00 00 2c 00 00 00
9373 12:47:30.811174 in-data: f2 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9374 12:47:30.818224 ELOG: Event(A1) added with size 10 at 2023-07-20 12:47:34 UTC
9375 12:47:30.825201 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9376 12:47:30.831094 ELOG: Event(A0) added with size 9 at 2023-07-20 12:47:34 UTC
9377 12:47:30.834536 elog_add_boot_reason: Logged dev mode boot
9378 12:47:30.838082 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9379 12:47:30.841257 Finalize devices...
9380 12:47:30.841345 Devices finalized
9381 12:47:30.847868 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9382 12:47:30.851159 Writing coreboot table at 0xffe64000
9383 12:47:30.854198 0. 000000000010a000-0000000000113fff: RAMSTAGE
9384 12:47:30.857744 1. 0000000040000000-00000000400fffff: RAM
9385 12:47:30.864458 2. 0000000040100000-000000004032afff: RAMSTAGE
9386 12:47:30.867381 3. 000000004032b000-00000000545fffff: RAM
9387 12:47:30.870892 4. 0000000054600000-000000005465ffff: BL31
9388 12:47:30.874128 5. 0000000054660000-00000000ffe63fff: RAM
9389 12:47:30.881050 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9390 12:47:30.884332 7. 0000000100000000-000000023fffffff: RAM
9391 12:47:30.884414 Passing 5 GPIOs to payload:
9392 12:47:30.891127 NAME | PORT | POLARITY | VALUE
9393 12:47:30.894152 EC in RW | 0x000000aa | low | undefined
9394 12:47:30.900572 EC interrupt | 0x00000005 | low | undefined
9395 12:47:30.904033 TPM interrupt | 0x000000ab | high | undefined
9396 12:47:30.907285 SD card detect | 0x00000011 | high | undefined
9397 12:47:30.913825 speaker enable | 0x00000093 | high | undefined
9398 12:47:30.917169 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9399 12:47:30.920661 in-header: 03 f9 00 00 02 00 00 00
9400 12:47:30.920742 in-data: 02 00
9401 12:47:30.924015 ADC[4]: Raw value=895191 ID=7
9402 12:47:30.927325 ADC[3]: Raw value=213440 ID=1
9403 12:47:30.930711 RAM Code: 0x71
9404 12:47:30.930811 ADC[6]: Raw value=74722 ID=0
9405 12:47:30.934231 ADC[5]: Raw value=212330 ID=1
9406 12:47:30.937060 SKU Code: 0x1
9407 12:47:30.940557 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 8dbd
9408 12:47:30.943959 coreboot table: 964 bytes.
9409 12:47:30.946808 IMD ROOT 0. 0xfffff000 0x00001000
9410 12:47:30.950243 IMD SMALL 1. 0xffffe000 0x00001000
9411 12:47:30.953681 RO MCACHE 2. 0xffffc000 0x00001104
9412 12:47:30.956862 CONSOLE 3. 0xfff7c000 0x00080000
9413 12:47:30.960883 FMAP 4. 0xfff7b000 0x00000452
9414 12:47:30.963937 TIME STAMP 5. 0xfff7a000 0x00000910
9415 12:47:30.967049 VBOOT WORK 6. 0xfff66000 0x00014000
9416 12:47:30.970502 RAMOOPS 7. 0xffe66000 0x00100000
9417 12:47:30.974052 COREBOOT 8. 0xffe64000 0x00002000
9418 12:47:30.974151 IMD small region:
9419 12:47:30.976803 IMD ROOT 0. 0xffffec00 0x00000400
9420 12:47:30.980052 VPD 1. 0xffffeba0 0x0000004c
9421 12:47:30.987320 MMC STATUS 2. 0xffffeb80 0x00000004
9422 12:47:30.990082 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9423 12:47:30.993448 Probing TPM: done!
9424 12:47:30.996671 Connected to device vid:did:rid of 1ae0:0028:00
9425 12:47:31.007098 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9426 12:47:31.010364 Initialized TPM device CR50 revision 0
9427 12:47:31.014452 Checking cr50 for pending updates
9428 12:47:31.017440 Reading cr50 TPM mode
9429 12:47:31.026428 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9430 12:47:31.032817 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9431 12:47:31.073026 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9432 12:47:31.076215 Checking segment from ROM address 0x40100000
9433 12:47:31.079886 Checking segment from ROM address 0x4010001c
9434 12:47:31.086473 Loading segment from ROM address 0x40100000
9435 12:47:31.086570 code (compression=0)
9436 12:47:31.092918 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9437 12:47:31.103391 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9438 12:47:31.103516 it's not compressed!
9439 12:47:31.109719 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9440 12:47:31.116393 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9441 12:47:31.133605 Loading segment from ROM address 0x4010001c
9442 12:47:31.133745 Entry Point 0x80000000
9443 12:47:31.137118 Loaded segments
9444 12:47:31.139943 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9445 12:47:31.146909 Jumping to boot code at 0x80000000(0xffe64000)
9446 12:47:31.153327 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9447 12:47:31.159761 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9448 12:47:31.167720 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9449 12:47:31.171325 Checking segment from ROM address 0x40100000
9450 12:47:31.174589 Checking segment from ROM address 0x4010001c
9451 12:47:31.181380 Loading segment from ROM address 0x40100000
9452 12:47:31.181479 code (compression=1)
9453 12:47:31.188146 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9454 12:47:31.197785 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9455 12:47:31.197899 using LZMA
9456 12:47:31.206171 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9457 12:47:31.213057 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9458 12:47:31.216259 Loading segment from ROM address 0x4010001c
9459 12:47:31.216352 Entry Point 0x54601000
9460 12:47:31.219366 Loaded segments
9461 12:47:31.222679 NOTICE: MT8192 bl31_setup
9462 12:47:31.229556 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9463 12:47:31.233178 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9464 12:47:31.236612 WARNING: region 0:
9465 12:47:31.239921 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9466 12:47:31.240003 WARNING: region 1:
9467 12:47:31.246457 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9468 12:47:31.250060 WARNING: region 2:
9469 12:47:31.253333 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9470 12:47:31.256197 WARNING: region 3:
9471 12:47:31.259610 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9472 12:47:31.263116 WARNING: region 4:
9473 12:47:31.270399 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9474 12:47:31.270489 WARNING: region 5:
9475 12:47:31.272975 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9476 12:47:31.276306 WARNING: region 6:
9477 12:47:31.279637 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9478 12:47:31.282907 WARNING: region 7:
9479 12:47:31.286313 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9480 12:47:31.293149 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9481 12:47:31.296327 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9482 12:47:31.299752 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9483 12:47:31.306686 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9484 12:47:31.310106 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9485 12:47:31.313313 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9486 12:47:31.320041 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9487 12:47:31.323180 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9488 12:47:31.326389 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9489 12:47:31.333267 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9490 12:47:31.336388 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9491 12:47:31.343412 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9492 12:47:31.346871 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9493 12:47:31.349965 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9494 12:47:31.356786 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9495 12:47:31.360250 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9496 12:47:31.363157 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9497 12:47:31.369958 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9498 12:47:31.373497 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9499 12:47:31.376758 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9500 12:47:31.383771 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9501 12:47:31.386917 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9502 12:47:31.393145 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9503 12:47:31.396364 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9504 12:47:31.403500 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9505 12:47:31.406433 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9506 12:47:31.409895 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9507 12:47:31.416312 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9508 12:47:31.419905 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9509 12:47:31.423148 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9510 12:47:31.430249 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9511 12:47:31.433065 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9512 12:47:31.439874 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9513 12:47:31.443229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9514 12:47:31.446436 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9515 12:47:31.449519 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9516 12:47:31.456435 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9517 12:47:31.459506 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9518 12:47:31.462930 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9519 12:47:31.466482 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9520 12:47:31.472733 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9521 12:47:31.476126 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9522 12:47:31.479545 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9523 12:47:31.482986 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9524 12:47:31.489324 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9525 12:47:31.492705 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9526 12:47:31.496104 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9527 12:47:31.499903 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9528 12:47:31.506349 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9529 12:47:31.509078 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9530 12:47:31.515898 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9531 12:47:31.519067 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9532 12:47:31.525686 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9533 12:47:31.529341 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9534 12:47:31.532470 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9535 12:47:31.539305 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9536 12:47:31.542676 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9537 12:47:31.548961 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9538 12:47:31.552717 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9539 12:47:31.559252 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9540 12:47:31.562452 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9541 12:47:31.565871 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9542 12:47:31.572172 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9543 12:47:31.575593 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9544 12:47:31.582337 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9545 12:47:31.585852 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9546 12:47:31.592666 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9547 12:47:31.595972 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9548 12:47:31.602326 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9549 12:47:31.605652 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9550 12:47:31.608822 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9551 12:47:31.615954 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9552 12:47:31.619078 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9553 12:47:31.625906 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9554 12:47:31.629332 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9555 12:47:31.635376 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9556 12:47:31.639183 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9557 12:47:31.642439 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9558 12:47:31.649199 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9559 12:47:31.652252 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9560 12:47:31.658550 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9561 12:47:31.661965 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9562 12:47:31.669113 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9563 12:47:31.672731 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9564 12:47:31.675532 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9565 12:47:31.682490 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9566 12:47:31.685231 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9567 12:47:31.692059 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9568 12:47:31.695425 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9569 12:47:31.702364 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9570 12:47:31.705938 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9571 12:47:31.708995 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9572 12:47:31.715670 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9573 12:47:31.719165 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9574 12:47:31.725208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9575 12:47:31.729123 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9576 12:47:31.735216 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9577 12:47:31.738884 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9578 12:47:31.742035 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9579 12:47:31.745573 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9580 12:47:31.748786 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9581 12:47:31.755598 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9582 12:47:31.759073 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9583 12:47:31.765283 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9584 12:47:31.768816 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9585 12:47:31.771888 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9586 12:47:31.779105 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9587 12:47:31.781982 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9588 12:47:31.789147 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9589 12:47:31.792063 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9590 12:47:31.795662 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9591 12:47:31.801928 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9592 12:47:31.805211 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9593 12:47:31.812095 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9594 12:47:31.815224 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9595 12:47:31.818673 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9596 12:47:31.825462 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9597 12:47:31.828408 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9598 12:47:31.832311 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9599 12:47:31.838550 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9600 12:47:31.842027 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9601 12:47:31.845271 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9602 12:47:31.848695 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9603 12:47:31.855328 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9604 12:47:31.858384 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9605 12:47:31.862069 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9606 12:47:31.868771 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9607 12:47:31.872156 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9608 12:47:31.879046 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9609 12:47:31.881746 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9610 12:47:31.885316 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9611 12:47:31.891684 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9612 12:47:31.895201 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9613 12:47:31.898628 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9614 12:47:31.905287 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9615 12:47:31.908776 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9616 12:47:31.914969 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9617 12:47:31.918615 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9618 12:47:31.922149 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9619 12:47:31.928341 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9620 12:47:31.931844 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9621 12:47:31.938459 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9622 12:47:31.942006 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9623 12:47:31.944835 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9624 12:47:31.952056 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9625 12:47:31.955503 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9626 12:47:31.961432 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9627 12:47:31.964856 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9628 12:47:31.968191 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9629 12:47:31.974757 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9630 12:47:31.978050 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9631 12:47:31.981847 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9632 12:47:31.988137 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9633 12:47:31.991640 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9634 12:47:31.998307 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9635 12:47:32.001513 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9636 12:47:32.004542 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9637 12:47:32.011341 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9638 12:47:32.014721 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9639 12:47:32.021436 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9640 12:47:32.024532 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9641 12:47:32.027720 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9642 12:47:32.034838 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9643 12:47:32.037594 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9644 12:47:32.044558 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9645 12:47:32.047542 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9646 12:47:32.050898 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9647 12:47:32.057898 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9648 12:47:32.061199 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9649 12:47:32.067776 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9650 12:47:32.071092 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9651 12:47:32.074172 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9652 12:47:32.081177 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9653 12:47:32.084286 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9654 12:47:32.090775 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9655 12:47:32.094180 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9656 12:47:32.097694 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9657 12:47:32.104057 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9658 12:47:32.107865 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9659 12:47:32.110768 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9660 12:47:32.117689 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9661 12:47:32.120497 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9662 12:47:32.127560 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9663 12:47:32.130698 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9664 12:47:32.134354 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9665 12:47:32.140430 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9666 12:47:32.143994 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9667 12:47:32.150775 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9668 12:47:32.154111 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9669 12:47:32.157302 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9670 12:47:32.163775 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9671 12:47:32.167278 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9672 12:47:32.173914 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9673 12:47:32.177100 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9674 12:47:32.183687 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9675 12:47:32.187070 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9676 12:47:32.190408 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9677 12:47:32.197151 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9678 12:47:32.200514 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9679 12:47:32.207263 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9680 12:47:32.210805 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9681 12:47:32.213584 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9682 12:47:32.220052 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9683 12:47:32.223877 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9684 12:47:32.230238 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9685 12:47:32.233591 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9686 12:47:32.240254 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9687 12:47:32.243512 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9688 12:47:32.246707 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9689 12:47:32.253456 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9690 12:47:32.256984 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9691 12:47:32.263498 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9692 12:47:32.266868 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9693 12:47:32.273060 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9694 12:47:32.276574 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9695 12:47:32.280029 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9696 12:47:32.286277 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9697 12:47:32.289692 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9698 12:47:32.296197 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9699 12:47:32.299559 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9700 12:47:32.306396 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9701 12:47:32.309866 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9702 12:47:32.313153 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9703 12:47:32.320255 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9704 12:47:32.323205 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9705 12:47:32.329534 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9706 12:47:32.333059 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9707 12:47:32.336495 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9708 12:47:32.342767 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9709 12:47:32.346086 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9710 12:47:32.349529 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9711 12:47:32.353100 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9712 12:47:32.359621 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9713 12:47:32.362942 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9714 12:47:32.366014 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9715 12:47:32.372348 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9716 12:47:32.375625 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9717 12:47:32.382220 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9718 12:47:32.386042 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9719 12:47:32.389247 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9720 12:47:32.395605 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9721 12:47:32.398997 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9722 12:47:32.402319 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9723 12:47:32.409042 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9724 12:47:32.412201 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9725 12:47:32.415715 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9726 12:47:32.421973 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9727 12:47:32.425508 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9728 12:47:32.432071 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9729 12:47:32.435155 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9730 12:47:32.438452 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9731 12:47:32.445089 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9732 12:47:32.448729 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9733 12:47:32.452105 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9734 12:47:32.459296 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9735 12:47:32.461729 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9736 12:47:32.468392 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9737 12:47:32.471854 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9738 12:47:32.475360 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9739 12:47:32.482052 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9740 12:47:32.485157 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9741 12:47:32.488155 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9742 12:47:32.494789 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9743 12:47:32.498173 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9744 12:47:32.501603 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9745 12:47:32.508226 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9746 12:47:32.511551 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9747 12:47:32.517861 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9748 12:47:32.521752 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9749 12:47:32.524658 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9750 12:47:32.528053 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9751 12:47:32.534897 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9752 12:47:32.538152 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9753 12:47:32.541426 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9754 12:47:32.544436 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9755 12:47:32.551272 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9756 12:47:32.554964 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9757 12:47:32.558234 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9758 12:47:32.561219 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9759 12:47:32.564330 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9760 12:47:32.571048 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9761 12:47:32.574408 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9762 12:47:32.581131 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9763 12:47:32.584616 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9764 12:47:32.587555 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9765 12:47:32.594411 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9766 12:47:32.597630 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9767 12:47:32.604531 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9768 12:47:32.607773 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9769 12:47:32.611002 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9770 12:47:32.617537 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9771 12:47:32.620913 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9772 12:47:32.627378 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9773 12:47:32.630764 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9774 12:47:32.638198 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9775 12:47:32.641037 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9776 12:47:32.644288 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9777 12:47:32.650459 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9778 12:47:32.654121 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9779 12:47:32.660789 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9780 12:47:32.664187 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9781 12:47:32.667272 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9782 12:47:32.674036 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9783 12:47:32.677225 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9784 12:47:32.684084 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9785 12:47:32.687020 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9786 12:47:32.690558 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9787 12:47:32.697286 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9788 12:47:32.700210 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9789 12:47:32.706903 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9790 12:47:32.710274 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9791 12:47:32.717033 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9792 12:47:32.720178 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9793 12:47:32.724225 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9794 12:47:32.730300 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9795 12:47:32.733388 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9796 12:47:32.740234 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9797 12:47:32.743863 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9798 12:47:32.747006 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9799 12:47:32.753179 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9800 12:47:32.756735 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9801 12:47:32.763298 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9802 12:47:32.767157 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9803 12:47:32.769810 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9804 12:47:32.777521 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9805 12:47:32.779667 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9806 12:47:32.786437 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9807 12:47:32.789695 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9808 12:47:32.796671 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9809 12:47:32.799621 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9810 12:47:32.803188 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9811 12:47:32.809559 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9812 12:47:32.812962 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9813 12:47:32.819296 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9814 12:47:32.822751 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9815 12:47:32.826105 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9816 12:47:32.833051 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9817 12:47:32.835970 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9818 12:47:32.842476 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9819 12:47:32.846321 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9820 12:47:32.849174 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9821 12:47:32.855703 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9822 12:47:32.859491 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9823 12:47:32.866421 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9824 12:47:32.869758 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9825 12:47:32.872596 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9826 12:47:32.879603 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9827 12:47:32.882650 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9828 12:47:32.889569 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9829 12:47:32.892237 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9830 12:47:32.899001 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9831 12:47:32.902652 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9832 12:47:32.905509 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9833 12:47:32.912523 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9834 12:47:32.915774 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9835 12:47:32.922403 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9836 12:47:32.925552 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9837 12:47:32.932339 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9838 12:47:32.935588 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9839 12:47:32.938703 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9840 12:47:32.945667 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9841 12:47:32.948833 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9842 12:47:32.955198 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9843 12:47:32.958499 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9844 12:47:32.965012 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9845 12:47:32.968350 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9846 12:47:32.975150 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9847 12:47:32.978609 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9848 12:47:32.981395 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9849 12:47:32.988275 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9850 12:47:32.991601 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9851 12:47:32.998268 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9852 12:47:33.001603 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9853 12:47:33.008820 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9854 12:47:33.011784 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9855 12:47:33.018020 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9856 12:47:33.021583 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9857 12:47:33.024813 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9858 12:47:33.031063 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9859 12:47:33.034522 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9860 12:47:33.040939 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9861 12:47:33.044309 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9862 12:47:33.050666 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9863 12:47:33.054020 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9864 12:47:33.060811 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9865 12:47:33.064113 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9866 12:47:33.067353 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9867 12:47:33.074174 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9868 12:47:33.077496 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9869 12:47:33.083904 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9870 12:47:33.087698 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9871 12:47:33.094393 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9872 12:47:33.096994 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9873 12:47:33.100364 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9874 12:47:33.107104 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9875 12:47:33.110529 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9876 12:47:33.117128 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9877 12:47:33.120572 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9878 12:47:33.126629 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9879 12:47:33.130379 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9880 12:47:33.136970 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9881 12:47:33.140145 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9882 12:47:33.143696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9883 12:47:33.149895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9884 12:47:33.153464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9885 12:47:33.160025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9886 12:47:33.163283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9887 12:47:33.170341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9888 12:47:33.173032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9889 12:47:33.179856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9890 12:47:33.183218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9891 12:47:33.189552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9892 12:47:33.192876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9893 12:47:33.199715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9894 12:47:33.203209 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9895 12:47:33.209712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9896 12:47:33.213176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9897 12:47:33.216747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9898 12:47:33.222833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9899 12:47:33.226168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9900 12:47:33.232916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9901 12:47:33.235856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9902 12:47:33.242712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9903 12:47:33.245819 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9904 12:47:33.252495 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9905 12:47:33.255936 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9906 12:47:33.262717 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9907 12:47:33.265939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9908 12:47:33.272862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9909 12:47:33.275828 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9910 12:47:33.282015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9911 12:47:33.289153 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9912 12:47:33.292354 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9913 12:47:33.298919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9914 12:47:33.302282 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9915 12:47:33.302372 INFO: [APUAPC] vio 0
9916 12:47:33.309536 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9917 12:47:33.313138 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9918 12:47:33.315909 INFO: [APUAPC] D0_APC_0: 0x400510
9919 12:47:33.319300 INFO: [APUAPC] D0_APC_1: 0x0
9920 12:47:33.323134 INFO: [APUAPC] D0_APC_2: 0x1540
9921 12:47:33.325977 INFO: [APUAPC] D0_APC_3: 0x0
9922 12:47:33.329366 INFO: [APUAPC] D1_APC_0: 0xffffffff
9923 12:47:33.332801 INFO: [APUAPC] D1_APC_1: 0xffffffff
9924 12:47:33.336143 INFO: [APUAPC] D1_APC_2: 0x3fffff
9925 12:47:33.339716 INFO: [APUAPC] D1_APC_3: 0x0
9926 12:47:33.342670 INFO: [APUAPC] D2_APC_0: 0xffffffff
9927 12:47:33.345966 INFO: [APUAPC] D2_APC_1: 0xffffffff
9928 12:47:33.349301 INFO: [APUAPC] D2_APC_2: 0x3fffff
9929 12:47:33.352871 INFO: [APUAPC] D2_APC_3: 0x0
9930 12:47:33.355821 INFO: [APUAPC] D3_APC_0: 0xffffffff
9931 12:47:33.359524 INFO: [APUAPC] D3_APC_1: 0xffffffff
9932 12:47:33.362531 INFO: [APUAPC] D3_APC_2: 0x3fffff
9933 12:47:33.365973 INFO: [APUAPC] D3_APC_3: 0x0
9934 12:47:33.369297 INFO: [APUAPC] D4_APC_0: 0xffffffff
9935 12:47:33.372569 INFO: [APUAPC] D4_APC_1: 0xffffffff
9936 12:47:33.375510 INFO: [APUAPC] D4_APC_2: 0x3fffff
9937 12:47:33.375595 INFO: [APUAPC] D4_APC_3: 0x0
9938 12:47:33.382603 INFO: [APUAPC] D5_APC_0: 0xffffffff
9939 12:47:33.385847 INFO: [APUAPC] D5_APC_1: 0xffffffff
9940 12:47:33.389095 INFO: [APUAPC] D5_APC_2: 0x3fffff
9941 12:47:33.389196 INFO: [APUAPC] D5_APC_3: 0x0
9942 12:47:33.392433 INFO: [APUAPC] D6_APC_0: 0xffffffff
9943 12:47:33.395753 INFO: [APUAPC] D6_APC_1: 0xffffffff
9944 12:47:33.399098 INFO: [APUAPC] D6_APC_2: 0x3fffff
9945 12:47:33.402076 INFO: [APUAPC] D6_APC_3: 0x0
9946 12:47:33.405508 INFO: [APUAPC] D7_APC_0: 0xffffffff
9947 12:47:33.409201 INFO: [APUAPC] D7_APC_1: 0xffffffff
9948 12:47:33.412081 INFO: [APUAPC] D7_APC_2: 0x3fffff
9949 12:47:33.415640 INFO: [APUAPC] D7_APC_3: 0x0
9950 12:47:33.418631 INFO: [APUAPC] D8_APC_0: 0xffffffff
9951 12:47:33.422196 INFO: [APUAPC] D8_APC_1: 0xffffffff
9952 12:47:33.425477 INFO: [APUAPC] D8_APC_2: 0x3fffff
9953 12:47:33.428387 INFO: [APUAPC] D8_APC_3: 0x0
9954 12:47:33.431947 INFO: [APUAPC] D9_APC_0: 0xffffffff
9955 12:47:33.435247 INFO: [APUAPC] D9_APC_1: 0xffffffff
9956 12:47:33.438661 INFO: [APUAPC] D9_APC_2: 0x3fffff
9957 12:47:33.442025 INFO: [APUAPC] D9_APC_3: 0x0
9958 12:47:33.445503 INFO: [APUAPC] D10_APC_0: 0xffffffff
9959 12:47:33.448437 INFO: [APUAPC] D10_APC_1: 0xffffffff
9960 12:47:33.451814 INFO: [APUAPC] D10_APC_2: 0x3fffff
9961 12:47:33.454927 INFO: [APUAPC] D10_APC_3: 0x0
9962 12:47:33.458335 INFO: [APUAPC] D11_APC_0: 0xffffffff
9963 12:47:33.461839 INFO: [APUAPC] D11_APC_1: 0xffffffff
9964 12:47:33.465357 INFO: [APUAPC] D11_APC_2: 0x3fffff
9965 12:47:33.468605 INFO: [APUAPC] D11_APC_3: 0x0
9966 12:47:33.471670 INFO: [APUAPC] D12_APC_0: 0xffffffff
9967 12:47:33.474796 INFO: [APUAPC] D12_APC_1: 0xffffffff
9968 12:47:33.478120 INFO: [APUAPC] D12_APC_2: 0x3fffff
9969 12:47:33.481382 INFO: [APUAPC] D12_APC_3: 0x0
9970 12:47:33.484859 INFO: [APUAPC] D13_APC_0: 0xffffffff
9971 12:47:33.488024 INFO: [APUAPC] D13_APC_1: 0xffffffff
9972 12:47:33.491577 INFO: [APUAPC] D13_APC_2: 0x3fffff
9973 12:47:33.494660 INFO: [APUAPC] D13_APC_3: 0x0
9974 12:47:33.498025 INFO: [APUAPC] D14_APC_0: 0xffffffff
9975 12:47:33.501533 INFO: [APUAPC] D14_APC_1: 0xffffffff
9976 12:47:33.505045 INFO: [APUAPC] D14_APC_2: 0x3fffff
9977 12:47:33.507870 INFO: [APUAPC] D14_APC_3: 0x0
9978 12:47:33.511345 INFO: [APUAPC] D15_APC_0: 0xffffffff
9979 12:47:33.517708 INFO: [APUAPC] D15_APC_1: 0xffffffff
9980 12:47:33.521472 INFO: [APUAPC] D15_APC_2: 0x3fffff
9981 12:47:33.521567 INFO: [APUAPC] D15_APC_3: 0x0
9982 12:47:33.524435 INFO: [APUAPC] APC_CON: 0x4
9983 12:47:33.528015 INFO: [NOCDAPC] D0_APC_0: 0x0
9984 12:47:33.531164 INFO: [NOCDAPC] D0_APC_1: 0x0
9985 12:47:33.534594 INFO: [NOCDAPC] D1_APC_0: 0x0
9986 12:47:33.537550 INFO: [NOCDAPC] D1_APC_1: 0xfff
9987 12:47:33.541368 INFO: [NOCDAPC] D2_APC_0: 0x0
9988 12:47:33.544263 INFO: [NOCDAPC] D2_APC_1: 0xfff
9989 12:47:33.547627 INFO: [NOCDAPC] D3_APC_0: 0x0
9990 12:47:33.547714 INFO: [NOCDAPC] D3_APC_1: 0xfff
9991 12:47:33.551171 INFO: [NOCDAPC] D4_APC_0: 0x0
9992 12:47:33.554604 INFO: [NOCDAPC] D4_APC_1: 0xfff
9993 12:47:33.557769 INFO: [NOCDAPC] D5_APC_0: 0x0
9994 12:47:33.561170 INFO: [NOCDAPC] D5_APC_1: 0xfff
9995 12:47:33.563998 INFO: [NOCDAPC] D6_APC_0: 0x0
9996 12:47:33.567474 INFO: [NOCDAPC] D6_APC_1: 0xfff
9997 12:47:33.570869 INFO: [NOCDAPC] D7_APC_0: 0x0
9998 12:47:33.574307 INFO: [NOCDAPC] D7_APC_1: 0xfff
9999 12:47:33.577274 INFO: [NOCDAPC] D8_APC_0: 0x0
10000 12:47:33.581009 INFO: [NOCDAPC] D8_APC_1: 0xfff
10001 12:47:33.581095 INFO: [NOCDAPC] D9_APC_0: 0x0
10002 12:47:33.584515 INFO: [NOCDAPC] D9_APC_1: 0xfff
10003 12:47:33.587440 INFO: [NOCDAPC] D10_APC_0: 0x0
10004 12:47:33.590735 INFO: [NOCDAPC] D10_APC_1: 0xfff
10005 12:47:33.594015 INFO: [NOCDAPC] D11_APC_0: 0x0
10006 12:47:33.597384 INFO: [NOCDAPC] D11_APC_1: 0xfff
10007 12:47:33.601012 INFO: [NOCDAPC] D12_APC_0: 0x0
10008 12:47:33.604319 INFO: [NOCDAPC] D12_APC_1: 0xfff
10009 12:47:33.607383 INFO: [NOCDAPC] D13_APC_0: 0x0
10010 12:47:33.610821 INFO: [NOCDAPC] D13_APC_1: 0xfff
10011 12:47:33.614093 INFO: [NOCDAPC] D14_APC_0: 0x0
10012 12:47:33.617039 INFO: [NOCDAPC] D14_APC_1: 0xfff
10013 12:47:33.620446 INFO: [NOCDAPC] D15_APC_0: 0x0
10014 12:47:33.623728 INFO: [NOCDAPC] D15_APC_1: 0xfff
10015 12:47:33.627222 INFO: [NOCDAPC] APC_CON: 0x4
10016 12:47:33.630438 INFO: [APUAPC] set_apusys_apc done
10017 12:47:33.630526 INFO: [DEVAPC] devapc_init done
10018 12:47:33.637393 INFO: GICv3 without legacy support detected.
10019 12:47:33.640564 INFO: ARM GICv3 driver initialized in EL3
10020 12:47:33.643788 INFO: Maximum SPI INTID supported: 639
10021 12:47:33.647310 INFO: BL31: Initializing runtime services
10022 12:47:33.653907 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10023 12:47:33.656835 INFO: SPM: enable CPC mode
10024 12:47:33.660178 INFO: mcdi ready for mcusys-off-idle and system suspend
10025 12:47:33.666835 INFO: BL31: Preparing for EL3 exit to normal world
10026 12:47:33.670406 INFO: Entry point address = 0x80000000
10027 12:47:33.670498 INFO: SPSR = 0x8
10028 12:47:33.677634
10029 12:47:33.677729
10030 12:47:33.677795
10031 12:47:33.680654 Starting depthcharge on Spherion...
10032 12:47:33.680736
10033 12:47:33.680800 Wipe memory regions:
10034 12:47:33.680859
10035 12:47:33.681526 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10036 12:47:33.681630 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10037 12:47:33.681709 Setting prompt string to ['asurada:']
10038 12:47:33.681785 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10039 12:47:33.683939 [0x00000040000000, 0x00000054600000)
10040 12:47:33.806792
10041 12:47:33.806947 [0x00000054660000, 0x00000080000000)
10042 12:47:34.067203
10043 12:47:34.067358 [0x000000821a7280, 0x000000ffe64000)
10044 12:47:34.812111
10045 12:47:34.812266 [0x00000100000000, 0x00000240000000)
10046 12:47:36.702430
10047 12:47:36.705222 Initializing XHCI USB controller at 0x11200000.
10048 12:47:37.743537
10049 12:47:37.746478 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10050 12:47:37.746694
10051 12:47:37.746805
10052 12:47:37.746921
10053 12:47:37.747251 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10055 12:47:37.847698 asurada: tftpboot 192.168.201.1 11118918/tftp-deploy-4z2yt1i4/kernel/image.itb 11118918/tftp-deploy-4z2yt1i4/kernel/cmdline
10056 12:47:37.847933 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10057 12:47:37.848055 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10058 12:47:37.852318 tftpboot 192.168.201.1 11118918/tftp-deploy-4z2yt1i4/kernel/image.itp-deploy-4z2yt1i4/kernel/cmdline
10059 12:47:37.852516
10060 12:47:37.852618 Waiting for link
10061 12:47:38.012829
10062 12:47:38.013029 R8152: Initializing
10063 12:47:38.013129
10064 12:47:38.015977 Version 6 (ocp_data = 5c30)
10065 12:47:38.016105
10066 12:47:38.019189 R8152: Done initializing
10067 12:47:38.019364
10068 12:47:38.019485 Adding net device
10069 12:47:39.922803
10070 12:47:39.923004 done.
10071 12:47:39.923105
10072 12:47:39.923197 MAC: 00:24:32:30:78:ff
10073 12:47:39.923288
10074 12:47:39.925965 Sending DHCP discover... done.
10075 12:47:39.926125
10076 12:47:43.944492 Waiting for reply... done.
10077 12:47:43.944642
10078 12:47:43.944712 Sending DHCP request... done.
10079 12:47:43.947594
10080 12:47:43.947717 Waiting for reply... done.
10081 12:47:43.947785
10082 12:47:43.950979 My ip is 192.168.201.21
10083 12:47:43.951079
10084 12:47:43.954120 The DHCP server ip is 192.168.201.1
10085 12:47:43.954229
10086 12:47:43.957474 TFTP server IP predefined by user: 192.168.201.1
10087 12:47:43.957596
10088 12:47:43.964144 Bootfile predefined by user: 11118918/tftp-deploy-4z2yt1i4/kernel/image.itb
10089 12:47:43.964318
10090 12:47:43.967599 Sending tftp read request... done.
10091 12:47:43.967770
10092 12:47:43.971028 Waiting for the transfer...
10093 12:47:43.971195
10094 12:47:44.532295 00000000 ################################################################
10095 12:47:44.532440
10096 12:47:45.067165 00080000 ################################################################
10097 12:47:45.067317
10098 12:47:45.611216 00100000 ################################################################
10099 12:47:45.611457
10100 12:47:46.141705 00180000 ################################################################
10101 12:47:46.141921
10102 12:47:46.704198 00200000 ################################################################
10103 12:47:46.704365
10104 12:47:47.266062 00280000 ################################################################
10105 12:47:47.266272
10106 12:47:47.803236 00300000 ################################################################
10107 12:47:47.803500
10108 12:47:48.336930 00380000 ################################################################
10109 12:47:48.337074
10110 12:47:48.864902 00400000 ################################################################
10111 12:47:48.865065
10112 12:47:49.419481 00480000 ################################################################
10113 12:47:49.419712
10114 12:47:49.986413 00500000 ################################################################
10115 12:47:49.986546
10116 12:47:50.574374 00580000 ################################################################
10117 12:47:50.574595
10118 12:47:51.116887 00600000 ################################################################
10119 12:47:51.117039
10120 12:47:51.653455 00680000 ################################################################
10121 12:47:51.653710
10122 12:47:52.198318 00700000 ################################################################
10123 12:47:52.198478
10124 12:47:52.742722 00780000 ################################################################
10125 12:47:52.742900
10126 12:47:53.302455 00800000 ################################################################
10127 12:47:53.302696
10128 12:47:53.866888 00880000 ################################################################
10129 12:47:53.867043
10130 12:47:54.430142 00900000 ################################################################
10131 12:47:54.430327
10132 12:47:55.031224 00980000 ################################################################
10133 12:47:55.031430
10134 12:47:55.574846 00a00000 ################################################################
10135 12:47:55.574998
10136 12:47:56.131965 00a80000 ################################################################
10137 12:47:56.132120
10138 12:47:56.681319 00b00000 ################################################################
10139 12:47:56.681468
10140 12:47:57.246315 00b80000 ################################################################
10141 12:47:57.246585
10142 12:47:57.829688 00c00000 ################################################################
10143 12:47:57.829834
10144 12:47:58.405714 00c80000 ################################################################
10145 12:47:58.405872
10146 12:47:58.979662 00d00000 ################################################################
10147 12:47:58.979803
10148 12:47:59.541056 00d80000 ################################################################
10149 12:47:59.541221
10150 12:48:00.096750 00e00000 ################################################################
10151 12:48:00.096886
10152 12:48:00.673055 00e80000 ################################################################
10153 12:48:00.673223
10154 12:48:01.266347 00f00000 ################################################################
10155 12:48:01.266495
10156 12:48:01.838778 00f80000 ################################################################
10157 12:48:01.838983
10158 12:48:02.489874 01000000 ################################################################
10159 12:48:02.490623
10160 12:48:03.199066 01080000 ################################################################
10161 12:48:03.199203
10162 12:48:03.812002 01100000 ################################################################
10163 12:48:03.812150
10164 12:48:04.449079 01180000 ################################################################
10165 12:48:04.449634
10166 12:48:05.148284 01200000 ################################################################
10167 12:48:05.148860
10168 12:48:05.802619 01280000 ################################################################
10169 12:48:05.802819
10170 12:48:06.496357 01300000 ################################################################
10171 12:48:06.496986
10172 12:48:07.175869 01380000 ################################################################
10173 12:48:07.176409
10174 12:48:07.871706 01400000 ################################################################
10175 12:48:07.872255
10176 12:48:08.530976 01480000 ################################################################
10177 12:48:08.531144
10178 12:48:09.203449 01500000 ################################################################
10179 12:48:09.203998
10180 12:48:09.875089 01580000 ################################################################
10181 12:48:09.875676
10182 12:48:10.538140 01600000 ################################################################
10183 12:48:10.538680
10184 12:48:11.221997 01680000 ################################################################
10185 12:48:11.222530
10186 12:48:11.875654 01700000 ################################################################
10187 12:48:11.876151
10188 12:48:12.522302 01780000 ################################################################
10189 12:48:12.522789
10190 12:48:13.190271 01800000 ################################################################
10191 12:48:13.190891
10192 12:48:13.858929 01880000 ################################################################
10193 12:48:13.859462
10194 12:48:14.540238 01900000 ################################################################
10195 12:48:14.540365
10196 12:48:15.199986 01980000 ################################################################
10197 12:48:15.200501
10198 12:48:15.870157 01a00000 ################################################################
10199 12:48:15.870752
10200 12:48:16.767299 01a80000 ################################################################
10201 12:48:16.767979
10202 12:48:17.200914 01b00000 ################################################################
10203 12:48:17.201551
10204 12:48:17.785927 01b80000 ################################################################
10205 12:48:17.786062
10206 12:48:18.349295 01c00000 ################################################################
10207 12:48:18.349430
10208 12:48:18.892244 01c80000 ################################################################
10209 12:48:18.892375
10210 12:48:19.437314 01d00000 ################################################################
10211 12:48:19.437469
10212 12:48:19.982015 01d80000 ################################################################
10213 12:48:19.982173
10214 12:48:20.547653 01e00000 ################################################################
10215 12:48:20.547786
10216 12:48:21.113909 01e80000 ################################################################
10217 12:48:21.114040
10218 12:48:21.663367 01f00000 ################################################################
10219 12:48:21.663512
10220 12:48:22.204217 01f80000 ################################################################
10221 12:48:22.204346
10222 12:48:22.752312 02000000 ################################################################
10223 12:48:22.752496
10224 12:48:23.302733 02080000 ################################################################
10225 12:48:23.302948
10226 12:48:23.857446 02100000 ################################################################
10227 12:48:23.857610
10228 12:48:24.404865 02180000 ################################################################
10229 12:48:24.405027
10230 12:48:24.945227 02200000 ################################################################
10231 12:48:24.945394
10232 12:48:25.482186 02280000 ################################################################
10233 12:48:25.482343
10234 12:48:26.006075 02300000 ################################################################
10235 12:48:26.006226
10236 12:48:26.535473 02380000 ################################################################
10237 12:48:26.535642
10238 12:48:27.075244 02400000 ################################################################
10239 12:48:27.075382
10240 12:48:27.596568 02480000 ################################################################
10241 12:48:27.596698
10242 12:48:28.123729 02500000 ################################################################
10243 12:48:28.123858
10244 12:48:28.660659 02580000 ################################################################
10245 12:48:28.660794
10246 12:48:29.189360 02600000 ################################################################
10247 12:48:29.189504
10248 12:48:29.714965 02680000 ################################################################
10249 12:48:29.715133
10250 12:48:30.246730 02700000 ################################################################
10251 12:48:30.246873
10252 12:48:30.832579 02780000 ################################################################
10253 12:48:30.833093
10254 12:48:31.490885 02800000 ################################################################
10255 12:48:31.491426
10256 12:48:32.136237 02880000 ################################################################
10257 12:48:32.136371
10258 12:48:32.690004 02900000 ################################################################
10259 12:48:32.690135
10260 12:48:33.240086 02980000 ################################################################
10261 12:48:33.240222
10262 12:48:33.787114 02a00000 ################################################################
10263 12:48:33.787254
10264 12:48:34.351257 02a80000 ################################################################
10265 12:48:34.351456
10266 12:48:34.948205 02b00000 ################################################################
10267 12:48:34.948341
10268 12:48:35.530976 02b80000 ################################################################
10269 12:48:35.531140
10270 12:48:36.249918 02c00000 ################################################################
10271 12:48:36.250075
10272 12:48:36.736710 02c80000 ################################################################
10273 12:48:36.736861
10274 12:48:37.329185 02d00000 ################################################################
10275 12:48:37.329341
10276 12:48:37.987821 02d80000 ################################################################
10277 12:48:37.988368
10278 12:48:38.597614 02e00000 ################################################################
10279 12:48:38.597764
10280 12:48:39.203835 02e80000 ################################################################
10281 12:48:39.203989
10282 12:48:39.850176 02f00000 ################################################################
10283 12:48:39.850681
10284 12:48:40.161970 02f80000 ################################ done.
10285 12:48:40.162133
10286 12:48:40.165257 The bootfile was 50069142 bytes long.
10287 12:48:40.165345
10288 12:48:40.168650 Sending tftp read request... done.
10289 12:48:40.168732
10290 12:48:40.168797 Waiting for the transfer...
10291 12:48:40.168857
10292 12:48:40.171921 00000000 # done.
10293 12:48:40.172006
10294 12:48:40.178173 Command line loaded dynamically from TFTP file: 11118918/tftp-deploy-4z2yt1i4/kernel/cmdline
10295 12:48:40.178256
10296 12:48:40.192167 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10297 12:48:40.192723
10298 12:48:40.195077 Loading FIT.
10299 12:48:40.195608
10300 12:48:40.198569 Image ramdisk-1 has 39212006 bytes.
10301 12:48:40.198990
10302 12:48:40.202053 Image fdt-1 has 46924 bytes.
10303 12:48:40.202467
10304 12:48:40.202807 Image kernel-1 has 10808178 bytes.
10305 12:48:40.205324
10306 12:48:40.211905 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10307 12:48:40.212338
10308 12:48:40.231899 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10309 12:48:40.232582
10310 12:48:40.234804 Choosing best match conf-1 for compat google,spherion-rev2.
10311 12:48:40.239321
10312 12:48:40.317328 Connected to device vid:did:rid of 1ae0:0028:00
10313 12:48:40.327776
10314 12:48:40.330587 tpm_get_response: command 0x17b, return code 0x0
10315 12:48:40.331162
10316 12:48:40.333935 ec_init: CrosEC protocol v3 supported (256, 248)
10317 12:48:40.338001
10318 12:48:40.341096 tpm_cleanup: add release locality here.
10319 12:48:40.341563
10320 12:48:40.341926 Shutting down all USB controllers.
10321 12:48:40.344596
10322 12:48:40.345277 Removing current net device
10323 12:48:40.345670
10324 12:48:40.351591 Exiting depthcharge with code 4 at timestamp: 95966410
10325 12:48:40.352192
10326 12:48:40.354546 LZMA decompressing kernel-1 to 0x821a6718
10327 12:48:40.355068
10328 12:48:40.358130 LZMA decompressing kernel-1 to 0x40000000
10329 12:48:41.709091
10330 12:48:41.709579 jumping to kernel
10331 12:48:41.711164 end: 2.2.4 bootloader-commands (duration 00:01:08) [common]
10332 12:48:41.711797 start: 2.2.5 auto-login-action (timeout 00:03:17) [common]
10333 12:48:41.712212 Setting prompt string to ['Linux version [0-9]']
10334 12:48:41.712674 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10335 12:48:41.713129 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10336 12:48:41.791064
10337 12:48:41.794151 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10338 12:48:41.797931 start: 2.2.5.1 login-action (timeout 00:03:17) [common]
10339 12:48:41.798446 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10340 12:48:41.798987 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10341 12:48:41.799609 Using line separator: #'\n'#
10342 12:48:41.799998 No login prompt set.
10343 12:48:41.800482 Parsing kernel messages
10344 12:48:41.800861 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10345 12:48:41.801507 [login-action] Waiting for messages, (timeout 00:03:17)
10346 12:48:41.817325 [ 0.000000] Linux version 6.1.38-cip1 (KernelCI@build-j6766-arm64-gcc-10-defconfig-arm64-chromebook-9w8v6) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Jul 20 12:35:57 UTC 2023
10347 12:48:41.820798 [ 0.000000] random: crng init done
10348 12:48:41.827258 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10349 12:48:41.827780 [ 0.000000] efi: UEFI not found.
10350 12:48:41.837402 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10351 12:48:41.843870 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10352 12:48:41.853831 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10353 12:48:41.863472 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10354 12:48:41.870414 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10355 12:48:41.876959 [ 0.000000] printk: bootconsole [mtk8250] enabled
10356 12:48:41.883327 [ 0.000000] NUMA: No NUMA configuration found
10357 12:48:41.890231 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10358 12:48:41.893361 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10359 12:48:41.896584 [ 0.000000] Zone ranges:
10360 12:48:41.903339 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10361 12:48:41.906819 [ 0.000000] DMA32 empty
10362 12:48:41.912980 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10363 12:48:41.916549 [ 0.000000] Movable zone start for each node
10364 12:48:41.919436 [ 0.000000] Early memory node ranges
10365 12:48:41.925931 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10366 12:48:41.932661 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10367 12:48:41.938989 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10368 12:48:41.945775 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10369 12:48:41.949011 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10370 12:48:41.958932 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10371 12:48:42.014593 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10372 12:48:42.021192 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10373 12:48:42.027992 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10374 12:48:42.031550 [ 0.000000] psci: probing for conduit method from DT.
10375 12:48:42.038091 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10376 12:48:42.041121 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10377 12:48:42.048153 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10378 12:48:42.051232 [ 0.000000] psci: SMC Calling Convention v1.2
10379 12:48:42.057957 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10380 12:48:42.061069 [ 0.000000] Detected VIPT I-cache on CPU0
10381 12:48:42.067857 [ 0.000000] CPU features: detected: GIC system register CPU interface
10382 12:48:42.074120 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10383 12:48:42.080695 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10384 12:48:42.087265 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10385 12:48:42.094360 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10386 12:48:42.104093 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10387 12:48:42.107025 [ 0.000000] alternatives: applying boot alternatives
10388 12:48:42.113762 [ 0.000000] Fallback order for Node 0: 0
10389 12:48:42.120444 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10390 12:48:42.123580 [ 0.000000] Policy zone: Normal
10391 12:48:42.136943 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10392 12:48:42.146489 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10393 12:48:42.158922 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10394 12:48:42.169134 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10395 12:48:42.175362 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10396 12:48:42.179053 <6>[ 0.000000] software IO TLB: area num 8.
10397 12:48:42.235844 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10398 12:48:42.384844 <6>[ 0.000000] Memory: 7931908K/8385536K available (17984K kernel code, 4098K rwdata, 16796K rodata, 8384K init, 615K bss, 420860K reserved, 32768K cma-reserved)
10399 12:48:42.391311 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10400 12:48:42.397795 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10401 12:48:42.401404 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10402 12:48:42.407707 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10403 12:48:42.414287 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10404 12:48:42.417427 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10405 12:48:42.427315 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10406 12:48:42.433933 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10407 12:48:42.440739 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10408 12:48:42.447450 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10409 12:48:42.450370 <6>[ 0.000000] GICv3: 608 SPIs implemented
10410 12:48:42.453948 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10411 12:48:42.460267 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10412 12:48:42.463867 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10413 12:48:42.470509 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10414 12:48:42.483603 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10415 12:48:42.496774 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10416 12:48:42.503461 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10417 12:48:42.510780 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10418 12:48:42.524099 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10419 12:48:42.530844 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10420 12:48:42.537466 <6>[ 0.009178] Console: colour dummy device 80x25
10421 12:48:42.547224 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10422 12:48:42.553994 <6>[ 0.024347] pid_max: default: 32768 minimum: 301
10423 12:48:42.557423 <6>[ 0.029251] LSM: Security Framework initializing
10424 12:48:42.564179 <6>[ 0.034187] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10425 12:48:42.573586 <6>[ 0.042001] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10426 12:48:42.583855 <6>[ 0.051429] cblist_init_generic: Setting adjustable number of callback queues.
10427 12:48:42.587077 <6>[ 0.058882] cblist_init_generic: Setting shift to 3 and lim to 1.
10428 12:48:42.593822 <6>[ 0.065221] cblist_init_generic: Setting shift to 3 and lim to 1.
10429 12:48:42.600156 <6>[ 0.071628] rcu: Hierarchical SRCU implementation.
10430 12:48:42.607156 <6>[ 0.076641] rcu: Max phase no-delay instances is 1000.
10431 12:48:42.610624 <6>[ 0.083664] EFI services will not be available.
10432 12:48:42.616741 <6>[ 0.088633] smp: Bringing up secondary CPUs ...
10433 12:48:42.624501 <6>[ 0.093715] Detected VIPT I-cache on CPU1
10434 12:48:42.630911 <6>[ 0.093782] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10435 12:48:42.637548 <6>[ 0.093812] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10436 12:48:42.641066 <6>[ 0.094147] Detected VIPT I-cache on CPU2
10437 12:48:42.647638 <6>[ 0.094198] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10438 12:48:42.654427 <6>[ 0.094215] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10439 12:48:42.661076 <6>[ 0.094472] Detected VIPT I-cache on CPU3
10440 12:48:42.667267 <6>[ 0.094518] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10441 12:48:42.673947 <6>[ 0.094532] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10442 12:48:42.677570 <6>[ 0.094834] CPU features: detected: Spectre-v4
10443 12:48:42.683921 <6>[ 0.094840] CPU features: detected: Spectre-BHB
10444 12:48:42.687343 <6>[ 0.094846] Detected PIPT I-cache on CPU4
10445 12:48:42.694180 <6>[ 0.094904] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10446 12:48:42.700445 <6>[ 0.094921] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10447 12:48:42.706933 <6>[ 0.095215] Detected PIPT I-cache on CPU5
10448 12:48:42.713620 <6>[ 0.095279] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10449 12:48:42.720371 <6>[ 0.095295] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10450 12:48:42.723350 <6>[ 0.095579] Detected PIPT I-cache on CPU6
10451 12:48:42.729836 <6>[ 0.095646] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10452 12:48:42.737015 <6>[ 0.095663] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10453 12:48:42.743513 <6>[ 0.095961] Detected PIPT I-cache on CPU7
10454 12:48:42.750071 <6>[ 0.096026] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10455 12:48:42.756684 <6>[ 0.096043] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10456 12:48:42.759988 <6>[ 0.096090] smp: Brought up 1 node, 8 CPUs
10457 12:48:42.766476 <6>[ 0.237527] SMP: Total of 8 processors activated.
10458 12:48:42.770232 <6>[ 0.242478] CPU features: detected: 32-bit EL0 Support
10459 12:48:42.780241 <6>[ 0.247841] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10460 12:48:42.786959 <6>[ 0.256641] CPU features: detected: Common not Private translations
10461 12:48:42.793287 <6>[ 0.263117] CPU features: detected: CRC32 instructions
10462 12:48:42.796835 <6>[ 0.268468] CPU features: detected: RCpc load-acquire (LDAPR)
10463 12:48:42.803611 <6>[ 0.274465] CPU features: detected: LSE atomic instructions
10464 12:48:42.810571 <6>[ 0.280247] CPU features: detected: Privileged Access Never
10465 12:48:42.816710 <6>[ 0.286062] CPU features: detected: RAS Extension Support
10466 12:48:42.823453 <6>[ 0.291671] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10467 12:48:42.826718 <6>[ 0.298936] CPU: All CPU(s) started at EL2
10468 12:48:42.832972 <6>[ 0.303254] alternatives: applying system-wide alternatives
10469 12:48:42.842423 <6>[ 0.313928] devtmpfs: initialized
10470 12:48:42.854700 <6>[ 0.322983] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10471 12:48:42.864690 <6>[ 0.332944] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10472 12:48:42.871332 <6>[ 0.341186] pinctrl core: initialized pinctrl subsystem
10473 12:48:42.874336 <6>[ 0.347847] DMI not present or invalid.
10474 12:48:42.880934 <6>[ 0.352258] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10475 12:48:42.890888 <6>[ 0.359144] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10476 12:48:42.897552 <6>[ 0.366723] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10477 12:48:42.907452 <6>[ 0.374948] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10478 12:48:42.911306 <6>[ 0.383192] audit: initializing netlink subsys (disabled)
10479 12:48:42.921013 <5>[ 0.388875] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10480 12:48:42.927209 <6>[ 0.389567] thermal_sys: Registered thermal governor 'step_wise'
10481 12:48:42.934524 <6>[ 0.396846] thermal_sys: Registered thermal governor 'power_allocator'
10482 12:48:42.937302 <6>[ 0.403101] cpuidle: using governor menu
10483 12:48:42.944224 <6>[ 0.414065] NET: Registered PF_QIPCRTR protocol family
10484 12:48:42.951237 <6>[ 0.419554] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10485 12:48:42.957546 <6>[ 0.426658] ASID allocator initialised with 32768 entries
10486 12:48:42.960858 <6>[ 0.433227] Serial: AMBA PL011 UART driver
10487 12:48:42.970466 <4>[ 0.441885] Trying to register duplicate clock ID: 134
10488 12:48:43.024285 <6>[ 0.499072] KASLR enabled
10489 12:48:43.038400 <6>[ 0.506856] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10490 12:48:43.045210 <6>[ 0.513872] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10491 12:48:43.051797 <6>[ 0.520360] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10492 12:48:43.058358 <6>[ 0.527366] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10493 12:48:43.065068 <6>[ 0.533853] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10494 12:48:43.071656 <6>[ 0.540861] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10495 12:48:43.078276 <6>[ 0.547349] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10496 12:48:43.084674 <6>[ 0.554355] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10497 12:48:43.087915 <6>[ 0.561852] ACPI: Interpreter disabled.
10498 12:48:43.096651 <6>[ 0.568247] iommu: Default domain type: Translated
10499 12:48:43.103661 <6>[ 0.573359] iommu: DMA domain TLB invalidation policy: strict mode
10500 12:48:43.106776 <5>[ 0.580016] SCSI subsystem initialized
10501 12:48:43.113414 <6>[ 0.584191] usbcore: registered new interface driver usbfs
10502 12:48:43.120409 <6>[ 0.589922] usbcore: registered new interface driver hub
10503 12:48:43.123175 <6>[ 0.595474] usbcore: registered new device driver usb
10504 12:48:43.129872 <6>[ 0.601553] pps_core: LinuxPPS API ver. 1 registered
10505 12:48:43.140026 <6>[ 0.606747] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10506 12:48:43.143208 <6>[ 0.616094] PTP clock support registered
10507 12:48:43.146176 <6>[ 0.620337] EDAC MC: Ver: 3.0.0
10508 12:48:43.154096 <6>[ 0.625467] FPGA manager framework
10509 12:48:43.160709 <6>[ 0.629146] Advanced Linux Sound Architecture Driver Initialized.
10510 12:48:43.163571 <6>[ 0.635927] vgaarb: loaded
10511 12:48:43.170486 <6>[ 0.639114] clocksource: Switched to clocksource arch_sys_counter
10512 12:48:43.173883 <5>[ 0.645555] VFS: Disk quotas dquot_6.6.0
10513 12:48:43.180555 <6>[ 0.649742] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10514 12:48:43.183459 <6>[ 0.656913] pnp: PnP ACPI: disabled
10515 12:48:43.192229 <6>[ 0.663637] NET: Registered PF_INET protocol family
10516 12:48:43.202083 <6>[ 0.669235] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10517 12:48:43.213235 <6>[ 0.681553] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10518 12:48:43.223188 <6>[ 0.690362] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10519 12:48:43.230414 <6>[ 0.698333] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10520 12:48:43.236354 <6>[ 0.706987] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10521 12:48:43.248453 <6>[ 0.716732] TCP: Hash tables configured (established 65536 bind 65536)
10522 12:48:43.254902 <6>[ 0.723590] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10523 12:48:43.261654 <6>[ 0.730790] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10524 12:48:43.268861 <6>[ 0.738493] NET: Registered PF_UNIX/PF_LOCAL protocol family
10525 12:48:43.275138 <6>[ 0.744658] RPC: Registered named UNIX socket transport module.
10526 12:48:43.278167 <6>[ 0.750812] RPC: Registered udp transport module.
10527 12:48:43.284475 <6>[ 0.755748] RPC: Registered tcp transport module.
10528 12:48:43.291644 <6>[ 0.760681] RPC: Registered tcp NFSv4.1 backchannel transport module.
10529 12:48:43.294645 <6>[ 0.767353] PCI: CLS 0 bytes, default 64
10530 12:48:43.297650 <6>[ 0.771740] Unpacking initramfs...
10531 12:48:43.323079 <6>[ 0.791231] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10532 12:48:43.332551 <6>[ 0.799904] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10533 12:48:43.335920 <6>[ 0.808746] kvm [1]: IPA Size Limit: 40 bits
10534 12:48:43.342532 <6>[ 0.813277] kvm [1]: GICv3: no GICV resource entry
10535 12:48:43.346101 <6>[ 0.818297] kvm [1]: disabling GICv2 emulation
10536 12:48:43.352591 <6>[ 0.822987] kvm [1]: GIC system register CPU interface enabled
10537 12:48:43.356115 <6>[ 0.829153] kvm [1]: vgic interrupt IRQ18
10538 12:48:43.362276 <6>[ 0.833510] kvm [1]: VHE mode initialized successfully
10539 12:48:43.369332 <5>[ 0.839912] Initialise system trusted keyrings
10540 12:48:43.375825 <6>[ 0.844744] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10541 12:48:43.383313 <6>[ 0.854965] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10542 12:48:43.389874 <5>[ 0.861377] NFS: Registering the id_resolver key type
10543 12:48:43.393410 <5>[ 0.866678] Key type id_resolver registered
10544 12:48:43.400062 <5>[ 0.871096] Key type id_legacy registered
10545 12:48:43.406517 <6>[ 0.875376] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10546 12:48:43.413022 <6>[ 0.882299] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10547 12:48:43.419597 <6>[ 0.890029] 9p: Installing v9fs 9p2000 file system support
10548 12:48:43.456671 <5>[ 0.927864] Key type asymmetric registered
10549 12:48:43.459615 <5>[ 0.932204] Asymmetric key parser 'x509' registered
10550 12:48:43.469669 <6>[ 0.937351] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10551 12:48:43.473271 <6>[ 0.944964] io scheduler mq-deadline registered
10552 12:48:43.476172 <6>[ 0.949747] io scheduler kyber registered
10553 12:48:43.494632 <6>[ 0.966486] EINJ: ACPI disabled.
10554 12:48:43.526623 <4>[ 0.991540] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10555 12:48:43.536556 <4>[ 1.002190] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10556 12:48:43.551265 <6>[ 1.022942] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10557 12:48:43.559470 <6>[ 1.031015] printk: console [ttyS0] disabled
10558 12:48:43.587485 <6>[ 1.055687] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10559 12:48:43.594106 <6>[ 1.065166] printk: console [ttyS0] enabled
10560 12:48:43.597582 <6>[ 1.065166] printk: console [ttyS0] enabled
10561 12:48:43.604374 <6>[ 1.074061] printk: bootconsole [mtk8250] disabled
10562 12:48:43.607545 <6>[ 1.074061] printk: bootconsole [mtk8250] disabled
10563 12:48:43.614114 <6>[ 1.085382] SuperH (H)SCI(F) driver initialized
10564 12:48:43.617358 <6>[ 1.090676] msm_serial: driver initialized
10565 12:48:43.631678 <6>[ 1.099618] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10566 12:48:43.641698 <6>[ 1.108164] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10567 12:48:43.648060 <6>[ 1.116706] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10568 12:48:43.657981 <6>[ 1.125334] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10569 12:48:43.667702 <6>[ 1.134040] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10570 12:48:43.674014 <6>[ 1.142752] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10571 12:48:43.684107 <6>[ 1.151293] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10572 12:48:43.690749 <6>[ 1.160108] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10573 12:48:43.700309 <6>[ 1.168652] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10574 12:48:43.712849 <6>[ 1.184590] loop: module loaded
10575 12:48:43.719422 <6>[ 1.190614] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10576 12:48:43.742706 <4>[ 1.214003] mtk-pmic-keys: Failed to locate of_node [id: -1]
10577 12:48:43.749356 <6>[ 1.220800] megasas: 07.719.03.00-rc1
10578 12:48:43.758953 <6>[ 1.230368] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10579 12:48:43.771067 <6>[ 1.242492] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10580 12:48:43.788056 <6>[ 1.259262] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10581 12:48:43.844845 <6>[ 1.309593] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10582 12:48:44.883145 <6>[ 2.355099] Freeing initrd memory: 38288K
10583 12:48:44.894163 <6>[ 2.365367] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10584 12:48:44.904595 <6>[ 2.376173] tun: Universal TUN/TAP device driver, 1.6
10585 12:48:44.908162 <6>[ 2.382214] thunder_xcv, ver 1.0
10586 12:48:44.911410 <6>[ 2.385720] thunder_bgx, ver 1.0
10587 12:48:44.914301 <6>[ 2.389232] nicpf, ver 1.0
10588 12:48:44.924737 <6>[ 2.393230] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10589 12:48:44.928275 <6>[ 2.400706] hns3: Copyright (c) 2017 Huawei Corporation.
10590 12:48:44.931216 <6>[ 2.406292] hclge is initializing
10591 12:48:44.938025 <6>[ 2.409865] e1000: Intel(R) PRO/1000 Network Driver
10592 12:48:44.944594 <6>[ 2.414994] e1000: Copyright (c) 1999-2006 Intel Corporation.
10593 12:48:44.948162 <6>[ 2.421006] e1000e: Intel(R) PRO/1000 Network Driver
10594 12:48:44.954647 <6>[ 2.426221] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10595 12:48:44.961078 <6>[ 2.432408] igb: Intel(R) Gigabit Ethernet Network Driver
10596 12:48:44.967699 <6>[ 2.438057] igb: Copyright (c) 2007-2014 Intel Corporation.
10597 12:48:44.974669 <6>[ 2.443896] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10598 12:48:44.980868 <6>[ 2.450414] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10599 12:48:44.984189 <6>[ 2.456870] sky2: driver version 1.30
10600 12:48:44.990826 <6>[ 2.461841] VFIO - User Level meta-driver version: 0.3
10601 12:48:44.998069 <6>[ 2.470030] usbcore: registered new interface driver usb-storage
10602 12:48:45.004672 <6>[ 2.476484] usbcore: registered new device driver onboard-usb-hub
10603 12:48:45.013961 <6>[ 2.485527] mt6397-rtc mt6359-rtc: registered as rtc0
10604 12:48:45.023402 <6>[ 2.490987] mt6397-rtc mt6359-rtc: setting system clock to 2023-07-20T12:48:48 UTC (1689857328)
10605 12:48:45.026907 <6>[ 2.500544] i2c_dev: i2c /dev entries driver
10606 12:48:45.043562 <6>[ 2.512187] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10607 12:48:45.050216 <6>[ 2.522405] sdhci: Secure Digital Host Controller Interface driver
10608 12:48:45.057218 <6>[ 2.528844] sdhci: Copyright(c) Pierre Ossman
10609 12:48:45.064022 <6>[ 2.534230] Synopsys Designware Multimedia Card Interface Driver
10610 12:48:45.066986 <6>[ 2.540841] mmc0: CQHCI version 5.10
10611 12:48:45.074016 <6>[ 2.541375] sdhci-pltfm: SDHCI platform and OF driver helper
10612 12:48:45.080997 <6>[ 2.552695] ledtrig-cpu: registered to indicate activity on CPUs
10613 12:48:45.091368 <6>[ 2.560019] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10614 12:48:45.094944 <6>[ 2.567398] usbcore: registered new interface driver usbhid
10615 12:48:45.101649 <6>[ 2.573224] usbhid: USB HID core driver
10616 12:48:45.108295 <6>[ 2.577466] spi_master spi0: will run message pump with realtime priority
10617 12:48:45.153098 <6>[ 2.618260] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10618 12:48:45.172426 <6>[ 2.633788] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10619 12:48:45.175145 <6>[ 2.647372] mmc0: Command Queue Engine enabled
10620 12:48:45.182338 <6>[ 2.652118] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10621 12:48:45.188705 <6>[ 2.659277] cros-ec-spi spi0.0: Chrome EC device registered
10622 12:48:45.191976 <6>[ 2.659600] mmcblk0: mmc0:0001 DA4128 116 GiB
10623 12:48:45.203652 <6>[ 2.675236] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10624 12:48:45.210556 <6>[ 2.682589] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10625 12:48:45.217216 <6>[ 2.688680] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10626 12:48:45.223644 <6>[ 2.694775] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10627 12:48:45.233837 <6>[ 2.696568] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10628 12:48:45.241012 <6>[ 2.712715] NET: Registered PF_PACKET protocol family
10629 12:48:45.244180 <6>[ 2.718132] 9pnet: Installing 9P2000 support
10630 12:48:45.251121 <5>[ 2.722726] Key type dns_resolver registered
10631 12:48:45.254057 <6>[ 2.727896] registered taskstats version 1
10632 12:48:45.260776 <5>[ 2.732319] Loading compiled-in X.509 certificates
10633 12:48:45.295932 <4>[ 2.761085] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10634 12:48:45.305796 <4>[ 2.771817] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10635 12:48:45.316193 <3>[ 2.784799] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10636 12:48:45.328398 <6>[ 2.800258] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10637 12:48:45.334933 <6>[ 2.806998] xhci-mtk 11200000.usb: xHCI Host Controller
10638 12:48:45.342023 <6>[ 2.812503] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10639 12:48:45.351911 <6>[ 2.820358] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10640 12:48:45.358643 <6>[ 2.829787] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10641 12:48:45.364923 <6>[ 2.835888] xhci-mtk 11200000.usb: xHCI Host Controller
10642 12:48:45.371695 <6>[ 2.841497] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10643 12:48:45.378266 <6>[ 2.849165] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10644 12:48:45.385164 <6>[ 2.857059] hub 1-0:1.0: USB hub found
10645 12:48:45.388656 <6>[ 2.861094] hub 1-0:1.0: 1 port detected
10646 12:48:45.398263 <6>[ 2.865444] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10647 12:48:45.401947 <6>[ 2.874242] hub 2-0:1.0: USB hub found
10648 12:48:45.404728 <6>[ 2.878278] hub 2-0:1.0: 1 port detected
10649 12:48:45.413441 <6>[ 2.885522] mtk-msdc 11f70000.mmc: Got CD GPIO
10650 12:48:45.430901 <6>[ 2.899694] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10651 12:48:45.437522 <6>[ 2.907844] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10652 12:48:45.447973 <4>[ 2.915828] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10653 12:48:45.457590 <6>[ 2.925537] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10654 12:48:45.464426 <6>[ 2.933630] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10655 12:48:45.474173 <6>[ 2.941691] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10656 12:48:45.480899 <6>[ 2.949615] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10657 12:48:45.487325 <6>[ 2.957470] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10658 12:48:45.497472 <6>[ 2.965295] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10659 12:48:45.507360 <6>[ 2.976077] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10660 12:48:45.517115 <6>[ 2.984446] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10661 12:48:45.523748 <6>[ 2.992842] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10662 12:48:45.533933 <6>[ 3.001190] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10663 12:48:45.540700 <6>[ 3.009561] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10664 12:48:45.550245 <6>[ 3.017910] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10665 12:48:45.557463 <6>[ 3.026281] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10666 12:48:45.567182 <6>[ 3.034627] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10667 12:48:45.573976 <6>[ 3.042993] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10668 12:48:45.583705 <6>[ 3.051339] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10669 12:48:45.589948 <6>[ 3.059684] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10670 12:48:45.599974 <6>[ 3.068029] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10671 12:48:45.606413 <6>[ 3.076374] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10672 12:48:45.616553 <6>[ 3.084719] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10673 12:48:45.623231 <6>[ 3.093064] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10674 12:48:45.629871 <6>[ 3.102000] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10675 12:48:45.637556 <6>[ 3.109448] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10676 12:48:45.644656 <6>[ 3.116468] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10677 12:48:45.654779 <6>[ 3.123563] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10678 12:48:45.661697 <6>[ 3.130826] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10679 12:48:45.671346 <6>[ 3.137720] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10680 12:48:45.678360 <6>[ 3.146868] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10681 12:48:45.688319 <6>[ 3.156032] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10682 12:48:45.697988 <6>[ 3.165347] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10683 12:48:45.707557 <6>[ 3.174826] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10684 12:48:45.718035 <6>[ 3.184302] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10685 12:48:45.727555 <6>[ 3.193429] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10686 12:48:45.734194 <6>[ 3.202904] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10687 12:48:45.743899 <6>[ 3.212033] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10688 12:48:45.754145 <6>[ 3.221335] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10689 12:48:45.764204 <6>[ 3.231501] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10690 12:48:45.774651 <6>[ 3.243448] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10691 12:48:45.794438 <6>[ 3.263404] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10692 12:48:45.822204 <6>[ 3.293889] hub 2-1:1.0: USB hub found
10693 12:48:45.825118 <6>[ 3.298291] hub 2-1:1.0: 3 ports detected
10694 12:48:45.946503 <6>[ 3.415388] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10695 12:48:46.101006 <6>[ 3.572624] hub 1-1:1.0: USB hub found
10696 12:48:46.104508 <6>[ 3.577124] hub 1-1:1.0: 4 ports detected
10697 12:48:46.183086 <6>[ 3.651570] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10698 12:48:46.427295 <6>[ 3.895395] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10699 12:48:46.560503 <6>[ 4.031688] hub 1-1.4:1.0: USB hub found
10700 12:48:46.563550 <6>[ 4.036352] hub 1-1.4:1.0: 2 ports detected
10701 12:48:46.862900 <6>[ 4.331387] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10702 12:48:47.054676 <6>[ 4.523390] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10703 12:48:58.055978 <6>[ 15.531951] ALSA device list:
10704 12:48:58.062567 <6>[ 15.535208] No soundcards found.
10705 12:48:58.074601 <6>[ 15.547631] Freeing unused kernel memory: 8384K
10706 12:48:58.078301 <6>[ 15.552507] Run /init as init process
10707 12:48:58.107548 <6>[ 15.580705] NET: Registered PF_INET6 protocol family
10708 12:48:58.114323 <6>[ 15.587223] Segment Routing with IPv6
10709 12:48:58.117427 <6>[ 15.591184] In-situ OAM (IOAM) with IPv6
10710 12:48:58.152197 <30>[ 15.605759] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10711 12:48:58.155721 <30>[ 15.629464] systemd[1]: Detected architecture arm64.
10712 12:48:58.155886
10713 12:48:58.162270 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10714 12:48:58.162454
10715 12:48:58.178135 <30>[ 15.651546] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10716 12:48:58.326207 <30>[ 15.796349] systemd[1]: Queued start job for default target Graphical Interface.
10717 12:48:58.380154 <30>[ 15.852756] systemd[1]: Created slice system-getty.slice.
10718 12:48:58.386446 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10719 12:48:58.403618 <30>[ 15.876067] systemd[1]: Created slice system-modprobe.slice.
10720 12:48:58.410135 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10721 12:48:58.427105 <30>[ 15.899923] systemd[1]: Created slice system-serial\x2dgetty.slice.
10722 12:48:58.437400 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10723 12:48:58.451300 <30>[ 15.923805] systemd[1]: Created slice User and Session Slice.
10724 12:48:58.457286 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10725 12:48:58.478651 <30>[ 15.947915] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10726 12:48:58.488099 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10727 12:48:58.505873 <30>[ 15.975553] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10728 12:48:58.512172 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10729 12:48:58.532957 <30>[ 15.999471] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10730 12:48:58.539521 <30>[ 16.011504] systemd[1]: Reached target Local Encrypted Volumes.
10731 12:48:58.546375 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10732 12:48:58.562884 <30>[ 16.035772] systemd[1]: Reached target Paths.
10733 12:48:58.566302 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10734 12:48:58.582657 <30>[ 16.055433] systemd[1]: Reached target Remote File Systems.
10735 12:48:58.589148 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10736 12:48:58.602134 <30>[ 16.075416] systemd[1]: Reached target Slices.
10737 12:48:58.605938 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10738 12:48:58.622531 <30>[ 16.095448] systemd[1]: Reached target Swap.
10739 12:48:58.625983 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10740 12:48:58.646179 <30>[ 16.115638] systemd[1]: Listening on initctl Compatibility Named Pipe.
10741 12:48:58.652381 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10742 12:48:58.658942 <30>[ 16.130316] systemd[1]: Listening on Journal Audit Socket.
10743 12:48:58.665744 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10744 12:48:58.678656 <30>[ 16.151680] systemd[1]: Listening on Journal Socket (/dev/log).
10745 12:48:58.685362 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10746 12:48:58.703309 <30>[ 16.176166] systemd[1]: Listening on Journal Socket.
10747 12:48:58.709429 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10748 12:48:58.726267 <30>[ 16.195815] systemd[1]: Listening on Network Service Netlink Socket.
10749 12:48:58.732682 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10750 12:48:58.747216 <30>[ 16.220166] systemd[1]: Listening on udev Control Socket.
10751 12:48:58.753584 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10752 12:48:58.770551 <30>[ 16.244098] systemd[1]: Listening on udev Kernel Socket.
10753 12:48:58.777475 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10754 12:48:58.814231 <30>[ 16.287725] systemd[1]: Mounting Huge Pages File System...
10755 12:48:58.820546 Mounting [0;1;39mHuge Pages File System[0m...
10756 12:48:58.917082 <30>[ 16.309466] systemd[1]: Mounting POSIX Message Queue File System...
10757 12:48:58.917839 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10758 12:48:58.918357 <30>[ 16.333591] systemd[1]: Mounting Kernel Debug File System...
10759 12:48:58.918846 Mounting [0;1;39mKernel Debug File System[0m...
10760 12:48:58.919413 <30>[ 16.355639] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10761 12:48:58.919955 <30>[ 16.366566] systemd[1]: Starting Create list of static device nodes for the current kernel...
10762 12:48:58.920480 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10763 12:48:58.922142 <30>[ 16.393846] systemd[1]: Starting Load Kernel Module configfs...
10764 12:48:58.927027 Starting [0;1;39mLoad Kernel Module configfs[0m...
10765 12:48:58.944945 <30>[ 16.417861] systemd[1]: Starting Load Kernel Module drm...
10766 12:48:58.951112 Starting [0;1;39mLoad Kernel Module drm[0m...
10767 12:48:58.969091 <30>[ 16.439609] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10768 12:48:59.002644 <30>[ 16.475943] systemd[1]: Starting Journal Service...
10769 12:48:59.005605 Starting [0;1;39mJournal Service[0m...
10770 12:48:59.024656 <30>[ 16.498203] systemd[1]: Starting Load Kernel Modules...
10771 12:48:59.031379 Starting [0;1;39mLoad Kernel Modules[0m...
10772 12:48:59.052119 <30>[ 16.522086] systemd[1]: Starting Remount Root and Kernel File Systems...
10773 12:48:59.058583 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10774 12:48:59.072182 <30>[ 16.545805] systemd[1]: Starting Coldplug All udev Devices...
10775 12:48:59.078638 Starting [0;1;39mColdplug All udev Devices[0m...
10776 12:48:59.096486 <30>[ 16.569888] systemd[1]: Mounted Huge Pages File System.
10777 12:48:59.103243 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10778 12:48:59.118829 <30>[ 16.591999] systemd[1]: Started Journal Service.
10779 12:48:59.124993 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10780 12:48:59.139766 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10781 12:48:59.155456 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10782 12:48:59.178637 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10783 12:48:59.199579 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10784 12:48:59.215954 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10785 12:48:59.231300 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10786 12:48:59.251644 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10787 12:48:59.269823 See 'systemctl status systemd-remount-fs.service' for details.
10788 12:48:59.310947 Mounting [0;1;39mKernel Configuration File System[0m...
10789 12:48:59.333094 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10790 12:48:59.349877 <46>[ 16.820270] systemd-journald[175]: Received client request to flush runtime journal.
10791 12:48:59.358986 Starting [0;1;39mLoad/Save Random Seed[0m...
10792 12:48:59.381096 Starting [0;1;39mApply Kernel Variables[0m...
10793 12:48:59.400946 Starting [0;1;39mCreate System Users[0m...
10794 12:48:59.420823 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10795 12:48:59.446077 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10796 12:48:59.458981 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10797 12:48:59.478805 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10798 12:48:59.498645 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10799 12:48:59.518578 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10800 12:48:59.566819 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10801 12:48:59.587976 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10802 12:48:59.602019 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10803 12:48:59.617752 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10804 12:48:59.678340 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10805 12:48:59.701845 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10806 12:48:59.722869 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10807 12:48:59.743029 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10808 12:48:59.786806 Starting [0;1;39mNetwork Service[0m...
10809 12:48:59.808220 Starting [0;1;39mNetwork Time Synchronization[0m...
10810 12:48:59.826582 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10811 12:48:59.861234 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10812 12:48:59.875755 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10813 12:48:59.920678 <6>[ 17.391091] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10814 12:48:59.932753 <6>[ 17.405927] remoteproc remoteproc0: scp is available
10815 12:48:59.939224 <6>[ 17.411626] remoteproc remoteproc0: powering up scp
10816 12:48:59.949665 Startin<6>[ 17.419992] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10817 12:48:59.959256 g [0;1;39mNetwork Name Resoluti<6>[ 17.432246] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10818 12:48:59.959441 on[0m...
10819 12:48:59.973967 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronizatio<6>[ 17.446496] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10820 12:48:59.977396 n[0m.
10821 12:48:59.983782 <6>[ 17.454420] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10822 12:48:59.994935 <6>[ 17.465034] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10823 12:49:00.010828 [[0;32m OK [0m] Found device [0;1;39m/dev/t<3>[ 17.481287] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10824 12:49:00.010964 tyS0[0m.
10825 12:49:00.020608 <3>[ 17.490493] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10826 12:49:00.027239 <3>[ 17.499338] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10827 12:49:00.037566 <6>[ 17.503483] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10828 12:49:00.044122 <3>[ 17.507572] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10829 12:49:00.050775 <6>[ 17.519231] usbcore: registered new interface driver r8152
10830 12:49:00.057139 <3>[ 17.523373] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10831 12:49:00.067550 <3>[ 17.523396] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10832 12:49:00.073581 <3>[ 17.523428] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10833 12:49:00.083519 <3>[ 17.523443] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10834 12:49:00.087367 <6>[ 17.545805] mc: Linux media interface: v0.10
10835 12:49:00.093811 <4>[ 17.555531] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10836 12:49:00.103556 <3>[ 17.558123] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10837 12:49:00.110395 <3>[ 17.558225] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10838 12:49:00.120032 <3>[ 17.558234] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10839 12:49:00.126375 <3>[ 17.558242] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10840 12:49:00.136944 <3>[ 17.558575] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10841 12:49:00.143639 <3>[ 17.558587] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10842 12:49:00.153613 <3>[ 17.558596] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10843 12:49:00.159705 <3>[ 17.558608] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10844 12:49:00.170182 <3>[ 17.558615] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10845 12:49:00.176196 <3>[ 17.558666] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10846 12:49:00.186375 <6>[ 17.567359] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10847 12:49:00.193008 <6>[ 17.567370] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10848 12:49:00.199593 <4>[ 17.574057] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10849 12:49:00.206203 <6>[ 17.581704] remoteproc remoteproc0: remote processor scp is now up
10850 12:49:00.212709 <6>[ 17.592864] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10851 12:49:00.219328 <6>[ 17.608052] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10852 12:49:00.226475 <6>[ 17.614825] pci_bus 0000:00: root bus resource [bus 00-ff]
10853 12:49:00.233604 <4>[ 17.629166] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10854 12:49:00.240269 <4>[ 17.629166] Fallback method does not support PEC.
10855 12:49:00.246798 <6>[ 17.630845] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10856 12:49:00.257291 <6>[ 17.632037] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10857 12:49:00.264611 <6>[ 17.632484] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10858 12:49:00.274367 <4>[ 17.642992] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10859 12:49:00.284945 <6>[ 17.647481] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10860 12:49:00.291559 <4>[ 17.656209] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10861 12:49:00.298505 <6>[ 17.664046] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10862 12:49:00.308562 <6>[ 17.671036] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10863 12:49:00.315410 <6>[ 17.678671] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10864 12:49:00.321741 <6>[ 17.687311] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10865 12:49:00.328865 <6>[ 17.691692] pci 0000:00:00.0: supports D1 D2
10866 12:49:00.338705 <6>[ 17.706657] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10867 12:49:00.345417 <3>[ 17.713040] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10868 12:49:00.355510 <3>[ 17.713802] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6
10869 12:49:00.359098 <6>[ 17.715208] r8152 2-1.3:1.0 eth0: v1.12.13
10870 12:49:00.365746 <6>[ 17.718149] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10871 12:49:00.372492 <6>[ 17.720236] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10872 12:49:00.379321 <6>[ 17.745566] videodev: Linux video capture interface: v2.00
10873 12:49:00.389600 <3>[ 17.747061] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10874 12:49:00.396398 <3>[ 17.747764] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
10875 12:49:00.402928 <6>[ 17.753636] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10876 12:49:00.409666 <6>[ 17.753892] usbcore: registered new interface driver cdc_ether
10877 12:49:00.419252 <3>[ 17.761067] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10878 12:49:00.422997 <6>[ 17.764904] usbcore: registered new interface driver r8153_ecm
10879 12:49:00.429869 <6>[ 17.771529] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10880 12:49:00.436932 <6>[ 17.772216] Bluetooth: Core ver 2.22
10881 12:49:00.440086 <6>[ 17.772280] NET: Registered PF_BLUETOOTH protocol family
10882 12:49:00.446279 <6>[ 17.772282] Bluetooth: HCI device and connection manager initialized
10883 12:49:00.453370 <6>[ 17.772306] Bluetooth: HCI socket layer initialized
10884 12:49:00.457457 <6>[ 17.772312] Bluetooth: L2CAP socket layer initialized
10885 12:49:00.463874 <6>[ 17.772323] Bluetooth: SCO socket layer initialized
10886 12:49:00.470441 <3>[ 17.782627] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10887 12:49:00.478125 <6>[ 17.786046] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10888 12:49:00.484908 <6>[ 17.790469] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10889 12:49:00.491593 <6>[ 17.816796] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10890 12:49:00.501767 <3>[ 17.820776] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 12:49:00.508912 <6>[ 17.824416] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10892 12:49:00.515239 <6>[ 17.833606] usbcore: registered new interface driver btusb
10893 12:49:00.522401 <6>[ 17.833929] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10894 12:49:00.532588 <6>[ 17.834107] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10895 12:49:00.542372 <4>[ 17.834202] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10896 12:49:00.548954 <3>[ 17.834213] Bluetooth: hci0: Failed to load firmware file (-2)
10897 12:49:00.555780 <3>[ 17.834218] Bluetooth: hci0: Failed to set up firmware (-2)
10898 12:49:00.565243 <4>[ 17.834222] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10899 12:49:00.571951 <6>[ 17.834338] usbcore: registered new interface driver uvcvideo
10900 12:49:00.575735 <6>[ 17.837239] pci 0000:01:00.0: supports D1 D2
10901 12:49:00.585621 <3>[ 17.842282] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 12:49:00.595603 <3>[ 17.862485] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 12:49:00.602040 <6>[ 17.866747] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10904 12:49:00.608778 <6>[ 17.879489] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10905 12:49:00.615350 <3>[ 17.902534] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 12:49:00.625153 <6>[ 17.910003] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10907 12:49:00.631306 <6>[ 18.103304] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10908 12:49:00.641026 <6>[ 18.103320] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10909 12:49:00.647877 <6>[ 18.103337] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10910 12:49:00.657957 <6>[ 18.103353] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10911 12:49:00.661062 <6>[ 18.135345] pci 0000:00:00.0: PCI bridge to [bus 01]
10912 12:49:00.671044 <6>[ 18.140574] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10913 12:49:00.677881 [[0;32m OK [<6>[ 18.148776] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10914 12:49:00.684572 0m] Created slic<6>[ 18.157403] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10915 12:49:00.690945 e [0;1;39msyste<6>[ 18.164531] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10916 12:49:00.693866 m-systemd\x2dbacklight.slice[0m.
10917 12:49:00.713478 <5>[ 18.183960] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10918 12:49:00.719967 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10919 12:49:00.732946 <5>[ 18.203074] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10920 12:49:00.739282 <4>[ 18.210126] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10921 12:49:00.746130 <6>[ 18.219034] cfg80211: failed to load regulatory.db
10922 12:49:00.752631 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10923 12:49:00.793014 <6>[ 18.263048] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10924 12:49:00.799744 <6>[ 18.270561] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10925 12:49:00.805946 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10926 12:49:00.823572 <6>[ 18.297388] mt7921e 0000:01:00.0: ASIC revision: 79610010
10927 12:49:00.830424 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10928 12:49:00.849686 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10929 12:49:00.931833 <4>[ 18.398884] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10930 12:49:01.028350 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10931 12:49:01.052159 [[0;32m OK [0m] Reached targ<4>[ 18.517638] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10932 12:49:01.052286 et [0;1;39mNetwork[0m.
10933 12:49:01.073903 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10934 12:49:01.085964 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10935 12:49:01.105545 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10936 12:49:01.120772 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10937 12:49:01.133875 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10938 12:49:01.154028 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10939 12:49:01.171105 <4>[ 18.638426] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10940 12:49:01.179448 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10941 12:49:01.198081 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10942 12:49:01.221678 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10943 12:49:01.262751 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10944 12:49:01.292173 <4>[ 18.759494] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10945 12:49:01.303200 Starting [0;1;39mUser Login Management[0m...
10946 12:49:01.320166 Starting [0;1;39mPermit User Sessions[0m...
10947 12:49:01.337833 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10948 12:49:01.354549 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10949 12:49:01.375764 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10950 12:49:01.414150 <4>[ 18.881664] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10951 12:49:01.432056 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10952 12:49:01.448765 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10953 12:49:01.465588 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10954 12:49:01.486923 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10955 12:49:01.506398 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10956 12:49:01.535969 [[0;32m OK [0m] Reached targ<4>[ 19.002227] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10957 12:49:01.538876 et [0;1;39mGraphical Interface[0m.
10958 12:49:01.594000 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10959 12:49:01.617869 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10960 12:49:01.643972
10961 12:49:01.644127
10962 12:49:01.646901 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10963 12:49:01.646976
10964 12:49:01.660083 debian-bul<4>[ 19.126161] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10965 12:49:01.663766 lseye-arm64 login: root (automatic login)
10966 12:49:01.663870
10967 12:49:01.663935
10968 12:49:01.669890 Linux debian-bullseye-arm64 6.1.38-cip1 #1 SMP PREEMPT Thu Jul 20 12:35:57 UTC 2023 aarch64
10969 12:49:01.670008
10970 12:49:01.676452 The programs included with the Debian GNU/Linux system are free software;
10971 12:49:01.683121 the exact distribution terms for each program are described in the
10972 12:49:01.690013 individual files in /usr/share/doc/*/copyright.
10973 12:49:01.690149
10974 12:49:01.692911 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10975 12:49:01.696480 permitted by applicable law.
10976 12:49:01.696833 Matched prompt #10: / #
10978 12:49:01.697048 Setting prompt string to ['/ #']
10979 12:49:01.697141 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10981 12:49:01.697345 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10982 12:49:01.697448 start: 2.2.6 expect-shell-connection (timeout 00:02:57) [common]
10983 12:49:01.697519 Setting prompt string to ['/ #']
10984 12:49:01.697600 Forcing a shell prompt, looking for ['/ #']
10986 12:49:01.747815 / #
10987 12:49:01.748029 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10988 12:49:01.748156 Waiting using forced prompt support (timeout 00:02:30)
10989 12:49:01.753444
10990 12:49:01.753744 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10991 12:49:01.753840 start: 2.2.7 export-device-env (timeout 00:02:57) [common]
10992 12:49:01.753934 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10993 12:49:01.754035 end: 2.2 depthcharge-retry (duration 00:02:03) [common]
10994 12:49:01.754124 end: 2 depthcharge-action (duration 00:02:03) [common]
10995 12:49:01.754225 start: 3 lava-test-retry (timeout 00:07:37) [common]
10996 12:49:01.754309 start: 3.1 lava-test-shell (timeout 00:07:37) [common]
10997 12:49:01.754391 Using namespace: common
10999 12:49:01.854708 / # #
11000 12:49:01.854888 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11001 12:49:01.855037 <4>[ 19.249982] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11002 12:49:01.859910 #
11003 12:49:01.860205 Using /lava-11118918
11005 12:49:01.960519 / # export SHELL=/bin/sh
11006 12:49:01.960895 <4>[ 19.369947] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11007 12:49:02.003474 export SHELL=/bin/sh<6>[ 19.435527] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
11008 12:49:02.003634
11009 12:49:02.003734 <6>[ 19.443709] r8152 2-1.3:1.0 enx0024323078ff: carrier on
11011 12:49:02.104226 / # . /lava-11118918/environment
11012 12:49:02.104439 <4>[ 19.490015] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11013 12:49:02.109453 . /lava-11118918/environment
11015 12:49:02.209934 / # /lava-11118918/bin/lava-test-runner /lava-11118918/0
11016 12:49:02.210100 Test shell timeout: 10s (minimum of the action and connection timeout)
11017 12:49:02.210444 <3>[ 19.608659] mt7921e 0000:01:00.0: hardware init failed
11018 12:49:02.214466 /lava-11118918/bin/lava-test-runner /lava-11118918/0
11019 12:49:02.255471 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11020 12:49:02.255588 + cd /lava-11118918/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11021 12:49:02.255657 + cat uuid
11022 12:49:02.255904 + UUID=11118918_1.5.2.3.1
11023 12:49:02.255970 + set +x
11024 12:49:02.256030 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 11118918_1.5.2.3.1>
11025 12:49:02.256271 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 11118918_1.5.2.3.1
11026 12:49:02.256342 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (11118918_1.5.2.3.1)
11027 12:49:02.256426 Skipping test definition patterns.
11028 12:49:02.256773 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11029 12:49:02.263431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11030 12:49:02.263677 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11032 12:49:02.270172 d<4>[ 19.741035] use of bytesused == 0 is deprecated and will be removed in the future,
11033 12:49:02.276502 evice: /dev/vide<4>[ 19.749442] use the actual size instead.
11034 12:49:02.276582 o2
11035 12:49:02.283039 <4>[ 19.756340] ------------[ cut here ]------------
11036 12:49:02.289647 <4>[ 19.761277] get_vaddr_frames() cannot follow VM_IO mapping
11037 12:49:02.299824 <4>[ 19.761438] WARNING: CPU: 3 PID: 309 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11038 12:49:02.349433 <4>[ 19.779539] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 cfg80211 btusb mtk_vcodec_enc mtk_vcodec_common btintel mtk_vpu uvcvideo v4l2_mem2mem videobuf2_dma_contig videobuf2_vmalloc btmtk btrtl videobuf2_memops videobuf2_v4l2 btbcm videobuf2_common bluetooth r8153_ecm cdc_ether ecdh_generic videodev usbnet ecc cros_ec_rpmsg crct10dif_ce elants_i2c mc rfkill r8152 elan_i2c sbs_battery hid_google_hammer hid_vivaldi_common cros_ec_typec cros_ec_chardev pcie_mediatek_gen3 mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11039 12:49:02.356108 <4>[ 19.828924] CPU: 3 PID: 309 Comm: v4l2-compliance Not tainted 6.1.38-cip1 #1
11040 12:49:02.362773 <4>[ 19.836222] Hardware name: Google Spherion (rev0 - 3) (DT)
11041 12:49:02.369317 <4>[ 19.841957] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11042 12:49:02.375631 <4>[ 19.849168] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11043 12:49:02.382614 <4>[ 19.855259] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11044 12:49:02.385580 <4>[ 19.861349] sp : ffff8000091e3850
11045 12:49:02.392259 <4>[ 19.864912] x29: ffff8000091e3850 x28: ffffc640f023c000 x27: ffffc640f0238238
11046 12:49:02.401966 <4>[ 19.872299] x26: 0000000000000000 x25: ffffc640fdb856b8 x24: ffff61f0ce579298
11047 12:49:02.409011 <4>[ 19.879686] x23: ffff61f0c175e400 x22: ffff61f0c0d48010 x21: 0000000000000000
11048 12:49:02.415079 <4>[ 19.887073] x20: 00000000fffffff2 x19: ffff61f0cc953400 x18: fffffffffffe95c8
11049 12:49:02.421955 <4>[ 19.894460] x17: 0000000000000000 x16: ffffc640fba8bb40 x15: 0000000000000038
11050 12:49:02.431776 <4>[ 19.901847] x14: 000000000000004e x13: 0000000000000001 x12: 0000000000000001
11051 12:49:02.438902 <4>[ 19.909234] x11: 0000000000000000 x10: 0000000000000a60 x9 : ffff8000091e3700
11052 12:49:02.445402 <4>[ 19.916620] x8 : ffff61f0ccafc5c0 x7 : ffff61f1fef5be40 x6 : 00000000ffffffff
11053 12:49:02.451664 <4>[ 19.924006] x5 : 00000000410fd050 x4 : 0000000000c0000e x3 : 0000000000200000
11054 12:49:02.458932 <4>[ 19.931393] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff61f0ccafbb00
11055 12:49:02.461857 <4>[ 19.938780] Call trace:
11056 12:49:02.468240 <4>[ 19.941476] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11057 12:49:02.475037 <4>[ 19.947220] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11058 12:49:02.481566 <4>[ 19.953225] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11059 12:49:02.488400 <4>[ 19.959576] __prepare_userptr+0x280/0x410 [videobuf2_common]
11060 12:49:02.491315 <4>[ 19.965579] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11061 12:49:02.497995 <4>[ 19.971235] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11062 12:49:02.504989 <4>[ 19.977411] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11063 12:49:02.511626 <4>[ 19.982912] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11064 12:49:02.514889 <4>[ 19.988687] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11065 12:49:02.521318 <4>[ 19.994952] v4l_prepare_buf+0x48/0x60 [videodev]
11066 12:49:02.527899 <4>[ 19.999973] __video_do_ioctl+0x184/0x3d0 [videodev]
11067 12:49:02.531112 <4>[ 20.005216] video_usercopy+0x358/0x680 [videodev]
11068 12:49:02.534344 <4>[ 20.010286] video_ioctl2+0x18/0x30 [videodev]
11069 12:49:02.541086 <4>[ 20.015009] v4l2_ioctl+0x40/0x60 [videodev]
11070 12:49:02.544516 <4>[ 20.019558] __arm64_sys_ioctl+0xa8/0xf0
11071 12:49:02.548003 <4>[ 20.023739] invoke_syscall+0x48/0x114
11072 12:49:02.554269 <4>[ 20.027744] el0_svc_common.constprop.0+0x44/0xec
11073 12:49:02.557865 <4>[ 20.032699] do_el0_svc+0x2c/0xd0
11074 12:49:02.561004 <4>[ 20.036265] el0_svc+0x2c/0x84
11075 12:49:02.564524 <4>[ 20.039572] el0t_64_sync_handler+0xb8/0xc0
11076 12:49:02.567609 <4>[ 20.044007] el0t_64_sync+0x18c/0x190
11077 12:49:02.574287 <4>[ 20.047920] ---[ end trace 0000000000000000 ]---
11078 12:49:02.587592 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11079 12:49:02.596790 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11080 12:49:02.603129
11081 12:49:02.615305 Compliance test for mtk-vcodec-enc device /dev/video2:
11082 12:49:02.620851
11083 12:49:02.629490 Driver Info:
11084 12:49:02.639139 Driver name : mtk-vcodec-enc
11085 12:49:02.651598 Card type : MT8192 video encoder
11086 12:49:02.660759 Bus info : platform:17020000.vcodec
11087 12:49:02.666660 Driver version : 6.1.38
11088 12:49:02.676435 Capabilities : 0x84204000
11089 12:49:02.685775 Video Memory-to-Memory Multiplanar
11090 12:49:02.695027 Streaming
11091 12:49:02.704476 Extended Pix Format
11092 12:49:02.714281 Device Capabilities
11093 12:49:02.722835 Device Caps : 0x04204000
11094 12:49:02.732736 Video Memory-to-Memory Multiplanar
11095 12:49:02.741073 Streaming
11096 12:49:02.750312 Extended Pix Format
11097 12:49:02.760179 Detected Stateful Encoder
11098 12:49:02.769572
11099 12:49:02.779363 Required ioctls:
11100 12:49:02.792882 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11101 12:49:02.792989 test VIDIOC_QUERYCAP: OK
11102 12:49:02.793269 Received signal: <TESTSET> START Required-ioctls
11103 12:49:02.793377 Starting test_set Required-ioctls
11104 12:49:02.818297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11105 12:49:02.818589 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11107 12:49:02.820868 test invalid ioctls: OK
11108 12:49:02.842411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11109 12:49:02.842522
11110 12:49:02.842788 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11112 12:49:02.852585 Allow for multiple opens:
11113 12:49:02.858583 <LAVA_SIGNAL_TESTSET STOP>
11114 12:49:02.858845 Received signal: <TESTSET> STOP
11115 12:49:02.858941 Closing test_set Required-ioctls
11116 12:49:02.868971 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11117 12:49:02.869241 Received signal: <TESTSET> START Allow-for-multiple-opens
11118 12:49:02.869337 Starting test_set Allow-for-multiple-opens
11119 12:49:02.871943 test second /dev/video2 open: OK
11120 12:49:02.891984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11121 12:49:02.892260 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11123 12:49:02.895120 test VIDIOC_QUERYCAP: OK
11124 12:49:02.912662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11125 12:49:02.912940 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11127 12:49:02.915847 test VIDIOC_G/S_PRIORITY: OK
11128 12:49:02.935210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11129 12:49:02.935526 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11131 12:49:02.938755 test for unlimited opens: OK
11132 12:49:02.958731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11133 12:49:02.958840
11134 12:49:02.959109 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11136 12:49:02.968179 Debug ioctls:
11137 12:49:02.974385 <LAVA_SIGNAL_TESTSET STOP>
11138 12:49:02.974661 Received signal: <TESTSET> STOP
11139 12:49:02.974761 Closing test_set Allow-for-multiple-opens
11140 12:49:02.984253 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11141 12:49:02.984528 Received signal: <TESTSET> START Debug-ioctls
11142 12:49:02.984625 Starting test_set Debug-ioctls
11143 12:49:02.987874 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11144 12:49:03.006946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11145 12:49:03.007220 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11147 12:49:03.013390 test VIDIOC_LOG_STATUS: OK (Not Supported)
11148 12:49:03.031579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11149 12:49:03.031690
11150 12:49:03.031957 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11152 12:49:03.039278 Input ioctls:
11153 12:49:03.044940 <LAVA_SIGNAL_TESTSET STOP>
11154 12:49:03.045217 Received signal: <TESTSET> STOP
11155 12:49:03.045313 Closing test_set Debug-ioctls
11156 12:49:03.054511 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11157 12:49:03.054789 Received signal: <TESTSET> START Input-ioctls
11158 12:49:03.054887 Starting test_set Input-ioctls
11159 12:49:03.057668 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11160 12:49:03.080865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11161 12:49:03.081204 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11163 12:49:03.083714 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11164 12:49:03.099114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11165 12:49:03.099422 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11167 12:49:03.106121 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11168 12:49:03.122604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11169 12:49:03.122954 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11171 12:49:03.129083 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11172 12:49:03.147337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11173 12:49:03.147650 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11175 12:49:03.150340 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11176 12:49:03.171353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11177 12:49:03.171650 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11179 12:49:03.174977 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11180 12:49:03.198065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11181 12:49:03.198381 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11183 12:49:03.201059 Inputs: 0 Audio Inputs: 0 Tuners: 0
11184 12:49:03.207058
11185 12:49:03.222267 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11186 12:49:03.243581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11187 12:49:03.243943 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11189 12:49:03.250021 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11190 12:49:03.267232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11191 12:49:03.267612 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11193 12:49:03.273576 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11194 12:49:03.291774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11195 12:49:03.292060 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11197 12:49:03.297899 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11198 12:49:03.316072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11199 12:49:03.316324 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11201 12:49:03.323099 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11202 12:49:03.339512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11203 12:49:03.339630
11204 12:49:03.339896 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11206 12:49:03.359057 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11207 12:49:03.380247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11208 12:49:03.381116 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11210 12:49:03.386675 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11211 12:49:03.406475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11212 12:49:03.406739 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11214 12:49:03.409796 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11215 12:49:03.426748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11216 12:49:03.427002 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11218 12:49:03.430494 test VIDIOC_G/S_EDID: OK (Not Supported)
11219 12:49:03.448204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11220 12:49:03.448287
11221 12:49:03.448522 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11223 12:49:03.457098 Control ioctls:
11224 12:49:03.464043 <LAVA_SIGNAL_TESTSET STOP>
11225 12:49:03.464322 Received signal: <TESTSET> STOP
11226 12:49:03.464420 Closing test_set Input-ioctls
11227 12:49:03.472587 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11228 12:49:03.472864 Received signal: <TESTSET> START Control-ioctls
11229 12:49:03.472964 Starting test_set Control-ioctls
11230 12:49:03.475693 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11231 12:49:03.498265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11232 12:49:03.498371 test VIDIOC_QUERYCTRL: OK
11233 12:49:03.498631 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11235 12:49:03.518567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11236 12:49:03.518835 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11238 12:49:03.521384 test VIDIOC_G/S_CTRL: OK
11239 12:49:03.540063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11240 12:49:03.540326 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11242 12:49:03.543195 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11243 12:49:03.562834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11244 12:49:03.563095 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11246 12:49:03.572735 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11247 12:49:03.576049 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11248 12:49:03.599381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11249 12:49:03.599681 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11251 12:49:03.603214 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11252 12:49:03.620363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11253 12:49:03.620654 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11255 12:49:03.624183 Standard Controls: 16 Private Controls: 0
11256 12:49:03.630926
11257 12:49:03.641809 Format ioctls:
11258 12:49:03.648960 <LAVA_SIGNAL_TESTSET STOP>
11259 12:49:03.649239 Received signal: <TESTSET> STOP
11260 12:49:03.649311 Closing test_set Control-ioctls
11261 12:49:03.658321 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11262 12:49:03.658572 Received signal: <TESTSET> START Format-ioctls
11263 12:49:03.658638 Starting test_set Format-ioctls
11264 12:49:03.661056 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11265 12:49:03.686575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11266 12:49:03.686831 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11268 12:49:03.689777 test VIDIOC_G/S_PARM: OK
11269 12:49:03.708080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11270 12:49:03.708352 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11272 12:49:03.711190 test VIDIOC_G_FBUF: OK (Not Supported)
11273 12:49:03.730563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11274 12:49:03.730838 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11276 12:49:03.734334 test VIDIOC_G_FMT: OK
11277 12:49:03.752073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11278 12:49:03.752410 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11280 12:49:03.755884 test VIDIOC_TRY_FMT: OK
11281 12:49:03.776167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11282 12:49:03.776531 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11284 12:49:03.786714 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11285 12:49:03.786876 test VIDIOC_S_FMT: FAIL
11286 12:49:03.808551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11287 12:49:03.808854 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11289 12:49:03.812084 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11290 12:49:03.832443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11291 12:49:03.832702 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11293 12:49:03.835463 test Cropping: OK
11294 12:49:03.856591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11295 12:49:03.856856 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11297 12:49:03.860033 test Composing: OK (Not Supported)
11298 12:49:03.881399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11299 12:49:03.881656 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11301 12:49:03.884872 test Scaling: OK (Not Supported)
11302 12:49:03.904543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11303 12:49:03.904627
11304 12:49:03.904865 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11306 12:49:03.914116 Codec ioctls:
11307 12:49:03.921088 <LAVA_SIGNAL_TESTSET STOP>
11308 12:49:03.921340 Received signal: <TESTSET> STOP
11309 12:49:03.921409 Closing test_set Format-ioctls
11310 12:49:03.929372 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11311 12:49:03.929624 Received signal: <TESTSET> START Codec-ioctls
11312 12:49:03.929692 Starting test_set Codec-ioctls
11313 12:49:03.932802 test VIDIOC_(TRY_)ENCODER_CMD: OK
11314 12:49:03.952167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11315 12:49:03.952425 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11317 12:49:03.958916 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11318 12:49:03.976033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11319 12:49:03.976314 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11321 12:49:03.982702 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11322 12:49:03.999708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11323 12:49:03.999791
11324 12:49:04.000025 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11326 12:49:04.009429 Buffer ioctls:
11327 12:49:04.017039 <LAVA_SIGNAL_TESTSET STOP>
11328 12:49:04.017289 Received signal: <TESTSET> STOP
11329 12:49:04.017356 Closing test_set Codec-ioctls
11330 12:49:04.025789 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11331 12:49:04.026042 Received signal: <TESTSET> START Buffer-ioctls
11332 12:49:04.026112 Starting test_set Buffer-ioctls
11333 12:49:04.028737 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11334 12:49:04.051657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11335 12:49:04.051742 test VIDIOC_EXPBUF: OK
11336 12:49:04.051977 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11338 12:49:04.071742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11339 12:49:04.072006 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11341 12:49:04.075497 test Requests: OK (Not Supported)
11342 12:49:04.095842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11343 12:49:04.095929
11344 12:49:04.096164 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11346 12:49:04.106120 Test input 0:
11347 12:49:04.116317
11348 12:49:04.126983 Streaming ioctls:
11349 12:49:04.132703 <LAVA_SIGNAL_TESTSET STOP>
11350 12:49:04.132999 Received signal: <TESTSET> STOP
11351 12:49:04.133106 Closing test_set Buffer-ioctls
11352 12:49:04.141380 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11353 12:49:04.141668 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11354 12:49:04.141765 Starting test_set Streaming-ioctls_Test-input-0
11355 12:49:04.145124 test read/write: OK (Not Supported)
11356 12:49:04.164638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11357 12:49:04.164922 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11359 12:49:04.171408 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11360 12:49:04.182293 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11361 12:49:04.186626 test blocking wait: FAIL
11362 12:49:04.210515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11363 12:49:04.210840 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11365 12:49:04.220379 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11366 12:49:04.220514 test MMAP (select): FAIL
11367 12:49:04.244330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11368 12:49:04.244681 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11370 12:49:04.250982 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11371 12:49:04.255410 test MMAP (epoll): FAIL
11372 12:49:04.280419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11373 12:49:04.280754 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11375 12:49:04.290174 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11376 12:49:04.296810 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11377 12:49:04.300604 test USERPTR (select): FAIL
11378 12:49:04.324116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11379 12:49:04.324394 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11381 12:49:04.330594 test DMABUF: Cannot test, specify --expbuf-device
11382 12:49:04.334128
11383 12:49:04.351792 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11384 12:49:04.355116 <LAVA_TEST_RUNNER EXIT>
11385 12:49:04.355378 ok: lava_test_shell seems to have completed
11386 12:49:04.355487 Marking unfinished test run as failed
11388 12:49:04.356735 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11389 12:49:04.356868 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11390 12:49:04.356964 end: 3 lava-test-retry (duration 00:00:03) [common]
11391 12:49:04.357054 start: 4 finalize (timeout 00:07:34) [common]
11392 12:49:04.357175 start: 4.1 power-off (timeout 00:00:30) [common]
11393 12:49:04.357335 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11394 12:49:04.440392 >> Command sent successfully.
11395 12:49:04.443236 Returned 0 in 0 seconds
11396 12:49:04.543606 end: 4.1 power-off (duration 00:00:00) [common]
11398 12:49:04.544195 start: 4.2 read-feedback (timeout 00:07:34) [common]
11399 12:49:04.544690 Listened to connection for namespace 'common' for up to 1s
11400 12:49:05.545551 Finalising connection for namespace 'common'
11401 12:49:05.545727 Disconnecting from shell: Finalise
11402 12:49:05.545832 / #
11403 12:49:05.646155 end: 4.2 read-feedback (duration 00:00:01) [common]
11404 12:49:05.646372 end: 4 finalize (duration 00:00:01) [common]
11405 12:49:05.646519 Cleaning after the job
11406 12:49:05.646633 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11118918/tftp-deploy-4z2yt1i4/ramdisk
11407 12:49:05.652366 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11118918/tftp-deploy-4z2yt1i4/kernel
11408 12:49:05.660506 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11118918/tftp-deploy-4z2yt1i4/dtb
11409 12:49:05.660701 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11118918/tftp-deploy-4z2yt1i4/modules
11410 12:49:05.668263 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11118918
11411 12:49:05.736120 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11118918
11412 12:49:05.736296 Job finished correctly