Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 68
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 32
- Errors: 1
1 04:40:01.305332 lava-dispatcher, installed at version: 2023.05.1
2 04:40:01.305555 start: 0 validate
3 04:40:01.305693 Start time: 2023-08-09 04:40:01.305685+00:00 (UTC)
4 04:40:01.305854 Using caching service: 'http://localhost/cache/?uri=%s'
5 04:40:01.306005 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 04:40:01.572512 Using caching service: 'http://localhost/cache/?uri=%s'
7 04:40:01.572726 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.42-cip2-1-g47d13938e615%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 04:40:01.829909 Using caching service: 'http://localhost/cache/?uri=%s'
9 04:40:01.830102 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.42-cip2-1-g47d13938e615%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 04:40:02.095870 Using caching service: 'http://localhost/cache/?uri=%s'
11 04:40:02.096051 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.42-cip2-1-g47d13938e615%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 04:40:02.355433 validate duration: 1.05
14 04:40:02.355721 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 04:40:02.355822 start: 1.1 download-retry (timeout 00:10:00) [common]
16 04:40:02.355916 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 04:40:02.356049 Not decompressing ramdisk as can be used compressed.
18 04:40:02.356140 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 04:40:02.356209 saving as /var/lib/lava/dispatcher/tmp/11241315/tftp-deploy-7vkciubz/ramdisk/rootfs.cpio.gz
20 04:40:02.356272 total size: 26246609 (25MB)
21 04:40:02.357335 progress 0% (0MB)
22 04:40:02.364606 progress 5% (1MB)
23 04:40:02.371679 progress 10% (2MB)
24 04:40:02.378844 progress 15% (3MB)
25 04:40:02.385936 progress 20% (5MB)
26 04:40:02.393039 progress 25% (6MB)
27 04:40:02.400091 progress 30% (7MB)
28 04:40:02.407119 progress 35% (8MB)
29 04:40:02.414211 progress 40% (10MB)
30 04:40:02.421279 progress 45% (11MB)
31 04:40:02.428368 progress 50% (12MB)
32 04:40:02.435386 progress 55% (13MB)
33 04:40:02.442421 progress 60% (15MB)
34 04:40:02.449457 progress 65% (16MB)
35 04:40:02.456454 progress 70% (17MB)
36 04:40:02.463483 progress 75% (18MB)
37 04:40:02.470541 progress 80% (20MB)
38 04:40:02.477615 progress 85% (21MB)
39 04:40:02.484654 progress 90% (22MB)
40 04:40:02.491576 progress 95% (23MB)
41 04:40:02.498504 progress 100% (25MB)
42 04:40:02.498808 25MB downloaded in 0.14s (175.62MB/s)
43 04:40:02.498976 end: 1.1.1 http-download (duration 00:00:00) [common]
45 04:40:02.499250 end: 1.1 download-retry (duration 00:00:00) [common]
46 04:40:02.499339 start: 1.2 download-retry (timeout 00:10:00) [common]
47 04:40:02.499426 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 04:40:02.499575 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.42-cip2-1-g47d13938e615/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 04:40:02.499652 saving as /var/lib/lava/dispatcher/tmp/11241315/tftp-deploy-7vkciubz/kernel/Image
50 04:40:02.499719 total size: 49220096 (46MB)
51 04:40:02.499781 No compression specified
52 04:40:02.500911 progress 0% (0MB)
53 04:40:02.513991 progress 5% (2MB)
54 04:40:02.527272 progress 10% (4MB)
55 04:40:02.540346 progress 15% (7MB)
56 04:40:02.553298 progress 20% (9MB)
57 04:40:02.566262 progress 25% (11MB)
58 04:40:02.579301 progress 30% (14MB)
59 04:40:02.592217 progress 35% (16MB)
60 04:40:02.605146 progress 40% (18MB)
61 04:40:02.618060 progress 45% (21MB)
62 04:40:02.631102 progress 50% (23MB)
63 04:40:02.643997 progress 55% (25MB)
64 04:40:02.656878 progress 60% (28MB)
65 04:40:02.669800 progress 65% (30MB)
66 04:40:02.682790 progress 70% (32MB)
67 04:40:02.695683 progress 75% (35MB)
68 04:40:02.708584 progress 80% (37MB)
69 04:40:02.721454 progress 85% (39MB)
70 04:40:02.734307 progress 90% (42MB)
71 04:40:02.747439 progress 95% (44MB)
72 04:40:02.760348 progress 100% (46MB)
73 04:40:02.760523 46MB downloaded in 0.26s (179.99MB/s)
74 04:40:02.760679 end: 1.2.1 http-download (duration 00:00:00) [common]
76 04:40:02.760907 end: 1.2 download-retry (duration 00:00:00) [common]
77 04:40:02.760993 start: 1.3 download-retry (timeout 00:10:00) [common]
78 04:40:02.761082 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 04:40:02.761225 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.42-cip2-1-g47d13938e615/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 04:40:02.761295 saving as /var/lib/lava/dispatcher/tmp/11241315/tftp-deploy-7vkciubz/dtb/mt8192-asurada-spherion-r0.dtb
81 04:40:02.761356 total size: 47278 (0MB)
82 04:40:02.761415 No compression specified
83 04:40:02.762546 progress 69% (0MB)
84 04:40:02.762824 progress 100% (0MB)
85 04:40:02.762980 0MB downloaded in 0.00s (27.81MB/s)
86 04:40:02.763100 end: 1.3.1 http-download (duration 00:00:00) [common]
88 04:40:02.763320 end: 1.3 download-retry (duration 00:00:00) [common]
89 04:40:02.763406 start: 1.4 download-retry (timeout 00:10:00) [common]
90 04:40:02.763488 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 04:40:02.763645 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.42-cip2-1-g47d13938e615/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 04:40:02.763712 saving as /var/lib/lava/dispatcher/tmp/11241315/tftp-deploy-7vkciubz/modules/modules.tar
93 04:40:02.763773 total size: 8557308 (8MB)
94 04:40:02.763832 Using unxz to decompress xz
95 04:40:02.768068 progress 0% (0MB)
96 04:40:02.790021 progress 5% (0MB)
97 04:40:02.812324 progress 10% (0MB)
98 04:40:02.838589 progress 15% (1MB)
99 04:40:02.864424 progress 20% (1MB)
100 04:40:02.890423 progress 25% (2MB)
101 04:40:02.917279 progress 30% (2MB)
102 04:40:02.943036 progress 35% (2MB)
103 04:40:02.969710 progress 40% (3MB)
104 04:40:02.994130 progress 45% (3MB)
105 04:40:03.022283 progress 50% (4MB)
106 04:40:03.050353 progress 55% (4MB)
107 04:40:03.077781 progress 60% (4MB)
108 04:40:03.100789 progress 65% (5MB)
109 04:40:03.127544 progress 70% (5MB)
110 04:40:03.152596 progress 75% (6MB)
111 04:40:03.178799 progress 80% (6MB)
112 04:40:03.208778 progress 85% (6MB)
113 04:40:03.238034 progress 90% (7MB)
114 04:40:03.262694 progress 95% (7MB)
115 04:40:03.287237 progress 100% (8MB)
116 04:40:03.291928 8MB downloaded in 0.53s (15.45MB/s)
117 04:40:03.292226 end: 1.4.1 http-download (duration 00:00:01) [common]
119 04:40:03.292490 end: 1.4 download-retry (duration 00:00:01) [common]
120 04:40:03.292583 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 04:40:03.292679 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 04:40:03.292767 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 04:40:03.292856 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 04:40:03.293106 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je
125 04:40:03.293255 makedir: /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin
126 04:40:03.293364 makedir: /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/tests
127 04:40:03.293465 makedir: /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/results
128 04:40:03.293577 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-add-keys
129 04:40:03.293784 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-add-sources
130 04:40:03.293938 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-background-process-start
131 04:40:03.294070 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-background-process-stop
132 04:40:03.294198 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-common-functions
133 04:40:03.294324 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-echo-ipv4
134 04:40:03.294453 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-install-packages
135 04:40:03.294585 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-installed-packages
136 04:40:03.294710 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-os-build
137 04:40:03.294836 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-probe-channel
138 04:40:03.294961 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-probe-ip
139 04:40:03.295088 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-target-ip
140 04:40:03.295212 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-target-mac
141 04:40:03.295343 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-target-storage
142 04:40:03.295514 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-test-case
143 04:40:03.295690 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-test-event
144 04:40:03.295819 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-test-feedback
145 04:40:03.295947 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-test-raise
146 04:40:03.296075 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-test-reference
147 04:40:03.296202 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-test-runner
148 04:40:03.296327 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-test-set
149 04:40:03.296456 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-test-shell
150 04:40:03.296586 Updating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-install-packages (oe)
151 04:40:03.296742 Updating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/bin/lava-installed-packages (oe)
152 04:40:03.296866 Creating /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/environment
153 04:40:03.296990 LAVA metadata
154 04:40:03.297080 - LAVA_JOB_ID=11241315
155 04:40:03.297192 - LAVA_DISPATCHER_IP=192.168.201.1
156 04:40:03.297313 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 04:40:03.297379 skipped lava-vland-overlay
158 04:40:03.297454 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 04:40:03.297533 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 04:40:03.297593 skipped lava-multinode-overlay
161 04:40:03.297672 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 04:40:03.297755 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 04:40:03.297828 Loading test definitions
164 04:40:03.297956 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 04:40:03.298032 Using /lava-11241315 at stage 0
166 04:40:03.298342 uuid=11241315_1.5.2.3.1 testdef=None
167 04:40:03.298476 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 04:40:03.298573 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 04:40:03.299092 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 04:40:03.299310 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 04:40:03.299950 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 04:40:03.300184 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 04:40:03.302729 runner path: /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 11241315_1.5.2.3.1
176 04:40:03.302893 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 04:40:03.303102 Creating lava-test-runner.conf files
179 04:40:03.303168 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11241315/lava-overlay-f17_t6je/lava-11241315/0 for stage 0
180 04:40:03.303276 - 0_v4l2-compliance-mtk-vcodec-enc
181 04:40:03.303401 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 04:40:03.303487 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 04:40:03.310455 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 04:40:03.310600 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 04:40:03.310692 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 04:40:03.310778 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 04:40:03.310872 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 04:40:04.086356 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 04:40:04.086725 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 04:40:04.086846 extracting modules file /var/lib/lava/dispatcher/tmp/11241315/tftp-deploy-7vkciubz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11241315/extract-overlay-ramdisk-fomittyt/ramdisk
191 04:40:04.327141 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 04:40:04.327315 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 04:40:04.327415 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11241315/compress-overlay-w9cuxmoh/overlay-1.5.2.4.tar.gz to ramdisk
194 04:40:04.327491 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11241315/compress-overlay-w9cuxmoh/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11241315/extract-overlay-ramdisk-fomittyt/ramdisk
195 04:40:04.334211 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 04:40:04.334332 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 04:40:04.334424 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 04:40:04.334512 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 04:40:04.334592 Building ramdisk /var/lib/lava/dispatcher/tmp/11241315/extract-overlay-ramdisk-fomittyt/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11241315/extract-overlay-ramdisk-fomittyt/ramdisk
200 04:40:04.927392 >> 227021 blocks
201 04:40:08.847688 rename /var/lib/lava/dispatcher/tmp/11241315/extract-overlay-ramdisk-fomittyt/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11241315/tftp-deploy-7vkciubz/ramdisk/ramdisk.cpio.gz
202 04:40:08.848192 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 04:40:08.848405 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 04:40:08.848595 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 04:40:08.848777 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11241315/tftp-deploy-7vkciubz/kernel/Image'
206 04:40:21.846769 Returned 0 in 12 seconds
207 04:40:21.947411 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11241315/tftp-deploy-7vkciubz/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11241315/tftp-deploy-7vkciubz/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11241315/tftp-deploy-7vkciubz/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11241315/tftp-deploy-7vkciubz/kernel/image.itb
208 04:40:22.581119 output: FIT description: Kernel Image image with one or more FDT blobs
209 04:40:22.581490 output: Created: Wed Aug 9 05:40:22 2023
210 04:40:22.581579 output: Image 0 (kernel-1)
211 04:40:22.581649 output: Description:
212 04:40:22.581715 output: Created: Wed Aug 9 05:40:22 2023
213 04:40:22.581779 output: Type: Kernel Image
214 04:40:22.581842 output: Compression: lzma compressed
215 04:40:22.581905 output: Data Size: 11036366 Bytes = 10777.70 KiB = 10.53 MiB
216 04:40:22.581967 output: Architecture: AArch64
217 04:40:22.582026 output: OS: Linux
218 04:40:22.582089 output: Load Address: 0x00000000
219 04:40:22.582147 output: Entry Point: 0x00000000
220 04:40:22.582206 output: Hash algo: crc32
221 04:40:22.582261 output: Hash value: 9e750869
222 04:40:22.582315 output: Image 1 (fdt-1)
223 04:40:22.582370 output: Description: mt8192-asurada-spherion-r0
224 04:40:22.582424 output: Created: Wed Aug 9 05:40:22 2023
225 04:40:22.582478 output: Type: Flat Device Tree
226 04:40:22.582532 output: Compression: uncompressed
227 04:40:22.582586 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 04:40:22.582641 output: Architecture: AArch64
229 04:40:22.582695 output: Hash algo: crc32
230 04:40:22.582749 output: Hash value: cc4352de
231 04:40:22.582803 output: Image 2 (ramdisk-1)
232 04:40:22.582857 output: Description: unavailable
233 04:40:22.582911 output: Created: Wed Aug 9 05:40:22 2023
234 04:40:22.582965 output: Type: RAMDisk Image
235 04:40:22.583020 output: Compression: Unknown Compression
236 04:40:22.583073 output: Data Size: 39229146 Bytes = 38309.71 KiB = 37.41 MiB
237 04:40:22.583127 output: Architecture: AArch64
238 04:40:22.583181 output: OS: Linux
239 04:40:22.583235 output: Load Address: unavailable
240 04:40:22.583288 output: Entry Point: unavailable
241 04:40:22.583342 output: Hash algo: crc32
242 04:40:22.583395 output: Hash value: 34d9296c
243 04:40:22.583448 output: Default Configuration: 'conf-1'
244 04:40:22.583505 output: Configuration 0 (conf-1)
245 04:40:22.583579 output: Description: mt8192-asurada-spherion-r0
246 04:40:22.583636 output: Kernel: kernel-1
247 04:40:22.583689 output: Init Ramdisk: ramdisk-1
248 04:40:22.583743 output: FDT: fdt-1
249 04:40:22.583797 output: Loadables: kernel-1
250 04:40:22.583857 output:
251 04:40:22.584070 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 04:40:22.584175 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 04:40:22.584286 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 04:40:22.584382 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 04:40:22.584467 No LXC device requested
256 04:40:22.584551 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 04:40:22.584642 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 04:40:22.584722 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 04:40:22.584792 Checking files for TFTP limit of 4294967296 bytes.
260 04:40:22.585306 end: 1 tftp-deploy (duration 00:00:20) [common]
261 04:40:22.585413 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 04:40:22.585515 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 04:40:22.585643 substitutions:
264 04:40:22.585712 - {DTB}: 11241315/tftp-deploy-7vkciubz/dtb/mt8192-asurada-spherion-r0.dtb
265 04:40:22.585779 - {INITRD}: 11241315/tftp-deploy-7vkciubz/ramdisk/ramdisk.cpio.gz
266 04:40:22.585840 - {KERNEL}: 11241315/tftp-deploy-7vkciubz/kernel/Image
267 04:40:22.585900 - {LAVA_MAC}: None
268 04:40:22.585958 - {PRESEED_CONFIG}: None
269 04:40:22.586015 - {PRESEED_LOCAL}: None
270 04:40:22.586072 - {RAMDISK}: 11241315/tftp-deploy-7vkciubz/ramdisk/ramdisk.cpio.gz
271 04:40:22.586128 - {ROOT_PART}: None
272 04:40:22.586184 - {ROOT}: None
273 04:40:22.586239 - {SERVER_IP}: 192.168.201.1
274 04:40:22.586295 - {TEE}: None
275 04:40:22.586350 Parsed boot commands:
276 04:40:22.586405 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 04:40:22.586590 Parsed boot commands: tftpboot 192.168.201.1 11241315/tftp-deploy-7vkciubz/kernel/image.itb 11241315/tftp-deploy-7vkciubz/kernel/cmdline
278 04:40:22.586682 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 04:40:22.586776 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 04:40:22.586876 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 04:40:22.586964 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 04:40:22.587043 Not connected, no need to disconnect.
283 04:40:22.587121 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 04:40:22.587212 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 04:40:22.587311 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 04:40:22.591359 Setting prompt string to ['lava-test: # ']
287 04:40:22.591782 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 04:40:22.591903 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 04:40:22.592005 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 04:40:22.592106 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 04:40:22.592312 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 04:40:27.726384 >> Command sent successfully.
293 04:40:27.728907 Returned 0 in 5 seconds
294 04:40:27.829300 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 04:40:27.829901 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 04:40:27.830037 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 04:40:27.830131 Setting prompt string to 'Starting depthcharge on Spherion...'
299 04:40:27.830202 Changing prompt to 'Starting depthcharge on Spherion...'
300 04:40:27.830273 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 04:40:27.830535 [Enter `^Ec?' for help]
302 04:40:28.003636
303 04:40:28.003780
304 04:40:28.003864 F0: 102B 0000
305 04:40:28.003931
306 04:40:28.003992 F3: 1001 0000 [0200]
307 04:40:28.004052
308 04:40:28.007411 F3: 1001 0000
309 04:40:28.007538
310 04:40:28.007622 F7: 102D 0000
311 04:40:28.007685
312 04:40:28.010528 F1: 0000 0000
313 04:40:28.010614
314 04:40:28.010681 V0: 0000 0000 [0001]
315 04:40:28.010746
316 04:40:28.014196 00: 0007 8000
317 04:40:28.014286
318 04:40:28.014353 01: 0000 0000
319 04:40:28.014416
320 04:40:28.014475 BP: 0C00 0209 [0000]
321 04:40:28.017228
322 04:40:28.017313 G0: 1182 0000
323 04:40:28.017380
324 04:40:28.017442 EC: 0000 0021 [4000]
325 04:40:28.020828
326 04:40:28.020914 S7: 0000 0000 [0000]
327 04:40:28.020981
328 04:40:28.021043 CC: 0000 0000 [0001]
329 04:40:28.024692
330 04:40:28.024777 T0: 0000 0040 [010F]
331 04:40:28.024857
332 04:40:28.024920 Jump to BL
333 04:40:28.024981
334 04:40:28.050454
335 04:40:28.050557
336 04:40:28.050624
337 04:40:28.057728 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 04:40:28.060810 ARM64: Exception handlers installed.
339 04:40:28.064979 ARM64: Testing exception
340 04:40:28.068023 ARM64: Done test exception
341 04:40:28.074641 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 04:40:28.084953 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 04:40:28.091510 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 04:40:28.101582 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 04:40:28.108051 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 04:40:28.118512 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 04:40:28.129251 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 04:40:28.135970 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 04:40:28.153702 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 04:40:28.156704 WDT: Last reset was cold boot
351 04:40:28.160284 SPI1(PAD0) initialized at 2873684 Hz
352 04:40:28.163859 SPI5(PAD0) initialized at 992727 Hz
353 04:40:28.166969 VBOOT: Loading verstage.
354 04:40:28.173577 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 04:40:28.176610 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 04:40:28.181509 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 04:40:28.184649 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 04:40:28.191511 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 04:40:28.197651 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 04:40:28.208545 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 04:40:28.208629
362 04:40:28.208694
363 04:40:28.218795 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 04:40:28.222292 ARM64: Exception handlers installed.
365 04:40:28.225770 ARM64: Testing exception
366 04:40:28.225874 ARM64: Done test exception
367 04:40:28.232314 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 04:40:28.235983 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 04:40:28.249699 Probing TPM: . done!
370 04:40:28.249793 TPM ready after 0 ms
371 04:40:28.256548 Connected to device vid:did:rid of 1ae0:0028:00
372 04:40:28.263128 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 04:40:28.323369 Initialized TPM device CR50 revision 0
374 04:40:28.334662 tlcl_send_startup: Startup return code is 0
375 04:40:28.334816 TPM: setup succeeded
376 04:40:28.346602 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 04:40:28.355110 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 04:40:28.369160 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 04:40:28.376088 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 04:40:28.379998 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 04:40:28.383809 in-header: 03 07 00 00 08 00 00 00
382 04:40:28.387610 in-data: aa e4 47 04 13 02 00 00
383 04:40:28.391235 Chrome EC: UHEPI supported
384 04:40:28.394503 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 04:40:28.399307 in-header: 03 95 00 00 08 00 00 00
386 04:40:28.403055 in-data: 18 20 20 08 00 00 00 00
387 04:40:28.403150 Phase 1
388 04:40:28.406972 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 04:40:28.414245 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 04:40:28.422258 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 04:40:28.422382 Recovery requested (1009000e)
392 04:40:28.432562 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 04:40:28.437591 tlcl_extend: response is 0
394 04:40:28.447207 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 04:40:28.453044 tlcl_extend: response is 0
396 04:40:28.459268 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 04:40:28.479198 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 04:40:28.486277 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 04:40:28.486417
400 04:40:28.486515
401 04:40:28.496081 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 04:40:28.499620 ARM64: Exception handlers installed.
403 04:40:28.502802 ARM64: Testing exception
404 04:40:28.502886 ARM64: Done test exception
405 04:40:28.525081 pmic_efuse_setting: Set efuses in 11 msecs
406 04:40:28.528122 pmwrap_interface_init: Select PMIF_VLD_RDY
407 04:40:28.535028 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 04:40:28.538179 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 04:40:28.541929 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 04:40:28.549863 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 04:40:28.553136 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 04:40:28.557059 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 04:40:28.564601 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 04:40:28.568544 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 04:40:28.572109 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 04:40:28.575817 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 04:40:28.583068 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 04:40:28.586848 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 04:40:28.590545 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 04:40:28.597701 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 04:40:28.601789 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 04:40:28.609047 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 04:40:28.612685 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 04:40:28.619893 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 04:40:28.627291 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 04:40:28.631052 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 04:40:28.639153 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 04:40:28.642925 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 04:40:28.650361 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 04:40:28.654016 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 04:40:28.657774 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 04:40:28.665328 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 04:40:28.669388 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 04:40:28.673099 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 04:40:28.680492 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 04:40:28.684033 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 04:40:28.687885 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 04:40:28.695478 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 04:40:28.698556 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 04:40:28.705699 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 04:40:28.709472 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 04:40:28.713642 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 04:40:28.721052 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 04:40:28.724559 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 04:40:28.728367 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 04:40:28.731943 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 04:40:28.735722 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 04:40:28.742876 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 04:40:28.746640 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 04:40:28.750242 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 04:40:28.753926 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 04:40:28.757768 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 04:40:28.761967 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 04:40:28.769017 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 04:40:28.772523 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 04:40:28.776721 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 04:40:28.779781 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 04:40:28.787769 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 04:40:28.794999 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 04:40:28.802545 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 04:40:28.809950 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 04:40:28.817477 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 04:40:28.821152 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 04:40:28.825319 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 04:40:28.832844 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 04:40:28.840514 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0xb
467 04:40:28.843890 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 04:40:28.846956 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 04:40:28.850756 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 04:40:28.862399 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 04:40:28.872008 [RTC]rtc_get_frequency_meter,154: input=23, output=941
472 04:40:28.881850 [RTC]rtc_get_frequency_meter,154: input=19, output=850
473 04:40:28.891022 [RTC]rtc_get_frequency_meter,154: input=17, output=804
474 04:40:28.900237 [RTC]rtc_get_frequency_meter,154: input=16, output=780
475 04:40:28.910053 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 04:40:28.921100 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 04:40:28.924880 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 04:40:28.928535 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 04:40:28.932338 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 04:40:28.935378 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 04:40:28.943034 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 04:40:28.946799 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 04:40:28.946887 ADC[4]: Raw value=905834 ID=7
484 04:40:28.950965 ADC[3]: Raw value=213441 ID=1
485 04:40:28.951055 RAM Code: 0x71
486 04:40:28.958693 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 04:40:28.962850 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 04:40:28.969984 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 04:40:28.977281 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 04:40:28.981444 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 04:40:28.985034 in-header: 03 07 00 00 08 00 00 00
492 04:40:28.988550 in-data: aa e4 47 04 13 02 00 00
493 04:40:28.988636 Chrome EC: UHEPI supported
494 04:40:28.996054 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 04:40:28.999654 in-header: 03 95 00 00 08 00 00 00
496 04:40:29.003295 in-data: 18 20 20 08 00 00 00 00
497 04:40:29.007115 MRC: failed to locate region type 0.
498 04:40:29.015059 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 04:40:29.018177 DRAM-K: Running full calibration
500 04:40:29.021946 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 04:40:29.025730 header.status = 0x0
502 04:40:29.030045 header.version = 0x6 (expected: 0x6)
503 04:40:29.033687 header.size = 0xd00 (expected: 0xd00)
504 04:40:29.033775 header.flags = 0x0
505 04:40:29.040856 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 04:40:29.058150 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 04:40:29.065346 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 04:40:29.069451 dram_init: ddr_geometry: 2
509 04:40:29.069603 [EMI] MDL number = 2
510 04:40:29.072978 [EMI] Get MDL freq = 0
511 04:40:29.073136 dram_init: ddr_type: 0
512 04:40:29.076980 is_discrete_lpddr4: 1
513 04:40:29.080448 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 04:40:29.080540
515 04:40:29.080607
516 04:40:29.080670 [Bian_co] ETT version 0.0.0.1
517 04:40:29.088428 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 04:40:29.088518
519 04:40:29.092046 dramc_set_vcore_voltage set vcore to 650000
520 04:40:29.092132 Read voltage for 800, 4
521 04:40:29.092199 Vio18 = 0
522 04:40:29.095676 Vcore = 650000
523 04:40:29.095761 Vdram = 0
524 04:40:29.095829 Vddq = 0
525 04:40:29.099360 Vmddr = 0
526 04:40:29.099444 dram_init: config_dvfs: 1
527 04:40:29.106772 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 04:40:29.111027 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 04:40:29.114049 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 04:40:29.117751 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 04:40:29.121385 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 04:40:29.125803 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 04:40:29.128797 MEM_TYPE=3, freq_sel=18
534 04:40:29.131923 sv_algorithm_assistance_LP4_1600
535 04:40:29.135153 ============ PULL DRAM RESETB DOWN ============
536 04:40:29.139011 ========== PULL DRAM RESETB DOWN end =========
537 04:40:29.145250 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 04:40:29.149063 ===================================
539 04:40:29.149192 LPDDR4 DRAM CONFIGURATION
540 04:40:29.152812 ===================================
541 04:40:29.156597 EX_ROW_EN[0] = 0x0
542 04:40:29.156689 EX_ROW_EN[1] = 0x0
543 04:40:29.160231 LP4Y_EN = 0x0
544 04:40:29.160318 WORK_FSP = 0x0
545 04:40:29.160386 WL = 0x2
546 04:40:29.164374 RL = 0x2
547 04:40:29.164466 BL = 0x2
548 04:40:29.168021 RPST = 0x0
549 04:40:29.168111 RD_PRE = 0x0
550 04:40:29.171140 WR_PRE = 0x1
551 04:40:29.171225 WR_PST = 0x0
552 04:40:29.174616 DBI_WR = 0x0
553 04:40:29.174701 DBI_RD = 0x0
554 04:40:29.178032 OTF = 0x1
555 04:40:29.181061 ===================================
556 04:40:29.184742 ===================================
557 04:40:29.184828 ANA top config
558 04:40:29.188283 ===================================
559 04:40:29.191134 DLL_ASYNC_EN = 0
560 04:40:29.194705 ALL_SLAVE_EN = 1
561 04:40:29.194790 NEW_RANK_MODE = 1
562 04:40:29.197923 DLL_IDLE_MODE = 1
563 04:40:29.201295 LP45_APHY_COMB_EN = 1
564 04:40:29.204504 TX_ODT_DIS = 1
565 04:40:29.208297 NEW_8X_MODE = 1
566 04:40:29.208384 ===================================
567 04:40:29.211999 ===================================
568 04:40:29.215712 data_rate = 1600
569 04:40:29.218659 CKR = 1
570 04:40:29.221920 DQ_P2S_RATIO = 8
571 04:40:29.225625 ===================================
572 04:40:29.228824 CA_P2S_RATIO = 8
573 04:40:29.231914 DQ_CA_OPEN = 0
574 04:40:29.232001 DQ_SEMI_OPEN = 0
575 04:40:29.235802 CA_SEMI_OPEN = 0
576 04:40:29.238924 CA_FULL_RATE = 0
577 04:40:29.242250 DQ_CKDIV4_EN = 1
578 04:40:29.245304 CA_CKDIV4_EN = 1
579 04:40:29.245389 CA_PREDIV_EN = 0
580 04:40:29.249159 PH8_DLY = 0
581 04:40:29.252261 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 04:40:29.255376 DQ_AAMCK_DIV = 4
583 04:40:29.259279 CA_AAMCK_DIV = 4
584 04:40:29.262403 CA_ADMCK_DIV = 4
585 04:40:29.262488 DQ_TRACK_CA_EN = 0
586 04:40:29.265531 CA_PICK = 800
587 04:40:29.269299 CA_MCKIO = 800
588 04:40:29.272907 MCKIO_SEMI = 0
589 04:40:29.276450 PLL_FREQ = 3068
590 04:40:29.276535 DQ_UI_PI_RATIO = 32
591 04:40:29.280230 CA_UI_PI_RATIO = 0
592 04:40:29.284158 ===================================
593 04:40:29.287866 ===================================
594 04:40:29.291015 memory_type:LPDDR4
595 04:40:29.291100 GP_NUM : 10
596 04:40:29.294878 SRAM_EN : 1
597 04:40:29.294965 MD32_EN : 0
598 04:40:29.298296 ===================================
599 04:40:29.302324 [ANA_INIT] >>>>>>>>>>>>>>
600 04:40:29.305828 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 04:40:29.309305 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 04:40:29.312783 ===================================
603 04:40:29.312870 data_rate = 1600,PCW = 0X7600
604 04:40:29.315684 ===================================
605 04:40:29.319692 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 04:40:29.326398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 04:40:29.332640 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 04:40:29.336188 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 04:40:29.339252 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 04:40:29.343051 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 04:40:29.346262 [ANA_INIT] flow start
612 04:40:29.346346 [ANA_INIT] PLL >>>>>>>>
613 04:40:29.349338 [ANA_INIT] PLL <<<<<<<<
614 04:40:29.353139 [ANA_INIT] MIDPI >>>>>>>>
615 04:40:29.356143 [ANA_INIT] MIDPI <<<<<<<<
616 04:40:29.356228 [ANA_INIT] DLL >>>>>>>>
617 04:40:29.359255 [ANA_INIT] flow end
618 04:40:29.363033 ============ LP4 DIFF to SE enter ============
619 04:40:29.366146 ============ LP4 DIFF to SE exit ============
620 04:40:29.369291 [ANA_INIT] <<<<<<<<<<<<<
621 04:40:29.372953 [Flow] Enable top DCM control >>>>>
622 04:40:29.375974 [Flow] Enable top DCM control <<<<<
623 04:40:29.379482 Enable DLL master slave shuffle
624 04:40:29.383125 ==============================================================
625 04:40:29.386257 Gating Mode config
626 04:40:29.392918 ==============================================================
627 04:40:29.393017 Config description:
628 04:40:29.402829 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 04:40:29.409596 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 04:40:29.412868 SELPH_MODE 0: By rank 1: By Phase
631 04:40:29.419575 ==============================================================
632 04:40:29.423285 GAT_TRACK_EN = 1
633 04:40:29.426271 RX_GATING_MODE = 2
634 04:40:29.429605 RX_GATING_TRACK_MODE = 2
635 04:40:29.432849 SELPH_MODE = 1
636 04:40:29.436252 PICG_EARLY_EN = 1
637 04:40:29.436337 VALID_LAT_VALUE = 1
638 04:40:29.443014 ==============================================================
639 04:40:29.446747 Enter into Gating configuration >>>>
640 04:40:29.449778 Exit from Gating configuration <<<<
641 04:40:29.453567 Enter into DVFS_PRE_config >>>>>
642 04:40:29.462974 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 04:40:29.466633 Exit from DVFS_PRE_config <<<<<
644 04:40:29.469796 Enter into PICG configuration >>>>
645 04:40:29.473524 Exit from PICG configuration <<<<
646 04:40:29.476646 [RX_INPUT] configuration >>>>>
647 04:40:29.479729 [RX_INPUT] configuration <<<<<
648 04:40:29.483366 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 04:40:29.489922 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 04:40:29.496749 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 04:40:29.503097 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 04:40:29.509834 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 04:40:29.513328 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 04:40:29.519737 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 04:40:29.523407 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 04:40:29.526620 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 04:40:29.529698 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 04:40:29.536620 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 04:40:29.540312 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 04:40:29.543413 ===================================
661 04:40:29.546930 LPDDR4 DRAM CONFIGURATION
662 04:40:29.550349 ===================================
663 04:40:29.550434 EX_ROW_EN[0] = 0x0
664 04:40:29.553635 EX_ROW_EN[1] = 0x0
665 04:40:29.553719 LP4Y_EN = 0x0
666 04:40:29.556680 WORK_FSP = 0x0
667 04:40:29.556782 WL = 0x2
668 04:40:29.560482 RL = 0x2
669 04:40:29.560580 BL = 0x2
670 04:40:29.563572 RPST = 0x0
671 04:40:29.563666 RD_PRE = 0x0
672 04:40:29.566679 WR_PRE = 0x1
673 04:40:29.566762 WR_PST = 0x0
674 04:40:29.570417 DBI_WR = 0x0
675 04:40:29.570522 DBI_RD = 0x0
676 04:40:29.573654 OTF = 0x1
677 04:40:29.576624 ===================================
678 04:40:29.580344 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 04:40:29.583440 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 04:40:29.590327 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 04:40:29.593275 ===================================
682 04:40:29.593385 LPDDR4 DRAM CONFIGURATION
683 04:40:29.596905 ===================================
684 04:40:29.599743 EX_ROW_EN[0] = 0x10
685 04:40:29.603552 EX_ROW_EN[1] = 0x0
686 04:40:29.603655 LP4Y_EN = 0x0
687 04:40:29.606572 WORK_FSP = 0x0
688 04:40:29.606700 WL = 0x2
689 04:40:29.610059 RL = 0x2
690 04:40:29.610148 BL = 0x2
691 04:40:29.613565 RPST = 0x0
692 04:40:29.613652 RD_PRE = 0x0
693 04:40:29.616573 WR_PRE = 0x1
694 04:40:29.616668 WR_PST = 0x0
695 04:40:29.620198 DBI_WR = 0x0
696 04:40:29.620283 DBI_RD = 0x0
697 04:40:29.623109 OTF = 0x1
698 04:40:29.626587 ===================================
699 04:40:29.633255 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 04:40:29.636340 nWR fixed to 40
701 04:40:29.636443 [ModeRegInit_LP4] CH0 RK0
702 04:40:29.640110 [ModeRegInit_LP4] CH0 RK1
703 04:40:29.643106 [ModeRegInit_LP4] CH1 RK0
704 04:40:29.646897 [ModeRegInit_LP4] CH1 RK1
705 04:40:29.647008 match AC timing 13
706 04:40:29.650012 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 04:40:29.656794 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 04:40:29.660350 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 04:40:29.663265 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 04:40:29.670335 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 04:40:29.670424 [EMI DOE] emi_dcm 0
712 04:40:29.676563 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 04:40:29.676649 ==
714 04:40:29.680362 Dram Type= 6, Freq= 0, CH_0, rank 0
715 04:40:29.683557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 04:40:29.683642 ==
717 04:40:29.690202 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 04:40:29.693334 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 04:40:29.703275 [CA 0] Center 36 (6~67) winsize 62
720 04:40:29.706876 [CA 1] Center 36 (6~67) winsize 62
721 04:40:29.709922 [CA 2] Center 34 (4~65) winsize 62
722 04:40:29.713763 [CA 3] Center 34 (4~64) winsize 61
723 04:40:29.716779 [CA 4] Center 33 (2~64) winsize 63
724 04:40:29.720294 [CA 5] Center 32 (2~62) winsize 61
725 04:40:29.720380
726 04:40:29.723174 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 04:40:29.723258
728 04:40:29.726940 [CATrainingPosCal] consider 1 rank data
729 04:40:29.730290 u2DelayCellTimex100 = 270/100 ps
730 04:40:29.733373 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 04:40:29.736510 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 04:40:29.743259 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 04:40:29.746912 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
734 04:40:29.750081 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
735 04:40:29.753812 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 04:40:29.753890
737 04:40:29.756715 CA PerBit enable=1, Macro0, CA PI delay=32
738 04:40:29.756805
739 04:40:29.759861 [CBTSetCACLKResult] CA Dly = 32
740 04:40:29.759949 CS Dly: 5 (0~36)
741 04:40:29.763583 ==
742 04:40:29.763661 Dram Type= 6, Freq= 0, CH_0, rank 1
743 04:40:29.769958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 04:40:29.770035 ==
745 04:40:29.773444 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 04:40:29.779961 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 04:40:29.790010 [CA 0] Center 36 (6~67) winsize 62
748 04:40:29.793279 [CA 1] Center 36 (6~67) winsize 62
749 04:40:29.796336 [CA 2] Center 34 (3~65) winsize 63
750 04:40:29.800050 [CA 3] Center 34 (3~65) winsize 63
751 04:40:29.803080 [CA 4] Center 32 (2~63) winsize 62
752 04:40:29.806303 [CA 5] Center 32 (2~63) winsize 62
753 04:40:29.806388
754 04:40:29.809911 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 04:40:29.809999
756 04:40:29.812948 [CATrainingPosCal] consider 2 rank data
757 04:40:29.816526 u2DelayCellTimex100 = 270/100 ps
758 04:40:29.819646 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 04:40:29.823281 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 04:40:29.829941 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 04:40:29.833197 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
762 04:40:29.836858 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
763 04:40:29.839680 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 04:40:29.839766
765 04:40:29.843348 CA PerBit enable=1, Macro0, CA PI delay=32
766 04:40:29.843460
767 04:40:29.846607 [CBTSetCACLKResult] CA Dly = 32
768 04:40:29.846692 CS Dly: 5 (0~37)
769 04:40:29.846759
770 04:40:29.850451 ----->DramcWriteLeveling(PI) begin...
771 04:40:29.850541 ==
772 04:40:29.854186 Dram Type= 6, Freq= 0, CH_0, rank 0
773 04:40:29.857722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 04:40:29.857839 ==
775 04:40:29.862132 Write leveling (Byte 0): 34 => 34
776 04:40:29.865136 Write leveling (Byte 1): 30 => 30
777 04:40:29.868911 DramcWriteLeveling(PI) end<-----
778 04:40:29.869002
779 04:40:29.869069 ==
780 04:40:29.871923 Dram Type= 6, Freq= 0, CH_0, rank 0
781 04:40:29.875764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 04:40:29.875853 ==
783 04:40:29.879392 [Gating] SW mode calibration
784 04:40:29.886771 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 04:40:29.889589 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 04:40:29.896584 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 04:40:29.899838 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 04:40:29.902872 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
789 04:40:29.909829 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 04:40:29.913597 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 04:40:29.916763 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 04:40:29.923402 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 04:40:29.926533 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 04:40:29.929728 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 04:40:29.936345 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 04:40:29.939827 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 04:40:29.943568 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 04:40:29.950333 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 04:40:29.953650 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 04:40:29.956698 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 04:40:29.960313 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 04:40:29.966916 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 04:40:29.969986 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
804 04:40:29.973682 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 04:40:29.980051 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 04:40:29.983782 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 04:40:29.986851 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 04:40:29.993613 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 04:40:29.996647 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 04:40:30.000293 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 04:40:30.007014 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 04:40:30.010547 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
813 04:40:30.013824 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
814 04:40:30.019918 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 04:40:30.023651 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 04:40:30.026694 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 04:40:30.030300 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 04:40:30.037032 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
819 04:40:30.040131 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
820 04:40:30.043550 0 10 8 | B1->B0 | 3333 2626 | 0 0 | (0 0) (0 0)
821 04:40:30.050176 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 04:40:30.053380 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 04:40:30.057071 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 04:40:30.063993 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 04:40:30.067106 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 04:40:30.070358 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 04:40:30.076863 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
828 04:40:30.080457 0 11 8 | B1->B0 | 2c2c 4444 | 1 0 | (0 0) (0 0)
829 04:40:30.083640 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
830 04:40:30.090471 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 04:40:30.093732 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 04:40:30.096799 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 04:40:30.103840 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 04:40:30.106946 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 04:40:30.110622 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 04:40:30.117165 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 04:40:30.119976 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 04:40:30.123424 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 04:40:30.127129 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 04:40:30.133344 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 04:40:30.137052 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 04:40:30.140051 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 04:40:30.146711 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 04:40:30.150400 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 04:40:30.153759 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 04:40:30.160494 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 04:40:30.163600 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 04:40:30.167121 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 04:40:30.173783 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 04:40:30.177342 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 04:40:30.180465 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 04:40:30.187336 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 04:40:30.187427 Total UI for P1: 0, mck2ui 16
854 04:40:30.193533 best dqsien dly found for B0: ( 0, 14, 6)
855 04:40:30.197071 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
856 04:40:30.200302 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 04:40:30.204069 Total UI for P1: 0, mck2ui 16
858 04:40:30.207843 best dqsien dly found for B1: ( 0, 14, 10)
859 04:40:30.211102 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
860 04:40:30.214099 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 04:40:30.214188
862 04:40:30.217877 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
863 04:40:30.221060 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 04:40:30.224263 [Gating] SW calibration Done
865 04:40:30.224348 ==
866 04:40:30.227957 Dram Type= 6, Freq= 0, CH_0, rank 0
867 04:40:30.230905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 04:40:30.234185 ==
869 04:40:30.234305 RX Vref Scan: 0
870 04:40:30.234372
871 04:40:30.237545 RX Vref 0 -> 0, step: 1
872 04:40:30.237630
873 04:40:30.241175 RX Delay -130 -> 252, step: 16
874 04:40:30.244315 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
875 04:40:30.247672 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
876 04:40:30.251228 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
877 04:40:30.254338 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
878 04:40:30.261058 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
879 04:40:30.264569 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
880 04:40:30.267557 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
881 04:40:30.271329 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
882 04:40:30.274350 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
883 04:40:30.277703 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
884 04:40:30.284438 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
885 04:40:30.287988 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
886 04:40:30.291034 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
887 04:40:30.294664 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
888 04:40:30.300913 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
889 04:40:30.304772 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
890 04:40:30.304866 ==
891 04:40:30.307790 Dram Type= 6, Freq= 0, CH_0, rank 0
892 04:40:30.310925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 04:40:30.311047 ==
894 04:40:30.311114 DQS Delay:
895 04:40:30.314618 DQS0 = 0, DQS1 = 0
896 04:40:30.314738 DQM Delay:
897 04:40:30.317639 DQM0 = 89, DQM1 = 83
898 04:40:30.317725 DQ Delay:
899 04:40:30.321385 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
900 04:40:30.324494 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
901 04:40:30.327649 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
902 04:40:30.330951 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
903 04:40:30.331030
904 04:40:30.331094
905 04:40:30.331203 ==
906 04:40:30.334543 Dram Type= 6, Freq= 0, CH_0, rank 0
907 04:40:30.337632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 04:40:30.341431 ==
909 04:40:30.341515
910 04:40:30.341581
911 04:40:30.341642 TX Vref Scan disable
912 04:40:30.344346 == TX Byte 0 ==
913 04:40:30.347817 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
914 04:40:30.350975 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
915 04:40:30.354535 == TX Byte 1 ==
916 04:40:30.358093 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
917 04:40:30.361040 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
918 04:40:30.361127 ==
919 04:40:30.364695 Dram Type= 6, Freq= 0, CH_0, rank 0
920 04:40:30.371103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 04:40:30.371190 ==
922 04:40:30.383609 TX Vref=22, minBit 7, minWin=27, winSum=447
923 04:40:30.386815 TX Vref=24, minBit 8, minWin=27, winSum=450
924 04:40:30.390139 TX Vref=26, minBit 10, minWin=27, winSum=455
925 04:40:30.393731 TX Vref=28, minBit 5, minWin=28, winSum=457
926 04:40:30.396733 TX Vref=30, minBit 5, minWin=28, winSum=456
927 04:40:30.400128 TX Vref=32, minBit 2, minWin=28, winSum=454
928 04:40:30.406846 [TxChooseVref] Worse bit 5, Min win 28, Win sum 457, Final Vref 28
929 04:40:30.406981
930 04:40:30.409994 Final TX Range 1 Vref 28
931 04:40:30.410075
932 04:40:30.410139 ==
933 04:40:30.413824 Dram Type= 6, Freq= 0, CH_0, rank 0
934 04:40:30.416876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 04:40:30.416976 ==
936 04:40:30.417044
937 04:40:30.417142
938 04:40:30.420661 TX Vref Scan disable
939 04:40:30.423719 == TX Byte 0 ==
940 04:40:30.427323 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
941 04:40:30.430520 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
942 04:40:30.433650 == TX Byte 1 ==
943 04:40:30.437380 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
944 04:40:30.440556 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
945 04:40:30.440635
946 04:40:30.444229 [DATLAT]
947 04:40:30.444304 Freq=800, CH0 RK0
948 04:40:30.444367
949 04:40:30.447322 DATLAT Default: 0xa
950 04:40:30.447392 0, 0xFFFF, sum = 0
951 04:40:30.450351 1, 0xFFFF, sum = 0
952 04:40:30.450437 2, 0xFFFF, sum = 0
953 04:40:30.453807 3, 0xFFFF, sum = 0
954 04:40:30.453893 4, 0xFFFF, sum = 0
955 04:40:30.457263 5, 0xFFFF, sum = 0
956 04:40:30.457381 6, 0xFFFF, sum = 0
957 04:40:30.460830 7, 0xFFFF, sum = 0
958 04:40:30.460928 8, 0xFFFF, sum = 0
959 04:40:30.463739 9, 0x0, sum = 1
960 04:40:30.463824 10, 0x0, sum = 2
961 04:40:30.467219 11, 0x0, sum = 3
962 04:40:30.467305 12, 0x0, sum = 4
963 04:40:30.470644 best_step = 10
964 04:40:30.470771
965 04:40:30.470838 ==
966 04:40:30.474257 Dram Type= 6, Freq= 0, CH_0, rank 0
967 04:40:30.477087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 04:40:30.477172 ==
969 04:40:30.480624 RX Vref Scan: 1
970 04:40:30.480724
971 04:40:30.480791 Set Vref Range= 32 -> 127
972 04:40:30.480854
973 04:40:30.483842 RX Vref 32 -> 127, step: 1
974 04:40:30.483927
975 04:40:30.487327 RX Delay -95 -> 252, step: 8
976 04:40:30.487412
977 04:40:30.490978 Set Vref, RX VrefLevel [Byte0]: 32
978 04:40:30.494135 [Byte1]: 32
979 04:40:30.494222
980 04:40:30.497621 Set Vref, RX VrefLevel [Byte0]: 33
981 04:40:30.500643 [Byte1]: 33
982 04:40:30.500729
983 04:40:30.504399 Set Vref, RX VrefLevel [Byte0]: 34
984 04:40:30.507268 [Byte1]: 34
985 04:40:30.511461
986 04:40:30.511586 Set Vref, RX VrefLevel [Byte0]: 35
987 04:40:30.515302 [Byte1]: 35
988 04:40:30.519458
989 04:40:30.519580 Set Vref, RX VrefLevel [Byte0]: 36
990 04:40:30.522571 [Byte1]: 36
991 04:40:30.527130
992 04:40:30.527210 Set Vref, RX VrefLevel [Byte0]: 37
993 04:40:30.530146 [Byte1]: 37
994 04:40:30.534473
995 04:40:30.534561 Set Vref, RX VrefLevel [Byte0]: 38
996 04:40:30.538186 [Byte1]: 38
997 04:40:30.541963
998 04:40:30.542049 Set Vref, RX VrefLevel [Byte0]: 39
999 04:40:30.545283 [Byte1]: 39
1000 04:40:30.550073
1001 04:40:30.550165 Set Vref, RX VrefLevel [Byte0]: 40
1002 04:40:30.553200 [Byte1]: 40
1003 04:40:30.556978
1004 04:40:30.557065 Set Vref, RX VrefLevel [Byte0]: 41
1005 04:40:30.560032 [Byte1]: 41
1006 04:40:30.564843
1007 04:40:30.564931 Set Vref, RX VrefLevel [Byte0]: 42
1008 04:40:30.567621 [Byte1]: 42
1009 04:40:30.572284
1010 04:40:30.572372 Set Vref, RX VrefLevel [Byte0]: 43
1011 04:40:30.575543 [Byte1]: 43
1012 04:40:30.580199
1013 04:40:30.580293 Set Vref, RX VrefLevel [Byte0]: 44
1014 04:40:30.583005 [Byte1]: 44
1015 04:40:30.587600
1016 04:40:30.587691 Set Vref, RX VrefLevel [Byte0]: 45
1017 04:40:30.590958 [Byte1]: 45
1018 04:40:30.595118
1019 04:40:30.595212 Set Vref, RX VrefLevel [Byte0]: 46
1020 04:40:30.598318 [Byte1]: 46
1021 04:40:30.602437
1022 04:40:30.602523 Set Vref, RX VrefLevel [Byte0]: 47
1023 04:40:30.605943 [Byte1]: 47
1024 04:40:30.610415
1025 04:40:30.610504 Set Vref, RX VrefLevel [Byte0]: 48
1026 04:40:30.613447 [Byte1]: 48
1027 04:40:30.617707
1028 04:40:30.617791 Set Vref, RX VrefLevel [Byte0]: 49
1029 04:40:30.620832 [Byte1]: 49
1030 04:40:30.625229
1031 04:40:30.625315 Set Vref, RX VrefLevel [Byte0]: 50
1032 04:40:30.628391 [Byte1]: 50
1033 04:40:30.633292
1034 04:40:30.633380 Set Vref, RX VrefLevel [Byte0]: 51
1035 04:40:30.636311 [Byte1]: 51
1036 04:40:30.640697
1037 04:40:30.640784 Set Vref, RX VrefLevel [Byte0]: 52
1038 04:40:30.643717 [Byte1]: 52
1039 04:40:30.647999
1040 04:40:30.648088 Set Vref, RX VrefLevel [Byte0]: 53
1041 04:40:30.651802 [Byte1]: 53
1042 04:40:30.655467
1043 04:40:30.655605 Set Vref, RX VrefLevel [Byte0]: 54
1044 04:40:30.659150 [Byte1]: 54
1045 04:40:30.663449
1046 04:40:30.663554 Set Vref, RX VrefLevel [Byte0]: 55
1047 04:40:30.666624 [Byte1]: 55
1048 04:40:30.670790
1049 04:40:30.670872 Set Vref, RX VrefLevel [Byte0]: 56
1050 04:40:30.674539 [Byte1]: 56
1051 04:40:30.678848
1052 04:40:30.678931 Set Vref, RX VrefLevel [Byte0]: 57
1053 04:40:30.681887 [Byte1]: 57
1054 04:40:30.686033
1055 04:40:30.686116 Set Vref, RX VrefLevel [Byte0]: 58
1056 04:40:30.689238 [Byte1]: 58
1057 04:40:30.693854
1058 04:40:30.693939 Set Vref, RX VrefLevel [Byte0]: 59
1059 04:40:30.697053 [Byte1]: 59
1060 04:40:30.701350
1061 04:40:30.701436 Set Vref, RX VrefLevel [Byte0]: 60
1062 04:40:30.705045 [Byte1]: 60
1063 04:40:30.708727
1064 04:40:30.708806 Set Vref, RX VrefLevel [Byte0]: 61
1065 04:40:30.712137 [Byte1]: 61
1066 04:40:30.716511
1067 04:40:30.716595 Set Vref, RX VrefLevel [Byte0]: 62
1068 04:40:30.719784 [Byte1]: 62
1069 04:40:30.724344
1070 04:40:30.724432 Set Vref, RX VrefLevel [Byte0]: 63
1071 04:40:30.727308 [Byte1]: 63
1072 04:40:30.731493
1073 04:40:30.731612 Set Vref, RX VrefLevel [Byte0]: 64
1074 04:40:30.735329 [Byte1]: 64
1075 04:40:30.739397
1076 04:40:30.739536 Set Vref, RX VrefLevel [Byte0]: 65
1077 04:40:30.742697 [Byte1]: 65
1078 04:40:30.747321
1079 04:40:30.747445 Set Vref, RX VrefLevel [Byte0]: 66
1080 04:40:30.750472 [Byte1]: 66
1081 04:40:30.754753
1082 04:40:30.754827 Set Vref, RX VrefLevel [Byte0]: 67
1083 04:40:30.757834 [Byte1]: 67
1084 04:40:30.762324
1085 04:40:30.762413 Set Vref, RX VrefLevel [Byte0]: 68
1086 04:40:30.765461 [Byte1]: 68
1087 04:40:30.769733
1088 04:40:30.769818 Set Vref, RX VrefLevel [Byte0]: 69
1089 04:40:30.772912 [Byte1]: 69
1090 04:40:30.777115
1091 04:40:30.777199 Set Vref, RX VrefLevel [Byte0]: 70
1092 04:40:30.780908 [Byte1]: 70
1093 04:40:30.784751
1094 04:40:30.784855 Set Vref, RX VrefLevel [Byte0]: 71
1095 04:40:30.788444 [Byte1]: 71
1096 04:40:30.792871
1097 04:40:30.792975 Set Vref, RX VrefLevel [Byte0]: 72
1098 04:40:30.795970 [Byte1]: 72
1099 04:40:30.799996
1100 04:40:30.800080 Set Vref, RX VrefLevel [Byte0]: 73
1101 04:40:30.803881 [Byte1]: 73
1102 04:40:30.807535
1103 04:40:30.807623 Set Vref, RX VrefLevel [Byte0]: 74
1104 04:40:30.811155 [Byte1]: 74
1105 04:40:30.815270
1106 04:40:30.815354 Set Vref, RX VrefLevel [Byte0]: 75
1107 04:40:30.818530 [Byte1]: 75
1108 04:40:30.822829
1109 04:40:30.822914 Set Vref, RX VrefLevel [Byte0]: 76
1110 04:40:30.826140 [Byte1]: 76
1111 04:40:30.830582
1112 04:40:30.830684 Set Vref, RX VrefLevel [Byte0]: 77
1113 04:40:30.834091 [Byte1]: 77
1114 04:40:30.837915
1115 04:40:30.838001 Final RX Vref Byte 0 = 54 to rank0
1116 04:40:30.841606 Final RX Vref Byte 1 = 65 to rank0
1117 04:40:30.844930 Final RX Vref Byte 0 = 54 to rank1
1118 04:40:30.848642 Final RX Vref Byte 1 = 65 to rank1==
1119 04:40:30.851726 Dram Type= 6, Freq= 0, CH_0, rank 0
1120 04:40:30.854818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1121 04:40:30.858575 ==
1122 04:40:30.858664 DQS Delay:
1123 04:40:30.858732 DQS0 = 0, DQS1 = 0
1124 04:40:30.861737 DQM Delay:
1125 04:40:30.861823 DQM0 = 91, DQM1 = 86
1126 04:40:30.864894 DQ Delay:
1127 04:40:30.864978 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1128 04:40:30.868014 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1129 04:40:30.871735 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =80
1130 04:40:30.878027 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1131 04:40:30.878112
1132 04:40:30.878177
1133 04:40:30.885114 [DQSOSCAuto] RK0, (LSB)MR18= 0x493f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1134 04:40:30.888329 CH0 RK0: MR19=606, MR18=493F
1135 04:40:30.895051 CH0_RK0: MR19=0x606, MR18=0x493F, DQSOSC=391, MR23=63, INC=96, DEC=64
1136 04:40:30.895137
1137 04:40:30.898710 ----->DramcWriteLeveling(PI) begin...
1138 04:40:30.898811 ==
1139 04:40:30.901884 Dram Type= 6, Freq= 0, CH_0, rank 1
1140 04:40:30.905001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1141 04:40:30.905086 ==
1142 04:40:30.908690 Write leveling (Byte 0): 36 => 36
1143 04:40:30.911815 Write leveling (Byte 1): 30 => 30
1144 04:40:30.914949 DramcWriteLeveling(PI) end<-----
1145 04:40:30.915032
1146 04:40:30.915096 ==
1147 04:40:30.918644 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 04:40:30.921751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1149 04:40:30.921836 ==
1150 04:40:30.965664 [Gating] SW mode calibration
1151 04:40:30.966006 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1152 04:40:30.966098 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1153 04:40:30.966182 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 04:40:30.966259 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1155 04:40:30.966326 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1156 04:40:30.966466 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 04:40:30.966574 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 04:40:30.966664 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 04:40:30.972083 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 04:40:30.972261 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 04:40:30.975198 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 04:40:30.981986 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 04:40:30.985694 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 04:40:30.988691 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 04:40:30.995707 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 04:40:30.998893 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 04:40:31.001995 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 04:40:31.008704 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 04:40:31.011866 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 04:40:31.014953 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 04:40:31.021765 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1172 04:40:31.025672 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 04:40:31.028601 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 04:40:31.035501 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 04:40:31.038628 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 04:40:31.042196 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 04:40:31.048960 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 04:40:31.052043 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 04:40:31.055235 0 9 8 | B1->B0 | 2e2e 2c2c | 1 0 | (1 1) (0 0)
1180 04:40:31.058961 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 04:40:31.065403 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 04:40:31.068957 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 04:40:31.071867 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 04:40:31.078664 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 04:40:31.081899 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 04:40:31.085587 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 04:40:31.091903 0 10 8 | B1->B0 | 2c2c 2a2a | 1 0 | (1 0) (0 1)
1188 04:40:31.096064 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 04:40:31.099751 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 04:40:31.103610 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 04:40:31.107308 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 04:40:31.114236 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 04:40:31.117994 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 04:40:31.121177 0 11 4 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
1195 04:40:31.124995 0 11 8 | B1->B0 | 3d3d 3939 | 1 0 | (0 0) (0 0)
1196 04:40:31.131611 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 04:40:31.135293 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 04:40:31.138341 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 04:40:31.145224 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 04:40:31.148397 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 04:40:31.151363 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 04:40:31.158282 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 04:40:31.161348 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1204 04:40:31.165070 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 04:40:31.171792 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 04:40:31.174861 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 04:40:31.178517 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 04:40:31.185197 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 04:40:31.188072 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 04:40:31.191624 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 04:40:31.195246 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 04:40:31.201898 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 04:40:31.204815 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 04:40:31.207997 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 04:40:31.215232 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 04:40:31.218288 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 04:40:31.221994 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 04:40:31.228303 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 04:40:31.231469 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1220 04:40:31.235175 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 04:40:31.238309 Total UI for P1: 0, mck2ui 16
1222 04:40:31.241337 best dqsien dly found for B0: ( 0, 14, 8)
1223 04:40:31.245104 Total UI for P1: 0, mck2ui 16
1224 04:40:31.248262 best dqsien dly found for B1: ( 0, 14, 8)
1225 04:40:31.251400 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1226 04:40:31.255033 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1227 04:40:31.255157
1228 04:40:31.258108 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 04:40:31.264783 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1230 04:40:31.264882 [Gating] SW calibration Done
1231 04:40:31.264947 ==
1232 04:40:31.268590 Dram Type= 6, Freq= 0, CH_0, rank 1
1233 04:40:31.274795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1234 04:40:31.274875 ==
1235 04:40:31.274940 RX Vref Scan: 0
1236 04:40:31.275031
1237 04:40:31.278687 RX Vref 0 -> 0, step: 1
1238 04:40:31.278761
1239 04:40:31.281611 RX Delay -130 -> 252, step: 16
1240 04:40:31.285079 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1241 04:40:31.288342 iDelay=222, Bit 1, Center 101 (-2 ~ 205) 208
1242 04:40:31.291912 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1243 04:40:31.298528 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1244 04:40:31.302194 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1245 04:40:31.305385 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1246 04:40:31.308348 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1247 04:40:31.312088 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1248 04:40:31.315117 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1249 04:40:31.321918 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1250 04:40:31.325406 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1251 04:40:31.328396 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1252 04:40:31.332143 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1253 04:40:31.338445 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1254 04:40:31.341698 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1255 04:40:31.345247 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1256 04:40:31.345363 ==
1257 04:40:31.348437 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 04:40:31.352168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1259 04:40:31.352254 ==
1260 04:40:31.355219 DQS Delay:
1261 04:40:31.355302 DQS0 = 0, DQS1 = 0
1262 04:40:31.355367 DQM Delay:
1263 04:40:31.358506 DQM0 = 94, DQM1 = 82
1264 04:40:31.358589 DQ Delay:
1265 04:40:31.362215 DQ0 =93, DQ1 =101, DQ2 =85, DQ3 =85
1266 04:40:31.365145 DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =109
1267 04:40:31.368703 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1268 04:40:31.372370 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
1269 04:40:31.372454
1270 04:40:31.372518
1271 04:40:31.372577 ==
1272 04:40:31.375410 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 04:40:31.382231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 04:40:31.382331 ==
1275 04:40:31.382412
1276 04:40:31.382472
1277 04:40:31.382529 TX Vref Scan disable
1278 04:40:31.386015 == TX Byte 0 ==
1279 04:40:31.388913 Update DQ dly =587 (2 ,2, 11) DQ OEN =(1 ,7)
1280 04:40:31.392764 Update DQM dly =587 (2 ,2, 11) DQM OEN =(1 ,7)
1281 04:40:31.395855 == TX Byte 1 ==
1282 04:40:31.399511 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1283 04:40:31.402613 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1284 04:40:31.405722 ==
1285 04:40:31.409520 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 04:40:31.412569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 04:40:31.412728 ==
1288 04:40:31.425466 TX Vref=22, minBit 11, minWin=27, winSum=448
1289 04:40:31.428860 TX Vref=24, minBit 1, minWin=28, winSum=452
1290 04:40:31.432638 TX Vref=26, minBit 4, minWin=28, winSum=456
1291 04:40:31.435535 TX Vref=28, minBit 1, minWin=28, winSum=458
1292 04:40:31.439294 TX Vref=30, minBit 7, minWin=28, winSum=459
1293 04:40:31.442507 TX Vref=32, minBit 2, minWin=28, winSum=456
1294 04:40:31.449042 [TxChooseVref] Worse bit 7, Min win 28, Win sum 459, Final Vref 30
1295 04:40:31.449151
1296 04:40:31.452239 Final TX Range 1 Vref 30
1297 04:40:31.452325
1298 04:40:31.452392 ==
1299 04:40:31.456070 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 04:40:31.459085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 04:40:31.459203 ==
1302 04:40:31.459296
1303 04:40:31.459394
1304 04:40:31.462872 TX Vref Scan disable
1305 04:40:31.466058 == TX Byte 0 ==
1306 04:40:31.469112 Update DQ dly =587 (2 ,2, 11) DQ OEN =(1 ,7)
1307 04:40:31.472689 Update DQM dly =587 (2 ,2, 11) DQM OEN =(1 ,7)
1308 04:40:31.475688 == TX Byte 1 ==
1309 04:40:31.479412 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1310 04:40:31.482592 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1311 04:40:31.482679
1312 04:40:31.485638 [DATLAT]
1313 04:40:31.485722 Freq=800, CH0 RK1
1314 04:40:31.485790
1315 04:40:31.489404 DATLAT Default: 0xa
1316 04:40:31.489488 0, 0xFFFF, sum = 0
1317 04:40:31.492466 1, 0xFFFF, sum = 0
1318 04:40:31.492552 2, 0xFFFF, sum = 0
1319 04:40:31.495985 3, 0xFFFF, sum = 0
1320 04:40:31.496099 4, 0xFFFF, sum = 0
1321 04:40:31.499266 5, 0xFFFF, sum = 0
1322 04:40:31.499353 6, 0xFFFF, sum = 0
1323 04:40:31.502204 7, 0xFFFF, sum = 0
1324 04:40:31.505898 8, 0xFFFF, sum = 0
1325 04:40:31.505984 9, 0x0, sum = 1
1326 04:40:31.506052 10, 0x0, sum = 2
1327 04:40:31.508967 11, 0x0, sum = 3
1328 04:40:31.509086 12, 0x0, sum = 4
1329 04:40:31.512733 best_step = 10
1330 04:40:31.512818
1331 04:40:31.512883 ==
1332 04:40:31.515909 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 04:40:31.518899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 04:40:31.518979 ==
1335 04:40:31.522410 RX Vref Scan: 0
1336 04:40:31.522484
1337 04:40:31.522549 RX Vref 0 -> 0, step: 1
1338 04:40:31.522609
1339 04:40:31.525992 RX Delay -79 -> 252, step: 8
1340 04:40:31.532606 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1341 04:40:31.535684 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1342 04:40:31.539339 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1343 04:40:31.542491 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1344 04:40:31.546241 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1345 04:40:31.552788 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1346 04:40:31.555884 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1347 04:40:31.559010 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1348 04:40:31.562167 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1349 04:40:31.565858 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1350 04:40:31.569077 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1351 04:40:31.575884 iDelay=209, Bit 11, Center 72 (-31 ~ 176) 208
1352 04:40:31.579380 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1353 04:40:31.582807 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1354 04:40:31.586192 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1355 04:40:31.592745 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1356 04:40:31.592826 ==
1357 04:40:31.596331 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 04:40:31.599373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 04:40:31.599457 ==
1360 04:40:31.599546 DQS Delay:
1361 04:40:31.602534 DQS0 = 0, DQS1 = 0
1362 04:40:31.602626 DQM Delay:
1363 04:40:31.606156 DQM0 = 93, DQM1 = 82
1364 04:40:31.606238 DQ Delay:
1365 04:40:31.609292 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1366 04:40:31.612958 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1367 04:40:31.616057 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =72
1368 04:40:31.619831 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =88
1369 04:40:31.619916
1370 04:40:31.619980
1371 04:40:31.625934 [DQSOSCAuto] RK1, (LSB)MR18= 0x4111, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1372 04:40:31.629681 CH0 RK1: MR19=606, MR18=4111
1373 04:40:31.636368 CH0_RK1: MR19=0x606, MR18=0x4111, DQSOSC=393, MR23=63, INC=95, DEC=63
1374 04:40:31.639483 [RxdqsGatingPostProcess] freq 800
1375 04:40:31.642771 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1376 04:40:31.646432 Pre-setting of DQS Precalculation
1377 04:40:31.653036 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1378 04:40:31.653121 ==
1379 04:40:31.656040 Dram Type= 6, Freq= 0, CH_1, rank 0
1380 04:40:31.659828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 04:40:31.659912 ==
1382 04:40:31.665882 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1383 04:40:31.672819 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1384 04:40:31.680646 [CA 0] Center 36 (6~67) winsize 62
1385 04:40:31.683766 [CA 1] Center 36 (6~67) winsize 62
1386 04:40:31.687351 [CA 2] Center 34 (4~65) winsize 62
1387 04:40:31.690806 [CA 3] Center 34 (4~65) winsize 62
1388 04:40:31.694308 [CA 4] Center 34 (4~65) winsize 62
1389 04:40:31.697623 [CA 5] Center 34 (4~64) winsize 61
1390 04:40:31.697746
1391 04:40:31.700748 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1392 04:40:31.700831
1393 04:40:31.703945 [CATrainingPosCal] consider 1 rank data
1394 04:40:31.707654 u2DelayCellTimex100 = 270/100 ps
1395 04:40:31.710650 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 04:40:31.714382 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1397 04:40:31.720516 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1398 04:40:31.724306 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1399 04:40:31.727308 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1400 04:40:31.730935 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1401 04:40:31.731077
1402 04:40:31.734009 CA PerBit enable=1, Macro0, CA PI delay=34
1403 04:40:31.734122
1404 04:40:31.737582 [CBTSetCACLKResult] CA Dly = 34
1405 04:40:31.737691 CS Dly: 5 (0~36)
1406 04:40:31.737795 ==
1407 04:40:31.740622 Dram Type= 6, Freq= 0, CH_1, rank 1
1408 04:40:31.747400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1409 04:40:31.747523 ==
1410 04:40:31.750481 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1411 04:40:31.757246 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1412 04:40:31.767088 [CA 0] Center 36 (6~67) winsize 62
1413 04:40:31.770659 [CA 1] Center 37 (6~68) winsize 63
1414 04:40:31.774464 [CA 2] Center 35 (4~66) winsize 63
1415 04:40:31.778074 [CA 3] Center 34 (4~65) winsize 62
1416 04:40:31.781792 [CA 4] Center 35 (5~65) winsize 61
1417 04:40:31.781912 [CA 5] Center 34 (4~65) winsize 62
1418 04:40:31.785584
1419 04:40:31.789456 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1420 04:40:31.789551
1421 04:40:31.793086 [CATrainingPosCal] consider 2 rank data
1422 04:40:31.793163 u2DelayCellTimex100 = 270/100 ps
1423 04:40:31.796749 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 04:40:31.802978 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1425 04:40:31.806611 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 04:40:31.810354 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1427 04:40:31.813275 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1428 04:40:31.816436 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1429 04:40:31.816509
1430 04:40:31.819650 CA PerBit enable=1, Macro0, CA PI delay=34
1431 04:40:31.819722
1432 04:40:31.823388 [CBTSetCACLKResult] CA Dly = 34
1433 04:40:31.823488 CS Dly: 6 (0~38)
1434 04:40:31.823570
1435 04:40:31.826315 ----->DramcWriteLeveling(PI) begin...
1436 04:40:31.829960 ==
1437 04:40:31.833416 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 04:40:31.836473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 04:40:31.836548 ==
1440 04:40:31.840062 Write leveling (Byte 0): 26 => 26
1441 04:40:31.843097 Write leveling (Byte 1): 29 => 29
1442 04:40:31.846832 DramcWriteLeveling(PI) end<-----
1443 04:40:31.846946
1444 04:40:31.847043 ==
1445 04:40:31.849815 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 04:40:31.852990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 04:40:31.853097 ==
1448 04:40:31.856648 [Gating] SW mode calibration
1449 04:40:31.863458 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1450 04:40:31.866565 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1451 04:40:31.873505 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1452 04:40:31.876791 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1453 04:40:31.879833 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 04:40:31.886626 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 04:40:31.889718 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 04:40:31.893410 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 04:40:31.900107 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 04:40:31.903227 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 04:40:31.906725 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 04:40:31.913555 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 04:40:31.916594 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 04:40:31.920265 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 04:40:31.927081 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 04:40:31.929951 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 04:40:31.933442 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 04:40:31.936738 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 04:40:31.943501 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1468 04:40:31.946929 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 04:40:31.950499 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1470 04:40:31.957145 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 04:40:31.960118 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 04:40:31.964015 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 04:40:31.970493 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 04:40:31.973527 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 04:40:31.977315 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 04:40:31.983573 0 9 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1477 04:40:31.986742 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1478 04:40:31.990433 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 04:40:31.997346 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 04:40:32.000373 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 04:40:32.003499 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 04:40:32.010224 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 04:40:32.013984 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 04:40:32.017118 0 10 4 | B1->B0 | 3333 2d2d | 0 0 | (0 1) (0 1)
1485 04:40:32.020285 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1486 04:40:32.026932 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 04:40:32.030131 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 04:40:32.033940 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 04:40:32.040252 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 04:40:32.043975 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 04:40:32.046955 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 04:40:32.053786 0 11 4 | B1->B0 | 2b2b 3a3a | 0 0 | (0 0) (0 0)
1493 04:40:32.057102 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1494 04:40:32.060713 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 04:40:32.067335 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 04:40:32.070224 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 04:40:32.073569 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 04:40:32.080226 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 04:40:32.083421 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 04:40:32.087354 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1501 04:40:32.093875 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 04:40:32.097275 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 04:40:32.100639 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 04:40:32.103541 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 04:40:32.110386 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 04:40:32.114263 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 04:40:32.117235 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 04:40:32.123523 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 04:40:32.127256 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 04:40:32.130312 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 04:40:32.137240 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 04:40:32.140371 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 04:40:32.143563 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 04:40:32.150643 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 04:40:32.153757 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 04:40:32.156823 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1517 04:40:32.163741 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 04:40:32.163828 Total UI for P1: 0, mck2ui 16
1519 04:40:32.170085 best dqsien dly found for B0: ( 0, 14, 6)
1520 04:40:32.170199 Total UI for P1: 0, mck2ui 16
1521 04:40:32.177020 best dqsien dly found for B1: ( 0, 14, 4)
1522 04:40:32.180230 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1523 04:40:32.183769 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1524 04:40:32.183881
1525 04:40:32.186882 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1526 04:40:32.190487 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1527 04:40:32.193699 [Gating] SW calibration Done
1528 04:40:32.193810 ==
1529 04:40:32.197281 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 04:40:32.200228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 04:40:32.200345 ==
1532 04:40:32.203610 RX Vref Scan: 0
1533 04:40:32.203720
1534 04:40:32.203800 RX Vref 0 -> 0, step: 1
1535 04:40:32.203862
1536 04:40:32.207048 RX Delay -130 -> 252, step: 16
1537 04:40:32.210455 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1538 04:40:32.217315 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1539 04:40:32.220614 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1540 04:40:32.224008 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1541 04:40:32.226963 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1542 04:40:32.230693 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1543 04:40:32.233683 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1544 04:40:32.240587 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1545 04:40:32.243724 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1546 04:40:32.247417 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1547 04:40:32.250597 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1548 04:40:32.254259 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1549 04:40:32.260476 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1550 04:40:32.263760 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1551 04:40:32.267482 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1552 04:40:32.270511 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1553 04:40:32.270590 ==
1554 04:40:32.273815 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 04:40:32.280573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 04:40:32.280682 ==
1557 04:40:32.280753 DQS Delay:
1558 04:40:32.280815 DQS0 = 0, DQS1 = 0
1559 04:40:32.284240 DQM Delay:
1560 04:40:32.284317 DQM0 = 94, DQM1 = 89
1561 04:40:32.287376 DQ Delay:
1562 04:40:32.290920 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1563 04:40:32.294039 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1564 04:40:32.297152 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1565 04:40:32.300881 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1566 04:40:32.301006
1567 04:40:32.301102
1568 04:40:32.301191 ==
1569 04:40:32.303961 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 04:40:32.307650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 04:40:32.307743 ==
1572 04:40:32.307808
1573 04:40:32.307869
1574 04:40:32.310533 TX Vref Scan disable
1575 04:40:32.310602 == TX Byte 0 ==
1576 04:40:32.317438 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1577 04:40:32.321079 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1578 04:40:32.321166 == TX Byte 1 ==
1579 04:40:32.327677 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1580 04:40:32.331021 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1581 04:40:32.331143 ==
1582 04:40:32.334426 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 04:40:32.337905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 04:40:32.337985 ==
1585 04:40:32.351316 TX Vref=22, minBit 1, minWin=26, winSum=435
1586 04:40:32.354567 TX Vref=24, minBit 1, minWin=26, winSum=439
1587 04:40:32.358383 TX Vref=26, minBit 2, minWin=27, winSum=445
1588 04:40:32.361487 TX Vref=28, minBit 3, minWin=26, winSum=445
1589 04:40:32.364736 TX Vref=30, minBit 0, minWin=27, winSum=447
1590 04:40:32.368350 TX Vref=32, minBit 3, minWin=26, winSum=443
1591 04:40:32.374736 [TxChooseVref] Worse bit 0, Min win 27, Win sum 447, Final Vref 30
1592 04:40:32.374816
1593 04:40:32.378543 Final TX Range 1 Vref 30
1594 04:40:32.378618
1595 04:40:32.378694 ==
1596 04:40:32.381483 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 04:40:32.384882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 04:40:32.384960 ==
1599 04:40:32.385023
1600 04:40:32.385081
1601 04:40:32.388233 TX Vref Scan disable
1602 04:40:32.391501 == TX Byte 0 ==
1603 04:40:32.394537 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1604 04:40:32.398344 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1605 04:40:32.401861 == TX Byte 1 ==
1606 04:40:32.404865 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1607 04:40:32.408069 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1608 04:40:32.408155
1609 04:40:32.411775 [DATLAT]
1610 04:40:32.411888 Freq=800, CH1 RK0
1611 04:40:32.411983
1612 04:40:32.414864 DATLAT Default: 0xa
1613 04:40:32.414949 0, 0xFFFF, sum = 0
1614 04:40:32.418552 1, 0xFFFF, sum = 0
1615 04:40:32.418638 2, 0xFFFF, sum = 0
1616 04:40:32.421678 3, 0xFFFF, sum = 0
1617 04:40:32.421795 4, 0xFFFF, sum = 0
1618 04:40:32.424884 5, 0xFFFF, sum = 0
1619 04:40:32.424998 6, 0xFFFF, sum = 0
1620 04:40:32.428631 7, 0xFFFF, sum = 0
1621 04:40:32.428719 8, 0xFFFF, sum = 0
1622 04:40:32.431823 9, 0x0, sum = 1
1623 04:40:32.431910 10, 0x0, sum = 2
1624 04:40:32.435389 11, 0x0, sum = 3
1625 04:40:32.435521 12, 0x0, sum = 4
1626 04:40:32.438404 best_step = 10
1627 04:40:32.438488
1628 04:40:32.438553 ==
1629 04:40:32.442067 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 04:40:32.445303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 04:40:32.445415 ==
1632 04:40:32.448494 RX Vref Scan: 1
1633 04:40:32.448646
1634 04:40:32.448785 Set Vref Range= 32 -> 127
1635 04:40:32.448916
1636 04:40:32.451439 RX Vref 32 -> 127, step: 1
1637 04:40:32.451558
1638 04:40:32.455114 RX Delay -63 -> 252, step: 8
1639 04:40:32.455198
1640 04:40:32.458053 Set Vref, RX VrefLevel [Byte0]: 32
1641 04:40:32.461418 [Byte1]: 32
1642 04:40:32.461502
1643 04:40:32.464690 Set Vref, RX VrefLevel [Byte0]: 33
1644 04:40:32.468511 [Byte1]: 33
1645 04:40:32.471356
1646 04:40:32.471472 Set Vref, RX VrefLevel [Byte0]: 34
1647 04:40:32.475069 [Byte1]: 34
1648 04:40:32.478745
1649 04:40:32.478856 Set Vref, RX VrefLevel [Byte0]: 35
1650 04:40:32.482562 [Byte1]: 35
1651 04:40:32.486348
1652 04:40:32.486455 Set Vref, RX VrefLevel [Byte0]: 36
1653 04:40:32.490054 [Byte1]: 36
1654 04:40:32.493749
1655 04:40:32.493837 Set Vref, RX VrefLevel [Byte0]: 37
1656 04:40:32.497302 [Byte1]: 37
1657 04:40:32.501370
1658 04:40:32.501457 Set Vref, RX VrefLevel [Byte0]: 38
1659 04:40:32.504491 [Byte1]: 38
1660 04:40:32.508685
1661 04:40:32.508775 Set Vref, RX VrefLevel [Byte0]: 39
1662 04:40:32.512344 [Byte1]: 39
1663 04:40:32.516459
1664 04:40:32.516546 Set Vref, RX VrefLevel [Byte0]: 40
1665 04:40:32.519548 [Byte1]: 40
1666 04:40:32.523801
1667 04:40:32.523888 Set Vref, RX VrefLevel [Byte0]: 41
1668 04:40:32.526970 [Byte1]: 41
1669 04:40:32.531505
1670 04:40:32.531599 Set Vref, RX VrefLevel [Byte0]: 42
1671 04:40:32.534527 [Byte1]: 42
1672 04:40:32.538837
1673 04:40:32.538919 Set Vref, RX VrefLevel [Byte0]: 43
1674 04:40:32.542332 [Byte1]: 43
1675 04:40:32.546605
1676 04:40:32.546699 Set Vref, RX VrefLevel [Byte0]: 44
1677 04:40:32.549764 [Byte1]: 44
1678 04:40:32.554016
1679 04:40:32.557171 Set Vref, RX VrefLevel [Byte0]: 45
1680 04:40:32.560181 [Byte1]: 45
1681 04:40:32.560266
1682 04:40:32.563894 Set Vref, RX VrefLevel [Byte0]: 46
1683 04:40:32.566972 [Byte1]: 46
1684 04:40:32.567060
1685 04:40:32.570751 Set Vref, RX VrefLevel [Byte0]: 47
1686 04:40:32.573614 [Byte1]: 47
1687 04:40:32.573700
1688 04:40:32.577161 Set Vref, RX VrefLevel [Byte0]: 48
1689 04:40:32.580710 [Byte1]: 48
1690 04:40:32.584180
1691 04:40:32.584266 Set Vref, RX VrefLevel [Byte0]: 49
1692 04:40:32.587156 [Byte1]: 49
1693 04:40:32.591268
1694 04:40:32.591359 Set Vref, RX VrefLevel [Byte0]: 50
1695 04:40:32.594793 [Byte1]: 50
1696 04:40:32.598696
1697 04:40:32.598783 Set Vref, RX VrefLevel [Byte0]: 51
1698 04:40:32.602539 [Byte1]: 51
1699 04:40:32.606268
1700 04:40:32.606356 Set Vref, RX VrefLevel [Byte0]: 52
1701 04:40:32.609864 [Byte1]: 52
1702 04:40:32.613908
1703 04:40:32.613995 Set Vref, RX VrefLevel [Byte0]: 53
1704 04:40:32.617325 [Byte1]: 53
1705 04:40:32.621554
1706 04:40:32.621639 Set Vref, RX VrefLevel [Byte0]: 54
1707 04:40:32.624671 [Byte1]: 54
1708 04:40:32.628674
1709 04:40:32.628759 Set Vref, RX VrefLevel [Byte0]: 55
1710 04:40:32.632338 [Byte1]: 55
1711 04:40:32.636672
1712 04:40:32.636798 Set Vref, RX VrefLevel [Byte0]: 56
1713 04:40:32.639750 [Byte1]: 56
1714 04:40:32.644186
1715 04:40:32.644295 Set Vref, RX VrefLevel [Byte0]: 57
1716 04:40:32.647167 [Byte1]: 57
1717 04:40:32.651442
1718 04:40:32.651564 Set Vref, RX VrefLevel [Byte0]: 58
1719 04:40:32.654957 [Byte1]: 58
1720 04:40:32.658753
1721 04:40:32.658865 Set Vref, RX VrefLevel [Byte0]: 59
1722 04:40:32.662505 [Byte1]: 59
1723 04:40:32.666183
1724 04:40:32.666269 Set Vref, RX VrefLevel [Byte0]: 60
1725 04:40:32.670036 [Byte1]: 60
1726 04:40:32.673914
1727 04:40:32.674000 Set Vref, RX VrefLevel [Byte0]: 61
1728 04:40:32.677025 [Byte1]: 61
1729 04:40:32.681255
1730 04:40:32.681341 Set Vref, RX VrefLevel [Byte0]: 62
1731 04:40:32.684466 [Byte1]: 62
1732 04:40:32.689085
1733 04:40:32.689201 Set Vref, RX VrefLevel [Byte0]: 63
1734 04:40:32.692261 [Byte1]: 63
1735 04:40:32.696202
1736 04:40:32.696314 Set Vref, RX VrefLevel [Byte0]: 64
1737 04:40:32.699754 [Byte1]: 64
1738 04:40:32.704044
1739 04:40:32.704175 Set Vref, RX VrefLevel [Byte0]: 65
1740 04:40:32.707156 [Byte1]: 65
1741 04:40:32.711495
1742 04:40:32.711588 Set Vref, RX VrefLevel [Byte0]: 66
1743 04:40:32.714533 [Byte1]: 66
1744 04:40:32.719036
1745 04:40:32.719148 Set Vref, RX VrefLevel [Byte0]: 67
1746 04:40:32.722067 [Byte1]: 67
1747 04:40:32.726268
1748 04:40:32.726376 Set Vref, RX VrefLevel [Byte0]: 68
1749 04:40:32.729642 [Byte1]: 68
1750 04:40:32.734099
1751 04:40:32.734215 Set Vref, RX VrefLevel [Byte0]: 69
1752 04:40:32.736829 [Byte1]: 69
1753 04:40:32.741303
1754 04:40:32.741411 Set Vref, RX VrefLevel [Byte0]: 70
1755 04:40:32.744898 [Byte1]: 70
1756 04:40:32.748910
1757 04:40:32.749023 Set Vref, RX VrefLevel [Byte0]: 71
1758 04:40:32.751954 [Byte1]: 71
1759 04:40:32.756179
1760 04:40:32.756297 Set Vref, RX VrefLevel [Byte0]: 72
1761 04:40:32.759749 [Byte1]: 72
1762 04:40:32.763958
1763 04:40:32.764077 Final RX Vref Byte 0 = 57 to rank0
1764 04:40:32.767235 Final RX Vref Byte 1 = 54 to rank0
1765 04:40:32.770323 Final RX Vref Byte 0 = 57 to rank1
1766 04:40:32.774202 Final RX Vref Byte 1 = 54 to rank1==
1767 04:40:32.777177 Dram Type= 6, Freq= 0, CH_1, rank 0
1768 04:40:32.780886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1769 04:40:32.783956 ==
1770 04:40:32.784068 DQS Delay:
1771 04:40:32.784172 DQS0 = 0, DQS1 = 0
1772 04:40:32.787186 DQM Delay:
1773 04:40:32.787304 DQM0 = 95, DQM1 = 89
1774 04:40:32.790906 DQ Delay:
1775 04:40:32.793784 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =96
1776 04:40:32.797486 DQ4 =96, DQ5 =108, DQ6 =100, DQ7 =92
1777 04:40:32.797595 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1778 04:40:32.803734 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1779 04:40:32.803846
1780 04:40:32.803940
1781 04:40:32.810839 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
1782 04:40:32.814194 CH1 RK0: MR19=606, MR18=2F4B
1783 04:40:32.820387 CH1_RK0: MR19=0x606, MR18=0x2F4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1784 04:40:32.820506
1785 04:40:32.824243 ----->DramcWriteLeveling(PI) begin...
1786 04:40:32.824357 ==
1787 04:40:32.827302 Dram Type= 6, Freq= 0, CH_1, rank 1
1788 04:40:32.830444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1789 04:40:32.830559 ==
1790 04:40:32.833984 Write leveling (Byte 0): 29 => 29
1791 04:40:32.837643 Write leveling (Byte 1): 29 => 29
1792 04:40:32.840697 DramcWriteLeveling(PI) end<-----
1793 04:40:32.840819
1794 04:40:32.840915 ==
1795 04:40:32.843777 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 04:40:32.847278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1797 04:40:32.847388 ==
1798 04:40:32.850895 [Gating] SW mode calibration
1799 04:40:32.857382 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1800 04:40:32.864149 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1801 04:40:32.867476 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1802 04:40:32.870556 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1803 04:40:32.877377 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 04:40:32.880551 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 04:40:32.883704 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 04:40:32.890737 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 04:40:32.893842 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 04:40:32.897611 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 04:40:32.903962 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 04:40:32.907762 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 04:40:32.910822 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 04:40:32.913988 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 04:40:32.921114 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 04:40:32.924260 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 04:40:32.927440 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 04:40:32.934367 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 04:40:32.937452 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1818 04:40:32.940695 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1819 04:40:32.947297 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1820 04:40:32.951027 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 04:40:32.954192 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 04:40:32.960735 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 04:40:32.963927 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 04:40:32.967227 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 04:40:32.974371 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 04:40:32.977323 0 9 4 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1827 04:40:32.980655 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1828 04:40:32.987339 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 04:40:32.990465 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 04:40:32.994284 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 04:40:33.000624 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 04:40:33.004191 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 04:40:33.007334 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1834 04:40:33.010633 0 10 4 | B1->B0 | 2a2a 3030 | 0 0 | (1 0) (0 1)
1835 04:40:33.017386 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 04:40:33.021058 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 04:40:33.024248 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 04:40:33.030800 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 04:40:33.034360 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 04:40:33.037385 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 04:40:33.044137 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 04:40:33.047707 0 11 4 | B1->B0 | 3838 2b2b | 0 0 | (1 1) (0 0)
1843 04:40:33.050667 0 11 8 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
1844 04:40:33.057451 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 04:40:33.060493 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 04:40:33.064233 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 04:40:33.070996 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 04:40:33.074121 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 04:40:33.077833 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 04:40:33.084169 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1851 04:40:33.087541 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 04:40:33.090913 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 04:40:33.094379 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 04:40:33.101110 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 04:40:33.104165 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 04:40:33.107290 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 04:40:33.113892 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 04:40:33.117683 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 04:40:33.120747 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 04:40:33.127346 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 04:40:33.131082 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 04:40:33.134331 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 04:40:33.140916 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 04:40:33.144332 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 04:40:33.147243 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1866 04:40:33.154290 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1867 04:40:33.157405 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1868 04:40:33.161052 Total UI for P1: 0, mck2ui 16
1869 04:40:33.164629 best dqsien dly found for B1: ( 0, 14, 2)
1870 04:40:33.167502 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 04:40:33.171208 Total UI for P1: 0, mck2ui 16
1872 04:40:33.174453 best dqsien dly found for B0: ( 0, 14, 8)
1873 04:40:33.177598 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1874 04:40:33.180717 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1875 04:40:33.180799
1876 04:40:33.184444 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1877 04:40:33.190637 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1878 04:40:33.190773 [Gating] SW calibration Done
1879 04:40:33.190879 ==
1880 04:40:33.194245 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 04:40:33.200934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1882 04:40:33.201012 ==
1883 04:40:33.201075 RX Vref Scan: 0
1884 04:40:33.201137
1885 04:40:33.204283 RX Vref 0 -> 0, step: 1
1886 04:40:33.204380
1887 04:40:33.207757 RX Delay -130 -> 252, step: 16
1888 04:40:33.211305 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1889 04:40:33.214464 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1890 04:40:33.217588 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1891 04:40:33.220744 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1892 04:40:33.227711 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1893 04:40:33.231187 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1894 04:40:33.234696 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1895 04:40:33.237703 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1896 04:40:33.240922 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1897 04:40:33.247601 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1898 04:40:33.250939 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1899 04:40:33.254605 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1900 04:40:33.257480 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1901 04:40:33.260840 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1902 04:40:33.267551 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1903 04:40:33.271392 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1904 04:40:33.271493 ==
1905 04:40:33.274408 Dram Type= 6, Freq= 0, CH_1, rank 1
1906 04:40:33.278122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1907 04:40:33.278205 ==
1908 04:40:33.281156 DQS Delay:
1909 04:40:33.281311 DQS0 = 0, DQS1 = 0
1910 04:40:33.281408 DQM Delay:
1911 04:40:33.284250 DQM0 = 92, DQM1 = 87
1912 04:40:33.284347 DQ Delay:
1913 04:40:33.288001 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1914 04:40:33.291699 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1915 04:40:33.294658 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1916 04:40:33.297824 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1917 04:40:33.297973
1918 04:40:33.298067
1919 04:40:33.298156 ==
1920 04:40:33.301069 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 04:40:33.307803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 04:40:33.307886 ==
1923 04:40:33.307953
1924 04:40:33.308018
1925 04:40:33.308076 TX Vref Scan disable
1926 04:40:33.311329 == TX Byte 0 ==
1927 04:40:33.314927 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1928 04:40:33.318413 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1929 04:40:33.321513 == TX Byte 1 ==
1930 04:40:33.324538 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1931 04:40:33.328346 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1932 04:40:33.331588 ==
1933 04:40:33.334605 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 04:40:33.337990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 04:40:33.338098 ==
1936 04:40:33.350624 TX Vref=22, minBit 1, minWin=27, winSum=445
1937 04:40:33.353663 TX Vref=24, minBit 2, minWin=27, winSum=449
1938 04:40:33.357279 TX Vref=26, minBit 1, minWin=27, winSum=448
1939 04:40:33.360104 TX Vref=28, minBit 2, minWin=27, winSum=451
1940 04:40:33.363710 TX Vref=30, minBit 2, minWin=27, winSum=452
1941 04:40:33.366870 TX Vref=32, minBit 2, minWin=27, winSum=451
1942 04:40:33.373588 [TxChooseVref] Worse bit 2, Min win 27, Win sum 452, Final Vref 30
1943 04:40:33.373707
1944 04:40:33.376922 Final TX Range 1 Vref 30
1945 04:40:33.377044
1946 04:40:33.377145 ==
1947 04:40:33.380839 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 04:40:33.384140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 04:40:33.384248 ==
1950 04:40:33.384350
1951 04:40:33.384456
1952 04:40:33.387212 TX Vref Scan disable
1953 04:40:33.390478 == TX Byte 0 ==
1954 04:40:33.394084 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1955 04:40:33.397144 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1956 04:40:33.400902 == TX Byte 1 ==
1957 04:40:33.404029 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1958 04:40:33.407281 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1959 04:40:33.407390
1960 04:40:33.410771 [DATLAT]
1961 04:40:33.410882 Freq=800, CH1 RK1
1962 04:40:33.410981
1963 04:40:33.413855 DATLAT Default: 0xa
1964 04:40:33.413966 0, 0xFFFF, sum = 0
1965 04:40:33.417480 1, 0xFFFF, sum = 0
1966 04:40:33.417592 2, 0xFFFF, sum = 0
1967 04:40:33.420593 3, 0xFFFF, sum = 0
1968 04:40:33.420697 4, 0xFFFF, sum = 0
1969 04:40:33.424217 5, 0xFFFF, sum = 0
1970 04:40:33.424335 6, 0xFFFF, sum = 0
1971 04:40:33.427171 7, 0xFFFF, sum = 0
1972 04:40:33.427279 8, 0xFFFF, sum = 0
1973 04:40:33.430963 9, 0x0, sum = 1
1974 04:40:33.431071 10, 0x0, sum = 2
1975 04:40:33.434027 11, 0x0, sum = 3
1976 04:40:33.434141 12, 0x0, sum = 4
1977 04:40:33.437184 best_step = 10
1978 04:40:33.437300
1979 04:40:33.437395 ==
1980 04:40:33.440972 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 04:40:33.444206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 04:40:33.444314 ==
1983 04:40:33.447246 RX Vref Scan: 0
1984 04:40:33.447352
1985 04:40:33.447455 RX Vref 0 -> 0, step: 1
1986 04:40:33.447622
1987 04:40:33.450628 RX Delay -79 -> 252, step: 8
1988 04:40:33.454370 iDelay=209, Bit 0, Center 100 (1 ~ 200) 200
1989 04:40:33.460708 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1990 04:40:33.464307 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1991 04:40:33.467228 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1992 04:40:33.471154 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1993 04:40:33.474395 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1994 04:40:33.477510 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1995 04:40:33.484448 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1996 04:40:33.487492 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1997 04:40:33.490952 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1998 04:40:33.494087 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
1999 04:40:33.497636 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2000 04:40:33.504341 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2001 04:40:33.507883 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2002 04:40:33.511379 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2003 04:40:33.514402 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2004 04:40:33.514518 ==
2005 04:40:33.517497 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 04:40:33.521023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 04:40:33.524703 ==
2008 04:40:33.524809 DQS Delay:
2009 04:40:33.524902 DQS0 = 0, DQS1 = 0
2010 04:40:33.527839 DQM Delay:
2011 04:40:33.527912 DQM0 = 97, DQM1 = 91
2012 04:40:33.531367 DQ Delay:
2013 04:40:33.531450 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =92
2014 04:40:33.534287 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2015 04:40:33.538005 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =84
2016 04:40:33.544804 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2017 04:40:33.544891
2018 04:40:33.544959
2019 04:40:33.551090 [DQSOSCAuto] RK1, (LSB)MR18= 0x440d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2020 04:40:33.554256 CH1 RK1: MR19=606, MR18=440D
2021 04:40:33.560965 CH1_RK1: MR19=0x606, MR18=0x440D, DQSOSC=392, MR23=63, INC=96, DEC=64
2022 04:40:33.564543 [RxdqsGatingPostProcess] freq 800
2023 04:40:33.567703 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2024 04:40:33.571439 Pre-setting of DQS Precalculation
2025 04:40:33.577870 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2026 04:40:33.584370 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2027 04:40:33.591221 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2028 04:40:33.591334
2029 04:40:33.591429
2030 04:40:33.594768 [Calibration Summary] 1600 Mbps
2031 04:40:33.594844 CH 0, Rank 0
2032 04:40:33.597876 SW Impedance : PASS
2033 04:40:33.601143 DUTY Scan : NO K
2034 04:40:33.601252 ZQ Calibration : PASS
2035 04:40:33.604564 Jitter Meter : NO K
2036 04:40:33.604666 CBT Training : PASS
2037 04:40:33.608070 Write leveling : PASS
2038 04:40:33.611059 RX DQS gating : PASS
2039 04:40:33.611174 RX DQ/DQS(RDDQC) : PASS
2040 04:40:33.614389 TX DQ/DQS : PASS
2041 04:40:33.617814 RX DATLAT : PASS
2042 04:40:33.617921 RX DQ/DQS(Engine): PASS
2043 04:40:33.621346 TX OE : NO K
2044 04:40:33.621447 All Pass.
2045 04:40:33.621541
2046 04:40:33.624923 CH 0, Rank 1
2047 04:40:33.625020 SW Impedance : PASS
2048 04:40:33.627903 DUTY Scan : NO K
2049 04:40:33.631324 ZQ Calibration : PASS
2050 04:40:33.631438 Jitter Meter : NO K
2051 04:40:33.634960 CBT Training : PASS
2052 04:40:33.637994 Write leveling : PASS
2053 04:40:33.638102 RX DQS gating : PASS
2054 04:40:33.641597 RX DQ/DQS(RDDQC) : PASS
2055 04:40:33.641699 TX DQ/DQS : PASS
2056 04:40:33.644672 RX DATLAT : PASS
2057 04:40:33.647848 RX DQ/DQS(Engine): PASS
2058 04:40:33.647957 TX OE : NO K
2059 04:40:33.651510 All Pass.
2060 04:40:33.651613
2061 04:40:33.651678 CH 1, Rank 0
2062 04:40:33.654665 SW Impedance : PASS
2063 04:40:33.654774 DUTY Scan : NO K
2064 04:40:33.657854 ZQ Calibration : PASS
2065 04:40:33.661557 Jitter Meter : NO K
2066 04:40:33.661640 CBT Training : PASS
2067 04:40:33.664478 Write leveling : PASS
2068 04:40:33.667895 RX DQS gating : PASS
2069 04:40:33.667992 RX DQ/DQS(RDDQC) : PASS
2070 04:40:33.671652 TX DQ/DQS : PASS
2071 04:40:33.674721 RX DATLAT : PASS
2072 04:40:33.674799 RX DQ/DQS(Engine): PASS
2073 04:40:33.677880 TX OE : NO K
2074 04:40:33.677951 All Pass.
2075 04:40:33.678012
2076 04:40:33.681540 CH 1, Rank 1
2077 04:40:33.681607 SW Impedance : PASS
2078 04:40:33.685090 DUTY Scan : NO K
2079 04:40:33.685160 ZQ Calibration : PASS
2080 04:40:33.688047 Jitter Meter : NO K
2081 04:40:33.691736 CBT Training : PASS
2082 04:40:33.691819 Write leveling : PASS
2083 04:40:33.694936 RX DQS gating : PASS
2084 04:40:33.697944 RX DQ/DQS(RDDQC) : PASS
2085 04:40:33.698063 TX DQ/DQS : PASS
2086 04:40:33.701602 RX DATLAT : PASS
2087 04:40:33.704702 RX DQ/DQS(Engine): PASS
2088 04:40:33.704814 TX OE : NO K
2089 04:40:33.708440 All Pass.
2090 04:40:33.708525
2091 04:40:33.708613 DramC Write-DBI off
2092 04:40:33.711895 PER_BANK_REFRESH: Hybrid Mode
2093 04:40:33.711991 TX_TRACKING: ON
2094 04:40:33.714996 [GetDramInforAfterCalByMRR] Vendor 6.
2095 04:40:33.721520 [GetDramInforAfterCalByMRR] Revision 606.
2096 04:40:33.725303 [GetDramInforAfterCalByMRR] Revision 2 0.
2097 04:40:33.725390 MR0 0x3b3b
2098 04:40:33.725456 MR8 0x5151
2099 04:40:33.728234 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2100 04:40:33.728333
2101 04:40:33.731905 MR0 0x3b3b
2102 04:40:33.732015 MR8 0x5151
2103 04:40:33.735008 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 04:40:33.735079
2105 04:40:33.744900 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2106 04:40:33.748431 [FAST_K] Save calibration result to emmc
2107 04:40:33.751428 [FAST_K] Save calibration result to emmc
2108 04:40:33.755226 dram_init: config_dvfs: 1
2109 04:40:33.758333 dramc_set_vcore_voltage set vcore to 662500
2110 04:40:33.761468 Read voltage for 1200, 2
2111 04:40:33.761556 Vio18 = 0
2112 04:40:33.761649 Vcore = 662500
2113 04:40:33.765191 Vdram = 0
2114 04:40:33.765292 Vddq = 0
2115 04:40:33.765395 Vmddr = 0
2116 04:40:33.771436 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2117 04:40:33.775053 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2118 04:40:33.778445 MEM_TYPE=3, freq_sel=15
2119 04:40:33.781723 sv_algorithm_assistance_LP4_1600
2120 04:40:33.784888 ============ PULL DRAM RESETB DOWN ============
2121 04:40:33.788380 ========== PULL DRAM RESETB DOWN end =========
2122 04:40:33.794912 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2123 04:40:33.797991 ===================================
2124 04:40:33.798115 LPDDR4 DRAM CONFIGURATION
2125 04:40:33.801631 ===================================
2126 04:40:33.804706 EX_ROW_EN[0] = 0x0
2127 04:40:33.804817 EX_ROW_EN[1] = 0x0
2128 04:40:33.808472 LP4Y_EN = 0x0
2129 04:40:33.811608 WORK_FSP = 0x0
2130 04:40:33.811690 WL = 0x4
2131 04:40:33.815197 RL = 0x4
2132 04:40:33.815283 BL = 0x2
2133 04:40:33.818230 RPST = 0x0
2134 04:40:33.818341 RD_PRE = 0x0
2135 04:40:33.821436 WR_PRE = 0x1
2136 04:40:33.821520 WR_PST = 0x0
2137 04:40:33.825082 DBI_WR = 0x0
2138 04:40:33.825199 DBI_RD = 0x0
2139 04:40:33.828050 OTF = 0x1
2140 04:40:33.831603 ===================================
2141 04:40:33.835136 ===================================
2142 04:40:33.835244 ANA top config
2143 04:40:33.838222 ===================================
2144 04:40:33.841845 DLL_ASYNC_EN = 0
2145 04:40:33.844851 ALL_SLAVE_EN = 0
2146 04:40:33.844966 NEW_RANK_MODE = 1
2147 04:40:33.848468 DLL_IDLE_MODE = 1
2148 04:40:33.851602 LP45_APHY_COMB_EN = 1
2149 04:40:33.854763 TX_ODT_DIS = 1
2150 04:40:33.854849 NEW_8X_MODE = 1
2151 04:40:33.858263 ===================================
2152 04:40:33.861755 ===================================
2153 04:40:33.864840 data_rate = 2400
2154 04:40:33.868601 CKR = 1
2155 04:40:33.871632 DQ_P2S_RATIO = 8
2156 04:40:33.874906 ===================================
2157 04:40:33.878600 CA_P2S_RATIO = 8
2158 04:40:33.881680 DQ_CA_OPEN = 0
2159 04:40:33.881767 DQ_SEMI_OPEN = 0
2160 04:40:33.885154 CA_SEMI_OPEN = 0
2161 04:40:33.888814 CA_FULL_RATE = 0
2162 04:40:33.891816 DQ_CKDIV4_EN = 0
2163 04:40:33.894836 CA_CKDIV4_EN = 0
2164 04:40:33.898521 CA_PREDIV_EN = 0
2165 04:40:33.898605 PH8_DLY = 17
2166 04:40:33.901439 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2167 04:40:33.905204 DQ_AAMCK_DIV = 4
2168 04:40:33.908266 CA_AAMCK_DIV = 4
2169 04:40:33.911322 CA_ADMCK_DIV = 4
2170 04:40:33.915055 DQ_TRACK_CA_EN = 0
2171 04:40:33.915168 CA_PICK = 1200
2172 04:40:33.918093 CA_MCKIO = 1200
2173 04:40:33.921351 MCKIO_SEMI = 0
2174 04:40:33.925197 PLL_FREQ = 2366
2175 04:40:33.928293 DQ_UI_PI_RATIO = 32
2176 04:40:33.931366 CA_UI_PI_RATIO = 0
2177 04:40:33.934871 ===================================
2178 04:40:33.938635 ===================================
2179 04:40:33.941624 memory_type:LPDDR4
2180 04:40:33.941728 GP_NUM : 10
2181 04:40:33.945082 SRAM_EN : 1
2182 04:40:33.945167 MD32_EN : 0
2183 04:40:33.948217 ===================================
2184 04:40:33.952005 [ANA_INIT] >>>>>>>>>>>>>>
2185 04:40:33.955057 <<<<<< [CONFIGURE PHASE]: ANA_TX
2186 04:40:33.958739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2187 04:40:33.961811 ===================================
2188 04:40:33.964893 data_rate = 2400,PCW = 0X5b00
2189 04:40:33.968403 ===================================
2190 04:40:33.971948 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2191 04:40:33.975028 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2192 04:40:33.982041 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 04:40:33.985068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2194 04:40:33.988303 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2195 04:40:33.991884 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2196 04:40:33.995306 [ANA_INIT] flow start
2197 04:40:33.998052 [ANA_INIT] PLL >>>>>>>>
2198 04:40:33.998163 [ANA_INIT] PLL <<<<<<<<
2199 04:40:34.001797 [ANA_INIT] MIDPI >>>>>>>>
2200 04:40:34.004826 [ANA_INIT] MIDPI <<<<<<<<
2201 04:40:34.008452 [ANA_INIT] DLL >>>>>>>>
2202 04:40:34.008537 [ANA_INIT] DLL <<<<<<<<
2203 04:40:34.011453 [ANA_INIT] flow end
2204 04:40:34.015149 ============ LP4 DIFF to SE enter ============
2205 04:40:34.018369 ============ LP4 DIFF to SE exit ============
2206 04:40:34.021939 [ANA_INIT] <<<<<<<<<<<<<
2207 04:40:34.024983 [Flow] Enable top DCM control >>>>>
2208 04:40:34.028098 [Flow] Enable top DCM control <<<<<
2209 04:40:34.031710 Enable DLL master slave shuffle
2210 04:40:34.038453 ==============================================================
2211 04:40:34.038577 Gating Mode config
2212 04:40:34.045161 ==============================================================
2213 04:40:34.045275 Config description:
2214 04:40:34.055181 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2215 04:40:34.061949 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2216 04:40:34.068180 SELPH_MODE 0: By rank 1: By Phase
2217 04:40:34.071884 ==============================================================
2218 04:40:34.075028 GAT_TRACK_EN = 1
2219 04:40:34.078427 RX_GATING_MODE = 2
2220 04:40:34.081531 RX_GATING_TRACK_MODE = 2
2221 04:40:34.085298 SELPH_MODE = 1
2222 04:40:34.088401 PICG_EARLY_EN = 1
2223 04:40:34.091535 VALID_LAT_VALUE = 1
2224 04:40:34.095243 ==============================================================
2225 04:40:34.098314 Enter into Gating configuration >>>>
2226 04:40:34.102075 Exit from Gating configuration <<<<
2227 04:40:34.104747 Enter into DVFS_PRE_config >>>>>
2228 04:40:34.118750 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2229 04:40:34.118862 Exit from DVFS_PRE_config <<<<<
2230 04:40:34.121707 Enter into PICG configuration >>>>
2231 04:40:34.125466 Exit from PICG configuration <<<<
2232 04:40:34.128444 [RX_INPUT] configuration >>>>>
2233 04:40:34.131598 [RX_INPUT] configuration <<<<<
2234 04:40:34.138290 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2235 04:40:34.141520 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2236 04:40:34.148885 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 04:40:34.155456 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 04:40:34.162195 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2239 04:40:34.168739 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2240 04:40:34.171821 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2241 04:40:34.175634 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2242 04:40:34.178691 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2243 04:40:34.181833 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2244 04:40:34.188403 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2245 04:40:34.191751 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2246 04:40:34.195492 ===================================
2247 04:40:34.198605 LPDDR4 DRAM CONFIGURATION
2248 04:40:34.201618 ===================================
2249 04:40:34.201693 EX_ROW_EN[0] = 0x0
2250 04:40:34.205548 EX_ROW_EN[1] = 0x0
2251 04:40:34.205709 LP4Y_EN = 0x0
2252 04:40:34.208637 WORK_FSP = 0x0
2253 04:40:34.208760 WL = 0x4
2254 04:40:34.211557 RL = 0x4
2255 04:40:34.211653 BL = 0x2
2256 04:40:34.215124 RPST = 0x0
2257 04:40:34.218488 RD_PRE = 0x0
2258 04:40:34.218605 WR_PRE = 0x1
2259 04:40:34.221625 WR_PST = 0x0
2260 04:40:34.221696 DBI_WR = 0x0
2261 04:40:34.224989 DBI_RD = 0x0
2262 04:40:34.225097 OTF = 0x1
2263 04:40:34.228380 ===================================
2264 04:40:34.231804 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2265 04:40:34.238284 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2266 04:40:34.242045 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 04:40:34.245140 ===================================
2268 04:40:34.248922 LPDDR4 DRAM CONFIGURATION
2269 04:40:34.251858 ===================================
2270 04:40:34.251944 EX_ROW_EN[0] = 0x10
2271 04:40:34.255419 EX_ROW_EN[1] = 0x0
2272 04:40:34.255551 LP4Y_EN = 0x0
2273 04:40:34.258575 WORK_FSP = 0x0
2274 04:40:34.258650 WL = 0x4
2275 04:40:34.261541 RL = 0x4
2276 04:40:34.261681 BL = 0x2
2277 04:40:34.265251 RPST = 0x0
2278 04:40:34.265377 RD_PRE = 0x0
2279 04:40:34.268205 WR_PRE = 0x1
2280 04:40:34.268288 WR_PST = 0x0
2281 04:40:34.271852 DBI_WR = 0x0
2282 04:40:34.271950 DBI_RD = 0x0
2283 04:40:34.275072 OTF = 0x1
2284 04:40:34.278745 ===================================
2285 04:40:34.284823 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2286 04:40:34.284907 ==
2287 04:40:34.288743 Dram Type= 6, Freq= 0, CH_0, rank 0
2288 04:40:34.291838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2289 04:40:34.291922 ==
2290 04:40:34.295035 [Duty_Offset_Calibration]
2291 04:40:34.295117 B0:2 B1:1 CA:1
2292 04:40:34.295182
2293 04:40:34.298125 [DutyScan_Calibration_Flow] k_type=0
2294 04:40:34.308956
2295 04:40:34.309102 ==CLK 0==
2296 04:40:34.312633 Final CLK duty delay cell = 0
2297 04:40:34.315791 [0] MAX Duty = 5187%(X100), DQS PI = 24
2298 04:40:34.319336 [0] MIN Duty = 4875%(X100), DQS PI = 0
2299 04:40:34.319451 [0] AVG Duty = 5031%(X100)
2300 04:40:34.322252
2301 04:40:34.322355 CH0 CLK Duty spec in!! Max-Min= 312%
2302 04:40:34.329295 [DutyScan_Calibration_Flow] ====Done====
2303 04:40:34.329450
2304 04:40:34.332365 [DutyScan_Calibration_Flow] k_type=1
2305 04:40:34.346681
2306 04:40:34.346823 ==DQS 0 ==
2307 04:40:34.350256 Final DQS duty delay cell = -4
2308 04:40:34.353429 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2309 04:40:34.356973 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2310 04:40:34.360346 [-4] AVG Duty = 4937%(X100)
2311 04:40:34.360425
2312 04:40:34.360504 ==DQS 1 ==
2313 04:40:34.363862 Final DQS duty delay cell = -4
2314 04:40:34.366816 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2315 04:40:34.370097 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2316 04:40:34.373518 [-4] AVG Duty = 4906%(X100)
2317 04:40:34.373626
2318 04:40:34.377247 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2319 04:40:34.377359
2320 04:40:34.380305 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2321 04:40:34.383476 [DutyScan_Calibration_Flow] ====Done====
2322 04:40:34.383574
2323 04:40:34.386653 [DutyScan_Calibration_Flow] k_type=3
2324 04:40:34.404015
2325 04:40:34.404150 ==DQM 0 ==
2326 04:40:34.407048 Final DQM duty delay cell = 0
2327 04:40:34.410717 [0] MAX Duty = 5156%(X100), DQS PI = 30
2328 04:40:34.414183 [0] MIN Duty = 4906%(X100), DQS PI = 50
2329 04:40:34.417263 [0] AVG Duty = 5031%(X100)
2330 04:40:34.417353
2331 04:40:34.417419 ==DQM 1 ==
2332 04:40:34.420433 Final DQM duty delay cell = 0
2333 04:40:34.424101 [0] MAX Duty = 5093%(X100), DQS PI = 0
2334 04:40:34.427172 [0] MIN Duty = 5031%(X100), DQS PI = 36
2335 04:40:34.427293 [0] AVG Duty = 5062%(X100)
2336 04:40:34.430840
2337 04:40:34.433805 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2338 04:40:34.433892
2339 04:40:34.437236 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2340 04:40:34.441003 [DutyScan_Calibration_Flow] ====Done====
2341 04:40:34.441086
2342 04:40:34.444231 [DutyScan_Calibration_Flow] k_type=2
2343 04:40:34.460387
2344 04:40:34.460524 ==DQ 0 ==
2345 04:40:34.463949 Final DQ duty delay cell = 0
2346 04:40:34.466891 [0] MAX Duty = 5031%(X100), DQS PI = 24
2347 04:40:34.470259 [0] MIN Duty = 4875%(X100), DQS PI = 0
2348 04:40:34.470376 [0] AVG Duty = 4953%(X100)
2349 04:40:34.470471
2350 04:40:34.473585 ==DQ 1 ==
2351 04:40:34.477089 Final DQ duty delay cell = 0
2352 04:40:34.480168 [0] MAX Duty = 5093%(X100), DQS PI = 24
2353 04:40:34.483608 [0] MIN Duty = 4938%(X100), DQS PI = 36
2354 04:40:34.483722 [0] AVG Duty = 5015%(X100)
2355 04:40:34.483819
2356 04:40:34.487370 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2357 04:40:34.487481
2358 04:40:34.490512 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2359 04:40:34.496745 [DutyScan_Calibration_Flow] ====Done====
2360 04:40:34.496833 ==
2361 04:40:34.500573 Dram Type= 6, Freq= 0, CH_1, rank 0
2362 04:40:34.503641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2363 04:40:34.503718 ==
2364 04:40:34.506906 [Duty_Offset_Calibration]
2365 04:40:34.506991 B0:1 B1:0 CA:0
2366 04:40:34.507057
2367 04:40:34.510676 [DutyScan_Calibration_Flow] k_type=0
2368 04:40:34.519317
2369 04:40:34.519410 ==CLK 0==
2370 04:40:34.523045 Final CLK duty delay cell = -4
2371 04:40:34.526380 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2372 04:40:34.529494 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2373 04:40:34.533223 [-4] AVG Duty = 4969%(X100)
2374 04:40:34.533311
2375 04:40:34.536305 CH1 CLK Duty spec in!! Max-Min= 124%
2376 04:40:34.539257 [DutyScan_Calibration_Flow] ====Done====
2377 04:40:34.539385
2378 04:40:34.542696 [DutyScan_Calibration_Flow] k_type=1
2379 04:40:34.559414
2380 04:40:34.559581 ==DQS 0 ==
2381 04:40:34.562681 Final DQS duty delay cell = 0
2382 04:40:34.565855 [0] MAX Duty = 5094%(X100), DQS PI = 24
2383 04:40:34.569049 [0] MIN Duty = 4875%(X100), DQS PI = 0
2384 04:40:34.569157 [0] AVG Duty = 4984%(X100)
2385 04:40:34.572298
2386 04:40:34.572376 ==DQS 1 ==
2387 04:40:34.576073 Final DQS duty delay cell = 0
2388 04:40:34.579008 [0] MAX Duty = 5187%(X100), DQS PI = 20
2389 04:40:34.582384 [0] MIN Duty = 4969%(X100), DQS PI = 10
2390 04:40:34.582494 [0] AVG Duty = 5078%(X100)
2391 04:40:34.585958
2392 04:40:34.589619 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2393 04:40:34.589726
2394 04:40:34.592488 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2395 04:40:34.596049 [DutyScan_Calibration_Flow] ====Done====
2396 04:40:34.596169
2397 04:40:34.599260 [DutyScan_Calibration_Flow] k_type=3
2398 04:40:34.615969
2399 04:40:34.616091 ==DQM 0 ==
2400 04:40:34.619050 Final DQM duty delay cell = 0
2401 04:40:34.622342 [0] MAX Duty = 5156%(X100), DQS PI = 6
2402 04:40:34.625991 [0] MIN Duty = 5031%(X100), DQS PI = 0
2403 04:40:34.626112 [0] AVG Duty = 5093%(X100)
2404 04:40:34.626214
2405 04:40:34.629041 ==DQM 1 ==
2406 04:40:34.632656 Final DQM duty delay cell = 0
2407 04:40:34.636142 [0] MAX Duty = 5031%(X100), DQS PI = 16
2408 04:40:34.638960 [0] MIN Duty = 4907%(X100), DQS PI = 36
2409 04:40:34.639084 [0] AVG Duty = 4969%(X100)
2410 04:40:34.639180
2411 04:40:34.646061 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2412 04:40:34.646194
2413 04:40:34.649211 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2414 04:40:34.652691 [DutyScan_Calibration_Flow] ====Done====
2415 04:40:34.652803
2416 04:40:34.655966 [DutyScan_Calibration_Flow] k_type=2
2417 04:40:34.671430
2418 04:40:34.671562 ==DQ 0 ==
2419 04:40:34.674493 Final DQ duty delay cell = -4
2420 04:40:34.678283 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2421 04:40:34.681487 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2422 04:40:34.681572 [-4] AVG Duty = 4984%(X100)
2423 04:40:34.685026
2424 04:40:34.685113 ==DQ 1 ==
2425 04:40:34.688579 Final DQ duty delay cell = 0
2426 04:40:34.691433 [0] MAX Duty = 5125%(X100), DQS PI = 20
2427 04:40:34.695087 [0] MIN Duty = 4969%(X100), DQS PI = 12
2428 04:40:34.695191 [0] AVG Duty = 5047%(X100)
2429 04:40:34.695268
2430 04:40:34.698682 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2431 04:40:34.701498
2432 04:40:34.705328 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2433 04:40:34.708512 [DutyScan_Calibration_Flow] ====Done====
2434 04:40:34.711596 nWR fixed to 30
2435 04:40:34.711691 [ModeRegInit_LP4] CH0 RK0
2436 04:40:34.715249 [ModeRegInit_LP4] CH0 RK1
2437 04:40:34.718373 [ModeRegInit_LP4] CH1 RK0
2438 04:40:34.718489 [ModeRegInit_LP4] CH1 RK1
2439 04:40:34.721558 match AC timing 7
2440 04:40:34.724715 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2441 04:40:34.728481 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2442 04:40:34.735143 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2443 04:40:34.738254 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2444 04:40:34.745130 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2445 04:40:34.745246 ==
2446 04:40:34.748159 Dram Type= 6, Freq= 0, CH_0, rank 0
2447 04:40:34.751511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2448 04:40:34.751607 ==
2449 04:40:34.758360 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2450 04:40:34.761843 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2451 04:40:34.771831 [CA 0] Center 39 (8~70) winsize 63
2452 04:40:34.774847 [CA 1] Center 39 (8~70) winsize 63
2453 04:40:34.778205 [CA 2] Center 35 (5~66) winsize 62
2454 04:40:34.781735 [CA 3] Center 34 (4~65) winsize 62
2455 04:40:34.784879 [CA 4] Center 33 (3~64) winsize 62
2456 04:40:34.788649 [CA 5] Center 32 (3~62) winsize 60
2457 04:40:34.788744
2458 04:40:34.791680 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2459 04:40:34.791800
2460 04:40:34.795202 [CATrainingPosCal] consider 1 rank data
2461 04:40:34.798699 u2DelayCellTimex100 = 270/100 ps
2462 04:40:34.801757 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2463 04:40:34.805451 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2464 04:40:34.808994 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2465 04:40:34.815259 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2466 04:40:34.818936 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2467 04:40:34.822405 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2468 04:40:34.822517
2469 04:40:34.825444 CA PerBit enable=1, Macro0, CA PI delay=32
2470 04:40:34.825559
2471 04:40:34.828505 [CBTSetCACLKResult] CA Dly = 32
2472 04:40:34.828618 CS Dly: 6 (0~37)
2473 04:40:34.828728 ==
2474 04:40:34.832354 Dram Type= 6, Freq= 0, CH_0, rank 1
2475 04:40:34.838708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2476 04:40:34.838837 ==
2477 04:40:34.842425 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2478 04:40:34.848612 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2479 04:40:34.857308 [CA 0] Center 38 (8~69) winsize 62
2480 04:40:34.860870 [CA 1] Center 38 (8~69) winsize 62
2481 04:40:34.864446 [CA 2] Center 35 (4~66) winsize 63
2482 04:40:34.867456 [CA 3] Center 34 (4~65) winsize 62
2483 04:40:34.870938 [CA 4] Center 33 (3~64) winsize 62
2484 04:40:34.874059 [CA 5] Center 32 (3~62) winsize 60
2485 04:40:34.874146
2486 04:40:34.877702 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2487 04:40:34.877791
2488 04:40:34.881113 [CATrainingPosCal] consider 2 rank data
2489 04:40:34.884416 u2DelayCellTimex100 = 270/100 ps
2490 04:40:34.887538 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2491 04:40:34.890883 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2492 04:40:34.897336 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2493 04:40:34.901032 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2494 04:40:34.904070 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2495 04:40:34.907292 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2496 04:40:34.907385
2497 04:40:34.910806 CA PerBit enable=1, Macro0, CA PI delay=32
2498 04:40:34.910892
2499 04:40:34.914318 [CBTSetCACLKResult] CA Dly = 32
2500 04:40:34.914431 CS Dly: 6 (0~38)
2501 04:40:34.914533
2502 04:40:34.917305 ----->DramcWriteLeveling(PI) begin...
2503 04:40:34.921027 ==
2504 04:40:34.921118 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 04:40:34.927104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 04:40:34.927218 ==
2507 04:40:34.930910 Write leveling (Byte 0): 33 => 33
2508 04:40:34.934063 Write leveling (Byte 1): 27 => 27
2509 04:40:34.937237 DramcWriteLeveling(PI) end<-----
2510 04:40:34.937328
2511 04:40:34.937399 ==
2512 04:40:34.941179 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 04:40:34.944261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 04:40:34.944374 ==
2515 04:40:34.947330 [Gating] SW mode calibration
2516 04:40:34.954156 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2517 04:40:34.957368 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2518 04:40:34.964054 0 15 0 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
2519 04:40:34.967276 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2520 04:40:34.971066 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 04:40:34.977341 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 04:40:34.981083 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 04:40:34.984088 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 04:40:34.991026 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
2525 04:40:34.994340 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
2526 04:40:34.997662 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2527 04:40:35.004033 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 04:40:35.007251 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 04:40:35.010702 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 04:40:35.017611 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 04:40:35.020982 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 04:40:35.024152 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2533 04:40:35.030718 1 0 28 | B1->B0 | 2626 4545 | 0 0 | (0 0) (0 0)
2534 04:40:35.034494 1 1 0 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
2535 04:40:35.037564 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 04:40:35.040723 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 04:40:35.047653 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 04:40:35.050752 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 04:40:35.054505 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 04:40:35.060865 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 04:40:35.064555 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2542 04:40:35.067733 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2543 04:40:35.074434 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 04:40:35.077640 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 04:40:35.081425 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 04:40:35.087628 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 04:40:35.091361 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 04:40:35.094473 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 04:40:35.101264 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 04:40:35.104449 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 04:40:35.107438 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 04:40:35.114220 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 04:40:35.118101 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 04:40:35.121111 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 04:40:35.124649 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 04:40:35.131544 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2557 04:40:35.134951 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2558 04:40:35.138173 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2559 04:40:35.141526 Total UI for P1: 0, mck2ui 16
2560 04:40:35.145004 best dqsien dly found for B0: ( 1, 3, 26)
2561 04:40:35.151526 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 04:40:35.151654 Total UI for P1: 0, mck2ui 16
2563 04:40:35.154971 best dqsien dly found for B1: ( 1, 4, 0)
2564 04:40:35.161460 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2565 04:40:35.164766 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2566 04:40:35.164857
2567 04:40:35.168537 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2568 04:40:35.171575 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2569 04:40:35.174628 [Gating] SW calibration Done
2570 04:40:35.174726 ==
2571 04:40:35.178317 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 04:40:35.181457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 04:40:35.181545 ==
2574 04:40:35.181611 RX Vref Scan: 0
2575 04:40:35.184654
2576 04:40:35.184739 RX Vref 0 -> 0, step: 1
2577 04:40:35.184805
2578 04:40:35.188354 RX Delay -40 -> 252, step: 8
2579 04:40:35.191464 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
2580 04:40:35.195264 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2581 04:40:35.201445 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2582 04:40:35.205161 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2583 04:40:35.208252 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2584 04:40:35.211442 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2585 04:40:35.215331 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2586 04:40:35.221454 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2587 04:40:35.224967 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2588 04:40:35.228128 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2589 04:40:35.231743 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2590 04:40:35.235112 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2591 04:40:35.241475 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2592 04:40:35.245378 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2593 04:40:35.248740 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2594 04:40:35.252095 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2595 04:40:35.252208 ==
2596 04:40:35.255137 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 04:40:35.258723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 04:40:35.261862 ==
2599 04:40:35.261952 DQS Delay:
2600 04:40:35.262030 DQS0 = 0, DQS1 = 0
2601 04:40:35.265414 DQM Delay:
2602 04:40:35.265500 DQM0 = 122, DQM1 = 113
2603 04:40:35.268620 DQ Delay:
2604 04:40:35.271768 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2605 04:40:35.275441 DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =127
2606 04:40:35.278962 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2607 04:40:35.282003 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2608 04:40:35.282088
2609 04:40:35.282153
2610 04:40:35.282213 ==
2611 04:40:35.285153 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 04:40:35.288984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 04:40:35.289068 ==
2614 04:40:35.289133
2615 04:40:35.289201
2616 04:40:35.292230 TX Vref Scan disable
2617 04:40:35.295348 == TX Byte 0 ==
2618 04:40:35.298565 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2619 04:40:35.302287 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2620 04:40:35.305341 == TX Byte 1 ==
2621 04:40:35.309053 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2622 04:40:35.312172 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2623 04:40:35.312259 ==
2624 04:40:35.315237 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 04:40:35.319054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 04:40:35.322051 ==
2627 04:40:35.332521 TX Vref=22, minBit 0, minWin=25, winSum=414
2628 04:40:35.335626 TX Vref=24, minBit 0, minWin=25, winSum=421
2629 04:40:35.339341 TX Vref=26, minBit 7, minWin=25, winSum=424
2630 04:40:35.342461 TX Vref=28, minBit 0, minWin=26, winSum=426
2631 04:40:35.345946 TX Vref=30, minBit 0, minWin=26, winSum=428
2632 04:40:35.349379 TX Vref=32, minBit 1, minWin=26, winSum=427
2633 04:40:35.355751 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 30
2634 04:40:35.355836
2635 04:40:35.359120 Final TX Range 1 Vref 30
2636 04:40:35.359203
2637 04:40:35.359267 ==
2638 04:40:35.362628 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 04:40:35.365806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 04:40:35.365889 ==
2641 04:40:35.365954
2642 04:40:35.369234
2643 04:40:35.369317 TX Vref Scan disable
2644 04:40:35.372830 == TX Byte 0 ==
2645 04:40:35.376017 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2646 04:40:35.378985 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2647 04:40:35.382422 == TX Byte 1 ==
2648 04:40:35.386036 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2649 04:40:35.389176 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2650 04:40:35.389280
2651 04:40:35.392636 [DATLAT]
2652 04:40:35.392741 Freq=1200, CH0 RK0
2653 04:40:35.392832
2654 04:40:35.395762 DATLAT Default: 0xd
2655 04:40:35.395859 0, 0xFFFF, sum = 0
2656 04:40:35.399362 1, 0xFFFF, sum = 0
2657 04:40:35.399475 2, 0xFFFF, sum = 0
2658 04:40:35.402409 3, 0xFFFF, sum = 0
2659 04:40:35.402511 4, 0xFFFF, sum = 0
2660 04:40:35.406017 5, 0xFFFF, sum = 0
2661 04:40:35.406099 6, 0xFFFF, sum = 0
2662 04:40:35.409243 7, 0xFFFF, sum = 0
2663 04:40:35.409324 8, 0xFFFF, sum = 0
2664 04:40:35.412981 9, 0xFFFF, sum = 0
2665 04:40:35.413065 10, 0xFFFF, sum = 0
2666 04:40:35.415922 11, 0xFFFF, sum = 0
2667 04:40:35.416006 12, 0x0, sum = 1
2668 04:40:35.419695 13, 0x0, sum = 2
2669 04:40:35.419779 14, 0x0, sum = 3
2670 04:40:35.422721 15, 0x0, sum = 4
2671 04:40:35.422804 best_step = 13
2672 04:40:35.422871
2673 04:40:35.422931 ==
2674 04:40:35.425937 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 04:40:35.433145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 04:40:35.433230 ==
2677 04:40:35.433294 RX Vref Scan: 1
2678 04:40:35.433354
2679 04:40:35.436274 Set Vref Range= 32 -> 127
2680 04:40:35.436356
2681 04:40:35.439459 RX Vref 32 -> 127, step: 1
2682 04:40:35.439569
2683 04:40:35.442575 RX Delay -13 -> 252, step: 4
2684 04:40:35.442659
2685 04:40:35.442723 Set Vref, RX VrefLevel [Byte0]: 32
2686 04:40:35.446369 [Byte1]: 32
2687 04:40:35.450640
2688 04:40:35.450721 Set Vref, RX VrefLevel [Byte0]: 33
2689 04:40:35.454422 [Byte1]: 33
2690 04:40:35.458719
2691 04:40:35.458804 Set Vref, RX VrefLevel [Byte0]: 34
2692 04:40:35.461655 [Byte1]: 34
2693 04:40:35.466561
2694 04:40:35.466648 Set Vref, RX VrefLevel [Byte0]: 35
2695 04:40:35.469653 [Byte1]: 35
2696 04:40:35.474557
2697 04:40:35.474653 Set Vref, RX VrefLevel [Byte0]: 36
2698 04:40:35.477928 [Byte1]: 36
2699 04:40:35.482430
2700 04:40:35.482534 Set Vref, RX VrefLevel [Byte0]: 37
2701 04:40:35.485746 [Byte1]: 37
2702 04:40:35.490163
2703 04:40:35.490255 Set Vref, RX VrefLevel [Byte0]: 38
2704 04:40:35.493295 [Byte1]: 38
2705 04:40:35.498151
2706 04:40:35.498272 Set Vref, RX VrefLevel [Byte0]: 39
2707 04:40:35.501262 [Byte1]: 39
2708 04:40:35.505809
2709 04:40:35.505905 Set Vref, RX VrefLevel [Byte0]: 40
2710 04:40:35.509207 [Byte1]: 40
2711 04:40:35.514139
2712 04:40:35.514271 Set Vref, RX VrefLevel [Byte0]: 41
2713 04:40:35.516948 [Byte1]: 41
2714 04:40:35.521923
2715 04:40:35.522036 Set Vref, RX VrefLevel [Byte0]: 42
2716 04:40:35.524894 [Byte1]: 42
2717 04:40:35.529361
2718 04:40:35.529463 Set Vref, RX VrefLevel [Byte0]: 43
2719 04:40:35.533010 [Byte1]: 43
2720 04:40:35.537440
2721 04:40:35.537543 Set Vref, RX VrefLevel [Byte0]: 44
2722 04:40:35.540518 [Byte1]: 44
2723 04:40:35.545628
2724 04:40:35.545728 Set Vref, RX VrefLevel [Byte0]: 45
2725 04:40:35.548768 [Byte1]: 45
2726 04:40:35.552987
2727 04:40:35.556509 Set Vref, RX VrefLevel [Byte0]: 46
2728 04:40:35.559498 [Byte1]: 46
2729 04:40:35.559616
2730 04:40:35.563270 Set Vref, RX VrefLevel [Byte0]: 47
2731 04:40:35.566243 [Byte1]: 47
2732 04:40:35.566342
2733 04:40:35.570005 Set Vref, RX VrefLevel [Byte0]: 48
2734 04:40:35.573083 [Byte1]: 48
2735 04:40:35.576715
2736 04:40:35.576827 Set Vref, RX VrefLevel [Byte0]: 49
2737 04:40:35.580569 [Byte1]: 49
2738 04:40:35.584985
2739 04:40:35.585087 Set Vref, RX VrefLevel [Byte0]: 50
2740 04:40:35.588454 [Byte1]: 50
2741 04:40:35.592458
2742 04:40:35.592564 Set Vref, RX VrefLevel [Byte0]: 51
2743 04:40:35.595895 [Byte1]: 51
2744 04:40:35.600711
2745 04:40:35.600844 Set Vref, RX VrefLevel [Byte0]: 52
2746 04:40:35.603803 [Byte1]: 52
2747 04:40:35.608647
2748 04:40:35.608752 Set Vref, RX VrefLevel [Byte0]: 53
2749 04:40:35.611661 [Byte1]: 53
2750 04:40:35.616587
2751 04:40:35.616689 Set Vref, RX VrefLevel [Byte0]: 54
2752 04:40:35.619610 [Byte1]: 54
2753 04:40:35.624513
2754 04:40:35.624618 Set Vref, RX VrefLevel [Byte0]: 55
2755 04:40:35.627361 [Byte1]: 55
2756 04:40:35.631940
2757 04:40:35.632055 Set Vref, RX VrefLevel [Byte0]: 56
2758 04:40:35.635477 [Byte1]: 56
2759 04:40:35.639878
2760 04:40:35.639963 Set Vref, RX VrefLevel [Byte0]: 57
2761 04:40:35.643788 [Byte1]: 57
2762 04:40:35.648106
2763 04:40:35.648192 Set Vref, RX VrefLevel [Byte0]: 58
2764 04:40:35.651348 [Byte1]: 58
2765 04:40:35.655679
2766 04:40:35.655762 Set Vref, RX VrefLevel [Byte0]: 59
2767 04:40:35.659373 [Byte1]: 59
2768 04:40:35.663640
2769 04:40:35.663728 Set Vref, RX VrefLevel [Byte0]: 60
2770 04:40:35.667334 [Byte1]: 60
2771 04:40:35.671437
2772 04:40:35.671576 Set Vref, RX VrefLevel [Byte0]: 61
2773 04:40:35.675401 [Byte1]: 61
2774 04:40:35.679599
2775 04:40:35.679682 Set Vref, RX VrefLevel [Byte0]: 62
2776 04:40:35.682698 [Byte1]: 62
2777 04:40:35.687609
2778 04:40:35.687691 Set Vref, RX VrefLevel [Byte0]: 63
2779 04:40:35.690705 [Byte1]: 63
2780 04:40:35.695663
2781 04:40:35.695745 Set Vref, RX VrefLevel [Byte0]: 64
2782 04:40:35.698661 [Byte1]: 64
2783 04:40:35.702929
2784 04:40:35.703012 Set Vref, RX VrefLevel [Byte0]: 65
2785 04:40:35.706692 [Byte1]: 65
2786 04:40:35.710898
2787 04:40:35.710982 Set Vref, RX VrefLevel [Byte0]: 66
2788 04:40:35.714565 [Byte1]: 66
2789 04:40:35.719059
2790 04:40:35.719144 Set Vref, RX VrefLevel [Byte0]: 67
2791 04:40:35.722416 [Byte1]: 67
2792 04:40:35.726577
2793 04:40:35.726657 Set Vref, RX VrefLevel [Byte0]: 68
2794 04:40:35.730165 [Byte1]: 68
2795 04:40:35.734738
2796 04:40:35.734815 Set Vref, RX VrefLevel [Byte0]: 69
2797 04:40:35.738210 [Byte1]: 69
2798 04:40:35.742400
2799 04:40:35.742503 Final RX Vref Byte 0 = 56 to rank0
2800 04:40:35.745921 Final RX Vref Byte 1 = 50 to rank0
2801 04:40:35.749509 Final RX Vref Byte 0 = 56 to rank1
2802 04:40:35.752545 Final RX Vref Byte 1 = 50 to rank1==
2803 04:40:35.755697 Dram Type= 6, Freq= 0, CH_0, rank 0
2804 04:40:35.762729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2805 04:40:35.762851 ==
2806 04:40:35.762919 DQS Delay:
2807 04:40:35.763017 DQS0 = 0, DQS1 = 0
2808 04:40:35.766304 DQM Delay:
2809 04:40:35.766388 DQM0 = 120, DQM1 = 112
2810 04:40:35.769492 DQ Delay:
2811 04:40:35.772863 DQ0 =120, DQ1 =120, DQ2 =120, DQ3 =118
2812 04:40:35.775789 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2813 04:40:35.779444 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2814 04:40:35.782600 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =122
2815 04:40:35.782683
2816 04:40:35.782785
2817 04:40:35.789553 [DQSOSCAuto] RK0, (LSB)MR18= 0x140d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2818 04:40:35.792630 CH0 RK0: MR19=404, MR18=140D
2819 04:40:35.799354 CH0_RK0: MR19=0x404, MR18=0x140D, DQSOSC=402, MR23=63, INC=40, DEC=27
2820 04:40:35.799440
2821 04:40:35.802975 ----->DramcWriteLeveling(PI) begin...
2822 04:40:35.803116 ==
2823 04:40:35.806171 Dram Type= 6, Freq= 0, CH_0, rank 1
2824 04:40:35.809340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 04:40:35.812547 ==
2826 04:40:35.812645 Write leveling (Byte 0): 33 => 33
2827 04:40:35.816245 Write leveling (Byte 1): 30 => 30
2828 04:40:35.819333 DramcWriteLeveling(PI) end<-----
2829 04:40:35.819414
2830 04:40:35.819480 ==
2831 04:40:35.823200 Dram Type= 6, Freq= 0, CH_0, rank 1
2832 04:40:35.829873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2833 04:40:35.829966 ==
2834 04:40:35.830038 [Gating] SW mode calibration
2835 04:40:35.839879 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2836 04:40:35.842867 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2837 04:40:35.846427 0 15 0 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 0)
2838 04:40:35.852905 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 04:40:35.856435 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 04:40:35.859737 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 04:40:35.866663 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 04:40:35.869714 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 04:40:35.872824 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 04:40:35.879475 0 15 28 | B1->B0 | 3232 3030 | 1 1 | (0 0) (1 1)
2845 04:40:35.883274 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2846 04:40:35.886417 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 04:40:35.892681 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 04:40:35.896608 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 04:40:35.899682 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 04:40:35.906317 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 04:40:35.909350 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 04:40:35.913166 1 0 28 | B1->B0 | 3939 3939 | 0 0 | (0 0) (0 0)
2853 04:40:35.916264 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2854 04:40:35.923290 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 04:40:35.926434 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 04:40:35.929532 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 04:40:35.936299 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 04:40:35.940054 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 04:40:35.942900 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 04:40:35.949339 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2861 04:40:35.952667 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 04:40:35.955986 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 04:40:35.963164 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 04:40:35.966508 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 04:40:35.969447 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 04:40:35.976434 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 04:40:35.979736 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 04:40:35.982935 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 04:40:35.989766 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 04:40:35.993175 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 04:40:35.996159 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 04:40:35.999986 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 04:40:36.006162 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 04:40:36.009819 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 04:40:36.012897 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 04:40:36.019666 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2877 04:40:36.023388 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2878 04:40:36.026540 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 04:40:36.029720 Total UI for P1: 0, mck2ui 16
2880 04:40:36.032820 best dqsien dly found for B0: ( 1, 3, 30)
2881 04:40:36.036150 Total UI for P1: 0, mck2ui 16
2882 04:40:36.039746 best dqsien dly found for B1: ( 1, 3, 30)
2883 04:40:36.042908 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2884 04:40:36.046647 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2885 04:40:36.046781
2886 04:40:36.052868 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2887 04:40:36.056491 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2888 04:40:36.056595 [Gating] SW calibration Done
2889 04:40:36.059468 ==
2890 04:40:36.063026 Dram Type= 6, Freq= 0, CH_0, rank 1
2891 04:40:36.066499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 04:40:36.066599 ==
2893 04:40:36.066689 RX Vref Scan: 0
2894 04:40:36.066760
2895 04:40:36.069754 RX Vref 0 -> 0, step: 1
2896 04:40:36.069828
2897 04:40:36.073118 RX Delay -40 -> 252, step: 8
2898 04:40:36.076520 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2899 04:40:36.079735 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2900 04:40:36.083193 iDelay=200, Bit 2, Center 123 (56 ~ 191) 136
2901 04:40:36.089871 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2902 04:40:36.093162 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2903 04:40:36.096277 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2904 04:40:36.099867 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2905 04:40:36.103408 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2906 04:40:36.110265 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2907 04:40:36.113284 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2908 04:40:36.116383 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2909 04:40:36.119937 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2910 04:40:36.123070 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2911 04:40:36.129989 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2912 04:40:36.133099 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2913 04:40:36.136998 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2914 04:40:36.137077 ==
2915 04:40:36.140193 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 04:40:36.143241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 04:40:36.143333 ==
2918 04:40:36.146891 DQS Delay:
2919 04:40:36.146965 DQS0 = 0, DQS1 = 0
2920 04:40:36.150116 DQM Delay:
2921 04:40:36.150220 DQM0 = 122, DQM1 = 112
2922 04:40:36.150313 DQ Delay:
2923 04:40:36.153114 DQ0 =119, DQ1 =119, DQ2 =123, DQ3 =119
2924 04:40:36.156915 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2925 04:40:36.163718 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2926 04:40:36.166835 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2927 04:40:36.166919
2928 04:40:36.166983
2929 04:40:36.167059 ==
2930 04:40:36.170048 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 04:40:36.173749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 04:40:36.173841 ==
2933 04:40:36.173908
2934 04:40:36.173970
2935 04:40:36.176735 TX Vref Scan disable
2936 04:40:36.176823 == TX Byte 0 ==
2937 04:40:36.183471 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2938 04:40:36.187168 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2939 04:40:36.187257 == TX Byte 1 ==
2940 04:40:36.193547 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2941 04:40:36.197052 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2942 04:40:36.197137 ==
2943 04:40:36.200378 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 04:40:36.203577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 04:40:36.203663 ==
2946 04:40:36.216483 TX Vref=22, minBit 1, minWin=25, winSum=415
2947 04:40:36.219867 TX Vref=24, minBit 3, minWin=25, winSum=417
2948 04:40:36.223346 TX Vref=26, minBit 3, minWin=25, winSum=420
2949 04:40:36.226906 TX Vref=28, minBit 12, minWin=25, winSum=421
2950 04:40:36.229965 TX Vref=30, minBit 15, minWin=25, winSum=426
2951 04:40:36.236789 TX Vref=32, minBit 0, minWin=26, winSum=423
2952 04:40:36.239946 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 32
2953 04:40:36.240037
2954 04:40:36.243232 Final TX Range 1 Vref 32
2955 04:40:36.243319
2956 04:40:36.243384 ==
2957 04:40:36.247018 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 04:40:36.250092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 04:40:36.250177 ==
2960 04:40:36.253265
2961 04:40:36.253349
2962 04:40:36.253413 TX Vref Scan disable
2963 04:40:36.256418 == TX Byte 0 ==
2964 04:40:36.260107 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2965 04:40:36.263359 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2966 04:40:36.266999 == TX Byte 1 ==
2967 04:40:36.270095 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2968 04:40:36.273191 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2969 04:40:36.273275
2970 04:40:36.276923 [DATLAT]
2971 04:40:36.277011 Freq=1200, CH0 RK1
2972 04:40:36.277077
2973 04:40:36.279961 DATLAT Default: 0xd
2974 04:40:36.280044 0, 0xFFFF, sum = 0
2975 04:40:36.283624 1, 0xFFFF, sum = 0
2976 04:40:36.283709 2, 0xFFFF, sum = 0
2977 04:40:36.286647 3, 0xFFFF, sum = 0
2978 04:40:36.286731 4, 0xFFFF, sum = 0
2979 04:40:36.290337 5, 0xFFFF, sum = 0
2980 04:40:36.290422 6, 0xFFFF, sum = 0
2981 04:40:36.293397 7, 0xFFFF, sum = 0
2982 04:40:36.293481 8, 0xFFFF, sum = 0
2983 04:40:36.296988 9, 0xFFFF, sum = 0
2984 04:40:36.300040 10, 0xFFFF, sum = 0
2985 04:40:36.300125 11, 0xFFFF, sum = 0
2986 04:40:36.303689 12, 0x0, sum = 1
2987 04:40:36.303773 13, 0x0, sum = 2
2988 04:40:36.303839 14, 0x0, sum = 3
2989 04:40:36.306688 15, 0x0, sum = 4
2990 04:40:36.306772 best_step = 13
2991 04:40:36.306840
2992 04:40:36.310183 ==
2993 04:40:36.310271 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 04:40:36.317211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 04:40:36.317298 ==
2996 04:40:36.317364 RX Vref Scan: 0
2997 04:40:36.317425
2998 04:40:36.320206 RX Vref 0 -> 0, step: 1
2999 04:40:36.320320
3000 04:40:36.323576 RX Delay -13 -> 252, step: 4
3001 04:40:36.327151 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3002 04:40:36.330735 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3003 04:40:36.336778 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3004 04:40:36.340268 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3005 04:40:36.343348 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3006 04:40:36.347340 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3007 04:40:36.350283 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3008 04:40:36.357274 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3009 04:40:36.360289 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3010 04:40:36.363453 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3011 04:40:36.367282 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3012 04:40:36.370244 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3013 04:40:36.377158 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3014 04:40:36.380158 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3015 04:40:36.383903 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3016 04:40:36.386941 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3017 04:40:36.387025 ==
3018 04:40:36.390667 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 04:40:36.393843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 04:40:36.397267 ==
3021 04:40:36.397364 DQS Delay:
3022 04:40:36.397430 DQS0 = 0, DQS1 = 0
3023 04:40:36.400362 DQM Delay:
3024 04:40:36.400446 DQM0 = 121, DQM1 = 110
3025 04:40:36.404156 DQ Delay:
3026 04:40:36.407321 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3027 04:40:36.410432 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3028 04:40:36.413524 DQ8 =100, DQ9 =100, DQ10 =110, DQ11 =104
3029 04:40:36.417054 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3030 04:40:36.417138
3031 04:40:36.417202
3032 04:40:36.423753 [DQSOSCAuto] RK1, (LSB)MR18= 0xdef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3033 04:40:36.427053 CH0 RK1: MR19=403, MR18=DEF
3034 04:40:36.433757 CH0_RK1: MR19=0x403, MR18=0xDEF, DQSOSC=405, MR23=63, INC=39, DEC=26
3035 04:40:36.437247 [RxdqsGatingPostProcess] freq 1200
3036 04:40:36.443680 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3037 04:40:36.443774 best DQS0 dly(2T, 0.5T) = (0, 11)
3038 04:40:36.447123 best DQS1 dly(2T, 0.5T) = (0, 12)
3039 04:40:36.450557 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3040 04:40:36.454064 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3041 04:40:36.457123 best DQS0 dly(2T, 0.5T) = (0, 11)
3042 04:40:36.460380 best DQS1 dly(2T, 0.5T) = (0, 11)
3043 04:40:36.464072 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3044 04:40:36.467224 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3045 04:40:36.470342 Pre-setting of DQS Precalculation
3046 04:40:36.474017 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3047 04:40:36.477117 ==
3048 04:40:36.480805 Dram Type= 6, Freq= 0, CH_1, rank 0
3049 04:40:36.484017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3050 04:40:36.484103 ==
3051 04:40:36.486964 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3052 04:40:36.493928 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3053 04:40:36.503215 [CA 0] Center 37 (7~68) winsize 62
3054 04:40:36.506218 [CA 1] Center 37 (7~68) winsize 62
3055 04:40:36.509944 [CA 2] Center 35 (5~65) winsize 61
3056 04:40:36.513005 [CA 3] Center 34 (5~64) winsize 60
3057 04:40:36.516670 [CA 4] Center 34 (4~64) winsize 61
3058 04:40:36.519760 [CA 5] Center 33 (3~63) winsize 61
3059 04:40:36.519846
3060 04:40:36.522947 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3061 04:40:36.523033
3062 04:40:36.526588 [CATrainingPosCal] consider 1 rank data
3063 04:40:36.529637 u2DelayCellTimex100 = 270/100 ps
3064 04:40:36.533087 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3065 04:40:36.536061 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3066 04:40:36.542837 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3067 04:40:36.546204 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3068 04:40:36.549467 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3069 04:40:36.552748 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3070 04:40:36.552833
3071 04:40:36.556235 CA PerBit enable=1, Macro0, CA PI delay=33
3072 04:40:36.556320
3073 04:40:36.559811 [CBTSetCACLKResult] CA Dly = 33
3074 04:40:36.559897 CS Dly: 8 (0~39)
3075 04:40:36.559964 ==
3076 04:40:36.563053 Dram Type= 6, Freq= 0, CH_1, rank 1
3077 04:40:36.569465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 04:40:36.569552 ==
3079 04:40:36.573022 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3080 04:40:36.580023 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3081 04:40:36.588621 [CA 0] Center 37 (7~68) winsize 62
3082 04:40:36.591842 [CA 1] Center 37 (7~68) winsize 62
3083 04:40:36.595545 [CA 2] Center 35 (5~65) winsize 61
3084 04:40:36.598674 [CA 3] Center 35 (5~65) winsize 61
3085 04:40:36.601749 [CA 4] Center 34 (4~65) winsize 62
3086 04:40:36.605537 [CA 5] Center 34 (4~64) winsize 61
3087 04:40:36.605626
3088 04:40:36.608760 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3089 04:40:36.608846
3090 04:40:36.612270 [CATrainingPosCal] consider 2 rank data
3091 04:40:36.615122 u2DelayCellTimex100 = 270/100 ps
3092 04:40:36.618830 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3093 04:40:36.621925 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3094 04:40:36.628799 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3095 04:40:36.631757 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3096 04:40:36.635371 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3097 04:40:36.638569 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3098 04:40:36.638654
3099 04:40:36.642425 CA PerBit enable=1, Macro0, CA PI delay=33
3100 04:40:36.642512
3101 04:40:36.645123 [CBTSetCACLKResult] CA Dly = 33
3102 04:40:36.645225 CS Dly: 9 (0~41)
3103 04:40:36.645305
3104 04:40:36.648844 ----->DramcWriteLeveling(PI) begin...
3105 04:40:36.652016 ==
3106 04:40:36.652100 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 04:40:36.658657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 04:40:36.658743 ==
3109 04:40:36.661772 Write leveling (Byte 0): 25 => 25
3110 04:40:36.665741 Write leveling (Byte 1): 29 => 29
3111 04:40:36.668534 DramcWriteLeveling(PI) end<-----
3112 04:40:36.668632
3113 04:40:36.668697 ==
3114 04:40:36.672010 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 04:40:36.675354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 04:40:36.675439 ==
3117 04:40:36.678302 [Gating] SW mode calibration
3118 04:40:36.685332 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3119 04:40:36.688757 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3120 04:40:36.695384 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3121 04:40:36.698356 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 04:40:36.701983 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 04:40:36.708332 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 04:40:36.712102 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 04:40:36.715320 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 04:40:36.722004 0 15 24 | B1->B0 | 3434 2727 | 0 1 | (0 1) (1 0)
3127 04:40:36.724941 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3128 04:40:36.728728 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 04:40:36.735667 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 04:40:36.738696 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 04:40:36.742001 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 04:40:36.748815 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 04:40:36.751997 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 04:40:36.755116 1 0 24 | B1->B0 | 3434 4141 | 0 0 | (0 0) (0 0)
3135 04:40:36.758874 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 04:40:36.765180 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 04:40:36.768652 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 04:40:36.771969 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 04:40:36.778705 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 04:40:36.782398 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 04:40:36.785322 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 04:40:36.791988 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3143 04:40:36.795644 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3144 04:40:36.798650 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 04:40:36.805427 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 04:40:36.808532 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 04:40:36.812226 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 04:40:36.819194 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 04:40:36.822362 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 04:40:36.825358 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 04:40:36.832444 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 04:40:36.835598 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 04:40:36.838695 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 04:40:36.845479 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 04:40:36.848752 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 04:40:36.852370 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 04:40:36.855333 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 04:40:36.862341 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3159 04:40:36.865666 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3160 04:40:36.868798 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 04:40:36.872602 Total UI for P1: 0, mck2ui 16
3162 04:40:36.875752 best dqsien dly found for B0: ( 1, 3, 26)
3163 04:40:36.878939 Total UI for P1: 0, mck2ui 16
3164 04:40:36.882114 best dqsien dly found for B1: ( 1, 3, 26)
3165 04:40:36.885635 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3166 04:40:36.888958 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3167 04:40:36.889033
3168 04:40:36.895701 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3169 04:40:36.898889 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3170 04:40:36.898965 [Gating] SW calibration Done
3171 04:40:36.902718 ==
3172 04:40:36.905507 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 04:40:36.908956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 04:40:36.909039 ==
3175 04:40:36.909105 RX Vref Scan: 0
3176 04:40:36.909164
3177 04:40:36.912270 RX Vref 0 -> 0, step: 1
3178 04:40:36.912391
3179 04:40:36.915633 RX Delay -40 -> 252, step: 8
3180 04:40:36.918999 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3181 04:40:36.922740 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3182 04:40:36.925978 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3183 04:40:36.932892 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3184 04:40:36.935772 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3185 04:40:36.939298 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3186 04:40:36.942406 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3187 04:40:36.945875 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3188 04:40:36.952324 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3189 04:40:36.955983 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3190 04:40:36.959132 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3191 04:40:36.962726 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3192 04:40:36.965705 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3193 04:40:36.972595 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3194 04:40:36.975613 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3195 04:40:36.979237 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3196 04:40:36.979341 ==
3197 04:40:36.982449 Dram Type= 6, Freq= 0, CH_1, rank 0
3198 04:40:36.985572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3199 04:40:36.985677 ==
3200 04:40:36.989430 DQS Delay:
3201 04:40:36.989515 DQS0 = 0, DQS1 = 0
3202 04:40:36.992415 DQM Delay:
3203 04:40:36.992526 DQM0 = 119, DQM1 = 116
3204 04:40:36.992622 DQ Delay:
3205 04:40:36.995969 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3206 04:40:37.002647 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3207 04:40:37.005795 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111
3208 04:40:37.009151 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3209 04:40:37.009238
3210 04:40:37.009304
3211 04:40:37.009365 ==
3212 04:40:37.012651 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 04:40:37.015805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 04:40:37.015892 ==
3215 04:40:37.015959
3216 04:40:37.016020
3217 04:40:37.019217 TX Vref Scan disable
3218 04:40:37.022699 == TX Byte 0 ==
3219 04:40:37.025719 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3220 04:40:37.029021 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3221 04:40:37.032368 == TX Byte 1 ==
3222 04:40:37.035873 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3223 04:40:37.039559 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3224 04:40:37.039644 ==
3225 04:40:37.042692 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 04:40:37.046285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 04:40:37.046397 ==
3228 04:40:37.059060 TX Vref=22, minBit 9, minWin=25, winSum=414
3229 04:40:37.062856 TX Vref=24, minBit 10, minWin=25, winSum=419
3230 04:40:37.065910 TX Vref=26, minBit 3, minWin=26, winSum=427
3231 04:40:37.069066 TX Vref=28, minBit 9, minWin=25, winSum=428
3232 04:40:37.072759 TX Vref=30, minBit 2, minWin=26, winSum=430
3233 04:40:37.079521 TX Vref=32, minBit 10, minWin=26, winSum=431
3234 04:40:37.082641 [TxChooseVref] Worse bit 10, Min win 26, Win sum 431, Final Vref 32
3235 04:40:37.082748
3236 04:40:37.085647 Final TX Range 1 Vref 32
3237 04:40:37.085753
3238 04:40:37.085847 ==
3239 04:40:37.089444 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 04:40:37.092750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 04:40:37.092836 ==
3242 04:40:37.095732
3243 04:40:37.095844
3244 04:40:37.095941 TX Vref Scan disable
3245 04:40:37.099366 == TX Byte 0 ==
3246 04:40:37.102239 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3247 04:40:37.109335 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3248 04:40:37.109432 == TX Byte 1 ==
3249 04:40:37.112146 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3250 04:40:37.119096 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3251 04:40:37.119187
3252 04:40:37.119254 [DATLAT]
3253 04:40:37.119316 Freq=1200, CH1 RK0
3254 04:40:37.119409
3255 04:40:37.122411 DATLAT Default: 0xd
3256 04:40:37.122523 0, 0xFFFF, sum = 0
3257 04:40:37.125940 1, 0xFFFF, sum = 0
3258 04:40:37.126032 2, 0xFFFF, sum = 0
3259 04:40:37.129075 3, 0xFFFF, sum = 0
3260 04:40:37.132770 4, 0xFFFF, sum = 0
3261 04:40:37.132856 5, 0xFFFF, sum = 0
3262 04:40:37.135453 6, 0xFFFF, sum = 0
3263 04:40:37.135579 7, 0xFFFF, sum = 0
3264 04:40:37.139084 8, 0xFFFF, sum = 0
3265 04:40:37.139170 9, 0xFFFF, sum = 0
3266 04:40:37.142509 10, 0xFFFF, sum = 0
3267 04:40:37.142626 11, 0xFFFF, sum = 0
3268 04:40:37.145892 12, 0x0, sum = 1
3269 04:40:37.145978 13, 0x0, sum = 2
3270 04:40:37.148806 14, 0x0, sum = 3
3271 04:40:37.148921 15, 0x0, sum = 4
3272 04:40:37.149018 best_step = 13
3273 04:40:37.152329
3274 04:40:37.152441 ==
3275 04:40:37.155406 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 04:40:37.159083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 04:40:37.159193 ==
3278 04:40:37.159287 RX Vref Scan: 1
3279 04:40:37.159377
3280 04:40:37.162302 Set Vref Range= 32 -> 127
3281 04:40:37.162406
3282 04:40:37.165553 RX Vref 32 -> 127, step: 1
3283 04:40:37.165658
3284 04:40:37.169209 RX Delay -5 -> 252, step: 4
3285 04:40:37.169314
3286 04:40:37.172270 Set Vref, RX VrefLevel [Byte0]: 32
3287 04:40:37.175441 [Byte1]: 32
3288 04:40:37.175550
3289 04:40:37.179260 Set Vref, RX VrefLevel [Byte0]: 33
3290 04:40:37.182325 [Byte1]: 33
3291 04:40:37.182409
3292 04:40:37.185416 Set Vref, RX VrefLevel [Byte0]: 34
3293 04:40:37.189118 [Byte1]: 34
3294 04:40:37.192998
3295 04:40:37.193082 Set Vref, RX VrefLevel [Byte0]: 35
3296 04:40:37.196744 [Byte1]: 35
3297 04:40:37.201115
3298 04:40:37.201199 Set Vref, RX VrefLevel [Byte0]: 36
3299 04:40:37.204339 [Byte1]: 36
3300 04:40:37.209084
3301 04:40:37.209169 Set Vref, RX VrefLevel [Byte0]: 37
3302 04:40:37.212274 [Byte1]: 37
3303 04:40:37.216553
3304 04:40:37.216637 Set Vref, RX VrefLevel [Byte0]: 38
3305 04:40:37.219992 [Byte1]: 38
3306 04:40:37.224665
3307 04:40:37.224749 Set Vref, RX VrefLevel [Byte0]: 39
3308 04:40:37.228169 [Byte1]: 39
3309 04:40:37.232438
3310 04:40:37.232523 Set Vref, RX VrefLevel [Byte0]: 40
3311 04:40:37.235528 [Byte1]: 40
3312 04:40:37.240394
3313 04:40:37.240504 Set Vref, RX VrefLevel [Byte0]: 41
3314 04:40:37.243512 [Byte1]: 41
3315 04:40:37.248399
3316 04:40:37.248498 Set Vref, RX VrefLevel [Byte0]: 42
3317 04:40:37.251402 [Byte1]: 42
3318 04:40:37.256234
3319 04:40:37.256309 Set Vref, RX VrefLevel [Byte0]: 43
3320 04:40:37.259214 [Byte1]: 43
3321 04:40:37.264018
3322 04:40:37.264131 Set Vref, RX VrefLevel [Byte0]: 44
3323 04:40:37.270196 [Byte1]: 44
3324 04:40:37.270306
3325 04:40:37.273829 Set Vref, RX VrefLevel [Byte0]: 45
3326 04:40:37.276749 [Byte1]: 45
3327 04:40:37.276825
3328 04:40:37.280445 Set Vref, RX VrefLevel [Byte0]: 46
3329 04:40:37.283755 [Byte1]: 46
3330 04:40:37.287379
3331 04:40:37.287490 Set Vref, RX VrefLevel [Byte0]: 47
3332 04:40:37.290454 [Byte1]: 47
3333 04:40:37.295495
3334 04:40:37.295590 Set Vref, RX VrefLevel [Byte0]: 48
3335 04:40:37.298654 [Byte1]: 48
3336 04:40:37.303441
3337 04:40:37.303554 Set Vref, RX VrefLevel [Byte0]: 49
3338 04:40:37.306932 [Byte1]: 49
3339 04:40:37.311073
3340 04:40:37.311183 Set Vref, RX VrefLevel [Byte0]: 50
3341 04:40:37.314233 [Byte1]: 50
3342 04:40:37.318598
3343 04:40:37.318685 Set Vref, RX VrefLevel [Byte0]: 51
3344 04:40:37.322182 [Byte1]: 51
3345 04:40:37.327056
3346 04:40:37.327141 Set Vref, RX VrefLevel [Byte0]: 52
3347 04:40:37.330131 [Byte1]: 52
3348 04:40:37.334359
3349 04:40:37.334443 Set Vref, RX VrefLevel [Byte0]: 53
3350 04:40:37.337724 [Byte1]: 53
3351 04:40:37.342481
3352 04:40:37.342600 Set Vref, RX VrefLevel [Byte0]: 54
3353 04:40:37.345699 [Byte1]: 54
3354 04:40:37.349988
3355 04:40:37.350070 Set Vref, RX VrefLevel [Byte0]: 55
3356 04:40:37.353557 [Byte1]: 55
3357 04:40:37.358354
3358 04:40:37.358435 Set Vref, RX VrefLevel [Byte0]: 56
3359 04:40:37.361400 [Byte1]: 56
3360 04:40:37.365674
3361 04:40:37.365760 Set Vref, RX VrefLevel [Byte0]: 57
3362 04:40:37.369306 [Byte1]: 57
3363 04:40:37.373619
3364 04:40:37.373700 Set Vref, RX VrefLevel [Byte0]: 58
3365 04:40:37.377409 [Byte1]: 58
3366 04:40:37.381830
3367 04:40:37.381943 Set Vref, RX VrefLevel [Byte0]: 59
3368 04:40:37.384729 [Byte1]: 59
3369 04:40:37.389705
3370 04:40:37.389801 Set Vref, RX VrefLevel [Byte0]: 60
3371 04:40:37.392633 [Byte1]: 60
3372 04:40:37.397603
3373 04:40:37.397715 Set Vref, RX VrefLevel [Byte0]: 61
3374 04:40:37.400607 [Byte1]: 61
3375 04:40:37.404917
3376 04:40:37.404993 Set Vref, RX VrefLevel [Byte0]: 62
3377 04:40:37.408273 [Byte1]: 62
3378 04:40:37.413248
3379 04:40:37.413366 Set Vref, RX VrefLevel [Byte0]: 63
3380 04:40:37.416285 [Byte1]: 63
3381 04:40:37.421363
3382 04:40:37.421439 Set Vref, RX VrefLevel [Byte0]: 64
3383 04:40:37.424247 [Byte1]: 64
3384 04:40:37.428454
3385 04:40:37.428531 Set Vref, RX VrefLevel [Byte0]: 65
3386 04:40:37.435318 [Byte1]: 65
3387 04:40:37.435451
3388 04:40:37.438408 Set Vref, RX VrefLevel [Byte0]: 66
3389 04:40:37.442201 [Byte1]: 66
3390 04:40:37.442290
3391 04:40:37.445632 Set Vref, RX VrefLevel [Byte0]: 67
3392 04:40:37.448402 [Byte1]: 67
3393 04:40:37.452402
3394 04:40:37.452498 Set Vref, RX VrefLevel [Byte0]: 68
3395 04:40:37.455436 [Byte1]: 68
3396 04:40:37.460280
3397 04:40:37.460362 Set Vref, RX VrefLevel [Byte0]: 69
3398 04:40:37.463261 [Byte1]: 69
3399 04:40:37.468189
3400 04:40:37.468286 Final RX Vref Byte 0 = 54 to rank0
3401 04:40:37.471238 Final RX Vref Byte 1 = 55 to rank0
3402 04:40:37.474772 Final RX Vref Byte 0 = 54 to rank1
3403 04:40:37.478403 Final RX Vref Byte 1 = 55 to rank1==
3404 04:40:37.481381 Dram Type= 6, Freq= 0, CH_1, rank 0
3405 04:40:37.488065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3406 04:40:37.488163 ==
3407 04:40:37.488229 DQS Delay:
3408 04:40:37.488289 DQS0 = 0, DQS1 = 0
3409 04:40:37.491130 DQM Delay:
3410 04:40:37.491250 DQM0 = 120, DQM1 = 117
3411 04:40:37.495030 DQ Delay:
3412 04:40:37.498003 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3413 04:40:37.501605 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3414 04:40:37.504540 DQ8 =104, DQ9 =108, DQ10 =118, DQ11 =112
3415 04:40:37.508254 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3416 04:40:37.508339
3417 04:40:37.508403
3418 04:40:37.515083 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe11, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3419 04:40:37.518054 CH1 RK0: MR19=304, MR18=FE11
3420 04:40:37.524870 CH1_RK0: MR19=0x304, MR18=0xFE11, DQSOSC=403, MR23=63, INC=40, DEC=26
3421 04:40:37.524971
3422 04:40:37.528049 ----->DramcWriteLeveling(PI) begin...
3423 04:40:37.528134 ==
3424 04:40:37.531485 Dram Type= 6, Freq= 0, CH_1, rank 1
3425 04:40:37.534653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3426 04:40:37.538400 ==
3427 04:40:37.538510 Write leveling (Byte 0): 25 => 25
3428 04:40:37.541492 Write leveling (Byte 1): 28 => 28
3429 04:40:37.544591 DramcWriteLeveling(PI) end<-----
3430 04:40:37.544679
3431 04:40:37.544745 ==
3432 04:40:37.547893 Dram Type= 6, Freq= 0, CH_1, rank 1
3433 04:40:37.554869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3434 04:40:37.554955 ==
3435 04:40:37.555021 [Gating] SW mode calibration
3436 04:40:37.564787 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3437 04:40:37.568381 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3438 04:40:37.571269 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 04:40:37.578121 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 04:40:37.581813 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 04:40:37.584872 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 04:40:37.591592 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 04:40:37.595028 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3444 04:40:37.598174 0 15 24 | B1->B0 | 2c2c 3232 | 0 1 | (0 0) (1 1)
3445 04:40:37.604799 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
3446 04:40:37.608570 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 04:40:37.611564 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 04:40:37.618451 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 04:40:37.621960 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 04:40:37.624995 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 04:40:37.631753 1 0 20 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3452 04:40:37.635379 1 0 24 | B1->B0 | 4040 2727 | 0 0 | (0 0) (0 0)
3453 04:40:37.638426 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 04:40:37.642106 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 04:40:37.648450 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 04:40:37.651523 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 04:40:37.655416 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 04:40:37.661771 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 04:40:37.665232 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 04:40:37.668379 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3461 04:40:37.674960 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3462 04:40:37.678465 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 04:40:37.681764 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 04:40:37.688434 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 04:40:37.691671 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 04:40:37.695220 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 04:40:37.701508 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 04:40:37.704931 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 04:40:37.708579 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 04:40:37.714874 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 04:40:37.718678 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 04:40:37.721592 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 04:40:37.728267 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 04:40:37.731366 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 04:40:37.734970 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3476 04:40:37.741674 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3477 04:40:37.741765 Total UI for P1: 0, mck2ui 16
3478 04:40:37.744773 best dqsien dly found for B1: ( 1, 3, 20)
3479 04:40:37.751636 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3480 04:40:37.754852 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 04:40:37.757941 Total UI for P1: 0, mck2ui 16
3482 04:40:37.761194 best dqsien dly found for B0: ( 1, 3, 26)
3483 04:40:37.764449 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3484 04:40:37.768000 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3485 04:40:37.768088
3486 04:40:37.771685 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3487 04:40:37.778277 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3488 04:40:37.778393 [Gating] SW calibration Done
3489 04:40:37.778497 ==
3490 04:40:37.781390 Dram Type= 6, Freq= 0, CH_1, rank 1
3491 04:40:37.787982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3492 04:40:37.788070 ==
3493 04:40:37.788158 RX Vref Scan: 0
3494 04:40:37.788241
3495 04:40:37.791079 RX Vref 0 -> 0, step: 1
3496 04:40:37.791191
3497 04:40:37.794592 RX Delay -40 -> 252, step: 8
3498 04:40:37.797443 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3499 04:40:37.801081 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3500 04:40:37.804248 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3501 04:40:37.811254 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3502 04:40:37.813995 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3503 04:40:37.817755 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3504 04:40:37.820833 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3505 04:40:37.824026 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3506 04:40:37.830550 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3507 04:40:37.834235 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3508 04:40:37.837424 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3509 04:40:37.840671 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3510 04:40:37.843702 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3511 04:40:37.850478 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3512 04:40:37.853612 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3513 04:40:37.857436 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3514 04:40:37.857541 ==
3515 04:40:37.860526 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 04:40:37.863615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 04:40:37.867322 ==
3518 04:40:37.867427 DQS Delay:
3519 04:40:37.867528 DQS0 = 0, DQS1 = 0
3520 04:40:37.870253 DQM Delay:
3521 04:40:37.870355 DQM0 = 121, DQM1 = 117
3522 04:40:37.873419 DQ Delay:
3523 04:40:37.877105 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3524 04:40:37.880111 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3525 04:40:37.883906 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3526 04:40:37.886966 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3527 04:40:37.887069
3528 04:40:37.887161
3529 04:40:37.887250 ==
3530 04:40:37.890197 Dram Type= 6, Freq= 0, CH_1, rank 1
3531 04:40:37.893425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3532 04:40:37.893522 ==
3533 04:40:37.896958
3534 04:40:37.897029
3535 04:40:37.897090 TX Vref Scan disable
3536 04:40:37.900407 == TX Byte 0 ==
3537 04:40:37.903354 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3538 04:40:37.906910 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3539 04:40:37.910338 == TX Byte 1 ==
3540 04:40:37.913955 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3541 04:40:37.916886 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3542 04:40:37.916966 ==
3543 04:40:37.920280 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 04:40:37.926977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 04:40:37.927071 ==
3546 04:40:37.937351 TX Vref=22, minBit 9, minWin=25, winSum=421
3547 04:40:37.940929 TX Vref=24, minBit 1, minWin=26, winSum=424
3548 04:40:37.944183 TX Vref=26, minBit 2, minWin=26, winSum=428
3549 04:40:37.947336 TX Vref=28, minBit 9, minWin=26, winSum=432
3550 04:40:37.950932 TX Vref=30, minBit 9, minWin=26, winSum=435
3551 04:40:37.954074 TX Vref=32, minBit 9, minWin=26, winSum=436
3552 04:40:37.961058 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 32
3553 04:40:37.961137
3554 04:40:37.964115 Final TX Range 1 Vref 32
3555 04:40:37.964197
3556 04:40:37.964264 ==
3557 04:40:37.967267 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 04:40:37.970429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 04:40:37.970505 ==
3560 04:40:37.974014
3561 04:40:37.974128
3562 04:40:37.974224 TX Vref Scan disable
3563 04:40:37.977074 == TX Byte 0 ==
3564 04:40:37.980910 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3565 04:40:37.983998 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3566 04:40:37.987513 == TX Byte 1 ==
3567 04:40:37.990671 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3568 04:40:37.993772 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3569 04:40:37.993847
3570 04:40:37.997492 [DATLAT]
3571 04:40:37.997604 Freq=1200, CH1 RK1
3572 04:40:37.997704
3573 04:40:38.000640 DATLAT Default: 0xd
3574 04:40:38.000725 0, 0xFFFF, sum = 0
3575 04:40:38.003739 1, 0xFFFF, sum = 0
3576 04:40:38.003825 2, 0xFFFF, sum = 0
3577 04:40:38.007356 3, 0xFFFF, sum = 0
3578 04:40:38.007472 4, 0xFFFF, sum = 0
3579 04:40:38.010498 5, 0xFFFF, sum = 0
3580 04:40:38.010613 6, 0xFFFF, sum = 0
3581 04:40:38.014204 7, 0xFFFF, sum = 0
3582 04:40:38.017137 8, 0xFFFF, sum = 0
3583 04:40:38.017244 9, 0xFFFF, sum = 0
3584 04:40:38.020665 10, 0xFFFF, sum = 0
3585 04:40:38.020791 11, 0xFFFF, sum = 0
3586 04:40:38.023859 12, 0x0, sum = 1
3587 04:40:38.023952 13, 0x0, sum = 2
3588 04:40:38.027592 14, 0x0, sum = 3
3589 04:40:38.027687 15, 0x0, sum = 4
3590 04:40:38.027777 best_step = 13
3591 04:40:38.027859
3592 04:40:38.030517 ==
3593 04:40:38.034226 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 04:40:38.037008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 04:40:38.037121 ==
3596 04:40:38.037217 RX Vref Scan: 0
3597 04:40:38.037308
3598 04:40:38.040412 RX Vref 0 -> 0, step: 1
3599 04:40:38.040496
3600 04:40:38.043891 RX Delay -5 -> 252, step: 4
3601 04:40:38.047426 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3602 04:40:38.053847 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3603 04:40:38.057742 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3604 04:40:38.060660 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3605 04:40:38.063702 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3606 04:40:38.067316 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3607 04:40:38.070388 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3608 04:40:38.077122 iDelay=195, Bit 7, Center 118 (55 ~ 182) 128
3609 04:40:38.080889 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3610 04:40:38.083787 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3611 04:40:38.086919 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3612 04:40:38.090636 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3613 04:40:38.097304 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3614 04:40:38.100386 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3615 04:40:38.103542 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3616 04:40:38.107252 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3617 04:40:38.107341 ==
3618 04:40:38.110135 Dram Type= 6, Freq= 0, CH_1, rank 1
3619 04:40:38.117020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3620 04:40:38.117124 ==
3621 04:40:38.117191 DQS Delay:
3622 04:40:38.120199 DQS0 = 0, DQS1 = 0
3623 04:40:38.120284 DQM Delay:
3624 04:40:38.123911 DQM0 = 119, DQM1 = 118
3625 04:40:38.124030 DQ Delay:
3626 04:40:38.126992 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3627 04:40:38.130439 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =118
3628 04:40:38.133526 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3629 04:40:38.136896 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3630 04:40:38.136980
3631 04:40:38.137044
3632 04:40:38.146825 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3633 04:40:38.146918 CH1 RK1: MR19=403, MR18=10ED
3634 04:40:38.153725 CH1_RK1: MR19=0x403, MR18=0x10ED, DQSOSC=403, MR23=63, INC=40, DEC=26
3635 04:40:38.156883 [RxdqsGatingPostProcess] freq 1200
3636 04:40:38.163608 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3637 04:40:38.167144 best DQS0 dly(2T, 0.5T) = (0, 11)
3638 04:40:38.170398 best DQS1 dly(2T, 0.5T) = (0, 11)
3639 04:40:38.173506 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3640 04:40:38.176721 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3641 04:40:38.180179 best DQS0 dly(2T, 0.5T) = (0, 11)
3642 04:40:38.180289 best DQS1 dly(2T, 0.5T) = (0, 11)
3643 04:40:38.183832 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3644 04:40:38.186992 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3645 04:40:38.190190 Pre-setting of DQS Precalculation
3646 04:40:38.197007 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3647 04:40:38.203444 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3648 04:40:38.210175 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3649 04:40:38.210263
3650 04:40:38.210363
3651 04:40:38.213255 [Calibration Summary] 2400 Mbps
3652 04:40:38.216929 CH 0, Rank 0
3653 04:40:38.217012 SW Impedance : PASS
3654 04:40:38.220044 DUTY Scan : NO K
3655 04:40:38.220126 ZQ Calibration : PASS
3656 04:40:38.223330 Jitter Meter : NO K
3657 04:40:38.226941 CBT Training : PASS
3658 04:40:38.227023 Write leveling : PASS
3659 04:40:38.230018 RX DQS gating : PASS
3660 04:40:38.233133 RX DQ/DQS(RDDQC) : PASS
3661 04:40:38.233215 TX DQ/DQS : PASS
3662 04:40:38.236781 RX DATLAT : PASS
3663 04:40:38.240261 RX DQ/DQS(Engine): PASS
3664 04:40:38.240343 TX OE : NO K
3665 04:40:38.243545 All Pass.
3666 04:40:38.243680
3667 04:40:38.243776 CH 0, Rank 1
3668 04:40:38.246660 SW Impedance : PASS
3669 04:40:38.246743 DUTY Scan : NO K
3670 04:40:38.250150 ZQ Calibration : PASS
3671 04:40:38.253210 Jitter Meter : NO K
3672 04:40:38.253304 CBT Training : PASS
3673 04:40:38.256536 Write leveling : PASS
3674 04:40:38.260205 RX DQS gating : PASS
3675 04:40:38.260289 RX DQ/DQS(RDDQC) : PASS
3676 04:40:38.262895 TX DQ/DQS : PASS
3677 04:40:38.266338 RX DATLAT : PASS
3678 04:40:38.266445 RX DQ/DQS(Engine): PASS
3679 04:40:38.269895 TX OE : NO K
3680 04:40:38.269980 All Pass.
3681 04:40:38.270075
3682 04:40:38.273254 CH 1, Rank 0
3683 04:40:38.273340 SW Impedance : PASS
3684 04:40:38.276465 DUTY Scan : NO K
3685 04:40:38.279462 ZQ Calibration : PASS
3686 04:40:38.279588 Jitter Meter : NO K
3687 04:40:38.283128 CBT Training : PASS
3688 04:40:38.283212 Write leveling : PASS
3689 04:40:38.286133 RX DQS gating : PASS
3690 04:40:38.289723 RX DQ/DQS(RDDQC) : PASS
3691 04:40:38.289810 TX DQ/DQS : PASS
3692 04:40:38.292825 RX DATLAT : PASS
3693 04:40:38.296059 RX DQ/DQS(Engine): PASS
3694 04:40:38.296166 TX OE : NO K
3695 04:40:38.299758 All Pass.
3696 04:40:38.299866
3697 04:40:38.299961 CH 1, Rank 1
3698 04:40:38.302809 SW Impedance : PASS
3699 04:40:38.302923 DUTY Scan : NO K
3700 04:40:38.306375 ZQ Calibration : PASS
3701 04:40:38.309385 Jitter Meter : NO K
3702 04:40:38.309537 CBT Training : PASS
3703 04:40:38.313053 Write leveling : PASS
3704 04:40:38.316555 RX DQS gating : PASS
3705 04:40:38.316657 RX DQ/DQS(RDDQC) : PASS
3706 04:40:38.319736 TX DQ/DQS : PASS
3707 04:40:38.319817 RX DATLAT : PASS
3708 04:40:38.322823 RX DQ/DQS(Engine): PASS
3709 04:40:38.325978 TX OE : NO K
3710 04:40:38.326080 All Pass.
3711 04:40:38.326187
3712 04:40:38.329656 DramC Write-DBI off
3713 04:40:38.332895 PER_BANK_REFRESH: Hybrid Mode
3714 04:40:38.333004 TX_TRACKING: ON
3715 04:40:38.342981 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3716 04:40:38.346426 [FAST_K] Save calibration result to emmc
3717 04:40:38.349522 dramc_set_vcore_voltage set vcore to 650000
3718 04:40:38.349611 Read voltage for 600, 5
3719 04:40:38.353136 Vio18 = 0
3720 04:40:38.353224 Vcore = 650000
3721 04:40:38.353294 Vdram = 0
3722 04:40:38.356515 Vddq = 0
3723 04:40:38.356599 Vmddr = 0
3724 04:40:38.363195 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3725 04:40:38.366049 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3726 04:40:38.369794 MEM_TYPE=3, freq_sel=19
3727 04:40:38.372870 sv_algorithm_assistance_LP4_1600
3728 04:40:38.375909 ============ PULL DRAM RESETB DOWN ============
3729 04:40:38.379446 ========== PULL DRAM RESETB DOWN end =========
3730 04:40:38.386479 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3731 04:40:38.389431 ===================================
3732 04:40:38.389536 LPDDR4 DRAM CONFIGURATION
3733 04:40:38.392881 ===================================
3734 04:40:38.395954 EX_ROW_EN[0] = 0x0
3735 04:40:38.396058 EX_ROW_EN[1] = 0x0
3736 04:40:38.399642 LP4Y_EN = 0x0
3737 04:40:38.399721 WORK_FSP = 0x0
3738 04:40:38.402890 WL = 0x2
3739 04:40:38.405907 RL = 0x2
3740 04:40:38.406025 BL = 0x2
3741 04:40:38.409644 RPST = 0x0
3742 04:40:38.409751 RD_PRE = 0x0
3743 04:40:38.412784 WR_PRE = 0x1
3744 04:40:38.412887 WR_PST = 0x0
3745 04:40:38.416411 DBI_WR = 0x0
3746 04:40:38.416533 DBI_RD = 0x0
3747 04:40:38.419296 OTF = 0x1
3748 04:40:38.422923 ===================================
3749 04:40:38.425879 ===================================
3750 04:40:38.425997 ANA top config
3751 04:40:38.429150 ===================================
3752 04:40:38.432926 DLL_ASYNC_EN = 0
3753 04:40:38.436127 ALL_SLAVE_EN = 1
3754 04:40:38.436237 NEW_RANK_MODE = 1
3755 04:40:38.439285 DLL_IDLE_MODE = 1
3756 04:40:38.442398 LP45_APHY_COMB_EN = 1
3757 04:40:38.446364 TX_ODT_DIS = 1
3758 04:40:38.446485 NEW_8X_MODE = 1
3759 04:40:38.449411 ===================================
3760 04:40:38.452618 ===================================
3761 04:40:38.455789 data_rate = 1200
3762 04:40:38.459421 CKR = 1
3763 04:40:38.462356 DQ_P2S_RATIO = 8
3764 04:40:38.465991 ===================================
3765 04:40:38.469483 CA_P2S_RATIO = 8
3766 04:40:38.472229 DQ_CA_OPEN = 0
3767 04:40:38.475719 DQ_SEMI_OPEN = 0
3768 04:40:38.475850 CA_SEMI_OPEN = 0
3769 04:40:38.479253 CA_FULL_RATE = 0
3770 04:40:38.482631 DQ_CKDIV4_EN = 1
3771 04:40:38.485747 CA_CKDIV4_EN = 1
3772 04:40:38.489284 CA_PREDIV_EN = 0
3773 04:40:38.492412 PH8_DLY = 0
3774 04:40:38.492491 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3775 04:40:38.495501 DQ_AAMCK_DIV = 4
3776 04:40:38.498774 CA_AAMCK_DIV = 4
3777 04:40:38.502425 CA_ADMCK_DIV = 4
3778 04:40:38.505666 DQ_TRACK_CA_EN = 0
3779 04:40:38.508922 CA_PICK = 600
3780 04:40:38.509001 CA_MCKIO = 600
3781 04:40:38.512299 MCKIO_SEMI = 0
3782 04:40:38.515587 PLL_FREQ = 2288
3783 04:40:38.519399 DQ_UI_PI_RATIO = 32
3784 04:40:38.522680 CA_UI_PI_RATIO = 0
3785 04:40:38.525441 ===================================
3786 04:40:38.528900 ===================================
3787 04:40:38.532220 memory_type:LPDDR4
3788 04:40:38.532320 GP_NUM : 10
3789 04:40:38.535836 SRAM_EN : 1
3790 04:40:38.535917 MD32_EN : 0
3791 04:40:38.539002 ===================================
3792 04:40:38.542083 [ANA_INIT] >>>>>>>>>>>>>>
3793 04:40:38.545871 <<<<<< [CONFIGURE PHASE]: ANA_TX
3794 04:40:38.549044 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3795 04:40:38.552228 ===================================
3796 04:40:38.555831 data_rate = 1200,PCW = 0X5800
3797 04:40:38.558978 ===================================
3798 04:40:38.562053 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3799 04:40:38.565664 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3800 04:40:38.572453 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3801 04:40:38.579071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3802 04:40:38.582133 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3803 04:40:38.585302 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3804 04:40:38.585392 [ANA_INIT] flow start
3805 04:40:38.588810 [ANA_INIT] PLL >>>>>>>>
3806 04:40:38.592382 [ANA_INIT] PLL <<<<<<<<
3807 04:40:38.592461 [ANA_INIT] MIDPI >>>>>>>>
3808 04:40:38.595287 [ANA_INIT] MIDPI <<<<<<<<
3809 04:40:38.598898 [ANA_INIT] DLL >>>>>>>>
3810 04:40:38.598991 [ANA_INIT] flow end
3811 04:40:38.602048 ============ LP4 DIFF to SE enter ============
3812 04:40:38.608940 ============ LP4 DIFF to SE exit ============
3813 04:40:38.609023 [ANA_INIT] <<<<<<<<<<<<<
3814 04:40:38.612158 [Flow] Enable top DCM control >>>>>
3815 04:40:38.615323 [Flow] Enable top DCM control <<<<<
3816 04:40:38.619083 Enable DLL master slave shuffle
3817 04:40:38.625458 ==============================================================
3818 04:40:38.625553 Gating Mode config
3819 04:40:38.631969 ==============================================================
3820 04:40:38.635533 Config description:
3821 04:40:38.645500 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3822 04:40:38.652157 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3823 04:40:38.655410 SELPH_MODE 0: By rank 1: By Phase
3824 04:40:38.662160 ==============================================================
3825 04:40:38.665219 GAT_TRACK_EN = 1
3826 04:40:38.668839 RX_GATING_MODE = 2
3827 04:40:38.668923 RX_GATING_TRACK_MODE = 2
3828 04:40:38.671919 SELPH_MODE = 1
3829 04:40:38.675524 PICG_EARLY_EN = 1
3830 04:40:38.678494 VALID_LAT_VALUE = 1
3831 04:40:38.685489 ==============================================================
3832 04:40:38.688520 Enter into Gating configuration >>>>
3833 04:40:38.691930 Exit from Gating configuration <<<<
3834 04:40:38.695078 Enter into DVFS_PRE_config >>>>>
3835 04:40:38.705188 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3836 04:40:38.708916 Exit from DVFS_PRE_config <<<<<
3837 04:40:38.712012 Enter into PICG configuration >>>>
3838 04:40:38.715326 Exit from PICG configuration <<<<
3839 04:40:38.718868 [RX_INPUT] configuration >>>>>
3840 04:40:38.721974 [RX_INPUT] configuration <<<<<
3841 04:40:38.725160 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3842 04:40:38.731953 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3843 04:40:38.738694 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3844 04:40:38.741882 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3845 04:40:38.748384 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3846 04:40:38.755267 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3847 04:40:38.758106 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3848 04:40:38.764771 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3849 04:40:38.768360 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3850 04:40:38.771629 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3851 04:40:38.775259 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3852 04:40:38.782099 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3853 04:40:38.785111 ===================================
3854 04:40:38.785212 LPDDR4 DRAM CONFIGURATION
3855 04:40:38.788174 ===================================
3856 04:40:38.791328 EX_ROW_EN[0] = 0x0
3857 04:40:38.795003 EX_ROW_EN[1] = 0x0
3858 04:40:38.795090 LP4Y_EN = 0x0
3859 04:40:38.798310 WORK_FSP = 0x0
3860 04:40:38.798396 WL = 0x2
3861 04:40:38.801615 RL = 0x2
3862 04:40:38.801708 BL = 0x2
3863 04:40:38.804925 RPST = 0x0
3864 04:40:38.805001 RD_PRE = 0x0
3865 04:40:38.808078 WR_PRE = 0x1
3866 04:40:38.808153 WR_PST = 0x0
3867 04:40:38.811662 DBI_WR = 0x0
3868 04:40:38.811770 DBI_RD = 0x0
3869 04:40:38.814786 OTF = 0x1
3870 04:40:38.817947 ===================================
3871 04:40:38.821555 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3872 04:40:38.824801 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3873 04:40:38.831643 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3874 04:40:38.834623 ===================================
3875 04:40:38.834709 LPDDR4 DRAM CONFIGURATION
3876 04:40:38.838195 ===================================
3877 04:40:38.841232 EX_ROW_EN[0] = 0x10
3878 04:40:38.845007 EX_ROW_EN[1] = 0x0
3879 04:40:38.845091 LP4Y_EN = 0x0
3880 04:40:38.848182 WORK_FSP = 0x0
3881 04:40:38.848266 WL = 0x2
3882 04:40:38.851319 RL = 0x2
3883 04:40:38.851403 BL = 0x2
3884 04:40:38.854370 RPST = 0x0
3885 04:40:38.854462 RD_PRE = 0x0
3886 04:40:38.858075 WR_PRE = 0x1
3887 04:40:38.858153 WR_PST = 0x0
3888 04:40:38.861155 DBI_WR = 0x0
3889 04:40:38.861235 DBI_RD = 0x0
3890 04:40:38.864262 OTF = 0x1
3891 04:40:38.867849 ===================================
3892 04:40:38.874616 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3893 04:40:38.877504 nWR fixed to 30
3894 04:40:38.877587 [ModeRegInit_LP4] CH0 RK0
3895 04:40:38.880901 [ModeRegInit_LP4] CH0 RK1
3896 04:40:38.884270 [ModeRegInit_LP4] CH1 RK0
3897 04:40:38.887653 [ModeRegInit_LP4] CH1 RK1
3898 04:40:38.887767 match AC timing 17
3899 04:40:38.891046 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3900 04:40:38.897741 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3901 04:40:38.900790 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3902 04:40:38.904543 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3903 04:40:38.911310 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3904 04:40:38.911401 ==
3905 04:40:38.914294 Dram Type= 6, Freq= 0, CH_0, rank 0
3906 04:40:38.917592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3907 04:40:38.917684 ==
3908 04:40:38.924291 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3909 04:40:38.928006 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3910 04:40:38.932419 [CA 0] Center 35 (5~66) winsize 62
3911 04:40:38.935650 [CA 1] Center 36 (5~67) winsize 63
3912 04:40:38.939250 [CA 2] Center 33 (3~64) winsize 62
3913 04:40:38.942222 [CA 3] Center 33 (2~64) winsize 63
3914 04:40:38.945432 [CA 4] Center 33 (2~64) winsize 63
3915 04:40:38.948584 [CA 5] Center 32 (2~63) winsize 62
3916 04:40:38.948664
3917 04:40:38.952384 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3918 04:40:38.952479
3919 04:40:38.955504 [CATrainingPosCal] consider 1 rank data
3920 04:40:38.959205 u2DelayCellTimex100 = 270/100 ps
3921 04:40:38.962320 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3922 04:40:38.965298 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3923 04:40:38.972308 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3924 04:40:38.975299 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3925 04:40:38.979138 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3926 04:40:38.982272 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3927 04:40:38.982355
3928 04:40:38.985326 CA PerBit enable=1, Macro0, CA PI delay=32
3929 04:40:38.985405
3930 04:40:38.988920 [CBTSetCACLKResult] CA Dly = 32
3931 04:40:38.989006 CS Dly: 4 (0~35)
3932 04:40:38.991973 ==
3933 04:40:38.995174 Dram Type= 6, Freq= 0, CH_0, rank 1
3934 04:40:38.998990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3935 04:40:38.999069 ==
3936 04:40:39.002023 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3937 04:40:39.008866 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3938 04:40:39.012636 [CA 0] Center 35 (5~66) winsize 62
3939 04:40:39.016074 [CA 1] Center 35 (5~66) winsize 62
3940 04:40:39.019113 [CA 2] Center 34 (3~65) winsize 63
3941 04:40:39.022602 [CA 3] Center 33 (3~64) winsize 62
3942 04:40:39.025543 [CA 4] Center 33 (2~64) winsize 63
3943 04:40:39.029033 [CA 5] Center 32 (1~63) winsize 63
3944 04:40:39.029137
3945 04:40:39.032467 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3946 04:40:39.032549
3947 04:40:39.035994 [CATrainingPosCal] consider 2 rank data
3948 04:40:39.039071 u2DelayCellTimex100 = 270/100 ps
3949 04:40:39.042857 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3950 04:40:39.045753 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3951 04:40:39.052535 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3952 04:40:39.055667 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3953 04:40:39.058780 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3954 04:40:39.062686 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3955 04:40:39.062782
3956 04:40:39.065609 CA PerBit enable=1, Macro0, CA PI delay=32
3957 04:40:39.065723
3958 04:40:39.068807 [CBTSetCACLKResult] CA Dly = 32
3959 04:40:39.068903 CS Dly: 4 (0~36)
3960 04:40:39.068980
3961 04:40:39.072577 ----->DramcWriteLeveling(PI) begin...
3962 04:40:39.075825 ==
3963 04:40:39.075901 Dram Type= 6, Freq= 0, CH_0, rank 0
3964 04:40:39.082491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3965 04:40:39.082580 ==
3966 04:40:39.085572 Write leveling (Byte 0): 35 => 35
3967 04:40:39.089616 Write leveling (Byte 1): 31 => 31
3968 04:40:39.092594 DramcWriteLeveling(PI) end<-----
3969 04:40:39.092707
3970 04:40:39.092799 ==
3971 04:40:39.095683 Dram Type= 6, Freq= 0, CH_0, rank 0
3972 04:40:39.098819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3973 04:40:39.098899 ==
3974 04:40:39.102524 [Gating] SW mode calibration
3975 04:40:39.108772 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3976 04:40:39.112622 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3977 04:40:39.119289 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 04:40:39.122857 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 04:40:39.125506 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3980 04:40:39.132275 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
3981 04:40:39.135850 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
3982 04:40:39.139045 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 04:40:39.145435 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 04:40:39.149204 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 04:40:39.152457 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 04:40:39.159339 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 04:40:39.162512 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 04:40:39.165630 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
3989 04:40:39.172638 0 10 16 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
3990 04:40:39.175727 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 04:40:39.178923 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 04:40:39.185708 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 04:40:39.189304 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 04:40:39.192408 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 04:40:39.195414 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 04:40:39.202297 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 04:40:39.205461 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3998 04:40:39.209285 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 04:40:39.215428 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 04:40:39.219248 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 04:40:39.222272 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 04:40:39.228839 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 04:40:39.231977 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 04:40:39.235634 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 04:40:39.241839 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 04:40:39.245665 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 04:40:39.248646 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 04:40:39.255472 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 04:40:39.258730 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 04:40:39.261983 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 04:40:39.268747 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 04:40:39.272275 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4013 04:40:39.275445 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4014 04:40:39.278419 Total UI for P1: 0, mck2ui 16
4015 04:40:39.282001 best dqsien dly found for B0: ( 0, 13, 12)
4016 04:40:39.288851 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 04:40:39.288968 Total UI for P1: 0, mck2ui 16
4018 04:40:39.295226 best dqsien dly found for B1: ( 0, 13, 16)
4019 04:40:39.298799 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4020 04:40:39.301785 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4021 04:40:39.301872
4022 04:40:39.305562 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4023 04:40:39.308584 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4024 04:40:39.311927 [Gating] SW calibration Done
4025 04:40:39.312006 ==
4026 04:40:39.315550 Dram Type= 6, Freq= 0, CH_0, rank 0
4027 04:40:39.318618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 04:40:39.318704 ==
4029 04:40:39.321642 RX Vref Scan: 0
4030 04:40:39.321733
4031 04:40:39.321813 RX Vref 0 -> 0, step: 1
4032 04:40:39.321888
4033 04:40:39.325460 RX Delay -230 -> 252, step: 16
4034 04:40:39.328681 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4035 04:40:39.335410 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4036 04:40:39.338429 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4037 04:40:39.341580 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4038 04:40:39.345362 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4039 04:40:39.351754 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4040 04:40:39.355381 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4041 04:40:39.358481 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4042 04:40:39.361635 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4043 04:40:39.365303 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4044 04:40:39.371856 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4045 04:40:39.374949 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4046 04:40:39.378634 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4047 04:40:39.381897 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4048 04:40:39.388573 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4049 04:40:39.392045 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4050 04:40:39.392131 ==
4051 04:40:39.395216 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 04:40:39.398599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 04:40:39.398702 ==
4054 04:40:39.401666 DQS Delay:
4055 04:40:39.401769 DQS0 = 0, DQS1 = 0
4056 04:40:39.401859 DQM Delay:
4057 04:40:39.405121 DQM0 = 52, DQM1 = 46
4058 04:40:39.405227 DQ Delay:
4059 04:40:39.408320 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4060 04:40:39.411772 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4061 04:40:39.415035 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4062 04:40:39.418259 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4063 04:40:39.418367
4064 04:40:39.418473
4065 04:40:39.418575 ==
4066 04:40:39.421960 Dram Type= 6, Freq= 0, CH_0, rank 0
4067 04:40:39.428232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4068 04:40:39.428316 ==
4069 04:40:39.428381
4070 04:40:39.428474
4071 04:40:39.428532 TX Vref Scan disable
4072 04:40:39.432038 == TX Byte 0 ==
4073 04:40:39.435780 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4074 04:40:39.441770 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4075 04:40:39.441889 == TX Byte 1 ==
4076 04:40:39.445354 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4077 04:40:39.452200 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4078 04:40:39.452287 ==
4079 04:40:39.455358 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 04:40:39.458550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 04:40:39.458635 ==
4082 04:40:39.458701
4083 04:40:39.458762
4084 04:40:39.462225 TX Vref Scan disable
4085 04:40:39.465211 == TX Byte 0 ==
4086 04:40:39.468870 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4087 04:40:39.471988 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4088 04:40:39.475091 == TX Byte 1 ==
4089 04:40:39.478750 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4090 04:40:39.481717 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4091 04:40:39.481802
4092 04:40:39.481869 [DATLAT]
4093 04:40:39.485271 Freq=600, CH0 RK0
4094 04:40:39.485384
4095 04:40:39.485480 DATLAT Default: 0x9
4096 04:40:39.488303 0, 0xFFFF, sum = 0
4097 04:40:39.492093 1, 0xFFFF, sum = 0
4098 04:40:39.492208 2, 0xFFFF, sum = 0
4099 04:40:39.495276 3, 0xFFFF, sum = 0
4100 04:40:39.495384 4, 0xFFFF, sum = 0
4101 04:40:39.498368 5, 0xFFFF, sum = 0
4102 04:40:39.498484 6, 0xFFFF, sum = 0
4103 04:40:39.502131 7, 0xFFFF, sum = 0
4104 04:40:39.502249 8, 0x0, sum = 1
4105 04:40:39.502347 9, 0x0, sum = 2
4106 04:40:39.505221 10, 0x0, sum = 3
4107 04:40:39.505329 11, 0x0, sum = 4
4108 04:40:39.508379 best_step = 9
4109 04:40:39.508495
4110 04:40:39.508599 ==
4111 04:40:39.512068 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 04:40:39.515072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 04:40:39.515192 ==
4114 04:40:39.518596 RX Vref Scan: 1
4115 04:40:39.518705
4116 04:40:39.518800 RX Vref 0 -> 0, step: 1
4117 04:40:39.518890
4118 04:40:39.521791 RX Delay -163 -> 252, step: 8
4119 04:40:39.521868
4120 04:40:39.524947 Set Vref, RX VrefLevel [Byte0]: 56
4121 04:40:39.528261 [Byte1]: 50
4122 04:40:39.532270
4123 04:40:39.532363 Final RX Vref Byte 0 = 56 to rank0
4124 04:40:39.535874 Final RX Vref Byte 1 = 50 to rank0
4125 04:40:39.539210 Final RX Vref Byte 0 = 56 to rank1
4126 04:40:39.542230 Final RX Vref Byte 1 = 50 to rank1==
4127 04:40:39.545501 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 04:40:39.552219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 04:40:39.552368 ==
4130 04:40:39.552469 DQS Delay:
4131 04:40:39.552563 DQS0 = 0, DQS1 = 0
4132 04:40:39.555783 DQM Delay:
4133 04:40:39.555869 DQM0 = 52, DQM1 = 47
4134 04:40:39.558949 DQ Delay:
4135 04:40:39.562246 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4136 04:40:39.565832 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4137 04:40:39.568904 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4138 04:40:39.572069 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =52
4139 04:40:39.572156
4140 04:40:39.572222
4141 04:40:39.579028 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e61, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4142 04:40:39.582110 CH0 RK0: MR19=808, MR18=6E61
4143 04:40:39.589131 CH0_RK0: MR19=0x808, MR18=0x6E61, DQSOSC=389, MR23=63, INC=173, DEC=115
4144 04:40:39.589223
4145 04:40:39.591990 ----->DramcWriteLeveling(PI) begin...
4146 04:40:39.592083 ==
4147 04:40:39.595697 Dram Type= 6, Freq= 0, CH_0, rank 1
4148 04:40:39.598789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 04:40:39.598870 ==
4150 04:40:39.601943 Write leveling (Byte 0): 33 => 33
4151 04:40:39.605636 Write leveling (Byte 1): 32 => 32
4152 04:40:39.608854 DramcWriteLeveling(PI) end<-----
4153 04:40:39.608937
4154 04:40:39.609004 ==
4155 04:40:39.611868 Dram Type= 6, Freq= 0, CH_0, rank 1
4156 04:40:39.615631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 04:40:39.615719 ==
4158 04:40:39.618833 [Gating] SW mode calibration
4159 04:40:39.625387 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4160 04:40:39.632343 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4161 04:40:39.635278 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 04:40:39.641726 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4163 04:40:39.645112 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4164 04:40:39.648766 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
4165 04:40:39.652327 0 9 16 | B1->B0 | 2f2f 2a2a | 1 0 | (0 0) (0 0)
4166 04:40:39.658760 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 04:40:39.661773 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 04:40:39.665619 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 04:40:39.672088 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 04:40:39.675425 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 04:40:39.678299 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 04:40:39.685536 0 10 12 | B1->B0 | 2626 2828 | 0 0 | (0 0) (0 0)
4173 04:40:39.688734 0 10 16 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
4174 04:40:39.691696 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 04:40:39.698403 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 04:40:39.701766 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 04:40:39.705531 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 04:40:39.711956 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 04:40:39.715057 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4180 04:40:39.718175 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 04:40:39.725054 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4182 04:40:39.728261 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 04:40:39.732045 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 04:40:39.738257 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 04:40:39.741920 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 04:40:39.745029 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 04:40:39.752204 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 04:40:39.755309 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 04:40:39.758373 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 04:40:39.761652 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 04:40:39.768480 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 04:40:39.771603 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 04:40:39.778337 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 04:40:39.781316 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 04:40:39.784910 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 04:40:39.788439 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4197 04:40:39.794821 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4198 04:40:39.798174 Total UI for P1: 0, mck2ui 16
4199 04:40:39.801228 best dqsien dly found for B1: ( 0, 13, 12)
4200 04:40:39.804924 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 04:40:39.808492 Total UI for P1: 0, mck2ui 16
4202 04:40:39.811357 best dqsien dly found for B0: ( 0, 13, 16)
4203 04:40:39.815278 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4204 04:40:39.818300 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4205 04:40:39.818386
4206 04:40:39.821505 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4207 04:40:39.825208 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4208 04:40:39.828318 [Gating] SW calibration Done
4209 04:40:39.828395 ==
4210 04:40:39.831403 Dram Type= 6, Freq= 0, CH_0, rank 1
4211 04:40:39.838357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4212 04:40:39.838443 ==
4213 04:40:39.838510 RX Vref Scan: 0
4214 04:40:39.838572
4215 04:40:39.841417 RX Vref 0 -> 0, step: 1
4216 04:40:39.841503
4217 04:40:39.845114 RX Delay -230 -> 252, step: 16
4218 04:40:39.848123 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4219 04:40:39.851869 iDelay=218, Bit 1, Center 57 (-86 ~ 201) 288
4220 04:40:39.854703 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4221 04:40:39.861544 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4222 04:40:39.864969 iDelay=218, Bit 4, Center 65 (-86 ~ 217) 304
4223 04:40:39.867978 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4224 04:40:39.871533 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4225 04:40:39.874667 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4226 04:40:39.881541 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4227 04:40:39.884549 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4228 04:40:39.888135 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4229 04:40:39.891229 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4230 04:40:39.897930 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4231 04:40:39.901637 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4232 04:40:39.904637 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4233 04:40:39.907963 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4234 04:40:39.908052 ==
4235 04:40:39.911450 Dram Type= 6, Freq= 0, CH_0, rank 1
4236 04:40:39.918350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 04:40:39.918443 ==
4238 04:40:39.918519 DQS Delay:
4239 04:40:39.918584 DQS0 = 0, DQS1 = 0
4240 04:40:39.921354 DQM Delay:
4241 04:40:39.921438 DQM0 = 56, DQM1 = 43
4242 04:40:39.924837 DQ Delay:
4243 04:40:39.928214 DQ0 =57, DQ1 =57, DQ2 =49, DQ3 =49
4244 04:40:39.931285 DQ4 =65, DQ5 =41, DQ6 =65, DQ7 =65
4245 04:40:39.931392 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4246 04:40:39.938048 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4247 04:40:39.938135
4248 04:40:39.938201
4249 04:40:39.938263 ==
4250 04:40:39.941135 Dram Type= 6, Freq= 0, CH_0, rank 1
4251 04:40:39.944388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4252 04:40:39.944467 ==
4253 04:40:39.944535
4254 04:40:39.944602
4255 04:40:39.947911 TX Vref Scan disable
4256 04:40:39.947997 == TX Byte 0 ==
4257 04:40:39.954899 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4258 04:40:39.958233 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4259 04:40:39.958319 == TX Byte 1 ==
4260 04:40:39.964489 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4261 04:40:39.967934 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4262 04:40:39.968022 ==
4263 04:40:39.971085 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 04:40:39.974746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 04:40:39.974853 ==
4266 04:40:39.974922
4267 04:40:39.974984
4268 04:40:39.977875 TX Vref Scan disable
4269 04:40:39.980999 == TX Byte 0 ==
4270 04:40:39.984762 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4271 04:40:39.987826 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4272 04:40:39.990994 == TX Byte 1 ==
4273 04:40:39.994758 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4274 04:40:39.997874 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4275 04:40:40.000869
4276 04:40:40.000966 [DATLAT]
4277 04:40:40.001033 Freq=600, CH0 RK1
4278 04:40:40.001096
4279 04:40:40.004657 DATLAT Default: 0x9
4280 04:40:40.004741 0, 0xFFFF, sum = 0
4281 04:40:40.007699 1, 0xFFFF, sum = 0
4282 04:40:40.007813 2, 0xFFFF, sum = 0
4283 04:40:40.011416 3, 0xFFFF, sum = 0
4284 04:40:40.011502 4, 0xFFFF, sum = 0
4285 04:40:40.014645 5, 0xFFFF, sum = 0
4286 04:40:40.017607 6, 0xFFFF, sum = 0
4287 04:40:40.017700 7, 0xFFFF, sum = 0
4288 04:40:40.017770 8, 0x0, sum = 1
4289 04:40:40.021357 9, 0x0, sum = 2
4290 04:40:40.021444 10, 0x0, sum = 3
4291 04:40:40.024439 11, 0x0, sum = 4
4292 04:40:40.024525 best_step = 9
4293 04:40:40.024592
4294 04:40:40.024653 ==
4295 04:40:40.027783 Dram Type= 6, Freq= 0, CH_0, rank 1
4296 04:40:40.034472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4297 04:40:40.034558 ==
4298 04:40:40.034625 RX Vref Scan: 0
4299 04:40:40.034687
4300 04:40:40.037416 RX Vref 0 -> 0, step: 1
4301 04:40:40.037500
4302 04:40:40.041068 RX Delay -163 -> 252, step: 8
4303 04:40:40.044247 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4304 04:40:40.050982 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4305 04:40:40.054068 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4306 04:40:40.057802 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4307 04:40:40.060911 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4308 04:40:40.064173 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4309 04:40:40.067622 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4310 04:40:40.074244 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4311 04:40:40.077313 iDelay=205, Bit 8, Center 40 (-99 ~ 180) 280
4312 04:40:40.080890 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4313 04:40:40.083990 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4314 04:40:40.090836 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4315 04:40:40.094078 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4316 04:40:40.097334 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4317 04:40:40.100495 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4318 04:40:40.104085 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4319 04:40:40.107165 ==
4320 04:40:40.107250 Dram Type= 6, Freq= 0, CH_0, rank 1
4321 04:40:40.113788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4322 04:40:40.113889 ==
4323 04:40:40.113957 DQS Delay:
4324 04:40:40.117003 DQS0 = 0, DQS1 = 0
4325 04:40:40.117090 DQM Delay:
4326 04:40:40.120739 DQM0 = 54, DQM1 = 47
4327 04:40:40.120833 DQ Delay:
4328 04:40:40.124005 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4329 04:40:40.127002 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =64
4330 04:40:40.130835 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40
4331 04:40:40.133998 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4332 04:40:40.134088
4333 04:40:40.134155
4334 04:40:40.140482 [DQSOSCAuto] RK1, (LSB)MR18= 0x6424, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4335 04:40:40.144086 CH0 RK1: MR19=808, MR18=6424
4336 04:40:40.150547 CH0_RK1: MR19=0x808, MR18=0x6424, DQSOSC=391, MR23=63, INC=171, DEC=114
4337 04:40:40.153591 [RxdqsGatingPostProcess] freq 600
4338 04:40:40.160340 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4339 04:40:40.160427 Pre-setting of DQS Precalculation
4340 04:40:40.167245 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4341 04:40:40.167329 ==
4342 04:40:40.170744 Dram Type= 6, Freq= 0, CH_1, rank 0
4343 04:40:40.173925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4344 04:40:40.174003 ==
4345 04:40:40.180470 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4346 04:40:40.187189 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4347 04:40:40.190333 [CA 0] Center 35 (5~66) winsize 62
4348 04:40:40.193914 [CA 1] Center 36 (5~67) winsize 63
4349 04:40:40.197097 [CA 2] Center 34 (4~65) winsize 62
4350 04:40:40.200140 [CA 3] Center 34 (4~65) winsize 62
4351 04:40:40.203257 [CA 4] Center 34 (4~65) winsize 62
4352 04:40:40.206947 [CA 5] Center 34 (3~65) winsize 63
4353 04:40:40.207059
4354 04:40:40.210010 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4355 04:40:40.210090
4356 04:40:40.213218 [CATrainingPosCal] consider 1 rank data
4357 04:40:40.217074 u2DelayCellTimex100 = 270/100 ps
4358 04:40:40.220054 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4359 04:40:40.223720 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4360 04:40:40.227026 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4361 04:40:40.230000 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4362 04:40:40.233086 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4363 04:40:40.236915 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4364 04:40:40.236994
4365 04:40:40.243633 CA PerBit enable=1, Macro0, CA PI delay=34
4366 04:40:40.243713
4367 04:40:40.243778 [CBTSetCACLKResult] CA Dly = 34
4368 04:40:40.246870 CS Dly: 6 (0~37)
4369 04:40:40.246946 ==
4370 04:40:40.250014 Dram Type= 6, Freq= 0, CH_1, rank 1
4371 04:40:40.253623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4372 04:40:40.253706 ==
4373 04:40:40.260134 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4374 04:40:40.266490 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4375 04:40:40.270152 [CA 0] Center 36 (5~67) winsize 63
4376 04:40:40.273368 [CA 1] Center 36 (5~67) winsize 63
4377 04:40:40.277012 [CA 2] Center 34 (4~65) winsize 62
4378 04:40:40.280050 [CA 3] Center 34 (4~65) winsize 62
4379 04:40:40.283479 [CA 4] Center 34 (4~65) winsize 62
4380 04:40:40.287025 [CA 5] Center 34 (3~65) winsize 63
4381 04:40:40.287132
4382 04:40:40.290011 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4383 04:40:40.290100
4384 04:40:40.293704 [CATrainingPosCal] consider 2 rank data
4385 04:40:40.296858 u2DelayCellTimex100 = 270/100 ps
4386 04:40:40.299913 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4387 04:40:40.303624 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4388 04:40:40.306602 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4389 04:40:40.309776 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4390 04:40:40.313598 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4391 04:40:40.316759 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4392 04:40:40.316845
4393 04:40:40.323403 CA PerBit enable=1, Macro0, CA PI delay=34
4394 04:40:40.323490
4395 04:40:40.323568 [CBTSetCACLKResult] CA Dly = 34
4396 04:40:40.326612 CS Dly: 6 (0~38)
4397 04:40:40.326697
4398 04:40:40.329777 ----->DramcWriteLeveling(PI) begin...
4399 04:40:40.329863 ==
4400 04:40:40.333558 Dram Type= 6, Freq= 0, CH_1, rank 0
4401 04:40:40.336852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 04:40:40.336940 ==
4403 04:40:40.339864 Write leveling (Byte 0): 29 => 29
4404 04:40:40.343062 Write leveling (Byte 1): 30 => 30
4405 04:40:40.346106 DramcWriteLeveling(PI) end<-----
4406 04:40:40.346219
4407 04:40:40.346284 ==
4408 04:40:40.349891 Dram Type= 6, Freq= 0, CH_1, rank 0
4409 04:40:40.356121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4410 04:40:40.356211 ==
4411 04:40:40.356276 [Gating] SW mode calibration
4412 04:40:40.366117 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4413 04:40:40.369850 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4414 04:40:40.373005 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4415 04:40:40.379667 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4416 04:40:40.383194 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4417 04:40:40.385998 0 9 12 | B1->B0 | 3131 2f2f | 0 1 | (0 0) (1 0)
4418 04:40:40.392613 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 04:40:40.396316 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 04:40:40.399498 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 04:40:40.406212 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 04:40:40.409658 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 04:40:40.412701 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 04:40:40.419550 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 04:40:40.422806 0 10 12 | B1->B0 | 3535 3d3d | 0 0 | (0 0) (0 0)
4426 04:40:40.425835 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 04:40:40.432568 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 04:40:40.436429 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 04:40:40.439512 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 04:40:40.445874 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 04:40:40.449591 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 04:40:40.452358 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 04:40:40.459736 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4434 04:40:40.462758 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4435 04:40:40.465907 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 04:40:40.472493 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 04:40:40.476227 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 04:40:40.479301 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 04:40:40.482351 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 04:40:40.489384 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 04:40:40.492357 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 04:40:40.495999 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 04:40:40.502806 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 04:40:40.505897 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 04:40:40.509396 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 04:40:40.515988 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 04:40:40.519074 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 04:40:40.522448 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4449 04:40:40.528845 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4450 04:40:40.532176 Total UI for P1: 0, mck2ui 16
4451 04:40:40.535635 best dqsien dly found for B1: ( 0, 13, 10)
4452 04:40:40.539237 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 04:40:40.542367 Total UI for P1: 0, mck2ui 16
4454 04:40:40.545560 best dqsien dly found for B0: ( 0, 13, 10)
4455 04:40:40.548824 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4456 04:40:40.552524 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4457 04:40:40.552610
4458 04:40:40.555504 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4459 04:40:40.559175 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4460 04:40:40.562446 [Gating] SW calibration Done
4461 04:40:40.562532 ==
4462 04:40:40.565464 Dram Type= 6, Freq= 0, CH_1, rank 0
4463 04:40:40.572373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4464 04:40:40.572505 ==
4465 04:40:40.572606 RX Vref Scan: 0
4466 04:40:40.572700
4467 04:40:40.575890 RX Vref 0 -> 0, step: 1
4468 04:40:40.576018
4469 04:40:40.578816 RX Delay -230 -> 252, step: 16
4470 04:40:40.581996 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4471 04:40:40.585700 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4472 04:40:40.588810 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4473 04:40:40.595665 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4474 04:40:40.598856 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4475 04:40:40.602046 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4476 04:40:40.605575 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4477 04:40:40.608492 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4478 04:40:40.615663 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4479 04:40:40.618842 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4480 04:40:40.621971 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4481 04:40:40.625222 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4482 04:40:40.631780 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4483 04:40:40.634784 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4484 04:40:40.638560 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4485 04:40:40.641728 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4486 04:40:40.641813 ==
4487 04:40:40.645208 Dram Type= 6, Freq= 0, CH_1, rank 0
4488 04:40:40.651364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4489 04:40:40.651487 ==
4490 04:40:40.651606 DQS Delay:
4491 04:40:40.654535 DQS0 = 0, DQS1 = 0
4492 04:40:40.654622 DQM Delay:
4493 04:40:40.658495 DQM0 = 52, DQM1 = 51
4494 04:40:40.658581 DQ Delay:
4495 04:40:40.661143 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4496 04:40:40.664420 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4497 04:40:40.668318 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =49
4498 04:40:40.671123 DQ12 =65, DQ13 =57, DQ14 =49, DQ15 =65
4499 04:40:40.671212
4500 04:40:40.671278
4501 04:40:40.671340 ==
4502 04:40:40.674366 Dram Type= 6, Freq= 0, CH_1, rank 0
4503 04:40:40.678224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4504 04:40:40.678311 ==
4505 04:40:40.678426
4506 04:40:40.678520
4507 04:40:40.681070 TX Vref Scan disable
4508 04:40:40.684234 == TX Byte 0 ==
4509 04:40:40.687990 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4510 04:40:40.691036 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4511 04:40:40.694154 == TX Byte 1 ==
4512 04:40:40.697982 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4513 04:40:40.701009 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4514 04:40:40.701122 ==
4515 04:40:40.704145 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 04:40:40.711045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 04:40:40.711163 ==
4518 04:40:40.711277
4519 04:40:40.711372
4520 04:40:40.711469 TX Vref Scan disable
4521 04:40:40.715337 == TX Byte 0 ==
4522 04:40:40.718446 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4523 04:40:40.725321 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4524 04:40:40.725411 == TX Byte 1 ==
4525 04:40:40.728384 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4526 04:40:40.735222 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4527 04:40:40.735309
4528 04:40:40.735376 [DATLAT]
4529 04:40:40.735439 Freq=600, CH1 RK0
4530 04:40:40.735499
4531 04:40:40.738384 DATLAT Default: 0x9
4532 04:40:40.738469 0, 0xFFFF, sum = 0
4533 04:40:40.741804 1, 0xFFFF, sum = 0
4534 04:40:40.741890 2, 0xFFFF, sum = 0
4535 04:40:40.745031 3, 0xFFFF, sum = 0
4536 04:40:40.745118 4, 0xFFFF, sum = 0
4537 04:40:40.748137 5, 0xFFFF, sum = 0
4538 04:40:40.751907 6, 0xFFFF, sum = 0
4539 04:40:40.751995 7, 0xFFFF, sum = 0
4540 04:40:40.752063 8, 0x0, sum = 1
4541 04:40:40.754952 9, 0x0, sum = 2
4542 04:40:40.755039 10, 0x0, sum = 3
4543 04:40:40.758158 11, 0x0, sum = 4
4544 04:40:40.758245 best_step = 9
4545 04:40:40.758311
4546 04:40:40.758377 ==
4547 04:40:40.761813 Dram Type= 6, Freq= 0, CH_1, rank 0
4548 04:40:40.768533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4549 04:40:40.768622 ==
4550 04:40:40.768698 RX Vref Scan: 1
4551 04:40:40.768761
4552 04:40:40.771828 RX Vref 0 -> 0, step: 1
4553 04:40:40.771915
4554 04:40:40.775093 RX Delay -163 -> 252, step: 8
4555 04:40:40.775203
4556 04:40:40.778105 Set Vref, RX VrefLevel [Byte0]: 54
4557 04:40:40.781540 [Byte1]: 55
4558 04:40:40.781652
4559 04:40:40.784667 Final RX Vref Byte 0 = 54 to rank0
4560 04:40:40.788510 Final RX Vref Byte 1 = 55 to rank0
4561 04:40:40.791427 Final RX Vref Byte 0 = 54 to rank1
4562 04:40:40.794980 Final RX Vref Byte 1 = 55 to rank1==
4563 04:40:40.798096 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 04:40:40.801323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 04:40:40.801433 ==
4566 04:40:40.804839 DQS Delay:
4567 04:40:40.804943 DQS0 = 0, DQS1 = 0
4568 04:40:40.805045 DQM Delay:
4569 04:40:40.807972 DQM0 = 48, DQM1 = 45
4570 04:40:40.808051 DQ Delay:
4571 04:40:40.811752 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4572 04:40:40.814792 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4573 04:40:40.818440 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4574 04:40:40.821541 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4575 04:40:40.821626
4576 04:40:40.821693
4577 04:40:40.831330 [DQSOSCAuto] RK0, (LSB)MR18= 0x456a, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4578 04:40:40.831420 CH1 RK0: MR19=808, MR18=456A
4579 04:40:40.838182 CH1_RK0: MR19=0x808, MR18=0x456A, DQSOSC=389, MR23=63, INC=173, DEC=115
4580 04:40:40.838270
4581 04:40:40.841239 ----->DramcWriteLeveling(PI) begin...
4582 04:40:40.844975 ==
4583 04:40:40.845062 Dram Type= 6, Freq= 0, CH_1, rank 1
4584 04:40:40.851758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 04:40:40.851860 ==
4586 04:40:40.854909 Write leveling (Byte 0): 30 => 30
4587 04:40:40.858030 Write leveling (Byte 1): 31 => 31
4588 04:40:40.861753 DramcWriteLeveling(PI) end<-----
4589 04:40:40.861844
4590 04:40:40.861911 ==
4591 04:40:40.864853 Dram Type= 6, Freq= 0, CH_1, rank 1
4592 04:40:40.867993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 04:40:40.868081 ==
4594 04:40:40.871300 [Gating] SW mode calibration
4595 04:40:40.878053 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4596 04:40:40.881622 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4597 04:40:40.888055 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4598 04:40:40.891176 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4599 04:40:40.894588 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4600 04:40:40.900924 0 9 12 | B1->B0 | 2e2e 2f2f | 1 0 | (1 0) (0 0)
4601 04:40:40.904384 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 04:40:40.908058 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 04:40:40.914686 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 04:40:40.918018 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 04:40:40.920939 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 04:40:40.927755 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 04:40:40.930883 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4608 04:40:40.934451 0 10 12 | B1->B0 | 3939 3535 | 1 0 | (0 0) (0 0)
4609 04:40:40.940914 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 04:40:40.944566 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 04:40:40.947722 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 04:40:40.954442 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 04:40:40.957572 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 04:40:40.960738 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 04:40:40.967429 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 04:40:40.971309 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4617 04:40:40.974422 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 04:40:40.981261 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 04:40:40.984425 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 04:40:40.987438 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 04:40:40.994260 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 04:40:40.997516 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 04:40:41.001118 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 04:40:41.007683 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 04:40:41.010681 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 04:40:41.013748 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 04:40:41.020583 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 04:40:41.024008 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 04:40:41.027481 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 04:40:41.034096 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 04:40:41.037386 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4632 04:40:41.040674 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4633 04:40:41.043616 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 04:40:41.047383 Total UI for P1: 0, mck2ui 16
4635 04:40:41.050504 best dqsien dly found for B0: ( 0, 13, 14)
4636 04:40:41.054122 Total UI for P1: 0, mck2ui 16
4637 04:40:41.057101 best dqsien dly found for B1: ( 0, 13, 10)
4638 04:40:41.060846 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4639 04:40:41.067031 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4640 04:40:41.067117
4641 04:40:41.070313 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4642 04:40:41.073981 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4643 04:40:41.077086 [Gating] SW calibration Done
4644 04:40:41.077172 ==
4645 04:40:41.080401 Dram Type= 6, Freq= 0, CH_1, rank 1
4646 04:40:41.083937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 04:40:41.084024 ==
4648 04:40:41.087189 RX Vref Scan: 0
4649 04:40:41.087300
4650 04:40:41.087395 RX Vref 0 -> 0, step: 1
4651 04:40:41.087486
4652 04:40:41.090282 RX Delay -230 -> 252, step: 16
4653 04:40:41.093812 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4654 04:40:41.100271 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4655 04:40:41.103763 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4656 04:40:41.107003 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4657 04:40:41.110107 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4658 04:40:41.113704 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4659 04:40:41.120332 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4660 04:40:41.123703 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4661 04:40:41.126891 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4662 04:40:41.129990 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4663 04:40:41.137376 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4664 04:40:41.140467 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4665 04:40:41.143458 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4666 04:40:41.147219 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4667 04:40:41.153668 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4668 04:40:41.156846 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4669 04:40:41.156935 ==
4670 04:40:41.160498 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 04:40:41.163427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 04:40:41.163508 ==
4673 04:40:41.163585 DQS Delay:
4674 04:40:41.166945 DQS0 = 0, DQS1 = 0
4675 04:40:41.167016 DQM Delay:
4676 04:40:41.170070 DQM0 = 50, DQM1 = 48
4677 04:40:41.170173 DQ Delay:
4678 04:40:41.173285 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4679 04:40:41.176479 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4680 04:40:41.180293 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4681 04:40:41.183427 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4682 04:40:41.183536
4683 04:40:41.183624
4684 04:40:41.183686 ==
4685 04:40:41.186543 Dram Type= 6, Freq= 0, CH_1, rank 1
4686 04:40:41.192940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4687 04:40:41.193051 ==
4688 04:40:41.193157
4689 04:40:41.193247
4690 04:40:41.193334 TX Vref Scan disable
4691 04:40:41.196481 == TX Byte 0 ==
4692 04:40:41.200032 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4693 04:40:41.203239 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4694 04:40:41.207017 == TX Byte 1 ==
4695 04:40:41.210235 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4696 04:40:41.213350 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4697 04:40:41.216937 ==
4698 04:40:41.219958 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 04:40:41.223637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 04:40:41.223722 ==
4701 04:40:41.223787
4702 04:40:41.223847
4703 04:40:41.226671 TX Vref Scan disable
4704 04:40:41.226767 == TX Byte 0 ==
4705 04:40:41.233512 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4706 04:40:41.236733 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4707 04:40:41.236853 == TX Byte 1 ==
4708 04:40:41.243483 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4709 04:40:41.246402 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4710 04:40:41.246507
4711 04:40:41.246629 [DATLAT]
4712 04:40:41.250311 Freq=600, CH1 RK1
4713 04:40:41.250418
4714 04:40:41.250481 DATLAT Default: 0x9
4715 04:40:41.253455 0, 0xFFFF, sum = 0
4716 04:40:41.253604 1, 0xFFFF, sum = 0
4717 04:40:41.256566 2, 0xFFFF, sum = 0
4718 04:40:41.256642 3, 0xFFFF, sum = 0
4719 04:40:41.259747 4, 0xFFFF, sum = 0
4720 04:40:41.263349 5, 0xFFFF, sum = 0
4721 04:40:41.263470 6, 0xFFFF, sum = 0
4722 04:40:41.266412 7, 0xFFFF, sum = 0
4723 04:40:41.266517 8, 0x0, sum = 1
4724 04:40:41.266610 9, 0x0, sum = 2
4725 04:40:41.269748 10, 0x0, sum = 3
4726 04:40:41.269852 11, 0x0, sum = 4
4727 04:40:41.273206 best_step = 9
4728 04:40:41.273316
4729 04:40:41.273411 ==
4730 04:40:41.276761 Dram Type= 6, Freq= 0, CH_1, rank 1
4731 04:40:41.279854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4732 04:40:41.279935 ==
4733 04:40:41.283248 RX Vref Scan: 0
4734 04:40:41.283352
4735 04:40:41.283444 RX Vref 0 -> 0, step: 1
4736 04:40:41.283554
4737 04:40:41.286370 RX Delay -163 -> 252, step: 8
4738 04:40:41.293699 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4739 04:40:41.296983 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4740 04:40:41.299999 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4741 04:40:41.303721 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4742 04:40:41.309954 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4743 04:40:41.313798 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4744 04:40:41.316930 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4745 04:40:41.320153 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4746 04:40:41.323283 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4747 04:40:41.330194 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4748 04:40:41.333175 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4749 04:40:41.336848 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4750 04:40:41.340391 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4751 04:40:41.343317 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4752 04:40:41.350359 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4753 04:40:41.353293 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4754 04:40:41.353381 ==
4755 04:40:41.356871 Dram Type= 6, Freq= 0, CH_1, rank 1
4756 04:40:41.359977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4757 04:40:41.360063 ==
4758 04:40:41.363026 DQS Delay:
4759 04:40:41.363138 DQS0 = 0, DQS1 = 0
4760 04:40:41.363234 DQM Delay:
4761 04:40:41.366913 DQM0 = 48, DQM1 = 46
4762 04:40:41.366998 DQ Delay:
4763 04:40:41.370050 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4764 04:40:41.373306 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4765 04:40:41.376858 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4766 04:40:41.379942 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4767 04:40:41.380027
4768 04:40:41.380092
4769 04:40:41.390009 [DQSOSCAuto] RK1, (LSB)MR18= 0x6820, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 390 ps
4770 04:40:41.390125 CH1 RK1: MR19=808, MR18=6820
4771 04:40:41.396559 CH1_RK1: MR19=0x808, MR18=0x6820, DQSOSC=390, MR23=63, INC=172, DEC=114
4772 04:40:41.399990 [RxdqsGatingPostProcess] freq 600
4773 04:40:41.406250 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4774 04:40:41.409663 Pre-setting of DQS Precalculation
4775 04:40:41.413463 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4776 04:40:41.419538 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4777 04:40:41.429525 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4778 04:40:41.429614
4779 04:40:41.429681
4780 04:40:41.433220 [Calibration Summary] 1200 Mbps
4781 04:40:41.433305 CH 0, Rank 0
4782 04:40:41.436323 SW Impedance : PASS
4783 04:40:41.436408 DUTY Scan : NO K
4784 04:40:41.439467 ZQ Calibration : PASS
4785 04:40:41.443164 Jitter Meter : NO K
4786 04:40:41.443297 CBT Training : PASS
4787 04:40:41.446164 Write leveling : PASS
4788 04:40:41.446246 RX DQS gating : PASS
4789 04:40:41.449860 RX DQ/DQS(RDDQC) : PASS
4790 04:40:41.452786 TX DQ/DQS : PASS
4791 04:40:41.452869 RX DATLAT : PASS
4792 04:40:41.456155 RX DQ/DQS(Engine): PASS
4793 04:40:41.459721 TX OE : NO K
4794 04:40:41.459856 All Pass.
4795 04:40:41.459939
4796 04:40:41.460021 CH 0, Rank 1
4797 04:40:41.462566 SW Impedance : PASS
4798 04:40:41.466138 DUTY Scan : NO K
4799 04:40:41.466220 ZQ Calibration : PASS
4800 04:40:41.469354 Jitter Meter : NO K
4801 04:40:41.472513 CBT Training : PASS
4802 04:40:41.472601 Write leveling : PASS
4803 04:40:41.476331 RX DQS gating : PASS
4804 04:40:41.479476 RX DQ/DQS(RDDQC) : PASS
4805 04:40:41.479590 TX DQ/DQS : PASS
4806 04:40:41.482812 RX DATLAT : PASS
4807 04:40:41.485770 RX DQ/DQS(Engine): PASS
4808 04:40:41.485881 TX OE : NO K
4809 04:40:41.489554 All Pass.
4810 04:40:41.489640
4811 04:40:41.489724 CH 1, Rank 0
4812 04:40:41.492832 SW Impedance : PASS
4813 04:40:41.492913 DUTY Scan : NO K
4814 04:40:41.495886 ZQ Calibration : PASS
4815 04:40:41.499059 Jitter Meter : NO K
4816 04:40:41.499133 CBT Training : PASS
4817 04:40:41.502763 Write leveling : PASS
4818 04:40:41.502840 RX DQS gating : PASS
4819 04:40:41.505745 RX DQ/DQS(RDDQC) : PASS
4820 04:40:41.509265 TX DQ/DQS : PASS
4821 04:40:41.509372 RX DATLAT : PASS
4822 04:40:41.512457 RX DQ/DQS(Engine): PASS
4823 04:40:41.515871 TX OE : NO K
4824 04:40:41.515975 All Pass.
4825 04:40:41.516078
4826 04:40:41.516210 CH 1, Rank 1
4827 04:40:41.519275 SW Impedance : PASS
4828 04:40:41.522247 DUTY Scan : NO K
4829 04:40:41.522349 ZQ Calibration : PASS
4830 04:40:41.525640 Jitter Meter : NO K
4831 04:40:41.529007 CBT Training : PASS
4832 04:40:41.529090 Write leveling : PASS
4833 04:40:41.532163 RX DQS gating : PASS
4834 04:40:41.535668 RX DQ/DQS(RDDQC) : PASS
4835 04:40:41.535756 TX DQ/DQS : PASS
4836 04:40:41.539514 RX DATLAT : PASS
4837 04:40:41.542663 RX DQ/DQS(Engine): PASS
4838 04:40:41.542746 TX OE : NO K
4839 04:40:41.545813 All Pass.
4840 04:40:41.545897
4841 04:40:41.545963 DramC Write-DBI off
4842 04:40:41.549107 PER_BANK_REFRESH: Hybrid Mode
4843 04:40:41.549211 TX_TRACKING: ON
4844 04:40:41.558876 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4845 04:40:41.562371 [FAST_K] Save calibration result to emmc
4846 04:40:41.566006 dramc_set_vcore_voltage set vcore to 662500
4847 04:40:41.569400 Read voltage for 933, 3
4848 04:40:41.569492 Vio18 = 0
4849 04:40:41.572360 Vcore = 662500
4850 04:40:41.572449 Vdram = 0
4851 04:40:41.572516 Vddq = 0
4852 04:40:41.572578 Vmddr = 0
4853 04:40:41.578761 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4854 04:40:41.585865 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4855 04:40:41.585968 MEM_TYPE=3, freq_sel=17
4856 04:40:41.588877 sv_algorithm_assistance_LP4_1600
4857 04:40:41.592155 ============ PULL DRAM RESETB DOWN ============
4858 04:40:41.599056 ========== PULL DRAM RESETB DOWN end =========
4859 04:40:41.602299 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4860 04:40:41.605283 ===================================
4861 04:40:41.608541 LPDDR4 DRAM CONFIGURATION
4862 04:40:41.612085 ===================================
4863 04:40:41.612172 EX_ROW_EN[0] = 0x0
4864 04:40:41.615305 EX_ROW_EN[1] = 0x0
4865 04:40:41.615416 LP4Y_EN = 0x0
4866 04:40:41.618482 WORK_FSP = 0x0
4867 04:40:41.618567 WL = 0x3
4868 04:40:41.622365 RL = 0x3
4869 04:40:41.625443 BL = 0x2
4870 04:40:41.625529 RPST = 0x0
4871 04:40:41.629167 RD_PRE = 0x0
4872 04:40:41.629253 WR_PRE = 0x1
4873 04:40:41.632253 WR_PST = 0x0
4874 04:40:41.632337 DBI_WR = 0x0
4875 04:40:41.635769 DBI_RD = 0x0
4876 04:40:41.635854 OTF = 0x1
4877 04:40:41.638632 ===================================
4878 04:40:41.641995 ===================================
4879 04:40:41.642081 ANA top config
4880 04:40:41.645706 ===================================
4881 04:40:41.648873 DLL_ASYNC_EN = 0
4882 04:40:41.652278 ALL_SLAVE_EN = 1
4883 04:40:41.655482 NEW_RANK_MODE = 1
4884 04:40:41.658655 DLL_IDLE_MODE = 1
4885 04:40:41.658746 LP45_APHY_COMB_EN = 1
4886 04:40:41.662080 TX_ODT_DIS = 1
4887 04:40:41.665484 NEW_8X_MODE = 1
4888 04:40:41.668594 ===================================
4889 04:40:41.672317 ===================================
4890 04:40:41.675800 data_rate = 1866
4891 04:40:41.678719 CKR = 1
4892 04:40:41.678802 DQ_P2S_RATIO = 8
4893 04:40:41.682350 ===================================
4894 04:40:41.685419 CA_P2S_RATIO = 8
4895 04:40:41.688547 DQ_CA_OPEN = 0
4896 04:40:41.692290 DQ_SEMI_OPEN = 0
4897 04:40:41.695385 CA_SEMI_OPEN = 0
4898 04:40:41.698512 CA_FULL_RATE = 0
4899 04:40:41.698596 DQ_CKDIV4_EN = 1
4900 04:40:41.702233 CA_CKDIV4_EN = 1
4901 04:40:41.705412 CA_PREDIV_EN = 0
4902 04:40:41.708536 PH8_DLY = 0
4903 04:40:41.712328 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4904 04:40:41.712407 DQ_AAMCK_DIV = 4
4905 04:40:41.715382 CA_AAMCK_DIV = 4
4906 04:40:41.719098 CA_ADMCK_DIV = 4
4907 04:40:41.722365 DQ_TRACK_CA_EN = 0
4908 04:40:41.725471 CA_PICK = 933
4909 04:40:41.728679 CA_MCKIO = 933
4910 04:40:41.732349 MCKIO_SEMI = 0
4911 04:40:41.732433 PLL_FREQ = 3732
4912 04:40:41.735482 DQ_UI_PI_RATIO = 32
4913 04:40:41.738638 CA_UI_PI_RATIO = 0
4914 04:40:41.742394 ===================================
4915 04:40:41.745499 ===================================
4916 04:40:41.749133 memory_type:LPDDR4
4917 04:40:41.749242 GP_NUM : 10
4918 04:40:41.752209 SRAM_EN : 1
4919 04:40:41.755209 MD32_EN : 0
4920 04:40:41.758699 ===================================
4921 04:40:41.758785 [ANA_INIT] >>>>>>>>>>>>>>
4922 04:40:41.762126 <<<<<< [CONFIGURE PHASE]: ANA_TX
4923 04:40:41.765116 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4924 04:40:41.768628 ===================================
4925 04:40:41.772066 data_rate = 1866,PCW = 0X8f00
4926 04:40:41.775423 ===================================
4927 04:40:41.778678 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4928 04:40:41.785253 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4929 04:40:41.788722 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4930 04:40:41.795410 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4931 04:40:41.798512 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4932 04:40:41.802085 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4933 04:40:41.805250 [ANA_INIT] flow start
4934 04:40:41.805336 [ANA_INIT] PLL >>>>>>>>
4935 04:40:41.808422 [ANA_INIT] PLL <<<<<<<<
4936 04:40:41.812201 [ANA_INIT] MIDPI >>>>>>>>
4937 04:40:41.812284 [ANA_INIT] MIDPI <<<<<<<<
4938 04:40:41.815329 [ANA_INIT] DLL >>>>>>>>
4939 04:40:41.818359 [ANA_INIT] flow end
4940 04:40:41.822036 ============ LP4 DIFF to SE enter ============
4941 04:40:41.825176 ============ LP4 DIFF to SE exit ============
4942 04:40:41.828334 [ANA_INIT] <<<<<<<<<<<<<
4943 04:40:41.831467 [Flow] Enable top DCM control >>>>>
4944 04:40:41.835217 [Flow] Enable top DCM control <<<<<
4945 04:40:41.838372 Enable DLL master slave shuffle
4946 04:40:41.841584 ==============================================================
4947 04:40:41.844820 Gating Mode config
4948 04:40:41.851879 ==============================================================
4949 04:40:41.851991 Config description:
4950 04:40:41.861289 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4951 04:40:41.867984 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4952 04:40:41.871493 SELPH_MODE 0: By rank 1: By Phase
4953 04:40:41.878394 ==============================================================
4954 04:40:41.881516 GAT_TRACK_EN = 1
4955 04:40:41.884559 RX_GATING_MODE = 2
4956 04:40:41.888224 RX_GATING_TRACK_MODE = 2
4957 04:40:41.891349 SELPH_MODE = 1
4958 04:40:41.894439 PICG_EARLY_EN = 1
4959 04:40:41.898051 VALID_LAT_VALUE = 1
4960 04:40:41.901554 ==============================================================
4961 04:40:41.904882 Enter into Gating configuration >>>>
4962 04:40:41.908237 Exit from Gating configuration <<<<
4963 04:40:41.911369 Enter into DVFS_PRE_config >>>>>
4964 04:40:41.921514 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4965 04:40:41.924766 Exit from DVFS_PRE_config <<<<<
4966 04:40:41.927780 Enter into PICG configuration >>>>
4967 04:40:41.931542 Exit from PICG configuration <<<<
4968 04:40:41.934828 [RX_INPUT] configuration >>>>>
4969 04:40:41.937947 [RX_INPUT] configuration <<<<<
4970 04:40:41.944813 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4971 04:40:41.948143 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4972 04:40:41.954882 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4973 04:40:41.961472 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4974 04:40:41.967712 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4975 04:40:41.974391 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4976 04:40:41.978086 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4977 04:40:41.981010 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4978 04:40:41.984503 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4979 04:40:41.991319 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4980 04:40:41.994526 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4981 04:40:41.998327 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4982 04:40:42.001551 ===================================
4983 04:40:42.004859 LPDDR4 DRAM CONFIGURATION
4984 04:40:42.007919 ===================================
4985 04:40:42.008035 EX_ROW_EN[0] = 0x0
4986 04:40:42.011083 EX_ROW_EN[1] = 0x0
4987 04:40:42.011209 LP4Y_EN = 0x0
4988 04:40:42.014752 WORK_FSP = 0x0
4989 04:40:42.014844 WL = 0x3
4990 04:40:42.018138 RL = 0x3
4991 04:40:42.021001 BL = 0x2
4992 04:40:42.021078 RPST = 0x0
4993 04:40:42.024623 RD_PRE = 0x0
4994 04:40:42.024727 WR_PRE = 0x1
4995 04:40:42.027675 WR_PST = 0x0
4996 04:40:42.027769 DBI_WR = 0x0
4997 04:40:42.031166 DBI_RD = 0x0
4998 04:40:42.031268 OTF = 0x1
4999 04:40:42.034542 ===================================
5000 04:40:42.037595 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5001 04:40:42.044389 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5002 04:40:42.047540 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5003 04:40:42.051274 ===================================
5004 04:40:42.054417 LPDDR4 DRAM CONFIGURATION
5005 04:40:42.057611 ===================================
5006 04:40:42.057686 EX_ROW_EN[0] = 0x10
5007 04:40:42.060803 EX_ROW_EN[1] = 0x0
5008 04:40:42.060912 LP4Y_EN = 0x0
5009 04:40:42.064383 WORK_FSP = 0x0
5010 04:40:42.064472 WL = 0x3
5011 04:40:42.067317 RL = 0x3
5012 04:40:42.067417 BL = 0x2
5013 04:40:42.071174 RPST = 0x0
5014 04:40:42.074051 RD_PRE = 0x0
5015 04:40:42.074156 WR_PRE = 0x1
5016 04:40:42.077817 WR_PST = 0x0
5017 04:40:42.077895 DBI_WR = 0x0
5018 04:40:42.080977 DBI_RD = 0x0
5019 04:40:42.081054 OTF = 0x1
5020 04:40:42.084029 ===================================
5021 04:40:42.090755 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5022 04:40:42.094270 nWR fixed to 30
5023 04:40:42.097814 [ModeRegInit_LP4] CH0 RK0
5024 04:40:42.097900 [ModeRegInit_LP4] CH0 RK1
5025 04:40:42.101326 [ModeRegInit_LP4] CH1 RK0
5026 04:40:42.104342 [ModeRegInit_LP4] CH1 RK1
5027 04:40:42.104472 match AC timing 9
5028 04:40:42.111093 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5029 04:40:42.114774 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5030 04:40:42.118050 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5031 04:40:42.124771 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5032 04:40:42.128319 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5033 04:40:42.128403 ==
5034 04:40:42.131339 Dram Type= 6, Freq= 0, CH_0, rank 0
5035 04:40:42.134527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5036 04:40:42.134604 ==
5037 04:40:42.141371 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5038 04:40:42.148227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5039 04:40:42.150946 [CA 0] Center 37 (6~68) winsize 63
5040 04:40:42.154577 [CA 1] Center 37 (7~68) winsize 62
5041 04:40:42.157652 [CA 2] Center 34 (4~65) winsize 62
5042 04:40:42.161332 [CA 3] Center 34 (3~65) winsize 63
5043 04:40:42.164195 [CA 4] Center 33 (3~64) winsize 62
5044 04:40:42.167835 [CA 5] Center 32 (2~62) winsize 61
5045 04:40:42.167916
5046 04:40:42.170961 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5047 04:40:42.171055
5048 04:40:42.174180 [CATrainingPosCal] consider 1 rank data
5049 04:40:42.177825 u2DelayCellTimex100 = 270/100 ps
5050 04:40:42.180894 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5051 04:40:42.184598 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5052 04:40:42.187644 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5053 04:40:42.190844 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5054 04:40:42.194537 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5055 04:40:42.197677 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5056 04:40:42.200624
5057 04:40:42.204306 CA PerBit enable=1, Macro0, CA PI delay=32
5058 04:40:42.204383
5059 04:40:42.207875 [CBTSetCACLKResult] CA Dly = 32
5060 04:40:42.207995 CS Dly: 5 (0~36)
5061 04:40:42.208057 ==
5062 04:40:42.210958 Dram Type= 6, Freq= 0, CH_0, rank 1
5063 04:40:42.214006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5064 04:40:42.217630 ==
5065 04:40:42.220808 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5066 04:40:42.227592 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5067 04:40:42.230705 [CA 0] Center 37 (6~68) winsize 63
5068 04:40:42.233787 [CA 1] Center 37 (7~68) winsize 62
5069 04:40:42.237344 [CA 2] Center 34 (4~65) winsize 62
5070 04:40:42.240518 [CA 3] Center 34 (4~65) winsize 62
5071 04:40:42.244380 [CA 4] Center 33 (3~63) winsize 61
5072 04:40:42.247466 [CA 5] Center 32 (2~62) winsize 61
5073 04:40:42.247610
5074 04:40:42.250547 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5075 04:40:42.250679
5076 04:40:42.254212 [CATrainingPosCal] consider 2 rank data
5077 04:40:42.257357 u2DelayCellTimex100 = 270/100 ps
5078 04:40:42.260422 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5079 04:40:42.264200 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5080 04:40:42.267121 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5081 04:40:42.270408 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5082 04:40:42.277017 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5083 04:40:42.280253 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5084 04:40:42.280361
5085 04:40:42.283833 CA PerBit enable=1, Macro0, CA PI delay=32
5086 04:40:42.283911
5087 04:40:42.287173 [CBTSetCACLKResult] CA Dly = 32
5088 04:40:42.287282 CS Dly: 5 (0~37)
5089 04:40:42.287375
5090 04:40:42.290417 ----->DramcWriteLeveling(PI) begin...
5091 04:40:42.290524 ==
5092 04:40:42.293465 Dram Type= 6, Freq= 0, CH_0, rank 0
5093 04:40:42.300520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 04:40:42.300607 ==
5095 04:40:42.303730 Write leveling (Byte 0): 33 => 33
5096 04:40:42.303827 Write leveling (Byte 1): 30 => 30
5097 04:40:42.306805 DramcWriteLeveling(PI) end<-----
5098 04:40:42.306889
5099 04:40:42.310473 ==
5100 04:40:42.313570 Dram Type= 6, Freq= 0, CH_0, rank 0
5101 04:40:42.317280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5102 04:40:42.317369 ==
5103 04:40:42.320491 [Gating] SW mode calibration
5104 04:40:42.326848 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5105 04:40:42.329914 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5106 04:40:42.336660 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5107 04:40:42.340335 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 04:40:42.343361 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 04:40:42.350278 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 04:40:42.353381 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 04:40:42.356664 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 04:40:42.363448 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5113 04:40:42.366613 0 14 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
5114 04:40:42.370349 0 15 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
5115 04:40:42.376584 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 04:40:42.380379 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 04:40:42.383397 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 04:40:42.389983 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 04:40:42.393455 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 04:40:42.396784 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5121 04:40:42.403587 0 15 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
5122 04:40:42.406421 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5123 04:40:42.410066 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 04:40:42.413275 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 04:40:42.419872 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 04:40:42.423036 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 04:40:42.426846 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 04:40:42.433388 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 04:40:42.436574 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5130 04:40:42.439837 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5131 04:40:42.446699 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 04:40:42.449639 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 04:40:42.453461 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 04:40:42.459700 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 04:40:42.462945 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 04:40:42.466688 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 04:40:42.472929 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 04:40:42.476845 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 04:40:42.479821 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 04:40:42.486558 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 04:40:42.489575 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 04:40:42.493531 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 04:40:42.499743 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 04:40:42.503319 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5145 04:40:42.506595 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5146 04:40:42.509471 Total UI for P1: 0, mck2ui 16
5147 04:40:42.512945 best dqsien dly found for B0: ( 1, 2, 24)
5148 04:40:42.519772 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5149 04:40:42.522629 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 04:40:42.526315 Total UI for P1: 0, mck2ui 16
5151 04:40:42.529901 best dqsien dly found for B1: ( 1, 2, 30)
5152 04:40:42.532880 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5153 04:40:42.536077 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5154 04:40:42.536182
5155 04:40:42.539701 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5156 04:40:42.543166 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5157 04:40:42.546343 [Gating] SW calibration Done
5158 04:40:42.546448 ==
5159 04:40:42.549556 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 04:40:42.552590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 04:40:42.552703 ==
5162 04:40:42.556115 RX Vref Scan: 0
5163 04:40:42.556200
5164 04:40:42.559367 RX Vref 0 -> 0, step: 1
5165 04:40:42.559465
5166 04:40:42.559592 RX Delay -80 -> 252, step: 8
5167 04:40:42.566345 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5168 04:40:42.569326 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5169 04:40:42.572454 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5170 04:40:42.576331 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5171 04:40:42.579511 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5172 04:40:42.585786 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5173 04:40:42.589256 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5174 04:40:42.592382 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5175 04:40:42.595940 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5176 04:40:42.599059 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5177 04:40:42.602227 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5178 04:40:42.608983 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5179 04:40:42.612646 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5180 04:40:42.615671 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5181 04:40:42.619125 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5182 04:40:42.622605 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5183 04:40:42.622687 ==
5184 04:40:42.625532 Dram Type= 6, Freq= 0, CH_0, rank 0
5185 04:40:42.632759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5186 04:40:42.632874 ==
5187 04:40:42.632968 DQS Delay:
5188 04:40:42.635746 DQS0 = 0, DQS1 = 0
5189 04:40:42.635846 DQM Delay:
5190 04:40:42.635914 DQM0 = 104, DQM1 = 96
5191 04:40:42.639065 DQ Delay:
5192 04:40:42.642517 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5193 04:40:42.645580 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5194 04:40:42.649429 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5195 04:40:42.652479 DQ12 =99, DQ13 =103, DQ14 =107, DQ15 =99
5196 04:40:42.652588
5197 04:40:42.652680
5198 04:40:42.652773 ==
5199 04:40:42.655715 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 04:40:42.658769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 04:40:42.658861 ==
5202 04:40:42.658954
5203 04:40:42.659041
5204 04:40:42.662329 TX Vref Scan disable
5205 04:40:42.665498 == TX Byte 0 ==
5206 04:40:42.669220 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5207 04:40:42.672336 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5208 04:40:42.675503 == TX Byte 1 ==
5209 04:40:42.679305 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5210 04:40:42.682347 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5211 04:40:42.682458 ==
5212 04:40:42.685391 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 04:40:42.689189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 04:40:42.692288 ==
5215 04:40:42.692386
5216 04:40:42.692488
5217 04:40:42.692576 TX Vref Scan disable
5218 04:40:42.695952 == TX Byte 0 ==
5219 04:40:42.699530 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5220 04:40:42.706024 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5221 04:40:42.706134 == TX Byte 1 ==
5222 04:40:42.709264 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5223 04:40:42.716128 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5224 04:40:42.716233
5225 04:40:42.716330 [DATLAT]
5226 04:40:42.716419 Freq=933, CH0 RK0
5227 04:40:42.716509
5228 04:40:42.719260 DATLAT Default: 0xd
5229 04:40:42.719363 0, 0xFFFF, sum = 0
5230 04:40:42.722265 1, 0xFFFF, sum = 0
5231 04:40:42.722365 2, 0xFFFF, sum = 0
5232 04:40:42.725648 3, 0xFFFF, sum = 0
5233 04:40:42.729026 4, 0xFFFF, sum = 0
5234 04:40:42.729136 5, 0xFFFF, sum = 0
5235 04:40:42.732402 6, 0xFFFF, sum = 0
5236 04:40:42.732506 7, 0xFFFF, sum = 0
5237 04:40:42.735850 8, 0xFFFF, sum = 0
5238 04:40:42.735952 9, 0xFFFF, sum = 0
5239 04:40:42.738806 10, 0x0, sum = 1
5240 04:40:42.738910 11, 0x0, sum = 2
5241 04:40:42.742541 12, 0x0, sum = 3
5242 04:40:42.742640 13, 0x0, sum = 4
5243 04:40:42.742713 best_step = 11
5244 04:40:42.742773
5245 04:40:42.745738 ==
5246 04:40:42.749183 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 04:40:42.751976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 04:40:42.752057 ==
5249 04:40:42.752120 RX Vref Scan: 1
5250 04:40:42.752179
5251 04:40:42.755431 RX Vref 0 -> 0, step: 1
5252 04:40:42.755548
5253 04:40:42.759080 RX Delay -45 -> 252, step: 4
5254 04:40:42.759162
5255 04:40:42.762240 Set Vref, RX VrefLevel [Byte0]: 56
5256 04:40:42.765228 [Byte1]: 50
5257 04:40:42.765310
5258 04:40:42.768831 Final RX Vref Byte 0 = 56 to rank0
5259 04:40:42.771948 Final RX Vref Byte 1 = 50 to rank0
5260 04:40:42.775071 Final RX Vref Byte 0 = 56 to rank1
5261 04:40:42.778711 Final RX Vref Byte 1 = 50 to rank1==
5262 04:40:42.781908 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 04:40:42.785152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 04:40:42.788897 ==
5265 04:40:42.789008 DQS Delay:
5266 04:40:42.789077 DQS0 = 0, DQS1 = 0
5267 04:40:42.791971 DQM Delay:
5268 04:40:42.792042 DQM0 = 104, DQM1 = 95
5269 04:40:42.795071 DQ Delay:
5270 04:40:42.798729 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =104
5271 04:40:42.801698 DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =110
5272 04:40:42.805206 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =90
5273 04:40:42.808252 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =102
5274 04:40:42.808392
5275 04:40:42.808529
5276 04:40:42.815048 [DQSOSCAuto] RK0, (LSB)MR18= 0x332b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5277 04:40:42.818790 CH0 RK0: MR19=505, MR18=332B
5278 04:40:42.824906 CH0_RK0: MR19=0x505, MR18=0x332B, DQSOSC=405, MR23=63, INC=66, DEC=44
5279 04:40:42.825018
5280 04:40:42.828619 ----->DramcWriteLeveling(PI) begin...
5281 04:40:42.828733 ==
5282 04:40:42.831755 Dram Type= 6, Freq= 0, CH_0, rank 1
5283 04:40:42.835319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 04:40:42.835422 ==
5285 04:40:42.838670 Write leveling (Byte 0): 32 => 32
5286 04:40:42.841939 Write leveling (Byte 1): 29 => 29
5287 04:40:42.844988 DramcWriteLeveling(PI) end<-----
5288 04:40:42.845127
5289 04:40:42.845222 ==
5290 04:40:42.848377 Dram Type= 6, Freq= 0, CH_0, rank 1
5291 04:40:42.851776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 04:40:42.855210 ==
5293 04:40:42.855324 [Gating] SW mode calibration
5294 04:40:42.861858 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5295 04:40:42.868206 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5296 04:40:42.871704 0 14 0 | B1->B0 | 3434 3131 | 1 1 | (0 0) (0 0)
5297 04:40:42.878352 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 04:40:42.881513 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 04:40:42.885217 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 04:40:42.891474 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 04:40:42.895260 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 04:40:42.898423 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5303 04:40:42.905230 0 14 28 | B1->B0 | 2929 2c2c | 0 1 | (0 0) (1 0)
5304 04:40:42.908282 0 15 0 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
5305 04:40:42.911320 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 04:40:42.918565 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 04:40:42.921577 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 04:40:42.924729 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 04:40:42.931753 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 04:40:42.934786 0 15 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5311 04:40:42.937954 0 15 28 | B1->B0 | 3b3b 3939 | 0 1 | (0 0) (0 0)
5312 04:40:42.944704 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5313 04:40:42.948229 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 04:40:42.951747 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 04:40:42.954806 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 04:40:42.961614 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 04:40:42.964436 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 04:40:42.968000 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5319 04:40:42.974782 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5320 04:40:42.978365 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 04:40:42.981499 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 04:40:42.987890 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 04:40:42.991537 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 04:40:42.994670 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 04:40:43.001719 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 04:40:43.004742 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 04:40:43.007880 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 04:40:43.014252 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 04:40:43.017914 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 04:40:43.021454 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 04:40:43.027639 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 04:40:43.031443 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 04:40:43.034644 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 04:40:43.041153 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 04:40:43.044317 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5336 04:40:43.047969 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5337 04:40:43.051098 Total UI for P1: 0, mck2ui 16
5338 04:40:43.054273 best dqsien dly found for B1: ( 1, 2, 30)
5339 04:40:43.061282 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 04:40:43.061390 Total UI for P1: 0, mck2ui 16
5341 04:40:43.064193 best dqsien dly found for B0: ( 1, 2, 30)
5342 04:40:43.071050 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5343 04:40:43.074671 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5344 04:40:43.074751
5345 04:40:43.077668 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5346 04:40:43.081274 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5347 04:40:43.084407 [Gating] SW calibration Done
5348 04:40:43.084520 ==
5349 04:40:43.088100 Dram Type= 6, Freq= 0, CH_0, rank 1
5350 04:40:43.091155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 04:40:43.091278 ==
5352 04:40:43.094226 RX Vref Scan: 0
5353 04:40:43.094335
5354 04:40:43.094463 RX Vref 0 -> 0, step: 1
5355 04:40:43.094551
5356 04:40:43.097783 RX Delay -80 -> 252, step: 8
5357 04:40:43.100624 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5358 04:40:43.107898 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5359 04:40:43.111050 iDelay=208, Bit 2, Center 107 (16 ~ 199) 184
5360 04:40:43.114214 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5361 04:40:43.117383 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5362 04:40:43.120582 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5363 04:40:43.124161 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5364 04:40:43.130975 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5365 04:40:43.134008 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5366 04:40:43.137662 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5367 04:40:43.141018 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5368 04:40:43.144199 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5369 04:40:43.147226 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5370 04:40:43.154134 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5371 04:40:43.157195 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5372 04:40:43.160852 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5373 04:40:43.160956 ==
5374 04:40:43.163679 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 04:40:43.167058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 04:40:43.170647 ==
5377 04:40:43.170760 DQS Delay:
5378 04:40:43.170853 DQS0 = 0, DQS1 = 0
5379 04:40:43.174054 DQM Delay:
5380 04:40:43.174160 DQM0 = 106, DQM1 = 94
5381 04:40:43.177192 DQ Delay:
5382 04:40:43.180307 DQ0 =107, DQ1 =107, DQ2 =107, DQ3 =103
5383 04:40:43.183767 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5384 04:40:43.186915 DQ8 =87, DQ9 =83, DQ10 =91, DQ11 =87
5385 04:40:43.190369 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =103
5386 04:40:43.190478
5387 04:40:43.190579
5388 04:40:43.190668 ==
5389 04:40:43.193461 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 04:40:43.197254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 04:40:43.197374 ==
5392 04:40:43.197518
5393 04:40:43.197615
5394 04:40:43.200396 TX Vref Scan disable
5395 04:40:43.203592 == TX Byte 0 ==
5396 04:40:43.206743 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5397 04:40:43.210082 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5398 04:40:43.213660 == TX Byte 1 ==
5399 04:40:43.216862 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5400 04:40:43.220474 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5401 04:40:43.220582 ==
5402 04:40:43.223512 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 04:40:43.226709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 04:40:43.230292 ==
5405 04:40:43.230398
5406 04:40:43.230490
5407 04:40:43.230578 TX Vref Scan disable
5408 04:40:43.233786 == TX Byte 0 ==
5409 04:40:43.237007 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5410 04:40:43.243756 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5411 04:40:43.243839 == TX Byte 1 ==
5412 04:40:43.246807 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5413 04:40:43.253576 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5414 04:40:43.253682
5415 04:40:43.253791 [DATLAT]
5416 04:40:43.253883 Freq=933, CH0 RK1
5417 04:40:43.253970
5418 04:40:43.256696 DATLAT Default: 0xb
5419 04:40:43.256767 0, 0xFFFF, sum = 0
5420 04:40:43.260474 1, 0xFFFF, sum = 0
5421 04:40:43.260546 2, 0xFFFF, sum = 0
5422 04:40:43.263679 3, 0xFFFF, sum = 0
5423 04:40:43.266719 4, 0xFFFF, sum = 0
5424 04:40:43.266817 5, 0xFFFF, sum = 0
5425 04:40:43.270445 6, 0xFFFF, sum = 0
5426 04:40:43.270517 7, 0xFFFF, sum = 0
5427 04:40:43.273392 8, 0xFFFF, sum = 0
5428 04:40:43.273499 9, 0xFFFF, sum = 0
5429 04:40:43.276770 10, 0x0, sum = 1
5430 04:40:43.276846 11, 0x0, sum = 2
5431 04:40:43.280325 12, 0x0, sum = 3
5432 04:40:43.280409 13, 0x0, sum = 4
5433 04:40:43.280476 best_step = 11
5434 04:40:43.280536
5435 04:40:43.283633 ==
5436 04:40:43.286798 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 04:40:43.289924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 04:40:43.290009 ==
5439 04:40:43.290075 RX Vref Scan: 0
5440 04:40:43.290135
5441 04:40:43.293378 RX Vref 0 -> 0, step: 1
5442 04:40:43.293461
5443 04:40:43.296428 RX Delay -53 -> 252, step: 4
5444 04:40:43.300032 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5445 04:40:43.306920 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5446 04:40:43.310041 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5447 04:40:43.313233 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5448 04:40:43.316839 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5449 04:40:43.319936 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5450 04:40:43.327158 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5451 04:40:43.330486 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5452 04:40:43.333368 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5453 04:40:43.337002 iDelay=199, Bit 9, Center 84 (-1 ~ 170) 172
5454 04:40:43.339943 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5455 04:40:43.343540 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5456 04:40:43.349885 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5457 04:40:43.353088 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5458 04:40:43.356776 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5459 04:40:43.359807 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5460 04:40:43.359912 ==
5461 04:40:43.363583 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 04:40:43.369852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 04:40:43.369941 ==
5464 04:40:43.370027 DQS Delay:
5465 04:40:43.370108 DQS0 = 0, DQS1 = 0
5466 04:40:43.373669 DQM Delay:
5467 04:40:43.373755 DQM0 = 104, DQM1 = 93
5468 04:40:43.376657 DQ Delay:
5469 04:40:43.380132 DQ0 =102, DQ1 =104, DQ2 =102, DQ3 =100
5470 04:40:43.383208 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5471 04:40:43.386913 DQ8 =86, DQ9 =84, DQ10 =94, DQ11 =86
5472 04:40:43.389721 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =102
5473 04:40:43.389807
5474 04:40:43.389891
5475 04:40:43.396804 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5476 04:40:43.399707 CH0 RK1: MR19=505, MR18=2A03
5477 04:40:43.406298 CH0_RK1: MR19=0x505, MR18=0x2A03, DQSOSC=408, MR23=63, INC=65, DEC=43
5478 04:40:43.409994 [RxdqsGatingPostProcess] freq 933
5479 04:40:43.416449 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5480 04:40:43.416535 best DQS0 dly(2T, 0.5T) = (0, 10)
5481 04:40:43.419619 best DQS1 dly(2T, 0.5T) = (0, 10)
5482 04:40:43.423345 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5483 04:40:43.426472 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5484 04:40:43.429569 best DQS0 dly(2T, 0.5T) = (0, 10)
5485 04:40:43.433291 best DQS1 dly(2T, 0.5T) = (0, 10)
5486 04:40:43.436239 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5487 04:40:43.439868 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5488 04:40:43.443233 Pre-setting of DQS Precalculation
5489 04:40:43.449730 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5490 04:40:43.449817 ==
5491 04:40:43.453021 Dram Type= 6, Freq= 0, CH_1, rank 0
5492 04:40:43.456086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 04:40:43.456175 ==
5494 04:40:43.463125 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5495 04:40:43.466197 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5496 04:40:43.469898 [CA 0] Center 36 (6~67) winsize 62
5497 04:40:43.473638 [CA 1] Center 37 (6~68) winsize 63
5498 04:40:43.476894 [CA 2] Center 34 (4~65) winsize 62
5499 04:40:43.480458 [CA 3] Center 34 (4~65) winsize 62
5500 04:40:43.483462 [CA 4] Center 34 (4~64) winsize 61
5501 04:40:43.486544 [CA 5] Center 33 (3~64) winsize 62
5502 04:40:43.486622
5503 04:40:43.490291 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5504 04:40:43.490371
5505 04:40:43.493449 [CATrainingPosCal] consider 1 rank data
5506 04:40:43.496515 u2DelayCellTimex100 = 270/100 ps
5507 04:40:43.500309 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5508 04:40:43.503388 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5509 04:40:43.509848 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5510 04:40:43.513397 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5511 04:40:43.516967 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5512 04:40:43.520013 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5513 04:40:43.520116
5514 04:40:43.523213 CA PerBit enable=1, Macro0, CA PI delay=33
5515 04:40:43.523299
5516 04:40:43.527014 [CBTSetCACLKResult] CA Dly = 33
5517 04:40:43.527098 CS Dly: 6 (0~37)
5518 04:40:43.527164 ==
5519 04:40:43.530278 Dram Type= 6, Freq= 0, CH_1, rank 1
5520 04:40:43.537237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5521 04:40:43.537321 ==
5522 04:40:43.540349 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5523 04:40:43.546728 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5524 04:40:43.550198 [CA 0] Center 36 (6~67) winsize 62
5525 04:40:43.553355 [CA 1] Center 37 (7~68) winsize 62
5526 04:40:43.557195 [CA 2] Center 35 (5~65) winsize 61
5527 04:40:43.560076 [CA 3] Center 34 (4~65) winsize 62
5528 04:40:43.563075 [CA 4] Center 34 (4~65) winsize 62
5529 04:40:43.566462 [CA 5] Center 33 (3~64) winsize 62
5530 04:40:43.566561
5531 04:40:43.569859 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5532 04:40:43.569961
5533 04:40:43.573258 [CATrainingPosCal] consider 2 rank data
5534 04:40:43.576875 u2DelayCellTimex100 = 270/100 ps
5535 04:40:43.579896 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5536 04:40:43.583015 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5537 04:40:43.589737 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5538 04:40:43.593300 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5539 04:40:43.596892 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5540 04:40:43.599908 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5541 04:40:43.599994
5542 04:40:43.603576 CA PerBit enable=1, Macro0, CA PI delay=33
5543 04:40:43.603649
5544 04:40:43.606592 [CBTSetCACLKResult] CA Dly = 33
5545 04:40:43.606663 CS Dly: 7 (0~39)
5546 04:40:43.606725
5547 04:40:43.610246 ----->DramcWriteLeveling(PI) begin...
5548 04:40:43.613269 ==
5549 04:40:43.616899 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 04:40:43.619857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 04:40:43.619979 ==
5552 04:40:43.623406 Write leveling (Byte 0): 22 => 22
5553 04:40:43.626544 Write leveling (Byte 1): 26 => 26
5554 04:40:43.629685 DramcWriteLeveling(PI) end<-----
5555 04:40:43.629772
5556 04:40:43.629859 ==
5557 04:40:43.633386 Dram Type= 6, Freq= 0, CH_1, rank 0
5558 04:40:43.636616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5559 04:40:43.636703 ==
5560 04:40:43.639771 [Gating] SW mode calibration
5561 04:40:43.646737 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5562 04:40:43.653240 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5563 04:40:43.656216 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 04:40:43.660092 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 04:40:43.666368 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 04:40:43.669411 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 04:40:43.673279 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 04:40:43.676174 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 04:40:43.683040 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5570 04:40:43.686381 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (1 0)
5571 04:40:43.689792 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 04:40:43.696360 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 04:40:43.699624 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 04:40:43.702620 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 04:40:43.710142 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 04:40:43.713008 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 04:40:43.716064 0 15 24 | B1->B0 | 2525 3636 | 0 1 | (0 0) (0 0)
5578 04:40:43.722838 0 15 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5579 04:40:43.726420 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 04:40:43.730066 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 04:40:43.736403 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 04:40:43.739972 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 04:40:43.743346 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 04:40:43.750148 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 04:40:43.753370 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5586 04:40:43.756435 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5587 04:40:43.762930 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 04:40:43.766572 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 04:40:43.769526 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 04:40:43.773378 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 04:40:43.779561 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 04:40:43.783345 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 04:40:43.786326 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 04:40:43.792968 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 04:40:43.796446 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 04:40:43.799722 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 04:40:43.806515 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 04:40:43.809885 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 04:40:43.812834 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 04:40:43.819752 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 04:40:43.822959 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5602 04:40:43.826679 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 04:40:43.829519 Total UI for P1: 0, mck2ui 16
5604 04:40:43.832938 best dqsien dly found for B0: ( 1, 2, 24)
5605 04:40:43.836565 Total UI for P1: 0, mck2ui 16
5606 04:40:43.839470 best dqsien dly found for B1: ( 1, 2, 24)
5607 04:40:43.842742 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5608 04:40:43.846516 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5609 04:40:43.846603
5610 04:40:43.852914 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5611 04:40:43.856492 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5612 04:40:43.856583 [Gating] SW calibration Done
5613 04:40:43.859606 ==
5614 04:40:43.862592 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 04:40:43.866313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 04:40:43.866401 ==
5617 04:40:43.866487 RX Vref Scan: 0
5618 04:40:43.866568
5619 04:40:43.869433 RX Vref 0 -> 0, step: 1
5620 04:40:43.869519
5621 04:40:43.872622 RX Delay -80 -> 252, step: 8
5622 04:40:43.876411 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5623 04:40:43.879573 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5624 04:40:43.882603 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5625 04:40:43.889456 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5626 04:40:43.892744 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5627 04:40:43.895916 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5628 04:40:43.899030 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5629 04:40:43.902889 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5630 04:40:43.906030 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5631 04:40:43.912476 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5632 04:40:43.915922 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5633 04:40:43.918912 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5634 04:40:43.922614 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5635 04:40:43.926136 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5636 04:40:43.932348 iDelay=208, Bit 14, Center 107 (24 ~ 191) 168
5637 04:40:43.935890 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5638 04:40:43.936027 ==
5639 04:40:43.938960 Dram Type= 6, Freq= 0, CH_1, rank 0
5640 04:40:43.942476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 04:40:43.942602 ==
5642 04:40:43.942697 DQS Delay:
5643 04:40:43.945904 DQS0 = 0, DQS1 = 0
5644 04:40:43.945984 DQM Delay:
5645 04:40:43.949197 DQM0 = 103, DQM1 = 98
5646 04:40:43.949271 DQ Delay:
5647 04:40:43.952568 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5648 04:40:43.955622 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5649 04:40:43.959300 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5650 04:40:43.962530 DQ12 =107, DQ13 =103, DQ14 =107, DQ15 =107
5651 04:40:43.962618
5652 04:40:43.962685
5653 04:40:43.962746 ==
5654 04:40:43.966225 Dram Type= 6, Freq= 0, CH_1, rank 0
5655 04:40:43.972323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5656 04:40:43.972414 ==
5657 04:40:43.972481
5658 04:40:43.972543
5659 04:40:43.972604 TX Vref Scan disable
5660 04:40:43.976175 == TX Byte 0 ==
5661 04:40:43.979194 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5662 04:40:43.986004 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5663 04:40:43.986099 == TX Byte 1 ==
5664 04:40:43.989854 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5665 04:40:43.996121 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5666 04:40:43.996210 ==
5667 04:40:43.999221 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 04:40:44.002973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 04:40:44.003088 ==
5670 04:40:44.003162
5671 04:40:44.003225
5672 04:40:44.006309 TX Vref Scan disable
5673 04:40:44.006398 == TX Byte 0 ==
5674 04:40:44.012861 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5675 04:40:44.015968 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5676 04:40:44.016054 == TX Byte 1 ==
5677 04:40:44.022643 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5678 04:40:44.026104 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5679 04:40:44.026191
5680 04:40:44.026258 [DATLAT]
5681 04:40:44.029095 Freq=933, CH1 RK0
5682 04:40:44.029181
5683 04:40:44.029248 DATLAT Default: 0xd
5684 04:40:44.032299 0, 0xFFFF, sum = 0
5685 04:40:44.032386 1, 0xFFFF, sum = 0
5686 04:40:44.036134 2, 0xFFFF, sum = 0
5687 04:40:44.039271 3, 0xFFFF, sum = 0
5688 04:40:44.039358 4, 0xFFFF, sum = 0
5689 04:40:44.042300 5, 0xFFFF, sum = 0
5690 04:40:44.042388 6, 0xFFFF, sum = 0
5691 04:40:44.045836 7, 0xFFFF, sum = 0
5692 04:40:44.045920 8, 0xFFFF, sum = 0
5693 04:40:44.049275 9, 0xFFFF, sum = 0
5694 04:40:44.049360 10, 0x0, sum = 1
5695 04:40:44.052178 11, 0x0, sum = 2
5696 04:40:44.052264 12, 0x0, sum = 3
5697 04:40:44.052332 13, 0x0, sum = 4
5698 04:40:44.055443 best_step = 11
5699 04:40:44.055575
5700 04:40:44.055679 ==
5701 04:40:44.059206 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 04:40:44.062416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 04:40:44.062522 ==
5704 04:40:44.065904 RX Vref Scan: 1
5705 04:40:44.066040
5706 04:40:44.069347 RX Vref 0 -> 0, step: 1
5707 04:40:44.069452
5708 04:40:44.069553 RX Delay -45 -> 252, step: 4
5709 04:40:44.069653
5710 04:40:44.072548 Set Vref, RX VrefLevel [Byte0]: 54
5711 04:40:44.075441 [Byte1]: 55
5712 04:40:44.080038
5713 04:40:44.080126 Final RX Vref Byte 0 = 54 to rank0
5714 04:40:44.083253 Final RX Vref Byte 1 = 55 to rank0
5715 04:40:44.086991 Final RX Vref Byte 0 = 54 to rank1
5716 04:40:44.090187 Final RX Vref Byte 1 = 55 to rank1==
5717 04:40:44.093353 Dram Type= 6, Freq= 0, CH_1, rank 0
5718 04:40:44.099750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5719 04:40:44.099840 ==
5720 04:40:44.099938 DQS Delay:
5721 04:40:44.103425 DQS0 = 0, DQS1 = 0
5722 04:40:44.103572 DQM Delay:
5723 04:40:44.103642 DQM0 = 104, DQM1 = 100
5724 04:40:44.106609 DQ Delay:
5725 04:40:44.109818 DQ0 =106, DQ1 =96, DQ2 =96, DQ3 =102
5726 04:40:44.113031 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =104
5727 04:40:44.116784 DQ8 =92, DQ9 =94, DQ10 =100, DQ11 =94
5728 04:40:44.119785 DQ12 =106, DQ13 =106, DQ14 =106, DQ15 =106
5729 04:40:44.119869
5730 04:40:44.120003
5731 04:40:44.129674 [DQSOSCAuto] RK0, (LSB)MR18= 0x172e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5732 04:40:44.129769 CH1 RK0: MR19=505, MR18=172E
5733 04:40:44.136216 CH1_RK0: MR19=0x505, MR18=0x172E, DQSOSC=407, MR23=63, INC=65, DEC=43
5734 04:40:44.136305
5735 04:40:44.139362 ----->DramcWriteLeveling(PI) begin...
5736 04:40:44.139473 ==
5737 04:40:44.143040 Dram Type= 6, Freq= 0, CH_1, rank 1
5738 04:40:44.149193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 04:40:44.149285 ==
5740 04:40:44.152779 Write leveling (Byte 0): 25 => 25
5741 04:40:44.152859 Write leveling (Byte 1): 27 => 27
5742 04:40:44.155865 DramcWriteLeveling(PI) end<-----
5743 04:40:44.155960
5744 04:40:44.158989 ==
5745 04:40:44.162651 Dram Type= 6, Freq= 0, CH_1, rank 1
5746 04:40:44.165628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 04:40:44.165718 ==
5748 04:40:44.169125 [Gating] SW mode calibration
5749 04:40:44.175565 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5750 04:40:44.178825 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5751 04:40:44.185939 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 04:40:44.189359 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 04:40:44.192355 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 04:40:44.199394 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 04:40:44.202464 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 04:40:44.205645 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 04:40:44.212468 0 14 24 | B1->B0 | 2e2e 3333 | 0 1 | (0 0) (1 0)
5758 04:40:44.215602 0 14 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 0)
5759 04:40:44.218820 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 04:40:44.225624 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 04:40:44.228773 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 04:40:44.232506 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 04:40:44.239207 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 04:40:44.242109 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 04:40:44.245562 0 15 24 | B1->B0 | 3232 2626 | 0 1 | (0 0) (0 0)
5766 04:40:44.248714 0 15 28 | B1->B0 | 4646 3d3d | 0 1 | (0 0) (0 0)
5767 04:40:44.255371 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 04:40:44.258988 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 04:40:44.262104 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 04:40:44.269136 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 04:40:44.272333 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 04:40:44.275311 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 04:40:44.282236 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5774 04:40:44.285384 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5775 04:40:44.288981 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 04:40:44.295479 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 04:40:44.298713 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 04:40:44.302068 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 04:40:44.308890 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 04:40:44.312377 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 04:40:44.315496 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 04:40:44.322578 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 04:40:44.325696 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 04:40:44.328725 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 04:40:44.335510 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 04:40:44.338567 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 04:40:44.342302 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 04:40:44.348366 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 04:40:44.351865 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5790 04:40:44.355479 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 04:40:44.358563 Total UI for P1: 0, mck2ui 16
5792 04:40:44.362045 best dqsien dly found for B0: ( 1, 2, 24)
5793 04:40:44.365752 Total UI for P1: 0, mck2ui 16
5794 04:40:44.368913 best dqsien dly found for B1: ( 1, 2, 24)
5795 04:40:44.372133 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5796 04:40:44.375229 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5797 04:40:44.375376
5798 04:40:44.378897 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5799 04:40:44.384942 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5800 04:40:44.385045 [Gating] SW calibration Done
5801 04:40:44.385128 ==
5802 04:40:44.388173 Dram Type= 6, Freq= 0, CH_1, rank 1
5803 04:40:44.395026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 04:40:44.395131 ==
5805 04:40:44.395228 RX Vref Scan: 0
5806 04:40:44.395321
5807 04:40:44.398718 RX Vref 0 -> 0, step: 1
5808 04:40:44.398822
5809 04:40:44.401706 RX Delay -80 -> 252, step: 8
5810 04:40:44.405379 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5811 04:40:44.408347 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5812 04:40:44.411621 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5813 04:40:44.415337 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5814 04:40:44.421966 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5815 04:40:44.424950 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5816 04:40:44.428754 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5817 04:40:44.431802 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5818 04:40:44.434990 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5819 04:40:44.438743 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5820 04:40:44.441793 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5821 04:40:44.448484 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5822 04:40:44.451658 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5823 04:40:44.455350 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5824 04:40:44.458252 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5825 04:40:44.465419 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5826 04:40:44.465512 ==
5827 04:40:44.468571 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 04:40:44.471588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 04:40:44.471670 ==
5830 04:40:44.471735 DQS Delay:
5831 04:40:44.475312 DQS0 = 0, DQS1 = 0
5832 04:40:44.475419 DQM Delay:
5833 04:40:44.478422 DQM0 = 103, DQM1 = 98
5834 04:40:44.478528 DQ Delay:
5835 04:40:44.482048 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =99
5836 04:40:44.485012 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5837 04:40:44.488700 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5838 04:40:44.491901 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5839 04:40:44.491988
5840 04:40:44.492055
5841 04:40:44.492117 ==
5842 04:40:44.495099 Dram Type= 6, Freq= 0, CH_1, rank 1
5843 04:40:44.498834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5844 04:40:44.498924 ==
5845 04:40:44.502033
5846 04:40:44.502121
5847 04:40:44.502209 TX Vref Scan disable
5848 04:40:44.505095 == TX Byte 0 ==
5849 04:40:44.508804 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5850 04:40:44.511943 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5851 04:40:44.515411 == TX Byte 1 ==
5852 04:40:44.518574 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5853 04:40:44.521743 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5854 04:40:44.521830 ==
5855 04:40:44.525416 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 04:40:44.531972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 04:40:44.532061 ==
5858 04:40:44.532128
5859 04:40:44.532190
5860 04:40:44.532250 TX Vref Scan disable
5861 04:40:44.535918 == TX Byte 0 ==
5862 04:40:44.539557 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5863 04:40:44.545750 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5864 04:40:44.545853 == TX Byte 1 ==
5865 04:40:44.548930 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5866 04:40:44.556209 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5867 04:40:44.556308
5868 04:40:44.556376 [DATLAT]
5869 04:40:44.556440 Freq=933, CH1 RK1
5870 04:40:44.556501
5871 04:40:44.559289 DATLAT Default: 0xb
5872 04:40:44.559374 0, 0xFFFF, sum = 0
5873 04:40:44.562318 1, 0xFFFF, sum = 0
5874 04:40:44.565975 2, 0xFFFF, sum = 0
5875 04:40:44.566067 3, 0xFFFF, sum = 0
5876 04:40:44.569043 4, 0xFFFF, sum = 0
5877 04:40:44.569129 5, 0xFFFF, sum = 0
5878 04:40:44.572183 6, 0xFFFF, sum = 0
5879 04:40:44.572269 7, 0xFFFF, sum = 0
5880 04:40:44.575480 8, 0xFFFF, sum = 0
5881 04:40:44.575617 9, 0xFFFF, sum = 0
5882 04:40:44.578931 10, 0x0, sum = 1
5883 04:40:44.579017 11, 0x0, sum = 2
5884 04:40:44.582745 12, 0x0, sum = 3
5885 04:40:44.582831 13, 0x0, sum = 4
5886 04:40:44.582935 best_step = 11
5887 04:40:44.582996
5888 04:40:44.585807 ==
5889 04:40:44.589448 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 04:40:44.592421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 04:40:44.592519 ==
5892 04:40:44.592601 RX Vref Scan: 0
5893 04:40:44.592707
5894 04:40:44.596092 RX Vref 0 -> 0, step: 1
5895 04:40:44.596190
5896 04:40:44.599347 RX Delay -45 -> 252, step: 4
5897 04:40:44.602538 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5898 04:40:44.608847 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5899 04:40:44.612844 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5900 04:40:44.615843 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5901 04:40:44.618899 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5902 04:40:44.622511 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5903 04:40:44.629360 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5904 04:40:44.632861 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5905 04:40:44.636061 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5906 04:40:44.638991 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5907 04:40:44.642546 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5908 04:40:44.646053 iDelay=203, Bit 11, Center 96 (15 ~ 178) 164
5909 04:40:44.652174 iDelay=203, Bit 12, Center 108 (23 ~ 194) 172
5910 04:40:44.655971 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5911 04:40:44.659044 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5912 04:40:44.662257 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5913 04:40:44.662370 ==
5914 04:40:44.665489 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 04:40:44.672123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 04:40:44.672234 ==
5917 04:40:44.672334 DQS Delay:
5918 04:40:44.675875 DQS0 = 0, DQS1 = 0
5919 04:40:44.675958 DQM Delay:
5920 04:40:44.676041 DQM0 = 104, DQM1 = 100
5921 04:40:44.679013 DQ Delay:
5922 04:40:44.682677 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5923 04:40:44.685492 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5924 04:40:44.689466 DQ8 =90, DQ9 =88, DQ10 =100, DQ11 =96
5925 04:40:44.692448 DQ12 =108, DQ13 =106, DQ14 =104, DQ15 =108
5926 04:40:44.692540
5927 04:40:44.692608
5928 04:40:44.699042 [DQSOSCAuto] RK1, (LSB)MR18= 0x2dff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 407 ps
5929 04:40:44.702636 CH1 RK1: MR19=504, MR18=2DFF
5930 04:40:44.708926 CH1_RK1: MR19=0x504, MR18=0x2DFF, DQSOSC=407, MR23=63, INC=65, DEC=43
5931 04:40:44.712033 [RxdqsGatingPostProcess] freq 933
5932 04:40:44.718994 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5933 04:40:44.722309 best DQS0 dly(2T, 0.5T) = (0, 10)
5934 04:40:44.725185 best DQS1 dly(2T, 0.5T) = (0, 10)
5935 04:40:44.728732 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5936 04:40:44.728819 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5937 04:40:44.732398 best DQS0 dly(2T, 0.5T) = (0, 10)
5938 04:40:44.735392 best DQS1 dly(2T, 0.5T) = (0, 10)
5939 04:40:44.739015 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5940 04:40:44.742291 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5941 04:40:44.745848 Pre-setting of DQS Precalculation
5942 04:40:44.752048 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5943 04:40:44.759256 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5944 04:40:44.765160 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5945 04:40:44.765302
5946 04:40:44.765406
5947 04:40:44.768797 [Calibration Summary] 1866 Mbps
5948 04:40:44.768944 CH 0, Rank 0
5949 04:40:44.771927 SW Impedance : PASS
5950 04:40:44.775754 DUTY Scan : NO K
5951 04:40:44.775855 ZQ Calibration : PASS
5952 04:40:44.778944 Jitter Meter : NO K
5953 04:40:44.782181 CBT Training : PASS
5954 04:40:44.782281 Write leveling : PASS
5955 04:40:44.785301 RX DQS gating : PASS
5956 04:40:44.788876 RX DQ/DQS(RDDQC) : PASS
5957 04:40:44.788985 TX DQ/DQS : PASS
5958 04:40:44.791978 RX DATLAT : PASS
5959 04:40:44.792080 RX DQ/DQS(Engine): PASS
5960 04:40:44.795504 TX OE : NO K
5961 04:40:44.795646 All Pass.
5962 04:40:44.795743
5963 04:40:44.798721 CH 0, Rank 1
5964 04:40:44.798827 SW Impedance : PASS
5965 04:40:44.802399 DUTY Scan : NO K
5966 04:40:44.805174 ZQ Calibration : PASS
5967 04:40:44.805249 Jitter Meter : NO K
5968 04:40:44.808695 CBT Training : PASS
5969 04:40:44.811927 Write leveling : PASS
5970 04:40:44.812030 RX DQS gating : PASS
5971 04:40:44.815625 RX DQ/DQS(RDDQC) : PASS
5972 04:40:44.818757 TX DQ/DQS : PASS
5973 04:40:44.818842 RX DATLAT : PASS
5974 04:40:44.821876 RX DQ/DQS(Engine): PASS
5975 04:40:44.824965 TX OE : NO K
5976 04:40:44.825040 All Pass.
5977 04:40:44.825103
5978 04:40:44.825162 CH 1, Rank 0
5979 04:40:44.828657 SW Impedance : PASS
5980 04:40:44.831808 DUTY Scan : NO K
5981 04:40:44.831892 ZQ Calibration : PASS
5982 04:40:44.835340 Jitter Meter : NO K
5983 04:40:44.838370 CBT Training : PASS
5984 04:40:44.838486 Write leveling : PASS
5985 04:40:44.841958 RX DQS gating : PASS
5986 04:40:44.842063 RX DQ/DQS(RDDQC) : PASS
5987 04:40:44.845251 TX DQ/DQS : PASS
5988 04:40:44.848189 RX DATLAT : PASS
5989 04:40:44.848297 RX DQ/DQS(Engine): PASS
5990 04:40:44.851370 TX OE : NO K
5991 04:40:44.851490 All Pass.
5992 04:40:44.851595
5993 04:40:44.855124 CH 1, Rank 1
5994 04:40:44.855238 SW Impedance : PASS
5995 04:40:44.858231 DUTY Scan : NO K
5996 04:40:44.861959 ZQ Calibration : PASS
5997 04:40:44.862072 Jitter Meter : NO K
5998 04:40:44.864861 CBT Training : PASS
5999 04:40:44.868435 Write leveling : PASS
6000 04:40:44.868520 RX DQS gating : PASS
6001 04:40:44.871364 RX DQ/DQS(RDDQC) : PASS
6002 04:40:44.874993 TX DQ/DQS : PASS
6003 04:40:44.875080 RX DATLAT : PASS
6004 04:40:44.878037 RX DQ/DQS(Engine): PASS
6005 04:40:44.881696 TX OE : NO K
6006 04:40:44.881785 All Pass.
6007 04:40:44.881853
6008 04:40:44.881916 DramC Write-DBI off
6009 04:40:44.884736 PER_BANK_REFRESH: Hybrid Mode
6010 04:40:44.887904 TX_TRACKING: ON
6011 04:40:44.895178 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6012 04:40:44.898481 [FAST_K] Save calibration result to emmc
6013 04:40:44.905010 dramc_set_vcore_voltage set vcore to 650000
6014 04:40:44.905098 Read voltage for 400, 6
6015 04:40:44.908357 Vio18 = 0
6016 04:40:44.908454 Vcore = 650000
6017 04:40:44.908522 Vdram = 0
6018 04:40:44.911405 Vddq = 0
6019 04:40:44.911491 Vmddr = 0
6020 04:40:44.914870 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6021 04:40:44.921182 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6022 04:40:44.924912 MEM_TYPE=3, freq_sel=20
6023 04:40:44.925001 sv_algorithm_assistance_LP4_800
6024 04:40:44.931302 ============ PULL DRAM RESETB DOWN ============
6025 04:40:44.935013 ========== PULL DRAM RESETB DOWN end =========
6026 04:40:44.938057 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6027 04:40:44.941084 ===================================
6028 04:40:44.944717 LPDDR4 DRAM CONFIGURATION
6029 04:40:44.947767 ===================================
6030 04:40:44.951432 EX_ROW_EN[0] = 0x0
6031 04:40:44.951526 EX_ROW_EN[1] = 0x0
6032 04:40:44.954478 LP4Y_EN = 0x0
6033 04:40:44.954604 WORK_FSP = 0x0
6034 04:40:44.958117 WL = 0x2
6035 04:40:44.958242 RL = 0x2
6036 04:40:44.961269 BL = 0x2
6037 04:40:44.961385 RPST = 0x0
6038 04:40:44.964462 RD_PRE = 0x0
6039 04:40:44.964547 WR_PRE = 0x1
6040 04:40:44.968093 WR_PST = 0x0
6041 04:40:44.968206 DBI_WR = 0x0
6042 04:40:44.971319 DBI_RD = 0x0
6043 04:40:44.971422 OTF = 0x1
6044 04:40:44.974991 ===================================
6045 04:40:44.977807 ===================================
6046 04:40:44.981588 ANA top config
6047 04:40:44.984693 ===================================
6048 04:40:44.987679 DLL_ASYNC_EN = 0
6049 04:40:44.987776 ALL_SLAVE_EN = 1
6050 04:40:44.991491 NEW_RANK_MODE = 1
6051 04:40:44.994553 DLL_IDLE_MODE = 1
6052 04:40:44.998225 LP45_APHY_COMB_EN = 1
6053 04:40:44.998353 TX_ODT_DIS = 1
6054 04:40:45.001263 NEW_8X_MODE = 1
6055 04:40:45.004932 ===================================
6056 04:40:45.008113 ===================================
6057 04:40:45.011059 data_rate = 800
6058 04:40:45.014341 CKR = 1
6059 04:40:45.017907 DQ_P2S_RATIO = 4
6060 04:40:45.021255 ===================================
6061 04:40:45.024888 CA_P2S_RATIO = 4
6062 04:40:45.024978 DQ_CA_OPEN = 0
6063 04:40:45.028251 DQ_SEMI_OPEN = 1
6064 04:40:45.031219 CA_SEMI_OPEN = 1
6065 04:40:45.034922 CA_FULL_RATE = 0
6066 04:40:45.038063 DQ_CKDIV4_EN = 0
6067 04:40:45.041141 CA_CKDIV4_EN = 1
6068 04:40:45.041258 CA_PREDIV_EN = 0
6069 04:40:45.044959 PH8_DLY = 0
6070 04:40:45.047985 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6071 04:40:45.051491 DQ_AAMCK_DIV = 0
6072 04:40:45.054310 CA_AAMCK_DIV = 0
6073 04:40:45.057752 CA_ADMCK_DIV = 4
6074 04:40:45.057865 DQ_TRACK_CA_EN = 0
6075 04:40:45.061484 CA_PICK = 800
6076 04:40:45.064458 CA_MCKIO = 400
6077 04:40:45.068157 MCKIO_SEMI = 400
6078 04:40:45.071311 PLL_FREQ = 3016
6079 04:40:45.074468 DQ_UI_PI_RATIO = 32
6080 04:40:45.078285 CA_UI_PI_RATIO = 32
6081 04:40:45.081425 ===================================
6082 04:40:45.084452 ===================================
6083 04:40:45.084566 memory_type:LPDDR4
6084 04:40:45.088251 GP_NUM : 10
6085 04:40:45.091325 SRAM_EN : 1
6086 04:40:45.091440 MD32_EN : 0
6087 04:40:45.094430 ===================================
6088 04:40:45.097970 [ANA_INIT] >>>>>>>>>>>>>>
6089 04:40:45.101050 <<<<<< [CONFIGURE PHASE]: ANA_TX
6090 04:40:45.104618 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6091 04:40:45.108004 ===================================
6092 04:40:45.111608 data_rate = 800,PCW = 0X7400
6093 04:40:45.111700 ===================================
6094 04:40:45.117765 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6095 04:40:45.121316 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6096 04:40:45.134758 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6097 04:40:45.138197 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6098 04:40:45.141243 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6099 04:40:45.144346 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6100 04:40:45.147441 [ANA_INIT] flow start
6101 04:40:45.147556 [ANA_INIT] PLL >>>>>>>>
6102 04:40:45.151222 [ANA_INIT] PLL <<<<<<<<
6103 04:40:45.154341 [ANA_INIT] MIDPI >>>>>>>>
6104 04:40:45.157901 [ANA_INIT] MIDPI <<<<<<<<
6105 04:40:45.158012 [ANA_INIT] DLL >>>>>>>>
6106 04:40:45.160831 [ANA_INIT] flow end
6107 04:40:45.164376 ============ LP4 DIFF to SE enter ============
6108 04:40:45.167940 ============ LP4 DIFF to SE exit ============
6109 04:40:45.171085 [ANA_INIT] <<<<<<<<<<<<<
6110 04:40:45.174703 [Flow] Enable top DCM control >>>>>
6111 04:40:45.177793 [Flow] Enable top DCM control <<<<<
6112 04:40:45.180900 Enable DLL master slave shuffle
6113 04:40:45.184570 ==============================================================
6114 04:40:45.187513 Gating Mode config
6115 04:40:45.194438 ==============================================================
6116 04:40:45.194527 Config description:
6117 04:40:45.204282 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6118 04:40:45.210926 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6119 04:40:45.217777 SELPH_MODE 0: By rank 1: By Phase
6120 04:40:45.221010 ==============================================================
6121 04:40:45.224250 GAT_TRACK_EN = 0
6122 04:40:45.227980 RX_GATING_MODE = 2
6123 04:40:45.230999 RX_GATING_TRACK_MODE = 2
6124 04:40:45.234250 SELPH_MODE = 1
6125 04:40:45.237971 PICG_EARLY_EN = 1
6126 04:40:45.240990 VALID_LAT_VALUE = 1
6127 04:40:45.244351 ==============================================================
6128 04:40:45.247416 Enter into Gating configuration >>>>
6129 04:40:45.251269 Exit from Gating configuration <<<<
6130 04:40:45.254441 Enter into DVFS_PRE_config >>>>>
6131 04:40:45.267459 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6132 04:40:45.267608 Exit from DVFS_PRE_config <<<<<
6133 04:40:45.271060 Enter into PICG configuration >>>>
6134 04:40:45.274254 Exit from PICG configuration <<<<
6135 04:40:45.277846 [RX_INPUT] configuration >>>>>
6136 04:40:45.281429 [RX_INPUT] configuration <<<<<
6137 04:40:45.287397 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6138 04:40:45.291343 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6139 04:40:45.297451 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6140 04:40:45.304207 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6141 04:40:45.310798 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6142 04:40:45.317552 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6143 04:40:45.320679 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6144 04:40:45.324411 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6145 04:40:45.327499 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6146 04:40:45.333878 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6147 04:40:45.337637 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6148 04:40:45.340696 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6149 04:40:45.344048 ===================================
6150 04:40:45.347702 LPDDR4 DRAM CONFIGURATION
6151 04:40:45.350714 ===================================
6152 04:40:45.350799 EX_ROW_EN[0] = 0x0
6153 04:40:45.354085 EX_ROW_EN[1] = 0x0
6154 04:40:45.357879 LP4Y_EN = 0x0
6155 04:40:45.357966 WORK_FSP = 0x0
6156 04:40:45.360946 WL = 0x2
6157 04:40:45.361030 RL = 0x2
6158 04:40:45.364075 BL = 0x2
6159 04:40:45.364159 RPST = 0x0
6160 04:40:45.367856 RD_PRE = 0x0
6161 04:40:45.367942 WR_PRE = 0x1
6162 04:40:45.371091 WR_PST = 0x0
6163 04:40:45.371173 DBI_WR = 0x0
6164 04:40:45.374349 DBI_RD = 0x0
6165 04:40:45.374475 OTF = 0x1
6166 04:40:45.377469 ===================================
6167 04:40:45.381375 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6168 04:40:45.387430 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6169 04:40:45.391085 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6170 04:40:45.394551 ===================================
6171 04:40:45.397469 LPDDR4 DRAM CONFIGURATION
6172 04:40:45.400950 ===================================
6173 04:40:45.401035 EX_ROW_EN[0] = 0x10
6174 04:40:45.404135 EX_ROW_EN[1] = 0x0
6175 04:40:45.404219 LP4Y_EN = 0x0
6176 04:40:45.407484 WORK_FSP = 0x0
6177 04:40:45.407598 WL = 0x2
6178 04:40:45.410618 RL = 0x2
6179 04:40:45.410741 BL = 0x2
6180 04:40:45.414204 RPST = 0x0
6181 04:40:45.417205 RD_PRE = 0x0
6182 04:40:45.417290 WR_PRE = 0x1
6183 04:40:45.420592 WR_PST = 0x0
6184 04:40:45.420677 DBI_WR = 0x0
6185 04:40:45.423782 DBI_RD = 0x0
6186 04:40:45.423898 OTF = 0x1
6187 04:40:45.427489 ===================================
6188 04:40:45.433696 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6189 04:40:45.437521 nWR fixed to 30
6190 04:40:45.441304 [ModeRegInit_LP4] CH0 RK0
6191 04:40:45.441390 [ModeRegInit_LP4] CH0 RK1
6192 04:40:45.444496 [ModeRegInit_LP4] CH1 RK0
6193 04:40:45.447467 [ModeRegInit_LP4] CH1 RK1
6194 04:40:45.447605 match AC timing 19
6195 04:40:45.454627 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6196 04:40:45.457722 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6197 04:40:45.461248 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6198 04:40:45.467495 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6199 04:40:45.471509 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6200 04:40:45.471619 ==
6201 04:40:45.474322 Dram Type= 6, Freq= 0, CH_0, rank 0
6202 04:40:45.477379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6203 04:40:45.477469 ==
6204 04:40:45.484210 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6205 04:40:45.490716 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6206 04:40:45.494367 [CA 0] Center 36 (8~64) winsize 57
6207 04:40:45.497482 [CA 1] Center 36 (8~64) winsize 57
6208 04:40:45.500552 [CA 2] Center 36 (8~64) winsize 57
6209 04:40:45.504341 [CA 3] Center 36 (8~64) winsize 57
6210 04:40:45.504429 [CA 4] Center 36 (8~64) winsize 57
6211 04:40:45.507250 [CA 5] Center 36 (8~64) winsize 57
6212 04:40:45.510320
6213 04:40:45.513889 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6214 04:40:45.513973
6215 04:40:45.516934 [CATrainingPosCal] consider 1 rank data
6216 04:40:45.520569 u2DelayCellTimex100 = 270/100 ps
6217 04:40:45.523430 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 04:40:45.527061 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 04:40:45.530626 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 04:40:45.533769 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 04:40:45.537107 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 04:40:45.540147 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 04:40:45.540255
6224 04:40:45.543986 CA PerBit enable=1, Macro0, CA PI delay=36
6225 04:40:45.544081
6226 04:40:45.547180 [CBTSetCACLKResult] CA Dly = 36
6227 04:40:45.550259 CS Dly: 1 (0~32)
6228 04:40:45.550361 ==
6229 04:40:45.553410 Dram Type= 6, Freq= 0, CH_0, rank 1
6230 04:40:45.556941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6231 04:40:45.557061 ==
6232 04:40:45.563629 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6233 04:40:45.570066 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6234 04:40:45.573259 [CA 0] Center 36 (8~64) winsize 57
6235 04:40:45.573368 [CA 1] Center 36 (8~64) winsize 57
6236 04:40:45.576991 [CA 2] Center 36 (8~64) winsize 57
6237 04:40:45.580131 [CA 3] Center 36 (8~64) winsize 57
6238 04:40:45.583656 [CA 4] Center 36 (8~64) winsize 57
6239 04:40:45.586711 [CA 5] Center 36 (8~64) winsize 57
6240 04:40:45.586790
6241 04:40:45.589882 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6242 04:40:45.589965
6243 04:40:45.593638 [CATrainingPosCal] consider 2 rank data
6244 04:40:45.596886 u2DelayCellTimex100 = 270/100 ps
6245 04:40:45.600429 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 04:40:45.603467 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 04:40:45.610191 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 04:40:45.613604 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 04:40:45.616754 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 04:40:45.619988 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 04:40:45.620101
6252 04:40:45.623337 CA PerBit enable=1, Macro0, CA PI delay=36
6253 04:40:45.623451
6254 04:40:45.626864 [CBTSetCACLKResult] CA Dly = 36
6255 04:40:45.626955 CS Dly: 1 (0~32)
6256 04:40:45.627060
6257 04:40:45.630031 ----->DramcWriteLeveling(PI) begin...
6258 04:40:45.633594 ==
6259 04:40:45.636567 Dram Type= 6, Freq= 0, CH_0, rank 0
6260 04:40:45.640342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 04:40:45.640450 ==
6262 04:40:45.643246 Write leveling (Byte 0): 40 => 8
6263 04:40:45.647064 Write leveling (Byte 1): 40 => 8
6264 04:40:45.647171 DramcWriteLeveling(PI) end<-----
6265 04:40:45.650152
6266 04:40:45.650270 ==
6267 04:40:45.653434 Dram Type= 6, Freq= 0, CH_0, rank 0
6268 04:40:45.657020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6269 04:40:45.657155 ==
6270 04:40:45.660221 [Gating] SW mode calibration
6271 04:40:45.666731 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6272 04:40:45.670283 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6273 04:40:45.676688 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6274 04:40:45.680152 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6275 04:40:45.683391 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 04:40:45.690232 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 04:40:45.693386 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 04:40:45.696537 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 04:40:45.703692 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 04:40:45.706788 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 04:40:45.709911 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6282 04:40:45.713565 Total UI for P1: 0, mck2ui 16
6283 04:40:45.716666 best dqsien dly found for B0: ( 0, 14, 24)
6284 04:40:45.720271 Total UI for P1: 0, mck2ui 16
6285 04:40:45.723426 best dqsien dly found for B1: ( 0, 14, 24)
6286 04:40:45.726918 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6287 04:40:45.729915 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6288 04:40:45.730016
6289 04:40:45.737067 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6290 04:40:45.740170 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6291 04:40:45.740245 [Gating] SW calibration Done
6292 04:40:45.743253 ==
6293 04:40:45.743369 Dram Type= 6, Freq= 0, CH_0, rank 0
6294 04:40:45.750005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 04:40:45.750120 ==
6296 04:40:45.750213 RX Vref Scan: 0
6297 04:40:45.750301
6298 04:40:45.753770 RX Vref 0 -> 0, step: 1
6299 04:40:45.753879
6300 04:40:45.756809 RX Delay -410 -> 252, step: 16
6301 04:40:45.759966 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6302 04:40:45.763706 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6303 04:40:45.769965 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6304 04:40:45.773559 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6305 04:40:45.776918 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6306 04:40:45.780074 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6307 04:40:45.786560 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6308 04:40:45.790121 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6309 04:40:45.793687 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6310 04:40:45.796846 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6311 04:40:45.803489 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6312 04:40:45.806622 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6313 04:40:45.810249 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6314 04:40:45.813457 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6315 04:40:45.820310 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6316 04:40:45.823327 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6317 04:40:45.823411 ==
6318 04:40:45.827016 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 04:40:45.830132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 04:40:45.830218 ==
6321 04:40:45.833322 DQS Delay:
6322 04:40:45.833406 DQS0 = 27, DQS1 = 35
6323 04:40:45.836943 DQM Delay:
6324 04:40:45.837027 DQM0 = 9, DQM1 = 11
6325 04:40:45.837092 DQ Delay:
6326 04:40:45.839914 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6327 04:40:45.843708 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6328 04:40:45.846591 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6329 04:40:45.850222 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6330 04:40:45.850297
6331 04:40:45.850369
6332 04:40:45.850432 ==
6333 04:40:45.853115 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 04:40:45.856933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 04:40:45.860028 ==
6336 04:40:45.860114
6337 04:40:45.860178
6338 04:40:45.860238 TX Vref Scan disable
6339 04:40:45.863277 == TX Byte 0 ==
6340 04:40:45.866480 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 04:40:45.870308 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 04:40:45.873205 == TX Byte 1 ==
6343 04:40:45.876336 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6344 04:40:45.879928 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6345 04:40:45.880044 ==
6346 04:40:45.882855 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 04:40:45.889632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 04:40:45.889726 ==
6349 04:40:45.889792
6350 04:40:45.889855
6351 04:40:45.889916 TX Vref Scan disable
6352 04:40:45.893365 == TX Byte 0 ==
6353 04:40:45.896708 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 04:40:45.899532 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 04:40:45.902683 == TX Byte 1 ==
6356 04:40:45.906517 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6357 04:40:45.909606 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6358 04:40:45.909681
6359 04:40:45.913244 [DATLAT]
6360 04:40:45.913322 Freq=400, CH0 RK0
6361 04:40:45.913424
6362 04:40:45.916287 DATLAT Default: 0xf
6363 04:40:45.916361 0, 0xFFFF, sum = 0
6364 04:40:45.919438 1, 0xFFFF, sum = 0
6365 04:40:45.919566 2, 0xFFFF, sum = 0
6366 04:40:45.922522 3, 0xFFFF, sum = 0
6367 04:40:45.922595 4, 0xFFFF, sum = 0
6368 04:40:45.926320 5, 0xFFFF, sum = 0
6369 04:40:45.926409 6, 0xFFFF, sum = 0
6370 04:40:45.929351 7, 0xFFFF, sum = 0
6371 04:40:45.929436 8, 0xFFFF, sum = 0
6372 04:40:45.932929 9, 0xFFFF, sum = 0
6373 04:40:45.933032 10, 0xFFFF, sum = 0
6374 04:40:45.936084 11, 0xFFFF, sum = 0
6375 04:40:45.939106 12, 0xFFFF, sum = 0
6376 04:40:45.939216 13, 0x0, sum = 1
6377 04:40:45.942803 14, 0x0, sum = 2
6378 04:40:45.942915 15, 0x0, sum = 3
6379 04:40:45.943011 16, 0x0, sum = 4
6380 04:40:45.945750 best_step = 14
6381 04:40:45.945826
6382 04:40:45.945889 ==
6383 04:40:45.949419 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 04:40:45.952300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 04:40:45.952386 ==
6386 04:40:45.955900 RX Vref Scan: 1
6387 04:40:45.956006
6388 04:40:45.956099 RX Vref 0 -> 0, step: 1
6389 04:40:45.958954
6390 04:40:45.959067 RX Delay -311 -> 252, step: 8
6391 04:40:45.959163
6392 04:40:45.962775 Set Vref, RX VrefLevel [Byte0]: 56
6393 04:40:45.965895 [Byte1]: 50
6394 04:40:45.970940
6395 04:40:45.971054 Final RX Vref Byte 0 = 56 to rank0
6396 04:40:45.974005 Final RX Vref Byte 1 = 50 to rank0
6397 04:40:45.977847 Final RX Vref Byte 0 = 56 to rank1
6398 04:40:45.981047 Final RX Vref Byte 1 = 50 to rank1==
6399 04:40:45.984123 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 04:40:45.991136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 04:40:45.991245 ==
6402 04:40:45.991343 DQS Delay:
6403 04:40:45.991462 DQS0 = 28, DQS1 = 36
6404 04:40:45.994661 DQM Delay:
6405 04:40:45.994768 DQM0 = 11, DQM1 = 12
6406 04:40:45.997930 DQ Delay:
6407 04:40:46.000965 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6408 04:40:46.001074 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6409 04:40:46.004570 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6410 04:40:46.007473 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6411 04:40:46.007588
6412 04:40:46.007661
6413 04:40:46.017594 [DQSOSCAuto] RK0, (LSB)MR18= 0xcdbb, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6414 04:40:46.020635 CH0 RK0: MR19=C0C, MR18=CDBB
6415 04:40:46.027494 CH0_RK0: MR19=0xC0C, MR18=0xCDBB, DQSOSC=384, MR23=63, INC=400, DEC=267
6416 04:40:46.027629 ==
6417 04:40:46.030767 Dram Type= 6, Freq= 0, CH_0, rank 1
6418 04:40:46.033920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 04:40:46.034026 ==
6420 04:40:46.037614 [Gating] SW mode calibration
6421 04:40:46.044322 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6422 04:40:46.047190 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6423 04:40:46.053907 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6424 04:40:46.057560 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6425 04:40:46.060469 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 04:40:46.067321 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 04:40:46.071003 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 04:40:46.074035 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 04:40:46.080797 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 04:40:46.084098 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 04:40:46.087146 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6432 04:40:46.090389 Total UI for P1: 0, mck2ui 16
6433 04:40:46.094313 best dqsien dly found for B0: ( 0, 14, 24)
6434 04:40:46.097510 Total UI for P1: 0, mck2ui 16
6435 04:40:46.100940 best dqsien dly found for B1: ( 0, 14, 24)
6436 04:40:46.104022 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6437 04:40:46.107723 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6438 04:40:46.107807
6439 04:40:46.114302 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6440 04:40:46.117416 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6441 04:40:46.120732 [Gating] SW calibration Done
6442 04:40:46.120816 ==
6443 04:40:46.123970 Dram Type= 6, Freq= 0, CH_0, rank 1
6444 04:40:46.127562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 04:40:46.127680 ==
6446 04:40:46.127751 RX Vref Scan: 0
6447 04:40:46.127813
6448 04:40:46.130729 RX Vref 0 -> 0, step: 1
6449 04:40:46.130812
6450 04:40:46.133687 RX Delay -410 -> 252, step: 16
6451 04:40:46.137560 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6452 04:40:46.144262 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6453 04:40:46.147217 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6454 04:40:46.150308 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6455 04:40:46.153731 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6456 04:40:46.160442 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6457 04:40:46.163909 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6458 04:40:46.166778 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6459 04:40:46.170615 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6460 04:40:46.173741 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6461 04:40:46.180555 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6462 04:40:46.183891 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6463 04:40:46.186927 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6464 04:40:46.193723 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6465 04:40:46.196797 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6466 04:40:46.200037 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6467 04:40:46.200127 ==
6468 04:40:46.203947 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 04:40:46.206749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 04:40:46.210186 ==
6471 04:40:46.210291 DQS Delay:
6472 04:40:46.210357 DQS0 = 27, DQS1 = 35
6473 04:40:46.213869 DQM Delay:
6474 04:40:46.213954 DQM0 = 12, DQM1 = 11
6475 04:40:46.217276 DQ Delay:
6476 04:40:46.217360 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6477 04:40:46.220222 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6478 04:40:46.223462 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6479 04:40:46.227134 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6480 04:40:46.227241
6481 04:40:46.227350
6482 04:40:46.227469 ==
6483 04:40:46.230152 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 04:40:46.236707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 04:40:46.236806 ==
6486 04:40:46.236882
6487 04:40:46.236943
6488 04:40:46.237001 TX Vref Scan disable
6489 04:40:46.239909 == TX Byte 0 ==
6490 04:40:46.243281 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6491 04:40:46.246717 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6492 04:40:46.250020 == TX Byte 1 ==
6493 04:40:46.253607 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6494 04:40:46.256637 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6495 04:40:46.260256 ==
6496 04:40:46.260347 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 04:40:46.266480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 04:40:46.266566 ==
6499 04:40:46.266633
6500 04:40:46.266693
6501 04:40:46.270193 TX Vref Scan disable
6502 04:40:46.270278 == TX Byte 0 ==
6503 04:40:46.273046 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6504 04:40:46.276501 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6505 04:40:46.280333 == TX Byte 1 ==
6506 04:40:46.283366 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6507 04:40:46.286434 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6508 04:40:46.286525
6509 04:40:46.290324 [DATLAT]
6510 04:40:46.290411 Freq=400, CH0 RK1
6511 04:40:46.290477
6512 04:40:46.293379 DATLAT Default: 0xe
6513 04:40:46.293464 0, 0xFFFF, sum = 0
6514 04:40:46.296595 1, 0xFFFF, sum = 0
6515 04:40:46.296684 2, 0xFFFF, sum = 0
6516 04:40:46.299751 3, 0xFFFF, sum = 0
6517 04:40:46.299837 4, 0xFFFF, sum = 0
6518 04:40:46.302959 5, 0xFFFF, sum = 0
6519 04:40:46.303045 6, 0xFFFF, sum = 0
6520 04:40:46.306757 7, 0xFFFF, sum = 0
6521 04:40:46.309864 8, 0xFFFF, sum = 0
6522 04:40:46.309991 9, 0xFFFF, sum = 0
6523 04:40:46.312835 10, 0xFFFF, sum = 0
6524 04:40:46.312975 11, 0xFFFF, sum = 0
6525 04:40:46.316650 12, 0xFFFF, sum = 0
6526 04:40:46.316734 13, 0x0, sum = 1
6527 04:40:46.320054 14, 0x0, sum = 2
6528 04:40:46.320152 15, 0x0, sum = 3
6529 04:40:46.323088 16, 0x0, sum = 4
6530 04:40:46.323172 best_step = 14
6531 04:40:46.323238
6532 04:40:46.323298 ==
6533 04:40:46.326278 Dram Type= 6, Freq= 0, CH_0, rank 1
6534 04:40:46.329521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6535 04:40:46.329605 ==
6536 04:40:46.333267 RX Vref Scan: 0
6537 04:40:46.333350
6538 04:40:46.336500 RX Vref 0 -> 0, step: 1
6539 04:40:46.336584
6540 04:40:46.336650 RX Delay -311 -> 252, step: 8
6541 04:40:46.345217 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6542 04:40:46.348513 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6543 04:40:46.351436 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6544 04:40:46.355096 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6545 04:40:46.361520 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6546 04:40:46.364883 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6547 04:40:46.368007 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6548 04:40:46.371609 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6549 04:40:46.378148 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6550 04:40:46.381398 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6551 04:40:46.384765 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6552 04:40:46.388154 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6553 04:40:46.394622 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6554 04:40:46.397868 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6555 04:40:46.401602 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6556 04:40:46.407925 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6557 04:40:46.408058 ==
6558 04:40:46.411581 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 04:40:46.414633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 04:40:46.414721 ==
6561 04:40:46.414806 DQS Delay:
6562 04:40:46.417806 DQS0 = 24, DQS1 = 32
6563 04:40:46.417893 DQM Delay:
6564 04:40:46.421676 DQM0 = 9, DQM1 = 9
6565 04:40:46.421764 DQ Delay:
6566 04:40:46.424641 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6567 04:40:46.428004 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6568 04:40:46.431051 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6569 04:40:46.434707 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6570 04:40:46.434790
6571 04:40:46.434900
6572 04:40:46.440942 [DQSOSCAuto] RK1, (LSB)MR18= 0xbd5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6573 04:40:46.444604 CH0 RK1: MR19=C0C, MR18=BD5C
6574 04:40:46.451373 CH0_RK1: MR19=0xC0C, MR18=0xBD5C, DQSOSC=386, MR23=63, INC=396, DEC=264
6575 04:40:46.454454 [RxdqsGatingPostProcess] freq 400
6576 04:40:46.457674 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6577 04:40:46.461404 best DQS0 dly(2T, 0.5T) = (0, 10)
6578 04:40:46.464517 best DQS1 dly(2T, 0.5T) = (0, 10)
6579 04:40:46.467647 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6580 04:40:46.471377 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6581 04:40:46.474363 best DQS0 dly(2T, 0.5T) = (0, 10)
6582 04:40:46.477881 best DQS1 dly(2T, 0.5T) = (0, 10)
6583 04:40:46.480997 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6584 04:40:46.484562 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6585 04:40:46.487927 Pre-setting of DQS Precalculation
6586 04:40:46.491197 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6587 04:40:46.494334 ==
6588 04:40:46.494414 Dram Type= 6, Freq= 0, CH_1, rank 0
6589 04:40:46.500979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 04:40:46.501071 ==
6591 04:40:46.504597 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6592 04:40:46.511178 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6593 04:40:46.514470 [CA 0] Center 36 (8~64) winsize 57
6594 04:40:46.517878 [CA 1] Center 36 (8~64) winsize 57
6595 04:40:46.520813 [CA 2] Center 36 (8~64) winsize 57
6596 04:40:46.524565 [CA 3] Center 36 (8~64) winsize 57
6597 04:40:46.527663 [CA 4] Center 36 (8~64) winsize 57
6598 04:40:46.530759 [CA 5] Center 36 (8~64) winsize 57
6599 04:40:46.530877
6600 04:40:46.534031 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6601 04:40:46.534134
6602 04:40:46.537754 [CATrainingPosCal] consider 1 rank data
6603 04:40:46.540833 u2DelayCellTimex100 = 270/100 ps
6604 04:40:46.544611 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 04:40:46.547825 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 04:40:46.551106 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 04:40:46.554351 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 04:40:46.557505 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 04:40:46.564492 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 04:40:46.564584
6611 04:40:46.567674 CA PerBit enable=1, Macro0, CA PI delay=36
6612 04:40:46.567760
6613 04:40:46.570806 [CBTSetCACLKResult] CA Dly = 36
6614 04:40:46.570891 CS Dly: 1 (0~32)
6615 04:40:46.570959 ==
6616 04:40:46.574448 Dram Type= 6, Freq= 0, CH_1, rank 1
6617 04:40:46.577574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6618 04:40:46.577660 ==
6619 04:40:46.584460 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6620 04:40:46.590685 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6621 04:40:46.594501 [CA 0] Center 36 (8~64) winsize 57
6622 04:40:46.597448 [CA 1] Center 36 (8~64) winsize 57
6623 04:40:46.600966 [CA 2] Center 36 (8~64) winsize 57
6624 04:40:46.604161 [CA 3] Center 36 (8~64) winsize 57
6625 04:40:46.607248 [CA 4] Center 36 (8~64) winsize 57
6626 04:40:46.610862 [CA 5] Center 36 (8~64) winsize 57
6627 04:40:46.610951
6628 04:40:46.613662 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6629 04:40:46.613750
6630 04:40:46.617153 [CATrainingPosCal] consider 2 rank data
6631 04:40:46.620711 u2DelayCellTimex100 = 270/100 ps
6632 04:40:46.623568 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 04:40:46.627493 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 04:40:46.630397 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 04:40:46.633713 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 04:40:46.637011 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 04:40:46.640555 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 04:40:46.640641
6639 04:40:46.643902 CA PerBit enable=1, Macro0, CA PI delay=36
6640 04:40:46.643978
6641 04:40:46.647459 [CBTSetCACLKResult] CA Dly = 36
6642 04:40:46.650677 CS Dly: 1 (0~32)
6643 04:40:46.650757
6644 04:40:46.653797 ----->DramcWriteLeveling(PI) begin...
6645 04:40:46.653874 ==
6646 04:40:46.657431 Dram Type= 6, Freq= 0, CH_1, rank 0
6647 04:40:46.660626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 04:40:46.660712 ==
6649 04:40:46.663744 Write leveling (Byte 0): 40 => 8
6650 04:40:46.666966 Write leveling (Byte 1): 40 => 8
6651 04:40:46.670885 DramcWriteLeveling(PI) end<-----
6652 04:40:46.670971
6653 04:40:46.671036 ==
6654 04:40:46.674003 Dram Type= 6, Freq= 0, CH_1, rank 0
6655 04:40:46.677056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 04:40:46.677161 ==
6657 04:40:46.680203 [Gating] SW mode calibration
6658 04:40:46.687060 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6659 04:40:46.693888 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6660 04:40:46.696917 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6661 04:40:46.703684 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6662 04:40:46.706662 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 04:40:46.710601 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 04:40:46.716705 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 04:40:46.720370 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 04:40:46.723300 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 04:40:46.727029 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 04:40:46.733311 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6669 04:40:46.737056 Total UI for P1: 0, mck2ui 16
6670 04:40:46.740056 best dqsien dly found for B0: ( 0, 14, 24)
6671 04:40:46.743551 Total UI for P1: 0, mck2ui 16
6672 04:40:46.746802 best dqsien dly found for B1: ( 0, 14, 24)
6673 04:40:46.749996 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6674 04:40:46.753521 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6675 04:40:46.753619
6676 04:40:46.756881 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6677 04:40:46.760158 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6678 04:40:46.763390 [Gating] SW calibration Done
6679 04:40:46.763507 ==
6680 04:40:46.766526 Dram Type= 6, Freq= 0, CH_1, rank 0
6681 04:40:46.769715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 04:40:46.769799 ==
6683 04:40:46.773321 RX Vref Scan: 0
6684 04:40:46.773401
6685 04:40:46.776424 RX Vref 0 -> 0, step: 1
6686 04:40:46.776503
6687 04:40:46.776585 RX Delay -410 -> 252, step: 16
6688 04:40:46.783113 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6689 04:40:46.786829 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6690 04:40:46.790029 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6691 04:40:46.796364 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6692 04:40:46.800019 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6693 04:40:46.803098 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6694 04:40:46.806342 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6695 04:40:46.809886 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6696 04:40:46.816622 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6697 04:40:46.819737 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6698 04:40:46.822904 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6699 04:40:46.826554 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6700 04:40:46.833390 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6701 04:40:46.836400 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6702 04:40:46.840080 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6703 04:40:46.846245 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6704 04:40:46.846376 ==
6705 04:40:46.850074 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 04:40:46.853317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 04:40:46.853410 ==
6708 04:40:46.853493 DQS Delay:
6709 04:40:46.856293 DQS0 = 35, DQS1 = 35
6710 04:40:46.856388 DQM Delay:
6711 04:40:46.859725 DQM0 = 17, DQM1 = 13
6712 04:40:46.859814 DQ Delay:
6713 04:40:46.863173 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6714 04:40:46.866378 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6715 04:40:46.869939 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6716 04:40:46.873227 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6717 04:40:46.873324
6718 04:40:46.873391
6719 04:40:46.873451 ==
6720 04:40:46.876541 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 04:40:46.879693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 04:40:46.879775 ==
6723 04:40:46.879875
6724 04:40:46.879959
6725 04:40:46.882667 TX Vref Scan disable
6726 04:40:46.882792 == TX Byte 0 ==
6727 04:40:46.889370 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 04:40:46.893176 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 04:40:46.893271 == TX Byte 1 ==
6730 04:40:46.899381 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6731 04:40:46.903140 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6732 04:40:46.903232 ==
6733 04:40:46.906500 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 04:40:46.909629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 04:40:46.909709 ==
6736 04:40:46.909782
6737 04:40:46.909885
6738 04:40:46.912769 TX Vref Scan disable
6739 04:40:46.916340 == TX Byte 0 ==
6740 04:40:46.919341 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 04:40:46.923270 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 04:40:46.923379 == TX Byte 1 ==
6743 04:40:46.929572 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6744 04:40:46.932542 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6745 04:40:46.932627
6746 04:40:46.932692 [DATLAT]
6747 04:40:46.935903 Freq=400, CH1 RK0
6748 04:40:46.935998
6749 04:40:46.936061 DATLAT Default: 0xf
6750 04:40:46.939342 0, 0xFFFF, sum = 0
6751 04:40:46.939430 1, 0xFFFF, sum = 0
6752 04:40:46.942430 2, 0xFFFF, sum = 0
6753 04:40:46.942547 3, 0xFFFF, sum = 0
6754 04:40:46.946074 4, 0xFFFF, sum = 0
6755 04:40:46.949245 5, 0xFFFF, sum = 0
6756 04:40:46.949343 6, 0xFFFF, sum = 0
6757 04:40:46.952473 7, 0xFFFF, sum = 0
6758 04:40:46.952566 8, 0xFFFF, sum = 0
6759 04:40:46.956445 9, 0xFFFF, sum = 0
6760 04:40:46.956544 10, 0xFFFF, sum = 0
6761 04:40:46.959602 11, 0xFFFF, sum = 0
6762 04:40:46.959699 12, 0xFFFF, sum = 0
6763 04:40:46.962772 13, 0x0, sum = 1
6764 04:40:46.962851 14, 0x0, sum = 2
6765 04:40:46.965831 15, 0x0, sum = 3
6766 04:40:46.965921 16, 0x0, sum = 4
6767 04:40:46.969358 best_step = 14
6768 04:40:46.969455
6769 04:40:46.969518 ==
6770 04:40:46.972337 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 04:40:46.976142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 04:40:46.976242 ==
6773 04:40:46.976361 RX Vref Scan: 1
6774 04:40:46.976422
6775 04:40:46.979144 RX Vref 0 -> 0, step: 1
6776 04:40:46.979233
6777 04:40:46.982219 RX Delay -311 -> 252, step: 8
6778 04:40:46.982336
6779 04:40:46.985966 Set Vref, RX VrefLevel [Byte0]: 54
6780 04:40:46.988794 [Byte1]: 55
6781 04:40:46.992675
6782 04:40:46.992788 Final RX Vref Byte 0 = 54 to rank0
6783 04:40:46.996374 Final RX Vref Byte 1 = 55 to rank0
6784 04:40:46.999776 Final RX Vref Byte 0 = 54 to rank1
6785 04:40:47.002729 Final RX Vref Byte 1 = 55 to rank1==
6786 04:40:47.006207 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 04:40:47.012828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 04:40:47.012917 ==
6789 04:40:47.013001 DQS Delay:
6790 04:40:47.016427 DQS0 = 28, DQS1 = 32
6791 04:40:47.016504 DQM Delay:
6792 04:40:47.016583 DQM0 = 9, DQM1 = 9
6793 04:40:47.019487 DQ Delay:
6794 04:40:47.023128 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6795 04:40:47.023265 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6796 04:40:47.026144 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6797 04:40:47.029981 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6798 04:40:47.030094
6799 04:40:47.030186
6800 04:40:47.039665 [DQSOSCAuto] RK0, (LSB)MR18= 0x8cc3, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6801 04:40:47.043184 CH1 RK0: MR19=C0C, MR18=8CC3
6802 04:40:47.046038 CH1_RK0: MR19=0xC0C, MR18=0x8CC3, DQSOSC=385, MR23=63, INC=398, DEC=265
6803 04:40:47.049331 ==
6804 04:40:47.053041 Dram Type= 6, Freq= 0, CH_1, rank 1
6805 04:40:47.056049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 04:40:47.056175 ==
6807 04:40:47.059370 [Gating] SW mode calibration
6808 04:40:47.066202 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6809 04:40:47.069284 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6810 04:40:47.076251 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6811 04:40:47.079344 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6812 04:40:47.082769 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 04:40:47.089111 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6814 04:40:47.092726 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 04:40:47.095823 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 04:40:47.102361 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 04:40:47.105755 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 04:40:47.109181 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6819 04:40:47.112758 Total UI for P1: 0, mck2ui 16
6820 04:40:47.115920 best dqsien dly found for B0: ( 0, 14, 24)
6821 04:40:47.119182 Total UI for P1: 0, mck2ui 16
6822 04:40:47.122589 best dqsien dly found for B1: ( 0, 14, 24)
6823 04:40:47.126114 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6824 04:40:47.129465 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6825 04:40:47.129582
6826 04:40:47.135700 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6827 04:40:47.139269 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6828 04:40:47.139392 [Gating] SW calibration Done
6829 04:40:47.142429 ==
6830 04:40:47.145580 Dram Type= 6, Freq= 0, CH_1, rank 1
6831 04:40:47.149300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 04:40:47.149440 ==
6833 04:40:47.149554 RX Vref Scan: 0
6834 04:40:47.149674
6835 04:40:47.152210 RX Vref 0 -> 0, step: 1
6836 04:40:47.152324
6837 04:40:47.155691 RX Delay -410 -> 252, step: 16
6838 04:40:47.158841 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6839 04:40:47.162194 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6840 04:40:47.168947 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6841 04:40:47.172683 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6842 04:40:47.175877 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6843 04:40:47.178959 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6844 04:40:47.185781 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6845 04:40:47.189240 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6846 04:40:47.192562 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6847 04:40:47.195613 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6848 04:40:47.202450 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6849 04:40:47.205532 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6850 04:40:47.209259 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6851 04:40:47.212183 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6852 04:40:47.218882 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6853 04:40:47.222021 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6854 04:40:47.222157 ==
6855 04:40:47.225725 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 04:40:47.228698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 04:40:47.228802 ==
6858 04:40:47.232237 DQS Delay:
6859 04:40:47.232333 DQS0 = 35, DQS1 = 35
6860 04:40:47.235548 DQM Delay:
6861 04:40:47.235702 DQM0 = 18, DQM1 = 15
6862 04:40:47.235799 DQ Delay:
6863 04:40:47.239210 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6864 04:40:47.242201 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6865 04:40:47.245487 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6866 04:40:47.248878 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6867 04:40:47.248992
6868 04:40:47.249072
6869 04:40:47.249148 ==
6870 04:40:47.252071 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 04:40:47.258874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 04:40:47.258967 ==
6873 04:40:47.259091
6874 04:40:47.259185
6875 04:40:47.259331 TX Vref Scan disable
6876 04:40:47.262401 == TX Byte 0 ==
6877 04:40:47.265481 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6878 04:40:47.268649 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6879 04:40:47.272449 == TX Byte 1 ==
6880 04:40:47.275720 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6881 04:40:47.278644 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6882 04:40:47.278746 ==
6883 04:40:47.282465 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 04:40:47.288642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 04:40:47.288721 ==
6886 04:40:47.288792
6887 04:40:47.288851
6888 04:40:47.288908 TX Vref Scan disable
6889 04:40:47.292319 == TX Byte 0 ==
6890 04:40:47.295294 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6891 04:40:47.299035 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6892 04:40:47.302205 == TX Byte 1 ==
6893 04:40:47.305367 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6894 04:40:47.309034 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6895 04:40:47.309136
6896 04:40:47.312394 [DATLAT]
6897 04:40:47.312469 Freq=400, CH1 RK1
6898 04:40:47.312535
6899 04:40:47.315390 DATLAT Default: 0xe
6900 04:40:47.315503 0, 0xFFFF, sum = 0
6901 04:40:47.318808 1, 0xFFFF, sum = 0
6902 04:40:47.318930 2, 0xFFFF, sum = 0
6903 04:40:47.322374 3, 0xFFFF, sum = 0
6904 04:40:47.322462 4, 0xFFFF, sum = 0
6905 04:40:47.325579 5, 0xFFFF, sum = 0
6906 04:40:47.325663 6, 0xFFFF, sum = 0
6907 04:40:47.328557 7, 0xFFFF, sum = 0
6908 04:40:47.328652 8, 0xFFFF, sum = 0
6909 04:40:47.332254 9, 0xFFFF, sum = 0
6910 04:40:47.335245 10, 0xFFFF, sum = 0
6911 04:40:47.335340 11, 0xFFFF, sum = 0
6912 04:40:47.338344 12, 0xFFFF, sum = 0
6913 04:40:47.338418 13, 0x0, sum = 1
6914 04:40:47.341951 14, 0x0, sum = 2
6915 04:40:47.342027 15, 0x0, sum = 3
6916 04:40:47.342088 16, 0x0, sum = 4
6917 04:40:47.345540 best_step = 14
6918 04:40:47.345648
6919 04:40:47.345744 ==
6920 04:40:47.348804 Dram Type= 6, Freq= 0, CH_1, rank 1
6921 04:40:47.351943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6922 04:40:47.352022 ==
6923 04:40:47.354996 RX Vref Scan: 0
6924 04:40:47.355101
6925 04:40:47.358565 RX Vref 0 -> 0, step: 1
6926 04:40:47.358668
6927 04:40:47.358765 RX Delay -311 -> 252, step: 8
6928 04:40:47.366817 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6929 04:40:47.370249 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6930 04:40:47.373547 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6931 04:40:47.376830 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6932 04:40:47.383855 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6933 04:40:47.387230 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6934 04:40:47.390152 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6935 04:40:47.393478 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6936 04:40:47.400115 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6937 04:40:47.403697 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6938 04:40:47.406858 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6939 04:40:47.409998 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6940 04:40:47.417037 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6941 04:40:47.420038 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6942 04:40:47.423492 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6943 04:40:47.426967 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6944 04:40:47.430457 ==
6945 04:40:47.433483 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 04:40:47.436671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 04:40:47.436758 ==
6948 04:40:47.436825 DQS Delay:
6949 04:40:47.440327 DQS0 = 28, DQS1 = 36
6950 04:40:47.440411 DQM Delay:
6951 04:40:47.443451 DQM0 = 11, DQM1 = 14
6952 04:40:47.443590 DQ Delay:
6953 04:40:47.446986 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6954 04:40:47.450025 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6955 04:40:47.453546 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =12
6956 04:40:47.456656 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6957 04:40:47.456739
6958 04:40:47.456804
6959 04:40:47.463666 [DQSOSCAuto] RK1, (LSB)MR18= 0xc456, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6960 04:40:47.466855 CH1 RK1: MR19=C0C, MR18=C456
6961 04:40:47.473558 CH1_RK1: MR19=0xC0C, MR18=0xC456, DQSOSC=385, MR23=63, INC=398, DEC=265
6962 04:40:47.476780 [RxdqsGatingPostProcess] freq 400
6963 04:40:47.479843 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6964 04:40:47.483388 best DQS0 dly(2T, 0.5T) = (0, 10)
6965 04:40:47.486886 best DQS1 dly(2T, 0.5T) = (0, 10)
6966 04:40:47.490250 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6967 04:40:47.493054 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6968 04:40:47.496433 best DQS0 dly(2T, 0.5T) = (0, 10)
6969 04:40:47.499632 best DQS1 dly(2T, 0.5T) = (0, 10)
6970 04:40:47.503322 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6971 04:40:47.506386 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6972 04:40:47.510024 Pre-setting of DQS Precalculation
6973 04:40:47.513164 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6974 04:40:47.522956 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6975 04:40:47.529878 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6976 04:40:47.529964
6977 04:40:47.530029
6978 04:40:47.532876 [Calibration Summary] 800 Mbps
6979 04:40:47.532960 CH 0, Rank 0
6980 04:40:47.536366 SW Impedance : PASS
6981 04:40:47.536450 DUTY Scan : NO K
6982 04:40:47.539885 ZQ Calibration : PASS
6983 04:40:47.543361 Jitter Meter : NO K
6984 04:40:47.543473 CBT Training : PASS
6985 04:40:47.546421 Write leveling : PASS
6986 04:40:47.549532 RX DQS gating : PASS
6987 04:40:47.549731 RX DQ/DQS(RDDQC) : PASS
6988 04:40:47.553118 TX DQ/DQS : PASS
6989 04:40:47.556161 RX DATLAT : PASS
6990 04:40:47.556263 RX DQ/DQS(Engine): PASS
6991 04:40:47.559692 TX OE : NO K
6992 04:40:47.559812 All Pass.
6993 04:40:47.559935
6994 04:40:47.562752 CH 0, Rank 1
6995 04:40:47.562822 SW Impedance : PASS
6996 04:40:47.566553 DUTY Scan : NO K
6997 04:40:47.569736 ZQ Calibration : PASS
6998 04:40:47.569819 Jitter Meter : NO K
6999 04:40:47.572688 CBT Training : PASS
7000 04:40:47.572771 Write leveling : NO K
7001 04:40:47.576361 RX DQS gating : PASS
7002 04:40:47.579346 RX DQ/DQS(RDDQC) : PASS
7003 04:40:47.579464 TX DQ/DQS : PASS
7004 04:40:47.583095 RX DATLAT : PASS
7005 04:40:47.586196 RX DQ/DQS(Engine): PASS
7006 04:40:47.586300 TX OE : NO K
7007 04:40:47.589319 All Pass.
7008 04:40:47.589428
7009 04:40:47.589521 CH 1, Rank 0
7010 04:40:47.593027 SW Impedance : PASS
7011 04:40:47.593135 DUTY Scan : NO K
7012 04:40:47.596154 ZQ Calibration : PASS
7013 04:40:47.599145 Jitter Meter : NO K
7014 04:40:47.599249 CBT Training : PASS
7015 04:40:47.602815 Write leveling : PASS
7016 04:40:47.606313 RX DQS gating : PASS
7017 04:40:47.606414 RX DQ/DQS(RDDQC) : PASS
7018 04:40:47.609665 TX DQ/DQS : PASS
7019 04:40:47.613044 RX DATLAT : PASS
7020 04:40:47.613159 RX DQ/DQS(Engine): PASS
7021 04:40:47.616491 TX OE : NO K
7022 04:40:47.616598 All Pass.
7023 04:40:47.616696
7024 04:40:47.619432 CH 1, Rank 1
7025 04:40:47.619558 SW Impedance : PASS
7026 04:40:47.623322 DUTY Scan : NO K
7027 04:40:47.623431 ZQ Calibration : PASS
7028 04:40:47.626334 Jitter Meter : NO K
7029 04:40:47.629586 CBT Training : PASS
7030 04:40:47.629703 Write leveling : NO K
7031 04:40:47.633207 RX DQS gating : PASS
7032 04:40:47.636319 RX DQ/DQS(RDDQC) : PASS
7033 04:40:47.636411 TX DQ/DQS : PASS
7034 04:40:47.639327 RX DATLAT : PASS
7035 04:40:47.642913 RX DQ/DQS(Engine): PASS
7036 04:40:47.643008 TX OE : NO K
7037 04:40:47.646496 All Pass.
7038 04:40:47.646577
7039 04:40:47.646641 DramC Write-DBI off
7040 04:40:47.649425 PER_BANK_REFRESH: Hybrid Mode
7041 04:40:47.649511 TX_TRACKING: ON
7042 04:40:47.659657 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7043 04:40:47.662663 [FAST_K] Save calibration result to emmc
7044 04:40:47.666234 dramc_set_vcore_voltage set vcore to 725000
7045 04:40:47.669402 Read voltage for 1600, 0
7046 04:40:47.669507 Vio18 = 0
7047 04:40:47.672588 Vcore = 725000
7048 04:40:47.672664 Vdram = 0
7049 04:40:47.672747 Vddq = 0
7050 04:40:47.676262 Vmddr = 0
7051 04:40:47.679182 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7052 04:40:47.685973 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7053 04:40:47.686083 MEM_TYPE=3, freq_sel=13
7054 04:40:47.689043 sv_algorithm_assistance_LP4_3733
7055 04:40:47.695971 ============ PULL DRAM RESETB DOWN ============
7056 04:40:47.698913 ========== PULL DRAM RESETB DOWN end =========
7057 04:40:47.702705 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7058 04:40:47.705872 ===================================
7059 04:40:47.709164 LPDDR4 DRAM CONFIGURATION
7060 04:40:47.712687 ===================================
7061 04:40:47.712765 EX_ROW_EN[0] = 0x0
7062 04:40:47.715655 EX_ROW_EN[1] = 0x0
7063 04:40:47.719141 LP4Y_EN = 0x0
7064 04:40:47.719230 WORK_FSP = 0x1
7065 04:40:47.722666 WL = 0x5
7066 04:40:47.722744 RL = 0x5
7067 04:40:47.725643 BL = 0x2
7068 04:40:47.725731 RPST = 0x0
7069 04:40:47.729035 RD_PRE = 0x0
7070 04:40:47.729115 WR_PRE = 0x1
7071 04:40:47.732746 WR_PST = 0x1
7072 04:40:47.732820 DBI_WR = 0x0
7073 04:40:47.736000 DBI_RD = 0x0
7074 04:40:47.736086 OTF = 0x1
7075 04:40:47.738947 ===================================
7076 04:40:47.742639 ===================================
7077 04:40:47.745779 ANA top config
7078 04:40:47.748776 ===================================
7079 04:40:47.748873 DLL_ASYNC_EN = 0
7080 04:40:47.752477 ALL_SLAVE_EN = 0
7081 04:40:47.755842 NEW_RANK_MODE = 1
7082 04:40:47.758742 DLL_IDLE_MODE = 1
7083 04:40:47.762257 LP45_APHY_COMB_EN = 1
7084 04:40:47.762363 TX_ODT_DIS = 0
7085 04:40:47.765701 NEW_8X_MODE = 1
7086 04:40:47.768896 ===================================
7087 04:40:47.772410 ===================================
7088 04:40:47.775664 data_rate = 3200
7089 04:40:47.778764 CKR = 1
7090 04:40:47.782338 DQ_P2S_RATIO = 8
7091 04:40:47.785941 ===================================
7092 04:40:47.786030 CA_P2S_RATIO = 8
7093 04:40:47.788999 DQ_CA_OPEN = 0
7094 04:40:47.792090 DQ_SEMI_OPEN = 0
7095 04:40:47.795904 CA_SEMI_OPEN = 0
7096 04:40:47.798936 CA_FULL_RATE = 0
7097 04:40:47.802286 DQ_CKDIV4_EN = 0
7098 04:40:47.802363 CA_CKDIV4_EN = 0
7099 04:40:47.805307 CA_PREDIV_EN = 0
7100 04:40:47.808989 PH8_DLY = 12
7101 04:40:47.812218 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7102 04:40:47.815288 DQ_AAMCK_DIV = 4
7103 04:40:47.818866 CA_AAMCK_DIV = 4
7104 04:40:47.818942 CA_ADMCK_DIV = 4
7105 04:40:47.822122 DQ_TRACK_CA_EN = 0
7106 04:40:47.825666 CA_PICK = 1600
7107 04:40:47.828784 CA_MCKIO = 1600
7108 04:40:47.832431 MCKIO_SEMI = 0
7109 04:40:47.835254 PLL_FREQ = 3068
7110 04:40:47.838875 DQ_UI_PI_RATIO = 32
7111 04:40:47.841951 CA_UI_PI_RATIO = 0
7112 04:40:47.842049 ===================================
7113 04:40:47.845507 ===================================
7114 04:40:47.848490 memory_type:LPDDR4
7115 04:40:47.852385 GP_NUM : 10
7116 04:40:47.852469 SRAM_EN : 1
7117 04:40:47.855574 MD32_EN : 0
7118 04:40:47.858550 ===================================
7119 04:40:47.861723 [ANA_INIT] >>>>>>>>>>>>>>
7120 04:40:47.865382 <<<<<< [CONFIGURE PHASE]: ANA_TX
7121 04:40:47.868897 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7122 04:40:47.871761 ===================================
7123 04:40:47.871845 data_rate = 3200,PCW = 0X7600
7124 04:40:47.875352 ===================================
7125 04:40:47.882047 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7126 04:40:47.885222 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7127 04:40:47.891822 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7128 04:40:47.895112 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7129 04:40:47.898286 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7130 04:40:47.902018 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7131 04:40:47.905226 [ANA_INIT] flow start
7132 04:40:47.908261 [ANA_INIT] PLL >>>>>>>>
7133 04:40:47.908343 [ANA_INIT] PLL <<<<<<<<
7134 04:40:47.911864 [ANA_INIT] MIDPI >>>>>>>>
7135 04:40:47.915008 [ANA_INIT] MIDPI <<<<<<<<
7136 04:40:47.915094 [ANA_INIT] DLL >>>>>>>>
7137 04:40:47.918584 [ANA_INIT] DLL <<<<<<<<
7138 04:40:47.921646 [ANA_INIT] flow end
7139 04:40:47.925279 ============ LP4 DIFF to SE enter ============
7140 04:40:47.928342 ============ LP4 DIFF to SE exit ============
7141 04:40:47.931387 [ANA_INIT] <<<<<<<<<<<<<
7142 04:40:47.935068 [Flow] Enable top DCM control >>>>>
7143 04:40:47.938254 [Flow] Enable top DCM control <<<<<
7144 04:40:47.941963 Enable DLL master slave shuffle
7145 04:40:47.945081 ==============================================================
7146 04:40:47.948111 Gating Mode config
7147 04:40:47.954788 ==============================================================
7148 04:40:47.954874 Config description:
7149 04:40:47.965036 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7150 04:40:47.971368 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7151 04:40:47.974802 SELPH_MODE 0: By rank 1: By Phase
7152 04:40:47.981272 ==============================================================
7153 04:40:47.984706 GAT_TRACK_EN = 1
7154 04:40:47.988092 RX_GATING_MODE = 2
7155 04:40:47.991475 RX_GATING_TRACK_MODE = 2
7156 04:40:47.994845 SELPH_MODE = 1
7157 04:40:47.998255 PICG_EARLY_EN = 1
7158 04:40:48.001357 VALID_LAT_VALUE = 1
7159 04:40:48.005285 ==============================================================
7160 04:40:48.008378 Enter into Gating configuration >>>>
7161 04:40:48.011543 Exit from Gating configuration <<<<
7162 04:40:48.014558 Enter into DVFS_PRE_config >>>>>
7163 04:40:48.024547 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7164 04:40:48.028217 Exit from DVFS_PRE_config <<<<<
7165 04:40:48.031373 Enter into PICG configuration >>>>
7166 04:40:48.034944 Exit from PICG configuration <<<<
7167 04:40:48.037996 [RX_INPUT] configuration >>>>>
7168 04:40:48.041771 [RX_INPUT] configuration <<<<<
7169 04:40:48.047949 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7170 04:40:48.051666 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7171 04:40:48.057808 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7172 04:40:48.064558 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7173 04:40:48.071429 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7174 04:40:48.077969 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7175 04:40:48.081162 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7176 04:40:48.084252 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7177 04:40:48.087825 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7178 04:40:48.094386 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7179 04:40:48.097957 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7180 04:40:48.100887 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7181 04:40:48.104476 ===================================
7182 04:40:48.107778 LPDDR4 DRAM CONFIGURATION
7183 04:40:48.111074 ===================================
7184 04:40:48.111158 EX_ROW_EN[0] = 0x0
7185 04:40:48.114225 EX_ROW_EN[1] = 0x0
7186 04:40:48.117845 LP4Y_EN = 0x0
7187 04:40:48.117928 WORK_FSP = 0x1
7188 04:40:48.120909 WL = 0x5
7189 04:40:48.120992 RL = 0x5
7190 04:40:48.124240 BL = 0x2
7191 04:40:48.124326 RPST = 0x0
7192 04:40:48.127950 RD_PRE = 0x0
7193 04:40:48.128035 WR_PRE = 0x1
7194 04:40:48.130796 WR_PST = 0x1
7195 04:40:48.130880 DBI_WR = 0x0
7196 04:40:48.134380 DBI_RD = 0x0
7197 04:40:48.134465 OTF = 0x1
7198 04:40:48.137357 ===================================
7199 04:40:48.141124 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7200 04:40:48.147834 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7201 04:40:48.150994 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7202 04:40:48.154038 ===================================
7203 04:40:48.157825 LPDDR4 DRAM CONFIGURATION
7204 04:40:48.160983 ===================================
7205 04:40:48.161090 EX_ROW_EN[0] = 0x10
7206 04:40:48.164209 EX_ROW_EN[1] = 0x0
7207 04:40:48.164308 LP4Y_EN = 0x0
7208 04:40:48.167357 WORK_FSP = 0x1
7209 04:40:48.167446 WL = 0x5
7210 04:40:48.170608 RL = 0x5
7211 04:40:48.174262 BL = 0x2
7212 04:40:48.174348 RPST = 0x0
7213 04:40:48.177316 RD_PRE = 0x0
7214 04:40:48.177399 WR_PRE = 0x1
7215 04:40:48.180848 WR_PST = 0x1
7216 04:40:48.180935 DBI_WR = 0x0
7217 04:40:48.184394 DBI_RD = 0x0
7218 04:40:48.184484 OTF = 0x1
7219 04:40:48.187262 ===================================
7220 04:40:48.193882 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7221 04:40:48.194012 ==
7222 04:40:48.197408 Dram Type= 6, Freq= 0, CH_0, rank 0
7223 04:40:48.200486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7224 04:40:48.200590 ==
7225 04:40:48.203918 [Duty_Offset_Calibration]
7226 04:40:48.207510 B0:2 B1:1 CA:1
7227 04:40:48.207632
7228 04:40:48.210591 [DutyScan_Calibration_Flow] k_type=0
7229 04:40:48.219444
7230 04:40:48.219537 ==CLK 0==
7231 04:40:48.222526 Final CLK duty delay cell = 0
7232 04:40:48.225901 [0] MAX Duty = 5156%(X100), DQS PI = 22
7233 04:40:48.228850 [0] MIN Duty = 4907%(X100), DQS PI = 0
7234 04:40:48.228934 [0] AVG Duty = 5031%(X100)
7235 04:40:48.232512
7236 04:40:48.235740 CH0 CLK Duty spec in!! Max-Min= 249%
7237 04:40:48.238791 [DutyScan_Calibration_Flow] ====Done====
7238 04:40:48.238873
7239 04:40:48.241783 [DutyScan_Calibration_Flow] k_type=1
7240 04:40:48.258427
7241 04:40:48.258540 ==DQS 0 ==
7242 04:40:48.261550 Final DQS duty delay cell = -4
7243 04:40:48.264631 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7244 04:40:48.267813 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7245 04:40:48.271536 [-4] AVG Duty = 4906%(X100)
7246 04:40:48.271636
7247 04:40:48.271702 ==DQS 1 ==
7248 04:40:48.274584 Final DQS duty delay cell = 0
7249 04:40:48.277740 [0] MAX Duty = 5218%(X100), DQS PI = 22
7250 04:40:48.281014 [0] MIN Duty = 5062%(X100), DQS PI = 32
7251 04:40:48.284651 [0] AVG Duty = 5140%(X100)
7252 04:40:48.284751
7253 04:40:48.288332 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7254 04:40:48.288410
7255 04:40:48.291417 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7256 04:40:48.294461 [DutyScan_Calibration_Flow] ====Done====
7257 04:40:48.294596
7258 04:40:48.297674 [DutyScan_Calibration_Flow] k_type=3
7259 04:40:48.314765
7260 04:40:48.314851 ==DQM 0 ==
7261 04:40:48.318066 Final DQM duty delay cell = 0
7262 04:40:48.321266 [0] MAX Duty = 5218%(X100), DQS PI = 34
7263 04:40:48.325231 [0] MIN Duty = 4907%(X100), DQS PI = 54
7264 04:40:48.328131 [0] AVG Duty = 5062%(X100)
7265 04:40:48.328211
7266 04:40:48.328316 ==DQM 1 ==
7267 04:40:48.331441 Final DQM duty delay cell = -4
7268 04:40:48.334501 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7269 04:40:48.338263 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7270 04:40:48.341089 [-4] AVG Duty = 4906%(X100)
7271 04:40:48.341198
7272 04:40:48.344486 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7273 04:40:48.344607
7274 04:40:48.348224 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7275 04:40:48.351139 [DutyScan_Calibration_Flow] ====Done====
7276 04:40:48.351242
7277 04:40:48.354790 [DutyScan_Calibration_Flow] k_type=2
7278 04:40:48.372213
7279 04:40:48.372305 ==DQ 0 ==
7280 04:40:48.375830 Final DQ duty delay cell = 0
7281 04:40:48.379072 [0] MAX Duty = 5062%(X100), DQS PI = 26
7282 04:40:48.382118 [0] MIN Duty = 4907%(X100), DQS PI = 0
7283 04:40:48.382227 [0] AVG Duty = 4984%(X100)
7284 04:40:48.382321
7285 04:40:48.385885 ==DQ 1 ==
7286 04:40:48.388986 Final DQ duty delay cell = 0
7287 04:40:48.392764 [0] MAX Duty = 5125%(X100), DQS PI = 6
7288 04:40:48.395758 [0] MIN Duty = 4907%(X100), DQS PI = 34
7289 04:40:48.395853 [0] AVG Duty = 5016%(X100)
7290 04:40:48.395945
7291 04:40:48.398854 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7292 04:40:48.398936
7293 04:40:48.402539 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7294 04:40:48.408848 [DutyScan_Calibration_Flow] ====Done====
7295 04:40:48.408951 ==
7296 04:40:48.412513 Dram Type= 6, Freq= 0, CH_1, rank 0
7297 04:40:48.415355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7298 04:40:48.415466 ==
7299 04:40:48.418747 [Duty_Offset_Calibration]
7300 04:40:48.418840 B0:1 B1:0 CA:0
7301 04:40:48.418901
7302 04:40:48.422138 [DutyScan_Calibration_Flow] k_type=0
7303 04:40:48.431817
7304 04:40:48.431953 ==CLK 0==
7305 04:40:48.434728 Final CLK duty delay cell = -4
7306 04:40:48.438369 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7307 04:40:48.441276 [-4] MIN Duty = 4875%(X100), DQS PI = 0
7308 04:40:48.444754 [-4] AVG Duty = 4937%(X100)
7309 04:40:48.444870
7310 04:40:48.448411 CH1 CLK Duty spec in!! Max-Min= 125%
7311 04:40:48.451348 [DutyScan_Calibration_Flow] ====Done====
7312 04:40:48.451447
7313 04:40:48.454970 [DutyScan_Calibration_Flow] k_type=1
7314 04:40:48.471605
7315 04:40:48.471705 ==DQS 0 ==
7316 04:40:48.474731 Final DQS duty delay cell = 0
7317 04:40:48.478465 [0] MAX Duty = 5094%(X100), DQS PI = 18
7318 04:40:48.481546 [0] MIN Duty = 4844%(X100), DQS PI = 48
7319 04:40:48.484727 [0] AVG Duty = 4969%(X100)
7320 04:40:48.484811
7321 04:40:48.484874 ==DQS 1 ==
7322 04:40:48.487872 Final DQS duty delay cell = 0
7323 04:40:48.491646 [0] MAX Duty = 5249%(X100), DQS PI = 18
7324 04:40:48.494584 [0] MIN Duty = 4969%(X100), DQS PI = 8
7325 04:40:48.497820 [0] AVG Duty = 5109%(X100)
7326 04:40:48.497902
7327 04:40:48.501611 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7328 04:40:48.501693
7329 04:40:48.504750 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7330 04:40:48.507813 [DutyScan_Calibration_Flow] ====Done====
7331 04:40:48.507895
7332 04:40:48.511484 [DutyScan_Calibration_Flow] k_type=3
7333 04:40:48.528263
7334 04:40:48.528375 ==DQM 0 ==
7335 04:40:48.531879 Final DQM duty delay cell = 0
7336 04:40:48.535238 [0] MAX Duty = 5218%(X100), DQS PI = 18
7337 04:40:48.538534 [0] MIN Duty = 4969%(X100), DQS PI = 48
7338 04:40:48.538615 [0] AVG Duty = 5093%(X100)
7339 04:40:48.541819
7340 04:40:48.541929 ==DQM 1 ==
7341 04:40:48.545334 Final DQM duty delay cell = 0
7342 04:40:48.548773 [0] MAX Duty = 5093%(X100), DQS PI = 18
7343 04:40:48.552033 [0] MIN Duty = 4907%(X100), DQS PI = 52
7344 04:40:48.552111 [0] AVG Duty = 5000%(X100)
7345 04:40:48.555611
7346 04:40:48.558169 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7347 04:40:48.558304
7348 04:40:48.561931 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7349 04:40:48.564961 [DutyScan_Calibration_Flow] ====Done====
7350 04:40:48.565044
7351 04:40:48.568483 [DutyScan_Calibration_Flow] k_type=2
7352 04:40:48.584755
7353 04:40:48.584854 ==DQ 0 ==
7354 04:40:48.587953 Final DQ duty delay cell = -4
7355 04:40:48.591116 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7356 04:40:48.594324 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7357 04:40:48.598218 [-4] AVG Duty = 4968%(X100)
7358 04:40:48.598320
7359 04:40:48.598413 ==DQ 1 ==
7360 04:40:48.600948 Final DQ duty delay cell = 0
7361 04:40:48.604655 [0] MAX Duty = 5124%(X100), DQS PI = 18
7362 04:40:48.607779 [0] MIN Duty = 4938%(X100), DQS PI = 8
7363 04:40:48.610982 [0] AVG Duty = 5031%(X100)
7364 04:40:48.611065
7365 04:40:48.614836 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7366 04:40:48.614916
7367 04:40:48.617922 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7368 04:40:48.620936 [DutyScan_Calibration_Flow] ====Done====
7369 04:40:48.624678 nWR fixed to 30
7370 04:40:48.627801 [ModeRegInit_LP4] CH0 RK0
7371 04:40:48.627906 [ModeRegInit_LP4] CH0 RK1
7372 04:40:48.631054 [ModeRegInit_LP4] CH1 RK0
7373 04:40:48.634502 [ModeRegInit_LP4] CH1 RK1
7374 04:40:48.634609 match AC timing 5
7375 04:40:48.640846 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7376 04:40:48.644330 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7377 04:40:48.647783 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7378 04:40:48.654344 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7379 04:40:48.657346 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7380 04:40:48.657454 [MiockJmeterHQA]
7381 04:40:48.657546
7382 04:40:48.660882 [DramcMiockJmeter] u1RxGatingPI = 0
7383 04:40:48.663962 0 : 4252, 4027
7384 04:40:48.664045 4 : 4363, 4138
7385 04:40:48.667423 8 : 4252, 4027
7386 04:40:48.667558 12 : 4252, 4027
7387 04:40:48.667630 16 : 4254, 4029
7388 04:40:48.670894 20 : 4252, 4027
7389 04:40:48.671046 24 : 4363, 4137
7390 04:40:48.673992 28 : 4253, 4027
7391 04:40:48.674099 32 : 4363, 4137
7392 04:40:48.677336 36 : 4253, 4027
7393 04:40:48.677446 40 : 4252, 4027
7394 04:40:48.681054 44 : 4252, 4027
7395 04:40:48.681133 48 : 4255, 4030
7396 04:40:48.681196 52 : 4252, 4027
7397 04:40:48.684445 56 : 4252, 4027
7398 04:40:48.684523 60 : 4365, 4140
7399 04:40:48.687340 64 : 4253, 4029
7400 04:40:48.687459 68 : 4253, 4029
7401 04:40:48.690670 72 : 4250, 4026
7402 04:40:48.690744 76 : 4360, 4137
7403 04:40:48.694192 80 : 4250, 4027
7404 04:40:48.694300 84 : 4360, 4137
7405 04:40:48.694367 88 : 4250, 119
7406 04:40:48.697425 92 : 4252, 0
7407 04:40:48.697505 96 : 4252, 0
7408 04:40:48.697593 100 : 4252, 0
7409 04:40:48.701097 104 : 4250, 0
7410 04:40:48.701176 108 : 4361, 0
7411 04:40:48.704073 112 : 4360, 0
7412 04:40:48.704149 116 : 4250, 0
7413 04:40:48.704265 120 : 4250, 0
7414 04:40:48.707679 124 : 4363, 0
7415 04:40:48.707769 128 : 4250, 0
7416 04:40:48.710777 132 : 4253, 0
7417 04:40:48.710855 136 : 4250, 0
7418 04:40:48.710935 140 : 4252, 0
7419 04:40:48.714556 144 : 4360, 0
7420 04:40:48.714664 148 : 4250, 0
7421 04:40:48.714799 152 : 4250, 0
7422 04:40:48.717630 156 : 4253, 0
7423 04:40:48.717723 160 : 4360, 0
7424 04:40:48.720876 164 : 4250, 0
7425 04:40:48.720968 168 : 4250, 0
7426 04:40:48.721035 172 : 4250, 0
7427 04:40:48.724652 176 : 4250, 0
7428 04:40:48.724737 180 : 4253, 0
7429 04:40:48.727820 184 : 4250, 0
7430 04:40:48.727896 188 : 4250, 0
7431 04:40:48.727958 192 : 4252, 0
7432 04:40:48.730901 196 : 4360, 0
7433 04:40:48.730976 200 : 4250, 0
7434 04:40:48.734771 204 : 4250, 1239
7435 04:40:48.734846 208 : 4250, 3979
7436 04:40:48.737698 212 : 4250, 4027
7437 04:40:48.737813 216 : 4360, 4137
7438 04:40:48.737916 220 : 4250, 4026
7439 04:40:48.741320 224 : 4250, 4027
7440 04:40:48.741431 228 : 4361, 4138
7441 04:40:48.744467 232 : 4360, 4137
7442 04:40:48.744582 236 : 4250, 4027
7443 04:40:48.747644 240 : 4363, 4140
7444 04:40:48.747755 244 : 4250, 4026
7445 04:40:48.750743 248 : 4250, 4027
7446 04:40:48.750858 252 : 4250, 4026
7447 04:40:48.754475 256 : 4253, 4029
7448 04:40:48.754588 260 : 4250, 4027
7449 04:40:48.758047 264 : 4250, 4027
7450 04:40:48.758162 268 : 4250, 4026
7451 04:40:48.760987 272 : 4253, 4029
7452 04:40:48.761097 276 : 4250, 4027
7453 04:40:48.761209 280 : 4361, 4138
7454 04:40:48.764228 284 : 4360, 4137
7455 04:40:48.764358 288 : 4250, 4027
7456 04:40:48.767810 292 : 4363, 4140
7457 04:40:48.767948 296 : 4250, 4027
7458 04:40:48.770927 300 : 4250, 4027
7459 04:40:48.771033 304 : 4253, 4027
7460 04:40:48.773966 308 : 4253, 3991
7461 04:40:48.774072 312 : 4250, 2022
7462 04:40:48.774167
7463 04:40:48.777186 MIOCK jitter meter ch=0
7464 04:40:48.777289
7465 04:40:48.780788 1T = (312-88) = 224 dly cells
7466 04:40:48.787111 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7467 04:40:48.787227 ==
7468 04:40:48.790842 Dram Type= 6, Freq= 0, CH_0, rank 0
7469 04:40:48.794374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7470 04:40:48.794470 ==
7471 04:40:48.797157 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7472 04:40:48.803880 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7473 04:40:48.807403 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7474 04:40:48.813586 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7475 04:40:48.822450 [CA 0] Center 43 (13~74) winsize 62
7476 04:40:48.825457 [CA 1] Center 43 (13~74) winsize 62
7477 04:40:48.829262 [CA 2] Center 38 (9~68) winsize 60
7478 04:40:48.832327 [CA 3] Center 38 (8~68) winsize 61
7479 04:40:48.835396 [CA 4] Center 37 (7~67) winsize 61
7480 04:40:48.838497 [CA 5] Center 36 (7~65) winsize 59
7481 04:40:48.838606
7482 04:40:48.841985 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7483 04:40:48.842117
7484 04:40:48.845219 [CATrainingPosCal] consider 1 rank data
7485 04:40:48.848906 u2DelayCellTimex100 = 290/100 ps
7486 04:40:48.855167 CA0 delay=43 (13~74),Diff = 7 PI (23 cell)
7487 04:40:48.858945 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7488 04:40:48.862240 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7489 04:40:48.865198 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7490 04:40:48.868952 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7491 04:40:48.871814 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7492 04:40:48.871901
7493 04:40:48.875303 CA PerBit enable=1, Macro0, CA PI delay=36
7494 04:40:48.875421
7495 04:40:48.878856 [CBTSetCACLKResult] CA Dly = 36
7496 04:40:48.881856 CS Dly: 9 (0~40)
7497 04:40:48.885452 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7498 04:40:48.888718 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7499 04:40:48.888805 ==
7500 04:40:48.892209 Dram Type= 6, Freq= 0, CH_0, rank 1
7501 04:40:48.895205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7502 04:40:48.895314 ==
7503 04:40:48.902074 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7504 04:40:48.905390 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7505 04:40:48.911933 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7506 04:40:48.915407 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7507 04:40:48.925322 [CA 0] Center 42 (12~73) winsize 62
7508 04:40:48.928834 [CA 1] Center 42 (12~73) winsize 62
7509 04:40:48.931946 [CA 2] Center 38 (8~68) winsize 61
7510 04:40:48.935191 [CA 3] Center 37 (8~67) winsize 60
7511 04:40:48.938947 [CA 4] Center 36 (6~66) winsize 61
7512 04:40:48.941965 [CA 5] Center 35 (5~65) winsize 61
7513 04:40:48.942050
7514 04:40:48.945073 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7515 04:40:48.945158
7516 04:40:48.948804 [CATrainingPosCal] consider 2 rank data
7517 04:40:48.951845 u2DelayCellTimex100 = 290/100 ps
7518 04:40:48.955038 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7519 04:40:48.961838 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7520 04:40:48.964989 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7521 04:40:48.968275 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
7522 04:40:48.972090 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7523 04:40:48.975245 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7524 04:40:48.975345
7525 04:40:48.978160 CA PerBit enable=1, Macro0, CA PI delay=36
7526 04:40:48.978245
7527 04:40:48.981762 [CBTSetCACLKResult] CA Dly = 36
7528 04:40:48.985242 CS Dly: 10 (0~42)
7529 04:40:48.988176 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7530 04:40:48.991504 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7531 04:40:48.991625
7532 04:40:48.994984 ----->DramcWriteLeveling(PI) begin...
7533 04:40:48.995060 ==
7534 04:40:48.998195 Dram Type= 6, Freq= 0, CH_0, rank 0
7535 04:40:49.004920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 04:40:49.005006 ==
7537 04:40:49.008379 Write leveling (Byte 0): 35 => 35
7538 04:40:49.008547 Write leveling (Byte 1): 28 => 28
7539 04:40:49.012001 DramcWriteLeveling(PI) end<-----
7540 04:40:49.012118
7541 04:40:49.012211 ==
7542 04:40:49.015080 Dram Type= 6, Freq= 0, CH_0, rank 0
7543 04:40:49.021417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7544 04:40:49.021507 ==
7545 04:40:49.024888 [Gating] SW mode calibration
7546 04:40:49.031790 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7547 04:40:49.034864 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7548 04:40:49.041779 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7549 04:40:49.044897 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7550 04:40:49.048057 1 4 8 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7551 04:40:49.055128 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7552 04:40:49.058141 1 4 16 | B1->B0 | 2323 3535 | 0 1 | (0 0) (1 1)
7553 04:40:49.061369 1 4 20 | B1->B0 | 3333 3636 | 1 1 | (1 1) (1 1)
7554 04:40:49.068205 1 4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7555 04:40:49.071395 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7556 04:40:49.074608 1 5 0 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
7557 04:40:49.081350 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7558 04:40:49.084487 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 1)
7559 04:40:49.088288 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
7560 04:40:49.091411 1 5 16 | B1->B0 | 3434 2a29 | 0 1 | (0 0) (0 0)
7561 04:40:49.097966 1 5 20 | B1->B0 | 2727 2626 | 0 0 | (1 0) (0 0)
7562 04:40:49.101195 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
7563 04:40:49.104742 1 5 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
7564 04:40:49.111726 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7565 04:40:49.114832 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7566 04:40:49.118116 1 6 8 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
7567 04:40:49.124875 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (1 1)
7568 04:40:49.127968 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7569 04:40:49.131477 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7570 04:40:49.137707 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (1 1)
7571 04:40:49.141244 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 04:40:49.144289 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 04:40:49.151263 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 04:40:49.154795 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7575 04:40:49.157868 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7576 04:40:49.164568 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7577 04:40:49.167652 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7578 04:40:49.170865 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7579 04:40:49.177724 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 04:40:49.181050 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 04:40:49.184265 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 04:40:49.191004 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 04:40:49.194145 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 04:40:49.197821 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 04:40:49.204588 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 04:40:49.207630 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 04:40:49.210974 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 04:40:49.214331 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 04:40:49.220931 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 04:40:49.224270 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7591 04:40:49.227674 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7592 04:40:49.234308 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7593 04:40:49.237885 Total UI for P1: 0, mck2ui 16
7594 04:40:49.240941 best dqsien dly found for B0: ( 1, 9, 10)
7595 04:40:49.244441 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7596 04:40:49.247390 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 04:40:49.250915 Total UI for P1: 0, mck2ui 16
7598 04:40:49.254359 best dqsien dly found for B1: ( 1, 9, 18)
7599 04:40:49.257678 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7600 04:40:49.260965 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7601 04:40:49.261055
7602 04:40:49.267481 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7603 04:40:49.270962 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7604 04:40:49.274739 [Gating] SW calibration Done
7605 04:40:49.274844 ==
7606 04:40:49.277906 Dram Type= 6, Freq= 0, CH_0, rank 0
7607 04:40:49.281028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7608 04:40:49.281111 ==
7609 04:40:49.281183 RX Vref Scan: 0
7610 04:40:49.281244
7611 04:40:49.284175 RX Vref 0 -> 0, step: 1
7612 04:40:49.284245
7613 04:40:49.287924 RX Delay 0 -> 252, step: 8
7614 04:40:49.290919 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7615 04:40:49.294221 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7616 04:40:49.297807 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7617 04:40:49.304487 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7618 04:40:49.307576 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7619 04:40:49.310787 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7620 04:40:49.313965 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7621 04:40:49.317620 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7622 04:40:49.324346 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7623 04:40:49.327179 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7624 04:40:49.330838 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7625 04:40:49.333815 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7626 04:40:49.337232 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7627 04:40:49.344096 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7628 04:40:49.347292 iDelay=200, Bit 14, Center 143 (96 ~ 191) 96
7629 04:40:49.350387 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7630 04:40:49.350472 ==
7631 04:40:49.354154 Dram Type= 6, Freq= 0, CH_0, rank 0
7632 04:40:49.357315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 04:40:49.357398 ==
7634 04:40:49.360463 DQS Delay:
7635 04:40:49.360550 DQS0 = 0, DQS1 = 0
7636 04:40:49.364076 DQM Delay:
7637 04:40:49.364226 DQM0 = 136, DQM1 = 130
7638 04:40:49.367206 DQ Delay:
7639 04:40:49.370647 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =131
7640 04:40:49.374295 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7641 04:40:49.377595 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7642 04:40:49.380477 DQ12 =135, DQ13 =139, DQ14 =143, DQ15 =135
7643 04:40:49.380572
7644 04:40:49.380638
7645 04:40:49.380716 ==
7646 04:40:49.384184 Dram Type= 6, Freq= 0, CH_0, rank 0
7647 04:40:49.387360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7648 04:40:49.387484 ==
7649 04:40:49.387584
7650 04:40:49.387717
7651 04:40:49.390387 TX Vref Scan disable
7652 04:40:49.394119 == TX Byte 0 ==
7653 04:40:49.397300 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7654 04:40:49.400477 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7655 04:40:49.404119 == TX Byte 1 ==
7656 04:40:49.407269 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7657 04:40:49.410399 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7658 04:40:49.410500 ==
7659 04:40:49.414080 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 04:40:49.420393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 04:40:49.420504 ==
7662 04:40:49.432751
7663 04:40:49.435658 TX Vref early break, caculate TX vref
7664 04:40:49.439171 TX Vref=16, minBit 0, minWin=22, winSum=377
7665 04:40:49.442816 TX Vref=18, minBit 0, minWin=23, winSum=385
7666 04:40:49.445471 TX Vref=20, minBit 1, minWin=24, winSum=398
7667 04:40:49.448972 TX Vref=22, minBit 3, minWin=24, winSum=406
7668 04:40:49.452558 TX Vref=24, minBit 0, minWin=25, winSum=413
7669 04:40:49.459020 TX Vref=26, minBit 1, minWin=25, winSum=418
7670 04:40:49.462231 TX Vref=28, minBit 1, minWin=24, winSum=424
7671 04:40:49.465796 TX Vref=30, minBit 1, minWin=24, winSum=414
7672 04:40:49.468876 TX Vref=32, minBit 6, minWin=23, winSum=402
7673 04:40:49.471972 TX Vref=34, minBit 1, minWin=22, winSum=394
7674 04:40:49.479030 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 26
7675 04:40:49.479120
7676 04:40:49.481961 Final TX Range 0 Vref 26
7677 04:40:49.482033
7678 04:40:49.482095 ==
7679 04:40:49.485614 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 04:40:49.488961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 04:40:49.489050 ==
7682 04:40:49.489117
7683 04:40:49.489178
7684 04:40:49.492449 TX Vref Scan disable
7685 04:40:49.498685 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7686 04:40:49.498770 == TX Byte 0 ==
7687 04:40:49.502376 u2DelayCellOfst[0]=10 cells (3 PI)
7688 04:40:49.505508 u2DelayCellOfst[1]=13 cells (4 PI)
7689 04:40:49.508567 u2DelayCellOfst[2]=10 cells (3 PI)
7690 04:40:49.512316 u2DelayCellOfst[3]=10 cells (3 PI)
7691 04:40:49.515424 u2DelayCellOfst[4]=6 cells (2 PI)
7692 04:40:49.518528 u2DelayCellOfst[5]=0 cells (0 PI)
7693 04:40:49.522172 u2DelayCellOfst[6]=16 cells (5 PI)
7694 04:40:49.525269 u2DelayCellOfst[7]=16 cells (5 PI)
7695 04:40:49.528869 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7696 04:40:49.532186 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7697 04:40:49.535433 == TX Byte 1 ==
7698 04:40:49.535530 u2DelayCellOfst[8]=3 cells (1 PI)
7699 04:40:49.539178 u2DelayCellOfst[9]=0 cells (0 PI)
7700 04:40:49.542188 u2DelayCellOfst[10]=10 cells (3 PI)
7701 04:40:49.545124 u2DelayCellOfst[11]=6 cells (2 PI)
7702 04:40:49.548758 u2DelayCellOfst[12]=13 cells (4 PI)
7703 04:40:49.552235 u2DelayCellOfst[13]=10 cells (3 PI)
7704 04:40:49.555494 u2DelayCellOfst[14]=16 cells (5 PI)
7705 04:40:49.558423 u2DelayCellOfst[15]=10 cells (3 PI)
7706 04:40:49.561825 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7707 04:40:49.568307 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7708 04:40:49.568397 DramC Write-DBI on
7709 04:40:49.568463 ==
7710 04:40:49.572015 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 04:40:49.575196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 04:40:49.578912 ==
7713 04:40:49.579021
7714 04:40:49.579142
7715 04:40:49.579204 TX Vref Scan disable
7716 04:40:49.581909 == TX Byte 0 ==
7717 04:40:49.585527 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7718 04:40:49.588571 == TX Byte 1 ==
7719 04:40:49.592202 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7720 04:40:49.595448 DramC Write-DBI off
7721 04:40:49.595584
7722 04:40:49.595652 [DATLAT]
7723 04:40:49.595744 Freq=1600, CH0 RK0
7724 04:40:49.595803
7725 04:40:49.598525 DATLAT Default: 0xf
7726 04:40:49.598634 0, 0xFFFF, sum = 0
7727 04:40:49.602351 1, 0xFFFF, sum = 0
7728 04:40:49.605386 2, 0xFFFF, sum = 0
7729 04:40:49.605498 3, 0xFFFF, sum = 0
7730 04:40:49.608504 4, 0xFFFF, sum = 0
7731 04:40:49.608603 5, 0xFFFF, sum = 0
7732 04:40:49.611686 6, 0xFFFF, sum = 0
7733 04:40:49.611789 7, 0xFFFF, sum = 0
7734 04:40:49.615507 8, 0xFFFF, sum = 0
7735 04:40:49.615652 9, 0xFFFF, sum = 0
7736 04:40:49.618570 10, 0xFFFF, sum = 0
7737 04:40:49.618654 11, 0xFFFF, sum = 0
7738 04:40:49.621806 12, 0xFFFF, sum = 0
7739 04:40:49.621895 13, 0xFFFF, sum = 0
7740 04:40:49.624842 14, 0x0, sum = 1
7741 04:40:49.624925 15, 0x0, sum = 2
7742 04:40:49.628748 16, 0x0, sum = 3
7743 04:40:49.628832 17, 0x0, sum = 4
7744 04:40:49.631707 best_step = 15
7745 04:40:49.631791
7746 04:40:49.631856 ==
7747 04:40:49.635191 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 04:40:49.638572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 04:40:49.638659 ==
7750 04:40:49.641647 RX Vref Scan: 1
7751 04:40:49.641745
7752 04:40:49.641809 Set Vref Range= 24 -> 127
7753 04:40:49.641870
7754 04:40:49.645935 RX Vref 24 -> 127, step: 1
7755 04:40:49.646113
7756 04:40:49.648322 RX Delay 19 -> 252, step: 4
7757 04:40:49.648449
7758 04:40:49.651638 Set Vref, RX VrefLevel [Byte0]: 24
7759 04:40:49.655216 [Byte1]: 24
7760 04:40:49.655386
7761 04:40:49.658218 Set Vref, RX VrefLevel [Byte0]: 25
7762 04:40:49.661587 [Byte1]: 25
7763 04:40:49.661701
7764 04:40:49.665139 Set Vref, RX VrefLevel [Byte0]: 26
7765 04:40:49.668529 [Byte1]: 26
7766 04:40:49.672609
7767 04:40:49.672703 Set Vref, RX VrefLevel [Byte0]: 27
7768 04:40:49.675409 [Byte1]: 27
7769 04:40:49.679989
7770 04:40:49.680094 Set Vref, RX VrefLevel [Byte0]: 28
7771 04:40:49.683301 [Byte1]: 28
7772 04:40:49.687226
7773 04:40:49.687358 Set Vref, RX VrefLevel [Byte0]: 29
7774 04:40:49.690906 [Byte1]: 29
7775 04:40:49.695539
7776 04:40:49.695645 Set Vref, RX VrefLevel [Byte0]: 30
7777 04:40:49.698317 [Byte1]: 30
7778 04:40:49.702494
7779 04:40:49.702652 Set Vref, RX VrefLevel [Byte0]: 31
7780 04:40:49.706008 [Byte1]: 31
7781 04:40:49.710285
7782 04:40:49.710398 Set Vref, RX VrefLevel [Byte0]: 32
7783 04:40:49.713329 [Byte1]: 32
7784 04:40:49.717785
7785 04:40:49.717919 Set Vref, RX VrefLevel [Byte0]: 33
7786 04:40:49.720884 [Byte1]: 33
7787 04:40:49.725236
7788 04:40:49.725319 Set Vref, RX VrefLevel [Byte0]: 34
7789 04:40:49.728542 [Byte1]: 34
7790 04:40:49.732678
7791 04:40:49.732766 Set Vref, RX VrefLevel [Byte0]: 35
7792 04:40:49.736331 [Byte1]: 35
7793 04:40:49.740723
7794 04:40:49.740802 Set Vref, RX VrefLevel [Byte0]: 36
7795 04:40:49.743855 [Byte1]: 36
7796 04:40:49.748312
7797 04:40:49.748389 Set Vref, RX VrefLevel [Byte0]: 37
7798 04:40:49.751337 [Byte1]: 37
7799 04:40:49.755712
7800 04:40:49.755795 Set Vref, RX VrefLevel [Byte0]: 38
7801 04:40:49.758961 [Byte1]: 38
7802 04:40:49.763214
7803 04:40:49.763294 Set Vref, RX VrefLevel [Byte0]: 39
7804 04:40:49.766224 [Byte1]: 39
7805 04:40:49.770877
7806 04:40:49.770998 Set Vref, RX VrefLevel [Byte0]: 40
7807 04:40:49.774263 [Byte1]: 40
7808 04:40:49.778356
7809 04:40:49.778477 Set Vref, RX VrefLevel [Byte0]: 41
7810 04:40:49.781291 [Byte1]: 41
7811 04:40:49.785593
7812 04:40:49.785672 Set Vref, RX VrefLevel [Byte0]: 42
7813 04:40:49.789241 [Byte1]: 42
7814 04:40:49.793292
7815 04:40:49.793400 Set Vref, RX VrefLevel [Byte0]: 43
7816 04:40:49.796926 [Byte1]: 43
7817 04:40:49.801221
7818 04:40:49.801326 Set Vref, RX VrefLevel [Byte0]: 44
7819 04:40:49.804299 [Byte1]: 44
7820 04:40:49.808855
7821 04:40:49.808969 Set Vref, RX VrefLevel [Byte0]: 45
7822 04:40:49.812168 [Byte1]: 45
7823 04:40:49.816045
7824 04:40:49.816133 Set Vref, RX VrefLevel [Byte0]: 46
7825 04:40:49.819650 [Byte1]: 46
7826 04:40:49.823978
7827 04:40:49.824080 Set Vref, RX VrefLevel [Byte0]: 47
7828 04:40:49.826976 [Byte1]: 47
7829 04:40:49.831291
7830 04:40:49.831396 Set Vref, RX VrefLevel [Byte0]: 48
7831 04:40:49.834435 [Byte1]: 48
7832 04:40:49.838688
7833 04:40:49.838787 Set Vref, RX VrefLevel [Byte0]: 49
7834 04:40:49.842473 [Byte1]: 49
7835 04:40:49.846264
7836 04:40:49.846370 Set Vref, RX VrefLevel [Byte0]: 50
7837 04:40:49.849996 [Byte1]: 50
7838 04:40:49.853918
7839 04:40:49.854023 Set Vref, RX VrefLevel [Byte0]: 51
7840 04:40:49.857486 [Byte1]: 51
7841 04:40:49.861965
7842 04:40:49.862074 Set Vref, RX VrefLevel [Byte0]: 52
7843 04:40:49.864934 [Byte1]: 52
7844 04:40:49.869513
7845 04:40:49.869606 Set Vref, RX VrefLevel [Byte0]: 53
7846 04:40:49.872156 [Byte1]: 53
7847 04:40:49.876568
7848 04:40:49.876688 Set Vref, RX VrefLevel [Byte0]: 54
7849 04:40:49.880150 [Byte1]: 54
7850 04:40:49.884204
7851 04:40:49.884291 Set Vref, RX VrefLevel [Byte0]: 55
7852 04:40:49.887759 [Byte1]: 55
7853 04:40:49.891913
7854 04:40:49.892002 Set Vref, RX VrefLevel [Byte0]: 56
7855 04:40:49.895021 [Byte1]: 56
7856 04:40:49.899221
7857 04:40:49.899305 Set Vref, RX VrefLevel [Byte0]: 57
7858 04:40:49.902724 [Byte1]: 57
7859 04:40:49.907061
7860 04:40:49.907168 Set Vref, RX VrefLevel [Byte0]: 58
7861 04:40:49.910671 [Byte1]: 58
7862 04:40:49.914927
7863 04:40:49.915032 Set Vref, RX VrefLevel [Byte0]: 59
7864 04:40:49.917947 [Byte1]: 59
7865 04:40:49.922066
7866 04:40:49.922177 Set Vref, RX VrefLevel [Byte0]: 60
7867 04:40:49.925437 [Byte1]: 60
7868 04:40:49.929737
7869 04:40:49.929845 Set Vref, RX VrefLevel [Byte0]: 61
7870 04:40:49.933079 [Byte1]: 61
7871 04:40:49.937538
7872 04:40:49.937645 Set Vref, RX VrefLevel [Byte0]: 62
7873 04:40:49.940718 [Byte1]: 62
7874 04:40:49.944785
7875 04:40:49.944872 Set Vref, RX VrefLevel [Byte0]: 63
7876 04:40:49.948679 [Byte1]: 63
7877 04:40:49.952370
7878 04:40:49.952478 Set Vref, RX VrefLevel [Byte0]: 64
7879 04:40:49.955541 [Byte1]: 64
7880 04:40:49.959999
7881 04:40:49.960089 Set Vref, RX VrefLevel [Byte0]: 65
7882 04:40:49.963570 [Byte1]: 65
7883 04:40:49.967813
7884 04:40:49.967934 Set Vref, RX VrefLevel [Byte0]: 66
7885 04:40:49.970853 [Byte1]: 66
7886 04:40:49.975185
7887 04:40:49.975293 Set Vref, RX VrefLevel [Byte0]: 67
7888 04:40:49.979055 [Byte1]: 67
7889 04:40:49.982640
7890 04:40:49.982759 Set Vref, RX VrefLevel [Byte0]: 68
7891 04:40:49.986254 [Byte1]: 68
7892 04:40:49.990262
7893 04:40:49.990365 Set Vref, RX VrefLevel [Byte0]: 69
7894 04:40:49.993715 [Byte1]: 69
7895 04:40:49.997819
7896 04:40:49.997926 Set Vref, RX VrefLevel [Byte0]: 70
7897 04:40:50.001288 [Byte1]: 70
7898 04:40:50.005532
7899 04:40:50.005634 Set Vref, RX VrefLevel [Byte0]: 71
7900 04:40:50.008973 [Byte1]: 71
7901 04:40:50.012936
7902 04:40:50.013021 Set Vref, RX VrefLevel [Byte0]: 72
7903 04:40:50.016604 [Byte1]: 72
7904 04:40:50.020411
7905 04:40:50.020517 Final RX Vref Byte 0 = 60 to rank0
7906 04:40:50.023571 Final RX Vref Byte 1 = 61 to rank0
7907 04:40:50.027323 Final RX Vref Byte 0 = 60 to rank1
7908 04:40:50.030464 Final RX Vref Byte 1 = 61 to rank1==
7909 04:40:50.034188 Dram Type= 6, Freq= 0, CH_0, rank 0
7910 04:40:50.040613 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7911 04:40:50.040698 ==
7912 04:40:50.040774 DQS Delay:
7913 04:40:50.040846 DQS0 = 0, DQS1 = 0
7914 04:40:50.043846 DQM Delay:
7915 04:40:50.043918 DQM0 = 134, DQM1 = 128
7916 04:40:50.046998 DQ Delay:
7917 04:40:50.050403 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134
7918 04:40:50.053767 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7919 04:40:50.057456 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
7920 04:40:50.060562 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =136
7921 04:40:50.060663
7922 04:40:50.060728
7923 04:40:50.060789
7924 04:40:50.063613 [DramC_TX_OE_Calibration] TA2
7925 04:40:50.067317 Original DQ_B0 (3 6) =30, OEN = 27
7926 04:40:50.070451 Original DQ_B1 (3 6) =30, OEN = 27
7927 04:40:50.073606 24, 0x0, End_B0=24 End_B1=24
7928 04:40:50.073721 25, 0x0, End_B0=25 End_B1=25
7929 04:40:50.077331 26, 0x0, End_B0=26 End_B1=26
7930 04:40:50.080352 27, 0x0, End_B0=27 End_B1=27
7931 04:40:50.083993 28, 0x0, End_B0=28 End_B1=28
7932 04:40:50.084101 29, 0x0, End_B0=29 End_B1=29
7933 04:40:50.087467 30, 0x0, End_B0=30 End_B1=30
7934 04:40:50.090598 31, 0x4141, End_B0=30 End_B1=30
7935 04:40:50.093722 Byte0 end_step=30 best_step=27
7936 04:40:50.097219 Byte1 end_step=30 best_step=27
7937 04:40:50.100445 Byte0 TX OE(2T, 0.5T) = (3, 3)
7938 04:40:50.100552 Byte1 TX OE(2T, 0.5T) = (3, 3)
7939 04:40:50.100646
7940 04:40:50.103979
7941 04:40:50.110824 [DQSOSCAuto] RK0, (LSB)MR18= 0x231e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
7942 04:40:50.113983 CH0 RK0: MR19=303, MR18=231E
7943 04:40:50.120530 CH0_RK0: MR19=0x303, MR18=0x231E, DQSOSC=392, MR23=63, INC=24, DEC=16
7944 04:40:50.120649
7945 04:40:50.123949 ----->DramcWriteLeveling(PI) begin...
7946 04:40:50.124060 ==
7947 04:40:50.126954 Dram Type= 6, Freq= 0, CH_0, rank 1
7948 04:40:50.130704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7949 04:40:50.130790 ==
7950 04:40:50.133873 Write leveling (Byte 0): 36 => 36
7951 04:40:50.137083 Write leveling (Byte 1): 29 => 29
7952 04:40:50.140206 DramcWriteLeveling(PI) end<-----
7953 04:40:50.140288
7954 04:40:50.140352 ==
7955 04:40:50.143907 Dram Type= 6, Freq= 0, CH_0, rank 1
7956 04:40:50.147013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7957 04:40:50.147121 ==
7958 04:40:50.150268 [Gating] SW mode calibration
7959 04:40:50.156744 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7960 04:40:50.163507 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7961 04:40:50.166833 1 4 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7962 04:40:50.170356 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7963 04:40:50.176541 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7964 04:40:50.180444 1 4 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7965 04:40:50.183490 1 4 16 | B1->B0 | 2c2c 3636 | 1 0 | (1 1) (0 0)
7966 04:40:50.189991 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7967 04:40:50.193637 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7968 04:40:50.196721 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7969 04:40:50.203491 1 5 0 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7970 04:40:50.207043 1 5 4 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7971 04:40:50.210235 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7972 04:40:50.216662 1 5 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
7973 04:40:50.220133 1 5 16 | B1->B0 | 2e2e 2929 | 0 0 | (1 0) (0 0)
7974 04:40:50.223152 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7975 04:40:50.229811 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7976 04:40:50.233381 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7977 04:40:50.236528 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7978 04:40:50.243431 1 6 4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7979 04:40:50.246526 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7980 04:40:50.249597 1 6 12 | B1->B0 | 2727 3837 | 0 1 | (0 0) (1 1)
7981 04:40:50.256331 1 6 16 | B1->B0 | 3f3f 4645 | 0 1 | (0 0) (0 0)
7982 04:40:50.260044 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7983 04:40:50.262951 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7984 04:40:50.269489 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7985 04:40:50.273185 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7986 04:40:50.276160 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 04:40:50.282869 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7988 04:40:50.286692 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7989 04:40:50.289653 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7990 04:40:50.296490 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 04:40:50.299376 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 04:40:50.303068 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 04:40:50.306159 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 04:40:50.312953 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 04:40:50.315989 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 04:40:50.319870 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 04:40:50.326344 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 04:40:50.329841 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 04:40:50.333045 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 04:40:50.339523 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 04:40:50.342543 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 04:40:50.346396 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 04:40:50.352555 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 04:40:50.356362 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8005 04:40:50.359499 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8006 04:40:50.366231 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 04:40:50.366348 Total UI for P1: 0, mck2ui 16
8008 04:40:50.372720 best dqsien dly found for B0: ( 1, 9, 14)
8009 04:40:50.372808 Total UI for P1: 0, mck2ui 16
8010 04:40:50.379547 best dqsien dly found for B1: ( 1, 9, 14)
8011 04:40:50.382807 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8012 04:40:50.386311 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8013 04:40:50.386419
8014 04:40:50.389375 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8015 04:40:50.392829 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8016 04:40:50.396313 [Gating] SW calibration Done
8017 04:40:50.396400 ==
8018 04:40:50.399449 Dram Type= 6, Freq= 0, CH_0, rank 1
8019 04:40:50.402437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8020 04:40:50.402517 ==
8021 04:40:50.406160 RX Vref Scan: 0
8022 04:40:50.406238
8023 04:40:50.406306 RX Vref 0 -> 0, step: 1
8024 04:40:50.406370
8025 04:40:50.409140 RX Delay 0 -> 252, step: 8
8026 04:40:50.412641 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8027 04:40:50.419537 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8028 04:40:50.422693 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8029 04:40:50.425893 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8030 04:40:50.429604 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8031 04:40:50.432420 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8032 04:40:50.435965 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8033 04:40:50.442491 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8034 04:40:50.446187 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8035 04:40:50.449254 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8036 04:40:50.452338 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8037 04:40:50.459217 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8038 04:40:50.462321 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8039 04:40:50.465874 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8040 04:40:50.469060 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8041 04:40:50.472152 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8042 04:40:50.475821 ==
8043 04:40:50.475924 Dram Type= 6, Freq= 0, CH_0, rank 1
8044 04:40:50.482065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8045 04:40:50.482201 ==
8046 04:40:50.482312 DQS Delay:
8047 04:40:50.485883 DQS0 = 0, DQS1 = 0
8048 04:40:50.485973 DQM Delay:
8049 04:40:50.488947 DQM0 = 137, DQM1 = 130
8050 04:40:50.489027 DQ Delay:
8051 04:40:50.492027 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8052 04:40:50.495673 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8053 04:40:50.498720 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =123
8054 04:40:50.502322 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8055 04:40:50.502414
8056 04:40:50.502480
8057 04:40:50.502541 ==
8058 04:40:50.505227 Dram Type= 6, Freq= 0, CH_0, rank 1
8059 04:40:50.512043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8060 04:40:50.512138 ==
8061 04:40:50.512204
8062 04:40:50.512269
8063 04:40:50.512328 TX Vref Scan disable
8064 04:40:50.515622 == TX Byte 0 ==
8065 04:40:50.519176 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8066 04:40:50.522536 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8067 04:40:50.525598 == TX Byte 1 ==
8068 04:40:50.529296 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8069 04:40:50.532560 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8070 04:40:50.536120 ==
8071 04:40:50.539112 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 04:40:50.542082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 04:40:50.542159 ==
8074 04:40:50.555408
8075 04:40:50.558399 TX Vref early break, caculate TX vref
8076 04:40:50.562256 TX Vref=16, minBit 0, minWin=23, winSum=388
8077 04:40:50.565347 TX Vref=18, minBit 1, minWin=23, winSum=392
8078 04:40:50.569032 TX Vref=20, minBit 0, minWin=24, winSum=401
8079 04:40:50.572266 TX Vref=22, minBit 0, minWin=24, winSum=410
8080 04:40:50.575452 TX Vref=24, minBit 1, minWin=24, winSum=420
8081 04:40:50.582038 TX Vref=26, minBit 3, minWin=25, winSum=428
8082 04:40:50.585076 TX Vref=28, minBit 7, minWin=25, winSum=426
8083 04:40:50.588865 TX Vref=30, minBit 0, minWin=25, winSum=419
8084 04:40:50.592024 TX Vref=32, minBit 0, minWin=25, winSum=410
8085 04:40:50.595157 TX Vref=34, minBit 0, minWin=24, winSum=400
8086 04:40:50.602174 [TxChooseVref] Worse bit 3, Min win 25, Win sum 428, Final Vref 26
8087 04:40:50.602267
8088 04:40:50.605229 Final TX Range 0 Vref 26
8089 04:40:50.605317
8090 04:40:50.605405 ==
8091 04:40:50.608357 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 04:40:50.612208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 04:40:50.612310 ==
8094 04:40:50.612398
8095 04:40:50.612479
8096 04:40:50.615350 TX Vref Scan disable
8097 04:40:50.621795 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8098 04:40:50.621888 == TX Byte 0 ==
8099 04:40:50.625157 u2DelayCellOfst[0]=13 cells (4 PI)
8100 04:40:50.628347 u2DelayCellOfst[1]=16 cells (5 PI)
8101 04:40:50.631348 u2DelayCellOfst[2]=10 cells (3 PI)
8102 04:40:50.634821 u2DelayCellOfst[3]=10 cells (3 PI)
8103 04:40:50.638613 u2DelayCellOfst[4]=10 cells (3 PI)
8104 04:40:50.641574 u2DelayCellOfst[5]=0 cells (0 PI)
8105 04:40:50.645259 u2DelayCellOfst[6]=16 cells (5 PI)
8106 04:40:50.648416 u2DelayCellOfst[7]=16 cells (5 PI)
8107 04:40:50.651443 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8108 04:40:50.654873 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8109 04:40:50.658209 == TX Byte 1 ==
8110 04:40:50.661639 u2DelayCellOfst[8]=0 cells (0 PI)
8111 04:40:50.661727 u2DelayCellOfst[9]=0 cells (0 PI)
8112 04:40:50.664476 u2DelayCellOfst[10]=6 cells (2 PI)
8113 04:40:50.668036 u2DelayCellOfst[11]=6 cells (2 PI)
8114 04:40:50.671626 u2DelayCellOfst[12]=10 cells (3 PI)
8115 04:40:50.674809 u2DelayCellOfst[13]=10 cells (3 PI)
8116 04:40:50.677899 u2DelayCellOfst[14]=13 cells (4 PI)
8117 04:40:50.681039 u2DelayCellOfst[15]=10 cells (3 PI)
8118 04:40:50.684734 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8119 04:40:50.691558 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8120 04:40:50.691698 DramC Write-DBI on
8121 04:40:50.691797 ==
8122 04:40:50.694692 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 04:40:50.700845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 04:40:50.700931 ==
8125 04:40:50.700998
8126 04:40:50.701060
8127 04:40:50.701119 TX Vref Scan disable
8128 04:40:50.705287 == TX Byte 0 ==
8129 04:40:50.708425 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8130 04:40:50.711395 == TX Byte 1 ==
8131 04:40:50.715166 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8132 04:40:50.718340 DramC Write-DBI off
8133 04:40:50.718425
8134 04:40:50.718491 [DATLAT]
8135 04:40:50.718553 Freq=1600, CH0 RK1
8136 04:40:50.718612
8137 04:40:50.721510 DATLAT Default: 0xf
8138 04:40:50.721594 0, 0xFFFF, sum = 0
8139 04:40:50.725392 1, 0xFFFF, sum = 0
8140 04:40:50.728262 2, 0xFFFF, sum = 0
8141 04:40:50.728348 3, 0xFFFF, sum = 0
8142 04:40:50.731449 4, 0xFFFF, sum = 0
8143 04:40:50.731546 5, 0xFFFF, sum = 0
8144 04:40:50.735104 6, 0xFFFF, sum = 0
8145 04:40:50.735190 7, 0xFFFF, sum = 0
8146 04:40:50.738042 8, 0xFFFF, sum = 0
8147 04:40:50.738135 9, 0xFFFF, sum = 0
8148 04:40:50.741861 10, 0xFFFF, sum = 0
8149 04:40:50.741977 11, 0xFFFF, sum = 0
8150 04:40:50.745004 12, 0xFFFF, sum = 0
8151 04:40:50.745111 13, 0xFFFF, sum = 0
8152 04:40:50.748034 14, 0x0, sum = 1
8153 04:40:50.748112 15, 0x0, sum = 2
8154 04:40:50.751307 16, 0x0, sum = 3
8155 04:40:50.751415 17, 0x0, sum = 4
8156 04:40:50.754810 best_step = 15
8157 04:40:50.754896
8158 04:40:50.754961 ==
8159 04:40:50.758494 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 04:40:50.761189 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 04:40:50.761269 ==
8162 04:40:50.764542 RX Vref Scan: 0
8163 04:40:50.764650
8164 04:40:50.764719 RX Vref 0 -> 0, step: 1
8165 04:40:50.764818
8166 04:40:50.767857 RX Delay 19 -> 252, step: 4
8167 04:40:50.771263 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8168 04:40:50.778174 iDelay=195, Bit 1, Center 136 (91 ~ 182) 92
8169 04:40:50.781514 iDelay=195, Bit 2, Center 130 (79 ~ 182) 104
8170 04:40:50.784502 iDelay=195, Bit 3, Center 134 (83 ~ 186) 104
8171 04:40:50.787663 iDelay=195, Bit 4, Center 136 (87 ~ 186) 100
8172 04:40:50.791355 iDelay=195, Bit 5, Center 124 (71 ~ 178) 108
8173 04:40:50.797740 iDelay=195, Bit 6, Center 140 (91 ~ 190) 100
8174 04:40:50.801456 iDelay=195, Bit 7, Center 142 (91 ~ 194) 104
8175 04:40:50.804400 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8176 04:40:50.808273 iDelay=195, Bit 9, Center 116 (63 ~ 170) 108
8177 04:40:50.811377 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8178 04:40:50.818248 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
8179 04:40:50.821388 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8180 04:40:50.824618 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8181 04:40:50.827701 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8182 04:40:50.831409 iDelay=195, Bit 15, Center 136 (87 ~ 186) 100
8183 04:40:50.834497 ==
8184 04:40:50.837649 Dram Type= 6, Freq= 0, CH_0, rank 1
8185 04:40:50.840920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8186 04:40:50.841006 ==
8187 04:40:50.841074 DQS Delay:
8188 04:40:50.844634 DQS0 = 0, DQS1 = 0
8189 04:40:50.844719 DQM Delay:
8190 04:40:50.847701 DQM0 = 134, DQM1 = 127
8191 04:40:50.847786 DQ Delay:
8192 04:40:50.851319 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =134
8193 04:40:50.854361 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =142
8194 04:40:50.858014 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8195 04:40:50.860965 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8196 04:40:50.861051
8197 04:40:50.861116
8198 04:40:50.861177
8199 04:40:50.864441 [DramC_TX_OE_Calibration] TA2
8200 04:40:50.867983 Original DQ_B0 (3 6) =30, OEN = 27
8201 04:40:50.870779 Original DQ_B1 (3 6) =30, OEN = 27
8202 04:40:50.874196 24, 0x0, End_B0=24 End_B1=24
8203 04:40:50.877812 25, 0x0, End_B0=25 End_B1=25
8204 04:40:50.877924 26, 0x0, End_B0=26 End_B1=26
8205 04:40:50.880938 27, 0x0, End_B0=27 End_B1=27
8206 04:40:50.884179 28, 0x0, End_B0=28 End_B1=28
8207 04:40:50.887824 29, 0x0, End_B0=29 End_B1=29
8208 04:40:50.887913 30, 0x0, End_B0=30 End_B1=30
8209 04:40:50.891068 31, 0x4545, End_B0=30 End_B1=30
8210 04:40:50.894284 Byte0 end_step=30 best_step=27
8211 04:40:50.897842 Byte1 end_step=30 best_step=27
8212 04:40:50.901072 Byte0 TX OE(2T, 0.5T) = (3, 3)
8213 04:40:50.904346 Byte1 TX OE(2T, 0.5T) = (3, 3)
8214 04:40:50.904444
8215 04:40:50.904523
8216 04:40:50.910734 [DQSOSCAuto] RK1, (LSB)MR18= 0x2109, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8217 04:40:50.914367 CH0 RK1: MR19=303, MR18=2109
8218 04:40:50.921158 CH0_RK1: MR19=0x303, MR18=0x2109, DQSOSC=393, MR23=63, INC=23, DEC=15
8219 04:40:50.924275 [RxdqsGatingPostProcess] freq 1600
8220 04:40:50.927359 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8221 04:40:50.931130 best DQS0 dly(2T, 0.5T) = (1, 1)
8222 04:40:50.934271 best DQS1 dly(2T, 0.5T) = (1, 1)
8223 04:40:50.937286 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8224 04:40:50.940958 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8225 04:40:50.944155 best DQS0 dly(2T, 0.5T) = (1, 1)
8226 04:40:50.947308 best DQS1 dly(2T, 0.5T) = (1, 1)
8227 04:40:50.950886 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8228 04:40:50.954218 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8229 04:40:50.957129 Pre-setting of DQS Precalculation
8230 04:40:50.960279 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8231 04:40:50.960365 ==
8232 04:40:50.964146 Dram Type= 6, Freq= 0, CH_1, rank 0
8233 04:40:50.970921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8234 04:40:50.971026 ==
8235 04:40:50.973834 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8236 04:40:50.980506 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8237 04:40:50.983702 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8238 04:40:50.990335 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8239 04:40:50.997766 [CA 0] Center 41 (12~71) winsize 60
8240 04:40:51.001346 [CA 1] Center 41 (12~71) winsize 60
8241 04:40:51.004826 [CA 2] Center 38 (9~68) winsize 60
8242 04:40:51.007700 [CA 3] Center 37 (8~67) winsize 60
8243 04:40:51.011553 [CA 4] Center 38 (9~67) winsize 59
8244 04:40:51.014787 [CA 5] Center 37 (8~66) winsize 59
8245 04:40:51.014894
8246 04:40:51.017961 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8247 04:40:51.018079
8248 04:40:51.021335 [CATrainingPosCal] consider 1 rank data
8249 04:40:51.024803 u2DelayCellTimex100 = 290/100 ps
8250 04:40:51.027947 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8251 04:40:51.035025 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8252 04:40:51.038143 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8253 04:40:51.041315 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8254 04:40:51.044990 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8255 04:40:51.048231 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8256 04:40:51.048317
8257 04:40:51.051253 CA PerBit enable=1, Macro0, CA PI delay=37
8258 04:40:51.051368
8259 04:40:51.054924 [CBTSetCACLKResult] CA Dly = 37
8260 04:40:51.055040 CS Dly: 10 (0~41)
8261 04:40:51.061102 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8262 04:40:51.064917 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8263 04:40:51.065032 ==
8264 04:40:51.068108 Dram Type= 6, Freq= 0, CH_1, rank 1
8265 04:40:51.071284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8266 04:40:51.071390 ==
8267 04:40:51.077962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8268 04:40:51.081127 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8269 04:40:51.087971 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8270 04:40:51.091513 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8271 04:40:51.101295 [CA 0] Center 42 (12~72) winsize 61
8272 04:40:51.104463 [CA 1] Center 41 (12~71) winsize 60
8273 04:40:51.108256 [CA 2] Center 38 (9~68) winsize 60
8274 04:40:51.111429 [CA 3] Center 37 (8~67) winsize 60
8275 04:40:51.114532 [CA 4] Center 38 (8~68) winsize 61
8276 04:40:51.117527 [CA 5] Center 37 (8~67) winsize 60
8277 04:40:51.117609
8278 04:40:51.121165 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8279 04:40:51.121273
8280 04:40:51.124234 [CATrainingPosCal] consider 2 rank data
8281 04:40:51.127701 u2DelayCellTimex100 = 290/100 ps
8282 04:40:51.131450 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8283 04:40:51.137523 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8284 04:40:51.141137 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8285 04:40:51.144172 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8286 04:40:51.147503 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8287 04:40:51.151143 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8288 04:40:51.151265
8289 04:40:51.154429 CA PerBit enable=1, Macro0, CA PI delay=37
8290 04:40:51.154546
8291 04:40:51.157812 [CBTSetCACLKResult] CA Dly = 37
8292 04:40:51.160889 CS Dly: 11 (0~44)
8293 04:40:51.164613 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8294 04:40:51.167722 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8295 04:40:51.167814
8296 04:40:51.170835 ----->DramcWriteLeveling(PI) begin...
8297 04:40:51.170907 ==
8298 04:40:51.174550 Dram Type= 6, Freq= 0, CH_1, rank 0
8299 04:40:51.177542 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 04:40:51.180616 ==
8301 04:40:51.180694 Write leveling (Byte 0): 25 => 25
8302 04:40:51.184336 Write leveling (Byte 1): 27 => 27
8303 04:40:51.187349 DramcWriteLeveling(PI) end<-----
8304 04:40:51.187464
8305 04:40:51.187576 ==
8306 04:40:51.190983 Dram Type= 6, Freq= 0, CH_1, rank 0
8307 04:40:51.197719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 04:40:51.197836 ==
8309 04:40:51.200909 [Gating] SW mode calibration
8310 04:40:51.207858 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8311 04:40:51.210798 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8312 04:40:51.217727 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8313 04:40:51.220775 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8314 04:40:51.224388 1 4 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8315 04:40:51.230666 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8316 04:40:51.234476 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 04:40:51.237355 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 04:40:51.241234 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 04:40:51.247502 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 04:40:51.250607 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8321 04:40:51.254169 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8322 04:40:51.260657 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
8323 04:40:51.264014 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
8324 04:40:51.267446 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 04:40:51.273988 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 04:40:51.276974 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 04:40:51.280698 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 04:40:51.287383 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 04:40:51.290519 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 04:40:51.293695 1 6 8 | B1->B0 | 2424 3d3d | 1 0 | (0 0) (0 0)
8331 04:40:51.300351 1 6 12 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
8332 04:40:51.303922 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 04:40:51.307062 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 04:40:51.313870 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 04:40:51.317010 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 04:40:51.320769 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 04:40:51.326781 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 04:40:51.330581 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8339 04:40:51.333632 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8340 04:40:51.340536 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 04:40:51.343655 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 04:40:51.346791 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 04:40:51.353700 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 04:40:51.356969 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 04:40:51.360477 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 04:40:51.367225 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 04:40:51.370389 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 04:40:51.373617 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 04:40:51.380307 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 04:40:51.383627 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 04:40:51.386804 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 04:40:51.390398 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 04:40:51.396538 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 04:40:51.400345 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8355 04:40:51.403479 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8356 04:40:51.410077 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 04:40:51.413791 Total UI for P1: 0, mck2ui 16
8358 04:40:51.416867 best dqsien dly found for B0: ( 1, 9, 12)
8359 04:40:51.420031 Total UI for P1: 0, mck2ui 16
8360 04:40:51.423729 best dqsien dly found for B1: ( 1, 9, 10)
8361 04:40:51.426568 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8362 04:40:51.430068 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8363 04:40:51.430180
8364 04:40:51.433650 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8365 04:40:51.436841 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8366 04:40:51.439964 [Gating] SW calibration Done
8367 04:40:51.440052 ==
8368 04:40:51.443556 Dram Type= 6, Freq= 0, CH_1, rank 0
8369 04:40:51.446606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 04:40:51.446699 ==
8371 04:40:51.450310 RX Vref Scan: 0
8372 04:40:51.450399
8373 04:40:51.450467 RX Vref 0 -> 0, step: 1
8374 04:40:51.453557
8375 04:40:51.453643 RX Delay 0 -> 252, step: 8
8376 04:40:51.456557 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8377 04:40:51.463301 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8378 04:40:51.466340 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8379 04:40:51.469994 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8380 04:40:51.473029 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8381 04:40:51.476739 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8382 04:40:51.482883 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8383 04:40:51.486696 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8384 04:40:51.489688 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8385 04:40:51.493353 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8386 04:40:51.496352 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8387 04:40:51.503010 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8388 04:40:51.506160 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8389 04:40:51.509358 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8390 04:40:51.512883 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8391 04:40:51.519908 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8392 04:40:51.520007 ==
8393 04:40:51.523035 Dram Type= 6, Freq= 0, CH_1, rank 0
8394 04:40:51.526327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8395 04:40:51.526447 ==
8396 04:40:51.526551 DQS Delay:
8397 04:40:51.529782 DQS0 = 0, DQS1 = 0
8398 04:40:51.529900 DQM Delay:
8399 04:40:51.533030 DQM0 = 136, DQM1 = 132
8400 04:40:51.533144 DQ Delay:
8401 04:40:51.536532 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8402 04:40:51.539360 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8403 04:40:51.542783 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8404 04:40:51.546661 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8405 04:40:51.546750
8406 04:40:51.546835
8407 04:40:51.549510 ==
8408 04:40:51.549624 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 04:40:51.556505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 04:40:51.556606 ==
8411 04:40:51.556675
8412 04:40:51.556741
8413 04:40:51.559513 TX Vref Scan disable
8414 04:40:51.559602 == TX Byte 0 ==
8415 04:40:51.562731 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8416 04:40:51.569235 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8417 04:40:51.569360 == TX Byte 1 ==
8418 04:40:51.572887 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8419 04:40:51.579652 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8420 04:40:51.579779 ==
8421 04:40:51.582752 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 04:40:51.585938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 04:40:51.586051 ==
8424 04:40:51.598493
8425 04:40:51.602228 TX Vref early break, caculate TX vref
8426 04:40:51.605288 TX Vref=16, minBit 1, minWin=22, winSum=378
8427 04:40:51.608945 TX Vref=18, minBit 1, minWin=23, winSum=388
8428 04:40:51.611841 TX Vref=20, minBit 0, minWin=24, winSum=400
8429 04:40:51.615256 TX Vref=22, minBit 0, minWin=24, winSum=406
8430 04:40:51.618738 TX Vref=24, minBit 0, minWin=25, winSum=420
8431 04:40:51.625320 TX Vref=26, minBit 0, minWin=25, winSum=424
8432 04:40:51.628553 TX Vref=28, minBit 0, minWin=26, winSum=430
8433 04:40:51.631942 TX Vref=30, minBit 0, minWin=25, winSum=420
8434 04:40:51.634906 TX Vref=32, minBit 0, minWin=25, winSum=416
8435 04:40:51.638619 TX Vref=34, minBit 0, minWin=24, winSum=407
8436 04:40:51.645380 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8437 04:40:51.645513
8438 04:40:51.648256 Final TX Range 0 Vref 28
8439 04:40:51.648364
8440 04:40:51.648470 ==
8441 04:40:51.651727 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 04:40:51.654904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 04:40:51.654986 ==
8444 04:40:51.655088
8445 04:40:51.655178
8446 04:40:51.658294 TX Vref Scan disable
8447 04:40:51.664873 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8448 04:40:51.665001 == TX Byte 0 ==
8449 04:40:51.668564 u2DelayCellOfst[0]=20 cells (6 PI)
8450 04:40:51.671754 u2DelayCellOfst[1]=13 cells (4 PI)
8451 04:40:51.674755 u2DelayCellOfst[2]=0 cells (0 PI)
8452 04:40:51.678427 u2DelayCellOfst[3]=10 cells (3 PI)
8453 04:40:51.681438 u2DelayCellOfst[4]=10 cells (3 PI)
8454 04:40:51.684535 u2DelayCellOfst[5]=20 cells (6 PI)
8455 04:40:51.688275 u2DelayCellOfst[6]=20 cells (6 PI)
8456 04:40:51.691454 u2DelayCellOfst[7]=10 cells (3 PI)
8457 04:40:51.694483 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8458 04:40:51.698359 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8459 04:40:51.701413 == TX Byte 1 ==
8460 04:40:51.704504 u2DelayCellOfst[8]=0 cells (0 PI)
8461 04:40:51.704583 u2DelayCellOfst[9]=3 cells (1 PI)
8462 04:40:51.708051 u2DelayCellOfst[10]=13 cells (4 PI)
8463 04:40:51.711152 u2DelayCellOfst[11]=3 cells (1 PI)
8464 04:40:51.714249 u2DelayCellOfst[12]=16 cells (5 PI)
8465 04:40:51.718001 u2DelayCellOfst[13]=16 cells (5 PI)
8466 04:40:51.721119 u2DelayCellOfst[14]=16 cells (5 PI)
8467 04:40:51.724261 u2DelayCellOfst[15]=16 cells (5 PI)
8468 04:40:51.728128 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8469 04:40:51.734221 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8470 04:40:51.734343 DramC Write-DBI on
8471 04:40:51.734457 ==
8472 04:40:51.737782 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 04:40:51.744504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 04:40:51.744612 ==
8475 04:40:51.744690
8476 04:40:51.744753
8477 04:40:51.744813 TX Vref Scan disable
8478 04:40:51.748365 == TX Byte 0 ==
8479 04:40:51.751343 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8480 04:40:51.754589 == TX Byte 1 ==
8481 04:40:51.758301 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8482 04:40:51.758464 DramC Write-DBI off
8483 04:40:51.761816
8484 04:40:51.761954 [DATLAT]
8485 04:40:51.762040 Freq=1600, CH1 RK0
8486 04:40:51.762109
8487 04:40:51.764786 DATLAT Default: 0xf
8488 04:40:51.764900 0, 0xFFFF, sum = 0
8489 04:40:51.768539 1, 0xFFFF, sum = 0
8490 04:40:51.768632 2, 0xFFFF, sum = 0
8491 04:40:51.771416 3, 0xFFFF, sum = 0
8492 04:40:51.774803 4, 0xFFFF, sum = 0
8493 04:40:51.774890 5, 0xFFFF, sum = 0
8494 04:40:51.778138 6, 0xFFFF, sum = 0
8495 04:40:51.778235 7, 0xFFFF, sum = 0
8496 04:40:51.781468 8, 0xFFFF, sum = 0
8497 04:40:51.781554 9, 0xFFFF, sum = 0
8498 04:40:51.784889 10, 0xFFFF, sum = 0
8499 04:40:51.785018 11, 0xFFFF, sum = 0
8500 04:40:51.787935 12, 0xFFFF, sum = 0
8501 04:40:51.788022 13, 0xFFFF, sum = 0
8502 04:40:51.791705 14, 0x0, sum = 1
8503 04:40:51.791792 15, 0x0, sum = 2
8504 04:40:51.794801 16, 0x0, sum = 3
8505 04:40:51.794888 17, 0x0, sum = 4
8506 04:40:51.798585 best_step = 15
8507 04:40:51.798671
8508 04:40:51.798738 ==
8509 04:40:51.801677 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 04:40:51.804769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 04:40:51.804861 ==
8512 04:40:51.804928 RX Vref Scan: 1
8513 04:40:51.804990
8514 04:40:51.807980 Set Vref Range= 24 -> 127
8515 04:40:51.808066
8516 04:40:51.811748 RX Vref 24 -> 127, step: 1
8517 04:40:51.811839
8518 04:40:51.814771 RX Delay 27 -> 252, step: 4
8519 04:40:51.814851
8520 04:40:51.818578 Set Vref, RX VrefLevel [Byte0]: 24
8521 04:40:51.821590 [Byte1]: 24
8522 04:40:51.821679
8523 04:40:51.824632 Set Vref, RX VrefLevel [Byte0]: 25
8524 04:40:51.828288 [Byte1]: 25
8525 04:40:51.828382
8526 04:40:51.831390 Set Vref, RX VrefLevel [Byte0]: 26
8527 04:40:51.834491 [Byte1]: 26
8528 04:40:51.838214
8529 04:40:51.838301 Set Vref, RX VrefLevel [Byte0]: 27
8530 04:40:51.841935 [Byte1]: 27
8531 04:40:51.845642
8532 04:40:51.845721 Set Vref, RX VrefLevel [Byte0]: 28
8533 04:40:51.849154 [Byte1]: 28
8534 04:40:51.853384
8535 04:40:51.853465 Set Vref, RX VrefLevel [Byte0]: 29
8536 04:40:51.856695 [Byte1]: 29
8537 04:40:51.860902
8538 04:40:51.860996 Set Vref, RX VrefLevel [Byte0]: 30
8539 04:40:51.864238 [Byte1]: 30
8540 04:40:51.868213
8541 04:40:51.868301 Set Vref, RX VrefLevel [Byte0]: 31
8542 04:40:51.871523 [Byte1]: 31
8543 04:40:51.875911
8544 04:40:51.875998 Set Vref, RX VrefLevel [Byte0]: 32
8545 04:40:51.879046 [Byte1]: 32
8546 04:40:51.883402
8547 04:40:51.883485 Set Vref, RX VrefLevel [Byte0]: 33
8548 04:40:51.887089 [Byte1]: 33
8549 04:40:51.891236
8550 04:40:51.891319 Set Vref, RX VrefLevel [Byte0]: 34
8551 04:40:51.894386 [Byte1]: 34
8552 04:40:51.898798
8553 04:40:51.898888 Set Vref, RX VrefLevel [Byte0]: 35
8554 04:40:51.902087 [Byte1]: 35
8555 04:40:51.906433
8556 04:40:51.906524 Set Vref, RX VrefLevel [Byte0]: 36
8557 04:40:51.909546 [Byte1]: 36
8558 04:40:51.913921
8559 04:40:51.914009 Set Vref, RX VrefLevel [Byte0]: 37
8560 04:40:51.917003 [Byte1]: 37
8561 04:40:51.921418
8562 04:40:51.921503 Set Vref, RX VrefLevel [Byte0]: 38
8563 04:40:51.924511 [Byte1]: 38
8564 04:40:51.928774
8565 04:40:51.928859 Set Vref, RX VrefLevel [Byte0]: 39
8566 04:40:51.932362 [Byte1]: 39
8567 04:40:51.936611
8568 04:40:51.936699 Set Vref, RX VrefLevel [Byte0]: 40
8569 04:40:51.939770 [Byte1]: 40
8570 04:40:51.944041
8571 04:40:51.944128 Set Vref, RX VrefLevel [Byte0]: 41
8572 04:40:51.947092 [Byte1]: 41
8573 04:40:51.951493
8574 04:40:51.951593 Set Vref, RX VrefLevel [Byte0]: 42
8575 04:40:51.954759 [Byte1]: 42
8576 04:40:51.959236
8577 04:40:51.959321 Set Vref, RX VrefLevel [Byte0]: 43
8578 04:40:51.962247 [Byte1]: 43
8579 04:40:51.966419
8580 04:40:51.966504 Set Vref, RX VrefLevel [Byte0]: 44
8581 04:40:51.969785 [Byte1]: 44
8582 04:40:51.974032
8583 04:40:51.974111 Set Vref, RX VrefLevel [Byte0]: 45
8584 04:40:51.977491 [Byte1]: 45
8585 04:40:51.981315
8586 04:40:51.981393 Set Vref, RX VrefLevel [Byte0]: 46
8587 04:40:51.984568 [Byte1]: 46
8588 04:40:51.988983
8589 04:40:51.989063 Set Vref, RX VrefLevel [Byte0]: 47
8590 04:40:51.992529 [Byte1]: 47
8591 04:40:51.996332
8592 04:40:51.996444 Set Vref, RX VrefLevel [Byte0]: 48
8593 04:40:52.000041 [Byte1]: 48
8594 04:40:52.004274
8595 04:40:52.004362 Set Vref, RX VrefLevel [Byte0]: 49
8596 04:40:52.007096 [Byte1]: 49
8597 04:40:52.011734
8598 04:40:52.011816 Set Vref, RX VrefLevel [Byte0]: 50
8599 04:40:52.014931 [Byte1]: 50
8600 04:40:52.019165
8601 04:40:52.019253 Set Vref, RX VrefLevel [Byte0]: 51
8602 04:40:52.022688 [Byte1]: 51
8603 04:40:52.026434
8604 04:40:52.026513 Set Vref, RX VrefLevel [Byte0]: 52
8605 04:40:52.030384 [Byte1]: 52
8606 04:40:52.034383
8607 04:40:52.034463 Set Vref, RX VrefLevel [Byte0]: 53
8608 04:40:52.037557 [Byte1]: 53
8609 04:40:52.041973
8610 04:40:52.042050 Set Vref, RX VrefLevel [Byte0]: 54
8611 04:40:52.044997 [Byte1]: 54
8612 04:40:52.049440
8613 04:40:52.049524 Set Vref, RX VrefLevel [Byte0]: 55
8614 04:40:52.052540 [Byte1]: 55
8615 04:40:52.056844
8616 04:40:52.056964 Set Vref, RX VrefLevel [Byte0]: 56
8617 04:40:52.060012 [Byte1]: 56
8618 04:40:52.064587
8619 04:40:52.064679 Set Vref, RX VrefLevel [Byte0]: 57
8620 04:40:52.067661 [Byte1]: 57
8621 04:40:52.072034
8622 04:40:52.072126 Set Vref, RX VrefLevel [Byte0]: 58
8623 04:40:52.075228 [Byte1]: 58
8624 04:40:52.079363
8625 04:40:52.079483 Set Vref, RX VrefLevel [Byte0]: 59
8626 04:40:52.082934 [Byte1]: 59
8627 04:40:52.086625
8628 04:40:52.086712 Set Vref, RX VrefLevel [Byte0]: 60
8629 04:40:52.090288 [Byte1]: 60
8630 04:40:52.094208
8631 04:40:52.094301 Set Vref, RX VrefLevel [Byte0]: 61
8632 04:40:52.097619 [Byte1]: 61
8633 04:40:52.102073
8634 04:40:52.102161 Set Vref, RX VrefLevel [Byte0]: 62
8635 04:40:52.104978 [Byte1]: 62
8636 04:40:52.109180
8637 04:40:52.109268 Set Vref, RX VrefLevel [Byte0]: 63
8638 04:40:52.112832 [Byte1]: 63
8639 04:40:52.117323
8640 04:40:52.117411 Set Vref, RX VrefLevel [Byte0]: 64
8641 04:40:52.120131 [Byte1]: 64
8642 04:40:52.124225
8643 04:40:52.124313 Set Vref, RX VrefLevel [Byte0]: 65
8644 04:40:52.127900 [Byte1]: 65
8645 04:40:52.131894
8646 04:40:52.131983 Set Vref, RX VrefLevel [Byte0]: 66
8647 04:40:52.135470 [Byte1]: 66
8648 04:40:52.139679
8649 04:40:52.139760 Set Vref, RX VrefLevel [Byte0]: 67
8650 04:40:52.142683 [Byte1]: 67
8651 04:40:52.146942
8652 04:40:52.147055 Set Vref, RX VrefLevel [Byte0]: 68
8653 04:40:52.150186 [Byte1]: 68
8654 04:40:52.154540
8655 04:40:52.154617 Set Vref, RX VrefLevel [Byte0]: 69
8656 04:40:52.157705 [Byte1]: 69
8657 04:40:52.162159
8658 04:40:52.162236 Set Vref, RX VrefLevel [Byte0]: 70
8659 04:40:52.165805 [Byte1]: 70
8660 04:40:52.169595
8661 04:40:52.169675 Set Vref, RX VrefLevel [Byte0]: 71
8662 04:40:52.173290 [Byte1]: 71
8663 04:40:52.177112
8664 04:40:52.177189 Set Vref, RX VrefLevel [Byte0]: 72
8665 04:40:52.180849 [Byte1]: 72
8666 04:40:52.184960
8667 04:40:52.185037 Set Vref, RX VrefLevel [Byte0]: 73
8668 04:40:52.187927 [Byte1]: 73
8669 04:40:52.192172
8670 04:40:52.192250 Set Vref, RX VrefLevel [Byte0]: 74
8671 04:40:52.195407 [Byte1]: 74
8672 04:40:52.199646
8673 04:40:52.199724 Set Vref, RX VrefLevel [Byte0]: 75
8674 04:40:52.203258 [Byte1]: 75
8675 04:40:52.207261
8676 04:40:52.207360 Set Vref, RX VrefLevel [Byte0]: 76
8677 04:40:52.210464 [Byte1]: 76
8678 04:40:52.214784
8679 04:40:52.214860 Set Vref, RX VrefLevel [Byte0]: 77
8680 04:40:52.218253 [Byte1]: 77
8681 04:40:52.222620
8682 04:40:52.222709 Set Vref, RX VrefLevel [Byte0]: 78
8683 04:40:52.225858 [Byte1]: 78
8684 04:40:52.230090
8685 04:40:52.230183 Final RX Vref Byte 0 = 59 to rank0
8686 04:40:52.232996 Final RX Vref Byte 1 = 59 to rank0
8687 04:40:52.236430 Final RX Vref Byte 0 = 59 to rank1
8688 04:40:52.239839 Final RX Vref Byte 1 = 59 to rank1==
8689 04:40:52.243431 Dram Type= 6, Freq= 0, CH_1, rank 0
8690 04:40:52.250078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8691 04:40:52.250157 ==
8692 04:40:52.250221 DQS Delay:
8693 04:40:52.250280 DQS0 = 0, DQS1 = 0
8694 04:40:52.253021 DQM Delay:
8695 04:40:52.253101 DQM0 = 134, DQM1 = 130
8696 04:40:52.256794 DQ Delay:
8697 04:40:52.259928 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8698 04:40:52.263037 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8699 04:40:52.266142 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =122
8700 04:40:52.269470 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
8701 04:40:52.269549
8702 04:40:52.269626
8703 04:40:52.269688
8704 04:40:52.273226 [DramC_TX_OE_Calibration] TA2
8705 04:40:52.276359 Original DQ_B0 (3 6) =30, OEN = 27
8706 04:40:52.279531 Original DQ_B1 (3 6) =30, OEN = 27
8707 04:40:52.282711 24, 0x0, End_B0=24 End_B1=24
8708 04:40:52.282801 25, 0x0, End_B0=25 End_B1=25
8709 04:40:52.286408 26, 0x0, End_B0=26 End_B1=26
8710 04:40:52.289487 27, 0x0, End_B0=27 End_B1=27
8711 04:40:52.293208 28, 0x0, End_B0=28 End_B1=28
8712 04:40:52.296214 29, 0x0, End_B0=29 End_B1=29
8713 04:40:52.296363 30, 0x0, End_B0=30 End_B1=30
8714 04:40:52.299301 31, 0x4141, End_B0=30 End_B1=30
8715 04:40:52.303000 Byte0 end_step=30 best_step=27
8716 04:40:52.306153 Byte1 end_step=30 best_step=27
8717 04:40:52.309326 Byte0 TX OE(2T, 0.5T) = (3, 3)
8718 04:40:52.313087 Byte1 TX OE(2T, 0.5T) = (3, 3)
8719 04:40:52.313168
8720 04:40:52.313232
8721 04:40:52.319251 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8722 04:40:52.322626 CH1 RK0: MR19=303, MR18=1826
8723 04:40:52.329449 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8724 04:40:52.329528
8725 04:40:52.332839 ----->DramcWriteLeveling(PI) begin...
8726 04:40:52.332929 ==
8727 04:40:52.336376 Dram Type= 6, Freq= 0, CH_1, rank 1
8728 04:40:52.339733 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8729 04:40:52.339827 ==
8730 04:40:52.342899 Write leveling (Byte 0): 25 => 25
8731 04:40:52.346203 Write leveling (Byte 1): 29 => 29
8732 04:40:52.349647 DramcWriteLeveling(PI) end<-----
8733 04:40:52.349737
8734 04:40:52.349814 ==
8735 04:40:52.352714 Dram Type= 6, Freq= 0, CH_1, rank 1
8736 04:40:52.356322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8737 04:40:52.356403 ==
8738 04:40:52.359921 [Gating] SW mode calibration
8739 04:40:52.366023 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8740 04:40:52.372636 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8741 04:40:52.376525 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8742 04:40:52.379698 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 04:40:52.386402 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8744 04:40:52.389485 1 4 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
8745 04:40:52.393133 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8746 04:40:52.399521 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8747 04:40:52.402738 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 04:40:52.406454 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8749 04:40:52.412618 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 04:40:52.416371 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8751 04:40:52.419309 1 5 8 | B1->B0 | 3131 3434 | 0 1 | (0 1) (1 1)
8752 04:40:52.426365 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8753 04:40:52.429506 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8754 04:40:52.432513 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 04:40:52.439438 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 04:40:52.442725 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 04:40:52.446161 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 04:40:52.452692 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 04:40:52.456067 1 6 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
8760 04:40:52.459214 1 6 12 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
8761 04:40:52.465978 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 04:40:52.469472 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 04:40:52.472801 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 04:40:52.475846 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 04:40:52.482628 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 04:40:52.485840 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8767 04:40:52.489451 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8768 04:40:52.495792 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8769 04:40:52.499324 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 04:40:52.502245 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 04:40:52.509027 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 04:40:52.512235 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 04:40:52.515868 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 04:40:52.522626 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 04:40:52.525786 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 04:40:52.528966 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 04:40:52.535844 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 04:40:52.538907 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 04:40:52.541953 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 04:40:52.548778 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 04:40:52.552217 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 04:40:52.555581 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8783 04:40:52.562355 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8784 04:40:52.565490 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8785 04:40:52.568894 Total UI for P1: 0, mck2ui 16
8786 04:40:52.572282 best dqsien dly found for B1: ( 1, 9, 6)
8787 04:40:52.575439 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 04:40:52.578676 Total UI for P1: 0, mck2ui 16
8789 04:40:52.582032 best dqsien dly found for B0: ( 1, 9, 12)
8790 04:40:52.585310 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8791 04:40:52.588763 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8792 04:40:52.588885
8793 04:40:52.592494 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8794 04:40:52.598881 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8795 04:40:52.598977 [Gating] SW calibration Done
8796 04:40:52.599066 ==
8797 04:40:52.602690 Dram Type= 6, Freq= 0, CH_1, rank 1
8798 04:40:52.608803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8799 04:40:52.608924 ==
8800 04:40:52.609036 RX Vref Scan: 0
8801 04:40:52.609151
8802 04:40:52.612407 RX Vref 0 -> 0, step: 1
8803 04:40:52.612531
8804 04:40:52.615591 RX Delay 0 -> 252, step: 8
8805 04:40:52.619354 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8806 04:40:52.622547 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8807 04:40:52.625531 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8808 04:40:52.629265 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8809 04:40:52.635599 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8810 04:40:52.639275 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8811 04:40:52.642447 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8812 04:40:52.645549 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8813 04:40:52.648766 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8814 04:40:52.655478 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8815 04:40:52.658980 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8816 04:40:52.662529 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8817 04:40:52.665908 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8818 04:40:52.669264 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8819 04:40:52.675892 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8820 04:40:52.678965 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8821 04:40:52.679081 ==
8822 04:40:52.682025 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 04:40:52.685519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 04:40:52.685643 ==
8825 04:40:52.689029 DQS Delay:
8826 04:40:52.689110 DQS0 = 0, DQS1 = 0
8827 04:40:52.689175 DQM Delay:
8828 04:40:52.692355 DQM0 = 136, DQM1 = 133
8829 04:40:52.692446 DQ Delay:
8830 04:40:52.695579 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8831 04:40:52.698854 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8832 04:40:52.702667 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8833 04:40:52.708783 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8834 04:40:52.708900
8835 04:40:52.708972
8836 04:40:52.709035 ==
8837 04:40:52.712453 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 04:40:52.715691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 04:40:52.715777 ==
8840 04:40:52.715844
8841 04:40:52.715916
8842 04:40:52.718970 TX Vref Scan disable
8843 04:40:52.719055 == TX Byte 0 ==
8844 04:40:52.725898 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8845 04:40:52.728944 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8846 04:40:52.729030 == TX Byte 1 ==
8847 04:40:52.735787 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8848 04:40:52.738815 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8849 04:40:52.738913 ==
8850 04:40:52.742488 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 04:40:52.745632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 04:40:52.745716 ==
8853 04:40:52.759309
8854 04:40:52.762815 TX Vref early break, caculate TX vref
8855 04:40:52.765957 TX Vref=16, minBit 0, minWin=23, winSum=382
8856 04:40:52.769626 TX Vref=18, minBit 0, minWin=23, winSum=389
8857 04:40:52.772739 TX Vref=20, minBit 0, minWin=24, winSum=403
8858 04:40:52.775895 TX Vref=22, minBit 0, minWin=24, winSum=411
8859 04:40:52.779383 TX Vref=24, minBit 6, minWin=25, winSum=418
8860 04:40:52.785785 TX Vref=26, minBit 0, minWin=26, winSum=427
8861 04:40:52.789482 TX Vref=28, minBit 0, minWin=26, winSum=426
8862 04:40:52.792882 TX Vref=30, minBit 6, minWin=25, winSum=421
8863 04:40:52.796172 TX Vref=32, minBit 1, minWin=24, winSum=411
8864 04:40:52.799185 TX Vref=34, minBit 0, minWin=23, winSum=402
8865 04:40:52.806022 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 26
8866 04:40:52.806141
8867 04:40:52.809194 Final TX Range 0 Vref 26
8868 04:40:52.809309
8869 04:40:52.809417 ==
8870 04:40:52.812794 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 04:40:52.816002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 04:40:52.816091 ==
8873 04:40:52.816161
8874 04:40:52.816223
8875 04:40:52.819618 TX Vref Scan disable
8876 04:40:52.826162 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8877 04:40:52.826259 == TX Byte 0 ==
8878 04:40:52.829202 u2DelayCellOfst[0]=16 cells (5 PI)
8879 04:40:52.833004 u2DelayCellOfst[1]=10 cells (3 PI)
8880 04:40:52.836042 u2DelayCellOfst[2]=0 cells (0 PI)
8881 04:40:52.839144 u2DelayCellOfst[3]=6 cells (2 PI)
8882 04:40:52.842913 u2DelayCellOfst[4]=10 cells (3 PI)
8883 04:40:52.845922 u2DelayCellOfst[5]=16 cells (5 PI)
8884 04:40:52.846037 u2DelayCellOfst[6]=16 cells (5 PI)
8885 04:40:52.849206 u2DelayCellOfst[7]=3 cells (1 PI)
8886 04:40:52.856025 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8887 04:40:52.859262 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8888 04:40:52.859376 == TX Byte 1 ==
8889 04:40:52.862261 u2DelayCellOfst[8]=0 cells (0 PI)
8890 04:40:52.865893 u2DelayCellOfst[9]=3 cells (1 PI)
8891 04:40:52.869556 u2DelayCellOfst[10]=10 cells (3 PI)
8892 04:40:52.872732 u2DelayCellOfst[11]=6 cells (2 PI)
8893 04:40:52.875838 u2DelayCellOfst[12]=13 cells (4 PI)
8894 04:40:52.878931 u2DelayCellOfst[13]=13 cells (4 PI)
8895 04:40:52.882592 u2DelayCellOfst[14]=16 cells (5 PI)
8896 04:40:52.885818 u2DelayCellOfst[15]=16 cells (5 PI)
8897 04:40:52.888798 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8898 04:40:52.896215 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8899 04:40:52.896315 DramC Write-DBI on
8900 04:40:52.896383 ==
8901 04:40:52.898989 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 04:40:52.902477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 04:40:52.902565 ==
8904 04:40:52.905727
8905 04:40:52.905814
8906 04:40:52.905880 TX Vref Scan disable
8907 04:40:52.909167 == TX Byte 0 ==
8908 04:40:52.912371 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8909 04:40:52.915996 == TX Byte 1 ==
8910 04:40:52.918980 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8911 04:40:52.919060 DramC Write-DBI off
8912 04:40:52.919124
8913 04:40:52.922504 [DATLAT]
8914 04:40:52.922595 Freq=1600, CH1 RK1
8915 04:40:52.922668
8916 04:40:52.925807 DATLAT Default: 0xf
8917 04:40:52.925907 0, 0xFFFF, sum = 0
8918 04:40:52.929325 1, 0xFFFF, sum = 0
8919 04:40:52.929431 2, 0xFFFF, sum = 0
8920 04:40:52.932266 3, 0xFFFF, sum = 0
8921 04:40:52.932347 4, 0xFFFF, sum = 0
8922 04:40:52.935512 5, 0xFFFF, sum = 0
8923 04:40:52.935597 6, 0xFFFF, sum = 0
8924 04:40:52.938813 7, 0xFFFF, sum = 0
8925 04:40:52.942563 8, 0xFFFF, sum = 0
8926 04:40:52.942661 9, 0xFFFF, sum = 0
8927 04:40:52.945830 10, 0xFFFF, sum = 0
8928 04:40:52.945918 11, 0xFFFF, sum = 0
8929 04:40:52.948957 12, 0xFFFF, sum = 0
8930 04:40:52.949037 13, 0xFFFF, sum = 0
8931 04:40:52.952637 14, 0x0, sum = 1
8932 04:40:52.952714 15, 0x0, sum = 2
8933 04:40:52.955830 16, 0x0, sum = 3
8934 04:40:52.955916 17, 0x0, sum = 4
8935 04:40:52.955983 best_step = 15
8936 04:40:52.958923
8937 04:40:52.959006 ==
8938 04:40:52.962741 Dram Type= 6, Freq= 0, CH_1, rank 1
8939 04:40:52.965778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8940 04:40:52.965867 ==
8941 04:40:52.965933 RX Vref Scan: 0
8942 04:40:52.965994
8943 04:40:52.968862 RX Vref 0 -> 0, step: 1
8944 04:40:52.968950
8945 04:40:52.972462 RX Delay 19 -> 252, step: 4
8946 04:40:52.975723 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8947 04:40:52.978772 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8948 04:40:52.985755 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8949 04:40:52.989016 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8950 04:40:52.992175 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8951 04:40:52.995883 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8952 04:40:52.999158 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8953 04:40:53.005795 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8954 04:40:53.008659 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8955 04:40:53.012315 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8956 04:40:53.015598 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8957 04:40:53.018885 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8958 04:40:53.025512 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8959 04:40:53.028465 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8960 04:40:53.031957 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8961 04:40:53.035176 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8962 04:40:53.035260 ==
8963 04:40:53.038962 Dram Type= 6, Freq= 0, CH_1, rank 1
8964 04:40:53.045362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8965 04:40:53.045450 ==
8966 04:40:53.045517 DQS Delay:
8967 04:40:53.048840 DQS0 = 0, DQS1 = 0
8968 04:40:53.048925 DQM Delay:
8969 04:40:53.048992 DQM0 = 134, DQM1 = 130
8970 04:40:53.052288 DQ Delay:
8971 04:40:53.055212 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =130
8972 04:40:53.058439 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8973 04:40:53.061795 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8974 04:40:53.065550 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8975 04:40:53.065635
8976 04:40:53.065701
8977 04:40:53.065763
8978 04:40:53.068803 [DramC_TX_OE_Calibration] TA2
8979 04:40:53.071772 Original DQ_B0 (3 6) =30, OEN = 27
8980 04:40:53.075404 Original DQ_B1 (3 6) =30, OEN = 27
8981 04:40:53.078468 24, 0x0, End_B0=24 End_B1=24
8982 04:40:53.078556 25, 0x0, End_B0=25 End_B1=25
8983 04:40:53.082189 26, 0x0, End_B0=26 End_B1=26
8984 04:40:53.085456 27, 0x0, End_B0=27 End_B1=27
8985 04:40:53.088436 28, 0x0, End_B0=28 End_B1=28
8986 04:40:53.088529 29, 0x0, End_B0=29 End_B1=29
8987 04:40:53.092204 30, 0x0, End_B0=30 End_B1=30
8988 04:40:53.095233 31, 0x4141, End_B0=30 End_B1=30
8989 04:40:53.098471 Byte0 end_step=30 best_step=27
8990 04:40:53.102140 Byte1 end_step=30 best_step=27
8991 04:40:53.105131 Byte0 TX OE(2T, 0.5T) = (3, 3)
8992 04:40:53.105220 Byte1 TX OE(2T, 0.5T) = (3, 3)
8993 04:40:53.108622
8994 04:40:53.108716
8995 04:40:53.115487 [DQSOSCAuto] RK1, (LSB)MR18= 0x2409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
8996 04:40:53.118702 CH1 RK1: MR19=303, MR18=2409
8997 04:40:53.125200 CH1_RK1: MR19=0x303, MR18=0x2409, DQSOSC=391, MR23=63, INC=24, DEC=16
8998 04:40:53.128949 [RxdqsGatingPostProcess] freq 1600
8999 04:40:53.131948 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9000 04:40:53.135429 best DQS0 dly(2T, 0.5T) = (1, 1)
9001 04:40:53.138859 best DQS1 dly(2T, 0.5T) = (1, 1)
9002 04:40:53.141984 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9003 04:40:53.145053 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9004 04:40:53.148855 best DQS0 dly(2T, 0.5T) = (1, 1)
9005 04:40:53.152047 best DQS1 dly(2T, 0.5T) = (1, 1)
9006 04:40:53.155641 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9007 04:40:53.158939 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9008 04:40:53.159024 Pre-setting of DQS Precalculation
9009 04:40:53.165471 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9010 04:40:53.171672 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9011 04:40:53.178467 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9012 04:40:53.178567
9013 04:40:53.178634
9014 04:40:53.182225 [Calibration Summary] 3200 Mbps
9015 04:40:53.185212 CH 0, Rank 0
9016 04:40:53.185297 SW Impedance : PASS
9017 04:40:53.189041 DUTY Scan : NO K
9018 04:40:53.192032 ZQ Calibration : PASS
9019 04:40:53.192124 Jitter Meter : NO K
9020 04:40:53.195613 CBT Training : PASS
9021 04:40:53.198708 Write leveling : PASS
9022 04:40:53.198791 RX DQS gating : PASS
9023 04:40:53.201986 RX DQ/DQS(RDDQC) : PASS
9024 04:40:53.202061 TX DQ/DQS : PASS
9025 04:40:53.205012 RX DATLAT : PASS
9026 04:40:53.208774 RX DQ/DQS(Engine): PASS
9027 04:40:53.208865 TX OE : PASS
9028 04:40:53.211909 All Pass.
9029 04:40:53.211998
9030 04:40:53.212065 CH 0, Rank 1
9031 04:40:53.215468 SW Impedance : PASS
9032 04:40:53.215554 DUTY Scan : NO K
9033 04:40:53.218409 ZQ Calibration : PASS
9034 04:40:53.222185 Jitter Meter : NO K
9035 04:40:53.222288 CBT Training : PASS
9036 04:40:53.225216 Write leveling : PASS
9037 04:40:53.228676 RX DQS gating : PASS
9038 04:40:53.228760 RX DQ/DQS(RDDQC) : PASS
9039 04:40:53.231656 TX DQ/DQS : PASS
9040 04:40:53.235309 RX DATLAT : PASS
9041 04:40:53.235422 RX DQ/DQS(Engine): PASS
9042 04:40:53.238430 TX OE : PASS
9043 04:40:53.238515 All Pass.
9044 04:40:53.238581
9045 04:40:53.242021 CH 1, Rank 0
9046 04:40:53.242106 SW Impedance : PASS
9047 04:40:53.244871 DUTY Scan : NO K
9048 04:40:53.248360 ZQ Calibration : PASS
9049 04:40:53.248445 Jitter Meter : NO K
9050 04:40:53.251711 CBT Training : PASS
9051 04:40:53.251796 Write leveling : PASS
9052 04:40:53.254907 RX DQS gating : PASS
9053 04:40:53.258504 RX DQ/DQS(RDDQC) : PASS
9054 04:40:53.258588 TX DQ/DQS : PASS
9055 04:40:53.261838 RX DATLAT : PASS
9056 04:40:53.264998 RX DQ/DQS(Engine): PASS
9057 04:40:53.265074 TX OE : PASS
9058 04:40:53.268226 All Pass.
9059 04:40:53.268308
9060 04:40:53.268380 CH 1, Rank 1
9061 04:40:53.271873 SW Impedance : PASS
9062 04:40:53.271994 DUTY Scan : NO K
9063 04:40:53.275128 ZQ Calibration : PASS
9064 04:40:53.278767 Jitter Meter : NO K
9065 04:40:53.278852 CBT Training : PASS
9066 04:40:53.281744 Write leveling : PASS
9067 04:40:53.285242 RX DQS gating : PASS
9068 04:40:53.285319 RX DQ/DQS(RDDQC) : PASS
9069 04:40:53.288470 TX DQ/DQS : PASS
9070 04:40:53.291924 RX DATLAT : PASS
9071 04:40:53.292015 RX DQ/DQS(Engine): PASS
9072 04:40:53.294958 TX OE : PASS
9073 04:40:53.295046 All Pass.
9074 04:40:53.295112
9075 04:40:53.298656 DramC Write-DBI on
9076 04:40:53.298742 PER_BANK_REFRESH: Hybrid Mode
9077 04:40:53.301753 TX_TRACKING: ON
9078 04:40:53.311857 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9079 04:40:53.318355 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9080 04:40:53.325310 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9081 04:40:53.328178 [FAST_K] Save calibration result to emmc
9082 04:40:53.331814 sync common calibartion params.
9083 04:40:53.335243 sync cbt_mode0:1, 1:1
9084 04:40:53.335353 dram_init: ddr_geometry: 2
9085 04:40:53.338489 dram_init: ddr_geometry: 2
9086 04:40:53.341461 dram_init: ddr_geometry: 2
9087 04:40:53.345241 0:dram_rank_size:100000000
9088 04:40:53.345324 1:dram_rank_size:100000000
9089 04:40:53.351356 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9090 04:40:53.355048 DFS_SHUFFLE_HW_MODE: ON
9091 04:40:53.358495 dramc_set_vcore_voltage set vcore to 725000
9092 04:40:53.361584 Read voltage for 1600, 0
9093 04:40:53.361698 Vio18 = 0
9094 04:40:53.361793 Vcore = 725000
9095 04:40:53.364632 Vdram = 0
9096 04:40:53.364709 Vddq = 0
9097 04:40:53.364774 Vmddr = 0
9098 04:40:53.368109 switch to 3200 Mbps bootup
9099 04:40:53.368218 [DramcRunTimeConfig]
9100 04:40:53.371275 PHYPLL
9101 04:40:53.371358 DPM_CONTROL_AFTERK: ON
9102 04:40:53.375050 PER_BANK_REFRESH: ON
9103 04:40:53.378015 REFRESH_OVERHEAD_REDUCTION: ON
9104 04:40:53.378101 CMD_PICG_NEW_MODE: OFF
9105 04:40:53.381255 XRTWTW_NEW_MODE: ON
9106 04:40:53.381341 XRTRTR_NEW_MODE: ON
9107 04:40:53.384918 TX_TRACKING: ON
9108 04:40:53.385004 RDSEL_TRACKING: OFF
9109 04:40:53.387956 DQS Precalculation for DVFS: ON
9110 04:40:53.391714 RX_TRACKING: OFF
9111 04:40:53.391801 HW_GATING DBG: ON
9112 04:40:53.394589 ZQCS_ENABLE_LP4: ON
9113 04:40:53.394673 RX_PICG_NEW_MODE: ON
9114 04:40:53.398140 TX_PICG_NEW_MODE: ON
9115 04:40:53.398245 ENABLE_RX_DCM_DPHY: ON
9116 04:40:53.401503 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9117 04:40:53.405010 DUMMY_READ_FOR_TRACKING: OFF
9118 04:40:53.407914 !!! SPM_CONTROL_AFTERK: OFF
9119 04:40:53.411638 !!! SPM could not control APHY
9120 04:40:53.411732 IMPEDANCE_TRACKING: ON
9121 04:40:53.414778 TEMP_SENSOR: ON
9122 04:40:53.414854 HW_SAVE_FOR_SR: OFF
9123 04:40:53.417951 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9124 04:40:53.421615 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9125 04:40:53.424724 Read ODT Tracking: ON
9126 04:40:53.427947 Refresh Rate DeBounce: ON
9127 04:40:53.428077 DFS_NO_QUEUE_FLUSH: ON
9128 04:40:53.431555 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9129 04:40:53.435069 ENABLE_DFS_RUNTIME_MRW: OFF
9130 04:40:53.438071 DDR_RESERVE_NEW_MODE: ON
9131 04:40:53.438192 MR_CBT_SWITCH_FREQ: ON
9132 04:40:53.441522 =========================
9133 04:40:53.460252 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9134 04:40:53.463272 dram_init: ddr_geometry: 2
9135 04:40:53.481416 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9136 04:40:53.485224 dram_init: dram init end (result: 0)
9137 04:40:53.491475 DRAM-K: Full calibration passed in 24462 msecs
9138 04:40:53.495112 MRC: failed to locate region type 0.
9139 04:40:53.495224 DRAM rank0 size:0x100000000,
9140 04:40:53.498234 DRAM rank1 size=0x100000000
9141 04:40:53.508562 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9142 04:40:53.514986 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9143 04:40:53.521779 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9144 04:40:53.528019 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9145 04:40:53.531768 DRAM rank0 size:0x100000000,
9146 04:40:53.535057 DRAM rank1 size=0x100000000
9147 04:40:53.535161 CBMEM:
9148 04:40:53.538024 IMD: root @ 0xfffff000 254 entries.
9149 04:40:53.541503 IMD: root @ 0xffffec00 62 entries.
9150 04:40:53.545090 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9151 04:40:53.548020 WARNING: RO_VPD is uninitialized or empty.
9152 04:40:53.554619 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9153 04:40:53.561358 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9154 04:40:53.574495 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9155 04:40:53.586087 BS: romstage times (exec / console): total (unknown) / 23995 ms
9156 04:40:53.586229
9157 04:40:53.586311
9158 04:40:53.596113 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9159 04:40:53.599260 ARM64: Exception handlers installed.
9160 04:40:53.602339 ARM64: Testing exception
9161 04:40:53.606027 ARM64: Done test exception
9162 04:40:53.606140 Enumerating buses...
9163 04:40:53.609095 Show all devs... Before device enumeration.
9164 04:40:53.612312 Root Device: enabled 1
9165 04:40:53.615935 CPU_CLUSTER: 0: enabled 1
9166 04:40:53.616035 CPU: 00: enabled 1
9167 04:40:53.619055 Compare with tree...
9168 04:40:53.619139 Root Device: enabled 1
9169 04:40:53.622447 CPU_CLUSTER: 0: enabled 1
9170 04:40:53.625496 CPU: 00: enabled 1
9171 04:40:53.625581 Root Device scanning...
9172 04:40:53.629266 scan_static_bus for Root Device
9173 04:40:53.632253 CPU_CLUSTER: 0 enabled
9174 04:40:53.635972 scan_static_bus for Root Device done
9175 04:40:53.639138 scan_bus: bus Root Device finished in 8 msecs
9176 04:40:53.639237 done
9177 04:40:53.645895 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9178 04:40:53.648805 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9179 04:40:53.655384 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9180 04:40:53.658711 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9181 04:40:53.662271 Allocating resources...
9182 04:40:53.665317 Reading resources...
9183 04:40:53.668845 Root Device read_resources bus 0 link: 0
9184 04:40:53.668932 DRAM rank0 size:0x100000000,
9185 04:40:53.672010 DRAM rank1 size=0x100000000
9186 04:40:53.675170 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9187 04:40:53.678763 CPU: 00 missing read_resources
9188 04:40:53.681731 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9189 04:40:53.688415 Root Device read_resources bus 0 link: 0 done
9190 04:40:53.688508 Done reading resources.
9191 04:40:53.695252 Show resources in subtree (Root Device)...After reading.
9192 04:40:53.698296 Root Device child on link 0 CPU_CLUSTER: 0
9193 04:40:53.701978 CPU_CLUSTER: 0 child on link 0 CPU: 00
9194 04:40:53.711899 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9195 04:40:53.711990 CPU: 00
9196 04:40:53.714998 Root Device assign_resources, bus 0 link: 0
9197 04:40:53.718794 CPU_CLUSTER: 0 missing set_resources
9198 04:40:53.724895 Root Device assign_resources, bus 0 link: 0 done
9199 04:40:53.724982 Done setting resources.
9200 04:40:53.731995 Show resources in subtree (Root Device)...After assigning values.
9201 04:40:53.735230 Root Device child on link 0 CPU_CLUSTER: 0
9202 04:40:53.738189 CPU_CLUSTER: 0 child on link 0 CPU: 00
9203 04:40:53.748170 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9204 04:40:53.748262 CPU: 00
9205 04:40:53.751698 Done allocating resources.
9206 04:40:53.754624 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9207 04:40:53.758165 Enabling resources...
9208 04:40:53.758252 done.
9209 04:40:53.765222 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9210 04:40:53.765314 Initializing devices...
9211 04:40:53.768051 Root Device init
9212 04:40:53.768137 init hardware done!
9213 04:40:53.771462 0x00000018: ctrlr->caps
9214 04:40:53.774794 52.000 MHz: ctrlr->f_max
9215 04:40:53.774883 0.400 MHz: ctrlr->f_min
9216 04:40:53.778462 0x40ff8080: ctrlr->voltages
9217 04:40:53.778549 sclk: 390625
9218 04:40:53.781553 Bus Width = 1
9219 04:40:53.781639 sclk: 390625
9220 04:40:53.785093 Bus Width = 1
9221 04:40:53.785178 Early init status = 3
9222 04:40:53.791796 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9223 04:40:53.795028 in-header: 03 fc 00 00 01 00 00 00
9224 04:40:53.795141 in-data: 00
9225 04:40:53.801733 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9226 04:40:53.804877 in-header: 03 fd 00 00 00 00 00 00
9227 04:40:53.808699 in-data:
9228 04:40:53.811835 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9229 04:40:53.814959 in-header: 03 fc 00 00 01 00 00 00
9230 04:40:53.818676 in-data: 00
9231 04:40:53.821829 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9232 04:40:53.825517 in-header: 03 fd 00 00 00 00 00 00
9233 04:40:53.829273 in-data:
9234 04:40:53.832199 [SSUSB] Setting up USB HOST controller...
9235 04:40:53.835804 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9236 04:40:53.838955 [SSUSB] phy power-on done.
9237 04:40:53.842136 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9238 04:40:53.848940 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9239 04:40:53.852208 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9240 04:40:53.858795 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9241 04:40:53.865452 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9242 04:40:53.872514 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9243 04:40:53.878889 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9244 04:40:53.885370 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9245 04:40:53.888425 SPM: binary array size = 0x9dc
9246 04:40:53.892069 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9247 04:40:53.898627 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9248 04:40:53.905427 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9249 04:40:53.911690 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9250 04:40:53.915341 configure_display: Starting display init
9251 04:40:53.948804 anx7625_power_on_init: Init interface.
9252 04:40:53.952462 anx7625_disable_pd_protocol: Disabled PD feature.
9253 04:40:53.955461 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9254 04:40:53.983398 anx7625_start_dp_work: Secure OCM version=00
9255 04:40:53.986964 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9256 04:40:54.001687 sp_tx_get_edid_block: EDID Block = 1
9257 04:40:54.103983 Extracted contents:
9258 04:40:54.107299 header: 00 ff ff ff ff ff ff 00
9259 04:40:54.110893 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9260 04:40:54.113851 version: 01 04
9261 04:40:54.117597 basic params: 95 1f 11 78 0a
9262 04:40:54.120635 chroma info: 76 90 94 55 54 90 27 21 50 54
9263 04:40:54.124356 established: 00 00 00
9264 04:40:54.127663 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9265 04:40:54.134236 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9266 04:40:54.140491 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9267 04:40:54.147410 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9268 04:40:54.153874 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9269 04:40:54.157524 extensions: 00
9270 04:40:54.157649 checksum: fb
9271 04:40:54.157753
9272 04:40:54.160620 Manufacturer: IVO Model 57d Serial Number 0
9273 04:40:54.164327 Made week 0 of 2020
9274 04:40:54.164420 EDID version: 1.4
9275 04:40:54.167485 Digital display
9276 04:40:54.170653 6 bits per primary color channel
9277 04:40:54.170732 DisplayPort interface
9278 04:40:54.173798 Maximum image size: 31 cm x 17 cm
9279 04:40:54.176848 Gamma: 220%
9280 04:40:54.176980 Check DPMS levels
9281 04:40:54.180657 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9282 04:40:54.183766 First detailed timing is preferred timing
9283 04:40:54.186902 Established timings supported:
9284 04:40:54.190500 Standard timings supported:
9285 04:40:54.190607 Detailed timings
9286 04:40:54.197464 Hex of detail: 383680a07038204018303c0035ae10000019
9287 04:40:54.200103 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9288 04:40:54.206947 0780 0798 07c8 0820 hborder 0
9289 04:40:54.210028 0438 043b 0447 0458 vborder 0
9290 04:40:54.213706 -hsync -vsync
9291 04:40:54.213808 Did detailed timing
9292 04:40:54.220011 Hex of detail: 000000000000000000000000000000000000
9293 04:40:54.220133 Manufacturer-specified data, tag 0
9294 04:40:54.226826 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9295 04:40:54.229980 ASCII string: InfoVision
9296 04:40:54.233584 Hex of detail: 000000fe00523134304e574635205248200a
9297 04:40:54.236663 ASCII string: R140NWF5 RH
9298 04:40:54.236744 Checksum
9299 04:40:54.239745 Checksum: 0xfb (valid)
9300 04:40:54.243412 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9301 04:40:54.246469 DSI data_rate: 832800000 bps
9302 04:40:54.253176 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9303 04:40:54.256683 anx7625_parse_edid: pixelclock(138800).
9304 04:40:54.259707 hactive(1920), hsync(48), hfp(24), hbp(88)
9305 04:40:54.263407 vactive(1080), vsync(12), vfp(3), vbp(17)
9306 04:40:54.266473 anx7625_dsi_config: config dsi.
9307 04:40:54.272668 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9308 04:40:54.285977 anx7625_dsi_config: success to config DSI
9309 04:40:54.289221 anx7625_dp_start: MIPI phy setup OK.
9310 04:40:54.292884 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9311 04:40:54.295983 mtk_ddp_mode_set invalid vrefresh 60
9312 04:40:54.299778 main_disp_path_setup
9313 04:40:54.299891 ovl_layer_smi_id_en
9314 04:40:54.302651 ovl_layer_smi_id_en
9315 04:40:54.302770 ccorr_config
9316 04:40:54.302868 aal_config
9317 04:40:54.306073 gamma_config
9318 04:40:54.306171 postmask_config
9319 04:40:54.309537 dither_config
9320 04:40:54.312826 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9321 04:40:54.319159 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9322 04:40:54.322698 Root Device init finished in 551 msecs
9323 04:40:54.325759 CPU_CLUSTER: 0 init
9324 04:40:54.332729 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9325 04:40:54.335609 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9326 04:40:54.338954 APU_MBOX 0x190000b0 = 0x10001
9327 04:40:54.342454 APU_MBOX 0x190001b0 = 0x10001
9328 04:40:54.346212 APU_MBOX 0x190005b0 = 0x10001
9329 04:40:54.349320 APU_MBOX 0x190006b0 = 0x10001
9330 04:40:54.352433 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9331 04:40:54.364863 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9332 04:40:54.377395 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9333 04:40:54.384265 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9334 04:40:54.395851 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9335 04:40:54.405183 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9336 04:40:54.408385 CPU_CLUSTER: 0 init finished in 81 msecs
9337 04:40:54.411376 Devices initialized
9338 04:40:54.414678 Show all devs... After init.
9339 04:40:54.414790 Root Device: enabled 1
9340 04:40:54.418375 CPU_CLUSTER: 0: enabled 1
9341 04:40:54.421807 CPU: 00: enabled 1
9342 04:40:54.425201 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9343 04:40:54.427975 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9344 04:40:54.431353 ELOG: NV offset 0x57f000 size 0x1000
9345 04:40:54.438228 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9346 04:40:54.444696 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9347 04:40:54.448072 ELOG: Event(17) added with size 13 at 2023-08-09 04:40:19 UTC
9348 04:40:54.451392 out: cmd=0x121: 03 db 21 01 00 00 00 00
9349 04:40:54.455044 in-header: 03 d5 00 00 2c 00 00 00
9350 04:40:54.468712 in-data: 8a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9351 04:40:54.475081 ELOG: Event(A1) added with size 10 at 2023-08-09 04:40:19 UTC
9352 04:40:54.481882 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9353 04:40:54.488209 ELOG: Event(A0) added with size 9 at 2023-08-09 04:40:19 UTC
9354 04:40:54.491858 elog_add_boot_reason: Logged dev mode boot
9355 04:40:54.495005 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9356 04:40:54.498590 Finalize devices...
9357 04:40:54.498681 Devices finalized
9358 04:40:54.504689 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9359 04:40:54.508535 Writing coreboot table at 0xffe64000
9360 04:40:54.511757 0. 000000000010a000-0000000000113fff: RAMSTAGE
9361 04:40:54.514682 1. 0000000040000000-00000000400fffff: RAM
9362 04:40:54.521748 2. 0000000040100000-000000004032afff: RAMSTAGE
9363 04:40:54.524798 3. 000000004032b000-00000000545fffff: RAM
9364 04:40:54.527928 4. 0000000054600000-000000005465ffff: BL31
9365 04:40:54.531306 5. 0000000054660000-00000000ffe63fff: RAM
9366 04:40:54.538129 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9367 04:40:54.541040 7. 0000000100000000-000000023fffffff: RAM
9368 04:40:54.541128 Passing 5 GPIOs to payload:
9369 04:40:54.547913 NAME | PORT | POLARITY | VALUE
9370 04:40:54.551331 EC in RW | 0x000000aa | low | undefined
9371 04:40:54.557915 EC interrupt | 0x00000005 | low | undefined
9372 04:40:54.561254 TPM interrupt | 0x000000ab | high | undefined
9373 04:40:54.564936 SD card detect | 0x00000011 | high | undefined
9374 04:40:54.571211 speaker enable | 0x00000093 | high | undefined
9375 04:40:54.574780 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9376 04:40:54.578172 in-header: 03 f9 00 00 02 00 00 00
9377 04:40:54.578262 in-data: 02 00
9378 04:40:54.581286 ADC[4]: Raw value=904357 ID=7
9379 04:40:54.584500 ADC[3]: Raw value=213441 ID=1
9380 04:40:54.584593 RAM Code: 0x71
9381 04:40:54.588106 ADC[6]: Raw value=75332 ID=0
9382 04:40:54.591259 ADC[5]: Raw value=212703 ID=1
9383 04:40:54.591371 SKU Code: 0x1
9384 04:40:54.598163 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2f90
9385 04:40:54.601273 coreboot table: 964 bytes.
9386 04:40:54.604526 IMD ROOT 0. 0xfffff000 0x00001000
9387 04:40:54.607618 IMD SMALL 1. 0xffffe000 0x00001000
9388 04:40:54.611325 RO MCACHE 2. 0xffffc000 0x00001104
9389 04:40:54.614439 CONSOLE 3. 0xfff7c000 0x00080000
9390 04:40:54.617645 FMAP 4. 0xfff7b000 0x00000452
9391 04:40:54.621252 TIME STAMP 5. 0xfff7a000 0x00000910
9392 04:40:54.624267 VBOOT WORK 6. 0xfff66000 0x00014000
9393 04:40:54.627868 RAMOOPS 7. 0xffe66000 0x00100000
9394 04:40:54.631301 COREBOOT 8. 0xffe64000 0x00002000
9395 04:40:54.631382 IMD small region:
9396 04:40:54.634609 IMD ROOT 0. 0xffffec00 0x00000400
9397 04:40:54.637595 VPD 1. 0xffffeba0 0x0000004c
9398 04:40:54.641250 MMC STATUS 2. 0xffffeb80 0x00000004
9399 04:40:54.647702 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9400 04:40:54.651217 Probing TPM: done!
9401 04:40:54.654248 Connected to device vid:did:rid of 1ae0:0028:00
9402 04:40:54.664454 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9403 04:40:54.668006 Initialized TPM device CR50 revision 0
9404 04:40:54.671703 Checking cr50 for pending updates
9405 04:40:54.674871 Reading cr50 TPM mode
9406 04:40:54.683453 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9407 04:40:54.690111 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9408 04:40:54.730053 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9409 04:40:54.733065 Checking segment from ROM address 0x40100000
9410 04:40:54.736683 Checking segment from ROM address 0x4010001c
9411 04:40:54.743352 Loading segment from ROM address 0x40100000
9412 04:40:54.743474 code (compression=0)
9413 04:40:54.753178 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9414 04:40:54.760148 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9415 04:40:54.760240 it's not compressed!
9416 04:40:54.766729 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9417 04:40:54.770186 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9418 04:40:54.790575 Loading segment from ROM address 0x4010001c
9419 04:40:54.790683 Entry Point 0x80000000
9420 04:40:54.793599 Loaded segments
9421 04:40:54.797342 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9422 04:40:54.804089 Jumping to boot code at 0x80000000(0xffe64000)
9423 04:40:54.810297 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9424 04:40:54.817136 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9425 04:40:54.824688 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9426 04:40:54.828541 Checking segment from ROM address 0x40100000
9427 04:40:54.831793 Checking segment from ROM address 0x4010001c
9428 04:40:54.838253 Loading segment from ROM address 0x40100000
9429 04:40:54.838343 code (compression=1)
9430 04:40:54.844899 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9431 04:40:54.855092 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9432 04:40:54.855209 using LZMA
9433 04:40:54.863375 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9434 04:40:54.870212 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9435 04:40:54.873248 Loading segment from ROM address 0x4010001c
9436 04:40:54.873371 Entry Point 0x54601000
9437 04:40:54.876400 Loaded segments
9438 04:40:54.879767 NOTICE: MT8192 bl31_setup
9439 04:40:54.886664 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9440 04:40:54.890206 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9441 04:40:54.893504 WARNING: region 0:
9442 04:40:54.897195 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9443 04:40:54.897290 WARNING: region 1:
9444 04:40:54.903362 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9445 04:40:54.906970 WARNING: region 2:
9446 04:40:54.910181 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9447 04:40:54.913209 WARNING: region 3:
9448 04:40:54.916948 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9449 04:40:54.919974 WARNING: region 4:
9450 04:40:54.926923 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9451 04:40:54.927014 WARNING: region 5:
9452 04:40:54.929925 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9453 04:40:54.933614 WARNING: region 6:
9454 04:40:54.936885 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9455 04:40:54.936975 WARNING: region 7:
9456 04:40:54.943906 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9457 04:40:54.950589 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9458 04:40:54.953552 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9459 04:40:54.957137 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9460 04:40:54.963732 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9461 04:40:54.967250 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9462 04:40:54.970103 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9463 04:40:54.976967 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9464 04:40:54.980560 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9465 04:40:54.983529 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9466 04:40:54.990337 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9467 04:40:54.993665 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9468 04:40:55.000235 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9469 04:40:55.003613 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9470 04:40:55.006969 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9471 04:40:55.013791 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9472 04:40:55.016810 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9473 04:40:55.020565 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9474 04:40:55.027002 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9475 04:40:55.030602 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9476 04:40:55.033643 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9477 04:40:55.040509 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9478 04:40:55.043843 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9479 04:40:55.050524 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9480 04:40:55.053497 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9481 04:40:55.057486 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9482 04:40:55.063933 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9483 04:40:55.067444 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9484 04:40:55.074182 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9485 04:40:55.077615 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9486 04:40:55.080522 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9487 04:40:55.087717 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9488 04:40:55.090678 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9489 04:40:55.094405 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9490 04:40:55.100477 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9491 04:40:55.103950 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9492 04:40:55.107369 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9493 04:40:55.110382 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9494 04:40:55.117257 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9495 04:40:55.120802 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9496 04:40:55.124161 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9497 04:40:55.127162 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9498 04:40:55.134085 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9499 04:40:55.137268 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9500 04:40:55.140989 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9501 04:40:55.143977 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9502 04:40:55.150916 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9503 04:40:55.153973 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9504 04:40:55.157186 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9505 04:40:55.164099 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9506 04:40:55.167462 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9507 04:40:55.170908 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9508 04:40:55.177504 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9509 04:40:55.180533 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9510 04:40:55.187389 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9511 04:40:55.191027 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9512 04:40:55.197230 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9513 04:40:55.200981 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9514 04:40:55.204178 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9515 04:40:55.210694 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9516 04:40:55.214286 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9517 04:40:55.220828 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9518 04:40:55.224423 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9519 04:40:55.230769 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9520 04:40:55.234320 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9521 04:40:55.237350 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9522 04:40:55.244185 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9523 04:40:55.247987 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9524 04:40:55.254079 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9525 04:40:55.257739 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9526 04:40:55.260957 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9527 04:40:55.267763 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9528 04:40:55.271732 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9529 04:40:55.277889 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9530 04:40:55.281343 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9531 04:40:55.287840 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9532 04:40:55.291396 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9533 04:40:55.294317 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9534 04:40:55.301261 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9535 04:40:55.304717 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9536 04:40:55.311508 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9537 04:40:55.314711 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9538 04:40:55.321507 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9539 04:40:55.324501 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9540 04:40:55.328069 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9541 04:40:55.334498 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9542 04:40:55.338192 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9543 04:40:55.344790 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9544 04:40:55.347805 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9545 04:40:55.354820 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9546 04:40:55.357784 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9547 04:40:55.361607 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9548 04:40:55.367764 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9549 04:40:55.370982 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9550 04:40:55.377971 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9551 04:40:55.381707 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9552 04:40:55.388281 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9553 04:40:55.391428 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9554 04:40:55.394883 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9555 04:40:55.397896 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9556 04:40:55.404579 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9557 04:40:55.408145 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9558 04:40:55.411681 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9559 04:40:55.417927 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9560 04:40:55.421594 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9561 04:40:55.424602 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9562 04:40:55.431404 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9563 04:40:55.434930 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9564 04:40:55.441821 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9565 04:40:55.444753 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9566 04:40:55.448313 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9567 04:40:55.454791 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9568 04:40:55.458703 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9569 04:40:55.464820 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9570 04:40:55.468123 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9571 04:40:55.471858 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9572 04:40:55.478049 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9573 04:40:55.481781 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9574 04:40:55.484924 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9575 04:40:55.491695 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9576 04:40:55.495073 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9577 04:40:55.498557 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9578 04:40:55.502231 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9579 04:40:55.505140 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9580 04:40:55.511882 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9581 04:40:55.515632 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9582 04:40:55.518621 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9583 04:40:55.525159 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9584 04:40:55.528477 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9585 04:40:55.535382 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9586 04:40:55.538513 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9587 04:40:55.542120 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9588 04:40:55.549061 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9589 04:40:55.552040 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9590 04:40:55.555461 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9591 04:40:55.562147 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9592 04:40:55.565860 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9593 04:40:55.572260 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9594 04:40:55.575353 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9595 04:40:55.579059 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9596 04:40:55.585295 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9597 04:40:55.589105 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9598 04:40:55.595414 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9599 04:40:55.599120 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9600 04:40:55.602268 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9601 04:40:55.608577 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9602 04:40:55.612069 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9603 04:40:55.619003 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9604 04:40:55.622160 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9605 04:40:55.625373 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9606 04:40:55.631889 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9607 04:40:55.635192 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9608 04:40:55.638667 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9609 04:40:55.645638 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9610 04:40:55.648512 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9611 04:40:55.655175 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9612 04:40:55.658766 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9613 04:40:55.662241 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9614 04:40:55.668449 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9615 04:40:55.672090 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9616 04:40:55.678407 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9617 04:40:55.682198 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9618 04:40:55.685402 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9619 04:40:55.692275 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9620 04:40:55.695475 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9621 04:40:55.702323 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9622 04:40:55.705499 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9623 04:40:55.708658 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9624 04:40:55.715243 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9625 04:40:55.718960 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9626 04:40:55.721762 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9627 04:40:55.728260 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9628 04:40:55.732057 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9629 04:40:55.738369 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9630 04:40:55.741824 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9631 04:40:55.745271 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9632 04:40:55.751903 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9633 04:40:55.754783 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9634 04:40:55.761556 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9635 04:40:55.764975 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9636 04:40:55.768485 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9637 04:40:55.775432 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9638 04:40:55.778571 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9639 04:40:55.781682 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9640 04:40:55.788465 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9641 04:40:55.792162 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9642 04:40:55.798405 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9643 04:40:55.802091 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9644 04:40:55.805081 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9645 04:40:55.811888 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9646 04:40:55.814905 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9647 04:40:55.821364 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9648 04:40:55.825073 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9649 04:40:55.831450 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9650 04:40:55.834967 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9651 04:40:55.838653 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9652 04:40:55.844920 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9653 04:40:55.848607 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9654 04:40:55.855048 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9655 04:40:55.858486 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9656 04:40:55.861487 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9657 04:40:55.868216 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9658 04:40:55.871922 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9659 04:40:55.878016 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9660 04:40:55.881484 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9661 04:40:55.888033 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9662 04:40:55.891446 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9663 04:40:55.894624 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9664 04:40:55.901639 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9665 04:40:55.904803 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9666 04:40:55.911104 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9667 04:40:55.914782 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9668 04:40:55.918081 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9669 04:40:55.924537 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9670 04:40:55.928218 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9671 04:40:55.935015 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9672 04:40:55.937940 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9673 04:40:55.941412 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9674 04:40:55.948141 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9675 04:40:55.951123 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9676 04:40:55.957927 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9677 04:40:55.961433 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9678 04:40:55.967578 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9679 04:40:55.971382 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9680 04:40:55.974488 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9681 04:40:55.981155 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9682 04:40:55.984370 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9683 04:40:55.990936 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9684 04:40:55.994494 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9685 04:40:55.997841 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9686 04:40:56.004511 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9687 04:40:56.007526 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9688 04:40:56.011327 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9689 04:40:56.014374 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9690 04:40:56.021089 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9691 04:40:56.024307 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9692 04:40:56.027935 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9693 04:40:56.034019 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9694 04:40:56.037663 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9695 04:40:56.041338 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9696 04:40:56.047824 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9697 04:40:56.051034 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9698 04:40:56.057411 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9699 04:40:56.061040 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9700 04:40:56.064197 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9701 04:40:56.070723 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9702 04:40:56.074314 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9703 04:40:56.077308 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9704 04:40:56.084369 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9705 04:40:56.087161 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9706 04:40:56.090847 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9707 04:40:56.097699 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9708 04:40:56.100660 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9709 04:40:56.107451 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9710 04:40:56.110339 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9711 04:40:56.113924 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9712 04:40:56.120686 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9713 04:40:56.123758 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9714 04:40:56.127399 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9715 04:40:56.133599 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9716 04:40:56.137128 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9717 04:40:56.140594 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9718 04:40:56.147452 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9719 04:40:56.150529 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9720 04:40:56.154146 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9721 04:40:56.160791 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9722 04:40:56.163847 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9723 04:40:56.170611 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9724 04:40:56.173854 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9725 04:40:56.177399 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9726 04:40:56.180399 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9727 04:40:56.186941 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9728 04:40:56.190364 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9729 04:40:56.193985 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9730 04:40:56.196869 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9731 04:40:56.203827 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9732 04:40:56.206959 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9733 04:40:56.210607 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9734 04:40:56.213762 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9735 04:40:56.220260 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9736 04:40:56.223232 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9737 04:40:56.227019 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9738 04:40:56.233291 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9739 04:40:56.236605 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9740 04:40:56.240309 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9741 04:40:56.246948 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9742 04:40:56.249845 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9743 04:40:56.256764 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9744 04:40:56.260268 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9745 04:40:56.266908 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9746 04:40:56.270078 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9747 04:40:56.273737 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9748 04:40:56.280150 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9749 04:40:56.283660 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9750 04:40:56.286728 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9751 04:40:56.293528 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9752 04:40:56.297026 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9753 04:40:56.303197 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9754 04:40:56.306735 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9755 04:40:56.310243 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9756 04:40:56.316575 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9757 04:40:56.320360 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9758 04:40:56.326573 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9759 04:40:56.330282 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9760 04:40:56.336663 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9761 04:40:56.339890 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9762 04:40:56.342950 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9763 04:40:56.349619 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9764 04:40:56.353303 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9765 04:40:56.359745 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9766 04:40:56.362758 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9767 04:40:56.366250 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9768 04:40:56.372927 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9769 04:40:56.376647 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9770 04:40:56.382885 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9771 04:40:56.386442 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9772 04:40:56.389541 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9773 04:40:56.396376 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9774 04:40:56.399357 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9775 04:40:56.406644 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9776 04:40:56.409559 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9777 04:40:56.416531 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9778 04:40:56.419452 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9779 04:40:56.422918 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9780 04:40:56.429871 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9781 04:40:56.432936 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9782 04:40:56.439260 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9783 04:40:56.442766 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9784 04:40:56.446386 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9785 04:40:56.452531 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9786 04:40:56.456250 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9787 04:40:56.462411 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9788 04:40:56.465827 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9789 04:40:56.469384 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9790 04:40:56.475927 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9791 04:40:56.479052 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9792 04:40:56.485863 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9793 04:40:56.488818 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9794 04:40:56.492364 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9795 04:40:56.498843 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9796 04:40:56.502442 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9797 04:40:56.508960 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9798 04:40:56.512047 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9799 04:40:56.519099 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9800 04:40:56.522289 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9801 04:40:56.525239 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9802 04:40:56.531883 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9803 04:40:56.535556 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9804 04:40:56.541844 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9805 04:40:56.545602 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9806 04:40:56.548655 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9807 04:40:56.555478 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9808 04:40:56.558807 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9809 04:40:56.565144 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9810 04:40:56.568868 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9811 04:40:56.571744 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9812 04:40:56.578744 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9813 04:40:56.581497 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9814 04:40:56.588691 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9815 04:40:56.591968 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9816 04:40:56.598428 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9817 04:40:56.601616 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9818 04:40:56.604847 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9819 04:40:56.611615 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9820 04:40:56.615208 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9821 04:40:56.621972 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9822 04:40:56.625263 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9823 04:40:56.631900 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9824 04:40:56.634949 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9825 04:40:56.641625 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9826 04:40:56.645383 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9827 04:40:56.648430 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9828 04:40:56.655257 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9829 04:40:56.658326 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9830 04:40:56.665330 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9831 04:40:56.668256 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9832 04:40:56.675037 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9833 04:40:56.678454 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9834 04:40:56.681399 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9835 04:40:56.688018 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9836 04:40:56.691346 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9837 04:40:56.698131 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9838 04:40:56.701761 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9839 04:40:56.707921 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9840 04:40:56.711258 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9841 04:40:56.717881 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9842 04:40:56.721341 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9843 04:40:56.725013 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9844 04:40:56.731617 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9845 04:40:56.734707 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9846 04:40:56.741382 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9847 04:40:56.744940 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9848 04:40:56.751172 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9849 04:40:56.754697 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9850 04:40:56.757841 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9851 04:40:56.764809 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9852 04:40:56.767762 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9853 04:40:56.774257 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9854 04:40:56.777707 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9855 04:40:56.784555 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9856 04:40:56.788120 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9857 04:40:56.790837 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9858 04:40:56.798029 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9859 04:40:56.801043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9860 04:40:56.804405 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9861 04:40:56.811379 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9862 04:40:56.814525 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9863 04:40:56.821354 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9864 04:40:56.824508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9865 04:40:56.830662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9866 04:40:56.834246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9867 04:40:56.840927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9868 04:40:56.843997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9869 04:40:56.850740 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9870 04:40:56.854398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9871 04:40:56.861206 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9872 04:40:56.864359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9873 04:40:56.870562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9874 04:40:56.874423 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9875 04:40:56.880678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9876 04:40:56.884223 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9877 04:40:56.891150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9878 04:40:56.894230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9879 04:40:56.900738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9880 04:40:56.904134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9881 04:40:56.910690 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9882 04:40:56.914009 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9883 04:40:56.921153 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9884 04:40:56.924219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9885 04:40:56.930403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9886 04:40:56.933964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9887 04:40:56.940909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9888 04:40:56.943871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9889 04:40:56.950710 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9890 04:40:56.953946 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9891 04:40:56.957404 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9892 04:40:56.960570 INFO: [APUAPC] vio 0
9893 04:40:56.967443 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9894 04:40:56.970521 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9895 04:40:56.973639 INFO: [APUAPC] D0_APC_0: 0x400510
9896 04:40:56.977387 INFO: [APUAPC] D0_APC_1: 0x0
9897 04:40:56.980569 INFO: [APUAPC] D0_APC_2: 0x1540
9898 04:40:56.983493 INFO: [APUAPC] D0_APC_3: 0x0
9899 04:40:56.987299 INFO: [APUAPC] D1_APC_0: 0xffffffff
9900 04:40:56.990396 INFO: [APUAPC] D1_APC_1: 0xffffffff
9901 04:40:56.994174 INFO: [APUAPC] D1_APC_2: 0x3fffff
9902 04:40:56.997069 INFO: [APUAPC] D1_APC_3: 0x0
9903 04:40:57.000431 INFO: [APUAPC] D2_APC_0: 0xffffffff
9904 04:40:57.003474 INFO: [APUAPC] D2_APC_1: 0xffffffff
9905 04:40:57.007276 INFO: [APUAPC] D2_APC_2: 0x3fffff
9906 04:40:57.007390 INFO: [APUAPC] D2_APC_3: 0x0
9907 04:40:57.010386 INFO: [APUAPC] D3_APC_0: 0xffffffff
9908 04:40:57.016988 INFO: [APUAPC] D3_APC_1: 0xffffffff
9909 04:40:57.020441 INFO: [APUAPC] D3_APC_2: 0x3fffff
9910 04:40:57.020528 INFO: [APUAPC] D3_APC_3: 0x0
9911 04:40:57.023883 INFO: [APUAPC] D4_APC_0: 0xffffffff
9912 04:40:57.026949 INFO: [APUAPC] D4_APC_1: 0xffffffff
9913 04:40:57.030328 INFO: [APUAPC] D4_APC_2: 0x3fffff
9914 04:40:57.033722 INFO: [APUAPC] D4_APC_3: 0x0
9915 04:40:57.036698 INFO: [APUAPC] D5_APC_0: 0xffffffff
9916 04:40:57.040375 INFO: [APUAPC] D5_APC_1: 0xffffffff
9917 04:40:57.043438 INFO: [APUAPC] D5_APC_2: 0x3fffff
9918 04:40:57.046950 INFO: [APUAPC] D5_APC_3: 0x0
9919 04:40:57.049950 INFO: [APUAPC] D6_APC_0: 0xffffffff
9920 04:40:57.053820 INFO: [APUAPC] D6_APC_1: 0xffffffff
9921 04:40:57.056891 INFO: [APUAPC] D6_APC_2: 0x3fffff
9922 04:40:57.059963 INFO: [APUAPC] D6_APC_3: 0x0
9923 04:40:57.063526 INFO: [APUAPC] D7_APC_0: 0xffffffff
9924 04:40:57.066549 INFO: [APUAPC] D7_APC_1: 0xffffffff
9925 04:40:57.070381 INFO: [APUAPC] D7_APC_2: 0x3fffff
9926 04:40:57.073508 INFO: [APUAPC] D7_APC_3: 0x0
9927 04:40:57.077262 INFO: [APUAPC] D8_APC_0: 0xffffffff
9928 04:40:57.080351 INFO: [APUAPC] D8_APC_1: 0xffffffff
9929 04:40:57.083370 INFO: [APUAPC] D8_APC_2: 0x3fffff
9930 04:40:57.086483 INFO: [APUAPC] D8_APC_3: 0x0
9931 04:40:57.090209 INFO: [APUAPC] D9_APC_0: 0xffffffff
9932 04:40:57.093387 INFO: [APUAPC] D9_APC_1: 0xffffffff
9933 04:40:57.096505 INFO: [APUAPC] D9_APC_2: 0x3fffff
9934 04:40:57.100341 INFO: [APUAPC] D9_APC_3: 0x0
9935 04:40:57.103322 INFO: [APUAPC] D10_APC_0: 0xffffffff
9936 04:40:57.106450 INFO: [APUAPC] D10_APC_1: 0xffffffff
9937 04:40:57.109837 INFO: [APUAPC] D10_APC_2: 0x3fffff
9938 04:40:57.113277 INFO: [APUAPC] D10_APC_3: 0x0
9939 04:40:57.116846 INFO: [APUAPC] D11_APC_0: 0xffffffff
9940 04:40:57.120048 INFO: [APUAPC] D11_APC_1: 0xffffffff
9941 04:40:57.123654 INFO: [APUAPC] D11_APC_2: 0x3fffff
9942 04:40:57.126864 INFO: [APUAPC] D11_APC_3: 0x0
9943 04:40:57.129837 INFO: [APUAPC] D12_APC_0: 0xffffffff
9944 04:40:57.133424 INFO: [APUAPC] D12_APC_1: 0xffffffff
9945 04:40:57.136812 INFO: [APUAPC] D12_APC_2: 0x3fffff
9946 04:40:57.140183 INFO: [APUAPC] D12_APC_3: 0x0
9947 04:40:57.143658 INFO: [APUAPC] D13_APC_0: 0xffffffff
9948 04:40:57.146755 INFO: [APUAPC] D13_APC_1: 0xffffffff
9949 04:40:57.149970 INFO: [APUAPC] D13_APC_2: 0x3fffff
9950 04:40:57.153405 INFO: [APUAPC] D13_APC_3: 0x0
9951 04:40:57.156531 INFO: [APUAPC] D14_APC_0: 0xffffffff
9952 04:40:57.159846 INFO: [APUAPC] D14_APC_1: 0xffffffff
9953 04:40:57.163319 INFO: [APUAPC] D14_APC_2: 0x3fffff
9954 04:40:57.166906 INFO: [APUAPC] D14_APC_3: 0x0
9955 04:40:57.169767 INFO: [APUAPC] D15_APC_0: 0xffffffff
9956 04:40:57.173616 INFO: [APUAPC] D15_APC_1: 0xffffffff
9957 04:40:57.176635 INFO: [APUAPC] D15_APC_2: 0x3fffff
9958 04:40:57.179781 INFO: [APUAPC] D15_APC_3: 0x0
9959 04:40:57.183425 INFO: [APUAPC] APC_CON: 0x4
9960 04:40:57.186592 INFO: [NOCDAPC] D0_APC_0: 0x0
9961 04:40:57.189838 INFO: [NOCDAPC] D0_APC_1: 0x0
9962 04:40:57.189917 INFO: [NOCDAPC] D1_APC_0: 0x0
9963 04:40:57.193476 INFO: [NOCDAPC] D1_APC_1: 0xfff
9964 04:40:57.196542 INFO: [NOCDAPC] D2_APC_0: 0x0
9965 04:40:57.199702 INFO: [NOCDAPC] D2_APC_1: 0xfff
9966 04:40:57.203440 INFO: [NOCDAPC] D3_APC_0: 0x0
9967 04:40:57.206608 INFO: [NOCDAPC] D3_APC_1: 0xfff
9968 04:40:57.209678 INFO: [NOCDAPC] D4_APC_0: 0x0
9969 04:40:57.213349 INFO: [NOCDAPC] D4_APC_1: 0xfff
9970 04:40:57.216401 INFO: [NOCDAPC] D5_APC_0: 0x0
9971 04:40:57.219898 INFO: [NOCDAPC] D5_APC_1: 0xfff
9972 04:40:57.219976 INFO: [NOCDAPC] D6_APC_0: 0x0
9973 04:40:57.223379 INFO: [NOCDAPC] D6_APC_1: 0xfff
9974 04:40:57.226235 INFO: [NOCDAPC] D7_APC_0: 0x0
9975 04:40:57.229869 INFO: [NOCDAPC] D7_APC_1: 0xfff
9976 04:40:57.233203 INFO: [NOCDAPC] D8_APC_0: 0x0
9977 04:40:57.236805 INFO: [NOCDAPC] D8_APC_1: 0xfff
9978 04:40:57.239976 INFO: [NOCDAPC] D9_APC_0: 0x0
9979 04:40:57.243273 INFO: [NOCDAPC] D9_APC_1: 0xfff
9980 04:40:57.246262 INFO: [NOCDAPC] D10_APC_0: 0x0
9981 04:40:57.249492 INFO: [NOCDAPC] D10_APC_1: 0xfff
9982 04:40:57.253197 INFO: [NOCDAPC] D11_APC_0: 0x0
9983 04:40:57.256619 INFO: [NOCDAPC] D11_APC_1: 0xfff
9984 04:40:57.256696 INFO: [NOCDAPC] D12_APC_0: 0x0
9985 04:40:57.259589 INFO: [NOCDAPC] D12_APC_1: 0xfff
9986 04:40:57.263067 INFO: [NOCDAPC] D13_APC_0: 0x0
9987 04:40:57.266361 INFO: [NOCDAPC] D13_APC_1: 0xfff
9988 04:40:57.269696 INFO: [NOCDAPC] D14_APC_0: 0x0
9989 04:40:57.273145 INFO: [NOCDAPC] D14_APC_1: 0xfff
9990 04:40:57.276413 INFO: [NOCDAPC] D15_APC_0: 0x0
9991 04:40:57.279720 INFO: [NOCDAPC] D15_APC_1: 0xfff
9992 04:40:57.282612 INFO: [NOCDAPC] APC_CON: 0x4
9993 04:40:57.286254 INFO: [APUAPC] set_apusys_apc done
9994 04:40:57.289313 INFO: [DEVAPC] devapc_init done
9995 04:40:57.292948 INFO: GICv3 without legacy support detected.
9996 04:40:57.296160 INFO: ARM GICv3 driver initialized in EL3
9997 04:40:57.299258 INFO: Maximum SPI INTID supported: 639
9998 04:40:57.306131 INFO: BL31: Initializing runtime services
9999 04:40:57.309215 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10000 04:40:57.313010 INFO: SPM: enable CPC mode
10001 04:40:57.319313 INFO: mcdi ready for mcusys-off-idle and system suspend
10002 04:40:57.323003 INFO: BL31: Preparing for EL3 exit to normal world
10003 04:40:57.326314 INFO: Entry point address = 0x80000000
10004 04:40:57.329231 INFO: SPSR = 0x8
10005 04:40:57.334647
10006 04:40:57.334741
10007 04:40:57.334842
10008 04:40:57.337915 Starting depthcharge on Spherion...
10009 04:40:57.338007
10010 04:40:57.338069 Wipe memory regions:
10011 04:40:57.338160
10012 04:40:57.338973 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10013 04:40:57.339142 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10014 04:40:57.339252 Setting prompt string to ['asurada:']
10015 04:40:57.339360 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10016 04:40:57.341518 [0x00000040000000, 0x00000054600000)
10017 04:40:57.463848
10018 04:40:57.464002 [0x00000054660000, 0x00000080000000)
10019 04:40:57.724132
10020 04:40:57.724327 [0x000000821a7280, 0x000000ffe64000)
10021 04:40:58.469092
10022 04:40:58.469245 [0x00000100000000, 0x00000240000000)
10023 04:41:00.359215
10024 04:41:00.362918 Initializing XHCI USB controller at 0x11200000.
10025 04:41:01.400292
10026 04:41:01.403812 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10027 04:41:01.403927
10028 04:41:01.404016
10029 04:41:01.404107
10030 04:41:01.404409 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10032 04:41:01.504813 asurada: tftpboot 192.168.201.1 11241315/tftp-deploy-7vkciubz/kernel/image.itb 11241315/tftp-deploy-7vkciubz/kernel/cmdline
10033 04:41:01.504974 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10034 04:41:01.505114 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10035 04:41:01.508958 tftpboot 192.168.201.1 11241315/tftp-deploy-7vkciubz/kernel/image.ittp-deploy-7vkciubz/kernel/cmdline
10036 04:41:01.509058
10037 04:41:01.509125 Waiting for link
10038 04:41:01.669582
10039 04:41:01.669761 R8152: Initializing
10040 04:41:01.669861
10041 04:41:01.673106 Version 9 (ocp_data = 6010)
10042 04:41:01.673213
10043 04:41:01.675997 R8152: Done initializing
10044 04:41:01.676114
10045 04:41:01.676238 Adding net device
10046 04:41:03.548727
10047 04:41:03.548884 done.
10048 04:41:03.548989
10049 04:41:03.549088 MAC: 00:e0:4c:78:7a:aa
10050 04:41:03.549180
10051 04:41:03.551899 Sending DHCP discover... done.
10052 04:41:03.551987
10053 04:41:03.555909 Waiting for reply... done.
10054 04:41:03.556005
10055 04:41:03.558583 Sending DHCP request... done.
10056 04:41:03.558678
10057 04:41:03.562196 Waiting for reply... done.
10058 04:41:03.562274
10059 04:41:03.562338 My ip is 192.168.201.12
10060 04:41:03.562414
10061 04:41:03.565407 The DHCP server ip is 192.168.201.1
10062 04:41:03.565533
10063 04:41:03.572099 TFTP server IP predefined by user: 192.168.201.1
10064 04:41:03.572195
10065 04:41:03.578772 Bootfile predefined by user: 11241315/tftp-deploy-7vkciubz/kernel/image.itb
10066 04:41:03.578850
10067 04:41:03.581867 Sending tftp read request... done.
10068 04:41:03.581948
10069 04:41:03.585418 Waiting for the transfer...
10070 04:41:03.585498
10071 04:41:03.845906 00000000 ################################################################
10072 04:41:03.846043
10073 04:41:04.105762 00080000 ################################################################
10074 04:41:04.105927
10075 04:41:04.363277 00100000 ################################################################
10076 04:41:04.363443
10077 04:41:04.617169 00180000 ################################################################
10078 04:41:04.617311
10079 04:41:04.874808 00200000 ################################################################
10080 04:41:04.874949
10081 04:41:05.126823 00280000 ################################################################
10082 04:41:05.126970
10083 04:41:05.392767 00300000 ################################################################
10084 04:41:05.392930
10085 04:41:05.658072 00380000 ################################################################
10086 04:41:05.658223
10087 04:41:05.920049 00400000 ################################################################
10088 04:41:05.920206
10089 04:41:06.187485 00480000 ################################################################
10090 04:41:06.187658
10091 04:41:06.460099 00500000 ################################################################
10092 04:41:06.460237
10093 04:41:06.730007 00580000 ################################################################
10094 04:41:06.730163
10095 04:41:06.999513 00600000 ################################################################
10096 04:41:06.999683
10097 04:41:07.256477 00680000 ################################################################
10098 04:41:07.256618
10099 04:41:07.522658 00700000 ################################################################
10100 04:41:07.522799
10101 04:41:07.786755 00780000 ################################################################
10102 04:41:07.786894
10103 04:41:08.054064 00800000 ################################################################
10104 04:41:08.054205
10105 04:41:08.313098 00880000 ################################################################
10106 04:41:08.313237
10107 04:41:08.569675 00900000 ################################################################
10108 04:41:08.569829
10109 04:41:08.838559 00980000 ################################################################
10110 04:41:08.838691
10111 04:41:09.104107 00a00000 ################################################################
10112 04:41:09.104243
10113 04:41:09.367706 00a80000 ################################################################
10114 04:41:09.367838
10115 04:41:09.626207 00b00000 ################################################################
10116 04:41:09.626350
10117 04:41:09.897086 00b80000 ################################################################
10118 04:41:09.897222
10119 04:41:10.169593 00c00000 ################################################################
10120 04:41:10.169767
10121 04:41:10.432607 00c80000 ################################################################
10122 04:41:10.432742
10123 04:41:10.693354 00d00000 ################################################################
10124 04:41:10.693495
10125 04:41:10.956474 00d80000 ################################################################
10126 04:41:10.956615
10127 04:41:11.204772 00e00000 ################################################################
10128 04:41:11.204922
10129 04:41:11.450729 00e80000 ################################################################
10130 04:41:11.450909
10131 04:41:11.698777 00f00000 ################################################################
10132 04:41:11.698915
10133 04:41:11.942660 00f80000 ################################################################
10134 04:41:11.942798
10135 04:41:12.187579 01000000 ################################################################
10136 04:41:12.187724
10137 04:41:12.437860 01080000 ################################################################
10138 04:41:12.438011
10139 04:41:12.696981 01100000 ################################################################
10140 04:41:12.697158
10141 04:41:12.938232 01180000 ################################################################
10142 04:41:12.938415
10143 04:41:13.181325 01200000 ################################################################
10144 04:41:13.181515
10145 04:41:13.424319 01280000 ################################################################
10146 04:41:13.424475
10147 04:41:13.668432 01300000 ################################################################
10148 04:41:13.668586
10149 04:41:13.911710 01380000 ################################################################
10150 04:41:13.911865
10151 04:41:14.154779 01400000 ################################################################
10152 04:41:14.154917
10153 04:41:14.398405 01480000 ################################################################
10154 04:41:14.398558
10155 04:41:14.642358 01500000 ################################################################
10156 04:41:14.642534
10157 04:41:14.887918 01580000 ################################################################
10158 04:41:14.888069
10159 04:41:15.141132 01600000 ################################################################
10160 04:41:15.141286
10161 04:41:15.394015 01680000 ################################################################
10162 04:41:15.394157
10163 04:41:15.643208 01700000 ################################################################
10164 04:41:15.643347
10165 04:41:15.894203 01780000 ################################################################
10166 04:41:15.894381
10167 04:41:16.151466 01800000 ################################################################
10168 04:41:16.151652
10169 04:41:16.410177 01880000 ################################################################
10170 04:41:16.410317
10171 04:41:16.688638 01900000 ################################################################
10172 04:41:16.688779
10173 04:41:16.981041 01980000 ################################################################
10174 04:41:16.981187
10175 04:41:17.251363 01a00000 ################################################################
10176 04:41:17.251568
10177 04:41:17.528304 01a80000 ################################################################
10178 04:41:17.528444
10179 04:41:17.794896 01b00000 ################################################################
10180 04:41:17.795029
10181 04:41:18.058830 01b80000 ################################################################
10182 04:41:18.058992
10183 04:41:18.338289 01c00000 ################################################################
10184 04:41:18.338460
10185 04:41:18.586628 01c80000 ################################################################
10186 04:41:18.586787
10187 04:41:18.833063 01d00000 ################################################################
10188 04:41:18.833240
10189 04:41:19.078869 01d80000 ################################################################
10190 04:41:19.079012
10191 04:41:19.328463 01e00000 ################################################################
10192 04:41:19.328618
10193 04:41:19.571163 01e80000 ################################################################
10194 04:41:19.571351
10195 04:41:19.811556 01f00000 ################################################################
10196 04:41:19.811705
10197 04:41:20.051974 01f80000 ################################################################
10198 04:41:20.052115
10199 04:41:20.297319 02000000 ################################################################
10200 04:41:20.297470
10201 04:41:20.553917 02080000 ################################################################
10202 04:41:20.554080
10203 04:41:20.810548 02100000 ################################################################
10204 04:41:20.810713
10205 04:41:21.060160 02180000 ################################################################
10206 04:41:21.060308
10207 04:41:21.312476 02200000 ################################################################
10208 04:41:21.312615
10209 04:41:21.564851 02280000 ################################################################
10210 04:41:21.565035
10211 04:41:21.818801 02300000 ################################################################
10212 04:41:21.818967
10213 04:41:22.067818 02380000 ################################################################
10214 04:41:22.068003
10215 04:41:22.313056 02400000 ################################################################
10216 04:41:22.313203
10217 04:41:22.556424 02480000 ################################################################
10218 04:41:22.556580
10219 04:41:22.799764 02500000 ################################################################
10220 04:41:22.799937
10221 04:41:23.043487 02580000 ################################################################
10222 04:41:23.043685
10223 04:41:23.295941 02600000 ################################################################
10224 04:41:23.296091
10225 04:41:23.546516 02680000 ################################################################
10226 04:41:23.546724
10227 04:41:23.804465 02700000 ################################################################
10228 04:41:23.804608
10229 04:41:24.053491 02780000 ################################################################
10230 04:41:24.053661
10231 04:41:24.299239 02800000 ################################################################
10232 04:41:24.299393
10233 04:41:24.542085 02880000 ################################################################
10234 04:41:24.542274
10235 04:41:24.782161 02900000 ################################################################
10236 04:41:24.782313
10237 04:41:25.022579 02980000 ################################################################
10238 04:41:25.022747
10239 04:41:25.262646 02a00000 ################################################################
10240 04:41:25.262802
10241 04:41:25.510321 02a80000 ################################################################
10242 04:41:25.510460
10243 04:41:25.754857 02b00000 ################################################################
10244 04:41:25.755033
10245 04:41:26.000069 02b80000 ################################################################
10246 04:41:26.000200
10247 04:41:26.244530 02c00000 ################################################################
10248 04:41:26.244688
10249 04:41:26.489345 02c80000 ################################################################
10250 04:41:26.489495
10251 04:41:26.734650 02d00000 ################################################################
10252 04:41:26.734786
10253 04:41:26.982853 02d80000 ################################################################
10254 04:41:26.983017
10255 04:41:27.235674 02e00000 ################################################################
10256 04:41:27.235809
10257 04:41:27.481109 02e80000 ################################################################
10258 04:41:27.481322
10259 04:41:27.722710 02f00000 ################################################################
10260 04:41:27.722880
10261 04:41:27.957761 02f80000 ############################################################## done.
10262 04:41:27.957901
10263 04:41:27.960828 The bootfile was 50314826 bytes long.
10264 04:41:27.960931
10265 04:41:27.963974 Sending tftp read request... done.
10266 04:41:27.964058
10267 04:41:27.964122 Waiting for the transfer...
10268 04:41:27.964182
10269 04:41:27.967340 00000000 # done.
10270 04:41:27.967426
10271 04:41:27.973815 Command line loaded dynamically from TFTP file: 11241315/tftp-deploy-7vkciubz/kernel/cmdline
10272 04:41:27.973900
10273 04:41:27.987335 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10274 04:41:27.987457
10275 04:41:27.990731 Loading FIT.
10276 04:41:27.990836
10277 04:41:27.993855 Image ramdisk-1 has 39229146 bytes.
10278 04:41:27.993939
10279 04:41:27.994005 Image fdt-1 has 47278 bytes.
10280 04:41:27.997509
10281 04:41:27.997592 Image kernel-1 has 11036366 bytes.
10282 04:41:27.997658
10283 04:41:28.007535 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10284 04:41:28.007665
10285 04:41:28.023982 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10286 04:41:28.024114
10287 04:41:28.030560 Choosing best match conf-1 for compat google,spherion-rev2.
10288 04:41:28.034305
10289 04:41:28.039657 Connected to device vid:did:rid of 1ae0:0028:00
10290 04:41:28.047253
10291 04:41:28.050910 tpm_get_response: command 0x17b, return code 0x0
10292 04:41:28.051040
10293 04:41:28.054013 ec_init: CrosEC protocol v3 supported (256, 248)
10294 04:41:28.057820
10295 04:41:28.061083 tpm_cleanup: add release locality here.
10296 04:41:28.061196
10297 04:41:28.061262 Shutting down all USB controllers.
10298 04:41:28.064872
10299 04:41:28.064995 Removing current net device
10300 04:41:28.065122
10301 04:41:28.071283 Exiting depthcharge with code 4 at timestamp: 60016936
10302 04:41:28.071367
10303 04:41:28.075045 LZMA decompressing kernel-1 to 0x821a6718
10304 04:41:28.075130
10305 04:41:28.078118 LZMA decompressing kernel-1 to 0x40000000
10306 04:41:29.467036
10307 04:41:29.467635 jumping to kernel
10308 04:41:29.469162 end: 2.2.4 bootloader-commands (duration 00:00:32) [common]
10309 04:41:29.469835 start: 2.2.5 auto-login-action (timeout 00:03:53) [common]
10310 04:41:29.470243 Setting prompt string to ['Linux version [0-9]']
10311 04:41:29.470601 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10312 04:41:29.470954 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10313 04:41:29.548011
10314 04:41:29.551494 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10315 04:41:29.555223 start: 2.2.5.1 login-action (timeout 00:03:53) [common]
10316 04:41:29.555371 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10317 04:41:29.555527 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10318 04:41:29.555632 Using line separator: #'\n'#
10319 04:41:29.555739 No login prompt set.
10320 04:41:29.555863 Parsing kernel messages
10321 04:41:29.555939 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10322 04:41:29.556076 [login-action] Waiting for messages, (timeout 00:03:53)
10323 04:41:29.574594 [ 0.000000] Linux version 6.1.42-cip2 (KernelCI@build-j7071-arm64-gcc-10-defconfig-arm64-chromebook-7p24g) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Aug 9 04:18:34 UTC 2023
10324 04:41:29.577956 [ 0.000000] random: crng init done
10325 04:41:29.581564 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10326 04:41:29.584491 [ 0.000000] efi: UEFI not found.
10327 04:41:29.594452 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10328 04:41:29.601482 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10329 04:41:29.611057 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10330 04:41:29.621515 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10331 04:41:29.628213 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10332 04:41:29.631412 [ 0.000000] printk: bootconsole [mtk8250] enabled
10333 04:41:29.639810 [ 0.000000] NUMA: No NUMA configuration found
10334 04:41:29.646911 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10335 04:41:29.653203 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10336 04:41:29.653449 [ 0.000000] Zone ranges:
10337 04:41:29.659360 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10338 04:41:29.662942 [ 0.000000] DMA32 empty
10339 04:41:29.670026 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10340 04:41:29.673202 [ 0.000000] Movable zone start for each node
10341 04:41:29.676668 [ 0.000000] Early memory node ranges
10342 04:41:29.682770 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10343 04:41:29.689544 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10344 04:41:29.696192 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10345 04:41:29.703069 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10346 04:41:29.709999 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10347 04:41:29.716459 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10348 04:41:29.772438 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10349 04:41:29.779145 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10350 04:41:29.785366 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10351 04:41:29.788919 [ 0.000000] psci: probing for conduit method from DT.
10352 04:41:29.795506 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10353 04:41:29.798806 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10354 04:41:29.805232 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10355 04:41:29.808879 [ 0.000000] psci: SMC Calling Convention v1.2
10356 04:41:29.815590 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10357 04:41:29.818614 [ 0.000000] Detected VIPT I-cache on CPU0
10358 04:41:29.825437 [ 0.000000] CPU features: detected: GIC system register CPU interface
10359 04:41:29.831606 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10360 04:41:29.838619 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10361 04:41:29.845534 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10362 04:41:29.851789 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10363 04:41:29.858684 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10364 04:41:29.865025 [ 0.000000] alternatives: applying boot alternatives
10365 04:41:29.868643 [ 0.000000] Fallback order for Node 0: 0
10366 04:41:29.878204 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10367 04:41:29.881307 [ 0.000000] Policy zone: Normal
10368 04:41:29.895213 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10369 04:41:29.904732 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10370 04:41:29.915258 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10371 04:41:29.925437 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10372 04:41:29.932316 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10373 04:41:29.935643 <6>[ 0.000000] software IO TLB: area num 8.
10374 04:41:29.992226 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10375 04:41:30.140955 <6>[ 0.000000] Memory: 7931248K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 421520K reserved, 32768K cma-reserved)
10376 04:41:30.147564 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10377 04:41:30.154172 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10378 04:41:30.157426 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10379 04:41:30.164135 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10380 04:41:30.170915 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10381 04:41:30.173962 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10382 04:41:30.184204 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10383 04:41:30.190600 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10384 04:41:30.197201 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10385 04:41:30.204058 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10386 04:41:30.207234 <6>[ 0.000000] GICv3: 608 SPIs implemented
10387 04:41:30.210296 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10388 04:41:30.217461 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10389 04:41:30.220521 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10390 04:41:30.227266 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10391 04:41:30.240796 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10392 04:41:30.254021 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10393 04:41:30.260586 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10394 04:41:30.268226 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10395 04:41:30.281537 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10396 04:41:30.287718 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10397 04:41:30.294654 <6>[ 0.009239] Console: colour dummy device 80x25
10398 04:41:30.304875 <6>[ 0.013967] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10399 04:41:30.311654 <6>[ 0.024408] pid_max: default: 32768 minimum: 301
10400 04:41:30.314817 <6>[ 0.029282] LSM: Security Framework initializing
10401 04:41:30.321443 <6>[ 0.034221] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10402 04:41:30.331482 <6>[ 0.042033] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10403 04:41:30.337693 <6>[ 0.051464] cblist_init_generic: Setting adjustable number of callback queues.
10404 04:41:30.344713 <6>[ 0.058956] cblist_init_generic: Setting shift to 3 and lim to 1.
10405 04:41:30.354305 <6>[ 0.065332] cblist_init_generic: Setting adjustable number of callback queues.
10406 04:41:30.357741 <6>[ 0.072758] cblist_init_generic: Setting shift to 3 and lim to 1.
10407 04:41:30.364466 <6>[ 0.079156] rcu: Hierarchical SRCU implementation.
10408 04:41:30.371414 <6>[ 0.084170] rcu: Max phase no-delay instances is 1000.
10409 04:41:30.377972 <6>[ 0.091204] EFI services will not be available.
10410 04:41:30.381349 <6>[ 0.096171] smp: Bringing up secondary CPUs ...
10411 04:41:30.388957 <6>[ 0.101221] Detected VIPT I-cache on CPU1
10412 04:41:30.395395 <6>[ 0.101291] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10413 04:41:30.402500 <6>[ 0.101321] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10414 04:41:30.405380 <6>[ 0.101661] Detected VIPT I-cache on CPU2
10415 04:41:30.412382 <6>[ 0.101715] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10416 04:41:30.419152 <6>[ 0.101732] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10417 04:41:30.425968 <6>[ 0.101987] Detected VIPT I-cache on CPU3
10418 04:41:30.432075 <6>[ 0.102034] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10419 04:41:30.438937 <6>[ 0.102047] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10420 04:41:30.442029 <6>[ 0.102350] CPU features: detected: Spectre-v4
10421 04:41:30.448763 <6>[ 0.102356] CPU features: detected: Spectre-BHB
10422 04:41:30.452460 <6>[ 0.102362] Detected PIPT I-cache on CPU4
10423 04:41:30.458562 <6>[ 0.102419] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10424 04:41:30.465328 <6>[ 0.102435] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10425 04:41:30.471695 <6>[ 0.102727] Detected PIPT I-cache on CPU5
10426 04:41:30.478916 <6>[ 0.102791] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10427 04:41:30.485686 <6>[ 0.102807] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10428 04:41:30.488717 <6>[ 0.103094] Detected PIPT I-cache on CPU6
10429 04:41:30.495023 <6>[ 0.103159] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10430 04:41:30.502069 <6>[ 0.103176] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10431 04:41:30.508137 <6>[ 0.103472] Detected PIPT I-cache on CPU7
10432 04:41:30.514905 <6>[ 0.103538] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10433 04:41:30.521734 <6>[ 0.103554] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10434 04:41:30.525428 <6>[ 0.103601] smp: Brought up 1 node, 8 CPUs
10435 04:41:30.531474 <6>[ 0.245016] SMP: Total of 8 processors activated.
10436 04:41:30.535289 <6>[ 0.249937] CPU features: detected: 32-bit EL0 Support
10437 04:41:30.545181 <6>[ 0.255300] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10438 04:41:30.551576 <6>[ 0.264100] CPU features: detected: Common not Private translations
10439 04:41:30.554992 <6>[ 0.270615] CPU features: detected: CRC32 instructions
10440 04:41:30.561966 <6>[ 0.276000] CPU features: detected: RCpc load-acquire (LDAPR)
10441 04:41:30.568356 <6>[ 0.281960] CPU features: detected: LSE atomic instructions
10442 04:41:30.574652 <6>[ 0.287741] CPU features: detected: Privileged Access Never
10443 04:41:30.578316 <6>[ 0.293521] CPU features: detected: RAS Extension Support
10444 04:41:30.587939 <6>[ 0.299130] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10445 04:41:30.591147 <6>[ 0.306353] CPU: All CPU(s) started at EL2
10446 04:41:30.597699 <6>[ 0.310670] alternatives: applying system-wide alternatives
10447 04:41:30.606197 <6>[ 0.321366] devtmpfs: initialized
10448 04:41:30.618804 <6>[ 0.330241] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10449 04:41:30.628463 <6>[ 0.340204] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10450 04:41:30.634813 <6>[ 0.348216] pinctrl core: initialized pinctrl subsystem
10451 04:41:30.638567 <6>[ 0.355085] DMI not present or invalid.
10452 04:41:30.645386 <6>[ 0.359494] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10453 04:41:30.654842 <6>[ 0.366361] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10454 04:41:30.661832 <6>[ 0.373950] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10455 04:41:30.671910 <6>[ 0.382163] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10456 04:41:30.674951 <6>[ 0.390405] audit: initializing netlink subsys (disabled)
10457 04:41:30.684843 <5>[ 0.396088] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10458 04:41:30.691349 <6>[ 0.396834] thermal_sys: Registered thermal governor 'step_wise'
10459 04:41:30.697706 <6>[ 0.404055] thermal_sys: Registered thermal governor 'power_allocator'
10460 04:41:30.701645 <6>[ 0.410312] cpuidle: using governor menu
10461 04:41:30.708143 <6>[ 0.421277] NET: Registered PF_QIPCRTR protocol family
10462 04:41:30.714514 <6>[ 0.426756] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10463 04:41:30.721356 <6>[ 0.433861] ASID allocator initialised with 32768 entries
10464 04:41:30.724577 <6>[ 0.440522] Serial: AMBA PL011 UART driver
10465 04:41:30.734611 <4>[ 0.449607] Trying to register duplicate clock ID: 134
10466 04:41:30.791395 <6>[ 0.509811] KASLR enabled
10467 04:41:30.806129 <6>[ 0.517584] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10468 04:41:30.812322 <6>[ 0.524599] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10469 04:41:30.819394 <6>[ 0.531087] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10470 04:41:30.825597 <6>[ 0.538090] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10471 04:41:30.832621 <6>[ 0.544575] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10472 04:41:30.839031 <6>[ 0.551576] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10473 04:41:30.846088 <6>[ 0.558060] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10474 04:41:30.852825 <6>[ 0.565061] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10475 04:41:30.855647 <6>[ 0.572583] ACPI: Interpreter disabled.
10476 04:41:30.864511 <6>[ 0.579078] iommu: Default domain type: Translated
10477 04:41:30.871059 <6>[ 0.584192] iommu: DMA domain TLB invalidation policy: strict mode
10478 04:41:30.874058 <5>[ 0.590850] SCSI subsystem initialized
10479 04:41:30.880659 <6>[ 0.595030] usbcore: registered new interface driver usbfs
10480 04:41:30.887211 <6>[ 0.600764] usbcore: registered new interface driver hub
10481 04:41:30.890693 <6>[ 0.606318] usbcore: registered new device driver usb
10482 04:41:30.897347 <6>[ 0.612465] pps_core: LinuxPPS API ver. 1 registered
10483 04:41:30.907456 <6>[ 0.617661] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10484 04:41:30.910661 <6>[ 0.627007] PTP clock support registered
10485 04:41:30.914504 <6>[ 0.631251] EDAC MC: Ver: 3.0.0
10486 04:41:30.921441 <6>[ 0.636440] FPGA manager framework
10487 04:41:30.927847 <6>[ 0.640121] Advanced Linux Sound Architecture Driver Initialized.
10488 04:41:30.931539 <6>[ 0.646906] vgaarb: loaded
10489 04:41:30.937793 <6>[ 0.650084] clocksource: Switched to clocksource arch_sys_counter
10490 04:41:30.941730 <5>[ 0.656529] VFS: Disk quotas dquot_6.6.0
10491 04:41:30.948229 <6>[ 0.660713] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10492 04:41:30.951233 <6>[ 0.667903] pnp: PnP ACPI: disabled
10493 04:41:30.959495 <6>[ 0.674631] NET: Registered PF_INET protocol family
10494 04:41:30.969623 <6>[ 0.680242] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10495 04:41:30.980990 <6>[ 0.692554] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10496 04:41:30.990895 <6>[ 0.701369] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10497 04:41:30.997521 <6>[ 0.709338] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10498 04:41:31.004110 <6>[ 0.718034] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10499 04:41:31.016190 <6>[ 0.727778] TCP: Hash tables configured (established 65536 bind 65536)
10500 04:41:31.023041 <6>[ 0.734640] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10501 04:41:31.029738 <6>[ 0.741838] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10502 04:41:31.036027 <6>[ 0.749544] NET: Registered PF_UNIX/PF_LOCAL protocol family
10503 04:41:31.043045 <6>[ 0.755715] RPC: Registered named UNIX socket transport module.
10504 04:41:31.046162 <6>[ 0.761870] RPC: Registered udp transport module.
10505 04:41:31.052534 <6>[ 0.766805] RPC: Registered tcp transport module.
10506 04:41:31.059430 <6>[ 0.771734] RPC: Registered tcp NFSv4.1 backchannel transport module.
10507 04:41:31.062670 <6>[ 0.778403] PCI: CLS 0 bytes, default 64
10508 04:41:31.065773 <6>[ 0.782796] Unpacking initramfs...
10509 04:41:31.090467 <6>[ 0.802195] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10510 04:41:31.100630 <6>[ 0.810859] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10511 04:41:31.103698 <6>[ 0.819736] kvm [1]: IPA Size Limit: 40 bits
10512 04:41:31.110354 <6>[ 0.824263] kvm [1]: GICv3: no GICV resource entry
10513 04:41:31.113637 <6>[ 0.829280] kvm [1]: disabling GICv2 emulation
10514 04:41:31.120516 <6>[ 0.833974] kvm [1]: GIC system register CPU interface enabled
10515 04:41:31.123439 <6>[ 0.840134] kvm [1]: vgic interrupt IRQ18
10516 04:41:31.130493 <6>[ 0.844502] kvm [1]: VHE mode initialized successfully
10517 04:41:31.137331 <5>[ 0.850932] Initialise system trusted keyrings
10518 04:41:31.143662 <6>[ 0.855734] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10519 04:41:31.151060 <6>[ 0.865692] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10520 04:41:31.157532 <5>[ 0.872093] NFS: Registering the id_resolver key type
10521 04:41:31.161010 <5>[ 0.877396] Key type id_resolver registered
10522 04:41:31.167408 <5>[ 0.881812] Key type id_legacy registered
10523 04:41:31.174086 <6>[ 0.886101] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10524 04:41:31.180413 <6>[ 0.893025] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10525 04:41:31.186993 <6>[ 0.900724] 9p: Installing v9fs 9p2000 file system support
10526 04:41:31.223637 <5>[ 0.938847] Key type asymmetric registered
10527 04:41:31.227480 <5>[ 0.943194] Asymmetric key parser 'x509' registered
10528 04:41:31.237289 <6>[ 0.948341] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10529 04:41:31.240376 <6>[ 0.955961] io scheduler mq-deadline registered
10530 04:41:31.243677 <6>[ 0.960723] io scheduler kyber registered
10531 04:41:31.263171 <6>[ 0.978205] EINJ: ACPI disabled.
10532 04:41:31.296347 <4>[ 1.004502] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10533 04:41:31.306022 <4>[ 1.015126] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10534 04:41:31.321374 <6>[ 1.036266] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10535 04:41:31.329264 <6>[ 1.044382] printk: console [ttyS0] disabled
10536 04:41:31.357152 <6>[ 1.069045] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10537 04:41:31.364095 <6>[ 1.078514] printk: console [ttyS0] enabled
10538 04:41:31.367222 <6>[ 1.078514] printk: console [ttyS0] enabled
10539 04:41:31.374014 <6>[ 1.087410] printk: bootconsole [mtk8250] disabled
10540 04:41:31.377164 <6>[ 1.087410] printk: bootconsole [mtk8250] disabled
10541 04:41:31.384038 <6>[ 1.098867] SuperH (H)SCI(F) driver initialized
10542 04:41:31.387078 <6>[ 1.104190] msm_serial: driver initialized
10543 04:41:31.401667 <6>[ 1.113332] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10544 04:41:31.411546 <6>[ 1.121879] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10545 04:41:31.418593 <6>[ 1.130427] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10546 04:41:31.428076 <6>[ 1.139056] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10547 04:41:31.437868 <6>[ 1.147763] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10548 04:41:31.444688 <6>[ 1.156488] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10549 04:41:31.454484 <6>[ 1.165029] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10550 04:41:31.461326 <6>[ 1.173843] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10551 04:41:31.471256 <6>[ 1.182388] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10552 04:41:31.483512 <6>[ 1.198383] loop: module loaded
10553 04:41:31.490120 <6>[ 1.204347] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10554 04:41:31.513173 <4>[ 1.227985] mtk-pmic-keys: Failed to locate of_node [id: -1]
10555 04:41:31.519437 <6>[ 1.234724] megasas: 07.719.03.00-rc1
10556 04:41:31.529261 <6>[ 1.244528] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10557 04:41:31.538538 <6>[ 1.253463] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10558 04:41:31.555156 <6>[ 1.270184] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10559 04:41:31.612502 <6>[ 1.320600] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10560 04:41:32.655044 <6>[ 2.369696] Freeing initrd memory: 38304K
10561 04:41:32.665324 <6>[ 2.380107] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10562 04:41:32.676120 <6>[ 2.391270] tun: Universal TUN/TAP device driver, 1.6
10563 04:41:32.679841 <6>[ 2.397384] thunder_xcv, ver 1.0
10564 04:41:32.682996 <6>[ 2.400890] thunder_bgx, ver 1.0
10565 04:41:32.686450 <6>[ 2.404386] nicpf, ver 1.0
10566 04:41:32.696843 <6>[ 2.408459] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10567 04:41:32.700390 <6>[ 2.415934] hns3: Copyright (c) 2017 Huawei Corporation.
10568 04:41:32.706753 <6>[ 2.421523] hclge is initializing
10569 04:41:32.710261 <6>[ 2.425104] e1000: Intel(R) PRO/1000 Network Driver
10570 04:41:32.716874 <6>[ 2.430234] e1000: Copyright (c) 1999-2006 Intel Corporation.
10571 04:41:32.720455 <6>[ 2.436246] e1000e: Intel(R) PRO/1000 Network Driver
10572 04:41:32.726562 <6>[ 2.441462] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10573 04:41:32.733425 <6>[ 2.447649] igb: Intel(R) Gigabit Ethernet Network Driver
10574 04:41:32.740340 <6>[ 2.453299] igb: Copyright (c) 2007-2014 Intel Corporation.
10575 04:41:32.746430 <6>[ 2.459136] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10576 04:41:32.753269 <6>[ 2.465653] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10577 04:41:32.756296 <6>[ 2.472125] sky2: driver version 1.30
10578 04:41:32.763001 <6>[ 2.477174] VFIO - User Level meta-driver version: 0.3
10579 04:41:32.770569 <6>[ 2.485528] usbcore: registered new interface driver usb-storage
10580 04:41:32.777230 <6>[ 2.491984] usbcore: registered new device driver onboard-usb-hub
10581 04:41:32.786110 <6>[ 2.501170] mt6397-rtc mt6359-rtc: registered as rtc0
10582 04:41:32.796097 <6>[ 2.506637] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-09T04:40:57 UTC (1691556057)
10583 04:41:32.799325 <6>[ 2.516247] i2c_dev: i2c /dev entries driver
10584 04:41:32.816332 <6>[ 2.528223] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10585 04:41:32.836452 <6>[ 2.551238] cpu cpu0: EM: created perf domain
10586 04:41:32.839605 <6>[ 2.556242] cpu cpu4: EM: created perf domain
10587 04:41:32.847099 <6>[ 2.561853] sdhci: Secure Digital Host Controller Interface driver
10588 04:41:32.853224 <6>[ 2.568285] sdhci: Copyright(c) Pierre Ossman
10589 04:41:32.859809 <6>[ 2.573248] Synopsys Designware Multimedia Card Interface Driver
10590 04:41:32.866548 <6>[ 2.579892] sdhci-pltfm: SDHCI platform and OF driver helper
10591 04:41:32.869764 <6>[ 2.579930] mmc0: CQHCI version 5.10
10592 04:41:32.876587 <6>[ 2.589869] ledtrig-cpu: registered to indicate activity on CPUs
10593 04:41:32.883570 <6>[ 2.596853] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10594 04:41:32.890251 <6>[ 2.603917] usbcore: registered new interface driver usbhid
10595 04:41:32.893446 <6>[ 2.609740] usbhid: USB HID core driver
10596 04:41:32.900408 <6>[ 2.613934] spi_master spi0: will run message pump with realtime priority
10597 04:41:32.943236 <6>[ 2.651792] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10598 04:41:32.960099 <6>[ 2.668006] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10599 04:41:32.966910 <6>[ 2.681549] mmc0: Command Queue Engine enabled
10600 04:41:32.973642 <6>[ 2.686321] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10601 04:41:32.980265 <6>[ 2.693593] mmcblk0: mmc0:0001 DA4128 116 GiB
10602 04:41:32.983489 <6>[ 2.698541] cros-ec-spi spi0.0: Chrome EC device registered
10603 04:41:32.990053 <6>[ 2.702196] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10604 04:41:32.997230 <6>[ 2.711915] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10605 04:41:33.004118 <6>[ 2.718065] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10606 04:41:33.010603 <6>[ 2.724031] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10607 04:41:33.028988 <6>[ 2.740762] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10608 04:41:33.036398 <6>[ 2.751359] NET: Registered PF_PACKET protocol family
10609 04:41:33.040078 <6>[ 2.756759] 9pnet: Installing 9P2000 support
10610 04:41:33.046585 <5>[ 2.761321] Key type dns_resolver registered
10611 04:41:33.049830 <6>[ 2.766309] registered taskstats version 1
10612 04:41:33.056509 <5>[ 2.770693] Loading compiled-in X.509 certificates
10613 04:41:33.086458 <4>[ 2.794744] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10614 04:41:33.097053 <4>[ 2.805488] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10615 04:41:33.103020 <3>[ 2.816027] debugfs: File 'uA_load' in directory '/' already present!
10616 04:41:33.109899 <3>[ 2.822728] debugfs: File 'min_uV' in directory '/' already present!
10617 04:41:33.116107 <3>[ 2.829334] debugfs: File 'max_uV' in directory '/' already present!
10618 04:41:33.122475 <3>[ 2.835941] debugfs: File 'constraint_flags' in directory '/' already present!
10619 04:41:33.133756 <3>[ 2.845675] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10620 04:41:33.143136 <6>[ 2.858225] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10621 04:41:33.149828 <6>[ 2.864996] xhci-mtk 11200000.usb: xHCI Host Controller
10622 04:41:33.156647 <6>[ 2.870500] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10623 04:41:33.166843 <6>[ 2.878337] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10624 04:41:33.173477 <6>[ 2.887756] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10625 04:41:33.180177 <6>[ 2.893840] xhci-mtk 11200000.usb: xHCI Host Controller
10626 04:41:33.186737 <6>[ 2.899318] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10627 04:41:33.193594 <6>[ 2.906963] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10628 04:41:33.200042 <6>[ 2.914779] hub 1-0:1.0: USB hub found
10629 04:41:33.203667 <6>[ 2.918802] hub 1-0:1.0: 1 port detected
10630 04:41:33.209829 <6>[ 2.923080] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10631 04:41:33.216900 <6>[ 2.931829] hub 2-0:1.0: USB hub found
10632 04:41:33.219892 <6>[ 2.935854] hub 2-0:1.0: 1 port detected
10633 04:41:33.228369 <6>[ 2.943828] mtk-msdc 11f70000.mmc: Got CD GPIO
10634 04:41:33.239458 <6>[ 2.951332] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10635 04:41:33.246329 <6>[ 2.959353] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10636 04:41:33.256000 <4>[ 2.967249] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10637 04:41:33.265931 <6>[ 2.976769] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10638 04:41:33.272881 <6>[ 2.984846] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10639 04:41:33.279401 <6>[ 2.992866] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10640 04:41:33.288889 <6>[ 3.000784] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10641 04:41:33.295788 <6>[ 3.008600] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10642 04:41:33.305778 <6>[ 3.016418] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10643 04:41:33.315621 <6>[ 3.026862] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10644 04:41:33.322565 <6>[ 3.035243] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10645 04:41:33.332189 <6>[ 3.043588] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10646 04:41:33.339023 <6>[ 3.051926] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10647 04:41:33.348753 <6>[ 3.060263] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10648 04:41:33.355726 <6>[ 3.068602] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10649 04:41:33.365847 <6>[ 3.076939] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10650 04:41:33.372050 <6>[ 3.085277] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10651 04:41:33.382346 <6>[ 3.093615] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10652 04:41:33.388840 <6>[ 3.101952] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10653 04:41:33.398652 <6>[ 3.110289] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10654 04:41:33.408530 <6>[ 3.118627] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10655 04:41:33.415581 <6>[ 3.126967] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10656 04:41:33.425416 <6>[ 3.135306] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10657 04:41:33.431485 <6>[ 3.143645] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10658 04:41:33.438674 <6>[ 3.152399] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10659 04:41:33.445210 <6>[ 3.159576] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10660 04:41:33.451768 <6>[ 3.166352] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10661 04:41:33.458456 <6>[ 3.173124] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10662 04:41:33.468859 <6>[ 3.180066] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10663 04:41:33.474856 <6>[ 3.186911] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10664 04:41:33.484956 <6>[ 3.196042] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10665 04:41:33.494777 <6>[ 3.205162] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10666 04:41:33.505069 <6>[ 3.214457] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10667 04:41:33.515166 <6>[ 3.223944] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10668 04:41:33.521873 <6>[ 3.233413] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10669 04:41:33.531284 <6>[ 3.242534] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10670 04:41:33.541669 <6>[ 3.252001] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10671 04:41:33.551273 <6>[ 3.261121] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10672 04:41:33.561739 <6>[ 3.270414] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10673 04:41:33.571128 <6>[ 3.280575] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10674 04:41:33.581676 <6>[ 3.292490] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10675 04:41:33.634824 <6>[ 3.346358] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10676 04:41:33.789290 <6>[ 3.504288] hub 1-1:1.0: USB hub found
10677 04:41:33.792112 <6>[ 3.508828] hub 1-1:1.0: 4 ports detected
10678 04:41:33.914552 <6>[ 3.626696] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10679 04:41:33.941305 <6>[ 3.656286] hub 2-1:1.0: USB hub found
10680 04:41:33.944815 <6>[ 3.660815] hub 2-1:1.0: 3 ports detected
10681 04:41:34.114630 <6>[ 3.826357] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10682 04:41:34.246754 <6>[ 3.961547] hub 1-1.4:1.0: USB hub found
10683 04:41:34.249798 <6>[ 3.966086] hub 1-1.4:1.0: 2 ports detected
10684 04:41:34.326773 <6>[ 4.038611] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10685 04:41:34.546846 <6>[ 4.258358] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10686 04:41:34.734450 <6>[ 4.446387] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10687 04:41:45.879965 <6>[ 15.599365] ALSA device list:
10688 04:41:45.886330 <6>[ 15.602657] No soundcards found.
10689 04:41:45.894235 <6>[ 15.610668] Freeing unused kernel memory: 8384K
10690 04:41:45.898022 <6>[ 15.615668] Run /init as init process
10691 04:41:45.945472 <6>[ 15.661951] NET: Registered PF_INET6 protocol family
10692 04:41:45.952174 <6>[ 15.668176] Segment Routing with IPv6
10693 04:41:45.955432 <6>[ 15.672128] In-situ OAM (IOAM) with IPv6
10694 04:41:45.990587 <30>[ 15.686794] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10695 04:41:45.993596 <30>[ 15.710688] systemd[1]: Detected architecture arm64.
10696 04:41:45.994031
10697 04:41:46.000256 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10698 04:41:46.000911
10699 04:41:46.013957 <30>[ 15.730404] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10700 04:41:46.176800 <30>[ 15.889849] systemd[1]: Queued start job for default target Graphical Interface.
10701 04:41:46.206581 <30>[ 15.922962] systemd[1]: Created slice system-getty.slice.
10702 04:41:46.213234 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10703 04:41:46.230279 <30>[ 15.946759] systemd[1]: Created slice system-modprobe.slice.
10704 04:41:46.237252 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10705 04:41:46.254646 <30>[ 15.970935] systemd[1]: Created slice system-serial\x2dgetty.slice.
10706 04:41:46.264837 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10707 04:41:46.278684 <30>[ 15.994873] systemd[1]: Created slice User and Session Slice.
10708 04:41:46.284573 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10709 04:41:46.305335 <30>[ 16.018429] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10710 04:41:46.315008 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10711 04:41:46.328971 <30>[ 16.042380] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10712 04:41:46.335926 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10713 04:41:46.356375 <30>[ 16.066331] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10714 04:41:46.363053 <30>[ 16.078416] systemd[1]: Reached target Local Encrypted Volumes.
10715 04:41:46.370218 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10716 04:41:46.386594 <30>[ 16.102837] systemd[1]: Reached target Paths.
10717 04:41:46.389978 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10718 04:41:46.406405 <30>[ 16.122322] systemd[1]: Reached target Remote File Systems.
10719 04:41:46.412946 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10720 04:41:46.426111 <30>[ 16.142301] systemd[1]: Reached target Slices.
10721 04:41:46.429286 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10722 04:41:46.446297 <30>[ 16.162344] systemd[1]: Reached target Swap.
10723 04:41:46.449556 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10724 04:41:46.470164 <30>[ 16.182794] systemd[1]: Listening on initctl Compatibility Named Pipe.
10725 04:41:46.476399 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10726 04:41:46.491003 <30>[ 16.207747] systemd[1]: Listening on Journal Audit Socket.
10727 04:41:46.497450 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10728 04:41:46.514415 <30>[ 16.231438] systemd[1]: Listening on Journal Socket (/dev/log).
10729 04:41:46.521030 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10730 04:41:46.537817 <30>[ 16.254813] systemd[1]: Listening on Journal Socket.
10731 04:41:46.544870 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10732 04:41:46.558004 <30>[ 16.274973] systemd[1]: Listening on Network Service Netlink Socket.
10733 04:41:46.568089 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10734 04:41:46.582777 <30>[ 16.299556] systemd[1]: Listening on udev Control Socket.
10735 04:41:46.589677 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10736 04:41:46.606420 <30>[ 16.323378] systemd[1]: Listening on udev Kernel Socket.
10737 04:41:46.613435 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10738 04:41:46.653737 <30>[ 16.370567] systemd[1]: Mounting Huge Pages File System...
10739 04:41:46.660474 Mounting [0;1;39mHuge Pages File System[0m...
10740 04:41:46.677099 <30>[ 16.393698] systemd[1]: Mounting POSIX Message Queue File System...
10741 04:41:46.683885 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10742 04:41:46.721642 <30>[ 16.438581] systemd[1]: Mounting Kernel Debug File System...
10743 04:41:46.728386 Mounting [0;1;39mKernel Debug File System[0m...
10744 04:41:46.745450 <30>[ 16.458613] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10745 04:41:46.757007 <30>[ 16.470548] systemd[1]: Starting Create list of static device nodes for the current kernel...
10746 04:41:46.763793 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10747 04:41:46.818064 <30>[ 16.535036] systemd[1]: Starting Load Kernel Module configfs...
10748 04:41:46.824609 Starting [0;1;39mLoad Kernel Module configfs[0m...
10749 04:41:46.841871 <30>[ 16.558859] systemd[1]: Starting Load Kernel Module drm...
10750 04:41:46.848394 Starting [0;1;39mLoad Kernel Module drm[0m...
10751 04:41:46.864995 <30>[ 16.578750] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10752 04:41:46.910504 <30>[ 16.627268] systemd[1]: Starting Journal Service...
10753 04:41:46.913761 Starting [0;1;39mJournal Service[0m...
10754 04:41:46.934149 <30>[ 16.651108] systemd[1]: Starting Load Kernel Modules...
10755 04:41:46.941247 Starting [0;1;39mLoad Kernel Modules[0m...
10756 04:41:46.961345 <30>[ 16.674917] systemd[1]: Starting Remount Root and Kernel File Systems...
10757 04:41:46.967805 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10758 04:41:47.006361 <30>[ 16.722921] systemd[1]: Starting Coldplug All udev Devices...
10759 04:41:47.012991 Starting [0;1;39mColdplug All udev Devices[0m...
10760 04:41:47.028992 <30>[ 16.745501] systemd[1]: Started Journal Service.
10761 04:41:47.035677 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10762 04:41:47.051614 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10763 04:41:47.066684 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10764 04:41:47.082341 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10765 04:41:47.102215 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10766 04:41:47.120098 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10767 04:41:47.135826 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10768 04:41:47.151606 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10769 04:41:47.172215 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10770 04:41:47.185591 See 'systemctl status systemd-remount-fs.service' for details.
10771 04:41:47.238903 Mounting [0;1;39mKernel Configuration File System[0m...
10772 04:41:47.258660 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10773 04:41:47.272179 <46>[ 16.985151] systemd-journald[189]: Received client request to flush runtime journal.
10774 04:41:47.283316 Starting [0;1;39mLoad/Save Random Seed[0m...
10775 04:41:47.303148 Starting [0;1;39mApply Kernel Variables[0m...
10776 04:41:47.323828 Starting [0;1;39mCreate System Users[0m...
10777 04:41:47.343913 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10778 04:41:47.358900 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10779 04:41:47.378793 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10780 04:41:47.391633 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10781 04:41:47.407969 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10782 04:41:47.423797 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10783 04:41:47.474848 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10784 04:41:47.502436 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10785 04:41:47.515026 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10786 04:41:47.530124 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10787 04:41:47.566152 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10788 04:41:47.591449 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10789 04:41:47.611476 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10790 04:41:47.631473 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10791 04:41:47.679297 Starting [0;1;39mNetwork Service[0m...
10792 04:41:47.709218 Starting [0;1;39mNetwork Time Synchronization[0m...
10793 04:41:47.732100 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10794 04:41:47.752798 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10795 04:41:47.786274 <6>[ 17.499293] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10796 04:41:47.799861 [[0;32m OK [<6>[ 17.513099] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10797 04:41:47.806325 0m] Found device<6>[ 17.513704] remoteproc remoteproc0: scp is available
10798 04:41:47.816698 <6>[ 17.522228] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10799 04:41:47.826194 [0;1;39m/dev/t<3>[ 17.529191] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10800 04:41:47.826656 tyS0[0m.
10801 04:41:47.829618 <6>[ 17.529259] remoteproc remoteproc0: powering up scp
10802 04:41:47.839879 <6>[ 17.529265] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10803 04:41:47.846165 <6>[ 17.529288] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10804 04:41:47.852862 <6>[ 17.537673] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10805 04:41:47.862773 <3>[ 17.546952] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10806 04:41:47.866645 <6>[ 17.553200] mc: Linux media interface: v0.10
10807 04:41:47.875825 <3>[ 17.561430] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10808 04:41:47.878973 <6>[ 17.584357] videodev: Linux video capture interface: v2.00
10809 04:41:47.885431 <6>[ 17.586303] usbcore: registered new interface driver r8152
10810 04:41:47.895469 <3>[ 17.593705] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10811 04:41:47.905590 [[0;32m OK [<3>[ 17.616494] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10812 04:41:47.912009 0m] Started [0;<6>[ 17.618652] usbcore: registered new interface driver cdc_ether
10813 04:41:47.922460 1;39mNetwork Tim<3>[ 17.625945] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10814 04:41:47.931906 e Synchronizatio<3>[ 17.625962] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10815 04:41:47.932005 n[0m.
10816 04:41:47.938637 <3>[ 17.625974] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10817 04:41:47.942176 <6>[ 17.635061] Bluetooth: Core ver 2.22
10818 04:41:47.951809 <3>[ 17.654690] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10819 04:41:47.958419 <6>[ 17.654773] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10820 04:41:47.968249 <6>[ 17.654913] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10821 04:41:47.971908 <6>[ 17.654920] remoteproc remoteproc0: remote processor scp is now up
10822 04:41:47.978755 <6>[ 17.662488] NET: Registered PF_BLUETOOTH protocol family
10823 04:41:47.985370 <6>[ 17.662644] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10824 04:41:47.995395 <4>[ 17.684344] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10825 04:41:47.999048 <4>[ 17.684344] Fallback method does not support PEC.
10826 04:41:48.005722 <6>[ 17.688665] Bluetooth: HCI device and connection manager initialized
10827 04:41:48.012677 <6>[ 17.688703] Bluetooth: HCI socket layer initialized
10828 04:41:48.019477 <6>[ 17.695487] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10829 04:41:48.025749 <3>[ 17.695506] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10830 04:41:48.035430 <3>[ 17.695530] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10831 04:41:48.042330 <3>[ 17.695538] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10832 04:41:48.049901 <3>[ 17.695638] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10833 04:41:48.059885 <3>[ 17.695647] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10834 04:41:48.066770 <3>[ 17.695655] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10835 04:41:48.077669 <3>[ 17.695669] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10836 04:41:48.084281 <3>[ 17.695677] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10837 04:41:48.091090 <3>[ 17.695765] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10838 04:41:48.098324 <6>[ 17.700730] Bluetooth: L2CAP socket layer initialized
10839 04:41:48.101748 <6>[ 17.708514] pci_bus 0000:00: root bus resource [bus 00-ff]
10840 04:41:48.108612 <6>[ 17.710900] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10841 04:41:48.118238 <3>[ 17.714186] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10842 04:41:48.125161 <6>[ 17.722042] Bluetooth: SCO socket layer initialized
10843 04:41:48.131504 <6>[ 17.725463] usbcore: registered new interface driver r8153_ecm
10844 04:41:48.139241 <6>[ 17.728631] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10845 04:41:48.145413 <4>[ 17.736273] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10846 04:41:48.151789 <4>[ 17.738778] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10847 04:41:48.161667 <4>[ 17.738792] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10848 04:41:48.172552 <6>[ 17.740712] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10849 04:41:48.179651 <4>[ 17.748854] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10850 04:41:48.185766 <6>[ 17.756833] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10851 04:41:48.192529 <3>[ 17.771793] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10852 04:41:48.202558 <3>[ 17.772630] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10853 04:41:48.209223 <6>[ 17.772968] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10854 04:41:48.212239 <6>[ 17.795821] r8152 2-1.3:1.0 eth0: v1.12.13
10855 04:41:48.219000 <6>[ 17.797278] pci 0000:00:00.0: supports D1 D2
10856 04:41:48.225625 <3>[ 17.802869] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10857 04:41:48.235599 <6>[ 17.813848] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10858 04:41:48.246532 <6>[ 17.814405] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10859 04:41:48.253892 <6>[ 17.816428] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10860 04:41:48.261278 <6>[ 17.818665] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10861 04:41:48.267865 <6>[ 17.819639] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10862 04:41:48.278214 <3>[ 17.824457] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10863 04:41:48.284777 <6>[ 17.824697] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10864 04:41:48.291559 <6>[ 17.831650] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10865 04:41:48.301413 <3>[ 17.862366] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10866 04:41:48.308100 <6>[ 17.865975] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10867 04:41:48.318923 <6>[ 17.879711] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10868 04:41:48.325677 <6>[ 17.883070] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10869 04:41:48.335700 <3>[ 17.896946] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10870 04:41:48.342486 <6>[ 17.900281] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10871 04:41:48.345677 <6>[ 17.900408] pci 0000:01:00.0: supports D1 D2
10872 04:41:48.352434 <6>[ 17.908940] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10873 04:41:48.358726 <6>[ 17.915361] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10874 04:41:48.365573 <6>[ 17.930226] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10875 04:41:48.372531 <6>[ 17.932197] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10876 04:41:48.386865 <6>[ 17.932624] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10877 04:41:48.393625 <6>[ 17.932755] usbcore: registered new interface driver uvcvideo
10878 04:41:48.399810 <6>[ 17.935119] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10879 04:41:48.407728 <6>[ 17.935132] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10880 04:41:48.417964 <6>[ 17.935154] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10881 04:41:48.420892 <6>[ 17.938420] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10882 04:41:48.427403 <6>[ 17.959168] usbcore: registered new interface driver btusb
10883 04:41:48.437962 <4>[ 17.959938] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10884 04:41:48.444632 <3>[ 17.959945] Bluetooth: hci0: Failed to load firmware file (-2)
10885 04:41:48.450724 <3>[ 17.959948] Bluetooth: hci0: Failed to set up firmware (-2)
10886 04:41:48.460902 <4>[ 17.959950] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10887 04:41:48.467548 <6>[ 17.966771] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10888 04:41:48.477550 <3>[ 17.978358] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10889 04:41:48.483727 <6>[ 17.981886] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10890 04:41:48.494044 <3>[ 18.000852] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 04:41:48.500441 <6>[ 18.007936] pci 0000:00:00.0: PCI bridge to [bus 01]
10892 04:41:48.507112 <6>[ 18.007941] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10893 04:41:48.516868 <3>[ 18.048291] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 04:41:48.523315 <6>[ 18.056103] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10895 04:41:48.530266 [[0;32m OK [<6>[ 18.244807] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10896 04:41:48.536342 0m] Created slic<6>[ 18.252536] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10897 04:41:48.543010 e [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10898 04:41:48.564683 [[0;32m OK [0m] Reached target [0;1;39mSyst<5>[ 18.278032] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10899 04:41:48.568200 em Time Set[0m.
10900 04:41:48.585250 [[0;32m OK [<5>[ 18.299199] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10901 04:41:48.598467 0m] Reached target [0;1;39mSystem Time Synchron<4>[ 18.310633] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10902 04:41:48.598554 ized[0m.
10903 04:41:48.605157 <6>[ 18.320513] cfg80211: failed to load regulatory.db
10904 04:41:48.646867 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10905 04:41:48.657769 <6>[ 18.371230] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10906 04:41:48.664312 <6>[ 18.378772] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10907 04:41:48.673309 Starting [0;1;39mNetwork Name Resolution[0m...
10908 04:41:48.688636 <6>[ 18.405547] mt7921e 0000:01:00.0: ASIC revision: 79610010
10909 04:41:48.701327 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10910 04:41:48.723704 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10911 04:41:48.742921 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10912 04:41:48.796109 <4>[ 18.506542] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10913 04:41:48.879879 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10914 04:41:48.894006 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10915 04:41:48.916777 <4>[ 18.626851] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10916 04:41:48.923241 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10917 04:41:48.937950 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10918 04:41:48.957757 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10919 04:41:48.977114 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10920 04:41:48.989728 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10921 04:41:49.009523 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10922 04:41:49.023090 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10923 04:41:49.036973 <4>[ 18.746804] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10924 04:41:49.043265 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10925 04:41:49.066099 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10926 04:41:49.110905 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10927 04:41:49.148123 Starting [0;1;39mUser Login Management[0m...
10928 04:41:49.158006 <4>[ 18.868957] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10929 04:41:49.173305 Starting [0;1;39mPermit User Sessions[0m...
10930 04:41:49.191997 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10931 04:41:49.242722 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10932 04:41:49.269068 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10933 04:41:49.285712 <4>[ 18.995608] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10934 04:41:49.292703 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10935 04:41:49.312966 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10936 04:41:49.331378 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10937 04:41:49.347806 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10938 04:41:49.364280 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10939 04:41:49.382869 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10940 04:41:49.408895 <4>[ 19.118574] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10941 04:41:49.430862 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10942 04:41:49.456170 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10943 04:41:49.473072
10944 04:41:49.473651
10945 04:41:49.476795 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10946 04:41:49.477383
10947 04:41:49.479828 debian-bullseye-arm64 login: root (automatic login)
10948 04:41:49.480247
10949 04:41:49.480567
10950 04:41:49.494244 Linux debian-bullseye-arm64 6.1.42-cip2 #1 SMP PREEMPT Wed Aug 9 04:18:34 UTC 2023 aarch64
10951 04:41:49.494848
10952 04:41:49.500826 The programs included with the Debian GNU/Linux system are free software;
10953 04:41:49.507496 the exact distribution terms for each program are described in the
10954 04:41:49.510962 individual files in /usr/share/doc/*/copyright.
10955 04:41:49.511509
10956 04:41:49.527264 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the exte<4>[ 19.237313] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10957 04:41:49.527962 nt
10958 04:41:49.530691 permitted by applicable law.
10959 04:41:49.532794 Matched prompt #10: / #
10961 04:41:49.534564 Setting prompt string to ['/ #']
10962 04:41:49.535178 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10964 04:41:49.536752 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10965 04:41:49.537466 start: 2.2.6 expect-shell-connection (timeout 00:03:33) [common]
10966 04:41:49.538081 Setting prompt string to ['/ #']
10967 04:41:49.538617 Forcing a shell prompt, looking for ['/ #']
10969 04:41:49.589961 / #
10970 04:41:49.590480 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10971 04:41:49.590930 Waiting using forced prompt support (timeout 00:02:30)
10972 04:41:49.596115
10973 04:41:49.596923 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10974 04:41:49.597587 start: 2.2.7 export-device-env (timeout 00:03:33) [common]
10975 04:41:49.598150 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10976 04:41:49.598666 end: 2.2 depthcharge-retry (duration 00:01:27) [common]
10977 04:41:49.599183 end: 2 depthcharge-action (duration 00:01:27) [common]
10978 04:41:49.599779 start: 3 lava-test-retry (timeout 00:08:13) [common]
10979 04:41:49.600279 start: 3.1 lava-test-shell (timeout 00:08:13) [common]
10980 04:41:49.600723 Using namespace: common
10982 04:41:49.701866 / # #
10983 04:41:49.702461 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10984 04:41:49.703088 <4>[ 19.358744] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10985 04:41:49.707583 #
10986 04:41:49.708339 Using /lava-11241315
10988 04:41:49.809472 / # export SHELL=/bin/sh
10989 04:41:49.810212 <4>[ 19.478925] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10990 04:41:49.855901 export SHELL=/bin/sh<6>[ 19.528535] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
10991 04:41:49.856371
10992 04:41:49.856821 <6>[ 19.536474] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10994 04:41:49.958404 / # . /lava-11241315/environment
10995 04:41:49.959287 <4>[ 19.598867] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10996 04:41:49.964807 . /lava-11241315/environment
10998 04:41:50.066777 / # /lava-11241315/bin/lava-test-runner /lava-11241315/0
10999 04:41:50.067450 Test shell timeout: 10s (minimum of the action and connection timeout)
11000 04:41:50.069071 <3>[ 19.716959] mt7921e 0000:01:00.0: hardware init failed
11001 04:41:50.073607 /lava-11241315/bin/lava-test-runner /lava-11241315/0
11002 04:41:50.115642 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11003 04:41:50.115758 + cd /lava-11241315/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11004 04:41:50.115831 + cat uuid
11005 04:41:50.115895 + UUID=11241315_1.5.2.3.1
11006 04:41:50.115955 + set +x
11007 04:41:50.116016 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 11241315_1.5.2.3.1>
11008 04:41:50.116255 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 11241315_1.5.2.3.1
11009 04:41:50.116334 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (11241315_1.5.2.3.1)
11010 04:41:50.116429 Skipping test definition patterns.
11011 04:41:50.116541 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11012 04:41:50.123461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11013 04:41:50.123764 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11015 04:41:50.133344 device: /dev/video2<4>[ 19.844970] use of bytesused == 0 is deprecated and will be removed in the future,
11016 04:41:50.133430
11017 04:41:50.136803 <4>[ 19.854033] use the actual size instead.
11018 04:41:50.143357 <4>[ 19.859971] ------------[ cut here ]------------
11019 04:41:50.150362 <4>[ 19.864859] get_vaddr_frames() cannot follow VM_IO mapping
11020 04:41:50.160158 <4>[ 19.865010] WARNING: CPU: 2 PID: 317 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11021 04:41:50.209616 <4>[ 19.883121] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 cfg80211 btusb btintel mtk_vcodec_enc btmtk mtk_vcodec_common btrtl uvcvideo mtk_vpu videobuf2_vmalloc v4l2_mem2mem btbcm cros_ec_rpmsg crct10dif_ce elants_i2c videobuf2_dma_contig cros_ec_chardev r8153_ecm elan_i2c videobuf2_memops bluetooth videobuf2_v4l2 cdc_ether ecdh_generic videobuf2_common usbnet ecc hid_google_hammer hid_vivaldi_common videodev sbs_battery rfkill mc r8152 pcie_mediatek_gen3 cros_ec_typec mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11022 04:41:50.216217 <4>[ 19.932504] CPU: 2 PID: 317 Comm: v4l2-compliance Not tainted 6.1.42-cip2 #1
11023 04:41:50.222679 <4>[ 19.939802] Hardware name: Google Spherion (rev0 - 3) (DT)
11024 04:41:50.229415 <4>[ 19.945537] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11025 04:41:50.236048 <4>[ 19.952749] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11026 04:41:50.242879 <4>[ 19.958840] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11027 04:41:50.246379 <4>[ 19.964930] sp : ffff8000091e3850
11028 04:41:50.252954 <4>[ 19.968493] x29: ffff8000091e3850 x28: ffffb6dce50cf000 x27: ffffb6dce50cb238
11029 04:41:50.262888 <4>[ 19.975881] x26: 0000000000000000 x25: ffffb6dd5322c678 x24: ffff34218e7cda98
11030 04:41:50.269593 <4>[ 19.983267] x23: ffff34218099fc00 x22: ffff342180d48410 x21: 0000000000000000
11031 04:41:50.275867 <4>[ 19.990655] x20: 00000000fffffff2 x19: ffff34218b81fa80 x18: fffffffffffe9768
11032 04:41:50.282506 <4>[ 19.998042] x17: 0000000000000000 x16: ffffb6dd5108bb40 x15: 0000000000000038
11033 04:41:50.289558 <4>[ 20.005428] x14: ffffb6dd53b134a8 x13: 000000000000064e x12: 000000000000021a
11034 04:41:50.299249 <4>[ 20.012815] x11: fffffffffffe9768 x10: fffffffffffe9730 x9 : 00000000fffff21a
11035 04:41:50.306185 <4>[ 20.020202] x8 : ffffb6dd53b134a8 x7 : ffffb6dd53b6b4a8 x6 : 0000000000001938
11036 04:41:50.312871 <4>[ 20.027588] x5 : ffff3422bef3fa18 x4 : 00000000fffff21a x3 : ffff7d456baec000
11037 04:41:50.319361 <4>[ 20.034975] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff3421814a49c0
11038 04:41:50.322345 <4>[ 20.042362] Call trace:
11039 04:41:50.329134 <4>[ 20.045058] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11040 04:41:50.335952 <4>[ 20.050802] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11041 04:41:50.342612 <4>[ 20.056804] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11042 04:41:50.345567 <4>[ 20.063155] __prepare_userptr+0x280/0x410 [videobuf2_common]
11043 04:41:50.352359 <4>[ 20.069158] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11044 04:41:50.358878 <4>[ 20.074814] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11045 04:41:50.365869 <4>[ 20.080991] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11046 04:41:50.368995 <4>[ 20.086493] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11047 04:41:50.375931 <4>[ 20.092250] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11048 04:41:50.381989 <4>[ 20.098515] v4l_prepare_buf+0x48/0x60 [videodev]
11049 04:41:50.385650 <4>[ 20.103542] __video_do_ioctl+0x184/0x3d0 [videodev]
11050 04:41:50.392146 <4>[ 20.108787] video_usercopy+0x358/0x680 [videodev]
11051 04:41:50.395287 <4>[ 20.113858] video_ioctl2+0x18/0x30 [videodev]
11052 04:41:50.402461 <4>[ 20.118581] v4l2_ioctl+0x40/0x60 [videodev]
11053 04:41:50.405465 <4>[ 20.123130] __arm64_sys_ioctl+0xa8/0xf0
11054 04:41:50.409103 <4>[ 20.127312] invoke_syscall+0x48/0x114
11055 04:41:50.415322 <4>[ 20.131317] el0_svc_common.constprop.0+0x44/0xec
11056 04:41:50.419053 <4>[ 20.136272] do_el0_svc+0x2c/0xd0
11057 04:41:50.422045 <4>[ 20.139838] el0_svc+0x2c/0x84
11058 04:41:50.425094 <4>[ 20.143145] el0t_64_sync_handler+0xb8/0xc0
11059 04:41:50.428788 <4>[ 20.147579] el0t_64_sync+0x18c/0x190
11060 04:41:50.435307 <4>[ 20.151493] ---[ end trace 0000000000000000 ]---
11061 04:41:50.446327 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11062 04:41:50.455299 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11063 04:41:50.462615
11064 04:41:50.477790 Compliance test for mtk-vcodec-enc device /dev/video2:
11065 04:41:50.490095
11066 04:41:50.499336 Driver Info:
11067 04:41:50.512927 Driver name : mtk-vcodec-enc
11068 04:41:50.527747 Card type : MT8192 video encoder
11069 04:41:50.540365 Bus info : platform:17020000.vcodec
11070 04:41:50.548322 Driver version : 6.1.42
11071 04:41:50.560726 Capabilities : 0x84204000
11072 04:41:50.575336 Video Memory-to-Memory Multiplanar
11073 04:41:50.586275 Streaming
11074 04:41:50.601996 Extended Pix Format
11075 04:41:50.614884 Device Capabilities
11076 04:41:50.628130 Device Caps : 0x04204000
11077 04:41:50.638403 Video Memory-to-Memory Multiplanar
11078 04:41:50.648910 Streaming
11079 04:41:50.661332 Extended Pix Format
11080 04:41:50.672686 Detected Stateful Encoder
11081 04:41:50.681627
11082 04:41:50.692414 Required ioctls:
11083 04:41:50.708149 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11084 04:41:50.708576 test VIDIOC_QUERYCAP: OK
11085 04:41:50.709229 Received signal: <TESTSET> START Required-ioctls
11086 04:41:50.709594 Starting test_set Required-ioctls
11087 04:41:50.732810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11088 04:41:50.733747 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11090 04:41:50.736082 test invalid ioctls: OK
11091 04:41:50.756498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11092 04:41:50.757140
11093 04:41:50.758020 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11095 04:41:50.767978 Allow for multiple opens:
11096 04:41:50.779454 <LAVA_SIGNAL_TESTSET STOP>
11097 04:41:50.780323 Received signal: <TESTSET> STOP
11098 04:41:50.780870 Closing test_set Required-ioctls
11099 04:41:50.788862 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11100 04:41:50.789842 Received signal: <TESTSET> START Allow-for-multiple-opens
11101 04:41:50.790424 Starting test_set Allow-for-multiple-opens
11102 04:41:50.791939 test second /dev/video2 open: OK
11103 04:41:50.812495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11104 04:41:50.813337 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11106 04:41:50.815423 test VIDIOC_QUERYCAP: OK
11107 04:41:50.837461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11108 04:41:50.837718 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11110 04:41:50.840839 test VIDIOC_G/S_PRIORITY: OK
11111 04:41:50.861515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11112 04:41:50.861769 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11114 04:41:50.865020 test for unlimited opens: OK
11115 04:41:50.885757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11116 04:41:50.885870
11117 04:41:50.886156 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11119 04:41:50.896973 Debug ioctls:
11120 04:41:50.904487 <LAVA_SIGNAL_TESTSET STOP>
11121 04:41:50.905460 Received signal: <TESTSET> STOP
11122 04:41:50.906073 Closing test_set Allow-for-multiple-opens
11123 04:41:50.915990 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11124 04:41:50.916711 Received signal: <TESTSET> START Debug-ioctls
11125 04:41:50.917160 Starting test_set Debug-ioctls
11126 04:41:50.928772 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11127 04:41:50.954603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11128 04:41:50.955470 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11130 04:41:50.961504 test VIDIOC_LOG_STATUS: OK (Not Supported)
11131 04:41:50.986849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11132 04:41:50.987316
11133 04:41:50.988007 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11135 04:41:50.997443 Input ioctls:
11136 04:41:51.007209 <LAVA_SIGNAL_TESTSET STOP>
11137 04:41:51.007918 Received signal: <TESTSET> STOP
11138 04:41:51.008270 Closing test_set Debug-ioctls
11139 04:41:51.017693 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11140 04:41:51.017945 Received signal: <TESTSET> START Input-ioctls
11141 04:41:51.018016 Starting test_set Input-ioctls
11142 04:41:51.020734 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11143 04:41:51.045215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11144 04:41:51.046008 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11146 04:41:51.048268 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11147 04:41:51.063982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11148 04:41:51.064659 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11150 04:41:51.070593 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11151 04:41:51.087734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11152 04:41:51.088424 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11154 04:41:51.094131 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11155 04:41:51.112871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11156 04:41:51.113640 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11158 04:41:51.116591 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11159 04:41:51.135350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11160 04:41:51.136300 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11162 04:41:51.138248 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11163 04:41:51.159966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11164 04:41:51.160749 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11166 04:41:51.163181 Inputs: 0 Audio Inputs: 0 Tuners: 0
11167 04:41:51.169573
11168 04:41:51.187071 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11169 04:41:51.209542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11170 04:41:51.210223 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11172 04:41:51.215679 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11173 04:41:51.233477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11174 04:41:51.234170 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11176 04:41:51.239621 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11177 04:41:51.263071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11178 04:41:51.263747 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11180 04:41:51.269140 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11181 04:41:51.287594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11182 04:41:51.288273 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11184 04:41:51.294203 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11185 04:41:51.312390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11186 04:41:51.312823
11187 04:41:51.313411 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11189 04:41:51.331368 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11190 04:41:51.352544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11191 04:41:51.353238 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11193 04:41:51.359029 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11194 04:41:51.379441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11195 04:41:51.380185 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11197 04:41:51.382430 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11198 04:41:51.404680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11199 04:41:51.405366 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11201 04:41:51.407468 test VIDIOC_G/S_EDID: OK (Not Supported)
11202 04:41:51.434893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11203 04:41:51.435514
11204 04:41:51.436233 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11206 04:41:51.445309 Control ioctls:
11207 04:41:51.453817 <LAVA_SIGNAL_TESTSET STOP>
11208 04:41:51.454493 Received signal: <TESTSET> STOP
11209 04:41:51.454880 Closing test_set Input-ioctls
11210 04:41:51.463617 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11211 04:41:51.464294 Received signal: <TESTSET> START Control-ioctls
11212 04:41:51.464647 Starting test_set Control-ioctls
11213 04:41:51.466610 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11214 04:41:51.492037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11215 04:41:51.492492 test VIDIOC_QUERYCTRL: OK
11216 04:41:51.493246 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11218 04:41:51.514034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11219 04:41:51.514888 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11221 04:41:51.517384 test VIDIOC_G/S_CTRL: OK
11222 04:41:51.539102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11223 04:41:51.539837 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11225 04:41:51.541940 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11226 04:41:51.563807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11227 04:41:51.564645 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11229 04:41:51.573563 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11230 04:41:51.577105 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11231 04:41:51.609869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11232 04:41:51.610697 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11234 04:41:51.613357 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11235 04:41:51.634123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11236 04:41:51.634839 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11238 04:41:51.637511 Standard Controls: 16 Private Controls: 0
11239 04:41:51.644311
11240 04:41:51.654366 Format ioctls:
11241 04:41:51.660907 <LAVA_SIGNAL_TESTSET STOP>
11242 04:41:51.661582 Received signal: <TESTSET> STOP
11243 04:41:51.661937 Closing test_set Control-ioctls
11244 04:41:51.670623 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11245 04:41:51.671298 Received signal: <TESTSET> START Format-ioctls
11246 04:41:51.671764 Starting test_set Format-ioctls
11247 04:41:51.673611 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11248 04:41:51.698927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11249 04:41:51.699774 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11251 04:41:51.701921 test VIDIOC_G/S_PARM: OK
11252 04:41:51.720600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11253 04:41:51.721664 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11255 04:41:51.723682 test VIDIOC_G_FBUF: OK (Not Supported)
11256 04:41:51.744315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11257 04:41:51.745193 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11259 04:41:51.747431 test VIDIOC_G_FMT: OK
11260 04:41:51.770658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11261 04:41:51.771333 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11263 04:41:51.774130 test VIDIOC_TRY_FMT: OK
11264 04:41:51.794569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11265 04:41:51.795133 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11267 04:41:51.804874 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11268 04:41:51.807791 test VIDIOC_S_FMT: FAIL
11269 04:41:51.835586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11270 04:41:51.836137 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11272 04:41:51.838775 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11273 04:41:51.859846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11274 04:41:51.860380 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11276 04:41:51.862878 test Cropping: OK
11277 04:41:51.890293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11278 04:41:51.890559 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11280 04:41:51.893588 test Composing: OK (Not Supported)
11281 04:41:51.914835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11282 04:41:51.915115 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11284 04:41:51.917746 test Scaling: OK (Not Supported)
11285 04:41:51.939668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11286 04:41:51.939762
11287 04:41:51.940000 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11289 04:41:51.955205 Codec ioctls:
11290 04:41:51.962688 <LAVA_SIGNAL_TESTSET STOP>
11291 04:41:51.962949 Received signal: <TESTSET> STOP
11292 04:41:51.963019 Closing test_set Format-ioctls
11293 04:41:51.971726 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11294 04:41:51.972013 Received signal: <TESTSET> START Codec-ioctls
11295 04:41:51.972113 Starting test_set Codec-ioctls
11296 04:41:51.974920 test VIDIOC_(TRY_)ENCODER_CMD: OK
11297 04:41:51.994731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11298 04:41:51.995473 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11300 04:41:52.001184 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11301 04:41:52.019407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11302 04:41:52.020157 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11304 04:41:52.026087 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11305 04:41:52.045402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11306 04:41:52.045837
11307 04:41:52.046426 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11309 04:41:52.055932 Buffer ioctls:
11310 04:41:52.064875 <LAVA_SIGNAL_TESTSET STOP>
11311 04:41:52.065559 Received signal: <TESTSET> STOP
11312 04:41:52.065913 Closing test_set Codec-ioctls
11313 04:41:52.075072 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11314 04:41:52.075762 Received signal: <TESTSET> START Buffer-ioctls
11315 04:41:52.076127 Starting test_set Buffer-ioctls
11316 04:41:52.078058 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11317 04:41:52.102212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11318 04:41:52.102838 test VIDIOC_EXPBUF: OK
11319 04:41:52.103562 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11321 04:41:52.124333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11322 04:41:52.125041 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11324 04:41:52.127636 test Requests: OK (Not Supported)
11325 04:41:52.149041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11326 04:41:52.149639
11327 04:41:52.150397 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11329 04:41:52.159391 Test input 0:
11330 04:41:52.170427
11331 04:41:52.180691 Streaming ioctls:
11332 04:41:52.187621 <LAVA_SIGNAL_TESTSET STOP>
11333 04:41:52.188310 Received signal: <TESTSET> STOP
11334 04:41:52.188670 Closing test_set Buffer-ioctls
11335 04:41:52.197675 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11336 04:41:52.198357 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11337 04:41:52.198714 Starting test_set Streaming-ioctls_Test-input-0
11338 04:41:52.200738 test read/write: OK (Not Supported)
11339 04:41:52.222630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11340 04:41:52.223317 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11342 04:41:52.229299 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11343 04:41:52.242453 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11344 04:41:52.245505 test blocking wait: FAIL
11345 04:41:52.270931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11346 04:41:52.271645 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11348 04:41:52.280746 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11349 04:41:52.287582 test MMAP (select): FAIL
11350 04:41:52.314774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11351 04:41:52.315034 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11353 04:41:52.321285 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11354 04:41:52.324274 test MMAP (epoll): FAIL
11355 04:41:52.349784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11356 04:41:52.350488 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11358 04:41:52.356496 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11359 04:41:52.367326 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11360 04:41:52.375633 test USERPTR (select): FAIL
11361 04:41:52.400292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11362 04:41:52.401199 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11364 04:41:52.406738 test DMABUF: Cannot test, specify --expbuf-device
11365 04:41:52.410207
11366 04:41:52.429845 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11367 04:41:52.435826 <LAVA_TEST_RUNNER EXIT>
11368 04:41:52.436553 ok: lava_test_shell seems to have completed
11369 04:41:52.436941 Marking unfinished test run as failed
11371 04:41:52.441673 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11372 04:41:52.442272 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11373 04:41:52.442715 end: 3 lava-test-retry (duration 00:00:03) [common]
11374 04:41:52.443163 start: 4 finalize (timeout 00:08:10) [common]
11375 04:41:52.443688 start: 4.1 power-off (timeout 00:00:30) [common]
11376 04:41:52.444423 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11377 04:41:52.570290 >> Command sent successfully.
11378 04:41:52.583920 Returned 0 in 0 seconds
11379 04:41:52.685519 end: 4.1 power-off (duration 00:00:00) [common]
11381 04:41:52.687902 start: 4.2 read-feedback (timeout 00:08:10) [common]
11382 04:41:52.689626 Listened to connection for namespace 'common' for up to 1s
11383 04:41:53.690102 Finalising connection for namespace 'common'
11384 04:41:53.690965 Disconnecting from shell: Finalise
11385 04:41:53.691687 / #
11386 04:41:53.792948 end: 4.2 read-feedback (duration 00:00:01) [common]
11387 04:41:53.793759 end: 4 finalize (duration 00:00:01) [common]
11388 04:41:53.794564 Cleaning after the job
11389 04:41:53.795318 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11241315/tftp-deploy-7vkciubz/ramdisk
11390 04:41:53.820897 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11241315/tftp-deploy-7vkciubz/kernel
11391 04:41:53.837498 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11241315/tftp-deploy-7vkciubz/dtb
11392 04:41:53.837823 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11241315/tftp-deploy-7vkciubz/modules
11393 04:41:53.847467 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11241315
11394 04:41:53.920385 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11241315
11395 04:41:53.920573 Job finished correctly