Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 31
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 45
- Errors: 1
1 12:19:31.079235 lava-dispatcher, installed at version: 2023.06
2 12:19:31.079456 start: 0 validate
3 12:19:31.079599 Start time: 2023-08-16 12:19:31.079591+00:00 (UTC)
4 12:19:31.079751 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:19:31.079908 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 12:19:31.333733 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:19:31.334464 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-1-g0a940c1b3dc0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:19:31.596088 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:19:31.596832 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-1-g0a940c1b3dc0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:20:12.107244 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:20:12.107449 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:20:12.610416 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:20:12.610584 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-1-g0a940c1b3dc0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:20:22.114468 validate duration: 51.03
16 12:20:22.114803 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:20:22.114909 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:20:22.114998 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:20:22.115127 Not decompressing ramdisk as can be used compressed.
20 12:20:22.115214 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 12:20:22.115279 saving as /var/lib/lava/dispatcher/tmp/11299297/tftp-deploy-mxwlri9y/ramdisk/initrd.cpio.gz
22 12:20:22.115342 total size: 4665412 (4 MB)
23 12:20:22.363830 progress 0 % (0 MB)
24 12:20:22.365401 progress 5 % (0 MB)
25 12:20:22.366738 progress 10 % (0 MB)
26 12:20:22.368144 progress 15 % (0 MB)
27 12:20:22.369427 progress 20 % (0 MB)
28 12:20:22.370727 progress 25 % (1 MB)
29 12:20:22.372056 progress 30 % (1 MB)
30 12:20:22.373333 progress 35 % (1 MB)
31 12:20:22.374685 progress 40 % (1 MB)
32 12:20:22.376205 progress 45 % (2 MB)
33 12:20:22.377445 progress 50 % (2 MB)
34 12:20:22.378774 progress 55 % (2 MB)
35 12:20:22.380083 progress 60 % (2 MB)
36 12:20:22.381326 progress 65 % (2 MB)
37 12:20:22.382587 progress 70 % (3 MB)
38 12:20:22.383976 progress 75 % (3 MB)
39 12:20:22.385271 progress 80 % (3 MB)
40 12:20:22.386759 progress 85 % (3 MB)
41 12:20:22.388019 progress 90 % (4 MB)
42 12:20:22.389253 progress 95 % (4 MB)
43 12:20:22.390503 progress 100 % (4 MB)
44 12:20:22.390698 4 MB downloaded in 0.28 s (16.16 MB/s)
45 12:20:22.390853 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:20:22.391089 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:20:22.391195 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:20:22.391317 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:20:22.391492 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-1-g0a940c1b3dc0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:20:22.391566 saving as /var/lib/lava/dispatcher/tmp/11299297/tftp-deploy-mxwlri9y/kernel/Image
52 12:20:22.391627 total size: 49220096 (46 MB)
53 12:20:22.391689 No compression specified
54 12:20:22.392835 progress 0 % (0 MB)
55 12:20:22.406014 progress 5 % (2 MB)
56 12:20:22.419565 progress 10 % (4 MB)
57 12:20:22.433212 progress 15 % (7 MB)
58 12:20:22.446910 progress 20 % (9 MB)
59 12:20:22.460842 progress 25 % (11 MB)
60 12:20:22.474753 progress 30 % (14 MB)
61 12:20:22.488416 progress 35 % (16 MB)
62 12:20:22.501955 progress 40 % (18 MB)
63 12:20:22.515454 progress 45 % (21 MB)
64 12:20:22.529125 progress 50 % (23 MB)
65 12:20:22.542600 progress 55 % (25 MB)
66 12:20:22.556201 progress 60 % (28 MB)
67 12:20:22.569566 progress 65 % (30 MB)
68 12:20:22.582810 progress 70 % (32 MB)
69 12:20:22.595964 progress 75 % (35 MB)
70 12:20:22.608983 progress 80 % (37 MB)
71 12:20:22.621896 progress 85 % (39 MB)
72 12:20:22.635240 progress 90 % (42 MB)
73 12:20:22.648191 progress 95 % (44 MB)
74 12:20:22.661199 progress 100 % (46 MB)
75 12:20:22.661362 46 MB downloaded in 0.27 s (174.03 MB/s)
76 12:20:22.661520 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:20:22.661754 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:20:22.661843 start: 1.3 download-retry (timeout 00:09:59) [common]
80 12:20:22.661933 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 12:20:22.662081 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-1-g0a940c1b3dc0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:20:22.662153 saving as /var/lib/lava/dispatcher/tmp/11299297/tftp-deploy-mxwlri9y/dtb/mt8192-asurada-spherion-r0.dtb
83 12:20:22.662213 total size: 47278 (0 MB)
84 12:20:22.662273 No compression specified
85 12:20:22.663480 progress 69 % (0 MB)
86 12:20:22.663782 progress 100 % (0 MB)
87 12:20:22.663955 0 MB downloaded in 0.00 s (25.91 MB/s)
88 12:20:22.664074 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:20:22.664293 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:20:22.664379 start: 1.4 download-retry (timeout 00:09:59) [common]
92 12:20:22.664458 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 12:20:22.664569 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 12:20:22.664635 saving as /var/lib/lava/dispatcher/tmp/11299297/tftp-deploy-mxwlri9y/nfsrootfs/full.rootfs.tar
95 12:20:22.664694 total size: 125290964 (119 MB)
96 12:20:22.664754 Using unxz to decompress xz
97 12:20:22.668967 progress 0 % (0 MB)
98 12:20:23.015256 progress 5 % (6 MB)
99 12:20:23.359396 progress 10 % (11 MB)
100 12:20:23.707606 progress 15 % (17 MB)
101 12:20:23.905285 progress 20 % (23 MB)
102 12:20:24.093475 progress 25 % (29 MB)
103 12:20:24.467680 progress 30 % (35 MB)
104 12:20:24.822577 progress 35 % (41 MB)
105 12:20:25.210834 progress 40 % (47 MB)
106 12:20:25.590551 progress 45 % (53 MB)
107 12:20:25.986745 progress 50 % (59 MB)
108 12:20:26.347341 progress 55 % (65 MB)
109 12:20:26.717338 progress 60 % (71 MB)
110 12:20:27.061258 progress 65 % (77 MB)
111 12:20:27.434039 progress 70 % (83 MB)
112 12:20:27.825696 progress 75 % (89 MB)
113 12:20:28.249737 progress 80 % (95 MB)
114 12:20:28.672168 progress 85 % (101 MB)
115 12:20:28.919706 progress 90 % (107 MB)
116 12:20:29.261044 progress 95 % (113 MB)
117 12:20:29.637061 progress 100 % (119 MB)
118 12:20:29.642916 119 MB downloaded in 6.98 s (17.12 MB/s)
119 12:20:29.643183 end: 1.4.1 http-download (duration 00:00:07) [common]
121 12:20:29.643472 end: 1.4 download-retry (duration 00:00:07) [common]
122 12:20:29.643576 start: 1.5 download-retry (timeout 00:09:52) [common]
123 12:20:29.643666 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 12:20:29.643839 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-1-g0a940c1b3dc0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:20:29.643912 saving as /var/lib/lava/dispatcher/tmp/11299297/tftp-deploy-mxwlri9y/modules/modules.tar
126 12:20:29.643992 total size: 8615968 (8 MB)
127 12:20:29.644072 Using unxz to decompress xz
128 12:20:29.903582 progress 0 % (0 MB)
129 12:20:29.926125 progress 5 % (0 MB)
130 12:20:29.949031 progress 10 % (0 MB)
131 12:20:29.977283 progress 15 % (1 MB)
132 12:20:30.004842 progress 20 % (1 MB)
133 12:20:30.033444 progress 25 % (2 MB)
134 12:20:30.061193 progress 30 % (2 MB)
135 12:20:30.088773 progress 35 % (2 MB)
136 12:20:30.115063 progress 40 % (3 MB)
137 12:20:30.140142 progress 45 % (3 MB)
138 12:20:30.166915 progress 50 % (4 MB)
139 12:20:30.192857 progress 55 % (4 MB)
140 12:20:30.217997 progress 60 % (4 MB)
141 12:20:30.241587 progress 65 % (5 MB)
142 12:20:30.269737 progress 70 % (5 MB)
143 12:20:30.294703 progress 75 % (6 MB)
144 12:20:30.321734 progress 80 % (6 MB)
145 12:20:30.352735 progress 85 % (7 MB)
146 12:20:30.380438 progress 90 % (7 MB)
147 12:20:30.405440 progress 95 % (7 MB)
148 12:20:30.429472 progress 100 % (8 MB)
149 12:20:30.436107 8 MB downloaded in 0.79 s (10.37 MB/s)
150 12:20:30.436464 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:20:30.436736 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:20:30.436831 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 12:20:30.436926 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 12:20:32.621208 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11299297/extract-nfsrootfs-oufad8j8
156 12:20:32.621417 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 12:20:32.621524 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 12:20:32.621699 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv
159 12:20:32.621831 makedir: /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin
160 12:20:32.621934 makedir: /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/tests
161 12:20:32.622030 makedir: /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/results
162 12:20:32.622132 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-add-keys
163 12:20:32.622279 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-add-sources
164 12:20:32.622408 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-background-process-start
165 12:20:32.622535 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-background-process-stop
166 12:20:32.622703 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-common-functions
167 12:20:32.622828 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-echo-ipv4
168 12:20:32.622953 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-install-packages
169 12:20:32.623080 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-installed-packages
170 12:20:32.623203 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-os-build
171 12:20:32.623328 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-probe-channel
172 12:20:32.623453 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-probe-ip
173 12:20:32.623577 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-target-ip
174 12:20:32.623700 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-target-mac
175 12:20:32.623823 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-target-storage
176 12:20:32.623946 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-test-case
177 12:20:32.624072 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-test-event
178 12:20:32.624195 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-test-feedback
179 12:20:32.624319 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-test-raise
180 12:20:32.624442 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-test-reference
181 12:20:32.624566 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-test-runner
182 12:20:32.624691 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-test-set
183 12:20:32.624816 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-test-shell
184 12:20:32.624942 Updating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-install-packages (oe)
185 12:20:32.625095 Updating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/bin/lava-installed-packages (oe)
186 12:20:32.625218 Creating /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/environment
187 12:20:32.625314 LAVA metadata
188 12:20:32.625386 - LAVA_JOB_ID=11299297
189 12:20:32.625449 - LAVA_DISPATCHER_IP=192.168.201.1
190 12:20:32.625551 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
191 12:20:32.625618 skipped lava-vland-overlay
192 12:20:32.625693 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 12:20:32.625771 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
194 12:20:32.625831 skipped lava-multinode-overlay
195 12:20:32.625903 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 12:20:32.625980 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
197 12:20:32.626053 Loading test definitions
198 12:20:32.626140 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
199 12:20:32.626211 Using /lava-11299297 at stage 0
200 12:20:32.626523 uuid=11299297_1.6.2.3.1 testdef=None
201 12:20:32.626633 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 12:20:32.626732 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
203 12:20:32.627242 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 12:20:32.627460 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
206 12:20:32.628118 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 12:20:32.628343 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
209 12:20:32.628957 runner path: /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/0/tests/0_dmesg test_uuid 11299297_1.6.2.3.1
210 12:20:32.629112 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 12:20:32.629335 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:49) [common]
213 12:20:32.629406 Using /lava-11299297 at stage 1
214 12:20:32.629709 uuid=11299297_1.6.2.3.5 testdef=None
215 12:20:32.629797 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 12:20:32.629880 start: 1.6.2.3.6 test-overlay (timeout 00:09:49) [common]
217 12:20:32.630344 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 12:20:32.630557 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:49) [common]
220 12:20:32.631511 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 12:20:32.631735 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:49) [common]
223 12:20:32.632354 runner path: /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/1/tests/1_bootrr test_uuid 11299297_1.6.2.3.5
224 12:20:32.632506 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 12:20:32.632709 Creating lava-test-runner.conf files
227 12:20:32.632771 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/0 for stage 0
228 12:20:32.632862 - 0_dmesg
229 12:20:32.632940 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11299297/lava-overlay-2ib964mv/lava-11299297/1 for stage 1
230 12:20:32.633030 - 1_bootrr
231 12:20:32.633123 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 12:20:32.633207 start: 1.6.2.4 compress-overlay (timeout 00:09:49) [common]
233 12:20:32.640491 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 12:20:32.640623 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:49) [common]
235 12:20:32.640712 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 12:20:32.640798 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 12:20:32.640882 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:49) [common]
238 12:20:32.762634 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 12:20:32.763047 start: 1.6.4 extract-modules (timeout 00:09:49) [common]
240 12:20:32.763229 extracting modules file /var/lib/lava/dispatcher/tmp/11299297/tftp-deploy-mxwlri9y/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11299297/extract-nfsrootfs-oufad8j8
241 12:20:32.988695 extracting modules file /var/lib/lava/dispatcher/tmp/11299297/tftp-deploy-mxwlri9y/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11299297/extract-overlay-ramdisk-wsqeuaow/ramdisk
242 12:20:33.221836 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 12:20:33.222044 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 12:20:33.222142 [common] Applying overlay to NFS
245 12:20:33.222216 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11299297/compress-overlay-6v5h812t/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11299297/extract-nfsrootfs-oufad8j8
246 12:20:33.231028 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 12:20:33.231181 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 12:20:33.231291 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 12:20:33.231382 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 12:20:33.231467 Building ramdisk /var/lib/lava/dispatcher/tmp/11299297/extract-overlay-ramdisk-wsqeuaow/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11299297/extract-overlay-ramdisk-wsqeuaow/ramdisk
251 12:20:33.556098 >> 119212 blocks
252 12:20:35.489606 rename /var/lib/lava/dispatcher/tmp/11299297/extract-overlay-ramdisk-wsqeuaow/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11299297/tftp-deploy-mxwlri9y/ramdisk/ramdisk.cpio.gz
253 12:20:35.490045 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 12:20:35.490168 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 12:20:35.490278 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 12:20:35.490428 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11299297/tftp-deploy-mxwlri9y/kernel/Image'
257 12:20:48.037985 Returned 0 in 12 seconds
258 12:20:48.139025 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11299297/tftp-deploy-mxwlri9y/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11299297/tftp-deploy-mxwlri9y/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11299297/tftp-deploy-mxwlri9y/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11299297/tftp-deploy-mxwlri9y/kernel/image.itb
259 12:20:48.506070 output: FIT description: Kernel Image image with one or more FDT blobs
260 12:20:48.506454 output: Created: Wed Aug 16 13:20:48 2023
261 12:20:48.506530 output: Image 0 (kernel-1)
262 12:20:48.506601 output: Description:
263 12:20:48.506705 output: Created: Wed Aug 16 13:20:48 2023
264 12:20:48.506769 output: Type: Kernel Image
265 12:20:48.506834 output: Compression: lzma compressed
266 12:20:48.506895 output: Data Size: 11040376 Bytes = 10781.62 KiB = 10.53 MiB
267 12:20:48.506959 output: Architecture: AArch64
268 12:20:48.507018 output: OS: Linux
269 12:20:48.507079 output: Load Address: 0x00000000
270 12:20:48.507132 output: Entry Point: 0x00000000
271 12:20:48.507187 output: Hash algo: crc32
272 12:20:48.507241 output: Hash value: 79630449
273 12:20:48.507295 output: Image 1 (fdt-1)
274 12:20:48.507349 output: Description: mt8192-asurada-spherion-r0
275 12:20:48.507403 output: Created: Wed Aug 16 13:20:48 2023
276 12:20:48.507457 output: Type: Flat Device Tree
277 12:20:48.507510 output: Compression: uncompressed
278 12:20:48.507565 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 12:20:48.507618 output: Architecture: AArch64
280 12:20:48.507672 output: Hash algo: crc32
281 12:20:48.507725 output: Hash value: cc4352de
282 12:20:48.507779 output: Image 2 (ramdisk-1)
283 12:20:48.507832 output: Description: unavailable
284 12:20:48.507884 output: Created: Wed Aug 16 13:20:48 2023
285 12:20:48.507938 output: Type: RAMDisk Image
286 12:20:48.507991 output: Compression: Unknown Compression
287 12:20:48.508045 output: Data Size: 17770465 Bytes = 17353.97 KiB = 16.95 MiB
288 12:20:48.508098 output: Architecture: AArch64
289 12:20:48.508152 output: OS: Linux
290 12:20:48.508205 output: Load Address: unavailable
291 12:20:48.508257 output: Entry Point: unavailable
292 12:20:48.508310 output: Hash algo: crc32
293 12:20:48.508363 output: Hash value: 8f8bad21
294 12:20:48.508417 output: Default Configuration: 'conf-1'
295 12:20:48.508470 output: Configuration 0 (conf-1)
296 12:20:48.508524 output: Description: mt8192-asurada-spherion-r0
297 12:20:48.508577 output: Kernel: kernel-1
298 12:20:48.508631 output: Init Ramdisk: ramdisk-1
299 12:20:48.508684 output: FDT: fdt-1
300 12:20:48.508736 output: Loadables: kernel-1
301 12:20:48.508789 output:
302 12:20:48.508988 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 12:20:48.509087 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 12:20:48.509189 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
305 12:20:48.509282 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:34) [common]
306 12:20:48.509360 No LXC device requested
307 12:20:48.509439 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 12:20:48.509525 start: 1.8 deploy-device-env (timeout 00:09:34) [common]
309 12:20:48.509603 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 12:20:48.509672 Checking files for TFTP limit of 4294967296 bytes.
311 12:20:48.510183 end: 1 tftp-deploy (duration 00:00:26) [common]
312 12:20:48.510351 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 12:20:48.510446 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 12:20:48.510574 substitutions:
315 12:20:48.510649 - {DTB}: 11299297/tftp-deploy-mxwlri9y/dtb/mt8192-asurada-spherion-r0.dtb
316 12:20:48.510714 - {INITRD}: 11299297/tftp-deploy-mxwlri9y/ramdisk/ramdisk.cpio.gz
317 12:20:48.510774 - {KERNEL}: 11299297/tftp-deploy-mxwlri9y/kernel/Image
318 12:20:48.510833 - {LAVA_MAC}: None
319 12:20:48.510889 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11299297/extract-nfsrootfs-oufad8j8
320 12:20:48.510945 - {NFS_SERVER_IP}: 192.168.201.1
321 12:20:48.511000 - {PRESEED_CONFIG}: None
322 12:20:48.511055 - {PRESEED_LOCAL}: None
323 12:20:48.511110 - {RAMDISK}: 11299297/tftp-deploy-mxwlri9y/ramdisk/ramdisk.cpio.gz
324 12:20:48.511164 - {ROOT_PART}: None
325 12:20:48.511219 - {ROOT}: None
326 12:20:48.511274 - {SERVER_IP}: 192.168.201.1
327 12:20:48.511328 - {TEE}: None
328 12:20:48.511382 Parsed boot commands:
329 12:20:48.511435 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 12:20:48.511622 Parsed boot commands: tftpboot 192.168.201.1 11299297/tftp-deploy-mxwlri9y/kernel/image.itb 11299297/tftp-deploy-mxwlri9y/kernel/cmdline
331 12:20:48.511710 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 12:20:48.511795 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 12:20:48.511889 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 12:20:48.511974 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 12:20:48.512047 Not connected, no need to disconnect.
336 12:20:48.512122 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 12:20:48.512206 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 12:20:48.512308 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
339 12:20:48.516402 Setting prompt string to ['lava-test: # ']
340 12:20:48.516770 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 12:20:48.516884 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 12:20:48.516984 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 12:20:48.517080 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 12:20:48.517284 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
345 12:20:53.669480 >> Command sent successfully.
346 12:20:53.680986 Returned 0 in 5 seconds
347 12:20:53.782384 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 12:20:53.784025 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 12:20:53.784598 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 12:20:53.785103 Setting prompt string to 'Starting depthcharge on Spherion...'
352 12:20:53.785508 Changing prompt to 'Starting depthcharge on Spherion...'
353 12:20:53.785919 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 12:20:53.787372 [Enter `^Ec?' for help]
355 12:20:53.945552
356 12:20:53.946060
357 12:20:53.946408 F0: 102B 0000
358 12:20:53.946803
359 12:20:53.947127 F3: 1001 0000 [0200]
360 12:20:53.947440
361 12:20:53.949238 F3: 1001 0000
362 12:20:53.949669
363 12:20:53.950009 F7: 102D 0000
364 12:20:53.950326
365 12:20:53.950754 F1: 0000 0000
366 12:20:53.951110
367 12:20:53.953075 V0: 0000 0000 [0001]
368 12:20:53.953704
369 12:20:53.954238 00: 0007 8000
370 12:20:53.954859
371 12:20:53.957023 01: 0000 0000
372 12:20:53.957523
373 12:20:53.957944 BP: 0C00 0209 [0000]
374 12:20:53.958427
375 12:20:53.958914 G0: 1182 0000
376 12:20:53.960512
377 12:20:53.961009 EC: 0000 0021 [4000]
378 12:20:53.961463
379 12:20:53.963879 S7: 0000 0000 [0000]
380 12:20:53.964392
381 12:20:53.964858 CC: 0000 0000 [0001]
382 12:20:53.965312
383 12:20:53.967414 T0: 0000 0040 [010F]
384 12:20:53.967921
385 12:20:53.968344 Jump to BL
386 12:20:53.968753
387 12:20:53.991869
388 12:20:53.992278
389 12:20:53.992349
390 12:20:53.998727 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 12:20:54.002269 ARM64: Exception handlers installed.
392 12:20:54.005315 ARM64: Testing exception
393 12:20:54.009223 ARM64: Done test exception
394 12:20:54.016363 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 12:20:54.027162 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 12:20:54.033744 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 12:20:54.045002 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 12:20:54.051354 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 12:20:54.058081 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 12:20:54.068018 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 12:20:54.074705 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 12:20:54.094954 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 12:20:54.097866 WDT: Last reset was cold boot
404 12:20:54.101202 SPI1(PAD0) initialized at 2873684 Hz
405 12:20:54.104758 SPI5(PAD0) initialized at 992727 Hz
406 12:20:54.108129 VBOOT: Loading verstage.
407 12:20:54.114507 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 12:20:54.117942 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 12:20:54.121449 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 12:20:54.124693 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 12:20:54.132152 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 12:20:54.138775 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 12:20:54.150034 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
414 12:20:54.150116
415 12:20:54.150181
416 12:20:54.160211 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 12:20:54.162891 ARM64: Exception handlers installed.
418 12:20:54.166050 ARM64: Testing exception
419 12:20:54.166131 ARM64: Done test exception
420 12:20:54.172728 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 12:20:54.176287 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:20:54.190554 Probing TPM: . done!
423 12:20:54.190691 TPM ready after 0 ms
424 12:20:54.197331 Connected to device vid:did:rid of 1ae0:0028:00
425 12:20:54.207073 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
426 12:20:54.245556 Initialized TPM device CR50 revision 0
427 12:20:54.257279 tlcl_send_startup: Startup return code is 0
428 12:20:54.257366 TPM: setup succeeded
429 12:20:54.268872 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 12:20:54.277471 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 12:20:54.287819 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 12:20:54.296279 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 12:20:54.299606 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 12:20:54.302950 in-header: 03 07 00 00 08 00 00 00
435 12:20:54.306153 in-data: aa e4 47 04 13 02 00 00
436 12:20:54.309658 Chrome EC: UHEPI supported
437 12:20:54.316374 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 12:20:54.319628 in-header: 03 ad 00 00 08 00 00 00
439 12:20:54.323155 in-data: 00 20 20 08 00 00 00 00
440 12:20:54.323239 Phase 1
441 12:20:54.326368 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 12:20:54.332773 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 12:20:54.339574 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 12:20:54.343090 Recovery requested (1009000e)
445 12:20:54.346850 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 12:20:54.355295 tlcl_extend: response is 0
447 12:20:54.363593 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 12:20:54.369027 tlcl_extend: response is 0
449 12:20:54.375292 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 12:20:54.395891 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
451 12:20:54.402699 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 12:20:54.402783
453 12:20:54.402849
454 12:20:54.412930 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 12:20:54.416540 ARM64: Exception handlers installed.
456 12:20:54.416624 ARM64: Testing exception
457 12:20:54.420578 ARM64: Done test exception
458 12:20:54.441431 pmic_efuse_setting: Set efuses in 11 msecs
459 12:20:54.444728 pmwrap_interface_init: Select PMIF_VLD_RDY
460 12:20:54.452535 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 12:20:54.455400 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 12:20:54.459061 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 12:20:54.465055 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 12:20:54.469296 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 12:20:54.475510 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 12:20:54.479206 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 12:20:54.485963 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 12:20:54.488636 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 12:20:54.492268 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 12:20:54.499394 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 12:20:54.502098 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 12:20:54.508785 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 12:20:54.512695 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 12:20:54.518868 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 12:20:54.525568 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 12:20:54.531755 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 12:20:54.535387 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 12:20:54.541930 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 12:20:54.548668 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 12:20:54.552022 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 12:20:54.559678 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 12:20:54.563018 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 12:20:54.569893 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 12:20:54.577287 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 12:20:54.579498 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 12:20:54.586885 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 12:20:54.590358 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 12:20:54.596902 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 12:20:54.600696 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 12:20:54.604487 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 12:20:54.611267 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 12:20:54.614437 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 12:20:54.621355 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 12:20:54.624525 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 12:20:54.630772 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 12:20:54.634071 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 12:20:54.640684 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 12:20:54.644860 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 12:20:54.648329 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 12:20:54.655817 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 12:20:54.659392 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 12:20:54.662370 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 12:20:54.666307 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 12:20:54.672414 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 12:20:54.675979 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 12:20:54.678869 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 12:20:54.682517 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 12:20:54.689260 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 12:20:54.692680 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 12:20:54.695778 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 12:20:54.705673 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 12:20:54.711954 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 12:20:54.718848 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 12:20:54.725544 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 12:20:54.735339 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 12:20:54.738840 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 12:20:54.742666 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 12:20:54.748577 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 12:20:54.755665 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x8
520 12:20:54.758514 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 12:20:54.765733 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
522 12:20:54.768925 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 12:20:54.778836 [RTC]rtc_get_frequency_meter,154: input=15, output=834
524 12:20:54.788074 [RTC]rtc_get_frequency_meter,154: input=7, output=709
525 12:20:54.797430 [RTC]rtc_get_frequency_meter,154: input=11, output=772
526 12:20:54.806953 [RTC]rtc_get_frequency_meter,154: input=13, output=804
527 12:20:54.816469 [RTC]rtc_get_frequency_meter,154: input=12, output=788
528 12:20:54.826300 [RTC]rtc_get_frequency_meter,154: input=12, output=788
529 12:20:54.835686 [RTC]rtc_get_frequency_meter,154: input=13, output=802
530 12:20:54.838615 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
531 12:20:54.846299 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
532 12:20:54.849396 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 12:20:54.852664 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 12:20:54.859584 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 12:20:54.862575 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 12:20:54.866456 ADC[4]: Raw value=903031 ID=7
537 12:20:54.866565 ADC[3]: Raw value=213282 ID=1
538 12:20:54.870069 RAM Code: 0x71
539 12:20:54.873110 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 12:20:54.879345 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 12:20:54.886229 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 12:20:54.892704 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 12:20:54.896217 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 12:20:54.899182 in-header: 03 07 00 00 08 00 00 00
545 12:20:54.902479 in-data: aa e4 47 04 13 02 00 00
546 12:20:54.905734 Chrome EC: UHEPI supported
547 12:20:54.912293 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 12:20:54.916126 in-header: 03 dd 00 00 08 00 00 00
549 12:20:54.919702 in-data: 90 20 60 08 00 00 00 00
550 12:20:54.922344 MRC: failed to locate region type 0.
551 12:20:54.929191 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 12:20:54.932793 DRAM-K: Running full calibration
553 12:20:54.939043 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 12:20:54.939128 header.status = 0x0
555 12:20:54.943067 header.version = 0x6 (expected: 0x6)
556 12:20:54.945806 header.size = 0xd00 (expected: 0xd00)
557 12:20:54.949183 header.flags = 0x0
558 12:20:54.955917 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 12:20:54.972293 read SPI 0x72590 0x1c583: 12496 us, 9290 KB/s, 74.320 Mbps
560 12:20:54.979199 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 12:20:54.982484 dram_init: ddr_geometry: 2
562 12:20:54.985700 [EMI] MDL number = 2
563 12:20:54.985781 [EMI] Get MDL freq = 0
564 12:20:54.988915 dram_init: ddr_type: 0
565 12:20:54.989021 is_discrete_lpddr4: 1
566 12:20:54.992640 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 12:20:54.992739
568 12:20:54.992829
569 12:20:54.995581 [Bian_co] ETT version 0.0.0.1
570 12:20:55.002452 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 12:20:55.002557
572 12:20:55.005794 dramc_set_vcore_voltage set vcore to 650000
573 12:20:55.008962 Read voltage for 800, 4
574 12:20:55.009047 Vio18 = 0
575 12:20:55.009116 Vcore = 650000
576 12:20:55.012262 Vdram = 0
577 12:20:55.012362 Vddq = 0
578 12:20:55.012453 Vmddr = 0
579 12:20:55.015337 dram_init: config_dvfs: 1
580 12:20:55.018415 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 12:20:55.025321 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 12:20:55.028776 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
583 12:20:55.032164 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
584 12:20:55.035091 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
585 12:20:55.041597 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
586 12:20:55.041701 MEM_TYPE=3, freq_sel=18
587 12:20:55.045026 sv_algorithm_assistance_LP4_1600
588 12:20:55.048408 ============ PULL DRAM RESETB DOWN ============
589 12:20:55.055193 ========== PULL DRAM RESETB DOWN end =========
590 12:20:55.058077 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 12:20:55.061663 ===================================
592 12:20:55.065363 LPDDR4 DRAM CONFIGURATION
593 12:20:55.068318 ===================================
594 12:20:55.068432 EX_ROW_EN[0] = 0x0
595 12:20:55.071647 EX_ROW_EN[1] = 0x0
596 12:20:55.071752 LP4Y_EN = 0x0
597 12:20:55.074717 WORK_FSP = 0x0
598 12:20:55.074819 WL = 0x2
599 12:20:55.078742 RL = 0x2
600 12:20:55.081415 BL = 0x2
601 12:20:55.081517 RPST = 0x0
602 12:20:55.085008 RD_PRE = 0x0
603 12:20:55.085106 WR_PRE = 0x1
604 12:20:55.088121 WR_PST = 0x0
605 12:20:55.088221 DBI_WR = 0x0
606 12:20:55.091668 DBI_RD = 0x0
607 12:20:55.091741 OTF = 0x1
608 12:20:55.094757 ===================================
609 12:20:55.098150 ===================================
610 12:20:55.101461 ANA top config
611 12:20:55.104768 ===================================
612 12:20:55.104842 DLL_ASYNC_EN = 0
613 12:20:55.108128 ALL_SLAVE_EN = 1
614 12:20:55.111345 NEW_RANK_MODE = 1
615 12:20:55.115023 DLL_IDLE_MODE = 1
616 12:20:55.115110 LP45_APHY_COMB_EN = 1
617 12:20:55.117912 TX_ODT_DIS = 1
618 12:20:55.121138 NEW_8X_MODE = 1
619 12:20:55.124466 ===================================
620 12:20:55.128126 ===================================
621 12:20:55.131440 data_rate = 1600
622 12:20:55.134546 CKR = 1
623 12:20:55.138526 DQ_P2S_RATIO = 8
624 12:20:55.141399 ===================================
625 12:20:55.141500 CA_P2S_RATIO = 8
626 12:20:55.144662 DQ_CA_OPEN = 0
627 12:20:55.147833 DQ_SEMI_OPEN = 0
628 12:20:55.151292 CA_SEMI_OPEN = 0
629 12:20:55.154416 CA_FULL_RATE = 0
630 12:20:55.157965 DQ_CKDIV4_EN = 1
631 12:20:55.158077 CA_CKDIV4_EN = 1
632 12:20:55.161253 CA_PREDIV_EN = 0
633 12:20:55.164410 PH8_DLY = 0
634 12:20:55.167523 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 12:20:55.171360 DQ_AAMCK_DIV = 4
636 12:20:55.171438 CA_AAMCK_DIV = 4
637 12:20:55.174911 CA_ADMCK_DIV = 4
638 12:20:55.177720 DQ_TRACK_CA_EN = 0
639 12:20:55.181377 CA_PICK = 800
640 12:20:55.184512 CA_MCKIO = 800
641 12:20:55.187925 MCKIO_SEMI = 0
642 12:20:55.191058 PLL_FREQ = 3068
643 12:20:55.194738 DQ_UI_PI_RATIO = 32
644 12:20:55.194812 CA_UI_PI_RATIO = 0
645 12:20:55.197613 ===================================
646 12:20:55.200961 ===================================
647 12:20:55.204266 memory_type:LPDDR4
648 12:20:55.207902 GP_NUM : 10
649 12:20:55.207977 SRAM_EN : 1
650 12:20:55.210959 MD32_EN : 0
651 12:20:55.214569 ===================================
652 12:20:55.217585 [ANA_INIT] >>>>>>>>>>>>>>
653 12:20:55.217686 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 12:20:55.220767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 12:20:55.224557 ===================================
656 12:20:55.228181 data_rate = 1600,PCW = 0X7600
657 12:20:55.230812 ===================================
658 12:20:55.235197 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 12:20:55.241007 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 12:20:55.247643 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 12:20:55.251189 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 12:20:55.254445 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 12:20:55.257891 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 12:20:55.261317 [ANA_INIT] flow start
665 12:20:55.261399 [ANA_INIT] PLL >>>>>>>>
666 12:20:55.264937 [ANA_INIT] PLL <<<<<<<<
667 12:20:55.267474 [ANA_INIT] MIDPI >>>>>>>>
668 12:20:55.267573 [ANA_INIT] MIDPI <<<<<<<<
669 12:20:55.271419 [ANA_INIT] DLL >>>>>>>>
670 12:20:55.274516 [ANA_INIT] flow end
671 12:20:55.277949 ============ LP4 DIFF to SE enter ============
672 12:20:55.281063 ============ LP4 DIFF to SE exit ============
673 12:20:55.284045 [ANA_INIT] <<<<<<<<<<<<<
674 12:20:55.287495 [Flow] Enable top DCM control >>>>>
675 12:20:55.290890 [Flow] Enable top DCM control <<<<<
676 12:20:55.294157 Enable DLL master slave shuffle
677 12:20:55.297643 ==============================================================
678 12:20:55.300757 Gating Mode config
679 12:20:55.307476 ==============================================================
680 12:20:55.307551 Config description:
681 12:20:55.317253 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 12:20:55.324195 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 12:20:55.330474 SELPH_MODE 0: By rank 1: By Phase
684 12:20:55.333775 ==============================================================
685 12:20:55.337333 GAT_TRACK_EN = 1
686 12:20:55.340614 RX_GATING_MODE = 2
687 12:20:55.344300 RX_GATING_TRACK_MODE = 2
688 12:20:55.347259 SELPH_MODE = 1
689 12:20:55.350946 PICG_EARLY_EN = 1
690 12:20:55.353927 VALID_LAT_VALUE = 1
691 12:20:55.357194 ==============================================================
692 12:20:55.360594 Enter into Gating configuration >>>>
693 12:20:55.364308 Exit from Gating configuration <<<<
694 12:20:55.367222 Enter into DVFS_PRE_config >>>>>
695 12:20:55.380621 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 12:20:55.383599 Exit from DVFS_PRE_config <<<<<
697 12:20:55.387006 Enter into PICG configuration >>>>
698 12:20:55.387085 Exit from PICG configuration <<<<
699 12:20:55.390347 [RX_INPUT] configuration >>>>>
700 12:20:55.394126 [RX_INPUT] configuration <<<<<
701 12:20:55.400279 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 12:20:55.403932 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 12:20:55.411444 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 12:20:55.418840 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 12:20:55.422246 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 12:20:55.429747 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 12:20:55.433124 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 12:20:55.436439 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 12:20:55.440319 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 12:20:55.447289 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 12:20:55.451030 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 12:20:55.454538 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 12:20:55.458103 ===================================
714 12:20:55.461527 LPDDR4 DRAM CONFIGURATION
715 12:20:55.461613 ===================================
716 12:20:55.465356 EX_ROW_EN[0] = 0x0
717 12:20:55.468641 EX_ROW_EN[1] = 0x0
718 12:20:55.468722 LP4Y_EN = 0x0
719 12:20:55.472349 WORK_FSP = 0x0
720 12:20:55.472457 WL = 0x2
721 12:20:55.475936 RL = 0x2
722 12:20:55.476040 BL = 0x2
723 12:20:55.476142 RPST = 0x0
724 12:20:55.479899 RD_PRE = 0x0
725 12:20:55.480001 WR_PRE = 0x1
726 12:20:55.483331 WR_PST = 0x0
727 12:20:55.483410 DBI_WR = 0x0
728 12:20:55.487268 DBI_RD = 0x0
729 12:20:55.487347 OTF = 0x1
730 12:20:55.490840 ===================================
731 12:20:55.494645 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 12:20:55.498149 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 12:20:55.505288 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 12:20:55.508596 ===================================
735 12:20:55.508681 LPDDR4 DRAM CONFIGURATION
736 12:20:55.512374 ===================================
737 12:20:55.515931 EX_ROW_EN[0] = 0x10
738 12:20:55.516015 EX_ROW_EN[1] = 0x0
739 12:20:55.519834 LP4Y_EN = 0x0
740 12:20:55.519917 WORK_FSP = 0x0
741 12:20:55.523299 WL = 0x2
742 12:20:55.523382 RL = 0x2
743 12:20:55.526903 BL = 0x2
744 12:20:55.526987 RPST = 0x0
745 12:20:55.530564 RD_PRE = 0x0
746 12:20:55.530685 WR_PRE = 0x1
747 12:20:55.530751 WR_PST = 0x0
748 12:20:55.534637 DBI_WR = 0x0
749 12:20:55.534735 DBI_RD = 0x0
750 12:20:55.537953 OTF = 0x1
751 12:20:55.541724 ===================================
752 12:20:55.548623 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 12:20:55.552194 nWR fixed to 40
754 12:20:55.552278 [ModeRegInit_LP4] CH0 RK0
755 12:20:55.555976 [ModeRegInit_LP4] CH0 RK1
756 12:20:55.556060 [ModeRegInit_LP4] CH1 RK0
757 12:20:55.560018 [ModeRegInit_LP4] CH1 RK1
758 12:20:55.560101 match AC timing 13
759 12:20:55.567531 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 12:20:55.570426 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 12:20:55.574025 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 12:20:55.580708 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 12:20:55.584239 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 12:20:55.584327 [EMI DOE] emi_dcm 0
765 12:20:55.591076 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 12:20:55.591160 ==
767 12:20:55.594300 Dram Type= 6, Freq= 0, CH_0, rank 0
768 12:20:55.597586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 12:20:55.597670 ==
770 12:20:55.604338 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 12:20:55.607976 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 12:20:55.618420 [CA 0] Center 37 (7~68) winsize 62
773 12:20:55.621780 [CA 1] Center 36 (6~67) winsize 62
774 12:20:55.624802 [CA 2] Center 34 (4~65) winsize 62
775 12:20:55.628459 [CA 3] Center 34 (4~65) winsize 62
776 12:20:55.631849 [CA 4] Center 33 (3~64) winsize 62
777 12:20:55.635425 [CA 5] Center 33 (3~64) winsize 62
778 12:20:55.635509
779 12:20:55.638930 [CmdBusTrainingLP45] Vref(ca) range 1: 32
780 12:20:55.639014
781 12:20:55.641877 [CATrainingPosCal] consider 1 rank data
782 12:20:55.645294 u2DelayCellTimex100 = 270/100 ps
783 12:20:55.649159 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
784 12:20:55.652168 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
785 12:20:55.655426 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
786 12:20:55.658712 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
787 12:20:55.665726 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
788 12:20:55.668523 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
789 12:20:55.668607
790 12:20:55.671751 CA PerBit enable=1, Macro0, CA PI delay=33
791 12:20:55.671835
792 12:20:55.675236 [CBTSetCACLKResult] CA Dly = 33
793 12:20:55.675319 CS Dly: 6 (0~37)
794 12:20:55.675385 ==
795 12:20:55.678470 Dram Type= 6, Freq= 0, CH_0, rank 1
796 12:20:55.685365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 12:20:55.685459 ==
798 12:20:55.689018 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 12:20:55.695273 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 12:20:55.704070 [CA 0] Center 37 (6~68) winsize 63
801 12:20:55.707530 [CA 1] Center 37 (7~68) winsize 62
802 12:20:55.710935 [CA 2] Center 34 (4~65) winsize 62
803 12:20:55.714492 [CA 3] Center 34 (4~65) winsize 62
804 12:20:55.717434 [CA 4] Center 33 (3~64) winsize 62
805 12:20:55.721100 [CA 5] Center 33 (2~64) winsize 63
806 12:20:55.721184
807 12:20:55.724657 [CmdBusTrainingLP45] Vref(ca) range 1: 34
808 12:20:55.724740
809 12:20:55.727300 [CATrainingPosCal] consider 2 rank data
810 12:20:55.730881 u2DelayCellTimex100 = 270/100 ps
811 12:20:55.734204 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
812 12:20:55.741192 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
813 12:20:55.743926 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
814 12:20:55.747706 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
815 12:20:55.751873 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
816 12:20:55.755637 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
817 12:20:55.755723
818 12:20:55.758751 CA PerBit enable=1, Macro0, CA PI delay=33
819 12:20:55.758834
820 12:20:55.762821 [CBTSetCACLKResult] CA Dly = 33
821 12:20:55.762905 CS Dly: 6 (0~38)
822 12:20:55.762970
823 12:20:55.766354 ----->DramcWriteLeveling(PI) begin...
824 12:20:55.766439 ==
825 12:20:55.769993 Dram Type= 6, Freq= 0, CH_0, rank 0
826 12:20:55.773499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 12:20:55.773588 ==
828 12:20:55.776977 Write leveling (Byte 0): 33 => 33
829 12:20:55.781171 Write leveling (Byte 1): 31 => 31
830 12:20:55.783758 DramcWriteLeveling(PI) end<-----
831 12:20:55.783840
832 12:20:55.783906 ==
833 12:20:55.787214 Dram Type= 6, Freq= 0, CH_0, rank 0
834 12:20:55.790425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 12:20:55.790509 ==
836 12:20:55.793413 [Gating] SW mode calibration
837 12:20:55.800671 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 12:20:55.806782 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 12:20:55.810288 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 12:20:55.814137 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
841 12:20:55.820133 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
842 12:20:55.823623 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
843 12:20:55.826541 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 12:20:55.833175 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 12:20:55.836281 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 12:20:55.839689 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 12:20:55.846326 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 12:20:55.849794 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 12:20:55.853492 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 12:20:55.859416 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 12:20:55.862899 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 12:20:55.866338 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 12:20:55.872916 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 12:20:55.876375 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 12:20:55.880181 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 12:20:55.886537 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:20:55.889465 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
858 12:20:55.892638 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:20:55.899544 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:20:55.902641 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:20:55.905967 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:20:55.913257 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:20:55.915719 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:20:55.919631 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:20:55.925947 0 9 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
866 12:20:55.929108 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
867 12:20:55.932462 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 12:20:55.939642 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 12:20:55.942857 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 12:20:55.946128 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 12:20:55.949352 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 12:20:55.955972 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
873 12:20:55.959356 0 10 8 | B1->B0 | 3232 2e2e | 0 0 | (0 1) (0 0)
874 12:20:55.962543 0 10 12 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
875 12:20:55.969291 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 12:20:55.972269 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 12:20:55.975936 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 12:20:55.982362 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 12:20:55.985896 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 12:20:55.988757 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
881 12:20:55.996102 0 11 8 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
882 12:20:55.999750 0 11 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
883 12:20:56.003186 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 12:20:56.006465 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 12:20:56.013358 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 12:20:56.017340 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 12:20:56.020511 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 12:20:56.024552 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
889 12:20:56.032005 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
890 12:20:56.035360 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
891 12:20:56.038350 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 12:20:56.041998 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 12:20:56.049289 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 12:20:56.052799 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 12:20:56.056494 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 12:20:56.059576 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 12:20:56.066307 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 12:20:56.069639 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 12:20:56.073118 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 12:20:56.079717 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 12:20:56.082881 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 12:20:56.086243 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 12:20:56.093126 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 12:20:56.096388 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:20:56.099448 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
906 12:20:56.103666 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
907 12:20:56.107112 Total UI for P1: 0, mck2ui 16
908 12:20:56.110334 best dqsien dly found for B0: ( 0, 14, 8)
909 12:20:56.113829 Total UI for P1: 0, mck2ui 16
910 12:20:56.117171 best dqsien dly found for B1: ( 0, 14, 10)
911 12:20:56.121182 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
912 12:20:56.124934 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
913 12:20:56.125042
914 12:20:56.127883 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
915 12:20:56.131529 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
916 12:20:56.135346 [Gating] SW calibration Done
917 12:20:56.135423 ==
918 12:20:56.138874 Dram Type= 6, Freq= 0, CH_0, rank 0
919 12:20:56.142579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 12:20:56.142700 ==
921 12:20:56.145982 RX Vref Scan: 0
922 12:20:56.146065
923 12:20:56.146130 RX Vref 0 -> 0, step: 1
924 12:20:56.146190
925 12:20:56.148910 RX Delay -130 -> 252, step: 16
926 12:20:56.152703 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
927 12:20:56.159627 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
928 12:20:56.162545 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
929 12:20:56.166075 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
930 12:20:56.169120 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
931 12:20:56.172747 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
932 12:20:56.178930 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
933 12:20:56.182373 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
934 12:20:56.185919 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
935 12:20:56.189103 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
936 12:20:56.192608 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
937 12:20:56.199260 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
938 12:20:56.202659 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
939 12:20:56.205938 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
940 12:20:56.209008 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
941 12:20:56.215407 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
942 12:20:56.215490 ==
943 12:20:56.218554 Dram Type= 6, Freq= 0, CH_0, rank 0
944 12:20:56.221986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
945 12:20:56.222069 ==
946 12:20:56.222134 DQS Delay:
947 12:20:56.225448 DQS0 = 0, DQS1 = 0
948 12:20:56.225530 DQM Delay:
949 12:20:56.228958 DQM0 = 86, DQM1 = 70
950 12:20:56.229041 DQ Delay:
951 12:20:56.231888 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
952 12:20:56.235322 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
953 12:20:56.238877 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
954 12:20:56.241751 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
955 12:20:56.241833
956 12:20:56.241897
957 12:20:56.241957 ==
958 12:20:56.245508 Dram Type= 6, Freq= 0, CH_0, rank 0
959 12:20:56.248641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 12:20:56.248724 ==
961 12:20:56.248790
962 12:20:56.251743
963 12:20:56.251826 TX Vref Scan disable
964 12:20:56.255486 == TX Byte 0 ==
965 12:20:56.258789 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
966 12:20:56.261697 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
967 12:20:56.265270 == TX Byte 1 ==
968 12:20:56.268107 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
969 12:20:56.271409 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
970 12:20:56.271492 ==
971 12:20:56.275210 Dram Type= 6, Freq= 0, CH_0, rank 0
972 12:20:56.281746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 12:20:56.281829 ==
974 12:20:56.293381 TX Vref=22, minBit 5, minWin=27, winSum=446
975 12:20:56.296864 TX Vref=24, minBit 4, minWin=27, winSum=445
976 12:20:56.300389 TX Vref=26, minBit 8, minWin=27, winSum=445
977 12:20:56.303541 TX Vref=28, minBit 10, minWin=27, winSum=448
978 12:20:56.306905 TX Vref=30, minBit 10, minWin=27, winSum=448
979 12:20:56.313736 TX Vref=32, minBit 10, minWin=27, winSum=447
980 12:20:56.316662 [TxChooseVref] Worse bit 10, Min win 27, Win sum 448, Final Vref 28
981 12:20:56.316746
982 12:20:56.320112 Final TX Range 1 Vref 28
983 12:20:56.320195
984 12:20:56.320261 ==
985 12:20:56.323481 Dram Type= 6, Freq= 0, CH_0, rank 0
986 12:20:56.327045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 12:20:56.330345 ==
988 12:20:56.330428
989 12:20:56.330493
990 12:20:56.330554 TX Vref Scan disable
991 12:20:56.333845 == TX Byte 0 ==
992 12:20:56.336850 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
993 12:20:56.343895 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
994 12:20:56.343979 == TX Byte 1 ==
995 12:20:56.346997 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
996 12:20:56.353879 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
997 12:20:56.353962
998 12:20:56.354028 [DATLAT]
999 12:20:56.354130 Freq=800, CH0 RK0
1000 12:20:56.354189
1001 12:20:56.356892 DATLAT Default: 0xa
1002 12:20:56.356975 0, 0xFFFF, sum = 0
1003 12:20:56.360090 1, 0xFFFF, sum = 0
1004 12:20:56.363708 2, 0xFFFF, sum = 0
1005 12:20:56.363792 3, 0xFFFF, sum = 0
1006 12:20:56.366872 4, 0xFFFF, sum = 0
1007 12:20:56.366956 5, 0xFFFF, sum = 0
1008 12:20:56.369966 6, 0xFFFF, sum = 0
1009 12:20:56.370050 7, 0xFFFF, sum = 0
1010 12:20:56.373802 8, 0xFFFF, sum = 0
1011 12:20:56.373887 9, 0x0, sum = 1
1012 12:20:56.376667 10, 0x0, sum = 2
1013 12:20:56.376751 11, 0x0, sum = 3
1014 12:20:56.376818 12, 0x0, sum = 4
1015 12:20:56.380129 best_step = 10
1016 12:20:56.380212
1017 12:20:56.380281 ==
1018 12:20:56.383538 Dram Type= 6, Freq= 0, CH_0, rank 0
1019 12:20:56.386762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1020 12:20:56.386846 ==
1021 12:20:56.390378 RX Vref Scan: 1
1022 12:20:56.390461
1023 12:20:56.390527 Set Vref Range= 32 -> 127
1024 12:20:56.393600
1025 12:20:56.393689 RX Vref 32 -> 127, step: 1
1026 12:20:56.393755
1027 12:20:56.396626 RX Delay -111 -> 252, step: 8
1028 12:20:56.396709
1029 12:20:56.399962 Set Vref, RX VrefLevel [Byte0]: 32
1030 12:20:56.403126 [Byte1]: 32
1031 12:20:56.406407
1032 12:20:56.406487 Set Vref, RX VrefLevel [Byte0]: 33
1033 12:20:56.410122 [Byte1]: 33
1034 12:20:56.414486
1035 12:20:56.414567 Set Vref, RX VrefLevel [Byte0]: 34
1036 12:20:56.417929 [Byte1]: 34
1037 12:20:56.421749
1038 12:20:56.421830 Set Vref, RX VrefLevel [Byte0]: 35
1039 12:20:56.425748 [Byte1]: 35
1040 12:20:56.429276
1041 12:20:56.429357 Set Vref, RX VrefLevel [Byte0]: 36
1042 12:20:56.432916 [Byte1]: 36
1043 12:20:56.437520
1044 12:20:56.440594 Set Vref, RX VrefLevel [Byte0]: 37
1045 12:20:56.440676 [Byte1]: 37
1046 12:20:56.445376
1047 12:20:56.445457 Set Vref, RX VrefLevel [Byte0]: 38
1048 12:20:56.447878 [Byte1]: 38
1049 12:20:56.452597
1050 12:20:56.452679 Set Vref, RX VrefLevel [Byte0]: 39
1051 12:20:56.455895 [Byte1]: 39
1052 12:20:56.460392
1053 12:20:56.460473 Set Vref, RX VrefLevel [Byte0]: 40
1054 12:20:56.463327 [Byte1]: 40
1055 12:20:56.468078
1056 12:20:56.468159 Set Vref, RX VrefLevel [Byte0]: 41
1057 12:20:56.471333 [Byte1]: 41
1058 12:20:56.475394
1059 12:20:56.475475 Set Vref, RX VrefLevel [Byte0]: 42
1060 12:20:56.479166 [Byte1]: 42
1061 12:20:56.483135
1062 12:20:56.483216 Set Vref, RX VrefLevel [Byte0]: 43
1063 12:20:56.486330 [Byte1]: 43
1064 12:20:56.490851
1065 12:20:56.490932 Set Vref, RX VrefLevel [Byte0]: 44
1066 12:20:56.493942 [Byte1]: 44
1067 12:20:56.498141
1068 12:20:56.498222 Set Vref, RX VrefLevel [Byte0]: 45
1069 12:20:56.501394 [Byte1]: 45
1070 12:20:56.506159
1071 12:20:56.506240 Set Vref, RX VrefLevel [Byte0]: 46
1072 12:20:56.509141 [Byte1]: 46
1073 12:20:56.513363
1074 12:20:56.513445 Set Vref, RX VrefLevel [Byte0]: 47
1075 12:20:56.516772 [Byte1]: 47
1076 12:20:56.521047
1077 12:20:56.521128 Set Vref, RX VrefLevel [Byte0]: 48
1078 12:20:56.524595 [Byte1]: 48
1079 12:20:56.528648
1080 12:20:56.528729 Set Vref, RX VrefLevel [Byte0]: 49
1081 12:20:56.535308 [Byte1]: 49
1082 12:20:56.535390
1083 12:20:56.538612 Set Vref, RX VrefLevel [Byte0]: 50
1084 12:20:56.542411 [Byte1]: 50
1085 12:20:56.542510
1086 12:20:56.545088 Set Vref, RX VrefLevel [Byte0]: 51
1087 12:20:56.548904 [Byte1]: 51
1088 12:20:56.551928
1089 12:20:56.552010 Set Vref, RX VrefLevel [Byte0]: 52
1090 12:20:56.554922 [Byte1]: 52
1091 12:20:56.559570
1092 12:20:56.559652 Set Vref, RX VrefLevel [Byte0]: 53
1093 12:20:56.563294 [Byte1]: 53
1094 12:20:56.566981
1095 12:20:56.567063 Set Vref, RX VrefLevel [Byte0]: 54
1096 12:20:56.570589 [Byte1]: 54
1097 12:20:56.574622
1098 12:20:56.574719 Set Vref, RX VrefLevel [Byte0]: 55
1099 12:20:56.578204 [Byte1]: 55
1100 12:20:56.582195
1101 12:20:56.582276 Set Vref, RX VrefLevel [Byte0]: 56
1102 12:20:56.585760 [Byte1]: 56
1103 12:20:56.589821
1104 12:20:56.589903 Set Vref, RX VrefLevel [Byte0]: 57
1105 12:20:56.593496 [Byte1]: 57
1106 12:20:56.597943
1107 12:20:56.598024 Set Vref, RX VrefLevel [Byte0]: 58
1108 12:20:56.601085 [Byte1]: 58
1109 12:20:56.605761
1110 12:20:56.605843 Set Vref, RX VrefLevel [Byte0]: 59
1111 12:20:56.608839 [Byte1]: 59
1112 12:20:56.613380
1113 12:20:56.613462 Set Vref, RX VrefLevel [Byte0]: 60
1114 12:20:56.616392 [Byte1]: 60
1115 12:20:56.621049
1116 12:20:56.621131 Set Vref, RX VrefLevel [Byte0]: 61
1117 12:20:56.624551 [Byte1]: 61
1118 12:20:56.628658
1119 12:20:56.628738 Set Vref, RX VrefLevel [Byte0]: 62
1120 12:20:56.631588 [Byte1]: 62
1121 12:20:56.635986
1122 12:20:56.636093 Set Vref, RX VrefLevel [Byte0]: 63
1123 12:20:56.639366 [Byte1]: 63
1124 12:20:56.644121
1125 12:20:56.644224 Set Vref, RX VrefLevel [Byte0]: 64
1126 12:20:56.647286 [Byte1]: 64
1127 12:20:56.651652
1128 12:20:56.651733 Set Vref, RX VrefLevel [Byte0]: 65
1129 12:20:56.654569 [Byte1]: 65
1130 12:20:56.659249
1131 12:20:56.659331 Set Vref, RX VrefLevel [Byte0]: 66
1132 12:20:56.662432 [Byte1]: 66
1133 12:20:56.667376
1134 12:20:56.667458 Set Vref, RX VrefLevel [Byte0]: 67
1135 12:20:56.670932 [Byte1]: 67
1136 12:20:56.674551
1137 12:20:56.674684 Set Vref, RX VrefLevel [Byte0]: 68
1138 12:20:56.678029 [Byte1]: 68
1139 12:20:56.682299
1140 12:20:56.682406 Set Vref, RX VrefLevel [Byte0]: 69
1141 12:20:56.685195 [Byte1]: 69
1142 12:20:56.689454
1143 12:20:56.689535 Set Vref, RX VrefLevel [Byte0]: 70
1144 12:20:56.692578 [Byte1]: 70
1145 12:20:56.697421
1146 12:20:56.697503 Set Vref, RX VrefLevel [Byte0]: 71
1147 12:20:56.700603 [Byte1]: 71
1148 12:20:56.704789
1149 12:20:56.704869 Set Vref, RX VrefLevel [Byte0]: 72
1150 12:20:56.708353 [Byte1]: 72
1151 12:20:56.712587
1152 12:20:56.712669 Set Vref, RX VrefLevel [Byte0]: 73
1153 12:20:56.716187 [Byte1]: 73
1154 12:20:56.720401
1155 12:20:56.720483 Set Vref, RX VrefLevel [Byte0]: 74
1156 12:20:56.723543 [Byte1]: 74
1157 12:20:56.728270
1158 12:20:56.728352 Set Vref, RX VrefLevel [Byte0]: 75
1159 12:20:56.731952 [Byte1]: 75
1160 12:20:56.735428
1161 12:20:56.735509 Set Vref, RX VrefLevel [Byte0]: 76
1162 12:20:56.739048 [Byte1]: 76
1163 12:20:56.743325
1164 12:20:56.743407 Set Vref, RX VrefLevel [Byte0]: 77
1165 12:20:56.747055 [Byte1]: 77
1166 12:20:56.751050
1167 12:20:56.751132 Set Vref, RX VrefLevel [Byte0]: 78
1168 12:20:56.754528 [Byte1]: 78
1169 12:20:56.758999
1170 12:20:56.759081 Set Vref, RX VrefLevel [Byte0]: 79
1171 12:20:56.762114 [Byte1]: 79
1172 12:20:56.766005
1173 12:20:56.766087 Set Vref, RX VrefLevel [Byte0]: 80
1174 12:20:56.769118 [Byte1]: 80
1175 12:20:56.773524
1176 12:20:56.773606 Set Vref, RX VrefLevel [Byte0]: 81
1177 12:20:56.776897 [Byte1]: 81
1178 12:20:56.781364
1179 12:20:56.781446 Set Vref, RX VrefLevel [Byte0]: 82
1180 12:20:56.784525 [Byte1]: 82
1181 12:20:56.789203
1182 12:20:56.789285 Set Vref, RX VrefLevel [Byte0]: 83
1183 12:20:56.792303 [Byte1]: 83
1184 12:20:56.796906
1185 12:20:56.796988 Final RX Vref Byte 0 = 66 to rank0
1186 12:20:56.800300 Final RX Vref Byte 1 = 57 to rank0
1187 12:20:56.803678 Final RX Vref Byte 0 = 66 to rank1
1188 12:20:56.807161 Final RX Vref Byte 1 = 57 to rank1==
1189 12:20:56.811072 Dram Type= 6, Freq= 0, CH_0, rank 0
1190 12:20:56.814641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1191 12:20:56.814726 ==
1192 12:20:56.817845 DQS Delay:
1193 12:20:56.817926 DQS0 = 0, DQS1 = 0
1194 12:20:56.817992 DQM Delay:
1195 12:20:56.821918 DQM0 = 87, DQM1 = 75
1196 12:20:56.822000 DQ Delay:
1197 12:20:56.824875 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1198 12:20:56.828566 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1199 12:20:56.832696 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1200 12:20:56.836031 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1201 12:20:56.836113
1202 12:20:56.836178
1203 12:20:56.843675 [DQSOSCAuto] RK0, (LSB)MR18= 0x4829, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
1204 12:20:56.847371 CH0 RK0: MR19=606, MR18=4829
1205 12:20:56.850954 CH0_RK0: MR19=0x606, MR18=0x4829, DQSOSC=391, MR23=63, INC=96, DEC=64
1206 12:20:56.851062
1207 12:20:56.854523 ----->DramcWriteLeveling(PI) begin...
1208 12:20:56.854663 ==
1209 12:20:56.858140 Dram Type= 6, Freq= 0, CH_0, rank 1
1210 12:20:56.865238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1211 12:20:56.865321 ==
1212 12:20:56.865387 Write leveling (Byte 0): 34 => 34
1213 12:20:56.909273 Write leveling (Byte 1): 30 => 30
1214 12:20:56.909541 DramcWriteLeveling(PI) end<-----
1215 12:20:56.909614
1216 12:20:56.909676 ==
1217 12:20:56.909737 Dram Type= 6, Freq= 0, CH_0, rank 1
1218 12:20:56.909807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1219 12:20:56.909872 ==
1220 12:20:56.909929 [Gating] SW mode calibration
1221 12:20:56.910404 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1222 12:20:56.910656 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1223 12:20:56.910727 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1224 12:20:56.910791 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1225 12:20:56.911032 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1226 12:20:56.953015 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:20:56.953101 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:20:56.953168 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:20:56.953411 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:20:56.953838 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 12:20:56.954307 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:20:56.955061 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 12:20:56.955143 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 12:20:56.955391 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 12:20:56.955468 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 12:20:56.979615 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 12:20:56.979886 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 12:20:56.979958 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 12:20:56.980655 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 12:20:56.980737 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 12:20:56.983920 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1242 12:20:56.987625 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 12:20:56.987707 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 12:20:56.991029 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 12:20:56.995058 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 12:20:57.002081 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 12:20:57.006261 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 12:20:57.009817 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 12:20:57.013158 0 9 8 | B1->B0 | 2322 2c2c | 1 0 | (0 0) (0 0)
1250 12:20:57.016832 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1251 12:20:57.023585 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 12:20:57.027259 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 12:20:57.030480 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 12:20:57.034357 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 12:20:57.041701 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1256 12:20:57.045453 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1257 12:20:57.049158 0 10 8 | B1->B0 | 2f2f 2a2a | 0 0 | (1 0) (0 0)
1258 12:20:57.052873 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1259 12:20:57.056194 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 12:20:57.063355 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 12:20:57.067071 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 12:20:57.070630 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 12:20:57.074219 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 12:20:57.081160 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1265 12:20:57.085003 0 11 8 | B1->B0 | 3030 3838 | 1 0 | (1 1) (0 0)
1266 12:20:57.088534 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1267 12:20:57.092130 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 12:20:57.099433 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 12:20:57.102799 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 12:20:57.106857 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 12:20:57.110122 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 12:20:57.116837 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 12:20:57.119846 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 12:20:57.123316 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1275 12:20:57.129626 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 12:20:57.133066 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 12:20:57.136785 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 12:20:57.139911 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 12:20:57.146507 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 12:20:57.149597 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 12:20:57.153105 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 12:20:57.159829 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 12:20:57.163492 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 12:20:57.166746 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 12:20:57.172853 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 12:20:57.176069 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 12:20:57.180324 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 12:20:57.186272 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 12:20:57.189853 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1290 12:20:57.192853 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1291 12:20:57.196227 Total UI for P1: 0, mck2ui 16
1292 12:20:57.199487 best dqsien dly found for B0: ( 0, 14, 8)
1293 12:20:57.203047 Total UI for P1: 0, mck2ui 16
1294 12:20:57.206144 best dqsien dly found for B1: ( 0, 14, 10)
1295 12:20:57.209380 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1296 12:20:57.212986 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1297 12:20:57.213068
1298 12:20:57.219337 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1299 12:20:57.222693 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1300 12:20:57.226360 [Gating] SW calibration Done
1301 12:20:57.226442 ==
1302 12:20:57.229480 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 12:20:57.232361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 12:20:57.232447 ==
1305 12:20:57.232512 RX Vref Scan: 0
1306 12:20:57.232574
1307 12:20:57.235982 RX Vref 0 -> 0, step: 1
1308 12:20:57.236065
1309 12:20:57.239135 RX Delay -130 -> 252, step: 16
1310 12:20:57.242504 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1311 12:20:57.245727 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1312 12:20:57.252276 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1313 12:20:57.256517 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1314 12:20:57.259183 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1315 12:20:57.262255 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1316 12:20:57.265928 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1317 12:20:57.273153 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1318 12:20:57.275976 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1319 12:20:57.279338 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1320 12:20:57.282833 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1321 12:20:57.286063 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1322 12:20:57.292867 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1323 12:20:57.295613 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1324 12:20:57.298809 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1325 12:20:57.302109 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1326 12:20:57.302191 ==
1327 12:20:57.305575 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 12:20:57.311885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 12:20:57.311968 ==
1330 12:20:57.312033 DQS Delay:
1331 12:20:57.315295 DQS0 = 0, DQS1 = 0
1332 12:20:57.315377 DQM Delay:
1333 12:20:57.315441 DQM0 = 84, DQM1 = 78
1334 12:20:57.319005 DQ Delay:
1335 12:20:57.321902 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1336 12:20:57.325395 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1337 12:20:57.329225 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1338 12:20:57.332120 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1339 12:20:57.332201
1340 12:20:57.332266
1341 12:20:57.332325 ==
1342 12:20:57.335447 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 12:20:57.338640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 12:20:57.338723 ==
1345 12:20:57.338788
1346 12:20:57.338848
1347 12:20:57.342121 TX Vref Scan disable
1348 12:20:57.345129 == TX Byte 0 ==
1349 12:20:57.348707 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1350 12:20:57.351763 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1351 12:20:57.355094 == TX Byte 1 ==
1352 12:20:57.358541 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1353 12:20:57.361945 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1354 12:20:57.362027 ==
1355 12:20:57.365149 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 12:20:57.368789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 12:20:57.368871 ==
1358 12:20:57.383301 TX Vref=22, minBit 8, minWin=27, winSum=443
1359 12:20:57.386354 TX Vref=24, minBit 3, minWin=27, winSum=443
1360 12:20:57.389848 TX Vref=26, minBit 4, minWin=27, winSum=445
1361 12:20:57.393252 TX Vref=28, minBit 9, minWin=27, winSum=447
1362 12:20:57.396577 TX Vref=30, minBit 0, minWin=28, winSum=448
1363 12:20:57.403299 TX Vref=32, minBit 8, minWin=27, winSum=445
1364 12:20:57.406746 [TxChooseVref] Worse bit 0, Min win 28, Win sum 448, Final Vref 30
1365 12:20:57.406828
1366 12:20:57.409528 Final TX Range 1 Vref 30
1367 12:20:57.409609
1368 12:20:57.409674 ==
1369 12:20:57.412639 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 12:20:57.416193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 12:20:57.419727 ==
1372 12:20:57.419808
1373 12:20:57.419871
1374 12:20:57.419929 TX Vref Scan disable
1375 12:20:57.423473 == TX Byte 0 ==
1376 12:20:57.426518 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1377 12:20:57.430048 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1378 12:20:57.433229 == TX Byte 1 ==
1379 12:20:57.436331 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1380 12:20:57.442890 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1381 12:20:57.442971
1382 12:20:57.443034 [DATLAT]
1383 12:20:57.443093 Freq=800, CH0 RK1
1384 12:20:57.443150
1385 12:20:57.446773 DATLAT Default: 0xa
1386 12:20:57.446853 0, 0xFFFF, sum = 0
1387 12:20:57.449954 1, 0xFFFF, sum = 0
1388 12:20:57.450039 2, 0xFFFF, sum = 0
1389 12:20:57.453225 3, 0xFFFF, sum = 0
1390 12:20:57.456168 4, 0xFFFF, sum = 0
1391 12:20:57.456250 5, 0xFFFF, sum = 0
1392 12:20:57.459960 6, 0xFFFF, sum = 0
1393 12:20:57.460042 7, 0xFFFF, sum = 0
1394 12:20:57.462875 8, 0xFFFF, sum = 0
1395 12:20:57.462957 9, 0x0, sum = 1
1396 12:20:57.466566 10, 0x0, sum = 2
1397 12:20:57.466655 11, 0x0, sum = 3
1398 12:20:57.466723 12, 0x0, sum = 4
1399 12:20:57.470087 best_step = 10
1400 12:20:57.470168
1401 12:20:57.470233 ==
1402 12:20:57.472698 Dram Type= 6, Freq= 0, CH_0, rank 1
1403 12:20:57.476324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 12:20:57.476407 ==
1405 12:20:57.479242 RX Vref Scan: 0
1406 12:20:57.479324
1407 12:20:57.479389 RX Vref 0 -> 0, step: 1
1408 12:20:57.482738
1409 12:20:57.482818 RX Delay -95 -> 252, step: 8
1410 12:20:57.489687 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1411 12:20:57.492991 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1412 12:20:57.496323 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1413 12:20:57.500127 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1414 12:20:57.503380 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1415 12:20:57.509471 iDelay=217, Bit 5, Center 72 (-47 ~ 192) 240
1416 12:20:57.513222 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1417 12:20:57.516184 iDelay=217, Bit 7, Center 100 (-15 ~ 216) 232
1418 12:20:57.519537 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1419 12:20:57.526186 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1420 12:20:57.529715 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
1421 12:20:57.532863 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1422 12:20:57.536573 iDelay=217, Bit 12, Center 80 (-39 ~ 200) 240
1423 12:20:57.539491 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1424 12:20:57.545870 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1425 12:20:57.549296 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1426 12:20:57.549379 ==
1427 12:20:57.552785 Dram Type= 6, Freq= 0, CH_0, rank 1
1428 12:20:57.555910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1429 12:20:57.555992 ==
1430 12:20:57.559056 DQS Delay:
1431 12:20:57.559137 DQS0 = 0, DQS1 = 0
1432 12:20:57.559202 DQM Delay:
1433 12:20:57.562432 DQM0 = 85, DQM1 = 77
1434 12:20:57.562513 DQ Delay:
1435 12:20:57.565635 DQ0 =84, DQ1 =92, DQ2 =76, DQ3 =84
1436 12:20:57.569184 DQ4 =84, DQ5 =72, DQ6 =92, DQ7 =100
1437 12:20:57.572286 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1438 12:20:57.575665 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =84
1439 12:20:57.575747
1440 12:20:57.575812
1441 12:20:57.585342 [DQSOSCAuto] RK1, (LSB)MR18= 0x4107, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1442 12:20:57.588815 CH0 RK1: MR19=606, MR18=4107
1443 12:20:57.592285 CH0_RK1: MR19=0x606, MR18=0x4107, DQSOSC=393, MR23=63, INC=95, DEC=63
1444 12:20:57.595342 [RxdqsGatingPostProcess] freq 800
1445 12:20:57.601890 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1446 12:20:57.605221 Pre-setting of DQS Precalculation
1447 12:20:57.608724 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1448 12:20:57.611947 ==
1449 12:20:57.615406 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 12:20:57.618945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 12:20:57.619027 ==
1452 12:20:57.622014 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1453 12:20:57.628747 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1454 12:20:57.638558 [CA 0] Center 36 (6~67) winsize 62
1455 12:20:57.641807 [CA 1] Center 36 (6~67) winsize 62
1456 12:20:57.644935 [CA 2] Center 34 (4~65) winsize 62
1457 12:20:57.648550 [CA 3] Center 34 (3~65) winsize 63
1458 12:20:57.651455 [CA 4] Center 34 (4~65) winsize 62
1459 12:20:57.654614 [CA 5] Center 34 (3~65) winsize 63
1460 12:20:57.654716
1461 12:20:57.659038 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1462 12:20:57.659118
1463 12:20:57.661505 [CATrainingPosCal] consider 1 rank data
1464 12:20:57.665118 u2DelayCellTimex100 = 270/100 ps
1465 12:20:57.667898 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1466 12:20:57.674774 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1467 12:20:57.678055 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1468 12:20:57.681548 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1469 12:20:57.684889 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1470 12:20:57.687868 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1471 12:20:57.687949
1472 12:20:57.691486 CA PerBit enable=1, Macro0, CA PI delay=34
1473 12:20:57.691568
1474 12:20:57.694514 [CBTSetCACLKResult] CA Dly = 34
1475 12:20:57.697598 CS Dly: 4 (0~35)
1476 12:20:57.697680 ==
1477 12:20:57.701620 Dram Type= 6, Freq= 0, CH_1, rank 1
1478 12:20:57.704582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1479 12:20:57.704668 ==
1480 12:20:57.711234 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1481 12:20:57.714213 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1482 12:20:57.724414 [CA 0] Center 36 (6~67) winsize 62
1483 12:20:57.727920 [CA 1] Center 36 (6~67) winsize 62
1484 12:20:57.731603 [CA 2] Center 34 (4~65) winsize 62
1485 12:20:57.734617 [CA 3] Center 34 (3~65) winsize 63
1486 12:20:57.738092 [CA 4] Center 34 (4~65) winsize 62
1487 12:20:57.741579 [CA 5] Center 34 (4~65) winsize 62
1488 12:20:57.741660
1489 12:20:57.744934 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1490 12:20:57.745015
1491 12:20:57.747648 [CATrainingPosCal] consider 2 rank data
1492 12:20:57.751247 u2DelayCellTimex100 = 270/100 ps
1493 12:20:57.754208 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1494 12:20:57.761481 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1495 12:20:57.764481 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1496 12:20:57.767773 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1497 12:20:57.771366 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1498 12:20:57.774176 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1499 12:20:57.774257
1500 12:20:57.777619 CA PerBit enable=1, Macro0, CA PI delay=34
1501 12:20:57.777701
1502 12:20:57.781317 [CBTSetCACLKResult] CA Dly = 34
1503 12:20:57.781398 CS Dly: 5 (0~38)
1504 12:20:57.781462
1505 12:20:57.784262 ----->DramcWriteLeveling(PI) begin...
1506 12:20:57.787628 ==
1507 12:20:57.790971 Dram Type= 6, Freq= 0, CH_1, rank 0
1508 12:20:57.794144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1509 12:20:57.794226 ==
1510 12:20:57.797472 Write leveling (Byte 0): 27 => 27
1511 12:20:57.800700 Write leveling (Byte 1): 28 => 28
1512 12:20:57.804575 DramcWriteLeveling(PI) end<-----
1513 12:20:57.804657
1514 12:20:57.804721 ==
1515 12:20:57.807787 Dram Type= 6, Freq= 0, CH_1, rank 0
1516 12:20:57.810484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1517 12:20:57.810566 ==
1518 12:20:57.813956 [Gating] SW mode calibration
1519 12:20:57.820848 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1520 12:20:57.827420 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1521 12:20:57.830972 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1522 12:20:57.833846 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1523 12:20:57.840580 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1524 12:20:57.844038 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 12:20:57.847304 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 12:20:57.853688 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 12:20:57.857040 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 12:20:57.860344 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 12:20:57.867127 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 12:20:57.870519 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 12:20:57.873854 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 12:20:57.877124 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 12:20:57.883886 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 12:20:57.887227 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 12:20:57.890469 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 12:20:57.896879 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 12:20:57.900447 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1538 12:20:57.903562 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1539 12:20:57.910554 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 12:20:57.913697 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 12:20:57.917006 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 12:20:57.923629 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 12:20:57.926992 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 12:20:57.930431 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 12:20:57.936979 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 12:20:57.940162 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 12:20:57.943227 0 9 8 | B1->B0 | 2b2b 3333 | 0 1 | (0 0) (1 1)
1548 12:20:57.950060 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 12:20:57.953033 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 12:20:57.956415 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 12:20:57.963457 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 12:20:57.966571 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 12:20:57.969760 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1554 12:20:57.976529 0 10 4 | B1->B0 | 3333 3333 | 0 0 | (1 0) (0 1)
1555 12:20:57.979875 0 10 8 | B1->B0 | 2e2e 2727 | 1 1 | (1 0) (0 0)
1556 12:20:57.983362 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 12:20:57.989748 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 12:20:57.993884 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 12:20:57.996689 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 12:20:58.002862 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 12:20:58.005991 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 12:20:58.009477 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
1563 12:20:58.016245 0 11 8 | B1->B0 | 3737 4444 | 0 0 | (0 0) (0 0)
1564 12:20:58.019383 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 12:20:58.022895 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 12:20:58.029193 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 12:20:58.032856 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 12:20:58.036042 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 12:20:58.042856 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 12:20:58.046006 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1571 12:20:58.049127 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1572 12:20:58.056102 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 12:20:58.059437 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 12:20:58.062567 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 12:20:58.069437 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 12:20:58.072413 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 12:20:58.076299 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 12:20:58.082530 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 12:20:58.086023 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 12:20:58.089134 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 12:20:58.092274 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 12:20:58.099340 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 12:20:58.102645 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 12:20:58.105819 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 12:20:58.111928 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 12:20:58.115626 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1587 12:20:58.118868 Total UI for P1: 0, mck2ui 16
1588 12:20:58.122170 best dqsien dly found for B0: ( 0, 14, 2)
1589 12:20:58.125619 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1590 12:20:58.128862 Total UI for P1: 0, mck2ui 16
1591 12:20:58.131932 best dqsien dly found for B1: ( 0, 14, 4)
1592 12:20:58.135302 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1593 12:20:58.139039 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1594 12:20:58.142296
1595 12:20:58.145539 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1596 12:20:58.149265 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1597 12:20:58.151936 [Gating] SW calibration Done
1598 12:20:58.152043 ==
1599 12:20:58.155356 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 12:20:58.158562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 12:20:58.158658 ==
1602 12:20:58.158725 RX Vref Scan: 0
1603 12:20:58.158785
1604 12:20:58.162180 RX Vref 0 -> 0, step: 1
1605 12:20:58.162290
1606 12:20:58.165576 RX Delay -130 -> 252, step: 16
1607 12:20:58.168896 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1608 12:20:58.172022 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1609 12:20:58.178538 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1610 12:20:58.181934 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1611 12:20:58.185417 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1612 12:20:58.188223 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1613 12:20:58.191575 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1614 12:20:58.198309 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1615 12:20:58.202109 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1616 12:20:58.204702 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1617 12:20:58.208183 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1618 12:20:58.211736 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1619 12:20:58.218276 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1620 12:20:58.221274 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1621 12:20:58.224511 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1622 12:20:58.227871 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1623 12:20:58.231546 ==
1624 12:20:58.231628 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 12:20:58.238298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 12:20:58.238381 ==
1627 12:20:58.238446 DQS Delay:
1628 12:20:58.241078 DQS0 = 0, DQS1 = 0
1629 12:20:58.241160 DQM Delay:
1630 12:20:58.244331 DQM0 = 89, DQM1 = 78
1631 12:20:58.244413 DQ Delay:
1632 12:20:58.247607 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1633 12:20:58.250979 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1634 12:20:58.254948 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1635 12:20:58.257909 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1636 12:20:58.257990
1637 12:20:58.258054
1638 12:20:58.258113 ==
1639 12:20:58.260802 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 12:20:58.264513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 12:20:58.264595 ==
1642 12:20:58.264660
1643 12:20:58.264720
1644 12:20:58.268002 TX Vref Scan disable
1645 12:20:58.271252 == TX Byte 0 ==
1646 12:20:58.274392 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1647 12:20:58.278137 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1648 12:20:58.280855 == TX Byte 1 ==
1649 12:20:58.283998 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1650 12:20:58.287510 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1651 12:20:58.287592 ==
1652 12:20:58.290994 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 12:20:58.297437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 12:20:58.297519 ==
1655 12:20:58.309034 TX Vref=22, minBit 13, minWin=26, winSum=442
1656 12:20:58.312421 TX Vref=24, minBit 8, minWin=27, winSum=447
1657 12:20:58.315657 TX Vref=26, minBit 9, minWin=27, winSum=452
1658 12:20:58.319737 TX Vref=28, minBit 2, minWin=28, winSum=454
1659 12:20:58.322475 TX Vref=30, minBit 15, minWin=27, winSum=453
1660 12:20:58.329246 TX Vref=32, minBit 9, minWin=27, winSum=446
1661 12:20:58.332489 [TxChooseVref] Worse bit 2, Min win 28, Win sum 454, Final Vref 28
1662 12:20:58.332572
1663 12:20:58.336036 Final TX Range 1 Vref 28
1664 12:20:58.336118
1665 12:20:58.336199 ==
1666 12:20:58.338858 Dram Type= 6, Freq= 0, CH_1, rank 0
1667 12:20:58.342768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1668 12:20:58.346012 ==
1669 12:20:58.346093
1670 12:20:58.346157
1671 12:20:58.346217 TX Vref Scan disable
1672 12:20:58.349135 == TX Byte 0 ==
1673 12:20:58.352535 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1674 12:20:58.359175 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1675 12:20:58.359261 == TX Byte 1 ==
1676 12:20:58.362213 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1677 12:20:58.368785 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1678 12:20:58.368867
1679 12:20:58.368932 [DATLAT]
1680 12:20:58.368991 Freq=800, CH1 RK0
1681 12:20:58.369049
1682 12:20:58.372371 DATLAT Default: 0xa
1683 12:20:58.372453 0, 0xFFFF, sum = 0
1684 12:20:58.375972 1, 0xFFFF, sum = 0
1685 12:20:58.376055 2, 0xFFFF, sum = 0
1686 12:20:58.379040 3, 0xFFFF, sum = 0
1687 12:20:58.381960 4, 0xFFFF, sum = 0
1688 12:20:58.382042 5, 0xFFFF, sum = 0
1689 12:20:58.385257 6, 0xFFFF, sum = 0
1690 12:20:58.385340 7, 0xFFFF, sum = 0
1691 12:20:58.388907 8, 0xFFFF, sum = 0
1692 12:20:58.388990 9, 0x0, sum = 1
1693 12:20:58.392206 10, 0x0, sum = 2
1694 12:20:58.392289 11, 0x0, sum = 3
1695 12:20:58.392356 12, 0x0, sum = 4
1696 12:20:58.395481 best_step = 10
1697 12:20:58.395563
1698 12:20:58.395627 ==
1699 12:20:58.398554 Dram Type= 6, Freq= 0, CH_1, rank 0
1700 12:20:58.402009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1701 12:20:58.402091 ==
1702 12:20:58.405501 RX Vref Scan: 1
1703 12:20:58.405582
1704 12:20:58.409023 Set Vref Range= 32 -> 127
1705 12:20:58.409105
1706 12:20:58.409169 RX Vref 32 -> 127, step: 1
1707 12:20:58.409230
1708 12:20:58.412722 RX Delay -95 -> 252, step: 8
1709 12:20:58.412803
1710 12:20:58.415468 Set Vref, RX VrefLevel [Byte0]: 32
1711 12:20:58.418961 [Byte1]: 32
1712 12:20:58.419043
1713 12:20:58.422095 Set Vref, RX VrefLevel [Byte0]: 33
1714 12:20:58.425305 [Byte1]: 33
1715 12:20:58.429381
1716 12:20:58.429462 Set Vref, RX VrefLevel [Byte0]: 34
1717 12:20:58.432458 [Byte1]: 34
1718 12:20:58.437141
1719 12:20:58.437222 Set Vref, RX VrefLevel [Byte0]: 35
1720 12:20:58.439991 [Byte1]: 35
1721 12:20:58.444819
1722 12:20:58.444900 Set Vref, RX VrefLevel [Byte0]: 36
1723 12:20:58.448052 [Byte1]: 36
1724 12:20:58.452244
1725 12:20:58.452352 Set Vref, RX VrefLevel [Byte0]: 37
1726 12:20:58.455282 [Byte1]: 37
1727 12:20:58.459983
1728 12:20:58.460064 Set Vref, RX VrefLevel [Byte0]: 38
1729 12:20:58.462900 [Byte1]: 38
1730 12:20:58.467683
1731 12:20:58.467764 Set Vref, RX VrefLevel [Byte0]: 39
1732 12:20:58.470643 [Byte1]: 39
1733 12:20:58.474881
1734 12:20:58.474963 Set Vref, RX VrefLevel [Byte0]: 40
1735 12:20:58.478250 [Byte1]: 40
1736 12:20:58.482582
1737 12:20:58.482685 Set Vref, RX VrefLevel [Byte0]: 41
1738 12:20:58.485963 [Byte1]: 41
1739 12:20:58.490235
1740 12:20:58.490316 Set Vref, RX VrefLevel [Byte0]: 42
1741 12:20:58.493490 [Byte1]: 42
1742 12:20:58.497793
1743 12:20:58.497874 Set Vref, RX VrefLevel [Byte0]: 43
1744 12:20:58.500814 [Byte1]: 43
1745 12:20:58.505309
1746 12:20:58.505391 Set Vref, RX VrefLevel [Byte0]: 44
1747 12:20:58.508780 [Byte1]: 44
1748 12:20:58.513022
1749 12:20:58.513107 Set Vref, RX VrefLevel [Byte0]: 45
1750 12:20:58.516002 [Byte1]: 45
1751 12:20:58.520406
1752 12:20:58.520488 Set Vref, RX VrefLevel [Byte0]: 46
1753 12:20:58.524072 [Byte1]: 46
1754 12:20:58.528122
1755 12:20:58.528203 Set Vref, RX VrefLevel [Byte0]: 47
1756 12:20:58.531340 [Byte1]: 47
1757 12:20:58.535736
1758 12:20:58.535844 Set Vref, RX VrefLevel [Byte0]: 48
1759 12:20:58.538913 [Byte1]: 48
1760 12:20:58.543148
1761 12:20:58.543230 Set Vref, RX VrefLevel [Byte0]: 49
1762 12:20:58.547300 [Byte1]: 49
1763 12:20:58.551488
1764 12:20:58.551569 Set Vref, RX VrefLevel [Byte0]: 50
1765 12:20:58.554296 [Byte1]: 50
1766 12:20:58.558790
1767 12:20:58.558871 Set Vref, RX VrefLevel [Byte0]: 51
1768 12:20:58.561695 [Byte1]: 51
1769 12:20:58.566239
1770 12:20:58.566320 Set Vref, RX VrefLevel [Byte0]: 52
1771 12:20:58.569591 [Byte1]: 52
1772 12:20:58.573731
1773 12:20:58.573812 Set Vref, RX VrefLevel [Byte0]: 53
1774 12:20:58.577140 [Byte1]: 53
1775 12:20:58.581611
1776 12:20:58.581692 Set Vref, RX VrefLevel [Byte0]: 54
1777 12:20:58.584778 [Byte1]: 54
1778 12:20:58.589073
1779 12:20:58.589154 Set Vref, RX VrefLevel [Byte0]: 55
1780 12:20:58.592293 [Byte1]: 55
1781 12:20:58.596854
1782 12:20:58.596964 Set Vref, RX VrefLevel [Byte0]: 56
1783 12:20:58.599900 [Byte1]: 56
1784 12:20:58.603902
1785 12:20:58.603976 Set Vref, RX VrefLevel [Byte0]: 57
1786 12:20:58.607743 [Byte1]: 57
1787 12:20:58.611856
1788 12:20:58.611959 Set Vref, RX VrefLevel [Byte0]: 58
1789 12:20:58.615484 [Byte1]: 58
1790 12:20:58.619309
1791 12:20:58.619381 Set Vref, RX VrefLevel [Byte0]: 59
1792 12:20:58.622770 [Byte1]: 59
1793 12:20:58.626728
1794 12:20:58.626834 Set Vref, RX VrefLevel [Byte0]: 60
1795 12:20:58.630232 [Byte1]: 60
1796 12:20:58.634433
1797 12:20:58.637844 Set Vref, RX VrefLevel [Byte0]: 61
1798 12:20:58.637948 [Byte1]: 61
1799 12:20:58.642253
1800 12:20:58.642353 Set Vref, RX VrefLevel [Byte0]: 62
1801 12:20:58.645202 [Byte1]: 62
1802 12:20:58.649845
1803 12:20:58.649951 Set Vref, RX VrefLevel [Byte0]: 63
1804 12:20:58.652900 [Byte1]: 63
1805 12:20:58.657098
1806 12:20:58.657201 Set Vref, RX VrefLevel [Byte0]: 64
1807 12:20:58.660615 [Byte1]: 64
1808 12:20:58.665018
1809 12:20:58.665127 Set Vref, RX VrefLevel [Byte0]: 65
1810 12:20:58.668206 [Byte1]: 65
1811 12:20:58.672563
1812 12:20:58.672667 Set Vref, RX VrefLevel [Byte0]: 66
1813 12:20:58.675429 [Byte1]: 66
1814 12:20:58.680033
1815 12:20:58.680133 Set Vref, RX VrefLevel [Byte0]: 67
1816 12:20:58.683499 [Byte1]: 67
1817 12:20:58.687863
1818 12:20:58.687961 Set Vref, RX VrefLevel [Byte0]: 68
1819 12:20:58.691040 [Byte1]: 68
1820 12:20:58.695348
1821 12:20:58.695447 Set Vref, RX VrefLevel [Byte0]: 69
1822 12:20:58.699046 [Byte1]: 69
1823 12:20:58.702686
1824 12:20:58.702761 Set Vref, RX VrefLevel [Byte0]: 70
1825 12:20:58.706118 [Byte1]: 70
1826 12:20:58.710313
1827 12:20:58.710413 Set Vref, RX VrefLevel [Byte0]: 71
1828 12:20:58.713602 [Byte1]: 71
1829 12:20:58.718303
1830 12:20:58.718405 Set Vref, RX VrefLevel [Byte0]: 72
1831 12:20:58.721202 [Byte1]: 72
1832 12:20:58.725596
1833 12:20:58.725696 Set Vref, RX VrefLevel [Byte0]: 73
1834 12:20:58.728722 [Byte1]: 73
1835 12:20:58.733448
1836 12:20:58.733548 Set Vref, RX VrefLevel [Byte0]: 74
1837 12:20:58.736512 [Byte1]: 74
1838 12:20:58.740751
1839 12:20:58.740855 Final RX Vref Byte 0 = 54 to rank0
1840 12:20:58.744201 Final RX Vref Byte 1 = 63 to rank0
1841 12:20:58.747560 Final RX Vref Byte 0 = 54 to rank1
1842 12:20:58.750748 Final RX Vref Byte 1 = 63 to rank1==
1843 12:20:58.754176 Dram Type= 6, Freq= 0, CH_1, rank 0
1844 12:20:58.760394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1845 12:20:58.760472 ==
1846 12:20:58.760540 DQS Delay:
1847 12:20:58.764472 DQS0 = 0, DQS1 = 0
1848 12:20:58.764568 DQM Delay:
1849 12:20:58.764659 DQM0 = 86, DQM1 = 79
1850 12:20:58.767605 DQ Delay:
1851 12:20:58.770764 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1852 12:20:58.774702 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =80
1853 12:20:58.777226 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1854 12:20:58.780629 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1855 12:20:58.780729
1856 12:20:58.780818
1857 12:20:58.787456 [DQSOSCAuto] RK0, (LSB)MR18= 0x3723, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 395 ps
1858 12:20:58.790641 CH1 RK0: MR19=606, MR18=3723
1859 12:20:58.796899 CH1_RK0: MR19=0x606, MR18=0x3723, DQSOSC=395, MR23=63, INC=94, DEC=63
1860 12:20:58.797000
1861 12:20:58.800552 ----->DramcWriteLeveling(PI) begin...
1862 12:20:58.800651 ==
1863 12:20:58.803752 Dram Type= 6, Freq= 0, CH_1, rank 1
1864 12:20:58.807188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1865 12:20:58.807266 ==
1866 12:20:58.810344 Write leveling (Byte 0): 28 => 28
1867 12:20:58.813410 Write leveling (Byte 1): 28 => 28
1868 12:20:58.816802 DramcWriteLeveling(PI) end<-----
1869 12:20:58.816904
1870 12:20:58.816993 ==
1871 12:20:58.820346 Dram Type= 6, Freq= 0, CH_1, rank 1
1872 12:20:58.823655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1873 12:20:58.823756 ==
1874 12:20:58.826710 [Gating] SW mode calibration
1875 12:20:58.833926 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1876 12:20:58.840293 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1877 12:20:58.843445 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1878 12:20:58.850254 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1879 12:20:58.853270 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 12:20:58.857022 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 12:20:58.863278 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 12:20:58.866693 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 12:20:58.870197 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 12:20:58.876611 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 12:20:58.880067 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 12:20:58.883175 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 12:20:58.886515 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 12:20:58.893316 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 12:20:58.896583 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 12:20:58.900033 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 12:20:58.906453 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 12:20:58.909824 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 12:20:58.912953 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 12:20:58.920095 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1895 12:20:58.923216 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1896 12:20:58.926728 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 12:20:58.932926 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 12:20:58.936294 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 12:20:58.939873 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 12:20:58.946635 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 12:20:58.949409 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 12:20:58.952778 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 12:20:58.959535 0 9 8 | B1->B0 | 3030 2c2c | 1 1 | (1 1) (1 1)
1904 12:20:58.963057 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 12:20:58.966249 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 12:20:58.972451 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 12:20:58.976067 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 12:20:58.979186 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 12:20:58.985848 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 12:20:58.989111 0 10 4 | B1->B0 | 3131 3434 | 0 1 | (1 0) (1 1)
1911 12:20:58.992933 0 10 8 | B1->B0 | 2626 2e2e | 0 0 | (0 0) (0 0)
1912 12:20:58.999015 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 12:20:59.002390 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 12:20:59.005952 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 12:20:59.012561 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 12:20:59.015875 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 12:20:59.018839 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 12:20:59.025765 0 11 4 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1919 12:20:59.029028 0 11 8 | B1->B0 | 4242 3434 | 1 1 | (0 0) (0 0)
1920 12:20:59.032209 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 12:20:59.039047 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 12:20:59.042524 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 12:20:59.045891 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 12:20:59.052256 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 12:20:59.055216 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 12:20:59.058939 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 12:20:59.066201 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1928 12:20:59.068833 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 12:20:59.072232 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 12:20:59.078574 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 12:20:59.082057 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 12:20:59.085251 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 12:20:59.089004 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 12:20:59.095239 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 12:20:59.098562 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 12:20:59.102210 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 12:20:59.108813 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 12:20:59.111917 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 12:20:59.115816 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 12:20:59.121816 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 12:20:59.125595 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 12:20:59.128614 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 12:20:59.135571 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1944 12:20:59.135668 Total UI for P1: 0, mck2ui 16
1945 12:20:59.142697 best dqsien dly found for B1: ( 0, 14, 6)
1946 12:20:59.145387 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1947 12:20:59.148531 Total UI for P1: 0, mck2ui 16
1948 12:20:59.151837 best dqsien dly found for B0: ( 0, 14, 8)
1949 12:20:59.155392 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1950 12:20:59.158939 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1951 12:20:59.159034
1952 12:20:59.162106 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1953 12:20:59.164987 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1954 12:20:59.168711 [Gating] SW calibration Done
1955 12:20:59.168806 ==
1956 12:20:59.172000 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 12:20:59.175053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 12:20:59.179292 ==
1959 12:20:59.179422 RX Vref Scan: 0
1960 12:20:59.179514
1961 12:20:59.181865 RX Vref 0 -> 0, step: 1
1962 12:20:59.181947
1963 12:20:59.185004 RX Delay -130 -> 252, step: 16
1964 12:20:59.188500 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1965 12:20:59.191429 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1966 12:20:59.194798 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1967 12:20:59.197957 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1968 12:20:59.204880 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1969 12:20:59.207943 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1970 12:20:59.211797 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1971 12:20:59.215152 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1972 12:20:59.217992 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1973 12:20:59.225379 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1974 12:20:59.227870 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1975 12:20:59.231082 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1976 12:20:59.234783 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1977 12:20:59.241502 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1978 12:20:59.244906 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1979 12:20:59.247604 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1980 12:20:59.247702 ==
1981 12:20:59.250870 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 12:20:59.254704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 12:20:59.254806 ==
1984 12:20:59.257705 DQS Delay:
1985 12:20:59.257778 DQS0 = 0, DQS1 = 0
1986 12:20:59.261101 DQM Delay:
1987 12:20:59.261206 DQM0 = 86, DQM1 = 78
1988 12:20:59.261295 DQ Delay:
1989 12:20:59.264425 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =77
1990 12:20:59.267731 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1991 12:20:59.271275 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1992 12:20:59.274205 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1993 12:20:59.274301
1994 12:20:59.277549
1995 12:20:59.277654 ==
1996 12:20:59.280880 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 12:20:59.284782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 12:20:59.284882 ==
1999 12:20:59.284983
2000 12:20:59.285070
2001 12:20:59.287203 TX Vref Scan disable
2002 12:20:59.287299 == TX Byte 0 ==
2003 12:20:59.294216 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2004 12:20:59.297129 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2005 12:20:59.297236 == TX Byte 1 ==
2006 12:20:59.304162 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2007 12:20:59.307048 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2008 12:20:59.307146 ==
2009 12:20:59.310777 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 12:20:59.314000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 12:20:59.314070 ==
2012 12:20:59.327251 TX Vref=22, minBit 9, minWin=27, winSum=444
2013 12:20:59.330936 TX Vref=24, minBit 10, minWin=27, winSum=447
2014 12:20:59.334275 TX Vref=26, minBit 13, minWin=27, winSum=450
2015 12:20:59.337478 TX Vref=28, minBit 10, minWin=27, winSum=451
2016 12:20:59.340628 TX Vref=30, minBit 8, minWin=27, winSum=447
2017 12:20:59.347583 TX Vref=32, minBit 8, minWin=27, winSum=448
2018 12:20:59.350528 [TxChooseVref] Worse bit 10, Min win 27, Win sum 451, Final Vref 28
2019 12:20:59.350630
2020 12:20:59.353868 Final TX Range 1 Vref 28
2021 12:20:59.353937
2022 12:20:59.354010 ==
2023 12:20:59.357308 Dram Type= 6, Freq= 0, CH_1, rank 1
2024 12:20:59.360551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2025 12:20:59.363972 ==
2026 12:20:59.364050
2027 12:20:59.364112
2028 12:20:59.364170 TX Vref Scan disable
2029 12:20:59.367659 == TX Byte 0 ==
2030 12:20:59.370970 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2031 12:20:59.377766 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2032 12:20:59.377841 == TX Byte 1 ==
2033 12:20:59.380935 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2034 12:20:59.387680 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2035 12:20:59.387795
2036 12:20:59.387858 [DATLAT]
2037 12:20:59.387916 Freq=800, CH1 RK1
2038 12:20:59.387974
2039 12:20:59.391185 DATLAT Default: 0xa
2040 12:20:59.391259 0, 0xFFFF, sum = 0
2041 12:20:59.394233 1, 0xFFFF, sum = 0
2042 12:20:59.397469 2, 0xFFFF, sum = 0
2043 12:20:59.397542 3, 0xFFFF, sum = 0
2044 12:20:59.400734 4, 0xFFFF, sum = 0
2045 12:20:59.400804 5, 0xFFFF, sum = 0
2046 12:20:59.404438 6, 0xFFFF, sum = 0
2047 12:20:59.404534 7, 0xFFFF, sum = 0
2048 12:20:59.407634 8, 0xFFFF, sum = 0
2049 12:20:59.407705 9, 0x0, sum = 1
2050 12:20:59.410684 10, 0x0, sum = 2
2051 12:20:59.410781 11, 0x0, sum = 3
2052 12:20:59.410872 12, 0x0, sum = 4
2053 12:20:59.414382 best_step = 10
2054 12:20:59.414478
2055 12:20:59.414565 ==
2056 12:20:59.417438 Dram Type= 6, Freq= 0, CH_1, rank 1
2057 12:20:59.420913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2058 12:20:59.420983 ==
2059 12:20:59.424148 RX Vref Scan: 0
2060 12:20:59.424242
2061 12:20:59.424331 RX Vref 0 -> 0, step: 1
2062 12:20:59.427262
2063 12:20:59.427335 RX Delay -111 -> 252, step: 8
2064 12:20:59.434518 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
2065 12:20:59.438487 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2066 12:20:59.440949 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2067 12:20:59.444348 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2068 12:20:59.447901 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2069 12:20:59.454291 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2070 12:20:59.457829 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2071 12:20:59.461534 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2072 12:20:59.464442 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2073 12:20:59.467594 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2074 12:20:59.474103 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2075 12:20:59.477976 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2076 12:20:59.481222 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2077 12:20:59.484233 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2078 12:20:59.490880 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2079 12:20:59.494168 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2080 12:20:59.494244 ==
2081 12:20:59.497553 Dram Type= 6, Freq= 0, CH_1, rank 1
2082 12:20:59.500782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2083 12:20:59.500887 ==
2084 12:20:59.500979 DQS Delay:
2085 12:20:59.504368 DQS0 = 0, DQS1 = 0
2086 12:20:59.504464 DQM Delay:
2087 12:20:59.508022 DQM0 = 86, DQM1 = 78
2088 12:20:59.508118 DQ Delay:
2089 12:20:59.511001 DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =84
2090 12:20:59.514047 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2091 12:20:59.517429 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
2092 12:20:59.520862 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2093 12:20:59.520958
2094 12:20:59.521048
2095 12:20:59.530959 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2096 12:20:59.531036 CH1 RK1: MR19=606, MR18=1B13
2097 12:20:59.537589 CH1_RK1: MR19=0x606, MR18=0x1B13, DQSOSC=403, MR23=63, INC=90, DEC=60
2098 12:20:59.540705 [RxdqsGatingPostProcess] freq 800
2099 12:20:59.547274 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2100 12:20:59.550981 Pre-setting of DQS Precalculation
2101 12:20:59.553634 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2102 12:20:59.560479 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2103 12:20:59.570211 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2104 12:20:59.570310
2105 12:20:59.570400
2106 12:20:59.573543 [Calibration Summary] 1600 Mbps
2107 12:20:59.573636 CH 0, Rank 0
2108 12:20:59.576845 SW Impedance : PASS
2109 12:20:59.576943 DUTY Scan : NO K
2110 12:20:59.580267 ZQ Calibration : PASS
2111 12:20:59.583415 Jitter Meter : NO K
2112 12:20:59.583497 CBT Training : PASS
2113 12:20:59.587098 Write leveling : PASS
2114 12:20:59.590518 RX DQS gating : PASS
2115 12:20:59.590657 RX DQ/DQS(RDDQC) : PASS
2116 12:20:59.594092 TX DQ/DQS : PASS
2117 12:20:59.594173 RX DATLAT : PASS
2118 12:20:59.597091 RX DQ/DQS(Engine): PASS
2119 12:20:59.600219 TX OE : NO K
2120 12:20:59.600298 All Pass.
2121 12:20:59.600361
2122 12:20:59.600419 CH 0, Rank 1
2123 12:20:59.603568 SW Impedance : PASS
2124 12:20:59.606929 DUTY Scan : NO K
2125 12:20:59.607009 ZQ Calibration : PASS
2126 12:20:59.610298 Jitter Meter : NO K
2127 12:20:59.613491 CBT Training : PASS
2128 12:20:59.613571 Write leveling : PASS
2129 12:20:59.616755 RX DQS gating : PASS
2130 12:20:59.620392 RX DQ/DQS(RDDQC) : PASS
2131 12:20:59.620471 TX DQ/DQS : PASS
2132 12:20:59.623502 RX DATLAT : PASS
2133 12:20:59.626571 RX DQ/DQS(Engine): PASS
2134 12:20:59.626663 TX OE : NO K
2135 12:20:59.630260 All Pass.
2136 12:20:59.630339
2137 12:20:59.630410 CH 1, Rank 0
2138 12:20:59.633374 SW Impedance : PASS
2139 12:20:59.633465 DUTY Scan : NO K
2140 12:20:59.636826 ZQ Calibration : PASS
2141 12:20:59.640198 Jitter Meter : NO K
2142 12:20:59.640278 CBT Training : PASS
2143 12:20:59.643326 Write leveling : PASS
2144 12:20:59.646966 RX DQS gating : PASS
2145 12:20:59.647046 RX DQ/DQS(RDDQC) : PASS
2146 12:20:59.649888 TX DQ/DQS : PASS
2147 12:20:59.649968 RX DATLAT : PASS
2148 12:20:59.653305 RX DQ/DQS(Engine): PASS
2149 12:20:59.656839 TX OE : NO K
2150 12:20:59.656919 All Pass.
2151 12:20:59.656982
2152 12:20:59.657039 CH 1, Rank 1
2153 12:20:59.660064 SW Impedance : PASS
2154 12:20:59.663343 DUTY Scan : NO K
2155 12:20:59.663423 ZQ Calibration : PASS
2156 12:20:59.666694 Jitter Meter : NO K
2157 12:20:59.670056 CBT Training : PASS
2158 12:20:59.670158 Write leveling : PASS
2159 12:20:59.673157 RX DQS gating : PASS
2160 12:20:59.677127 RX DQ/DQS(RDDQC) : PASS
2161 12:20:59.677225 TX DQ/DQS : PASS
2162 12:20:59.680004 RX DATLAT : PASS
2163 12:20:59.683151 RX DQ/DQS(Engine): PASS
2164 12:20:59.683228 TX OE : NO K
2165 12:20:59.686480 All Pass.
2166 12:20:59.686580
2167 12:20:59.686684 DramC Write-DBI off
2168 12:20:59.689657 PER_BANK_REFRESH: Hybrid Mode
2169 12:20:59.689755 TX_TRACKING: ON
2170 12:20:59.693188 [GetDramInforAfterCalByMRR] Vendor 6.
2171 12:20:59.700790 [GetDramInforAfterCalByMRR] Revision 606.
2172 12:20:59.703680 [GetDramInforAfterCalByMRR] Revision 2 0.
2173 12:20:59.703760 MR0 0x3b3b
2174 12:20:59.703828 MR8 0x5151
2175 12:20:59.706213 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2176 12:20:59.709816
2177 12:20:59.709902 MR0 0x3b3b
2178 12:20:59.709966 MR8 0x5151
2179 12:20:59.712763 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2180 12:20:59.712844
2181 12:20:59.722802 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2182 12:20:59.726465 [FAST_K] Save calibration result to emmc
2183 12:20:59.729884 [FAST_K] Save calibration result to emmc
2184 12:20:59.732947 dram_init: config_dvfs: 1
2185 12:20:59.736693 dramc_set_vcore_voltage set vcore to 662500
2186 12:20:59.739791 Read voltage for 1200, 2
2187 12:20:59.739907 Vio18 = 0
2188 12:20:59.739984 Vcore = 662500
2189 12:20:59.742811 Vdram = 0
2190 12:20:59.742891 Vddq = 0
2191 12:20:59.742954 Vmddr = 0
2192 12:20:59.750395 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2193 12:20:59.752817 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2194 12:20:59.756898 MEM_TYPE=3, freq_sel=15
2195 12:20:59.759617 sv_algorithm_assistance_LP4_1600
2196 12:20:59.762583 ============ PULL DRAM RESETB DOWN ============
2197 12:20:59.765808 ========== PULL DRAM RESETB DOWN end =========
2198 12:20:59.772405 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2199 12:20:59.776265 ===================================
2200 12:20:59.779764 LPDDR4 DRAM CONFIGURATION
2201 12:20:59.782909 ===================================
2202 12:20:59.782990 EX_ROW_EN[0] = 0x0
2203 12:20:59.785787 EX_ROW_EN[1] = 0x0
2204 12:20:59.785867 LP4Y_EN = 0x0
2205 12:20:59.789294 WORK_FSP = 0x0
2206 12:20:59.789374 WL = 0x4
2207 12:20:59.792332 RL = 0x4
2208 12:20:59.792412 BL = 0x2
2209 12:20:59.795740 RPST = 0x0
2210 12:20:59.795821 RD_PRE = 0x0
2211 12:20:59.799131 WR_PRE = 0x1
2212 12:20:59.799213 WR_PST = 0x0
2213 12:20:59.801982 DBI_WR = 0x0
2214 12:20:59.802105 DBI_RD = 0x0
2215 12:20:59.805595 OTF = 0x1
2216 12:20:59.808595 ===================================
2217 12:20:59.812450 ===================================
2218 12:20:59.812522 ANA top config
2219 12:20:59.815489 ===================================
2220 12:20:59.818908 DLL_ASYNC_EN = 0
2221 12:20:59.822425 ALL_SLAVE_EN = 0
2222 12:20:59.825269 NEW_RANK_MODE = 1
2223 12:20:59.828826 DLL_IDLE_MODE = 1
2224 12:20:59.828922 LP45_APHY_COMB_EN = 1
2225 12:20:59.832576 TX_ODT_DIS = 1
2226 12:20:59.835489 NEW_8X_MODE = 1
2227 12:20:59.838540 ===================================
2228 12:20:59.842151 ===================================
2229 12:20:59.845511 data_rate = 2400
2230 12:20:59.848617 CKR = 1
2231 12:20:59.848691 DQ_P2S_RATIO = 8
2232 12:20:59.852971 ===================================
2233 12:20:59.855530 CA_P2S_RATIO = 8
2234 12:20:59.858713 DQ_CA_OPEN = 0
2235 12:20:59.862511 DQ_SEMI_OPEN = 0
2236 12:20:59.865349 CA_SEMI_OPEN = 0
2237 12:20:59.868551 CA_FULL_RATE = 0
2238 12:20:59.868656 DQ_CKDIV4_EN = 0
2239 12:20:59.872082 CA_CKDIV4_EN = 0
2240 12:20:59.875415 CA_PREDIV_EN = 0
2241 12:20:59.878874 PH8_DLY = 17
2242 12:20:59.881835 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2243 12:20:59.885255 DQ_AAMCK_DIV = 4
2244 12:20:59.885358 CA_AAMCK_DIV = 4
2245 12:20:59.888714 CA_ADMCK_DIV = 4
2246 12:20:59.891995 DQ_TRACK_CA_EN = 0
2247 12:20:59.895361 CA_PICK = 1200
2248 12:20:59.898454 CA_MCKIO = 1200
2249 12:20:59.901780 MCKIO_SEMI = 0
2250 12:20:59.905337 PLL_FREQ = 2366
2251 12:20:59.905437 DQ_UI_PI_RATIO = 32
2252 12:20:59.908456 CA_UI_PI_RATIO = 0
2253 12:20:59.911673 ===================================
2254 12:20:59.914937 ===================================
2255 12:20:59.918276 memory_type:LPDDR4
2256 12:20:59.922188 GP_NUM : 10
2257 12:20:59.922319 SRAM_EN : 1
2258 12:20:59.925319 MD32_EN : 0
2259 12:20:59.928281 ===================================
2260 12:20:59.931803 [ANA_INIT] >>>>>>>>>>>>>>
2261 12:20:59.931877 <<<<<< [CONFIGURE PHASE]: ANA_TX
2262 12:20:59.935263 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2263 12:20:59.938273 ===================================
2264 12:20:59.942059 data_rate = 2400,PCW = 0X5b00
2265 12:20:59.944817 ===================================
2266 12:20:59.947928 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2267 12:20:59.954562 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2268 12:20:59.961913 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2269 12:20:59.964939 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2270 12:20:59.968163 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2271 12:20:59.971564 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2272 12:20:59.974502 [ANA_INIT] flow start
2273 12:20:59.974620 [ANA_INIT] PLL >>>>>>>>
2274 12:20:59.978119 [ANA_INIT] PLL <<<<<<<<
2275 12:20:59.981232 [ANA_INIT] MIDPI >>>>>>>>
2276 12:20:59.981304 [ANA_INIT] MIDPI <<<<<<<<
2277 12:20:59.984607 [ANA_INIT] DLL >>>>>>>>
2278 12:20:59.988133 [ANA_INIT] DLL <<<<<<<<
2279 12:20:59.988238 [ANA_INIT] flow end
2280 12:20:59.994503 ============ LP4 DIFF to SE enter ============
2281 12:20:59.998276 ============ LP4 DIFF to SE exit ============
2282 12:21:00.001463 [ANA_INIT] <<<<<<<<<<<<<
2283 12:21:00.004606 [Flow] Enable top DCM control >>>>>
2284 12:21:00.007888 [Flow] Enable top DCM control <<<<<
2285 12:21:00.007965 Enable DLL master slave shuffle
2286 12:21:00.014498 ==============================================================
2287 12:21:00.018179 Gating Mode config
2288 12:21:00.021060 ==============================================================
2289 12:21:00.024556 Config description:
2290 12:21:00.034343 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2291 12:21:00.041284 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2292 12:21:00.044873 SELPH_MODE 0: By rank 1: By Phase
2293 12:21:00.050996 ==============================================================
2294 12:21:00.054548 GAT_TRACK_EN = 1
2295 12:21:00.057673 RX_GATING_MODE = 2
2296 12:21:00.061116 RX_GATING_TRACK_MODE = 2
2297 12:21:00.064306 SELPH_MODE = 1
2298 12:21:00.064404 PICG_EARLY_EN = 1
2299 12:21:00.067868 VALID_LAT_VALUE = 1
2300 12:21:00.074413 ==============================================================
2301 12:21:00.077595 Enter into Gating configuration >>>>
2302 12:21:00.080869 Exit from Gating configuration <<<<
2303 12:21:00.084080 Enter into DVFS_PRE_config >>>>>
2304 12:21:00.094035 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2305 12:21:00.097395 Exit from DVFS_PRE_config <<<<<
2306 12:21:00.100562 Enter into PICG configuration >>>>
2307 12:21:00.104232 Exit from PICG configuration <<<<
2308 12:21:00.107538 [RX_INPUT] configuration >>>>>
2309 12:21:00.110418 [RX_INPUT] configuration <<<<<
2310 12:21:00.114133 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2311 12:21:00.120605 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2312 12:21:00.127231 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2313 12:21:00.134011 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2314 12:21:00.140198 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2315 12:21:00.147610 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2316 12:21:00.150114 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2317 12:21:00.153395 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2318 12:21:00.157254 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2319 12:21:00.163749 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2320 12:21:00.166952 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2321 12:21:00.170314 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2322 12:21:00.173475 ===================================
2323 12:21:00.176754 LPDDR4 DRAM CONFIGURATION
2324 12:21:00.180089 ===================================
2325 12:21:00.180190 EX_ROW_EN[0] = 0x0
2326 12:21:00.183349 EX_ROW_EN[1] = 0x0
2327 12:21:00.183454 LP4Y_EN = 0x0
2328 12:21:00.187098 WORK_FSP = 0x0
2329 12:21:00.187192 WL = 0x4
2330 12:21:00.190128 RL = 0x4
2331 12:21:00.193467 BL = 0x2
2332 12:21:00.193573 RPST = 0x0
2333 12:21:00.197107 RD_PRE = 0x0
2334 12:21:00.197210 WR_PRE = 0x1
2335 12:21:00.200525 WR_PST = 0x0
2336 12:21:00.200621 DBI_WR = 0x0
2337 12:21:00.203176 DBI_RD = 0x0
2338 12:21:00.203274 OTF = 0x1
2339 12:21:00.206842 ===================================
2340 12:21:00.210153 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2341 12:21:00.216451 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2342 12:21:00.220077 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2343 12:21:00.223347 ===================================
2344 12:21:00.226246 LPDDR4 DRAM CONFIGURATION
2345 12:21:00.229907 ===================================
2346 12:21:00.229986 EX_ROW_EN[0] = 0x10
2347 12:21:00.233303 EX_ROW_EN[1] = 0x0
2348 12:21:00.233401 LP4Y_EN = 0x0
2349 12:21:00.236261 WORK_FSP = 0x0
2350 12:21:00.236358 WL = 0x4
2351 12:21:00.240016 RL = 0x4
2352 12:21:00.242953 BL = 0x2
2353 12:21:00.243026 RPST = 0x0
2354 12:21:00.246319 RD_PRE = 0x0
2355 12:21:00.246417 WR_PRE = 0x1
2356 12:21:00.249917 WR_PST = 0x0
2357 12:21:00.250012 DBI_WR = 0x0
2358 12:21:00.252969 DBI_RD = 0x0
2359 12:21:00.253066 OTF = 0x1
2360 12:21:00.256206 ===================================
2361 12:21:00.262882 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2362 12:21:00.262964 ==
2363 12:21:00.265993 Dram Type= 6, Freq= 0, CH_0, rank 0
2364 12:21:00.269333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2365 12:21:00.269432 ==
2366 12:21:00.272419 [Duty_Offset_Calibration]
2367 12:21:00.276106 B0:1 B1:-1 CA:0
2368 12:21:00.276215
2369 12:21:00.279578 [DutyScan_Calibration_Flow] k_type=0
2370 12:21:00.287734
2371 12:21:00.287844 ==CLK 0==
2372 12:21:00.291229 Final CLK duty delay cell = 0
2373 12:21:00.294520 [0] MAX Duty = 5125%(X100), DQS PI = 24
2374 12:21:00.297371 [0] MIN Duty = 4875%(X100), DQS PI = 8
2375 12:21:00.297469 [0] AVG Duty = 5000%(X100)
2376 12:21:00.300849
2377 12:21:00.304450 CH0 CLK Duty spec in!! Max-Min= 250%
2378 12:21:00.307345 [DutyScan_Calibration_Flow] ====Done====
2379 12:21:00.307442
2380 12:21:00.310791 [DutyScan_Calibration_Flow] k_type=1
2381 12:21:00.324941
2382 12:21:00.325043 ==DQS 0 ==
2383 12:21:00.328396 Final DQS duty delay cell = -4
2384 12:21:00.331594 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2385 12:21:00.335612 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2386 12:21:00.338189 [-4] AVG Duty = 4968%(X100)
2387 12:21:00.338295
2388 12:21:00.338387 ==DQS 1 ==
2389 12:21:00.341824 Final DQS duty delay cell = -4
2390 12:21:00.345280 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2391 12:21:00.348317 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2392 12:21:00.352323 [-4] AVG Duty = 4938%(X100)
2393 12:21:00.352430
2394 12:21:00.354965 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2395 12:21:00.355071
2396 12:21:00.357940 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2397 12:21:00.362193 [DutyScan_Calibration_Flow] ====Done====
2398 12:21:00.362292
2399 12:21:00.365210 [DutyScan_Calibration_Flow] k_type=3
2400 12:21:00.382845
2401 12:21:00.382922 ==DQM 0 ==
2402 12:21:00.386317 Final DQM duty delay cell = 0
2403 12:21:00.389573 [0] MAX Duty = 5031%(X100), DQS PI = 16
2404 12:21:00.393623 [0] MIN Duty = 4875%(X100), DQS PI = 6
2405 12:21:00.396081 [0] AVG Duty = 4953%(X100)
2406 12:21:00.396153
2407 12:21:00.396216 ==DQM 1 ==
2408 12:21:00.399506 Final DQM duty delay cell = 4
2409 12:21:00.402813 [4] MAX Duty = 5187%(X100), DQS PI = 14
2410 12:21:00.406049 [4] MIN Duty = 5000%(X100), DQS PI = 22
2411 12:21:00.409574 [4] AVG Duty = 5093%(X100)
2412 12:21:00.409649
2413 12:21:00.413162 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2414 12:21:00.413261
2415 12:21:00.416290 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2416 12:21:00.419484 [DutyScan_Calibration_Flow] ====Done====
2417 12:21:00.419557
2418 12:21:00.422551 [DutyScan_Calibration_Flow] k_type=2
2419 12:21:00.438197
2420 12:21:00.438299 ==DQ 0 ==
2421 12:21:00.441515 Final DQ duty delay cell = -4
2422 12:21:00.444733 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2423 12:21:00.447885 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2424 12:21:00.451322 [-4] AVG Duty = 4969%(X100)
2425 12:21:00.451403
2426 12:21:00.451466 ==DQ 1 ==
2427 12:21:00.454599 Final DQ duty delay cell = -4
2428 12:21:00.457523 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2429 12:21:00.461195 [-4] MIN Duty = 4876%(X100), DQS PI = 40
2430 12:21:00.464546 [-4] AVG Duty = 4938%(X100)
2431 12:21:00.464651
2432 12:21:00.467786 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2433 12:21:00.467886
2434 12:21:00.471278 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2435 12:21:00.474322 [DutyScan_Calibration_Flow] ====Done====
2436 12:21:00.474404 ==
2437 12:21:00.477558 Dram Type= 6, Freq= 0, CH_1, rank 0
2438 12:21:00.481229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2439 12:21:00.481309 ==
2440 12:21:00.484577 [Duty_Offset_Calibration]
2441 12:21:00.484660 B0:-1 B1:1 CA:1
2442 12:21:00.487457
2443 12:21:00.490694 [DutyScan_Calibration_Flow] k_type=0
2444 12:21:00.499017
2445 12:21:00.499108 ==CLK 0==
2446 12:21:00.502007 Final CLK duty delay cell = 0
2447 12:21:00.505113 [0] MAX Duty = 5156%(X100), DQS PI = 20
2448 12:21:00.508912 [0] MIN Duty = 4969%(X100), DQS PI = 62
2449 12:21:00.512339 [0] AVG Duty = 5062%(X100)
2450 12:21:00.512420
2451 12:21:00.515936 CH1 CLK Duty spec in!! Max-Min= 187%
2452 12:21:00.519219 [DutyScan_Calibration_Flow] ====Done====
2453 12:21:00.519300
2454 12:21:00.521806 [DutyScan_Calibration_Flow] k_type=1
2455 12:21:00.538263
2456 12:21:00.538345 ==DQS 0 ==
2457 12:21:00.541606 Final DQS duty delay cell = 0
2458 12:21:00.544592 [0] MAX Duty = 5125%(X100), DQS PI = 16
2459 12:21:00.548352 [0] MIN Duty = 4938%(X100), DQS PI = 6
2460 12:21:00.548433 [0] AVG Duty = 5031%(X100)
2461 12:21:00.551198
2462 12:21:00.551278 ==DQS 1 ==
2463 12:21:00.554521 Final DQS duty delay cell = 0
2464 12:21:00.557654 [0] MAX Duty = 5094%(X100), DQS PI = 12
2465 12:21:00.561317 [0] MIN Duty = 4969%(X100), DQS PI = 58
2466 12:21:00.564695 [0] AVG Duty = 5031%(X100)
2467 12:21:00.564775
2468 12:21:00.567552 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2469 12:21:00.567633
2470 12:21:00.571077 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2471 12:21:00.574429 [DutyScan_Calibration_Flow] ====Done====
2472 12:21:00.574534
2473 12:21:00.577782 [DutyScan_Calibration_Flow] k_type=3
2474 12:21:00.593879
2475 12:21:00.593959 ==DQM 0 ==
2476 12:21:00.597151 Final DQM duty delay cell = -4
2477 12:21:00.600180 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2478 12:21:00.603750 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2479 12:21:00.606939 [-4] AVG Duty = 4969%(X100)
2480 12:21:00.607013
2481 12:21:00.607079 ==DQM 1 ==
2482 12:21:00.610569 Final DQM duty delay cell = 0
2483 12:21:00.613931 [0] MAX Duty = 5187%(X100), DQS PI = 4
2484 12:21:00.616694 [0] MIN Duty = 5000%(X100), DQS PI = 28
2485 12:21:00.620334 [0] AVG Duty = 5093%(X100)
2486 12:21:00.620413
2487 12:21:00.623328 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2488 12:21:00.623403
2489 12:21:00.626686 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2490 12:21:00.630622 [DutyScan_Calibration_Flow] ====Done====
2491 12:21:00.630699
2492 12:21:00.633516 [DutyScan_Calibration_Flow] k_type=2
2493 12:21:00.650364
2494 12:21:00.650467 ==DQ 0 ==
2495 12:21:00.654469 Final DQ duty delay cell = 0
2496 12:21:00.656976 [0] MAX Duty = 5187%(X100), DQS PI = 30
2497 12:21:00.660674 [0] MIN Duty = 4907%(X100), DQS PI = 8
2498 12:21:00.660772 [0] AVG Duty = 5047%(X100)
2499 12:21:00.660861
2500 12:21:00.663900 ==DQ 1 ==
2501 12:21:00.666901 Final DQ duty delay cell = 0
2502 12:21:00.670599 [0] MAX Duty = 5093%(X100), DQS PI = 8
2503 12:21:00.673815 [0] MIN Duty = 4969%(X100), DQS PI = 0
2504 12:21:00.673928 [0] AVG Duty = 5031%(X100)
2505 12:21:00.674021
2506 12:21:00.677148 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2507 12:21:00.677249
2508 12:21:00.680426 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2509 12:21:00.687310 [DutyScan_Calibration_Flow] ====Done====
2510 12:21:00.691059 nWR fixed to 30
2511 12:21:00.691248 [ModeRegInit_LP4] CH0 RK0
2512 12:21:00.693668 [ModeRegInit_LP4] CH0 RK1
2513 12:21:00.697297 [ModeRegInit_LP4] CH1 RK0
2514 12:21:00.697402 [ModeRegInit_LP4] CH1 RK1
2515 12:21:00.700444 match AC timing 7
2516 12:21:00.703730 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2517 12:21:00.707504 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2518 12:21:00.713510 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2519 12:21:00.717008 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2520 12:21:00.723761 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2521 12:21:00.723863 ==
2522 12:21:00.726951 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 12:21:00.730128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 12:21:00.730229 ==
2525 12:21:00.737101 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2526 12:21:00.740088 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2527 12:21:00.750139 [CA 0] Center 39 (9~70) winsize 62
2528 12:21:00.753644 [CA 1] Center 39 (9~69) winsize 61
2529 12:21:00.756916 [CA 2] Center 35 (5~66) winsize 62
2530 12:21:00.760078 [CA 3] Center 35 (5~66) winsize 62
2531 12:21:00.763522 [CA 4] Center 33 (4~63) winsize 60
2532 12:21:00.767100 [CA 5] Center 33 (3~63) winsize 61
2533 12:21:00.767201
2534 12:21:00.769904 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2535 12:21:00.770006
2536 12:21:00.773285 [CATrainingPosCal] consider 1 rank data
2537 12:21:00.776656 u2DelayCellTimex100 = 270/100 ps
2538 12:21:00.779723 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2539 12:21:00.786572 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2540 12:21:00.789745 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2541 12:21:00.793535 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2542 12:21:00.796786 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2543 12:21:00.799852 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2544 12:21:00.799929
2545 12:21:00.803366 CA PerBit enable=1, Macro0, CA PI delay=33
2546 12:21:00.803436
2547 12:21:00.806814 [CBTSetCACLKResult] CA Dly = 33
2548 12:21:00.806887 CS Dly: 8 (0~39)
2549 12:21:00.809534 ==
2550 12:21:00.812880 Dram Type= 6, Freq= 0, CH_0, rank 1
2551 12:21:00.816182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2552 12:21:00.816257 ==
2553 12:21:00.819806 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2554 12:21:00.826503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2555 12:21:00.835865 [CA 0] Center 39 (9~70) winsize 62
2556 12:21:00.839266 [CA 1] Center 39 (9~70) winsize 62
2557 12:21:00.842660 [CA 2] Center 35 (5~66) winsize 62
2558 12:21:00.845900 [CA 3] Center 34 (4~65) winsize 62
2559 12:21:00.849088 [CA 4] Center 33 (3~64) winsize 62
2560 12:21:00.852349 [CA 5] Center 33 (3~63) winsize 61
2561 12:21:00.852451
2562 12:21:00.855848 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2563 12:21:00.855951
2564 12:21:00.859150 [CATrainingPosCal] consider 2 rank data
2565 12:21:00.862908 u2DelayCellTimex100 = 270/100 ps
2566 12:21:00.865897 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2567 12:21:00.872503 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2568 12:21:00.875596 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2569 12:21:00.878979 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2570 12:21:00.882381 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2571 12:21:00.885308 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2572 12:21:00.885406
2573 12:21:00.889323 CA PerBit enable=1, Macro0, CA PI delay=33
2574 12:21:00.889428
2575 12:21:00.891972 [CBTSetCACLKResult] CA Dly = 33
2576 12:21:00.892043 CS Dly: 9 (0~41)
2577 12:21:00.895548
2578 12:21:00.899455 ----->DramcWriteLeveling(PI) begin...
2579 12:21:00.899554 ==
2580 12:21:00.902153 Dram Type= 6, Freq= 0, CH_0, rank 0
2581 12:21:00.906073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2582 12:21:00.906176 ==
2583 12:21:00.908756 Write leveling (Byte 0): 32 => 32
2584 12:21:00.911943 Write leveling (Byte 1): 28 => 28
2585 12:21:00.915527 DramcWriteLeveling(PI) end<-----
2586 12:21:00.915596
2587 12:21:00.915656 ==
2588 12:21:00.918919 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 12:21:00.922353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 12:21:00.922447 ==
2591 12:21:00.925493 [Gating] SW mode calibration
2592 12:21:00.931916 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2593 12:21:00.938351 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2594 12:21:00.941725 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
2595 12:21:00.945225 0 15 4 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
2596 12:21:00.952101 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 12:21:00.955277 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 12:21:00.958772 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 12:21:00.964985 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 12:21:00.968348 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2601 12:21:00.971564 0 15 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
2602 12:21:00.978686 1 0 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
2603 12:21:00.981770 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2604 12:21:00.985079 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 12:21:00.991397 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 12:21:00.994544 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 12:21:00.997910 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 12:21:01.004691 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 12:21:01.008193 1 0 28 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0)
2610 12:21:01.011550 1 1 0 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
2611 12:21:01.018204 1 1 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
2612 12:21:01.021501 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 12:21:01.025172 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 12:21:01.028212 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 12:21:01.034755 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 12:21:01.037941 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 12:21:01.044384 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2618 12:21:01.047690 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2619 12:21:01.051332 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2620 12:21:01.054280 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 12:21:01.061121 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 12:21:01.064168 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 12:21:01.067670 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 12:21:01.074739 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 12:21:01.078326 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 12:21:01.081452 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 12:21:01.087903 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 12:21:01.090966 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 12:21:01.094824 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 12:21:01.101630 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 12:21:01.104430 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 12:21:01.107535 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2633 12:21:01.114186 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2634 12:21:01.117965 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2635 12:21:01.120845 Total UI for P1: 0, mck2ui 16
2636 12:21:01.124598 best dqsien dly found for B0: ( 1, 3, 26)
2637 12:21:01.127622 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2638 12:21:01.130553 Total UI for P1: 0, mck2ui 16
2639 12:21:01.134348 best dqsien dly found for B1: ( 1, 4, 0)
2640 12:21:01.137634 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2641 12:21:01.140614 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2642 12:21:01.140688
2643 12:21:01.147230 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2644 12:21:01.151119 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2645 12:21:01.151198 [Gating] SW calibration Done
2646 12:21:01.154071 ==
2647 12:21:01.154145 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 12:21:01.160511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 12:21:01.160588 ==
2650 12:21:01.160651 RX Vref Scan: 0
2651 12:21:01.160715
2652 12:21:01.163744 RX Vref 0 -> 0, step: 1
2653 12:21:01.163812
2654 12:21:01.167224 RX Delay -40 -> 252, step: 8
2655 12:21:01.170555 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2656 12:21:01.174323 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2657 12:21:01.177094 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2658 12:21:01.183878 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2659 12:21:01.187187 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2660 12:21:01.190173 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2661 12:21:01.193667 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2662 12:21:01.197219 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2663 12:21:01.203286 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2664 12:21:01.207185 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2665 12:21:01.210452 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2666 12:21:01.213550 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2667 12:21:01.216773 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2668 12:21:01.223158 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2669 12:21:01.226873 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2670 12:21:01.230362 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2671 12:21:01.230436 ==
2672 12:21:01.233212 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 12:21:01.236790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 12:21:01.240400 ==
2675 12:21:01.240472 DQS Delay:
2676 12:21:01.240534 DQS0 = 0, DQS1 = 0
2677 12:21:01.243540 DQM Delay:
2678 12:21:01.243614 DQM0 = 119, DQM1 = 106
2679 12:21:01.246604 DQ Delay:
2680 12:21:01.249686 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2681 12:21:01.253055 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2682 12:21:01.256605 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2683 12:21:01.260190 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2684 12:21:01.260266
2685 12:21:01.260332
2686 12:21:01.260391 ==
2687 12:21:01.263103 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 12:21:01.266966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 12:21:01.267040 ==
2690 12:21:01.267102
2691 12:21:01.267160
2692 12:21:01.270038 TX Vref Scan disable
2693 12:21:01.273150 == TX Byte 0 ==
2694 12:21:01.276630 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2695 12:21:01.280030 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2696 12:21:01.283508 == TX Byte 1 ==
2697 12:21:01.286280 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2698 12:21:01.289801 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2699 12:21:01.289875 ==
2700 12:21:01.293369 Dram Type= 6, Freq= 0, CH_0, rank 0
2701 12:21:01.299740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2702 12:21:01.299816 ==
2703 12:21:01.310582 TX Vref=22, minBit 14, minWin=24, winSum=415
2704 12:21:01.313459 TX Vref=24, minBit 0, minWin=26, winSum=423
2705 12:21:01.316808 TX Vref=26, minBit 8, minWin=26, winSum=428
2706 12:21:01.320040 TX Vref=28, minBit 5, minWin=26, winSum=429
2707 12:21:01.323574 TX Vref=30, minBit 4, minWin=26, winSum=431
2708 12:21:01.330238 TX Vref=32, minBit 4, minWin=26, winSum=427
2709 12:21:01.333625 [TxChooseVref] Worse bit 4, Min win 26, Win sum 431, Final Vref 30
2710 12:21:01.333700
2711 12:21:01.336770 Final TX Range 1 Vref 30
2712 12:21:01.336842
2713 12:21:01.336902 ==
2714 12:21:01.340038 Dram Type= 6, Freq= 0, CH_0, rank 0
2715 12:21:01.343552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2716 12:21:01.346847 ==
2717 12:21:01.346945
2718 12:21:01.347035
2719 12:21:01.347134 TX Vref Scan disable
2720 12:21:01.350377 == TX Byte 0 ==
2721 12:21:01.353418 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2722 12:21:01.357056 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2723 12:21:01.360185 == TX Byte 1 ==
2724 12:21:01.363512 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2725 12:21:01.367013 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2726 12:21:01.370389
2727 12:21:01.370461 [DATLAT]
2728 12:21:01.370523 Freq=1200, CH0 RK0
2729 12:21:01.370586
2730 12:21:01.373405 DATLAT Default: 0xd
2731 12:21:01.373475 0, 0xFFFF, sum = 0
2732 12:21:01.376965 1, 0xFFFF, sum = 0
2733 12:21:01.379911 2, 0xFFFF, sum = 0
2734 12:21:01.379986 3, 0xFFFF, sum = 0
2735 12:21:01.383265 4, 0xFFFF, sum = 0
2736 12:21:01.383339 5, 0xFFFF, sum = 0
2737 12:21:01.386516 6, 0xFFFF, sum = 0
2738 12:21:01.386615 7, 0xFFFF, sum = 0
2739 12:21:01.389905 8, 0xFFFF, sum = 0
2740 12:21:01.389979 9, 0xFFFF, sum = 0
2741 12:21:01.393713 10, 0xFFFF, sum = 0
2742 12:21:01.393784 11, 0xFFFF, sum = 0
2743 12:21:01.396817 12, 0x0, sum = 1
2744 12:21:01.396889 13, 0x0, sum = 2
2745 12:21:01.400218 14, 0x0, sum = 3
2746 12:21:01.400289 15, 0x0, sum = 4
2747 12:21:01.400349 best_step = 13
2748 12:21:01.403301
2749 12:21:01.403370 ==
2750 12:21:01.406498 Dram Type= 6, Freq= 0, CH_0, rank 0
2751 12:21:01.409950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2752 12:21:01.410024 ==
2753 12:21:01.410085 RX Vref Scan: 1
2754 12:21:01.410142
2755 12:21:01.413136 Set Vref Range= 32 -> 127
2756 12:21:01.413204
2757 12:21:01.416749 RX Vref 32 -> 127, step: 1
2758 12:21:01.416820
2759 12:21:01.419817 RX Delay -21 -> 252, step: 4
2760 12:21:01.419891
2761 12:21:01.423568 Set Vref, RX VrefLevel [Byte0]: 32
2762 12:21:01.426762 [Byte1]: 32
2763 12:21:01.426834
2764 12:21:01.430029 Set Vref, RX VrefLevel [Byte0]: 33
2765 12:21:01.433311 [Byte1]: 33
2766 12:21:01.436904
2767 12:21:01.436975 Set Vref, RX VrefLevel [Byte0]: 34
2768 12:21:01.440101 [Byte1]: 34
2769 12:21:01.444759
2770 12:21:01.444843 Set Vref, RX VrefLevel [Byte0]: 35
2771 12:21:01.447829 [Byte1]: 35
2772 12:21:01.452739
2773 12:21:01.452810 Set Vref, RX VrefLevel [Byte0]: 36
2774 12:21:01.456267 [Byte1]: 36
2775 12:21:01.460329
2776 12:21:01.460402 Set Vref, RX VrefLevel [Byte0]: 37
2777 12:21:01.463680 [Byte1]: 37
2778 12:21:01.468392
2779 12:21:01.468472 Set Vref, RX VrefLevel [Byte0]: 38
2780 12:21:01.472117 [Byte1]: 38
2781 12:21:01.476173
2782 12:21:01.476253 Set Vref, RX VrefLevel [Byte0]: 39
2783 12:21:01.480352 [Byte1]: 39
2784 12:21:01.484290
2785 12:21:01.484371 Set Vref, RX VrefLevel [Byte0]: 40
2786 12:21:01.487707 [Byte1]: 40
2787 12:21:01.492642
2788 12:21:01.492722 Set Vref, RX VrefLevel [Byte0]: 41
2789 12:21:01.495272 [Byte1]: 41
2790 12:21:01.499919
2791 12:21:01.499998 Set Vref, RX VrefLevel [Byte0]: 42
2792 12:21:01.503690 [Byte1]: 42
2793 12:21:01.507767
2794 12:21:01.507839 Set Vref, RX VrefLevel [Byte0]: 43
2795 12:21:01.511650 [Byte1]: 43
2796 12:21:01.516102
2797 12:21:01.516173 Set Vref, RX VrefLevel [Byte0]: 44
2798 12:21:01.519298 [Byte1]: 44
2799 12:21:01.524112
2800 12:21:01.524182 Set Vref, RX VrefLevel [Byte0]: 45
2801 12:21:01.527404 [Byte1]: 45
2802 12:21:01.531713
2803 12:21:01.531788 Set Vref, RX VrefLevel [Byte0]: 46
2804 12:21:01.535034 [Byte1]: 46
2805 12:21:01.539716
2806 12:21:01.539786 Set Vref, RX VrefLevel [Byte0]: 47
2807 12:21:01.543008 [Byte1]: 47
2808 12:21:01.547556
2809 12:21:01.547626 Set Vref, RX VrefLevel [Byte0]: 48
2810 12:21:01.551197 [Byte1]: 48
2811 12:21:01.555608
2812 12:21:01.555679 Set Vref, RX VrefLevel [Byte0]: 49
2813 12:21:01.558880 [Byte1]: 49
2814 12:21:01.563521
2815 12:21:01.563592 Set Vref, RX VrefLevel [Byte0]: 50
2816 12:21:01.566742 [Byte1]: 50
2817 12:21:01.571566
2818 12:21:01.574421 Set Vref, RX VrefLevel [Byte0]: 51
2819 12:21:01.577641 [Byte1]: 51
2820 12:21:01.577713
2821 12:21:01.580907 Set Vref, RX VrefLevel [Byte0]: 52
2822 12:21:01.584366 [Byte1]: 52
2823 12:21:01.584442
2824 12:21:01.587853 Set Vref, RX VrefLevel [Byte0]: 53
2825 12:21:01.591064 [Byte1]: 53
2826 12:21:01.595459
2827 12:21:01.595535 Set Vref, RX VrefLevel [Byte0]: 54
2828 12:21:01.598627 [Byte1]: 54
2829 12:21:01.602971
2830 12:21:01.603042 Set Vref, RX VrefLevel [Byte0]: 55
2831 12:21:01.606252 [Byte1]: 55
2832 12:21:01.611080
2833 12:21:01.611155 Set Vref, RX VrefLevel [Byte0]: 56
2834 12:21:01.614610 [Byte1]: 56
2835 12:21:01.619275
2836 12:21:01.619346 Set Vref, RX VrefLevel [Byte0]: 57
2837 12:21:01.622184 [Byte1]: 57
2838 12:21:01.626971
2839 12:21:01.627052 Set Vref, RX VrefLevel [Byte0]: 58
2840 12:21:01.630390 [Byte1]: 58
2841 12:21:01.634770
2842 12:21:01.634849 Set Vref, RX VrefLevel [Byte0]: 59
2843 12:21:01.638512 [Byte1]: 59
2844 12:21:01.643067
2845 12:21:01.643150 Set Vref, RX VrefLevel [Byte0]: 60
2846 12:21:01.646373 [Byte1]: 60
2847 12:21:01.650587
2848 12:21:01.650676 Set Vref, RX VrefLevel [Byte0]: 61
2849 12:21:01.654033 [Byte1]: 61
2850 12:21:01.658622
2851 12:21:01.658703 Set Vref, RX VrefLevel [Byte0]: 62
2852 12:21:01.661930 [Byte1]: 62
2853 12:21:01.666812
2854 12:21:01.666895 Set Vref, RX VrefLevel [Byte0]: 63
2855 12:21:01.669701 [Byte1]: 63
2856 12:21:01.674465
2857 12:21:01.674576 Set Vref, RX VrefLevel [Byte0]: 64
2858 12:21:01.677928 [Byte1]: 64
2859 12:21:01.682148
2860 12:21:01.682229 Set Vref, RX VrefLevel [Byte0]: 65
2861 12:21:01.686130 [Byte1]: 65
2862 12:21:01.690130
2863 12:21:01.690205 Set Vref, RX VrefLevel [Byte0]: 66
2864 12:21:01.694127 [Byte1]: 66
2865 12:21:01.698008
2866 12:21:01.698084 Set Vref, RX VrefLevel [Byte0]: 67
2867 12:21:01.701349 [Byte1]: 67
2868 12:21:01.705857
2869 12:21:01.709302 Set Vref, RX VrefLevel [Byte0]: 68
2870 12:21:01.712637 [Byte1]: 68
2871 12:21:01.712728
2872 12:21:01.715868 Set Vref, RX VrefLevel [Byte0]: 69
2873 12:21:01.718950 [Byte1]: 69
2874 12:21:01.719030
2875 12:21:01.722392 Set Vref, RX VrefLevel [Byte0]: 70
2876 12:21:01.725537 [Byte1]: 70
2877 12:21:01.730321
2878 12:21:01.730429 Set Vref, RX VrefLevel [Byte0]: 71
2879 12:21:01.733595 [Byte1]: 71
2880 12:21:01.737770
2881 12:21:01.737849 Set Vref, RX VrefLevel [Byte0]: 72
2882 12:21:01.741248 [Byte1]: 72
2883 12:21:01.745655
2884 12:21:01.745734 Set Vref, RX VrefLevel [Byte0]: 73
2885 12:21:01.749055 [Byte1]: 73
2886 12:21:01.754067
2887 12:21:01.754146 Set Vref, RX VrefLevel [Byte0]: 74
2888 12:21:01.757486 [Byte1]: 74
2889 12:21:01.762010
2890 12:21:01.762090 Set Vref, RX VrefLevel [Byte0]: 75
2891 12:21:01.765000 [Byte1]: 75
2892 12:21:01.770024
2893 12:21:01.770104 Set Vref, RX VrefLevel [Byte0]: 76
2894 12:21:01.775971 [Byte1]: 76
2895 12:21:01.776052
2896 12:21:01.779375 Set Vref, RX VrefLevel [Byte0]: 77
2897 12:21:01.782819 [Byte1]: 77
2898 12:21:01.782900
2899 12:21:01.786318 Final RX Vref Byte 0 = 60 to rank0
2900 12:21:01.789659 Final RX Vref Byte 1 = 58 to rank0
2901 12:21:01.792602 Final RX Vref Byte 0 = 60 to rank1
2902 12:21:01.795956 Final RX Vref Byte 1 = 58 to rank1==
2903 12:21:01.799530 Dram Type= 6, Freq= 0, CH_0, rank 0
2904 12:21:01.802695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2905 12:21:01.802776 ==
2906 12:21:01.806319 DQS Delay:
2907 12:21:01.806399 DQS0 = 0, DQS1 = 0
2908 12:21:01.809344 DQM Delay:
2909 12:21:01.809423 DQM0 = 118, DQM1 = 107
2910 12:21:01.812448 DQ Delay:
2911 12:21:01.815982 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =114
2912 12:21:01.819278 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =126
2913 12:21:01.823158 DQ8 =96, DQ9 =94, DQ10 =112, DQ11 =100
2914 12:21:01.825668 DQ12 =112, DQ13 =110, DQ14 =122, DQ15 =114
2915 12:21:01.825744
2916 12:21:01.825807
2917 12:21:01.832629 [DQSOSCAuto] RK0, (LSB)MR18= 0xdf9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 405 ps
2918 12:21:01.835734 CH0 RK0: MR19=403, MR18=DF9
2919 12:21:01.842485 CH0_RK0: MR19=0x403, MR18=0xDF9, DQSOSC=405, MR23=63, INC=39, DEC=26
2920 12:21:01.842564
2921 12:21:01.845480 ----->DramcWriteLeveling(PI) begin...
2922 12:21:01.845551 ==
2923 12:21:01.848871 Dram Type= 6, Freq= 0, CH_0, rank 1
2924 12:21:01.852168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2925 12:21:01.852235 ==
2926 12:21:01.856003 Write leveling (Byte 0): 32 => 32
2927 12:21:01.859044 Write leveling (Byte 1): 30 => 30
2928 12:21:01.862340 DramcWriteLeveling(PI) end<-----
2929 12:21:01.862408
2930 12:21:01.862467 ==
2931 12:21:01.865715 Dram Type= 6, Freq= 0, CH_0, rank 1
2932 12:21:01.868610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2933 12:21:01.872109 ==
2934 12:21:01.872185 [Gating] SW mode calibration
2935 12:21:01.882222 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2936 12:21:01.885570 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2937 12:21:01.888789 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2938 12:21:01.895574 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2939 12:21:01.898779 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2940 12:21:01.902188 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2941 12:21:01.908743 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2942 12:21:01.912421 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2943 12:21:01.915593 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2944 12:21:01.921776 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2945 12:21:01.925155 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2946 12:21:01.928523 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2947 12:21:01.935258 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2948 12:21:01.938665 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2949 12:21:01.941722 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2950 12:21:01.948649 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2951 12:21:01.951997 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2952 12:21:01.954842 1 0 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2953 12:21:01.961725 1 1 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2954 12:21:01.964889 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2955 12:21:01.968605 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2956 12:21:01.974820 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2957 12:21:01.977988 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2958 12:21:01.981445 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2959 12:21:01.988021 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2960 12:21:01.991412 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2961 12:21:01.994775 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2962 12:21:02.001191 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 12:21:02.004397 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 12:21:02.008007 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 12:21:02.014831 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 12:21:02.018233 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 12:21:02.021089 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2968 12:21:02.027730 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 12:21:02.031149 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 12:21:02.034771 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 12:21:02.042194 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 12:21:02.044407 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 12:21:02.048024 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 12:21:02.054351 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 12:21:02.057283 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2976 12:21:02.060869 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2977 12:21:02.067249 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2978 12:21:02.067330 Total UI for P1: 0, mck2ui 16
2979 12:21:02.070937 best dqsien dly found for B0: ( 1, 3, 26)
2980 12:21:02.077257 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2981 12:21:02.080460 Total UI for P1: 0, mck2ui 16
2982 12:21:02.084114 best dqsien dly found for B1: ( 1, 4, 0)
2983 12:21:02.087437 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2984 12:21:02.090920 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2985 12:21:02.091014
2986 12:21:02.094376 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2987 12:21:02.097431 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2988 12:21:02.101146 [Gating] SW calibration Done
2989 12:21:02.101226 ==
2990 12:21:02.104078 Dram Type= 6, Freq= 0, CH_0, rank 1
2991 12:21:02.107613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2992 12:21:02.107713 ==
2993 12:21:02.110578 RX Vref Scan: 0
2994 12:21:02.110728
2995 12:21:02.110820 RX Vref 0 -> 0, step: 1
2996 12:21:02.114281
2997 12:21:02.114360 RX Delay -40 -> 252, step: 8
2998 12:21:02.120588 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2999 12:21:02.123784 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3000 12:21:02.127133 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3001 12:21:02.130839 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3002 12:21:02.133683 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3003 12:21:02.137040 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3004 12:21:02.144010 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3005 12:21:02.147209 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3006 12:21:02.150426 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3007 12:21:02.153655 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3008 12:21:02.157652 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3009 12:21:02.164297 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3010 12:21:02.167139 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3011 12:21:02.171054 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3012 12:21:02.173739 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3013 12:21:02.180486 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3014 12:21:02.180566 ==
3015 12:21:02.183658 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 12:21:02.186967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 12:21:02.187037 ==
3018 12:21:02.187099 DQS Delay:
3019 12:21:02.190063 DQS0 = 0, DQS1 = 0
3020 12:21:02.190135 DQM Delay:
3021 12:21:02.193661 DQM0 = 116, DQM1 = 109
3022 12:21:02.193731 DQ Delay:
3023 12:21:02.196794 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
3024 12:21:02.200137 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
3025 12:21:02.203624 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3026 12:21:02.206956 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =119
3027 12:21:02.207024
3028 12:21:02.207087
3029 12:21:02.207144 ==
3030 12:21:02.210224 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 12:21:02.216772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 12:21:02.216843 ==
3033 12:21:02.216906
3034 12:21:02.216963
3035 12:21:02.217018 TX Vref Scan disable
3036 12:21:02.220994 == TX Byte 0 ==
3037 12:21:02.224314 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3038 12:21:02.227139 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3039 12:21:02.230452 == TX Byte 1 ==
3040 12:21:02.233710 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3041 12:21:02.237255 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3042 12:21:02.240377 ==
3043 12:21:02.243652 Dram Type= 6, Freq= 0, CH_0, rank 1
3044 12:21:02.247237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 12:21:02.247311 ==
3046 12:21:02.258548 TX Vref=22, minBit 5, minWin=25, winSum=418
3047 12:21:02.261926 TX Vref=24, minBit 5, minWin=25, winSum=424
3048 12:21:02.264932 TX Vref=26, minBit 0, minWin=26, winSum=423
3049 12:21:02.268145 TX Vref=28, minBit 10, minWin=26, winSum=434
3050 12:21:02.271817 TX Vref=30, minBit 10, minWin=26, winSum=435
3051 12:21:02.278046 TX Vref=32, minBit 10, minWin=25, winSum=428
3052 12:21:02.281498 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 30
3053 12:21:02.285134
3054 12:21:02.285234 Final TX Range 1 Vref 30
3055 12:21:02.285303
3056 12:21:02.285362 ==
3057 12:21:02.288444 Dram Type= 6, Freq= 0, CH_0, rank 1
3058 12:21:02.294473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3059 12:21:02.294545 ==
3060 12:21:02.294647
3061 12:21:02.294707
3062 12:21:02.294763 TX Vref Scan disable
3063 12:21:02.298450 == TX Byte 0 ==
3064 12:21:02.302125 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3065 12:21:02.308945 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3066 12:21:02.309026 == TX Byte 1 ==
3067 12:21:02.311862 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3068 12:21:02.318405 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3069 12:21:02.318504
3070 12:21:02.318617 [DATLAT]
3071 12:21:02.318695 Freq=1200, CH0 RK1
3072 12:21:02.318754
3073 12:21:02.321939 DATLAT Default: 0xd
3074 12:21:02.325118 0, 0xFFFF, sum = 0
3075 12:21:02.325190 1, 0xFFFF, sum = 0
3076 12:21:02.328448 2, 0xFFFF, sum = 0
3077 12:21:02.328530 3, 0xFFFF, sum = 0
3078 12:21:02.331531 4, 0xFFFF, sum = 0
3079 12:21:02.331612 5, 0xFFFF, sum = 0
3080 12:21:02.335369 6, 0xFFFF, sum = 0
3081 12:21:02.335451 7, 0xFFFF, sum = 0
3082 12:21:02.338832 8, 0xFFFF, sum = 0
3083 12:21:02.338904 9, 0xFFFF, sum = 0
3084 12:21:02.341636 10, 0xFFFF, sum = 0
3085 12:21:02.341709 11, 0xFFFF, sum = 0
3086 12:21:02.344803 12, 0x0, sum = 1
3087 12:21:02.344881 13, 0x0, sum = 2
3088 12:21:02.348382 14, 0x0, sum = 3
3089 12:21:02.348453 15, 0x0, sum = 4
3090 12:21:02.351901 best_step = 13
3091 12:21:02.351969
3092 12:21:02.352032 ==
3093 12:21:02.355426 Dram Type= 6, Freq= 0, CH_0, rank 1
3094 12:21:02.358316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3095 12:21:02.358390 ==
3096 12:21:02.358449 RX Vref Scan: 0
3097 12:21:02.361530
3098 12:21:02.361598 RX Vref 0 -> 0, step: 1
3099 12:21:02.361657
3100 12:21:02.364760 RX Delay -21 -> 252, step: 4
3101 12:21:02.371663 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3102 12:21:02.374862 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3103 12:21:02.378159 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3104 12:21:02.381321 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3105 12:21:02.384621 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3106 12:21:02.391333 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3107 12:21:02.394458 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3108 12:21:02.397992 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3109 12:21:02.401134 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3110 12:21:02.404329 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3111 12:21:02.407971 iDelay=199, Bit 10, Center 112 (43 ~ 182) 140
3112 12:21:02.414712 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3113 12:21:02.417605 iDelay=199, Bit 12, Center 116 (51 ~ 182) 132
3114 12:21:02.421213 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
3115 12:21:02.424651 iDelay=199, Bit 14, Center 122 (59 ~ 186) 128
3116 12:21:02.430931 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3117 12:21:02.431006 ==
3118 12:21:02.434778 Dram Type= 6, Freq= 0, CH_0, rank 1
3119 12:21:02.437970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 12:21:02.438040 ==
3121 12:21:02.438099 DQS Delay:
3122 12:21:02.440811 DQS0 = 0, DQS1 = 0
3123 12:21:02.440879 DQM Delay:
3124 12:21:02.444440 DQM0 = 116, DQM1 = 109
3125 12:21:02.444511 DQ Delay:
3126 12:21:02.447605 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3127 12:21:02.451069 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3128 12:21:02.454451 DQ8 =98, DQ9 =94, DQ10 =112, DQ11 =100
3129 12:21:02.458218 DQ12 =116, DQ13 =114, DQ14 =122, DQ15 =116
3130 12:21:02.458289
3131 12:21:02.458353
3132 12:21:02.467754 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 403 ps
3133 12:21:02.470708 CH0 RK1: MR19=403, MR18=10EA
3134 12:21:02.477428 CH0_RK1: MR19=0x403, MR18=0x10EA, DQSOSC=403, MR23=63, INC=40, DEC=26
3135 12:21:02.477502 [RxdqsGatingPostProcess] freq 1200
3136 12:21:02.484185 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3137 12:21:02.487503 best DQS0 dly(2T, 0.5T) = (0, 11)
3138 12:21:02.490421 best DQS1 dly(2T, 0.5T) = (0, 12)
3139 12:21:02.494513 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3140 12:21:02.497529 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3141 12:21:02.500465 best DQS0 dly(2T, 0.5T) = (0, 11)
3142 12:21:02.504063 best DQS1 dly(2T, 0.5T) = (0, 12)
3143 12:21:02.506992 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3144 12:21:02.510830 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3145 12:21:02.513800 Pre-setting of DQS Precalculation
3146 12:21:02.516974 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3147 12:21:02.517046 ==
3148 12:21:02.520452 Dram Type= 6, Freq= 0, CH_1, rank 0
3149 12:21:02.524061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3150 12:21:02.524131 ==
3151 12:21:02.530779 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3152 12:21:02.537604 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3153 12:21:02.544811 [CA 0] Center 37 (7~68) winsize 62
3154 12:21:02.548555 [CA 1] Center 38 (8~68) winsize 61
3155 12:21:02.551623 [CA 2] Center 34 (4~64) winsize 61
3156 12:21:02.555199 [CA 3] Center 33 (3~64) winsize 62
3157 12:21:02.558351 [CA 4] Center 34 (4~64) winsize 61
3158 12:21:02.562014 [CA 5] Center 33 (3~64) winsize 62
3159 12:21:02.562095
3160 12:21:02.564936 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3161 12:21:02.565017
3162 12:21:02.568494 [CATrainingPosCal] consider 1 rank data
3163 12:21:02.571455 u2DelayCellTimex100 = 270/100 ps
3164 12:21:02.574924 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3165 12:21:02.581647 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3166 12:21:02.584828 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3167 12:21:02.588412 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3168 12:21:02.591941 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3169 12:21:02.594800 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3170 12:21:02.594885
3171 12:21:02.598527 CA PerBit enable=1, Macro0, CA PI delay=33
3172 12:21:02.598668
3173 12:21:02.601267 [CBTSetCACLKResult] CA Dly = 33
3174 12:21:02.601347 CS Dly: 6 (0~37)
3175 12:21:02.604889 ==
3176 12:21:02.608228 Dram Type= 6, Freq= 0, CH_1, rank 1
3177 12:21:02.611349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3178 12:21:02.611433 ==
3179 12:21:02.614550 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3180 12:21:02.621228 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3181 12:21:02.630478 [CA 0] Center 37 (7~67) winsize 61
3182 12:21:02.633894 [CA 1] Center 38 (8~68) winsize 61
3183 12:21:02.637661 [CA 2] Center 34 (4~65) winsize 62
3184 12:21:02.640681 [CA 3] Center 33 (3~64) winsize 62
3185 12:21:02.644181 [CA 4] Center 34 (3~65) winsize 63
3186 12:21:02.647232 [CA 5] Center 33 (3~64) winsize 62
3187 12:21:02.647309
3188 12:21:02.650773 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3189 12:21:02.650845
3190 12:21:02.654321 [CATrainingPosCal] consider 2 rank data
3191 12:21:02.657250 u2DelayCellTimex100 = 270/100 ps
3192 12:21:02.660388 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3193 12:21:02.664129 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3194 12:21:02.670876 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3195 12:21:02.673864 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3196 12:21:02.677088 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3197 12:21:02.680886 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3198 12:21:02.680966
3199 12:21:02.683823 CA PerBit enable=1, Macro0, CA PI delay=33
3200 12:21:02.683904
3201 12:21:02.688004 [CBTSetCACLKResult] CA Dly = 33
3202 12:21:02.688085 CS Dly: 7 (0~40)
3203 12:21:02.688149
3204 12:21:02.690492 ----->DramcWriteLeveling(PI) begin...
3205 12:21:02.693574 ==
3206 12:21:02.697423 Dram Type= 6, Freq= 0, CH_1, rank 0
3207 12:21:02.700149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3208 12:21:02.700230 ==
3209 12:21:02.703718 Write leveling (Byte 0): 25 => 25
3210 12:21:02.706978 Write leveling (Byte 1): 28 => 28
3211 12:21:02.710234 DramcWriteLeveling(PI) end<-----
3212 12:21:02.710314
3213 12:21:02.710376 ==
3214 12:21:02.713476 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 12:21:02.717476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 12:21:02.717557 ==
3217 12:21:02.720428 [Gating] SW mode calibration
3218 12:21:02.727105 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3219 12:21:02.733923 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3220 12:21:02.736892 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3221 12:21:02.740039 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3222 12:21:02.747051 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3223 12:21:02.750106 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3224 12:21:02.753669 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3225 12:21:02.757196 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3226 12:21:02.763290 0 15 24 | B1->B0 | 3434 2d2d | 0 1 | (0 0) (1 0)
3227 12:21:02.766765 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (0 1) (1 0)
3228 12:21:02.773277 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3229 12:21:02.776600 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3230 12:21:02.779595 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3231 12:21:02.786563 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3232 12:21:02.789651 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3233 12:21:02.793545 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3234 12:21:02.796815 1 0 24 | B1->B0 | 2a2a 4040 | 1 0 | (1 1) (0 0)
3235 12:21:02.803291 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3236 12:21:02.806523 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3237 12:21:02.809886 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3238 12:21:02.816224 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3239 12:21:02.819395 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3240 12:21:02.822549 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3241 12:21:02.829725 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3242 12:21:02.833022 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3243 12:21:02.835753 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3244 12:21:02.843073 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 12:21:02.845859 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 12:21:02.849411 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 12:21:02.856243 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 12:21:02.859431 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 12:21:02.862893 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3250 12:21:02.869489 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 12:21:02.872579 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 12:21:02.875767 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 12:21:02.882459 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3254 12:21:02.885667 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3255 12:21:02.888957 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3256 12:21:02.895670 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 12:21:02.898801 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3258 12:21:02.902120 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3259 12:21:02.908781 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3260 12:21:02.912084 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3261 12:21:02.915623 Total UI for P1: 0, mck2ui 16
3262 12:21:02.919416 best dqsien dly found for B0: ( 1, 3, 26)
3263 12:21:02.922276 Total UI for P1: 0, mck2ui 16
3264 12:21:02.926007 best dqsien dly found for B1: ( 1, 3, 26)
3265 12:21:02.929276 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3266 12:21:02.932097 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3267 12:21:02.932170
3268 12:21:02.935120 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3269 12:21:02.938456 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3270 12:21:02.942099 [Gating] SW calibration Done
3271 12:21:02.942166 ==
3272 12:21:02.945327 Dram Type= 6, Freq= 0, CH_1, rank 0
3273 12:21:02.948877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3274 12:21:02.952211 ==
3275 12:21:02.952282 RX Vref Scan: 0
3276 12:21:02.952343
3277 12:21:02.955314 RX Vref 0 -> 0, step: 1
3278 12:21:02.955383
3279 12:21:02.958354 RX Delay -40 -> 252, step: 8
3280 12:21:02.961840 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3281 12:21:02.964899 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3282 12:21:02.968507 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3283 12:21:02.971698 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3284 12:21:02.978453 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3285 12:21:02.981719 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3286 12:21:02.984974 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3287 12:21:02.988006 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3288 12:21:02.991468 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3289 12:21:02.998270 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3290 12:21:03.001302 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3291 12:21:03.004703 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3292 12:21:03.007969 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3293 12:21:03.011436 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3294 12:21:03.017752 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3295 12:21:03.021120 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3296 12:21:03.021195 ==
3297 12:21:03.024837 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 12:21:03.028391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 12:21:03.028467 ==
3300 12:21:03.031702 DQS Delay:
3301 12:21:03.031777 DQS0 = 0, DQS1 = 0
3302 12:21:03.031839 DQM Delay:
3303 12:21:03.034416 DQM0 = 117, DQM1 = 108
3304 12:21:03.034485 DQ Delay:
3305 12:21:03.038353 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3306 12:21:03.041232 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3307 12:21:03.044734 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3308 12:21:03.050954 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =119
3309 12:21:03.051028
3310 12:21:03.051090
3311 12:21:03.051152 ==
3312 12:21:03.054352 Dram Type= 6, Freq= 0, CH_1, rank 0
3313 12:21:03.058258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3314 12:21:03.058327 ==
3315 12:21:03.058387
3316 12:21:03.058443
3317 12:21:03.061009 TX Vref Scan disable
3318 12:21:03.061081 == TX Byte 0 ==
3319 12:21:03.067795 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3320 12:21:03.070821 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3321 12:21:03.070903 == TX Byte 1 ==
3322 12:21:03.077667 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3323 12:21:03.080914 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3324 12:21:03.080995 ==
3325 12:21:03.084831 Dram Type= 6, Freq= 0, CH_1, rank 0
3326 12:21:03.087531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3327 12:21:03.087624 ==
3328 12:21:03.100438 TX Vref=22, minBit 9, minWin=24, winSum=412
3329 12:21:03.103763 TX Vref=24, minBit 9, minWin=25, winSum=423
3330 12:21:03.107009 TX Vref=26, minBit 9, minWin=25, winSum=424
3331 12:21:03.110300 TX Vref=28, minBit 8, minWin=25, winSum=427
3332 12:21:03.113555 TX Vref=30, minBit 9, minWin=25, winSum=429
3333 12:21:03.120366 TX Vref=32, minBit 8, minWin=25, winSum=422
3334 12:21:03.124035 [TxChooseVref] Worse bit 9, Min win 25, Win sum 429, Final Vref 30
3335 12:21:03.124117
3336 12:21:03.127010 Final TX Range 1 Vref 30
3337 12:21:03.127090
3338 12:21:03.127153 ==
3339 12:21:03.130206 Dram Type= 6, Freq= 0, CH_1, rank 0
3340 12:21:03.133958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3341 12:21:03.134038 ==
3342 12:21:03.136921
3343 12:21:03.137000
3344 12:21:03.137064 TX Vref Scan disable
3345 12:21:03.140111 == TX Byte 0 ==
3346 12:21:03.143532 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3347 12:21:03.147012 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3348 12:21:03.149983 == TX Byte 1 ==
3349 12:21:03.153725 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3350 12:21:03.156918 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3351 12:21:03.160189
3352 12:21:03.160273 [DATLAT]
3353 12:21:03.160337 Freq=1200, CH1 RK0
3354 12:21:03.160395
3355 12:21:03.163422 DATLAT Default: 0xd
3356 12:21:03.163501 0, 0xFFFF, sum = 0
3357 12:21:03.166767 1, 0xFFFF, sum = 0
3358 12:21:03.166847 2, 0xFFFF, sum = 0
3359 12:21:03.170368 3, 0xFFFF, sum = 0
3360 12:21:03.173272 4, 0xFFFF, sum = 0
3361 12:21:03.173353 5, 0xFFFF, sum = 0
3362 12:21:03.176932 6, 0xFFFF, sum = 0
3363 12:21:03.177013 7, 0xFFFF, sum = 0
3364 12:21:03.179998 8, 0xFFFF, sum = 0
3365 12:21:03.180079 9, 0xFFFF, sum = 0
3366 12:21:03.183489 10, 0xFFFF, sum = 0
3367 12:21:03.183570 11, 0xFFFF, sum = 0
3368 12:21:03.186864 12, 0x0, sum = 1
3369 12:21:03.186945 13, 0x0, sum = 2
3370 12:21:03.189682 14, 0x0, sum = 3
3371 12:21:03.189762 15, 0x0, sum = 4
3372 12:21:03.193080 best_step = 13
3373 12:21:03.193158
3374 12:21:03.193220 ==
3375 12:21:03.196645 Dram Type= 6, Freq= 0, CH_1, rank 0
3376 12:21:03.199898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3377 12:21:03.199978 ==
3378 12:21:03.200041 RX Vref Scan: 1
3379 12:21:03.200099
3380 12:21:03.203209 Set Vref Range= 32 -> 127
3381 12:21:03.203288
3382 12:21:03.206619 RX Vref 32 -> 127, step: 1
3383 12:21:03.206712
3384 12:21:03.209961 RX Delay -21 -> 252, step: 4
3385 12:21:03.210040
3386 12:21:03.213185 Set Vref, RX VrefLevel [Byte0]: 32
3387 12:21:03.216372 [Byte1]: 32
3388 12:21:03.216452
3389 12:21:03.220350 Set Vref, RX VrefLevel [Byte0]: 33
3390 12:21:03.223474 [Byte1]: 33
3391 12:21:03.226887
3392 12:21:03.226966 Set Vref, RX VrefLevel [Byte0]: 34
3393 12:21:03.229984 [Byte1]: 34
3394 12:21:03.234830
3395 12:21:03.234910 Set Vref, RX VrefLevel [Byte0]: 35
3396 12:21:03.238184 [Byte1]: 35
3397 12:21:03.242547
3398 12:21:03.242645 Set Vref, RX VrefLevel [Byte0]: 36
3399 12:21:03.246006 [Byte1]: 36
3400 12:21:03.250511
3401 12:21:03.250652 Set Vref, RX VrefLevel [Byte0]: 37
3402 12:21:03.254308 [Byte1]: 37
3403 12:21:03.258271
3404 12:21:03.258349 Set Vref, RX VrefLevel [Byte0]: 38
3405 12:21:03.262058 [Byte1]: 38
3406 12:21:03.266276
3407 12:21:03.266355 Set Vref, RX VrefLevel [Byte0]: 39
3408 12:21:03.269488 [Byte1]: 39
3409 12:21:03.274781
3410 12:21:03.274861 Set Vref, RX VrefLevel [Byte0]: 40
3411 12:21:03.277932 [Byte1]: 40
3412 12:21:03.282043
3413 12:21:03.282122 Set Vref, RX VrefLevel [Byte0]: 41
3414 12:21:03.285402 [Byte1]: 41
3415 12:21:03.290346
3416 12:21:03.290419 Set Vref, RX VrefLevel [Byte0]: 42
3417 12:21:03.293337 [Byte1]: 42
3418 12:21:03.298007
3419 12:21:03.298077 Set Vref, RX VrefLevel [Byte0]: 43
3420 12:21:03.301568 [Byte1]: 43
3421 12:21:03.306093
3422 12:21:03.306162 Set Vref, RX VrefLevel [Byte0]: 44
3423 12:21:03.309585 [Byte1]: 44
3424 12:21:03.314301
3425 12:21:03.314371 Set Vref, RX VrefLevel [Byte0]: 45
3426 12:21:03.317381 [Byte1]: 45
3427 12:21:03.321592
3428 12:21:03.321663 Set Vref, RX VrefLevel [Byte0]: 46
3429 12:21:03.325237 [Byte1]: 46
3430 12:21:03.329670
3431 12:21:03.329744 Set Vref, RX VrefLevel [Byte0]: 47
3432 12:21:03.332876 [Byte1]: 47
3433 12:21:03.337436
3434 12:21:03.337505 Set Vref, RX VrefLevel [Byte0]: 48
3435 12:21:03.341168 [Byte1]: 48
3436 12:21:03.345686
3437 12:21:03.345757 Set Vref, RX VrefLevel [Byte0]: 49
3438 12:21:03.348795 [Byte1]: 49
3439 12:21:03.353215
3440 12:21:03.353284 Set Vref, RX VrefLevel [Byte0]: 50
3441 12:21:03.357112 [Byte1]: 50
3442 12:21:03.361315
3443 12:21:03.361384 Set Vref, RX VrefLevel [Byte0]: 51
3444 12:21:03.364654 [Byte1]: 51
3445 12:21:03.369730
3446 12:21:03.369804 Set Vref, RX VrefLevel [Byte0]: 52
3447 12:21:03.372735 [Byte1]: 52
3448 12:21:03.376915
3449 12:21:03.376985 Set Vref, RX VrefLevel [Byte0]: 53
3450 12:21:03.380458 [Byte1]: 53
3451 12:21:03.384912
3452 12:21:03.384989 Set Vref, RX VrefLevel [Byte0]: 54
3453 12:21:03.388356 [Byte1]: 54
3454 12:21:03.392785
3455 12:21:03.392858 Set Vref, RX VrefLevel [Byte0]: 55
3456 12:21:03.396553 [Byte1]: 55
3457 12:21:03.401113
3458 12:21:03.401199 Set Vref, RX VrefLevel [Byte0]: 56
3459 12:21:03.404365 [Byte1]: 56
3460 12:21:03.408712
3461 12:21:03.408794 Set Vref, RX VrefLevel [Byte0]: 57
3462 12:21:03.411864 [Byte1]: 57
3463 12:21:03.416991
3464 12:21:03.417063 Set Vref, RX VrefLevel [Byte0]: 58
3465 12:21:03.419956 [Byte1]: 58
3466 12:21:03.424375
3467 12:21:03.427615 Set Vref, RX VrefLevel [Byte0]: 59
3468 12:21:03.431034 [Byte1]: 59
3469 12:21:03.431117
3470 12:21:03.434746 Set Vref, RX VrefLevel [Byte0]: 60
3471 12:21:03.438051 [Byte1]: 60
3472 12:21:03.438133
3473 12:21:03.440652 Set Vref, RX VrefLevel [Byte0]: 61
3474 12:21:03.443887 [Byte1]: 61
3475 12:21:03.448320
3476 12:21:03.448391 Set Vref, RX VrefLevel [Byte0]: 62
3477 12:21:03.452184 [Byte1]: 62
3478 12:21:03.456417
3479 12:21:03.456485 Set Vref, RX VrefLevel [Byte0]: 63
3480 12:21:03.459456 [Byte1]: 63
3481 12:21:03.463935
3482 12:21:03.464003 Set Vref, RX VrefLevel [Byte0]: 64
3483 12:21:03.467269 [Byte1]: 64
3484 12:21:03.472295
3485 12:21:03.472374 Set Vref, RX VrefLevel [Byte0]: 65
3486 12:21:03.475472 [Byte1]: 65
3487 12:21:03.480346
3488 12:21:03.480417 Set Vref, RX VrefLevel [Byte0]: 66
3489 12:21:03.483332 [Byte1]: 66
3490 12:21:03.488206
3491 12:21:03.488276 Set Vref, RX VrefLevel [Byte0]: 67
3492 12:21:03.494861 [Byte1]: 67
3493 12:21:03.494961
3494 12:21:03.497612 Set Vref, RX VrefLevel [Byte0]: 68
3495 12:21:03.501016 [Byte1]: 68
3496 12:21:03.501112
3497 12:21:03.504859 Set Vref, RX VrefLevel [Byte0]: 69
3498 12:21:03.507457 [Byte1]: 69
3499 12:21:03.511711
3500 12:21:03.511787 Final RX Vref Byte 0 = 52 to rank0
3501 12:21:03.514988 Final RX Vref Byte 1 = 56 to rank0
3502 12:21:03.518337 Final RX Vref Byte 0 = 52 to rank1
3503 12:21:03.521650 Final RX Vref Byte 1 = 56 to rank1==
3504 12:21:03.525000 Dram Type= 6, Freq= 0, CH_1, rank 0
3505 12:21:03.532115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 12:21:03.532196 ==
3507 12:21:03.532296 DQS Delay:
3508 12:21:03.532383 DQS0 = 0, DQS1 = 0
3509 12:21:03.535365 DQM Delay:
3510 12:21:03.535436 DQM0 = 116, DQM1 = 110
3511 12:21:03.538550 DQ Delay:
3512 12:21:03.541544 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =112
3513 12:21:03.544946 DQ4 =114, DQ5 =128, DQ6 =126, DQ7 =112
3514 12:21:03.548238 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =100
3515 12:21:03.551698 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =118
3516 12:21:03.551767
3517 12:21:03.551827
3518 12:21:03.558150 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3519 12:21:03.561849 CH1 RK0: MR19=403, MR18=4F7
3520 12:21:03.568262 CH1_RK0: MR19=0x403, MR18=0x4F7, DQSOSC=408, MR23=63, INC=39, DEC=26
3521 12:21:03.568334
3522 12:21:03.571416 ----->DramcWriteLeveling(PI) begin...
3523 12:21:03.571491 ==
3524 12:21:03.574836 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 12:21:03.577863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 12:21:03.581612 ==
3527 12:21:03.581684 Write leveling (Byte 0): 25 => 25
3528 12:21:03.585069 Write leveling (Byte 1): 27 => 27
3529 12:21:03.588233 DramcWriteLeveling(PI) end<-----
3530 12:21:03.588301
3531 12:21:03.588361 ==
3532 12:21:03.591013 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 12:21:03.597625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 12:21:03.597708 ==
3535 12:21:03.601025 [Gating] SW mode calibration
3536 12:21:03.608139 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3537 12:21:03.610755 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3538 12:21:03.617491 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3539 12:21:03.621207 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3540 12:21:03.624393 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3541 12:21:03.630723 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3542 12:21:03.634050 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3543 12:21:03.637634 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3544 12:21:03.643970 0 15 24 | B1->B0 | 3333 3434 | 0 0 | (0 1) (0 1)
3545 12:21:03.647063 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3546 12:21:03.650529 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3547 12:21:03.657553 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3548 12:21:03.660443 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3549 12:21:03.663516 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3550 12:21:03.670211 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3551 12:21:03.673780 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3552 12:21:03.677134 1 0 24 | B1->B0 | 3333 2626 | 1 0 | (0 0) (0 0)
3553 12:21:03.683672 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3554 12:21:03.686737 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3555 12:21:03.690178 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3556 12:21:03.696580 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3557 12:21:03.699724 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3558 12:21:03.703710 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 12:21:03.709889 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3560 12:21:03.713137 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3561 12:21:03.716414 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3562 12:21:03.723135 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 12:21:03.726440 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 12:21:03.730195 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 12:21:03.736569 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 12:21:03.739992 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 12:21:03.742962 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 12:21:03.749611 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 12:21:03.753015 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 12:21:03.756436 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 12:21:03.762835 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 12:21:03.766220 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 12:21:03.769542 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 12:21:03.776014 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 12:21:03.779498 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 12:21:03.782756 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3577 12:21:03.789428 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3578 12:21:03.789510 Total UI for P1: 0, mck2ui 16
3579 12:21:03.795646 best dqsien dly found for B1: ( 1, 3, 24)
3580 12:21:03.798856 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3581 12:21:03.802628 Total UI for P1: 0, mck2ui 16
3582 12:21:03.805544 best dqsien dly found for B0: ( 1, 3, 26)
3583 12:21:03.809052 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3584 12:21:03.812115 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3585 12:21:03.812221
3586 12:21:03.815306 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3587 12:21:03.818713 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3588 12:21:03.822088 [Gating] SW calibration Done
3589 12:21:03.822167 ==
3590 12:21:03.825734 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 12:21:03.828491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 12:21:03.831925 ==
3593 12:21:03.832006 RX Vref Scan: 0
3594 12:21:03.832069
3595 12:21:03.835505 RX Vref 0 -> 0, step: 1
3596 12:21:03.835585
3597 12:21:03.838833 RX Delay -40 -> 252, step: 8
3598 12:21:03.842367 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3599 12:21:03.845033 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3600 12:21:03.848597 iDelay=208, Bit 2, Center 107 (40 ~ 175) 136
3601 12:21:03.851798 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3602 12:21:03.858457 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3603 12:21:03.861743 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3604 12:21:03.864796 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3605 12:21:03.868240 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3606 12:21:03.871358 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
3607 12:21:03.878113 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3608 12:21:03.881669 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3609 12:21:03.885106 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3610 12:21:03.888574 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3611 12:21:03.891553 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3612 12:21:03.898229 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3613 12:21:03.901168 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3614 12:21:03.901248 ==
3615 12:21:03.904476 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 12:21:03.907964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 12:21:03.908045 ==
3618 12:21:03.911136 DQS Delay:
3619 12:21:03.911216 DQS0 = 0, DQS1 = 0
3620 12:21:03.914521 DQM Delay:
3621 12:21:03.914628 DQM0 = 118, DQM1 = 110
3622 12:21:03.914706 DQ Delay:
3623 12:21:03.917609 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3624 12:21:03.924132 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3625 12:21:03.927806 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =103
3626 12:21:03.931026 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3627 12:21:03.931106
3628 12:21:03.931169
3629 12:21:03.931227 ==
3630 12:21:03.934553 Dram Type= 6, Freq= 0, CH_1, rank 1
3631 12:21:03.937396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3632 12:21:03.937476 ==
3633 12:21:03.937539
3634 12:21:03.937597
3635 12:21:03.941010 TX Vref Scan disable
3636 12:21:03.944085 == TX Byte 0 ==
3637 12:21:03.947487 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3638 12:21:03.950609 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3639 12:21:03.953939 == TX Byte 1 ==
3640 12:21:03.957285 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3641 12:21:03.960709 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3642 12:21:03.960789 ==
3643 12:21:03.963935 Dram Type= 6, Freq= 0, CH_1, rank 1
3644 12:21:03.967479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3645 12:21:03.970184 ==
3646 12:21:03.980720 TX Vref=22, minBit 8, minWin=25, winSum=422
3647 12:21:03.983720 TX Vref=24, minBit 8, minWin=26, winSum=428
3648 12:21:03.987130 TX Vref=26, minBit 9, minWin=26, winSum=432
3649 12:21:03.990373 TX Vref=28, minBit 9, minWin=26, winSum=434
3650 12:21:03.993619 TX Vref=30, minBit 9, minWin=26, winSum=433
3651 12:21:04.000174 TX Vref=32, minBit 15, minWin=25, winSum=432
3652 12:21:04.003727 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 28
3653 12:21:04.003807
3654 12:21:04.006738 Final TX Range 1 Vref 28
3655 12:21:04.006819
3656 12:21:04.006883 ==
3657 12:21:04.010436 Dram Type= 6, Freq= 0, CH_1, rank 1
3658 12:21:04.013813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3659 12:21:04.016552 ==
3660 12:21:04.016632
3661 12:21:04.016695
3662 12:21:04.016753 TX Vref Scan disable
3663 12:21:04.020129 == TX Byte 0 ==
3664 12:21:04.023582 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3665 12:21:04.030442 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3666 12:21:04.030552 == TX Byte 1 ==
3667 12:21:04.033623 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3668 12:21:04.040433 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3669 12:21:04.040513
3670 12:21:04.040596 [DATLAT]
3671 12:21:04.040659 Freq=1200, CH1 RK1
3672 12:21:04.040716
3673 12:21:04.044005 DATLAT Default: 0xd
3674 12:21:04.044085 0, 0xFFFF, sum = 0
3675 12:21:04.047117 1, 0xFFFF, sum = 0
3676 12:21:04.050082 2, 0xFFFF, sum = 0
3677 12:21:04.050163 3, 0xFFFF, sum = 0
3678 12:21:04.053589 4, 0xFFFF, sum = 0
3679 12:21:04.053670 5, 0xFFFF, sum = 0
3680 12:21:04.056777 6, 0xFFFF, sum = 0
3681 12:21:04.056859 7, 0xFFFF, sum = 0
3682 12:21:04.060819 8, 0xFFFF, sum = 0
3683 12:21:04.060901 9, 0xFFFF, sum = 0
3684 12:21:04.063152 10, 0xFFFF, sum = 0
3685 12:21:04.063233 11, 0xFFFF, sum = 0
3686 12:21:04.066718 12, 0x0, sum = 1
3687 12:21:04.066799 13, 0x0, sum = 2
3688 12:21:04.070320 14, 0x0, sum = 3
3689 12:21:04.070401 15, 0x0, sum = 4
3690 12:21:04.073326 best_step = 13
3691 12:21:04.073405
3692 12:21:04.073468 ==
3693 12:21:04.076367 Dram Type= 6, Freq= 0, CH_1, rank 1
3694 12:21:04.079650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3695 12:21:04.079731 ==
3696 12:21:04.083160 RX Vref Scan: 0
3697 12:21:04.083239
3698 12:21:04.083302 RX Vref 0 -> 0, step: 1
3699 12:21:04.083361
3700 12:21:04.086367 RX Delay -21 -> 252, step: 4
3701 12:21:04.092894 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3702 12:21:04.095984 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3703 12:21:04.099529 iDelay=199, Bit 2, Center 108 (43 ~ 174) 132
3704 12:21:04.102725 iDelay=199, Bit 3, Center 114 (47 ~ 182) 136
3705 12:21:04.106376 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3706 12:21:04.112371 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3707 12:21:04.116111 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3708 12:21:04.119767 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3709 12:21:04.122449 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3710 12:21:04.125710 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3711 12:21:04.132347 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3712 12:21:04.135748 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3713 12:21:04.139066 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3714 12:21:04.142562 iDelay=199, Bit 13, Center 120 (55 ~ 186) 132
3715 12:21:04.148962 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3716 12:21:04.152456 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3717 12:21:04.152537 ==
3718 12:21:04.155504 Dram Type= 6, Freq= 0, CH_1, rank 1
3719 12:21:04.158539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3720 12:21:04.158700 ==
3721 12:21:04.162279 DQS Delay:
3722 12:21:04.162359 DQS0 = 0, DQS1 = 0
3723 12:21:04.162423 DQM Delay:
3724 12:21:04.165243 DQM0 = 117, DQM1 = 111
3725 12:21:04.165325 DQ Delay:
3726 12:21:04.168691 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =114
3727 12:21:04.171823 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =116
3728 12:21:04.175188 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =100
3729 12:21:04.182069 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =120
3730 12:21:04.182150
3731 12:21:04.182212
3732 12:21:04.188431 [DQSOSCAuto] RK1, (LSB)MR18= 0xf8f4, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
3733 12:21:04.191756 CH1 RK1: MR19=303, MR18=F8F4
3734 12:21:04.198412 CH1_RK1: MR19=0x303, MR18=0xF8F4, DQSOSC=413, MR23=63, INC=38, DEC=25
3735 12:21:04.202120 [RxdqsGatingPostProcess] freq 1200
3736 12:21:04.204888 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3737 12:21:04.208402 best DQS0 dly(2T, 0.5T) = (0, 11)
3738 12:21:04.211467 best DQS1 dly(2T, 0.5T) = (0, 11)
3739 12:21:04.214818 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3740 12:21:04.218242 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3741 12:21:04.221359 best DQS0 dly(2T, 0.5T) = (0, 11)
3742 12:21:04.224801 best DQS1 dly(2T, 0.5T) = (0, 11)
3743 12:21:04.227902 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3744 12:21:04.231736 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3745 12:21:04.234545 Pre-setting of DQS Precalculation
3746 12:21:04.238022 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3747 12:21:04.247890 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3748 12:21:04.254791 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3749 12:21:04.254873
3750 12:21:04.254937
3751 12:21:04.257683 [Calibration Summary] 2400 Mbps
3752 12:21:04.257764 CH 0, Rank 0
3753 12:21:04.261464 SW Impedance : PASS
3754 12:21:04.261545 DUTY Scan : NO K
3755 12:21:04.264416 ZQ Calibration : PASS
3756 12:21:04.267973 Jitter Meter : NO K
3757 12:21:04.268054 CBT Training : PASS
3758 12:21:04.271488 Write leveling : PASS
3759 12:21:04.274113 RX DQS gating : PASS
3760 12:21:04.274194 RX DQ/DQS(RDDQC) : PASS
3761 12:21:04.277419 TX DQ/DQS : PASS
3762 12:21:04.281208 RX DATLAT : PASS
3763 12:21:04.281290 RX DQ/DQS(Engine): PASS
3764 12:21:04.284372 TX OE : NO K
3765 12:21:04.284480 All Pass.
3766 12:21:04.284573
3767 12:21:04.287732 CH 0, Rank 1
3768 12:21:04.287813 SW Impedance : PASS
3769 12:21:04.291045 DUTY Scan : NO K
3770 12:21:04.294311 ZQ Calibration : PASS
3771 12:21:04.294418 Jitter Meter : NO K
3772 12:21:04.297560 CBT Training : PASS
3773 12:21:04.300879 Write leveling : PASS
3774 12:21:04.300989 RX DQS gating : PASS
3775 12:21:04.303831 RX DQ/DQS(RDDQC) : PASS
3776 12:21:04.307119 TX DQ/DQS : PASS
3777 12:21:04.307201 RX DATLAT : PASS
3778 12:21:04.311010 RX DQ/DQS(Engine): PASS
3779 12:21:04.313968 TX OE : NO K
3780 12:21:04.314050 All Pass.
3781 12:21:04.314114
3782 12:21:04.314173 CH 1, Rank 0
3783 12:21:04.317207 SW Impedance : PASS
3784 12:21:04.320687 DUTY Scan : NO K
3785 12:21:04.320769 ZQ Calibration : PASS
3786 12:21:04.323726 Jitter Meter : NO K
3787 12:21:04.327453 CBT Training : PASS
3788 12:21:04.327535 Write leveling : PASS
3789 12:21:04.330328 RX DQS gating : PASS
3790 12:21:04.330409 RX DQ/DQS(RDDQC) : PASS
3791 12:21:04.333385 TX DQ/DQS : PASS
3792 12:21:04.336983 RX DATLAT : PASS
3793 12:21:04.337064 RX DQ/DQS(Engine): PASS
3794 12:21:04.340192 TX OE : NO K
3795 12:21:04.340274 All Pass.
3796 12:21:04.340338
3797 12:21:04.343516 CH 1, Rank 1
3798 12:21:04.343597 SW Impedance : PASS
3799 12:21:04.346910 DUTY Scan : NO K
3800 12:21:04.350059 ZQ Calibration : PASS
3801 12:21:04.350140 Jitter Meter : NO K
3802 12:21:04.353439 CBT Training : PASS
3803 12:21:04.356502 Write leveling : PASS
3804 12:21:04.356584 RX DQS gating : PASS
3805 12:21:04.360599 RX DQ/DQS(RDDQC) : PASS
3806 12:21:04.363210 TX DQ/DQS : PASS
3807 12:21:04.363292 RX DATLAT : PASS
3808 12:21:04.366563 RX DQ/DQS(Engine): PASS
3809 12:21:04.369922 TX OE : NO K
3810 12:21:04.370003 All Pass.
3811 12:21:04.370068
3812 12:21:04.373547 DramC Write-DBI off
3813 12:21:04.373629 PER_BANK_REFRESH: Hybrid Mode
3814 12:21:04.376567 TX_TRACKING: ON
3815 12:21:04.383331 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3816 12:21:04.389902 [FAST_K] Save calibration result to emmc
3817 12:21:04.393725 dramc_set_vcore_voltage set vcore to 650000
3818 12:21:04.393807 Read voltage for 600, 5
3819 12:21:04.396726 Vio18 = 0
3820 12:21:04.396808 Vcore = 650000
3821 12:21:04.396872 Vdram = 0
3822 12:21:04.399659 Vddq = 0
3823 12:21:04.399739 Vmddr = 0
3824 12:21:04.403533 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3825 12:21:04.409815 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3826 12:21:04.412888 MEM_TYPE=3, freq_sel=19
3827 12:21:04.416338 sv_algorithm_assistance_LP4_1600
3828 12:21:04.420118 ============ PULL DRAM RESETB DOWN ============
3829 12:21:04.423475 ========== PULL DRAM RESETB DOWN end =========
3830 12:21:04.429487 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3831 12:21:04.432602 ===================================
3832 12:21:04.432683 LPDDR4 DRAM CONFIGURATION
3833 12:21:04.436216 ===================================
3834 12:21:04.439685 EX_ROW_EN[0] = 0x0
3835 12:21:04.439765 EX_ROW_EN[1] = 0x0
3836 12:21:04.442601 LP4Y_EN = 0x0
3837 12:21:04.442698 WORK_FSP = 0x0
3838 12:21:04.446140 WL = 0x2
3839 12:21:04.446220 RL = 0x2
3840 12:21:04.449554 BL = 0x2
3841 12:21:04.452966 RPST = 0x0
3842 12:21:04.453046 RD_PRE = 0x0
3843 12:21:04.456199 WR_PRE = 0x1
3844 12:21:04.456279 WR_PST = 0x0
3845 12:21:04.459653 DBI_WR = 0x0
3846 12:21:04.459735 DBI_RD = 0x0
3847 12:21:04.462732 OTF = 0x1
3848 12:21:04.465747 ===================================
3849 12:21:04.469123 ===================================
3850 12:21:04.469205 ANA top config
3851 12:21:04.472359 ===================================
3852 12:21:04.475896 DLL_ASYNC_EN = 0
3853 12:21:04.479620 ALL_SLAVE_EN = 1
3854 12:21:04.479727 NEW_RANK_MODE = 1
3855 12:21:04.482565 DLL_IDLE_MODE = 1
3856 12:21:04.485636 LP45_APHY_COMB_EN = 1
3857 12:21:04.489155 TX_ODT_DIS = 1
3858 12:21:04.492328 NEW_8X_MODE = 1
3859 12:21:04.495577 ===================================
3860 12:21:04.499086 ===================================
3861 12:21:04.499167 data_rate = 1200
3862 12:21:04.502325 CKR = 1
3863 12:21:04.505508 DQ_P2S_RATIO = 8
3864 12:21:04.508630 ===================================
3865 12:21:04.511863 CA_P2S_RATIO = 8
3866 12:21:04.515180 DQ_CA_OPEN = 0
3867 12:21:04.518623 DQ_SEMI_OPEN = 0
3868 12:21:04.518717 CA_SEMI_OPEN = 0
3869 12:21:04.522258 CA_FULL_RATE = 0
3870 12:21:04.525133 DQ_CKDIV4_EN = 1
3871 12:21:04.528809 CA_CKDIV4_EN = 1
3872 12:21:04.532199 CA_PREDIV_EN = 0
3873 12:21:04.535214 PH8_DLY = 0
3874 12:21:04.538129 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3875 12:21:04.538213 DQ_AAMCK_DIV = 4
3876 12:21:04.541710 CA_AAMCK_DIV = 4
3877 12:21:04.545148 CA_ADMCK_DIV = 4
3878 12:21:04.547927 DQ_TRACK_CA_EN = 0
3879 12:21:04.551588 CA_PICK = 600
3880 12:21:04.554956 CA_MCKIO = 600
3881 12:21:04.557784 MCKIO_SEMI = 0
3882 12:21:04.557864 PLL_FREQ = 2288
3883 12:21:04.561371 DQ_UI_PI_RATIO = 32
3884 12:21:04.564637 CA_UI_PI_RATIO = 0
3885 12:21:04.567652 ===================================
3886 12:21:04.571375 ===================================
3887 12:21:04.574473 memory_type:LPDDR4
3888 12:21:04.577734 GP_NUM : 10
3889 12:21:04.577815 SRAM_EN : 1
3890 12:21:04.580893 MD32_EN : 0
3891 12:21:04.584052 ===================================
3892 12:21:04.584137 [ANA_INIT] >>>>>>>>>>>>>>
3893 12:21:04.587582 <<<<<< [CONFIGURE PHASE]: ANA_TX
3894 12:21:04.590842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3895 12:21:04.594217 ===================================
3896 12:21:04.597519 data_rate = 1200,PCW = 0X5800
3897 12:21:04.600741 ===================================
3898 12:21:04.604014 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3899 12:21:04.610644 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3900 12:21:04.617009 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3901 12:21:04.620756 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3902 12:21:04.623668 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3903 12:21:04.627623 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3904 12:21:04.630167 [ANA_INIT] flow start
3905 12:21:04.630247 [ANA_INIT] PLL >>>>>>>>
3906 12:21:04.633822 [ANA_INIT] PLL <<<<<<<<
3907 12:21:04.636651 [ANA_INIT] MIDPI >>>>>>>>
3908 12:21:04.640260 [ANA_INIT] MIDPI <<<<<<<<
3909 12:21:04.640341 [ANA_INIT] DLL >>>>>>>>
3910 12:21:04.643355 [ANA_INIT] flow end
3911 12:21:04.646762 ============ LP4 DIFF to SE enter ============
3912 12:21:04.649784 ============ LP4 DIFF to SE exit ============
3913 12:21:04.653146 [ANA_INIT] <<<<<<<<<<<<<
3914 12:21:04.656359 [Flow] Enable top DCM control >>>>>
3915 12:21:04.659699 [Flow] Enable top DCM control <<<<<
3916 12:21:04.662758 Enable DLL master slave shuffle
3917 12:21:04.670019 ==============================================================
3918 12:21:04.670100 Gating Mode config
3919 12:21:04.676001 ==============================================================
3920 12:21:04.676082 Config description:
3921 12:21:04.685979 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3922 12:21:04.692679 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3923 12:21:04.699040 SELPH_MODE 0: By rank 1: By Phase
3924 12:21:04.705984 ==============================================================
3925 12:21:04.706066 GAT_TRACK_EN = 1
3926 12:21:04.708947 RX_GATING_MODE = 2
3927 12:21:04.712060 RX_GATING_TRACK_MODE = 2
3928 12:21:04.715604 SELPH_MODE = 1
3929 12:21:04.718683 PICG_EARLY_EN = 1
3930 12:21:04.722293 VALID_LAT_VALUE = 1
3931 12:21:04.729523 ==============================================================
3932 12:21:04.732060 Enter into Gating configuration >>>>
3933 12:21:04.735206 Exit from Gating configuration <<<<
3934 12:21:04.738586 Enter into DVFS_PRE_config >>>>>
3935 12:21:04.748409 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3936 12:21:04.752272 Exit from DVFS_PRE_config <<<<<
3937 12:21:04.755201 Enter into PICG configuration >>>>
3938 12:21:04.758720 Exit from PICG configuration <<<<
3939 12:21:04.762090 [RX_INPUT] configuration >>>>>
3940 12:21:04.765239 [RX_INPUT] configuration <<<<<
3941 12:21:04.768505 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3942 12:21:04.775085 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3943 12:21:04.781593 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3944 12:21:04.788674 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3945 12:21:04.791856 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3946 12:21:04.798042 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3947 12:21:04.801678 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3948 12:21:04.808106 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3949 12:21:04.811218 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3950 12:21:04.814417 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3951 12:21:04.817637 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3952 12:21:04.824165 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3953 12:21:04.827545 ===================================
3954 12:21:04.831205 LPDDR4 DRAM CONFIGURATION
3955 12:21:04.834274 ===================================
3956 12:21:04.834356 EX_ROW_EN[0] = 0x0
3957 12:21:04.837336 EX_ROW_EN[1] = 0x0
3958 12:21:04.837417 LP4Y_EN = 0x0
3959 12:21:04.840755 WORK_FSP = 0x0
3960 12:21:04.840836 WL = 0x2
3961 12:21:04.844018 RL = 0x2
3962 12:21:04.844099 BL = 0x2
3963 12:21:04.847292 RPST = 0x0
3964 12:21:04.847372 RD_PRE = 0x0
3965 12:21:04.850978 WR_PRE = 0x1
3966 12:21:04.851059 WR_PST = 0x0
3967 12:21:04.854171 DBI_WR = 0x0
3968 12:21:04.854252 DBI_RD = 0x0
3969 12:21:04.857154 OTF = 0x1
3970 12:21:04.861201 ===================================
3971 12:21:04.863731 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3972 12:21:04.867238 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3973 12:21:04.873851 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3974 12:21:04.877056 ===================================
3975 12:21:04.880354 LPDDR4 DRAM CONFIGURATION
3976 12:21:04.883766 ===================================
3977 12:21:04.883851 EX_ROW_EN[0] = 0x10
3978 12:21:04.887072 EX_ROW_EN[1] = 0x0
3979 12:21:04.887155 LP4Y_EN = 0x0
3980 12:21:04.890039 WORK_FSP = 0x0
3981 12:21:04.890123 WL = 0x2
3982 12:21:04.893748 RL = 0x2
3983 12:21:04.893831 BL = 0x2
3984 12:21:04.896826 RPST = 0x0
3985 12:21:04.896909 RD_PRE = 0x0
3986 12:21:04.900090 WR_PRE = 0x1
3987 12:21:04.903602 WR_PST = 0x0
3988 12:21:04.903685 DBI_WR = 0x0
3989 12:21:04.906535 DBI_RD = 0x0
3990 12:21:04.906655 OTF = 0x1
3991 12:21:04.909774 ===================================
3992 12:21:04.916490 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3993 12:21:04.920424 nWR fixed to 30
3994 12:21:04.923405 [ModeRegInit_LP4] CH0 RK0
3995 12:21:04.923489 [ModeRegInit_LP4] CH0 RK1
3996 12:21:04.926777 [ModeRegInit_LP4] CH1 RK0
3997 12:21:04.930506 [ModeRegInit_LP4] CH1 RK1
3998 12:21:04.930612 match AC timing 17
3999 12:21:04.936897 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4000 12:21:04.940059 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4001 12:21:04.943186 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4002 12:21:04.950067 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4003 12:21:04.953316 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4004 12:21:04.953400 ==
4005 12:21:04.956872 Dram Type= 6, Freq= 0, CH_0, rank 0
4006 12:21:04.959885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 12:21:04.959969 ==
4008 12:21:04.966461 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4009 12:21:04.973542 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4010 12:21:04.976387 [CA 0] Center 36 (6~66) winsize 61
4011 12:21:04.979663 [CA 1] Center 36 (6~66) winsize 61
4012 12:21:04.983498 [CA 2] Center 34 (4~65) winsize 62
4013 12:21:04.986420 [CA 3] Center 34 (4~65) winsize 62
4014 12:21:04.989869 [CA 4] Center 33 (3~64) winsize 62
4015 12:21:04.992679 [CA 5] Center 33 (3~64) winsize 62
4016 12:21:04.992763
4017 12:21:04.996563 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4018 12:21:04.996647
4019 12:21:04.999607 [CATrainingPosCal] consider 1 rank data
4020 12:21:05.003127 u2DelayCellTimex100 = 270/100 ps
4021 12:21:05.006322 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4022 12:21:05.009390 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4023 12:21:05.012721 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4024 12:21:05.019096 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4025 12:21:05.022369 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4026 12:21:05.025810 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4027 12:21:05.025893
4028 12:21:05.029014 CA PerBit enable=1, Macro0, CA PI delay=33
4029 12:21:05.029098
4030 12:21:05.032364 [CBTSetCACLKResult] CA Dly = 33
4031 12:21:05.032448 CS Dly: 4 (0~35)
4032 12:21:05.032535 ==
4033 12:21:05.035710 Dram Type= 6, Freq= 0, CH_0, rank 1
4034 12:21:05.041998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 12:21:05.042082 ==
4036 12:21:05.045519 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4037 12:21:05.052090 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4038 12:21:05.055559 [CA 0] Center 36 (6~66) winsize 61
4039 12:21:05.058752 [CA 1] Center 36 (6~66) winsize 61
4040 12:21:05.062189 [CA 2] Center 34 (4~65) winsize 62
4041 12:21:05.065305 [CA 3] Center 34 (4~65) winsize 62
4042 12:21:05.068988 [CA 4] Center 33 (3~64) winsize 62
4043 12:21:05.071914 [CA 5] Center 33 (3~64) winsize 62
4044 12:21:05.071998
4045 12:21:05.076273 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4046 12:21:05.076357
4047 12:21:05.078546 [CATrainingPosCal] consider 2 rank data
4048 12:21:05.082122 u2DelayCellTimex100 = 270/100 ps
4049 12:21:05.085302 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4050 12:21:05.091629 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4051 12:21:05.095556 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4052 12:21:05.098553 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4053 12:21:05.102434 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4054 12:21:05.105431 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4055 12:21:05.105515
4056 12:21:05.108311 CA PerBit enable=1, Macro0, CA PI delay=33
4057 12:21:05.108396
4058 12:21:05.111511 [CBTSetCACLKResult] CA Dly = 33
4059 12:21:05.115065 CS Dly: 4 (0~36)
4060 12:21:05.115149
4061 12:21:05.117919 ----->DramcWriteLeveling(PI) begin...
4062 12:21:05.118004 ==
4063 12:21:05.121354 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 12:21:05.124627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 12:21:05.124712 ==
4066 12:21:05.128106 Write leveling (Byte 0): 32 => 32
4067 12:21:05.131170 Write leveling (Byte 1): 32 => 32
4068 12:21:05.134903 DramcWriteLeveling(PI) end<-----
4069 12:21:05.134987
4070 12:21:05.135071 ==
4071 12:21:05.137960 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 12:21:05.141138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 12:21:05.141222 ==
4074 12:21:05.144566 [Gating] SW mode calibration
4075 12:21:05.150885 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4076 12:21:05.157617 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4077 12:21:05.160866 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4078 12:21:05.167572 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4079 12:21:05.170789 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4080 12:21:05.174230 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (0 0)
4081 12:21:05.180726 0 9 16 | B1->B0 | 3131 2626 | 1 0 | (1 0) (0 0)
4082 12:21:05.183856 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4083 12:21:05.187331 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4084 12:21:05.193488 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4085 12:21:05.196962 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4086 12:21:05.200517 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4087 12:21:05.207152 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4088 12:21:05.210337 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4089 12:21:05.213730 0 10 16 | B1->B0 | 3434 4242 | 0 0 | (0 0) (1 1)
4090 12:21:05.217019 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4091 12:21:05.223376 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4092 12:21:05.227085 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 12:21:05.229853 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4094 12:21:05.236703 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4095 12:21:05.239846 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4096 12:21:05.246860 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4097 12:21:05.249854 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 12:21:05.252808 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 12:21:05.259484 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 12:21:05.262974 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 12:21:05.266197 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 12:21:05.272562 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 12:21:05.275968 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 12:21:05.279612 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 12:21:05.285846 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 12:21:05.289431 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 12:21:05.293049 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 12:21:05.298764 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 12:21:05.302078 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 12:21:05.305994 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 12:21:05.311969 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4112 12:21:05.315752 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4113 12:21:05.318524 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4114 12:21:05.325092 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4115 12:21:05.325178 Total UI for P1: 0, mck2ui 16
4116 12:21:05.332429 best dqsien dly found for B0: ( 0, 13, 12)
4117 12:21:05.332514 Total UI for P1: 0, mck2ui 16
4118 12:21:05.335638 best dqsien dly found for B1: ( 0, 13, 14)
4119 12:21:05.342031 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4120 12:21:05.345257 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4121 12:21:05.345395
4122 12:21:05.348388 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4123 12:21:05.351550 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4124 12:21:05.355067 [Gating] SW calibration Done
4125 12:21:05.355151 ==
4126 12:21:05.358478 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 12:21:05.361885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 12:21:05.361972 ==
4129 12:21:05.364918 RX Vref Scan: 0
4130 12:21:05.365017
4131 12:21:05.365083 RX Vref 0 -> 0, step: 1
4132 12:21:05.365144
4133 12:21:05.368164 RX Delay -230 -> 252, step: 16
4134 12:21:05.374960 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4135 12:21:05.378217 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4136 12:21:05.381526 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4137 12:21:05.384654 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4138 12:21:05.388015 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4139 12:21:05.394730 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4140 12:21:05.398095 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4141 12:21:05.401118 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4142 12:21:05.404662 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4143 12:21:05.410981 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4144 12:21:05.414227 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4145 12:21:05.417499 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4146 12:21:05.421147 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4147 12:21:05.427694 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4148 12:21:05.430819 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4149 12:21:05.434241 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4150 12:21:05.434349 ==
4151 12:21:05.437789 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 12:21:05.440551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 12:21:05.444260 ==
4154 12:21:05.444346 DQS Delay:
4155 12:21:05.444413 DQS0 = 0, DQS1 = 0
4156 12:21:05.447363 DQM Delay:
4157 12:21:05.447448 DQM0 = 41, DQM1 = 31
4158 12:21:05.450768 DQ Delay:
4159 12:21:05.454167 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4160 12:21:05.454250 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4161 12:21:05.457100 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4162 12:21:05.460346 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4163 12:21:05.463691
4164 12:21:05.463774
4165 12:21:05.463838 ==
4166 12:21:05.467172 Dram Type= 6, Freq= 0, CH_0, rank 0
4167 12:21:05.470408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 12:21:05.470517 ==
4169 12:21:05.470661
4170 12:21:05.470740
4171 12:21:05.473840 TX Vref Scan disable
4172 12:21:05.473952 == TX Byte 0 ==
4173 12:21:05.480538 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4174 12:21:05.483671 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4175 12:21:05.483759 == TX Byte 1 ==
4176 12:21:05.490704 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4177 12:21:05.493753 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4178 12:21:05.493851 ==
4179 12:21:05.497048 Dram Type= 6, Freq= 0, CH_0, rank 0
4180 12:21:05.500167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 12:21:05.500250 ==
4182 12:21:05.500315
4183 12:21:05.503620
4184 12:21:05.503702 TX Vref Scan disable
4185 12:21:05.506921 == TX Byte 0 ==
4186 12:21:05.510126 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4187 12:21:05.516852 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4188 12:21:05.516953 == TX Byte 1 ==
4189 12:21:05.519923 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4190 12:21:05.526900 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4191 12:21:05.526983
4192 12:21:05.527047 [DATLAT]
4193 12:21:05.527108 Freq=600, CH0 RK0
4194 12:21:05.527167
4195 12:21:05.530603 DATLAT Default: 0x9
4196 12:21:05.530698 0, 0xFFFF, sum = 0
4197 12:21:05.533041 1, 0xFFFF, sum = 0
4198 12:21:05.536602 2, 0xFFFF, sum = 0
4199 12:21:05.536685 3, 0xFFFF, sum = 0
4200 12:21:05.539856 4, 0xFFFF, sum = 0
4201 12:21:05.539939 5, 0xFFFF, sum = 0
4202 12:21:05.543112 6, 0xFFFF, sum = 0
4203 12:21:05.543261 7, 0xFFFF, sum = 0
4204 12:21:05.546441 8, 0x0, sum = 1
4205 12:21:05.546537 9, 0x0, sum = 2
4206 12:21:05.546612 10, 0x0, sum = 3
4207 12:21:05.550238 11, 0x0, sum = 4
4208 12:21:05.550322 best_step = 9
4209 12:21:05.550394
4210 12:21:05.550454 ==
4211 12:21:05.553619 Dram Type= 6, Freq= 0, CH_0, rank 0
4212 12:21:05.559902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 12:21:05.560013 ==
4214 12:21:05.560081 RX Vref Scan: 1
4215 12:21:05.560162
4216 12:21:05.562724 RX Vref 0 -> 0, step: 1
4217 12:21:05.562801
4218 12:21:05.566369 RX Delay -195 -> 252, step: 8
4219 12:21:05.566442
4220 12:21:05.569667 Set Vref, RX VrefLevel [Byte0]: 60
4221 12:21:05.572684 [Byte1]: 58
4222 12:21:05.572789
4223 12:21:05.575897 Final RX Vref Byte 0 = 60 to rank0
4224 12:21:05.579150 Final RX Vref Byte 1 = 58 to rank0
4225 12:21:05.582844 Final RX Vref Byte 0 = 60 to rank1
4226 12:21:05.585806 Final RX Vref Byte 1 = 58 to rank1==
4227 12:21:05.589069 Dram Type= 6, Freq= 0, CH_0, rank 0
4228 12:21:05.592704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 12:21:05.595923 ==
4230 12:21:05.596048 DQS Delay:
4231 12:21:05.596144 DQS0 = 0, DQS1 = 0
4232 12:21:05.599473 DQM Delay:
4233 12:21:05.599555 DQM0 = 41, DQM1 = 33
4234 12:21:05.602455 DQ Delay:
4235 12:21:05.602537 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4236 12:21:05.605804 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
4237 12:21:05.609303 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4238 12:21:05.612551 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4239 12:21:05.612634
4240 12:21:05.616133
4241 12:21:05.622557 [DQSOSCAuto] RK0, (LSB)MR18= 0x6239, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
4242 12:21:05.625866 CH0 RK0: MR19=808, MR18=6239
4243 12:21:05.632475 CH0_RK0: MR19=0x808, MR18=0x6239, DQSOSC=391, MR23=63, INC=171, DEC=114
4244 12:21:05.632557
4245 12:21:05.635877 ----->DramcWriteLeveling(PI) begin...
4246 12:21:05.635959 ==
4247 12:21:05.638736 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 12:21:05.642270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 12:21:05.642352 ==
4250 12:21:05.645871 Write leveling (Byte 0): 36 => 36
4251 12:21:05.648590 Write leveling (Byte 1): 29 => 29
4252 12:21:05.652292 DramcWriteLeveling(PI) end<-----
4253 12:21:05.652373
4254 12:21:05.652437 ==
4255 12:21:05.655477 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 12:21:05.659111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 12:21:05.659196 ==
4258 12:21:05.662270 [Gating] SW mode calibration
4259 12:21:05.668780 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4260 12:21:05.675448 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4261 12:21:05.678434 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4262 12:21:05.684709 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4263 12:21:05.688578 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4264 12:21:05.691576 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4265 12:21:05.698244 0 9 16 | B1->B0 | 2e2e 2c2c | 0 0 | (0 1) (0 0)
4266 12:21:05.701885 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4267 12:21:05.704803 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4268 12:21:05.711306 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4269 12:21:05.714774 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4270 12:21:05.718537 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4271 12:21:05.724900 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4272 12:21:05.727992 0 10 12 | B1->B0 | 2525 2727 | 0 1 | (0 0) (0 0)
4273 12:21:05.731217 0 10 16 | B1->B0 | 3a3a 3f3e | 1 1 | (0 0) (0 0)
4274 12:21:05.737699 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 12:21:05.741383 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 12:21:05.744388 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4277 12:21:05.751101 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 12:21:05.754229 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4279 12:21:05.757512 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4280 12:21:05.764267 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4281 12:21:05.767828 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 12:21:05.770751 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 12:21:05.777367 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 12:21:05.780838 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 12:21:05.784154 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 12:21:05.790575 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 12:21:05.793836 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 12:21:05.797431 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 12:21:05.804134 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 12:21:05.807052 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 12:21:05.810176 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 12:21:05.816656 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 12:21:05.820510 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 12:21:05.823417 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 12:21:05.830209 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 12:21:05.833957 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4297 12:21:05.836814 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4298 12:21:05.840604 Total UI for P1: 0, mck2ui 16
4299 12:21:05.843397 best dqsien dly found for B0: ( 0, 13, 12)
4300 12:21:05.846570 Total UI for P1: 0, mck2ui 16
4301 12:21:05.850147 best dqsien dly found for B1: ( 0, 13, 12)
4302 12:21:05.853588 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4303 12:21:05.856610 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4304 12:21:05.856694
4305 12:21:05.863094 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4306 12:21:05.866537 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4307 12:21:05.866646 [Gating] SW calibration Done
4308 12:21:05.869519 ==
4309 12:21:05.872731 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 12:21:05.876279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 12:21:05.876364 ==
4312 12:21:05.876450 RX Vref Scan: 0
4313 12:21:05.876531
4314 12:21:05.879418 RX Vref 0 -> 0, step: 1
4315 12:21:05.879503
4316 12:21:05.882653 RX Delay -230 -> 252, step: 16
4317 12:21:05.886288 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4318 12:21:05.889430 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4319 12:21:05.895804 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4320 12:21:05.899283 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4321 12:21:05.902347 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4322 12:21:05.906231 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4323 12:21:05.912825 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4324 12:21:05.916268 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4325 12:21:05.919518 iDelay=218, Bit 8, Center 33 (-134 ~ 201) 336
4326 12:21:05.922245 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4327 12:21:05.929274 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4328 12:21:05.933028 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4329 12:21:05.935397 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4330 12:21:05.938756 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4331 12:21:05.945558 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4332 12:21:05.948532 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4333 12:21:05.948617 ==
4334 12:21:05.951894 Dram Type= 6, Freq= 0, CH_0, rank 1
4335 12:21:05.955888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 12:21:05.955973 ==
4337 12:21:05.958878 DQS Delay:
4338 12:21:05.958963 DQS0 = 0, DQS1 = 0
4339 12:21:05.959050 DQM Delay:
4340 12:21:05.961916 DQM0 = 41, DQM1 = 35
4341 12:21:05.962000 DQ Delay:
4342 12:21:05.965232 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4343 12:21:05.968640 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4344 12:21:05.971753 DQ8 =33, DQ9 =17, DQ10 =33, DQ11 =33
4345 12:21:05.975351 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4346 12:21:05.975458
4347 12:21:05.975549
4348 12:21:05.975639 ==
4349 12:21:05.978686 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 12:21:05.985012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 12:21:05.985098 ==
4352 12:21:05.985162
4353 12:21:05.985222
4354 12:21:05.985280 TX Vref Scan disable
4355 12:21:05.988677 == TX Byte 0 ==
4356 12:21:05.991771 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4357 12:21:05.998609 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4358 12:21:05.998705 == TX Byte 1 ==
4359 12:21:06.001745 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4360 12:21:06.008581 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4361 12:21:06.008662 ==
4362 12:21:06.011458 Dram Type= 6, Freq= 0, CH_0, rank 1
4363 12:21:06.014965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 12:21:06.015048 ==
4365 12:21:06.015114
4366 12:21:06.015173
4367 12:21:06.018315 TX Vref Scan disable
4368 12:21:06.021762 == TX Byte 0 ==
4369 12:21:06.024824 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4370 12:21:06.028066 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4371 12:21:06.031833 == TX Byte 1 ==
4372 12:21:06.034819 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4373 12:21:06.038109 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4374 12:21:06.038191
4375 12:21:06.041544 [DATLAT]
4376 12:21:06.041625 Freq=600, CH0 RK1
4377 12:21:06.041689
4378 12:21:06.044770 DATLAT Default: 0x9
4379 12:21:06.044851 0, 0xFFFF, sum = 0
4380 12:21:06.048542 1, 0xFFFF, sum = 0
4381 12:21:06.048625 2, 0xFFFF, sum = 0
4382 12:21:06.051194 3, 0xFFFF, sum = 0
4383 12:21:06.051276 4, 0xFFFF, sum = 0
4384 12:21:06.054571 5, 0xFFFF, sum = 0
4385 12:21:06.054677 6, 0xFFFF, sum = 0
4386 12:21:06.057696 7, 0xFFFF, sum = 0
4387 12:21:06.057778 8, 0x0, sum = 1
4388 12:21:06.061236 9, 0x0, sum = 2
4389 12:21:06.061319 10, 0x0, sum = 3
4390 12:21:06.064550 11, 0x0, sum = 4
4391 12:21:06.064633 best_step = 9
4392 12:21:06.064697
4393 12:21:06.064757 ==
4394 12:21:06.067611 Dram Type= 6, Freq= 0, CH_0, rank 1
4395 12:21:06.071053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 12:21:06.074553 ==
4397 12:21:06.074677 RX Vref Scan: 0
4398 12:21:06.074742
4399 12:21:06.078285 RX Vref 0 -> 0, step: 1
4400 12:21:06.078366
4401 12:21:06.080777 RX Delay -195 -> 252, step: 8
4402 12:21:06.084837 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4403 12:21:06.087440 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4404 12:21:06.093882 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4405 12:21:06.097324 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4406 12:21:06.100880 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4407 12:21:06.104100 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4408 12:21:06.110914 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4409 12:21:06.114008 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4410 12:21:06.117397 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4411 12:21:06.120727 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4412 12:21:06.127217 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4413 12:21:06.130526 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4414 12:21:06.133642 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4415 12:21:06.137106 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4416 12:21:06.143649 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4417 12:21:06.146708 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4418 12:21:06.146784 ==
4419 12:21:06.149928 Dram Type= 6, Freq= 0, CH_0, rank 1
4420 12:21:06.153402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 12:21:06.153483 ==
4422 12:21:06.156743 DQS Delay:
4423 12:21:06.156820 DQS0 = 0, DQS1 = 0
4424 12:21:06.156883 DQM Delay:
4425 12:21:06.159716 DQM0 = 41, DQM1 = 33
4426 12:21:06.159784 DQ Delay:
4427 12:21:06.163176 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4428 12:21:06.166208 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4429 12:21:06.169618 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =24
4430 12:21:06.172884 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4431 12:21:06.172956
4432 12:21:06.173018
4433 12:21:06.182700 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e10, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
4434 12:21:06.186198 CH0 RK1: MR19=808, MR18=5E10
4435 12:21:06.192652 CH0_RK1: MR19=0x808, MR18=0x5E10, DQSOSC=392, MR23=63, INC=170, DEC=113
4436 12:21:06.192726 [RxdqsGatingPostProcess] freq 600
4437 12:21:06.199935 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4438 12:21:06.202406 Pre-setting of DQS Precalculation
4439 12:21:06.205923 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4440 12:21:06.209047 ==
4441 12:21:06.212876 Dram Type= 6, Freq= 0, CH_1, rank 0
4442 12:21:06.215760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4443 12:21:06.215872 ==
4444 12:21:06.219157 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4445 12:21:06.225502 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4446 12:21:06.229695 [CA 0] Center 35 (5~66) winsize 62
4447 12:21:06.233039 [CA 1] Center 35 (5~66) winsize 62
4448 12:21:06.236422 [CA 2] Center 34 (3~65) winsize 63
4449 12:21:06.239690 [CA 3] Center 33 (3~64) winsize 62
4450 12:21:06.242737 [CA 4] Center 34 (4~64) winsize 61
4451 12:21:06.246187 [CA 5] Center 33 (3~64) winsize 62
4452 12:21:06.246260
4453 12:21:06.249857 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4454 12:21:06.249928
4455 12:21:06.252876 [CATrainingPosCal] consider 1 rank data
4456 12:21:06.255804 u2DelayCellTimex100 = 270/100 ps
4457 12:21:06.259156 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4458 12:21:06.265879 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4459 12:21:06.269052 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4460 12:21:06.272477 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4461 12:21:06.275714 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4462 12:21:06.279105 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4463 12:21:06.279176
4464 12:21:06.282333 CA PerBit enable=1, Macro0, CA PI delay=33
4465 12:21:06.282407
4466 12:21:06.285910 [CBTSetCACLKResult] CA Dly = 33
4467 12:21:06.289256 CS Dly: 4 (0~35)
4468 12:21:06.289324 ==
4469 12:21:06.291943 Dram Type= 6, Freq= 0, CH_1, rank 1
4470 12:21:06.295219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 12:21:06.295288 ==
4472 12:21:06.302208 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4473 12:21:06.305398 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4474 12:21:06.310097 [CA 0] Center 35 (5~66) winsize 62
4475 12:21:06.313256 [CA 1] Center 36 (6~66) winsize 61
4476 12:21:06.316369 [CA 2] Center 34 (4~65) winsize 62
4477 12:21:06.319782 [CA 3] Center 33 (3~64) winsize 62
4478 12:21:06.323355 [CA 4] Center 34 (4~65) winsize 62
4479 12:21:06.326452 [CA 5] Center 34 (3~65) winsize 63
4480 12:21:06.326521
4481 12:21:06.329836 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4482 12:21:06.329909
4483 12:21:06.333004 [CATrainingPosCal] consider 2 rank data
4484 12:21:06.335980 u2DelayCellTimex100 = 270/100 ps
4485 12:21:06.339695 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4486 12:21:06.346020 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4487 12:21:06.349276 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4488 12:21:06.353218 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4489 12:21:06.355961 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4490 12:21:06.359788 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4491 12:21:06.359872
4492 12:21:06.363047 CA PerBit enable=1, Macro0, CA PI delay=33
4493 12:21:06.363132
4494 12:21:06.365886 [CBTSetCACLKResult] CA Dly = 33
4495 12:21:06.369350 CS Dly: 5 (0~37)
4496 12:21:06.369435
4497 12:21:06.372572 ----->DramcWriteLeveling(PI) begin...
4498 12:21:06.372658 ==
4499 12:21:06.375705 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 12:21:06.379188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 12:21:06.379273 ==
4502 12:21:06.382265 Write leveling (Byte 0): 30 => 30
4503 12:21:06.385931 Write leveling (Byte 1): 31 => 31
4504 12:21:06.388983 DramcWriteLeveling(PI) end<-----
4505 12:21:06.389068
4506 12:21:06.389153 ==
4507 12:21:06.392463 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 12:21:06.395754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 12:21:06.395839 ==
4510 12:21:06.398902 [Gating] SW mode calibration
4511 12:21:06.405194 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4512 12:21:06.411851 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4513 12:21:06.415437 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4514 12:21:06.418856 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4515 12:21:06.424974 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4516 12:21:06.428320 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (1 0) (0 1)
4517 12:21:06.431703 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4518 12:21:06.438308 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4519 12:21:06.441548 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4520 12:21:06.445042 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4521 12:21:06.452721 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4522 12:21:06.455052 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4523 12:21:06.458508 0 10 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
4524 12:21:06.464839 0 10 12 | B1->B0 | 2f2f 4242 | 0 1 | (1 1) (0 0)
4525 12:21:06.468188 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4526 12:21:06.471448 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4527 12:21:06.478139 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 12:21:06.481278 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 12:21:06.484560 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 12:21:06.491306 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4531 12:21:06.494312 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4532 12:21:06.498067 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4533 12:21:06.504785 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 12:21:06.507973 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 12:21:06.511246 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 12:21:06.517599 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 12:21:06.520900 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 12:21:06.524244 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 12:21:06.531019 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 12:21:06.533978 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 12:21:06.537452 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 12:21:06.544537 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 12:21:06.547607 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 12:21:06.550447 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 12:21:06.557361 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 12:21:06.560834 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 12:21:06.563855 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 12:21:06.570462 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4549 12:21:06.574024 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4550 12:21:06.576998 Total UI for P1: 0, mck2ui 16
4551 12:21:06.580312 best dqsien dly found for B0: ( 0, 13, 12)
4552 12:21:06.584225 Total UI for P1: 0, mck2ui 16
4553 12:21:06.587214 best dqsien dly found for B1: ( 0, 13, 12)
4554 12:21:06.590455 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4555 12:21:06.593835 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4556 12:21:06.593905
4557 12:21:06.596751 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4558 12:21:06.600070 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4559 12:21:06.603590 [Gating] SW calibration Done
4560 12:21:06.603664 ==
4561 12:21:06.606871 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 12:21:06.613412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 12:21:06.613492 ==
4564 12:21:06.613557 RX Vref Scan: 0
4565 12:21:06.613617
4566 12:21:06.616515 RX Vref 0 -> 0, step: 1
4567 12:21:06.616582
4568 12:21:06.620289 RX Delay -230 -> 252, step: 16
4569 12:21:06.623143 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4570 12:21:06.626629 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4571 12:21:06.629982 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4572 12:21:06.636509 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4573 12:21:06.639516 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4574 12:21:06.643414 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4575 12:21:06.646026 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4576 12:21:06.653290 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4577 12:21:06.656042 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4578 12:21:06.659341 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4579 12:21:06.662886 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4580 12:21:06.669574 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4581 12:21:06.672810 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4582 12:21:06.675892 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4583 12:21:06.679309 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4584 12:21:06.685926 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4585 12:21:06.686008 ==
4586 12:21:06.689169 Dram Type= 6, Freq= 0, CH_1, rank 0
4587 12:21:06.692595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 12:21:06.692677 ==
4589 12:21:06.692740 DQS Delay:
4590 12:21:06.695569 DQS0 = 0, DQS1 = 0
4591 12:21:06.695638 DQM Delay:
4592 12:21:06.699325 DQM0 = 42, DQM1 = 34
4593 12:21:06.699395 DQ Delay:
4594 12:21:06.702372 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4595 12:21:06.705633 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =41
4596 12:21:06.708795 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4597 12:21:06.712003 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =49
4598 12:21:06.712070
4599 12:21:06.712129
4600 12:21:06.712192 ==
4601 12:21:06.715294 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 12:21:06.718706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 12:21:06.718773 ==
4604 12:21:06.722044
4605 12:21:06.722116
4606 12:21:06.722177 TX Vref Scan disable
4607 12:21:06.725679 == TX Byte 0 ==
4608 12:21:06.728991 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4609 12:21:06.731744 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4610 12:21:06.735280 == TX Byte 1 ==
4611 12:21:06.738621 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4612 12:21:06.742141 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4613 12:21:06.745209 ==
4614 12:21:06.745290 Dram Type= 6, Freq= 0, CH_1, rank 0
4615 12:21:06.752132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 12:21:06.752207 ==
4617 12:21:06.752275
4618 12:21:06.752335
4619 12:21:06.752391 TX Vref Scan disable
4620 12:21:06.756648 == TX Byte 0 ==
4621 12:21:06.759927 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4622 12:21:06.766639 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4623 12:21:06.766717 == TX Byte 1 ==
4624 12:21:06.769558 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4625 12:21:06.776433 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4626 12:21:06.776515
4627 12:21:06.776579 [DATLAT]
4628 12:21:06.776638 Freq=600, CH1 RK0
4629 12:21:06.776696
4630 12:21:06.779380 DATLAT Default: 0x9
4631 12:21:06.782852 0, 0xFFFF, sum = 0
4632 12:21:06.782935 1, 0xFFFF, sum = 0
4633 12:21:06.786404 2, 0xFFFF, sum = 0
4634 12:21:06.786478 3, 0xFFFF, sum = 0
4635 12:21:06.789467 4, 0xFFFF, sum = 0
4636 12:21:06.789543 5, 0xFFFF, sum = 0
4637 12:21:06.792502 6, 0xFFFF, sum = 0
4638 12:21:06.792569 7, 0xFFFF, sum = 0
4639 12:21:06.796095 8, 0x0, sum = 1
4640 12:21:06.796168 9, 0x0, sum = 2
4641 12:21:06.799595 10, 0x0, sum = 3
4642 12:21:06.799667 11, 0x0, sum = 4
4643 12:21:06.799729 best_step = 9
4644 12:21:06.799786
4645 12:21:06.802256 ==
4646 12:21:06.805802 Dram Type= 6, Freq= 0, CH_1, rank 0
4647 12:21:06.809021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 12:21:06.809100 ==
4649 12:21:06.809163 RX Vref Scan: 1
4650 12:21:06.809221
4651 12:21:06.812368 RX Vref 0 -> 0, step: 1
4652 12:21:06.812433
4653 12:21:06.815340 RX Delay -195 -> 252, step: 8
4654 12:21:06.815407
4655 12:21:06.819125 Set Vref, RX VrefLevel [Byte0]: 52
4656 12:21:06.822106 [Byte1]: 56
4657 12:21:06.822177
4658 12:21:06.825776 Final RX Vref Byte 0 = 52 to rank0
4659 12:21:06.828864 Final RX Vref Byte 1 = 56 to rank0
4660 12:21:06.832113 Final RX Vref Byte 0 = 52 to rank1
4661 12:21:06.835665 Final RX Vref Byte 1 = 56 to rank1==
4662 12:21:06.839028 Dram Type= 6, Freq= 0, CH_1, rank 0
4663 12:21:06.845521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 12:21:06.845594 ==
4665 12:21:06.845655 DQS Delay:
4666 12:21:06.845713 DQS0 = 0, DQS1 = 0
4667 12:21:06.848638 DQM Delay:
4668 12:21:06.848719 DQM0 = 45, DQM1 = 34
4669 12:21:06.851945 DQ Delay:
4670 12:21:06.855260 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =40
4671 12:21:06.858780 DQ4 =40, DQ5 =56, DQ6 =56, DQ7 =40
4672 12:21:06.862108 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4673 12:21:06.865118 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4674 12:21:06.865199
4675 12:21:06.865264
4676 12:21:06.871563 [DQSOSCAuto] RK0, (LSB)MR18= 0x5338, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4677 12:21:06.875338 CH1 RK0: MR19=808, MR18=5338
4678 12:21:06.881829 CH1_RK0: MR19=0x808, MR18=0x5338, DQSOSC=394, MR23=63, INC=168, DEC=112
4679 12:21:06.881936
4680 12:21:06.884833 ----->DramcWriteLeveling(PI) begin...
4681 12:21:06.884917 ==
4682 12:21:06.888399 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 12:21:06.891637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 12:21:06.891720 ==
4685 12:21:06.894991 Write leveling (Byte 0): 31 => 31
4686 12:21:06.898147 Write leveling (Byte 1): 29 => 29
4687 12:21:06.901570 DramcWriteLeveling(PI) end<-----
4688 12:21:06.901652
4689 12:21:06.901715 ==
4690 12:21:06.905186 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 12:21:06.907962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 12:21:06.908045 ==
4693 12:21:06.911506 [Gating] SW mode calibration
4694 12:21:06.918180 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4695 12:21:06.924818 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4696 12:21:06.927919 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4697 12:21:06.934468 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4698 12:21:06.937779 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4699 12:21:06.941769 0 9 12 | B1->B0 | 3030 3232 | 1 1 | (1 1) (1 0)
4700 12:21:06.948122 0 9 16 | B1->B0 | 2525 2626 | 0 0 | (0 0) (0 0)
4701 12:21:06.951106 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4702 12:21:06.954558 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4703 12:21:06.961040 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4704 12:21:06.964242 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4705 12:21:06.967224 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4706 12:21:06.973788 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4707 12:21:06.977310 0 10 12 | B1->B0 | 3333 3030 | 0 0 | (1 1) (0 0)
4708 12:21:06.981006 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4709 12:21:06.987528 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4710 12:21:06.990762 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4711 12:21:06.993809 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4712 12:21:07.000452 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4713 12:21:07.003964 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4714 12:21:07.007307 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4715 12:21:07.013546 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4716 12:21:07.017482 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 12:21:07.020176 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 12:21:07.026754 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 12:21:07.030298 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 12:21:07.033272 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 12:21:07.039699 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 12:21:07.043006 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 12:21:07.046695 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 12:21:07.053131 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 12:21:07.056079 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 12:21:07.059302 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 12:21:07.066294 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 12:21:07.069162 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 12:21:07.073033 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 12:21:07.078989 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 12:21:07.082667 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4732 12:21:07.086262 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4733 12:21:07.089275 Total UI for P1: 0, mck2ui 16
4734 12:21:07.092573 best dqsien dly found for B0: ( 0, 13, 12)
4735 12:21:07.096135 Total UI for P1: 0, mck2ui 16
4736 12:21:07.099458 best dqsien dly found for B1: ( 0, 13, 12)
4737 12:21:07.102478 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4738 12:21:07.105572 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4739 12:21:07.109050
4740 12:21:07.112130 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4741 12:21:07.115501 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4742 12:21:07.119271 [Gating] SW calibration Done
4743 12:21:07.119355 ==
4744 12:21:07.122168 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 12:21:07.125535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 12:21:07.125620 ==
4747 12:21:07.125707 RX Vref Scan: 0
4748 12:21:07.129039
4749 12:21:07.129122 RX Vref 0 -> 0, step: 1
4750 12:21:07.129208
4751 12:21:07.132093 RX Delay -230 -> 252, step: 16
4752 12:21:07.136290 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4753 12:21:07.141929 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4754 12:21:07.144927 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4755 12:21:07.148238 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4756 12:21:07.152351 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4757 12:21:07.158459 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4758 12:21:07.161778 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4759 12:21:07.164963 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4760 12:21:07.168586 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4761 12:21:07.171396 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4762 12:21:07.178257 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4763 12:21:07.181835 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4764 12:21:07.185017 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4765 12:21:07.188064 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4766 12:21:07.194913 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4767 12:21:07.198003 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4768 12:21:07.198088 ==
4769 12:21:07.201596 Dram Type= 6, Freq= 0, CH_1, rank 1
4770 12:21:07.204486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4771 12:21:07.204570 ==
4772 12:21:07.207753 DQS Delay:
4773 12:21:07.207837 DQS0 = 0, DQS1 = 0
4774 12:21:07.211582 DQM Delay:
4775 12:21:07.211667 DQM0 = 40, DQM1 = 37
4776 12:21:07.211752 DQ Delay:
4777 12:21:07.214824 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4778 12:21:07.217665 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4779 12:21:07.221002 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4780 12:21:07.224092 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4781 12:21:07.224176
4782 12:21:07.224262
4783 12:21:07.227481 ==
4784 12:21:07.227564 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 12:21:07.234018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 12:21:07.234103 ==
4787 12:21:07.234189
4788 12:21:07.234271
4789 12:21:07.237590 TX Vref Scan disable
4790 12:21:07.237674 == TX Byte 0 ==
4791 12:21:07.243871 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4792 12:21:07.247372 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4793 12:21:07.247455 == TX Byte 1 ==
4794 12:21:07.253818 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4795 12:21:07.257311 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4796 12:21:07.257391 ==
4797 12:21:07.260538 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 12:21:07.263729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 12:21:07.263809 ==
4800 12:21:07.263872
4801 12:21:07.263929
4802 12:21:07.267114 TX Vref Scan disable
4803 12:21:07.270547 == TX Byte 0 ==
4804 12:21:07.273743 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4805 12:21:07.276717 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4806 12:21:07.280517 == TX Byte 1 ==
4807 12:21:07.283782 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4808 12:21:07.286829 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4809 12:21:07.290545
4810 12:21:07.290676 [DATLAT]
4811 12:21:07.290740 Freq=600, CH1 RK1
4812 12:21:07.290800
4813 12:21:07.293452 DATLAT Default: 0x9
4814 12:21:07.293531 0, 0xFFFF, sum = 0
4815 12:21:07.296870 1, 0xFFFF, sum = 0
4816 12:21:07.296954 2, 0xFFFF, sum = 0
4817 12:21:07.299968 3, 0xFFFF, sum = 0
4818 12:21:07.303348 4, 0xFFFF, sum = 0
4819 12:21:07.303429 5, 0xFFFF, sum = 0
4820 12:21:07.306477 6, 0xFFFF, sum = 0
4821 12:21:07.306585 7, 0xFFFF, sum = 0
4822 12:21:07.309752 8, 0x0, sum = 1
4823 12:21:07.309833 9, 0x0, sum = 2
4824 12:21:07.309897 10, 0x0, sum = 3
4825 12:21:07.313219 11, 0x0, sum = 4
4826 12:21:07.313300 best_step = 9
4827 12:21:07.313363
4828 12:21:07.313421 ==
4829 12:21:07.316558 Dram Type= 6, Freq= 0, CH_1, rank 1
4830 12:21:07.322936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4831 12:21:07.323016 ==
4832 12:21:07.323080 RX Vref Scan: 0
4833 12:21:07.323139
4834 12:21:07.326383 RX Vref 0 -> 0, step: 1
4835 12:21:07.326463
4836 12:21:07.329608 RX Delay -195 -> 252, step: 8
4837 12:21:07.336179 iDelay=213, Bit 0, Center 44 (-107 ~ 196) 304
4838 12:21:07.339592 iDelay=213, Bit 1, Center 36 (-115 ~ 188) 304
4839 12:21:07.343093 iDelay=213, Bit 2, Center 28 (-123 ~ 180) 304
4840 12:21:07.346094 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4841 12:21:07.349795 iDelay=213, Bit 4, Center 40 (-115 ~ 196) 312
4842 12:21:07.356051 iDelay=213, Bit 5, Center 52 (-99 ~ 204) 304
4843 12:21:07.359183 iDelay=213, Bit 6, Center 56 (-99 ~ 212) 312
4844 12:21:07.362819 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4845 12:21:07.365942 iDelay=213, Bit 8, Center 20 (-139 ~ 180) 320
4846 12:21:07.369434 iDelay=213, Bit 9, Center 20 (-139 ~ 180) 320
4847 12:21:07.375735 iDelay=213, Bit 10, Center 36 (-123 ~ 196) 320
4848 12:21:07.379057 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4849 12:21:07.382191 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4850 12:21:07.389178 iDelay=213, Bit 13, Center 44 (-115 ~ 204) 320
4851 12:21:07.392190 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4852 12:21:07.395993 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4853 12:21:07.396073 ==
4854 12:21:07.398777 Dram Type= 6, Freq= 0, CH_1, rank 1
4855 12:21:07.402516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4856 12:21:07.402651 ==
4857 12:21:07.405636 DQS Delay:
4858 12:21:07.405716 DQS0 = 0, DQS1 = 0
4859 12:21:07.409060 DQM Delay:
4860 12:21:07.409139 DQM0 = 42, DQM1 = 35
4861 12:21:07.409202 DQ Delay:
4862 12:21:07.412522 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4863 12:21:07.415756 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =40
4864 12:21:07.418900 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4865 12:21:07.422129 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4866 12:21:07.422209
4867 12:21:07.422272
4868 12:21:07.432484 [DQSOSCAuto] RK1, (LSB)MR18= 0x3024, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 400 ps
4869 12:21:07.435280 CH1 RK1: MR19=808, MR18=3024
4870 12:21:07.441848 CH1_RK1: MR19=0x808, MR18=0x3024, DQSOSC=400, MR23=63, INC=163, DEC=109
4871 12:21:07.445134 [RxdqsGatingPostProcess] freq 600
4872 12:21:07.448560 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4873 12:21:07.451637 Pre-setting of DQS Precalculation
4874 12:21:07.458724 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4875 12:21:07.464922 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4876 12:21:07.471532 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4877 12:21:07.471612
4878 12:21:07.471675
4879 12:21:07.474981 [Calibration Summary] 1200 Mbps
4880 12:21:07.475061 CH 0, Rank 0
4881 12:21:07.477904 SW Impedance : PASS
4882 12:21:07.481434 DUTY Scan : NO K
4883 12:21:07.481514 ZQ Calibration : PASS
4884 12:21:07.484766 Jitter Meter : NO K
4885 12:21:07.484847 CBT Training : PASS
4886 12:21:07.488150 Write leveling : PASS
4887 12:21:07.491247 RX DQS gating : PASS
4888 12:21:07.491327 RX DQ/DQS(RDDQC) : PASS
4889 12:21:07.494998 TX DQ/DQS : PASS
4890 12:21:07.497770 RX DATLAT : PASS
4891 12:21:07.497851 RX DQ/DQS(Engine): PASS
4892 12:21:07.501151 TX OE : NO K
4893 12:21:07.501223 All Pass.
4894 12:21:07.501291
4895 12:21:07.504675 CH 0, Rank 1
4896 12:21:07.504745 SW Impedance : PASS
4897 12:21:07.507691 DUTY Scan : NO K
4898 12:21:07.511208 ZQ Calibration : PASS
4899 12:21:07.511288 Jitter Meter : NO K
4900 12:21:07.514214 CBT Training : PASS
4901 12:21:07.517655 Write leveling : PASS
4902 12:21:07.517735 RX DQS gating : PASS
4903 12:21:07.521239 RX DQ/DQS(RDDQC) : PASS
4904 12:21:07.524550 TX DQ/DQS : PASS
4905 12:21:07.524627 RX DATLAT : PASS
4906 12:21:07.527822 RX DQ/DQS(Engine): PASS
4907 12:21:07.531045 TX OE : NO K
4908 12:21:07.531153 All Pass.
4909 12:21:07.531218
4910 12:21:07.531277 CH 1, Rank 0
4911 12:21:07.534451 SW Impedance : PASS
4912 12:21:07.537490 DUTY Scan : NO K
4913 12:21:07.537571 ZQ Calibration : PASS
4914 12:21:07.541732 Jitter Meter : NO K
4915 12:21:07.544264 CBT Training : PASS
4916 12:21:07.544344 Write leveling : PASS
4917 12:21:07.547596 RX DQS gating : PASS
4918 12:21:07.550755 RX DQ/DQS(RDDQC) : PASS
4919 12:21:07.550835 TX DQ/DQS : PASS
4920 12:21:07.554217 RX DATLAT : PASS
4921 12:21:07.554297 RX DQ/DQS(Engine): PASS
4922 12:21:07.557557 TX OE : NO K
4923 12:21:07.557637 All Pass.
4924 12:21:07.557700
4925 12:21:07.560926 CH 1, Rank 1
4926 12:21:07.561005 SW Impedance : PASS
4927 12:21:07.563983 DUTY Scan : NO K
4928 12:21:07.567608 ZQ Calibration : PASS
4929 12:21:07.567688 Jitter Meter : NO K
4930 12:21:07.570778 CBT Training : PASS
4931 12:21:07.574110 Write leveling : PASS
4932 12:21:07.574190 RX DQS gating : PASS
4933 12:21:07.577350 RX DQ/DQS(RDDQC) : PASS
4934 12:21:07.580739 TX DQ/DQS : PASS
4935 12:21:07.580819 RX DATLAT : PASS
4936 12:21:07.584026 RX DQ/DQS(Engine): PASS
4937 12:21:07.587550 TX OE : NO K
4938 12:21:07.587630 All Pass.
4939 12:21:07.587693
4940 12:21:07.590264 DramC Write-DBI off
4941 12:21:07.590343 PER_BANK_REFRESH: Hybrid Mode
4942 12:21:07.593840 TX_TRACKING: ON
4943 12:21:07.600517 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4944 12:21:07.607101 [FAST_K] Save calibration result to emmc
4945 12:21:07.610837 dramc_set_vcore_voltage set vcore to 662500
4946 12:21:07.610920 Read voltage for 933, 3
4947 12:21:07.613620 Vio18 = 0
4948 12:21:07.613694 Vcore = 662500
4949 12:21:07.613756 Vdram = 0
4950 12:21:07.616990 Vddq = 0
4951 12:21:07.617067 Vmddr = 0
4952 12:21:07.620581 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4953 12:21:07.626479 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4954 12:21:07.630266 MEM_TYPE=3, freq_sel=17
4955 12:21:07.633445 sv_algorithm_assistance_LP4_1600
4956 12:21:07.636502 ============ PULL DRAM RESETB DOWN ============
4957 12:21:07.640070 ========== PULL DRAM RESETB DOWN end =========
4958 12:21:07.646536 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4959 12:21:07.649958 ===================================
4960 12:21:07.650036 LPDDR4 DRAM CONFIGURATION
4961 12:21:07.653025 ===================================
4962 12:21:07.656206 EX_ROW_EN[0] = 0x0
4963 12:21:07.659532 EX_ROW_EN[1] = 0x0
4964 12:21:07.659604 LP4Y_EN = 0x0
4965 12:21:07.663196 WORK_FSP = 0x0
4966 12:21:07.663274 WL = 0x3
4967 12:21:07.666151 RL = 0x3
4968 12:21:07.666224 BL = 0x2
4969 12:21:07.669926 RPST = 0x0
4970 12:21:07.669998 RD_PRE = 0x0
4971 12:21:07.673020 WR_PRE = 0x1
4972 12:21:07.673091 WR_PST = 0x0
4973 12:21:07.676703 DBI_WR = 0x0
4974 12:21:07.676789 DBI_RD = 0x0
4975 12:21:07.679460 OTF = 0x1
4976 12:21:07.682910 ===================================
4977 12:21:07.686071 ===================================
4978 12:21:07.686143 ANA top config
4979 12:21:07.689404 ===================================
4980 12:21:07.693256 DLL_ASYNC_EN = 0
4981 12:21:07.695930 ALL_SLAVE_EN = 1
4982 12:21:07.696000 NEW_RANK_MODE = 1
4983 12:21:07.699214 DLL_IDLE_MODE = 1
4984 12:21:07.702515 LP45_APHY_COMB_EN = 1
4985 12:21:07.706196 TX_ODT_DIS = 1
4986 12:21:07.709333 NEW_8X_MODE = 1
4987 12:21:07.712618 ===================================
4988 12:21:07.716214 ===================================
4989 12:21:07.719406 data_rate = 1866
4990 12:21:07.719484 CKR = 1
4991 12:21:07.722219 DQ_P2S_RATIO = 8
4992 12:21:07.725568 ===================================
4993 12:21:07.729122 CA_P2S_RATIO = 8
4994 12:21:07.732374 DQ_CA_OPEN = 0
4995 12:21:07.735787 DQ_SEMI_OPEN = 0
4996 12:21:07.739113 CA_SEMI_OPEN = 0
4997 12:21:07.739197 CA_FULL_RATE = 0
4998 12:21:07.742126 DQ_CKDIV4_EN = 1
4999 12:21:07.745690 CA_CKDIV4_EN = 1
5000 12:21:07.748797 CA_PREDIV_EN = 0
5001 12:21:07.753036 PH8_DLY = 0
5002 12:21:07.755710 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5003 12:21:07.755794 DQ_AAMCK_DIV = 4
5004 12:21:07.758546 CA_AAMCK_DIV = 4
5005 12:21:07.761794 CA_ADMCK_DIV = 4
5006 12:21:07.765121 DQ_TRACK_CA_EN = 0
5007 12:21:07.768830 CA_PICK = 933
5008 12:21:07.771791 CA_MCKIO = 933
5009 12:21:07.775198 MCKIO_SEMI = 0
5010 12:21:07.775281 PLL_FREQ = 3732
5011 12:21:07.778849 DQ_UI_PI_RATIO = 32
5012 12:21:07.782142 CA_UI_PI_RATIO = 0
5013 12:21:07.785000 ===================================
5014 12:21:07.788550 ===================================
5015 12:21:07.791992 memory_type:LPDDR4
5016 12:21:07.792075 GP_NUM : 10
5017 12:21:07.794866 SRAM_EN : 1
5018 12:21:07.798444 MD32_EN : 0
5019 12:21:07.802072 ===================================
5020 12:21:07.802156 [ANA_INIT] >>>>>>>>>>>>>>
5021 12:21:07.804879 <<<<<< [CONFIGURE PHASE]: ANA_TX
5022 12:21:07.808246 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5023 12:21:07.811795 ===================================
5024 12:21:07.814801 data_rate = 1866,PCW = 0X8f00
5025 12:21:07.818722 ===================================
5026 12:21:07.821522 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5027 12:21:07.827781 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5028 12:21:07.834521 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5029 12:21:07.837725 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5030 12:21:07.841313 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5031 12:21:07.844567 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5032 12:21:07.848341 [ANA_INIT] flow start
5033 12:21:07.848424 [ANA_INIT] PLL >>>>>>>>
5034 12:21:07.851155 [ANA_INIT] PLL <<<<<<<<
5035 12:21:07.854670 [ANA_INIT] MIDPI >>>>>>>>
5036 12:21:07.854749 [ANA_INIT] MIDPI <<<<<<<<
5037 12:21:07.857682 [ANA_INIT] DLL >>>>>>>>
5038 12:21:07.861166 [ANA_INIT] flow end
5039 12:21:07.864378 ============ LP4 DIFF to SE enter ============
5040 12:21:07.867704 ============ LP4 DIFF to SE exit ============
5041 12:21:07.871124 [ANA_INIT] <<<<<<<<<<<<<
5042 12:21:07.874319 [Flow] Enable top DCM control >>>>>
5043 12:21:07.877996 [Flow] Enable top DCM control <<<<<
5044 12:21:07.880810 Enable DLL master slave shuffle
5045 12:21:07.884347 ==============================================================
5046 12:21:07.887470 Gating Mode config
5047 12:21:07.894328 ==============================================================
5048 12:21:07.894412 Config description:
5049 12:21:07.904415 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5050 12:21:07.910402 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5051 12:21:07.917238 SELPH_MODE 0: By rank 1: By Phase
5052 12:21:07.920345 ==============================================================
5053 12:21:07.923677 GAT_TRACK_EN = 1
5054 12:21:07.927239 RX_GATING_MODE = 2
5055 12:21:07.930087 RX_GATING_TRACK_MODE = 2
5056 12:21:07.933704 SELPH_MODE = 1
5057 12:21:07.936971 PICG_EARLY_EN = 1
5058 12:21:07.940526 VALID_LAT_VALUE = 1
5059 12:21:07.943315 ==============================================================
5060 12:21:07.947389 Enter into Gating configuration >>>>
5061 12:21:07.950782 Exit from Gating configuration <<<<
5062 12:21:07.953433 Enter into DVFS_PRE_config >>>>>
5063 12:21:07.966700 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5064 12:21:07.970210 Exit from DVFS_PRE_config <<<<<
5065 12:21:07.973464 Enter into PICG configuration >>>>
5066 12:21:07.976626 Exit from PICG configuration <<<<
5067 12:21:07.976708 [RX_INPUT] configuration >>>>>
5068 12:21:07.980058 [RX_INPUT] configuration <<<<<
5069 12:21:07.986951 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5070 12:21:07.989840 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5071 12:21:07.996418 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5072 12:21:08.003314 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5073 12:21:08.010313 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5074 12:21:08.016918 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5075 12:21:08.019534 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5076 12:21:08.023040 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5077 12:21:08.029797 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5078 12:21:08.033096 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5079 12:21:08.036043 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5080 12:21:08.042440 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5081 12:21:08.045723 ===================================
5082 12:21:08.045805 LPDDR4 DRAM CONFIGURATION
5083 12:21:08.049107 ===================================
5084 12:21:08.052621 EX_ROW_EN[0] = 0x0
5085 12:21:08.052703 EX_ROW_EN[1] = 0x0
5086 12:21:08.056348 LP4Y_EN = 0x0
5087 12:21:08.056430 WORK_FSP = 0x0
5088 12:21:08.059445 WL = 0x3
5089 12:21:08.059526 RL = 0x3
5090 12:21:08.062548 BL = 0x2
5091 12:21:08.065481 RPST = 0x0
5092 12:21:08.065562 RD_PRE = 0x0
5093 12:21:08.068786 WR_PRE = 0x1
5094 12:21:08.068868 WR_PST = 0x0
5095 12:21:08.072370 DBI_WR = 0x0
5096 12:21:08.072451 DBI_RD = 0x0
5097 12:21:08.075935 OTF = 0x1
5098 12:21:08.078855 ===================================
5099 12:21:08.082316 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5100 12:21:08.085577 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5101 12:21:08.088841 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5102 12:21:08.092526 ===================================
5103 12:21:08.095651 LPDDR4 DRAM CONFIGURATION
5104 12:21:08.098895 ===================================
5105 12:21:08.102172 EX_ROW_EN[0] = 0x10
5106 12:21:08.102254 EX_ROW_EN[1] = 0x0
5107 12:21:08.105950 LP4Y_EN = 0x0
5108 12:21:08.106032 WORK_FSP = 0x0
5109 12:21:08.108806 WL = 0x3
5110 12:21:08.108887 RL = 0x3
5111 12:21:08.112210 BL = 0x2
5112 12:21:08.115353 RPST = 0x0
5113 12:21:08.115460 RD_PRE = 0x0
5114 12:21:08.119092 WR_PRE = 0x1
5115 12:21:08.119174 WR_PST = 0x0
5116 12:21:08.122268 DBI_WR = 0x0
5117 12:21:08.122349 DBI_RD = 0x0
5118 12:21:08.125424 OTF = 0x1
5119 12:21:08.128771 ===================================
5120 12:21:08.135528 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5121 12:21:08.138901 nWR fixed to 30
5122 12:21:08.138984 [ModeRegInit_LP4] CH0 RK0
5123 12:21:08.141821 [ModeRegInit_LP4] CH0 RK1
5124 12:21:08.145370 [ModeRegInit_LP4] CH1 RK0
5125 12:21:08.145451 [ModeRegInit_LP4] CH1 RK1
5126 12:21:08.148571 match AC timing 9
5127 12:21:08.151389 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5128 12:21:08.154827 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5129 12:21:08.161529 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5130 12:21:08.164979 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5131 12:21:08.171262 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5132 12:21:08.171344 ==
5133 12:21:08.174562 Dram Type= 6, Freq= 0, CH_0, rank 0
5134 12:21:08.177881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 12:21:08.177964 ==
5136 12:21:08.184402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5137 12:21:08.190747 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5138 12:21:08.194640 [CA 0] Center 37 (7~68) winsize 62
5139 12:21:08.198023 [CA 1] Center 37 (7~68) winsize 62
5140 12:21:08.201157 [CA 2] Center 34 (4~65) winsize 62
5141 12:21:08.204178 [CA 3] Center 34 (4~65) winsize 62
5142 12:21:08.207550 [CA 4] Center 33 (3~64) winsize 62
5143 12:21:08.211004 [CA 5] Center 33 (3~63) winsize 61
5144 12:21:08.211085
5145 12:21:08.214083 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5146 12:21:08.214164
5147 12:21:08.217234 [CATrainingPosCal] consider 1 rank data
5148 12:21:08.220692 u2DelayCellTimex100 = 270/100 ps
5149 12:21:08.224160 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5150 12:21:08.227416 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5151 12:21:08.230668 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5152 12:21:08.234446 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5153 12:21:08.237262 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5154 12:21:08.240630 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5155 12:21:08.240714
5156 12:21:08.247633 CA PerBit enable=1, Macro0, CA PI delay=33
5157 12:21:08.247718
5158 12:21:08.250207 [CBTSetCACLKResult] CA Dly = 33
5159 12:21:08.250288 CS Dly: 7 (0~38)
5160 12:21:08.250361 ==
5161 12:21:08.253805 Dram Type= 6, Freq= 0, CH_0, rank 1
5162 12:21:08.257011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 12:21:08.257084 ==
5164 12:21:08.264171 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5165 12:21:08.270753 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5166 12:21:08.273384 [CA 0] Center 37 (7~68) winsize 62
5167 12:21:08.276976 [CA 1] Center 37 (7~68) winsize 62
5168 12:21:08.279964 [CA 2] Center 34 (4~65) winsize 62
5169 12:21:08.283642 [CA 3] Center 34 (4~65) winsize 62
5170 12:21:08.286755 [CA 4] Center 33 (3~64) winsize 62
5171 12:21:08.290110 [CA 5] Center 33 (3~63) winsize 61
5172 12:21:08.290192
5173 12:21:08.293209 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5174 12:21:08.293290
5175 12:21:08.296759 [CATrainingPosCal] consider 2 rank data
5176 12:21:08.300176 u2DelayCellTimex100 = 270/100 ps
5177 12:21:08.303591 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5178 12:21:08.306164 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5179 12:21:08.309917 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5180 12:21:08.312871 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5181 12:21:08.319723 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5182 12:21:08.322932 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5183 12:21:08.323013
5184 12:21:08.326273 CA PerBit enable=1, Macro0, CA PI delay=33
5185 12:21:08.326354
5186 12:21:08.329426 [CBTSetCACLKResult] CA Dly = 33
5187 12:21:08.329508 CS Dly: 7 (0~39)
5188 12:21:08.329571
5189 12:21:08.332519 ----->DramcWriteLeveling(PI) begin...
5190 12:21:08.332602 ==
5191 12:21:08.336054 Dram Type= 6, Freq= 0, CH_0, rank 0
5192 12:21:08.342428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5193 12:21:08.342536 ==
5194 12:21:08.345600 Write leveling (Byte 0): 31 => 31
5195 12:21:08.349477 Write leveling (Byte 1): 29 => 29
5196 12:21:08.353104 DramcWriteLeveling(PI) end<-----
5197 12:21:08.353186
5198 12:21:08.353250 ==
5199 12:21:08.355769 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 12:21:08.359118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 12:21:08.359195 ==
5202 12:21:08.362087 [Gating] SW mode calibration
5203 12:21:08.369122 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5204 12:21:08.375756 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5205 12:21:08.378760 0 14 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5206 12:21:08.381923 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
5207 12:21:08.388529 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5208 12:21:08.392301 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5209 12:21:08.395344 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5210 12:21:08.401639 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5211 12:21:08.405026 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5212 12:21:08.408135 0 14 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5213 12:21:08.415246 0 15 0 | B1->B0 | 3333 2424 | 1 1 | (1 0) (1 0)
5214 12:21:08.418267 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5215 12:21:08.421389 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5216 12:21:08.428712 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5217 12:21:08.431704 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5218 12:21:08.434673 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5219 12:21:08.441192 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5220 12:21:08.444767 0 15 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5221 12:21:08.447751 1 0 0 | B1->B0 | 3333 4444 | 0 0 | (1 1) (0 0)
5222 12:21:08.455122 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5223 12:21:08.457789 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5224 12:21:08.461365 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5225 12:21:08.467745 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5226 12:21:08.471141 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5227 12:21:08.474057 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5228 12:21:08.481055 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5229 12:21:08.483983 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5230 12:21:08.487351 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 12:21:08.494084 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 12:21:08.497278 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 12:21:08.500916 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 12:21:08.507240 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 12:21:08.510362 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 12:21:08.514257 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 12:21:08.520161 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 12:21:08.523711 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 12:21:08.527194 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 12:21:08.533766 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 12:21:08.536533 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 12:21:08.540336 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 12:21:08.546759 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 12:21:08.550144 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5245 12:21:08.553754 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5246 12:21:08.556603 Total UI for P1: 0, mck2ui 16
5247 12:21:08.559901 best dqsien dly found for B0: ( 1, 2, 28)
5248 12:21:08.566844 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5249 12:21:08.566919 Total UI for P1: 0, mck2ui 16
5250 12:21:08.569905 best dqsien dly found for B1: ( 1, 3, 0)
5251 12:21:08.576548 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5252 12:21:08.579478 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5253 12:21:08.579561
5254 12:21:08.582822 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5255 12:21:08.586394 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5256 12:21:08.589770 [Gating] SW calibration Done
5257 12:21:08.589850 ==
5258 12:21:08.592682 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 12:21:08.596118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 12:21:08.596189 ==
5261 12:21:08.599667 RX Vref Scan: 0
5262 12:21:08.599737
5263 12:21:08.599797 RX Vref 0 -> 0, step: 1
5264 12:21:08.599854
5265 12:21:08.602904 RX Delay -80 -> 252, step: 8
5266 12:21:08.606213 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5267 12:21:08.612390 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5268 12:21:08.615826 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5269 12:21:08.619083 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5270 12:21:08.622775 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5271 12:21:08.625717 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5272 12:21:08.629085 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5273 12:21:08.635808 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5274 12:21:08.638996 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5275 12:21:08.642242 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5276 12:21:08.645715 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5277 12:21:08.649306 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5278 12:21:08.655572 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5279 12:21:08.659019 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5280 12:21:08.662285 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5281 12:21:08.665071 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5282 12:21:08.665153 ==
5283 12:21:08.668650 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 12:21:08.675557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 12:21:08.675640 ==
5286 12:21:08.675705 DQS Delay:
5287 12:21:08.675765 DQS0 = 0, DQS1 = 0
5288 12:21:08.678996 DQM Delay:
5289 12:21:08.679078 DQM0 = 96, DQM1 = 86
5290 12:21:08.681928 DQ Delay:
5291 12:21:08.684909 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5292 12:21:08.688277 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5293 12:21:08.691792 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5294 12:21:08.694985 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5295 12:21:08.695066
5296 12:21:08.695140
5297 12:21:08.695202 ==
5298 12:21:08.698372 Dram Type= 6, Freq= 0, CH_0, rank 0
5299 12:21:08.701419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 12:21:08.701501 ==
5301 12:21:08.701566
5302 12:21:08.701626
5303 12:21:08.705310 TX Vref Scan disable
5304 12:21:08.705392 == TX Byte 0 ==
5305 12:21:08.711419 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5306 12:21:08.714559 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5307 12:21:08.718510 == TX Byte 1 ==
5308 12:21:08.721487 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5309 12:21:08.724614 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5310 12:21:08.724687 ==
5311 12:21:08.727770 Dram Type= 6, Freq= 0, CH_0, rank 0
5312 12:21:08.730990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 12:21:08.734363 ==
5314 12:21:08.734438
5315 12:21:08.734500
5316 12:21:08.734584 TX Vref Scan disable
5317 12:21:08.737870 == TX Byte 0 ==
5318 12:21:08.741313 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5319 12:21:08.744978 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5320 12:21:08.748085 == TX Byte 1 ==
5321 12:21:08.751255 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5322 12:21:08.757981 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5323 12:21:08.758064
5324 12:21:08.758128 [DATLAT]
5325 12:21:08.758188 Freq=933, CH0 RK0
5326 12:21:08.758246
5327 12:21:08.761577 DATLAT Default: 0xd
5328 12:21:08.761646 0, 0xFFFF, sum = 0
5329 12:21:08.764437 1, 0xFFFF, sum = 0
5330 12:21:08.767959 2, 0xFFFF, sum = 0
5331 12:21:08.768031 3, 0xFFFF, sum = 0
5332 12:21:08.771585 4, 0xFFFF, sum = 0
5333 12:21:08.771661 5, 0xFFFF, sum = 0
5334 12:21:08.774567 6, 0xFFFF, sum = 0
5335 12:21:08.774694 7, 0xFFFF, sum = 0
5336 12:21:08.777724 8, 0xFFFF, sum = 0
5337 12:21:08.777799 9, 0xFFFF, sum = 0
5338 12:21:08.781131 10, 0x0, sum = 1
5339 12:21:08.781208 11, 0x0, sum = 2
5340 12:21:08.784604 12, 0x0, sum = 3
5341 12:21:08.784680 13, 0x0, sum = 4
5342 12:21:08.784743 best_step = 11
5343 12:21:08.787505
5344 12:21:08.787577 ==
5345 12:21:08.790940 Dram Type= 6, Freq= 0, CH_0, rank 0
5346 12:21:08.794405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 12:21:08.794505 ==
5348 12:21:08.794599 RX Vref Scan: 1
5349 12:21:08.794679
5350 12:21:08.797532 RX Vref 0 -> 0, step: 1
5351 12:21:08.797606
5352 12:21:08.800507 RX Delay -61 -> 252, step: 4
5353 12:21:08.800576
5354 12:21:08.804291 Set Vref, RX VrefLevel [Byte0]: 60
5355 12:21:08.807638 [Byte1]: 58
5356 12:21:08.810689
5357 12:21:08.810765 Final RX Vref Byte 0 = 60 to rank0
5358 12:21:08.814135 Final RX Vref Byte 1 = 58 to rank0
5359 12:21:08.817079 Final RX Vref Byte 0 = 60 to rank1
5360 12:21:08.820237 Final RX Vref Byte 1 = 58 to rank1==
5361 12:21:08.823528 Dram Type= 6, Freq= 0, CH_0, rank 0
5362 12:21:08.830111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 12:21:08.830187 ==
5364 12:21:08.830248 DQS Delay:
5365 12:21:08.833359 DQS0 = 0, DQS1 = 0
5366 12:21:08.833424 DQM Delay:
5367 12:21:08.833482 DQM0 = 96, DQM1 = 87
5368 12:21:08.837174 DQ Delay:
5369 12:21:08.840463 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5370 12:21:08.843601 DQ4 =96, DQ5 =88, DQ6 =106, DQ7 =106
5371 12:21:08.846913 DQ8 =80, DQ9 =78, DQ10 =86, DQ11 =82
5372 12:21:08.849959 DQ12 =94, DQ13 =88, DQ14 =100, DQ15 =94
5373 12:21:08.850025
5374 12:21:08.850084
5375 12:21:08.857123 [DQSOSCAuto] RK0, (LSB)MR18= 0x290f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5376 12:21:08.859824 CH0 RK0: MR19=505, MR18=290F
5377 12:21:08.866493 CH0_RK0: MR19=0x505, MR18=0x290F, DQSOSC=408, MR23=63, INC=65, DEC=43
5378 12:21:08.866575
5379 12:21:08.869578 ----->DramcWriteLeveling(PI) begin...
5380 12:21:08.869660 ==
5381 12:21:08.873013 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 12:21:08.876249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 12:21:08.876330 ==
5384 12:21:08.879717 Write leveling (Byte 0): 36 => 36
5385 12:21:08.883183 Write leveling (Byte 1): 32 => 32
5386 12:21:08.886632 DramcWriteLeveling(PI) end<-----
5387 12:21:08.886730
5388 12:21:08.886796 ==
5389 12:21:08.890020 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 12:21:08.896052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 12:21:08.896135 ==
5392 12:21:08.896199 [Gating] SW mode calibration
5393 12:21:08.906192 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5394 12:21:08.909573 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5395 12:21:08.912534 0 14 0 | B1->B0 | 2929 3333 | 1 0 | (0 0) (0 0)
5396 12:21:08.919665 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5397 12:21:08.922376 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5398 12:21:08.925986 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5399 12:21:08.932538 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5400 12:21:08.935873 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5401 12:21:08.939140 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5402 12:21:08.945589 0 14 28 | B1->B0 | 3333 2d2d | 0 0 | (0 0) (0 0)
5403 12:21:08.949104 0 15 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5404 12:21:08.952200 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5405 12:21:08.958912 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5406 12:21:08.962418 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5407 12:21:08.965560 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5408 12:21:08.972059 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5409 12:21:08.975604 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5410 12:21:08.978703 0 15 28 | B1->B0 | 2727 3737 | 1 1 | (0 0) (0 0)
5411 12:21:08.985005 1 0 0 | B1->B0 | 3e3e 4444 | 0 0 | (0 0) (0 0)
5412 12:21:08.988508 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5413 12:21:08.992468 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5414 12:21:08.998563 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5415 12:21:09.001714 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 12:21:09.004955 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5417 12:21:09.011567 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5418 12:21:09.014999 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5419 12:21:09.018090 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5420 12:21:09.025417 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5421 12:21:09.028125 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 12:21:09.031425 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 12:21:09.038047 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 12:21:09.041365 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 12:21:09.044991 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 12:21:09.051323 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 12:21:09.054878 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 12:21:09.057893 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 12:21:09.064860 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 12:21:09.068279 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 12:21:09.071104 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 12:21:09.078041 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 12:21:09.081905 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 12:21:09.084167 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5435 12:21:09.091145 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5436 12:21:09.094272 Total UI for P1: 0, mck2ui 16
5437 12:21:09.098037 best dqsien dly found for B0: ( 1, 2, 28)
5438 12:21:09.100917 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5439 12:21:09.104242 Total UI for P1: 0, mck2ui 16
5440 12:21:09.107307 best dqsien dly found for B1: ( 1, 3, 0)
5441 12:21:09.110885 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5442 12:21:09.114168 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5443 12:21:09.114241
5444 12:21:09.117520 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5445 12:21:09.120597 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5446 12:21:09.123941 [Gating] SW calibration Done
5447 12:21:09.124025 ==
5448 12:21:09.126947 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 12:21:09.133471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 12:21:09.133548 ==
5451 12:21:09.133612 RX Vref Scan: 0
5452 12:21:09.133672
5453 12:21:09.136801 RX Vref 0 -> 0, step: 1
5454 12:21:09.136870
5455 12:21:09.140101 RX Delay -80 -> 252, step: 8
5456 12:21:09.143551 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5457 12:21:09.146752 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5458 12:21:09.149931 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5459 12:21:09.153757 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5460 12:21:09.160003 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5461 12:21:09.163396 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5462 12:21:09.166641 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5463 12:21:09.169643 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5464 12:21:09.173292 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5465 12:21:09.176715 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5466 12:21:09.183615 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5467 12:21:09.186882 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5468 12:21:09.189831 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5469 12:21:09.193531 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5470 12:21:09.196443 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5471 12:21:09.202562 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5472 12:21:09.202694 ==
5473 12:21:09.205929 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 12:21:09.209300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 12:21:09.209376 ==
5476 12:21:09.209438 DQS Delay:
5477 12:21:09.213468 DQS0 = 0, DQS1 = 0
5478 12:21:09.213542 DQM Delay:
5479 12:21:09.215717 DQM0 = 96, DQM1 = 89
5480 12:21:09.215790 DQ Delay:
5481 12:21:09.219296 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5482 12:21:09.222624 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5483 12:21:09.226219 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5484 12:21:09.229122 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5485 12:21:09.229197
5486 12:21:09.229257
5487 12:21:09.229315 ==
5488 12:21:09.232538 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 12:21:09.235968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 12:21:09.239327 ==
5491 12:21:09.239424
5492 12:21:09.239496
5493 12:21:09.239554 TX Vref Scan disable
5494 12:21:09.242537 == TX Byte 0 ==
5495 12:21:09.246190 Update DQ dly =720 (2 ,6, 16) DQ OEN =(2 ,3)
5496 12:21:09.249188 Update DQM dly =720 (2 ,6, 16) DQM OEN =(2 ,3)
5497 12:21:09.252798 == TX Byte 1 ==
5498 12:21:09.256375 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5499 12:21:09.259264 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5500 12:21:09.262350 ==
5501 12:21:09.265933 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 12:21:09.269171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 12:21:09.269240 ==
5504 12:21:09.269300
5505 12:21:09.269366
5506 12:21:09.272449 TX Vref Scan disable
5507 12:21:09.272514 == TX Byte 0 ==
5508 12:21:09.279080 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5509 12:21:09.282408 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5510 12:21:09.282479 == TX Byte 1 ==
5511 12:21:09.288865 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5512 12:21:09.292240 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5513 12:21:09.292317
5514 12:21:09.292379 [DATLAT]
5515 12:21:09.295324 Freq=933, CH0 RK1
5516 12:21:09.295398
5517 12:21:09.295459 DATLAT Default: 0xb
5518 12:21:09.298825 0, 0xFFFF, sum = 0
5519 12:21:09.298899 1, 0xFFFF, sum = 0
5520 12:21:09.302286 2, 0xFFFF, sum = 0
5521 12:21:09.305525 3, 0xFFFF, sum = 0
5522 12:21:09.305594 4, 0xFFFF, sum = 0
5523 12:21:09.308562 5, 0xFFFF, sum = 0
5524 12:21:09.308631 6, 0xFFFF, sum = 0
5525 12:21:09.311883 7, 0xFFFF, sum = 0
5526 12:21:09.311951 8, 0xFFFF, sum = 0
5527 12:21:09.315134 9, 0xFFFF, sum = 0
5528 12:21:09.315204 10, 0x0, sum = 1
5529 12:21:09.318626 11, 0x0, sum = 2
5530 12:21:09.318710 12, 0x0, sum = 3
5531 12:21:09.321560 13, 0x0, sum = 4
5532 12:21:09.321642 best_step = 11
5533 12:21:09.321707
5534 12:21:09.321771 ==
5535 12:21:09.328893 Dram Type= 6, Freq= 0, CH_0, rank 1
5536 12:21:09.328972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 12:21:09.329035 ==
5538 12:21:09.331464 RX Vref Scan: 0
5539 12:21:09.331541
5540 12:21:09.335312 RX Vref 0 -> 0, step: 1
5541 12:21:09.335385
5542 12:21:09.335450 RX Delay -61 -> 252, step: 4
5543 12:21:09.342892 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5544 12:21:09.346033 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5545 12:21:09.349367 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5546 12:21:09.352524 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5547 12:21:09.356407 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5548 12:21:09.362934 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5549 12:21:09.365555 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5550 12:21:09.369338 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5551 12:21:09.372393 iDelay=203, Bit 8, Center 82 (-9 ~ 174) 184
5552 12:21:09.375974 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5553 12:21:09.382755 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5554 12:21:09.385551 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5555 12:21:09.389332 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5556 12:21:09.392124 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5557 12:21:09.395772 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5558 12:21:09.398754 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5559 12:21:09.402003 ==
5560 12:21:09.405782 Dram Type= 6, Freq= 0, CH_0, rank 1
5561 12:21:09.408599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 12:21:09.408674 ==
5563 12:21:09.408736 DQS Delay:
5564 12:21:09.412058 DQS0 = 0, DQS1 = 0
5565 12:21:09.412127 DQM Delay:
5566 12:21:09.415718 DQM0 = 95, DQM1 = 88
5567 12:21:09.415784 DQ Delay:
5568 12:21:09.418478 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94
5569 12:21:09.421735 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5570 12:21:09.425204 DQ8 =82, DQ9 =78, DQ10 =90, DQ11 =82
5571 12:21:09.428430 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =94
5572 12:21:09.428503
5573 12:21:09.428568
5574 12:21:09.435306 [DQSOSCAuto] RK1, (LSB)MR18= 0x25f5, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 410 ps
5575 12:21:09.438468 CH0 RK1: MR19=504, MR18=25F5
5576 12:21:09.445211 CH0_RK1: MR19=0x504, MR18=0x25F5, DQSOSC=410, MR23=63, INC=64, DEC=42
5577 12:21:09.448621 [RxdqsGatingPostProcess] freq 933
5578 12:21:09.455302 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5579 12:21:09.458218 best DQS0 dly(2T, 0.5T) = (0, 10)
5580 12:21:09.458289 best DQS1 dly(2T, 0.5T) = (0, 11)
5581 12:21:09.461989 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5582 12:21:09.465053 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5583 12:21:09.468196 best DQS0 dly(2T, 0.5T) = (0, 10)
5584 12:21:09.471706 best DQS1 dly(2T, 0.5T) = (0, 11)
5585 12:21:09.475395 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5586 12:21:09.478120 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5587 12:21:09.481734 Pre-setting of DQS Precalculation
5588 12:21:09.487931 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5589 12:21:09.488008 ==
5590 12:21:09.491905 Dram Type= 6, Freq= 0, CH_1, rank 0
5591 12:21:09.495208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5592 12:21:09.495280 ==
5593 12:21:09.501702 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5594 12:21:09.508053 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5595 12:21:09.510941 [CA 0] Center 36 (6~67) winsize 62
5596 12:21:09.515104 [CA 1] Center 36 (6~67) winsize 62
5597 12:21:09.517501 [CA 2] Center 34 (4~65) winsize 62
5598 12:21:09.520808 [CA 3] Center 33 (3~64) winsize 62
5599 12:21:09.524729 [CA 4] Center 34 (4~64) winsize 61
5600 12:21:09.524805 [CA 5] Center 33 (3~64) winsize 62
5601 12:21:09.527602
5602 12:21:09.530755 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5603 12:21:09.530824
5604 12:21:09.534063 [CATrainingPosCal] consider 1 rank data
5605 12:21:09.537851 u2DelayCellTimex100 = 270/100 ps
5606 12:21:09.541030 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5607 12:21:09.544897 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5608 12:21:09.547195 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5609 12:21:09.550826 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5610 12:21:09.554079 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5611 12:21:09.557535 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5612 12:21:09.557605
5613 12:21:09.563910 CA PerBit enable=1, Macro0, CA PI delay=33
5614 12:21:09.563986
5615 12:21:09.564047 [CBTSetCACLKResult] CA Dly = 33
5616 12:21:09.567232 CS Dly: 5 (0~36)
5617 12:21:09.567300 ==
5618 12:21:09.570625 Dram Type= 6, Freq= 0, CH_1, rank 1
5619 12:21:09.573372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5620 12:21:09.573442 ==
5621 12:21:09.580537 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5622 12:21:09.587106 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5623 12:21:09.590029 [CA 0] Center 36 (6~67) winsize 62
5624 12:21:09.593342 [CA 1] Center 37 (7~67) winsize 61
5625 12:21:09.596920 [CA 2] Center 34 (4~65) winsize 62
5626 12:21:09.600201 [CA 3] Center 33 (3~64) winsize 62
5627 12:21:09.603128 [CA 4] Center 34 (3~65) winsize 63
5628 12:21:09.606744 [CA 5] Center 33 (3~64) winsize 62
5629 12:21:09.606818
5630 12:21:09.609786 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5631 12:21:09.609856
5632 12:21:09.612983 [CATrainingPosCal] consider 2 rank data
5633 12:21:09.616297 u2DelayCellTimex100 = 270/100 ps
5634 12:21:09.619947 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5635 12:21:09.623453 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5636 12:21:09.626314 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5637 12:21:09.629437 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5638 12:21:09.636005 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5639 12:21:09.639236 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5640 12:21:09.639308
5641 12:21:09.642752 CA PerBit enable=1, Macro0, CA PI delay=33
5642 12:21:09.642831
5643 12:21:09.646111 [CBTSetCACLKResult] CA Dly = 33
5644 12:21:09.646182 CS Dly: 6 (0~39)
5645 12:21:09.646241
5646 12:21:09.649597 ----->DramcWriteLeveling(PI) begin...
5647 12:21:09.649672 ==
5648 12:21:09.652702 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 12:21:09.659535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 12:21:09.659615 ==
5651 12:21:09.662398 Write leveling (Byte 0): 25 => 25
5652 12:21:09.666267 Write leveling (Byte 1): 26 => 26
5653 12:21:09.666338 DramcWriteLeveling(PI) end<-----
5654 12:21:09.666398
5655 12:21:09.669172 ==
5656 12:21:09.672189 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 12:21:09.675931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 12:21:09.676004 ==
5659 12:21:09.679246 [Gating] SW mode calibration
5660 12:21:09.685696 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5661 12:21:09.688763 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5662 12:21:09.695915 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5663 12:21:09.698568 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5664 12:21:09.701986 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5665 12:21:09.708764 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5666 12:21:09.711670 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5667 12:21:09.715026 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5668 12:21:09.722002 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5669 12:21:09.725235 0 14 28 | B1->B0 | 2e2e 2a2a | 0 0 | (0 0) (0 0)
5670 12:21:09.728532 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5671 12:21:09.734896 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5672 12:21:09.738076 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5673 12:21:09.741771 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5674 12:21:09.748243 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5675 12:21:09.751371 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5676 12:21:09.754490 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5677 12:21:09.761340 0 15 28 | B1->B0 | 3939 3e3e | 1 1 | (0 0) (0 0)
5678 12:21:09.764758 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 12:21:09.767810 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5680 12:21:09.774409 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5681 12:21:09.778017 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 12:21:09.781338 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5683 12:21:09.787617 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5684 12:21:09.791098 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5685 12:21:09.794210 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 12:21:09.801445 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 12:21:09.804344 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 12:21:09.807570 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 12:21:09.814298 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 12:21:09.817872 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 12:21:09.820764 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 12:21:09.827423 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 12:21:09.830623 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 12:21:09.833777 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 12:21:09.840486 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 12:21:09.844058 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 12:21:09.847218 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 12:21:09.853468 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 12:21:09.857154 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 12:21:09.860229 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5701 12:21:09.866914 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5702 12:21:09.870511 Total UI for P1: 0, mck2ui 16
5703 12:21:09.873498 best dqsien dly found for B0: ( 1, 2, 24)
5704 12:21:09.876762 Total UI for P1: 0, mck2ui 16
5705 12:21:09.880242 best dqsien dly found for B1: ( 1, 2, 24)
5706 12:21:09.883984 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5707 12:21:09.887188 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5708 12:21:09.887261
5709 12:21:09.890680 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5710 12:21:09.893176 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5711 12:21:09.896729 [Gating] SW calibration Done
5712 12:21:09.896801 ==
5713 12:21:09.900008 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 12:21:09.903098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 12:21:09.903171 ==
5716 12:21:09.906732 RX Vref Scan: 0
5717 12:21:09.906814
5718 12:21:09.910338 RX Vref 0 -> 0, step: 1
5719 12:21:09.910419
5720 12:21:09.910482 RX Delay -80 -> 252, step: 8
5721 12:21:09.916544 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5722 12:21:09.919768 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5723 12:21:09.923525 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5724 12:21:09.926174 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5725 12:21:09.929592 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5726 12:21:09.933233 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5727 12:21:09.939825 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5728 12:21:09.942828 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5729 12:21:09.946370 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5730 12:21:09.949590 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5731 12:21:09.952697 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5732 12:21:09.959685 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5733 12:21:09.962643 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5734 12:21:09.965849 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5735 12:21:09.969964 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5736 12:21:09.972970 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5737 12:21:09.973096 ==
5738 12:21:09.975718 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 12:21:09.982565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 12:21:09.982719 ==
5741 12:21:09.982811 DQS Delay:
5742 12:21:09.985763 DQS0 = 0, DQS1 = 0
5743 12:21:09.985872 DQM Delay:
5744 12:21:09.989146 DQM0 = 103, DQM1 = 92
5745 12:21:09.989246 DQ Delay:
5746 12:21:09.992876 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =103
5747 12:21:09.995747 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5748 12:21:09.999062 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5749 12:21:10.002480 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5750 12:21:10.002578
5751 12:21:10.002706
5752 12:21:10.002767 ==
5753 12:21:10.005697 Dram Type= 6, Freq= 0, CH_1, rank 0
5754 12:21:10.008961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 12:21:10.009037 ==
5756 12:21:10.009107
5757 12:21:10.012051
5758 12:21:10.012118 TX Vref Scan disable
5759 12:21:10.016032 == TX Byte 0 ==
5760 12:21:10.019028 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5761 12:21:10.022487 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5762 12:21:10.025620 == TX Byte 1 ==
5763 12:21:10.028943 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5764 12:21:10.032150 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5765 12:21:10.032221 ==
5766 12:21:10.035348 Dram Type= 6, Freq= 0, CH_1, rank 0
5767 12:21:10.042237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 12:21:10.042311 ==
5769 12:21:10.042379
5770 12:21:10.042437
5771 12:21:10.044950 TX Vref Scan disable
5772 12:21:10.045016 == TX Byte 0 ==
5773 12:21:10.051753 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5774 12:21:10.055191 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5775 12:21:10.055266 == TX Byte 1 ==
5776 12:21:10.061608 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5777 12:21:10.064867 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5778 12:21:10.064942
5779 12:21:10.065005 [DATLAT]
5780 12:21:10.068147 Freq=933, CH1 RK0
5781 12:21:10.068218
5782 12:21:10.068285 DATLAT Default: 0xd
5783 12:21:10.071657 0, 0xFFFF, sum = 0
5784 12:21:10.071735 1, 0xFFFF, sum = 0
5785 12:21:10.075165 2, 0xFFFF, sum = 0
5786 12:21:10.075232 3, 0xFFFF, sum = 0
5787 12:21:10.078243 4, 0xFFFF, sum = 0
5788 12:21:10.078309 5, 0xFFFF, sum = 0
5789 12:21:10.081211 6, 0xFFFF, sum = 0
5790 12:21:10.081285 7, 0xFFFF, sum = 0
5791 12:21:10.084645 8, 0xFFFF, sum = 0
5792 12:21:10.088134 9, 0xFFFF, sum = 0
5793 12:21:10.088213 10, 0x0, sum = 1
5794 12:21:10.088278 11, 0x0, sum = 2
5795 12:21:10.091685 12, 0x0, sum = 3
5796 12:21:10.091759 13, 0x0, sum = 4
5797 12:21:10.094469 best_step = 11
5798 12:21:10.094538
5799 12:21:10.094623 ==
5800 12:21:10.097934 Dram Type= 6, Freq= 0, CH_1, rank 0
5801 12:21:10.101069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 12:21:10.101156 ==
5803 12:21:10.104072 RX Vref Scan: 1
5804 12:21:10.104141
5805 12:21:10.107538 RX Vref 0 -> 0, step: 1
5806 12:21:10.107609
5807 12:21:10.107670 RX Delay -61 -> 252, step: 4
5808 12:21:10.107736
5809 12:21:10.111167 Set Vref, RX VrefLevel [Byte0]: 52
5810 12:21:10.114477 [Byte1]: 56
5811 12:21:10.118625
5812 12:21:10.118716 Final RX Vref Byte 0 = 52 to rank0
5813 12:21:10.122311 Final RX Vref Byte 1 = 56 to rank0
5814 12:21:10.125484 Final RX Vref Byte 0 = 52 to rank1
5815 12:21:10.128763 Final RX Vref Byte 1 = 56 to rank1==
5816 12:21:10.131861 Dram Type= 6, Freq= 0, CH_1, rank 0
5817 12:21:10.139004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 12:21:10.139084 ==
5819 12:21:10.139146 DQS Delay:
5820 12:21:10.142052 DQS0 = 0, DQS1 = 0
5821 12:21:10.142119 DQM Delay:
5822 12:21:10.142177 DQM0 = 100, DQM1 = 94
5823 12:21:10.145719 DQ Delay:
5824 12:21:10.149028 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =98
5825 12:21:10.151599 DQ4 =98, DQ5 =110, DQ6 =110, DQ7 =96
5826 12:21:10.155184 DQ8 =84, DQ9 =86, DQ10 =94, DQ11 =84
5827 12:21:10.158742 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =102
5828 12:21:10.158817
5829 12:21:10.158879
5830 12:21:10.165069 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5831 12:21:10.168539 CH1 RK0: MR19=505, MR18=1B0B
5832 12:21:10.174989 CH1_RK0: MR19=0x505, MR18=0x1B0B, DQSOSC=413, MR23=63, INC=63, DEC=42
5833 12:21:10.175063
5834 12:21:10.178224 ----->DramcWriteLeveling(PI) begin...
5835 12:21:10.178318 ==
5836 12:21:10.181526 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 12:21:10.184979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 12:21:10.185052 ==
5839 12:21:10.188235 Write leveling (Byte 0): 29 => 29
5840 12:21:10.191064 Write leveling (Byte 1): 29 => 29
5841 12:21:10.194805 DramcWriteLeveling(PI) end<-----
5842 12:21:10.194882
5843 12:21:10.194946 ==
5844 12:21:10.197793 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 12:21:10.204708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 12:21:10.204784 ==
5847 12:21:10.204846 [Gating] SW mode calibration
5848 12:21:10.214764 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5849 12:21:10.217735 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5850 12:21:10.224266 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5851 12:21:10.227540 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5852 12:21:10.230874 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5853 12:21:10.237211 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5854 12:21:10.240500 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5855 12:21:10.243961 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5856 12:21:10.250645 0 14 24 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 1)
5857 12:21:10.254036 0 14 28 | B1->B0 | 2929 3030 | 0 1 | (1 0) (1 0)
5858 12:21:10.256930 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5859 12:21:10.263509 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5860 12:21:10.266905 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5861 12:21:10.270420 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5862 12:21:10.276761 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5863 12:21:10.279886 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5864 12:21:10.283218 0 15 24 | B1->B0 | 2929 2626 | 0 0 | (0 0) (0 0)
5865 12:21:10.290087 0 15 28 | B1->B0 | 4646 3333 | 0 0 | (0 0) (0 0)
5866 12:21:10.293335 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 12:21:10.296586 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5868 12:21:10.303337 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5869 12:21:10.306469 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 12:21:10.310149 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5871 12:21:10.316345 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5872 12:21:10.319649 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5873 12:21:10.322752 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5874 12:21:10.329276 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 12:21:10.332721 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 12:21:10.336432 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 12:21:10.343050 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 12:21:10.345971 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 12:21:10.348817 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 12:21:10.355498 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 12:21:10.358843 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 12:21:10.362195 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 12:21:10.368899 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 12:21:10.372333 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 12:21:10.375200 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 12:21:10.382177 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 12:21:10.385505 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 12:21:10.388816 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5889 12:21:10.395600 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5890 12:21:10.395676 Total UI for P1: 0, mck2ui 16
5891 12:21:10.401666 best dqsien dly found for B0: ( 1, 2, 24)
5892 12:21:10.401743 Total UI for P1: 0, mck2ui 16
5893 12:21:10.408522 best dqsien dly found for B1: ( 1, 2, 24)
5894 12:21:10.412025 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5895 12:21:10.415163 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5896 12:21:10.415240
5897 12:21:10.418402 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5898 12:21:10.421408 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5899 12:21:10.424624 [Gating] SW calibration Done
5900 12:21:10.424696 ==
5901 12:21:10.428174 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 12:21:10.431067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 12:21:10.431136 ==
5904 12:21:10.434945 RX Vref Scan: 0
5905 12:21:10.435015
5906 12:21:10.437864 RX Vref 0 -> 0, step: 1
5907 12:21:10.437932
5908 12:21:10.437995 RX Delay -80 -> 252, step: 8
5909 12:21:10.444381 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5910 12:21:10.447893 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5911 12:21:10.450937 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5912 12:21:10.454769 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5913 12:21:10.457765 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5914 12:21:10.460828 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5915 12:21:10.467319 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5916 12:21:10.470910 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5917 12:21:10.474021 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5918 12:21:10.477556 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5919 12:21:10.480645 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5920 12:21:10.487294 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5921 12:21:10.490842 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5922 12:21:10.493860 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5923 12:21:10.497161 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5924 12:21:10.500540 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5925 12:21:10.500614 ==
5926 12:21:10.503543 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 12:21:10.510771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 12:21:10.510845 ==
5929 12:21:10.510911 DQS Delay:
5930 12:21:10.513496 DQS0 = 0, DQS1 = 0
5931 12:21:10.513562 DQM Delay:
5932 12:21:10.513623 DQM0 = 98, DQM1 = 91
5933 12:21:10.516767 DQ Delay:
5934 12:21:10.520277 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =95
5935 12:21:10.523798 DQ4 =99, DQ5 =107, DQ6 =107, DQ7 =95
5936 12:21:10.526898 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =83
5937 12:21:10.530531 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5938 12:21:10.530642
5939 12:21:10.530703
5940 12:21:10.530760 ==
5941 12:21:10.533900 Dram Type= 6, Freq= 0, CH_1, rank 1
5942 12:21:10.536872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5943 12:21:10.536942 ==
5944 12:21:10.537002
5945 12:21:10.537057
5946 12:21:10.540286 TX Vref Scan disable
5947 12:21:10.543282 == TX Byte 0 ==
5948 12:21:10.546738 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5949 12:21:10.550072 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5950 12:21:10.553180 == TX Byte 1 ==
5951 12:21:10.556626 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5952 12:21:10.559681 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5953 12:21:10.559754 ==
5954 12:21:10.563851 Dram Type= 6, Freq= 0, CH_1, rank 1
5955 12:21:10.569990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5956 12:21:10.570065 ==
5957 12:21:10.570128
5958 12:21:10.570186
5959 12:21:10.570241 TX Vref Scan disable
5960 12:21:10.573542 == TX Byte 0 ==
5961 12:21:10.576867 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5962 12:21:10.583877 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5963 12:21:10.583951 == TX Byte 1 ==
5964 12:21:10.586868 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5965 12:21:10.593337 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5966 12:21:10.593414
5967 12:21:10.593475 [DATLAT]
5968 12:21:10.593533 Freq=933, CH1 RK1
5969 12:21:10.593590
5970 12:21:10.596388 DATLAT Default: 0xb
5971 12:21:10.600315 0, 0xFFFF, sum = 0
5972 12:21:10.600422 1, 0xFFFF, sum = 0
5973 12:21:10.603249 2, 0xFFFF, sum = 0
5974 12:21:10.603317 3, 0xFFFF, sum = 0
5975 12:21:10.606753 4, 0xFFFF, sum = 0
5976 12:21:10.606824 5, 0xFFFF, sum = 0
5977 12:21:10.609693 6, 0xFFFF, sum = 0
5978 12:21:10.609770 7, 0xFFFF, sum = 0
5979 12:21:10.612981 8, 0xFFFF, sum = 0
5980 12:21:10.613051 9, 0xFFFF, sum = 0
5981 12:21:10.616307 10, 0x0, sum = 1
5982 12:21:10.616378 11, 0x0, sum = 2
5983 12:21:10.620015 12, 0x0, sum = 3
5984 12:21:10.620087 13, 0x0, sum = 4
5985 12:21:10.620149 best_step = 11
5986 12:21:10.623040
5987 12:21:10.623108 ==
5988 12:21:10.626488 Dram Type= 6, Freq= 0, CH_1, rank 1
5989 12:21:10.629631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5990 12:21:10.629700 ==
5991 12:21:10.629759 RX Vref Scan: 0
5992 12:21:10.629816
5993 12:21:10.632803 RX Vref 0 -> 0, step: 1
5994 12:21:10.632876
5995 12:21:10.636347 RX Delay -61 -> 252, step: 4
5996 12:21:10.643035 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5997 12:21:10.646800 iDelay=207, Bit 1, Center 96 (7 ~ 186) 180
5998 12:21:10.649523 iDelay=207, Bit 2, Center 88 (-1 ~ 178) 180
5999 12:21:10.652619 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6000 12:21:10.656041 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
6001 12:21:10.659369 iDelay=207, Bit 5, Center 110 (19 ~ 202) 184
6002 12:21:10.665709 iDelay=207, Bit 6, Center 112 (19 ~ 206) 188
6003 12:21:10.669144 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6004 12:21:10.672678 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
6005 12:21:10.675799 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6006 12:21:10.679092 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
6007 12:21:10.686033 iDelay=207, Bit 11, Center 82 (-9 ~ 174) 184
6008 12:21:10.689409 iDelay=207, Bit 12, Center 100 (7 ~ 194) 188
6009 12:21:10.692323 iDelay=207, Bit 13, Center 100 (7 ~ 194) 188
6010 12:21:10.695963 iDelay=207, Bit 14, Center 100 (7 ~ 194) 188
6011 12:21:10.699823 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6012 12:21:10.699903 ==
6013 12:21:10.702628 Dram Type= 6, Freq= 0, CH_1, rank 1
6014 12:21:10.708930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6015 12:21:10.709011 ==
6016 12:21:10.709074 DQS Delay:
6017 12:21:10.712531 DQS0 = 0, DQS1 = 0
6018 12:21:10.712611 DQM Delay:
6019 12:21:10.715496 DQM0 = 100, DQM1 = 93
6020 12:21:10.715575 DQ Delay:
6021 12:21:10.718639 DQ0 =104, DQ1 =96, DQ2 =88, DQ3 =98
6022 12:21:10.722142 DQ4 =98, DQ5 =110, DQ6 =112, DQ7 =98
6023 12:21:10.725494 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =82
6024 12:21:10.728858 DQ12 =100, DQ13 =100, DQ14 =100, DQ15 =102
6025 12:21:10.728928
6026 12:21:10.728988
6027 12:21:10.738770 [DQSOSCAuto] RK1, (LSB)MR18= 0x801, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
6028 12:21:10.738843 CH1 RK1: MR19=505, MR18=801
6029 12:21:10.745363 CH1_RK1: MR19=0x505, MR18=0x801, DQSOSC=419, MR23=63, INC=61, DEC=41
6030 12:21:10.748155 [RxdqsGatingPostProcess] freq 933
6031 12:21:10.755442 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6032 12:21:10.758477 best DQS0 dly(2T, 0.5T) = (0, 10)
6033 12:21:10.761282 best DQS1 dly(2T, 0.5T) = (0, 10)
6034 12:21:10.764873 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6035 12:21:10.768069 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6036 12:21:10.768149 best DQS0 dly(2T, 0.5T) = (0, 10)
6037 12:21:10.771524 best DQS1 dly(2T, 0.5T) = (0, 10)
6038 12:21:10.774779 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6039 12:21:10.777898 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6040 12:21:10.781367 Pre-setting of DQS Precalculation
6041 12:21:10.787685 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6042 12:21:10.794246 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6043 12:21:10.801320 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6044 12:21:10.801400
6045 12:21:10.801464
6046 12:21:10.804670 [Calibration Summary] 1866 Mbps
6047 12:21:10.804750 CH 0, Rank 0
6048 12:21:10.807396 SW Impedance : PASS
6049 12:21:10.810760 DUTY Scan : NO K
6050 12:21:10.810840 ZQ Calibration : PASS
6051 12:21:10.814488 Jitter Meter : NO K
6052 12:21:10.817531 CBT Training : PASS
6053 12:21:10.817611 Write leveling : PASS
6054 12:21:10.821186 RX DQS gating : PASS
6055 12:21:10.823895 RX DQ/DQS(RDDQC) : PASS
6056 12:21:10.823974 TX DQ/DQS : PASS
6057 12:21:10.827259 RX DATLAT : PASS
6058 12:21:10.830854 RX DQ/DQS(Engine): PASS
6059 12:21:10.830933 TX OE : NO K
6060 12:21:10.834288 All Pass.
6061 12:21:10.834368
6062 12:21:10.834431 CH 0, Rank 1
6063 12:21:10.837634 SW Impedance : PASS
6064 12:21:10.837713 DUTY Scan : NO K
6065 12:21:10.840514 ZQ Calibration : PASS
6066 12:21:10.843814 Jitter Meter : NO K
6067 12:21:10.843894 CBT Training : PASS
6068 12:21:10.846970 Write leveling : PASS
6069 12:21:10.850018 RX DQS gating : PASS
6070 12:21:10.850096 RX DQ/DQS(RDDQC) : PASS
6071 12:21:10.853537 TX DQ/DQS : PASS
6072 12:21:10.856782 RX DATLAT : PASS
6073 12:21:10.856860 RX DQ/DQS(Engine): PASS
6074 12:21:10.860516 TX OE : NO K
6075 12:21:10.860590 All Pass.
6076 12:21:10.860651
6077 12:21:10.863794 CH 1, Rank 0
6078 12:21:10.863866 SW Impedance : PASS
6079 12:21:10.866922 DUTY Scan : NO K
6080 12:21:10.870262 ZQ Calibration : PASS
6081 12:21:10.870332 Jitter Meter : NO K
6082 12:21:10.873540 CBT Training : PASS
6083 12:21:10.873612 Write leveling : PASS
6084 12:21:10.876944 RX DQS gating : PASS
6085 12:21:10.880070 RX DQ/DQS(RDDQC) : PASS
6086 12:21:10.880143 TX DQ/DQS : PASS
6087 12:21:10.883491 RX DATLAT : PASS
6088 12:21:10.886833 RX DQ/DQS(Engine): PASS
6089 12:21:10.886910 TX OE : NO K
6090 12:21:10.889927 All Pass.
6091 12:21:10.889998
6092 12:21:10.890059 CH 1, Rank 1
6093 12:21:10.893755 SW Impedance : PASS
6094 12:21:10.893830 DUTY Scan : NO K
6095 12:21:10.896771 ZQ Calibration : PASS
6096 12:21:10.900029 Jitter Meter : NO K
6097 12:21:10.900102 CBT Training : PASS
6098 12:21:10.903356 Write leveling : PASS
6099 12:21:10.906297 RX DQS gating : PASS
6100 12:21:10.906370 RX DQ/DQS(RDDQC) : PASS
6101 12:21:10.909508 TX DQ/DQS : PASS
6102 12:21:10.912819 RX DATLAT : PASS
6103 12:21:10.912888 RX DQ/DQS(Engine): PASS
6104 12:21:10.916409 TX OE : NO K
6105 12:21:10.916480 All Pass.
6106 12:21:10.916540
6107 12:21:10.919855 DramC Write-DBI off
6108 12:21:10.923755 PER_BANK_REFRESH: Hybrid Mode
6109 12:21:10.923830 TX_TRACKING: ON
6110 12:21:10.932959 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6111 12:21:10.936076 [FAST_K] Save calibration result to emmc
6112 12:21:10.939113 dramc_set_vcore_voltage set vcore to 650000
6113 12:21:10.942617 Read voltage for 400, 6
6114 12:21:10.942694 Vio18 = 0
6115 12:21:10.942756 Vcore = 650000
6116 12:21:10.946201 Vdram = 0
6117 12:21:10.946277 Vddq = 0
6118 12:21:10.946338 Vmddr = 0
6119 12:21:10.952518 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6120 12:21:10.956073 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6121 12:21:10.959028 MEM_TYPE=3, freq_sel=20
6122 12:21:10.962430 sv_algorithm_assistance_LP4_800
6123 12:21:10.966450 ============ PULL DRAM RESETB DOWN ============
6124 12:21:10.972631 ========== PULL DRAM RESETB DOWN end =========
6125 12:21:10.975720 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6126 12:21:10.979162 ===================================
6127 12:21:10.982155 LPDDR4 DRAM CONFIGURATION
6128 12:21:10.985607 ===================================
6129 12:21:10.985687 EX_ROW_EN[0] = 0x0
6130 12:21:10.988735 EX_ROW_EN[1] = 0x0
6131 12:21:10.988814 LP4Y_EN = 0x0
6132 12:21:10.992178 WORK_FSP = 0x0
6133 12:21:10.992258 WL = 0x2
6134 12:21:10.995228 RL = 0x2
6135 12:21:10.995407 BL = 0x2
6136 12:21:10.998951 RPST = 0x0
6137 12:21:11.002185 RD_PRE = 0x0
6138 12:21:11.002265 WR_PRE = 0x1
6139 12:21:11.005088 WR_PST = 0x0
6140 12:21:11.005167 DBI_WR = 0x0
6141 12:21:11.008856 DBI_RD = 0x0
6142 12:21:11.008936 OTF = 0x1
6143 12:21:11.012036 ===================================
6144 12:21:11.015173 ===================================
6145 12:21:11.018326 ANA top config
6146 12:21:11.021752 ===================================
6147 12:21:11.021832 DLL_ASYNC_EN = 0
6148 12:21:11.024882 ALL_SLAVE_EN = 1
6149 12:21:11.028160 NEW_RANK_MODE = 1
6150 12:21:11.031358 DLL_IDLE_MODE = 1
6151 12:21:11.031468 LP45_APHY_COMB_EN = 1
6152 12:21:11.035678 TX_ODT_DIS = 1
6153 12:21:11.038438 NEW_8X_MODE = 1
6154 12:21:11.041488 ===================================
6155 12:21:11.044581 ===================================
6156 12:21:11.048029 data_rate = 800
6157 12:21:11.051697 CKR = 1
6158 12:21:11.054604 DQ_P2S_RATIO = 4
6159 12:21:11.058098 ===================================
6160 12:21:11.058178 CA_P2S_RATIO = 4
6161 12:21:11.061526 DQ_CA_OPEN = 0
6162 12:21:11.064626 DQ_SEMI_OPEN = 1
6163 12:21:11.068014 CA_SEMI_OPEN = 1
6164 12:21:11.071200 CA_FULL_RATE = 0
6165 12:21:11.074626 DQ_CKDIV4_EN = 0
6166 12:21:11.074705 CA_CKDIV4_EN = 1
6167 12:21:11.078268 CA_PREDIV_EN = 0
6168 12:21:11.081355 PH8_DLY = 0
6169 12:21:11.084655 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6170 12:21:11.087539 DQ_AAMCK_DIV = 0
6171 12:21:11.091445 CA_AAMCK_DIV = 0
6172 12:21:11.091525 CA_ADMCK_DIV = 4
6173 12:21:11.094145 DQ_TRACK_CA_EN = 0
6174 12:21:11.097869 CA_PICK = 800
6175 12:21:11.101025 CA_MCKIO = 400
6176 12:21:11.104139 MCKIO_SEMI = 400
6177 12:21:11.108019 PLL_FREQ = 3016
6178 12:21:11.110928 DQ_UI_PI_RATIO = 32
6179 12:21:11.114079 CA_UI_PI_RATIO = 32
6180 12:21:11.117620 ===================================
6181 12:21:11.120752 ===================================
6182 12:21:11.120832 memory_type:LPDDR4
6183 12:21:11.123917 GP_NUM : 10
6184 12:21:11.127472 SRAM_EN : 1
6185 12:21:11.127552 MD32_EN : 0
6186 12:21:11.130394 ===================================
6187 12:21:11.133600 [ANA_INIT] >>>>>>>>>>>>>>
6188 12:21:11.137203 <<<<<< [CONFIGURE PHASE]: ANA_TX
6189 12:21:11.140616 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6190 12:21:11.143941 ===================================
6191 12:21:11.147542 data_rate = 800,PCW = 0X7400
6192 12:21:11.150546 ===================================
6193 12:21:11.153777 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6194 12:21:11.157060 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6195 12:21:11.170498 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6196 12:21:11.173382 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6197 12:21:11.176920 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6198 12:21:11.179878 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6199 12:21:11.183000 [ANA_INIT] flow start
6200 12:21:11.186497 [ANA_INIT] PLL >>>>>>>>
6201 12:21:11.186612 [ANA_INIT] PLL <<<<<<<<
6202 12:21:11.189731 [ANA_INIT] MIDPI >>>>>>>>
6203 12:21:11.192915 [ANA_INIT] MIDPI <<<<<<<<
6204 12:21:11.192995 [ANA_INIT] DLL >>>>>>>>
6205 12:21:11.196534 [ANA_INIT] flow end
6206 12:21:11.199780 ============ LP4 DIFF to SE enter ============
6207 12:21:11.203172 ============ LP4 DIFF to SE exit ============
6208 12:21:11.206488 [ANA_INIT] <<<<<<<<<<<<<
6209 12:21:11.209509 [Flow] Enable top DCM control >>>>>
6210 12:21:11.213239 [Flow] Enable top DCM control <<<<<
6211 12:21:11.216702 Enable DLL master slave shuffle
6212 12:21:11.222492 ==============================================================
6213 12:21:11.222611 Gating Mode config
6214 12:21:11.229268 ==============================================================
6215 12:21:11.233004 Config description:
6216 12:21:11.239039 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6217 12:21:11.245998 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6218 12:21:11.252593 SELPH_MODE 0: By rank 1: By Phase
6219 12:21:11.259088 ==============================================================
6220 12:21:11.262505 GAT_TRACK_EN = 0
6221 12:21:11.262647 RX_GATING_MODE = 2
6222 12:21:11.265547 RX_GATING_TRACK_MODE = 2
6223 12:21:11.269026 SELPH_MODE = 1
6224 12:21:11.272089 PICG_EARLY_EN = 1
6225 12:21:11.275727 VALID_LAT_VALUE = 1
6226 12:21:11.281825 ==============================================================
6227 12:21:11.285211 Enter into Gating configuration >>>>
6228 12:21:11.288592 Exit from Gating configuration <<<<
6229 12:21:11.292004 Enter into DVFS_PRE_config >>>>>
6230 12:21:11.301636 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6231 12:21:11.304868 Exit from DVFS_PRE_config <<<<<
6232 12:21:11.308487 Enter into PICG configuration >>>>
6233 12:21:11.311672 Exit from PICG configuration <<<<
6234 12:21:11.314935 [RX_INPUT] configuration >>>>>
6235 12:21:11.318200 [RX_INPUT] configuration <<<<<
6236 12:21:11.321549 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6237 12:21:11.328069 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6238 12:21:11.334939 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6239 12:21:11.341003 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6240 12:21:11.348030 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6241 12:21:11.351183 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6242 12:21:11.357980 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6243 12:21:11.361377 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6244 12:21:11.364171 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6245 12:21:11.367893 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6246 12:21:11.374368 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6247 12:21:11.377385 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6248 12:21:11.380757 ===================================
6249 12:21:11.384151 LPDDR4 DRAM CONFIGURATION
6250 12:21:11.387585 ===================================
6251 12:21:11.387655 EX_ROW_EN[0] = 0x0
6252 12:21:11.390824 EX_ROW_EN[1] = 0x0
6253 12:21:11.390891 LP4Y_EN = 0x0
6254 12:21:11.393905 WORK_FSP = 0x0
6255 12:21:11.393972 WL = 0x2
6256 12:21:11.397106 RL = 0x2
6257 12:21:11.397173 BL = 0x2
6258 12:21:11.400588 RPST = 0x0
6259 12:21:11.403743 RD_PRE = 0x0
6260 12:21:11.403810 WR_PRE = 0x1
6261 12:21:11.407356 WR_PST = 0x0
6262 12:21:11.407425 DBI_WR = 0x0
6263 12:21:11.410576 DBI_RD = 0x0
6264 12:21:11.410685 OTF = 0x1
6265 12:21:11.414051 ===================================
6266 12:21:11.417353 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6267 12:21:11.423544 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6268 12:21:11.426940 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6269 12:21:11.430267 ===================================
6270 12:21:11.433562 LPDDR4 DRAM CONFIGURATION
6271 12:21:11.437195 ===================================
6272 12:21:11.437266 EX_ROW_EN[0] = 0x10
6273 12:21:11.440044 EX_ROW_EN[1] = 0x0
6274 12:21:11.440118 LP4Y_EN = 0x0
6275 12:21:11.443841 WORK_FSP = 0x0
6276 12:21:11.443910 WL = 0x2
6277 12:21:11.447086 RL = 0x2
6278 12:21:11.447158 BL = 0x2
6279 12:21:11.450124 RPST = 0x0
6280 12:21:11.453194 RD_PRE = 0x0
6281 12:21:11.453269 WR_PRE = 0x1
6282 12:21:11.456535 WR_PST = 0x0
6283 12:21:11.456612 DBI_WR = 0x0
6284 12:21:11.459854 DBI_RD = 0x0
6285 12:21:11.459939 OTF = 0x1
6286 12:21:11.463375 ===================================
6287 12:21:11.470504 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6288 12:21:11.474299 nWR fixed to 30
6289 12:21:11.477536 [ModeRegInit_LP4] CH0 RK0
6290 12:21:11.477615 [ModeRegInit_LP4] CH0 RK1
6291 12:21:11.480172 [ModeRegInit_LP4] CH1 RK0
6292 12:21:11.483717 [ModeRegInit_LP4] CH1 RK1
6293 12:21:11.483796 match AC timing 19
6294 12:21:11.490031 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6295 12:21:11.493988 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6296 12:21:11.496851 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6297 12:21:11.503538 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6298 12:21:11.506616 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6299 12:21:11.506706 ==
6300 12:21:11.510366 Dram Type= 6, Freq= 0, CH_0, rank 0
6301 12:21:11.513300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 12:21:11.513370 ==
6303 12:21:11.520428 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6304 12:21:11.526423 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6305 12:21:11.530019 [CA 0] Center 36 (8~64) winsize 57
6306 12:21:11.533062 [CA 1] Center 36 (8~64) winsize 57
6307 12:21:11.536490 [CA 2] Center 36 (8~64) winsize 57
6308 12:21:11.539814 [CA 3] Center 36 (8~64) winsize 57
6309 12:21:11.543387 [CA 4] Center 36 (8~64) winsize 57
6310 12:21:11.543460 [CA 5] Center 36 (8~64) winsize 57
6311 12:21:11.546184
6312 12:21:11.549598 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6313 12:21:11.549673
6314 12:21:11.552779 [CATrainingPosCal] consider 1 rank data
6315 12:21:11.556207 u2DelayCellTimex100 = 270/100 ps
6316 12:21:11.559822 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 12:21:11.562701 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 12:21:11.565862 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 12:21:11.569330 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 12:21:11.572669 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 12:21:11.576004 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 12:21:11.576073
6323 12:21:11.579172 CA PerBit enable=1, Macro0, CA PI delay=36
6324 12:21:11.582820
6325 12:21:11.582893 [CBTSetCACLKResult] CA Dly = 36
6326 12:21:11.585763 CS Dly: 1 (0~32)
6327 12:21:11.585835 ==
6328 12:21:11.589341 Dram Type= 6, Freq= 0, CH_0, rank 1
6329 12:21:11.592454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 12:21:11.592531 ==
6331 12:21:11.599137 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6332 12:21:11.606092 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6333 12:21:11.609436 [CA 0] Center 36 (8~64) winsize 57
6334 12:21:11.612292 [CA 1] Center 36 (8~64) winsize 57
6335 12:21:11.615650 [CA 2] Center 36 (8~64) winsize 57
6336 12:21:11.618897 [CA 3] Center 36 (8~64) winsize 57
6337 12:21:11.618978 [CA 4] Center 36 (8~64) winsize 57
6338 12:21:11.622201 [CA 5] Center 36 (8~64) winsize 57
6339 12:21:11.622281
6340 12:21:11.628944 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6341 12:21:11.629024
6342 12:21:11.632323 [CATrainingPosCal] consider 2 rank data
6343 12:21:11.635239 u2DelayCellTimex100 = 270/100 ps
6344 12:21:11.639047 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6345 12:21:11.641747 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6346 12:21:11.645108 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6347 12:21:11.648706 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6348 12:21:11.652443 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6349 12:21:11.655282 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6350 12:21:11.655390
6351 12:21:11.658166 CA PerBit enable=1, Macro0, CA PI delay=36
6352 12:21:11.658245
6353 12:21:11.661423 [CBTSetCACLKResult] CA Dly = 36
6354 12:21:11.664716 CS Dly: 1 (0~32)
6355 12:21:11.664821
6356 12:21:11.668047 ----->DramcWriteLeveling(PI) begin...
6357 12:21:11.668127 ==
6358 12:21:11.671332 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 12:21:11.675269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 12:21:11.675349 ==
6361 12:21:11.678188 Write leveling (Byte 0): 40 => 8
6362 12:21:11.681351 Write leveling (Byte 1): 32 => 0
6363 12:21:11.685005 DramcWriteLeveling(PI) end<-----
6364 12:21:11.685084
6365 12:21:11.685146 ==
6366 12:21:11.688163 Dram Type= 6, Freq= 0, CH_0, rank 0
6367 12:21:11.691651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6368 12:21:11.691730 ==
6369 12:21:11.694709 [Gating] SW mode calibration
6370 12:21:11.701332 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6371 12:21:11.707484 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6372 12:21:11.711350 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6373 12:21:11.717630 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6374 12:21:11.720847 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6375 12:21:11.724530 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6376 12:21:11.730497 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6377 12:21:11.734442 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6378 12:21:11.737377 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6379 12:21:11.744278 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6380 12:21:11.747317 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6381 12:21:11.750684 Total UI for P1: 0, mck2ui 16
6382 12:21:11.754154 best dqsien dly found for B0: ( 0, 14, 24)
6383 12:21:11.757001 Total UI for P1: 0, mck2ui 16
6384 12:21:11.760332 best dqsien dly found for B1: ( 0, 14, 24)
6385 12:21:11.763952 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6386 12:21:11.766748 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6387 12:21:11.766828
6388 12:21:11.770087 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6389 12:21:11.773612 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6390 12:21:11.776890 [Gating] SW calibration Done
6391 12:21:11.776970 ==
6392 12:21:11.780124 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 12:21:11.786804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 12:21:11.786884 ==
6395 12:21:11.786948 RX Vref Scan: 0
6396 12:21:11.787007
6397 12:21:11.790107 RX Vref 0 -> 0, step: 1
6398 12:21:11.790229
6399 12:21:11.793109 RX Delay -410 -> 252, step: 16
6400 12:21:11.796762 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6401 12:21:11.800061 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6402 12:21:11.806385 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6403 12:21:11.810211 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6404 12:21:11.813170 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6405 12:21:11.816419 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6406 12:21:11.823450 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6407 12:21:11.826295 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6408 12:21:11.829737 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6409 12:21:11.832732 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6410 12:21:11.839714 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6411 12:21:11.842928 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6412 12:21:11.846456 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6413 12:21:11.849649 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6414 12:21:11.856519 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6415 12:21:11.859383 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6416 12:21:11.859463 ==
6417 12:21:11.862552 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 12:21:11.865908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 12:21:11.865988 ==
6420 12:21:11.869244 DQS Delay:
6421 12:21:11.869323 DQS0 = 43, DQS1 = 59
6422 12:21:11.872969 DQM Delay:
6423 12:21:11.873048 DQM0 = 10, DQM1 = 11
6424 12:21:11.873111 DQ Delay:
6425 12:21:11.875748 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6426 12:21:11.879261 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6427 12:21:11.882731 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6428 12:21:11.885797 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6429 12:21:11.885904
6430 12:21:11.885994
6431 12:21:11.886080 ==
6432 12:21:11.888940 Dram Type= 6, Freq= 0, CH_0, rank 0
6433 12:21:11.895635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6434 12:21:11.895716 ==
6435 12:21:11.895779
6436 12:21:11.895838
6437 12:21:11.895894 TX Vref Scan disable
6438 12:21:11.898851 == TX Byte 0 ==
6439 12:21:11.902204 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6440 12:21:11.905893 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6441 12:21:11.908993 == TX Byte 1 ==
6442 12:21:11.911873 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6443 12:21:11.918542 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6444 12:21:11.918679 ==
6445 12:21:11.922125 Dram Type= 6, Freq= 0, CH_0, rank 0
6446 12:21:11.925194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 12:21:11.925275 ==
6448 12:21:11.925338
6449 12:21:11.925397
6450 12:21:11.928325 TX Vref Scan disable
6451 12:21:11.928405 == TX Byte 0 ==
6452 12:21:11.931568 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6453 12:21:11.938289 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6454 12:21:11.938394 == TX Byte 1 ==
6455 12:21:11.941650 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6456 12:21:11.948419 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6457 12:21:11.948499
6458 12:21:11.948562 [DATLAT]
6459 12:21:11.948620 Freq=400, CH0 RK0
6460 12:21:11.952218
6461 12:21:11.952297 DATLAT Default: 0xf
6462 12:21:11.955467 0, 0xFFFF, sum = 0
6463 12:21:11.955548 1, 0xFFFF, sum = 0
6464 12:21:11.958202 2, 0xFFFF, sum = 0
6465 12:21:11.958283 3, 0xFFFF, sum = 0
6466 12:21:11.961380 4, 0xFFFF, sum = 0
6467 12:21:11.961462 5, 0xFFFF, sum = 0
6468 12:21:11.964961 6, 0xFFFF, sum = 0
6469 12:21:11.965042 7, 0xFFFF, sum = 0
6470 12:21:11.967990 8, 0xFFFF, sum = 0
6471 12:21:11.968072 9, 0xFFFF, sum = 0
6472 12:21:11.971305 10, 0xFFFF, sum = 0
6473 12:21:11.971389 11, 0xFFFF, sum = 0
6474 12:21:11.974783 12, 0xFFFF, sum = 0
6475 12:21:11.974864 13, 0x0, sum = 1
6476 12:21:11.977831 14, 0x0, sum = 2
6477 12:21:11.977912 15, 0x0, sum = 3
6478 12:21:11.980981 16, 0x0, sum = 4
6479 12:21:11.981063 best_step = 14
6480 12:21:11.981127
6481 12:21:11.981185 ==
6482 12:21:11.984944 Dram Type= 6, Freq= 0, CH_0, rank 0
6483 12:21:11.990988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 12:21:11.991068 ==
6485 12:21:11.991131 RX Vref Scan: 1
6486 12:21:11.991191
6487 12:21:11.994249 RX Vref 0 -> 0, step: 1
6488 12:21:11.994353
6489 12:21:11.997974 RX Delay -359 -> 252, step: 8
6490 12:21:11.998055
6491 12:21:12.000650 Set Vref, RX VrefLevel [Byte0]: 60
6492 12:21:12.004391 [Byte1]: 58
6493 12:21:12.008341
6494 12:21:12.008421 Final RX Vref Byte 0 = 60 to rank0
6495 12:21:12.011195 Final RX Vref Byte 1 = 58 to rank0
6496 12:21:12.014508 Final RX Vref Byte 0 = 60 to rank1
6497 12:21:12.017755 Final RX Vref Byte 1 = 58 to rank1==
6498 12:21:12.021168 Dram Type= 6, Freq= 0, CH_0, rank 0
6499 12:21:12.027584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 12:21:12.027672 ==
6501 12:21:12.027766 DQS Delay:
6502 12:21:12.031821 DQS0 = 48, DQS1 = 60
6503 12:21:12.031902 DQM Delay:
6504 12:21:12.031965 DQM0 = 11, DQM1 = 12
6505 12:21:12.034240 DQ Delay:
6506 12:21:12.037642 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6507 12:21:12.040773 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6508 12:21:12.040853 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6509 12:21:12.043961 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =20
6510 12:21:12.048375
6511 12:21:12.048457
6512 12:21:12.053740 [DQSOSCAuto] RK0, (LSB)MR18= 0xc487, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 385 ps
6513 12:21:12.057115 CH0 RK0: MR19=C0C, MR18=C487
6514 12:21:12.064335 CH0_RK0: MR19=0xC0C, MR18=0xC487, DQSOSC=385, MR23=63, INC=398, DEC=265
6515 12:21:12.064413 ==
6516 12:21:12.067021 Dram Type= 6, Freq= 0, CH_0, rank 1
6517 12:21:12.070562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 12:21:12.070686 ==
6519 12:21:12.074097 [Gating] SW mode calibration
6520 12:21:12.080093 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6521 12:21:12.087240 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6522 12:21:12.090036 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6523 12:21:12.093432 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6524 12:21:12.100309 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6525 12:21:12.103520 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6526 12:21:12.106729 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6527 12:21:12.113205 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6528 12:21:12.116498 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6529 12:21:12.119794 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6530 12:21:12.126570 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6531 12:21:12.126672 Total UI for P1: 0, mck2ui 16
6532 12:21:12.133787 best dqsien dly found for B0: ( 0, 14, 24)
6533 12:21:12.133861 Total UI for P1: 0, mck2ui 16
6534 12:21:12.139828 best dqsien dly found for B1: ( 0, 14, 24)
6535 12:21:12.142918 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6536 12:21:12.146489 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6537 12:21:12.146610
6538 12:21:12.150099 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6539 12:21:12.152891 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6540 12:21:12.156211 [Gating] SW calibration Done
6541 12:21:12.156285 ==
6542 12:21:12.159522 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 12:21:12.162884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 12:21:12.162955 ==
6545 12:21:12.165983 RX Vref Scan: 0
6546 12:21:12.166052
6547 12:21:12.166112 RX Vref 0 -> 0, step: 1
6548 12:21:12.169469
6549 12:21:12.169537 RX Delay -410 -> 252, step: 16
6550 12:21:12.175911 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6551 12:21:12.179483 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6552 12:21:12.182842 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6553 12:21:12.185969 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6554 12:21:12.192848 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6555 12:21:12.196581 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6556 12:21:12.199224 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6557 12:21:12.202689 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6558 12:21:12.209288 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6559 12:21:12.212568 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6560 12:21:12.215759 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6561 12:21:12.222122 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6562 12:21:12.225541 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6563 12:21:12.228797 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6564 12:21:12.232184 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6565 12:21:12.238490 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6566 12:21:12.238563 ==
6567 12:21:12.242223 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 12:21:12.245339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 12:21:12.245420 ==
6570 12:21:12.245483 DQS Delay:
6571 12:21:12.248499 DQS0 = 43, DQS1 = 59
6572 12:21:12.248602 DQM Delay:
6573 12:21:12.251736 DQM0 = 10, DQM1 = 15
6574 12:21:12.251808 DQ Delay:
6575 12:21:12.255567 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6576 12:21:12.258575 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6577 12:21:12.262006 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6578 12:21:12.265083 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6579 12:21:12.265164
6580 12:21:12.265226
6581 12:21:12.265284 ==
6582 12:21:12.268359 Dram Type= 6, Freq= 0, CH_0, rank 1
6583 12:21:12.271757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 12:21:12.271837 ==
6585 12:21:12.271908
6586 12:21:12.275050
6587 12:21:12.275129 TX Vref Scan disable
6588 12:21:12.278135 == TX Byte 0 ==
6589 12:21:12.281842 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6590 12:21:12.284981 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6591 12:21:12.288464 == TX Byte 1 ==
6592 12:21:12.291578 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6593 12:21:12.295312 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6594 12:21:12.295392 ==
6595 12:21:12.298576 Dram Type= 6, Freq= 0, CH_0, rank 1
6596 12:21:12.301554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 12:21:12.301635 ==
6598 12:21:12.304919
6599 12:21:12.304999
6600 12:21:12.305062 TX Vref Scan disable
6601 12:21:12.308581 == TX Byte 0 ==
6602 12:21:12.311377 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6603 12:21:12.314737 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6604 12:21:12.318377 == TX Byte 1 ==
6605 12:21:12.321213 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6606 12:21:12.324665 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6607 12:21:12.324745
6608 12:21:12.324808 [DATLAT]
6609 12:21:12.327997 Freq=400, CH0 RK1
6610 12:21:12.328077
6611 12:21:12.331539 DATLAT Default: 0xe
6612 12:21:12.331619 0, 0xFFFF, sum = 0
6613 12:21:12.334587 1, 0xFFFF, sum = 0
6614 12:21:12.334719 2, 0xFFFF, sum = 0
6615 12:21:12.337881 3, 0xFFFF, sum = 0
6616 12:21:12.337963 4, 0xFFFF, sum = 0
6617 12:21:12.341566 5, 0xFFFF, sum = 0
6618 12:21:12.341647 6, 0xFFFF, sum = 0
6619 12:21:12.344662 7, 0xFFFF, sum = 0
6620 12:21:12.344744 8, 0xFFFF, sum = 0
6621 12:21:12.347697 9, 0xFFFF, sum = 0
6622 12:21:12.347778 10, 0xFFFF, sum = 0
6623 12:21:12.351266 11, 0xFFFF, sum = 0
6624 12:21:12.351347 12, 0xFFFF, sum = 0
6625 12:21:12.354345 13, 0x0, sum = 1
6626 12:21:12.354426 14, 0x0, sum = 2
6627 12:21:12.358388 15, 0x0, sum = 3
6628 12:21:12.358495 16, 0x0, sum = 4
6629 12:21:12.361425 best_step = 14
6630 12:21:12.361504
6631 12:21:12.361567 ==
6632 12:21:12.364309 Dram Type= 6, Freq= 0, CH_0, rank 1
6633 12:21:12.367657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6634 12:21:12.367736 ==
6635 12:21:12.371000 RX Vref Scan: 0
6636 12:21:12.371080
6637 12:21:12.371143 RX Vref 0 -> 0, step: 1
6638 12:21:12.371202
6639 12:21:12.374324 RX Delay -359 -> 252, step: 8
6640 12:21:12.382169 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6641 12:21:12.385226 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6642 12:21:12.388528 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6643 12:21:12.395516 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6644 12:21:12.398751 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6645 12:21:12.402074 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6646 12:21:12.405622 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6647 12:21:12.411657 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6648 12:21:12.415050 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6649 12:21:12.418435 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6650 12:21:12.422148 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6651 12:21:12.428465 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6652 12:21:12.431631 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6653 12:21:12.434766 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6654 12:21:12.438470 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6655 12:21:12.445081 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6656 12:21:12.445181 ==
6657 12:21:12.448155 Dram Type= 6, Freq= 0, CH_0, rank 1
6658 12:21:12.451099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 12:21:12.451180 ==
6660 12:21:12.451244 DQS Delay:
6661 12:21:12.454757 DQS0 = 44, DQS1 = 60
6662 12:21:12.454837 DQM Delay:
6663 12:21:12.458097 DQM0 = 7, DQM1 = 14
6664 12:21:12.458177 DQ Delay:
6665 12:21:12.461574 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6666 12:21:12.464745 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6667 12:21:12.468325 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6668 12:21:12.470729 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6669 12:21:12.470810
6670 12:21:12.470872
6671 12:21:12.477768 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe4a, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 386 ps
6672 12:21:12.481129 CH0 RK1: MR19=C0C, MR18=BE4A
6673 12:21:12.487321 CH0_RK1: MR19=0xC0C, MR18=0xBE4A, DQSOSC=386, MR23=63, INC=396, DEC=264
6674 12:21:12.491007 [RxdqsGatingPostProcess] freq 400
6675 12:21:12.497331 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6676 12:21:12.500661 best DQS0 dly(2T, 0.5T) = (0, 10)
6677 12:21:12.504138 best DQS1 dly(2T, 0.5T) = (0, 10)
6678 12:21:12.507449 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6679 12:21:12.510386 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6680 12:21:12.514012 best DQS0 dly(2T, 0.5T) = (0, 10)
6681 12:21:12.514092 best DQS1 dly(2T, 0.5T) = (0, 10)
6682 12:21:12.517734 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6683 12:21:12.520940 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6684 12:21:12.523700 Pre-setting of DQS Precalculation
6685 12:21:12.531162 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6686 12:21:12.531242 ==
6687 12:21:12.533861 Dram Type= 6, Freq= 0, CH_1, rank 0
6688 12:21:12.537184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 12:21:12.537265 ==
6690 12:21:12.543785 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6691 12:21:12.550222 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6692 12:21:12.553520 [CA 0] Center 36 (8~64) winsize 57
6693 12:21:12.557060 [CA 1] Center 36 (8~64) winsize 57
6694 12:21:12.559767 [CA 2] Center 36 (8~64) winsize 57
6695 12:21:12.559847 [CA 3] Center 36 (8~64) winsize 57
6696 12:21:12.563667 [CA 4] Center 36 (8~64) winsize 57
6697 12:21:12.566571 [CA 5] Center 36 (8~64) winsize 57
6698 12:21:12.566662
6699 12:21:12.573187 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6700 12:21:12.573271
6701 12:21:12.576138 [CATrainingPosCal] consider 1 rank data
6702 12:21:12.579478 u2DelayCellTimex100 = 270/100 ps
6703 12:21:12.582775 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 12:21:12.586318 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 12:21:12.589372 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 12:21:12.592944 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 12:21:12.596631 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 12:21:12.599392 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 12:21:12.599478
6710 12:21:12.602778 CA PerBit enable=1, Macro0, CA PI delay=36
6711 12:21:12.602889
6712 12:21:12.606157 [CBTSetCACLKResult] CA Dly = 36
6713 12:21:12.609578 CS Dly: 1 (0~32)
6714 12:21:12.609662 ==
6715 12:21:12.612513 Dram Type= 6, Freq= 0, CH_1, rank 1
6716 12:21:12.616030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 12:21:12.616101 ==
6718 12:21:12.622596 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6719 12:21:12.629287 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6720 12:21:12.632293 [CA 0] Center 36 (8~64) winsize 57
6721 12:21:12.632368 [CA 1] Center 36 (8~64) winsize 57
6722 12:21:12.635829 [CA 2] Center 36 (8~64) winsize 57
6723 12:21:12.638798 [CA 3] Center 36 (8~64) winsize 57
6724 12:21:12.642309 [CA 4] Center 36 (8~64) winsize 57
6725 12:21:12.645518 [CA 5] Center 36 (8~64) winsize 57
6726 12:21:12.645589
6727 12:21:12.649265 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6728 12:21:12.649341
6729 12:21:12.655494 [CATrainingPosCal] consider 2 rank data
6730 12:21:12.655568 u2DelayCellTimex100 = 270/100 ps
6731 12:21:12.662051 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6732 12:21:12.665452 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6733 12:21:12.668564 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6734 12:21:12.672129 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6735 12:21:12.675515 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6736 12:21:12.678751 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6737 12:21:12.678821
6738 12:21:12.681878 CA PerBit enable=1, Macro0, CA PI delay=36
6739 12:21:12.681949
6740 12:21:12.685299 [CBTSetCACLKResult] CA Dly = 36
6741 12:21:12.688381 CS Dly: 1 (0~32)
6742 12:21:12.688456
6743 12:21:12.692021 ----->DramcWriteLeveling(PI) begin...
6744 12:21:12.692089 ==
6745 12:21:12.695122 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 12:21:12.698314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 12:21:12.698388 ==
6748 12:21:12.701314 Write leveling (Byte 0): 40 => 8
6749 12:21:12.704878 Write leveling (Byte 1): 40 => 8
6750 12:21:12.707944 DramcWriteLeveling(PI) end<-----
6751 12:21:12.708014
6752 12:21:12.708075 ==
6753 12:21:12.711575 Dram Type= 6, Freq= 0, CH_1, rank 0
6754 12:21:12.714837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6755 12:21:12.714912 ==
6756 12:21:12.718500 [Gating] SW mode calibration
6757 12:21:12.724730 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6758 12:21:12.731293 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6759 12:21:12.734343 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6760 12:21:12.737829 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6761 12:21:12.744586 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6762 12:21:12.747740 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6763 12:21:12.751219 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6764 12:21:12.757732 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6765 12:21:12.760895 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6766 12:21:12.764572 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6767 12:21:12.770819 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6768 12:21:12.774341 Total UI for P1: 0, mck2ui 16
6769 12:21:12.777596 best dqsien dly found for B0: ( 0, 14, 24)
6770 12:21:12.780715 Total UI for P1: 0, mck2ui 16
6771 12:21:12.784099 best dqsien dly found for B1: ( 0, 14, 24)
6772 12:21:12.787604 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6773 12:21:12.790473 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6774 12:21:12.790539
6775 12:21:12.793877 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6776 12:21:12.797200 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6777 12:21:12.800865 [Gating] SW calibration Done
6778 12:21:12.800939 ==
6779 12:21:12.804651 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 12:21:12.807209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 12:21:12.807280 ==
6782 12:21:12.810800 RX Vref Scan: 0
6783 12:21:12.810870
6784 12:21:12.813918 RX Vref 0 -> 0, step: 1
6785 12:21:12.813988
6786 12:21:12.816948 RX Delay -410 -> 252, step: 16
6787 12:21:12.820194 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6788 12:21:12.823746 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6789 12:21:12.826892 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6790 12:21:12.833757 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6791 12:21:12.836924 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6792 12:21:12.840000 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6793 12:21:12.843845 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6794 12:21:12.849874 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6795 12:21:12.853491 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6796 12:21:12.856436 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6797 12:21:12.860376 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6798 12:21:12.866806 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6799 12:21:12.869742 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6800 12:21:12.873167 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6801 12:21:12.880011 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6802 12:21:12.883160 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6803 12:21:12.883240 ==
6804 12:21:12.886347 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 12:21:12.889698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 12:21:12.889779 ==
6807 12:21:12.893226 DQS Delay:
6808 12:21:12.893306 DQS0 = 43, DQS1 = 51
6809 12:21:12.893368 DQM Delay:
6810 12:21:12.896148 DQM0 = 12, DQM1 = 14
6811 12:21:12.896227 DQ Delay:
6812 12:21:12.899494 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6813 12:21:12.902949 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6814 12:21:12.906283 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6815 12:21:12.909501 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6816 12:21:12.909581
6817 12:21:12.909644
6818 12:21:12.909702 ==
6819 12:21:12.912385 Dram Type= 6, Freq= 0, CH_1, rank 0
6820 12:21:12.916012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6821 12:21:12.919338 ==
6822 12:21:12.919426
6823 12:21:12.919533
6824 12:21:12.919593 TX Vref Scan disable
6825 12:21:12.922711 == TX Byte 0 ==
6826 12:21:12.925668 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6827 12:21:12.929107 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6828 12:21:12.932769 == TX Byte 1 ==
6829 12:21:12.936252 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6830 12:21:12.939282 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6831 12:21:12.939354 ==
6832 12:21:12.942265 Dram Type= 6, Freq= 0, CH_1, rank 0
6833 12:21:12.948741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 12:21:12.948821 ==
6835 12:21:12.948884
6836 12:21:12.948942
6837 12:21:12.948998 TX Vref Scan disable
6838 12:21:12.952017 == TX Byte 0 ==
6839 12:21:12.955393 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6840 12:21:12.958797 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6841 12:21:12.962085 == TX Byte 1 ==
6842 12:21:12.965678 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6843 12:21:12.968724 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6844 12:21:12.968804
6845 12:21:12.972219 [DATLAT]
6846 12:21:12.972300 Freq=400, CH1 RK0
6847 12:21:12.972363
6848 12:21:12.975174 DATLAT Default: 0xf
6849 12:21:12.975254 0, 0xFFFF, sum = 0
6850 12:21:12.978554 1, 0xFFFF, sum = 0
6851 12:21:12.978686 2, 0xFFFF, sum = 0
6852 12:21:12.982018 3, 0xFFFF, sum = 0
6853 12:21:12.982098 4, 0xFFFF, sum = 0
6854 12:21:12.985155 5, 0xFFFF, sum = 0
6855 12:21:12.985238 6, 0xFFFF, sum = 0
6856 12:21:12.988455 7, 0xFFFF, sum = 0
6857 12:21:12.988537 8, 0xFFFF, sum = 0
6858 12:21:12.991840 9, 0xFFFF, sum = 0
6859 12:21:12.995221 10, 0xFFFF, sum = 0
6860 12:21:12.995302 11, 0xFFFF, sum = 0
6861 12:21:12.998494 12, 0xFFFF, sum = 0
6862 12:21:12.998624 13, 0x0, sum = 1
6863 12:21:13.001780 14, 0x0, sum = 2
6864 12:21:13.001860 15, 0x0, sum = 3
6865 12:21:13.001925 16, 0x0, sum = 4
6866 12:21:13.004783 best_step = 14
6867 12:21:13.004863
6868 12:21:13.004925 ==
6869 12:21:13.008266 Dram Type= 6, Freq= 0, CH_1, rank 0
6870 12:21:13.011618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 12:21:13.011699 ==
6872 12:21:13.014844 RX Vref Scan: 1
6873 12:21:13.014924
6874 12:21:13.018472 RX Vref 0 -> 0, step: 1
6875 12:21:13.018577
6876 12:21:13.018692 RX Delay -343 -> 252, step: 8
6877 12:21:13.018756
6878 12:21:13.021595 Set Vref, RX VrefLevel [Byte0]: 52
6879 12:21:13.024515 [Byte1]: 56
6880 12:21:13.030125
6881 12:21:13.030204 Final RX Vref Byte 0 = 52 to rank0
6882 12:21:13.033624 Final RX Vref Byte 1 = 56 to rank0
6883 12:21:13.036494 Final RX Vref Byte 0 = 52 to rank1
6884 12:21:13.040358 Final RX Vref Byte 1 = 56 to rank1==
6885 12:21:13.043382 Dram Type= 6, Freq= 0, CH_1, rank 0
6886 12:21:13.049693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 12:21:13.049774 ==
6888 12:21:13.049837 DQS Delay:
6889 12:21:13.052973 DQS0 = 44, DQS1 = 56
6890 12:21:13.053053 DQM Delay:
6891 12:21:13.053116 DQM0 = 9, DQM1 = 14
6892 12:21:13.056586 DQ Delay:
6893 12:21:13.060203 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6894 12:21:13.060283 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6895 12:21:13.062943 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6896 12:21:13.066549 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6897 12:21:13.069736
6898 12:21:13.069840
6899 12:21:13.076238 [DQSOSCAuto] RK0, (LSB)MR18= 0xa278, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 389 ps
6900 12:21:13.079791 CH1 RK0: MR19=C0C, MR18=A278
6901 12:21:13.086189 CH1_RK0: MR19=0xC0C, MR18=0xA278, DQSOSC=389, MR23=63, INC=390, DEC=260
6902 12:21:13.086276 ==
6903 12:21:13.089577 Dram Type= 6, Freq= 0, CH_1, rank 1
6904 12:21:13.093092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 12:21:13.093174 ==
6906 12:21:13.095704 [Gating] SW mode calibration
6907 12:21:13.102880 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6908 12:21:13.108957 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6909 12:21:13.112132 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6910 12:21:13.116162 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6911 12:21:13.122496 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6912 12:21:13.125329 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6913 12:21:13.128855 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6914 12:21:13.135169 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6915 12:21:13.138538 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6916 12:21:13.142140 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6917 12:21:13.148534 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6918 12:21:13.152345 Total UI for P1: 0, mck2ui 16
6919 12:21:13.155107 best dqsien dly found for B0: ( 0, 14, 24)
6920 12:21:13.155188 Total UI for P1: 0, mck2ui 16
6921 12:21:13.162052 best dqsien dly found for B1: ( 0, 14, 24)
6922 12:21:13.165566 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6923 12:21:13.168185 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6924 12:21:13.168265
6925 12:21:13.171743 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6926 12:21:13.174846 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6927 12:21:13.178191 [Gating] SW calibration Done
6928 12:21:13.178272 ==
6929 12:21:13.182255 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 12:21:13.185405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 12:21:13.185487 ==
6932 12:21:13.188235 RX Vref Scan: 0
6933 12:21:13.188316
6934 12:21:13.191697 RX Vref 0 -> 0, step: 1
6935 12:21:13.191778
6936 12:21:13.191907 RX Delay -410 -> 252, step: 16
6937 12:21:13.198236 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6938 12:21:13.201264 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6939 12:21:13.204505 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6940 12:21:13.211229 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6941 12:21:13.214475 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6942 12:21:13.218126 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6943 12:21:13.221539 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6944 12:21:13.227742 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6945 12:21:13.231238 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6946 12:21:13.234325 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6947 12:21:13.237957 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6948 12:21:13.244116 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6949 12:21:13.247496 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6950 12:21:13.250508 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6951 12:21:13.253989 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6952 12:21:13.260640 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6953 12:21:13.260721 ==
6954 12:21:13.264287 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 12:21:13.267618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 12:21:13.267700 ==
6957 12:21:13.267764 DQS Delay:
6958 12:21:13.270860 DQS0 = 43, DQS1 = 51
6959 12:21:13.270941 DQM Delay:
6960 12:21:13.274076 DQM0 = 13, DQM1 = 15
6961 12:21:13.274160 DQ Delay:
6962 12:21:13.276926 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6963 12:21:13.280182 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6964 12:21:13.283452 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6965 12:21:13.287122 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6966 12:21:13.287203
6967 12:21:13.287266
6968 12:21:13.287326 ==
6969 12:21:13.290298 Dram Type= 6, Freq= 0, CH_1, rank 1
6970 12:21:13.293818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6971 12:21:13.293945 ==
6972 12:21:13.296765
6973 12:21:13.296844
6974 12:21:13.296907 TX Vref Scan disable
6975 12:21:13.300050 == TX Byte 0 ==
6976 12:21:13.303325 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6977 12:21:13.306858 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6978 12:21:13.310178 == TX Byte 1 ==
6979 12:21:13.313597 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6980 12:21:13.316588 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6981 12:21:13.316668 ==
6982 12:21:13.320109 Dram Type= 6, Freq= 0, CH_1, rank 1
6983 12:21:13.326334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6984 12:21:13.326415 ==
6985 12:21:13.326479
6986 12:21:13.326538
6987 12:21:13.326620 TX Vref Scan disable
6988 12:21:13.329948 == TX Byte 0 ==
6989 12:21:13.333226 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6990 12:21:13.336551 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6991 12:21:13.339657 == TX Byte 1 ==
6992 12:21:13.342785 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6993 12:21:13.346218 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6994 12:21:13.346299
6995 12:21:13.349464 [DATLAT]
6996 12:21:13.349544 Freq=400, CH1 RK1
6997 12:21:13.349608
6998 12:21:13.352782 DATLAT Default: 0xe
6999 12:21:13.352863 0, 0xFFFF, sum = 0
7000 12:21:13.356073 1, 0xFFFF, sum = 0
7001 12:21:13.356156 2, 0xFFFF, sum = 0
7002 12:21:13.359610 3, 0xFFFF, sum = 0
7003 12:21:13.359692 4, 0xFFFF, sum = 0
7004 12:21:13.362631 5, 0xFFFF, sum = 0
7005 12:21:13.362727 6, 0xFFFF, sum = 0
7006 12:21:13.365899 7, 0xFFFF, sum = 0
7007 12:21:13.365981 8, 0xFFFF, sum = 0
7008 12:21:13.369602 9, 0xFFFF, sum = 0
7009 12:21:13.369683 10, 0xFFFF, sum = 0
7010 12:21:13.372754 11, 0xFFFF, sum = 0
7011 12:21:13.376014 12, 0xFFFF, sum = 0
7012 12:21:13.376096 13, 0x0, sum = 1
7013 12:21:13.379296 14, 0x0, sum = 2
7014 12:21:13.379377 15, 0x0, sum = 3
7015 12:21:13.379441 16, 0x0, sum = 4
7016 12:21:13.382559 best_step = 14
7017 12:21:13.382689
7018 12:21:13.382753 ==
7019 12:21:13.385647 Dram Type= 6, Freq= 0, CH_1, rank 1
7020 12:21:13.389138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7021 12:21:13.389223 ==
7022 12:21:13.392214 RX Vref Scan: 0
7023 12:21:13.392294
7024 12:21:13.395552 RX Vref 0 -> 0, step: 1
7025 12:21:13.395633
7026 12:21:13.395697 RX Delay -343 -> 252, step: 8
7027 12:21:13.404507 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7028 12:21:13.407866 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
7029 12:21:13.410522 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7030 12:21:13.418119 iDelay=225, Bit 3, Center -36 (-279 ~ 208) 488
7031 12:21:13.420976 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7032 12:21:13.424049 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7033 12:21:13.427329 iDelay=225, Bit 6, Center -20 (-263 ~ 224) 488
7034 12:21:13.430538 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7035 12:21:13.437052 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7036 12:21:13.440807 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7037 12:21:13.443766 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7038 12:21:13.450318 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
7039 12:21:13.453872 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7040 12:21:13.456871 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7041 12:21:13.460350 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7042 12:21:13.466737 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
7043 12:21:13.466818 ==
7044 12:21:13.470278 Dram Type= 6, Freq= 0, CH_1, rank 1
7045 12:21:13.473737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7046 12:21:13.473818 ==
7047 12:21:13.473883 DQS Delay:
7048 12:21:13.476577 DQS0 = 44, DQS1 = 56
7049 12:21:13.476657 DQM Delay:
7050 12:21:13.480001 DQM0 = 10, DQM1 = 11
7051 12:21:13.480082 DQ Delay:
7052 12:21:13.483160 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
7053 12:21:13.486507 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
7054 12:21:13.489850 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
7055 12:21:13.493742 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
7056 12:21:13.493823
7057 12:21:13.493889
7058 12:21:13.499982 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a5a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7059 12:21:13.503018 CH1 RK1: MR19=C0C, MR18=6A5A
7060 12:21:13.510218 CH1_RK1: MR19=0xC0C, MR18=0x6A5A, DQSOSC=396, MR23=63, INC=376, DEC=251
7061 12:21:13.513237 [RxdqsGatingPostProcess] freq 400
7062 12:21:13.519745 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7063 12:21:13.523377 best DQS0 dly(2T, 0.5T) = (0, 10)
7064 12:21:13.526302 best DQS1 dly(2T, 0.5T) = (0, 10)
7065 12:21:13.530311 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7066 12:21:13.533136 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7067 12:21:13.533216 best DQS0 dly(2T, 0.5T) = (0, 10)
7068 12:21:13.536174 best DQS1 dly(2T, 0.5T) = (0, 10)
7069 12:21:13.539628 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7070 12:21:13.542793 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7071 12:21:13.546332 Pre-setting of DQS Precalculation
7072 12:21:13.553138 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7073 12:21:13.559284 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7074 12:21:13.565961 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7075 12:21:13.566041
7076 12:21:13.566105
7077 12:21:13.569703 [Calibration Summary] 800 Mbps
7078 12:21:13.569783 CH 0, Rank 0
7079 12:21:13.572565 SW Impedance : PASS
7080 12:21:13.575994 DUTY Scan : NO K
7081 12:21:13.576075 ZQ Calibration : PASS
7082 12:21:13.579811 Jitter Meter : NO K
7083 12:21:13.582799 CBT Training : PASS
7084 12:21:13.582880 Write leveling : PASS
7085 12:21:13.585807 RX DQS gating : PASS
7086 12:21:13.589062 RX DQ/DQS(RDDQC) : PASS
7087 12:21:13.589143 TX DQ/DQS : PASS
7088 12:21:13.593344 RX DATLAT : PASS
7089 12:21:13.595718 RX DQ/DQS(Engine): PASS
7090 12:21:13.595799 TX OE : NO K
7091 12:21:13.599282 All Pass.
7092 12:21:13.599362
7093 12:21:13.599426 CH 0, Rank 1
7094 12:21:13.602172 SW Impedance : PASS
7095 12:21:13.602252 DUTY Scan : NO K
7096 12:21:13.606139 ZQ Calibration : PASS
7097 12:21:13.609229 Jitter Meter : NO K
7098 12:21:13.609310 CBT Training : PASS
7099 12:21:13.612402 Write leveling : NO K
7100 12:21:13.616218 RX DQS gating : PASS
7101 12:21:13.616298 RX DQ/DQS(RDDQC) : PASS
7102 12:21:13.618641 TX DQ/DQS : PASS
7103 12:21:13.618735 RX DATLAT : PASS
7104 12:21:13.622077 RX DQ/DQS(Engine): PASS
7105 12:21:13.625396 TX OE : NO K
7106 12:21:13.625477 All Pass.
7107 12:21:13.625541
7108 12:21:13.625599 CH 1, Rank 0
7109 12:21:13.628682 SW Impedance : PASS
7110 12:21:13.632450 DUTY Scan : NO K
7111 12:21:13.632531 ZQ Calibration : PASS
7112 12:21:13.635241 Jitter Meter : NO K
7113 12:21:13.638976 CBT Training : PASS
7114 12:21:13.639057 Write leveling : PASS
7115 12:21:13.642464 RX DQS gating : PASS
7116 12:21:13.645157 RX DQ/DQS(RDDQC) : PASS
7117 12:21:13.645237 TX DQ/DQS : PASS
7118 12:21:13.648975 RX DATLAT : PASS
7119 12:21:13.651932 RX DQ/DQS(Engine): PASS
7120 12:21:13.652011 TX OE : NO K
7121 12:21:13.655064 All Pass.
7122 12:21:13.655145
7123 12:21:13.655208 CH 1, Rank 1
7124 12:21:13.658555 SW Impedance : PASS
7125 12:21:13.658645 DUTY Scan : NO K
7126 12:21:13.661808 ZQ Calibration : PASS
7127 12:21:13.665116 Jitter Meter : NO K
7128 12:21:13.665196 CBT Training : PASS
7129 12:21:13.669119 Write leveling : NO K
7130 12:21:13.671723 RX DQS gating : PASS
7131 12:21:13.671804 RX DQ/DQS(RDDQC) : PASS
7132 12:21:13.675321 TX DQ/DQS : PASS
7133 12:21:13.678249 RX DATLAT : PASS
7134 12:21:13.678329 RX DQ/DQS(Engine): PASS
7135 12:21:13.681783 TX OE : NO K
7136 12:21:13.681864 All Pass.
7137 12:21:13.681927
7138 12:21:13.684956 DramC Write-DBI off
7139 12:21:13.688469 PER_BANK_REFRESH: Hybrid Mode
7140 12:21:13.688553 TX_TRACKING: ON
7141 12:21:13.698641 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7142 12:21:13.701510 [FAST_K] Save calibration result to emmc
7143 12:21:13.704912 dramc_set_vcore_voltage set vcore to 725000
7144 12:21:13.708168 Read voltage for 1600, 0
7145 12:21:13.708249 Vio18 = 0
7146 12:21:13.708313 Vcore = 725000
7147 12:21:13.711424 Vdram = 0
7148 12:21:13.711505 Vddq = 0
7149 12:21:13.711569 Vmddr = 0
7150 12:21:13.718089 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7151 12:21:13.721275 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7152 12:21:13.724410 MEM_TYPE=3, freq_sel=13
7153 12:21:13.727871 sv_algorithm_assistance_LP4_3733
7154 12:21:13.731315 ============ PULL DRAM RESETB DOWN ============
7155 12:21:13.734435 ========== PULL DRAM RESETB DOWN end =========
7156 12:21:13.741652 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7157 12:21:13.744768 ===================================
7158 12:21:13.744849 LPDDR4 DRAM CONFIGURATION
7159 12:21:13.747958 ===================================
7160 12:21:13.750915 EX_ROW_EN[0] = 0x0
7161 12:21:13.754697 EX_ROW_EN[1] = 0x0
7162 12:21:13.754777 LP4Y_EN = 0x0
7163 12:21:13.757583 WORK_FSP = 0x1
7164 12:21:13.757664 WL = 0x5
7165 12:21:13.761490 RL = 0x5
7166 12:21:13.761571 BL = 0x2
7167 12:21:13.764267 RPST = 0x0
7168 12:21:13.764347 RD_PRE = 0x0
7169 12:21:13.767288 WR_PRE = 0x1
7170 12:21:13.767368 WR_PST = 0x1
7171 12:21:13.771064 DBI_WR = 0x0
7172 12:21:13.771144 DBI_RD = 0x0
7173 12:21:13.774194 OTF = 0x1
7174 12:21:13.777597 ===================================
7175 12:21:13.780659 ===================================
7176 12:21:13.780740 ANA top config
7177 12:21:13.784278 ===================================
7178 12:21:13.787466 DLL_ASYNC_EN = 0
7179 12:21:13.790523 ALL_SLAVE_EN = 0
7180 12:21:13.793739 NEW_RANK_MODE = 1
7181 12:21:13.793821 DLL_IDLE_MODE = 1
7182 12:21:13.797723 LP45_APHY_COMB_EN = 1
7183 12:21:13.800593 TX_ODT_DIS = 0
7184 12:21:13.803712 NEW_8X_MODE = 1
7185 12:21:13.807199 ===================================
7186 12:21:13.810473 ===================================
7187 12:21:13.813862 data_rate = 3200
7188 12:21:13.816882 CKR = 1
7189 12:21:13.816962 DQ_P2S_RATIO = 8
7190 12:21:13.820371 ===================================
7191 12:21:13.823438 CA_P2S_RATIO = 8
7192 12:21:13.826729 DQ_CA_OPEN = 0
7193 12:21:13.830413 DQ_SEMI_OPEN = 0
7194 12:21:13.833268 CA_SEMI_OPEN = 0
7195 12:21:13.836865 CA_FULL_RATE = 0
7196 12:21:13.836945 DQ_CKDIV4_EN = 0
7197 12:21:13.839997 CA_CKDIV4_EN = 0
7198 12:21:13.843229 CA_PREDIV_EN = 0
7199 12:21:13.846909 PH8_DLY = 12
7200 12:21:13.849944 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7201 12:21:13.853554 DQ_AAMCK_DIV = 4
7202 12:21:13.853633 CA_AAMCK_DIV = 4
7203 12:21:13.856712 CA_ADMCK_DIV = 4
7204 12:21:13.860154 DQ_TRACK_CA_EN = 0
7205 12:21:13.863240 CA_PICK = 1600
7206 12:21:13.866571 CA_MCKIO = 1600
7207 12:21:13.870199 MCKIO_SEMI = 0
7208 12:21:13.873587 PLL_FREQ = 3068
7209 12:21:13.873668 DQ_UI_PI_RATIO = 32
7210 12:21:13.876965 CA_UI_PI_RATIO = 0
7211 12:21:13.879879 ===================================
7212 12:21:13.883139 ===================================
7213 12:21:13.886277 memory_type:LPDDR4
7214 12:21:13.889574 GP_NUM : 10
7215 12:21:13.889654 SRAM_EN : 1
7216 12:21:13.892850 MD32_EN : 0
7217 12:21:13.896083 ===================================
7218 12:21:13.899407 [ANA_INIT] >>>>>>>>>>>>>>
7219 12:21:13.902725 <<<<<< [CONFIGURE PHASE]: ANA_TX
7220 12:21:13.906003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7221 12:21:13.909490 ===================================
7222 12:21:13.909571 data_rate = 3200,PCW = 0X7600
7223 12:21:13.912490 ===================================
7224 12:21:13.915706 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7225 12:21:13.923238 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7226 12:21:13.929180 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7227 12:21:13.932731 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7228 12:21:13.935689 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7229 12:21:13.939404 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7230 12:21:13.942495 [ANA_INIT] flow start
7231 12:21:13.945973 [ANA_INIT] PLL >>>>>>>>
7232 12:21:13.946054 [ANA_INIT] PLL <<<<<<<<
7233 12:21:13.948952 [ANA_INIT] MIDPI >>>>>>>>
7234 12:21:13.952995 [ANA_INIT] MIDPI <<<<<<<<
7235 12:21:13.953076 [ANA_INIT] DLL >>>>>>>>
7236 12:21:13.955597 [ANA_INIT] DLL <<<<<<<<
7237 12:21:13.959148 [ANA_INIT] flow end
7238 12:21:13.962241 ============ LP4 DIFF to SE enter ============
7239 12:21:13.965795 ============ LP4 DIFF to SE exit ============
7240 12:21:13.969734 [ANA_INIT] <<<<<<<<<<<<<
7241 12:21:13.972132 [Flow] Enable top DCM control >>>>>
7242 12:21:13.975483 [Flow] Enable top DCM control <<<<<
7243 12:21:13.978854 Enable DLL master slave shuffle
7244 12:21:13.982112 ==============================================================
7245 12:21:13.985708 Gating Mode config
7246 12:21:13.991883 ==============================================================
7247 12:21:13.991963 Config description:
7248 12:21:14.001765 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7249 12:21:14.008491 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7250 12:21:14.014891 SELPH_MODE 0: By rank 1: By Phase
7251 12:21:14.018235 ==============================================================
7252 12:21:14.021668 GAT_TRACK_EN = 1
7253 12:21:14.025206 RX_GATING_MODE = 2
7254 12:21:14.028424 RX_GATING_TRACK_MODE = 2
7255 12:21:14.031987 SELPH_MODE = 1
7256 12:21:14.035244 PICG_EARLY_EN = 1
7257 12:21:14.038392 VALID_LAT_VALUE = 1
7258 12:21:14.041361 ==============================================================
7259 12:21:14.044754 Enter into Gating configuration >>>>
7260 12:21:14.048617 Exit from Gating configuration <<<<
7261 12:21:14.051532 Enter into DVFS_PRE_config >>>>>
7262 12:21:14.064404 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7263 12:21:14.068028 Exit from DVFS_PRE_config <<<<<
7264 12:21:14.071336 Enter into PICG configuration >>>>
7265 12:21:14.074554 Exit from PICG configuration <<<<
7266 12:21:14.074682 [RX_INPUT] configuration >>>>>
7267 12:21:14.077819 [RX_INPUT] configuration <<<<<
7268 12:21:14.084556 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7269 12:21:14.087711 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7270 12:21:14.094511 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7271 12:21:14.101044 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7272 12:21:14.107859 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7273 12:21:14.114501 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7274 12:21:14.117553 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7275 12:21:14.121068 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7276 12:21:14.127245 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7277 12:21:14.130714 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7278 12:21:14.134268 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7279 12:21:14.137962 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7280 12:21:14.140593 ===================================
7281 12:21:14.144554 LPDDR4 DRAM CONFIGURATION
7282 12:21:14.147395 ===================================
7283 12:21:14.150886 EX_ROW_EN[0] = 0x0
7284 12:21:14.150967 EX_ROW_EN[1] = 0x0
7285 12:21:14.153682 LP4Y_EN = 0x0
7286 12:21:14.153762 WORK_FSP = 0x1
7287 12:21:14.157394 WL = 0x5
7288 12:21:14.157505 RL = 0x5
7289 12:21:14.160614 BL = 0x2
7290 12:21:14.160694 RPST = 0x0
7291 12:21:14.163635 RD_PRE = 0x0
7292 12:21:14.163715 WR_PRE = 0x1
7293 12:21:14.167144 WR_PST = 0x1
7294 12:21:14.170683 DBI_WR = 0x0
7295 12:21:14.170763 DBI_RD = 0x0
7296 12:21:14.173948 OTF = 0x1
7297 12:21:14.177120 ===================================
7298 12:21:14.180143 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7299 12:21:14.183627 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7300 12:21:14.187069 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7301 12:21:14.190079 ===================================
7302 12:21:14.193652 LPDDR4 DRAM CONFIGURATION
7303 12:21:14.196549 ===================================
7304 12:21:14.200068 EX_ROW_EN[0] = 0x10
7305 12:21:14.200149 EX_ROW_EN[1] = 0x0
7306 12:21:14.203467 LP4Y_EN = 0x0
7307 12:21:14.203577 WORK_FSP = 0x1
7308 12:21:14.207161 WL = 0x5
7309 12:21:14.207241 RL = 0x5
7310 12:21:14.209890 BL = 0x2
7311 12:21:14.213235 RPST = 0x0
7312 12:21:14.213323 RD_PRE = 0x0
7313 12:21:14.216654 WR_PRE = 0x1
7314 12:21:14.216735 WR_PST = 0x1
7315 12:21:14.219523 DBI_WR = 0x0
7316 12:21:14.219604 DBI_RD = 0x0
7317 12:21:14.223179 OTF = 0x1
7318 12:21:14.226198 ===================================
7319 12:21:14.229576 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7320 12:21:14.233041 ==
7321 12:21:14.236107 Dram Type= 6, Freq= 0, CH_0, rank 0
7322 12:21:14.239512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7323 12:21:14.239597 ==
7324 12:21:14.242529 [Duty_Offset_Calibration]
7325 12:21:14.242667 B0:1 B1:-1 CA:0
7326 12:21:14.242733
7327 12:21:14.245873 [DutyScan_Calibration_Flow] k_type=0
7328 12:21:14.256338
7329 12:21:14.256418 ==CLK 0==
7330 12:21:14.259357 Final CLK duty delay cell = 0
7331 12:21:14.262985 [0] MAX Duty = 5124%(X100), DQS PI = 22
7332 12:21:14.266344 [0] MIN Duty = 4907%(X100), DQS PI = 4
7333 12:21:14.266424 [0] AVG Duty = 5015%(X100)
7334 12:21:14.269350
7335 12:21:14.272785 CH0 CLK Duty spec in!! Max-Min= 217%
7336 12:21:14.276366 [DutyScan_Calibration_Flow] ====Done====
7337 12:21:14.276446
7338 12:21:14.279563 [DutyScan_Calibration_Flow] k_type=1
7339 12:21:14.295364
7340 12:21:14.295444 ==DQS 0 ==
7341 12:21:14.298496 Final DQS duty delay cell = -4
7342 12:21:14.302157 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7343 12:21:14.305507 [-4] MIN Duty = 4844%(X100), DQS PI = 58
7344 12:21:14.308929 [-4] AVG Duty = 4922%(X100)
7345 12:21:14.309009
7346 12:21:14.309071 ==DQS 1 ==
7347 12:21:14.312003 Final DQS duty delay cell = 0
7348 12:21:14.315661 [0] MAX Duty = 5156%(X100), DQS PI = 0
7349 12:21:14.318398 [0] MIN Duty = 5031%(X100), DQS PI = 20
7350 12:21:14.321772 [0] AVG Duty = 5093%(X100)
7351 12:21:14.321852
7352 12:21:14.326550 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7353 12:21:14.326668
7354 12:21:14.328516 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7355 12:21:14.332020 [DutyScan_Calibration_Flow] ====Done====
7356 12:21:14.332099
7357 12:21:14.334774 [DutyScan_Calibration_Flow] k_type=3
7358 12:21:14.353146
7359 12:21:14.353226 ==DQM 0 ==
7360 12:21:14.356383 Final DQM duty delay cell = 0
7361 12:21:14.359601 [0] MAX Duty = 5124%(X100), DQS PI = 24
7362 12:21:14.362921 [0] MIN Duty = 4907%(X100), DQS PI = 8
7363 12:21:14.363001 [0] AVG Duty = 5015%(X100)
7364 12:21:14.366391
7365 12:21:14.366470 ==DQM 1 ==
7366 12:21:14.369718 Final DQM duty delay cell = 0
7367 12:21:14.372900 [0] MAX Duty = 5031%(X100), DQS PI = 10
7368 12:21:14.376114 [0] MIN Duty = 4782%(X100), DQS PI = 20
7369 12:21:14.379609 [0] AVG Duty = 4906%(X100)
7370 12:21:14.379688
7371 12:21:14.382529 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7372 12:21:14.382634
7373 12:21:14.386201 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7374 12:21:14.389540 [DutyScan_Calibration_Flow] ====Done====
7375 12:21:14.389622
7376 12:21:14.392715 [DutyScan_Calibration_Flow] k_type=2
7377 12:21:14.409804
7378 12:21:14.409884 ==DQ 0 ==
7379 12:21:14.412927 Final DQ duty delay cell = -4
7380 12:21:14.415665 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7381 12:21:14.419278 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7382 12:21:14.422743 [-4] AVG Duty = 4953%(X100)
7383 12:21:14.422822
7384 12:21:14.422884 ==DQ 1 ==
7385 12:21:14.425505 Final DQ duty delay cell = 0
7386 12:21:14.429765 [0] MAX Duty = 5125%(X100), DQS PI = 2
7387 12:21:14.432261 [0] MIN Duty = 5000%(X100), DQS PI = 36
7388 12:21:14.435296 [0] AVG Duty = 5062%(X100)
7389 12:21:14.435377
7390 12:21:14.438736 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7391 12:21:14.438820
7392 12:21:14.442152 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7393 12:21:14.445427 [DutyScan_Calibration_Flow] ====Done====
7394 12:21:14.445507 ==
7395 12:21:14.448935 Dram Type= 6, Freq= 0, CH_1, rank 0
7396 12:21:14.452124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7397 12:21:14.452205 ==
7398 12:21:14.455590 [Duty_Offset_Calibration]
7399 12:21:14.455696 B0:-1 B1:1 CA:2
7400 12:21:14.455788
7401 12:21:14.458895 [DutyScan_Calibration_Flow] k_type=0
7402 12:21:14.469901
7403 12:21:14.469982 ==CLK 0==
7404 12:21:14.473711 Final CLK duty delay cell = 0
7405 12:21:14.476799 [0] MAX Duty = 5187%(X100), DQS PI = 22
7406 12:21:14.479693 [0] MIN Duty = 4969%(X100), DQS PI = 62
7407 12:21:14.482999 [0] AVG Duty = 5078%(X100)
7408 12:21:14.483080
7409 12:21:14.486457 CH1 CLK Duty spec in!! Max-Min= 218%
7410 12:21:14.489589 [DutyScan_Calibration_Flow] ====Done====
7411 12:21:14.489670
7412 12:21:14.493050 [DutyScan_Calibration_Flow] k_type=1
7413 12:21:14.509348
7414 12:21:14.509428 ==DQS 0 ==
7415 12:21:14.512831 Final DQS duty delay cell = 0
7416 12:21:14.516096 [0] MAX Duty = 5156%(X100), DQS PI = 18
7417 12:21:14.519549 [0] MIN Duty = 4907%(X100), DQS PI = 8
7418 12:21:14.522667 [0] AVG Duty = 5031%(X100)
7419 12:21:14.522747
7420 12:21:14.522811 ==DQS 1 ==
7421 12:21:14.526039 Final DQS duty delay cell = 0
7422 12:21:14.529600 [0] MAX Duty = 5093%(X100), DQS PI = 26
7423 12:21:14.532427 [0] MIN Duty = 4969%(X100), DQS PI = 54
7424 12:21:14.535663 [0] AVG Duty = 5031%(X100)
7425 12:21:14.535743
7426 12:21:14.539116 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7427 12:21:14.539197
7428 12:21:14.542584 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7429 12:21:14.546031 [DutyScan_Calibration_Flow] ====Done====
7430 12:21:14.546111
7431 12:21:14.549174 [DutyScan_Calibration_Flow] k_type=3
7432 12:21:14.565403
7433 12:21:14.565484 ==DQM 0 ==
7434 12:21:14.569215 Final DQM duty delay cell = -4
7435 12:21:14.572136 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7436 12:21:14.575919 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7437 12:21:14.578963 [-4] AVG Duty = 4937%(X100)
7438 12:21:14.579044
7439 12:21:14.579107 ==DQM 1 ==
7440 12:21:14.582088 Final DQM duty delay cell = 0
7441 12:21:14.585257 [0] MAX Duty = 5156%(X100), DQS PI = 6
7442 12:21:14.588752 [0] MIN Duty = 4969%(X100), DQS PI = 34
7443 12:21:14.591804 [0] AVG Duty = 5062%(X100)
7444 12:21:14.591915
7445 12:21:14.595271 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7446 12:21:14.595352
7447 12:21:14.598806 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7448 12:21:14.602104 [DutyScan_Calibration_Flow] ====Done====
7449 12:21:14.602185
7450 12:21:14.604952 [DutyScan_Calibration_Flow] k_type=2
7451 12:21:14.623085
7452 12:21:14.623166 ==DQ 0 ==
7453 12:21:14.626250 Final DQ duty delay cell = 0
7454 12:21:14.629821 [0] MAX Duty = 5187%(X100), DQS PI = 32
7455 12:21:14.632824 [0] MIN Duty = 4906%(X100), DQS PI = 10
7456 12:21:14.632905 [0] AVG Duty = 5046%(X100)
7457 12:21:14.636083
7458 12:21:14.636163 ==DQ 1 ==
7459 12:21:14.639616 Final DQ duty delay cell = 0
7460 12:21:14.642367 [0] MAX Duty = 5156%(X100), DQS PI = 8
7461 12:21:14.646149 [0] MIN Duty = 4969%(X100), DQS PI = 56
7462 12:21:14.646231 [0] AVG Duty = 5062%(X100)
7463 12:21:14.648913
7464 12:21:14.652659 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7465 12:21:14.652740
7466 12:21:14.656598 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7467 12:21:14.659529 [DutyScan_Calibration_Flow] ====Done====
7468 12:21:14.662510 nWR fixed to 30
7469 12:21:14.662596 [ModeRegInit_LP4] CH0 RK0
7470 12:21:14.665669 [ModeRegInit_LP4] CH0 RK1
7471 12:21:14.668769 [ModeRegInit_LP4] CH1 RK0
7472 12:21:14.672221 [ModeRegInit_LP4] CH1 RK1
7473 12:21:14.672301 match AC timing 5
7474 12:21:14.678781 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7475 12:21:14.682534 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7476 12:21:14.685604 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7477 12:21:14.692124 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7478 12:21:14.695253 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7479 12:21:14.695334 [MiockJmeterHQA]
7480 12:21:14.695398
7481 12:21:14.698543 [DramcMiockJmeter] u1RxGatingPI = 0
7482 12:21:14.702080 0 : 4252, 4027
7483 12:21:14.702163 4 : 4364, 4137
7484 12:21:14.705264 8 : 4253, 4026
7485 12:21:14.705347 12 : 4252, 4027
7486 12:21:14.708477 16 : 4258, 4031
7487 12:21:14.708559 20 : 4252, 4027
7488 12:21:14.708624 24 : 4363, 4137
7489 12:21:14.711833 28 : 4363, 4138
7490 12:21:14.711915 32 : 4253, 4026
7491 12:21:14.715034 36 : 4252, 4027
7492 12:21:14.715116 40 : 4252, 4027
7493 12:21:14.718490 44 : 4253, 4026
7494 12:21:14.718572 48 : 4255, 4029
7495 12:21:14.721508 52 : 4363, 4137
7496 12:21:14.721590 56 : 4253, 4027
7497 12:21:14.721655 60 : 4253, 4026
7498 12:21:14.724929 64 : 4252, 4029
7499 12:21:14.725010 68 : 4252, 4029
7500 12:21:14.728110 72 : 4250, 4026
7501 12:21:14.728192 76 : 4361, 4137
7502 12:21:14.731324 80 : 4360, 4137
7503 12:21:14.731406 84 : 4250, 4026
7504 12:21:14.734426 88 : 4253, 4028
7505 12:21:14.734524 92 : 4250, 753
7506 12:21:14.734596 96 : 4250, 0
7507 12:21:14.738025 100 : 4250, 0
7508 12:21:14.738107 104 : 4252, 0
7509 12:21:14.741066 108 : 4252, 0
7510 12:21:14.741148 112 : 4361, 0
7511 12:21:14.741213 116 : 4250, 0
7512 12:21:14.744226 120 : 4360, 0
7513 12:21:14.744308 124 : 4360, 0
7514 12:21:14.747961 128 : 4250, 0
7515 12:21:14.748043 132 : 4250, 0
7516 12:21:14.748108 136 : 4250, 0
7517 12:21:14.751312 140 : 4250, 0
7518 12:21:14.751394 144 : 4250, 0
7519 12:21:14.751459 148 : 4252, 0
7520 12:21:14.754328 152 : 4250, 0
7521 12:21:14.754411 156 : 4250, 0
7522 12:21:14.757782 160 : 4252, 0
7523 12:21:14.757864 164 : 4361, 0
7524 12:21:14.757932 168 : 4360, 0
7525 12:21:14.761057 172 : 4250, 0
7526 12:21:14.761139 176 : 4360, 0
7527 12:21:14.764599 180 : 4250, 0
7528 12:21:14.764681 184 : 4250, 0
7529 12:21:14.764746 188 : 4250, 0
7530 12:21:14.767674 192 : 4250, 0
7531 12:21:14.767756 196 : 4250, 0
7532 12:21:14.770952 200 : 4252, 0
7533 12:21:14.771034 204 : 4250, 0
7534 12:21:14.771099 208 : 4251, 0
7535 12:21:14.774205 212 : 4252, 0
7536 12:21:14.774287 216 : 4250, 0
7537 12:21:14.774352 220 : 4360, 0
7538 12:21:14.777659 224 : 4361, 123
7539 12:21:14.777742 228 : 4250, 3176
7540 12:21:14.780985 232 : 4361, 4137
7541 12:21:14.781070 236 : 4250, 4027
7542 12:21:14.784013 240 : 4360, 4138
7543 12:21:14.784095 244 : 4361, 4138
7544 12:21:14.787674 248 : 4250, 4026
7545 12:21:14.787756 252 : 4250, 4027
7546 12:21:14.791253 256 : 4363, 4140
7547 12:21:14.791336 260 : 4250, 4026
7548 12:21:14.793935 264 : 4250, 4026
7549 12:21:14.794056 268 : 4250, 4027
7550 12:21:14.797186 272 : 4250, 4027
7551 12:21:14.797268 276 : 4250, 4027
7552 12:21:14.800436 280 : 4250, 4026
7553 12:21:14.800518 284 : 4361, 4137
7554 12:21:14.800582 288 : 4250, 4027
7555 12:21:14.803969 292 : 4250, 4027
7556 12:21:14.804051 296 : 4361, 4137
7557 12:21:14.807184 300 : 4250, 4026
7558 12:21:14.807270 304 : 4250, 4027
7559 12:21:14.810384 308 : 4363, 4140
7560 12:21:14.810466 312 : 4250, 4026
7561 12:21:14.813593 316 : 4250, 4026
7562 12:21:14.813675 320 : 4250, 4027
7563 12:21:14.816971 324 : 4250, 4027
7564 12:21:14.817053 328 : 4250, 4027
7565 12:21:14.820700 332 : 4250, 4026
7566 12:21:14.820782 336 : 4361, 3804
7567 12:21:14.824156 340 : 4250, 1801
7568 12:21:14.824237
7569 12:21:14.824322 MIOCK jitter meter ch=0
7570 12:21:14.824383
7571 12:21:14.827153 1T = (340-92) = 248 dly cells
7572 12:21:14.834405 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7573 12:21:14.834486 ==
7574 12:21:14.836635 Dram Type= 6, Freq= 0, CH_0, rank 0
7575 12:21:14.840031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7576 12:21:14.840112 ==
7577 12:21:14.846831 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7578 12:21:14.850313 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7579 12:21:14.853387 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7580 12:21:14.859971 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7581 12:21:14.869576 [CA 0] Center 43 (13~74) winsize 62
7582 12:21:14.872901 [CA 1] Center 43 (13~74) winsize 62
7583 12:21:14.876251 [CA 2] Center 39 (10~69) winsize 60
7584 12:21:14.879714 [CA 3] Center 39 (9~69) winsize 61
7585 12:21:14.882775 [CA 4] Center 37 (8~66) winsize 59
7586 12:21:14.886247 [CA 5] Center 36 (7~66) winsize 60
7587 12:21:14.886328
7588 12:21:14.889613 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7589 12:21:14.889694
7590 12:21:14.896163 [CATrainingPosCal] consider 1 rank data
7591 12:21:14.896244 u2DelayCellTimex100 = 262/100 ps
7592 12:21:14.902737 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7593 12:21:14.905802 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7594 12:21:14.909860 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7595 12:21:14.912578 CA3 delay=39 (9~69),Diff = 3 PI (11 cell)
7596 12:21:14.915975 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7597 12:21:14.919379 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7598 12:21:14.919460
7599 12:21:14.922495 CA PerBit enable=1, Macro0, CA PI delay=36
7600 12:21:14.922579
7601 12:21:14.925562 [CBTSetCACLKResult] CA Dly = 36
7602 12:21:14.929427 CS Dly: 12 (0~43)
7603 12:21:14.932519 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7604 12:21:14.935872 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7605 12:21:14.935953 ==
7606 12:21:14.939176 Dram Type= 6, Freq= 0, CH_0, rank 1
7607 12:21:14.945572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7608 12:21:14.945653 ==
7609 12:21:14.948527 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7610 12:21:14.955372 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7611 12:21:14.958629 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7612 12:21:14.965098 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7613 12:21:14.973327 [CA 0] Center 42 (12~73) winsize 62
7614 12:21:14.976948 [CA 1] Center 43 (13~73) winsize 61
7615 12:21:14.980089 [CA 2] Center 37 (8~67) winsize 60
7616 12:21:14.983537 [CA 3] Center 37 (7~67) winsize 61
7617 12:21:14.986796 [CA 4] Center 35 (6~65) winsize 60
7618 12:21:14.989774 [CA 5] Center 35 (5~65) winsize 61
7619 12:21:14.989855
7620 12:21:14.993355 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7621 12:21:14.993436
7622 12:21:14.996407 [CATrainingPosCal] consider 2 rank data
7623 12:21:14.999986 u2DelayCellTimex100 = 262/100 ps
7624 12:21:15.006526 CA0 delay=43 (13~73),Diff = 7 PI (26 cell)
7625 12:21:15.009940 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7626 12:21:15.013430 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7627 12:21:15.016814 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7628 12:21:15.019714 CA4 delay=36 (8~65),Diff = 0 PI (0 cell)
7629 12:21:15.022951 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7630 12:21:15.023031
7631 12:21:15.026213 CA PerBit enable=1, Macro0, CA PI delay=36
7632 12:21:15.026294
7633 12:21:15.029638 [CBTSetCACLKResult] CA Dly = 36
7634 12:21:15.033162 CS Dly: 12 (0~43)
7635 12:21:15.036000 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7636 12:21:15.039290 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7637 12:21:15.039370
7638 12:21:15.042912 ----->DramcWriteLeveling(PI) begin...
7639 12:21:15.042994 ==
7640 12:21:15.046028 Dram Type= 6, Freq= 0, CH_0, rank 0
7641 12:21:15.052638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7642 12:21:15.052719 ==
7643 12:21:15.055674 Write leveling (Byte 0): 36 => 36
7644 12:21:15.058952 Write leveling (Byte 1): 27 => 27
7645 12:21:15.062214 DramcWriteLeveling(PI) end<-----
7646 12:21:15.062295
7647 12:21:15.062358 ==
7648 12:21:15.065631 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 12:21:15.069286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 12:21:15.069367 ==
7651 12:21:15.072535 [Gating] SW mode calibration
7652 12:21:15.079094 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7653 12:21:15.082828 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7654 12:21:15.088908 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 12:21:15.092456 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 12:21:15.095778 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 12:21:15.102123 1 4 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7658 12:21:15.105832 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7659 12:21:15.108658 1 4 20 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7660 12:21:15.116007 1 4 24 | B1->B0 | 3332 3434 | 1 1 | (1 1) (1 1)
7661 12:21:15.118934 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7662 12:21:15.122152 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7663 12:21:15.128553 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7664 12:21:15.132241 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7665 12:21:15.135151 1 5 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
7666 12:21:15.142006 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7667 12:21:15.145028 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
7668 12:21:15.148430 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
7669 12:21:15.154948 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7670 12:21:15.158164 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7671 12:21:15.161629 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7672 12:21:15.168040 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7673 12:21:15.171333 1 6 12 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
7674 12:21:15.174864 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7675 12:21:15.181358 1 6 20 | B1->B0 | 2e2e 4646 | 0 0 | (1 1) (0 0)
7676 12:21:15.184936 1 6 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7677 12:21:15.188186 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7678 12:21:15.194358 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7679 12:21:15.198097 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7680 12:21:15.201302 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7681 12:21:15.208303 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7682 12:21:15.211295 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7683 12:21:15.214792 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7684 12:21:15.221102 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 12:21:15.224529 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 12:21:15.228114 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 12:21:15.234273 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 12:21:15.237600 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 12:21:15.240986 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 12:21:15.247591 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 12:21:15.250929 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 12:21:15.254065 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 12:21:15.260667 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 12:21:15.263947 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 12:21:15.267214 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 12:21:15.273926 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 12:21:15.277552 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7698 12:21:15.280455 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7699 12:21:15.283869 Total UI for P1: 0, mck2ui 16
7700 12:21:15.287065 best dqsien dly found for B0: ( 1, 9, 12)
7701 12:21:15.294131 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7702 12:21:15.297096 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7703 12:21:15.300409 Total UI for P1: 0, mck2ui 16
7704 12:21:15.303376 best dqsien dly found for B1: ( 1, 9, 18)
7705 12:21:15.306754 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7706 12:21:15.310135 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7707 12:21:15.310215
7708 12:21:15.313880 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7709 12:21:15.319896 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7710 12:21:15.319978 [Gating] SW calibration Done
7711 12:21:15.320042 ==
7712 12:21:15.323551 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 12:21:15.329701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 12:21:15.329783 ==
7715 12:21:15.329847 RX Vref Scan: 0
7716 12:21:15.329907
7717 12:21:15.333006 RX Vref 0 -> 0, step: 1
7718 12:21:15.333087
7719 12:21:15.336835 RX Delay 0 -> 252, step: 8
7720 12:21:15.339591 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7721 12:21:15.342892 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7722 12:21:15.346532 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7723 12:21:15.352850 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7724 12:21:15.356413 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7725 12:21:15.359410 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7726 12:21:15.363174 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7727 12:21:15.366042 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7728 12:21:15.372663 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7729 12:21:15.375718 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7730 12:21:15.379666 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7731 12:21:15.382913 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7732 12:21:15.386051 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7733 12:21:15.392327 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7734 12:21:15.395533 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7735 12:21:15.399098 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7736 12:21:15.399178 ==
7737 12:21:15.402026 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 12:21:15.405601 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 12:21:15.408686 ==
7740 12:21:15.408766 DQS Delay:
7741 12:21:15.408830 DQS0 = 0, DQS1 = 0
7742 12:21:15.412150 DQM Delay:
7743 12:21:15.412230 DQM0 = 136, DQM1 = 126
7744 12:21:15.415679 DQ Delay:
7745 12:21:15.418711 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7746 12:21:15.422066 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =147
7747 12:21:15.425383 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7748 12:21:15.429388 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7749 12:21:15.429468
7750 12:21:15.429532
7751 12:21:15.429590 ==
7752 12:21:15.431861 Dram Type= 6, Freq= 0, CH_0, rank 0
7753 12:21:15.435208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7754 12:21:15.435288 ==
7755 12:21:15.438692
7756 12:21:15.438801
7757 12:21:15.438899 TX Vref Scan disable
7758 12:21:15.441504 == TX Byte 0 ==
7759 12:21:15.444779 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7760 12:21:15.448440 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7761 12:21:15.451380 == TX Byte 1 ==
7762 12:21:15.455013 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7763 12:21:15.458170 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7764 12:21:15.461775 ==
7765 12:21:15.464485 Dram Type= 6, Freq= 0, CH_0, rank 0
7766 12:21:15.467876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7767 12:21:15.467957 ==
7768 12:21:15.481109
7769 12:21:15.484160 TX Vref early break, caculate TX vref
7770 12:21:15.487694 TX Vref=16, minBit 4, minWin=22, winSum=370
7771 12:21:15.490798 TX Vref=18, minBit 1, minWin=23, winSum=379
7772 12:21:15.494307 TX Vref=20, minBit 2, minWin=23, winSum=388
7773 12:21:15.497303 TX Vref=22, minBit 1, minWin=24, winSum=400
7774 12:21:15.500597 TX Vref=24, minBit 3, minWin=24, winSum=405
7775 12:21:15.507162 TX Vref=26, minBit 0, minWin=25, winSum=412
7776 12:21:15.510584 TX Vref=28, minBit 0, minWin=25, winSum=418
7777 12:21:15.513995 TX Vref=30, minBit 0, minWin=24, winSum=410
7778 12:21:15.517062 TX Vref=32, minBit 7, minWin=23, winSum=399
7779 12:21:15.520639 TX Vref=34, minBit 0, minWin=23, winSum=384
7780 12:21:15.527422 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
7781 12:21:15.527502
7782 12:21:15.530407 Final TX Range 0 Vref 28
7783 12:21:15.530487
7784 12:21:15.530549 ==
7785 12:21:15.533627 Dram Type= 6, Freq= 0, CH_0, rank 0
7786 12:21:15.537258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7787 12:21:15.537338 ==
7788 12:21:15.537402
7789 12:21:15.537460
7790 12:21:15.540448 TX Vref Scan disable
7791 12:21:15.546860 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7792 12:21:15.546960 == TX Byte 0 ==
7793 12:21:15.550136 u2DelayCellOfst[0]=14 cells (4 PI)
7794 12:21:15.553473 u2DelayCellOfst[1]=18 cells (5 PI)
7795 12:21:15.556565 u2DelayCellOfst[2]=14 cells (4 PI)
7796 12:21:15.560024 u2DelayCellOfst[3]=14 cells (4 PI)
7797 12:21:15.563372 u2DelayCellOfst[4]=11 cells (3 PI)
7798 12:21:15.566503 u2DelayCellOfst[5]=0 cells (0 PI)
7799 12:21:15.569965 u2DelayCellOfst[6]=22 cells (6 PI)
7800 12:21:15.573280 u2DelayCellOfst[7]=22 cells (6 PI)
7801 12:21:15.576902 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7802 12:21:15.579776 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7803 12:21:15.582892 == TX Byte 1 ==
7804 12:21:15.586939 u2DelayCellOfst[8]=0 cells (0 PI)
7805 12:21:15.590535 u2DelayCellOfst[9]=0 cells (0 PI)
7806 12:21:15.593406 u2DelayCellOfst[10]=3 cells (1 PI)
7807 12:21:15.593486 u2DelayCellOfst[11]=0 cells (0 PI)
7808 12:21:15.596462 u2DelayCellOfst[12]=11 cells (3 PI)
7809 12:21:15.600196 u2DelayCellOfst[13]=11 cells (3 PI)
7810 12:21:15.602995 u2DelayCellOfst[14]=11 cells (3 PI)
7811 12:21:15.606562 u2DelayCellOfst[15]=11 cells (3 PI)
7812 12:21:15.612864 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7813 12:21:15.616108 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7814 12:21:15.616188 DramC Write-DBI on
7815 12:21:15.619218 ==
7816 12:21:15.623086 Dram Type= 6, Freq= 0, CH_0, rank 0
7817 12:21:15.625805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7818 12:21:15.625892 ==
7819 12:21:15.625972
7820 12:21:15.626045
7821 12:21:15.629169 TX Vref Scan disable
7822 12:21:15.629248 == TX Byte 0 ==
7823 12:21:15.635686 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7824 12:21:15.635766 == TX Byte 1 ==
7825 12:21:15.639075 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7826 12:21:15.642219 DramC Write-DBI off
7827 12:21:15.642298
7828 12:21:15.642361 [DATLAT]
7829 12:21:15.645384 Freq=1600, CH0 RK0
7830 12:21:15.645489
7831 12:21:15.645579 DATLAT Default: 0xf
7832 12:21:15.648769 0, 0xFFFF, sum = 0
7833 12:21:15.651822 1, 0xFFFF, sum = 0
7834 12:21:15.651904 2, 0xFFFF, sum = 0
7835 12:21:15.655518 3, 0xFFFF, sum = 0
7836 12:21:15.655599 4, 0xFFFF, sum = 0
7837 12:21:15.658823 5, 0xFFFF, sum = 0
7838 12:21:15.658905 6, 0xFFFF, sum = 0
7839 12:21:15.662756 7, 0xFFFF, sum = 0
7840 12:21:15.662837 8, 0xFFFF, sum = 0
7841 12:21:15.665183 9, 0xFFFF, sum = 0
7842 12:21:15.665271 10, 0xFFFF, sum = 0
7843 12:21:15.668784 11, 0xFFFF, sum = 0
7844 12:21:15.668864 12, 0xFFFF, sum = 0
7845 12:21:15.672405 13, 0xFFFF, sum = 0
7846 12:21:15.672486 14, 0x0, sum = 1
7847 12:21:15.675033 15, 0x0, sum = 2
7848 12:21:15.675114 16, 0x0, sum = 3
7849 12:21:15.678559 17, 0x0, sum = 4
7850 12:21:15.678704 best_step = 15
7851 12:21:15.678795
7852 12:21:15.678881 ==
7853 12:21:15.681727 Dram Type= 6, Freq= 0, CH_0, rank 0
7854 12:21:15.688694 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7855 12:21:15.688775 ==
7856 12:21:15.688838 RX Vref Scan: 1
7857 12:21:15.688897
7858 12:21:15.691587 Set Vref Range= 24 -> 127
7859 12:21:15.691667
7860 12:21:15.695326 RX Vref 24 -> 127, step: 1
7861 12:21:15.695405
7862 12:21:15.695468 RX Delay 19 -> 252, step: 4
7863 12:21:15.695526
7864 12:21:15.698448 Set Vref, RX VrefLevel [Byte0]: 24
7865 12:21:15.701702 [Byte1]: 24
7866 12:21:15.705890
7867 12:21:15.705970 Set Vref, RX VrefLevel [Byte0]: 25
7868 12:21:15.709068 [Byte1]: 25
7869 12:21:15.713504
7870 12:21:15.713584 Set Vref, RX VrefLevel [Byte0]: 26
7871 12:21:15.716983 [Byte1]: 26
7872 12:21:15.720837
7873 12:21:15.720916 Set Vref, RX VrefLevel [Byte0]: 27
7874 12:21:15.724054 [Byte1]: 27
7875 12:21:15.728496
7876 12:21:15.728576 Set Vref, RX VrefLevel [Byte0]: 28
7877 12:21:15.731737 [Byte1]: 28
7878 12:21:15.736008
7879 12:21:15.736088 Set Vref, RX VrefLevel [Byte0]: 29
7880 12:21:15.739029 [Byte1]: 29
7881 12:21:15.743477
7882 12:21:15.743557 Set Vref, RX VrefLevel [Byte0]: 30
7883 12:21:15.746900 [Byte1]: 30
7884 12:21:15.750904
7885 12:21:15.751012 Set Vref, RX VrefLevel [Byte0]: 31
7886 12:21:15.754646 [Byte1]: 31
7887 12:21:15.758419
7888 12:21:15.758524 Set Vref, RX VrefLevel [Byte0]: 32
7889 12:21:15.762231 [Byte1]: 32
7890 12:21:15.766526
7891 12:21:15.766633 Set Vref, RX VrefLevel [Byte0]: 33
7892 12:21:15.769630 [Byte1]: 33
7893 12:21:15.774357
7894 12:21:15.774437 Set Vref, RX VrefLevel [Byte0]: 34
7895 12:21:15.777177 [Byte1]: 34
7896 12:21:15.781494
7897 12:21:15.781574 Set Vref, RX VrefLevel [Byte0]: 35
7898 12:21:15.784870 [Byte1]: 35
7899 12:21:15.788902
7900 12:21:15.788982 Set Vref, RX VrefLevel [Byte0]: 36
7901 12:21:15.791951 [Byte1]: 36
7902 12:21:15.796538
7903 12:21:15.796617 Set Vref, RX VrefLevel [Byte0]: 37
7904 12:21:15.799957 [Byte1]: 37
7905 12:21:15.804224
7906 12:21:15.804307 Set Vref, RX VrefLevel [Byte0]: 38
7907 12:21:15.807129 [Byte1]: 38
7908 12:21:15.812049
7909 12:21:15.812128 Set Vref, RX VrefLevel [Byte0]: 39
7910 12:21:15.815168 [Byte1]: 39
7911 12:21:15.819130
7912 12:21:15.819222 Set Vref, RX VrefLevel [Byte0]: 40
7913 12:21:15.822502 [Byte1]: 40
7914 12:21:15.826950
7915 12:21:15.827030 Set Vref, RX VrefLevel [Byte0]: 41
7916 12:21:15.830767 [Byte1]: 41
7917 12:21:15.834350
7918 12:21:15.834442 Set Vref, RX VrefLevel [Byte0]: 42
7919 12:21:15.837829 [Byte1]: 42
7920 12:21:15.841974
7921 12:21:15.842062 Set Vref, RX VrefLevel [Byte0]: 43
7922 12:21:15.845027 [Byte1]: 43
7923 12:21:15.849514
7924 12:21:15.849594 Set Vref, RX VrefLevel [Byte0]: 44
7925 12:21:15.852890 [Byte1]: 44
7926 12:21:15.857131
7927 12:21:15.857211 Set Vref, RX VrefLevel [Byte0]: 45
7928 12:21:15.860750 [Byte1]: 45
7929 12:21:15.864817
7930 12:21:15.864923 Set Vref, RX VrefLevel [Byte0]: 46
7931 12:21:15.868159 [Byte1]: 46
7932 12:21:15.872066
7933 12:21:15.872145 Set Vref, RX VrefLevel [Byte0]: 47
7934 12:21:15.875245 [Byte1]: 47
7935 12:21:15.879871
7936 12:21:15.879950 Set Vref, RX VrefLevel [Byte0]: 48
7937 12:21:15.883110 [Byte1]: 48
7938 12:21:15.887784
7939 12:21:15.887865 Set Vref, RX VrefLevel [Byte0]: 49
7940 12:21:15.890938 [Byte1]: 49
7941 12:21:15.895116
7942 12:21:15.895197 Set Vref, RX VrefLevel [Byte0]: 50
7943 12:21:15.898864 [Byte1]: 50
7944 12:21:15.902252
7945 12:21:15.902332 Set Vref, RX VrefLevel [Byte0]: 51
7946 12:21:15.905897 [Byte1]: 51
7947 12:21:15.910050
7948 12:21:15.910131 Set Vref, RX VrefLevel [Byte0]: 52
7949 12:21:15.913590 [Byte1]: 52
7950 12:21:15.917912
7951 12:21:15.917992 Set Vref, RX VrefLevel [Byte0]: 53
7952 12:21:15.921144 [Byte1]: 53
7953 12:21:15.924980
7954 12:21:15.925061 Set Vref, RX VrefLevel [Byte0]: 54
7955 12:21:15.928637 [Byte1]: 54
7956 12:21:15.933078
7957 12:21:15.933159 Set Vref, RX VrefLevel [Byte0]: 55
7958 12:21:15.939192 [Byte1]: 55
7959 12:21:15.939273
7960 12:21:15.942483 Set Vref, RX VrefLevel [Byte0]: 56
7961 12:21:15.945623 [Byte1]: 56
7962 12:21:15.945704
7963 12:21:15.949201 Set Vref, RX VrefLevel [Byte0]: 57
7964 12:21:15.952563 [Byte1]: 57
7965 12:21:15.952644
7966 12:21:15.956011 Set Vref, RX VrefLevel [Byte0]: 58
7967 12:21:15.959043 [Byte1]: 58
7968 12:21:15.963767
7969 12:21:15.963847 Set Vref, RX VrefLevel [Byte0]: 59
7970 12:21:15.966432 [Byte1]: 59
7971 12:21:15.970439
7972 12:21:15.970523 Set Vref, RX VrefLevel [Byte0]: 60
7973 12:21:15.973987 [Byte1]: 60
7974 12:21:15.978194
7975 12:21:15.978275 Set Vref, RX VrefLevel [Byte0]: 61
7976 12:21:15.981860 [Byte1]: 61
7977 12:21:15.985995
7978 12:21:15.986075 Set Vref, RX VrefLevel [Byte0]: 62
7979 12:21:15.989480 [Byte1]: 62
7980 12:21:15.993390
7981 12:21:15.993471 Set Vref, RX VrefLevel [Byte0]: 63
7982 12:21:15.997235 [Byte1]: 63
7983 12:21:16.001131
7984 12:21:16.001211 Set Vref, RX VrefLevel [Byte0]: 64
7985 12:21:16.004762 [Byte1]: 64
7986 12:21:16.008383
7987 12:21:16.008463 Set Vref, RX VrefLevel [Byte0]: 65
7988 12:21:16.011653 [Byte1]: 65
7989 12:21:16.016528
7990 12:21:16.016608 Set Vref, RX VrefLevel [Byte0]: 66
7991 12:21:16.019770 [Byte1]: 66
7992 12:21:16.023490
7993 12:21:16.023570 Set Vref, RX VrefLevel [Byte0]: 67
7994 12:21:16.026933 [Byte1]: 67
7995 12:21:16.031817
7996 12:21:16.031897 Set Vref, RX VrefLevel [Byte0]: 68
7997 12:21:16.034193 [Byte1]: 68
7998 12:21:16.038887
7999 12:21:16.038968 Set Vref, RX VrefLevel [Byte0]: 69
8000 12:21:16.042194 [Byte1]: 69
8001 12:21:16.046313
8002 12:21:16.046394 Set Vref, RX VrefLevel [Byte0]: 70
8003 12:21:16.049997 [Byte1]: 70
8004 12:21:16.054010
8005 12:21:16.054091 Set Vref, RX VrefLevel [Byte0]: 71
8006 12:21:16.056976 [Byte1]: 71
8007 12:21:16.061636
8008 12:21:16.061719 Set Vref, RX VrefLevel [Byte0]: 72
8009 12:21:16.067996 [Byte1]: 72
8010 12:21:16.068076
8011 12:21:16.071312 Set Vref, RX VrefLevel [Byte0]: 73
8012 12:21:16.074459 [Byte1]: 73
8013 12:21:16.074539
8014 12:21:16.077760 Set Vref, RX VrefLevel [Byte0]: 74
8015 12:21:16.081114 [Byte1]: 74
8016 12:21:16.081194
8017 12:21:16.084344 Set Vref, RX VrefLevel [Byte0]: 75
8018 12:21:16.087665 [Byte1]: 75
8019 12:21:16.091675
8020 12:21:16.091756 Set Vref, RX VrefLevel [Byte0]: 76
8021 12:21:16.094934 [Byte1]: 76
8022 12:21:16.099674
8023 12:21:16.099754 Set Vref, RX VrefLevel [Byte0]: 77
8024 12:21:16.102814 [Byte1]: 77
8025 12:21:16.106793
8026 12:21:16.106874 Set Vref, RX VrefLevel [Byte0]: 78
8027 12:21:16.110414 [Byte1]: 78
8028 12:21:16.114359
8029 12:21:16.114439 Final RX Vref Byte 0 = 67 to rank0
8030 12:21:16.117782 Final RX Vref Byte 1 = 58 to rank0
8031 12:21:16.120976 Final RX Vref Byte 0 = 67 to rank1
8032 12:21:16.124395 Final RX Vref Byte 1 = 58 to rank1==
8033 12:21:16.127495 Dram Type= 6, Freq= 0, CH_0, rank 0
8034 12:21:16.134065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8035 12:21:16.134145 ==
8036 12:21:16.134210 DQS Delay:
8037 12:21:16.137374 DQS0 = 0, DQS1 = 0
8038 12:21:16.137453 DQM Delay:
8039 12:21:16.140663 DQM0 = 133, DQM1 = 123
8040 12:21:16.140744 DQ Delay:
8041 12:21:16.143958 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =132
8042 12:21:16.147160 DQ4 =134, DQ5 =120, DQ6 =140, DQ7 =144
8043 12:21:16.150557 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =116
8044 12:21:16.153781 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =130
8045 12:21:16.153862
8046 12:21:16.153924
8047 12:21:16.153993
8048 12:21:16.157628 [DramC_TX_OE_Calibration] TA2
8049 12:21:16.160801 Original DQ_B0 (3 6) =30, OEN = 27
8050 12:21:16.164173 Original DQ_B1 (3 6) =30, OEN = 27
8051 12:21:16.166806 24, 0x0, End_B0=24 End_B1=24
8052 12:21:16.170252 25, 0x0, End_B0=25 End_B1=25
8053 12:21:16.170334 26, 0x0, End_B0=26 End_B1=26
8054 12:21:16.173511 27, 0x0, End_B0=27 End_B1=27
8055 12:21:16.177073 28, 0x0, End_B0=28 End_B1=28
8056 12:21:16.180320 29, 0x0, End_B0=29 End_B1=29
8057 12:21:16.180402 30, 0x0, End_B0=30 End_B1=30
8058 12:21:16.183346 31, 0x4545, End_B0=30 End_B1=30
8059 12:21:16.186736 Byte0 end_step=30 best_step=27
8060 12:21:16.190488 Byte1 end_step=30 best_step=27
8061 12:21:16.193348 Byte0 TX OE(2T, 0.5T) = (3, 3)
8062 12:21:16.196949 Byte1 TX OE(2T, 0.5T) = (3, 3)
8063 12:21:16.197035
8064 12:21:16.197097
8065 12:21:16.203353 [DQSOSCAuto] RK0, (LSB)MR18= 0x2011, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
8066 12:21:16.206995 CH0 RK0: MR19=303, MR18=2011
8067 12:21:16.213064 CH0_RK0: MR19=0x303, MR18=0x2011, DQSOSC=393, MR23=63, INC=23, DEC=15
8068 12:21:16.213146
8069 12:21:16.216263 ----->DramcWriteLeveling(PI) begin...
8070 12:21:16.216345 ==
8071 12:21:16.219862 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 12:21:16.223359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 12:21:16.223440 ==
8074 12:21:16.226252 Write leveling (Byte 0): 36 => 36
8075 12:21:16.229491 Write leveling (Byte 1): 27 => 27
8076 12:21:16.233262 DramcWriteLeveling(PI) end<-----
8077 12:21:16.233342
8078 12:21:16.233405 ==
8079 12:21:16.236272 Dram Type= 6, Freq= 0, CH_0, rank 1
8080 12:21:16.243262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8081 12:21:16.243370 ==
8082 12:21:16.243437 [Gating] SW mode calibration
8083 12:21:16.252657 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8084 12:21:16.255974 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8085 12:21:16.262351 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8086 12:21:16.265711 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8087 12:21:16.268911 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8088 12:21:16.275754 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8089 12:21:16.279186 1 4 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8090 12:21:16.282166 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8091 12:21:16.289027 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8092 12:21:16.292209 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8093 12:21:16.295354 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8094 12:21:16.302049 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8095 12:21:16.305187 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8096 12:21:16.308598 1 5 12 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
8097 12:21:16.315189 1 5 16 | B1->B0 | 3434 2525 | 0 0 | (0 1) (1 0)
8098 12:21:16.318613 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8099 12:21:16.321864 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8100 12:21:16.328279 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8101 12:21:16.331464 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8102 12:21:16.334770 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8103 12:21:16.341506 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8104 12:21:16.344715 1 6 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
8105 12:21:16.348256 1 6 16 | B1->B0 | 2929 4343 | 0 0 | (1 1) (0 0)
8106 12:21:16.354381 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8107 12:21:16.357983 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8108 12:21:16.361254 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8109 12:21:16.367838 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8110 12:21:16.371661 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8111 12:21:16.374340 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8112 12:21:16.380963 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8113 12:21:16.384480 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8114 12:21:16.387495 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8115 12:21:16.394237 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 12:21:16.397541 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 12:21:16.400622 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 12:21:16.407058 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 12:21:16.410461 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 12:21:16.414046 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 12:21:16.420587 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 12:21:16.424188 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 12:21:16.427635 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8124 12:21:16.433886 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8125 12:21:16.437058 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8126 12:21:16.441461 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 12:21:16.447125 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8128 12:21:16.450558 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8129 12:21:16.454048 Total UI for P1: 0, mck2ui 16
8130 12:21:16.457154 best dqsien dly found for B0: ( 1, 9, 8)
8131 12:21:16.460335 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8132 12:21:16.467157 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8133 12:21:16.470381 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8134 12:21:16.473616 Total UI for P1: 0, mck2ui 16
8135 12:21:16.476612 best dqsien dly found for B1: ( 1, 9, 16)
8136 12:21:16.480182 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8137 12:21:16.483636 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8138 12:21:16.483710
8139 12:21:16.486826 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8140 12:21:16.490152 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8141 12:21:16.493941 [Gating] SW calibration Done
8142 12:21:16.494042 ==
8143 12:21:16.496284 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 12:21:16.499854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 12:21:16.502972 ==
8146 12:21:16.503043 RX Vref Scan: 0
8147 12:21:16.503104
8148 12:21:16.506180 RX Vref 0 -> 0, step: 1
8149 12:21:16.506249
8150 12:21:16.506308 RX Delay 0 -> 252, step: 8
8151 12:21:16.513033 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8152 12:21:16.516168 iDelay=200, Bit 1, Center 139 (80 ~ 199) 120
8153 12:21:16.519405 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8154 12:21:16.523003 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8155 12:21:16.526517 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8156 12:21:16.533145 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8157 12:21:16.536131 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8158 12:21:16.540017 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8159 12:21:16.543100 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8160 12:21:16.546096 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8161 12:21:16.553019 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8162 12:21:16.556436 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8163 12:21:16.559441 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8164 12:21:16.562990 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8165 12:21:16.569114 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8166 12:21:16.572603 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8167 12:21:16.572703 ==
8168 12:21:16.576212 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 12:21:16.578973 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 12:21:16.579062 ==
8171 12:21:16.582375 DQS Delay:
8172 12:21:16.582482 DQS0 = 0, DQS1 = 0
8173 12:21:16.582572 DQM Delay:
8174 12:21:16.585764 DQM0 = 133, DQM1 = 129
8175 12:21:16.585866 DQ Delay:
8176 12:21:16.589250 DQ0 =135, DQ1 =139, DQ2 =127, DQ3 =127
8177 12:21:16.592095 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8178 12:21:16.599037 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =127
8179 12:21:16.602649 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8180 12:21:16.602751
8181 12:21:16.602852
8182 12:21:16.602941 ==
8183 12:21:16.605762 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 12:21:16.608863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 12:21:16.608966 ==
8186 12:21:16.609056
8187 12:21:16.609141
8188 12:21:16.612302 TX Vref Scan disable
8189 12:21:16.615673 == TX Byte 0 ==
8190 12:21:16.619321 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8191 12:21:16.621884 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8192 12:21:16.625518 == TX Byte 1 ==
8193 12:21:16.628499 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8194 12:21:16.631671 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8195 12:21:16.631752 ==
8196 12:21:16.635451 Dram Type= 6, Freq= 0, CH_0, rank 1
8197 12:21:16.638510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8198 12:21:16.641634 ==
8199 12:21:16.654073
8200 12:21:16.656738 TX Vref early break, caculate TX vref
8201 12:21:16.660143 TX Vref=16, minBit 1, minWin=22, winSum=378
8202 12:21:16.663889 TX Vref=18, minBit 0, minWin=23, winSum=387
8203 12:21:16.666798 TX Vref=20, minBit 1, minWin=23, winSum=395
8204 12:21:16.670125 TX Vref=22, minBit 1, minWin=23, winSum=398
8205 12:21:16.673788 TX Vref=24, minBit 3, minWin=24, winSum=411
8206 12:21:16.680088 TX Vref=26, minBit 0, minWin=25, winSum=415
8207 12:21:16.683384 TX Vref=28, minBit 0, minWin=25, winSum=410
8208 12:21:16.686993 TX Vref=30, minBit 0, minWin=24, winSum=401
8209 12:21:16.690187 TX Vref=32, minBit 0, minWin=24, winSum=395
8210 12:21:16.693561 TX Vref=34, minBit 1, minWin=23, winSum=385
8211 12:21:16.699864 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 26
8212 12:21:16.699948
8213 12:21:16.703159 Final TX Range 0 Vref 26
8214 12:21:16.703240
8215 12:21:16.703303 ==
8216 12:21:16.706354 Dram Type= 6, Freq= 0, CH_0, rank 1
8217 12:21:16.709980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8218 12:21:16.710061 ==
8219 12:21:16.710125
8220 12:21:16.710185
8221 12:21:16.713543 TX Vref Scan disable
8222 12:21:16.720162 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8223 12:21:16.720243 == TX Byte 0 ==
8224 12:21:16.722876 u2DelayCellOfst[0]=11 cells (3 PI)
8225 12:21:16.726268 u2DelayCellOfst[1]=14 cells (4 PI)
8226 12:21:16.729316 u2DelayCellOfst[2]=11 cells (3 PI)
8227 12:21:16.733073 u2DelayCellOfst[3]=11 cells (3 PI)
8228 12:21:16.736305 u2DelayCellOfst[4]=7 cells (2 PI)
8229 12:21:16.739424 u2DelayCellOfst[5]=0 cells (0 PI)
8230 12:21:16.742513 u2DelayCellOfst[6]=14 cells (4 PI)
8231 12:21:16.746303 u2DelayCellOfst[7]=18 cells (5 PI)
8232 12:21:16.749812 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8233 12:21:16.752680 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8234 12:21:16.755922 == TX Byte 1 ==
8235 12:21:16.759196 u2DelayCellOfst[8]=0 cells (0 PI)
8236 12:21:16.762557 u2DelayCellOfst[9]=0 cells (0 PI)
8237 12:21:16.765758 u2DelayCellOfst[10]=7 cells (2 PI)
8238 12:21:16.765868 u2DelayCellOfst[11]=0 cells (0 PI)
8239 12:21:16.769148 u2DelayCellOfst[12]=11 cells (3 PI)
8240 12:21:16.772516 u2DelayCellOfst[13]=11 cells (3 PI)
8241 12:21:16.776186 u2DelayCellOfst[14]=18 cells (5 PI)
8242 12:21:16.779385 u2DelayCellOfst[15]=11 cells (3 PI)
8243 12:21:16.785505 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8244 12:21:16.788957 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8245 12:21:16.789038 DramC Write-DBI on
8246 12:21:16.792354 ==
8247 12:21:16.792436 Dram Type= 6, Freq= 0, CH_0, rank 1
8248 12:21:16.798553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8249 12:21:16.798673 ==
8250 12:21:16.798746
8251 12:21:16.798807
8252 12:21:16.802070 TX Vref Scan disable
8253 12:21:16.802177 == TX Byte 0 ==
8254 12:21:16.808559 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8255 12:21:16.808648 == TX Byte 1 ==
8256 12:21:16.811690 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8257 12:21:16.815225 DramC Write-DBI off
8258 12:21:16.815300
8259 12:21:16.815362 [DATLAT]
8260 12:21:16.818582 Freq=1600, CH0 RK1
8261 12:21:16.818683
8262 12:21:16.818747 DATLAT Default: 0xf
8263 12:21:16.821997 0, 0xFFFF, sum = 0
8264 12:21:16.822063 1, 0xFFFF, sum = 0
8265 12:21:16.825242 2, 0xFFFF, sum = 0
8266 12:21:16.825308 3, 0xFFFF, sum = 0
8267 12:21:16.828415 4, 0xFFFF, sum = 0
8268 12:21:16.831662 5, 0xFFFF, sum = 0
8269 12:21:16.831764 6, 0xFFFF, sum = 0
8270 12:21:16.834859 7, 0xFFFF, sum = 0
8271 12:21:16.834942 8, 0xFFFF, sum = 0
8272 12:21:16.838147 9, 0xFFFF, sum = 0
8273 12:21:16.838230 10, 0xFFFF, sum = 0
8274 12:21:16.841674 11, 0xFFFF, sum = 0
8275 12:21:16.841756 12, 0xFFFF, sum = 0
8276 12:21:16.845136 13, 0xFFFF, sum = 0
8277 12:21:16.845222 14, 0x0, sum = 1
8278 12:21:16.848106 15, 0x0, sum = 2
8279 12:21:16.848188 16, 0x0, sum = 3
8280 12:21:16.851347 17, 0x0, sum = 4
8281 12:21:16.851429 best_step = 15
8282 12:21:16.851492
8283 12:21:16.851551 ==
8284 12:21:16.855359 Dram Type= 6, Freq= 0, CH_0, rank 1
8285 12:21:16.858469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 12:21:16.861595 ==
8287 12:21:16.861676 RX Vref Scan: 0
8288 12:21:16.861739
8289 12:21:16.865080 RX Vref 0 -> 0, step: 1
8290 12:21:16.865160
8291 12:21:16.868386 RX Delay 11 -> 252, step: 4
8292 12:21:16.871329 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8293 12:21:16.874355 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8294 12:21:16.877655 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8295 12:21:16.884583 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8296 12:21:16.887647 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8297 12:21:16.890600 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8298 12:21:16.894436 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8299 12:21:16.897558 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8300 12:21:16.904662 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8301 12:21:16.907672 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8302 12:21:16.910782 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8303 12:21:16.914312 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8304 12:21:16.920672 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8305 12:21:16.924195 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8306 12:21:16.927138 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8307 12:21:16.930536 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8308 12:21:16.930654 ==
8309 12:21:16.933835 Dram Type= 6, Freq= 0, CH_0, rank 1
8310 12:21:16.937084 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 12:21:16.940609 ==
8312 12:21:16.940690 DQS Delay:
8313 12:21:16.940753 DQS0 = 0, DQS1 = 0
8314 12:21:16.943659 DQM Delay:
8315 12:21:16.943740 DQM0 = 130, DQM1 = 125
8316 12:21:16.947024 DQ Delay:
8317 12:21:16.950738 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8318 12:21:16.953627 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =140
8319 12:21:16.957302 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8320 12:21:16.960215 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8321 12:21:16.960296
8322 12:21:16.960359
8323 12:21:16.960417
8324 12:21:16.963704 [DramC_TX_OE_Calibration] TA2
8325 12:21:16.966838 Original DQ_B0 (3 6) =30, OEN = 27
8326 12:21:16.970489 Original DQ_B1 (3 6) =30, OEN = 27
8327 12:21:16.973301 24, 0x0, End_B0=24 End_B1=24
8328 12:21:16.973382 25, 0x0, End_B0=25 End_B1=25
8329 12:21:16.976425 26, 0x0, End_B0=26 End_B1=26
8330 12:21:16.979735 27, 0x0, End_B0=27 End_B1=27
8331 12:21:16.983092 28, 0x0, End_B0=28 End_B1=28
8332 12:21:16.986563 29, 0x0, End_B0=29 End_B1=29
8333 12:21:16.986684 30, 0x0, End_B0=30 End_B1=30
8334 12:21:16.990075 31, 0x4141, End_B0=30 End_B1=30
8335 12:21:16.993488 Byte0 end_step=30 best_step=27
8336 12:21:16.996531 Byte1 end_step=30 best_step=27
8337 12:21:16.999645 Byte0 TX OE(2T, 0.5T) = (3, 3)
8338 12:21:17.002983 Byte1 TX OE(2T, 0.5T) = (3, 3)
8339 12:21:17.003083
8340 12:21:17.003172
8341 12:21:17.009597 [DQSOSCAuto] RK1, (LSB)MR18= 0x2205, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps
8342 12:21:17.012591 CH0 RK1: MR19=303, MR18=2205
8343 12:21:17.019559 CH0_RK1: MR19=0x303, MR18=0x2205, DQSOSC=392, MR23=63, INC=24, DEC=16
8344 12:21:17.022521 [RxdqsGatingPostProcess] freq 1600
8345 12:21:17.026209 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8346 12:21:17.029518 best DQS0 dly(2T, 0.5T) = (1, 1)
8347 12:21:17.032494 best DQS1 dly(2T, 0.5T) = (1, 1)
8348 12:21:17.035889 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8349 12:21:17.039462 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8350 12:21:17.042359 best DQS0 dly(2T, 0.5T) = (1, 1)
8351 12:21:17.045681 best DQS1 dly(2T, 0.5T) = (1, 1)
8352 12:21:17.049005 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8353 12:21:17.052231 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8354 12:21:17.055651 Pre-setting of DQS Precalculation
8355 12:21:17.059218 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8356 12:21:17.059318 ==
8357 12:21:17.062000 Dram Type= 6, Freq= 0, CH_1, rank 0
8358 12:21:17.068674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 12:21:17.068753 ==
8360 12:21:17.072677 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8361 12:21:17.079178 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8362 12:21:17.082118 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8363 12:21:17.088597 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8364 12:21:17.096318 [CA 0] Center 42 (12~72) winsize 61
8365 12:21:17.099957 [CA 1] Center 42 (13~72) winsize 60
8366 12:21:17.102804 [CA 2] Center 38 (9~67) winsize 59
8367 12:21:17.106409 [CA 3] Center 37 (8~66) winsize 59
8368 12:21:17.109977 [CA 4] Center 37 (8~67) winsize 60
8369 12:21:17.112983 [CA 5] Center 37 (8~67) winsize 60
8370 12:21:17.113081
8371 12:21:17.116396 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8372 12:21:17.116490
8373 12:21:17.120125 [CATrainingPosCal] consider 1 rank data
8374 12:21:17.122680 u2DelayCellTimex100 = 262/100 ps
8375 12:21:17.129789 CA0 delay=42 (12~72),Diff = 5 PI (18 cell)
8376 12:21:17.132974 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8377 12:21:17.136175 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8378 12:21:17.139685 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8379 12:21:17.143071 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8380 12:21:17.146045 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8381 12:21:17.146141
8382 12:21:17.149410 CA PerBit enable=1, Macro0, CA PI delay=37
8383 12:21:17.149514
8384 12:21:17.152496 [CBTSetCACLKResult] CA Dly = 37
8385 12:21:17.155501 CS Dly: 9 (0~40)
8386 12:21:17.158836 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8387 12:21:17.162192 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8388 12:21:17.162265 ==
8389 12:21:17.165813 Dram Type= 6, Freq= 0, CH_1, rank 1
8390 12:21:17.172321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8391 12:21:17.172400 ==
8392 12:21:17.175715 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8393 12:21:17.178859 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8394 12:21:17.185957 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8395 12:21:17.192385 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8396 12:21:17.199525 [CA 0] Center 42 (13~72) winsize 60
8397 12:21:17.203233 [CA 1] Center 42 (13~72) winsize 60
8398 12:21:17.206418 [CA 2] Center 38 (9~67) winsize 59
8399 12:21:17.209229 [CA 3] Center 37 (7~67) winsize 61
8400 12:21:17.212686 [CA 4] Center 37 (8~67) winsize 60
8401 12:21:17.216591 [CA 5] Center 37 (8~67) winsize 60
8402 12:21:17.216697
8403 12:21:17.219135 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8404 12:21:17.219207
8405 12:21:17.222830 [CATrainingPosCal] consider 2 rank data
8406 12:21:17.226000 u2DelayCellTimex100 = 262/100 ps
8407 12:21:17.232644 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8408 12:21:17.235761 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8409 12:21:17.239217 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8410 12:21:17.242270 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8411 12:21:17.245820 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8412 12:21:17.249374 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8413 12:21:17.249469
8414 12:21:17.252341 CA PerBit enable=1, Macro0, CA PI delay=37
8415 12:21:17.252443
8416 12:21:17.255564 [CBTSetCACLKResult] CA Dly = 37
8417 12:21:17.259098 CS Dly: 11 (0~44)
8418 12:21:17.262081 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8419 12:21:17.265635 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8420 12:21:17.265735
8421 12:21:17.268639 ----->DramcWriteLeveling(PI) begin...
8422 12:21:17.268739 ==
8423 12:21:17.272429 Dram Type= 6, Freq= 0, CH_1, rank 0
8424 12:21:17.278657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8425 12:21:17.278744 ==
8426 12:21:17.282002 Write leveling (Byte 0): 24 => 24
8427 12:21:17.285338 Write leveling (Byte 1): 29 => 29
8428 12:21:17.285442 DramcWriteLeveling(PI) end<-----
8429 12:21:17.285533
8430 12:21:17.289055 ==
8431 12:21:17.292309 Dram Type= 6, Freq= 0, CH_1, rank 0
8432 12:21:17.295104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8433 12:21:17.295213 ==
8434 12:21:17.298545 [Gating] SW mode calibration
8435 12:21:17.305021 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8436 12:21:17.308312 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8437 12:21:17.315432 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8438 12:21:17.318561 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8439 12:21:17.321706 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8440 12:21:17.328544 1 4 12 | B1->B0 | 3231 3434 | 1 1 | (1 1) (1 1)
8441 12:21:17.331367 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8442 12:21:17.334755 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8443 12:21:17.341146 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8444 12:21:17.344713 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8445 12:21:17.347745 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8446 12:21:17.354431 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8447 12:21:17.357411 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8448 12:21:17.361094 1 5 12 | B1->B0 | 2b2b 2424 | 1 0 | (1 0) (1 0)
8449 12:21:17.367471 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 12:21:17.370624 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8451 12:21:17.377339 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8452 12:21:17.380685 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8453 12:21:17.384268 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8454 12:21:17.387469 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8455 12:21:17.394171 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8456 12:21:17.397422 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8457 12:21:17.400348 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 12:21:17.407693 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8459 12:21:17.410520 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 12:21:17.413978 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8461 12:21:17.420295 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8462 12:21:17.423460 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8463 12:21:17.426882 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8464 12:21:17.433303 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8465 12:21:17.436803 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 12:21:17.440618 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 12:21:17.446681 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 12:21:17.450239 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 12:21:17.453708 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 12:21:17.460376 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 12:21:17.463258 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 12:21:17.467179 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 12:21:17.472999 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 12:21:17.476617 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 12:21:17.479804 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 12:21:17.486359 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 12:21:17.489559 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 12:21:17.493722 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 12:21:17.499428 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8480 12:21:17.503007 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8481 12:21:17.506165 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8482 12:21:17.509644 Total UI for P1: 0, mck2ui 16
8483 12:21:17.513028 best dqsien dly found for B0: ( 1, 9, 10)
8484 12:21:17.515842 Total UI for P1: 0, mck2ui 16
8485 12:21:17.519390 best dqsien dly found for B1: ( 1, 9, 12)
8486 12:21:17.522482 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8487 12:21:17.525943 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8488 12:21:17.529059
8489 12:21:17.532635 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8490 12:21:17.535863 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8491 12:21:17.539166 [Gating] SW calibration Done
8492 12:21:17.539262 ==
8493 12:21:17.542663 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 12:21:17.546179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 12:21:17.546274 ==
8496 12:21:17.549360 RX Vref Scan: 0
8497 12:21:17.549432
8498 12:21:17.549493 RX Vref 0 -> 0, step: 1
8499 12:21:17.549551
8500 12:21:17.552120 RX Delay 0 -> 252, step: 8
8501 12:21:17.555583 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8502 12:21:17.559148 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8503 12:21:17.565564 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8504 12:21:17.568839 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8505 12:21:17.572263 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8506 12:21:17.575214 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8507 12:21:17.578786 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8508 12:21:17.585327 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8509 12:21:17.588485 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8510 12:21:17.591989 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8511 12:21:17.595554 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8512 12:21:17.601554 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8513 12:21:17.605452 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8514 12:21:17.608605 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8515 12:21:17.611751 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8516 12:21:17.615350 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8517 12:21:17.618327 ==
8518 12:21:17.621863 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 12:21:17.624959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 12:21:17.625054 ==
8521 12:21:17.625145 DQS Delay:
8522 12:21:17.628400 DQS0 = 0, DQS1 = 0
8523 12:21:17.628469 DQM Delay:
8524 12:21:17.631464 DQM0 = 138, DQM1 = 130
8525 12:21:17.631532 DQ Delay:
8526 12:21:17.635045 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8527 12:21:17.638087 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8528 12:21:17.641124 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =123
8529 12:21:17.644742 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =143
8530 12:21:17.644834
8531 12:21:17.644924
8532 12:21:17.648182 ==
8533 12:21:17.648274 Dram Type= 6, Freq= 0, CH_1, rank 0
8534 12:21:17.654606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8535 12:21:17.654699 ==
8536 12:21:17.654761
8537 12:21:17.654820
8538 12:21:17.657900 TX Vref Scan disable
8539 12:21:17.657993 == TX Byte 0 ==
8540 12:21:17.661321 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8541 12:21:17.667934 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8542 12:21:17.668009 == TX Byte 1 ==
8543 12:21:17.671328 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8544 12:21:17.677762 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8545 12:21:17.677863 ==
8546 12:21:17.680930 Dram Type= 6, Freq= 0, CH_1, rank 0
8547 12:21:17.684250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8548 12:21:17.684346 ==
8549 12:21:17.696407
8550 12:21:17.699582 TX Vref early break, caculate TX vref
8551 12:21:17.702943 TX Vref=16, minBit 0, minWin=21, winSum=372
8552 12:21:17.706276 TX Vref=18, minBit 5, minWin=22, winSum=384
8553 12:21:17.709904 TX Vref=20, minBit 0, minWin=23, winSum=388
8554 12:21:17.712645 TX Vref=22, minBit 0, minWin=23, winSum=403
8555 12:21:17.716179 TX Vref=24, minBit 0, minWin=25, winSum=412
8556 12:21:17.722705 TX Vref=26, minBit 5, minWin=24, winSum=415
8557 12:21:17.725866 TX Vref=28, minBit 0, minWin=25, winSum=419
8558 12:21:17.729549 TX Vref=30, minBit 0, minWin=24, winSum=407
8559 12:21:17.732690 TX Vref=32, minBit 8, minWin=23, winSum=397
8560 12:21:17.739037 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
8561 12:21:17.739112
8562 12:21:17.742357 Final TX Range 0 Vref 28
8563 12:21:17.742431
8564 12:21:17.742492 ==
8565 12:21:17.745692 Dram Type= 6, Freq= 0, CH_1, rank 0
8566 12:21:17.749189 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8567 12:21:17.749286 ==
8568 12:21:17.749373
8569 12:21:17.749461
8570 12:21:17.752452 TX Vref Scan disable
8571 12:21:17.759034 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8572 12:21:17.759105 == TX Byte 0 ==
8573 12:21:17.762284 u2DelayCellOfst[0]=18 cells (5 PI)
8574 12:21:17.765686 u2DelayCellOfst[1]=11 cells (3 PI)
8575 12:21:17.769243 u2DelayCellOfst[2]=0 cells (0 PI)
8576 12:21:17.772045 u2DelayCellOfst[3]=3 cells (1 PI)
8577 12:21:17.775121 u2DelayCellOfst[4]=7 cells (2 PI)
8578 12:21:17.778979 u2DelayCellOfst[5]=18 cells (5 PI)
8579 12:21:17.782167 u2DelayCellOfst[6]=18 cells (5 PI)
8580 12:21:17.785490 u2DelayCellOfst[7]=7 cells (2 PI)
8581 12:21:17.788517 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8582 12:21:17.791661 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8583 12:21:17.795630 == TX Byte 1 ==
8584 12:21:17.795702 u2DelayCellOfst[8]=0 cells (0 PI)
8585 12:21:17.798853 u2DelayCellOfst[9]=7 cells (2 PI)
8586 12:21:17.801643 u2DelayCellOfst[10]=11 cells (3 PI)
8587 12:21:17.805448 u2DelayCellOfst[11]=7 cells (2 PI)
8588 12:21:17.808753 u2DelayCellOfst[12]=14 cells (4 PI)
8589 12:21:17.811969 u2DelayCellOfst[13]=18 cells (5 PI)
8590 12:21:17.814763 u2DelayCellOfst[14]=18 cells (5 PI)
8591 12:21:17.818163 u2DelayCellOfst[15]=18 cells (5 PI)
8592 12:21:17.821475 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8593 12:21:17.828358 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8594 12:21:17.828435 DramC Write-DBI on
8595 12:21:17.828498 ==
8596 12:21:17.831335 Dram Type= 6, Freq= 0, CH_1, rank 0
8597 12:21:17.838040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8598 12:21:17.838122 ==
8599 12:21:17.838185
8600 12:21:17.838244
8601 12:21:17.838300 TX Vref Scan disable
8602 12:21:17.841683 == TX Byte 0 ==
8603 12:21:17.845433 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8604 12:21:17.849059 == TX Byte 1 ==
8605 12:21:17.851790 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8606 12:21:17.854891 DramC Write-DBI off
8607 12:21:17.854963
8608 12:21:17.855023 [DATLAT]
8609 12:21:17.855080 Freq=1600, CH1 RK0
8610 12:21:17.855145
8611 12:21:17.858195 DATLAT Default: 0xf
8612 12:21:17.858265 0, 0xFFFF, sum = 0
8613 12:21:17.861611 1, 0xFFFF, sum = 0
8614 12:21:17.865035 2, 0xFFFF, sum = 0
8615 12:21:17.865108 3, 0xFFFF, sum = 0
8616 12:21:17.868447 4, 0xFFFF, sum = 0
8617 12:21:17.868518 5, 0xFFFF, sum = 0
8618 12:21:17.871677 6, 0xFFFF, sum = 0
8619 12:21:17.871780 7, 0xFFFF, sum = 0
8620 12:21:17.875024 8, 0xFFFF, sum = 0
8621 12:21:17.875132 9, 0xFFFF, sum = 0
8622 12:21:17.878349 10, 0xFFFF, sum = 0
8623 12:21:17.878447 11, 0xFFFF, sum = 0
8624 12:21:17.881743 12, 0xFFFF, sum = 0
8625 12:21:17.881839 13, 0xFFFF, sum = 0
8626 12:21:17.884799 14, 0x0, sum = 1
8627 12:21:17.884904 15, 0x0, sum = 2
8628 12:21:17.888103 16, 0x0, sum = 3
8629 12:21:17.888201 17, 0x0, sum = 4
8630 12:21:17.891134 best_step = 15
8631 12:21:17.891210
8632 12:21:17.891272 ==
8633 12:21:17.894782 Dram Type= 6, Freq= 0, CH_1, rank 0
8634 12:21:17.898188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8635 12:21:17.898285 ==
8636 12:21:17.901300 RX Vref Scan: 1
8637 12:21:17.901372
8638 12:21:17.901433 Set Vref Range= 24 -> 127
8639 12:21:17.901490
8640 12:21:17.904970 RX Vref 24 -> 127, step: 1
8641 12:21:17.905036
8642 12:21:17.908016 RX Delay 19 -> 252, step: 4
8643 12:21:17.908082
8644 12:21:17.911449 Set Vref, RX VrefLevel [Byte0]: 24
8645 12:21:17.914648 [Byte1]: 24
8646 12:21:17.914715
8647 12:21:17.917428 Set Vref, RX VrefLevel [Byte0]: 25
8648 12:21:17.921078 [Byte1]: 25
8649 12:21:17.924693
8650 12:21:17.924793 Set Vref, RX VrefLevel [Byte0]: 26
8651 12:21:17.927650 [Byte1]: 26
8652 12:21:17.931919
8653 12:21:17.932028 Set Vref, RX VrefLevel [Byte0]: 27
8654 12:21:17.935245 [Byte1]: 27
8655 12:21:17.939532
8656 12:21:17.939604 Set Vref, RX VrefLevel [Byte0]: 28
8657 12:21:17.942933 [Byte1]: 28
8658 12:21:17.947056
8659 12:21:17.947130 Set Vref, RX VrefLevel [Byte0]: 29
8660 12:21:17.950987 [Byte1]: 29
8661 12:21:17.955139
8662 12:21:17.955209 Set Vref, RX VrefLevel [Byte0]: 30
8663 12:21:17.957922 [Byte1]: 30
8664 12:21:17.962718
8665 12:21:17.962791 Set Vref, RX VrefLevel [Byte0]: 31
8666 12:21:17.965627 [Byte1]: 31
8667 12:21:17.969901
8668 12:21:17.969971 Set Vref, RX VrefLevel [Byte0]: 32
8669 12:21:17.973223 [Byte1]: 32
8670 12:21:17.977808
8671 12:21:17.977882 Set Vref, RX VrefLevel [Byte0]: 33
8672 12:21:17.980772 [Byte1]: 33
8673 12:21:17.985295
8674 12:21:17.985363 Set Vref, RX VrefLevel [Byte0]: 34
8675 12:21:17.988305 [Byte1]: 34
8676 12:21:17.992656
8677 12:21:17.992729 Set Vref, RX VrefLevel [Byte0]: 35
8678 12:21:17.996410 [Byte1]: 35
8679 12:21:18.000729
8680 12:21:18.000800 Set Vref, RX VrefLevel [Byte0]: 36
8681 12:21:18.003893 [Byte1]: 36
8682 12:21:18.007924
8683 12:21:18.007992 Set Vref, RX VrefLevel [Byte0]: 37
8684 12:21:18.011363 [Byte1]: 37
8685 12:21:18.015238
8686 12:21:18.015306 Set Vref, RX VrefLevel [Byte0]: 38
8687 12:21:18.018788 [Byte1]: 38
8688 12:21:18.022930
8689 12:21:18.023004 Set Vref, RX VrefLevel [Byte0]: 39
8690 12:21:18.026108 [Byte1]: 39
8691 12:21:18.030387
8692 12:21:18.030457 Set Vref, RX VrefLevel [Byte0]: 40
8693 12:21:18.033991 [Byte1]: 40
8694 12:21:18.038159
8695 12:21:18.038234 Set Vref, RX VrefLevel [Byte0]: 41
8696 12:21:18.041590 [Byte1]: 41
8697 12:21:18.045769
8698 12:21:18.045846 Set Vref, RX VrefLevel [Byte0]: 42
8699 12:21:18.049035 [Byte1]: 42
8700 12:21:18.053100
8701 12:21:18.053174 Set Vref, RX VrefLevel [Byte0]: 43
8702 12:21:18.056396 [Byte1]: 43
8703 12:21:18.060778
8704 12:21:18.060872 Set Vref, RX VrefLevel [Byte0]: 44
8705 12:21:18.064045 [Byte1]: 44
8706 12:21:18.068309
8707 12:21:18.068382 Set Vref, RX VrefLevel [Byte0]: 45
8708 12:21:18.071481 [Byte1]: 45
8709 12:21:18.076046
8710 12:21:18.076121 Set Vref, RX VrefLevel [Byte0]: 46
8711 12:21:18.079219 [Byte1]: 46
8712 12:21:18.083414
8713 12:21:18.083486 Set Vref, RX VrefLevel [Byte0]: 47
8714 12:21:18.086806 [Byte1]: 47
8715 12:21:18.091408
8716 12:21:18.091484 Set Vref, RX VrefLevel [Byte0]: 48
8717 12:21:18.094638 [Byte1]: 48
8718 12:21:18.098641
8719 12:21:18.098713 Set Vref, RX VrefLevel [Byte0]: 49
8720 12:21:18.101898 [Byte1]: 49
8721 12:21:18.106325
8722 12:21:18.106421 Set Vref, RX VrefLevel [Byte0]: 50
8723 12:21:18.109435 [Byte1]: 50
8724 12:21:18.113613
8725 12:21:18.113707 Set Vref, RX VrefLevel [Byte0]: 51
8726 12:21:18.116894 [Byte1]: 51
8727 12:21:18.121754
8728 12:21:18.121823 Set Vref, RX VrefLevel [Byte0]: 52
8729 12:21:18.124744 [Byte1]: 52
8730 12:21:18.128778
8731 12:21:18.128880 Set Vref, RX VrefLevel [Byte0]: 53
8732 12:21:18.132218 [Byte1]: 53
8733 12:21:18.136673
8734 12:21:18.136743 Set Vref, RX VrefLevel [Byte0]: 54
8735 12:21:18.139958 [Byte1]: 54
8736 12:21:18.144434
8737 12:21:18.147234 Set Vref, RX VrefLevel [Byte0]: 55
8738 12:21:18.147304 [Byte1]: 55
8739 12:21:18.151976
8740 12:21:18.152068 Set Vref, RX VrefLevel [Byte0]: 56
8741 12:21:18.154911 [Byte1]: 56
8742 12:21:18.159803
8743 12:21:18.159908 Set Vref, RX VrefLevel [Byte0]: 57
8744 12:21:18.162764 [Byte1]: 57
8745 12:21:18.166647
8746 12:21:18.166744 Set Vref, RX VrefLevel [Byte0]: 58
8747 12:21:18.170063 [Byte1]: 58
8748 12:21:18.174246
8749 12:21:18.174342 Set Vref, RX VrefLevel [Byte0]: 59
8750 12:21:18.177602 [Byte1]: 59
8751 12:21:18.182085
8752 12:21:18.182187 Set Vref, RX VrefLevel [Byte0]: 60
8753 12:21:18.185120 [Byte1]: 60
8754 12:21:18.189633
8755 12:21:18.189728 Set Vref, RX VrefLevel [Byte0]: 61
8756 12:21:18.193059 [Byte1]: 61
8757 12:21:18.197224
8758 12:21:18.197314 Set Vref, RX VrefLevel [Byte0]: 62
8759 12:21:18.200296 [Byte1]: 62
8760 12:21:18.204743
8761 12:21:18.204845 Set Vref, RX VrefLevel [Byte0]: 63
8762 12:21:18.207751 [Byte1]: 63
8763 12:21:18.212144
8764 12:21:18.212246 Set Vref, RX VrefLevel [Byte0]: 64
8765 12:21:18.215647 [Byte1]: 64
8766 12:21:18.219733
8767 12:21:18.219803 Set Vref, RX VrefLevel [Byte0]: 65
8768 12:21:18.223086 [Byte1]: 65
8769 12:21:18.227534
8770 12:21:18.227609 Set Vref, RX VrefLevel [Byte0]: 66
8771 12:21:18.230722 [Byte1]: 66
8772 12:21:18.235239
8773 12:21:18.235344 Set Vref, RX VrefLevel [Byte0]: 67
8774 12:21:18.238414 [Byte1]: 67
8775 12:21:18.242677
8776 12:21:18.246005 Set Vref, RX VrefLevel [Byte0]: 68
8777 12:21:18.249205 [Byte1]: 68
8778 12:21:18.249302
8779 12:21:18.252239 Set Vref, RX VrefLevel [Byte0]: 69
8780 12:21:18.255405 [Byte1]: 69
8781 12:21:18.255480
8782 12:21:18.259238 Set Vref, RX VrefLevel [Byte0]: 70
8783 12:21:18.262067 [Byte1]: 70
8784 12:21:18.265345
8785 12:21:18.265414 Set Vref, RX VrefLevel [Byte0]: 71
8786 12:21:18.268517 [Byte1]: 71
8787 12:21:18.272895
8788 12:21:18.272990 Set Vref, RX VrefLevel [Byte0]: 72
8789 12:21:18.276125 [Byte1]: 72
8790 12:21:18.280631
8791 12:21:18.280727 Set Vref, RX VrefLevel [Byte0]: 73
8792 12:21:18.283898 [Byte1]: 73
8793 12:21:18.287893
8794 12:21:18.287985 Final RX Vref Byte 0 = 54 to rank0
8795 12:21:18.291458 Final RX Vref Byte 1 = 56 to rank0
8796 12:21:18.294510 Final RX Vref Byte 0 = 54 to rank1
8797 12:21:18.298237 Final RX Vref Byte 1 = 56 to rank1==
8798 12:21:18.301520 Dram Type= 6, Freq= 0, CH_1, rank 0
8799 12:21:18.307898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8800 12:21:18.307976 ==
8801 12:21:18.308040 DQS Delay:
8802 12:21:18.308099 DQS0 = 0, DQS1 = 0
8803 12:21:18.311850 DQM Delay:
8804 12:21:18.311917 DQM0 = 134, DQM1 = 129
8805 12:21:18.314546 DQ Delay:
8806 12:21:18.317563 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8807 12:21:18.321101 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8808 12:21:18.324587 DQ8 =116, DQ9 =116, DQ10 =132, DQ11 =118
8809 12:21:18.327757 DQ12 =136, DQ13 =138, DQ14 =138, DQ15 =138
8810 12:21:18.327831
8811 12:21:18.327893
8812 12:21:18.327973
8813 12:21:18.330939 [DramC_TX_OE_Calibration] TA2
8814 12:21:18.334172 Original DQ_B0 (3 6) =30, OEN = 27
8815 12:21:18.337616 Original DQ_B1 (3 6) =30, OEN = 27
8816 12:21:18.340672 24, 0x0, End_B0=24 End_B1=24
8817 12:21:18.340781 25, 0x0, End_B0=25 End_B1=25
8818 12:21:18.344367 26, 0x0, End_B0=26 End_B1=26
8819 12:21:18.347252 27, 0x0, End_B0=27 End_B1=27
8820 12:21:18.350545 28, 0x0, End_B0=28 End_B1=28
8821 12:21:18.354429 29, 0x0, End_B0=29 End_B1=29
8822 12:21:18.354528 30, 0x0, End_B0=30 End_B1=30
8823 12:21:18.357404 31, 0x4141, End_B0=30 End_B1=30
8824 12:21:18.360941 Byte0 end_step=30 best_step=27
8825 12:21:18.363871 Byte1 end_step=30 best_step=27
8826 12:21:18.367107 Byte0 TX OE(2T, 0.5T) = (3, 3)
8827 12:21:18.370477 Byte1 TX OE(2T, 0.5T) = (3, 3)
8828 12:21:18.370573
8829 12:21:18.370703
8830 12:21:18.377099 [DQSOSCAuto] RK0, (LSB)MR18= 0x190f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8831 12:21:18.380460 CH1 RK0: MR19=303, MR18=190F
8832 12:21:18.386851 CH1_RK0: MR19=0x303, MR18=0x190F, DQSOSC=397, MR23=63, INC=23, DEC=15
8833 12:21:18.386920
8834 12:21:18.390108 ----->DramcWriteLeveling(PI) begin...
8835 12:21:18.390175 ==
8836 12:21:18.393262 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 12:21:18.396496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 12:21:18.396593 ==
8839 12:21:18.400151 Write leveling (Byte 0): 23 => 23
8840 12:21:18.403190 Write leveling (Byte 1): 26 => 26
8841 12:21:18.406844 DramcWriteLeveling(PI) end<-----
8842 12:21:18.406916
8843 12:21:18.406983 ==
8844 12:21:18.409770 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 12:21:18.416448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 12:21:18.416522 ==
8847 12:21:18.416585 [Gating] SW mode calibration
8848 12:21:18.426616 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8849 12:21:18.429497 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8850 12:21:18.432860 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8851 12:21:18.439658 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8852 12:21:18.442677 1 4 8 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
8853 12:21:18.446511 1 4 12 | B1->B0 | 3434 2423 | 1 1 | (1 1) (0 0)
8854 12:21:18.452682 1 4 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8855 12:21:18.456102 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8856 12:21:18.460137 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8857 12:21:18.466477 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8858 12:21:18.469608 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8859 12:21:18.472526 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8860 12:21:18.479621 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8861 12:21:18.482466 1 5 12 | B1->B0 | 2323 3434 | 0 1 | (1 0) (1 0)
8862 12:21:18.485654 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8863 12:21:18.492578 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8864 12:21:18.495670 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8865 12:21:18.499350 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8866 12:21:18.506077 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8867 12:21:18.509003 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8868 12:21:18.511966 1 6 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
8869 12:21:18.518821 1 6 12 | B1->B0 | 4646 2424 | 0 1 | (0 0) (0 0)
8870 12:21:18.522143 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8871 12:21:18.525610 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8872 12:21:18.532043 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8873 12:21:18.535344 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8874 12:21:18.539175 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8875 12:21:18.545282 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8876 12:21:18.548599 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8877 12:21:18.551819 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8878 12:21:18.558745 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8879 12:21:18.562276 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 12:21:18.565101 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 12:21:18.571780 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 12:21:18.575010 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 12:21:18.578870 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 12:21:18.585001 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 12:21:18.588394 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 12:21:18.591845 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8887 12:21:18.598730 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8888 12:21:18.601946 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8889 12:21:18.605059 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8890 12:21:18.611301 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8891 12:21:18.614689 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8892 12:21:18.617961 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8893 12:21:18.625017 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8894 12:21:18.628267 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8895 12:21:18.631522 Total UI for P1: 0, mck2ui 16
8896 12:21:18.634789 best dqsien dly found for B0: ( 1, 9, 12)
8897 12:21:18.638101 Total UI for P1: 0, mck2ui 16
8898 12:21:18.641017 best dqsien dly found for B1: ( 1, 9, 12)
8899 12:21:18.644542 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8900 12:21:18.647958 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8901 12:21:18.648055
8902 12:21:18.650954 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8903 12:21:18.654936 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8904 12:21:18.658269 [Gating] SW calibration Done
8905 12:21:18.658363 ==
8906 12:21:18.661114 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 12:21:18.667611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 12:21:18.667686 ==
8909 12:21:18.667749 RX Vref Scan: 0
8910 12:21:18.667807
8911 12:21:18.670773 RX Vref 0 -> 0, step: 1
8912 12:21:18.670840
8913 12:21:18.674532 RX Delay 0 -> 252, step: 8
8914 12:21:18.677624 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8915 12:21:18.680784 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8916 12:21:18.684483 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8917 12:21:18.687503 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8918 12:21:18.694293 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8919 12:21:18.697582 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8920 12:21:18.700809 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8921 12:21:18.703835 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8922 12:21:18.707228 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8923 12:21:18.713868 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8924 12:21:18.717073 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8925 12:21:18.720377 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8926 12:21:18.723833 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8927 12:21:18.730407 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8928 12:21:18.733607 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8929 12:21:18.736872 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8930 12:21:18.736969 ==
8931 12:21:18.740255 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 12:21:18.743099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 12:21:18.743167 ==
8934 12:21:18.746476 DQS Delay:
8935 12:21:18.746543 DQS0 = 0, DQS1 = 0
8936 12:21:18.750080 DQM Delay:
8937 12:21:18.750176 DQM0 = 137, DQM1 = 129
8938 12:21:18.750267 DQ Delay:
8939 12:21:18.756306 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8940 12:21:18.760197 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8941 12:21:18.763011 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8942 12:21:18.766463 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8943 12:21:18.766559
8944 12:21:18.766654
8945 12:21:18.766739 ==
8946 12:21:18.769577 Dram Type= 6, Freq= 0, CH_1, rank 1
8947 12:21:18.773207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8948 12:21:18.773300 ==
8949 12:21:18.773387
8950 12:21:18.773474
8951 12:21:18.776177 TX Vref Scan disable
8952 12:21:18.779698 == TX Byte 0 ==
8953 12:21:18.782947 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8954 12:21:18.786048 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8955 12:21:18.789611 == TX Byte 1 ==
8956 12:21:18.792605 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8957 12:21:18.795999 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8958 12:21:18.796076 ==
8959 12:21:18.799703 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 12:21:18.805732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 12:21:18.805829 ==
8962 12:21:18.817678
8963 12:21:18.820627 TX Vref early break, caculate TX vref
8964 12:21:18.823908 TX Vref=16, minBit 0, minWin=22, winSum=378
8965 12:21:18.828062 TX Vref=18, minBit 0, minWin=22, winSum=386
8966 12:21:18.830806 TX Vref=20, minBit 6, minWin=23, winSum=399
8967 12:21:18.834386 TX Vref=22, minBit 1, minWin=23, winSum=403
8968 12:21:18.837327 TX Vref=24, minBit 0, minWin=24, winSum=413
8969 12:21:18.843612 TX Vref=26, minBit 5, minWin=24, winSum=418
8970 12:21:18.847063 TX Vref=28, minBit 0, minWin=24, winSum=423
8971 12:21:18.850644 TX Vref=30, minBit 0, minWin=24, winSum=413
8972 12:21:18.853644 TX Vref=32, minBit 0, minWin=22, winSum=403
8973 12:21:18.857139 TX Vref=34, minBit 0, minWin=22, winSum=395
8974 12:21:18.863861 [TxChooseVref] Worse bit 0, Min win 24, Win sum 423, Final Vref 28
8975 12:21:18.863934
8976 12:21:18.867036 Final TX Range 0 Vref 28
8977 12:21:18.867105
8978 12:21:18.867163 ==
8979 12:21:18.870247 Dram Type= 6, Freq= 0, CH_1, rank 1
8980 12:21:18.873300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8981 12:21:18.873399 ==
8982 12:21:18.873487
8983 12:21:18.873572
8984 12:21:18.876795 TX Vref Scan disable
8985 12:21:18.883505 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8986 12:21:18.883575 == TX Byte 0 ==
8987 12:21:18.886711 u2DelayCellOfst[0]=22 cells (6 PI)
8988 12:21:18.889981 u2DelayCellOfst[1]=14 cells (4 PI)
8989 12:21:18.893067 u2DelayCellOfst[2]=0 cells (0 PI)
8990 12:21:18.896491 u2DelayCellOfst[3]=7 cells (2 PI)
8991 12:21:18.900196 u2DelayCellOfst[4]=11 cells (3 PI)
8992 12:21:18.903082 u2DelayCellOfst[5]=26 cells (7 PI)
8993 12:21:18.907090 u2DelayCellOfst[6]=22 cells (6 PI)
8994 12:21:18.909527 u2DelayCellOfst[7]=7 cells (2 PI)
8995 12:21:18.913362 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8996 12:21:18.916392 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8997 12:21:18.919502 == TX Byte 1 ==
8998 12:21:18.922876 u2DelayCellOfst[8]=0 cells (0 PI)
8999 12:21:18.926237 u2DelayCellOfst[9]=3 cells (1 PI)
9000 12:21:18.929865 u2DelayCellOfst[10]=11 cells (3 PI)
9001 12:21:18.929967 u2DelayCellOfst[11]=7 cells (2 PI)
9002 12:21:18.933191 u2DelayCellOfst[12]=14 cells (4 PI)
9003 12:21:18.935762 u2DelayCellOfst[13]=18 cells (5 PI)
9004 12:21:18.939127 u2DelayCellOfst[14]=18 cells (5 PI)
9005 12:21:18.942537 u2DelayCellOfst[15]=18 cells (5 PI)
9006 12:21:18.949151 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9007 12:21:18.952356 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
9008 12:21:18.952432 DramC Write-DBI on
9009 12:21:18.955490 ==
9010 12:21:18.959061 Dram Type= 6, Freq= 0, CH_1, rank 1
9011 12:21:18.962213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9012 12:21:18.962309 ==
9013 12:21:18.962397
9014 12:21:18.962466
9015 12:21:18.965904 TX Vref Scan disable
9016 12:21:18.965974 == TX Byte 0 ==
9017 12:21:18.971931 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9018 12:21:18.972008 == TX Byte 1 ==
9019 12:21:18.975238 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9020 12:21:18.978456 DramC Write-DBI off
9021 12:21:18.978552
9022 12:21:18.978672 [DATLAT]
9023 12:21:18.981732 Freq=1600, CH1 RK1
9024 12:21:18.981802
9025 12:21:18.981869 DATLAT Default: 0xf
9026 12:21:18.985362 0, 0xFFFF, sum = 0
9027 12:21:18.985432 1, 0xFFFF, sum = 0
9028 12:21:18.988370 2, 0xFFFF, sum = 0
9029 12:21:18.988442 3, 0xFFFF, sum = 0
9030 12:21:18.991961 4, 0xFFFF, sum = 0
9031 12:21:18.995153 5, 0xFFFF, sum = 0
9032 12:21:18.995258 6, 0xFFFF, sum = 0
9033 12:21:18.998776 7, 0xFFFF, sum = 0
9034 12:21:18.998854 8, 0xFFFF, sum = 0
9035 12:21:19.001964 9, 0xFFFF, sum = 0
9036 12:21:19.002062 10, 0xFFFF, sum = 0
9037 12:21:19.004781 11, 0xFFFF, sum = 0
9038 12:21:19.004881 12, 0xFFFF, sum = 0
9039 12:21:19.008793 13, 0xFFFF, sum = 0
9040 12:21:19.008891 14, 0x0, sum = 1
9041 12:21:19.011831 15, 0x0, sum = 2
9042 12:21:19.011903 16, 0x0, sum = 3
9043 12:21:19.015119 17, 0x0, sum = 4
9044 12:21:19.015193 best_step = 15
9045 12:21:19.015255
9046 12:21:19.015312 ==
9047 12:21:19.018038 Dram Type= 6, Freq= 0, CH_1, rank 1
9048 12:21:19.024784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9049 12:21:19.024857 ==
9050 12:21:19.024918 RX Vref Scan: 0
9051 12:21:19.024980
9052 12:21:19.028644 RX Vref 0 -> 0, step: 1
9053 12:21:19.028717
9054 12:21:19.031485 RX Delay 11 -> 252, step: 4
9055 12:21:19.034626 iDelay=203, Bit 0, Center 136 (83 ~ 190) 108
9056 12:21:19.038269 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9057 12:21:19.041065 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9058 12:21:19.047618 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9059 12:21:19.051057 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9060 12:21:19.054405 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9061 12:21:19.057647 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9062 12:21:19.061135 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9063 12:21:19.068069 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9064 12:21:19.071642 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9065 12:21:19.074603 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9066 12:21:19.077301 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9067 12:21:19.084239 iDelay=203, Bit 12, Center 138 (83 ~ 194) 112
9068 12:21:19.087549 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9069 12:21:19.090699 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9070 12:21:19.093924 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9071 12:21:19.094025 ==
9072 12:21:19.097383 Dram Type= 6, Freq= 0, CH_1, rank 1
9073 12:21:19.103899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9074 12:21:19.103977 ==
9075 12:21:19.104041 DQS Delay:
9076 12:21:19.107196 DQS0 = 0, DQS1 = 0
9077 12:21:19.107268 DQM Delay:
9078 12:21:19.107328 DQM0 = 133, DQM1 = 127
9079 12:21:19.110805 DQ Delay:
9080 12:21:19.113487 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =130
9081 12:21:19.117514 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =130
9082 12:21:19.120446 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =118
9083 12:21:19.123616 DQ12 =138, DQ13 =134, DQ14 =134, DQ15 =138
9084 12:21:19.123684
9085 12:21:19.123743
9086 12:21:19.123804
9087 12:21:19.127128 [DramC_TX_OE_Calibration] TA2
9088 12:21:19.130456 Original DQ_B0 (3 6) =30, OEN = 27
9089 12:21:19.133578 Original DQ_B1 (3 6) =30, OEN = 27
9090 12:21:19.137067 24, 0x0, End_B0=24 End_B1=24
9091 12:21:19.137139 25, 0x0, End_B0=25 End_B1=25
9092 12:21:19.139989 26, 0x0, End_B0=26 End_B1=26
9093 12:21:19.143384 27, 0x0, End_B0=27 End_B1=27
9094 12:21:19.146798 28, 0x0, End_B0=28 End_B1=28
9095 12:21:19.149922 29, 0x0, End_B0=29 End_B1=29
9096 12:21:19.150027 30, 0x0, End_B0=30 End_B1=30
9097 12:21:19.153206 31, 0x4545, End_B0=30 End_B1=30
9098 12:21:19.156995 Byte0 end_step=30 best_step=27
9099 12:21:19.160079 Byte1 end_step=30 best_step=27
9100 12:21:19.163856 Byte0 TX OE(2T, 0.5T) = (3, 3)
9101 12:21:19.166582 Byte1 TX OE(2T, 0.5T) = (3, 3)
9102 12:21:19.166698
9103 12:21:19.166794
9104 12:21:19.173603 [DQSOSCAuto] RK1, (LSB)MR18= 0xb07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9105 12:21:19.176557 CH1 RK1: MR19=303, MR18=B07
9106 12:21:19.183674 CH1_RK1: MR19=0x303, MR18=0xB07, DQSOSC=404, MR23=63, INC=22, DEC=15
9107 12:21:19.186489 [RxdqsGatingPostProcess] freq 1600
9108 12:21:19.190095 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9109 12:21:19.194096 best DQS0 dly(2T, 0.5T) = (1, 1)
9110 12:21:19.196681 best DQS1 dly(2T, 0.5T) = (1, 1)
9111 12:21:19.199927 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9112 12:21:19.203501 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9113 12:21:19.206704 best DQS0 dly(2T, 0.5T) = (1, 1)
9114 12:21:19.210077 best DQS1 dly(2T, 0.5T) = (1, 1)
9115 12:21:19.213304 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9116 12:21:19.216333 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9117 12:21:19.219597 Pre-setting of DQS Precalculation
9118 12:21:19.223152 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9119 12:21:19.229974 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9120 12:21:19.239585 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9121 12:21:19.239658
9122 12:21:19.239725
9123 12:21:19.239784 [Calibration Summary] 3200 Mbps
9124 12:21:19.243177 CH 0, Rank 0
9125 12:21:19.246179 SW Impedance : PASS
9126 12:21:19.246248 DUTY Scan : NO K
9127 12:21:19.249254 ZQ Calibration : PASS
9128 12:21:19.249351 Jitter Meter : NO K
9129 12:21:19.252744 CBT Training : PASS
9130 12:21:19.255904 Write leveling : PASS
9131 12:21:19.256002 RX DQS gating : PASS
9132 12:21:19.259600 RX DQ/DQS(RDDQC) : PASS
9133 12:21:19.262761 TX DQ/DQS : PASS
9134 12:21:19.262875 RX DATLAT : PASS
9135 12:21:19.266006 RX DQ/DQS(Engine): PASS
9136 12:21:19.269323 TX OE : PASS
9137 12:21:19.269420 All Pass.
9138 12:21:19.269512
9139 12:21:19.269584 CH 0, Rank 1
9140 12:21:19.273053 SW Impedance : PASS
9141 12:21:19.275844 DUTY Scan : NO K
9142 12:21:19.275930 ZQ Calibration : PASS
9143 12:21:19.279176 Jitter Meter : NO K
9144 12:21:19.282889 CBT Training : PASS
9145 12:21:19.282988 Write leveling : PASS
9146 12:21:19.285761 RX DQS gating : PASS
9147 12:21:19.289123 RX DQ/DQS(RDDQC) : PASS
9148 12:21:19.289221 TX DQ/DQS : PASS
9149 12:21:19.292561 RX DATLAT : PASS
9150 12:21:19.295899 RX DQ/DQS(Engine): PASS
9151 12:21:19.295995 TX OE : PASS
9152 12:21:19.299069 All Pass.
9153 12:21:19.299167
9154 12:21:19.299230 CH 1, Rank 0
9155 12:21:19.302514 SW Impedance : PASS
9156 12:21:19.302613 DUTY Scan : NO K
9157 12:21:19.305708 ZQ Calibration : PASS
9158 12:21:19.308789 Jitter Meter : NO K
9159 12:21:19.308883 CBT Training : PASS
9160 12:21:19.312322 Write leveling : PASS
9161 12:21:19.315670 RX DQS gating : PASS
9162 12:21:19.315743 RX DQ/DQS(RDDQC) : PASS
9163 12:21:19.318674 TX DQ/DQS : PASS
9164 12:21:19.318742 RX DATLAT : PASS
9165 12:21:19.321736 RX DQ/DQS(Engine): PASS
9166 12:21:19.325495 TX OE : PASS
9167 12:21:19.325563 All Pass.
9168 12:21:19.325629
9169 12:21:19.325688 CH 1, Rank 1
9170 12:21:19.328390 SW Impedance : PASS
9171 12:21:19.332098 DUTY Scan : NO K
9172 12:21:19.332164 ZQ Calibration : PASS
9173 12:21:19.335203 Jitter Meter : NO K
9174 12:21:19.338714 CBT Training : PASS
9175 12:21:19.338809 Write leveling : PASS
9176 12:21:19.341676 RX DQS gating : PASS
9177 12:21:19.344870 RX DQ/DQS(RDDQC) : PASS
9178 12:21:19.344965 TX DQ/DQS : PASS
9179 12:21:19.348269 RX DATLAT : PASS
9180 12:21:19.351608 RX DQ/DQS(Engine): PASS
9181 12:21:19.351700 TX OE : PASS
9182 12:21:19.354638 All Pass.
9183 12:21:19.354727
9184 12:21:19.354787 DramC Write-DBI on
9185 12:21:19.358173 PER_BANK_REFRESH: Hybrid Mode
9186 12:21:19.361780 TX_TRACKING: ON
9187 12:21:19.368124 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9188 12:21:19.378160 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9189 12:21:19.385092 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9190 12:21:19.387669 [FAST_K] Save calibration result to emmc
9191 12:21:19.391195 sync common calibartion params.
9192 12:21:19.391294 sync cbt_mode0:1, 1:1
9193 12:21:19.395108 dram_init: ddr_geometry: 2
9194 12:21:19.397937 dram_init: ddr_geometry: 2
9195 12:21:19.401231 dram_init: ddr_geometry: 2
9196 12:21:19.401315 0:dram_rank_size:100000000
9197 12:21:19.404054 1:dram_rank_size:100000000
9198 12:21:19.410951 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9199 12:21:19.411049 DFS_SHUFFLE_HW_MODE: ON
9200 12:21:19.417636 dramc_set_vcore_voltage set vcore to 725000
9201 12:21:19.417714 Read voltage for 1600, 0
9202 12:21:19.420919 Vio18 = 0
9203 12:21:19.420987 Vcore = 725000
9204 12:21:19.421049 Vdram = 0
9205 12:21:19.423963 Vddq = 0
9206 12:21:19.424034 Vmddr = 0
9207 12:21:19.427163 switch to 3200 Mbps bootup
9208 12:21:19.427235 [DramcRunTimeConfig]
9209 12:21:19.427295 PHYPLL
9210 12:21:19.430726 DPM_CONTROL_AFTERK: ON
9211 12:21:19.433803 PER_BANK_REFRESH: ON
9212 12:21:19.433872 REFRESH_OVERHEAD_REDUCTION: ON
9213 12:21:19.437507 CMD_PICG_NEW_MODE: OFF
9214 12:21:19.440247 XRTWTW_NEW_MODE: ON
9215 12:21:19.440333 XRTRTR_NEW_MODE: ON
9216 12:21:19.444012 TX_TRACKING: ON
9217 12:21:19.444083 RDSEL_TRACKING: OFF
9218 12:21:19.446997 DQS Precalculation for DVFS: ON
9219 12:21:19.447067 RX_TRACKING: OFF
9220 12:21:19.450359 HW_GATING DBG: ON
9221 12:21:19.450434 ZQCS_ENABLE_LP4: ON
9222 12:21:19.453633 RX_PICG_NEW_MODE: ON
9223 12:21:19.456809 TX_PICG_NEW_MODE: ON
9224 12:21:19.456905 ENABLE_RX_DCM_DPHY: ON
9225 12:21:19.460015 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9226 12:21:19.463537 DUMMY_READ_FOR_TRACKING: OFF
9227 12:21:19.467048 !!! SPM_CONTROL_AFTERK: OFF
9228 12:21:19.470027 !!! SPM could not control APHY
9229 12:21:19.470131 IMPEDANCE_TRACKING: ON
9230 12:21:19.473533 TEMP_SENSOR: ON
9231 12:21:19.473608 HW_SAVE_FOR_SR: OFF
9232 12:21:19.476784 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9233 12:21:19.480215 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9234 12:21:19.483236 Read ODT Tracking: ON
9235 12:21:19.483311 Refresh Rate DeBounce: ON
9236 12:21:19.486707 DFS_NO_QUEUE_FLUSH: ON
9237 12:21:19.490092 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9238 12:21:19.493333 ENABLE_DFS_RUNTIME_MRW: OFF
9239 12:21:19.493417 DDR_RESERVE_NEW_MODE: ON
9240 12:21:19.496832 MR_CBT_SWITCH_FREQ: ON
9241 12:21:19.499793 =========================
9242 12:21:19.518602 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9243 12:21:19.521372 dram_init: ddr_geometry: 2
9244 12:21:19.539520 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9245 12:21:19.542985 dram_init: dram init end (result: 0)
9246 12:21:19.550031 DRAM-K: Full calibration passed in 24605 msecs
9247 12:21:19.552896 MRC: failed to locate region type 0.
9248 12:21:19.552991 DRAM rank0 size:0x100000000,
9249 12:21:19.556632 DRAM rank1 size=0x100000000
9250 12:21:19.566470 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9251 12:21:19.573019 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9252 12:21:19.579582 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9253 12:21:19.586412 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9254 12:21:19.589934 DRAM rank0 size:0x100000000,
9255 12:21:19.593692 DRAM rank1 size=0x100000000
9256 12:21:19.593795 CBMEM:
9257 12:21:19.596240 IMD: root @ 0xfffff000 254 entries.
9258 12:21:19.599916 IMD: root @ 0xffffec00 62 entries.
9259 12:21:19.602744 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9260 12:21:19.609179 WARNING: RO_VPD is uninitialized or empty.
9261 12:21:19.612414 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9262 12:21:19.619551 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9263 12:21:19.632326 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9264 12:21:19.643731 BS: romstage times (exec / console): total (unknown) / 24101 ms
9265 12:21:19.643809
9266 12:21:19.643872
9267 12:21:19.653906 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9268 12:21:19.657267 ARM64: Exception handlers installed.
9269 12:21:19.660485 ARM64: Testing exception
9270 12:21:19.663814 ARM64: Done test exception
9271 12:21:19.663884 Enumerating buses...
9272 12:21:19.667814 Show all devs... Before device enumeration.
9273 12:21:19.670815 Root Device: enabled 1
9274 12:21:19.673481 CPU_CLUSTER: 0: enabled 1
9275 12:21:19.673573 CPU: 00: enabled 1
9276 12:21:19.677182 Compare with tree...
9277 12:21:19.677279 Root Device: enabled 1
9278 12:21:19.680229 CPU_CLUSTER: 0: enabled 1
9279 12:21:19.683461 CPU: 00: enabled 1
9280 12:21:19.683557 Root Device scanning...
9281 12:21:19.686748 scan_static_bus for Root Device
9282 12:21:19.690247 CPU_CLUSTER: 0 enabled
9283 12:21:19.693213 scan_static_bus for Root Device done
9284 12:21:19.696519 scan_bus: bus Root Device finished in 8 msecs
9285 12:21:19.696622 done
9286 12:21:19.703655 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9287 12:21:19.706520 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9288 12:21:19.713482 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9289 12:21:19.716384 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9290 12:21:19.719649 Allocating resources...
9291 12:21:19.722880 Reading resources...
9292 12:21:19.726454 Root Device read_resources bus 0 link: 0
9293 12:21:19.729651 DRAM rank0 size:0x100000000,
9294 12:21:19.729757 DRAM rank1 size=0x100000000
9295 12:21:19.736204 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9296 12:21:19.736276 CPU: 00 missing read_resources
9297 12:21:19.742847 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9298 12:21:19.745962 Root Device read_resources bus 0 link: 0 done
9299 12:21:19.749385 Done reading resources.
9300 12:21:19.752477 Show resources in subtree (Root Device)...After reading.
9301 12:21:19.755894 Root Device child on link 0 CPU_CLUSTER: 0
9302 12:21:19.759257 CPU_CLUSTER: 0 child on link 0 CPU: 00
9303 12:21:19.769207 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9304 12:21:19.769316 CPU: 00
9305 12:21:19.775677 Root Device assign_resources, bus 0 link: 0
9306 12:21:19.779201 CPU_CLUSTER: 0 missing set_resources
9307 12:21:19.782436 Root Device assign_resources, bus 0 link: 0 done
9308 12:21:19.782542 Done setting resources.
9309 12:21:19.788747 Show resources in subtree (Root Device)...After assigning values.
9310 12:21:19.792259 Root Device child on link 0 CPU_CLUSTER: 0
9311 12:21:19.795619 CPU_CLUSTER: 0 child on link 0 CPU: 00
9312 12:21:19.805757 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9313 12:21:19.805841 CPU: 00
9314 12:21:19.808887 Done allocating resources.
9315 12:21:19.815434 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9316 12:21:19.815510 Enabling resources...
9317 12:21:19.818516 done.
9318 12:21:19.822122 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9319 12:21:19.825499 Initializing devices...
9320 12:21:19.825574 Root Device init
9321 12:21:19.828889 init hardware done!
9322 12:21:19.828961 0x00000018: ctrlr->caps
9323 12:21:19.832264 52.000 MHz: ctrlr->f_max
9324 12:21:19.835374 0.400 MHz: ctrlr->f_min
9325 12:21:19.835452 0x40ff8080: ctrlr->voltages
9326 12:21:19.838547 sclk: 390625
9327 12:21:19.838641 Bus Width = 1
9328 12:21:19.841965 sclk: 390625
9329 12:21:19.842037 Bus Width = 1
9330 12:21:19.845170 Early init status = 3
9331 12:21:19.848511 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9332 12:21:19.851918 in-header: 03 fc 00 00 01 00 00 00
9333 12:21:19.855302 in-data: 00
9334 12:21:19.858331 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9335 12:21:19.863355 in-header: 03 fd 00 00 00 00 00 00
9336 12:21:19.866035 in-data:
9337 12:21:19.869710 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9338 12:21:19.872604 in-header: 03 fc 00 00 01 00 00 00
9339 12:21:19.876098 in-data: 00
9340 12:21:19.879207 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9341 12:21:19.883933 in-header: 03 fd 00 00 00 00 00 00
9342 12:21:19.888419 in-data:
9343 12:21:19.890387 [SSUSB] Setting up USB HOST controller...
9344 12:21:19.893982 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9345 12:21:19.897356 [SSUSB] phy power-on done.
9346 12:21:19.900345 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9347 12:21:19.907124 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9348 12:21:19.910008 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9349 12:21:19.917065 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9350 12:21:19.923718 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9351 12:21:19.929885 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9352 12:21:19.936743 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9353 12:21:19.943064 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9354 12:21:19.946318 SPM: binary array size = 0x9dc
9355 12:21:19.952746 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9356 12:21:19.956343 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9357 12:21:19.965865 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9358 12:21:19.969114 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9359 12:21:19.972625 configure_display: Starting display init
9360 12:21:20.007402 anx7625_power_on_init: Init interface.
9361 12:21:20.010426 anx7625_disable_pd_protocol: Disabled PD feature.
9362 12:21:20.014504 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9363 12:21:20.041587 anx7625_start_dp_work: Secure OCM version=00
9364 12:21:20.044710 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9365 12:21:20.060823 sp_tx_get_edid_block: EDID Block = 1
9366 12:21:20.162094 Extracted contents:
9367 12:21:20.165644 header: 00 ff ff ff ff ff ff 00
9368 12:21:20.168923 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9369 12:21:20.172170 version: 01 04
9370 12:21:20.175811 basic params: 95 1f 11 78 0a
9371 12:21:20.178681 chroma info: 76 90 94 55 54 90 27 21 50 54
9372 12:21:20.182116 established: 00 00 00
9373 12:21:20.188715 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9374 12:21:20.195399 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9375 12:21:20.198314 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9376 12:21:20.205116 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9377 12:21:20.211862 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9378 12:21:20.214980 extensions: 00
9379 12:21:20.215081 checksum: fb
9380 12:21:20.215170
9381 12:21:20.221502 Manufacturer: IVO Model 57d Serial Number 0
9382 12:21:20.221601 Made week 0 of 2020
9383 12:21:20.224538 EDID version: 1.4
9384 12:21:20.224612 Digital display
9385 12:21:20.227967 6 bits per primary color channel
9386 12:21:20.231734 DisplayPort interface
9387 12:21:20.231815 Maximum image size: 31 cm x 17 cm
9388 12:21:20.235137 Gamma: 220%
9389 12:21:20.235216 Check DPMS levels
9390 12:21:20.241573 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9391 12:21:20.244541 First detailed timing is preferred timing
9392 12:21:20.247811 Established timings supported:
9393 12:21:20.247892 Standard timings supported:
9394 12:21:20.251254 Detailed timings
9395 12:21:20.254342 Hex of detail: 383680a07038204018303c0035ae10000019
9396 12:21:20.260814 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9397 12:21:20.264643 0780 0798 07c8 0820 hborder 0
9398 12:21:20.268139 0438 043b 0447 0458 vborder 0
9399 12:21:20.270817 -hsync -vsync
9400 12:21:20.270888 Did detailed timing
9401 12:21:20.277208 Hex of detail: 000000000000000000000000000000000000
9402 12:21:20.281006 Manufacturer-specified data, tag 0
9403 12:21:20.283989 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9404 12:21:20.287120 ASCII string: InfoVision
9405 12:21:20.290516 Hex of detail: 000000fe00523134304e574635205248200a
9406 12:21:20.294173 ASCII string: R140NWF5 RH
9407 12:21:20.294277 Checksum
9408 12:21:20.297520 Checksum: 0xfb (valid)
9409 12:21:20.300815 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9410 12:21:20.303926 DSI data_rate: 832800000 bps
9411 12:21:20.310407 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9412 12:21:20.313655 anx7625_parse_edid: pixelclock(138800).
9413 12:21:20.316902 hactive(1920), hsync(48), hfp(24), hbp(88)
9414 12:21:20.320310 vactive(1080), vsync(12), vfp(3), vbp(17)
9415 12:21:20.323297 anx7625_dsi_config: config dsi.
9416 12:21:20.330514 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9417 12:21:20.344478 anx7625_dsi_config: success to config DSI
9418 12:21:20.347675 anx7625_dp_start: MIPI phy setup OK.
9419 12:21:20.350935 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9420 12:21:20.354009 mtk_ddp_mode_set invalid vrefresh 60
9421 12:21:20.357753 main_disp_path_setup
9422 12:21:20.357852 ovl_layer_smi_id_en
9423 12:21:20.360575 ovl_layer_smi_id_en
9424 12:21:20.360680 ccorr_config
9425 12:21:20.360770 aal_config
9426 12:21:20.364353 gamma_config
9427 12:21:20.364451 postmask_config
9428 12:21:20.367035 dither_config
9429 12:21:20.370854 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9430 12:21:20.377419 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9431 12:21:20.380224 Root Device init finished in 551 msecs
9432 12:21:20.383872 CPU_CLUSTER: 0 init
9433 12:21:20.390187 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9434 12:21:20.397467 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9435 12:21:20.397550 APU_MBOX 0x190000b0 = 0x10001
9436 12:21:20.400310 APU_MBOX 0x190001b0 = 0x10001
9437 12:21:20.403458 APU_MBOX 0x190005b0 = 0x10001
9438 12:21:20.406866 APU_MBOX 0x190006b0 = 0x10001
9439 12:21:20.413128 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9440 12:21:20.423332 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9441 12:21:20.435684 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9442 12:21:20.442855 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9443 12:21:20.454130 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9444 12:21:20.463416 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9445 12:21:20.466581 CPU_CLUSTER: 0 init finished in 81 msecs
9446 12:21:20.469563 Devices initialized
9447 12:21:20.473027 Show all devs... After init.
9448 12:21:20.473121 Root Device: enabled 1
9449 12:21:20.476242 CPU_CLUSTER: 0: enabled 1
9450 12:21:20.479572 CPU: 00: enabled 1
9451 12:21:20.483064 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9452 12:21:20.486245 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9453 12:21:20.489880 ELOG: NV offset 0x57f000 size 0x1000
9454 12:21:20.496141 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9455 12:21:20.502698 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9456 12:21:20.505979 ELOG: Event(17) added with size 13 at 2023-08-16 12:21:20 UTC
9457 12:21:20.512838 out: cmd=0x121: 03 db 21 01 00 00 00 00
9458 12:21:20.516017 in-header: 03 da 00 00 2c 00 00 00
9459 12:21:20.526188 in-data: 85 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9460 12:21:20.532333 ELOG: Event(A1) added with size 10 at 2023-08-16 12:21:20 UTC
9461 12:21:20.539206 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9462 12:21:20.545540 ELOG: Event(A0) added with size 9 at 2023-08-16 12:21:20 UTC
9463 12:21:20.548987 elog_add_boot_reason: Logged dev mode boot
9464 12:21:20.555580 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9465 12:21:20.555678 Finalize devices...
9466 12:21:20.558849 Devices finalized
9467 12:21:20.562074 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9468 12:21:20.565469 Writing coreboot table at 0xffe64000
9469 12:21:20.568696 0. 000000000010a000-0000000000113fff: RAMSTAGE
9470 12:21:20.575087 1. 0000000040000000-00000000400fffff: RAM
9471 12:21:20.578501 2. 0000000040100000-000000004032afff: RAMSTAGE
9472 12:21:20.582110 3. 000000004032b000-00000000545fffff: RAM
9473 12:21:20.585089 4. 0000000054600000-000000005465ffff: BL31
9474 12:21:20.588792 5. 0000000054660000-00000000ffe63fff: RAM
9475 12:21:20.595427 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9476 12:21:20.598752 7. 0000000100000000-000000023fffffff: RAM
9477 12:21:20.601483 Passing 5 GPIOs to payload:
9478 12:21:20.605646 NAME | PORT | POLARITY | VALUE
9479 12:21:20.611963 EC in RW | 0x000000aa | low | undefined
9480 12:21:20.614887 EC interrupt | 0x00000005 | low | undefined
9481 12:21:20.618493 TPM interrupt | 0x000000ab | high | undefined
9482 12:21:20.625137 SD card detect | 0x00000011 | high | undefined
9483 12:21:20.628158 speaker enable | 0x00000093 | high | undefined
9484 12:21:20.631167 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9485 12:21:20.635089 in-header: 03 f9 00 00 02 00 00 00
9486 12:21:20.638238 in-data: 02 00
9487 12:21:20.641118 ADC[4]: Raw value=901182 ID=7
9488 12:21:20.644845 ADC[3]: Raw value=213282 ID=1
9489 12:21:20.644913 RAM Code: 0x71
9490 12:21:20.648150 ADC[6]: Raw value=75036 ID=0
9491 12:21:20.651466 ADC[5]: Raw value=212912 ID=1
9492 12:21:20.651534 SKU Code: 0x1
9493 12:21:20.658165 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a12d
9494 12:21:20.658265 coreboot table: 964 bytes.
9495 12:21:20.661050 IMD ROOT 0. 0xfffff000 0x00001000
9496 12:21:20.664275 IMD SMALL 1. 0xffffe000 0x00001000
9497 12:21:20.667919 RO MCACHE 2. 0xffffc000 0x00001104
9498 12:21:20.671243 CONSOLE 3. 0xfff7c000 0x00080000
9499 12:21:20.674283 FMAP 4. 0xfff7b000 0x00000452
9500 12:21:20.677930 TIME STAMP 5. 0xfff7a000 0x00000910
9501 12:21:20.680798 VBOOT WORK 6. 0xfff66000 0x00014000
9502 12:21:20.684379 RAMOOPS 7. 0xffe66000 0x00100000
9503 12:21:20.687214 COREBOOT 8. 0xffe64000 0x00002000
9504 12:21:20.690806 IMD small region:
9505 12:21:20.694190 IMD ROOT 0. 0xffffec00 0x00000400
9506 12:21:20.697213 VPD 1. 0xffffeba0 0x0000004c
9507 12:21:20.700708 MMC STATUS 2. 0xffffeb80 0x00000004
9508 12:21:20.707659 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9509 12:21:20.707734 Probing TPM: done!
9510 12:21:20.714758 Connected to device vid:did:rid of 1ae0:0028:00
9511 12:21:20.720948 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9512 12:21:20.723990 Initialized TPM device CR50 revision 0
9513 12:21:20.727475 Checking cr50 for pending updates
9514 12:21:20.733013 Reading cr50 TPM mode
9515 12:21:20.741943 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9516 12:21:20.747997 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9517 12:21:20.788172 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9518 12:21:20.791279 Checking segment from ROM address 0x40100000
9519 12:21:20.795208 Checking segment from ROM address 0x4010001c
9520 12:21:20.801481 Loading segment from ROM address 0x40100000
9521 12:21:20.801559 code (compression=0)
9522 12:21:20.811353 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9523 12:21:20.818248 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9524 12:21:20.818326 it's not compressed!
9525 12:21:20.824779 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9526 12:21:20.831329 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9527 12:21:20.848591 Loading segment from ROM address 0x4010001c
9528 12:21:20.848668 Entry Point 0x80000000
9529 12:21:20.852026 Loaded segments
9530 12:21:20.855053 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9531 12:21:20.861720 Jumping to boot code at 0x80000000(0xffe64000)
9532 12:21:20.868536 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9533 12:21:20.875118 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9534 12:21:20.882976 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9535 12:21:20.886118 Checking segment from ROM address 0x40100000
9536 12:21:20.889885 Checking segment from ROM address 0x4010001c
9537 12:21:20.896083 Loading segment from ROM address 0x40100000
9538 12:21:20.896161 code (compression=1)
9539 12:21:20.902677 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9540 12:21:20.912839 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9541 12:21:20.912938 using LZMA
9542 12:21:20.921406 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9543 12:21:20.928093 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9544 12:21:20.932077 Loading segment from ROM address 0x4010001c
9545 12:21:20.932155 Entry Point 0x54601000
9546 12:21:20.934614 Loaded segments
9547 12:21:20.937698 NOTICE: MT8192 bl31_setup
9548 12:21:20.945062 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9549 12:21:20.947994 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9550 12:21:20.951465 WARNING: region 0:
9551 12:21:20.954926 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9552 12:21:20.954995 WARNING: region 1:
9553 12:21:20.961448 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9554 12:21:20.964566 WARNING: region 2:
9555 12:21:20.967825 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9556 12:21:20.971311 WARNING: region 3:
9557 12:21:20.975107 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9558 12:21:20.978096 WARNING: region 4:
9559 12:21:20.984787 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9560 12:21:20.984885 WARNING: region 5:
9561 12:21:20.987763 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9562 12:21:20.991135 WARNING: region 6:
9563 12:21:20.994436 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9564 12:21:20.997981 WARNING: region 7:
9565 12:21:21.001516 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9566 12:21:21.008204 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9567 12:21:21.011466 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9568 12:21:21.014521 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9569 12:21:21.021365 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9570 12:21:21.024457 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9571 12:21:21.027954 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9572 12:21:21.034728 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9573 12:21:21.038075 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9574 12:21:21.044674 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9575 12:21:21.047705 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9576 12:21:21.051208 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9577 12:21:21.057799 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9578 12:21:21.061375 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9579 12:21:21.067935 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9580 12:21:21.070806 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9581 12:21:21.074177 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9582 12:21:21.081060 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9583 12:21:21.084917 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9584 12:21:21.087837 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9585 12:21:21.094109 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9586 12:21:21.097629 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9587 12:21:21.104241 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9588 12:21:21.107465 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9589 12:21:21.110780 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9590 12:21:21.117665 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9591 12:21:21.121023 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9592 12:21:21.127442 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9593 12:21:21.130774 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9594 12:21:21.134100 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9595 12:21:21.140596 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9596 12:21:21.144359 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9597 12:21:21.151142 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9598 12:21:21.153940 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9599 12:21:21.157546 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9600 12:21:21.160375 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9601 12:21:21.167691 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9602 12:21:21.170527 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9603 12:21:21.173747 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9604 12:21:21.177022 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9605 12:21:21.183913 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9606 12:21:21.186767 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9607 12:21:21.190811 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9608 12:21:21.193872 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9609 12:21:21.200531 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9610 12:21:21.203443 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9611 12:21:21.206940 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9612 12:21:21.213452 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9613 12:21:21.216459 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9614 12:21:21.220330 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9615 12:21:21.226850 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9616 12:21:21.229698 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9617 12:21:21.236394 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9618 12:21:21.239826 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9619 12:21:21.243151 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9620 12:21:21.249515 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9621 12:21:21.253200 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9622 12:21:21.259657 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9623 12:21:21.262908 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9624 12:21:21.269849 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9625 12:21:21.273028 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9626 12:21:21.276145 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9627 12:21:21.283202 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9628 12:21:21.286344 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9629 12:21:21.292758 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9630 12:21:21.296609 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9631 12:21:21.302477 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9632 12:21:21.306659 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9633 12:21:21.312576 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9634 12:21:21.315841 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9635 12:21:21.319569 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9636 12:21:21.326291 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9637 12:21:21.329241 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9638 12:21:21.336025 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9639 12:21:21.339024 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9640 12:21:21.345872 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9641 12:21:21.349095 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9642 12:21:21.355674 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9643 12:21:21.358915 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9644 12:21:21.362488 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9645 12:21:21.369031 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9646 12:21:21.372722 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9647 12:21:21.378799 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9648 12:21:21.382351 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9649 12:21:21.388909 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9650 12:21:21.392302 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9651 12:21:21.395943 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9652 12:21:21.402743 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9653 12:21:21.405521 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9654 12:21:21.412206 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9655 12:21:21.415614 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9656 12:21:21.422272 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9657 12:21:21.425477 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9658 12:21:21.431793 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9659 12:21:21.435675 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9660 12:21:21.438535 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9661 12:21:21.445873 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9662 12:21:21.448944 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9663 12:21:21.451670 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9664 12:21:21.458414 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9665 12:21:21.461883 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9666 12:21:21.465336 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9667 12:21:21.472134 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9668 12:21:21.474889 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9669 12:21:21.478667 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9670 12:21:21.485084 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9671 12:21:21.488802 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9672 12:21:21.494835 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9673 12:21:21.498071 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9674 12:21:21.502704 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9675 12:21:21.508455 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9676 12:21:21.511580 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9677 12:21:21.517949 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9678 12:21:21.521500 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9679 12:21:21.524859 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9680 12:21:21.532208 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9681 12:21:21.534886 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9682 12:21:21.538096 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9683 12:21:21.544905 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9684 12:21:21.547875 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9685 12:21:21.551216 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9686 12:21:21.558112 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9687 12:21:21.561361 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9688 12:21:21.564751 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9689 12:21:21.567976 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9690 12:21:21.574715 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9691 12:21:21.577935 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9692 12:21:21.584823 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9693 12:21:21.587812 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9694 12:21:21.591162 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9695 12:21:21.598235 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9696 12:21:21.601437 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9697 12:21:21.607823 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9698 12:21:21.611149 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9699 12:21:21.614311 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9700 12:21:21.621195 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9701 12:21:21.624552 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9702 12:21:21.630867 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9703 12:21:21.634100 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9704 12:21:21.637694 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9705 12:21:21.644370 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9706 12:21:21.647451 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9707 12:21:21.650797 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9708 12:21:21.657311 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9709 12:21:21.660713 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9710 12:21:21.667646 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9711 12:21:21.670865 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9712 12:21:21.674129 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9713 12:21:21.680697 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9714 12:21:21.683819 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9715 12:21:21.690461 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9716 12:21:21.694203 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9717 12:21:21.697490 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9718 12:21:21.704466 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9719 12:21:21.707054 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9720 12:21:21.713883 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9721 12:21:21.716904 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9722 12:21:21.720180 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9723 12:21:21.727136 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9724 12:21:21.730122 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9725 12:21:21.736631 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9726 12:21:21.740059 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9727 12:21:21.743652 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9728 12:21:21.750279 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9729 12:21:21.753656 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9730 12:21:21.759788 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9731 12:21:21.763898 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9732 12:21:21.766587 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9733 12:21:21.773380 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9734 12:21:21.776673 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9735 12:21:21.783175 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9736 12:21:21.786800 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9737 12:21:21.790166 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9738 12:21:21.796680 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9739 12:21:21.799460 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9740 12:21:21.806444 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9741 12:21:21.809546 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9742 12:21:21.813264 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9743 12:21:21.819536 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9744 12:21:21.823028 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9745 12:21:21.825999 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9746 12:21:21.832500 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9747 12:21:21.836086 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9748 12:21:21.842908 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9749 12:21:21.845934 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9750 12:21:21.852532 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9751 12:21:21.855865 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9752 12:21:21.858912 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9753 12:21:21.866053 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9754 12:21:21.868877 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9755 12:21:21.875158 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9756 12:21:21.879326 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9757 12:21:21.885272 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9758 12:21:21.889148 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9759 12:21:21.892036 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9760 12:21:21.898315 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9761 12:21:21.901995 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9762 12:21:21.908305 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9763 12:21:21.911811 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9764 12:21:21.915187 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9765 12:21:21.921869 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9766 12:21:21.924953 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9767 12:21:21.932133 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9768 12:21:21.934613 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9769 12:21:21.941757 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9770 12:21:21.944584 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9771 12:21:21.948156 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9772 12:21:21.954534 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9773 12:21:21.957927 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9774 12:21:21.964789 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9775 12:21:21.967715 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9776 12:21:21.974313 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9777 12:21:21.977578 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9778 12:21:21.981126 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9779 12:21:21.987674 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9780 12:21:21.991134 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9781 12:21:21.997249 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9782 12:21:22.000543 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9783 12:21:22.007167 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9784 12:21:22.010335 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9785 12:21:22.013908 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9786 12:21:22.020281 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9787 12:21:22.023685 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9788 12:21:22.030527 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9789 12:21:22.033566 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9790 12:21:22.040669 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9791 12:21:22.043638 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9792 12:21:22.046778 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9793 12:21:22.054059 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9794 12:21:22.056721 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9795 12:21:22.060123 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9796 12:21:22.066809 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9797 12:21:22.070229 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9798 12:21:22.072957 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9799 12:21:22.076652 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9800 12:21:22.083144 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9801 12:21:22.086392 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9802 12:21:22.093200 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9803 12:21:22.096106 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9804 12:21:22.099785 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9805 12:21:22.106312 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9806 12:21:22.109804 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9807 12:21:22.113155 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9808 12:21:22.119197 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9809 12:21:22.122474 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9810 12:21:22.125793 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9811 12:21:22.132562 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9812 12:21:22.135722 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9813 12:21:22.142551 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9814 12:21:22.145965 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9815 12:21:22.148828 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9816 12:21:22.155462 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9817 12:21:22.158794 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9818 12:21:22.166234 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9819 12:21:22.169356 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9820 12:21:22.172372 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9821 12:21:22.179070 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9822 12:21:22.181783 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9823 12:21:22.185471 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9824 12:21:22.192299 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9825 12:21:22.195457 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9826 12:21:22.201941 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9827 12:21:22.204781 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9828 12:21:22.208330 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9829 12:21:22.215121 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9830 12:21:22.218231 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9831 12:21:22.221338 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9832 12:21:22.228293 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9833 12:21:22.231502 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9834 12:21:22.234695 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9835 12:21:22.241288 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9836 12:21:22.244827 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9837 12:21:22.248324 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9838 12:21:22.251489 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9839 12:21:22.254381 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9840 12:21:22.261368 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9841 12:21:22.264368 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9842 12:21:22.267490 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9843 12:21:22.274341 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9844 12:21:22.277615 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9845 12:21:22.280612 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9846 12:21:22.287319 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9847 12:21:22.290967 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9848 12:21:22.294027 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9849 12:21:22.300919 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9850 12:21:22.304116 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9851 12:21:22.310502 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9852 12:21:22.314322 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9853 12:21:22.317188 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9854 12:21:22.323752 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9855 12:21:22.326898 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9856 12:21:22.333707 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9857 12:21:22.336871 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9858 12:21:22.340680 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9859 12:21:22.346741 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9860 12:21:22.350008 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9861 12:21:22.356623 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9862 12:21:22.359894 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9863 12:21:22.366457 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9864 12:21:22.369930 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9865 12:21:22.373477 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9866 12:21:22.379804 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9867 12:21:22.382922 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9868 12:21:22.389608 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9869 12:21:22.393152 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9870 12:21:22.399420 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9871 12:21:22.403087 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9872 12:21:22.406201 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9873 12:21:22.412767 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9874 12:21:22.416221 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9875 12:21:22.422914 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9876 12:21:22.426009 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9877 12:21:22.429654 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9878 12:21:22.436066 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9879 12:21:22.439143 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9880 12:21:22.446479 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9881 12:21:22.448975 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9882 12:21:22.452540 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9883 12:21:22.458810 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9884 12:21:22.462203 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9885 12:21:22.468995 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9886 12:21:22.472233 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9887 12:21:22.478925 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9888 12:21:22.481996 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9889 12:21:22.485213 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9890 12:21:22.491691 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9891 12:21:22.495117 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9892 12:21:22.501983 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9893 12:21:22.504970 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9894 12:21:22.511609 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9895 12:21:22.515182 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9896 12:21:22.518283 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9897 12:21:22.524752 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9898 12:21:22.528113 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9899 12:21:22.534394 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9900 12:21:22.537741 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9901 12:21:22.544149 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9902 12:21:22.547739 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9903 12:21:22.551182 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9904 12:21:22.557830 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9905 12:21:22.561239 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9906 12:21:22.567239 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9907 12:21:22.571080 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9908 12:21:22.574035 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9909 12:21:22.580708 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9910 12:21:22.583937 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9911 12:21:22.590584 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9912 12:21:22.594022 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9913 12:21:22.597700 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9914 12:21:22.603743 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9915 12:21:22.607312 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9916 12:21:22.613585 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9917 12:21:22.616868 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9918 12:21:22.623786 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9919 12:21:22.626996 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9920 12:21:22.630414 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9921 12:21:22.636775 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9922 12:21:22.640130 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9923 12:21:22.647120 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9924 12:21:22.650330 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9925 12:21:22.656957 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9926 12:21:22.659779 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9927 12:21:22.663333 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9928 12:21:22.669897 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9929 12:21:22.673130 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9930 12:21:22.680103 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9931 12:21:22.683207 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9932 12:21:22.689896 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9933 12:21:22.693218 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9934 12:21:22.699508 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9935 12:21:22.702752 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9936 12:21:22.706254 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9937 12:21:22.712636 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9938 12:21:22.716527 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9939 12:21:22.722548 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9940 12:21:22.726081 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9941 12:21:22.732754 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9942 12:21:22.735626 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9943 12:21:22.742364 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9944 12:21:22.745332 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9945 12:21:22.748900 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9946 12:21:22.755623 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9947 12:21:22.758842 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9948 12:21:22.765226 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9949 12:21:22.768737 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9950 12:21:22.775619 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9951 12:21:22.778891 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9952 12:21:22.785668 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9953 12:21:22.788990 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9954 12:21:22.792142 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9955 12:21:22.798839 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9956 12:21:22.802106 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9957 12:21:22.808694 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9958 12:21:22.811827 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9959 12:21:22.818206 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9960 12:21:22.822488 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9961 12:21:22.828350 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9962 12:21:22.831320 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9963 12:21:22.835857 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9964 12:21:22.841929 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9965 12:21:22.844616 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9966 12:21:22.851466 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9967 12:21:22.854753 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9968 12:21:22.858025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9969 12:21:22.864370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9970 12:21:22.867793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9971 12:21:22.874626 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9972 12:21:22.877938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9973 12:21:22.885100 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9974 12:21:22.887812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9975 12:21:22.894373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9976 12:21:22.897786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9977 12:21:22.904591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9978 12:21:22.908005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9979 12:21:22.914493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9980 12:21:22.918075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9981 12:21:22.924801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9982 12:21:22.927905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9983 12:21:22.934384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9984 12:21:22.937891 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9985 12:21:22.944760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9986 12:21:22.947699 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9987 12:21:22.954683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9988 12:21:22.957843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9989 12:21:22.964636 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9990 12:21:22.967670 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9991 12:21:22.974084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9992 12:21:22.977836 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9993 12:21:22.983810 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9994 12:21:22.987211 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9995 12:21:22.994020 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9996 12:21:22.997003 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9997 12:21:23.004350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9998 12:21:23.006992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9999 12:21:23.013711 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10000 12:21:23.017116 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10001 12:21:23.020312 INFO: [APUAPC] vio 0
10002 12:21:23.023998 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10003 12:21:23.030352 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10004 12:21:23.033696 INFO: [APUAPC] D0_APC_0: 0x400510
10005 12:21:23.036392 INFO: [APUAPC] D0_APC_1: 0x0
10006 12:21:23.036853 INFO: [APUAPC] D0_APC_2: 0x1540
10007 12:21:23.040383 INFO: [APUAPC] D0_APC_3: 0x0
10008 12:21:23.043838 INFO: [APUAPC] D1_APC_0: 0xffffffff
10009 12:21:23.046697 INFO: [APUAPC] D1_APC_1: 0xffffffff
10010 12:21:23.049991 INFO: [APUAPC] D1_APC_2: 0x3fffff
10011 12:21:23.053542 INFO: [APUAPC] D1_APC_3: 0x0
10012 12:21:23.056517 INFO: [APUAPC] D2_APC_0: 0xffffffff
10013 12:21:23.060043 INFO: [APUAPC] D2_APC_1: 0xffffffff
10014 12:21:23.063153 INFO: [APUAPC] D2_APC_2: 0x3fffff
10015 12:21:23.067155 INFO: [APUAPC] D2_APC_3: 0x0
10016 12:21:23.070497 INFO: [APUAPC] D3_APC_0: 0xffffffff
10017 12:21:23.073466 INFO: [APUAPC] D3_APC_1: 0xffffffff
10018 12:21:23.076639 INFO: [APUAPC] D3_APC_2: 0x3fffff
10019 12:21:23.080041 INFO: [APUAPC] D3_APC_3: 0x0
10020 12:21:23.083316 INFO: [APUAPC] D4_APC_0: 0xffffffff
10021 12:21:23.086694 INFO: [APUAPC] D4_APC_1: 0xffffffff
10022 12:21:23.089740 INFO: [APUAPC] D4_APC_2: 0x3fffff
10023 12:21:23.092969 INFO: [APUAPC] D4_APC_3: 0x0
10024 12:21:23.096338 INFO: [APUAPC] D5_APC_0: 0xffffffff
10025 12:21:23.099452 INFO: [APUAPC] D5_APC_1: 0xffffffff
10026 12:21:23.102536 INFO: [APUAPC] D5_APC_2: 0x3fffff
10027 12:21:23.106466 INFO: [APUAPC] D5_APC_3: 0x0
10028 12:21:23.109382 INFO: [APUAPC] D6_APC_0: 0xffffffff
10029 12:21:23.112962 INFO: [APUAPC] D6_APC_1: 0xffffffff
10030 12:21:23.116506 INFO: [APUAPC] D6_APC_2: 0x3fffff
10031 12:21:23.119221 INFO: [APUAPC] D6_APC_3: 0x0
10032 12:21:23.122632 INFO: [APUAPC] D7_APC_0: 0xffffffff
10033 12:21:23.126230 INFO: [APUAPC] D7_APC_1: 0xffffffff
10034 12:21:23.129578 INFO: [APUAPC] D7_APC_2: 0x3fffff
10035 12:21:23.132475 INFO: [APUAPC] D7_APC_3: 0x0
10036 12:21:23.135891 INFO: [APUAPC] D8_APC_0: 0xffffffff
10037 12:21:23.139298 INFO: [APUAPC] D8_APC_1: 0xffffffff
10038 12:21:23.143129 INFO: [APUAPC] D8_APC_2: 0x3fffff
10039 12:21:23.146101 INFO: [APUAPC] D8_APC_3: 0x0
10040 12:21:23.149098 INFO: [APUAPC] D9_APC_0: 0xffffffff
10041 12:21:23.152161 INFO: [APUAPC] D9_APC_1: 0xffffffff
10042 12:21:23.156404 INFO: [APUAPC] D9_APC_2: 0x3fffff
10043 12:21:23.159052 INFO: [APUAPC] D9_APC_3: 0x0
10044 12:21:23.162263 INFO: [APUAPC] D10_APC_0: 0xffffffff
10045 12:21:23.165808 INFO: [APUAPC] D10_APC_1: 0xffffffff
10046 12:21:23.168959 INFO: [APUAPC] D10_APC_2: 0x3fffff
10047 12:21:23.171938 INFO: [APUAPC] D10_APC_3: 0x0
10048 12:21:23.175635 INFO: [APUAPC] D11_APC_0: 0xffffffff
10049 12:21:23.179151 INFO: [APUAPC] D11_APC_1: 0xffffffff
10050 12:21:23.181927 INFO: [APUAPC] D11_APC_2: 0x3fffff
10051 12:21:23.185795 INFO: [APUAPC] D11_APC_3: 0x0
10052 12:21:23.188934 INFO: [APUAPC] D12_APC_0: 0xffffffff
10053 12:21:23.192121 INFO: [APUAPC] D12_APC_1: 0xffffffff
10054 12:21:23.195186 INFO: [APUAPC] D12_APC_2: 0x3fffff
10055 12:21:23.199219 INFO: [APUAPC] D12_APC_3: 0x0
10056 12:21:23.202337 INFO: [APUAPC] D13_APC_0: 0xffffffff
10057 12:21:23.205788 INFO: [APUAPC] D13_APC_1: 0xffffffff
10058 12:21:23.208626 INFO: [APUAPC] D13_APC_2: 0x3fffff
10059 12:21:23.212062 INFO: [APUAPC] D13_APC_3: 0x0
10060 12:21:23.215562 INFO: [APUAPC] D14_APC_0: 0xffffffff
10061 12:21:23.218304 INFO: [APUAPC] D14_APC_1: 0xffffffff
10062 12:21:23.221705 INFO: [APUAPC] D14_APC_2: 0x3fffff
10063 12:21:23.225571 INFO: [APUAPC] D14_APC_3: 0x0
10064 12:21:23.228767 INFO: [APUAPC] D15_APC_0: 0xffffffff
10065 12:21:23.231668 INFO: [APUAPC] D15_APC_1: 0xffffffff
10066 12:21:23.235137 INFO: [APUAPC] D15_APC_2: 0x3fffff
10067 12:21:23.238740 INFO: [APUAPC] D15_APC_3: 0x0
10068 12:21:23.242178 INFO: [APUAPC] APC_CON: 0x4
10069 12:21:23.245737 INFO: [NOCDAPC] D0_APC_0: 0x0
10070 12:21:23.248070 INFO: [NOCDAPC] D0_APC_1: 0x0
10071 12:21:23.251499 INFO: [NOCDAPC] D1_APC_0: 0x0
10072 12:21:23.251962 INFO: [NOCDAPC] D1_APC_1: 0xfff
10073 12:21:23.255138 INFO: [NOCDAPC] D2_APC_0: 0x0
10074 12:21:23.258241 INFO: [NOCDAPC] D2_APC_1: 0xfff
10075 12:21:23.262008 INFO: [NOCDAPC] D3_APC_0: 0x0
10076 12:21:23.265096 INFO: [NOCDAPC] D3_APC_1: 0xfff
10077 12:21:23.268045 INFO: [NOCDAPC] D4_APC_0: 0x0
10078 12:21:23.271317 INFO: [NOCDAPC] D4_APC_1: 0xfff
10079 12:21:23.275016 INFO: [NOCDAPC] D5_APC_0: 0x0
10080 12:21:23.278211 INFO: [NOCDAPC] D5_APC_1: 0xfff
10081 12:21:23.281456 INFO: [NOCDAPC] D6_APC_0: 0x0
10082 12:21:23.285033 INFO: [NOCDAPC] D6_APC_1: 0xfff
10083 12:21:23.285588 INFO: [NOCDAPC] D7_APC_0: 0x0
10084 12:21:23.288376 INFO: [NOCDAPC] D7_APC_1: 0xfff
10085 12:21:23.291555 INFO: [NOCDAPC] D8_APC_0: 0x0
10086 12:21:23.295092 INFO: [NOCDAPC] D8_APC_1: 0xfff
10087 12:21:23.297791 INFO: [NOCDAPC] D9_APC_0: 0x0
10088 12:21:23.300868 INFO: [NOCDAPC] D9_APC_1: 0xfff
10089 12:21:23.305095 INFO: [NOCDAPC] D10_APC_0: 0x0
10090 12:21:23.307687 INFO: [NOCDAPC] D10_APC_1: 0xfff
10091 12:21:23.311093 INFO: [NOCDAPC] D11_APC_0: 0x0
10092 12:21:23.314992 INFO: [NOCDAPC] D11_APC_1: 0xfff
10093 12:21:23.317545 INFO: [NOCDAPC] D12_APC_0: 0x0
10094 12:21:23.320847 INFO: [NOCDAPC] D12_APC_1: 0xfff
10095 12:21:23.323832 INFO: [NOCDAPC] D13_APC_0: 0x0
10096 12:21:23.327347 INFO: [NOCDAPC] D13_APC_1: 0xfff
10097 12:21:23.331062 INFO: [NOCDAPC] D14_APC_0: 0x0
10098 12:21:23.331526 INFO: [NOCDAPC] D14_APC_1: 0xfff
10099 12:21:23.334541 INFO: [NOCDAPC] D15_APC_0: 0x0
10100 12:21:23.337636 INFO: [NOCDAPC] D15_APC_1: 0xfff
10101 12:21:23.341092 INFO: [NOCDAPC] APC_CON: 0x4
10102 12:21:23.343804 INFO: [APUAPC] set_apusys_apc done
10103 12:21:23.347311 INFO: [DEVAPC] devapc_init done
10104 12:21:23.350645 INFO: GICv3 without legacy support detected.
10105 12:21:23.357351 INFO: ARM GICv3 driver initialized in EL3
10106 12:21:23.360518 INFO: Maximum SPI INTID supported: 639
10107 12:21:23.364081 INFO: BL31: Initializing runtime services
10108 12:21:23.370089 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10109 12:21:23.373808 INFO: SPM: enable CPC mode
10110 12:21:23.376705 INFO: mcdi ready for mcusys-off-idle and system suspend
10111 12:21:23.383094 INFO: BL31: Preparing for EL3 exit to normal world
10112 12:21:23.386767 INFO: Entry point address = 0x80000000
10113 12:21:23.387313 INFO: SPSR = 0x8
10114 12:21:23.393538
10115 12:21:23.394302
10116 12:21:23.394735
10117 12:21:23.396867 Starting depthcharge on Spherion...
10118 12:21:23.397704
10119 12:21:23.398112 Wipe memory regions:
10120 12:21:23.398458
10121 12:21:23.401222 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10122 12:21:23.401779 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10123 12:21:23.403605 Setting prompt string to ['asurada:']
10124 12:21:23.404076 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10125 12:21:23.404802 [0x00000040000000, 0x00000054600000)
10126 12:21:23.522742
10127 12:21:23.523296 [0x00000054660000, 0x00000080000000)
10128 12:21:23.782886
10129 12:21:23.783439 [0x000000821a7280, 0x000000ffe64000)
10130 12:21:24.528278
10131 12:21:24.528834 [0x00000100000000, 0x00000240000000)
10132 12:21:26.418175
10133 12:21:26.420776 Initializing XHCI USB controller at 0x11200000.
10134 12:21:27.402563
10135 12:21:27.403159 R8152: Initializing
10136 12:21:27.403530
10137 12:21:27.405902 Version 9 (ocp_data = 6010)
10138 12:21:27.406517
10139 12:21:27.409085 R8152: Done initializing
10140 12:21:27.409696
10141 12:21:27.410074 Adding net device
10142 12:21:27.930450
10143 12:21:27.933873 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10144 12:21:27.934271
10145 12:21:27.934665
10146 12:21:27.935017
10147 12:21:27.935760 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10149 12:21:28.036903 asurada: tftpboot 192.168.201.1 11299297/tftp-deploy-mxwlri9y/kernel/image.itb 11299297/tftp-deploy-mxwlri9y/kernel/cmdline
10150 12:21:28.037554 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10151 12:21:28.038155 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10152 12:21:28.042713 tftpboot 192.168.201.1 11299297/tftp-deploy-mxwlri9y/kernel/image.itp-deploy-mxwlri9y/kernel/cmdline
10153 12:21:28.043183
10154 12:21:28.043549 Waiting for link
10155 12:21:28.244701
10156 12:21:28.245445 done.
10157 12:21:28.246027
10158 12:21:28.246640 MAC: f4:f5:e8:50:de:0a
10159 12:21:28.247083
10160 12:21:28.248685 Sending DHCP discover... done.
10161 12:21:28.249140
10162 12:21:28.251414 Waiting for reply... done.
10163 12:21:28.251904
10164 12:21:28.254544 Sending DHCP request... done.
10165 12:21:28.255048
10166 12:21:28.260650 Waiting for reply... done.
10167 12:21:28.261113
10168 12:21:28.261477 My ip is 192.168.201.14
10169 12:21:28.261815
10170 12:21:28.263536 The DHCP server ip is 192.168.201.1
10171 12:21:28.264000
10172 12:21:28.270434 TFTP server IP predefined by user: 192.168.201.1
10173 12:21:28.270897
10174 12:21:28.276909 Bootfile predefined by user: 11299297/tftp-deploy-mxwlri9y/kernel/image.itb
10175 12:21:28.277358
10176 12:21:28.280072 Sending tftp read request... done.
10177 12:21:28.280648
10178 12:21:28.286351 Waiting for the transfer...
10179 12:21:28.286808
10180 12:21:28.604515 00000000 ################################################################
10181 12:21:28.604648
10182 12:21:28.834297 00080000 ################################################################
10183 12:21:28.834424
10184 12:21:29.068854 00100000 ################################################################
10185 12:21:29.069009
10186 12:21:29.308286 00180000 ################################################################
10187 12:21:29.308443
10188 12:21:29.548236 00200000 ################################################################
10189 12:21:29.548373
10190 12:21:29.811128 00280000 ################################################################
10191 12:21:29.811268
10192 12:21:30.074908 00300000 ################################################################
10193 12:21:30.075059
10194 12:21:30.314306 00380000 ################################################################
10195 12:21:30.314457
10196 12:21:30.562398 00400000 ################################################################
10197 12:21:30.562546
10198 12:21:30.819771 00480000 ################################################################
10199 12:21:30.819908
10200 12:21:31.068242 00500000 ################################################################
10201 12:21:31.068388
10202 12:21:31.337353 00580000 ################################################################
10203 12:21:31.337525
10204 12:21:31.609437 00600000 ################################################################
10205 12:21:31.609580
10206 12:21:31.872688 00680000 ################################################################
10207 12:21:31.872834
10208 12:21:32.125435 00700000 ################################################################
10209 12:21:32.125575
10210 12:21:32.395252 00780000 ################################################################
10211 12:21:32.395394
10212 12:21:32.666030 00800000 ################################################################
10213 12:21:32.666168
10214 12:21:32.926143 00880000 ################################################################
10215 12:21:32.926283
10216 12:21:33.193929 00900000 ################################################################
10217 12:21:33.194068
10218 12:21:33.524004 00980000 ################################################################
10219 12:21:33.524147
10220 12:21:33.797146 00a00000 ################################################################
10221 12:21:33.797292
10222 12:21:34.055273 00a80000 ################################################################
10223 12:21:34.055407
10224 12:21:34.294262 00b00000 ################################################################
10225 12:21:34.294401
10226 12:21:34.560828 00b80000 ################################################################
10227 12:21:34.560973
10228 12:21:34.831472 00c00000 ################################################################
10229 12:21:34.831617
10230 12:21:35.105520 00c80000 ################################################################
10231 12:21:35.105659
10232 12:21:35.375171 00d00000 ################################################################
10233 12:21:35.375313
10234 12:21:35.646476 00d80000 ################################################################
10235 12:21:35.646669
10236 12:21:35.917094 00e00000 ################################################################
10237 12:21:35.917236
10238 12:21:36.161936 00e80000 ################################################################
10239 12:21:36.162075
10240 12:21:36.422746 00f00000 ################################################################
10241 12:21:36.422887
10242 12:21:36.689552 00f80000 ################################################################
10243 12:21:36.689694
10244 12:21:36.951807 01000000 ################################################################
10245 12:21:36.951950
10246 12:21:37.213306 01080000 ################################################################
10247 12:21:37.213443
10248 12:21:37.481479 01100000 ################################################################
10249 12:21:37.481621
10250 12:21:37.735876 01180000 ################################################################
10251 12:21:37.736014
10252 12:21:37.985220 01200000 ################################################################
10253 12:21:37.985357
10254 12:21:38.256310 01280000 ################################################################
10255 12:21:38.256453
10256 12:21:38.518136 01300000 ################################################################
10257 12:21:38.518272
10258 12:21:38.786443 01380000 ################################################################
10259 12:21:38.786638
10260 12:21:39.053184 01400000 ################################################################
10261 12:21:39.053322
10262 12:21:39.319159 01480000 ################################################################
10263 12:21:39.319298
10264 12:21:39.586587 01500000 ################################################################
10265 12:21:39.586769
10266 12:21:39.853400 01580000 ################################################################
10267 12:21:39.853544
10268 12:21:40.121354 01600000 ################################################################
10269 12:21:40.121503
10270 12:21:40.381278 01680000 ################################################################
10271 12:21:40.381420
10272 12:21:40.638000 01700000 ################################################################
10273 12:21:40.638138
10274 12:21:40.910198 01780000 ################################################################
10275 12:21:40.910338
10276 12:21:41.181539 01800000 ################################################################
10277 12:21:41.181679
10278 12:21:41.445425 01880000 ################################################################
10279 12:21:41.445569
10280 12:21:41.697674 01900000 ################################################################
10281 12:21:41.697814
10282 12:21:41.948262 01980000 ################################################################
10283 12:21:41.948404
10284 12:21:42.217402 01a00000 ################################################################
10285 12:21:42.217542
10286 12:21:42.464007 01a80000 ################################################################
10287 12:21:42.464145
10288 12:21:42.715635 01b00000 ################################################################
10289 12:21:42.715786
10290 12:21:42.727379 01b80000 ### done.
10291 12:21:42.727464
10292 12:21:42.730322 The bootfile was 28860154 bytes long.
10293 12:21:42.730413
10294 12:21:42.734189 Sending tftp read request... done.
10295 12:21:42.734368
10296 12:21:42.734506 Waiting for the transfer...
10297 12:21:42.734653
10298 12:21:42.737291 00000000 # done.
10299 12:21:42.737402
10300 12:21:42.743921 Command line loaded dynamically from TFTP file: 11299297/tftp-deploy-mxwlri9y/kernel/cmdline
10301 12:21:42.744132
10302 12:21:42.766801 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11299297/extract-nfsrootfs-oufad8j8,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10303 12:21:42.767062
10304 12:21:42.767212 Loading FIT.
10305 12:21:42.767349
10306 12:21:42.770141 Image ramdisk-1 has 17770465 bytes.
10307 12:21:42.770347
10308 12:21:42.773772 Image fdt-1 has 47278 bytes.
10309 12:21:42.774096
10310 12:21:42.776556 Image kernel-1 has 11040376 bytes.
10311 12:21:42.776883
10312 12:21:42.786883 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10313 12:21:42.787346
10314 12:21:42.803419 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10315 12:21:42.804005
10316 12:21:42.810231 Choosing best match conf-1 for compat google,spherion-rev2.
10317 12:21:42.813586
10318 12:21:42.817755 Connected to device vid:did:rid of 1ae0:0028:00
10319 12:21:42.825037
10320 12:21:42.828086 tpm_get_response: command 0x17b, return code 0x0
10321 12:21:42.828567
10322 12:21:42.831533 ec_init: CrosEC protocol v3 supported (256, 248)
10323 12:21:42.835768
10324 12:21:42.838850 tpm_cleanup: add release locality here.
10325 12:21:42.839411
10326 12:21:42.839779 Shutting down all USB controllers.
10327 12:21:42.842372
10328 12:21:42.842872 Removing current net device
10329 12:21:42.843238
10330 12:21:42.848578 Exiting depthcharge with code 4 at timestamp: 48852700
10331 12:21:42.849125
10332 12:21:42.851988 LZMA decompressing kernel-1 to 0x821a6718
10333 12:21:42.852452
10334 12:21:42.855273 LZMA decompressing kernel-1 to 0x40000000
10335 12:21:44.243187
10336 12:21:44.243825 jumping to kernel
10337 12:21:44.245272 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
10338 12:21:44.245852 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10339 12:21:44.246285 Setting prompt string to ['Linux version [0-9]']
10340 12:21:44.246741 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10341 12:21:44.247148 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10342 12:21:44.324849
10343 12:21:44.327579 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10344 12:21:44.331494 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10345 12:21:44.332075 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10346 12:21:44.332474 Setting prompt string to []
10347 12:21:44.332890 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10348 12:21:44.333291 Using line separator: #'\n'#
10349 12:21:44.333633 No login prompt set.
10350 12:21:44.333975 Parsing kernel messages
10351 12:21:44.334290 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10352 12:21:44.334906 [login-action] Waiting for messages, (timeout 00:04:04)
10353 12:21:44.350702 [ 0.000000] Linux version 6.1.45-cip3 (KernelCI@build-j14831-arm64-gcc-10-defconfig-arm64-chromebook-g8jrt) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Aug 16 12:04:53 UTC 2023
10354 12:21:44.353940 [ 0.000000] random: crng init done
10355 12:21:44.361052 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10356 12:21:44.364025 [ 0.000000] efi: UEFI not found.
10357 12:21:44.370933 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10358 12:21:44.380353 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10359 12:21:44.387318 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10360 12:21:44.397392 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10361 12:21:44.403624 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10362 12:21:44.410259 [ 0.000000] printk: bootconsole [mtk8250] enabled
10363 12:21:44.416733 [ 0.000000] NUMA: No NUMA configuration found
10364 12:21:44.423244 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10365 12:21:44.426978 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10366 12:21:44.430039 [ 0.000000] Zone ranges:
10367 12:21:44.436573 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10368 12:21:44.439847 [ 0.000000] DMA32 empty
10369 12:21:44.446813 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10370 12:21:44.449861 [ 0.000000] Movable zone start for each node
10371 12:21:44.453066 [ 0.000000] Early memory node ranges
10372 12:21:44.460100 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10373 12:21:44.466325 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10374 12:21:44.473432 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10375 12:21:44.479695 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10376 12:21:44.486102 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10377 12:21:44.492925 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10378 12:21:44.548869 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10379 12:21:44.555232 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10380 12:21:44.561971 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10381 12:21:44.564990 [ 0.000000] psci: probing for conduit method from DT.
10382 12:21:44.571778 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10383 12:21:44.574891 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10384 12:21:44.581770 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10385 12:21:44.584673 [ 0.000000] psci: SMC Calling Convention v1.2
10386 12:21:44.591807 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10387 12:21:44.594906 [ 0.000000] Detected VIPT I-cache on CPU0
10388 12:21:44.601263 [ 0.000000] CPU features: detected: GIC system register CPU interface
10389 12:21:44.608489 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10390 12:21:44.614492 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10391 12:21:44.620896 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10392 12:21:44.631253 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10393 12:21:44.637604 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10394 12:21:44.640846 [ 0.000000] alternatives: applying boot alternatives
10395 12:21:44.648048 [ 0.000000] Fallback order for Node 0: 0
10396 12:21:44.653891 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10397 12:21:44.657786 [ 0.000000] Policy zone: Normal
10398 12:21:44.680609 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11299297/extract-nfsrootfs-oufad8j8,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10399 12:21:44.690402 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10400 12:21:44.701283 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10401 12:21:44.711148 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10402 12:21:44.717961 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10403 12:21:44.721042 <6>[ 0.000000] software IO TLB: area num 8.
10404 12:21:44.778659 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10405 12:21:44.927978 <6>[ 0.000000] Memory: 7952204K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 400564K reserved, 32768K cma-reserved)
10406 12:21:44.934430 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10407 12:21:44.941633 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10408 12:21:44.944764 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10409 12:21:44.950906 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10410 12:21:44.957768 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10411 12:21:44.960980 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10412 12:21:44.970697 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10413 12:21:44.977320 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10414 12:21:44.983939 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10415 12:21:44.990896 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10416 12:21:44.994011 <6>[ 0.000000] GICv3: 608 SPIs implemented
10417 12:21:44.997613 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10418 12:21:45.003864 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10419 12:21:45.007039 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10420 12:21:45.013556 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10421 12:21:45.027166 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10422 12:21:45.039921 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10423 12:21:45.046765 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10424 12:21:45.054167 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10425 12:21:45.067355 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10426 12:21:45.074183 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10427 12:21:45.080785 <6>[ 0.009184] Console: colour dummy device 80x25
10428 12:21:45.090534 <6>[ 0.013911] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10429 12:21:45.097078 <6>[ 0.024393] pid_max: default: 32768 minimum: 301
10430 12:21:45.101173 <6>[ 0.029265] LSM: Security Framework initializing
10431 12:21:45.106767 <6>[ 0.034201] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10432 12:21:45.117010 <6>[ 0.042015] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10433 12:21:45.126972 <6>[ 0.051439] cblist_init_generic: Setting adjustable number of callback queues.
10434 12:21:45.133508 <6>[ 0.058884] cblist_init_generic: Setting shift to 3 and lim to 1.
10435 12:21:45.139807 <6>[ 0.065222] cblist_init_generic: Setting adjustable number of callback queues.
10436 12:21:45.146745 <6>[ 0.072648] cblist_init_generic: Setting shift to 3 and lim to 1.
10437 12:21:45.149843 <6>[ 0.079084] rcu: Hierarchical SRCU implementation.
10438 12:21:45.156472 <6>[ 0.084130] rcu: Max phase no-delay instances is 1000.
10439 12:21:45.163076 <6>[ 0.091156] EFI services will not be available.
10440 12:21:45.166769 <6>[ 0.096156] smp: Bringing up secondary CPUs ...
10441 12:21:45.174948 <6>[ 0.101211] Detected VIPT I-cache on CPU1
10442 12:21:45.182118 <6>[ 0.101282] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10443 12:21:45.188584 <6>[ 0.101310] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10444 12:21:45.191777 <6>[ 0.101647] Detected VIPT I-cache on CPU2
10445 12:21:45.198751 <6>[ 0.101697] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10446 12:21:45.208374 <6>[ 0.101713] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10447 12:21:45.211523 <6>[ 0.101970] Detected VIPT I-cache on CPU3
10448 12:21:45.218271 <6>[ 0.102018] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10449 12:21:45.225102 <6>[ 0.102032] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10450 12:21:45.228099 <6>[ 0.102336] CPU features: detected: Spectre-v4
10451 12:21:45.234775 <6>[ 0.102342] CPU features: detected: Spectre-BHB
10452 12:21:45.238138 <6>[ 0.102347] Detected PIPT I-cache on CPU4
10453 12:21:45.244864 <6>[ 0.102405] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10454 12:21:45.251728 <6>[ 0.102422] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10455 12:21:45.258277 <6>[ 0.102720] Detected PIPT I-cache on CPU5
10456 12:21:45.264592 <6>[ 0.102782] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10457 12:21:45.270734 <6>[ 0.102798] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10458 12:21:45.274436 <6>[ 0.103083] Detected PIPT I-cache on CPU6
10459 12:21:45.280866 <6>[ 0.103148] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10460 12:21:45.290831 <6>[ 0.103164] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10461 12:21:45.294246 <6>[ 0.103463] Detected PIPT I-cache on CPU7
10462 12:21:45.301019 <6>[ 0.103527] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10463 12:21:45.307330 <6>[ 0.103544] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10464 12:21:45.310643 <6>[ 0.103592] smp: Brought up 1 node, 8 CPUs
10465 12:21:45.317361 <6>[ 0.244916] SMP: Total of 8 processors activated.
10466 12:21:45.320464 <6>[ 0.249837] CPU features: detected: 32-bit EL0 Support
10467 12:21:45.330199 <6>[ 0.255199] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10468 12:21:45.336939 <6>[ 0.264000] CPU features: detected: Common not Private translations
10469 12:21:45.343726 <6>[ 0.270476] CPU features: detected: CRC32 instructions
10470 12:21:45.349930 <6>[ 0.275827] CPU features: detected: RCpc load-acquire (LDAPR)
10471 12:21:45.353295 <6>[ 0.281788] CPU features: detected: LSE atomic instructions
10472 12:21:45.360310 <6>[ 0.287605] CPU features: detected: Privileged Access Never
10473 12:21:45.366749 <6>[ 0.293385] CPU features: detected: RAS Extension Support
10474 12:21:45.372894 <6>[ 0.299029] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10475 12:21:45.376753 <6>[ 0.306249] CPU: All CPU(s) started at EL2
10476 12:21:45.382986 <6>[ 0.310592] alternatives: applying system-wide alternatives
10477 12:21:45.392685 <6>[ 0.321303] devtmpfs: initialized
10478 12:21:45.409022 <6>[ 0.330198] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10479 12:21:45.415322 <6>[ 0.340160] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10480 12:21:45.421949 <6>[ 0.348328] pinctrl core: initialized pinctrl subsystem
10481 12:21:45.425155 <6>[ 0.355000] DMI not present or invalid.
10482 12:21:45.431910 <6>[ 0.359411] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10483 12:21:45.441653 <6>[ 0.366288] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10484 12:21:45.448147 <6>[ 0.373873] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10485 12:21:45.458233 <6>[ 0.382092] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10486 12:21:45.461460 <6>[ 0.390333] audit: initializing netlink subsys (disabled)
10487 12:21:45.471213 <5>[ 0.396025] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10488 12:21:45.477755 <6>[ 0.396733] thermal_sys: Registered thermal governor 'step_wise'
10489 12:21:45.484101 <6>[ 0.403991] thermal_sys: Registered thermal governor 'power_allocator'
10490 12:21:45.488130 <6>[ 0.410246] cpuidle: using governor menu
10491 12:21:45.494178 <6>[ 0.421205] NET: Registered PF_QIPCRTR protocol family
10492 12:21:45.500535 <6>[ 0.426695] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10493 12:21:45.507236 <6>[ 0.433803] ASID allocator initialised with 32768 entries
10494 12:21:45.510866 <6>[ 0.440376] Serial: AMBA PL011 UART driver
10495 12:21:45.520873 <4>[ 0.449171] Trying to register duplicate clock ID: 134
10496 12:21:45.574776 <6>[ 0.506584] KASLR enabled
10497 12:21:45.589051 <6>[ 0.514298] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10498 12:21:45.595511 <6>[ 0.521311] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10499 12:21:45.602035 <6>[ 0.527803] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10500 12:21:45.608864 <6>[ 0.534807] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10501 12:21:45.615058 <6>[ 0.541295] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10502 12:21:45.621336 <6>[ 0.548301] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10503 12:21:45.628748 <6>[ 0.554788] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10504 12:21:45.634730 <6>[ 0.561791] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10505 12:21:45.641305 <6>[ 0.569386] ACPI: Interpreter disabled.
10506 12:21:45.648450 <6>[ 0.575746] iommu: Default domain type: Translated
10507 12:21:45.655140 <6>[ 0.580857] iommu: DMA domain TLB invalidation policy: strict mode
10508 12:21:45.658108 <5>[ 0.587521] SCSI subsystem initialized
10509 12:21:45.664446 <6>[ 0.591679] usbcore: registered new interface driver usbfs
10510 12:21:45.667625 <6>[ 0.597410] usbcore: registered new interface driver hub
10511 12:21:45.674229 <6>[ 0.602958] usbcore: registered new device driver usb
10512 12:21:45.681539 <6>[ 0.609058] pps_core: LinuxPPS API ver. 1 registered
10513 12:21:45.690971 <6>[ 0.614251] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10514 12:21:45.693919 <6>[ 0.623597] PTP clock support registered
10515 12:21:45.697241 <6>[ 0.627837] EDAC MC: Ver: 3.0.0
10516 12:21:45.704678 <6>[ 0.632990] FPGA manager framework
10517 12:21:45.711037 <6>[ 0.636672] Advanced Linux Sound Architecture Driver Initialized.
10518 12:21:45.714288 <6>[ 0.643444] vgaarb: loaded
10519 12:21:45.721342 <6>[ 0.646626] clocksource: Switched to clocksource arch_sys_counter
10520 12:21:45.724490 <5>[ 0.653062] VFS: Disk quotas dquot_6.6.0
10521 12:21:45.730511 <6>[ 0.657247] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10522 12:21:45.733685 <6>[ 0.664432] pnp: PnP ACPI: disabled
10523 12:21:45.742444 <6>[ 0.671083] NET: Registered PF_INET protocol family
10524 12:21:45.752404 <6>[ 0.676671] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10525 12:21:45.764152 <6>[ 0.688993] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10526 12:21:45.773986 <6>[ 0.697809] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10527 12:21:45.779977 <6>[ 0.705782] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10528 12:21:45.789845 <6>[ 0.714487] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10529 12:21:45.796578 <6>[ 0.724241] TCP: Hash tables configured (established 65536 bind 65536)
10530 12:21:45.802627 <6>[ 0.731103] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10531 12:21:45.813275 <6>[ 0.738301] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10532 12:21:45.819502 <6>[ 0.746005] NET: Registered PF_UNIX/PF_LOCAL protocol family
10533 12:21:45.826068 <6>[ 0.752158] RPC: Registered named UNIX socket transport module.
10534 12:21:45.829870 <6>[ 0.758315] RPC: Registered udp transport module.
10535 12:21:45.836197 <6>[ 0.763249] RPC: Registered tcp transport module.
10536 12:21:45.843270 <6>[ 0.768179] RPC: Registered tcp NFSv4.1 backchannel transport module.
10537 12:21:45.845616 <6>[ 0.774845] PCI: CLS 0 bytes, default 64
10538 12:21:45.848650 <6>[ 0.779218] Unpacking initramfs...
10539 12:21:45.858967 <6>[ 0.783277] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10540 12:21:45.865169 <6>[ 0.791911] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10541 12:21:45.872703 <6>[ 0.800761] kvm [1]: IPA Size Limit: 40 bits
10542 12:21:45.875188 <6>[ 0.805292] kvm [1]: GICv3: no GICV resource entry
10543 12:21:45.882243 <6>[ 0.810315] kvm [1]: disabling GICv2 emulation
10544 12:21:45.888703 <6>[ 0.815001] kvm [1]: GIC system register CPU interface enabled
10545 12:21:45.891826 <6>[ 0.821174] kvm [1]: vgic interrupt IRQ18
10546 12:21:45.898692 <6>[ 0.826667] kvm [1]: VHE mode initialized successfully
10547 12:21:45.905033 <5>[ 0.833055] Initialise system trusted keyrings
10548 12:21:45.911522 <6>[ 0.837865] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10549 12:21:45.919603 <6>[ 0.847803] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10550 12:21:45.925844 <5>[ 0.854214] NFS: Registering the id_resolver key type
10551 12:21:45.928910 <5>[ 0.859511] Key type id_resolver registered
10552 12:21:45.935826 <5>[ 0.863925] Key type id_legacy registered
10553 12:21:45.942680 <6>[ 0.868202] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10554 12:21:45.949022 <6>[ 0.875125] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10555 12:21:45.955610 <6>[ 0.882848] 9p: Installing v9fs 9p2000 file system support
10556 12:21:45.992785 <5>[ 0.920840] Key type asymmetric registered
10557 12:21:45.995730 <5>[ 0.925171] Asymmetric key parser 'x509' registered
10558 12:21:46.005690 <6>[ 0.930322] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10559 12:21:46.008778 <6>[ 0.937937] io scheduler mq-deadline registered
10560 12:21:46.012122 <6>[ 0.942699] io scheduler kyber registered
10561 12:21:46.031441 <6>[ 0.959727] EINJ: ACPI disabled.
10562 12:21:46.064185 <4>[ 0.985711] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10563 12:21:46.073393 <4>[ 0.996339] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10564 12:21:46.088853 <6>[ 1.017013] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10565 12:21:46.096419 <6>[ 1.024974] printk: console [ttyS0] disabled
10566 12:21:46.124993 <6>[ 1.049622] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10567 12:21:46.131162 <6>[ 1.059094] printk: console [ttyS0] enabled
10568 12:21:46.134672 <6>[ 1.059094] printk: console [ttyS0] enabled
10569 12:21:46.141173 <6>[ 1.067990] printk: bootconsole [mtk8250] disabled
10570 12:21:46.144312 <6>[ 1.067990] printk: bootconsole [mtk8250] disabled
10571 12:21:46.151299 <6>[ 1.079042] SuperH (H)SCI(F) driver initialized
10572 12:21:46.153939 <6>[ 1.084307] msm_serial: driver initialized
10573 12:21:46.168186 <6>[ 1.093234] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10574 12:21:46.178164 <6>[ 1.101780] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10575 12:21:46.184863 <6>[ 1.110321] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10576 12:21:46.194517 <6>[ 1.118951] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10577 12:21:46.204586 <6>[ 1.127657] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10578 12:21:46.210695 <6>[ 1.136369] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10579 12:21:46.220426 <6>[ 1.144908] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10580 12:21:46.227572 <6>[ 1.153704] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10581 12:21:46.237285 <6>[ 1.162249] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10582 12:21:46.249458 <6>[ 1.177561] loop: module loaded
10583 12:21:46.255422 <6>[ 1.183600] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10584 12:21:46.278011 <4>[ 1.206704] mtk-pmic-keys: Failed to locate of_node [id: -1]
10585 12:21:46.284837 <6>[ 1.213455] megasas: 07.719.03.00-rc1
10586 12:21:46.294943 <6>[ 1.222918] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10587 12:21:46.305779 <6>[ 1.234005] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10588 12:21:46.321961 <6>[ 1.250534] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10589 12:21:46.382108 <6>[ 1.304356] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10590 12:21:46.591736 <6>[ 1.519818] Freeing initrd memory: 17348K
10591 12:21:46.601434 <6>[ 1.529947] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10592 12:21:46.612516 <6>[ 1.540756] tun: Universal TUN/TAP device driver, 1.6
10593 12:21:46.615648 <6>[ 1.546823] thunder_xcv, ver 1.0
10594 12:21:46.618973 <6>[ 1.550320] thunder_bgx, ver 1.0
10595 12:21:46.622031 <6>[ 1.553816] nicpf, ver 1.0
10596 12:21:46.632607 <6>[ 1.557830] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10597 12:21:46.636134 <6>[ 1.565307] hns3: Copyright (c) 2017 Huawei Corporation.
10598 12:21:46.642760 <6>[ 1.570892] hclge is initializing
10599 12:21:46.645901 <6>[ 1.574466] e1000: Intel(R) PRO/1000 Network Driver
10600 12:21:46.652699 <6>[ 1.579596] e1000: Copyright (c) 1999-2006 Intel Corporation.
10601 12:21:46.656161 <6>[ 1.585608] e1000e: Intel(R) PRO/1000 Network Driver
10602 12:21:46.662804 <6>[ 1.590824] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10603 12:21:46.669022 <6>[ 1.597008] igb: Intel(R) Gigabit Ethernet Network Driver
10604 12:21:46.676056 <6>[ 1.602658] igb: Copyright (c) 2007-2014 Intel Corporation.
10605 12:21:46.682244 <6>[ 1.608497] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10606 12:21:46.689129 <6>[ 1.615015] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10607 12:21:46.692301 <6>[ 1.621484] sky2: driver version 1.30
10608 12:21:46.698909 <6>[ 1.626480] VFIO - User Level meta-driver version: 0.3
10609 12:21:46.706225 <6>[ 1.634731] usbcore: registered new interface driver usb-storage
10610 12:21:46.712907 <6>[ 1.641175] usbcore: registered new device driver onboard-usb-hub
10611 12:21:46.721585 <6>[ 1.650287] mt6397-rtc mt6359-rtc: registered as rtc0
10612 12:21:46.731730 <6>[ 1.655753] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-16T12:21:46 UTC (1692188506)
10613 12:21:46.735196 <6>[ 1.665317] i2c_dev: i2c /dev entries driver
10614 12:21:46.751942 <6>[ 1.676988] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10615 12:21:46.772550 <6>[ 1.701000] cpu cpu0: EM: created perf domain
10616 12:21:46.775999 <6>[ 1.706022] cpu cpu4: EM: created perf domain
10617 12:21:46.783134 <6>[ 1.711646] sdhci: Secure Digital Host Controller Interface driver
10618 12:21:46.790211 <6>[ 1.718082] sdhci: Copyright(c) Pierre Ossman
10619 12:21:46.796943 <6>[ 1.723038] Synopsys Designware Multimedia Card Interface Driver
10620 12:21:46.803296 <6>[ 1.729667] sdhci-pltfm: SDHCI platform and OF driver helper
10621 12:21:46.806846 <6>[ 1.729710] mmc0: CQHCI version 5.10
10622 12:21:46.813178 <6>[ 1.739873] ledtrig-cpu: registered to indicate activity on CPUs
10623 12:21:46.820124 <6>[ 1.747052] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10624 12:21:46.826985 <6>[ 1.754112] usbcore: registered new interface driver usbhid
10625 12:21:46.830258 <6>[ 1.759934] usbhid: USB HID core driver
10626 12:21:46.836392 <6>[ 1.764131] spi_master spi0: will run message pump with realtime priority
10627 12:21:46.882762 <6>[ 1.804352] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10628 12:21:46.902398 <6>[ 1.820584] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10629 12:21:46.905940 <6>[ 1.834151] mmc0: Command Queue Engine enabled
10630 12:21:46.912313 <6>[ 1.838913] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10631 12:21:46.919127 <6>[ 1.846069] cros-ec-spi spi0.0: Chrome EC device registered
10632 12:21:46.922092 <6>[ 1.846404] mmcblk0: mmc0:0001 DA4128 116 GiB
10633 12:21:46.935735 <6>[ 1.863951] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10634 12:21:46.943286 <6>[ 1.871590] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10635 12:21:46.953564 <6>[ 1.876644] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10636 12:21:46.956215 <6>[ 1.877629] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10637 12:21:46.963268 <6>[ 1.887425] NET: Registered PF_PACKET protocol family
10638 12:21:46.969743 <6>[ 1.892218] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10639 12:21:46.973673 <6>[ 1.896750] 9pnet: Installing 9P2000 support
10640 12:21:46.979771 <5>[ 1.907789] Key type dns_resolver registered
10641 12:21:46.982572 <6>[ 1.912886] registered taskstats version 1
10642 12:21:46.989714 <5>[ 1.917293] Loading compiled-in X.509 certificates
10643 12:21:47.018167 <4>[ 1.939669] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10644 12:21:47.027953 <4>[ 1.950393] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10645 12:21:47.034588 <3>[ 1.960946] debugfs: File 'uA_load' in directory '/' already present!
10646 12:21:47.041508 <3>[ 1.967721] debugfs: File 'min_uV' in directory '/' already present!
10647 12:21:47.048082 <3>[ 1.974341] debugfs: File 'max_uV' in directory '/' already present!
10648 12:21:47.054319 <3>[ 1.980954] debugfs: File 'constraint_flags' in directory '/' already present!
10649 12:21:47.065435 <3>[ 1.990422] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10650 12:21:47.074976 <6>[ 2.003342] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10651 12:21:47.082016 <6>[ 2.010266] xhci-mtk 11200000.usb: xHCI Host Controller
10652 12:21:47.088797 <6>[ 2.015777] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10653 12:21:47.098698 <6>[ 2.023617] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10654 12:21:47.104968 <6>[ 2.033037] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10655 12:21:47.111544 <6>[ 2.039098] xhci-mtk 11200000.usb: xHCI Host Controller
10656 12:21:47.118390 <6>[ 2.044574] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10657 12:21:47.124920 <6>[ 2.052219] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10658 12:21:47.132052 <6>[ 2.060092] hub 1-0:1.0: USB hub found
10659 12:21:47.135241 <6>[ 2.064135] hub 1-0:1.0: 1 port detected
10660 12:21:47.144677 <6>[ 2.068409] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10661 12:21:47.148570 <6>[ 2.077188] hub 2-0:1.0: USB hub found
10662 12:21:47.151204 <6>[ 2.081232] hub 2-0:1.0: 1 port detected
10663 12:21:47.160930 <6>[ 2.089510] mtk-msdc 11f70000.mmc: Got CD GPIO
10664 12:21:47.171048 <6>[ 2.096019] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10665 12:21:47.178230 <6>[ 2.104040] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10666 12:21:47.187568 <4>[ 2.111933] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10667 12:21:47.197513 <6>[ 2.121461] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10668 12:21:47.203942 <6>[ 2.129540] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10669 12:21:47.210519 <6>[ 2.137540] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10670 12:21:47.220403 <6>[ 2.145460] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10671 12:21:47.227041 <6>[ 2.153278] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10672 12:21:47.237130 <6>[ 2.161094] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10673 12:21:47.247180 <6>[ 2.171613] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10674 12:21:47.253921 <6>[ 2.179996] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10675 12:21:47.264381 <6>[ 2.188344] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10676 12:21:47.270695 <6>[ 2.196683] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10677 12:21:47.281001 <6>[ 2.205021] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10678 12:21:47.286616 <6>[ 2.213359] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10679 12:21:47.296822 <6>[ 2.221696] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10680 12:21:47.303347 <6>[ 2.230035] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10681 12:21:47.313182 <6>[ 2.238372] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10682 12:21:47.319898 <6>[ 2.246710] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10683 12:21:47.330538 <6>[ 2.255067] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10684 12:21:47.339772 <6>[ 2.263405] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10685 12:21:47.346511 <6>[ 2.271744] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10686 12:21:47.356321 <6>[ 2.280082] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10687 12:21:47.363122 <6>[ 2.288419] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10688 12:21:47.369666 <6>[ 2.297161] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10689 12:21:47.377112 <6>[ 2.304300] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10690 12:21:47.382694 <6>[ 2.311064] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10691 12:21:47.389413 <6>[ 2.317823] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10692 12:21:47.399387 <6>[ 2.324753] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10693 12:21:47.406049 <6>[ 2.331605] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10694 12:21:47.416291 <6>[ 2.340735] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10695 12:21:47.425752 <6>[ 2.349855] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10696 12:21:47.435830 <6>[ 2.359151] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10697 12:21:47.445721 <6>[ 2.368621] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10698 12:21:47.452504 <6>[ 2.378088] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10699 12:21:47.462385 <6>[ 2.387208] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10700 12:21:47.471861 <6>[ 2.396675] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10701 12:21:47.482420 <6>[ 2.405794] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10702 12:21:47.492029 <6>[ 2.415089] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10703 12:21:47.501819 <6>[ 2.425249] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10704 12:21:47.511499 <6>[ 2.436485] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10705 12:21:47.517690 <6>[ 2.446014] Trying to probe devices needed for running init ...
10706 12:21:47.565347 <6>[ 2.490903] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10707 12:21:47.720488 <6>[ 2.648972] hub 1-1:1.0: USB hub found
10708 12:21:47.723492 <6>[ 2.653482] hub 1-1:1.0: 4 ports detected
10709 12:21:47.845538 <6>[ 2.771068] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10710 12:21:47.871288 <6>[ 2.800195] hub 2-1:1.0: USB hub found
10711 12:21:47.875181 <6>[ 2.804662] hub 2-1:1.0: 3 ports detected
10712 12:21:48.045339 <6>[ 2.970960] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10713 12:21:48.176696 <6>[ 3.105074] hub 1-1.1:1.0: USB hub found
10714 12:21:48.179900 <6>[ 3.109512] hub 1-1.1:1.0: 4 ports detected
10715 12:21:48.293558 <6>[ 3.218937] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10716 12:21:48.426758 <6>[ 3.354858] hub 1-1.4:1.0: USB hub found
10717 12:21:48.429540 <6>[ 3.359499] hub 1-1.4:1.0: 2 ports detected
10718 12:21:48.506209 <6>[ 3.430955] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10719 12:21:48.693695 <6>[ 3.618918] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10720 12:21:48.778310 <3>[ 3.707078] usb 1-1.1.4: device descriptor read/64, error -32
10721 12:21:48.970348 <3>[ 3.899131] usb 1-1.1.4: device descriptor read/64, error -32
10722 12:21:49.165513 <6>[ 4.090886] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10723 12:21:49.354003 <6>[ 4.278888] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10724 12:21:49.438438 <3>[ 4.367080] usb 1-1.1.4: device descriptor read/64, error -32
10725 12:21:49.630304 <3>[ 4.559104] usb 1-1.1.4: device descriptor read/64, error -32
10726 12:21:49.742674 <6>[ 4.671424] usb 1-1.1-port4: attempt power cycle
10727 12:21:49.829480 <6>[ 4.754930] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10728 12:21:50.353139 <6>[ 5.278930] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10729 12:21:50.359528 <4>[ 5.286340] usb 1-1.1.4: Device not responding to setup address.
10730 12:21:50.570699 <4>[ 5.499136] usb 1-1.1.4: Device not responding to setup address.
10731 12:21:50.782319 <3>[ 5.710999] usb 1-1.1.4: device not accepting address 10, error -71
10732 12:21:50.869861 <6>[ 5.794946] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10733 12:21:50.875870 <4>[ 5.802353] usb 1-1.1.4: Device not responding to setup address.
10734 12:21:51.086334 <4>[ 6.015213] usb 1-1.1.4: Device not responding to setup address.
10735 12:21:51.298203 <3>[ 6.226935] usb 1-1.1.4: device not accepting address 11, error -71
10736 12:21:51.305022 <3>[ 6.233969] usb 1-1.1-port4: unable to enumerate USB device
10737 12:21:59.803134 <6>[ 14.735915] ALSA device list:
10738 12:21:59.809649 <6>[ 14.739211] No soundcards found.
10739 12:21:59.817452 <6>[ 14.747187] Freeing unused kernel memory: 8384K
10740 12:21:59.820619 <6>[ 14.752269] Run /init as init process
10741 12:21:59.832273 Loading, please wait...
10742 12:21:59.852734 Starting version 247.3-7+deb11u2
10743 12:22:00.062158 <6>[ 14.988506] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10744 12:22:00.071682 <6>[ 14.996894] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10745 12:22:00.078805 <6>[ 15.005636] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10746 12:22:00.088537 <3>[ 15.006673] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10747 12:22:00.094888 <6>[ 15.009305] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10748 12:22:00.102025 <6>[ 15.022272] remoteproc remoteproc0: scp is available
10749 12:22:00.108336 <3>[ 15.022507] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10750 12:22:00.115216 <6>[ 15.023620] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10751 12:22:00.121396 <6>[ 15.031606] remoteproc remoteproc0: powering up scp
10752 12:22:00.127976 <3>[ 15.035041] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10753 12:22:00.138834 <6>[ 15.043116] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10754 12:22:00.145211 <6>[ 15.043125] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10755 12:22:00.151013 <4>[ 15.052238] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10756 12:22:00.157994 <4>[ 15.052238] Fallback method does not support PEC.
10757 12:22:00.164522 <3>[ 15.071257] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10758 12:22:00.171029 <6>[ 15.071988] mc: Linux media interface: v0.10
10759 12:22:00.177439 <4>[ 15.082424] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10760 12:22:00.184306 <3>[ 15.091934] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10761 12:22:00.191014 <6>[ 15.094643] usbcore: registered new interface driver r8152
10762 12:22:00.197238 <4>[ 15.100222] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10763 12:22:00.207062 <3>[ 15.104515] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10764 12:22:00.213879 <6>[ 15.136215] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10765 12:22:00.224096 <6>[ 15.139262] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10766 12:22:00.234428 <6>[ 15.139588] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10767 12:22:00.241712 <3>[ 15.140997] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10768 12:22:00.244103 <6>[ 15.147853] pci_bus 0000:00: root bus resource [bus 00-ff]
10769 12:22:00.254107 <3>[ 15.158079] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10770 12:22:00.261336 <6>[ 15.167038] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10771 12:22:00.271247 <3>[ 15.173332] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10772 12:22:00.277877 <3>[ 15.175196] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10773 12:22:00.288615 <6>[ 15.180844] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10774 12:22:00.294693 <6>[ 15.181599] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10775 12:22:00.304520 <6>[ 15.188933] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10776 12:22:00.311363 <3>[ 15.189469] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10777 12:22:00.320841 <3>[ 15.189474] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 12:22:00.327402 <3>[ 15.189478] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 12:22:00.337513 <3>[ 15.189513] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 12:22:00.344363 <3>[ 15.189516] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10781 12:22:00.350564 <3>[ 15.189519] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10782 12:22:00.360411 <3>[ 15.189523] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10783 12:22:00.367263 <3>[ 15.189534] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10784 12:22:00.376980 <3>[ 15.189546] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10785 12:22:00.383565 <6>[ 15.196075] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10786 12:22:00.390570 <6>[ 15.204847] remoteproc remoteproc0: remote processor scp is now up
10787 12:22:00.396900 <3>[ 15.209183] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10788 12:22:00.407015 <6>[ 15.212903] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10789 12:22:00.413416 <6>[ 15.218333] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10790 12:22:00.422699 <6>[ 15.222988] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10791 12:22:00.426130 <6>[ 15.229907] pci 0000:00:00.0: supports D1 D2
10792 12:22:00.432834 <6>[ 15.230521] videodev: Linux video capture interface: v2.00
10793 12:22:00.439412 <6>[ 15.233342] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10794 12:22:00.449713 <6>[ 15.235584] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10795 12:22:00.455612 <6>[ 15.246976] usbcore: registered new interface driver cdc_ether
10796 12:22:00.462720 <6>[ 15.254527] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10797 12:22:00.465836 <6>[ 15.255399] Bluetooth: Core ver 2.22
10798 12:22:00.472464 <6>[ 15.255522] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10799 12:22:00.480312 <6>[ 15.255616] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10800 12:22:00.485353 <6>[ 15.255641] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10801 12:22:00.495860 <6>[ 15.255658] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10802 12:22:00.502479 <6>[ 15.255673] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10803 12:22:00.505726 <6>[ 15.255778] pci 0000:01:00.0: supports D1 D2
10804 12:22:00.512509 <6>[ 15.255779] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10805 12:22:00.522168 <6>[ 15.266783] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10806 12:22:00.525219 <6>[ 15.270821] NET: Registered PF_BLUETOOTH protocol family
10807 12:22:00.532281 <6>[ 15.270977] usbcore: registered new interface driver r8153_ecm
10808 12:22:00.542271 <6>[ 15.278824] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10809 12:22:00.548070 <6>[ 15.286876] Bluetooth: HCI device and connection manager initialized
10810 12:22:00.554674 <6>[ 15.288086] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10811 12:22:00.564528 <6>[ 15.289475] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10812 12:22:00.571852 <6>[ 15.289565] usbcore: registered new interface driver uvcvideo
10813 12:22:00.581676 <6>[ 15.294951] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10814 12:22:00.585480 <6>[ 15.303042] Bluetooth: HCI socket layer initialized
10815 12:22:00.594235 <6>[ 15.311115] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10816 12:22:00.600899 <6>[ 15.311858] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10817 12:22:00.603911 <6>[ 15.317360] Bluetooth: L2CAP socket layer initialized
10818 12:22:00.613994 <6>[ 15.323797] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10819 12:22:00.617369 <6>[ 15.332562] Bluetooth: SCO socket layer initialized
10820 12:22:00.627298 <6>[ 15.340034] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10821 12:22:00.634811 <4>[ 15.399199] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10822 12:22:00.640834 <6>[ 15.400153] pci 0000:00:00.0: PCI bridge to [bus 01]
10823 12:22:00.647255 <4>[ 15.408395] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10824 12:22:00.653926 <6>[ 15.408803] usbcore: registered new interface driver btusb
10825 12:22:00.663778 <4>[ 15.409668] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10826 12:22:00.670758 <3>[ 15.409672] Bluetooth: hci0: Failed to load firmware file (-2)
10827 12:22:00.677227 <3>[ 15.409674] Bluetooth: hci0: Failed to set up firmware (-2)
10828 12:22:00.686759 <4>[ 15.409676] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10829 12:22:00.696431 <6>[ 15.414647] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10830 12:22:00.703564 <6>[ 15.414876] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10831 12:22:00.706421 <6>[ 15.474959] r8152 1-1.1.1:1.0 eth0: v1.12.13
10832 12:22:00.713156 <6>[ 15.475467] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10833 12:22:00.719851 <6>[ 15.491082] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10834 12:22:00.723061 <6>[ 15.501563] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10835 12:22:00.758081 <5>[ 15.685048] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10836 12:22:00.775348 <5>[ 15.702044] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10837 12:22:00.782096 <4>[ 15.708961] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10838 12:22:00.788823 <6>[ 15.717852] cfg80211: failed to load regulatory.db
10839 12:22:00.848420 <6>[ 15.775304] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10840 12:22:00.855199 <6>[ 15.782854] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10841 12:22:00.876746 <6>[ 15.806824] mt7921e 0000:01:00.0: ASIC revision: 79610010
10842 12:22:00.983674 <4>[ 15.906893] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10843 12:22:00.991480 Begin: Loading essential drivers ... done.
10844 12:22:00.994441 Begin: Running /scripts/init-premount ... done.
10845 12:22:01.001360 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10846 12:22:01.011710 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10847 12:22:01.015516 Device /sys/class/net/enxf4f5e850de0a found
10848 12:22:01.016073 done.
10849 12:22:01.059858 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10850 12:22:01.103371 <4>[ 16.026592] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10851 12:22:01.223110 <4>[ 16.146563] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10852 12:22:01.343135 <4>[ 16.266339] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10853 12:22:01.463145 <4>[ 16.386349] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10854 12:22:01.583063 <4>[ 16.506323] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10855 12:22:01.702965 <4>[ 16.626392] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10856 12:22:01.822737 <4>[ 16.746233] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10857 12:22:01.942750 <4>[ 16.866248] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10858 12:22:02.062718 <4>[ 16.986185] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10859 12:22:02.173687 <3>[ 17.104121] mt7921e 0000:01:00.0: hardware init failed
10860 12:22:02.207244 <6>[ 17.137315] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10861 12:22:02.225697 IP-Config: no response after 2 secs - giving up
10862 12:22:02.263945 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10863 12:22:02.270687 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10864 12:22:02.277739 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10865 12:22:02.283633 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10866 12:22:02.290754 host : mt8192-asurada-spherion-r0-cbg-9
10867 12:22:02.297062 domain : lava-rack
10868 12:22:02.300126 rootserver: 192.168.201.1 rootpath:
10869 12:22:02.300966 filename :
10870 12:22:02.365960 done.
10871 12:22:02.371991 Begin: Running /scripts/nfs-bottom ... done.
10872 12:22:02.386348 Begin: Running /scripts/init-bottom ... done.
10873 12:22:03.577744 <6>[ 18.507879] NET: Registered PF_INET6 protocol family
10874 12:22:03.584793 <6>[ 18.515094] Segment Routing with IPv6
10875 12:22:03.587647 <6>[ 18.519111] In-situ OAM (IOAM) with IPv6
10876 12:22:03.711250 <30>[ 18.621462] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10877 12:22:03.714221 <30>[ 18.645864] systemd[1]: Detected architecture arm64.
10878 12:22:03.735414
10879 12:22:03.738569 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10880 12:22:03.739037
10881 12:22:03.754627 <30>[ 18.685388] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10882 12:22:04.642560 <30>[ 19.569598] systemd[1]: Queued start job for default target Graphical Interface.
10883 12:22:04.675111 <30>[ 19.605361] systemd[1]: Created slice system-getty.slice.
10884 12:22:04.681468 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10885 12:22:04.698036 <30>[ 19.628360] systemd[1]: Created slice system-modprobe.slice.
10886 12:22:04.704771 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10887 12:22:04.721748 <30>[ 19.652144] systemd[1]: Created slice system-serial\x2dgetty.slice.
10888 12:22:04.731753 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10889 12:22:04.745866 <30>[ 19.675987] systemd[1]: Created slice User and Session Slice.
10890 12:22:04.752175 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10891 12:22:04.772583 <30>[ 19.699783] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10892 12:22:04.782867 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10893 12:22:04.800818 <30>[ 19.727581] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10894 12:22:04.806911 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10895 12:22:04.831468 <30>[ 19.755503] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10896 12:22:04.838633 <30>[ 19.767780] systemd[1]: Reached target Local Encrypted Volumes.
10897 12:22:04.844733 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10898 12:22:04.861047 <30>[ 19.791374] systemd[1]: Reached target Paths.
10899 12:22:04.867548 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10900 12:22:04.880442 <30>[ 19.810909] systemd[1]: Reached target Remote File Systems.
10901 12:22:04.886780 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10902 12:22:04.905083 <30>[ 19.835278] systemd[1]: Reached target Slices.
10903 12:22:04.911434 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10904 12:22:04.924481 <30>[ 19.854939] systemd[1]: Reached target Swap.
10905 12:22:04.927822 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10906 12:22:04.948002 <30>[ 19.875396] systemd[1]: Listening on initctl Compatibility Named Pipe.
10907 12:22:04.955237 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10908 12:22:04.962156 <30>[ 19.891666] systemd[1]: Listening on Journal Audit Socket.
10909 12:22:04.967900 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10910 12:22:04.985823 <30>[ 19.916354] systemd[1]: Listening on Journal Socket (/dev/log).
10911 12:22:04.992278 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10912 12:22:05.009104 <30>[ 19.939497] systemd[1]: Listening on Journal Socket.
10913 12:22:05.015375 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10914 12:22:05.033341 <30>[ 19.960551] systemd[1]: Listening on Network Service Netlink Socket.
10915 12:22:05.040060 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10916 12:22:05.055402 <30>[ 19.986040] systemd[1]: Listening on udev Control Socket.
10917 12:22:05.062121 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10918 12:22:05.076932 <30>[ 20.007357] systemd[1]: Listening on udev Kernel Socket.
10919 12:22:05.084003 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10920 12:22:05.132979 <30>[ 20.063336] systemd[1]: Mounting Huge Pages File System...
10921 12:22:05.139782 Mounting [0;1;39mHuge Pages File System[0m...
10922 12:22:05.154789 <30>[ 20.085314] systemd[1]: Mounting POSIX Message Queue File System...
10923 12:22:05.161544 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10924 12:22:05.204582 <30>[ 20.135449] systemd[1]: Mounting Kernel Debug File System...
10925 12:22:05.211624 Mounting [0;1;39mKernel Debug File System[0m...
10926 12:22:05.227695 <30>[ 20.155480] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10927 12:22:05.242317 <30>[ 20.169395] systemd[1]: Starting Create list of static device nodes for the current kernel...
10928 12:22:05.249019 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10929 12:22:05.269172 <30>[ 20.199902] systemd[1]: Starting Load Kernel Module configfs...
10930 12:22:05.275707 Starting [0;1;39mLoad Kernel Module configfs[0m...
10931 12:22:05.293055 <30>[ 20.223717] systemd[1]: Starting Load Kernel Module drm...
10932 12:22:05.299690 Starting [0;1;39mLoad Kernel Module drm[0m...
10933 12:22:05.317507 <30>[ 20.247852] systemd[1]: Starting Load Kernel Module fuse...
10934 12:22:05.323803 Starting [0;1;39mLoad Kernel Module fuse[0m...
10935 12:22:05.346523 <30>[ 20.273928] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10936 12:22:05.361231 <6>[ 20.292218] fuse: init (API version 7.37)
10937 12:22:05.381237 <30>[ 20.311814] systemd[1]: Starting Journal Service...
10938 12:22:05.387651 Starting [0;1;39mJournal Service[0m...
10939 12:22:05.411931 <30>[ 20.342439] systemd[1]: Starting Load Kernel Modules...
10940 12:22:05.418345 Starting [0;1;39mLoad Kernel Modules[0m...
10941 12:22:05.441019 <30>[ 20.368283] systemd[1]: Starting Remount Root and Kernel File Systems...
10942 12:22:05.447649 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10943 12:22:05.466326 <30>[ 20.397181] systemd[1]: Starting Coldplug All udev Devices...
10944 12:22:05.473554 Starting [0;1;39mColdplug All udev Devices[0m...
10945 12:22:05.495990 <30>[ 20.426428] systemd[1]: Mounted Huge Pages File System.
10946 12:22:05.502524 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10947 12:22:05.518992 <3>[ 20.446283] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 12:22:05.525357 <30>[ 20.455960] systemd[1]: Mounted POSIX Message Queue File System.
10949 12:22:05.531708 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10950 12:22:05.548134 <30>[ 20.479157] systemd[1]: Mounted Kernel Debug File System.
10951 12:22:05.558456 <3>[ 20.479812] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 12:22:05.565173 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10953 12:22:05.584842 <30>[ 20.511650] systemd[1]: Finished Create list of static device nodes for the current kernel.
10954 12:22:05.594113 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10955 12:22:05.607432 <3>[ 20.534768] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 12:22:05.613665 <30>[ 20.544657] systemd[1]: modprobe@configfs.service: Succeeded.
10957 12:22:05.620838 <30>[ 20.551625] systemd[1]: Finished Load Kernel Module configfs.
10958 12:22:05.627513 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10959 12:22:05.640114 <3>[ 20.567268] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 12:22:05.647231 <30>[ 20.577627] systemd[1]: modprobe@drm.service: Succeeded.
10961 12:22:05.653691 <30>[ 20.584272] systemd[1]: Finished Load Kernel Module drm.
10962 12:22:05.660519 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10963 12:22:05.674408 <3>[ 20.601717] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 12:22:05.681990 <30>[ 20.612373] systemd[1]: modprobe@fuse.service: Succeeded.
10965 12:22:05.689089 <30>[ 20.619720] systemd[1]: Finished Load Kernel Module fuse.
10966 12:22:05.695972 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10967 12:22:05.707993 <3>[ 20.634878] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10968 12:22:05.715712 <30>[ 20.646227] systemd[1]: Finished Load Kernel Modules.
10969 12:22:05.722530 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10970 12:22:05.740600 <3>[ 20.667195] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 12:22:05.747104 <30>[ 20.668730] systemd[1]: Finished Remount Root and Kernel File Systems.
10972 12:22:05.753626 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10973 12:22:05.769826 <3>[ 20.696298] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 12:22:05.799745 <3>[ 20.726656] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 12:22:05.817254 <30>[ 20.747522] systemd[1]: Mounting FUSE Control File System...
10976 12:22:05.830633 Mounting [0;1;39mFUSE Control File Sys<3>[ 20.757223] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10977 12:22:05.831172 tem[0m...
10978 12:22:05.851052 <30>[ 20.781570] systemd[1]: Mounting Kernel Configuration File System...
10979 12:22:05.858663 Mounting [0;1;39mKernel Configuration File System[0m...
10980 12:22:05.883784 <30>[ 20.811052] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10981 12:22:05.893439 <30>[ 20.820160] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10982 12:22:05.925216 <30>[ 20.855818] systemd[1]: Starting Load/Save Random Seed...
10983 12:22:05.931567 Starting [0;1;39mLoad/Save Random Seed[0m...
10984 12:22:05.958266 <4>[ 20.878775] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10985 12:22:05.964611 <30>[ 20.884023] systemd[1]: Starting Apply Kernel Variables...
10986 12:22:05.971838 <3>[ 20.894962] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10987 12:22:05.977665 Starting [0;1;39mApply Kernel Variables[0m...
10988 12:22:06.029125 <30>[ 20.959644] systemd[1]: Starting Create System Users...
10989 12:22:06.035721 Starting [0;1;39mCreate System Users[0m...
10990 12:22:06.054071 <30>[ 20.984579] systemd[1]: Started Journal Service.
10991 12:22:06.060925 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10992 12:22:06.079805 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10993 12:22:06.092680 See 'systemctl status systemd-udev-trigger.service' for details.
10994 12:22:06.109199 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10995 12:22:06.124310 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10996 12:22:06.141259 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10997 12:22:06.158140 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10998 12:22:06.174047 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10999 12:22:06.225102 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11000 12:22:06.246039 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11001 12:22:06.266421 <46>[ 21.193996] systemd-journald[294]: Received client request to flush runtime journal.
11002 12:22:07.342769 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11003 12:22:07.356530 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11004 12:22:07.372045 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11005 12:22:07.429183 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11006 12:22:07.665146 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11007 12:22:07.717332 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11008 12:22:07.794400 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11009 12:22:07.837615 Starting [0;1;39mNetwork Service[0m...
11010 12:22:08.148188 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11011 12:22:08.168021 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11012 12:22:08.231546 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11013 12:22:08.437940 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11014 12:22:08.455362 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11015 12:22:08.500369 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11016 12:22:08.541570 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11017 12:22:08.566457 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11018 12:22:08.581123 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11019 12:22:08.596446 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
11020 12:22:08.664896 Starting [0;1;39mNetwork Name Resolution[0m...
11021 12:22:08.695126 Starting [0;1;39mNetwork Time Synchronization[0m...
11022 12:22:08.713176 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11023 12:22:08.771176 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11024 12:22:08.921048 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11025 12:22:08.936897 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11026 12:22:08.955438 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11027 12:22:08.968204 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11028 12:22:08.983926 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11029 12:22:09.119216 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11030 12:22:09.149867 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11031 12:22:09.180792 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11032 12:22:09.205807 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11033 12:22:09.219875 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11034 12:22:09.251208 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11035 12:22:09.263389 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11036 12:22:09.279188 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11037 12:22:09.326720 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11038 12:22:09.377311 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11039 12:22:09.482102 Starting [0;1;39mUser Login Management[0m...
11040 12:22:09.493896 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11041 12:22:09.509339 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11042 12:22:09.526625 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11043 12:22:09.586261 Starting [0;1;39mPermit User Sessions[0m...
11044 12:22:09.701414 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11045 12:22:09.722397 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11046 12:22:09.763934 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11047 12:22:09.782959 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11048 12:22:09.805512 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11049 12:22:09.823143 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11050 12:22:09.842850 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11051 12:22:09.860373 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11052 12:22:09.915737 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11053 12:22:09.957591 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11054 12:22:10.036845
11055 12:22:10.037330
11056 12:22:10.039871 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11057 12:22:10.040294
11058 12:22:10.043111 debian-bullseye-arm64 login: root (automatic login)
11059 12:22:10.043542
11060 12:22:10.043875
11061 12:22:10.335819 Linux debian-bullseye-arm64 6.1.45-cip3 #1 SMP PREEMPT Wed Aug 16 12:04:53 UTC 2023 aarch64
11062 12:22:10.336308
11063 12:22:10.342460 The programs included with the Debian GNU/Linux system are free software;
11064 12:22:10.349211 the exact distribution terms for each program are described in the
11065 12:22:10.352784 individual files in /usr/share/doc/*/copyright.
11066 12:22:10.353205
11067 12:22:10.359175 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11068 12:22:10.362424 permitted by applicable law.
11069 12:22:10.453557 Matched prompt #10: / #
11071 12:22:10.454728 Setting prompt string to ['/ #']
11072 12:22:10.455167 end: 2.2.5.1 login-action (duration 00:00:26) [common]
11074 12:22:10.456384 end: 2.2.5 auto-login-action (duration 00:00:26) [common]
11075 12:22:10.456847 start: 2.2.6 expect-shell-connection (timeout 00:03:38) [common]
11076 12:22:10.457210 Setting prompt string to ['/ #']
11077 12:22:10.457519 Forcing a shell prompt, looking for ['/ #']
11079 12:22:10.508313 / #
11080 12:22:10.508950 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11081 12:22:10.509409 Waiting using forced prompt support (timeout 00:02:30)
11082 12:22:10.514712
11083 12:22:10.515583 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11084 12:22:10.516152 start: 2.2.7 export-device-env (timeout 00:03:38) [common]
11086 12:22:10.617479 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11299297/extract-nfsrootfs-oufad8j8'
11087 12:22:10.624547 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11299297/extract-nfsrootfs-oufad8j8'
11089 12:22:10.726320 / # export NFS_SERVER_IP='192.168.201.1'
11090 12:22:10.733314 export NFS_SERVER_IP='192.168.201.1'
11091 12:22:10.734250 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11092 12:22:10.734819 end: 2.2 depthcharge-retry (duration 00:01:22) [common]
11093 12:22:10.735308 end: 2 depthcharge-action (duration 00:01:22) [common]
11094 12:22:10.735804 start: 3 lava-test-retry (timeout 00:01:00) [common]
11095 12:22:10.736283 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11096 12:22:10.736690 Using namespace: common
11098 12:22:10.837827 / # #
11099 12:22:10.838674 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11100 12:22:10.843652 #
11101 12:22:10.844746 Using /lava-11299297
11103 12:22:10.946360 / # export SHELL=/bin/sh
11104 12:22:10.953203 export SHELL=/bin/sh
11106 12:22:11.054793 / # . /lava-11299297/environment
11107 12:22:11.061788 . /lava-11299297/environment
11109 12:22:11.169456 / # /lava-11299297/bin/lava-test-runner /lava-11299297/0
11110 12:22:11.170097 Test shell timeout: 10s (minimum of the action and connection timeout)
11111 12:22:11.176165 /lava-11299297/bin/lava-test-runner /lava-11299297/0
11112 12:22:11.403200 + export TESTRUN_ID=0_dmesg
11113 12:22:11.406938 + cd /lava-11299297/0/tests/0_dmesg
11114 12:22:11.409512 + cat uuid
11115 12:22:11.420569 + UUID=11299297_1.<8>[ 26.348619] <LAVA_SIGNAL_STARTRUN 0_dmesg 11299297_1.6.2.3.1>
11116 12:22:11.421094 6.2.3.1
11117 12:22:11.421436 + set +x
11118 12:22:11.422027 Received signal: <STARTRUN> 0_dmesg 11299297_1.6.2.3.1
11119 12:22:11.422377 Starting test lava.0_dmesg (11299297_1.6.2.3.1)
11120 12:22:11.422837 Skipping test definition patterns.
11121 12:22:11.426988 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11122 12:22:11.511948 <8>[ 26.439579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11123 12:22:11.512776 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11125 12:22:11.580411 <8>[ 26.508384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11126 12:22:11.581202 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11128 12:22:11.650216 <8>[ 26.578171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11129 12:22:11.651048 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11131 12:22:11.653847 + set +x
11132 12:22:11.657293 <8>[ 26.587785] <LAVA_SIGNAL_ENDRUN 0_dmesg 11299297_1.6.2.3.1>
11133 12:22:11.658146 Received signal: <ENDRUN> 0_dmesg 11299297_1.6.2.3.1
11134 12:22:11.658670 Ending use of test pattern.
11135 12:22:11.659043 Ending test lava.0_dmesg (11299297_1.6.2.3.1), duration 0.24
11137 12:22:11.664204 <LAVA_TEST_RUNNER EXIT>
11138 12:22:11.665040 ok: lava_test_shell seems to have completed
11139 12:22:11.665626 alert: pass
crit: pass
emerg: pass
11140 12:22:11.666077 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11141 12:22:11.666527 end: 3 lava-test-retry (duration 00:00:01) [common]
11142 12:22:11.667056 start: 4 lava-test-retry (timeout 00:01:00) [common]
11143 12:22:11.667592 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11144 12:22:11.667958 Using namespace: common
11146 12:22:11.769100 / # #
11147 12:22:11.769735 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11148 12:22:11.770304 Using /lava-11299297
11150 12:22:11.871503 export SHELL=/bin/sh
11151 12:22:11.872284 #
11153 12:22:11.973766 / # export SHELL=/bin/sh. /lava-11299297/environment
11154 12:22:11.974550
11156 12:22:12.076257 / # . /lava-11299297/environment/lava-11299297/bin/lava-test-runner /lava-11299297/1
11157 12:22:12.076879 Test shell timeout: 10s (minimum of the action and connection timeout)
11158 12:22:12.077487
11159 12:22:12.082732 / # /lava-11299297/bin/lava-test-runner /lava-11299297/1
11160 12:22:12.185155 + export TESTRUN_ID=1_bootrr
11161 12:22:12.187766 + cd /lava-11299297/1/tests/1_bootrr
11162 12:22:12.191034 + cat uuid
11163 12:22:12.201471 + UUID=11299297_1.<8>[ 27.129661] <LAVA_SIGNAL_STARTRUN 1_bootrr 11299297_1.6.2.3.5>
11164 12:22:12.201906 6.2.3.5
11165 12:22:12.202248 + set +x
11166 12:22:12.202830 Received signal: <STARTRUN> 1_bootrr 11299297_1.6.2.3.5
11167 12:22:12.203170 Starting test lava.1_bootrr (11299297_1.6.2.3.5)
11168 12:22:12.203550 Skipping test definition patterns.
11169 12:22:12.214496 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11299297/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11170 12:22:12.218016 + cd /opt/bootrr/libexec/bootrr
11171 12:22:12.218441 + sh helpers/bootrr-auto
11172 12:22:12.277640 /lava-11299297/1/../bin/lava-test-case
11173 12:22:12.301158 <8>[ 27.229342] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11174 12:22:12.301529 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11176 12:22:12.338343 /lava-11299297/1/../bin/lava-test-case
11177 12:22:12.359330 <8>[ 27.287899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11178 12:22:12.359609 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11180 12:22:12.380119 /lava-11299297/1/../bin/lava-test-case
11181 12:22:12.404006 <8>[ 27.332200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11182 12:22:12.404620 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11184 12:22:12.458625 /lava-11299297/1/../bin/lava-test-case
11185 12:22:12.486647 <8>[ 27.414662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11186 12:22:12.487434 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11188 12:22:12.531023 /lava-11299297/1/../bin/lava-test-case
11189 12:22:12.558525 <8>[ 27.486669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11190 12:22:12.559381 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11192 12:22:12.593278 /lava-11299297/1/../bin/lava-test-case
11193 12:22:12.619031 <8>[ 27.547000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11194 12:22:12.619398 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11196 12:22:12.645730 /lava-11299297/1/../bin/lava-test-case
11197 12:22:12.667373 <8>[ 27.595208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11198 12:22:12.668161 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11200 12:22:12.699592 /lava-11299297/1/../bin/lava-test-case
11201 12:22:12.723775 <8>[ 27.651940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11202 12:22:12.724465 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11204 12:22:12.746122 /lava-11299297/1/../bin/lava-test-case
11205 12:22:12.771180 <8>[ 27.699713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11206 12:22:12.771532 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11208 12:22:12.802082 /lava-11299297/1/../bin/lava-test-case
11209 12:22:12.827635 <8>[ 27.755362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11210 12:22:12.828006 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11212 12:22:12.853417 /lava-11299297/1/../bin/lava-test-case
11213 12:22:12.875305 <8>[ 27.803366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11214 12:22:12.876178 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11216 12:22:12.910118 /lava-11299297/1/../bin/lava-test-case
11217 12:22:12.931742 <8>[ 27.860274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11218 12:22:12.932097 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11220 12:22:12.962382 /lava-11299297/1/../bin/lava-test-case
11221 12:22:12.988018 <8>[ 27.916015] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11222 12:22:12.988861 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11224 12:22:13.019706 /lava-11299297/1/../bin/lava-test-case
11225 12:22:13.047103 <8>[ 27.975565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11226 12:22:13.047823 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11228 12:22:13.079909 /lava-11299297/1/../bin/lava-test-case
11229 12:22:13.105531 <8>[ 28.033143] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11230 12:22:13.106213 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11232 12:22:13.125546 /lava-11299297/1/../bin/lava-test-case
11233 12:22:13.153200 <8>[ 28.081354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11234 12:22:13.153886 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11236 12:22:13.195038 /lava-11299297/1/../bin/lava-test-case
11237 12:22:13.222995 <8>[ 28.151253] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11238 12:22:13.223800 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11240 12:22:13.246335 /lava-11299297/1/../bin/lava-test-case
11241 12:22:13.272916 <8>[ 28.201301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11242 12:22:13.273282 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11244 12:22:13.304821 /lava-11299297/1/../bin/lava-test-case
11245 12:22:13.331439 <8>[ 28.259354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11246 12:22:13.332227 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11248 12:22:13.353432 /lava-11299297/1/../bin/lava-test-case
11249 12:22:13.379870 <8>[ 28.308268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11250 12:22:13.380849 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11252 12:22:13.414260 /lava-11299297/1/../bin/lava-test-case
11253 12:22:13.436925 <8>[ 28.365206] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11254 12:22:13.437618 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11256 12:22:13.457166 /lava-11299297/1/../bin/lava-test-case
11257 12:22:13.490244 <8>[ 28.418449] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11258 12:22:13.491088 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11260 12:22:13.527028 /lava-11299297/1/../bin/lava-test-case
11261 12:22:13.550862 <8>[ 28.478547] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11262 12:22:13.551545 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11264 12:22:13.571173 /lava-11299297/1/../bin/lava-test-case
11265 12:22:13.595887 <8>[ 28.523714] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11266 12:22:13.596571 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11268 12:22:13.630230 /lava-11299297/1/../bin/lava-test-case
11269 12:22:13.652370 <8>[ 28.580375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11270 12:22:13.653160 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11272 12:22:13.687976 /lava-11299297/1/../bin/lava-test-case
11273 12:22:13.717094 <8>[ 28.645290] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11274 12:22:13.717918 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11276 12:22:13.741078 /lava-11299297/1/../bin/lava-test-case
11277 12:22:13.766320 <8>[ 28.694413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11278 12:22:13.767057 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11280 12:22:13.814585 /lava-11299297/1/../bin/lava-test-case
11281 12:22:13.840943 <8>[ 28.768550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11282 12:22:13.841732 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11284 12:22:13.859948 /lava-11299297/1/../bin/lava-test-case
11285 12:22:13.883262 <8>[ 28.811795] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11286 12:22:13.884024 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11288 12:22:13.918668 /lava-11299297/1/../bin/lava-test-case
11289 12:22:13.945592 <8>[ 28.873536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11290 12:22:13.946388 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11292 12:22:13.978302 /lava-11299297/1/../bin/lava-test-case
11293 12:22:14.004737 <8>[ 28.932595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11294 12:22:14.005520 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11296 12:22:14.039562 /lava-11299297/1/../bin/lava-test-case
11297 12:22:14.066878 <8>[ 28.995362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11298 12:22:14.067622 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11300 12:22:14.096881 /lava-11299297/1/../bin/lava-test-case
11301 12:22:14.122675 <8>[ 29.050918] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11302 12:22:14.123369 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11304 12:22:14.151641 /lava-11299297/1/../bin/lava-test-case
11305 12:22:14.178978 <8>[ 29.107188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11306 12:22:14.179657 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11308 12:22:14.214837 /lava-11299297/1/../bin/lava-test-case
11309 12:22:14.238890 <8>[ 29.167475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11310 12:22:14.239250 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11312 12:22:14.273762 /lava-11299297/1/../bin/lava-test-case
11313 12:22:14.295493 <8>[ 29.224120] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11314 12:22:14.295842 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11316 12:22:14.315230 /lava-11299297/1/../bin/lava-test-case
11317 12:22:14.336434 <8>[ 29.265015] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11318 12:22:14.337005 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11320 12:22:14.373075 /lava-11299297/1/../bin/lava-test-case
11321 12:22:14.397259 <8>[ 29.325135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11322 12:22:14.397937 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11324 12:22:14.417860 /lava-11299297/1/../bin/lava-test-case
11325 12:22:14.446127 <8>[ 29.374694] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11326 12:22:14.446513 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11328 12:22:14.481268 /lava-11299297/1/../bin/lava-test-case
11329 12:22:14.505276 <8>[ 29.433462] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11330 12:22:14.506093 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11332 12:22:14.525360 /lava-11299297/1/../bin/lava-test-case
11333 12:22:14.551989 <8>[ 29.480056] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11334 12:22:14.552808 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11336 12:22:14.586120 /lava-11299297/1/../bin/lava-test-case
11337 12:22:14.611799 <8>[ 29.540187] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11338 12:22:14.612518 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11340 12:22:14.633770 /lava-11299297/1/../bin/lava-test-case
11341 12:22:14.660528 <8>[ 29.588850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11342 12:22:14.661319 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11344 12:22:14.696482 /lava-11299297/1/../bin/lava-test-case
11345 12:22:14.720639 <8>[ 29.648733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11346 12:22:14.721430 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11348 12:22:14.741673 /lava-11299297/1/../bin/lava-test-case
11349 12:22:14.767586 <8>[ 29.696312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11350 12:22:14.767962 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11352 12:22:14.803963 /lava-11299297/1/../bin/lava-test-case
11353 12:22:14.825512 <8>[ 29.754395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11354 12:22:14.825784 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11356 12:22:14.846935 /lava-11299297/1/../bin/lava-test-case
11357 12:22:14.872860 <8>[ 29.801539] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11358 12:22:14.873222 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11360 12:22:14.904181 /lava-11299297/1/../bin/lava-test-case
11361 12:22:14.930320 <8>[ 29.858951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11362 12:22:14.931043 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11364 12:22:14.953089 /lava-11299297/1/../bin/lava-test-case
11365 12:22:14.980757 <8>[ 29.909172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11366 12:22:14.981447 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11368 12:22:15.013850 /lava-11299297/1/../bin/lava-test-case
11369 12:22:15.037263 <8>[ 29.966055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11370 12:22:15.037544 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11372 12:22:15.067615 /lava-11299297/1/../bin/lava-test-case
11373 12:22:15.092065 <8>[ 30.020921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11374 12:22:15.092432 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11376 12:22:15.120343 /lava-11299297/1/../bin/lava-test-case
11377 12:22:15.141064 <8>[ 30.069964] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11378 12:22:15.141463 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11380 12:22:15.173823 /lava-11299297/1/../bin/lava-test-case
11381 12:22:15.200409 <8>[ 30.129491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11382 12:22:15.200680 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11384 12:22:15.221586 /lava-11299297/1/../bin/lava-test-case
11385 12:22:15.248237 <8>[ 30.176333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11386 12:22:15.249126 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11388 12:22:15.282976 /lava-11299297/1/../bin/lava-test-case
11389 12:22:15.306416 <8>[ 30.234622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11390 12:22:15.306800 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11392 12:22:15.335834 /lava-11299297/1/../bin/lava-test-case
11393 12:22:15.360611 <8>[ 30.289338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11394 12:22:15.360921 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11396 12:22:15.392447 /lava-11299297/1/../bin/lava-test-case
11397 12:22:15.419705 <8>[ 30.348284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11398 12:22:15.420495 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11400 12:22:15.461921 /lava-11299297/1/../bin/lava-test-case
11401 12:22:15.491564 <8>[ 30.419807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11402 12:22:15.492299 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11404 12:22:15.524412 /lava-11299297/1/../bin/lava-test-case
11405 12:22:15.550651 <8>[ 30.479082] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11406 12:22:15.551337 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11408 12:22:15.573306 /lava-11299297/1/../bin/lava-test-case
11409 12:22:15.598446 <8>[ 30.526781] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11410 12:22:15.599167 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11412 12:22:15.633126 /lava-11299297/1/../bin/lava-test-case
11413 12:22:15.661368 <8>[ 30.589570] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11414 12:22:15.662154 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11416 12:22:15.693579 /lava-11299297/1/../bin/lava-test-case
11417 12:22:15.717121 <8>[ 30.645621] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11418 12:22:15.717795 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11420 12:22:15.738949 /lava-11299297/1/../bin/lava-test-case
11421 12:22:15.767971 <8>[ 30.695973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11422 12:22:15.768755 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11424 12:22:15.811742 /lava-11299297/1/../bin/lava-test-case
11425 12:22:15.837786 <8>[ 30.766574] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11426 12:22:15.838062 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11428 12:22:15.858793 /lava-11299297/1/../bin/lava-test-case
11429 12:22:15.886218 <8>[ 30.814495] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11430 12:22:15.887093 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11432 12:22:15.923175 /lava-11299297/1/../bin/lava-test-case
11433 12:22:15.949689 <8>[ 30.878230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11434 12:22:15.950482 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11436 12:22:15.972574 /lava-11299297/1/../bin/lava-test-case
11437 12:22:16.001578 <8>[ 30.929598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11438 12:22:16.002336 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11440 12:22:16.033632 /lava-11299297/1/../bin/lava-test-case
11441 12:22:16.060928 <8>[ 30.989415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11442 12:22:16.061654 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11444 12:22:16.096054 /lava-11299297/1/../bin/lava-test-case
11445 12:22:16.119258 <8>[ 31.048311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11446 12:22:16.119620 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11448 12:22:16.153914 /lava-11299297/1/../bin/lava-test-case
11449 12:22:16.179828 <8>[ 31.108496] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11450 12:22:16.180516 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11452 12:22:16.210556 /lava-11299297/1/../bin/lava-test-case
11453 12:22:16.233669 <8>[ 31.162289] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11454 12:22:16.234347 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11456 12:22:16.265254 /lava-11299297/1/../bin/lava-test-case
11457 12:22:16.290534 <8>[ 31.219089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11458 12:22:16.291263 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11460 12:22:16.326019 /lava-11299297/1/../bin/lava-test-case
11461 12:22:16.353769 <8>[ 31.282144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11462 12:22:16.354673 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11464 12:22:16.384873 /lava-11299297/1/../bin/lava-test-case
11465 12:22:16.408708 <8>[ 31.337503] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11466 12:22:16.409065 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11468 12:22:16.439332 /lava-11299297/1/../bin/lava-test-case
11469 12:22:16.461534 <8>[ 31.390210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11470 12:22:16.461895 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11472 12:22:16.499787 /lava-11299297/1/../bin/lava-test-case
11473 12:22:16.524967 <8>[ 31.453374] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11474 12:22:16.525333 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11476 12:22:16.553437 /lava-11299297/1/../bin/lava-test-case
11477 12:22:16.577067 <8>[ 31.505667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11478 12:22:16.577835 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11480 12:22:16.607113 /lava-11299297/1/../bin/lava-test-case
11481 12:22:16.629334 <8>[ 31.558393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11482 12:22:16.629599 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11484 12:22:16.661980 /lava-11299297/1/../bin/lava-test-case
11485 12:22:16.687333 <8>[ 31.616090] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11486 12:22:16.688119 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11488 12:22:16.719256 /lava-11299297/1/../bin/lava-test-case
11489 12:22:16.740931 <8>[ 31.670032] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11490 12:22:16.741204 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11492 12:22:16.772764 /lava-11299297/1/../bin/lava-test-case
11493 12:22:16.799572 <8>[ 31.728649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11494 12:22:16.799931 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11496 12:22:16.838453 /lava-11299297/1/../bin/lava-test-case
11497 12:22:16.860821 <8>[ 31.789794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11498 12:22:16.861110 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11500 12:22:16.881812 /lava-11299297/1/../bin/lava-test-case
11501 12:22:16.908255 <8>[ 31.836308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11502 12:22:16.909053 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11504 12:22:16.939015 /lava-11299297/1/../bin/lava-test-case
11505 12:22:16.962401 <8>[ 31.891484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11506 12:22:16.962767 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11508 12:22:16.981800 /lava-11299297/1/../bin/lava-test-case
11509 12:22:17.007062 <8>[ 31.935695] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11510 12:22:17.007701 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11512 12:22:17.040345 /lava-11299297/1/../bin/lava-test-case
11513 12:22:17.069148 <8>[ 31.997779] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11514 12:22:17.069910 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11516 12:22:17.090424 /lava-11299297/1/../bin/lava-test-case
11517 12:22:17.118540 <8>[ 32.047479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11518 12:22:17.119522 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11520 12:22:17.160910 /lava-11299297/1/../bin/lava-test-case
11521 12:22:17.186413 <8>[ 32.115415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11522 12:22:17.186685 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11524 12:22:17.206021 /lava-11299297/1/../bin/lava-test-case
11525 12:22:17.228299 <8>[ 32.157239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11526 12:22:17.228878 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11528 12:22:17.262685 /lava-11299297/1/../bin/lava-test-case
11529 12:22:17.289150 <8>[ 32.217458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11530 12:22:17.289902 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11532 12:22:17.310902 /lava-11299297/1/../bin/lava-test-case
11533 12:22:17.337689 <8>[ 32.266829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11534 12:22:17.337964 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11536 12:22:17.369612 /lava-11299297/1/../bin/lava-test-case
11537 12:22:17.394640 <8>[ 32.323684] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11538 12:22:17.395353 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11540 12:22:17.417216 /lava-11299297/1/../bin/lava-test-case
11541 12:22:17.438918 <8>[ 32.368121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11542 12:22:17.439274 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11544 12:22:17.480216 /lava-11299297/1/../bin/lava-test-case
11545 12:22:17.502890 <8>[ 32.432106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11546 12:22:17.503251 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11548 12:22:17.535590 /lava-11299297/1/../bin/lava-test-case
11549 12:22:17.561869 <8>[ 32.490230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11550 12:22:17.562699 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11552 12:22:17.583780 /lava-11299297/1/../bin/lava-test-case
11553 12:22:17.610945 <8>[ 32.539478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11554 12:22:17.611736 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11556 12:22:17.643019 /lava-11299297/1/../bin/lava-test-case
11557 12:22:17.666217 <8>[ 32.595033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11558 12:22:17.666573 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11560 12:22:17.688371 /lava-11299297/1/../bin/lava-test-case
11561 12:22:17.714957 <8>[ 32.643620] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11562 12:22:17.715717 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11564 12:22:17.749502 /lava-11299297/1/../bin/lava-test-case
11565 12:22:17.777847 <8>[ 32.706434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11566 12:22:17.778689 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11568 12:22:17.806233 /lava-11299297/1/../bin/lava-test-case
11569 12:22:17.834684 <8>[ 32.763592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11570 12:22:17.835371 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11572 12:22:18.883476 /lava-11299297/1/../bin/lava-test-case
11573 12:22:18.912813 <8>[ 33.841766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11574 12:22:18.913549 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11576 12:22:18.933931 /lava-11299297/1/../bin/lava-test-case
11577 12:22:18.957302 <8>[ 33.886084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11578 12:22:18.957662 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11580 12:22:19.988497 /lava-11299297/1/../bin/lava-test-case
11581 12:22:20.016493 <8>[ 34.945418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11582 12:22:20.017287 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11584 12:22:20.038708 /lava-11299297/1/../bin/lava-test-case
11585 12:22:20.066737 <8>[ 34.995780] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11586 12:22:20.067455 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11588 12:22:21.105382 /lava-11299297/1/../bin/lava-test-case
11589 12:22:21.132550 <8>[ 36.062015] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11590 12:22:21.132920 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11592 12:22:21.151591 /lava-11299297/1/../bin/lava-test-case
11593 12:22:21.173972 <8>[ 36.102868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11594 12:22:21.174699 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11596 12:22:22.209460 /lava-11299297/1/../bin/lava-test-case
11597 12:22:22.235775 <8>[ 37.165096] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11598 12:22:22.236047 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11600 12:22:22.255047 /lava-11299297/1/../bin/lava-test-case
11601 12:22:22.278386 <8>[ 37.207917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11602 12:22:22.278747 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11604 12:22:23.314097 /lava-11299297/1/../bin/lava-test-case
11605 12:22:23.338624 <8>[ 38.268223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11606 12:22:23.338986 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11608 12:22:23.358982 /lava-11299297/1/../bin/lava-test-case
11609 12:22:23.383237 <8>[ 38.312809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11610 12:22:23.383599 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11612 12:22:24.420270 /lava-11299297/1/../bin/lava-test-case
11613 12:22:24.450662 <8>[ 39.380128] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11614 12:22:24.451021 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11616 12:22:24.469431 /lava-11299297/1/../bin/lava-test-case
11617 12:22:24.493997 <8>[ 39.423801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11618 12:22:24.494669 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11620 12:22:25.535961 /lava-11299297/1/../bin/lava-test-case
11621 12:22:25.563604 <8>[ 40.493630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11622 12:22:25.563968 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11624 12:22:25.583801 /lava-11299297/1/../bin/lava-test-case
11625 12:22:25.608254 <8>[ 40.538228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11626 12:22:25.608714 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11628 12:22:25.629811 /lava-11299297/1/../bin/lava-test-case
11629 12:22:25.657464 <8>[ 40.586909] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11630 12:22:25.658253 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11632 12:22:26.698820 /lava-11299297/1/../bin/lava-test-case
11633 12:22:26.727922 <8>[ 41.657769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11634 12:22:26.728755 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11636 12:22:26.750654 /lava-11299297/1/../bin/lava-test-case
11637 12:22:26.777866 <8>[ 41.707712] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11638 12:22:26.778212 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11640 12:22:26.811174 /lava-11299297/1/../bin/lava-test-case
11641 12:22:26.837889 <8>[ 41.767622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11642 12:22:26.838729 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11644 12:22:26.861212 /lava-11299297/1/../bin/lava-test-case
11645 12:22:26.884434 <8>[ 41.813601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11646 12:22:26.885230 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11648 12:22:26.917326 /lava-11299297/1/../bin/lava-test-case
11649 12:22:26.941246 <8>[ 41.871147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11650 12:22:26.941924 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11652 12:22:26.975640 /lava-11299297/1/../bin/lava-test-case
11653 12:22:27.001045 <8>[ 41.931032] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11654 12:22:27.001736 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11656 12:22:27.039756 /lava-11299297/1/../bin/lava-test-case
11657 12:22:27.069178 <8>[ 41.998782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11658 12:22:27.069966 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11660 12:22:27.092707 /lava-11299297/1/../bin/lava-test-case
11661 12:22:27.120806 <8>[ 42.050648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11662 12:22:27.121496 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11664 12:22:27.153715 /lava-11299297/1/../bin/lava-test-case
11665 12:22:27.176970 <8>[ 42.106640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11666 12:22:27.177247 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11668 12:22:27.212056 /lava-11299297/1/../bin/lava-test-case
11669 12:22:27.238254 <8>[ 42.167900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11670 12:22:27.239197 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11672 12:22:27.265729 /lava-11299297/1/../bin/lava-test-case
11673 12:22:27.291414 <8>[ 42.221117] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11674 12:22:27.292201 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11676 12:22:27.328672 /lava-11299297/1/../bin/lava-test-case
11677 12:22:27.356667 <8>[ 42.286703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11678 12:22:27.357500 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11680 12:22:27.384994 /lava-11299297/1/../bin/lava-test-case
11681 12:22:27.411166 <8>[ 42.340925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11682 12:22:27.411958 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11684 12:22:27.448064 /lava-11299297/1/../bin/lava-test-case
11685 12:22:27.478456 <8>[ 42.408627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11686 12:22:27.479182 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11688 12:22:27.502074 /lava-11299297/1/../bin/lava-test-case
11689 12:22:27.529191 <8>[ 42.459073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11690 12:22:27.529984 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11692 12:22:27.565216 /lava-11299297/1/../bin/lava-test-case
11693 12:22:27.594187 <8>[ 42.523959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11694 12:22:27.595180 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11696 12:22:27.617907 /lava-11299297/1/../bin/lava-test-case
11697 12:22:27.646517 <8>[ 42.576315] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11698 12:22:27.647355 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11700 12:22:27.683996 /lava-11299297/1/../bin/lava-test-case
11701 12:22:27.709758 <8>[ 42.639777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11702 12:22:27.710444 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11704 12:22:27.742476 /lava-11299297/1/../bin/lava-test-case
11705 12:22:27.773836 <8>[ 42.703498] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11706 12:22:27.774708 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11708 12:22:27.808823 /lava-11299297/1/../bin/lava-test-case
11709 12:22:27.834271 <8>[ 42.764046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11710 12:22:27.835014 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11712 12:22:27.858056 /lava-11299297/1/../bin/lava-test-case
11713 12:22:27.887809 <8>[ 42.817455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11714 12:22:27.888734 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11716 12:22:28.933034 /lava-11299297/1/../bin/lava-test-case
11717 12:22:28.963865 <8>[ 43.892966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11718 12:22:28.964584 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11720 12:22:30.003348 /lava-11299297/1/../bin/lava-test-case
11721 12:22:30.030093 <8>[ 44.960442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11722 12:22:30.030999 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11724 12:22:30.050917 /lava-11299297/1/../bin/lava-test-case
11725 12:22:30.077312 <8>[ 45.007548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11726 12:22:30.077678 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11728 12:22:30.109090 /lava-11299297/1/../bin/lava-test-case
11729 12:22:30.133092 <8>[ 45.063238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11730 12:22:30.133800 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11732 12:22:30.155050 /lava-11299297/1/../bin/lava-test-case
11733 12:22:30.181846 <8>[ 45.111172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11734 12:22:30.182210 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11736 12:22:30.211417 /lava-11299297/1/../bin/lava-test-case
11737 12:22:30.236258 <8>[ 45.166572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11738 12:22:30.237051 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11740 12:22:30.258690 /lava-11299297/1/../bin/lava-test-case
11741 12:22:30.283377 <8>[ 45.213084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11742 12:22:30.284212 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11744 12:22:30.321890 /lava-11299297/1/../bin/lava-test-case
11745 12:22:30.349787 <8>[ 45.280027] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11746 12:22:30.350469 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11748 12:22:30.370087 /lava-11299297/1/../bin/lava-test-case
11749 12:22:30.394293 <8>[ 45.324276] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11750 12:22:30.395070 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11752 12:22:30.429166 /lava-11299297/1/../bin/lava-test-case
11753 12:22:30.456978 <8>[ 45.386822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11754 12:22:30.457792 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11756 12:22:30.479853 /lava-11299297/1/../bin/lava-test-case
11757 12:22:30.508043 <8>[ 45.438075] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11758 12:22:30.508873 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11760 12:22:30.542238 /lava-11299297/1/../bin/lava-test-case
11761 12:22:30.569057 <8>[ 45.499369] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11762 12:22:30.569743 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11764 12:22:30.592445 /lava-11299297/1/../bin/lava-test-case
11765 12:22:30.617239 <8>[ 45.547382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11766 12:22:30.618045 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11768 12:22:30.659119 /lava-11299297/1/../bin/lava-test-case
11769 12:22:30.683616 <8>[ 45.613797] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11770 12:22:30.684475 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11772 12:22:30.703962 /lava-11299297/1/../bin/lava-test-case
11773 12:22:30.729669 <8>[ 45.660065] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11774 12:22:30.730349 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11776 12:22:30.761384 /lava-11299297/1/../bin/lava-test-case
11777 12:22:30.785798 <8>[ 45.715842] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11778 12:22:30.786682 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11780 12:22:30.807522 /lava-11299297/1/../bin/lava-test-case
11781 12:22:30.833283 <8>[ 45.762878] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11782 12:22:30.834103 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11784 12:22:30.864402 /lava-11299297/1/../bin/lava-test-case
11785 12:22:30.888733 <8>[ 45.818821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11786 12:22:30.889529 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11788 12:22:30.909666 /lava-11299297/1/../bin/lava-test-case
11789 12:22:30.934789 <8>[ 45.864947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11790 12:22:30.935589 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11792 12:22:30.976641 /lava-11299297/1/../bin/lava-test-case
11793 12:22:31.003226 <8>[ 45.933941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11794 12:22:31.003599 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11796 12:22:31.023434 /lava-11299297/1/../bin/lava-tes<6>[ 45.959440] vpu: disabling
11797 12:22:31.023895 t-case
11798 12:22:31.026404 <6>[ 45.962800] vproc2: disabling
11799 12:22:31.030088 <6>[ 45.966717] vproc1: disabling
11800 12:22:31.033980 <6>[ 45.970182] vaud18: disabling
11801 12:22:31.040588 <6>[ 45.973853] vsram_others: disabling
11802 12:22:31.043727 <6>[ 45.977841] va09: disabling
11803 12:22:31.047119 <6>[ 45.981072] vsram_md: disabling
11804 12:22:31.050216 <6>[ 45.984694] Vgpu: disabling
11805 12:22:31.073116 <8>[ 46.003619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11806 12:22:31.073808 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11808 12:22:31.108407 /lava-11299297/1/../bin/lava-test-case
11809 12:22:31.131480 <8>[ 46.061941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11810 12:22:31.131845 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11812 12:22:32.161546 /lava-11299297/1/../bin/lava-test-case
11813 12:22:32.191377 <8>[ 47.121927] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11814 12:22:32.191741 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11816 12:22:33.223022 /lava-11299297/1/../bin/lava-test-case
11817 12:22:33.251521 <8>[ 48.182265] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11818 12:22:33.252400 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11819 12:22:33.252952 Bad test result: blocked
11820 12:22:33.273094 /lava-11299297/1/../bin/lava-test-case
11821 12:22:33.301070 <8>[ 48.231338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11822 12:22:33.301879 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11824 12:22:34.343310 /lava-11299297/1/../bin/lava-test-case
11825 12:22:34.375241 <8>[ 49.305456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11826 12:22:34.376072 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11828 12:22:34.398479 /lava-11299297/1/../bin/lava-test-case
11829 12:22:34.424109 <8>[ 49.354770] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11830 12:22:34.424806 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11832 12:22:34.459864 /lava-11299297/1/../bin/lava-test-case
11833 12:22:34.484951 <8>[ 49.415510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11834 12:22:34.485317 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11836 12:22:34.518995 /lava-11299297/1/../bin/lava-test-case
11837 12:22:34.540540 <8>[ 49.471217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11838 12:22:34.540893 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11840 12:22:34.557094 /lava-11299297/1/../bin/lava-test-case
11841 12:22:34.580249 <8>[ 49.511063] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11842 12:22:34.580828 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11844 12:22:34.611655 /lava-11299297/1/../bin/lava-test-case
11845 12:22:34.635338 <8>[ 49.566447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11846 12:22:34.635615 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11848 12:22:34.662262 /lava-11299297/1/../bin/lava-test-case
11849 12:22:34.682128 <8>[ 49.612619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11850 12:22:34.682687 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11852 12:22:35.721764 /lava-11299297/1/../bin/lava-test-case
11853 12:22:35.750787 <8>[ 50.681535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11854 12:22:35.751570 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11856 12:22:35.774451 /lava-11299297/1/../bin/lava-test-case
11857 12:22:35.802435 <8>[ 50.732653] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11858 12:22:35.803443 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11860 12:22:36.837821 /lava-11299297/1/../bin/lava-test-case
11861 12:22:36.866246 <8>[ 51.797429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11862 12:22:36.867072 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11864 12:22:36.887511 /lava-11299297/1/../bin/lava-test-case
11865 12:22:36.910021 <8>[ 51.841005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11866 12:22:36.910712 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11868 12:22:37.948055 /lava-11299297/1/../bin/lava-test-case
11869 12:22:37.974389 <8>[ 52.905427] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11870 12:22:37.975197 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11872 12:22:37.996907 /lava-11299297/1/../bin/lava-test-case
11873 12:22:38.020888 <8>[ 52.952025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11874 12:22:38.021638 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11876 12:22:39.063929 /lava-11299297/1/../bin/lava-test-case
11877 12:22:39.092051 <8>[ 54.023158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11878 12:22:39.092965 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11880 12:22:39.114714 /lava-11299297/1/../bin/lava-test-case
11881 12:22:39.142107 <8>[ 54.073001] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11882 12:22:39.142812 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11884 12:22:39.172946 /lava-11299297/1/../bin/lava-test-case
11885 12:22:39.198266 <8>[ 54.128654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11886 12:22:39.199116 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11888 12:22:39.227842 /lava-11299297/1/../bin/lava-test-case
11889 12:22:39.253990 <8>[ 54.185361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11890 12:22:39.254901 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11892 12:22:39.275665 /lava-11299297/1/../bin/lava-test-case
11893 12:22:39.300698 <8>[ 54.231914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11894 12:22:39.301515 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11896 12:22:39.339498 /lava-11299297/1/../bin/lava-test-case
11897 12:22:39.366304 <8>[ 54.297739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11898 12:22:39.367119 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11900 12:22:39.394037 /lava-11299297/1/../bin/lava-test-case
11901 12:22:39.418928 <8>[ 54.349583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11902 12:22:39.419775 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11904 12:22:39.451654 /lava-11299297/1/../bin/lava-test-case
11905 12:22:39.476581 <8>[ 54.408198] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11906 12:22:39.476867 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11908 12:22:39.498005 /lava-11299297/1/../bin/lava-test-case
11909 12:22:39.521837 <8>[ 54.453406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11910 12:22:39.522198 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11912 12:22:39.554785 /lava-11299297/1/../bin/lava-test-case
11913 12:22:39.575157 <8>[ 54.506688] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11914 12:22:39.575601 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11916 12:22:39.584492 + <8>[ 54.518962] <LAVA_SIGNAL_ENDRUN 1_bootrr 11299297_1.6.2.3.5>
11917 12:22:39.584979 Received signal: <ENDRUN> 1_bootrr 11299297_1.6.2.3.5
11918 12:22:39.585168 Ending use of test pattern.
11919 12:22:39.585319 Ending test lava.1_bootrr (11299297_1.6.2.3.5), duration 27.38
11921 12:22:39.587457 set +x
11922 12:22:39.590918 <LAVA_TEST_RUNNER EXIT>
11923 12:22:39.591431 ok: lava_test_shell seems to have completed
11924 12:22:39.594805 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11925 12:22:39.595300 end: 4.1 lava-test-shell (duration 00:00:28) [common]
11926 12:22:39.595603 end: 4 lava-test-retry (duration 00:00:28) [common]
11927 12:22:39.595960 start: 5 finalize (timeout 00:07:43) [common]
11928 12:22:39.596366 start: 5.1 power-off (timeout 00:00:30) [common]
11929 12:22:39.597045 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11930 12:22:39.682241 >> Command sent successfully.
11931 12:22:39.687105 Returned 0 in 0 seconds
11932 12:22:39.788094 end: 5.1 power-off (duration 00:00:00) [common]
11934 12:22:39.789904 start: 5.2 read-feedback (timeout 00:07:42) [common]
11935 12:22:39.791326 Listened to connection for namespace 'common' for up to 1s
11936 12:22:40.790908 Finalising connection for namespace 'common'
11937 12:22:40.791582 Disconnecting from shell: Finalise
11938 12:22:40.792002 / #
11939 12:22:40.893140 end: 5.2 read-feedback (duration 00:00:01) [common]
11940 12:22:40.893872 end: 5 finalize (duration 00:00:01) [common]
11941 12:22:40.894489 Cleaning after the job
11942 12:22:40.895046 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299297/tftp-deploy-mxwlri9y/ramdisk
11943 12:22:40.908629 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299297/tftp-deploy-mxwlri9y/kernel
11944 12:22:40.941872 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299297/tftp-deploy-mxwlri9y/dtb
11945 12:22:40.942159 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299297/tftp-deploy-mxwlri9y/nfsrootfs
11946 12:22:41.018568 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299297/tftp-deploy-mxwlri9y/modules
11947 12:22:41.025674 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11299297
11948 12:22:41.397483 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11299297
11949 12:22:41.397662 Job finished correctly