Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 19
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 27
- Errors: 1
1 00:24:22.412951 lava-dispatcher, installed at version: 2023.05.1
2 00:24:22.413170 start: 0 validate
3 00:24:22.413308 Start time: 2023-08-14 00:24:22.413299+00:00 (UTC)
4 00:24:22.413435 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:24:22.413565 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 00:24:22.684590 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:24:22.684893 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:25:17.226029 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:25:17.226804 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:25:17.496755 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:25:17.497482 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:25:22.268067 validate duration: 59.85
14 00:25:22.268315 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:25:22.268407 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:25:22.268492 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:25:22.268613 Not decompressing ramdisk as can be used compressed.
18 00:25:22.268694 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 00:25:22.268758 saving as /var/lib/lava/dispatcher/tmp/11280962/tftp-deploy-apdiwvfj/ramdisk/rootfs.cpio.gz
20 00:25:22.268816 total size: 8181372 (7MB)
21 00:25:22.533545 progress 0% (0MB)
22 00:25:22.535900 progress 5% (0MB)
23 00:25:22.537993 progress 10% (0MB)
24 00:25:22.540409 progress 15% (1MB)
25 00:25:22.542567 progress 20% (1MB)
26 00:25:22.544940 progress 25% (1MB)
27 00:25:22.547168 progress 30% (2MB)
28 00:25:22.549506 progress 35% (2MB)
29 00:25:22.551600 progress 40% (3MB)
30 00:25:22.553841 progress 45% (3MB)
31 00:25:22.555943 progress 50% (3MB)
32 00:25:22.558167 progress 55% (4MB)
33 00:25:22.560213 progress 60% (4MB)
34 00:25:22.562424 progress 65% (5MB)
35 00:25:22.564582 progress 70% (5MB)
36 00:25:22.566788 progress 75% (5MB)
37 00:25:22.568919 progress 80% (6MB)
38 00:25:22.571265 progress 85% (6MB)
39 00:25:22.573468 progress 90% (7MB)
40 00:25:22.575754 progress 95% (7MB)
41 00:25:22.577881 progress 100% (7MB)
42 00:25:22.578081 7MB downloaded in 0.31s (25.23MB/s)
43 00:25:22.578231 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:25:22.578500 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:25:22.578586 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:25:22.578669 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:25:22.578806 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:25:22.578891 saving as /var/lib/lava/dispatcher/tmp/11280962/tftp-deploy-apdiwvfj/kernel/Image
50 00:25:22.578953 total size: 49220096 (46MB)
51 00:25:22.579014 No compression specified
52 00:25:22.580271 progress 0% (0MB)
53 00:25:22.593268 progress 5% (2MB)
54 00:25:22.606230 progress 10% (4MB)
55 00:25:22.619198 progress 15% (7MB)
56 00:25:22.632134 progress 20% (9MB)
57 00:25:22.645002 progress 25% (11MB)
58 00:25:22.658363 progress 30% (14MB)
59 00:25:22.671708 progress 35% (16MB)
60 00:25:22.684609 progress 40% (18MB)
61 00:25:22.697480 progress 45% (21MB)
62 00:25:22.710457 progress 50% (23MB)
63 00:25:22.723911 progress 55% (25MB)
64 00:25:22.736783 progress 60% (28MB)
65 00:25:22.749624 progress 65% (30MB)
66 00:25:22.763285 progress 70% (32MB)
67 00:25:22.777828 progress 75% (35MB)
68 00:25:22.791208 progress 80% (37MB)
69 00:25:22.804409 progress 85% (39MB)
70 00:25:22.817470 progress 90% (42MB)
71 00:25:22.830296 progress 95% (44MB)
72 00:25:22.843108 progress 100% (46MB)
73 00:25:22.843272 46MB downloaded in 0.26s (177.59MB/s)
74 00:25:22.843429 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:25:22.843684 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:25:22.843773 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:25:22.843864 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:25:22.844010 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:25:22.844084 saving as /var/lib/lava/dispatcher/tmp/11280962/tftp-deploy-apdiwvfj/dtb/mt8192-asurada-spherion-r0.dtb
81 00:25:22.844151 total size: 47278 (0MB)
82 00:25:22.844212 No compression specified
83 00:25:22.845349 progress 69% (0MB)
84 00:25:22.845630 progress 100% (0MB)
85 00:25:22.845787 0MB downloaded in 0.00s (27.61MB/s)
86 00:25:22.845909 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:25:22.846184 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:25:22.846289 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:25:22.846392 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:25:22.846530 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:25:22.846605 saving as /var/lib/lava/dispatcher/tmp/11280962/tftp-deploy-apdiwvfj/modules/modules.tar
93 00:25:22.846710 total size: 8562896 (8MB)
94 00:25:22.846811 Using unxz to decompress xz
95 00:25:22.851506 progress 0% (0MB)
96 00:25:22.873440 progress 5% (0MB)
97 00:25:22.897044 progress 10% (0MB)
98 00:25:22.925424 progress 15% (1MB)
99 00:25:22.957235 progress 20% (1MB)
100 00:25:22.984544 progress 25% (2MB)
101 00:25:23.013415 progress 30% (2MB)
102 00:25:23.040059 progress 35% (2MB)
103 00:25:23.066215 progress 40% (3MB)
104 00:25:23.092097 progress 45% (3MB)
105 00:25:23.119240 progress 50% (4MB)
106 00:25:23.144842 progress 55% (4MB)
107 00:25:23.169944 progress 60% (4MB)
108 00:25:23.193016 progress 65% (5MB)
109 00:25:23.218670 progress 70% (5MB)
110 00:25:23.243251 progress 75% (6MB)
111 00:25:23.271826 progress 80% (6MB)
112 00:25:23.302498 progress 85% (6MB)
113 00:25:23.328500 progress 90% (7MB)
114 00:25:23.354004 progress 95% (7MB)
115 00:25:23.377725 progress 100% (8MB)
116 00:25:23.382901 8MB downloaded in 0.54s (15.23MB/s)
117 00:25:23.383237 end: 1.4.1 http-download (duration 00:00:01) [common]
119 00:25:23.383630 end: 1.4 download-retry (duration 00:00:01) [common]
120 00:25:23.383742 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:25:23.383858 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:25:23.383957 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:25:23.384068 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:25:23.384327 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k
125 00:25:23.384510 makedir: /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin
126 00:25:23.384657 makedir: /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/tests
127 00:25:23.384800 makedir: /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/results
128 00:25:23.384933 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-add-keys
129 00:25:23.385104 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-add-sources
130 00:25:23.385257 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-background-process-start
131 00:25:23.385410 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-background-process-stop
132 00:25:23.385562 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-common-functions
133 00:25:23.385738 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-echo-ipv4
134 00:25:23.385916 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-install-packages
135 00:25:23.386092 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-installed-packages
136 00:25:23.386267 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-os-build
137 00:25:23.386440 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-probe-channel
138 00:25:23.386590 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-probe-ip
139 00:25:23.386738 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-target-ip
140 00:25:23.386885 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-target-mac
141 00:25:23.387032 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-target-storage
142 00:25:23.387185 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-test-case
143 00:25:23.387335 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-test-event
144 00:25:23.387511 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-test-feedback
145 00:25:23.387697 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-test-raise
146 00:25:23.387871 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-test-reference
147 00:25:23.388019 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-test-runner
148 00:25:23.388168 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-test-set
149 00:25:23.388319 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-test-shell
150 00:25:23.388472 Updating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-install-packages (oe)
151 00:25:23.388654 Updating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/bin/lava-installed-packages (oe)
152 00:25:23.388827 Creating /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/environment
153 00:25:23.388970 LAVA metadata
154 00:25:23.389053 - LAVA_JOB_ID=11280962
155 00:25:23.389159 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:25:23.389323 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:25:23.389427 skipped lava-vland-overlay
158 00:25:23.389537 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:25:23.389658 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:25:23.389767 skipped lava-multinode-overlay
161 00:25:23.389878 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:25:23.390007 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:25:23.390125 Loading test definitions
164 00:25:23.390268 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:25:23.390382 Using /lava-11280962 at stage 0
166 00:25:23.390830 uuid=11280962_1.5.2.3.1 testdef=None
167 00:25:23.390957 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:25:23.391062 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:25:23.391849 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:25:23.392229 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:25:23.393184 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:25:23.393475 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:25:23.394136 runner path: /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/0/tests/0_dmesg test_uuid 11280962_1.5.2.3.1
176 00:25:23.394310 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:25:23.394570 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 00:25:23.394653 Using /lava-11280962 at stage 1
180 00:25:23.395105 uuid=11280962_1.5.2.3.5 testdef=None
181 00:25:23.395231 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 00:25:23.395359 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 00:25:23.396098 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 00:25:23.396377 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 00:25:23.397551 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 00:25:23.397814 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 00:25:23.398481 runner path: /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/1/tests/1_bootrr test_uuid 11280962_1.5.2.3.5
190 00:25:23.398651 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 00:25:23.398885 Creating lava-test-runner.conf files
193 00:25:23.398988 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/0 for stage 0
194 00:25:23.399130 - 0_dmesg
195 00:25:23.399251 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11280962/lava-overlay-1iwk860k/lava-11280962/1 for stage 1
196 00:25:23.399389 - 1_bootrr
197 00:25:23.399554 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 00:25:23.399681 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 00:25:23.408627 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 00:25:23.408766 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 00:25:23.408902 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 00:25:23.409078 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 00:25:23.409191 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 00:25:23.664670 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 00:25:23.665108 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 00:25:23.665239 extracting modules file /var/lib/lava/dispatcher/tmp/11280962/tftp-deploy-apdiwvfj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11280962/extract-overlay-ramdisk-yw1p82be/ramdisk
207 00:25:23.892302 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 00:25:23.892484 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
209 00:25:23.892698 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11280962/compress-overlay-jifj0vsw/overlay-1.5.2.4.tar.gz to ramdisk
210 00:25:23.892827 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11280962/compress-overlay-jifj0vsw/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11280962/extract-overlay-ramdisk-yw1p82be/ramdisk
211 00:25:23.901204 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 00:25:23.901327 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
213 00:25:23.901416 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 00:25:23.901505 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
215 00:25:23.901643 Building ramdisk /var/lib/lava/dispatcher/tmp/11280962/extract-overlay-ramdisk-yw1p82be/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11280962/extract-overlay-ramdisk-yw1p82be/ramdisk
216 00:25:24.294985 >> 143917 blocks
217 00:25:26.635630 rename /var/lib/lava/dispatcher/tmp/11280962/extract-overlay-ramdisk-yw1p82be/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11280962/tftp-deploy-apdiwvfj/ramdisk/ramdisk.cpio.gz
218 00:25:26.636073 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 00:25:26.636206 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 00:25:26.636310 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 00:25:26.636414 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11280962/tftp-deploy-apdiwvfj/kernel/Image'
222 00:25:39.698286 Returned 0 in 13 seconds
223 00:25:39.798949 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11280962/tftp-deploy-apdiwvfj/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11280962/tftp-deploy-apdiwvfj/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11280962/tftp-deploy-apdiwvfj/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11280962/tftp-deploy-apdiwvfj/kernel/image.itb
224 00:25:40.210784 output: FIT description: Kernel Image image with one or more FDT blobs
225 00:25:40.211161 output: Created: Mon Aug 14 01:25:40 2023
226 00:25:40.211272 output: Image 0 (kernel-1)
227 00:25:40.211371 output: Description:
228 00:25:40.211464 output: Created: Mon Aug 14 01:25:40 2023
229 00:25:40.211590 output: Type: Kernel Image
230 00:25:40.211652 output: Compression: lzma compressed
231 00:25:40.211712 output: Data Size: 11037315 Bytes = 10778.63 KiB = 10.53 MiB
232 00:25:40.211771 output: Architecture: AArch64
233 00:25:40.211830 output: OS: Linux
234 00:25:40.211887 output: Load Address: 0x00000000
235 00:25:40.211944 output: Entry Point: 0x00000000
236 00:25:40.212000 output: Hash algo: crc32
237 00:25:40.212052 output: Hash value: e7f77b4c
238 00:25:40.212105 output: Image 1 (fdt-1)
239 00:25:40.212156 output: Description: mt8192-asurada-spherion-r0
240 00:25:40.212208 output: Created: Mon Aug 14 01:25:40 2023
241 00:25:40.212260 output: Type: Flat Device Tree
242 00:25:40.212312 output: Compression: uncompressed
243 00:25:40.212365 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 00:25:40.212417 output: Architecture: AArch64
245 00:25:40.212468 output: Hash algo: crc32
246 00:25:40.212520 output: Hash value: cc4352de
247 00:25:40.212571 output: Image 2 (ramdisk-1)
248 00:25:40.212622 output: Description: unavailable
249 00:25:40.212673 output: Created: Mon Aug 14 01:25:40 2023
250 00:25:40.212725 output: Type: RAMDisk Image
251 00:25:40.212776 output: Compression: Unknown Compression
252 00:25:40.212827 output: Data Size: 21271556 Bytes = 20773.00 KiB = 20.29 MiB
253 00:25:40.212878 output: Architecture: AArch64
254 00:25:40.212929 output: OS: Linux
255 00:25:40.212980 output: Load Address: unavailable
256 00:25:40.213032 output: Entry Point: unavailable
257 00:25:40.213084 output: Hash algo: crc32
258 00:25:40.213135 output: Hash value: 5aa1c2ff
259 00:25:40.213191 output: Default Configuration: 'conf-1'
260 00:25:40.213291 output: Configuration 0 (conf-1)
261 00:25:40.213386 output: Description: mt8192-asurada-spherion-r0
262 00:25:40.213461 output: Kernel: kernel-1
263 00:25:40.213515 output: Init Ramdisk: ramdisk-1
264 00:25:40.213567 output: FDT: fdt-1
265 00:25:40.213619 output: Loadables: kernel-1
266 00:25:40.213671 output:
267 00:25:40.213872 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
268 00:25:40.213973 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
269 00:25:40.214080 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
270 00:25:40.214175 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
271 00:25:40.214254 No LXC device requested
272 00:25:40.214330 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 00:25:40.214414 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
274 00:25:40.214490 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 00:25:40.214563 Checking files for TFTP limit of 4294967296 bytes.
276 00:25:40.215080 end: 1 tftp-deploy (duration 00:00:18) [common]
277 00:25:40.215180 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 00:25:40.215267 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 00:25:40.215429 substitutions:
280 00:25:40.215548 - {DTB}: 11280962/tftp-deploy-apdiwvfj/dtb/mt8192-asurada-spherion-r0.dtb
281 00:25:40.215629 - {INITRD}: 11280962/tftp-deploy-apdiwvfj/ramdisk/ramdisk.cpio.gz
282 00:25:40.215688 - {KERNEL}: 11280962/tftp-deploy-apdiwvfj/kernel/Image
283 00:25:40.215745 - {LAVA_MAC}: None
284 00:25:40.215800 - {PRESEED_CONFIG}: None
285 00:25:40.215854 - {PRESEED_LOCAL}: None
286 00:25:40.215908 - {RAMDISK}: 11280962/tftp-deploy-apdiwvfj/ramdisk/ramdisk.cpio.gz
287 00:25:40.215962 - {ROOT_PART}: None
288 00:25:40.216015 - {ROOT}: None
289 00:25:40.216067 - {SERVER_IP}: 192.168.201.1
290 00:25:40.216120 - {TEE}: None
291 00:25:40.216173 Parsed boot commands:
292 00:25:40.216224 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 00:25:40.216414 Parsed boot commands: tftpboot 192.168.201.1 11280962/tftp-deploy-apdiwvfj/kernel/image.itb 11280962/tftp-deploy-apdiwvfj/kernel/cmdline
294 00:25:40.216504 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 00:25:40.216588 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 00:25:40.216680 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 00:25:40.216765 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 00:25:40.216834 Not connected, no need to disconnect.
299 00:25:40.216906 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 00:25:40.216990 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 00:25:40.217056 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
302 00:25:40.221881 Setting prompt string to ['lava-test: # ']
303 00:25:40.222558 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 00:25:40.222676 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 00:25:40.222779 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 00:25:40.222871 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 00:25:40.223087 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
308 00:25:45.359451 >> Command sent successfully.
309 00:25:45.361993 Returned 0 in 5 seconds
310 00:25:45.462410 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 00:25:45.462771 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 00:25:45.462873 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 00:25:45.462968 Setting prompt string to 'Starting depthcharge on Spherion...'
315 00:25:45.463038 Changing prompt to 'Starting depthcharge on Spherion...'
316 00:25:45.463107 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 00:25:45.463380 [Enter `^Ec?' for help]
318 00:25:45.639237
319 00:25:45.639402
320 00:25:45.639469 F0: 102B 0000
321 00:25:45.639577
322 00:25:45.639667 F3: 1001 0000 [0200]
323 00:25:45.639755
324 00:25:45.642905 F3: 1001 0000
325 00:25:45.643036
326 00:25:45.643132 F7: 102D 0000
327 00:25:45.643222
328 00:25:45.643310 F1: 0000 0000
329 00:25:45.643396
330 00:25:45.646715 V0: 0000 0000 [0001]
331 00:25:45.646808
332 00:25:45.646874 00: 0007 8000
333 00:25:45.646947
334 00:25:45.650518 01: 0000 0000
335 00:25:45.650619
336 00:25:45.650685 BP: 0C00 0209 [0000]
337 00:25:45.650746
338 00:25:45.650805 G0: 1182 0000
339 00:25:45.653890
340 00:25:45.653980 EC: 0000 0021 [4000]
341 00:25:45.654046
342 00:25:45.657509 S7: 0000 0000 [0000]
343 00:25:45.657601
344 00:25:45.657668 CC: 0000 0000 [0001]
345 00:25:45.657728
346 00:25:45.660730 T0: 0000 0040 [010F]
347 00:25:45.660857
348 00:25:45.660956 Jump to BL
349 00:25:45.661051
350 00:25:45.685543
351 00:25:45.685746
352 00:25:45.685850
353 00:25:45.693790 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 00:25:45.697282 ARM64: Exception handlers installed.
355 00:25:45.700979 ARM64: Testing exception
356 00:25:45.704906 ARM64: Done test exception
357 00:25:45.709039 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 00:25:45.720081 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 00:25:45.726475 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 00:25:45.737001 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 00:25:45.743729 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 00:25:45.753961 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 00:25:45.763852 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 00:25:45.770715 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 00:25:45.788507 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 00:25:45.791784 WDT: Last reset was cold boot
367 00:25:45.795365 SPI1(PAD0) initialized at 2873684 Hz
368 00:25:45.798517 SPI5(PAD0) initialized at 992727 Hz
369 00:25:45.801870 VBOOT: Loading verstage.
370 00:25:45.808669 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 00:25:45.812391 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 00:25:45.815329 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 00:25:45.819013 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 00:25:45.826149 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 00:25:45.832663 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 00:25:45.844547 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 00:25:45.844705
378 00:25:45.844806
379 00:25:45.854714 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 00:25:45.857766 ARM64: Exception handlers installed.
381 00:25:45.857888 ARM64: Testing exception
382 00:25:45.861581 ARM64: Done test exception
383 00:25:45.864564 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 00:25:45.871003 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 00:25:45.884709 Probing TPM: . done!
386 00:25:45.884863 TPM ready after 0 ms
387 00:25:45.892455 Connected to device vid:did:rid of 1ae0:0028:00
388 00:25:45.899167 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
389 00:25:46.007551 Initialized TPM device CR50 revision 0
390 00:25:46.023787 tlcl_send_startup: Startup return code is 0
391 00:25:46.023983 TPM: setup succeeded
392 00:25:46.036618 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 00:25:46.043570 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 00:25:46.055346 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 00:25:46.065191 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 00:25:46.068950 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 00:25:46.072671 in-header: 03 07 00 00 08 00 00 00
398 00:25:46.076532 in-data: aa e4 47 04 13 02 00 00
399 00:25:46.076661 Chrome EC: UHEPI supported
400 00:25:46.083700 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 00:25:46.087598 in-header: 03 95 00 00 08 00 00 00
402 00:25:46.091436 in-data: 18 20 20 08 00 00 00 00
403 00:25:46.091598 Phase 1
404 00:25:46.095060 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 00:25:46.102698 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 00:25:46.109378 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 00:25:46.113068 Recovery requested (1009000e)
408 00:25:46.118434 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 00:25:46.124181 tlcl_extend: response is 0
410 00:25:46.132379 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 00:25:46.137452 tlcl_extend: response is 0
412 00:25:46.144301 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 00:25:46.165391 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
414 00:25:46.171905 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 00:25:46.172032
416 00:25:46.172142
417 00:25:46.183080 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 00:25:46.186062 ARM64: Exception handlers installed.
419 00:25:46.186187 ARM64: Testing exception
420 00:25:46.189463 ARM64: Done test exception
421 00:25:46.210979 pmic_efuse_setting: Set efuses in 11 msecs
422 00:25:46.214316 pmwrap_interface_init: Select PMIF_VLD_RDY
423 00:25:46.218448 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 00:25:46.225792 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 00:25:46.229450 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 00:25:46.232969 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 00:25:46.240013 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 00:25:46.243934 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 00:25:46.247111 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 00:25:46.254994 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 00:25:46.258478 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 00:25:46.262551 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 00:25:46.266332 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 00:25:46.273919 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 00:25:46.277414 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 00:25:46.281087 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 00:25:46.288712 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 00:25:46.295826 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 00:25:46.299276 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 00:25:46.306569 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 00:25:46.310597 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 00:25:46.317442 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 00:25:46.321305 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 00:25:46.329047 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 00:25:46.332460 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 00:25:46.340392 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 00:25:46.344240 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 00:25:46.351171 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 00:25:46.355451 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 00:25:46.359227 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 00:25:46.366088 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 00:25:46.369878 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 00:25:46.373612 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 00:25:46.381146 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 00:25:46.384998 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 00:25:46.388533 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 00:25:46.396213 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 00:25:46.399114 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 00:25:46.403407 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 00:25:46.410410 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 00:25:46.414397 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 00:25:46.418304 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 00:25:46.421492 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 00:25:46.425861 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 00:25:46.432828 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 00:25:46.436497 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 00:25:46.440100 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 00:25:46.443667 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 00:25:46.447492 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 00:25:46.454930 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 00:25:46.458605 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 00:25:46.462441 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 00:25:46.466149 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 00:25:46.473963 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 00:25:46.481914 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 00:25:46.485187 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 00:25:46.495825 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 00:25:46.504130 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 00:25:46.508109 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 00:25:46.511735 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 00:25:46.514793 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 00:25:46.523964 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x39
483 00:25:46.527414 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 00:25:46.532128 [RTC]rtc_osc_init,62: osc32con val = 0xde70
485 00:25:46.539140 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 00:25:46.548257 [RTC]rtc_get_frequency_meter,154: input=15, output=758
487 00:25:46.558287 [RTC]rtc_get_frequency_meter,154: input=23, output=941
488 00:25:46.567186 [RTC]rtc_get_frequency_meter,154: input=19, output=851
489 00:25:46.576553 [RTC]rtc_get_frequency_meter,154: input=17, output=805
490 00:25:46.586243 [RTC]rtc_get_frequency_meter,154: input=16, output=781
491 00:25:46.595875 [RTC]rtc_get_frequency_meter,154: input=16, output=782
492 00:25:46.606126 [RTC]rtc_get_frequency_meter,154: input=17, output=805
493 00:25:46.610062 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
494 00:25:46.614266 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
495 00:25:46.617452 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 00:25:46.625028 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 00:25:46.629165 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 00:25:46.632259 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 00:25:46.632344 ADC[4]: Raw value=906573 ID=7
500 00:25:46.636155 ADC[3]: Raw value=213441 ID=1
501 00:25:46.640195 RAM Code: 0x71
502 00:25:46.643677 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 00:25:46.647375 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 00:25:46.654772 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 00:25:46.661963 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 00:25:46.665803 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 00:25:46.669240 in-header: 03 07 00 00 08 00 00 00
508 00:25:46.673201 in-data: aa e4 47 04 13 02 00 00
509 00:25:46.677439 Chrome EC: UHEPI supported
510 00:25:46.680183 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 00:25:46.685282 in-header: 03 95 00 00 08 00 00 00
512 00:25:46.688899 in-data: 18 20 20 08 00 00 00 00
513 00:25:46.692783 MRC: failed to locate region type 0.
514 00:25:46.700337 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 00:25:46.700442 DRAM-K: Running full calibration
516 00:25:46.708094 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 00:25:46.711804 header.status = 0x0
518 00:25:46.715487 header.version = 0x6 (expected: 0x6)
519 00:25:46.715586 header.size = 0xd00 (expected: 0xd00)
520 00:25:46.719894 header.flags = 0x0
521 00:25:46.723147 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 00:25:46.743654 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
523 00:25:46.751229 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 00:25:46.751341 dram_init: ddr_geometry: 2
525 00:25:46.754648 [EMI] MDL number = 2
526 00:25:46.754733 [EMI] Get MDL freq = 0
527 00:25:46.757963 dram_init: ddr_type: 0
528 00:25:46.761813 is_discrete_lpddr4: 1
529 00:25:46.764823 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 00:25:46.764910
531 00:25:46.764996
532 00:25:46.765077 [Bian_co] ETT version 0.0.0.1
533 00:25:46.771612 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 00:25:46.771701
535 00:25:46.775231 dramc_set_vcore_voltage set vcore to 650000
536 00:25:46.779022 Read voltage for 800, 4
537 00:25:46.779111 Vio18 = 0
538 00:25:46.779177 Vcore = 650000
539 00:25:46.782570 Vdram = 0
540 00:25:46.782685 Vddq = 0
541 00:25:46.782772 Vmddr = 0
542 00:25:46.786359 dram_init: config_dvfs: 1
543 00:25:46.790231 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 00:25:46.794193 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 00:25:46.797293 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
546 00:25:46.803901 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
547 00:25:46.807736 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
548 00:25:46.811111 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
549 00:25:46.814665 MEM_TYPE=3, freq_sel=18
550 00:25:46.814761 sv_algorithm_assistance_LP4_1600
551 00:25:46.821555 ============ PULL DRAM RESETB DOWN ============
552 00:25:46.824945 ========== PULL DRAM RESETB DOWN end =========
553 00:25:46.828323 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 00:25:46.831635 ===================================
555 00:25:46.834800 LPDDR4 DRAM CONFIGURATION
556 00:25:46.838160 ===================================
557 00:25:46.838251 EX_ROW_EN[0] = 0x0
558 00:25:46.842100 EX_ROW_EN[1] = 0x0
559 00:25:46.842216 LP4Y_EN = 0x0
560 00:25:46.846242 WORK_FSP = 0x0
561 00:25:46.846339 WL = 0x2
562 00:25:46.849584 RL = 0x2
563 00:25:46.849675 BL = 0x2
564 00:25:46.852567 RPST = 0x0
565 00:25:46.852653 RD_PRE = 0x0
566 00:25:46.855745 WR_PRE = 0x1
567 00:25:46.855831 WR_PST = 0x0
568 00:25:46.858898 DBI_WR = 0x0
569 00:25:46.858983 DBI_RD = 0x0
570 00:25:46.862188 OTF = 0x1
571 00:25:46.865896 ===================================
572 00:25:46.869381 ===================================
573 00:25:46.869471 ANA top config
574 00:25:46.872490 ===================================
575 00:25:46.875706 DLL_ASYNC_EN = 0
576 00:25:46.879315 ALL_SLAVE_EN = 1
577 00:25:46.882664 NEW_RANK_MODE = 1
578 00:25:46.882757 DLL_IDLE_MODE = 1
579 00:25:46.885795 LP45_APHY_COMB_EN = 1
580 00:25:46.888994 TX_ODT_DIS = 1
581 00:25:46.892336 NEW_8X_MODE = 1
582 00:25:46.895934 ===================================
583 00:25:46.898951 ===================================
584 00:25:46.902296 data_rate = 1600
585 00:25:46.902386 CKR = 1
586 00:25:46.905614 DQ_P2S_RATIO = 8
587 00:25:46.909628 ===================================
588 00:25:46.913003 CA_P2S_RATIO = 8
589 00:25:46.916770 DQ_CA_OPEN = 0
590 00:25:46.916868 DQ_SEMI_OPEN = 0
591 00:25:46.920468 CA_SEMI_OPEN = 0
592 00:25:46.924357 CA_FULL_RATE = 0
593 00:25:46.927624 DQ_CKDIV4_EN = 1
594 00:25:46.927720 CA_CKDIV4_EN = 1
595 00:25:46.931490 CA_PREDIV_EN = 0
596 00:25:46.935074 PH8_DLY = 0
597 00:25:46.938786 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 00:25:46.938880 DQ_AAMCK_DIV = 4
599 00:25:46.942971 CA_AAMCK_DIV = 4
600 00:25:46.945885 CA_ADMCK_DIV = 4
601 00:25:46.949278 DQ_TRACK_CA_EN = 0
602 00:25:46.952744 CA_PICK = 800
603 00:25:46.952834 CA_MCKIO = 800
604 00:25:46.955795 MCKIO_SEMI = 0
605 00:25:46.959352 PLL_FREQ = 3068
606 00:25:46.962747 DQ_UI_PI_RATIO = 32
607 00:25:46.966082 CA_UI_PI_RATIO = 0
608 00:25:46.969212 ===================================
609 00:25:46.972562 ===================================
610 00:25:46.976285 memory_type:LPDDR4
611 00:25:46.976370 GP_NUM : 10
612 00:25:46.979456 SRAM_EN : 1
613 00:25:46.979550 MD32_EN : 0
614 00:25:46.982751 ===================================
615 00:25:46.985704 [ANA_INIT] >>>>>>>>>>>>>>
616 00:25:46.989173 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 00:25:46.992512 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 00:25:46.996395 ===================================
619 00:25:46.999305 data_rate = 1600,PCW = 0X7600
620 00:25:47.002375 ===================================
621 00:25:47.006056 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 00:25:47.012457 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 00:25:47.015930 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 00:25:47.022618 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 00:25:47.025898 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 00:25:47.029325 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 00:25:47.029415 [ANA_INIT] flow start
628 00:25:47.032615 [ANA_INIT] PLL >>>>>>>>
629 00:25:47.032702 [ANA_INIT] PLL <<<<<<<<
630 00:25:47.036058 [ANA_INIT] MIDPI >>>>>>>>
631 00:25:47.039268 [ANA_INIT] MIDPI <<<<<<<<
632 00:25:47.042989 [ANA_INIT] DLL >>>>>>>>
633 00:25:47.043107 [ANA_INIT] flow end
634 00:25:47.046203 ============ LP4 DIFF to SE enter ============
635 00:25:47.052571 ============ LP4 DIFF to SE exit ============
636 00:25:47.052664 [ANA_INIT] <<<<<<<<<<<<<
637 00:25:47.055869 [Flow] Enable top DCM control >>>>>
638 00:25:47.059926 [Flow] Enable top DCM control <<<<<
639 00:25:47.063131 Enable DLL master slave shuffle
640 00:25:47.069690 ==============================================================
641 00:25:47.069779 Gating Mode config
642 00:25:47.076343 ==============================================================
643 00:25:47.079426 Config description:
644 00:25:47.086151 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 00:25:47.093143 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 00:25:47.099434 SELPH_MODE 0: By rank 1: By Phase
647 00:25:47.106239 ==============================================================
648 00:25:47.106343 GAT_TRACK_EN = 1
649 00:25:47.109934 RX_GATING_MODE = 2
650 00:25:47.112904 RX_GATING_TRACK_MODE = 2
651 00:25:47.116362 SELPH_MODE = 1
652 00:25:47.119673 PICG_EARLY_EN = 1
653 00:25:47.123466 VALID_LAT_VALUE = 1
654 00:25:47.129958 ==============================================================
655 00:25:47.133331 Enter into Gating configuration >>>>
656 00:25:47.136505 Exit from Gating configuration <<<<
657 00:25:47.139514 Enter into DVFS_PRE_config >>>>>
658 00:25:47.149786 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 00:25:47.153070 Exit from DVFS_PRE_config <<<<<
660 00:25:47.156456 Enter into PICG configuration >>>>
661 00:25:47.159730 Exit from PICG configuration <<<<
662 00:25:47.159819 [RX_INPUT] configuration >>>>>
663 00:25:47.163087 [RX_INPUT] configuration <<<<<
664 00:25:47.169691 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 00:25:47.173160 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 00:25:47.180246 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 00:25:47.186766 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 00:25:47.193258 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 00:25:47.199768 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 00:25:47.203655 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 00:25:47.207132 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 00:25:47.209967 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 00:25:47.216832 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 00:25:47.220356 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 00:25:47.223316 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 00:25:47.226815 ===================================
677 00:25:47.229981 LPDDR4 DRAM CONFIGURATION
678 00:25:47.233498 ===================================
679 00:25:47.236750 EX_ROW_EN[0] = 0x0
680 00:25:47.236836 EX_ROW_EN[1] = 0x0
681 00:25:47.240213 LP4Y_EN = 0x0
682 00:25:47.240299 WORK_FSP = 0x0
683 00:25:47.243460 WL = 0x2
684 00:25:47.243587 RL = 0x2
685 00:25:47.247015 BL = 0x2
686 00:25:47.247101 RPST = 0x0
687 00:25:47.250074 RD_PRE = 0x0
688 00:25:47.250158 WR_PRE = 0x1
689 00:25:47.253752 WR_PST = 0x0
690 00:25:47.253836 DBI_WR = 0x0
691 00:25:47.256930 DBI_RD = 0x0
692 00:25:47.257014 OTF = 0x1
693 00:25:47.260146 ===================================
694 00:25:47.263458 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 00:25:47.270418 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 00:25:47.273504 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 00:25:47.276825 ===================================
698 00:25:47.280376 LPDDR4 DRAM CONFIGURATION
699 00:25:47.283512 ===================================
700 00:25:47.283606 EX_ROW_EN[0] = 0x10
701 00:25:47.286858 EX_ROW_EN[1] = 0x0
702 00:25:47.290086 LP4Y_EN = 0x0
703 00:25:47.290174 WORK_FSP = 0x0
704 00:25:47.293830 WL = 0x2
705 00:25:47.293919 RL = 0x2
706 00:25:47.297261 BL = 0x2
707 00:25:47.297346 RPST = 0x0
708 00:25:47.300300 RD_PRE = 0x0
709 00:25:47.300385 WR_PRE = 0x1
710 00:25:47.303647 WR_PST = 0x0
711 00:25:47.303735 DBI_WR = 0x0
712 00:25:47.306763 DBI_RD = 0x0
713 00:25:47.306839 OTF = 0x1
714 00:25:47.310027 ===================================
715 00:25:47.316786 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 00:25:47.321080 nWR fixed to 40
717 00:25:47.324357 [ModeRegInit_LP4] CH0 RK0
718 00:25:47.324449 [ModeRegInit_LP4] CH0 RK1
719 00:25:47.327895 [ModeRegInit_LP4] CH1 RK0
720 00:25:47.331193 [ModeRegInit_LP4] CH1 RK1
721 00:25:47.331280 match AC timing 13
722 00:25:47.337300 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 00:25:47.340780 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 00:25:47.344176 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 00:25:47.350954 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 00:25:47.354484 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 00:25:47.354603 [EMI DOE] emi_dcm 0
728 00:25:47.360787 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 00:25:47.360877 ==
730 00:25:47.364192 Dram Type= 6, Freq= 0, CH_0, rank 0
731 00:25:47.367300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 00:25:47.367384 ==
733 00:25:47.374101 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 00:25:47.380762 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 00:25:47.388458 [CA 0] Center 36 (6~67) winsize 62
736 00:25:47.391577 [CA 1] Center 36 (6~67) winsize 62
737 00:25:47.395113 [CA 2] Center 34 (4~65) winsize 62
738 00:25:47.398200 [CA 3] Center 34 (4~64) winsize 61
739 00:25:47.401651 [CA 4] Center 33 (3~64) winsize 62
740 00:25:47.404936 [CA 5] Center 32 (2~62) winsize 61
741 00:25:47.405020
742 00:25:47.408254 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 00:25:47.408338
744 00:25:47.411751 [CATrainingPosCal] consider 1 rank data
745 00:25:47.415181 u2DelayCellTimex100 = 270/100 ps
746 00:25:47.418140 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
747 00:25:47.421438 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
748 00:25:47.428177 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
749 00:25:47.431603 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
750 00:25:47.435045 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
751 00:25:47.438349 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
752 00:25:47.438436
753 00:25:47.441830 CA PerBit enable=1, Macro0, CA PI delay=32
754 00:25:47.441915
755 00:25:47.445045 [CBTSetCACLKResult] CA Dly = 32
756 00:25:47.445132 CS Dly: 5 (0~36)
757 00:25:47.445198 ==
758 00:25:47.448432 Dram Type= 6, Freq= 0, CH_0, rank 1
759 00:25:47.455186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 00:25:47.455273 ==
761 00:25:47.458967 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 00:25:47.465255 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 00:25:47.474646 [CA 0] Center 36 (6~67) winsize 62
764 00:25:47.478049 [CA 1] Center 36 (6~67) winsize 62
765 00:25:47.481016 [CA 2] Center 34 (4~65) winsize 62
766 00:25:47.484304 [CA 3] Center 33 (3~64) winsize 62
767 00:25:47.488481 [CA 4] Center 32 (2~63) winsize 62
768 00:25:47.492202 [CA 5] Center 32 (2~63) winsize 62
769 00:25:47.492294
770 00:25:47.496215 [CmdBusTrainingLP45] Vref(ca) range 1: 32
771 00:25:47.496304
772 00:25:47.500029 [CATrainingPosCal] consider 2 rank data
773 00:25:47.503115 u2DelayCellTimex100 = 270/100 ps
774 00:25:47.506488 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
775 00:25:47.509922 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
776 00:25:47.514101 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
777 00:25:47.517447 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
778 00:25:47.521026 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
779 00:25:47.524617 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
780 00:25:47.524708
781 00:25:47.527759 CA PerBit enable=1, Macro0, CA PI delay=32
782 00:25:47.527845
783 00:25:47.531076 [CBTSetCACLKResult] CA Dly = 32
784 00:25:47.531160 CS Dly: 5 (0~36)
785 00:25:47.531226
786 00:25:47.537923 ----->DramcWriteLeveling(PI) begin...
787 00:25:47.538018 ==
788 00:25:47.541170 Dram Type= 6, Freq= 0, CH_0, rank 0
789 00:25:47.544458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 00:25:47.544577 ==
791 00:25:47.547418 Write leveling (Byte 0): 32 => 32
792 00:25:47.551107 Write leveling (Byte 1): 31 => 31
793 00:25:47.554461 DramcWriteLeveling(PI) end<-----
794 00:25:47.554549
795 00:25:47.554614 ==
796 00:25:47.557425 Dram Type= 6, Freq= 0, CH_0, rank 0
797 00:25:47.560789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 00:25:47.560877 ==
799 00:25:47.564614 [Gating] SW mode calibration
800 00:25:47.570775 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 00:25:47.577462 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 00:25:47.581057 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 00:25:47.584378 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
804 00:25:47.587848 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
805 00:25:47.594329 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 00:25:47.597704 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 00:25:47.601010 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 00:25:47.607887 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 00:25:47.610965 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 00:25:47.614476 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 00:25:47.621060 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 00:25:47.624259 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 00:25:47.627613 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 00:25:47.634590 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 00:25:47.637884 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 00:25:47.641238 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 00:25:47.647991 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 00:25:47.651075 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
819 00:25:47.654467 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
820 00:25:47.657747 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
821 00:25:47.664680 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 00:25:47.668401 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 00:25:47.671582 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 00:25:47.678178 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 00:25:47.681459 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:25:47.684766 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 00:25:47.691957 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 00:25:47.694852 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (1 1) (0 0)
829 00:25:47.698223 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
830 00:25:47.704774 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 00:25:47.707943 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 00:25:47.711525 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 00:25:47.718192 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 00:25:47.721429 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 00:25:47.725132 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
836 00:25:47.728154 0 10 8 | B1->B0 | 3030 2727 | 0 0 | (0 1) (1 0)
837 00:25:47.735079 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 00:25:47.738559 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 00:25:47.741867 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 00:25:47.748644 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 00:25:47.751802 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 00:25:47.755411 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 00:25:47.762118 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
844 00:25:47.765337 0 11 8 | B1->B0 | 3030 3f3f | 0 0 | (1 1) (0 0)
845 00:25:47.768431 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
846 00:25:47.775463 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 00:25:47.778699 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 00:25:47.781698 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 00:25:47.788517 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 00:25:47.791850 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 00:25:47.795412 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
852 00:25:47.798470 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
853 00:25:47.805565 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
854 00:25:47.808724 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 00:25:47.811944 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 00:25:47.818669 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 00:25:47.822484 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 00:25:47.825484 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 00:25:47.832140 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 00:25:47.835350 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 00:25:47.839414 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 00:25:47.842922 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 00:25:47.849582 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 00:25:47.853079 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 00:25:47.856122 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 00:25:47.863093 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 00:25:47.866450 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
868 00:25:47.869542 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
869 00:25:47.876733 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 00:25:47.876832 Total UI for P1: 0, mck2ui 16
871 00:25:47.879954 best dqsien dly found for B0: ( 0, 14, 6)
872 00:25:47.883059 Total UI for P1: 0, mck2ui 16
873 00:25:47.886311 best dqsien dly found for B1: ( 0, 14, 10)
874 00:25:47.890071 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
875 00:25:47.896659 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
876 00:25:47.896753
877 00:25:47.900130 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
878 00:25:47.903302 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
879 00:25:47.906806 [Gating] SW calibration Done
880 00:25:47.906899 ==
881 00:25:47.910096 Dram Type= 6, Freq= 0, CH_0, rank 0
882 00:25:47.913870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
883 00:25:47.913961 ==
884 00:25:47.914038 RX Vref Scan: 0
885 00:25:47.914103
886 00:25:47.916587 RX Vref 0 -> 0, step: 1
887 00:25:47.916673
888 00:25:47.920512 RX Delay -130 -> 252, step: 16
889 00:25:47.923402 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
890 00:25:47.927027 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
891 00:25:47.933621 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
892 00:25:47.937009 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
893 00:25:47.941058 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
894 00:25:47.943154 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
895 00:25:47.946850 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
896 00:25:47.950192 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
897 00:25:47.956603 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
898 00:25:47.960053 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
899 00:25:47.963772 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
900 00:25:47.967344 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
901 00:25:47.970115 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
902 00:25:47.976959 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
903 00:25:47.980201 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
904 00:25:47.983627 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
905 00:25:47.983721 ==
906 00:25:47.987260 Dram Type= 6, Freq= 0, CH_0, rank 0
907 00:25:47.990554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 00:25:47.990644 ==
909 00:25:47.993649 DQS Delay:
910 00:25:47.993734 DQS0 = 0, DQS1 = 0
911 00:25:47.997083 DQM Delay:
912 00:25:47.997171 DQM0 = 88, DQM1 = 82
913 00:25:47.997238 DQ Delay:
914 00:25:48.000523 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
915 00:25:48.004131 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
916 00:25:48.007430 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
917 00:25:48.010604 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
918 00:25:48.010692
919 00:25:48.010758
920 00:25:48.010818 ==
921 00:25:48.013911 Dram Type= 6, Freq= 0, CH_0, rank 0
922 00:25:48.020633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 00:25:48.020732 ==
924 00:25:48.020800
925 00:25:48.020860
926 00:25:48.020916 TX Vref Scan disable
927 00:25:48.024591 == TX Byte 0 ==
928 00:25:48.027789 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
929 00:25:48.031123 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
930 00:25:48.034675 == TX Byte 1 ==
931 00:25:48.037670 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
932 00:25:48.040898 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
933 00:25:48.044429 ==
934 00:25:48.047573 Dram Type= 6, Freq= 0, CH_0, rank 0
935 00:25:48.051556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 00:25:48.051662 ==
937 00:25:48.063746 TX Vref=22, minBit 4, minWin=27, winSum=445
938 00:25:48.066764 TX Vref=24, minBit 4, minWin=27, winSum=451
939 00:25:48.070539 TX Vref=26, minBit 0, minWin=28, winSum=456
940 00:25:48.073710 TX Vref=28, minBit 0, minWin=28, winSum=456
941 00:25:48.077298 TX Vref=30, minBit 0, minWin=28, winSum=457
942 00:25:48.080448 TX Vref=32, minBit 0, minWin=28, winSum=455
943 00:25:48.086919 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
944 00:25:48.087014
945 00:25:48.090066 Final TX Range 1 Vref 30
946 00:25:48.090151
947 00:25:48.090217 ==
948 00:25:48.093539 Dram Type= 6, Freq= 0, CH_0, rank 0
949 00:25:48.097206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 00:25:48.097290 ==
951 00:25:48.097356
952 00:25:48.097417
953 00:25:48.100577 TX Vref Scan disable
954 00:25:48.103764 == TX Byte 0 ==
955 00:25:48.106957 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
956 00:25:48.110431 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
957 00:25:48.114149 == TX Byte 1 ==
958 00:25:48.117218 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
959 00:25:48.120450 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
960 00:25:48.120533
961 00:25:48.123629 [DATLAT]
962 00:25:48.123711 Freq=800, CH0 RK0
963 00:25:48.123777
964 00:25:48.127137 DATLAT Default: 0xa
965 00:25:48.127219 0, 0xFFFF, sum = 0
966 00:25:48.130695 1, 0xFFFF, sum = 0
967 00:25:48.130783 2, 0xFFFF, sum = 0
968 00:25:48.133837 3, 0xFFFF, sum = 0
969 00:25:48.133920 4, 0xFFFF, sum = 0
970 00:25:48.137042 5, 0xFFFF, sum = 0
971 00:25:48.137126 6, 0xFFFF, sum = 0
972 00:25:48.140478 7, 0xFFFF, sum = 0
973 00:25:48.140562 8, 0xFFFF, sum = 0
974 00:25:48.143803 9, 0x0, sum = 1
975 00:25:48.143892 10, 0x0, sum = 2
976 00:25:48.147072 11, 0x0, sum = 3
977 00:25:48.147156 12, 0x0, sum = 4
978 00:25:48.150311 best_step = 10
979 00:25:48.150399
980 00:25:48.150465 ==
981 00:25:48.153776 Dram Type= 6, Freq= 0, CH_0, rank 0
982 00:25:48.157768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 00:25:48.157863 ==
984 00:25:48.157928 RX Vref Scan: 1
985 00:25:48.157989
986 00:25:48.161425 Set Vref Range= 32 -> 127
987 00:25:48.161507
988 00:25:48.164785 RX Vref 32 -> 127, step: 1
989 00:25:48.164872
990 00:25:48.168570 RX Delay -79 -> 252, step: 8
991 00:25:48.168660
992 00:25:48.168724 Set Vref, RX VrefLevel [Byte0]: 32
993 00:25:48.171991 [Byte1]: 32
994 00:25:48.176313
995 00:25:48.176402 Set Vref, RX VrefLevel [Byte0]: 33
996 00:25:48.179590 [Byte1]: 33
997 00:25:48.184138
998 00:25:48.184220 Set Vref, RX VrefLevel [Byte0]: 34
999 00:25:48.187476 [Byte1]: 34
1000 00:25:48.191419
1001 00:25:48.191551 Set Vref, RX VrefLevel [Byte0]: 35
1002 00:25:48.194435 [Byte1]: 35
1003 00:25:48.198810
1004 00:25:48.198892 Set Vref, RX VrefLevel [Byte0]: 36
1005 00:25:48.202253 [Byte1]: 36
1006 00:25:48.206330
1007 00:25:48.206411 Set Vref, RX VrefLevel [Byte0]: 37
1008 00:25:48.209693 [Byte1]: 37
1009 00:25:48.213529
1010 00:25:48.213611 Set Vref, RX VrefLevel [Byte0]: 38
1011 00:25:48.216976 [Byte1]: 38
1012 00:25:48.221542
1013 00:25:48.221622 Set Vref, RX VrefLevel [Byte0]: 39
1014 00:25:48.224736 [Byte1]: 39
1015 00:25:48.229170
1016 00:25:48.229252 Set Vref, RX VrefLevel [Byte0]: 40
1017 00:25:48.232207 [Byte1]: 40
1018 00:25:48.236372
1019 00:25:48.236452 Set Vref, RX VrefLevel [Byte0]: 41
1020 00:25:48.239848 [Byte1]: 41
1021 00:25:48.244107
1022 00:25:48.244187 Set Vref, RX VrefLevel [Byte0]: 42
1023 00:25:48.247204 [Byte1]: 42
1024 00:25:48.251746
1025 00:25:48.251831 Set Vref, RX VrefLevel [Byte0]: 43
1026 00:25:48.254830 [Byte1]: 43
1027 00:25:48.258847
1028 00:25:48.258950 Set Vref, RX VrefLevel [Byte0]: 44
1029 00:25:48.262246 [Byte1]: 44
1030 00:25:48.266584
1031 00:25:48.266665 Set Vref, RX VrefLevel [Byte0]: 45
1032 00:25:48.269897 [Byte1]: 45
1033 00:25:48.274484
1034 00:25:48.274565 Set Vref, RX VrefLevel [Byte0]: 46
1035 00:25:48.277334 [Byte1]: 46
1036 00:25:48.281631
1037 00:25:48.281712 Set Vref, RX VrefLevel [Byte0]: 47
1038 00:25:48.285177 [Byte1]: 47
1039 00:25:48.289176
1040 00:25:48.289257 Set Vref, RX VrefLevel [Byte0]: 48
1041 00:25:48.292803 [Byte1]: 48
1042 00:25:48.296742
1043 00:25:48.296823 Set Vref, RX VrefLevel [Byte0]: 49
1044 00:25:48.300226 [Byte1]: 49
1045 00:25:48.304289
1046 00:25:48.304393 Set Vref, RX VrefLevel [Byte0]: 50
1047 00:25:48.307548 [Byte1]: 50
1048 00:25:48.311840
1049 00:25:48.311921 Set Vref, RX VrefLevel [Byte0]: 51
1050 00:25:48.315163 [Byte1]: 51
1051 00:25:48.319787
1052 00:25:48.319867 Set Vref, RX VrefLevel [Byte0]: 52
1053 00:25:48.322704 [Byte1]: 52
1054 00:25:48.327127
1055 00:25:48.327209 Set Vref, RX VrefLevel [Byte0]: 53
1056 00:25:48.330548 [Byte1]: 53
1057 00:25:48.334603
1058 00:25:48.334693 Set Vref, RX VrefLevel [Byte0]: 54
1059 00:25:48.337802 [Byte1]: 54
1060 00:25:48.342096
1061 00:25:48.342177 Set Vref, RX VrefLevel [Byte0]: 55
1062 00:25:48.345430 [Byte1]: 55
1063 00:25:48.349664
1064 00:25:48.349747 Set Vref, RX VrefLevel [Byte0]: 56
1065 00:25:48.352836 [Byte1]: 56
1066 00:25:48.357233
1067 00:25:48.357313 Set Vref, RX VrefLevel [Byte0]: 57
1068 00:25:48.360454 [Byte1]: 57
1069 00:25:48.364580
1070 00:25:48.364661 Set Vref, RX VrefLevel [Byte0]: 58
1071 00:25:48.368189 [Byte1]: 58
1072 00:25:48.372177
1073 00:25:48.372258 Set Vref, RX VrefLevel [Byte0]: 59
1074 00:25:48.375796 [Byte1]: 59
1075 00:25:48.380035
1076 00:25:48.380116 Set Vref, RX VrefLevel [Byte0]: 60
1077 00:25:48.383637 [Byte1]: 60
1078 00:25:48.387668
1079 00:25:48.387749 Set Vref, RX VrefLevel [Byte0]: 61
1080 00:25:48.390975 [Byte1]: 61
1081 00:25:48.394979
1082 00:25:48.395059 Set Vref, RX VrefLevel [Byte0]: 62
1083 00:25:48.398072 [Byte1]: 62
1084 00:25:48.402361
1085 00:25:48.402441 Set Vref, RX VrefLevel [Byte0]: 63
1086 00:25:48.405864 [Byte1]: 63
1087 00:25:48.410253
1088 00:25:48.410342 Set Vref, RX VrefLevel [Byte0]: 64
1089 00:25:48.414030 [Byte1]: 64
1090 00:25:48.417808
1091 00:25:48.417889 Set Vref, RX VrefLevel [Byte0]: 65
1092 00:25:48.421078 [Byte1]: 65
1093 00:25:48.425144
1094 00:25:48.425227 Set Vref, RX VrefLevel [Byte0]: 66
1095 00:25:48.428693 [Byte1]: 66
1096 00:25:48.432462
1097 00:25:48.432544 Set Vref, RX VrefLevel [Byte0]: 67
1098 00:25:48.436196 [Byte1]: 67
1099 00:25:48.440503
1100 00:25:48.440584 Set Vref, RX VrefLevel [Byte0]: 68
1101 00:25:48.443486 [Byte1]: 68
1102 00:25:48.447890
1103 00:25:48.447970 Set Vref, RX VrefLevel [Byte0]: 69
1104 00:25:48.451200 [Byte1]: 69
1105 00:25:48.455482
1106 00:25:48.455600 Set Vref, RX VrefLevel [Byte0]: 70
1107 00:25:48.459018 [Byte1]: 70
1108 00:25:48.462810
1109 00:25:48.462890 Set Vref, RX VrefLevel [Byte0]: 71
1110 00:25:48.466369 [Byte1]: 71
1111 00:25:48.470442
1112 00:25:48.470521 Set Vref, RX VrefLevel [Byte0]: 72
1113 00:25:48.473979 [Byte1]: 72
1114 00:25:48.477950
1115 00:25:48.478030 Set Vref, RX VrefLevel [Byte0]: 73
1116 00:25:48.481538 [Byte1]: 73
1117 00:25:48.485557
1118 00:25:48.485637 Set Vref, RX VrefLevel [Byte0]: 74
1119 00:25:48.488964 [Byte1]: 74
1120 00:25:48.493360
1121 00:25:48.493442 Set Vref, RX VrefLevel [Byte0]: 75
1122 00:25:48.496686 [Byte1]: 75
1123 00:25:48.501043
1124 00:25:48.501125 Set Vref, RX VrefLevel [Byte0]: 76
1125 00:25:48.504184 [Byte1]: 76
1126 00:25:48.507944
1127 00:25:48.508030 Set Vref, RX VrefLevel [Byte0]: 77
1128 00:25:48.511371 [Byte1]: 77
1129 00:25:48.515954
1130 00:25:48.516038 Final RX Vref Byte 0 = 58 to rank0
1131 00:25:48.519128 Final RX Vref Byte 1 = 57 to rank0
1132 00:25:48.522225 Final RX Vref Byte 0 = 58 to rank1
1133 00:25:48.525878 Final RX Vref Byte 1 = 57 to rank1==
1134 00:25:48.528962 Dram Type= 6, Freq= 0, CH_0, rank 0
1135 00:25:48.536023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 00:25:48.536176 ==
1137 00:25:48.536251 DQS Delay:
1138 00:25:48.536320 DQS0 = 0, DQS1 = 0
1139 00:25:48.539065 DQM Delay:
1140 00:25:48.539173 DQM0 = 92, DQM1 = 84
1141 00:25:48.542341 DQ Delay:
1142 00:25:48.545892 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1143 00:25:48.549241 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1144 00:25:48.549395 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1145 00:25:48.556116 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1146 00:25:48.556267
1147 00:25:48.556356
1148 00:25:48.603605 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1149 00:25:48.603900 CH0 RK0: MR19=606, MR18=4B41
1150 00:25:48.604351 CH0_RK0: MR19=0x606, MR18=0x4B41, DQSOSC=391, MR23=63, INC=96, DEC=64
1151 00:25:48.604537
1152 00:25:48.604686 ----->DramcWriteLeveling(PI) begin...
1153 00:25:48.604831 ==
1154 00:25:48.604998 Dram Type= 6, Freq= 0, CH_0, rank 1
1155 00:25:48.605141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1156 00:25:48.605280 ==
1157 00:25:48.605412 Write leveling (Byte 0): 33 => 33
1158 00:25:48.605545 Write leveling (Byte 1): 30 => 30
1159 00:25:48.605675 DramcWriteLeveling(PI) end<-----
1160 00:25:48.605804
1161 00:25:48.605932 ==
1162 00:25:48.606104 Dram Type= 6, Freq= 0, CH_0, rank 1
1163 00:25:48.606242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1164 00:25:48.606375 ==
1165 00:25:48.606503 [Gating] SW mode calibration
1166 00:25:48.647613 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1167 00:25:48.647995 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1168 00:25:48.648085 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1169 00:25:48.648159 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1170 00:25:48.648402 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1171 00:25:48.648466 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 00:25:48.649149 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 00:25:48.649411 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 00:25:48.649481 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:25:48.676157 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:25:48.676332 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 00:25:48.676600 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 00:25:48.676856 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 00:25:48.676922 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 00:25:48.677166 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 00:25:48.677232 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 00:25:48.680374 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 00:25:48.683599 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 00:25:48.690297 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 00:25:48.693599 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 00:25:48.697185 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1187 00:25:48.703499 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 00:25:48.707239 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 00:25:48.710698 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 00:25:48.717088 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 00:25:48.720399 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 00:25:48.723691 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 00:25:48.730556 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 00:25:48.733788 0 9 8 | B1->B0 | 2c2c 2b2a | 0 1 | (0 0) (0 0)
1195 00:25:48.737777 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 00:25:48.741253 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 00:25:48.748600 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 00:25:48.751761 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1199 00:25:48.754865 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 00:25:48.758623 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1201 00:25:48.765875 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1202 00:25:48.768912 0 10 8 | B1->B0 | 2a2a 2828 | 1 0 | (1 1) (0 0)
1203 00:25:48.772628 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1204 00:25:48.775557 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 00:25:48.782778 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 00:25:48.786352 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 00:25:48.789365 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 00:25:48.795810 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 00:25:48.799156 0 11 4 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
1210 00:25:48.802604 0 11 8 | B1->B0 | 4343 3a3a | 0 1 | (0 0) (0 0)
1211 00:25:48.809413 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 00:25:48.812536 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 00:25:48.816133 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 00:25:48.822362 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 00:25:48.826233 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 00:25:48.828947 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 00:25:48.835750 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1218 00:25:48.838926 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1219 00:25:48.842574 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 00:25:48.849389 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 00:25:48.852630 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 00:25:48.856104 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 00:25:48.859235 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 00:25:48.865925 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 00:25:48.869128 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 00:25:48.872420 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 00:25:48.879404 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 00:25:48.882469 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 00:25:48.885712 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 00:25:48.892349 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 00:25:48.895694 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 00:25:48.899563 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 00:25:48.905896 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 00:25:48.909118 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1235 00:25:48.912755 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 00:25:48.915780 Total UI for P1: 0, mck2ui 16
1237 00:25:48.919403 best dqsien dly found for B0: ( 0, 14, 10)
1238 00:25:48.922652 Total UI for P1: 0, mck2ui 16
1239 00:25:48.926065 best dqsien dly found for B1: ( 0, 14, 8)
1240 00:25:48.929192 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1241 00:25:48.932818 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1242 00:25:48.932901
1243 00:25:48.935917 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1244 00:25:48.942853 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1245 00:25:48.942939 [Gating] SW calibration Done
1246 00:25:48.943005 ==
1247 00:25:48.946165 Dram Type= 6, Freq= 0, CH_0, rank 1
1248 00:25:48.952923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1249 00:25:48.953015 ==
1250 00:25:48.953080 RX Vref Scan: 0
1251 00:25:48.953141
1252 00:25:48.955881 RX Vref 0 -> 0, step: 1
1253 00:25:48.955962
1254 00:25:48.959635 RX Delay -130 -> 252, step: 16
1255 00:25:48.962898 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1256 00:25:48.965953 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1257 00:25:48.969357 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1258 00:25:48.973041 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1259 00:25:48.979873 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1260 00:25:48.983130 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1261 00:25:48.986443 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1262 00:25:48.989585 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1263 00:25:48.993123 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1264 00:25:48.999836 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1265 00:25:49.003063 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1266 00:25:49.006529 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1267 00:25:49.009631 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1268 00:25:49.013170 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1269 00:25:49.020090 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1270 00:25:49.023348 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1271 00:25:49.023557 ==
1272 00:25:49.026587 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 00:25:49.030256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 00:25:49.030415 ==
1275 00:25:49.032975 DQS Delay:
1276 00:25:49.033062 DQS0 = 0, DQS1 = 0
1277 00:25:49.033127 DQM Delay:
1278 00:25:49.036464 DQM0 = 90, DQM1 = 83
1279 00:25:49.036553 DQ Delay:
1280 00:25:49.039795 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1281 00:25:49.043382 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1282 00:25:49.046276 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1283 00:25:49.049795 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1284 00:25:49.049913
1285 00:25:49.050025
1286 00:25:49.050110 ==
1287 00:25:49.053375 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 00:25:49.060268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 00:25:49.060425 ==
1290 00:25:49.060498
1291 00:25:49.060565
1292 00:25:49.060627 TX Vref Scan disable
1293 00:25:49.063317 == TX Byte 0 ==
1294 00:25:49.067062 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1295 00:25:49.070094 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1296 00:25:49.073886 == TX Byte 1 ==
1297 00:25:49.076930 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1298 00:25:49.080365 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1299 00:25:49.083510 ==
1300 00:25:49.087224 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 00:25:49.090022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 00:25:49.090202 ==
1303 00:25:49.102679 TX Vref=22, minBit 10, minWin=27, winSum=447
1304 00:25:49.106604 TX Vref=24, minBit 8, minWin=27, winSum=450
1305 00:25:49.109777 TX Vref=26, minBit 1, minWin=28, winSum=455
1306 00:25:49.112883 TX Vref=28, minBit 2, minWin=28, winSum=453
1307 00:25:49.116779 TX Vref=30, minBit 2, minWin=28, winSum=457
1308 00:25:49.119489 TX Vref=32, minBit 0, minWin=28, winSum=452
1309 00:25:49.126499 [TxChooseVref] Worse bit 2, Min win 28, Win sum 457, Final Vref 30
1310 00:25:49.126740
1311 00:25:49.129722 Final TX Range 1 Vref 30
1312 00:25:49.129963
1313 00:25:49.130153 ==
1314 00:25:49.133639 Dram Type= 6, Freq= 0, CH_0, rank 1
1315 00:25:49.136887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1316 00:25:49.137209 ==
1317 00:25:49.137405
1318 00:25:49.139864
1319 00:25:49.140227 TX Vref Scan disable
1320 00:25:49.143496 == TX Byte 0 ==
1321 00:25:49.146872 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1322 00:25:49.149671 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1323 00:25:49.153400 == TX Byte 1 ==
1324 00:25:49.157140 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1325 00:25:49.160099 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1326 00:25:49.163112
1327 00:25:49.163590 [DATLAT]
1328 00:25:49.163950 Freq=800, CH0 RK1
1329 00:25:49.164267
1330 00:25:49.166359 DATLAT Default: 0xa
1331 00:25:49.166822 0, 0xFFFF, sum = 0
1332 00:25:49.169833 1, 0xFFFF, sum = 0
1333 00:25:49.170173 2, 0xFFFF, sum = 0
1334 00:25:49.173009 3, 0xFFFF, sum = 0
1335 00:25:49.173398 4, 0xFFFF, sum = 0
1336 00:25:49.176663 5, 0xFFFF, sum = 0
1337 00:25:49.177051 6, 0xFFFF, sum = 0
1338 00:25:49.179717 7, 0xFFFF, sum = 0
1339 00:25:49.180105 8, 0xFFFF, sum = 0
1340 00:25:49.183744 9, 0x0, sum = 1
1341 00:25:49.184219 10, 0x0, sum = 2
1342 00:25:49.187021 11, 0x0, sum = 3
1343 00:25:49.187503 12, 0x0, sum = 4
1344 00:25:49.189988 best_step = 10
1345 00:25:49.190366
1346 00:25:49.190666 ==
1347 00:25:49.193789 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 00:25:49.196843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 00:25:49.197232 ==
1350 00:25:49.199837 RX Vref Scan: 0
1351 00:25:49.200217
1352 00:25:49.200520 RX Vref 0 -> 0, step: 1
1353 00:25:49.200812
1354 00:25:49.203367 RX Delay -79 -> 252, step: 8
1355 00:25:49.210437 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1356 00:25:49.213299 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1357 00:25:49.216795 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1358 00:25:49.220124 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1359 00:25:49.223678 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1360 00:25:49.227216 iDelay=209, Bit 5, Center 84 (-31 ~ 200) 232
1361 00:25:49.233219 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1362 00:25:49.236924 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1363 00:25:49.240270 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1364 00:25:49.243765 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1365 00:25:49.247354 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1366 00:25:49.253618 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1367 00:25:49.257130 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1368 00:25:49.260452 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1369 00:25:49.264090 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1370 00:25:49.267139 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1371 00:25:49.270701 ==
1372 00:25:49.274026 Dram Type= 6, Freq= 0, CH_0, rank 1
1373 00:25:49.277421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1374 00:25:49.277932 ==
1375 00:25:49.278261 DQS Delay:
1376 00:25:49.280713 DQS0 = 0, DQS1 = 0
1377 00:25:49.281130 DQM Delay:
1378 00:25:49.283904 DQM0 = 93, DQM1 = 84
1379 00:25:49.284409 DQ Delay:
1380 00:25:49.287126 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1381 00:25:49.290470 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1382 00:25:49.294118 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1383 00:25:49.296713 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =88
1384 00:25:49.297124
1385 00:25:49.297443
1386 00:25:49.303952 [DQSOSCAuto] RK1, (LSB)MR18= 0x4718, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
1387 00:25:49.306821 CH0 RK1: MR19=606, MR18=4718
1388 00:25:49.313954 CH0_RK1: MR19=0x606, MR18=0x4718, DQSOSC=392, MR23=63, INC=96, DEC=64
1389 00:25:49.316817 [RxdqsGatingPostProcess] freq 800
1390 00:25:49.323457 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1391 00:25:49.324017 Pre-setting of DQS Precalculation
1392 00:25:49.330165 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1393 00:25:49.330670 ==
1394 00:25:49.333650 Dram Type= 6, Freq= 0, CH_1, rank 0
1395 00:25:49.336667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 00:25:49.337176 ==
1397 00:25:49.343295 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1398 00:25:49.349949 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1399 00:25:49.358616 [CA 0] Center 36 (6~67) winsize 62
1400 00:25:49.361334 [CA 1] Center 36 (6~67) winsize 62
1401 00:25:49.364884 [CA 2] Center 35 (5~65) winsize 61
1402 00:25:49.368303 [CA 3] Center 34 (4~65) winsize 62
1403 00:25:49.371798 [CA 4] Center 35 (5~65) winsize 61
1404 00:25:49.374992 [CA 5] Center 34 (4~64) winsize 61
1405 00:25:49.375466
1406 00:25:49.378272 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1407 00:25:49.378649
1408 00:25:49.381526 [CATrainingPosCal] consider 1 rank data
1409 00:25:49.384874 u2DelayCellTimex100 = 270/100 ps
1410 00:25:49.387870 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1411 00:25:49.391814 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1412 00:25:49.395777 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1413 00:25:49.398929 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1414 00:25:49.402552 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1415 00:25:49.405982 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1416 00:25:49.406360
1417 00:25:49.410110 CA PerBit enable=1, Macro0, CA PI delay=34
1418 00:25:49.413668
1419 00:25:49.414152 [CBTSetCACLKResult] CA Dly = 34
1420 00:25:49.417080 CS Dly: 5 (0~36)
1421 00:25:49.417467 ==
1422 00:25:49.420519 Dram Type= 6, Freq= 0, CH_1, rank 1
1423 00:25:49.424532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1424 00:25:49.424920 ==
1425 00:25:49.428686 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1426 00:25:49.435138 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1427 00:25:49.444513 [CA 0] Center 36 (6~67) winsize 62
1428 00:25:49.447757 [CA 1] Center 37 (6~68) winsize 63
1429 00:25:49.451343 [CA 2] Center 35 (4~66) winsize 63
1430 00:25:49.454824 [CA 3] Center 34 (4~65) winsize 62
1431 00:25:49.457807 [CA 4] Center 35 (5~66) winsize 62
1432 00:25:49.461379 [CA 5] Center 34 (4~65) winsize 62
1433 00:25:49.461894
1434 00:25:49.464228 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1435 00:25:49.464642
1436 00:25:49.467581 [CATrainingPosCal] consider 2 rank data
1437 00:25:49.471168 u2DelayCellTimex100 = 270/100 ps
1438 00:25:49.474519 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1439 00:25:49.477886 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1440 00:25:49.484564 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1441 00:25:49.487977 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1442 00:25:49.491496 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1443 00:25:49.494769 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1444 00:25:49.495299
1445 00:25:49.497821 CA PerBit enable=1, Macro0, CA PI delay=34
1446 00:25:49.498235
1447 00:25:49.501252 [CBTSetCACLKResult] CA Dly = 34
1448 00:25:49.501661 CS Dly: 6 (0~38)
1449 00:25:49.501990
1450 00:25:49.504981 ----->DramcWriteLeveling(PI) begin...
1451 00:25:49.505399 ==
1452 00:25:49.508524 Dram Type= 6, Freq= 0, CH_1, rank 0
1453 00:25:49.515041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1454 00:25:49.515580 ==
1455 00:25:49.518579 Write leveling (Byte 0): 27 => 27
1456 00:25:49.519105 Write leveling (Byte 1): 27 => 27
1457 00:25:49.522070 DramcWriteLeveling(PI) end<-----
1458 00:25:49.522583
1459 00:25:49.525020 ==
1460 00:25:49.525547 Dram Type= 6, Freq= 0, CH_1, rank 0
1461 00:25:49.531723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1462 00:25:49.532140 ==
1463 00:25:49.534811 [Gating] SW mode calibration
1464 00:25:49.541813 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1465 00:25:49.544446 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1466 00:25:49.551422 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1467 00:25:49.555227 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1468 00:25:49.558072 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 00:25:49.565088 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 00:25:49.568510 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 00:25:49.571589 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 00:25:49.578096 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 00:25:49.581362 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 00:25:49.585156 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 00:25:49.588537 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 00:25:49.594714 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 00:25:49.598029 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 00:25:49.601588 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 00:25:49.608238 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 00:25:49.611856 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 00:25:49.614797 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 00:25:49.622012 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1483 00:25:49.624660 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1484 00:25:49.628107 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 00:25:49.634842 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 00:25:49.638545 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 00:25:49.641856 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 00:25:49.648241 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 00:25:49.651672 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 00:25:49.655438 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 00:25:49.661923 0 9 4 | B1->B0 | 2323 2323 | 1 1 | (1 1) (1 1)
1492 00:25:49.665196 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1493 00:25:49.668496 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 00:25:49.672236 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 00:25:49.678544 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 00:25:49.681558 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 00:25:49.685479 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1498 00:25:49.691872 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1499 00:25:49.695288 0 10 4 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (0 0)
1500 00:25:49.698490 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1501 00:25:49.705295 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 00:25:49.708034 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 00:25:49.712183 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 00:25:49.718205 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 00:25:49.722090 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 00:25:49.725507 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 00:25:49.731824 0 11 4 | B1->B0 | 2d2d 3232 | 0 0 | (0 0) (0 0)
1508 00:25:49.734749 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1509 00:25:49.738190 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 00:25:49.745016 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 00:25:49.748547 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 00:25:49.752110 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 00:25:49.755269 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 00:25:49.761913 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1515 00:25:49.765410 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1516 00:25:49.769014 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 00:25:49.776040 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 00:25:49.778549 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 00:25:49.782104 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 00:25:49.788888 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 00:25:49.792497 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 00:25:49.795338 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 00:25:49.802294 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 00:25:49.805730 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 00:25:49.809285 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 00:25:49.815432 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 00:25:49.818741 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 00:25:49.822406 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 00:25:49.825392 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 00:25:49.832177 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 00:25:49.835763 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1532 00:25:49.839192 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 00:25:49.842433 Total UI for P1: 0, mck2ui 16
1534 00:25:49.845413 best dqsien dly found for B0: ( 0, 14, 4)
1535 00:25:49.848671 Total UI for P1: 0, mck2ui 16
1536 00:25:49.851678 best dqsien dly found for B1: ( 0, 14, 4)
1537 00:25:49.855381 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1538 00:25:49.858633 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1539 00:25:49.859045
1540 00:25:49.865272 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1541 00:25:49.868713 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1542 00:25:49.869241 [Gating] SW calibration Done
1543 00:25:49.871962 ==
1544 00:25:49.875497 Dram Type= 6, Freq= 0, CH_1, rank 0
1545 00:25:49.878790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1546 00:25:49.879330 ==
1547 00:25:49.879726 RX Vref Scan: 0
1548 00:25:49.880037
1549 00:25:49.882467 RX Vref 0 -> 0, step: 1
1550 00:25:49.882875
1551 00:25:49.885628 RX Delay -130 -> 252, step: 16
1552 00:25:49.889129 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1553 00:25:49.892448 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1554 00:25:49.895419 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1555 00:25:49.902480 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1556 00:25:49.905974 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1557 00:25:49.909224 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1558 00:25:49.912664 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1559 00:25:49.915694 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1560 00:25:49.922400 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1561 00:25:49.925884 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1562 00:25:49.929135 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1563 00:25:49.932735 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1564 00:25:49.935843 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1565 00:25:49.942461 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1566 00:25:49.946444 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1567 00:25:49.949199 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1568 00:25:49.949692 ==
1569 00:25:49.952685 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 00:25:49.955727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 00:25:49.956291 ==
1572 00:25:49.959556 DQS Delay:
1573 00:25:49.960087 DQS0 = 0, DQS1 = 0
1574 00:25:49.963112 DQM Delay:
1575 00:25:49.963678 DQM0 = 93, DQM1 = 86
1576 00:25:49.964019 DQ Delay:
1577 00:25:49.965799 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1578 00:25:49.969218 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1579 00:25:49.972849 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1580 00:25:49.976390 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1581 00:25:49.976802
1582 00:25:49.977190
1583 00:25:49.977501 ==
1584 00:25:49.979749 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 00:25:49.986618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 00:25:49.987131 ==
1587 00:25:49.987458
1588 00:25:49.987819
1589 00:25:49.988115 TX Vref Scan disable
1590 00:25:49.989845 == TX Byte 0 ==
1591 00:25:49.993456 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1592 00:25:49.996877 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1593 00:25:49.999695 == TX Byte 1 ==
1594 00:25:50.003932 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1595 00:25:50.006645 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1596 00:25:50.010529 ==
1597 00:25:50.013420 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 00:25:50.016880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 00:25:50.017409 ==
1600 00:25:50.029191 TX Vref=22, minBit 0, minWin=27, winSum=437
1601 00:25:50.032621 TX Vref=24, minBit 1, minWin=27, winSum=443
1602 00:25:50.035803 TX Vref=26, minBit 1, minWin=27, winSum=444
1603 00:25:50.038986 TX Vref=28, minBit 1, minWin=27, winSum=449
1604 00:25:50.042454 TX Vref=30, minBit 1, minWin=27, winSum=450
1605 00:25:50.045633 TX Vref=32, minBit 1, minWin=27, winSum=445
1606 00:25:50.052051 [TxChooseVref] Worse bit 1, Min win 27, Win sum 450, Final Vref 30
1607 00:25:50.052613
1608 00:25:50.055705 Final TX Range 1 Vref 30
1609 00:25:50.056209
1610 00:25:50.056574 ==
1611 00:25:50.058664 Dram Type= 6, Freq= 0, CH_1, rank 0
1612 00:25:50.062462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1613 00:25:50.063103 ==
1614 00:25:50.063670
1615 00:25:50.064004
1616 00:25:50.066039 TX Vref Scan disable
1617 00:25:50.069516 == TX Byte 0 ==
1618 00:25:50.072492 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1619 00:25:50.075714 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1620 00:25:50.079425 == TX Byte 1 ==
1621 00:25:50.082430 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1622 00:25:50.085514 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1623 00:25:50.085929
1624 00:25:50.089246 [DATLAT]
1625 00:25:50.089757 Freq=800, CH1 RK0
1626 00:25:50.090086
1627 00:25:50.092513 DATLAT Default: 0xa
1628 00:25:50.092922 0, 0xFFFF, sum = 0
1629 00:25:50.096328 1, 0xFFFF, sum = 0
1630 00:25:50.096865 2, 0xFFFF, sum = 0
1631 00:25:50.099549 3, 0xFFFF, sum = 0
1632 00:25:50.100072 4, 0xFFFF, sum = 0
1633 00:25:50.102559 5, 0xFFFF, sum = 0
1634 00:25:50.103080 6, 0xFFFF, sum = 0
1635 00:25:50.105706 7, 0xFFFF, sum = 0
1636 00:25:50.106123 8, 0xFFFF, sum = 0
1637 00:25:50.108929 9, 0x0, sum = 1
1638 00:25:50.109348 10, 0x0, sum = 2
1639 00:25:50.112264 11, 0x0, sum = 3
1640 00:25:50.112681 12, 0x0, sum = 4
1641 00:25:50.115918 best_step = 10
1642 00:25:50.116424
1643 00:25:50.116751 ==
1644 00:25:50.118944 Dram Type= 6, Freq= 0, CH_1, rank 0
1645 00:25:50.122690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1646 00:25:50.123204 ==
1647 00:25:50.123565 RX Vref Scan: 1
1648 00:25:50.125769
1649 00:25:50.126176 Set Vref Range= 32 -> 127
1650 00:25:50.126502
1651 00:25:50.129580 RX Vref 32 -> 127, step: 1
1652 00:25:50.130089
1653 00:25:50.132706 RX Delay -79 -> 252, step: 8
1654 00:25:50.133117
1655 00:25:50.135993 Set Vref, RX VrefLevel [Byte0]: 32
1656 00:25:50.139308 [Byte1]: 32
1657 00:25:50.139761
1658 00:25:50.142281 Set Vref, RX VrefLevel [Byte0]: 33
1659 00:25:50.145652 [Byte1]: 33
1660 00:25:50.146158
1661 00:25:50.149003 Set Vref, RX VrefLevel [Byte0]: 34
1662 00:25:50.152528 [Byte1]: 34
1663 00:25:50.156099
1664 00:25:50.156616 Set Vref, RX VrefLevel [Byte0]: 35
1665 00:25:50.159746 [Byte1]: 35
1666 00:25:50.164080
1667 00:25:50.164591 Set Vref, RX VrefLevel [Byte0]: 36
1668 00:25:50.167173 [Byte1]: 36
1669 00:25:50.171763
1670 00:25:50.172407 Set Vref, RX VrefLevel [Byte0]: 37
1671 00:25:50.174910 [Byte1]: 37
1672 00:25:50.178690
1673 00:25:50.179098 Set Vref, RX VrefLevel [Byte0]: 38
1674 00:25:50.182521 [Byte1]: 38
1675 00:25:50.186478
1676 00:25:50.186921 Set Vref, RX VrefLevel [Byte0]: 39
1677 00:25:50.189673 [Byte1]: 39
1678 00:25:50.194410
1679 00:25:50.194819 Set Vref, RX VrefLevel [Byte0]: 40
1680 00:25:50.197868 [Byte1]: 40
1681 00:25:50.201701
1682 00:25:50.202210 Set Vref, RX VrefLevel [Byte0]: 41
1683 00:25:50.205178 [Byte1]: 41
1684 00:25:50.209382
1685 00:25:50.209898 Set Vref, RX VrefLevel [Byte0]: 42
1686 00:25:50.212469 [Byte1]: 42
1687 00:25:50.216841
1688 00:25:50.217392 Set Vref, RX VrefLevel [Byte0]: 43
1689 00:25:50.219810 [Byte1]: 43
1690 00:25:50.224255
1691 00:25:50.224775 Set Vref, RX VrefLevel [Byte0]: 44
1692 00:25:50.227754 [Byte1]: 44
1693 00:25:50.231869
1694 00:25:50.232384 Set Vref, RX VrefLevel [Byte0]: 45
1695 00:25:50.235435 [Byte1]: 45
1696 00:25:50.239365
1697 00:25:50.239952 Set Vref, RX VrefLevel [Byte0]: 46
1698 00:25:50.242681 [Byte1]: 46
1699 00:25:50.247000
1700 00:25:50.247513 Set Vref, RX VrefLevel [Byte0]: 47
1701 00:25:50.249967 [Byte1]: 47
1702 00:25:50.254785
1703 00:25:50.255300 Set Vref, RX VrefLevel [Byte0]: 48
1704 00:25:50.257815 [Byte1]: 48
1705 00:25:50.262439
1706 00:25:50.262954 Set Vref, RX VrefLevel [Byte0]: 49
1707 00:25:50.265253 [Byte1]: 49
1708 00:25:50.269966
1709 00:25:50.270480 Set Vref, RX VrefLevel [Byte0]: 50
1710 00:25:50.273420 [Byte1]: 50
1711 00:25:50.277229
1712 00:25:50.277743 Set Vref, RX VrefLevel [Byte0]: 51
1713 00:25:50.280119 [Byte1]: 51
1714 00:25:50.284558
1715 00:25:50.285050 Set Vref, RX VrefLevel [Byte0]: 52
1716 00:25:50.288092 [Byte1]: 52
1717 00:25:50.292512
1718 00:25:50.292927 Set Vref, RX VrefLevel [Byte0]: 53
1719 00:25:50.295619 [Byte1]: 53
1720 00:25:50.299902
1721 00:25:50.300575 Set Vref, RX VrefLevel [Byte0]: 54
1722 00:25:50.303188 [Byte1]: 54
1723 00:25:50.307054
1724 00:25:50.307467 Set Vref, RX VrefLevel [Byte0]: 55
1725 00:25:50.311054 [Byte1]: 55
1726 00:25:50.315098
1727 00:25:50.315666 Set Vref, RX VrefLevel [Byte0]: 56
1728 00:25:50.318239 [Byte1]: 56
1729 00:25:50.322687
1730 00:25:50.323199 Set Vref, RX VrefLevel [Byte0]: 57
1731 00:25:50.325486 [Byte1]: 57
1732 00:25:50.330314
1733 00:25:50.330825 Set Vref, RX VrefLevel [Byte0]: 58
1734 00:25:50.333269 [Byte1]: 58
1735 00:25:50.337802
1736 00:25:50.338320 Set Vref, RX VrefLevel [Byte0]: 59
1737 00:25:50.340822 [Byte1]: 59
1738 00:25:50.345473
1739 00:25:50.346038 Set Vref, RX VrefLevel [Byte0]: 60
1740 00:25:50.348422 [Byte1]: 60
1741 00:25:50.352237
1742 00:25:50.352648 Set Vref, RX VrefLevel [Byte0]: 61
1743 00:25:50.355705 [Byte1]: 61
1744 00:25:50.360205
1745 00:25:50.360714 Set Vref, RX VrefLevel [Byte0]: 62
1746 00:25:50.363255 [Byte1]: 62
1747 00:25:50.368452
1748 00:25:50.368966 Set Vref, RX VrefLevel [Byte0]: 63
1749 00:25:50.370995 [Byte1]: 63
1750 00:25:50.375333
1751 00:25:50.375895 Set Vref, RX VrefLevel [Byte0]: 64
1752 00:25:50.378765 [Byte1]: 64
1753 00:25:50.382949
1754 00:25:50.383455 Set Vref, RX VrefLevel [Byte0]: 65
1755 00:25:50.386300 [Byte1]: 65
1756 00:25:50.390479
1757 00:25:50.391049 Set Vref, RX VrefLevel [Byte0]: 66
1758 00:25:50.393692 [Byte1]: 66
1759 00:25:50.397940
1760 00:25:50.398448 Set Vref, RX VrefLevel [Byte0]: 67
1761 00:25:50.401069 [Byte1]: 67
1762 00:25:50.405674
1763 00:25:50.406182 Set Vref, RX VrefLevel [Byte0]: 68
1764 00:25:50.408533 [Byte1]: 68
1765 00:25:50.413125
1766 00:25:50.413540 Set Vref, RX VrefLevel [Byte0]: 69
1767 00:25:50.416012 [Byte1]: 69
1768 00:25:50.420187
1769 00:25:50.420599 Set Vref, RX VrefLevel [Byte0]: 70
1770 00:25:50.423842 [Byte1]: 70
1771 00:25:50.428390
1772 00:25:50.428803 Set Vref, RX VrefLevel [Byte0]: 71
1773 00:25:50.431641 [Byte1]: 71
1774 00:25:50.435933
1775 00:25:50.436473 Set Vref, RX VrefLevel [Byte0]: 72
1776 00:25:50.438901 [Byte1]: 72
1777 00:25:50.443815
1778 00:25:50.444326 Set Vref, RX VrefLevel [Byte0]: 73
1779 00:25:50.446348 [Byte1]: 73
1780 00:25:50.450785
1781 00:25:50.451229 Set Vref, RX VrefLevel [Byte0]: 74
1782 00:25:50.453936 [Byte1]: 74
1783 00:25:50.458510
1784 00:25:50.459031 Set Vref, RX VrefLevel [Byte0]: 75
1785 00:25:50.461923 [Byte1]: 75
1786 00:25:50.466062
1787 00:25:50.466573 Final RX Vref Byte 0 = 57 to rank0
1788 00:25:50.469647 Final RX Vref Byte 1 = 57 to rank0
1789 00:25:50.472294 Final RX Vref Byte 0 = 57 to rank1
1790 00:25:50.476113 Final RX Vref Byte 1 = 57 to rank1==
1791 00:25:50.479392 Dram Type= 6, Freq= 0, CH_1, rank 0
1792 00:25:50.482948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 00:25:50.486273 ==
1794 00:25:50.486789 DQS Delay:
1795 00:25:50.487118 DQS0 = 0, DQS1 = 0
1796 00:25:50.489354 DQM Delay:
1797 00:25:50.489870 DQM0 = 95, DQM1 = 89
1798 00:25:50.492686 DQ Delay:
1799 00:25:50.496410 DQ0 =96, DQ1 =88, DQ2 =88, DQ3 =92
1800 00:25:50.496928 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
1801 00:25:50.499917 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1802 00:25:50.502893 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1803 00:25:50.506232
1804 00:25:50.506748
1805 00:25:50.512276 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1806 00:25:50.516060 CH1 RK0: MR19=606, MR18=2C48
1807 00:25:50.522869 CH1_RK0: MR19=0x606, MR18=0x2C48, DQSOSC=391, MR23=63, INC=96, DEC=64
1808 00:25:50.523289
1809 00:25:50.526366 ----->DramcWriteLeveling(PI) begin...
1810 00:25:50.526889 ==
1811 00:25:50.529774 Dram Type= 6, Freq= 0, CH_1, rank 1
1812 00:25:50.532951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1813 00:25:50.533472 ==
1814 00:25:50.535977 Write leveling (Byte 0): 25 => 25
1815 00:25:50.538940 Write leveling (Byte 1): 29 => 29
1816 00:25:50.542696 DramcWriteLeveling(PI) end<-----
1817 00:25:50.543226
1818 00:25:50.543612 ==
1819 00:25:50.546325 Dram Type= 6, Freq= 0, CH_1, rank 1
1820 00:25:50.549697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1821 00:25:50.550293 ==
1822 00:25:50.553172 [Gating] SW mode calibration
1823 00:25:50.559711 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1824 00:25:50.566407 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1825 00:25:50.569752 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1826 00:25:50.573105 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1827 00:25:50.579937 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 00:25:50.582744 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 00:25:50.586489 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 00:25:50.592583 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 00:25:50.596384 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 00:25:50.599909 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 00:25:50.606135 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 00:25:50.609833 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 00:25:50.612558 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 00:25:50.619480 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 00:25:50.622689 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 00:25:50.625861 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 00:25:50.629377 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 00:25:50.636445 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 00:25:50.639160 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1842 00:25:50.643076 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1843 00:25:50.649315 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1844 00:25:50.652145 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 00:25:50.655892 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 00:25:50.662940 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 00:25:50.666110 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 00:25:50.669098 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 00:25:50.676243 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 00:25:50.679281 0 9 4 | B1->B0 | 2b2b 2323 | 1 1 | (1 1) (1 1)
1851 00:25:50.683074 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
1852 00:25:50.689695 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 00:25:50.692664 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 00:25:50.696194 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 00:25:50.702903 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 00:25:50.706440 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1857 00:25:50.709236 0 10 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1858 00:25:50.712772 0 10 4 | B1->B0 | 2828 2f2f | 0 1 | (0 0) (1 0)
1859 00:25:50.719798 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 00:25:50.723277 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 00:25:50.726174 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 00:25:50.732692 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 00:25:50.736356 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 00:25:50.739398 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 00:25:50.746320 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1866 00:25:50.749775 0 11 4 | B1->B0 | 3939 2f2e | 0 1 | (1 1) (0 0)
1867 00:25:50.753023 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1868 00:25:50.759652 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 00:25:50.762843 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 00:25:50.766442 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 00:25:50.773403 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 00:25:50.776180 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 00:25:50.779761 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1874 00:25:50.782842 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1875 00:25:50.789765 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 00:25:50.793012 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 00:25:50.796737 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 00:25:50.803372 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 00:25:50.806542 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 00:25:50.810012 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 00:25:50.816415 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 00:25:50.819856 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 00:25:50.823367 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 00:25:50.830469 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 00:25:50.833385 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 00:25:50.836987 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 00:25:50.840290 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 00:25:50.847049 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 00:25:50.850011 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1890 00:25:50.853696 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1891 00:25:50.860248 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 00:25:50.863864 Total UI for P1: 0, mck2ui 16
1893 00:25:50.867331 best dqsien dly found for B0: ( 0, 14, 2)
1894 00:25:50.867894 Total UI for P1: 0, mck2ui 16
1895 00:25:50.873865 best dqsien dly found for B1: ( 0, 14, 2)
1896 00:25:50.876727 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1897 00:25:50.879964 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1898 00:25:50.880380
1899 00:25:50.883348 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1900 00:25:50.886884 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1901 00:25:50.890443 [Gating] SW calibration Done
1902 00:25:50.890985 ==
1903 00:25:50.893802 Dram Type= 6, Freq= 0, CH_1, rank 1
1904 00:25:50.897022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1905 00:25:50.897541 ==
1906 00:25:50.900567 RX Vref Scan: 0
1907 00:25:50.900981
1908 00:25:50.901415 RX Vref 0 -> 0, step: 1
1909 00:25:50.901737
1910 00:25:50.904124 RX Delay -130 -> 252, step: 16
1911 00:25:50.907028 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1912 00:25:50.913630 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1913 00:25:50.917038 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1914 00:25:50.920315 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1915 00:25:50.924091 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1916 00:25:50.927051 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1917 00:25:50.930316 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1918 00:25:50.937120 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1919 00:25:50.940424 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1920 00:25:50.943934 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1921 00:25:50.947447 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1922 00:25:50.950747 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1923 00:25:50.957084 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1924 00:25:50.960141 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1925 00:25:50.963968 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1926 00:25:50.967164 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1927 00:25:50.967759 ==
1928 00:25:50.970548 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 00:25:50.977566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 00:25:50.978089 ==
1931 00:25:50.978423 DQS Delay:
1932 00:25:50.980381 DQS0 = 0, DQS1 = 0
1933 00:25:50.980795 DQM Delay:
1934 00:25:50.981122 DQM0 = 93, DQM1 = 89
1935 00:25:50.983485 DQ Delay:
1936 00:25:50.987120 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1937 00:25:50.990822 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1938 00:25:50.993379 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1939 00:25:50.997303 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1940 00:25:50.997842
1941 00:25:50.998178
1942 00:25:50.998483 ==
1943 00:25:51.000095 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 00:25:51.004108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 00:25:51.004627 ==
1946 00:25:51.004962
1947 00:25:51.005281
1948 00:25:51.007196 TX Vref Scan disable
1949 00:25:51.010275 == TX Byte 0 ==
1950 00:25:51.013655 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1951 00:25:51.016882 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1952 00:25:51.030305 == TX Byte 1 ==
1953 00:25:51.030416 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1954 00:25:51.030486 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1955 00:25:51.030551 ==
1956 00:25:51.030613 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 00:25:51.040740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 00:25:51.040931 ==
1959 00:25:51.048255 TX Vref=22, minBit 1, minWin=26, winSum=442
1960 00:25:51.050949 TX Vref=24, minBit 0, minWin=27, winSum=443
1961 00:25:51.054818 TX Vref=26, minBit 0, minWin=27, winSum=449
1962 00:25:51.057446 TX Vref=28, minBit 0, minWin=27, winSum=448
1963 00:25:51.061060 TX Vref=30, minBit 0, minWin=27, winSum=449
1964 00:25:51.067862 TX Vref=32, minBit 0, minWin=27, winSum=448
1965 00:25:51.071495 [TxChooseVref] Worse bit 0, Min win 27, Win sum 449, Final Vref 26
1966 00:25:51.071804
1967 00:25:51.074601 Final TX Range 1 Vref 26
1968 00:25:51.074929
1969 00:25:51.075127 ==
1970 00:25:51.078583 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 00:25:51.081369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 00:25:51.081765 ==
1973 00:25:51.084528
1974 00:25:51.084908
1975 00:25:51.085207 TX Vref Scan disable
1976 00:25:51.088099 == TX Byte 0 ==
1977 00:25:51.091421 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1978 00:25:51.094624 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1979 00:25:51.098179 == TX Byte 1 ==
1980 00:25:51.101581 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1981 00:25:51.104996 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1982 00:25:51.108270
1983 00:25:51.108796 [DATLAT]
1984 00:25:51.109137 Freq=800, CH1 RK1
1985 00:25:51.109451
1986 00:25:51.112064 DATLAT Default: 0xa
1987 00:25:51.112585 0, 0xFFFF, sum = 0
1988 00:25:51.115278 1, 0xFFFF, sum = 0
1989 00:25:51.115837 2, 0xFFFF, sum = 0
1990 00:25:51.118230 3, 0xFFFF, sum = 0
1991 00:25:51.118717 4, 0xFFFF, sum = 0
1992 00:25:51.121671 5, 0xFFFF, sum = 0
1993 00:25:51.122096 6, 0xFFFF, sum = 0
1994 00:25:51.125685 7, 0xFFFF, sum = 0
1995 00:25:51.128045 8, 0xFFFF, sum = 0
1996 00:25:51.128479 9, 0x0, sum = 1
1997 00:25:51.128817 10, 0x0, sum = 2
1998 00:25:51.131636 11, 0x0, sum = 3
1999 00:25:51.132153 12, 0x0, sum = 4
2000 00:25:51.135089 best_step = 10
2001 00:25:51.135649
2002 00:25:51.135989 ==
2003 00:25:51.138290 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 00:25:51.141874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 00:25:51.142392 ==
2006 00:25:51.145069 RX Vref Scan: 0
2007 00:25:51.145581
2008 00:25:51.145914 RX Vref 0 -> 0, step: 1
2009 00:25:51.146225
2010 00:25:51.148199 RX Delay -63 -> 252, step: 8
2011 00:25:51.154881 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2012 00:25:51.158069 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2013 00:25:51.161509 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2014 00:25:51.165221 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2015 00:25:51.168471 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2016 00:25:51.171911 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2017 00:25:51.178261 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2018 00:25:51.182059 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2019 00:25:51.184922 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2020 00:25:51.188684 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2021 00:25:51.191869 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2022 00:25:51.198303 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2023 00:25:51.201370 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2024 00:25:51.204998 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2025 00:25:51.208395 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2026 00:25:51.211568 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2027 00:25:51.212000 ==
2028 00:25:51.215388 Dram Type= 6, Freq= 0, CH_1, rank 1
2029 00:25:51.222124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2030 00:25:51.222638 ==
2031 00:25:51.222971 DQS Delay:
2032 00:25:51.223281 DQS0 = 0, DQS1 = 0
2033 00:25:51.225198 DQM Delay:
2034 00:25:51.225613 DQM0 = 97, DQM1 = 91
2035 00:25:51.229076 DQ Delay:
2036 00:25:51.232164 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2037 00:25:51.235627 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2038 00:25:51.238978 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =84
2039 00:25:51.241767 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2040 00:25:51.242184
2041 00:25:51.242510
2042 00:25:51.249276 [DQSOSCAuto] RK1, (LSB)MR18= 0x4912, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2043 00:25:51.251854 CH1 RK1: MR19=606, MR18=4912
2044 00:25:51.258607 CH1_RK1: MR19=0x606, MR18=0x4912, DQSOSC=391, MR23=63, INC=96, DEC=64
2045 00:25:51.262169 [RxdqsGatingPostProcess] freq 800
2046 00:25:51.265579 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2047 00:25:51.268836 Pre-setting of DQS Precalculation
2048 00:25:51.276016 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2049 00:25:51.282477 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2050 00:25:51.288868 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2051 00:25:51.289385
2052 00:25:51.289715
2053 00:25:51.292481 [Calibration Summary] 1600 Mbps
2054 00:25:51.292992 CH 0, Rank 0
2055 00:25:51.295642 SW Impedance : PASS
2056 00:25:51.299166 DUTY Scan : NO K
2057 00:25:51.299719 ZQ Calibration : PASS
2058 00:25:51.302239 Jitter Meter : NO K
2059 00:25:51.305678 CBT Training : PASS
2060 00:25:51.306209 Write leveling : PASS
2061 00:25:51.308667 RX DQS gating : PASS
2062 00:25:51.309082 RX DQ/DQS(RDDQC) : PASS
2063 00:25:51.312191 TX DQ/DQS : PASS
2064 00:25:51.315494 RX DATLAT : PASS
2065 00:25:51.316063 RX DQ/DQS(Engine): PASS
2066 00:25:51.318600 TX OE : NO K
2067 00:25:51.319110 All Pass.
2068 00:25:51.319444
2069 00:25:51.322254 CH 0, Rank 1
2070 00:25:51.322855 SW Impedance : PASS
2071 00:25:51.325677 DUTY Scan : NO K
2072 00:25:51.328856 ZQ Calibration : PASS
2073 00:25:51.329270 Jitter Meter : NO K
2074 00:25:51.332081 CBT Training : PASS
2075 00:25:51.335599 Write leveling : PASS
2076 00:25:51.336098 RX DQS gating : PASS
2077 00:25:51.338977 RX DQ/DQS(RDDQC) : PASS
2078 00:25:51.342233 TX DQ/DQS : PASS
2079 00:25:51.342653 RX DATLAT : PASS
2080 00:25:51.346168 RX DQ/DQS(Engine): PASS
2081 00:25:51.346687 TX OE : NO K
2082 00:25:51.348644 All Pass.
2083 00:25:51.349058
2084 00:25:51.349386 CH 1, Rank 0
2085 00:25:51.352142 SW Impedance : PASS
2086 00:25:51.352598 DUTY Scan : NO K
2087 00:25:51.355885 ZQ Calibration : PASS
2088 00:25:51.358598 Jitter Meter : NO K
2089 00:25:51.359012 CBT Training : PASS
2090 00:25:51.362355 Write leveling : PASS
2091 00:25:51.365837 RX DQS gating : PASS
2092 00:25:51.366354 RX DQ/DQS(RDDQC) : PASS
2093 00:25:51.368554 TX DQ/DQS : PASS
2094 00:25:51.371809 RX DATLAT : PASS
2095 00:25:51.372225 RX DQ/DQS(Engine): PASS
2096 00:25:51.375267 TX OE : NO K
2097 00:25:51.375716 All Pass.
2098 00:25:51.376051
2099 00:25:51.378496 CH 1, Rank 1
2100 00:25:51.378906 SW Impedance : PASS
2101 00:25:51.381961 DUTY Scan : NO K
2102 00:25:51.385239 ZQ Calibration : PASS
2103 00:25:51.385658 Jitter Meter : NO K
2104 00:25:51.388860 CBT Training : PASS
2105 00:25:51.392440 Write leveling : PASS
2106 00:25:51.392954 RX DQS gating : PASS
2107 00:25:51.395478 RX DQ/DQS(RDDQC) : PASS
2108 00:25:51.395932 TX DQ/DQS : PASS
2109 00:25:51.399222 RX DATLAT : PASS
2110 00:25:51.402069 RX DQ/DQS(Engine): PASS
2111 00:25:51.402487 TX OE : NO K
2112 00:25:51.405583 All Pass.
2113 00:25:51.405995
2114 00:25:51.406323 DramC Write-DBI off
2115 00:25:51.408548 PER_BANK_REFRESH: Hybrid Mode
2116 00:25:51.412274 TX_TRACKING: ON
2117 00:25:51.415619 [GetDramInforAfterCalByMRR] Vendor 6.
2118 00:25:51.418427 [GetDramInforAfterCalByMRR] Revision 606.
2119 00:25:51.422130 [GetDramInforAfterCalByMRR] Revision 2 0.
2120 00:25:51.422613 MR0 0x3b3b
2121 00:25:51.422953 MR8 0x5151
2122 00:25:51.425610 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2123 00:25:51.428979
2124 00:25:51.429490 MR0 0x3b3b
2125 00:25:51.429823 MR8 0x5151
2126 00:25:51.432463 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2127 00:25:51.432991
2128 00:25:51.441838 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2129 00:25:51.445311 [FAST_K] Save calibration result to emmc
2130 00:25:51.448725 [FAST_K] Save calibration result to emmc
2131 00:25:51.452117 dram_init: config_dvfs: 1
2132 00:25:51.455464 dramc_set_vcore_voltage set vcore to 662500
2133 00:25:51.459307 Read voltage for 1200, 2
2134 00:25:51.459887 Vio18 = 0
2135 00:25:51.460224 Vcore = 662500
2136 00:25:51.462479 Vdram = 0
2137 00:25:51.462887 Vddq = 0
2138 00:25:51.463224 Vmddr = 0
2139 00:25:51.469095 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2140 00:25:51.472240 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2141 00:25:51.475578 MEM_TYPE=3, freq_sel=15
2142 00:25:51.479120 sv_algorithm_assistance_LP4_1600
2143 00:25:51.482601 ============ PULL DRAM RESETB DOWN ============
2144 00:25:51.485826 ========== PULL DRAM RESETB DOWN end =========
2145 00:25:51.492738 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2146 00:25:51.495474 ===================================
2147 00:25:51.495934 LPDDR4 DRAM CONFIGURATION
2148 00:25:51.498959 ===================================
2149 00:25:51.502480 EX_ROW_EN[0] = 0x0
2150 00:25:51.506319 EX_ROW_EN[1] = 0x0
2151 00:25:51.506830 LP4Y_EN = 0x0
2152 00:25:51.509122 WORK_FSP = 0x0
2153 00:25:51.509539 WL = 0x4
2154 00:25:51.512560 RL = 0x4
2155 00:25:51.512979 BL = 0x2
2156 00:25:51.515645 RPST = 0x0
2157 00:25:51.516212 RD_PRE = 0x0
2158 00:25:51.518965 WR_PRE = 0x1
2159 00:25:51.519383 WR_PST = 0x0
2160 00:25:51.522211 DBI_WR = 0x0
2161 00:25:51.522667 DBI_RD = 0x0
2162 00:25:51.525649 OTF = 0x1
2163 00:25:51.529470 ===================================
2164 00:25:51.533107 ===================================
2165 00:25:51.533640 ANA top config
2166 00:25:51.535560 ===================================
2167 00:25:51.539674 DLL_ASYNC_EN = 0
2168 00:25:51.542510 ALL_SLAVE_EN = 0
2169 00:25:51.542933 NEW_RANK_MODE = 1
2170 00:25:51.546065 DLL_IDLE_MODE = 1
2171 00:25:51.549688 LP45_APHY_COMB_EN = 1
2172 00:25:51.552770 TX_ODT_DIS = 1
2173 00:25:51.555656 NEW_8X_MODE = 1
2174 00:25:51.556084 ===================================
2175 00:25:51.559031 ===================================
2176 00:25:51.562871 data_rate = 2400
2177 00:25:51.566357 CKR = 1
2178 00:25:51.569799 DQ_P2S_RATIO = 8
2179 00:25:51.572266 ===================================
2180 00:25:51.576270 CA_P2S_RATIO = 8
2181 00:25:51.579745 DQ_CA_OPEN = 0
2182 00:25:51.580258 DQ_SEMI_OPEN = 0
2183 00:25:51.582567 CA_SEMI_OPEN = 0
2184 00:25:51.585969 CA_FULL_RATE = 0
2185 00:25:51.589330 DQ_CKDIV4_EN = 0
2186 00:25:51.592635 CA_CKDIV4_EN = 0
2187 00:25:51.596007 CA_PREDIV_EN = 0
2188 00:25:51.596429 PH8_DLY = 17
2189 00:25:51.599940 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2190 00:25:51.602835 DQ_AAMCK_DIV = 4
2191 00:25:51.606163 CA_AAMCK_DIV = 4
2192 00:25:51.609046 CA_ADMCK_DIV = 4
2193 00:25:51.613161 DQ_TRACK_CA_EN = 0
2194 00:25:51.613677 CA_PICK = 1200
2195 00:25:51.616185 CA_MCKIO = 1200
2196 00:25:51.619269 MCKIO_SEMI = 0
2197 00:25:51.623021 PLL_FREQ = 2366
2198 00:25:51.626069 DQ_UI_PI_RATIO = 32
2199 00:25:51.629154 CA_UI_PI_RATIO = 0
2200 00:25:51.632419 ===================================
2201 00:25:51.635988 ===================================
2202 00:25:51.636411 memory_type:LPDDR4
2203 00:25:51.639329 GP_NUM : 10
2204 00:25:51.642534 SRAM_EN : 1
2205 00:25:51.642959 MD32_EN : 0
2206 00:25:51.646217 ===================================
2207 00:25:51.649246 [ANA_INIT] >>>>>>>>>>>>>>
2208 00:25:51.652574 <<<<<< [CONFIGURE PHASE]: ANA_TX
2209 00:25:51.655993 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2210 00:25:51.658950 ===================================
2211 00:25:51.662395 data_rate = 2400,PCW = 0X5b00
2212 00:25:51.666068 ===================================
2213 00:25:51.669467 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2214 00:25:51.672727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2215 00:25:51.679181 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2216 00:25:51.682576 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2217 00:25:51.685915 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2218 00:25:51.689178 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2219 00:25:51.693039 [ANA_INIT] flow start
2220 00:25:51.696292 [ANA_INIT] PLL >>>>>>>>
2221 00:25:51.696712 [ANA_INIT] PLL <<<<<<<<
2222 00:25:51.699747 [ANA_INIT] MIDPI >>>>>>>>
2223 00:25:51.702828 [ANA_INIT] MIDPI <<<<<<<<
2224 00:25:51.706164 [ANA_INIT] DLL >>>>>>>>
2225 00:25:51.706673 [ANA_INIT] DLL <<<<<<<<
2226 00:25:51.709527 [ANA_INIT] flow end
2227 00:25:51.713155 ============ LP4 DIFF to SE enter ============
2228 00:25:51.715935 ============ LP4 DIFF to SE exit ============
2229 00:25:51.719438 [ANA_INIT] <<<<<<<<<<<<<
2230 00:25:51.722659 [Flow] Enable top DCM control >>>>>
2231 00:25:51.726408 [Flow] Enable top DCM control <<<<<
2232 00:25:51.729790 Enable DLL master slave shuffle
2233 00:25:51.732904 ==============================================================
2234 00:25:51.736168 Gating Mode config
2235 00:25:51.742796 ==============================================================
2236 00:25:51.743295 Config description:
2237 00:25:51.752970 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2238 00:25:51.759356 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2239 00:25:51.762880 SELPH_MODE 0: By rank 1: By Phase
2240 00:25:51.769439 ==============================================================
2241 00:25:51.773263 GAT_TRACK_EN = 1
2242 00:25:51.776402 RX_GATING_MODE = 2
2243 00:25:51.779493 RX_GATING_TRACK_MODE = 2
2244 00:25:51.783354 SELPH_MODE = 1
2245 00:25:51.786146 PICG_EARLY_EN = 1
2246 00:25:51.789619 VALID_LAT_VALUE = 1
2247 00:25:51.792882 ==============================================================
2248 00:25:51.796609 Enter into Gating configuration >>>>
2249 00:25:51.800040 Exit from Gating configuration <<<<
2250 00:25:51.803308 Enter into DVFS_PRE_config >>>>>
2251 00:25:51.812932 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2252 00:25:51.816477 Exit from DVFS_PRE_config <<<<<
2253 00:25:51.820056 Enter into PICG configuration >>>>
2254 00:25:51.823318 Exit from PICG configuration <<<<
2255 00:25:51.826819 [RX_INPUT] configuration >>>>>
2256 00:25:51.830150 [RX_INPUT] configuration <<<<<
2257 00:25:51.836495 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2258 00:25:51.840157 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2259 00:25:51.846223 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2260 00:25:51.853106 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2261 00:25:51.859485 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2262 00:25:51.866280 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2263 00:25:51.869598 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2264 00:25:51.872967 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2265 00:25:51.876392 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2266 00:25:51.879631 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2267 00:25:51.886390 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2268 00:25:51.889884 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2269 00:25:51.893675 ===================================
2270 00:25:51.896803 LPDDR4 DRAM CONFIGURATION
2271 00:25:51.899963 ===================================
2272 00:25:51.900467 EX_ROW_EN[0] = 0x0
2273 00:25:51.903207 EX_ROW_EN[1] = 0x0
2274 00:25:51.903663 LP4Y_EN = 0x0
2275 00:25:51.906932 WORK_FSP = 0x0
2276 00:25:51.907459 WL = 0x4
2277 00:25:51.910402 RL = 0x4
2278 00:25:51.910906 BL = 0x2
2279 00:25:51.913776 RPST = 0x0
2280 00:25:51.914294 RD_PRE = 0x0
2281 00:25:51.916543 WR_PRE = 0x1
2282 00:25:51.917065 WR_PST = 0x0
2283 00:25:51.920063 DBI_WR = 0x0
2284 00:25:51.920583 DBI_RD = 0x0
2285 00:25:51.923442 OTF = 0x1
2286 00:25:51.926979 ===================================
2287 00:25:51.930436 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2288 00:25:51.933779 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2289 00:25:51.939928 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2290 00:25:51.943352 ===================================
2291 00:25:51.943986 LPDDR4 DRAM CONFIGURATION
2292 00:25:51.946753 ===================================
2293 00:25:51.950289 EX_ROW_EN[0] = 0x10
2294 00:25:51.953321 EX_ROW_EN[1] = 0x0
2295 00:25:51.953745 LP4Y_EN = 0x0
2296 00:25:51.956961 WORK_FSP = 0x0
2297 00:25:51.957457 WL = 0x4
2298 00:25:51.960087 RL = 0x4
2299 00:25:51.960504 BL = 0x2
2300 00:25:51.963232 RPST = 0x0
2301 00:25:51.963779 RD_PRE = 0x0
2302 00:25:51.966898 WR_PRE = 0x1
2303 00:25:51.967425 WR_PST = 0x0
2304 00:25:51.969869 DBI_WR = 0x0
2305 00:25:51.970415 DBI_RD = 0x0
2306 00:25:51.973024 OTF = 0x1
2307 00:25:51.976539 ===================================
2308 00:25:51.983255 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2309 00:25:51.983722 ==
2310 00:25:51.986530 Dram Type= 6, Freq= 0, CH_0, rank 0
2311 00:25:51.989802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2312 00:25:51.990221 ==
2313 00:25:51.992942 [Duty_Offset_Calibration]
2314 00:25:51.993357 B0:2 B1:1 CA:1
2315 00:25:51.993685
2316 00:25:51.996657 [DutyScan_Calibration_Flow] k_type=0
2317 00:25:52.006699
2318 00:25:52.007146 ==CLK 0==
2319 00:25:52.009881 Final CLK duty delay cell = 0
2320 00:25:52.013694 [0] MAX Duty = 5187%(X100), DQS PI = 24
2321 00:25:52.016862 [0] MIN Duty = 4875%(X100), DQS PI = 0
2322 00:25:52.017286 [0] AVG Duty = 5031%(X100)
2323 00:25:52.020239
2324 00:25:52.020628 CH0 CLK Duty spec in!! Max-Min= 312%
2325 00:25:52.026944 [DutyScan_Calibration_Flow] ====Done====
2326 00:25:52.027324
2327 00:25:52.030147 [DutyScan_Calibration_Flow] k_type=1
2328 00:25:52.044669
2329 00:25:52.045154 ==DQS 0 ==
2330 00:25:52.047811 Final DQS duty delay cell = -4
2331 00:25:52.051624 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2332 00:25:52.054447 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2333 00:25:52.057903 [-4] AVG Duty = 4937%(X100)
2334 00:25:52.058321
2335 00:25:52.058650 ==DQS 1 ==
2336 00:25:52.061388 Final DQS duty delay cell = -4
2337 00:25:52.065065 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2338 00:25:52.068167 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2339 00:25:52.071105 [-4] AVG Duty = 4906%(X100)
2340 00:25:52.071555
2341 00:25:52.074576 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2342 00:25:52.074992
2343 00:25:52.078153 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2344 00:25:52.081259 [DutyScan_Calibration_Flow] ====Done====
2345 00:25:52.081674
2346 00:25:52.084531 [DutyScan_Calibration_Flow] k_type=3
2347 00:25:52.101805
2348 00:25:52.102279 ==DQM 0 ==
2349 00:25:52.105286 Final DQM duty delay cell = 0
2350 00:25:52.108439 [0] MAX Duty = 5156%(X100), DQS PI = 24
2351 00:25:52.111795 [0] MIN Duty = 4938%(X100), DQS PI = 0
2352 00:25:52.112214 [0] AVG Duty = 5047%(X100)
2353 00:25:52.115701
2354 00:25:52.116223 ==DQM 1 ==
2355 00:25:52.118630 Final DQM duty delay cell = 0
2356 00:25:52.121590 [0] MAX Duty = 5125%(X100), DQS PI = 10
2357 00:25:52.125237 [0] MIN Duty = 5031%(X100), DQS PI = 36
2358 00:25:52.125652 [0] AVG Duty = 5078%(X100)
2359 00:25:52.128397
2360 00:25:52.132015 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2361 00:25:52.132525
2362 00:25:52.134975 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2363 00:25:52.139072 [DutyScan_Calibration_Flow] ====Done====
2364 00:25:52.139667
2365 00:25:52.141756 [DutyScan_Calibration_Flow] k_type=2
2366 00:25:52.158569
2367 00:25:52.159089 ==DQ 0 ==
2368 00:25:52.161685 Final DQ duty delay cell = 0
2369 00:25:52.165365 [0] MAX Duty = 5031%(X100), DQS PI = 24
2370 00:25:52.168749 [0] MIN Duty = 4875%(X100), DQS PI = 62
2371 00:25:52.169276 [0] AVG Duty = 4953%(X100)
2372 00:25:52.169614
2373 00:25:52.171486 ==DQ 1 ==
2374 00:25:52.175005 Final DQ duty delay cell = 0
2375 00:25:52.178515 [0] MAX Duty = 5093%(X100), DQS PI = 8
2376 00:25:52.182314 [0] MIN Duty = 4938%(X100), DQS PI = 36
2377 00:25:52.182843 [0] AVG Duty = 5015%(X100)
2378 00:25:52.183182
2379 00:25:52.185312 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2380 00:25:52.185733
2381 00:25:52.189008 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2382 00:25:52.194795 [DutyScan_Calibration_Flow] ====Done====
2383 00:25:52.195217 ==
2384 00:25:52.198719 Dram Type= 6, Freq= 0, CH_1, rank 0
2385 00:25:52.201980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2386 00:25:52.202506 ==
2387 00:25:52.205007 [Duty_Offset_Calibration]
2388 00:25:52.205426 B0:1 B1:0 CA:0
2389 00:25:52.205758
2390 00:25:52.208304 [DutyScan_Calibration_Flow] k_type=0
2391 00:25:52.217285
2392 00:25:52.217709 ==CLK 0==
2393 00:25:52.220674 Final CLK duty delay cell = -4
2394 00:25:52.224132 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2395 00:25:52.227081 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2396 00:25:52.230337 [-4] AVG Duty = 4969%(X100)
2397 00:25:52.230757
2398 00:25:52.234251 CH1 CLK Duty spec in!! Max-Min= 124%
2399 00:25:52.237206 [DutyScan_Calibration_Flow] ====Done====
2400 00:25:52.237622
2401 00:25:52.240581 [DutyScan_Calibration_Flow] k_type=1
2402 00:25:52.256977
2403 00:25:52.257439 ==DQS 0 ==
2404 00:25:52.260308 Final DQS duty delay cell = 0
2405 00:25:52.263510 [0] MAX Duty = 5094%(X100), DQS PI = 24
2406 00:25:52.267307 [0] MIN Duty = 4875%(X100), DQS PI = 0
2407 00:25:52.267795 [0] AVG Duty = 4984%(X100)
2408 00:25:52.270334
2409 00:25:52.270746 ==DQS 1 ==
2410 00:25:52.273916 Final DQS duty delay cell = 0
2411 00:25:52.277506 [0] MAX Duty = 5187%(X100), DQS PI = 18
2412 00:25:52.280808 [0] MIN Duty = 4969%(X100), DQS PI = 10
2413 00:25:52.281330 [0] AVG Duty = 5078%(X100)
2414 00:25:52.281663
2415 00:25:52.287055 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2416 00:25:52.287469
2417 00:25:52.290945 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2418 00:25:52.294049 [DutyScan_Calibration_Flow] ====Done====
2419 00:25:52.294567
2420 00:25:52.297242 [DutyScan_Calibration_Flow] k_type=3
2421 00:25:52.313984
2422 00:25:52.314500 ==DQM 0 ==
2423 00:25:52.317115 Final DQM duty delay cell = 0
2424 00:25:52.320632 [0] MAX Duty = 5156%(X100), DQS PI = 6
2425 00:25:52.323603 [0] MIN Duty = 5031%(X100), DQS PI = 48
2426 00:25:52.324022 [0] AVG Duty = 5093%(X100)
2427 00:25:52.327310
2428 00:25:52.328051 ==DQM 1 ==
2429 00:25:52.330391 Final DQM duty delay cell = 0
2430 00:25:52.334020 [0] MAX Duty = 5031%(X100), DQS PI = 16
2431 00:25:52.337231 [0] MIN Duty = 4907%(X100), DQS PI = 36
2432 00:25:52.340387 [0] AVG Duty = 4969%(X100)
2433 00:25:52.340908
2434 00:25:52.343858 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2435 00:25:52.344377
2436 00:25:52.346995 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2437 00:25:52.350868 [DutyScan_Calibration_Flow] ====Done====
2438 00:25:52.351402
2439 00:25:52.353458 [DutyScan_Calibration_Flow] k_type=2
2440 00:25:52.369642
2441 00:25:52.370167 ==DQ 0 ==
2442 00:25:52.373442 Final DQ duty delay cell = -4
2443 00:25:52.376762 [-4] MAX Duty = 5094%(X100), DQS PI = 10
2444 00:25:52.379865 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2445 00:25:52.380285 [-4] AVG Duty = 5016%(X100)
2446 00:25:52.383628
2447 00:25:52.384138 ==DQ 1 ==
2448 00:25:52.386827 Final DQ duty delay cell = 0
2449 00:25:52.389681 [0] MAX Duty = 5125%(X100), DQS PI = 20
2450 00:25:52.393341 [0] MIN Duty = 4969%(X100), DQS PI = 12
2451 00:25:52.393864 [0] AVG Duty = 5047%(X100)
2452 00:25:52.394204
2453 00:25:52.396444 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2454 00:25:52.400000
2455 00:25:52.403708 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2456 00:25:52.406472 [DutyScan_Calibration_Flow] ====Done====
2457 00:25:52.409950 nWR fixed to 30
2458 00:25:52.410469 [ModeRegInit_LP4] CH0 RK0
2459 00:25:52.413518 [ModeRegInit_LP4] CH0 RK1
2460 00:25:52.416975 [ModeRegInit_LP4] CH1 RK0
2461 00:25:52.417634 [ModeRegInit_LP4] CH1 RK1
2462 00:25:52.420023 match AC timing 7
2463 00:25:52.422932 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2464 00:25:52.426683 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2465 00:25:52.433860 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2466 00:25:52.436572 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2467 00:25:52.443296 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2468 00:25:52.443870 ==
2469 00:25:52.446572 Dram Type= 6, Freq= 0, CH_0, rank 0
2470 00:25:52.449901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2471 00:25:52.450460 ==
2472 00:25:52.456487 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2473 00:25:52.459660 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2474 00:25:52.469875 [CA 0] Center 39 (8~70) winsize 63
2475 00:25:52.473277 [CA 1] Center 39 (8~70) winsize 63
2476 00:25:52.476572 [CA 2] Center 35 (5~66) winsize 62
2477 00:25:52.479982 [CA 3] Center 34 (4~65) winsize 62
2478 00:25:52.483012 [CA 4] Center 33 (3~64) winsize 62
2479 00:25:52.486656 [CA 5] Center 32 (3~62) winsize 60
2480 00:25:52.487202
2481 00:25:52.489845 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2482 00:25:52.490259
2483 00:25:52.493427 [CATrainingPosCal] consider 1 rank data
2484 00:25:52.496811 u2DelayCellTimex100 = 270/100 ps
2485 00:25:52.500128 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2486 00:25:52.503481 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2487 00:25:52.509720 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2488 00:25:52.513151 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2489 00:25:52.516691 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2490 00:25:52.520125 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2491 00:25:52.520610
2492 00:25:52.523619 CA PerBit enable=1, Macro0, CA PI delay=32
2493 00:25:52.524122
2494 00:25:52.526341 [CBTSetCACLKResult] CA Dly = 32
2495 00:25:52.526918 CS Dly: 6 (0~37)
2496 00:25:52.527439 ==
2497 00:25:52.529796 Dram Type= 6, Freq= 0, CH_0, rank 1
2498 00:25:52.536914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2499 00:25:52.537433 ==
2500 00:25:52.540440 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2501 00:25:52.546460 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2502 00:25:52.555757 [CA 0] Center 38 (8~69) winsize 62
2503 00:25:52.558691 [CA 1] Center 38 (8~69) winsize 62
2504 00:25:52.562286 [CA 2] Center 35 (4~66) winsize 63
2505 00:25:52.565992 [CA 3] Center 34 (4~65) winsize 62
2506 00:25:52.569046 [CA 4] Center 33 (3~64) winsize 62
2507 00:25:52.572147 [CA 5] Center 32 (2~62) winsize 61
2508 00:25:52.572567
2509 00:25:52.575337 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2510 00:25:52.575792
2511 00:25:52.578635 [CATrainingPosCal] consider 2 rank data
2512 00:25:52.582435 u2DelayCellTimex100 = 270/100 ps
2513 00:25:52.585497 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2514 00:25:52.588792 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2515 00:25:52.595659 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2516 00:25:52.599350 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2517 00:25:52.602900 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2518 00:25:52.606057 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2519 00:25:52.606477
2520 00:25:52.609229 CA PerBit enable=1, Macro0, CA PI delay=32
2521 00:25:52.609738
2522 00:25:52.612690 [CBTSetCACLKResult] CA Dly = 32
2523 00:25:52.613201 CS Dly: 6 (0~38)
2524 00:25:52.613538
2525 00:25:52.616105 ----->DramcWriteLeveling(PI) begin...
2526 00:25:52.616624 ==
2527 00:25:52.619361 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 00:25:52.626190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2529 00:25:52.626706 ==
2530 00:25:52.629454 Write leveling (Byte 0): 35 => 35
2531 00:25:52.632840 Write leveling (Byte 1): 28 => 28
2532 00:25:52.633355 DramcWriteLeveling(PI) end<-----
2533 00:25:52.635701
2534 00:25:52.636206 ==
2535 00:25:52.639206 Dram Type= 6, Freq= 0, CH_0, rank 0
2536 00:25:52.642755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2537 00:25:52.643274 ==
2538 00:25:52.645847 [Gating] SW mode calibration
2539 00:25:52.652686 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2540 00:25:52.655923 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2541 00:25:52.662768 0 15 0 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
2542 00:25:52.666006 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2543 00:25:52.669230 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 00:25:52.675918 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 00:25:52.679409 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 00:25:52.682544 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2547 00:25:52.689428 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2548 00:25:52.692603 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
2549 00:25:52.696062 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
2550 00:25:52.699905 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 00:25:52.706103 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 00:25:52.709785 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 00:25:52.712592 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 00:25:52.719753 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 00:25:52.722839 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
2556 00:25:52.726355 1 0 28 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2557 00:25:52.733157 1 1 0 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
2558 00:25:52.736687 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 00:25:52.739433 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 00:25:52.746484 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 00:25:52.749670 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 00:25:52.753094 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 00:25:52.759367 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2564 00:25:52.763004 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2565 00:25:52.766287 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2566 00:25:52.772645 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 00:25:52.776264 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 00:25:52.779321 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 00:25:52.786303 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 00:25:52.789512 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 00:25:52.793086 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 00:25:52.795911 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 00:25:52.803312 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 00:25:52.806434 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 00:25:52.809480 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 00:25:52.816196 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 00:25:52.819504 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 00:25:52.823084 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 00:25:52.829696 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2580 00:25:52.833051 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2581 00:25:52.836689 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2582 00:25:52.839599 Total UI for P1: 0, mck2ui 16
2583 00:25:52.843096 best dqsien dly found for B0: ( 1, 3, 26)
2584 00:25:52.846399 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 00:25:52.849893 Total UI for P1: 0, mck2ui 16
2586 00:25:52.853470 best dqsien dly found for B1: ( 1, 4, 0)
2587 00:25:52.859500 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2588 00:25:52.862799 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2589 00:25:52.863207
2590 00:25:52.866456 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2591 00:25:52.870004 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2592 00:25:52.873692 [Gating] SW calibration Done
2593 00:25:52.874200 ==
2594 00:25:52.877039 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 00:25:52.879738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 00:25:52.880220 ==
2597 00:25:52.880556 RX Vref Scan: 0
2598 00:25:52.880867
2599 00:25:52.883584 RX Vref 0 -> 0, step: 1
2600 00:25:52.884004
2601 00:25:52.886426 RX Delay -40 -> 252, step: 8
2602 00:25:52.889744 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2603 00:25:52.893365 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2604 00:25:52.900026 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2605 00:25:52.903507 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2606 00:25:52.906919 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2607 00:25:52.910629 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2608 00:25:52.913621 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2609 00:25:52.916903 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2610 00:25:52.923369 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2611 00:25:52.927123 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2612 00:25:52.929933 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2613 00:25:52.934101 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2614 00:25:52.937087 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2615 00:25:52.943818 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2616 00:25:52.946607 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2617 00:25:52.950000 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2618 00:25:52.950422 ==
2619 00:25:52.953885 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 00:25:52.957032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 00:25:52.957474 ==
2622 00:25:52.960065 DQS Delay:
2623 00:25:52.960489 DQS0 = 0, DQS1 = 0
2624 00:25:52.963566 DQM Delay:
2625 00:25:52.963979 DQM0 = 121, DQM1 = 113
2626 00:25:52.964309 DQ Delay:
2627 00:25:52.970713 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2628 00:25:52.973598 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2629 00:25:52.976896 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2630 00:25:52.980552 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2631 00:25:52.980964
2632 00:25:52.981282
2633 00:25:52.981584 ==
2634 00:25:52.983546 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 00:25:52.986890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 00:25:52.987307 ==
2637 00:25:52.987697
2638 00:25:52.988226
2639 00:25:52.990163 TX Vref Scan disable
2640 00:25:52.993840 == TX Byte 0 ==
2641 00:25:52.997167 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2642 00:25:53.000286 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2643 00:25:53.003814 == TX Byte 1 ==
2644 00:25:53.007072 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2645 00:25:53.010371 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2646 00:25:53.010784 ==
2647 00:25:53.013992 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 00:25:53.017017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 00:25:53.017543 ==
2650 00:25:53.030987 TX Vref=22, minBit 0, minWin=24, winSum=411
2651 00:25:53.034491 TX Vref=24, minBit 0, minWin=24, winSum=415
2652 00:25:53.037835 TX Vref=26, minBit 4, minWin=25, winSum=422
2653 00:25:53.040742 TX Vref=28, minBit 7, minWin=25, winSum=424
2654 00:25:53.043850 TX Vref=30, minBit 0, minWin=26, winSum=426
2655 00:25:53.047583 TX Vref=32, minBit 5, minWin=25, winSum=424
2656 00:25:53.054096 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 30
2657 00:25:53.054556
2658 00:25:53.057412 Final TX Range 1 Vref 30
2659 00:25:53.057825
2660 00:25:53.058150 ==
2661 00:25:53.060663 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 00:25:53.064078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 00:25:53.064491 ==
2664 00:25:53.064816
2665 00:25:53.065119
2666 00:25:53.067262 TX Vref Scan disable
2667 00:25:53.070930 == TX Byte 0 ==
2668 00:25:53.074175 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2669 00:25:53.077683 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2670 00:25:53.081182 == TX Byte 1 ==
2671 00:25:53.084216 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2672 00:25:53.087618 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2673 00:25:53.088090
2674 00:25:53.090659 [DATLAT]
2675 00:25:53.091066 Freq=1200, CH0 RK0
2676 00:25:53.091393
2677 00:25:53.094148 DATLAT Default: 0xd
2678 00:25:53.094650 0, 0xFFFF, sum = 0
2679 00:25:53.097345 1, 0xFFFF, sum = 0
2680 00:25:53.097761 2, 0xFFFF, sum = 0
2681 00:25:53.100615 3, 0xFFFF, sum = 0
2682 00:25:53.101156 4, 0xFFFF, sum = 0
2683 00:25:53.104362 5, 0xFFFF, sum = 0
2684 00:25:53.104779 6, 0xFFFF, sum = 0
2685 00:25:53.107683 7, 0xFFFF, sum = 0
2686 00:25:53.108203 8, 0xFFFF, sum = 0
2687 00:25:53.110924 9, 0xFFFF, sum = 0
2688 00:25:53.114420 10, 0xFFFF, sum = 0
2689 00:25:53.114941 11, 0xFFFF, sum = 0
2690 00:25:53.117667 12, 0x0, sum = 1
2691 00:25:53.118150 13, 0x0, sum = 2
2692 00:25:53.118485 14, 0x0, sum = 3
2693 00:25:53.121192 15, 0x0, sum = 4
2694 00:25:53.121712 best_step = 13
2695 00:25:53.122037
2696 00:25:53.122340 ==
2697 00:25:53.124489 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 00:25:53.131287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 00:25:53.131830 ==
2700 00:25:53.132158 RX Vref Scan: 1
2701 00:25:53.132461
2702 00:25:53.134228 Set Vref Range= 32 -> 127
2703 00:25:53.134637
2704 00:25:53.137861 RX Vref 32 -> 127, step: 1
2705 00:25:53.138399
2706 00:25:53.141342 RX Delay -13 -> 252, step: 4
2707 00:25:53.141837
2708 00:25:53.144798 Set Vref, RX VrefLevel [Byte0]: 32
2709 00:25:53.145296 [Byte1]: 32
2710 00:25:53.149262
2711 00:25:53.149766 Set Vref, RX VrefLevel [Byte0]: 33
2712 00:25:53.152040 [Byte1]: 33
2713 00:25:53.156678
2714 00:25:53.157250 Set Vref, RX VrefLevel [Byte0]: 34
2715 00:25:53.160266 [Byte1]: 34
2716 00:25:53.165081
2717 00:25:53.165613 Set Vref, RX VrefLevel [Byte0]: 35
2718 00:25:53.167887 [Byte1]: 35
2719 00:25:53.172792
2720 00:25:53.173336 Set Vref, RX VrefLevel [Byte0]: 36
2721 00:25:53.175869 [Byte1]: 36
2722 00:25:53.180501
2723 00:25:53.181054 Set Vref, RX VrefLevel [Byte0]: 37
2724 00:25:53.184124 [Byte1]: 37
2725 00:25:53.188551
2726 00:25:53.189138 Set Vref, RX VrefLevel [Byte0]: 38
2727 00:25:53.191816 [Byte1]: 38
2728 00:25:53.196149
2729 00:25:53.196603 Set Vref, RX VrefLevel [Byte0]: 39
2730 00:25:53.199477 [Byte1]: 39
2731 00:25:53.204389
2732 00:25:53.204894 Set Vref, RX VrefLevel [Byte0]: 40
2733 00:25:53.207614 [Byte1]: 40
2734 00:25:53.211896
2735 00:25:53.212442 Set Vref, RX VrefLevel [Byte0]: 41
2736 00:25:53.215434 [Byte1]: 41
2737 00:25:53.220286
2738 00:25:53.220850 Set Vref, RX VrefLevel [Byte0]: 42
2739 00:25:53.223381 [Byte1]: 42
2740 00:25:53.227562
2741 00:25:53.228015 Set Vref, RX VrefLevel [Byte0]: 43
2742 00:25:53.231126 [Byte1]: 43
2743 00:25:53.235448
2744 00:25:53.235925 Set Vref, RX VrefLevel [Byte0]: 44
2745 00:25:53.238749 [Byte1]: 44
2746 00:25:53.243284
2747 00:25:53.243743 Set Vref, RX VrefLevel [Byte0]: 45
2748 00:25:53.246795 [Byte1]: 45
2749 00:25:53.251336
2750 00:25:53.251830 Set Vref, RX VrefLevel [Byte0]: 46
2751 00:25:53.255185 [Byte1]: 46
2752 00:25:53.259834
2753 00:25:53.260343 Set Vref, RX VrefLevel [Byte0]: 47
2754 00:25:53.263057 [Byte1]: 47
2755 00:25:53.267640
2756 00:25:53.268183 Set Vref, RX VrefLevel [Byte0]: 48
2757 00:25:53.270949 [Byte1]: 48
2758 00:25:53.275390
2759 00:25:53.275986 Set Vref, RX VrefLevel [Byte0]: 49
2760 00:25:53.278900 [Byte1]: 49
2761 00:25:53.282996
2762 00:25:53.283559 Set Vref, RX VrefLevel [Byte0]: 50
2763 00:25:53.286377 [Byte1]: 50
2764 00:25:53.291102
2765 00:25:53.291694 Set Vref, RX VrefLevel [Byte0]: 51
2766 00:25:53.294271 [Byte1]: 51
2767 00:25:53.298893
2768 00:25:53.299385 Set Vref, RX VrefLevel [Byte0]: 52
2769 00:25:53.302295 [Byte1]: 52
2770 00:25:53.306853
2771 00:25:53.307329 Set Vref, RX VrefLevel [Byte0]: 53
2772 00:25:53.309805 [Byte1]: 53
2773 00:25:53.314708
2774 00:25:53.315118 Set Vref, RX VrefLevel [Byte0]: 54
2775 00:25:53.317631 [Byte1]: 54
2776 00:25:53.322648
2777 00:25:53.323131 Set Vref, RX VrefLevel [Byte0]: 55
2778 00:25:53.325599 [Byte1]: 55
2779 00:25:53.330758
2780 00:25:53.331309 Set Vref, RX VrefLevel [Byte0]: 56
2781 00:25:53.333693 [Byte1]: 56
2782 00:25:53.338355
2783 00:25:53.338846 Set Vref, RX VrefLevel [Byte0]: 57
2784 00:25:53.341650 [Byte1]: 57
2785 00:25:53.346154
2786 00:25:53.346568 Set Vref, RX VrefLevel [Byte0]: 58
2787 00:25:53.349627 [Byte1]: 58
2788 00:25:53.353948
2789 00:25:53.354362 Set Vref, RX VrefLevel [Byte0]: 59
2790 00:25:53.357356 [Byte1]: 59
2791 00:25:53.361721
2792 00:25:53.362136 Set Vref, RX VrefLevel [Byte0]: 60
2793 00:25:53.365167 [Byte1]: 60
2794 00:25:53.369610
2795 00:25:53.370021 Set Vref, RX VrefLevel [Byte0]: 61
2796 00:25:53.373488 [Byte1]: 61
2797 00:25:53.377924
2798 00:25:53.378438 Set Vref, RX VrefLevel [Byte0]: 62
2799 00:25:53.381374 [Byte1]: 62
2800 00:25:53.385382
2801 00:25:53.385861 Set Vref, RX VrefLevel [Byte0]: 63
2802 00:25:53.388867 [Byte1]: 63
2803 00:25:53.393669
2804 00:25:53.394201 Set Vref, RX VrefLevel [Byte0]: 64
2805 00:25:53.397411 [Byte1]: 64
2806 00:25:53.401700
2807 00:25:53.402197 Set Vref, RX VrefLevel [Byte0]: 65
2808 00:25:53.404604 [Byte1]: 65
2809 00:25:53.409017
2810 00:25:53.409430 Set Vref, RX VrefLevel [Byte0]: 66
2811 00:25:53.412733 [Byte1]: 66
2812 00:25:53.417793
2813 00:25:53.418303 Set Vref, RX VrefLevel [Byte0]: 67
2814 00:25:53.420404 [Byte1]: 67
2815 00:25:53.424863
2816 00:25:53.425350 Set Vref, RX VrefLevel [Byte0]: 68
2817 00:25:53.428518 [Byte1]: 68
2818 00:25:53.433404
2819 00:25:53.433973 Set Vref, RX VrefLevel [Byte0]: 69
2820 00:25:53.436244 [Byte1]: 69
2821 00:25:53.441183
2822 00:25:53.441850 Final RX Vref Byte 0 = 54 to rank0
2823 00:25:53.444397 Final RX Vref Byte 1 = 48 to rank0
2824 00:25:53.447655 Final RX Vref Byte 0 = 54 to rank1
2825 00:25:53.451474 Final RX Vref Byte 1 = 48 to rank1==
2826 00:25:53.454576 Dram Type= 6, Freq= 0, CH_0, rank 0
2827 00:25:53.457700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2828 00:25:53.460999 ==
2829 00:25:53.461430 DQS Delay:
2830 00:25:53.461819 DQS0 = 0, DQS1 = 0
2831 00:25:53.464353 DQM Delay:
2832 00:25:53.464906 DQM0 = 120, DQM1 = 111
2833 00:25:53.467444 DQ Delay:
2834 00:25:53.471058 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2835 00:25:53.474547 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =124
2836 00:25:53.478055 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =106
2837 00:25:53.481383 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2838 00:25:53.482099
2839 00:25:53.482622
2840 00:25:53.487850 [DQSOSCAuto] RK0, (LSB)MR18= 0x1610, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
2841 00:25:53.491068 CH0 RK0: MR19=404, MR18=1610
2842 00:25:53.497355 CH0_RK0: MR19=0x404, MR18=0x1610, DQSOSC=401, MR23=63, INC=40, DEC=27
2843 00:25:53.497776
2844 00:25:53.500873 ----->DramcWriteLeveling(PI) begin...
2845 00:25:53.501295 ==
2846 00:25:53.504067 Dram Type= 6, Freq= 0, CH_0, rank 1
2847 00:25:53.507609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 00:25:53.508030 ==
2849 00:25:53.511109 Write leveling (Byte 0): 34 => 34
2850 00:25:53.514603 Write leveling (Byte 1): 28 => 28
2851 00:25:53.517579 DramcWriteLeveling(PI) end<-----
2852 00:25:53.517801
2853 00:25:53.517976 ==
2854 00:25:53.520831 Dram Type= 6, Freq= 0, CH_0, rank 1
2855 00:25:53.524334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2856 00:25:53.527689 ==
2857 00:25:53.527947 [Gating] SW mode calibration
2858 00:25:53.537920 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2859 00:25:53.541101 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2860 00:25:53.544437 0 15 0 | B1->B0 | 3333 2e2e | 1 1 | (0 0) (1 1)
2861 00:25:53.550859 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 00:25:53.554470 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 00:25:53.557393 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 00:25:53.564595 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 00:25:53.567820 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 00:25:53.571216 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2867 00:25:53.577990 0 15 28 | B1->B0 | 3232 2f2f | 1 1 | (0 1) (0 1)
2868 00:25:53.581394 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 00:25:53.584502 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 00:25:53.588136 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 00:25:53.594213 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 00:25:53.598086 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 00:25:53.601123 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 00:25:53.607570 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2875 00:25:53.611413 1 0 28 | B1->B0 | 3838 3737 | 0 0 | (0 0) (0 0)
2876 00:25:53.614563 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 00:25:53.621075 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 00:25:53.624354 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 00:25:53.627852 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 00:25:53.634765 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 00:25:53.638075 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 00:25:53.641333 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 00:25:53.648031 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2884 00:25:53.651138 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2885 00:25:53.654769 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 00:25:53.661300 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 00:25:53.664873 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 00:25:53.668476 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 00:25:53.671129 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 00:25:53.677875 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 00:25:53.681416 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 00:25:53.684504 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 00:25:53.691553 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 00:25:53.695070 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 00:25:53.697724 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 00:25:53.704884 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 00:25:53.708119 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 00:25:53.711977 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 00:25:53.718033 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2900 00:25:53.721894 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 00:25:53.724676 Total UI for P1: 0, mck2ui 16
2902 00:25:53.728037 best dqsien dly found for B0: ( 1, 3, 28)
2903 00:25:53.731836 Total UI for P1: 0, mck2ui 16
2904 00:25:53.734863 best dqsien dly found for B1: ( 1, 3, 28)
2905 00:25:53.738154 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2906 00:25:53.741627 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2907 00:25:53.741744
2908 00:25:53.744829 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2909 00:25:53.748187 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2910 00:25:53.751856 [Gating] SW calibration Done
2911 00:25:53.751973 ==
2912 00:25:53.754994 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 00:25:53.758173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 00:25:53.758293 ==
2915 00:25:53.761764 RX Vref Scan: 0
2916 00:25:53.761882
2917 00:25:53.762002 RX Vref 0 -> 0, step: 1
2918 00:25:53.765207
2919 00:25:53.765324 RX Delay -40 -> 252, step: 8
2920 00:25:53.772179 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2921 00:25:53.775304 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2922 00:25:53.778454 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2923 00:25:53.782015 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2924 00:25:53.785029 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2925 00:25:53.788388 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2926 00:25:53.795261 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2927 00:25:53.798732 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2928 00:25:53.801596 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2929 00:25:53.805007 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2930 00:25:53.808289 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2931 00:25:53.815268 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2932 00:25:53.818806 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2933 00:25:53.821708 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2934 00:25:53.825218 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2935 00:25:53.828878 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2936 00:25:53.831763 ==
2937 00:25:53.831903 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 00:25:53.838400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 00:25:53.838631 ==
2940 00:25:53.838835 DQS Delay:
2941 00:25:53.842193 DQS0 = 0, DQS1 = 0
2942 00:25:53.842415 DQM Delay:
2943 00:25:53.845338 DQM0 = 122, DQM1 = 112
2944 00:25:53.845495 DQ Delay:
2945 00:25:53.848553 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2946 00:25:53.852076 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2947 00:25:53.855174 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2948 00:25:53.858788 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2949 00:25:53.858928
2950 00:25:53.859037
2951 00:25:53.859139 ==
2952 00:25:53.861805 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 00:25:53.868345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 00:25:53.868488 ==
2955 00:25:53.868598
2956 00:25:53.868700
2957 00:25:53.868798 TX Vref Scan disable
2958 00:25:53.872164 == TX Byte 0 ==
2959 00:25:53.875084 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2960 00:25:53.878460 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2961 00:25:53.882331 == TX Byte 1 ==
2962 00:25:53.885786 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2963 00:25:53.888668 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2964 00:25:53.892144 ==
2965 00:25:53.895485 Dram Type= 6, Freq= 0, CH_0, rank 1
2966 00:25:53.899204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2967 00:25:53.899682 ==
2968 00:25:53.910886 TX Vref=22, minBit 1, minWin=24, winSum=411
2969 00:25:53.914131 TX Vref=24, minBit 1, minWin=25, winSum=420
2970 00:25:53.917427 TX Vref=26, minBit 0, minWin=26, winSum=423
2971 00:25:53.920607 TX Vref=28, minBit 12, minWin=25, winSum=422
2972 00:25:53.923982 TX Vref=30, minBit 0, minWin=26, winSum=424
2973 00:25:53.926958 TX Vref=32, minBit 0, minWin=26, winSum=424
2974 00:25:53.933667 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30
2975 00:25:53.933838
2976 00:25:53.937269 Final TX Range 1 Vref 30
2977 00:25:53.937383
2978 00:25:53.937473 ==
2979 00:25:53.940399 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 00:25:53.943637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 00:25:53.943740 ==
2982 00:25:53.943820
2983 00:25:53.946989
2984 00:25:53.947080 TX Vref Scan disable
2985 00:25:53.950634 == TX Byte 0 ==
2986 00:25:53.953877 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2987 00:25:53.956880 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2988 00:25:53.960247 == TX Byte 1 ==
2989 00:25:53.963401 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2990 00:25:53.967328 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2991 00:25:53.967792
2992 00:25:53.970595 [DATLAT]
2993 00:25:53.971006 Freq=1200, CH0 RK1
2994 00:25:53.971336
2995 00:25:53.974260 DATLAT Default: 0xd
2996 00:25:53.974674 0, 0xFFFF, sum = 0
2997 00:25:53.977267 1, 0xFFFF, sum = 0
2998 00:25:53.977687 2, 0xFFFF, sum = 0
2999 00:25:53.980654 3, 0xFFFF, sum = 0
3000 00:25:53.981080 4, 0xFFFF, sum = 0
3001 00:25:53.984305 5, 0xFFFF, sum = 0
3002 00:25:53.984729 6, 0xFFFF, sum = 0
3003 00:25:53.987591 7, 0xFFFF, sum = 0
3004 00:25:53.990895 8, 0xFFFF, sum = 0
3005 00:25:53.991316 9, 0xFFFF, sum = 0
3006 00:25:53.994167 10, 0xFFFF, sum = 0
3007 00:25:53.994466 11, 0xFFFF, sum = 0
3008 00:25:53.997102 12, 0x0, sum = 1
3009 00:25:53.997328 13, 0x0, sum = 2
3010 00:25:54.000350 14, 0x0, sum = 3
3011 00:25:54.000576 15, 0x0, sum = 4
3012 00:25:54.000757 best_step = 13
3013 00:25:54.000921
3014 00:25:54.003833 ==
3015 00:25:54.007128 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 00:25:54.010584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 00:25:54.010833 ==
3018 00:25:54.011051 RX Vref Scan: 0
3019 00:25:54.011258
3020 00:25:54.013508 RX Vref 0 -> 0, step: 1
3021 00:25:54.013718
3022 00:25:54.016895 RX Delay -13 -> 252, step: 4
3023 00:25:54.020172 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3024 00:25:54.023821 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3025 00:25:54.030077 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3026 00:25:54.033669 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3027 00:25:54.037459 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3028 00:25:54.040697 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3029 00:25:54.043637 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3030 00:25:54.050583 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3031 00:25:54.053867 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3032 00:25:54.057228 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3033 00:25:54.060923 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3034 00:25:54.063977 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3035 00:25:54.070786 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3036 00:25:54.073882 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3037 00:25:54.077287 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3038 00:25:54.080727 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3039 00:25:54.080966 ==
3040 00:25:54.083919 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 00:25:54.090549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 00:25:54.090789 ==
3043 00:25:54.090979 DQS Delay:
3044 00:25:54.091158 DQS0 = 0, DQS1 = 0
3045 00:25:54.094161 DQM Delay:
3046 00:25:54.094550 DQM0 = 121, DQM1 = 110
3047 00:25:54.097391 DQ Delay:
3048 00:25:54.100851 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3049 00:25:54.104201 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3050 00:25:54.107774 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3051 00:25:54.110559 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3052 00:25:54.110796
3053 00:25:54.111001
3054 00:25:54.117324 [DQSOSCAuto] RK1, (LSB)MR18= 0xff0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 404 ps
3055 00:25:54.121047 CH0 RK1: MR19=403, MR18=FF0
3056 00:25:54.127619 CH0_RK1: MR19=0x403, MR18=0xFF0, DQSOSC=404, MR23=63, INC=40, DEC=26
3057 00:25:54.130708 [RxdqsGatingPostProcess] freq 1200
3058 00:25:54.137214 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3059 00:25:54.137480 best DQS0 dly(2T, 0.5T) = (0, 11)
3060 00:25:54.140588 best DQS1 dly(2T, 0.5T) = (0, 12)
3061 00:25:54.143986 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3062 00:25:54.147441 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3063 00:25:54.150712 best DQS0 dly(2T, 0.5T) = (0, 11)
3064 00:25:54.154357 best DQS1 dly(2T, 0.5T) = (0, 11)
3065 00:25:54.157402 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3066 00:25:54.160705 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3067 00:25:54.163877 Pre-setting of DQS Precalculation
3068 00:25:54.167257 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3069 00:25:54.170425 ==
3070 00:25:54.173964 Dram Type= 6, Freq= 0, CH_1, rank 0
3071 00:25:54.177087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 00:25:54.177470 ==
3073 00:25:54.181094 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3074 00:25:54.187127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3075 00:25:54.196494 [CA 0] Center 37 (7~68) winsize 62
3076 00:25:54.200021 [CA 1] Center 37 (7~68) winsize 62
3077 00:25:54.203199 [CA 2] Center 35 (5~65) winsize 61
3078 00:25:54.206565 [CA 3] Center 34 (5~64) winsize 60
3079 00:25:54.209837 [CA 4] Center 34 (4~64) winsize 61
3080 00:25:54.212937 [CA 5] Center 33 (3~63) winsize 61
3081 00:25:54.213165
3082 00:25:54.216893 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3083 00:25:54.217155
3084 00:25:54.220152 [CATrainingPosCal] consider 1 rank data
3085 00:25:54.222942 u2DelayCellTimex100 = 270/100 ps
3086 00:25:54.226594 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3087 00:25:54.229489 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3088 00:25:54.233807 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3089 00:25:54.240212 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3090 00:25:54.243384 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3091 00:25:54.246581 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3092 00:25:54.246696
3093 00:25:54.250414 CA PerBit enable=1, Macro0, CA PI delay=33
3094 00:25:54.250547
3095 00:25:54.253514 [CBTSetCACLKResult] CA Dly = 33
3096 00:25:54.253639 CS Dly: 7 (0~38)
3097 00:25:54.253764 ==
3098 00:25:54.257023 Dram Type= 6, Freq= 0, CH_1, rank 1
3099 00:25:54.263402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3100 00:25:54.263589 ==
3101 00:25:54.266731 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3102 00:25:54.273496 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3103 00:25:54.281963 [CA 0] Center 37 (7~68) winsize 62
3104 00:25:54.285249 [CA 1] Center 38 (8~68) winsize 61
3105 00:25:54.288411 [CA 2] Center 35 (5~65) winsize 61
3106 00:25:54.291927 [CA 3] Center 34 (4~65) winsize 62
3107 00:25:54.294970 [CA 4] Center 34 (4~65) winsize 62
3108 00:25:54.298422 [CA 5] Center 34 (4~64) winsize 61
3109 00:25:54.298535
3110 00:25:54.302140 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3111 00:25:54.302223
3112 00:25:54.305067 [CATrainingPosCal] consider 2 rank data
3113 00:25:54.308603 u2DelayCellTimex100 = 270/100 ps
3114 00:25:54.311852 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3115 00:25:54.314849 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3116 00:25:54.321822 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3117 00:25:54.325277 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3118 00:25:54.328498 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3119 00:25:54.332073 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3120 00:25:54.332179
3121 00:25:54.335183 CA PerBit enable=1, Macro0, CA PI delay=33
3122 00:25:54.335288
3123 00:25:54.338790 [CBTSetCACLKResult] CA Dly = 33
3124 00:25:54.338896 CS Dly: 8 (0~41)
3125 00:25:54.338979
3126 00:25:54.342201 ----->DramcWriteLeveling(PI) begin...
3127 00:25:54.345712 ==
3128 00:25:54.345827 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 00:25:54.351648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 00:25:54.351763 ==
3131 00:25:54.355407 Write leveling (Byte 0): 26 => 26
3132 00:25:54.358778 Write leveling (Byte 1): 27 => 27
3133 00:25:54.361962 DramcWriteLeveling(PI) end<-----
3134 00:25:54.362051
3135 00:25:54.362120 ==
3136 00:25:54.365377 Dram Type= 6, Freq= 0, CH_1, rank 0
3137 00:25:54.368688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 00:25:54.368781 ==
3139 00:25:54.372063 [Gating] SW mode calibration
3140 00:25:54.378354 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3141 00:25:54.382256 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3142 00:25:54.388808 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 00:25:54.391849 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 00:25:54.395416 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 00:25:54.402069 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 00:25:54.405315 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 00:25:54.408562 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 00:25:54.414982 0 15 24 | B1->B0 | 3232 2d2d | 0 0 | (0 0) (0 0)
3149 00:25:54.418889 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3150 00:25:54.422333 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 00:25:54.428724 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 00:25:54.432495 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 00:25:54.435423 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 00:25:54.442011 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 00:25:54.445521 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3156 00:25:54.448652 1 0 24 | B1->B0 | 3838 4141 | 1 0 | (0 0) (0 0)
3157 00:25:54.452067 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 00:25:54.458872 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 00:25:54.462731 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 00:25:54.465533 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 00:25:54.472544 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 00:25:54.475926 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 00:25:54.478597 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 00:25:54.485839 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3165 00:25:54.488812 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3166 00:25:54.492153 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 00:25:54.498738 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 00:25:54.501985 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 00:25:54.505447 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 00:25:54.511857 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 00:25:54.515711 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 00:25:54.518812 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 00:25:54.525764 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 00:25:54.528909 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 00:25:54.532564 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 00:25:54.535307 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 00:25:54.542405 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 00:25:54.545549 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 00:25:54.548879 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 00:25:54.555193 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3181 00:25:54.558962 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 00:25:54.562365 Total UI for P1: 0, mck2ui 16
3183 00:25:54.565710 best dqsien dly found for B0: ( 1, 3, 24)
3184 00:25:54.569365 Total UI for P1: 0, mck2ui 16
3185 00:25:54.572622 best dqsien dly found for B1: ( 1, 3, 24)
3186 00:25:54.575992 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3187 00:25:54.579545 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3188 00:25:54.579716
3189 00:25:54.582637 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3190 00:25:54.586437 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3191 00:25:54.589247 [Gating] SW calibration Done
3192 00:25:54.589498 ==
3193 00:25:54.592684 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 00:25:54.595873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 00:25:54.599246 ==
3196 00:25:54.599530 RX Vref Scan: 0
3197 00:25:54.599764
3198 00:25:54.602339 RX Vref 0 -> 0, step: 1
3199 00:25:54.602681
3200 00:25:54.605684 RX Delay -40 -> 252, step: 8
3201 00:25:54.609071 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3202 00:25:54.612782 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3203 00:25:54.615801 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3204 00:25:54.619262 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3205 00:25:54.622420 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3206 00:25:54.629192 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3207 00:25:54.632890 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3208 00:25:54.636238 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3209 00:25:54.639439 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3210 00:25:54.643485 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3211 00:25:54.649699 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3212 00:25:54.652800 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3213 00:25:54.656572 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3214 00:25:54.659484 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3215 00:25:54.662912 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3216 00:25:54.669430 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3217 00:25:54.670086 ==
3218 00:25:54.672924 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 00:25:54.676313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 00:25:54.676864 ==
3221 00:25:54.677471 DQS Delay:
3222 00:25:54.679860 DQS0 = 0, DQS1 = 0
3223 00:25:54.680487 DQM Delay:
3224 00:25:54.682976 DQM0 = 120, DQM1 = 116
3225 00:25:54.683409 DQ Delay:
3226 00:25:54.686157 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3227 00:25:54.689356 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3228 00:25:54.692856 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3229 00:25:54.696306 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3230 00:25:54.696634
3231 00:25:54.699099
3232 00:25:54.699452 ==
3233 00:25:54.702901 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 00:25:54.705894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 00:25:54.706234 ==
3236 00:25:54.706534
3237 00:25:54.706840
3238 00:25:54.709493 TX Vref Scan disable
3239 00:25:54.709766 == TX Byte 0 ==
3240 00:25:54.712519 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3241 00:25:54.719116 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3242 00:25:54.719390 == TX Byte 1 ==
3243 00:25:54.722750 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3244 00:25:54.729216 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3245 00:25:54.729307 ==
3246 00:25:54.732779 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 00:25:54.735721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 00:25:54.735842 ==
3249 00:25:54.747527 TX Vref=22, minBit 11, minWin=24, winSum=413
3250 00:25:54.750940 TX Vref=24, minBit 10, minWin=25, winSum=418
3251 00:25:54.754585 TX Vref=26, minBit 1, minWin=26, winSum=427
3252 00:25:54.757663 TX Vref=28, minBit 1, minWin=26, winSum=426
3253 00:25:54.761068 TX Vref=30, minBit 9, minWin=26, winSum=430
3254 00:25:54.764462 TX Vref=32, minBit 9, minWin=26, winSum=427
3255 00:25:54.770935 [TxChooseVref] Worse bit 9, Min win 26, Win sum 430, Final Vref 30
3256 00:25:54.771052
3257 00:25:54.774308 Final TX Range 1 Vref 30
3258 00:25:54.774401
3259 00:25:54.774473 ==
3260 00:25:54.777854 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 00:25:54.781200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 00:25:54.781315 ==
3263 00:25:54.781435
3264 00:25:54.784538
3265 00:25:54.784652 TX Vref Scan disable
3266 00:25:54.788196 == TX Byte 0 ==
3267 00:25:54.791093 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3268 00:25:54.794625 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3269 00:25:54.797777 == TX Byte 1 ==
3270 00:25:54.801143 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3271 00:25:54.804353 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3272 00:25:54.804510
3273 00:25:54.808074 [DATLAT]
3274 00:25:54.808254 Freq=1200, CH1 RK0
3275 00:25:54.808399
3276 00:25:54.811187 DATLAT Default: 0xd
3277 00:25:54.811397 0, 0xFFFF, sum = 0
3278 00:25:54.815056 1, 0xFFFF, sum = 0
3279 00:25:54.815337 2, 0xFFFF, sum = 0
3280 00:25:54.818515 3, 0xFFFF, sum = 0
3281 00:25:54.818775 4, 0xFFFF, sum = 0
3282 00:25:54.821495 5, 0xFFFF, sum = 0
3283 00:25:54.821824 6, 0xFFFF, sum = 0
3284 00:25:54.825047 7, 0xFFFF, sum = 0
3285 00:25:54.825469 8, 0xFFFF, sum = 0
3286 00:25:54.827944 9, 0xFFFF, sum = 0
3287 00:25:54.831454 10, 0xFFFF, sum = 0
3288 00:25:54.831983 11, 0xFFFF, sum = 0
3289 00:25:54.835123 12, 0x0, sum = 1
3290 00:25:54.835585 13, 0x0, sum = 2
3291 00:25:54.835934 14, 0x0, sum = 3
3292 00:25:54.838673 15, 0x0, sum = 4
3293 00:25:54.839097 best_step = 13
3294 00:25:54.839429
3295 00:25:54.839790 ==
3296 00:25:54.841475 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 00:25:54.848780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 00:25:54.849302 ==
3299 00:25:54.849639 RX Vref Scan: 1
3300 00:25:54.849949
3301 00:25:54.851835 Set Vref Range= 32 -> 127
3302 00:25:54.852355
3303 00:25:54.855021 RX Vref 32 -> 127, step: 1
3304 00:25:54.855622
3305 00:25:54.858149 RX Delay -5 -> 252, step: 4
3306 00:25:54.858571
3307 00:25:54.861508 Set Vref, RX VrefLevel [Byte0]: 32
3308 00:25:54.861935 [Byte1]: 32
3309 00:25:54.866603
3310 00:25:54.867020 Set Vref, RX VrefLevel [Byte0]: 33
3311 00:25:54.869710 [Byte1]: 33
3312 00:25:54.874073
3313 00:25:54.874489 Set Vref, RX VrefLevel [Byte0]: 34
3314 00:25:54.877631 [Byte1]: 34
3315 00:25:54.882257
3316 00:25:54.882669 Set Vref, RX VrefLevel [Byte0]: 35
3317 00:25:54.885369 [Byte1]: 35
3318 00:25:54.889992
3319 00:25:54.890387 Set Vref, RX VrefLevel [Byte0]: 36
3320 00:25:54.893149 [Byte1]: 36
3321 00:25:54.897985
3322 00:25:54.898371 Set Vref, RX VrefLevel [Byte0]: 37
3323 00:25:54.901105 [Byte1]: 37
3324 00:25:54.905752
3325 00:25:54.906135 Set Vref, RX VrefLevel [Byte0]: 38
3326 00:25:54.909477 [Byte1]: 38
3327 00:25:54.913725
3328 00:25:54.914106 Set Vref, RX VrefLevel [Byte0]: 39
3329 00:25:54.916995 [Byte1]: 39
3330 00:25:54.921404
3331 00:25:54.921773 Set Vref, RX VrefLevel [Byte0]: 40
3332 00:25:54.924694 [Byte1]: 40
3333 00:25:54.929004
3334 00:25:54.929313 Set Vref, RX VrefLevel [Byte0]: 41
3335 00:25:54.932293 [Byte1]: 41
3336 00:25:54.936770
3337 00:25:54.937065 Set Vref, RX VrefLevel [Byte0]: 42
3338 00:25:54.940376 [Byte1]: 42
3339 00:25:54.945157
3340 00:25:54.945453 Set Vref, RX VrefLevel [Byte0]: 43
3341 00:25:54.947788 [Byte1]: 43
3342 00:25:54.952520
3343 00:25:54.952819 Set Vref, RX VrefLevel [Byte0]: 44
3344 00:25:54.955724 [Byte1]: 44
3345 00:25:54.960458
3346 00:25:54.960758 Set Vref, RX VrefLevel [Byte0]: 45
3347 00:25:54.963680 [Byte1]: 45
3348 00:25:54.968443
3349 00:25:54.968737 Set Vref, RX VrefLevel [Byte0]: 46
3350 00:25:54.971868 [Byte1]: 46
3351 00:25:54.976196
3352 00:25:54.976533 Set Vref, RX VrefLevel [Byte0]: 47
3353 00:25:54.979300 [Byte1]: 47
3354 00:25:54.983807
3355 00:25:54.984223 Set Vref, RX VrefLevel [Byte0]: 48
3356 00:25:54.987419 [Byte1]: 48
3357 00:25:54.992387
3358 00:25:54.992731 Set Vref, RX VrefLevel [Byte0]: 49
3359 00:25:54.994912 [Byte1]: 49
3360 00:25:54.999722
3361 00:25:55.000014 Set Vref, RX VrefLevel [Byte0]: 50
3362 00:25:55.002875 [Byte1]: 50
3363 00:25:55.007804
3364 00:25:55.010828 Set Vref, RX VrefLevel [Byte0]: 51
3365 00:25:55.011143 [Byte1]: 51
3366 00:25:55.015182
3367 00:25:55.015477 Set Vref, RX VrefLevel [Byte0]: 52
3368 00:25:55.018446 [Byte1]: 52
3369 00:25:55.023104
3370 00:25:55.023401 Set Vref, RX VrefLevel [Byte0]: 53
3371 00:25:55.026714 [Byte1]: 53
3372 00:25:55.030766
3373 00:25:55.031065 Set Vref, RX VrefLevel [Byte0]: 54
3374 00:25:55.034284 [Byte1]: 54
3375 00:25:55.038907
3376 00:25:55.039200 Set Vref, RX VrefLevel [Byte0]: 55
3377 00:25:55.042317 [Byte1]: 55
3378 00:25:55.047055
3379 00:25:55.047349 Set Vref, RX VrefLevel [Byte0]: 56
3380 00:25:55.050637 [Byte1]: 56
3381 00:25:55.054836
3382 00:25:55.055274 Set Vref, RX VrefLevel [Byte0]: 57
3383 00:25:55.058127 [Byte1]: 57
3384 00:25:55.062912
3385 00:25:55.063326 Set Vref, RX VrefLevel [Byte0]: 58
3386 00:25:55.066290 [Byte1]: 58
3387 00:25:55.071231
3388 00:25:55.071822 Set Vref, RX VrefLevel [Byte0]: 59
3389 00:25:55.073920 [Byte1]: 59
3390 00:25:55.078854
3391 00:25:55.079414 Set Vref, RX VrefLevel [Byte0]: 60
3392 00:25:55.082308 [Byte1]: 60
3393 00:25:55.086833
3394 00:25:55.087389 Set Vref, RX VrefLevel [Byte0]: 61
3395 00:25:55.089699 [Byte1]: 61
3396 00:25:55.094426
3397 00:25:55.094986 Set Vref, RX VrefLevel [Byte0]: 62
3398 00:25:55.097569 [Byte1]: 62
3399 00:25:55.101689
3400 00:25:55.102148 Set Vref, RX VrefLevel [Byte0]: 63
3401 00:25:55.105351 [Byte1]: 63
3402 00:25:55.110028
3403 00:25:55.110669 Set Vref, RX VrefLevel [Byte0]: 64
3404 00:25:55.113220 [Byte1]: 64
3405 00:25:55.117828
3406 00:25:55.118441 Set Vref, RX VrefLevel [Byte0]: 65
3407 00:25:55.120845 [Byte1]: 65
3408 00:25:55.125959
3409 00:25:55.126482 Set Vref, RX VrefLevel [Byte0]: 66
3410 00:25:55.128693 [Byte1]: 66
3411 00:25:55.133223
3412 00:25:55.133818 Set Vref, RX VrefLevel [Byte0]: 67
3413 00:25:55.136494 [Byte1]: 67
3414 00:25:55.141311
3415 00:25:55.141722 Set Vref, RX VrefLevel [Byte0]: 68
3416 00:25:55.144483 [Byte1]: 68
3417 00:25:55.149073
3418 00:25:55.149601 Set Vref, RX VrefLevel [Byte0]: 69
3419 00:25:55.152390 [Byte1]: 69
3420 00:25:55.156550
3421 00:25:55.157132 Final RX Vref Byte 0 = 54 to rank0
3422 00:25:55.159868 Final RX Vref Byte 1 = 48 to rank0
3423 00:25:55.163381 Final RX Vref Byte 0 = 54 to rank1
3424 00:25:55.166997 Final RX Vref Byte 1 = 48 to rank1==
3425 00:25:55.170387 Dram Type= 6, Freq= 0, CH_1, rank 0
3426 00:25:55.174031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3427 00:25:55.176654 ==
3428 00:25:55.177067 DQS Delay:
3429 00:25:55.177395 DQS0 = 0, DQS1 = 0
3430 00:25:55.179967 DQM Delay:
3431 00:25:55.180381 DQM0 = 120, DQM1 = 116
3432 00:25:55.183585 DQ Delay:
3433 00:25:55.187397 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3434 00:25:55.190398 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3435 00:25:55.193631 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3436 00:25:55.196742 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3437 00:25:55.197357
3438 00:25:55.197884
3439 00:25:55.204040 [DQSOSCAuto] RK0, (LSB)MR18= 0x113, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3440 00:25:55.207158 CH1 RK0: MR19=404, MR18=113
3441 00:25:55.214022 CH1_RK0: MR19=0x404, MR18=0x113, DQSOSC=402, MR23=63, INC=40, DEC=27
3442 00:25:55.214629
3443 00:25:55.217262 ----->DramcWriteLeveling(PI) begin...
3444 00:25:55.217886 ==
3445 00:25:55.220280 Dram Type= 6, Freq= 0, CH_1, rank 1
3446 00:25:55.223800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 00:25:55.224242 ==
3448 00:25:55.226681 Write leveling (Byte 0): 27 => 27
3449 00:25:55.230196 Write leveling (Byte 1): 28 => 28
3450 00:25:55.233611 DramcWriteLeveling(PI) end<-----
3451 00:25:55.234131
3452 00:25:55.234668 ==
3453 00:25:55.236894 Dram Type= 6, Freq= 0, CH_1, rank 1
3454 00:25:55.240088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3455 00:25:55.243287 ==
3456 00:25:55.244010 [Gating] SW mode calibration
3457 00:25:55.250517 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3458 00:25:55.256971 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3459 00:25:55.260320 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 00:25:55.266709 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 00:25:55.270384 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 00:25:55.274028 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 00:25:55.280046 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 00:25:55.283378 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3465 00:25:55.286656 0 15 24 | B1->B0 | 2727 3333 | 0 1 | (1 0) (1 1)
3466 00:25:55.293752 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
3467 00:25:55.296963 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 00:25:55.300640 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 00:25:55.306944 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 00:25:55.310340 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 00:25:55.313157 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 00:25:55.319933 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3473 00:25:55.323282 1 0 24 | B1->B0 | 4545 2f2f | 0 0 | (0 0) (1 1)
3474 00:25:55.326933 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 00:25:55.330428 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 00:25:55.336618 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 00:25:55.340662 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 00:25:55.343625 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 00:25:55.349990 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 00:25:55.353177 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3481 00:25:55.356519 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3482 00:25:55.363168 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3483 00:25:55.366306 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 00:25:55.369920 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 00:25:55.376706 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 00:25:55.379947 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 00:25:55.383017 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 00:25:55.389877 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 00:25:55.393409 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 00:25:55.396503 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 00:25:55.402943 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 00:25:55.406250 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 00:25:55.409980 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 00:25:55.415951 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 00:25:55.419798 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 00:25:55.422849 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3497 00:25:55.430074 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3498 00:25:55.430180 Total UI for P1: 0, mck2ui 16
3499 00:25:55.433042 best dqsien dly found for B1: ( 1, 3, 20)
3500 00:25:55.439316 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3501 00:25:55.442875 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 00:25:55.446455 Total UI for P1: 0, mck2ui 16
3503 00:25:55.449404 best dqsien dly found for B0: ( 1, 3, 26)
3504 00:25:55.452930 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3505 00:25:55.455987 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3506 00:25:55.456085
3507 00:25:55.459442 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3508 00:25:55.466015 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3509 00:25:55.466120 [Gating] SW calibration Done
3510 00:25:55.466213 ==
3511 00:25:55.469923 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 00:25:55.476612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 00:25:55.476693 ==
3514 00:25:55.476773 RX Vref Scan: 0
3515 00:25:55.476850
3516 00:25:55.479550 RX Vref 0 -> 0, step: 1
3517 00:25:55.479622
3518 00:25:55.482969 RX Delay -40 -> 252, step: 8
3519 00:25:55.486480 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3520 00:25:55.489639 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3521 00:25:55.492882 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3522 00:25:55.496195 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3523 00:25:55.502748 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3524 00:25:55.505961 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3525 00:25:55.509197 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3526 00:25:55.512734 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3527 00:25:55.515830 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3528 00:25:55.522853 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3529 00:25:55.525887 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3530 00:25:55.529654 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3531 00:25:55.532593 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3532 00:25:55.539597 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3533 00:25:55.542663 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3534 00:25:55.546227 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3535 00:25:55.546390 ==
3536 00:25:55.549674 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 00:25:55.552520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 00:25:55.552677 ==
3539 00:25:55.556217 DQS Delay:
3540 00:25:55.556392 DQS0 = 0, DQS1 = 0
3541 00:25:55.559451 DQM Delay:
3542 00:25:55.559674 DQM0 = 120, DQM1 = 118
3543 00:25:55.559853 DQ Delay:
3544 00:25:55.563006 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3545 00:25:55.565969 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3546 00:25:55.572595 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3547 00:25:55.576292 DQ12 =127, DQ13 =123, DQ14 =123, DQ15 =123
3548 00:25:55.576473
3549 00:25:55.576597
3550 00:25:55.576710 ==
3551 00:25:55.579343 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 00:25:55.583053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 00:25:55.583248 ==
3554 00:25:55.583443
3555 00:25:55.583614
3556 00:25:55.585991 TX Vref Scan disable
3557 00:25:55.586181 == TX Byte 0 ==
3558 00:25:55.592600 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3559 00:25:55.596121 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3560 00:25:55.599414 == TX Byte 1 ==
3561 00:25:55.602603 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3562 00:25:55.606192 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3563 00:25:55.606435 ==
3564 00:25:55.609700 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 00:25:55.612658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 00:25:55.612893 ==
3567 00:25:55.625827 TX Vref=22, minBit 9, minWin=24, winSum=419
3568 00:25:55.629051 TX Vref=24, minBit 0, minWin=26, winSum=425
3569 00:25:55.632074 TX Vref=26, minBit 10, minWin=25, winSum=428
3570 00:25:55.635436 TX Vref=28, minBit 9, minWin=26, winSum=433
3571 00:25:55.639171 TX Vref=30, minBit 9, minWin=26, winSum=434
3572 00:25:55.645437 TX Vref=32, minBit 9, minWin=26, winSum=431
3573 00:25:55.648959 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3574 00:25:55.649039
3575 00:25:55.652324 Final TX Range 1 Vref 30
3576 00:25:55.652405
3577 00:25:55.652468 ==
3578 00:25:55.655296 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 00:25:55.658746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 00:25:55.658855 ==
3581 00:25:55.661811
3582 00:25:55.661915
3583 00:25:55.662006 TX Vref Scan disable
3584 00:25:55.665411 == TX Byte 0 ==
3585 00:25:55.668729 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3586 00:25:55.671883 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3587 00:25:55.675262 == TX Byte 1 ==
3588 00:25:55.678599 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3589 00:25:55.681833 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3590 00:25:55.685551
3591 00:25:55.685676 [DATLAT]
3592 00:25:55.685761 Freq=1200, CH1 RK1
3593 00:25:55.685859
3594 00:25:55.688412 DATLAT Default: 0xd
3595 00:25:55.688510 0, 0xFFFF, sum = 0
3596 00:25:55.691871 1, 0xFFFF, sum = 0
3597 00:25:55.691992 2, 0xFFFF, sum = 0
3598 00:25:55.695366 3, 0xFFFF, sum = 0
3599 00:25:55.695451 4, 0xFFFF, sum = 0
3600 00:25:55.698907 5, 0xFFFF, sum = 0
3601 00:25:55.702096 6, 0xFFFF, sum = 0
3602 00:25:55.702180 7, 0xFFFF, sum = 0
3603 00:25:55.705692 8, 0xFFFF, sum = 0
3604 00:25:55.705866 9, 0xFFFF, sum = 0
3605 00:25:55.708587 10, 0xFFFF, sum = 0
3606 00:25:55.708684 11, 0xFFFF, sum = 0
3607 00:25:55.712094 12, 0x0, sum = 1
3608 00:25:55.712195 13, 0x0, sum = 2
3609 00:25:55.715511 14, 0x0, sum = 3
3610 00:25:55.715620 15, 0x0, sum = 4
3611 00:25:55.715739 best_step = 13
3612 00:25:55.715878
3613 00:25:55.718429 ==
3614 00:25:55.721864 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 00:25:55.725415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 00:25:55.725526 ==
3617 00:25:55.725612 RX Vref Scan: 0
3618 00:25:55.725693
3619 00:25:55.728762 RX Vref 0 -> 0, step: 1
3620 00:25:55.728881
3621 00:25:55.732680 RX Delay -5 -> 252, step: 4
3622 00:25:55.735395 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3623 00:25:55.739246 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3624 00:25:55.745411 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3625 00:25:55.749080 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3626 00:25:55.752875 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3627 00:25:55.755633 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3628 00:25:55.759165 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3629 00:25:55.766032 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3630 00:25:55.769296 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3631 00:25:55.772643 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3632 00:25:55.775763 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3633 00:25:55.779275 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3634 00:25:55.785576 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3635 00:25:55.789331 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3636 00:25:55.792353 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3637 00:25:55.796032 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3638 00:25:55.796582 ==
3639 00:25:55.798929 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 00:25:55.805627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 00:25:55.806014 ==
3642 00:25:55.806321 DQS Delay:
3643 00:25:55.809052 DQS0 = 0, DQS1 = 0
3644 00:25:55.809450 DQM Delay:
3645 00:25:55.809756 DQM0 = 120, DQM1 = 116
3646 00:25:55.812350 DQ Delay:
3647 00:25:55.815179 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3648 00:25:55.818413 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3649 00:25:55.821741 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3650 00:25:55.825050 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3651 00:25:55.825131
3652 00:25:55.825194
3653 00:25:55.835413 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 403 ps
3654 00:25:55.835532 CH1 RK1: MR19=403, MR18=10EC
3655 00:25:55.841863 CH1_RK1: MR19=0x403, MR18=0x10EC, DQSOSC=403, MR23=63, INC=40, DEC=26
3656 00:25:55.845526 [RxdqsGatingPostProcess] freq 1200
3657 00:25:55.852061 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3658 00:25:55.854983 best DQS0 dly(2T, 0.5T) = (0, 11)
3659 00:25:55.858532 best DQS1 dly(2T, 0.5T) = (0, 11)
3660 00:25:55.862316 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3661 00:25:55.865329 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3662 00:25:55.868733 best DQS0 dly(2T, 0.5T) = (0, 11)
3663 00:25:55.869217 best DQS1 dly(2T, 0.5T) = (0, 11)
3664 00:25:55.872334 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3665 00:25:55.875087 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3666 00:25:55.878894 Pre-setting of DQS Precalculation
3667 00:25:55.885462 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3668 00:25:55.892094 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3669 00:25:55.898647 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3670 00:25:55.899218
3671 00:25:55.899878
3672 00:25:55.901859 [Calibration Summary] 2400 Mbps
3673 00:25:55.902297 CH 0, Rank 0
3674 00:25:55.905305 SW Impedance : PASS
3675 00:25:55.908822 DUTY Scan : NO K
3676 00:25:55.909240 ZQ Calibration : PASS
3677 00:25:55.912146 Jitter Meter : NO K
3678 00:25:55.915596 CBT Training : PASS
3679 00:25:55.916061 Write leveling : PASS
3680 00:25:55.918717 RX DQS gating : PASS
3681 00:25:55.922187 RX DQ/DQS(RDDQC) : PASS
3682 00:25:55.922603 TX DQ/DQS : PASS
3683 00:25:55.925494 RX DATLAT : PASS
3684 00:25:55.928749 RX DQ/DQS(Engine): PASS
3685 00:25:55.929253 TX OE : NO K
3686 00:25:55.931650 All Pass.
3687 00:25:55.932124
3688 00:25:55.932501 CH 0, Rank 1
3689 00:25:55.935039 SW Impedance : PASS
3690 00:25:55.935597 DUTY Scan : NO K
3691 00:25:55.938599 ZQ Calibration : PASS
3692 00:25:55.941829 Jitter Meter : NO K
3693 00:25:55.942344 CBT Training : PASS
3694 00:25:55.944971 Write leveling : PASS
3695 00:25:55.948421 RX DQS gating : PASS
3696 00:25:55.949047 RX DQ/DQS(RDDQC) : PASS
3697 00:25:55.951445 TX DQ/DQS : PASS
3698 00:25:55.951853 RX DATLAT : PASS
3699 00:25:55.954606 RX DQ/DQS(Engine): PASS
3700 00:25:55.958103 TX OE : NO K
3701 00:25:55.958342 All Pass.
3702 00:25:55.958524
3703 00:25:55.958693 CH 1, Rank 0
3704 00:25:55.961732 SW Impedance : PASS
3705 00:25:55.964500 DUTY Scan : NO K
3706 00:25:55.964684 ZQ Calibration : PASS
3707 00:25:55.968433 Jitter Meter : NO K
3708 00:25:55.971813 CBT Training : PASS
3709 00:25:55.971965 Write leveling : PASS
3710 00:25:55.974824 RX DQS gating : PASS
3711 00:25:55.978280 RX DQ/DQS(RDDQC) : PASS
3712 00:25:55.978480 TX DQ/DQS : PASS
3713 00:25:55.981305 RX DATLAT : PASS
3714 00:25:55.985053 RX DQ/DQS(Engine): PASS
3715 00:25:55.985205 TX OE : NO K
3716 00:25:55.987901 All Pass.
3717 00:25:55.988052
3718 00:25:55.988220 CH 1, Rank 1
3719 00:25:55.991409 SW Impedance : PASS
3720 00:25:55.991525 DUTY Scan : NO K
3721 00:25:55.994743 ZQ Calibration : PASS
3722 00:25:55.997952 Jitter Meter : NO K
3723 00:25:55.998059 CBT Training : PASS
3724 00:25:56.001341 Write leveling : PASS
3725 00:25:56.004268 RX DQS gating : PASS
3726 00:25:56.004350 RX DQ/DQS(RDDQC) : PASS
3727 00:25:56.007660 TX DQ/DQS : PASS
3728 00:25:56.007750 RX DATLAT : PASS
3729 00:25:56.011104 RX DQ/DQS(Engine): PASS
3730 00:25:56.014749 TX OE : NO K
3731 00:25:56.014834 All Pass.
3732 00:25:56.014903
3733 00:25:56.017699 DramC Write-DBI off
3734 00:25:56.017782 PER_BANK_REFRESH: Hybrid Mode
3735 00:25:56.021153 TX_TRACKING: ON
3736 00:25:56.031037 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3737 00:25:56.034531 [FAST_K] Save calibration result to emmc
3738 00:25:56.037962 dramc_set_vcore_voltage set vcore to 650000
3739 00:25:56.038045 Read voltage for 600, 5
3740 00:25:56.040810 Vio18 = 0
3741 00:25:56.040892 Vcore = 650000
3742 00:25:56.040956 Vdram = 0
3743 00:25:56.044142 Vddq = 0
3744 00:25:56.044225 Vmddr = 0
3745 00:25:56.047748 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3746 00:25:56.054175 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3747 00:25:56.057636 MEM_TYPE=3, freq_sel=19
3748 00:25:56.061289 sv_algorithm_assistance_LP4_1600
3749 00:25:56.064227 ============ PULL DRAM RESETB DOWN ============
3750 00:25:56.067877 ========== PULL DRAM RESETB DOWN end =========
3751 00:25:56.074597 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3752 00:25:56.077963 ===================================
3753 00:25:56.078042 LPDDR4 DRAM CONFIGURATION
3754 00:25:56.081155 ===================================
3755 00:25:56.084116 EX_ROW_EN[0] = 0x0
3756 00:25:56.084199 EX_ROW_EN[1] = 0x0
3757 00:25:56.088016 LP4Y_EN = 0x0
3758 00:25:56.088100 WORK_FSP = 0x0
3759 00:25:56.090940 WL = 0x2
3760 00:25:56.094135 RL = 0x2
3761 00:25:56.094222 BL = 0x2
3762 00:25:56.097461 RPST = 0x0
3763 00:25:56.097565 RD_PRE = 0x0
3764 00:25:56.100879 WR_PRE = 0x1
3765 00:25:56.100975 WR_PST = 0x0
3766 00:25:56.104390 DBI_WR = 0x0
3767 00:25:56.104473 DBI_RD = 0x0
3768 00:25:56.107940 OTF = 0x1
3769 00:25:56.110900 ===================================
3770 00:25:56.114170 ===================================
3771 00:25:56.114254 ANA top config
3772 00:25:56.117305 ===================================
3773 00:25:56.120830 DLL_ASYNC_EN = 0
3774 00:25:56.124364 ALL_SLAVE_EN = 1
3775 00:25:56.124447 NEW_RANK_MODE = 1
3776 00:25:56.127514 DLL_IDLE_MODE = 1
3777 00:25:56.130688 LP45_APHY_COMB_EN = 1
3778 00:25:56.134319 TX_ODT_DIS = 1
3779 00:25:56.134400 NEW_8X_MODE = 1
3780 00:25:56.137198 ===================================
3781 00:25:56.140741 ===================================
3782 00:25:56.144197 data_rate = 1200
3783 00:25:56.147622 CKR = 1
3784 00:25:56.150661 DQ_P2S_RATIO = 8
3785 00:25:56.154007 ===================================
3786 00:25:56.157671 CA_P2S_RATIO = 8
3787 00:25:56.161186 DQ_CA_OPEN = 0
3788 00:25:56.161275 DQ_SEMI_OPEN = 0
3789 00:25:56.164123 CA_SEMI_OPEN = 0
3790 00:25:56.167951 CA_FULL_RATE = 0
3791 00:25:56.170665 DQ_CKDIV4_EN = 1
3792 00:25:56.174216 CA_CKDIV4_EN = 1
3793 00:25:56.177604 CA_PREDIV_EN = 0
3794 00:25:56.177680 PH8_DLY = 0
3795 00:25:56.181047 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3796 00:25:56.184006 DQ_AAMCK_DIV = 4
3797 00:25:56.187443 CA_AAMCK_DIV = 4
3798 00:25:56.190773 CA_ADMCK_DIV = 4
3799 00:25:56.193870 DQ_TRACK_CA_EN = 0
3800 00:25:56.193949 CA_PICK = 600
3801 00:25:56.197436 CA_MCKIO = 600
3802 00:25:56.200794 MCKIO_SEMI = 0
3803 00:25:56.203917 PLL_FREQ = 2288
3804 00:25:56.207484 DQ_UI_PI_RATIO = 32
3805 00:25:56.210843 CA_UI_PI_RATIO = 0
3806 00:25:56.213648 ===================================
3807 00:25:56.216907 ===================================
3808 00:25:56.220495 memory_type:LPDDR4
3809 00:25:56.220578 GP_NUM : 10
3810 00:25:56.223846 SRAM_EN : 1
3811 00:25:56.223956 MD32_EN : 0
3812 00:25:56.226943 ===================================
3813 00:25:56.230168 [ANA_INIT] >>>>>>>>>>>>>>
3814 00:25:56.233378 <<<<<< [CONFIGURE PHASE]: ANA_TX
3815 00:25:56.236942 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3816 00:25:56.240572 ===================================
3817 00:25:56.243943 data_rate = 1200,PCW = 0X5800
3818 00:25:56.247005 ===================================
3819 00:25:56.250519 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3820 00:25:56.253935 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3821 00:25:56.260082 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3822 00:25:56.266514 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3823 00:25:56.270167 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3824 00:25:56.273688 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3825 00:25:56.273790 [ANA_INIT] flow start
3826 00:25:56.276412 [ANA_INIT] PLL >>>>>>>>
3827 00:25:56.280028 [ANA_INIT] PLL <<<<<<<<
3828 00:25:56.280115 [ANA_INIT] MIDPI >>>>>>>>
3829 00:25:56.283406 [ANA_INIT] MIDPI <<<<<<<<
3830 00:25:56.286889 [ANA_INIT] DLL >>>>>>>>
3831 00:25:56.286974 [ANA_INIT] flow end
3832 00:25:56.293336 ============ LP4 DIFF to SE enter ============
3833 00:25:56.296639 ============ LP4 DIFF to SE exit ============
3834 00:25:56.299932 [ANA_INIT] <<<<<<<<<<<<<
3835 00:25:56.300017 [Flow] Enable top DCM control >>>>>
3836 00:25:56.303024 [Flow] Enable top DCM control <<<<<
3837 00:25:56.306372 Enable DLL master slave shuffle
3838 00:25:56.313448 ==============================================================
3839 00:25:56.317000 Gating Mode config
3840 00:25:56.319912 ==============================================================
3841 00:25:56.323372 Config description:
3842 00:25:56.333246 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3843 00:25:56.339911 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3844 00:25:56.343203 SELPH_MODE 0: By rank 1: By Phase
3845 00:25:56.349840 ==============================================================
3846 00:25:56.353464 GAT_TRACK_EN = 1
3847 00:25:56.356177 RX_GATING_MODE = 2
3848 00:25:56.359701 RX_GATING_TRACK_MODE = 2
3849 00:25:56.359786 SELPH_MODE = 1
3850 00:25:56.363328 PICG_EARLY_EN = 1
3851 00:25:56.366170 VALID_LAT_VALUE = 1
3852 00:25:56.373132 ==============================================================
3853 00:25:56.376264 Enter into Gating configuration >>>>
3854 00:25:56.379262 Exit from Gating configuration <<<<
3855 00:25:56.382856 Enter into DVFS_PRE_config >>>>>
3856 00:25:56.392788 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3857 00:25:56.396137 Exit from DVFS_PRE_config <<<<<
3858 00:25:56.399544 Enter into PICG configuration >>>>
3859 00:25:56.403021 Exit from PICG configuration <<<<
3860 00:25:56.406121 [RX_INPUT] configuration >>>>>
3861 00:25:56.409445 [RX_INPUT] configuration <<<<<
3862 00:25:56.412823 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3863 00:25:56.419339 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3864 00:25:56.425743 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3865 00:25:56.432697 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3866 00:25:56.439066 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3867 00:25:56.442803 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3868 00:25:56.449752 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3869 00:25:56.452738 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3870 00:25:56.455977 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3871 00:25:56.459764 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3872 00:25:56.462473 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3873 00:25:56.469091 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3874 00:25:56.472444 ===================================
3875 00:25:56.475876 LPDDR4 DRAM CONFIGURATION
3876 00:25:56.479229 ===================================
3877 00:25:56.479331 EX_ROW_EN[0] = 0x0
3878 00:25:56.482327 EX_ROW_EN[1] = 0x0
3879 00:25:56.482414 LP4Y_EN = 0x0
3880 00:25:56.485874 WORK_FSP = 0x0
3881 00:25:56.485957 WL = 0x2
3882 00:25:56.489125 RL = 0x2
3883 00:25:56.489209 BL = 0x2
3884 00:25:56.492082 RPST = 0x0
3885 00:25:56.492164 RD_PRE = 0x0
3886 00:25:56.495614 WR_PRE = 0x1
3887 00:25:56.495697 WR_PST = 0x0
3888 00:25:56.498772 DBI_WR = 0x0
3889 00:25:56.498886 DBI_RD = 0x0
3890 00:25:56.502216 OTF = 0x1
3891 00:25:56.505798 ===================================
3892 00:25:56.509047 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3893 00:25:56.512130 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3894 00:25:56.519156 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3895 00:25:56.522167 ===================================
3896 00:25:56.522249 LPDDR4 DRAM CONFIGURATION
3897 00:25:56.525562 ===================================
3898 00:25:56.529050 EX_ROW_EN[0] = 0x10
3899 00:25:56.532300 EX_ROW_EN[1] = 0x0
3900 00:25:56.532382 LP4Y_EN = 0x0
3901 00:25:56.535660 WORK_FSP = 0x0
3902 00:25:56.535741 WL = 0x2
3903 00:25:56.538979 RL = 0x2
3904 00:25:56.539060 BL = 0x2
3905 00:25:56.542393 RPST = 0x0
3906 00:25:56.542484 RD_PRE = 0x0
3907 00:25:56.545263 WR_PRE = 0x1
3908 00:25:56.545344 WR_PST = 0x0
3909 00:25:56.548704 DBI_WR = 0x0
3910 00:25:56.548785 DBI_RD = 0x0
3911 00:25:56.552103 OTF = 0x1
3912 00:25:56.555828 ===================================
3913 00:25:56.561891 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3914 00:25:56.565431 nWR fixed to 30
3915 00:25:56.568939 [ModeRegInit_LP4] CH0 RK0
3916 00:25:56.569021 [ModeRegInit_LP4] CH0 RK1
3917 00:25:56.571805 [ModeRegInit_LP4] CH1 RK0
3918 00:25:56.575343 [ModeRegInit_LP4] CH1 RK1
3919 00:25:56.575425 match AC timing 17
3920 00:25:56.582278 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3921 00:25:56.585706 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3922 00:25:56.588365 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3923 00:25:56.595362 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3924 00:25:56.598330 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3925 00:25:56.598417 ==
3926 00:25:56.602093 Dram Type= 6, Freq= 0, CH_0, rank 0
3927 00:25:56.605058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3928 00:25:56.605140 ==
3929 00:25:56.611775 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3930 00:25:56.618264 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3931 00:25:56.621371 [CA 0] Center 36 (5~67) winsize 63
3932 00:25:56.624870 [CA 1] Center 36 (5~67) winsize 63
3933 00:25:56.628265 [CA 2] Center 33 (3~64) winsize 62
3934 00:25:56.631409 [CA 3] Center 33 (2~64) winsize 63
3935 00:25:56.634670 [CA 4] Center 33 (2~64) winsize 63
3936 00:25:56.638222 [CA 5] Center 32 (2~63) winsize 62
3937 00:25:56.638304
3938 00:25:56.641303 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3939 00:25:56.641385
3940 00:25:56.644653 [CATrainingPosCal] consider 1 rank data
3941 00:25:56.648374 u2DelayCellTimex100 = 270/100 ps
3942 00:25:56.651744 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3943 00:25:56.655198 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3944 00:25:56.657960 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3945 00:25:56.661402 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3946 00:25:56.664998 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3947 00:25:56.668488 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3948 00:25:56.671392
3949 00:25:56.674753 CA PerBit enable=1, Macro0, CA PI delay=32
3950 00:25:56.674835
3951 00:25:56.678367 [CBTSetCACLKResult] CA Dly = 32
3952 00:25:56.678449 CS Dly: 5 (0~36)
3953 00:25:56.678513 ==
3954 00:25:56.681746 Dram Type= 6, Freq= 0, CH_0, rank 1
3955 00:25:56.684723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3956 00:25:56.684805 ==
3957 00:25:56.691966 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3958 00:25:56.698071 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3959 00:25:56.701483 [CA 0] Center 35 (5~66) winsize 62
3960 00:25:56.704838 [CA 1] Center 35 (5~66) winsize 62
3961 00:25:56.708243 [CA 2] Center 34 (3~65) winsize 63
3962 00:25:56.711624 [CA 3] Center 33 (3~64) winsize 62
3963 00:25:56.714900 [CA 4] Center 33 (2~64) winsize 63
3964 00:25:56.718010 [CA 5] Center 32 (2~63) winsize 62
3965 00:25:56.718092
3966 00:25:56.721224 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3967 00:25:56.721306
3968 00:25:56.725002 [CATrainingPosCal] consider 2 rank data
3969 00:25:56.727820 u2DelayCellTimex100 = 270/100 ps
3970 00:25:56.731230 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3971 00:25:56.734717 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3972 00:25:56.738135 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3973 00:25:56.741454 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3974 00:25:56.744878 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3975 00:25:56.750996 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3976 00:25:56.751078
3977 00:25:56.754505 CA PerBit enable=1, Macro0, CA PI delay=32
3978 00:25:56.754586
3979 00:25:56.757955 [CBTSetCACLKResult] CA Dly = 32
3980 00:25:56.758037 CS Dly: 4 (0~35)
3981 00:25:56.758102
3982 00:25:56.761255 ----->DramcWriteLeveling(PI) begin...
3983 00:25:56.761337 ==
3984 00:25:56.764908 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 00:25:56.771180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 00:25:56.771263 ==
3987 00:25:56.774607 Write leveling (Byte 0): 35 => 35
3988 00:25:56.774701 Write leveling (Byte 1): 33 => 33
3989 00:25:56.777818 DramcWriteLeveling(PI) end<-----
3990 00:25:56.777899
3991 00:25:56.777963 ==
3992 00:25:56.781251 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 00:25:56.788194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 00:25:56.788276 ==
3995 00:25:56.791031 [Gating] SW mode calibration
3996 00:25:56.798047 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3997 00:25:56.801082 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3998 00:25:56.807929 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3999 00:25:56.811469 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 00:25:56.814899 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 00:25:56.821135 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4002 00:25:56.824405 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
4003 00:25:56.828180 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 00:25:56.831476 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 00:25:56.837849 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 00:25:56.841178 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 00:25:56.844170 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 00:25:56.851065 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 00:25:56.854543 0 10 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
4010 00:25:56.857950 0 10 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
4011 00:25:56.864664 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 00:25:56.867512 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 00:25:56.870862 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 00:25:56.877566 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 00:25:56.880933 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 00:25:56.883988 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 00:25:56.890779 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 00:25:56.894121 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4019 00:25:56.897505 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 00:25:56.904197 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 00:25:56.907373 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 00:25:56.910703 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 00:25:56.917113 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 00:25:56.920595 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 00:25:56.923783 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 00:25:56.930595 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 00:25:56.933733 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 00:25:56.937077 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 00:25:56.944147 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 00:25:56.946980 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 00:25:56.950725 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 00:25:56.957385 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 00:25:56.960219 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4034 00:25:56.963636 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4035 00:25:56.967237 Total UI for P1: 0, mck2ui 16
4036 00:25:56.970662 best dqsien dly found for B0: ( 0, 13, 12)
4037 00:25:56.973641 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 00:25:56.977145 Total UI for P1: 0, mck2ui 16
4039 00:25:56.980080 best dqsien dly found for B1: ( 0, 13, 16)
4040 00:25:56.987054 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4041 00:25:56.990534 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4042 00:25:56.990616
4043 00:25:56.993885 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4044 00:25:56.996952 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4045 00:25:57.000959 [Gating] SW calibration Done
4046 00:25:57.001041 ==
4047 00:25:57.003538 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 00:25:57.007180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 00:25:57.007262 ==
4050 00:25:57.010357 RX Vref Scan: 0
4051 00:25:57.010439
4052 00:25:57.010503 RX Vref 0 -> 0, step: 1
4053 00:25:57.010564
4054 00:25:57.013524 RX Delay -230 -> 252, step: 16
4055 00:25:57.017256 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4056 00:25:57.023553 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4057 00:25:57.027099 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4058 00:25:57.030450 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4059 00:25:57.033509 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4060 00:25:57.036903 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4061 00:25:57.043784 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4062 00:25:57.047161 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4063 00:25:57.050102 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4064 00:25:57.053466 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4065 00:25:57.060419 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4066 00:25:57.063302 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4067 00:25:57.066986 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4068 00:25:57.070420 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4069 00:25:57.076597 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4070 00:25:57.080040 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4071 00:25:57.080128 ==
4072 00:25:57.083243 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 00:25:57.087049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 00:25:57.087131 ==
4075 00:25:57.090018 DQS Delay:
4076 00:25:57.090100 DQS0 = 0, DQS1 = 0
4077 00:25:57.090165 DQM Delay:
4078 00:25:57.093384 DQM0 = 49, DQM1 = 45
4079 00:25:57.093466 DQ Delay:
4080 00:25:57.096794 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4081 00:25:57.099850 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =57
4082 00:25:57.103219 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4083 00:25:57.106472 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4084 00:25:57.106554
4085 00:25:57.106618
4086 00:25:57.106678 ==
4087 00:25:57.109852 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 00:25:57.116423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 00:25:57.116505 ==
4090 00:25:57.116570
4091 00:25:57.116629
4092 00:25:57.116686 TX Vref Scan disable
4093 00:25:57.120178 == TX Byte 0 ==
4094 00:25:57.123431 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4095 00:25:57.126863 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4096 00:25:57.130275 == TX Byte 1 ==
4097 00:25:57.133598 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4098 00:25:57.136625 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4099 00:25:57.140296 ==
4100 00:25:57.143326 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 00:25:57.146751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 00:25:57.146832 ==
4103 00:25:57.146897
4104 00:25:57.146957
4105 00:25:57.150084 TX Vref Scan disable
4106 00:25:57.150165 == TX Byte 0 ==
4107 00:25:57.156384 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4108 00:25:57.159872 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4109 00:25:57.163227 == TX Byte 1 ==
4110 00:25:57.166360 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4111 00:25:57.169669 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4112 00:25:57.169767
4113 00:25:57.169857 [DATLAT]
4114 00:25:57.173207 Freq=600, CH0 RK0
4115 00:25:57.173304
4116 00:25:57.173395 DATLAT Default: 0x9
4117 00:25:57.176578 0, 0xFFFF, sum = 0
4118 00:25:57.176678 1, 0xFFFF, sum = 0
4119 00:25:57.180080 2, 0xFFFF, sum = 0
4120 00:25:57.183585 3, 0xFFFF, sum = 0
4121 00:25:57.183684 4, 0xFFFF, sum = 0
4122 00:25:57.186381 5, 0xFFFF, sum = 0
4123 00:25:57.186453 6, 0xFFFF, sum = 0
4124 00:25:57.189753 7, 0xFFFF, sum = 0
4125 00:25:57.189851 8, 0x0, sum = 1
4126 00:25:57.189941 9, 0x0, sum = 2
4127 00:25:57.193355 10, 0x0, sum = 3
4128 00:25:57.193455 11, 0x0, sum = 4
4129 00:25:57.196838 best_step = 9
4130 00:25:57.196917
4131 00:25:57.197005 ==
4132 00:25:57.199830 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 00:25:57.203270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 00:25:57.203368 ==
4135 00:25:57.206756 RX Vref Scan: 1
4136 00:25:57.206846
4137 00:25:57.206912 RX Vref 0 -> 0, step: 1
4138 00:25:57.206974
4139 00:25:57.210193 RX Delay -163 -> 252, step: 8
4140 00:25:57.210275
4141 00:25:57.213273 Set Vref, RX VrefLevel [Byte0]: 54
4142 00:25:57.216649 [Byte1]: 48
4143 00:25:57.220534
4144 00:25:57.220615 Final RX Vref Byte 0 = 54 to rank0
4145 00:25:57.223890 Final RX Vref Byte 1 = 48 to rank0
4146 00:25:57.227183 Final RX Vref Byte 0 = 54 to rank1
4147 00:25:57.230665 Final RX Vref Byte 1 = 48 to rank1==
4148 00:25:57.233511 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 00:25:57.240483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 00:25:57.240565 ==
4151 00:25:57.240630 DQS Delay:
4152 00:25:57.240689 DQS0 = 0, DQS1 = 0
4153 00:25:57.243751 DQM Delay:
4154 00:25:57.243832 DQM0 = 53, DQM1 = 46
4155 00:25:57.247309 DQ Delay:
4156 00:25:57.250324 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4157 00:25:57.253980 DQ4 =52, DQ5 =44, DQ6 =64, DQ7 =64
4158 00:25:57.254061 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4159 00:25:57.260437 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52
4160 00:25:57.260518
4161 00:25:57.260583
4162 00:25:57.266954 [DQSOSCAuto] RK0, (LSB)MR18= 0x7568, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 387 ps
4163 00:25:57.270264 CH0 RK0: MR19=808, MR18=7568
4164 00:25:57.277214 CH0_RK0: MR19=0x808, MR18=0x7568, DQSOSC=387, MR23=63, INC=175, DEC=116
4165 00:25:57.277296
4166 00:25:57.280470 ----->DramcWriteLeveling(PI) begin...
4167 00:25:57.280596 ==
4168 00:25:57.283437 Dram Type= 6, Freq= 0, CH_0, rank 1
4169 00:25:57.287130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 00:25:57.287212 ==
4171 00:25:57.290563 Write leveling (Byte 0): 35 => 35
4172 00:25:57.293537 Write leveling (Byte 1): 31 => 31
4173 00:25:57.296889 DramcWriteLeveling(PI) end<-----
4174 00:25:57.296970
4175 00:25:57.297034 ==
4176 00:25:57.300157 Dram Type= 6, Freq= 0, CH_0, rank 1
4177 00:25:57.303368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 00:25:57.303453 ==
4179 00:25:57.306866 [Gating] SW mode calibration
4180 00:25:57.313910 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4181 00:25:57.320149 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4182 00:25:57.323534 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4183 00:25:57.326901 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4184 00:25:57.333699 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4185 00:25:57.336994 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (0 0) (0 1)
4186 00:25:57.340188 0 9 16 | B1->B0 | 2525 2b2b | 0 0 | (1 1) (0 0)
4187 00:25:57.347077 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 00:25:57.350565 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 00:25:57.353245 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 00:25:57.360035 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 00:25:57.363231 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 00:25:57.366999 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 00:25:57.373452 0 10 12 | B1->B0 | 2828 2424 | 0 0 | (1 1) (0 0)
4194 00:25:57.376957 0 10 16 | B1->B0 | 4040 4545 | 0 0 | (0 0) (0 0)
4195 00:25:57.380370 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 00:25:57.386728 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 00:25:57.390578 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 00:25:57.393952 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 00:25:57.400737 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 00:25:57.403413 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 00:25:57.406825 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4202 00:25:57.413652 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4203 00:25:57.417287 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 00:25:57.420153 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 00:25:57.423444 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 00:25:57.430680 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 00:25:57.433480 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 00:25:57.437128 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 00:25:57.443843 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 00:25:57.447216 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 00:25:57.450248 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 00:25:57.457292 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 00:25:57.460356 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 00:25:57.463513 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 00:25:57.470406 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 00:25:57.473667 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 00:25:57.476729 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 00:25:57.483819 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 00:25:57.483902 Total UI for P1: 0, mck2ui 16
4220 00:25:57.489921 best dqsien dly found for B0: ( 0, 13, 14)
4221 00:25:57.490003 Total UI for P1: 0, mck2ui 16
4222 00:25:57.493357 best dqsien dly found for B1: ( 0, 13, 14)
4223 00:25:57.499981 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4224 00:25:57.503779 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4225 00:25:57.503861
4226 00:25:57.506728 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4227 00:25:57.510397 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4228 00:25:57.513243 [Gating] SW calibration Done
4229 00:25:57.513325 ==
4230 00:25:57.516698 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 00:25:57.520322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 00:25:57.520413 ==
4233 00:25:57.523186 RX Vref Scan: 0
4234 00:25:57.523267
4235 00:25:57.523331 RX Vref 0 -> 0, step: 1
4236 00:25:57.523392
4237 00:25:57.526496 RX Delay -230 -> 252, step: 16
4238 00:25:57.530084 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4239 00:25:57.536863 iDelay=218, Bit 1, Center 57 (-86 ~ 201) 288
4240 00:25:57.540099 iDelay=218, Bit 2, Center 57 (-86 ~ 201) 288
4241 00:25:57.543503 iDelay=218, Bit 3, Center 57 (-86 ~ 201) 288
4242 00:25:57.546457 iDelay=218, Bit 4, Center 65 (-86 ~ 217) 304
4243 00:25:57.549739 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4244 00:25:57.556646 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4245 00:25:57.560411 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4246 00:25:57.562955 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4247 00:25:57.566505 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4248 00:25:57.569724 iDelay=218, Bit 10, Center 57 (-86 ~ 201) 288
4249 00:25:57.576283 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4250 00:25:57.579878 iDelay=218, Bit 12, Center 57 (-86 ~ 201) 288
4251 00:25:57.583033 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4252 00:25:57.586291 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4253 00:25:57.593111 iDelay=218, Bit 15, Center 57 (-86 ~ 201) 288
4254 00:25:57.593193 ==
4255 00:25:57.596744 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 00:25:57.600279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 00:25:57.600361 ==
4258 00:25:57.600427 DQS Delay:
4259 00:25:57.603050 DQS0 = 0, DQS1 = 0
4260 00:25:57.603154 DQM Delay:
4261 00:25:57.606492 DQM0 = 58, DQM1 = 48
4262 00:25:57.606573 DQ Delay:
4263 00:25:57.609791 DQ0 =57, DQ1 =57, DQ2 =57, DQ3 =57
4264 00:25:57.613189 DQ4 =65, DQ5 =41, DQ6 =65, DQ7 =65
4265 00:25:57.616631 DQ8 =33, DQ9 =33, DQ10 =57, DQ11 =33
4266 00:25:57.620144 DQ12 =57, DQ13 =57, DQ14 =57, DQ15 =57
4267 00:25:57.620225
4268 00:25:57.620289
4269 00:25:57.620348 ==
4270 00:25:57.623466 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 00:25:57.626447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 00:25:57.626529 ==
4273 00:25:57.626594
4274 00:25:57.626653
4275 00:25:57.630050 TX Vref Scan disable
4276 00:25:57.633371 == TX Byte 0 ==
4277 00:25:57.636492 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4278 00:25:57.640057 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4279 00:25:57.643475 == TX Byte 1 ==
4280 00:25:57.646258 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4281 00:25:57.650097 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4282 00:25:57.650178 ==
4283 00:25:57.653406 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 00:25:57.659706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 00:25:57.659787 ==
4286 00:25:57.659852
4287 00:25:57.659912
4288 00:25:57.659969 TX Vref Scan disable
4289 00:25:57.664021 == TX Byte 0 ==
4290 00:25:57.667673 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4291 00:25:57.670841 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4292 00:25:57.674259 == TX Byte 1 ==
4293 00:25:57.677791 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4294 00:25:57.684069 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4295 00:25:57.684151
4296 00:25:57.684216 [DATLAT]
4297 00:25:57.684276 Freq=600, CH0 RK1
4298 00:25:57.684334
4299 00:25:57.687627 DATLAT Default: 0x9
4300 00:25:57.687707 0, 0xFFFF, sum = 0
4301 00:25:57.690612 1, 0xFFFF, sum = 0
4302 00:25:57.690694 2, 0xFFFF, sum = 0
4303 00:25:57.694280 3, 0xFFFF, sum = 0
4304 00:25:57.694396 4, 0xFFFF, sum = 0
4305 00:25:57.697359 5, 0xFFFF, sum = 0
4306 00:25:57.701032 6, 0xFFFF, sum = 0
4307 00:25:57.701114 7, 0xFFFF, sum = 0
4308 00:25:57.701180 8, 0x0, sum = 1
4309 00:25:57.704282 9, 0x0, sum = 2
4310 00:25:57.704364 10, 0x0, sum = 3
4311 00:25:57.707143 11, 0x0, sum = 4
4312 00:25:57.707225 best_step = 9
4313 00:25:57.707289
4314 00:25:57.707347 ==
4315 00:25:57.710521 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 00:25:57.717271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 00:25:57.717353 ==
4318 00:25:57.717417 RX Vref Scan: 0
4319 00:25:57.717477
4320 00:25:57.720788 RX Vref 0 -> 0, step: 1
4321 00:25:57.720869
4322 00:25:57.723787 RX Delay -163 -> 252, step: 8
4323 00:25:57.727093 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4324 00:25:57.733620 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4325 00:25:57.737130 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4326 00:25:57.740585 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4327 00:25:57.744024 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4328 00:25:57.746976 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4329 00:25:57.753760 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4330 00:25:57.757091 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4331 00:25:57.760827 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4332 00:25:57.763897 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4333 00:25:57.767042 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4334 00:25:57.773654 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4335 00:25:57.777050 iDelay=197, Bit 12, Center 48 (-91 ~ 188) 280
4336 00:25:57.780414 iDelay=197, Bit 13, Center 56 (-83 ~ 196) 280
4337 00:25:57.783897 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4338 00:25:57.790111 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4339 00:25:57.790184 ==
4340 00:25:57.793586 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 00:25:57.796681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 00:25:57.796753 ==
4343 00:25:57.796821 DQS Delay:
4344 00:25:57.800097 DQS0 = 0, DQS1 = 0
4345 00:25:57.800166 DQM Delay:
4346 00:25:57.803433 DQM0 = 53, DQM1 = 46
4347 00:25:57.803533 DQ Delay:
4348 00:25:57.806752 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4349 00:25:57.810302 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =56
4350 00:25:57.813059 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4351 00:25:57.816956 DQ12 =48, DQ13 =56, DQ14 =56, DQ15 =52
4352 00:25:57.817026
4353 00:25:57.817090
4354 00:25:57.823566 [DQSOSCAuto] RK1, (LSB)MR18= 0x6827, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4355 00:25:57.826322 CH0 RK1: MR19=808, MR18=6827
4356 00:25:57.833184 CH0_RK1: MR19=0x808, MR18=0x6827, DQSOSC=390, MR23=63, INC=172, DEC=114
4357 00:25:57.836606 [RxdqsGatingPostProcess] freq 600
4358 00:25:57.843021 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4359 00:25:57.846380 Pre-setting of DQS Precalculation
4360 00:25:57.849839 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4361 00:25:57.849937 ==
4362 00:25:57.852802 Dram Type= 6, Freq= 0, CH_1, rank 0
4363 00:25:57.856742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 00:25:57.856813 ==
4365 00:25:57.863275 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4366 00:25:57.869672 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4367 00:25:57.872834 [CA 0] Center 36 (5~67) winsize 63
4368 00:25:57.876126 [CA 1] Center 36 (5~67) winsize 63
4369 00:25:57.879715 [CA 2] Center 34 (4~65) winsize 62
4370 00:25:57.882695 [CA 3] Center 34 (3~65) winsize 63
4371 00:25:57.886300 [CA 4] Center 34 (4~65) winsize 62
4372 00:25:57.889692 [CA 5] Center 34 (3~65) winsize 63
4373 00:25:57.889773
4374 00:25:57.893040 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4375 00:25:57.893121
4376 00:25:57.896520 [CATrainingPosCal] consider 1 rank data
4377 00:25:57.899281 u2DelayCellTimex100 = 270/100 ps
4378 00:25:57.902856 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4379 00:25:57.906399 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4380 00:25:57.909897 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4381 00:25:57.912590 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4382 00:25:57.916058 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4383 00:25:57.922944 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4384 00:25:57.923025
4385 00:25:57.925932 CA PerBit enable=1, Macro0, CA PI delay=34
4386 00:25:57.926014
4387 00:25:57.929500 [CBTSetCACLKResult] CA Dly = 34
4388 00:25:57.929581 CS Dly: 6 (0~37)
4389 00:25:57.929646 ==
4390 00:25:57.932826 Dram Type= 6, Freq= 0, CH_1, rank 1
4391 00:25:57.935932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 00:25:57.939791 ==
4393 00:25:57.942826 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4394 00:25:57.949203 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4395 00:25:57.952803 [CA 0] Center 36 (5~67) winsize 63
4396 00:25:57.956138 [CA 1] Center 36 (5~67) winsize 63
4397 00:25:57.959734 [CA 2] Center 35 (4~66) winsize 63
4398 00:25:57.962527 [CA 3] Center 34 (4~65) winsize 62
4399 00:25:57.965932 [CA 4] Center 35 (4~66) winsize 63
4400 00:25:57.969222 [CA 5] Center 34 (4~65) winsize 62
4401 00:25:57.969320
4402 00:25:57.972781 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4403 00:25:57.972880
4404 00:25:57.975902 [CATrainingPosCal] consider 2 rank data
4405 00:25:57.979044 u2DelayCellTimex100 = 270/100 ps
4406 00:25:57.982964 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4407 00:25:57.985740 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4408 00:25:57.989076 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4409 00:25:57.992588 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4410 00:25:57.999171 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4411 00:25:58.002773 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4412 00:25:58.002858
4413 00:25:58.005979 CA PerBit enable=1, Macro0, CA PI delay=34
4414 00:25:58.006060
4415 00:25:58.008869 [CBTSetCACLKResult] CA Dly = 34
4416 00:25:58.008950 CS Dly: 6 (0~37)
4417 00:25:58.009015
4418 00:25:58.012242 ----->DramcWriteLeveling(PI) begin...
4419 00:25:58.012325 ==
4420 00:25:58.015524 Dram Type= 6, Freq= 0, CH_1, rank 0
4421 00:25:58.022541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 00:25:58.022623 ==
4423 00:25:58.025900 Write leveling (Byte 0): 30 => 30
4424 00:25:58.029542 Write leveling (Byte 1): 31 => 31
4425 00:25:58.029624 DramcWriteLeveling(PI) end<-----
4426 00:25:58.029688
4427 00:25:58.032444 ==
4428 00:25:58.032525 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 00:25:58.038857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 00:25:58.038939 ==
4431 00:25:58.042482 [Gating] SW mode calibration
4432 00:25:58.048929 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4433 00:25:58.052260 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4434 00:25:58.059143 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4435 00:25:58.061956 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4436 00:25:58.065953 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4437 00:25:58.072602 0 9 12 | B1->B0 | 3232 2f2f | 0 1 | (0 1) (0 0)
4438 00:25:58.075429 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 00:25:58.079090 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 00:25:58.085613 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 00:25:58.088979 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 00:25:58.092300 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 00:25:58.098548 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 00:25:58.102247 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4445 00:25:58.105871 0 10 12 | B1->B0 | 3737 3b3b | 0 1 | (0 0) (0 0)
4446 00:25:58.112153 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 00:25:58.115689 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 00:25:58.118472 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 00:25:58.125301 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 00:25:58.128717 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 00:25:58.131671 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 00:25:58.135109 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 00:25:58.142081 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4454 00:25:58.145392 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 00:25:58.148802 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 00:25:58.155197 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 00:25:58.158576 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 00:25:58.162154 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 00:25:58.168506 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 00:25:58.171721 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 00:25:58.175148 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 00:25:58.181956 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 00:25:58.185534 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 00:25:58.188628 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 00:25:58.195092 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 00:25:58.198458 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 00:25:58.201844 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 00:25:58.208958 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 00:25:58.212411 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4470 00:25:58.215198 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 00:25:58.218592 Total UI for P1: 0, mck2ui 16
4472 00:25:58.221904 best dqsien dly found for B0: ( 0, 13, 12)
4473 00:25:58.225436 Total UI for P1: 0, mck2ui 16
4474 00:25:58.228497 best dqsien dly found for B1: ( 0, 13, 12)
4475 00:25:58.232042 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4476 00:25:58.234919 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4477 00:25:58.235001
4478 00:25:58.238435 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4479 00:25:58.245276 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4480 00:25:58.245356 [Gating] SW calibration Done
4481 00:25:58.248092 ==
4482 00:25:58.248174 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 00:25:58.255292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 00:25:58.255374 ==
4485 00:25:58.255438 RX Vref Scan: 0
4486 00:25:58.255497
4487 00:25:58.258417 RX Vref 0 -> 0, step: 1
4488 00:25:58.258498
4489 00:25:58.261595 RX Delay -230 -> 252, step: 16
4490 00:25:58.265044 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4491 00:25:58.268454 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4492 00:25:58.274921 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4493 00:25:58.278214 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4494 00:25:58.281545 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4495 00:25:58.285035 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4496 00:25:58.288419 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4497 00:25:58.294720 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4498 00:25:58.298483 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4499 00:25:58.301830 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4500 00:25:58.305175 iDelay=218, Bit 10, Center 57 (-86 ~ 201) 288
4501 00:25:58.308313 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4502 00:25:58.315179 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4503 00:25:58.318186 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4504 00:25:58.321686 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4505 00:25:58.324907 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4506 00:25:58.324989 ==
4507 00:25:58.328013 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 00:25:58.334811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 00:25:58.334893 ==
4510 00:25:58.334958 DQS Delay:
4511 00:25:58.338540 DQS0 = 0, DQS1 = 0
4512 00:25:58.338620 DQM Delay:
4513 00:25:58.338685 DQM0 = 53, DQM1 = 51
4514 00:25:58.341586 DQ Delay:
4515 00:25:58.344980 DQ0 =65, DQ1 =41, DQ2 =41, DQ3 =49
4516 00:25:58.348022 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4517 00:25:58.351868 DQ8 =33, DQ9 =33, DQ10 =57, DQ11 =41
4518 00:25:58.354753 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4519 00:25:58.354833
4520 00:25:58.354897
4521 00:25:58.354957 ==
4522 00:25:58.358318 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 00:25:58.361724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 00:25:58.361806 ==
4525 00:25:58.361870
4526 00:25:58.361929
4527 00:25:58.364935 TX Vref Scan disable
4528 00:25:58.368288 == TX Byte 0 ==
4529 00:25:58.371703 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4530 00:25:58.375129 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4531 00:25:58.375228 == TX Byte 1 ==
4532 00:25:58.381349 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4533 00:25:58.384783 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4534 00:25:58.384857 ==
4535 00:25:58.387923 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 00:25:58.391698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 00:25:58.391801 ==
4538 00:25:58.391900
4539 00:25:58.391990
4540 00:25:58.394603 TX Vref Scan disable
4541 00:25:58.398052 == TX Byte 0 ==
4542 00:25:58.401581 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4543 00:25:58.407921 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4544 00:25:58.408029 == TX Byte 1 ==
4545 00:25:58.411676 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4546 00:25:58.418533 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4547 00:25:58.418642
4548 00:25:58.418726 [DATLAT]
4549 00:25:58.418813 Freq=600, CH1 RK0
4550 00:25:58.418873
4551 00:25:58.421708 DATLAT Default: 0x9
4552 00:25:58.421782 0, 0xFFFF, sum = 0
4553 00:25:58.424464 1, 0xFFFF, sum = 0
4554 00:25:58.424535 2, 0xFFFF, sum = 0
4555 00:25:58.428125 3, 0xFFFF, sum = 0
4556 00:25:58.431354 4, 0xFFFF, sum = 0
4557 00:25:58.431429 5, 0xFFFF, sum = 0
4558 00:25:58.434939 6, 0xFFFF, sum = 0
4559 00:25:58.435013 7, 0xFFFF, sum = 0
4560 00:25:58.435081 8, 0x0, sum = 1
4561 00:25:58.438052 9, 0x0, sum = 2
4562 00:25:58.438122 10, 0x0, sum = 3
4563 00:25:58.441259 11, 0x0, sum = 4
4564 00:25:58.441357 best_step = 9
4565 00:25:58.441443
4566 00:25:58.441531 ==
4567 00:25:58.444862 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 00:25:58.451100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 00:25:58.451175 ==
4570 00:25:58.451236 RX Vref Scan: 1
4571 00:25:58.451300
4572 00:25:58.454783 RX Vref 0 -> 0, step: 1
4573 00:25:58.454856
4574 00:25:58.458235 RX Delay -163 -> 252, step: 8
4575 00:25:58.458303
4576 00:25:58.461066 Set Vref, RX VrefLevel [Byte0]: 54
4577 00:25:58.464548 [Byte1]: 48
4578 00:25:58.464646
4579 00:25:58.468110 Final RX Vref Byte 0 = 54 to rank0
4580 00:25:58.471399 Final RX Vref Byte 1 = 48 to rank0
4581 00:25:58.474479 Final RX Vref Byte 0 = 54 to rank1
4582 00:25:58.477689 Final RX Vref Byte 1 = 48 to rank1==
4583 00:25:58.481029 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 00:25:58.484819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 00:25:58.484899 ==
4586 00:25:58.487930 DQS Delay:
4587 00:25:58.488001 DQS0 = 0, DQS1 = 0
4588 00:25:58.488078 DQM Delay:
4589 00:25:58.490998 DQM0 = 48, DQM1 = 45
4590 00:25:58.491065 DQ Delay:
4591 00:25:58.494606 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4592 00:25:58.497748 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4593 00:25:58.501429 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4594 00:25:58.504463 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4595 00:25:58.504535
4596 00:25:58.504601
4597 00:25:58.514819 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d73, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4598 00:25:58.514893 CH1 RK0: MR19=808, MR18=4D73
4599 00:25:58.520976 CH1_RK0: MR19=0x808, MR18=0x4D73, DQSOSC=388, MR23=63, INC=174, DEC=116
4600 00:25:58.521051
4601 00:25:58.524385 ----->DramcWriteLeveling(PI) begin...
4602 00:25:58.528052 ==
4603 00:25:58.528126 Dram Type= 6, Freq= 0, CH_1, rank 1
4604 00:25:58.534390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 00:25:58.534465 ==
4606 00:25:58.537772 Write leveling (Byte 0): 30 => 30
4607 00:25:58.541236 Write leveling (Byte 1): 33 => 33
4608 00:25:58.544662 DramcWriteLeveling(PI) end<-----
4609 00:25:58.544733
4610 00:25:58.544793 ==
4611 00:25:58.548094 Dram Type= 6, Freq= 0, CH_1, rank 1
4612 00:25:58.551204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 00:25:58.551270 ==
4614 00:25:58.554384 [Gating] SW mode calibration
4615 00:25:58.561097 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4616 00:25:58.564628 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4617 00:25:58.571046 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4618 00:25:58.574296 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4619 00:25:58.577748 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4620 00:25:58.584145 0 9 12 | B1->B0 | 2e2e 2f2f | 0 0 | (0 1) (1 1)
4621 00:25:58.587390 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 00:25:58.590796 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 00:25:58.597565 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 00:25:58.600743 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 00:25:58.604047 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 00:25:58.610871 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 00:25:58.614321 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 00:25:58.617241 0 10 12 | B1->B0 | 3838 3333 | 1 1 | (0 0) (0 0)
4629 00:25:58.624040 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 00:25:58.627200 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 00:25:58.630652 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 00:25:58.637356 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 00:25:58.640702 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 00:25:58.643862 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 00:25:58.650848 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 00:25:58.653819 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4637 00:25:58.657125 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 00:25:58.664029 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 00:25:58.667162 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 00:25:58.670620 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 00:25:58.674541 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 00:25:58.681058 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 00:25:58.683903 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 00:25:58.687338 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 00:25:58.694100 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 00:25:58.697502 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 00:25:58.700568 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 00:25:58.707329 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 00:25:58.710638 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 00:25:58.714172 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 00:25:58.720417 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4652 00:25:58.723848 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4653 00:25:58.727190 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 00:25:58.730555 Total UI for P1: 0, mck2ui 16
4655 00:25:58.734418 best dqsien dly found for B0: ( 0, 13, 12)
4656 00:25:58.737002 Total UI for P1: 0, mck2ui 16
4657 00:25:58.740527 best dqsien dly found for B1: ( 0, 13, 10)
4658 00:25:58.744957 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4659 00:25:58.747285 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4660 00:25:58.747386
4661 00:25:58.754237 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4662 00:25:58.757021 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4663 00:25:58.760839 [Gating] SW calibration Done
4664 00:25:58.760922 ==
4665 00:25:58.763679 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 00:25:58.767073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 00:25:58.767173 ==
4668 00:25:58.767239 RX Vref Scan: 0
4669 00:25:58.767301
4670 00:25:58.770376 RX Vref 0 -> 0, step: 1
4671 00:25:58.770459
4672 00:25:58.774169 RX Delay -230 -> 252, step: 16
4673 00:25:58.777050 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4674 00:25:58.780421 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4675 00:25:58.787307 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4676 00:25:58.790353 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4677 00:25:58.793806 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4678 00:25:58.797305 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4679 00:25:58.800270 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4680 00:25:58.807250 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4681 00:25:58.810273 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4682 00:25:58.813884 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4683 00:25:58.817042 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4684 00:25:58.823596 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4685 00:25:58.826960 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4686 00:25:58.830144 iDelay=218, Bit 13, Center 65 (-86 ~ 217) 304
4687 00:25:58.833575 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4688 00:25:58.840478 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4689 00:25:58.840560 ==
4690 00:25:58.843658 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 00:25:58.847097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 00:25:58.847180 ==
4693 00:25:58.847245 DQS Delay:
4694 00:25:58.850368 DQS0 = 0, DQS1 = 0
4695 00:25:58.850450 DQM Delay:
4696 00:25:58.853949 DQM0 = 51, DQM1 = 48
4697 00:25:58.854030 DQ Delay:
4698 00:25:58.856758 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =49
4699 00:25:58.860318 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4700 00:25:58.863529 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4701 00:25:58.866954 DQ12 =57, DQ13 =65, DQ14 =49, DQ15 =65
4702 00:25:58.867083
4703 00:25:58.867179
4704 00:25:58.867270 ==
4705 00:25:58.870131 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 00:25:58.874219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 00:25:58.874302 ==
4708 00:25:58.874367
4709 00:25:58.874428
4710 00:25:58.877189 TX Vref Scan disable
4711 00:25:58.880206 == TX Byte 0 ==
4712 00:25:58.883407 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4713 00:25:58.887096 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4714 00:25:58.890650 == TX Byte 1 ==
4715 00:25:58.893501 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4716 00:25:58.896703 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4717 00:25:58.896785 ==
4718 00:25:58.900154 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 00:25:58.906857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 00:25:58.906942 ==
4721 00:25:58.907008
4722 00:25:58.907070
4723 00:25:58.907129 TX Vref Scan disable
4724 00:25:58.911153 == TX Byte 0 ==
4725 00:25:58.914310 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4726 00:25:58.917615 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4727 00:25:58.921349 == TX Byte 1 ==
4728 00:25:58.924438 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4729 00:25:58.927688 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4730 00:25:58.930870
4731 00:25:58.930953 [DATLAT]
4732 00:25:58.931018 Freq=600, CH1 RK1
4733 00:25:58.931080
4734 00:25:58.934140 DATLAT Default: 0x9
4735 00:25:58.934224 0, 0xFFFF, sum = 0
4736 00:25:58.937741 1, 0xFFFF, sum = 0
4737 00:25:58.937828 2, 0xFFFF, sum = 0
4738 00:25:58.941001 3, 0xFFFF, sum = 0
4739 00:25:58.941085 4, 0xFFFF, sum = 0
4740 00:25:58.944396 5, 0xFFFF, sum = 0
4741 00:25:58.944480 6, 0xFFFF, sum = 0
4742 00:25:58.947822 7, 0xFFFF, sum = 0
4743 00:25:58.947906 8, 0x0, sum = 1
4744 00:25:58.950979 9, 0x0, sum = 2
4745 00:25:58.951063 10, 0x0, sum = 3
4746 00:25:58.954655 11, 0x0, sum = 4
4747 00:25:58.954740 best_step = 9
4748 00:25:58.954806
4749 00:25:58.954867 ==
4750 00:25:58.957757 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 00:25:58.964537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 00:25:58.964621 ==
4753 00:25:58.964688 RX Vref Scan: 0
4754 00:25:58.964749
4755 00:25:58.967999 RX Vref 0 -> 0, step: 1
4756 00:25:58.968083
4757 00:25:58.970896 RX Delay -163 -> 252, step: 8
4758 00:25:58.974541 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4759 00:25:58.977960 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4760 00:25:58.984261 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4761 00:25:58.987526 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4762 00:25:58.991203 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4763 00:25:58.994334 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4764 00:25:58.998093 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4765 00:25:59.004651 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4766 00:25:59.008076 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4767 00:25:59.011058 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4768 00:25:59.014747 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4769 00:25:59.017812 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4770 00:25:59.024704 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4771 00:25:59.028085 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4772 00:25:59.031007 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4773 00:25:59.034234 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4774 00:25:59.034318 ==
4775 00:25:59.037722 Dram Type= 6, Freq= 0, CH_1, rank 1
4776 00:25:59.044361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4777 00:25:59.044446 ==
4778 00:25:59.044512 DQS Delay:
4779 00:25:59.047738 DQS0 = 0, DQS1 = 0
4780 00:25:59.047821 DQM Delay:
4781 00:25:59.047894 DQM0 = 49, DQM1 = 45
4782 00:25:59.051214 DQ Delay:
4783 00:25:59.054642 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4784 00:25:59.057495 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4785 00:25:59.060883 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4786 00:25:59.064133 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4787 00:25:59.064243
4788 00:25:59.064337
4789 00:25:59.071091 [DQSOSCAuto] RK1, (LSB)MR18= 0x7026, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 388 ps
4790 00:25:59.074028 CH1 RK1: MR19=808, MR18=7026
4791 00:25:59.080880 CH1_RK1: MR19=0x808, MR18=0x7026, DQSOSC=388, MR23=63, INC=174, DEC=116
4792 00:25:59.084346 [RxdqsGatingPostProcess] freq 600
4793 00:25:59.087361 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4794 00:25:59.090876 Pre-setting of DQS Precalculation
4795 00:25:59.097583 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4796 00:25:59.104543 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4797 00:25:59.111193 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4798 00:25:59.111309
4799 00:25:59.111406
4800 00:25:59.114440 [Calibration Summary] 1200 Mbps
4801 00:25:59.114524 CH 0, Rank 0
4802 00:25:59.117576 SW Impedance : PASS
4803 00:25:59.121176 DUTY Scan : NO K
4804 00:25:59.121260 ZQ Calibration : PASS
4805 00:25:59.124120 Jitter Meter : NO K
4806 00:25:59.127367 CBT Training : PASS
4807 00:25:59.127450 Write leveling : PASS
4808 00:25:59.130876 RX DQS gating : PASS
4809 00:25:59.134211 RX DQ/DQS(RDDQC) : PASS
4810 00:25:59.134295 TX DQ/DQS : PASS
4811 00:25:59.137869 RX DATLAT : PASS
4812 00:25:59.140657 RX DQ/DQS(Engine): PASS
4813 00:25:59.140740 TX OE : NO K
4814 00:25:59.140807 All Pass.
4815 00:25:59.143844
4816 00:25:59.143926 CH 0, Rank 1
4817 00:25:59.147640 SW Impedance : PASS
4818 00:25:59.147723 DUTY Scan : NO K
4819 00:25:59.150547 ZQ Calibration : PASS
4820 00:25:59.153805 Jitter Meter : NO K
4821 00:25:59.153888 CBT Training : PASS
4822 00:25:59.157187 Write leveling : PASS
4823 00:25:59.157270 RX DQS gating : PASS
4824 00:25:59.160448 RX DQ/DQS(RDDQC) : PASS
4825 00:25:59.164038 TX DQ/DQS : PASS
4826 00:25:59.164153 RX DATLAT : PASS
4827 00:25:59.167064 RX DQ/DQS(Engine): PASS
4828 00:25:59.170714 TX OE : NO K
4829 00:25:59.170798 All Pass.
4830 00:25:59.170864
4831 00:25:59.170925 CH 1, Rank 0
4832 00:25:59.173942 SW Impedance : PASS
4833 00:25:59.177146 DUTY Scan : NO K
4834 00:25:59.177230 ZQ Calibration : PASS
4835 00:25:59.180575 Jitter Meter : NO K
4836 00:25:59.183937 CBT Training : PASS
4837 00:25:59.184020 Write leveling : PASS
4838 00:25:59.187150 RX DQS gating : PASS
4839 00:25:59.190318 RX DQ/DQS(RDDQC) : PASS
4840 00:25:59.190401 TX DQ/DQS : PASS
4841 00:25:59.193994 RX DATLAT : PASS
4842 00:25:59.197272 RX DQ/DQS(Engine): PASS
4843 00:25:59.197356 TX OE : NO K
4844 00:25:59.197423 All Pass.
4845 00:25:59.200154
4846 00:25:59.200237 CH 1, Rank 1
4847 00:25:59.203667 SW Impedance : PASS
4848 00:25:59.203750 DUTY Scan : NO K
4849 00:25:59.207128 ZQ Calibration : PASS
4850 00:25:59.210135 Jitter Meter : NO K
4851 00:25:59.210245 CBT Training : PASS
4852 00:25:59.213420 Write leveling : PASS
4853 00:25:59.213503 RX DQS gating : PASS
4854 00:25:59.216813 RX DQ/DQS(RDDQC) : PASS
4855 00:25:59.220271 TX DQ/DQS : PASS
4856 00:25:59.220355 RX DATLAT : PASS
4857 00:25:59.223494 RX DQ/DQS(Engine): PASS
4858 00:25:59.227257 TX OE : NO K
4859 00:25:59.227371 All Pass.
4860 00:25:59.227474
4861 00:25:59.230168 DramC Write-DBI off
4862 00:25:59.230251 PER_BANK_REFRESH: Hybrid Mode
4863 00:25:59.233953 TX_TRACKING: ON
4864 00:25:59.240551 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4865 00:25:59.247142 [FAST_K] Save calibration result to emmc
4866 00:25:59.250724 dramc_set_vcore_voltage set vcore to 662500
4867 00:25:59.250807 Read voltage for 933, 3
4868 00:25:59.253459 Vio18 = 0
4869 00:25:59.253541 Vcore = 662500
4870 00:25:59.253607 Vdram = 0
4871 00:25:59.257282 Vddq = 0
4872 00:25:59.257365 Vmddr = 0
4873 00:25:59.260696 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4874 00:25:59.266629 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4875 00:25:59.270135 MEM_TYPE=3, freq_sel=17
4876 00:25:59.273816 sv_algorithm_assistance_LP4_1600
4877 00:25:59.277060 ============ PULL DRAM RESETB DOWN ============
4878 00:25:59.280338 ========== PULL DRAM RESETB DOWN end =========
4879 00:25:59.283321 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4880 00:25:59.286986 ===================================
4881 00:25:59.289923 LPDDR4 DRAM CONFIGURATION
4882 00:25:59.293313 ===================================
4883 00:25:59.297084 EX_ROW_EN[0] = 0x0
4884 00:25:59.297168 EX_ROW_EN[1] = 0x0
4885 00:25:59.300499 LP4Y_EN = 0x0
4886 00:25:59.300582 WORK_FSP = 0x0
4887 00:25:59.303326 WL = 0x3
4888 00:25:59.303409 RL = 0x3
4889 00:25:59.306910 BL = 0x2
4890 00:25:59.306993 RPST = 0x0
4891 00:25:59.310128 RD_PRE = 0x0
4892 00:25:59.310211 WR_PRE = 0x1
4893 00:25:59.313524 WR_PST = 0x0
4894 00:25:59.316573 DBI_WR = 0x0
4895 00:25:59.316677 DBI_RD = 0x0
4896 00:25:59.319919 OTF = 0x1
4897 00:25:59.323643 ===================================
4898 00:25:59.326561 ===================================
4899 00:25:59.326644 ANA top config
4900 00:25:59.330293 ===================================
4901 00:25:59.333350 DLL_ASYNC_EN = 0
4902 00:25:59.333448 ALL_SLAVE_EN = 1
4903 00:25:59.336574 NEW_RANK_MODE = 1
4904 00:25:59.340203 DLL_IDLE_MODE = 1
4905 00:25:59.343322 LP45_APHY_COMB_EN = 1
4906 00:25:59.346727 TX_ODT_DIS = 1
4907 00:25:59.346811 NEW_8X_MODE = 1
4908 00:25:59.350278 ===================================
4909 00:25:59.353263 ===================================
4910 00:25:59.356567 data_rate = 1866
4911 00:25:59.360036 CKR = 1
4912 00:25:59.363146 DQ_P2S_RATIO = 8
4913 00:25:59.366510 ===================================
4914 00:25:59.369762 CA_P2S_RATIO = 8
4915 00:25:59.373263 DQ_CA_OPEN = 0
4916 00:25:59.373346 DQ_SEMI_OPEN = 0
4917 00:25:59.376442 CA_SEMI_OPEN = 0
4918 00:25:59.379830 CA_FULL_RATE = 0
4919 00:25:59.383191 DQ_CKDIV4_EN = 1
4920 00:25:59.386389 CA_CKDIV4_EN = 1
4921 00:25:59.389768 CA_PREDIV_EN = 0
4922 00:25:59.389852 PH8_DLY = 0
4923 00:25:59.393550 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4924 00:25:59.396349 DQ_AAMCK_DIV = 4
4925 00:25:59.399812 CA_AAMCK_DIV = 4
4926 00:25:59.403423 CA_ADMCK_DIV = 4
4927 00:25:59.406605 DQ_TRACK_CA_EN = 0
4928 00:25:59.406689 CA_PICK = 933
4929 00:25:59.409515 CA_MCKIO = 933
4930 00:25:59.412856 MCKIO_SEMI = 0
4931 00:25:59.416280 PLL_FREQ = 3732
4932 00:25:59.419936 DQ_UI_PI_RATIO = 32
4933 00:25:59.422799 CA_UI_PI_RATIO = 0
4934 00:25:59.426665 ===================================
4935 00:25:59.429462 ===================================
4936 00:25:59.429545 memory_type:LPDDR4
4937 00:25:59.433035 GP_NUM : 10
4938 00:25:59.436471 SRAM_EN : 1
4939 00:25:59.436581 MD32_EN : 0
4940 00:25:59.439709 ===================================
4941 00:25:59.443105 [ANA_INIT] >>>>>>>>>>>>>>
4942 00:25:59.446182 <<<<<< [CONFIGURE PHASE]: ANA_TX
4943 00:25:59.449758 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4944 00:25:59.452761 ===================================
4945 00:25:59.456170 data_rate = 1866,PCW = 0X8f00
4946 00:25:59.459311 ===================================
4947 00:25:59.463269 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4948 00:25:59.466172 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4949 00:25:59.472896 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4950 00:25:59.476143 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4951 00:25:59.479613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4952 00:25:59.482792 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4953 00:25:59.486050 [ANA_INIT] flow start
4954 00:25:59.489708 [ANA_INIT] PLL >>>>>>>>
4955 00:25:59.489811 [ANA_INIT] PLL <<<<<<<<
4956 00:25:59.492771 [ANA_INIT] MIDPI >>>>>>>>
4957 00:25:59.496334 [ANA_INIT] MIDPI <<<<<<<<
4958 00:25:59.499428 [ANA_INIT] DLL >>>>>>>>
4959 00:25:59.499537 [ANA_INIT] flow end
4960 00:25:59.502886 ============ LP4 DIFF to SE enter ============
4961 00:25:59.509136 ============ LP4 DIFF to SE exit ============
4962 00:25:59.509241 [ANA_INIT] <<<<<<<<<<<<<
4963 00:25:59.512865 [Flow] Enable top DCM control >>>>>
4964 00:25:59.516099 [Flow] Enable top DCM control <<<<<
4965 00:25:59.519372 Enable DLL master slave shuffle
4966 00:25:59.526378 ==============================================================
4967 00:25:59.526484 Gating Mode config
4968 00:25:59.532411 ==============================================================
4969 00:25:59.535991 Config description:
4970 00:25:59.546200 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4971 00:25:59.552441 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4972 00:25:59.556100 SELPH_MODE 0: By rank 1: By Phase
4973 00:25:59.562555 ==============================================================
4974 00:25:59.565988 GAT_TRACK_EN = 1
4975 00:25:59.566098 RX_GATING_MODE = 2
4976 00:25:59.569472 RX_GATING_TRACK_MODE = 2
4977 00:25:59.572886 SELPH_MODE = 1
4978 00:25:59.575777 PICG_EARLY_EN = 1
4979 00:25:59.578998 VALID_LAT_VALUE = 1
4980 00:25:59.585798 ==============================================================
4981 00:25:59.589708 Enter into Gating configuration >>>>
4982 00:25:59.592716 Exit from Gating configuration <<<<
4983 00:25:59.595978 Enter into DVFS_PRE_config >>>>>
4984 00:25:59.606022 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4985 00:25:59.609014 Exit from DVFS_PRE_config <<<<<
4986 00:25:59.612545 Enter into PICG configuration >>>>
4987 00:25:59.615505 Exit from PICG configuration <<<<
4988 00:25:59.619224 [RX_INPUT] configuration >>>>>
4989 00:25:59.622098 [RX_INPUT] configuration <<<<<
4990 00:25:59.625710 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4991 00:25:59.632357 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4992 00:25:59.639160 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4993 00:25:59.642051 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4994 00:25:59.648842 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4995 00:25:59.655601 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4996 00:25:59.658977 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4997 00:25:59.661948 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4998 00:25:59.668714 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4999 00:25:59.671923 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5000 00:25:59.675392 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5001 00:25:59.682289 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5002 00:25:59.685182 ===================================
5003 00:25:59.685286 LPDDR4 DRAM CONFIGURATION
5004 00:25:59.688384 ===================================
5005 00:25:59.692026 EX_ROW_EN[0] = 0x0
5006 00:25:59.695553 EX_ROW_EN[1] = 0x0
5007 00:25:59.695654 LP4Y_EN = 0x0
5008 00:25:59.698348 WORK_FSP = 0x0
5009 00:25:59.698454 WL = 0x3
5010 00:25:59.701985 RL = 0x3
5011 00:25:59.702086 BL = 0x2
5012 00:25:59.705383 RPST = 0x0
5013 00:25:59.705489 RD_PRE = 0x0
5014 00:25:59.708681 WR_PRE = 0x1
5015 00:25:59.708788 WR_PST = 0x0
5016 00:25:59.711712 DBI_WR = 0x0
5017 00:25:59.711814 DBI_RD = 0x0
5018 00:25:59.715220 OTF = 0x1
5019 00:25:59.718610 ===================================
5020 00:25:59.722084 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5021 00:25:59.725405 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5022 00:25:59.731886 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5023 00:25:59.735294 ===================================
5024 00:25:59.735399 LPDDR4 DRAM CONFIGURATION
5025 00:25:59.738472 ===================================
5026 00:25:59.741533 EX_ROW_EN[0] = 0x10
5027 00:25:59.741640 EX_ROW_EN[1] = 0x0
5028 00:25:59.745098 LP4Y_EN = 0x0
5029 00:25:59.748355 WORK_FSP = 0x0
5030 00:25:59.748453 WL = 0x3
5031 00:25:59.751654 RL = 0x3
5032 00:25:59.751755 BL = 0x2
5033 00:25:59.754971 RPST = 0x0
5034 00:25:59.755069 RD_PRE = 0x0
5035 00:25:59.758404 WR_PRE = 0x1
5036 00:25:59.758505 WR_PST = 0x0
5037 00:25:59.761982 DBI_WR = 0x0
5038 00:25:59.762085 DBI_RD = 0x0
5039 00:25:59.764938 OTF = 0x1
5040 00:25:59.768420 ===================================
5041 00:25:59.775002 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5042 00:25:59.778262 nWR fixed to 30
5043 00:25:59.778366 [ModeRegInit_LP4] CH0 RK0
5044 00:25:59.781799 [ModeRegInit_LP4] CH0 RK1
5045 00:25:59.785210 [ModeRegInit_LP4] CH1 RK0
5046 00:25:59.785314 [ModeRegInit_LP4] CH1 RK1
5047 00:25:59.788235 match AC timing 9
5048 00:25:59.791643 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5049 00:25:59.795253 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5050 00:25:59.801902 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5051 00:25:59.805216 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5052 00:25:59.811952 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5053 00:25:59.812059 ==
5054 00:25:59.815214 Dram Type= 6, Freq= 0, CH_0, rank 0
5055 00:25:59.818362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5056 00:25:59.818468 ==
5057 00:25:59.825283 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5058 00:25:59.828572 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5059 00:25:59.832584 [CA 0] Center 37 (6~68) winsize 63
5060 00:25:59.835891 [CA 1] Center 37 (6~68) winsize 63
5061 00:25:59.839261 [CA 2] Center 34 (4~65) winsize 62
5062 00:25:59.842320 [CA 3] Center 33 (3~64) winsize 62
5063 00:25:59.845773 [CA 4] Center 33 (3~63) winsize 61
5064 00:25:59.848985 [CA 5] Center 32 (2~62) winsize 61
5065 00:25:59.849091
5066 00:25:59.852361 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5067 00:25:59.852466
5068 00:25:59.855748 [CATrainingPosCal] consider 1 rank data
5069 00:25:59.859261 u2DelayCellTimex100 = 270/100 ps
5070 00:25:59.862077 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5071 00:25:59.865922 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5072 00:25:59.872416 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5073 00:25:59.875991 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5074 00:25:59.878877 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5075 00:25:59.882735 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5076 00:25:59.882838
5077 00:25:59.885807 CA PerBit enable=1, Macro0, CA PI delay=32
5078 00:25:59.885910
5079 00:25:59.888996 [CBTSetCACLKResult] CA Dly = 32
5080 00:25:59.889105 CS Dly: 5 (0~36)
5081 00:25:59.892441 ==
5082 00:25:59.892547 Dram Type= 6, Freq= 0, CH_0, rank 1
5083 00:25:59.899303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5084 00:25:59.899418 ==
5085 00:25:59.902026 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5086 00:25:59.908786 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5087 00:25:59.912309 [CA 0] Center 37 (7~68) winsize 62
5088 00:25:59.915550 [CA 1] Center 37 (6~68) winsize 63
5089 00:25:59.918813 [CA 2] Center 34 (4~65) winsize 62
5090 00:25:59.922240 [CA 3] Center 34 (4~65) winsize 62
5091 00:25:59.925648 [CA 4] Center 32 (2~63) winsize 62
5092 00:25:59.928965 [CA 5] Center 32 (2~63) winsize 62
5093 00:25:59.929082
5094 00:25:59.932092 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5095 00:25:59.932193
5096 00:25:59.935646 [CATrainingPosCal] consider 2 rank data
5097 00:25:59.938750 u2DelayCellTimex100 = 270/100 ps
5098 00:25:59.942144 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5099 00:25:59.949162 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5100 00:25:59.951991 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5101 00:25:59.955436 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5102 00:25:59.958819 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5103 00:25:59.962363 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5104 00:25:59.962479
5105 00:25:59.965948 CA PerBit enable=1, Macro0, CA PI delay=32
5106 00:25:59.966052
5107 00:25:59.968615 [CBTSetCACLKResult] CA Dly = 32
5108 00:25:59.972174 CS Dly: 5 (0~37)
5109 00:25:59.972279
5110 00:25:59.975708 ----->DramcWriteLeveling(PI) begin...
5111 00:25:59.975823 ==
5112 00:25:59.979209 Dram Type= 6, Freq= 0, CH_0, rank 0
5113 00:25:59.982098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 00:25:59.982207 ==
5115 00:25:59.985567 Write leveling (Byte 0): 31 => 31
5116 00:25:59.988588 Write leveling (Byte 1): 29 => 29
5117 00:25:59.992003 DramcWriteLeveling(PI) end<-----
5118 00:25:59.992114
5119 00:25:59.992207 ==
5120 00:25:59.995150 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 00:25:59.998559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 00:25:59.998672 ==
5123 00:26:00.002045 [Gating] SW mode calibration
5124 00:26:00.008757 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5125 00:26:00.015419 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5126 00:26:00.018774 0 14 0 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
5127 00:26:00.021760 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 00:26:00.028724 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 00:26:00.031857 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 00:26:00.035193 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 00:26:00.041753 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 00:26:00.045322 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5133 00:26:00.048303 0 14 28 | B1->B0 | 3333 2424 | 1 0 | (1 0) (1 0)
5134 00:26:00.055332 0 15 0 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5135 00:26:00.058322 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 00:26:00.061642 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 00:26:00.068651 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 00:26:00.071995 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 00:26:00.075042 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 00:26:00.078394 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5141 00:26:00.085040 0 15 28 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
5142 00:26:00.088471 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5143 00:26:00.091380 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 00:26:00.098428 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 00:26:00.101234 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 00:26:00.104837 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 00:26:00.111512 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 00:26:00.114624 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5149 00:26:00.117926 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5150 00:26:00.125005 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5151 00:26:00.127872 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 00:26:00.131923 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 00:26:00.138146 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 00:26:00.141297 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 00:26:00.144757 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 00:26:00.151542 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 00:26:00.154786 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 00:26:00.158245 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 00:26:00.164680 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 00:26:00.168027 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 00:26:00.171484 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 00:26:00.178047 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 00:26:00.181300 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 00:26:00.185135 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 00:26:00.191174 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5166 00:26:00.191287 Total UI for P1: 0, mck2ui 16
5167 00:26:00.194619 best dqsien dly found for B0: ( 1, 2, 26)
5168 00:26:00.201971 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 00:26:00.204665 Total UI for P1: 0, mck2ui 16
5170 00:26:00.208037 best dqsien dly found for B1: ( 1, 2, 30)
5171 00:26:00.211445 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5172 00:26:00.214871 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5173 00:26:00.214983
5174 00:26:00.218390 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5175 00:26:00.221541 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5176 00:26:00.224640 [Gating] SW calibration Done
5177 00:26:00.224741 ==
5178 00:26:00.228016 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 00:26:00.231207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 00:26:00.231338 ==
5181 00:26:00.234947 RX Vref Scan: 0
5182 00:26:00.235051
5183 00:26:00.235145 RX Vref 0 -> 0, step: 1
5184 00:26:00.238213
5185 00:26:00.238315 RX Delay -80 -> 252, step: 8
5186 00:26:00.244474 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5187 00:26:00.247972 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5188 00:26:00.251279 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5189 00:26:00.254747 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5190 00:26:00.258451 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5191 00:26:00.261603 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5192 00:26:00.268116 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5193 00:26:00.271445 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5194 00:26:00.274565 iDelay=208, Bit 8, Center 83 (0 ~ 167) 168
5195 00:26:00.278071 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5196 00:26:00.281431 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5197 00:26:00.284928 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5198 00:26:00.291418 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5199 00:26:00.294845 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5200 00:26:00.297943 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5201 00:26:00.301293 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5202 00:26:00.301395 ==
5203 00:26:00.304560 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 00:26:00.308119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 00:26:00.311436 ==
5206 00:26:00.311543 DQS Delay:
5207 00:26:00.311610 DQS0 = 0, DQS1 = 0
5208 00:26:00.314932 DQM Delay:
5209 00:26:00.315031 DQM0 = 105, DQM1 = 95
5210 00:26:00.317890 DQ Delay:
5211 00:26:00.321118 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5212 00:26:00.324766 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5213 00:26:00.327625 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5214 00:26:00.331027 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5215 00:26:00.331128
5216 00:26:00.331219
5217 00:26:00.331311 ==
5218 00:26:00.334177 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 00:26:00.337412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 00:26:00.337549 ==
5221 00:26:00.337665
5222 00:26:00.337774
5223 00:26:00.340821 TX Vref Scan disable
5224 00:26:00.340904 == TX Byte 0 ==
5225 00:26:00.347668 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5226 00:26:00.350709 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5227 00:26:00.354266 == TX Byte 1 ==
5228 00:26:00.357272 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5229 00:26:00.360659 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5230 00:26:00.360743 ==
5231 00:26:00.364043 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 00:26:00.367372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 00:26:00.370862 ==
5234 00:26:00.370946
5235 00:26:00.371012
5236 00:26:00.371073 TX Vref Scan disable
5237 00:26:00.374340 == TX Byte 0 ==
5238 00:26:00.377681 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5239 00:26:00.384009 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5240 00:26:00.384093 == TX Byte 1 ==
5241 00:26:00.387330 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5242 00:26:00.394465 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5243 00:26:00.394549
5244 00:26:00.394615 [DATLAT]
5245 00:26:00.394676 Freq=933, CH0 RK0
5246 00:26:00.394735
5247 00:26:00.397280 DATLAT Default: 0xd
5248 00:26:00.397388 0, 0xFFFF, sum = 0
5249 00:26:00.400582 1, 0xFFFF, sum = 0
5250 00:26:00.400667 2, 0xFFFF, sum = 0
5251 00:26:00.404060 3, 0xFFFF, sum = 0
5252 00:26:00.407776 4, 0xFFFF, sum = 0
5253 00:26:00.407861 5, 0xFFFF, sum = 0
5254 00:26:00.410766 6, 0xFFFF, sum = 0
5255 00:26:00.410850 7, 0xFFFF, sum = 0
5256 00:26:00.414018 8, 0xFFFF, sum = 0
5257 00:26:00.414103 9, 0xFFFF, sum = 0
5258 00:26:00.417195 10, 0x0, sum = 1
5259 00:26:00.417279 11, 0x0, sum = 2
5260 00:26:00.420670 12, 0x0, sum = 3
5261 00:26:00.420755 13, 0x0, sum = 4
5262 00:26:00.420822 best_step = 11
5263 00:26:00.420883
5264 00:26:00.424053 ==
5265 00:26:00.424136 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 00:26:00.430801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 00:26:00.430886 ==
5268 00:26:00.430953 RX Vref Scan: 1
5269 00:26:00.431015
5270 00:26:00.433766 RX Vref 0 -> 0, step: 1
5271 00:26:00.433850
5272 00:26:00.437634 RX Delay -45 -> 252, step: 4
5273 00:26:00.437717
5274 00:26:00.440530 Set Vref, RX VrefLevel [Byte0]: 54
5275 00:26:00.443971 [Byte1]: 48
5276 00:26:00.444055
5277 00:26:00.447636 Final RX Vref Byte 0 = 54 to rank0
5278 00:26:00.450561 Final RX Vref Byte 1 = 48 to rank0
5279 00:26:00.454343 Final RX Vref Byte 0 = 54 to rank1
5280 00:26:00.457477 Final RX Vref Byte 1 = 48 to rank1==
5281 00:26:00.460668 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 00:26:00.464031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 00:26:00.464115 ==
5284 00:26:00.467302 DQS Delay:
5285 00:26:00.467418 DQS0 = 0, DQS1 = 0
5286 00:26:00.470362 DQM Delay:
5287 00:26:00.470446 DQM0 = 104, DQM1 = 95
5288 00:26:00.470512 DQ Delay:
5289 00:26:00.474060 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102
5290 00:26:00.476987 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5291 00:26:00.480537 DQ8 =86, DQ9 =84, DQ10 =94, DQ11 =90
5292 00:26:00.487513 DQ12 =98, DQ13 =98, DQ14 =108, DQ15 =102
5293 00:26:00.487608
5294 00:26:00.487674
5295 00:26:00.494018 [DQSOSCAuto] RK0, (LSB)MR18= 0x322a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5296 00:26:00.497459 CH0 RK0: MR19=505, MR18=322A
5297 00:26:00.503854 CH0_RK0: MR19=0x505, MR18=0x322A, DQSOSC=406, MR23=63, INC=65, DEC=43
5298 00:26:00.503936
5299 00:26:00.507154 ----->DramcWriteLeveling(PI) begin...
5300 00:26:00.507254 ==
5301 00:26:00.510457 Dram Type= 6, Freq= 0, CH_0, rank 1
5302 00:26:00.514063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 00:26:00.514162 ==
5304 00:26:00.517089 Write leveling (Byte 0): 33 => 33
5305 00:26:00.520600 Write leveling (Byte 1): 29 => 29
5306 00:26:00.523827 DramcWriteLeveling(PI) end<-----
5307 00:26:00.523938
5308 00:26:00.524053 ==
5309 00:26:00.527431 Dram Type= 6, Freq= 0, CH_0, rank 1
5310 00:26:00.530632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 00:26:00.530730 ==
5312 00:26:00.533723 [Gating] SW mode calibration
5313 00:26:00.540180 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5314 00:26:00.547221 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5315 00:26:00.550198 0 14 0 | B1->B0 | 3434 3231 | 1 1 | (1 1) (1 1)
5316 00:26:00.556677 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 00:26:00.560146 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 00:26:00.563458 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 00:26:00.567208 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 00:26:00.573735 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 00:26:00.577182 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5322 00:26:00.580066 0 14 28 | B1->B0 | 2c2c 2a2a | 1 1 | (1 1) (1 0)
5323 00:26:00.586622 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5324 00:26:00.590145 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 00:26:00.593446 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 00:26:00.599822 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 00:26:00.603702 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 00:26:00.606944 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 00:26:00.613297 0 15 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5330 00:26:00.616466 0 15 28 | B1->B0 | 4343 3737 | 0 1 | (0 0) (0 0)
5331 00:26:00.620161 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 00:26:00.626427 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 00:26:00.630092 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 00:26:00.633450 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 00:26:00.639888 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 00:26:00.643380 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 00:26:00.646365 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 00:26:00.653188 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5339 00:26:00.656660 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 00:26:00.659946 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 00:26:00.666290 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 00:26:00.669830 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 00:26:00.673382 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 00:26:00.679680 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 00:26:00.683105 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 00:26:00.686374 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 00:26:00.693130 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 00:26:00.696523 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 00:26:00.699451 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 00:26:00.703137 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 00:26:00.710093 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 00:26:00.713413 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 00:26:00.716492 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5354 00:26:00.722917 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5355 00:26:00.726507 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 00:26:00.730076 Total UI for P1: 0, mck2ui 16
5357 00:26:00.732893 best dqsien dly found for B0: ( 1, 2, 26)
5358 00:26:00.736566 Total UI for P1: 0, mck2ui 16
5359 00:26:00.739422 best dqsien dly found for B1: ( 1, 2, 28)
5360 00:26:00.742913 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5361 00:26:00.746306 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5362 00:26:00.746404
5363 00:26:00.749950 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5364 00:26:00.753068 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5365 00:26:00.756281 [Gating] SW calibration Done
5366 00:26:00.756402 ==
5367 00:26:00.759502 Dram Type= 6, Freq= 0, CH_0, rank 1
5368 00:26:00.766140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5369 00:26:00.766241 ==
5370 00:26:00.766380 RX Vref Scan: 0
5371 00:26:00.766483
5372 00:26:00.769421 RX Vref 0 -> 0, step: 1
5373 00:26:00.769531
5374 00:26:00.772674 RX Delay -80 -> 252, step: 8
5375 00:26:00.776270 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5376 00:26:00.779611 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5377 00:26:00.782544 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5378 00:26:00.786125 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5379 00:26:00.792603 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5380 00:26:00.795993 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5381 00:26:00.799246 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5382 00:26:00.802831 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5383 00:26:00.806159 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5384 00:26:00.809325 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5385 00:26:00.815781 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5386 00:26:00.819010 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5387 00:26:00.822513 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5388 00:26:00.826103 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5389 00:26:00.829294 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5390 00:26:00.836246 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5391 00:26:00.836348 ==
5392 00:26:00.839412 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 00:26:00.842271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 00:26:00.842371 ==
5395 00:26:00.842469 DQS Delay:
5396 00:26:00.845897 DQS0 = 0, DQS1 = 0
5397 00:26:00.845998 DQM Delay:
5398 00:26:00.849214 DQM0 = 105, DQM1 = 93
5399 00:26:00.849313 DQ Delay:
5400 00:26:00.852206 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5401 00:26:00.855735 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5402 00:26:00.859075 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5403 00:26:00.862265 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =103
5404 00:26:00.862368
5405 00:26:00.862465
5406 00:26:00.862556 ==
5407 00:26:00.865739 Dram Type= 6, Freq= 0, CH_0, rank 1
5408 00:26:00.872031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5409 00:26:00.872142 ==
5410 00:26:00.872242
5411 00:26:00.872333
5412 00:26:00.872426 TX Vref Scan disable
5413 00:26:00.875775 == TX Byte 0 ==
5414 00:26:00.879146 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5415 00:26:00.885647 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5416 00:26:00.885752 == TX Byte 1 ==
5417 00:26:00.889258 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5418 00:26:00.892208 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5419 00:26:00.895642 ==
5420 00:26:00.899007 Dram Type= 6, Freq= 0, CH_0, rank 1
5421 00:26:00.902405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5422 00:26:00.902508 ==
5423 00:26:00.902605
5424 00:26:00.902696
5425 00:26:00.905365 TX Vref Scan disable
5426 00:26:00.905460 == TX Byte 0 ==
5427 00:26:00.912405 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5428 00:26:00.915566 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5429 00:26:00.915665 == TX Byte 1 ==
5430 00:26:00.922235 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5431 00:26:00.925455 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5432 00:26:00.925567
5433 00:26:00.925663 [DATLAT]
5434 00:26:00.928872 Freq=933, CH0 RK1
5435 00:26:00.928989
5436 00:26:00.929085 DATLAT Default: 0xb
5437 00:26:00.932336 0, 0xFFFF, sum = 0
5438 00:26:00.932435 1, 0xFFFF, sum = 0
5439 00:26:00.935816 2, 0xFFFF, sum = 0
5440 00:26:00.935892 3, 0xFFFF, sum = 0
5441 00:26:00.938658 4, 0xFFFF, sum = 0
5442 00:26:00.938757 5, 0xFFFF, sum = 0
5443 00:26:00.942145 6, 0xFFFF, sum = 0
5444 00:26:00.945450 7, 0xFFFF, sum = 0
5445 00:26:00.945554 8, 0xFFFF, sum = 0
5446 00:26:00.948902 9, 0xFFFF, sum = 0
5447 00:26:00.949015 10, 0x0, sum = 1
5448 00:26:00.949111 11, 0x0, sum = 2
5449 00:26:00.951926 12, 0x0, sum = 3
5450 00:26:00.952025 13, 0x0, sum = 4
5451 00:26:00.955249 best_step = 11
5452 00:26:00.955347
5453 00:26:00.955435 ==
5454 00:26:00.959058 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 00:26:00.962040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 00:26:00.962137 ==
5457 00:26:00.965511 RX Vref Scan: 0
5458 00:26:00.965608
5459 00:26:00.965696 RX Vref 0 -> 0, step: 1
5460 00:26:00.965786
5461 00:26:00.968485 RX Delay -53 -> 252, step: 4
5462 00:26:00.975995 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5463 00:26:00.979872 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5464 00:26:00.982704 iDelay=199, Bit 2, Center 100 (11 ~ 190) 180
5465 00:26:00.985848 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5466 00:26:00.989340 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5467 00:26:00.995809 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5468 00:26:00.999167 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5469 00:26:01.002600 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5470 00:26:01.005747 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5471 00:26:01.009213 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5472 00:26:01.016217 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5473 00:26:01.019432 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5474 00:26:01.022672 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5475 00:26:01.026108 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5476 00:26:01.029142 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5477 00:26:01.035925 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5478 00:26:01.036032 ==
5479 00:26:01.039260 Dram Type= 6, Freq= 0, CH_0, rank 1
5480 00:26:01.042416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5481 00:26:01.042533 ==
5482 00:26:01.042625 DQS Delay:
5483 00:26:01.045649 DQS0 = 0, DQS1 = 0
5484 00:26:01.045749 DQM Delay:
5485 00:26:01.049008 DQM0 = 104, DQM1 = 93
5486 00:26:01.049105 DQ Delay:
5487 00:26:01.052496 DQ0 =102, DQ1 =106, DQ2 =100, DQ3 =100
5488 00:26:01.056079 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5489 00:26:01.059036 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =88
5490 00:26:01.062256 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =102
5491 00:26:01.062372
5492 00:26:01.062462
5493 00:26:01.072690 [DQSOSCAuto] RK1, (LSB)MR18= 0x2801, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps
5494 00:26:01.072797 CH0 RK1: MR19=505, MR18=2801
5495 00:26:01.079162 CH0_RK1: MR19=0x505, MR18=0x2801, DQSOSC=409, MR23=63, INC=64, DEC=43
5496 00:26:01.082267 [RxdqsGatingPostProcess] freq 933
5497 00:26:01.089393 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5498 00:26:01.092904 best DQS0 dly(2T, 0.5T) = (0, 10)
5499 00:26:01.095600 best DQS1 dly(2T, 0.5T) = (0, 10)
5500 00:26:01.099251 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5501 00:26:01.102518 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5502 00:26:01.102623 best DQS0 dly(2T, 0.5T) = (0, 10)
5503 00:26:01.105660 best DQS1 dly(2T, 0.5T) = (0, 10)
5504 00:26:01.108922 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5505 00:26:01.112649 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5506 00:26:01.115852 Pre-setting of DQS Precalculation
5507 00:26:01.122143 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5508 00:26:01.122252 ==
5509 00:26:01.125661 Dram Type= 6, Freq= 0, CH_1, rank 0
5510 00:26:01.128883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5511 00:26:01.128987 ==
5512 00:26:01.135524 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5513 00:26:01.142453 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5514 00:26:01.145603 [CA 0] Center 36 (6~67) winsize 62
5515 00:26:01.148815 [CA 1] Center 37 (6~68) winsize 63
5516 00:26:01.152236 [CA 2] Center 35 (5~65) winsize 61
5517 00:26:01.155199 [CA 3] Center 34 (4~65) winsize 62
5518 00:26:01.158692 [CA 4] Center 34 (4~65) winsize 62
5519 00:26:01.162120 [CA 5] Center 33 (3~64) winsize 62
5520 00:26:01.162233
5521 00:26:01.165259 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5522 00:26:01.165375
5523 00:26:01.168739 [CATrainingPosCal] consider 1 rank data
5524 00:26:01.172172 u2DelayCellTimex100 = 270/100 ps
5525 00:26:01.174988 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5526 00:26:01.178485 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5527 00:26:01.181979 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5528 00:26:01.185403 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5529 00:26:01.188613 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5530 00:26:01.191977 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5531 00:26:01.192078
5532 00:26:01.198546 CA PerBit enable=1, Macro0, CA PI delay=33
5533 00:26:01.198651
5534 00:26:01.198780 [CBTSetCACLKResult] CA Dly = 33
5535 00:26:01.201455 CS Dly: 6 (0~37)
5536 00:26:01.201560 ==
5537 00:26:01.205186 Dram Type= 6, Freq= 0, CH_1, rank 1
5538 00:26:01.208354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 00:26:01.208459 ==
5540 00:26:01.215145 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5541 00:26:01.221467 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5542 00:26:01.225112 [CA 0] Center 36 (6~67) winsize 62
5543 00:26:01.228268 [CA 1] Center 37 (6~68) winsize 63
5544 00:26:01.231494 [CA 2] Center 35 (5~65) winsize 61
5545 00:26:01.235022 [CA 3] Center 34 (4~65) winsize 62
5546 00:26:01.238546 [CA 4] Center 34 (4~65) winsize 62
5547 00:26:01.241893 [CA 5] Center 33 (3~64) winsize 62
5548 00:26:01.241997
5549 00:26:01.244676 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5550 00:26:01.244754
5551 00:26:01.248059 [CATrainingPosCal] consider 2 rank data
5552 00:26:01.251581 u2DelayCellTimex100 = 270/100 ps
5553 00:26:01.254616 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5554 00:26:01.258058 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5555 00:26:01.261612 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5556 00:26:01.265079 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5557 00:26:01.268017 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5558 00:26:01.271612 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5559 00:26:01.271725
5560 00:26:01.278448 CA PerBit enable=1, Macro0, CA PI delay=33
5561 00:26:01.278554
5562 00:26:01.281453 [CBTSetCACLKResult] CA Dly = 33
5563 00:26:01.281552 CS Dly: 7 (0~40)
5564 00:26:01.281644
5565 00:26:01.284930 ----->DramcWriteLeveling(PI) begin...
5566 00:26:01.285032 ==
5567 00:26:01.287926 Dram Type= 6, Freq= 0, CH_1, rank 0
5568 00:26:01.291820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5569 00:26:01.291924 ==
5570 00:26:01.294749 Write leveling (Byte 0): 26 => 26
5571 00:26:01.298433 Write leveling (Byte 1): 27 => 27
5572 00:26:01.301467 DramcWriteLeveling(PI) end<-----
5573 00:26:01.301580
5574 00:26:01.301679 ==
5575 00:26:01.304964 Dram Type= 6, Freq= 0, CH_1, rank 0
5576 00:26:01.308426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5577 00:26:01.311606 ==
5578 00:26:01.311706 [Gating] SW mode calibration
5579 00:26:01.321774 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5580 00:26:01.325071 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5581 00:26:01.328204 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 00:26:01.334805 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5583 00:26:01.338276 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5584 00:26:01.341379 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 00:26:01.348257 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 00:26:01.352065 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5587 00:26:01.355249 0 14 24 | B1->B0 | 3434 2e2e | 0 1 | (0 1) (1 0)
5588 00:26:01.361379 0 14 28 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (1 0)
5589 00:26:01.364765 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 00:26:01.368220 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 00:26:01.374624 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 00:26:01.378285 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 00:26:01.381657 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 00:26:01.388040 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5595 00:26:01.391449 0 15 24 | B1->B0 | 2727 3939 | 0 0 | (0 0) (0 0)
5596 00:26:01.394931 0 15 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5597 00:26:01.398401 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 00:26:01.404656 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 00:26:01.408039 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 00:26:01.411546 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 00:26:01.418261 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 00:26:01.421486 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 00:26:01.424477 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5604 00:26:01.431454 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5605 00:26:01.434657 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 00:26:01.437911 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 00:26:01.444821 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 00:26:01.447967 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 00:26:01.451217 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 00:26:01.458006 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 00:26:01.461747 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 00:26:01.464840 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 00:26:01.471143 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 00:26:01.474703 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 00:26:01.478390 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 00:26:01.484503 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 00:26:01.487988 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 00:26:01.491529 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5619 00:26:01.497935 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5620 00:26:01.501392 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5621 00:26:01.504303 Total UI for P1: 0, mck2ui 16
5622 00:26:01.507790 best dqsien dly found for B1: ( 1, 2, 24)
5623 00:26:01.511240 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 00:26:01.514392 Total UI for P1: 0, mck2ui 16
5625 00:26:01.517906 best dqsien dly found for B0: ( 1, 2, 24)
5626 00:26:01.521378 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5627 00:26:01.524628 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5628 00:26:01.524733
5629 00:26:01.527488 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5630 00:26:01.534101 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5631 00:26:01.534208 [Gating] SW calibration Done
5632 00:26:01.537719 ==
5633 00:26:01.537825 Dram Type= 6, Freq= 0, CH_1, rank 0
5634 00:26:01.544198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5635 00:26:01.544303 ==
5636 00:26:01.544403 RX Vref Scan: 0
5637 00:26:01.544496
5638 00:26:01.547368 RX Vref 0 -> 0, step: 1
5639 00:26:01.547472
5640 00:26:01.550732 RX Delay -80 -> 252, step: 8
5641 00:26:01.553989 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5642 00:26:01.557401 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5643 00:26:01.560660 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5644 00:26:01.567024 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5645 00:26:01.570788 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5646 00:26:01.573819 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5647 00:26:01.577198 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5648 00:26:01.580318 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5649 00:26:01.584217 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5650 00:26:01.590490 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5651 00:26:01.593636 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5652 00:26:01.596934 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5653 00:26:01.600516 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5654 00:26:01.603888 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5655 00:26:01.607491 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5656 00:26:01.614241 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5657 00:26:01.614325 ==
5658 00:26:01.617210 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 00:26:01.620416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 00:26:01.620500 ==
5661 00:26:01.620579 DQS Delay:
5662 00:26:01.623763 DQS0 = 0, DQS1 = 0
5663 00:26:01.623847 DQM Delay:
5664 00:26:01.627181 DQM0 = 103, DQM1 = 98
5665 00:26:01.627264 DQ Delay:
5666 00:26:01.630372 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5667 00:26:01.633709 DQ4 =99, DQ5 =119, DQ6 =111, DQ7 =103
5668 00:26:01.637289 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5669 00:26:01.640688 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5670 00:26:01.640772
5671 00:26:01.640837
5672 00:26:01.640899 ==
5673 00:26:01.643437 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 00:26:01.650709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 00:26:01.650793 ==
5676 00:26:01.650858
5677 00:26:01.650919
5678 00:26:01.650978 TX Vref Scan disable
5679 00:26:01.654145 == TX Byte 0 ==
5680 00:26:01.657493 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5681 00:26:01.663975 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5682 00:26:01.664059 == TX Byte 1 ==
5683 00:26:01.667018 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5684 00:26:01.673726 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5685 00:26:01.673813 ==
5686 00:26:01.677168 Dram Type= 6, Freq= 0, CH_1, rank 0
5687 00:26:01.680456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5688 00:26:01.680540 ==
5689 00:26:01.680606
5690 00:26:01.680667
5691 00:26:01.683856 TX Vref Scan disable
5692 00:26:01.683939 == TX Byte 0 ==
5693 00:26:01.691001 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5694 00:26:01.694061 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5695 00:26:01.694140 == TX Byte 1 ==
5696 00:26:01.700825 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5697 00:26:01.703753 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5698 00:26:01.703837
5699 00:26:01.703903 [DATLAT]
5700 00:26:01.707675 Freq=933, CH1 RK0
5701 00:26:01.707758
5702 00:26:01.707824 DATLAT Default: 0xd
5703 00:26:01.710763 0, 0xFFFF, sum = 0
5704 00:26:01.710847 1, 0xFFFF, sum = 0
5705 00:26:01.713745 2, 0xFFFF, sum = 0
5706 00:26:01.713830 3, 0xFFFF, sum = 0
5707 00:26:01.717112 4, 0xFFFF, sum = 0
5708 00:26:01.717198 5, 0xFFFF, sum = 0
5709 00:26:01.720457 6, 0xFFFF, sum = 0
5710 00:26:01.720542 7, 0xFFFF, sum = 0
5711 00:26:01.723758 8, 0xFFFF, sum = 0
5712 00:26:01.727180 9, 0xFFFF, sum = 0
5713 00:26:01.727295 10, 0x0, sum = 1
5714 00:26:01.727398 11, 0x0, sum = 2
5715 00:26:01.730709 12, 0x0, sum = 3
5716 00:26:01.730793 13, 0x0, sum = 4
5717 00:26:01.734045 best_step = 11
5718 00:26:01.734128
5719 00:26:01.734194 ==
5720 00:26:01.736813 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 00:26:01.740345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 00:26:01.740429 ==
5723 00:26:01.744019 RX Vref Scan: 1
5724 00:26:01.744102
5725 00:26:01.744168 RX Vref 0 -> 0, step: 1
5726 00:26:01.744230
5727 00:26:01.746884 RX Delay -45 -> 252, step: 4
5728 00:26:01.746966
5729 00:26:01.750346 Set Vref, RX VrefLevel [Byte0]: 54
5730 00:26:01.753755 [Byte1]: 48
5731 00:26:01.757829
5732 00:26:01.757911 Final RX Vref Byte 0 = 54 to rank0
5733 00:26:01.760948 Final RX Vref Byte 1 = 48 to rank0
5734 00:26:01.764958 Final RX Vref Byte 0 = 54 to rank1
5735 00:26:01.767865 Final RX Vref Byte 1 = 48 to rank1==
5736 00:26:01.771254 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 00:26:01.774534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 00:26:01.778144 ==
5739 00:26:01.778229 DQS Delay:
5740 00:26:01.778295 DQS0 = 0, DQS1 = 0
5741 00:26:01.781288 DQM Delay:
5742 00:26:01.781371 DQM0 = 103, DQM1 = 100
5743 00:26:01.784550 DQ Delay:
5744 00:26:01.787843 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5745 00:26:01.791340 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102
5746 00:26:01.794686 DQ8 =88, DQ9 =88, DQ10 =100, DQ11 =94
5747 00:26:01.798007 DQ12 =108, DQ13 =106, DQ14 =108, DQ15 =110
5748 00:26:01.798094
5749 00:26:01.798160
5750 00:26:01.804414 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a31, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5751 00:26:01.807932 CH1 RK0: MR19=505, MR18=1A31
5752 00:26:01.814738 CH1_RK0: MR19=0x505, MR18=0x1A31, DQSOSC=406, MR23=63, INC=65, DEC=43
5753 00:26:01.814839
5754 00:26:01.817989 ----->DramcWriteLeveling(PI) begin...
5755 00:26:01.818073 ==
5756 00:26:01.820927 Dram Type= 6, Freq= 0, CH_1, rank 1
5757 00:26:01.824289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5758 00:26:01.824372 ==
5759 00:26:01.827629 Write leveling (Byte 0): 28 => 28
5760 00:26:01.831679 Write leveling (Byte 1): 29 => 29
5761 00:26:01.834370 DramcWriteLeveling(PI) end<-----
5762 00:26:01.834453
5763 00:26:01.834533 ==
5764 00:26:01.837744 Dram Type= 6, Freq= 0, CH_1, rank 1
5765 00:26:01.844262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5766 00:26:01.844345 ==
5767 00:26:01.844409 [Gating] SW mode calibration
5768 00:26:01.854655 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5769 00:26:01.858064 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5770 00:26:01.860778 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5771 00:26:01.867762 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5772 00:26:01.871347 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 00:26:01.874116 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 00:26:01.881146 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 00:26:01.884625 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5776 00:26:01.887797 0 14 24 | B1->B0 | 2e2e 3232 | 0 0 | (1 0) (0 1)
5777 00:26:01.894330 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5778 00:26:01.897746 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5779 00:26:01.901170 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5780 00:26:01.907320 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 00:26:01.910919 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 00:26:01.914054 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 00:26:01.920811 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5784 00:26:01.923871 0 15 24 | B1->B0 | 3434 2828 | 0 0 | (1 1) (0 0)
5785 00:26:01.927140 0 15 28 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (1 1)
5786 00:26:01.934095 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 00:26:01.937611 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 00:26:01.940989 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 00:26:01.947327 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 00:26:01.950518 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 00:26:01.954252 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 00:26:01.960860 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5793 00:26:01.964221 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5794 00:26:01.967841 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 00:26:01.970722 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 00:26:01.977636 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 00:26:01.980420 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 00:26:01.984049 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 00:26:01.990771 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 00:26:01.994134 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 00:26:01.997620 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 00:26:02.004006 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 00:26:02.007494 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 00:26:02.010936 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 00:26:02.017582 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 00:26:02.020647 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 00:26:02.024294 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 00:26:02.031051 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 00:26:02.033988 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 00:26:02.037358 Total UI for P1: 0, mck2ui 16
5811 00:26:02.040799 best dqsien dly found for B0: ( 1, 2, 26)
5812 00:26:02.044002 Total UI for P1: 0, mck2ui 16
5813 00:26:02.047467 best dqsien dly found for B1: ( 1, 2, 26)
5814 00:26:02.050597 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5815 00:26:02.053931 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5816 00:26:02.054015
5817 00:26:02.057447 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5818 00:26:02.060855 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5819 00:26:02.064013 [Gating] SW calibration Done
5820 00:26:02.064097 ==
5821 00:26:02.067150 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 00:26:02.070445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 00:26:02.070557 ==
5824 00:26:02.074035 RX Vref Scan: 0
5825 00:26:02.074118
5826 00:26:02.077390 RX Vref 0 -> 0, step: 1
5827 00:26:02.077473
5828 00:26:02.077539 RX Delay -80 -> 252, step: 8
5829 00:26:02.084005 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5830 00:26:02.087510 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5831 00:26:02.090882 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5832 00:26:02.094371 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5833 00:26:02.097329 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5834 00:26:02.100787 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5835 00:26:02.107274 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5836 00:26:02.110647 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5837 00:26:02.114140 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5838 00:26:02.117002 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5839 00:26:02.120532 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5840 00:26:02.124028 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5841 00:26:02.130335 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5842 00:26:02.133743 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5843 00:26:02.137111 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5844 00:26:02.140790 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5845 00:26:02.140872 ==
5846 00:26:02.143434 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 00:26:02.150484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 00:26:02.150566 ==
5849 00:26:02.150632 DQS Delay:
5850 00:26:02.153550 DQS0 = 0, DQS1 = 0
5851 00:26:02.153631 DQM Delay:
5852 00:26:02.153696 DQM0 = 102, DQM1 = 98
5853 00:26:02.156941 DQ Delay:
5854 00:26:02.160185 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5855 00:26:02.163595 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5856 00:26:02.167027 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5857 00:26:02.170019 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =103
5858 00:26:02.170102
5859 00:26:02.170168
5860 00:26:02.170228 ==
5861 00:26:02.173365 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 00:26:02.176627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 00:26:02.176709 ==
5864 00:26:02.176773
5865 00:26:02.176833
5866 00:26:02.180344 TX Vref Scan disable
5867 00:26:02.183294 == TX Byte 0 ==
5868 00:26:02.186348 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5869 00:26:02.189718 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5870 00:26:02.193165 == TX Byte 1 ==
5871 00:26:02.196729 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5872 00:26:02.199869 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5873 00:26:02.199996 ==
5874 00:26:02.203196 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 00:26:02.209654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 00:26:02.209736 ==
5877 00:26:02.209801
5878 00:26:02.209861
5879 00:26:02.209919 TX Vref Scan disable
5880 00:26:02.214084 == TX Byte 0 ==
5881 00:26:02.216993 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5882 00:26:02.220279 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5883 00:26:02.223987 == TX Byte 1 ==
5884 00:26:02.227422 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5885 00:26:02.233734 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5886 00:26:02.233832
5887 00:26:02.233928 [DATLAT]
5888 00:26:02.234022 Freq=933, CH1 RK1
5889 00:26:02.234082
5890 00:26:02.237149 DATLAT Default: 0xb
5891 00:26:02.237248 0, 0xFFFF, sum = 0
5892 00:26:02.240447 1, 0xFFFF, sum = 0
5893 00:26:02.240593 2, 0xFFFF, sum = 0
5894 00:26:02.243786 3, 0xFFFF, sum = 0
5895 00:26:02.247161 4, 0xFFFF, sum = 0
5896 00:26:02.247263 5, 0xFFFF, sum = 0
5897 00:26:02.250228 6, 0xFFFF, sum = 0
5898 00:26:02.250334 7, 0xFFFF, sum = 0
5899 00:26:02.253759 8, 0xFFFF, sum = 0
5900 00:26:02.253865 9, 0xFFFF, sum = 0
5901 00:26:02.257058 10, 0x0, sum = 1
5902 00:26:02.257164 11, 0x0, sum = 2
5903 00:26:02.260252 12, 0x0, sum = 3
5904 00:26:02.260372 13, 0x0, sum = 4
5905 00:26:02.260483 best_step = 11
5906 00:26:02.260588
5907 00:26:02.263604 ==
5908 00:26:02.266807 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 00:26:02.270310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 00:26:02.270422 ==
5911 00:26:02.270519 RX Vref Scan: 0
5912 00:26:02.270612
5913 00:26:02.273257 RX Vref 0 -> 0, step: 1
5914 00:26:02.273361
5915 00:26:02.276564 RX Delay -45 -> 252, step: 4
5916 00:26:02.279819 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5917 00:26:02.286412 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5918 00:26:02.290087 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5919 00:26:02.293147 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5920 00:26:02.296586 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5921 00:26:02.299785 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5922 00:26:02.306705 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5923 00:26:02.309677 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5924 00:26:02.313102 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5925 00:26:02.316485 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5926 00:26:02.319826 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5927 00:26:02.326756 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5928 00:26:02.329640 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5929 00:26:02.333494 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5930 00:26:02.336610 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5931 00:26:02.339796 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5932 00:26:02.343133 ==
5933 00:26:02.343216 Dram Type= 6, Freq= 0, CH_1, rank 1
5934 00:26:02.350013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5935 00:26:02.350097 ==
5936 00:26:02.350164 DQS Delay:
5937 00:26:02.353197 DQS0 = 0, DQS1 = 0
5938 00:26:02.353281 DQM Delay:
5939 00:26:02.356932 DQM0 = 105, DQM1 = 100
5940 00:26:02.357015 DQ Delay:
5941 00:26:02.360196 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5942 00:26:02.362888 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5943 00:26:02.366359 DQ8 =92, DQ9 =88, DQ10 =102, DQ11 =94
5944 00:26:02.369739 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5945 00:26:02.369841
5946 00:26:02.369907
5947 00:26:02.380247 [DQSOSCAuto] RK1, (LSB)MR18= 0x3205, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 406 ps
5948 00:26:02.380357 CH1 RK1: MR19=505, MR18=3205
5949 00:26:02.386387 CH1_RK1: MR19=0x505, MR18=0x3205, DQSOSC=406, MR23=63, INC=65, DEC=43
5950 00:26:02.390383 [RxdqsGatingPostProcess] freq 933
5951 00:26:02.396528 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5952 00:26:02.400007 best DQS0 dly(2T, 0.5T) = (0, 10)
5953 00:26:02.403107 best DQS1 dly(2T, 0.5T) = (0, 10)
5954 00:26:02.407264 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5955 00:26:02.409936 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5956 00:26:02.410020 best DQS0 dly(2T, 0.5T) = (0, 10)
5957 00:26:02.413236 best DQS1 dly(2T, 0.5T) = (0, 10)
5958 00:26:02.416409 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5959 00:26:02.419988 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5960 00:26:02.422941 Pre-setting of DQS Precalculation
5961 00:26:02.429827 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5962 00:26:02.436403 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5963 00:26:02.443109 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5964 00:26:02.443193
5965 00:26:02.443258
5966 00:26:02.446648 [Calibration Summary] 1866 Mbps
5967 00:26:02.446732 CH 0, Rank 0
5968 00:26:02.450048 SW Impedance : PASS
5969 00:26:02.453259 DUTY Scan : NO K
5970 00:26:02.453342 ZQ Calibration : PASS
5971 00:26:02.456466 Jitter Meter : NO K
5972 00:26:02.459900 CBT Training : PASS
5973 00:26:02.459983 Write leveling : PASS
5974 00:26:02.462775 RX DQS gating : PASS
5975 00:26:02.466066 RX DQ/DQS(RDDQC) : PASS
5976 00:26:02.466152 TX DQ/DQS : PASS
5977 00:26:02.469657 RX DATLAT : PASS
5978 00:26:02.469740 RX DQ/DQS(Engine): PASS
5979 00:26:02.473065 TX OE : NO K
5980 00:26:02.473150 All Pass.
5981 00:26:02.473216
5982 00:26:02.476374 CH 0, Rank 1
5983 00:26:02.476457 SW Impedance : PASS
5984 00:26:02.479948 DUTY Scan : NO K
5985 00:26:02.482834 ZQ Calibration : PASS
5986 00:26:02.482917 Jitter Meter : NO K
5987 00:26:02.486328 CBT Training : PASS
5988 00:26:02.489828 Write leveling : PASS
5989 00:26:02.489911 RX DQS gating : PASS
5990 00:26:02.493209 RX DQ/DQS(RDDQC) : PASS
5991 00:26:02.496220 TX DQ/DQS : PASS
5992 00:26:02.496303 RX DATLAT : PASS
5993 00:26:02.499357 RX DQ/DQS(Engine): PASS
5994 00:26:02.502788 TX OE : NO K
5995 00:26:02.502872 All Pass.
5996 00:26:02.502938
5997 00:26:02.502998 CH 1, Rank 0
5998 00:26:02.506497 SW Impedance : PASS
5999 00:26:02.509504 DUTY Scan : NO K
6000 00:26:02.509586 ZQ Calibration : PASS
6001 00:26:02.513217 Jitter Meter : NO K
6002 00:26:02.516583 CBT Training : PASS
6003 00:26:02.516664 Write leveling : PASS
6004 00:26:02.519838 RX DQS gating : PASS
6005 00:26:02.519920 RX DQ/DQS(RDDQC) : PASS
6006 00:26:02.523073 TX DQ/DQS : PASS
6007 00:26:02.526129 RX DATLAT : PASS
6008 00:26:02.526210 RX DQ/DQS(Engine): PASS
6009 00:26:02.529633 TX OE : NO K
6010 00:26:02.529716 All Pass.
6011 00:26:02.529781
6012 00:26:02.533393 CH 1, Rank 1
6013 00:26:02.533474 SW Impedance : PASS
6014 00:26:02.536286 DUTY Scan : NO K
6015 00:26:02.539827 ZQ Calibration : PASS
6016 00:26:02.539908 Jitter Meter : NO K
6017 00:26:02.543136 CBT Training : PASS
6018 00:26:02.546800 Write leveling : PASS
6019 00:26:02.547004 RX DQS gating : PASS
6020 00:26:02.549949 RX DQ/DQS(RDDQC) : PASS
6021 00:26:02.553352 TX DQ/DQS : PASS
6022 00:26:02.553434 RX DATLAT : PASS
6023 00:26:02.556513 RX DQ/DQS(Engine): PASS
6024 00:26:02.556610 TX OE : NO K
6025 00:26:02.559707 All Pass.
6026 00:26:02.559816
6027 00:26:02.559914 DramC Write-DBI off
6028 00:26:02.563173 PER_BANK_REFRESH: Hybrid Mode
6029 00:26:02.566623 TX_TRACKING: ON
6030 00:26:02.573013 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6031 00:26:02.576450 [FAST_K] Save calibration result to emmc
6032 00:26:02.583242 dramc_set_vcore_voltage set vcore to 650000
6033 00:26:02.583362 Read voltage for 400, 6
6034 00:26:02.583472 Vio18 = 0
6035 00:26:02.586235 Vcore = 650000
6036 00:26:02.586349 Vdram = 0
6037 00:26:02.586443 Vddq = 0
6038 00:26:02.589651 Vmddr = 0
6039 00:26:02.593050 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6040 00:26:02.599756 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6041 00:26:02.599882 MEM_TYPE=3, freq_sel=20
6042 00:26:02.603138 sv_algorithm_assistance_LP4_800
6043 00:26:02.609724 ============ PULL DRAM RESETB DOWN ============
6044 00:26:02.613104 ========== PULL DRAM RESETB DOWN end =========
6045 00:26:02.616388 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6046 00:26:02.619770 ===================================
6047 00:26:02.623062 LPDDR4 DRAM CONFIGURATION
6048 00:26:02.626430 ===================================
6049 00:26:02.626534 EX_ROW_EN[0] = 0x0
6050 00:26:02.630005 EX_ROW_EN[1] = 0x0
6051 00:26:02.632906 LP4Y_EN = 0x0
6052 00:26:02.633053 WORK_FSP = 0x0
6053 00:26:02.636334 WL = 0x2
6054 00:26:02.636456 RL = 0x2
6055 00:26:02.639985 BL = 0x2
6056 00:26:02.640124 RPST = 0x0
6057 00:26:02.642847 RD_PRE = 0x0
6058 00:26:02.642966 WR_PRE = 0x1
6059 00:26:02.646222 WR_PST = 0x0
6060 00:26:02.646324 DBI_WR = 0x0
6061 00:26:02.649305 DBI_RD = 0x0
6062 00:26:02.649408 OTF = 0x1
6063 00:26:02.653154 ===================================
6064 00:26:02.656248 ===================================
6065 00:26:02.659869 ANA top config
6066 00:26:02.663129 ===================================
6067 00:26:02.663232 DLL_ASYNC_EN = 0
6068 00:26:02.666081 ALL_SLAVE_EN = 1
6069 00:26:02.669669 NEW_RANK_MODE = 1
6070 00:26:02.672904 DLL_IDLE_MODE = 1
6071 00:26:02.676455 LP45_APHY_COMB_EN = 1
6072 00:26:02.676560 TX_ODT_DIS = 1
6073 00:26:02.679260 NEW_8X_MODE = 1
6074 00:26:02.682568 ===================================
6075 00:26:02.686113 ===================================
6076 00:26:02.689571 data_rate = 800
6077 00:26:02.692961 CKR = 1
6078 00:26:02.695843 DQ_P2S_RATIO = 4
6079 00:26:02.699879 ===================================
6080 00:26:02.702627 CA_P2S_RATIO = 4
6081 00:26:02.702736 DQ_CA_OPEN = 0
6082 00:26:02.706036 DQ_SEMI_OPEN = 1
6083 00:26:02.709404 CA_SEMI_OPEN = 1
6084 00:26:02.712876 CA_FULL_RATE = 0
6085 00:26:02.715866 DQ_CKDIV4_EN = 0
6086 00:26:02.715974 CA_CKDIV4_EN = 1
6087 00:26:02.719233 CA_PREDIV_EN = 0
6088 00:26:02.722589 PH8_DLY = 0
6089 00:26:02.725987 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6090 00:26:02.729544 DQ_AAMCK_DIV = 0
6091 00:26:02.732889 CA_AAMCK_DIV = 0
6092 00:26:02.733003 CA_ADMCK_DIV = 4
6093 00:26:02.735748 DQ_TRACK_CA_EN = 0
6094 00:26:02.739351 CA_PICK = 800
6095 00:26:02.742607 CA_MCKIO = 400
6096 00:26:02.745800 MCKIO_SEMI = 400
6097 00:26:02.749033 PLL_FREQ = 3016
6098 00:26:02.752965 DQ_UI_PI_RATIO = 32
6099 00:26:02.756052 CA_UI_PI_RATIO = 32
6100 00:26:02.759329 ===================================
6101 00:26:02.762663 ===================================
6102 00:26:02.762773 memory_type:LPDDR4
6103 00:26:02.765914 GP_NUM : 10
6104 00:26:02.766024 SRAM_EN : 1
6105 00:26:02.769182 MD32_EN : 0
6106 00:26:02.772877 ===================================
6107 00:26:02.775981 [ANA_INIT] >>>>>>>>>>>>>>
6108 00:26:02.779263 <<<<<< [CONFIGURE PHASE]: ANA_TX
6109 00:26:02.782464 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6110 00:26:02.785813 ===================================
6111 00:26:02.785896 data_rate = 800,PCW = 0X7400
6112 00:26:02.789240 ===================================
6113 00:26:02.792780 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6114 00:26:02.798972 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6115 00:26:02.812734 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6116 00:26:02.815410 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6117 00:26:02.818964 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6118 00:26:02.822249 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6119 00:26:02.825552 [ANA_INIT] flow start
6120 00:26:02.825651 [ANA_INIT] PLL >>>>>>>>
6121 00:26:02.828867 [ANA_INIT] PLL <<<<<<<<
6122 00:26:02.832439 [ANA_INIT] MIDPI >>>>>>>>
6123 00:26:02.835833 [ANA_INIT] MIDPI <<<<<<<<
6124 00:26:02.835931 [ANA_INIT] DLL >>>>>>>>
6125 00:26:02.838660 [ANA_INIT] flow end
6126 00:26:02.842489 ============ LP4 DIFF to SE enter ============
6127 00:26:02.845691 ============ LP4 DIFF to SE exit ============
6128 00:26:02.849070 [ANA_INIT] <<<<<<<<<<<<<
6129 00:26:02.852569 [Flow] Enable top DCM control >>>>>
6130 00:26:02.855642 [Flow] Enable top DCM control <<<<<
6131 00:26:02.859312 Enable DLL master slave shuffle
6132 00:26:02.862217 ==============================================================
6133 00:26:02.865620 Gating Mode config
6134 00:26:02.872614 ==============================================================
6135 00:26:02.872715 Config description:
6136 00:26:02.881891 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6137 00:26:02.888632 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6138 00:26:02.895215 SELPH_MODE 0: By rank 1: By Phase
6139 00:26:02.898901 ==============================================================
6140 00:26:02.901778 GAT_TRACK_EN = 0
6141 00:26:02.905346 RX_GATING_MODE = 2
6142 00:26:02.908642 RX_GATING_TRACK_MODE = 2
6143 00:26:02.912004 SELPH_MODE = 1
6144 00:26:02.915444 PICG_EARLY_EN = 1
6145 00:26:02.918836 VALID_LAT_VALUE = 1
6146 00:26:02.921839 ==============================================================
6147 00:26:02.925139 Enter into Gating configuration >>>>
6148 00:26:02.928653 Exit from Gating configuration <<<<
6149 00:26:02.932212 Enter into DVFS_PRE_config >>>>>
6150 00:26:02.945465 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6151 00:26:02.948734 Exit from DVFS_PRE_config <<<<<
6152 00:26:02.948818 Enter into PICG configuration >>>>
6153 00:26:02.952271 Exit from PICG configuration <<<<
6154 00:26:02.955169 [RX_INPUT] configuration >>>>>
6155 00:26:02.958457 [RX_INPUT] configuration <<<<<
6156 00:26:02.965070 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6157 00:26:02.968329 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6158 00:26:02.975168 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6159 00:26:02.981443 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6160 00:26:02.988717 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6161 00:26:02.994770 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6162 00:26:02.998667 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6163 00:26:03.001727 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6164 00:26:03.005087 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6165 00:26:03.011695 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6166 00:26:03.014826 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6167 00:26:03.018361 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6168 00:26:03.021947 ===================================
6169 00:26:03.025003 LPDDR4 DRAM CONFIGURATION
6170 00:26:03.028518 ===================================
6171 00:26:03.031673 EX_ROW_EN[0] = 0x0
6172 00:26:03.031777 EX_ROW_EN[1] = 0x0
6173 00:26:03.034995 LP4Y_EN = 0x0
6174 00:26:03.035113 WORK_FSP = 0x0
6175 00:26:03.038546 WL = 0x2
6176 00:26:03.038650 RL = 0x2
6177 00:26:03.041412 BL = 0x2
6178 00:26:03.041514 RPST = 0x0
6179 00:26:03.045022 RD_PRE = 0x0
6180 00:26:03.045189 WR_PRE = 0x1
6181 00:26:03.048600 WR_PST = 0x0
6182 00:26:03.048700 DBI_WR = 0x0
6183 00:26:03.051473 DBI_RD = 0x0
6184 00:26:03.051608 OTF = 0x1
6185 00:26:03.054776 ===================================
6186 00:26:03.058447 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6187 00:26:03.064714 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6188 00:26:03.068194 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6189 00:26:03.071413 ===================================
6190 00:26:03.075026 LPDDR4 DRAM CONFIGURATION
6191 00:26:03.078347 ===================================
6192 00:26:03.078461 EX_ROW_EN[0] = 0x10
6193 00:26:03.081492 EX_ROW_EN[1] = 0x0
6194 00:26:03.084796 LP4Y_EN = 0x0
6195 00:26:03.084927 WORK_FSP = 0x0
6196 00:26:03.088136 WL = 0x2
6197 00:26:03.088220 RL = 0x2
6198 00:26:03.091303 BL = 0x2
6199 00:26:03.091430 RPST = 0x0
6200 00:26:03.094683 RD_PRE = 0x0
6201 00:26:03.094764 WR_PRE = 0x1
6202 00:26:03.098078 WR_PST = 0x0
6203 00:26:03.098159 DBI_WR = 0x0
6204 00:26:03.101516 DBI_RD = 0x0
6205 00:26:03.101599 OTF = 0x1
6206 00:26:03.104971 ===================================
6207 00:26:03.111633 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6208 00:26:03.115418 nWR fixed to 30
6209 00:26:03.118624 [ModeRegInit_LP4] CH0 RK0
6210 00:26:03.118706 [ModeRegInit_LP4] CH0 RK1
6211 00:26:03.121897 [ModeRegInit_LP4] CH1 RK0
6212 00:26:03.125471 [ModeRegInit_LP4] CH1 RK1
6213 00:26:03.125554 match AC timing 19
6214 00:26:03.132407 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6215 00:26:03.135368 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6216 00:26:03.138494 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6217 00:26:03.145601 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6218 00:26:03.148973 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6219 00:26:03.149057 ==
6220 00:26:03.152484 Dram Type= 6, Freq= 0, CH_0, rank 0
6221 00:26:03.155185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6222 00:26:03.155269 ==
6223 00:26:03.162139 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6224 00:26:03.168855 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6225 00:26:03.172025 [CA 0] Center 36 (8~64) winsize 57
6226 00:26:03.175667 [CA 1] Center 36 (8~64) winsize 57
6227 00:26:03.178528 [CA 2] Center 36 (8~64) winsize 57
6228 00:26:03.178609 [CA 3] Center 36 (8~64) winsize 57
6229 00:26:03.182059 [CA 4] Center 36 (8~64) winsize 57
6230 00:26:03.185215 [CA 5] Center 36 (8~64) winsize 57
6231 00:26:03.185297
6232 00:26:03.188543 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6233 00:26:03.191941
6234 00:26:03.195135 [CATrainingPosCal] consider 1 rank data
6235 00:26:03.195234 u2DelayCellTimex100 = 270/100 ps
6236 00:26:03.201993 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 00:26:03.205287 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 00:26:03.208869 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 00:26:03.212068 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 00:26:03.215102 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 00:26:03.218448 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 00:26:03.218551
6243 00:26:03.222000 CA PerBit enable=1, Macro0, CA PI delay=36
6244 00:26:03.222100
6245 00:26:03.225275 [CBTSetCACLKResult] CA Dly = 36
6246 00:26:03.228628 CS Dly: 1 (0~32)
6247 00:26:03.228727 ==
6248 00:26:03.231591 Dram Type= 6, Freq= 0, CH_0, rank 1
6249 00:26:03.235109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6250 00:26:03.235208 ==
6251 00:26:03.241834 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6252 00:26:03.244746 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6253 00:26:03.248157 [CA 0] Center 36 (8~64) winsize 57
6254 00:26:03.251622 [CA 1] Center 36 (8~64) winsize 57
6255 00:26:03.255180 [CA 2] Center 36 (8~64) winsize 57
6256 00:26:03.258088 [CA 3] Center 36 (8~64) winsize 57
6257 00:26:03.261473 [CA 4] Center 36 (8~64) winsize 57
6258 00:26:03.264823 [CA 5] Center 36 (8~64) winsize 57
6259 00:26:03.264926
6260 00:26:03.268350 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6261 00:26:03.268449
6262 00:26:03.271512 [CATrainingPosCal] consider 2 rank data
6263 00:26:03.274887 u2DelayCellTimex100 = 270/100 ps
6264 00:26:03.278355 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 00:26:03.281501 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 00:26:03.288277 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 00:26:03.291375 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 00:26:03.294501 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 00:26:03.298064 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 00:26:03.298167
6271 00:26:03.301256 CA PerBit enable=1, Macro0, CA PI delay=36
6272 00:26:03.301359
6273 00:26:03.304590 [CBTSetCACLKResult] CA Dly = 36
6274 00:26:03.304694 CS Dly: 1 (0~32)
6275 00:26:03.304789
6276 00:26:03.307762 ----->DramcWriteLeveling(PI) begin...
6277 00:26:03.311096 ==
6278 00:26:03.311197 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 00:26:03.317853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 00:26:03.317959 ==
6281 00:26:03.321001 Write leveling (Byte 0): 40 => 8
6282 00:26:03.324712 Write leveling (Byte 1): 40 => 8
6283 00:26:03.327617 DramcWriteLeveling(PI) end<-----
6284 00:26:03.327718
6285 00:26:03.327811 ==
6286 00:26:03.330818 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 00:26:03.334659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 00:26:03.334760 ==
6289 00:26:03.337882 [Gating] SW mode calibration
6290 00:26:03.344512 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6291 00:26:03.347849 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6292 00:26:03.354194 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6293 00:26:03.357780 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6294 00:26:03.360744 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6295 00:26:03.367876 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6296 00:26:03.371189 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6297 00:26:03.374133 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6298 00:26:03.381259 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6299 00:26:03.384093 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 00:26:03.387762 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 00:26:03.390933 Total UI for P1: 0, mck2ui 16
6302 00:26:03.394319 best dqsien dly found for B0: ( 0, 14, 24)
6303 00:26:03.397572 Total UI for P1: 0, mck2ui 16
6304 00:26:03.400868 best dqsien dly found for B1: ( 0, 14, 24)
6305 00:26:03.404195 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6306 00:26:03.408075 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6307 00:26:03.408157
6308 00:26:03.414567 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6309 00:26:03.417693 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6310 00:26:03.417823 [Gating] SW calibration Done
6311 00:26:03.420950 ==
6312 00:26:03.424577 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 00:26:03.427956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 00:26:03.428080 ==
6315 00:26:03.428177 RX Vref Scan: 0
6316 00:26:03.428268
6317 00:26:03.430871 RX Vref 0 -> 0, step: 1
6318 00:26:03.430971
6319 00:26:03.434369 RX Delay -410 -> 252, step: 16
6320 00:26:03.437690 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6321 00:26:03.440935 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6322 00:26:03.447944 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6323 00:26:03.451129 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6324 00:26:03.454358 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6325 00:26:03.458115 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6326 00:26:03.464596 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6327 00:26:03.467691 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6328 00:26:03.471037 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6329 00:26:03.474516 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6330 00:26:03.481188 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6331 00:26:03.484721 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6332 00:26:03.487994 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6333 00:26:03.491055 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6334 00:26:03.497487 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6335 00:26:03.500878 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6336 00:26:03.500974 ==
6337 00:26:03.504536 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 00:26:03.507916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 00:26:03.507997 ==
6340 00:26:03.510870 DQS Delay:
6341 00:26:03.510950 DQS0 = 27, DQS1 = 35
6342 00:26:03.514550 DQM Delay:
6343 00:26:03.514630 DQM0 = 8, DQM1 = 11
6344 00:26:03.514694 DQ Delay:
6345 00:26:03.517600 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6346 00:26:03.520820 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6347 00:26:03.524353 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6348 00:26:03.527466 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6349 00:26:03.527571
6350 00:26:03.527635
6351 00:26:03.527694 ==
6352 00:26:03.530947 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 00:26:03.537512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 00:26:03.537593 ==
6355 00:26:03.537657
6356 00:26:03.537717
6357 00:26:03.537823 TX Vref Scan disable
6358 00:26:03.540785 == TX Byte 0 ==
6359 00:26:03.544240 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6360 00:26:03.547539 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6361 00:26:03.551004 == TX Byte 1 ==
6362 00:26:03.554208 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6363 00:26:03.557401 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6364 00:26:03.557482 ==
6365 00:26:03.560969 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 00:26:03.567638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 00:26:03.567719 ==
6368 00:26:03.567783
6369 00:26:03.567859
6370 00:26:03.567930 TX Vref Scan disable
6371 00:26:03.570941 == TX Byte 0 ==
6372 00:26:03.574299 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6373 00:26:03.577982 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6374 00:26:03.580957 == TX Byte 1 ==
6375 00:26:03.584089 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 00:26:03.587835 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 00:26:03.587920
6378 00:26:03.590727 [DATLAT]
6379 00:26:03.590814 Freq=400, CH0 RK0
6380 00:26:03.590924
6381 00:26:03.594172 DATLAT Default: 0xf
6382 00:26:03.594254 0, 0xFFFF, sum = 0
6383 00:26:03.597411 1, 0xFFFF, sum = 0
6384 00:26:03.597494 2, 0xFFFF, sum = 0
6385 00:26:03.601136 3, 0xFFFF, sum = 0
6386 00:26:03.601219 4, 0xFFFF, sum = 0
6387 00:26:03.604296 5, 0xFFFF, sum = 0
6388 00:26:03.604380 6, 0xFFFF, sum = 0
6389 00:26:03.607889 7, 0xFFFF, sum = 0
6390 00:26:03.608003 8, 0xFFFF, sum = 0
6391 00:26:03.610992 9, 0xFFFF, sum = 0
6392 00:26:03.611078 10, 0xFFFF, sum = 0
6393 00:26:03.614031 11, 0xFFFF, sum = 0
6394 00:26:03.617427 12, 0xFFFF, sum = 0
6395 00:26:03.617510 13, 0x0, sum = 1
6396 00:26:03.617577 14, 0x0, sum = 2
6397 00:26:03.620953 15, 0x0, sum = 3
6398 00:26:03.621036 16, 0x0, sum = 4
6399 00:26:03.624000 best_step = 14
6400 00:26:03.624088
6401 00:26:03.624155 ==
6402 00:26:03.627389 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 00:26:03.630544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 00:26:03.630627 ==
6405 00:26:03.634346 RX Vref Scan: 1
6406 00:26:03.634429
6407 00:26:03.634497 RX Vref 0 -> 0, step: 1
6408 00:26:03.634559
6409 00:26:03.637367 RX Delay -311 -> 252, step: 8
6410 00:26:03.637449
6411 00:26:03.640972 Set Vref, RX VrefLevel [Byte0]: 54
6412 00:26:03.644313 [Byte1]: 48
6413 00:26:03.649096
6414 00:26:03.649177 Final RX Vref Byte 0 = 54 to rank0
6415 00:26:03.652326 Final RX Vref Byte 1 = 48 to rank0
6416 00:26:03.655757 Final RX Vref Byte 0 = 54 to rank1
6417 00:26:03.659193 Final RX Vref Byte 1 = 48 to rank1==
6418 00:26:03.662000 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 00:26:03.668687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 00:26:03.668790 ==
6421 00:26:03.668886 DQS Delay:
6422 00:26:03.671847 DQS0 = 28, DQS1 = 36
6423 00:26:03.671952 DQM Delay:
6424 00:26:03.672043 DQM0 = 11, DQM1 = 12
6425 00:26:03.675425 DQ Delay:
6426 00:26:03.678825 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6427 00:26:03.678929 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6428 00:26:03.681754 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6429 00:26:03.685371 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6430 00:26:03.685472
6431 00:26:03.685567
6432 00:26:03.695217 [DQSOSCAuto] RK0, (LSB)MR18= 0xd1be, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6433 00:26:03.698695 CH0 RK0: MR19=C0C, MR18=D1BE
6434 00:26:03.705502 CH0_RK0: MR19=0xC0C, MR18=0xD1BE, DQSOSC=384, MR23=63, INC=400, DEC=267
6435 00:26:03.705611 ==
6436 00:26:03.708709 Dram Type= 6, Freq= 0, CH_0, rank 1
6437 00:26:03.712294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 00:26:03.712396 ==
6439 00:26:03.715219 [Gating] SW mode calibration
6440 00:26:03.722020 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6441 00:26:03.725502 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6442 00:26:03.731854 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6443 00:26:03.735284 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6444 00:26:03.738651 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 00:26:03.745046 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6446 00:26:03.748338 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 00:26:03.752038 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 00:26:03.758554 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 00:26:03.761861 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 00:26:03.764795 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 00:26:03.768329 Total UI for P1: 0, mck2ui 16
6452 00:26:03.771726 best dqsien dly found for B0: ( 0, 14, 24)
6453 00:26:03.774957 Total UI for P1: 0, mck2ui 16
6454 00:26:03.778313 best dqsien dly found for B1: ( 0, 14, 24)
6455 00:26:03.781754 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6456 00:26:03.785257 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6457 00:26:03.788624
6458 00:26:03.791724 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6459 00:26:03.794767 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6460 00:26:03.798183 [Gating] SW calibration Done
6461 00:26:03.798265 ==
6462 00:26:03.801574 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 00:26:03.804994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 00:26:03.805134 ==
6465 00:26:03.805204 RX Vref Scan: 0
6466 00:26:03.805264
6467 00:26:03.808389 RX Vref 0 -> 0, step: 1
6468 00:26:03.808471
6469 00:26:03.811740 RX Delay -410 -> 252, step: 16
6470 00:26:03.814767 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6471 00:26:03.821433 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6472 00:26:03.824646 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6473 00:26:03.828292 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6474 00:26:03.831728 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6475 00:26:03.838170 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6476 00:26:03.841550 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6477 00:26:03.844671 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6478 00:26:03.848039 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6479 00:26:03.851489 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6480 00:26:03.857934 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6481 00:26:03.861511 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6482 00:26:03.865057 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6483 00:26:03.872006 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6484 00:26:03.874959 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6485 00:26:03.878192 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6486 00:26:03.878295 ==
6487 00:26:03.881565 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 00:26:03.885035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 00:26:03.885140 ==
6490 00:26:03.888017 DQS Delay:
6491 00:26:03.888138 DQS0 = 27, DQS1 = 35
6492 00:26:03.891841 DQM Delay:
6493 00:26:03.891941 DQM0 = 12, DQM1 = 11
6494 00:26:03.894567 DQ Delay:
6495 00:26:03.894665 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6496 00:26:03.898186 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6497 00:26:03.901381 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6498 00:26:03.905002 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6499 00:26:03.905103
6500 00:26:03.905198
6501 00:26:03.905291 ==
6502 00:26:03.907969 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 00:26:03.914570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 00:26:03.914675 ==
6505 00:26:03.914766
6506 00:26:03.914857
6507 00:26:03.914945 TX Vref Scan disable
6508 00:26:03.918094 == TX Byte 0 ==
6509 00:26:03.921458 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6510 00:26:03.924491 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6511 00:26:03.927838 == TX Byte 1 ==
6512 00:26:03.931251 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6513 00:26:03.934905 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6514 00:26:03.935038 ==
6515 00:26:03.938102 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 00:26:03.945119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 00:26:03.945221 ==
6518 00:26:03.945315
6519 00:26:03.945402
6520 00:26:03.945490 TX Vref Scan disable
6521 00:26:03.948302 == TX Byte 0 ==
6522 00:26:03.951312 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6523 00:26:03.954593 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6524 00:26:03.958196 == TX Byte 1 ==
6525 00:26:03.961268 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6526 00:26:03.964662 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6527 00:26:03.964763
6528 00:26:03.968144 [DATLAT]
6529 00:26:03.968247 Freq=400, CH0 RK1
6530 00:26:03.968339
6531 00:26:03.971572 DATLAT Default: 0xe
6532 00:26:03.971671 0, 0xFFFF, sum = 0
6533 00:26:03.974245 1, 0xFFFF, sum = 0
6534 00:26:03.974351 2, 0xFFFF, sum = 0
6535 00:26:03.977771 3, 0xFFFF, sum = 0
6536 00:26:03.977874 4, 0xFFFF, sum = 0
6537 00:26:03.981076 5, 0xFFFF, sum = 0
6538 00:26:03.981191 6, 0xFFFF, sum = 0
6539 00:26:03.984314 7, 0xFFFF, sum = 0
6540 00:26:03.984442 8, 0xFFFF, sum = 0
6541 00:26:03.987691 9, 0xFFFF, sum = 0
6542 00:26:03.991222 10, 0xFFFF, sum = 0
6543 00:26:03.991322 11, 0xFFFF, sum = 0
6544 00:26:03.994126 12, 0xFFFF, sum = 0
6545 00:26:03.994227 13, 0x0, sum = 1
6546 00:26:03.997942 14, 0x0, sum = 2
6547 00:26:03.998043 15, 0x0, sum = 3
6548 00:26:03.998135 16, 0x0, sum = 4
6549 00:26:04.001091 best_step = 14
6550 00:26:04.001187
6551 00:26:04.001297 ==
6552 00:26:04.004216 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 00:26:04.007761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 00:26:04.007858 ==
6555 00:26:04.011200 RX Vref Scan: 0
6556 00:26:04.011306
6557 00:26:04.011400 RX Vref 0 -> 0, step: 1
6558 00:26:04.014691
6559 00:26:04.014796 RX Delay -311 -> 252, step: 8
6560 00:26:04.022622 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6561 00:26:04.025968 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6562 00:26:04.029335 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6563 00:26:04.032875 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6564 00:26:04.039514 iDelay=217, Bit 4, Center -8 (-231 ~ 216) 448
6565 00:26:04.042630 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6566 00:26:04.045778 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6567 00:26:04.049214 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6568 00:26:04.055982 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6569 00:26:04.058923 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6570 00:26:04.062352 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6571 00:26:04.065727 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6572 00:26:04.072924 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6573 00:26:04.075620 iDelay=217, Bit 13, Center -16 (-231 ~ 200) 432
6574 00:26:04.079057 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6575 00:26:04.085466 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6576 00:26:04.085572 ==
6577 00:26:04.088856 Dram Type= 6, Freq= 0, CH_0, rank 1
6578 00:26:04.092006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 00:26:04.092097 ==
6580 00:26:04.092189 DQS Delay:
6581 00:26:04.095323 DQS0 = 24, DQS1 = 32
6582 00:26:04.095419 DQM Delay:
6583 00:26:04.098665 DQM0 = 10, DQM1 = 11
6584 00:26:04.098766 DQ Delay:
6585 00:26:04.102304 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6586 00:26:04.105681 DQ4 =16, DQ5 =0, DQ6 =12, DQ7 =16
6587 00:26:04.108953 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6588 00:26:04.112071 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6589 00:26:04.112171
6590 00:26:04.112266
6591 00:26:04.118463 [DQSOSCAuto] RK1, (LSB)MR18= 0xc160, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 385 ps
6592 00:26:04.121765 CH0 RK1: MR19=C0C, MR18=C160
6593 00:26:04.128340 CH0_RK1: MR19=0xC0C, MR18=0xC160, DQSOSC=385, MR23=63, INC=398, DEC=265
6594 00:26:04.131899 [RxdqsGatingPostProcess] freq 400
6595 00:26:04.138200 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6596 00:26:04.141696 best DQS0 dly(2T, 0.5T) = (0, 10)
6597 00:26:04.145314 best DQS1 dly(2T, 0.5T) = (0, 10)
6598 00:26:04.145411 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6599 00:26:04.148118 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6600 00:26:04.151429 best DQS0 dly(2T, 0.5T) = (0, 10)
6601 00:26:04.154846 best DQS1 dly(2T, 0.5T) = (0, 10)
6602 00:26:04.158433 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6603 00:26:04.161455 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6604 00:26:04.165039 Pre-setting of DQS Precalculation
6605 00:26:04.171404 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6606 00:26:04.171510 ==
6607 00:26:04.175061 Dram Type= 6, Freq= 0, CH_1, rank 0
6608 00:26:04.178661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 00:26:04.178764 ==
6610 00:26:04.184949 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6611 00:26:04.188376 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6612 00:26:04.191458 [CA 0] Center 36 (8~64) winsize 57
6613 00:26:04.194737 [CA 1] Center 36 (8~64) winsize 57
6614 00:26:04.198316 [CA 2] Center 36 (8~64) winsize 57
6615 00:26:04.201819 [CA 3] Center 36 (8~64) winsize 57
6616 00:26:04.205074 [CA 4] Center 36 (8~64) winsize 57
6617 00:26:04.208031 [CA 5] Center 36 (8~64) winsize 57
6618 00:26:04.208132
6619 00:26:04.211335 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6620 00:26:04.211436
6621 00:26:04.214726 [CATrainingPosCal] consider 1 rank data
6622 00:26:04.218089 u2DelayCellTimex100 = 270/100 ps
6623 00:26:04.221505 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 00:26:04.224757 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 00:26:04.228302 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 00:26:04.235024 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 00:26:04.238105 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 00:26:04.241586 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 00:26:04.241685
6630 00:26:04.244639 CA PerBit enable=1, Macro0, CA PI delay=36
6631 00:26:04.244739
6632 00:26:04.247861 [CBTSetCACLKResult] CA Dly = 36
6633 00:26:04.247938 CS Dly: 1 (0~32)
6634 00:26:04.248033 ==
6635 00:26:04.251254 Dram Type= 6, Freq= 0, CH_1, rank 1
6636 00:26:04.257866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 00:26:04.257970 ==
6638 00:26:04.261315 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6639 00:26:04.267902 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6640 00:26:04.271209 [CA 0] Center 36 (8~64) winsize 57
6641 00:26:04.274808 [CA 1] Center 36 (8~64) winsize 57
6642 00:26:04.278160 [CA 2] Center 36 (8~64) winsize 57
6643 00:26:04.281360 [CA 3] Center 36 (8~64) winsize 57
6644 00:26:04.285010 [CA 4] Center 36 (8~64) winsize 57
6645 00:26:04.288298 [CA 5] Center 36 (8~64) winsize 57
6646 00:26:04.288379
6647 00:26:04.291631 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6648 00:26:04.291715
6649 00:26:04.294471 [CATrainingPosCal] consider 2 rank data
6650 00:26:04.297885 u2DelayCellTimex100 = 270/100 ps
6651 00:26:04.301676 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 00:26:04.304832 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 00:26:04.307959 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 00:26:04.311468 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 00:26:04.314870 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 00:26:04.318125 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 00:26:04.318208
6658 00:26:04.324502 CA PerBit enable=1, Macro0, CA PI delay=36
6659 00:26:04.324585
6660 00:26:04.324650 [CBTSetCACLKResult] CA Dly = 36
6661 00:26:04.328425 CS Dly: 1 (0~32)
6662 00:26:04.328509
6663 00:26:04.331536 ----->DramcWriteLeveling(PI) begin...
6664 00:26:04.331621 ==
6665 00:26:04.334489 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 00:26:04.338215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 00:26:04.338300 ==
6668 00:26:04.341495 Write leveling (Byte 0): 40 => 8
6669 00:26:04.344828 Write leveling (Byte 1): 40 => 8
6670 00:26:04.348177 DramcWriteLeveling(PI) end<-----
6671 00:26:04.348260
6672 00:26:04.348326 ==
6673 00:26:04.351584 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 00:26:04.354951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 00:26:04.358040 ==
6676 00:26:04.358123 [Gating] SW mode calibration
6677 00:26:04.364729 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6678 00:26:04.371495 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6679 00:26:04.374658 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6680 00:26:04.381395 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6681 00:26:04.384656 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6682 00:26:04.387782 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6683 00:26:04.394914 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6684 00:26:04.398277 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6685 00:26:04.401033 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6686 00:26:04.407804 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 00:26:04.411211 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 00:26:04.414589 Total UI for P1: 0, mck2ui 16
6689 00:26:04.418166 best dqsien dly found for B0: ( 0, 14, 24)
6690 00:26:04.421411 Total UI for P1: 0, mck2ui 16
6691 00:26:04.424745 best dqsien dly found for B1: ( 0, 14, 24)
6692 00:26:04.427877 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6693 00:26:04.430964 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6694 00:26:04.431047
6695 00:26:04.434606 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6696 00:26:04.438133 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6697 00:26:04.441343 [Gating] SW calibration Done
6698 00:26:04.441426 ==
6699 00:26:04.444977 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 00:26:04.448189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 00:26:04.448273 ==
6702 00:26:04.451041 RX Vref Scan: 0
6703 00:26:04.451123
6704 00:26:04.454452 RX Vref 0 -> 0, step: 1
6705 00:26:04.454535
6706 00:26:04.454602 RX Delay -410 -> 252, step: 16
6707 00:26:04.461596 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6708 00:26:04.464953 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6709 00:26:04.467789 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6710 00:26:04.474469 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6711 00:26:04.477833 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6712 00:26:04.481139 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6713 00:26:04.484558 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6714 00:26:04.488071 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6715 00:26:04.494601 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6716 00:26:04.497924 iDelay=230, Bit 9, Center -27 (-250 ~ 197) 448
6717 00:26:04.501120 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6718 00:26:04.504372 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6719 00:26:04.510947 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6720 00:26:04.514612 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6721 00:26:04.517934 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6722 00:26:04.524704 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6723 00:26:04.524787 ==
6724 00:26:04.527771 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 00:26:04.531221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 00:26:04.531306 ==
6727 00:26:04.531372 DQS Delay:
6728 00:26:04.534584 DQS0 = 27, DQS1 = 27
6729 00:26:04.534680 DQM Delay:
6730 00:26:04.537513 DQM0 = 11, DQM1 = 8
6731 00:26:04.537594 DQ Delay:
6732 00:26:04.540980 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6733 00:26:04.544156 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6734 00:26:04.547530 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6735 00:26:04.550970 DQ12 =16, DQ13 =8, DQ14 =8, DQ15 =16
6736 00:26:04.551065
6737 00:26:04.551128
6738 00:26:04.551202 ==
6739 00:26:04.554396 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 00:26:04.557515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 00:26:04.557599 ==
6742 00:26:04.557665
6743 00:26:04.557726
6744 00:26:04.560792 TX Vref Scan disable
6745 00:26:04.560890 == TX Byte 0 ==
6746 00:26:04.567629 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6747 00:26:04.571026 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6748 00:26:04.571109 == TX Byte 1 ==
6749 00:26:04.574006 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 00:26:04.580914 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 00:26:04.581000 ==
6752 00:26:04.584408 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 00:26:04.587505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 00:26:04.587599 ==
6755 00:26:04.587666
6756 00:26:04.587727
6757 00:26:04.590755 TX Vref Scan disable
6758 00:26:04.590838 == TX Byte 0 ==
6759 00:26:04.597417 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6760 00:26:04.600976 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6761 00:26:04.601060 == TX Byte 1 ==
6762 00:26:04.607563 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 00:26:04.611118 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 00:26:04.611201
6765 00:26:04.611266 [DATLAT]
6766 00:26:04.614277 Freq=400, CH1 RK0
6767 00:26:04.614361
6768 00:26:04.614427 DATLAT Default: 0xf
6769 00:26:04.617299 0, 0xFFFF, sum = 0
6770 00:26:04.617384 1, 0xFFFF, sum = 0
6771 00:26:04.620744 2, 0xFFFF, sum = 0
6772 00:26:04.620828 3, 0xFFFF, sum = 0
6773 00:26:04.624150 4, 0xFFFF, sum = 0
6774 00:26:04.624234 5, 0xFFFF, sum = 0
6775 00:26:04.627712 6, 0xFFFF, sum = 0
6776 00:26:04.627797 7, 0xFFFF, sum = 0
6777 00:26:04.630641 8, 0xFFFF, sum = 0
6778 00:26:04.630726 9, 0xFFFF, sum = 0
6779 00:26:04.634214 10, 0xFFFF, sum = 0
6780 00:26:04.634298 11, 0xFFFF, sum = 0
6781 00:26:04.637478 12, 0xFFFF, sum = 0
6782 00:26:04.637575 13, 0x0, sum = 1
6783 00:26:04.640749 14, 0x0, sum = 2
6784 00:26:04.640834 15, 0x0, sum = 3
6785 00:26:04.644189 16, 0x0, sum = 4
6786 00:26:04.644274 best_step = 14
6787 00:26:04.644340
6788 00:26:04.644401 ==
6789 00:26:04.647481 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 00:26:04.653825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 00:26:04.653909 ==
6792 00:26:04.653975 RX Vref Scan: 1
6793 00:26:04.654038
6794 00:26:04.657112 RX Vref 0 -> 0, step: 1
6795 00:26:04.657196
6796 00:26:04.660705 RX Delay -295 -> 252, step: 8
6797 00:26:04.660815
6798 00:26:04.664229 Set Vref, RX VrefLevel [Byte0]: 54
6799 00:26:04.667100 [Byte1]: 48
6800 00:26:04.667183
6801 00:26:04.670552 Final RX Vref Byte 0 = 54 to rank0
6802 00:26:04.674102 Final RX Vref Byte 1 = 48 to rank0
6803 00:26:04.677503 Final RX Vref Byte 0 = 54 to rank1
6804 00:26:04.680660 Final RX Vref Byte 1 = 48 to rank1==
6805 00:26:04.683816 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 00:26:04.686888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 00:26:04.690333 ==
6808 00:26:04.690417 DQS Delay:
6809 00:26:04.690485 DQS0 = 32, DQS1 = 32
6810 00:26:04.693870 DQM Delay:
6811 00:26:04.693954 DQM0 = 14, DQM1 = 11
6812 00:26:04.697039 DQ Delay:
6813 00:26:04.697122 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6814 00:26:04.700303 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6815 00:26:04.703841 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6816 00:26:04.707196 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6817 00:26:04.707267
6818 00:26:04.707330
6819 00:26:04.717062 [DQSOSCAuto] RK0, (LSB)MR18= 0x8fc7, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 391 ps
6820 00:26:04.720676 CH1 RK0: MR19=C0C, MR18=8FC7
6821 00:26:04.727227 CH1_RK0: MR19=0xC0C, MR18=0x8FC7, DQSOSC=385, MR23=63, INC=398, DEC=265
6822 00:26:04.727309 ==
6823 00:26:04.730805 Dram Type= 6, Freq= 0, CH_1, rank 1
6824 00:26:04.733691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 00:26:04.733772 ==
6826 00:26:04.737046 [Gating] SW mode calibration
6827 00:26:04.743899 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6828 00:26:04.746835 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6829 00:26:04.754012 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6830 00:26:04.757247 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6831 00:26:04.760107 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6832 00:26:04.767009 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6833 00:26:04.770248 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6834 00:26:04.773330 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6835 00:26:04.780264 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6836 00:26:04.783759 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 00:26:04.786896 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 00:26:04.790222 Total UI for P1: 0, mck2ui 16
6839 00:26:04.793519 best dqsien dly found for B0: ( 0, 14, 24)
6840 00:26:04.796624 Total UI for P1: 0, mck2ui 16
6841 00:26:04.800138 best dqsien dly found for B1: ( 0, 14, 24)
6842 00:26:04.803393 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6843 00:26:04.806627 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6844 00:26:04.809765
6845 00:26:04.813407 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6846 00:26:04.816294 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6847 00:26:04.819789 [Gating] SW calibration Done
6848 00:26:04.819872 ==
6849 00:26:04.823003 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 00:26:04.826327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 00:26:04.826411 ==
6852 00:26:04.826478 RX Vref Scan: 0
6853 00:26:04.829944
6854 00:26:04.830027 RX Vref 0 -> 0, step: 1
6855 00:26:04.830094
6856 00:26:04.833345 RX Delay -410 -> 252, step: 16
6857 00:26:04.836398 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6858 00:26:04.843410 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6859 00:26:04.846414 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6860 00:26:04.849789 iDelay=230, Bit 3, Center -11 (-234 ~ 213) 448
6861 00:26:04.853120 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6862 00:26:04.859751 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6863 00:26:04.863178 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6864 00:26:04.866493 iDelay=230, Bit 7, Center -11 (-234 ~ 213) 448
6865 00:26:04.870141 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6866 00:26:04.876251 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6867 00:26:04.879758 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6868 00:26:04.883236 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6869 00:26:04.886582 iDelay=230, Bit 12, Center -3 (-234 ~ 229) 464
6870 00:26:04.892744 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6871 00:26:04.896175 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6872 00:26:04.899614 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6873 00:26:04.899719 ==
6874 00:26:04.903117 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 00:26:04.906189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 00:26:04.909619 ==
6877 00:26:04.909739 DQS Delay:
6878 00:26:04.909826 DQS0 = 35, DQS1 = 35
6879 00:26:04.912874 DQM Delay:
6880 00:26:04.912958 DQM0 = 21, DQM1 = 17
6881 00:26:04.916093 DQ Delay:
6882 00:26:04.916200 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =24
6883 00:26:04.919284 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =24
6884 00:26:04.922539 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6885 00:26:04.926057 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6886 00:26:04.926164
6887 00:26:04.926259
6888 00:26:04.929756 ==
6889 00:26:04.932545 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 00:26:04.936057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 00:26:04.936132 ==
6892 00:26:04.936196
6893 00:26:04.936257
6894 00:26:04.939392 TX Vref Scan disable
6895 00:26:04.939475 == TX Byte 0 ==
6896 00:26:04.942560 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6897 00:26:04.949555 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6898 00:26:04.949640 == TX Byte 1 ==
6899 00:26:04.952685 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6900 00:26:04.956439 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6901 00:26:04.959392 ==
6902 00:26:04.962512 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 00:26:04.965774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 00:26:04.965858 ==
6905 00:26:04.965924
6906 00:26:04.965986
6907 00:26:04.969199 TX Vref Scan disable
6908 00:26:04.969281 == TX Byte 0 ==
6909 00:26:04.972714 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6910 00:26:04.979324 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6911 00:26:04.979436 == TX Byte 1 ==
6912 00:26:04.982862 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6913 00:26:04.989362 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6914 00:26:04.989446
6915 00:26:04.989517 [DATLAT]
6916 00:26:04.989595 Freq=400, CH1 RK1
6917 00:26:04.989674
6918 00:26:04.992659 DATLAT Default: 0xe
6919 00:26:04.992743 0, 0xFFFF, sum = 0
6920 00:26:04.995808 1, 0xFFFF, sum = 0
6921 00:26:04.995893 2, 0xFFFF, sum = 0
6922 00:26:04.999209 3, 0xFFFF, sum = 0
6923 00:26:05.002591 4, 0xFFFF, sum = 0
6924 00:26:05.002676 5, 0xFFFF, sum = 0
6925 00:26:05.005751 6, 0xFFFF, sum = 0
6926 00:26:05.005835 7, 0xFFFF, sum = 0
6927 00:26:05.009494 8, 0xFFFF, sum = 0
6928 00:26:05.009579 9, 0xFFFF, sum = 0
6929 00:26:05.012805 10, 0xFFFF, sum = 0
6930 00:26:05.012890 11, 0xFFFF, sum = 0
6931 00:26:05.015908 12, 0xFFFF, sum = 0
6932 00:26:05.015993 13, 0x0, sum = 1
6933 00:26:05.019112 14, 0x0, sum = 2
6934 00:26:05.019197 15, 0x0, sum = 3
6935 00:26:05.022824 16, 0x0, sum = 4
6936 00:26:05.022909 best_step = 14
6937 00:26:05.022975
6938 00:26:05.023037 ==
6939 00:26:05.025786 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 00:26:05.029405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 00:26:05.029489 ==
6942 00:26:05.032572 RX Vref Scan: 0
6943 00:26:05.032682
6944 00:26:05.035664 RX Vref 0 -> 0, step: 1
6945 00:26:05.035767
6946 00:26:05.035861 RX Delay -311 -> 252, step: 8
6947 00:26:05.044642 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6948 00:26:05.047831 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6949 00:26:05.051009 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6950 00:26:05.054200 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6951 00:26:05.060997 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6952 00:26:05.064311 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6953 00:26:05.067819 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6954 00:26:05.071182 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6955 00:26:05.077605 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6956 00:26:05.081152 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6957 00:26:05.084248 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6958 00:26:05.087989 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6959 00:26:05.094251 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6960 00:26:05.097577 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6961 00:26:05.100882 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6962 00:26:05.107668 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6963 00:26:05.107779 ==
6964 00:26:05.110828 Dram Type= 6, Freq= 0, CH_1, rank 1
6965 00:26:05.114140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6966 00:26:05.114243 ==
6967 00:26:05.114337 DQS Delay:
6968 00:26:05.117408 DQS0 = 28, DQS1 = 32
6969 00:26:05.117510 DQM Delay:
6970 00:26:05.120572 DQM0 = 11, DQM1 = 11
6971 00:26:05.120676 DQ Delay:
6972 00:26:05.124021 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6973 00:26:05.127128 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6974 00:26:05.130428 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6975 00:26:05.133704 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6976 00:26:05.133806
6977 00:26:05.133903
6978 00:26:05.140782 [DQSOSCAuto] RK1, (LSB)MR18= 0xc758, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6979 00:26:05.143897 CH1 RK1: MR19=C0C, MR18=C758
6980 00:26:05.150787 CH1_RK1: MR19=0xC0C, MR18=0xC758, DQSOSC=385, MR23=63, INC=398, DEC=265
6981 00:26:05.153900 [RxdqsGatingPostProcess] freq 400
6982 00:26:05.160436 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6983 00:26:05.163746 best DQS0 dly(2T, 0.5T) = (0, 10)
6984 00:26:05.163849 best DQS1 dly(2T, 0.5T) = (0, 10)
6985 00:26:05.166952 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6986 00:26:05.170818 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6987 00:26:05.173955 best DQS0 dly(2T, 0.5T) = (0, 10)
6988 00:26:05.177346 best DQS1 dly(2T, 0.5T) = (0, 10)
6989 00:26:05.180811 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6990 00:26:05.183641 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6991 00:26:05.187129 Pre-setting of DQS Precalculation
6992 00:26:05.193968 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6993 00:26:05.200711 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6994 00:26:05.207460 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6995 00:26:05.207576
6996 00:26:05.207649
6997 00:26:05.210796 [Calibration Summary] 800 Mbps
6998 00:26:05.210900 CH 0, Rank 0
6999 00:26:05.213924 SW Impedance : PASS
7000 00:26:05.214020 DUTY Scan : NO K
7001 00:26:05.217368 ZQ Calibration : PASS
7002 00:26:05.220637 Jitter Meter : NO K
7003 00:26:05.220736 CBT Training : PASS
7004 00:26:05.223975 Write leveling : PASS
7005 00:26:05.227160 RX DQS gating : PASS
7006 00:26:05.227259 RX DQ/DQS(RDDQC) : PASS
7007 00:26:05.230484 TX DQ/DQS : PASS
7008 00:26:05.233925 RX DATLAT : PASS
7009 00:26:05.234040 RX DQ/DQS(Engine): PASS
7010 00:26:05.237114 TX OE : NO K
7011 00:26:05.237214 All Pass.
7012 00:26:05.237306
7013 00:26:05.240613 CH 0, Rank 1
7014 00:26:05.240720 SW Impedance : PASS
7015 00:26:05.243742 DUTY Scan : NO K
7016 00:26:05.246830 ZQ Calibration : PASS
7017 00:26:05.246930 Jitter Meter : NO K
7018 00:26:05.250374 CBT Training : PASS
7019 00:26:05.253819 Write leveling : NO K
7020 00:26:05.253917 RX DQS gating : PASS
7021 00:26:05.257407 RX DQ/DQS(RDDQC) : PASS
7022 00:26:05.257513 TX DQ/DQS : PASS
7023 00:26:05.260521 RX DATLAT : PASS
7024 00:26:05.263596 RX DQ/DQS(Engine): PASS
7025 00:26:05.263691 TX OE : NO K
7026 00:26:05.267355 All Pass.
7027 00:26:05.267454
7028 00:26:05.267583 CH 1, Rank 0
7029 00:26:05.270253 SW Impedance : PASS
7030 00:26:05.270357 DUTY Scan : NO K
7031 00:26:05.273784 ZQ Calibration : PASS
7032 00:26:05.276962 Jitter Meter : NO K
7033 00:26:05.277067 CBT Training : PASS
7034 00:26:05.280314 Write leveling : PASS
7035 00:26:05.283470 RX DQS gating : PASS
7036 00:26:05.283607 RX DQ/DQS(RDDQC) : PASS
7037 00:26:05.286767 TX DQ/DQS : PASS
7038 00:26:05.290446 RX DATLAT : PASS
7039 00:26:05.290555 RX DQ/DQS(Engine): PASS
7040 00:26:05.293310 TX OE : NO K
7041 00:26:05.293410 All Pass.
7042 00:26:05.293511
7043 00:26:05.296571 CH 1, Rank 1
7044 00:26:05.296674 SW Impedance : PASS
7045 00:26:05.300156 DUTY Scan : NO K
7046 00:26:05.303601 ZQ Calibration : PASS
7047 00:26:05.303707 Jitter Meter : NO K
7048 00:26:05.306887 CBT Training : PASS
7049 00:26:05.310110 Write leveling : NO K
7050 00:26:05.310213 RX DQS gating : PASS
7051 00:26:05.313427 RX DQ/DQS(RDDQC) : PASS
7052 00:26:05.313534 TX DQ/DQS : PASS
7053 00:26:05.316870 RX DATLAT : PASS
7054 00:26:05.320364 RX DQ/DQS(Engine): PASS
7055 00:26:05.320464 TX OE : NO K
7056 00:26:05.323217 All Pass.
7057 00:26:05.323319
7058 00:26:05.323411 DramC Write-DBI off
7059 00:26:05.326772 PER_BANK_REFRESH: Hybrid Mode
7060 00:26:05.329974 TX_TRACKING: ON
7061 00:26:05.336624 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7062 00:26:05.340327 [FAST_K] Save calibration result to emmc
7063 00:26:05.343209 dramc_set_vcore_voltage set vcore to 725000
7064 00:26:05.346562 Read voltage for 1600, 0
7065 00:26:05.346662 Vio18 = 0
7066 00:26:05.349917 Vcore = 725000
7067 00:26:05.350013 Vdram = 0
7068 00:26:05.350107 Vddq = 0
7069 00:26:05.353123 Vmddr = 0
7070 00:26:05.356602 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7071 00:26:05.363281 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7072 00:26:05.363395 MEM_TYPE=3, freq_sel=13
7073 00:26:05.366524 sv_algorithm_assistance_LP4_3733
7074 00:26:05.373112 ============ PULL DRAM RESETB DOWN ============
7075 00:26:05.376563 ========== PULL DRAM RESETB DOWN end =========
7076 00:26:05.380170 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7077 00:26:05.382917 ===================================
7078 00:26:05.386475 LPDDR4 DRAM CONFIGURATION
7079 00:26:05.390043 ===================================
7080 00:26:05.393192 EX_ROW_EN[0] = 0x0
7081 00:26:05.393275 EX_ROW_EN[1] = 0x0
7082 00:26:05.396362 LP4Y_EN = 0x0
7083 00:26:05.396479 WORK_FSP = 0x1
7084 00:26:05.400643 WL = 0x5
7085 00:26:05.400755 RL = 0x5
7086 00:26:05.403336 BL = 0x2
7087 00:26:05.403440 RPST = 0x0
7088 00:26:05.406232 RD_PRE = 0x0
7089 00:26:05.406337 WR_PRE = 0x1
7090 00:26:05.409924 WR_PST = 0x1
7091 00:26:05.410036 DBI_WR = 0x0
7092 00:26:05.413047 DBI_RD = 0x0
7093 00:26:05.413148 OTF = 0x1
7094 00:26:05.416394 ===================================
7095 00:26:05.419897 ===================================
7096 00:26:05.423189 ANA top config
7097 00:26:05.426528 ===================================
7098 00:26:05.429663 DLL_ASYNC_EN = 0
7099 00:26:05.429774 ALL_SLAVE_EN = 0
7100 00:26:05.432943 NEW_RANK_MODE = 1
7101 00:26:05.436234 DLL_IDLE_MODE = 1
7102 00:26:05.439669 LP45_APHY_COMB_EN = 1
7103 00:26:05.439785 TX_ODT_DIS = 0
7104 00:26:05.443027 NEW_8X_MODE = 1
7105 00:26:05.445940 ===================================
7106 00:26:05.449450 ===================================
7107 00:26:05.452880 data_rate = 3200
7108 00:26:05.456047 CKR = 1
7109 00:26:05.459557 DQ_P2S_RATIO = 8
7110 00:26:05.462577 ===================================
7111 00:26:05.466019 CA_P2S_RATIO = 8
7112 00:26:05.466119 DQ_CA_OPEN = 0
7113 00:26:05.469353 DQ_SEMI_OPEN = 0
7114 00:26:05.472942 CA_SEMI_OPEN = 0
7115 00:26:05.476196 CA_FULL_RATE = 0
7116 00:26:05.479865 DQ_CKDIV4_EN = 0
7117 00:26:05.482714 CA_CKDIV4_EN = 0
7118 00:26:05.482819 CA_PREDIV_EN = 0
7119 00:26:05.486113 PH8_DLY = 12
7120 00:26:05.489668 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7121 00:26:05.492607 DQ_AAMCK_DIV = 4
7122 00:26:05.495833 CA_AAMCK_DIV = 4
7123 00:26:05.499395 CA_ADMCK_DIV = 4
7124 00:26:05.499492 DQ_TRACK_CA_EN = 0
7125 00:26:05.502801 CA_PICK = 1600
7126 00:26:05.506234 CA_MCKIO = 1600
7127 00:26:05.509047 MCKIO_SEMI = 0
7128 00:26:05.512373 PLL_FREQ = 3068
7129 00:26:05.515710 DQ_UI_PI_RATIO = 32
7130 00:26:05.518801 CA_UI_PI_RATIO = 0
7131 00:26:05.522550 ===================================
7132 00:26:05.525339 ===================================
7133 00:26:05.525446 memory_type:LPDDR4
7134 00:26:05.529230 GP_NUM : 10
7135 00:26:05.532292 SRAM_EN : 1
7136 00:26:05.532401 MD32_EN : 0
7137 00:26:05.535416 ===================================
7138 00:26:05.539095 [ANA_INIT] >>>>>>>>>>>>>>
7139 00:26:05.542061 <<<<<< [CONFIGURE PHASE]: ANA_TX
7140 00:26:05.545484 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7141 00:26:05.548806 ===================================
7142 00:26:05.552015 data_rate = 3200,PCW = 0X7600
7143 00:26:05.555775 ===================================
7144 00:26:05.559297 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7145 00:26:05.562406 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7146 00:26:05.569021 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7147 00:26:05.572469 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7148 00:26:05.575533 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7149 00:26:05.579079 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7150 00:26:05.582013 [ANA_INIT] flow start
7151 00:26:05.585454 [ANA_INIT] PLL >>>>>>>>
7152 00:26:05.585556 [ANA_INIT] PLL <<<<<<<<
7153 00:26:05.588821 [ANA_INIT] MIDPI >>>>>>>>
7154 00:26:05.591763 [ANA_INIT] MIDPI <<<<<<<<
7155 00:26:05.595246 [ANA_INIT] DLL >>>>>>>>
7156 00:26:05.595347 [ANA_INIT] DLL <<<<<<<<
7157 00:26:05.598635 [ANA_INIT] flow end
7158 00:26:05.602085 ============ LP4 DIFF to SE enter ============
7159 00:26:05.605035 ============ LP4 DIFF to SE exit ============
7160 00:26:05.608367 [ANA_INIT] <<<<<<<<<<<<<
7161 00:26:05.612147 [Flow] Enable top DCM control >>>>>
7162 00:26:05.614973 [Flow] Enable top DCM control <<<<<
7163 00:26:05.618351 Enable DLL master slave shuffle
7164 00:26:05.625093 ==============================================================
7165 00:26:05.625204 Gating Mode config
7166 00:26:05.631841 ==============================================================
7167 00:26:05.631946 Config description:
7168 00:26:05.641971 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7169 00:26:05.648226 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7170 00:26:05.654801 SELPH_MODE 0: By rank 1: By Phase
7171 00:26:05.658086 ==============================================================
7172 00:26:05.661860 GAT_TRACK_EN = 1
7173 00:26:05.664966 RX_GATING_MODE = 2
7174 00:26:05.668106 RX_GATING_TRACK_MODE = 2
7175 00:26:05.671452 SELPH_MODE = 1
7176 00:26:05.675064 PICG_EARLY_EN = 1
7177 00:26:05.678041 VALID_LAT_VALUE = 1
7178 00:26:05.681614 ==============================================================
7179 00:26:05.685157 Enter into Gating configuration >>>>
7180 00:26:05.691286 Exit from Gating configuration <<<<
7181 00:26:05.691396 Enter into DVFS_PRE_config >>>>>
7182 00:26:05.704888 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7183 00:26:05.707706 Exit from DVFS_PRE_config <<<<<
7184 00:26:05.711096 Enter into PICG configuration >>>>
7185 00:26:05.714867 Exit from PICG configuration <<<<
7186 00:26:05.714968 [RX_INPUT] configuration >>>>>
7187 00:26:05.718092 [RX_INPUT] configuration <<<<<
7188 00:26:05.724718 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7189 00:26:05.728246 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7190 00:26:05.734369 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7191 00:26:05.741334 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7192 00:26:05.748093 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7193 00:26:05.754450 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7194 00:26:05.757908 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7195 00:26:05.761424 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7196 00:26:05.768030 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7197 00:26:05.771007 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7198 00:26:05.774587 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7199 00:26:05.777756 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7200 00:26:05.780815 ===================================
7201 00:26:05.784675 LPDDR4 DRAM CONFIGURATION
7202 00:26:05.787811 ===================================
7203 00:26:05.791092 EX_ROW_EN[0] = 0x0
7204 00:26:05.791229 EX_ROW_EN[1] = 0x0
7205 00:26:05.794342 LP4Y_EN = 0x0
7206 00:26:05.794456 WORK_FSP = 0x1
7207 00:26:05.797839 WL = 0x5
7208 00:26:05.797952 RL = 0x5
7209 00:26:05.801151 BL = 0x2
7210 00:26:05.801255 RPST = 0x0
7211 00:26:05.804165 RD_PRE = 0x0
7212 00:26:05.804252 WR_PRE = 0x1
7213 00:26:05.808018 WR_PST = 0x1
7214 00:26:05.808131 DBI_WR = 0x0
7215 00:26:05.810882 DBI_RD = 0x0
7216 00:26:05.811011 OTF = 0x1
7217 00:26:05.814732 ===================================
7218 00:26:05.820784 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7219 00:26:05.824472 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7220 00:26:05.827398 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7221 00:26:05.830693 ===================================
7222 00:26:05.834291 LPDDR4 DRAM CONFIGURATION
7223 00:26:05.837610 ===================================
7224 00:26:05.840743 EX_ROW_EN[0] = 0x10
7225 00:26:05.840853 EX_ROW_EN[1] = 0x0
7226 00:26:05.844113 LP4Y_EN = 0x0
7227 00:26:05.844246 WORK_FSP = 0x1
7228 00:26:05.847668 WL = 0x5
7229 00:26:05.847778 RL = 0x5
7230 00:26:05.851201 BL = 0x2
7231 00:26:05.851307 RPST = 0x0
7232 00:26:05.853984 RD_PRE = 0x0
7233 00:26:05.854119 WR_PRE = 0x1
7234 00:26:05.857500 WR_PST = 0x1
7235 00:26:05.857610 DBI_WR = 0x0
7236 00:26:05.860595 DBI_RD = 0x0
7237 00:26:05.860699 OTF = 0x1
7238 00:26:05.864446 ===================================
7239 00:26:05.870845 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7240 00:26:05.870958 ==
7241 00:26:05.874048 Dram Type= 6, Freq= 0, CH_0, rank 0
7242 00:26:05.881024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7243 00:26:05.881147 ==
7244 00:26:05.881246 [Duty_Offset_Calibration]
7245 00:26:05.884062 B0:2 B1:1 CA:1
7246 00:26:05.884164
7247 00:26:05.887145 [DutyScan_Calibration_Flow] k_type=0
7248 00:26:05.896515
7249 00:26:05.896651 ==CLK 0==
7250 00:26:05.899900 Final CLK duty delay cell = 0
7251 00:26:05.903363 [0] MAX Duty = 5156%(X100), DQS PI = 22
7252 00:26:05.906802 [0] MIN Duty = 4907%(X100), DQS PI = 0
7253 00:26:05.906910 [0] AVG Duty = 5031%(X100)
7254 00:26:05.909794
7255 00:26:05.912872 CH0 CLK Duty spec in!! Max-Min= 249%
7256 00:26:05.916893 [DutyScan_Calibration_Flow] ====Done====
7257 00:26:05.917000
7258 00:26:05.919861 [DutyScan_Calibration_Flow] k_type=1
7259 00:26:05.935739
7260 00:26:05.935832 ==DQS 0 ==
7261 00:26:05.938837 Final DQS duty delay cell = -4
7262 00:26:05.942508 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7263 00:26:05.945703 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7264 00:26:05.948758 [-4] AVG Duty = 4891%(X100)
7265 00:26:05.948866
7266 00:26:05.948961 ==DQS 1 ==
7267 00:26:05.952295 Final DQS duty delay cell = 0
7268 00:26:05.955806 [0] MAX Duty = 5218%(X100), DQS PI = 20
7269 00:26:05.959197 [0] MIN Duty = 5062%(X100), DQS PI = 34
7270 00:26:05.962089 [0] AVG Duty = 5140%(X100)
7271 00:26:05.962199
7272 00:26:05.965614 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7273 00:26:05.965719
7274 00:26:05.969196 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7275 00:26:05.972493 [DutyScan_Calibration_Flow] ====Done====
7276 00:26:05.972596
7277 00:26:05.975200 [DutyScan_Calibration_Flow] k_type=3
7278 00:26:05.992213
7279 00:26:05.992345 ==DQM 0 ==
7280 00:26:05.995653 Final DQM duty delay cell = 0
7281 00:26:05.998961 [0] MAX Duty = 5218%(X100), DQS PI = 32
7282 00:26:06.002269 [0] MIN Duty = 4907%(X100), DQS PI = 56
7283 00:26:06.005761 [0] AVG Duty = 5062%(X100)
7284 00:26:06.005868
7285 00:26:06.005962 ==DQM 1 ==
7286 00:26:06.008635 Final DQM duty delay cell = -4
7287 00:26:06.012118 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7288 00:26:06.015767 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7289 00:26:06.019011 [-4] AVG Duty = 4906%(X100)
7290 00:26:06.019128
7291 00:26:06.022078 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7292 00:26:06.022181
7293 00:26:06.025415 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7294 00:26:06.028917 [DutyScan_Calibration_Flow] ====Done====
7295 00:26:06.029029
7296 00:26:06.032137 [DutyScan_Calibration_Flow] k_type=2
7297 00:26:06.049686
7298 00:26:06.049819 ==DQ 0 ==
7299 00:26:06.053197 Final DQ duty delay cell = 0
7300 00:26:06.056180 [0] MAX Duty = 5062%(X100), DQS PI = 26
7301 00:26:06.059722 [0] MIN Duty = 4907%(X100), DQS PI = 0
7302 00:26:06.059803 [0] AVG Duty = 4984%(X100)
7303 00:26:06.063017
7304 00:26:06.063117 ==DQ 1 ==
7305 00:26:06.066709 Final DQ duty delay cell = 0
7306 00:26:06.069902 [0] MAX Duty = 5125%(X100), DQS PI = 6
7307 00:26:06.073050 [0] MIN Duty = 4938%(X100), DQS PI = 34
7308 00:26:06.073155 [0] AVG Duty = 5031%(X100)
7309 00:26:06.073248
7310 00:26:06.076526 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7311 00:26:06.079618
7312 00:26:06.083158 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7313 00:26:06.086435 [DutyScan_Calibration_Flow] ====Done====
7314 00:26:06.086542 ==
7315 00:26:06.089709 Dram Type= 6, Freq= 0, CH_1, rank 0
7316 00:26:06.092676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7317 00:26:06.092784 ==
7318 00:26:06.096457 [Duty_Offset_Calibration]
7319 00:26:06.096563 B0:1 B1:0 CA:0
7320 00:26:06.096657
7321 00:26:06.099547 [DutyScan_Calibration_Flow] k_type=0
7322 00:26:06.109634
7323 00:26:06.109775 ==CLK 0==
7324 00:26:06.112571 Final CLK duty delay cell = -4
7325 00:26:06.115832 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7326 00:26:06.119216 [-4] MIN Duty = 4875%(X100), DQS PI = 2
7327 00:26:06.122482 [-4] AVG Duty = 4937%(X100)
7328 00:26:06.122588
7329 00:26:06.125783 CH1 CLK Duty spec in!! Max-Min= 125%
7330 00:26:06.129393 [DutyScan_Calibration_Flow] ====Done====
7331 00:26:06.129472
7332 00:26:06.132594 [DutyScan_Calibration_Flow] k_type=1
7333 00:26:06.148284
7334 00:26:06.148374 ==DQS 0 ==
7335 00:26:06.151695 Final DQS duty delay cell = 0
7336 00:26:06.155023 [0] MAX Duty = 5094%(X100), DQS PI = 22
7337 00:26:06.158637 [0] MIN Duty = 4844%(X100), DQS PI = 42
7338 00:26:06.158720 [0] AVG Duty = 4969%(X100)
7339 00:26:06.161762
7340 00:26:06.161842 ==DQS 1 ==
7341 00:26:06.165212 Final DQS duty delay cell = -4
7342 00:26:06.168375 [-4] MAX Duty = 4969%(X100), DQS PI = 16
7343 00:26:06.172301 [-4] MIN Duty = 4750%(X100), DQS PI = 8
7344 00:26:06.175261 [-4] AVG Duty = 4859%(X100)
7345 00:26:06.175339
7346 00:26:06.178382 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7347 00:26:06.178491
7348 00:26:06.181739 CH1 DQS 1 Duty spec in!! Max-Min= 219%
7349 00:26:06.185223 [DutyScan_Calibration_Flow] ====Done====
7350 00:26:06.185303
7351 00:26:06.188080 [DutyScan_Calibration_Flow] k_type=3
7352 00:26:06.205828
7353 00:26:06.205942 ==DQM 0 ==
7354 00:26:06.208638 Final DQM duty delay cell = 0
7355 00:26:06.212150 [0] MAX Duty = 5218%(X100), DQS PI = 18
7356 00:26:06.215563 [0] MIN Duty = 4969%(X100), DQS PI = 48
7357 00:26:06.219276 [0] AVG Duty = 5093%(X100)
7358 00:26:06.219383
7359 00:26:06.219491 ==DQM 1 ==
7360 00:26:06.221734 Final DQM duty delay cell = 0
7361 00:26:06.225394 [0] MAX Duty = 5124%(X100), DQS PI = 18
7362 00:26:06.228400 [0] MIN Duty = 4938%(X100), DQS PI = 32
7363 00:26:06.232057 [0] AVG Duty = 5031%(X100)
7364 00:26:06.232142
7365 00:26:06.235050 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7366 00:26:06.235136
7367 00:26:06.238651 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7368 00:26:06.241625 [DutyScan_Calibration_Flow] ====Done====
7369 00:26:06.241709
7370 00:26:06.245256 [DutyScan_Calibration_Flow] k_type=2
7371 00:26:06.262173
7372 00:26:06.262264 ==DQ 0 ==
7373 00:26:06.264987 Final DQ duty delay cell = -4
7374 00:26:06.268520 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7375 00:26:06.271937 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7376 00:26:06.274732 [-4] AVG Duty = 4968%(X100)
7377 00:26:06.274845
7378 00:26:06.274944 ==DQ 1 ==
7379 00:26:06.278312 Final DQ duty delay cell = 0
7380 00:26:06.282122 [0] MAX Duty = 5156%(X100), DQS PI = 18
7381 00:26:06.284676 [0] MIN Duty = 4938%(X100), DQS PI = 8
7382 00:26:06.284759 [0] AVG Duty = 5047%(X100)
7383 00:26:06.288242
7384 00:26:06.291607 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7385 00:26:06.291688
7386 00:26:06.294887 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7387 00:26:06.298248 [DutyScan_Calibration_Flow] ====Done====
7388 00:26:06.302081 nWR fixed to 30
7389 00:26:06.302188 [ModeRegInit_LP4] CH0 RK0
7390 00:26:06.304804 [ModeRegInit_LP4] CH0 RK1
7391 00:26:06.307989 [ModeRegInit_LP4] CH1 RK0
7392 00:26:06.311478 [ModeRegInit_LP4] CH1 RK1
7393 00:26:06.311583 match AC timing 5
7394 00:26:06.314849 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7395 00:26:06.321692 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7396 00:26:06.324680 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7397 00:26:06.331310 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7398 00:26:06.334784 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7399 00:26:06.334903 [MiockJmeterHQA]
7400 00:26:06.334998
7401 00:26:06.338125 [DramcMiockJmeter] u1RxGatingPI = 0
7402 00:26:06.341475 0 : 4255, 4027
7403 00:26:06.341584 4 : 4253, 4026
7404 00:26:06.344967 8 : 4253, 4027
7405 00:26:06.345073 12 : 4255, 4030
7406 00:26:06.345171 16 : 4363, 4137
7407 00:26:06.348099 20 : 4254, 4029
7408 00:26:06.348210 24 : 4252, 4027
7409 00:26:06.351403 28 : 4253, 4027
7410 00:26:06.351507 32 : 4253, 4026
7411 00:26:06.355105 36 : 4252, 4027
7412 00:26:06.355227 40 : 4253, 4026
7413 00:26:06.355330 44 : 4366, 4140
7414 00:26:06.358255 48 : 4253, 4026
7415 00:26:06.358359 52 : 4255, 4030
7416 00:26:06.361777 56 : 4252, 4027
7417 00:26:06.361881 60 : 4362, 4137
7418 00:26:06.364652 64 : 4252, 4027
7419 00:26:06.364727 68 : 4253, 4027
7420 00:26:06.368211 72 : 4253, 4029
7421 00:26:06.368343 76 : 4249, 4027
7422 00:26:06.368465 80 : 4250, 4027
7423 00:26:06.371659 84 : 4250, 4027
7424 00:26:06.371744 88 : 4250, 347
7425 00:26:06.374940 92 : 4361, 0
7426 00:26:06.375053 96 : 4363, 0
7427 00:26:06.375150 100 : 4252, 0
7428 00:26:06.378410 104 : 4250, 0
7429 00:26:06.378522 108 : 4253, 0
7430 00:26:06.381921 112 : 4250, 0
7431 00:26:06.382014 116 : 4250, 0
7432 00:26:06.382081 120 : 4250, 0
7433 00:26:06.384933 124 : 4254, 0
7434 00:26:06.385026 128 : 4250, 0
7435 00:26:06.385094 132 : 4250, 0
7436 00:26:06.388237 136 : 4250, 0
7437 00:26:06.388324 140 : 4360, 0
7438 00:26:06.391424 144 : 4250, 0
7439 00:26:06.391552 148 : 4250, 0
7440 00:26:06.391652 152 : 4249, 0
7441 00:26:06.395071 156 : 4250, 0
7442 00:26:06.395178 160 : 4250, 0
7443 00:26:06.398329 164 : 4250, 0
7444 00:26:06.398432 168 : 4252, 0
7445 00:26:06.398527 172 : 4250, 0
7446 00:26:06.401314 176 : 4250, 0
7447 00:26:06.401411 180 : 4250, 0
7448 00:26:06.405007 184 : 4250, 0
7449 00:26:06.405081 188 : 4250, 0
7450 00:26:06.405143 192 : 4360, 0
7451 00:26:06.408028 196 : 4250, 0
7452 00:26:06.408100 200 : 4360, 0
7453 00:26:06.411452 204 : 4255, 1325
7454 00:26:06.411552 208 : 4250, 4006
7455 00:26:06.414642 212 : 4255, 4032
7456 00:26:06.414741 216 : 4250, 4027
7457 00:26:06.414833 220 : 4360, 4138
7458 00:26:06.418245 224 : 4249, 4027
7459 00:26:06.418343 228 : 4250, 4026
7460 00:26:06.421692 232 : 4250, 4027
7461 00:26:06.421789 236 : 4250, 4027
7462 00:26:06.424496 240 : 4360, 4137
7463 00:26:06.424568 244 : 4250, 4026
7464 00:26:06.427831 248 : 4361, 4137
7465 00:26:06.427908 252 : 4250, 4027
7466 00:26:06.431387 256 : 4249, 4027
7467 00:26:06.431486 260 : 4250, 4026
7468 00:26:06.434351 264 : 4250, 4026
7469 00:26:06.434451 268 : 4255, 4029
7470 00:26:06.437613 272 : 4360, 4138
7471 00:26:06.437721 276 : 4250, 4027
7472 00:26:06.437820 280 : 4250, 4026
7473 00:26:06.441850 284 : 4249, 4027
7474 00:26:06.441959 288 : 4250, 4027
7475 00:26:06.444552 292 : 4360, 4137
7476 00:26:06.444661 296 : 4250, 4027
7477 00:26:06.447834 300 : 4361, 4137
7478 00:26:06.447916 304 : 4250, 4027
7479 00:26:06.451079 308 : 4250, 3960
7480 00:26:06.451186 312 : 4250, 2215
7481 00:26:06.454558 316 : 4250, 19
7482 00:26:06.454663
7483 00:26:06.454728 MIOCK jitter meter ch=0
7484 00:26:06.454789
7485 00:26:06.458273 1T = (316-88) = 228 dly cells
7486 00:26:06.464773 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7487 00:26:06.464881 ==
7488 00:26:06.468086 Dram Type= 6, Freq= 0, CH_0, rank 0
7489 00:26:06.471106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7490 00:26:06.471211 ==
7491 00:26:06.478028 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7492 00:26:06.481337 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7493 00:26:06.484771 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7494 00:26:06.491032 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7495 00:26:06.500347 [CA 0] Center 42 (12~73) winsize 62
7496 00:26:06.504147 [CA 1] Center 43 (12~74) winsize 63
7497 00:26:06.507155 [CA 2] Center 37 (8~67) winsize 60
7498 00:26:06.510905 [CA 3] Center 37 (7~67) winsize 61
7499 00:26:06.514003 [CA 4] Center 36 (6~66) winsize 61
7500 00:26:06.517377 [CA 5] Center 35 (6~64) winsize 59
7501 00:26:06.517467
7502 00:26:06.520512 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7503 00:26:06.520597
7504 00:26:06.524178 [CATrainingPosCal] consider 1 rank data
7505 00:26:06.527104 u2DelayCellTimex100 = 285/100 ps
7506 00:26:06.530416 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7507 00:26:06.537343 CA1 delay=43 (12~74),Diff = 8 PI (27 cell)
7508 00:26:06.540798 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7509 00:26:06.544400 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7510 00:26:06.547320 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7511 00:26:06.550591 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7512 00:26:06.550702
7513 00:26:06.553841 CA PerBit enable=1, Macro0, CA PI delay=35
7514 00:26:06.553943
7515 00:26:06.557356 [CBTSetCACLKResult] CA Dly = 35
7516 00:26:06.557433 CS Dly: 9 (0~40)
7517 00:26:06.564158 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7518 00:26:06.567527 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7519 00:26:06.567604 ==
7520 00:26:06.570613 Dram Type= 6, Freq= 0, CH_0, rank 1
7521 00:26:06.574133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7522 00:26:06.574237 ==
7523 00:26:06.580423 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7524 00:26:06.583958 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7525 00:26:06.590380 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7526 00:26:06.594041 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7527 00:26:06.604056 [CA 0] Center 42 (12~73) winsize 62
7528 00:26:06.607352 [CA 1] Center 42 (12~73) winsize 62
7529 00:26:06.610895 [CA 2] Center 38 (8~68) winsize 61
7530 00:26:06.614316 [CA 3] Center 37 (7~67) winsize 61
7531 00:26:06.617486 [CA 4] Center 36 (6~66) winsize 61
7532 00:26:06.620907 [CA 5] Center 34 (5~64) winsize 60
7533 00:26:06.621017
7534 00:26:06.624314 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7535 00:26:06.624420
7536 00:26:06.627424 [CATrainingPosCal] consider 2 rank data
7537 00:26:06.630899 u2DelayCellTimex100 = 285/100 ps
7538 00:26:06.633865 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7539 00:26:06.640784 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7540 00:26:06.643667 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7541 00:26:06.647070 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7542 00:26:06.650770 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7543 00:26:06.654112 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7544 00:26:06.654220
7545 00:26:06.657658 CA PerBit enable=1, Macro0, CA PI delay=35
7546 00:26:06.657759
7547 00:26:06.660680 [CBTSetCACLKResult] CA Dly = 35
7548 00:26:06.663966 CS Dly: 10 (0~42)
7549 00:26:06.666943 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7550 00:26:06.670361 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7551 00:26:06.670463
7552 00:26:06.674028 ----->DramcWriteLeveling(PI) begin...
7553 00:26:06.674128 ==
7554 00:26:06.677207 Dram Type= 6, Freq= 0, CH_0, rank 0
7555 00:26:06.680648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7556 00:26:06.683828 ==
7557 00:26:06.683903 Write leveling (Byte 0): 33 => 33
7558 00:26:06.687318 Write leveling (Byte 1): 28 => 28
7559 00:26:06.690652 DramcWriteLeveling(PI) end<-----
7560 00:26:06.690754
7561 00:26:06.690848 ==
7562 00:26:06.693999 Dram Type= 6, Freq= 0, CH_0, rank 0
7563 00:26:06.700394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7564 00:26:06.700502 ==
7565 00:26:06.700600 [Gating] SW mode calibration
7566 00:26:06.710155 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7567 00:26:06.713415 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7568 00:26:06.716872 1 4 0 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7569 00:26:06.723545 1 4 4 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7570 00:26:06.727490 1 4 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7571 00:26:06.730292 1 4 12 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
7572 00:26:06.737234 1 4 16 | B1->B0 | 2424 3636 | 0 0 | (0 0) (1 1)
7573 00:26:06.740245 1 4 20 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
7574 00:26:06.743458 1 4 24 | B1->B0 | 3434 3938 | 1 1 | (1 1) (0 0)
7575 00:26:06.750300 1 4 28 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7576 00:26:06.753845 1 5 0 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7577 00:26:06.757113 1 5 4 | B1->B0 | 3434 3838 | 1 0 | (1 1) (1 1)
7578 00:26:06.763427 1 5 8 | B1->B0 | 3434 3837 | 1 1 | (1 1) (0 0)
7579 00:26:06.766957 1 5 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 1)
7580 00:26:06.770258 1 5 16 | B1->B0 | 3333 2d2c | 1 1 | (1 1) (0 0)
7581 00:26:06.777022 1 5 20 | B1->B0 | 2626 2c2b | 0 1 | (0 1) (0 0)
7582 00:26:06.780493 1 5 24 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7583 00:26:06.783563 1 5 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
7584 00:26:06.790125 1 6 0 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7585 00:26:06.793166 1 6 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7586 00:26:06.796681 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7587 00:26:06.803660 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7588 00:26:06.806661 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7589 00:26:06.810033 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7590 00:26:06.816607 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 00:26:06.820141 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 00:26:06.823620 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7593 00:26:06.826833 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7594 00:26:06.833322 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7595 00:26:06.836481 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7596 00:26:06.839900 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7597 00:26:06.846837 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7598 00:26:06.849920 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 00:26:06.853396 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 00:26:06.860329 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 00:26:06.863676 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 00:26:06.866613 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 00:26:06.873530 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 00:26:06.876794 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 00:26:06.880251 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 00:26:06.886507 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 00:26:06.890110 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 00:26:06.893358 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 00:26:06.900183 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 00:26:06.903307 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7611 00:26:06.906608 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7612 00:26:06.913480 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7613 00:26:06.913591 Total UI for P1: 0, mck2ui 16
7614 00:26:06.919744 best dqsien dly found for B0: ( 1, 9, 10)
7615 00:26:06.923003 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7616 00:26:06.926832 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 00:26:06.929854 Total UI for P1: 0, mck2ui 16
7618 00:26:06.933379 best dqsien dly found for B1: ( 1, 9, 18)
7619 00:26:06.936616 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7620 00:26:06.939583 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7621 00:26:06.939657
7622 00:26:06.945975 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7623 00:26:06.949338 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7624 00:26:06.952936 [Gating] SW calibration Done
7625 00:26:06.953009 ==
7626 00:26:06.956401 Dram Type= 6, Freq= 0, CH_0, rank 0
7627 00:26:06.959302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7628 00:26:06.959398 ==
7629 00:26:06.959488 RX Vref Scan: 0
7630 00:26:06.959572
7631 00:26:06.962932 RX Vref 0 -> 0, step: 1
7632 00:26:06.963000
7633 00:26:06.966444 RX Delay 0 -> 252, step: 8
7634 00:26:06.969428 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7635 00:26:06.972768 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7636 00:26:06.976184 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7637 00:26:06.982702 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7638 00:26:06.985751 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7639 00:26:06.989236 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7640 00:26:06.992276 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7641 00:26:06.995611 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7642 00:26:07.002360 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7643 00:26:07.005856 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7644 00:26:07.008968 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7645 00:26:07.012478 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7646 00:26:07.015848 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7647 00:26:07.022439 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7648 00:26:07.025917 iDelay=200, Bit 14, Center 143 (96 ~ 191) 96
7649 00:26:07.029402 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7650 00:26:07.029507 ==
7651 00:26:07.032391 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 00:26:07.035639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 00:26:07.039237 ==
7654 00:26:07.039342 DQS Delay:
7655 00:26:07.039444 DQS0 = 0, DQS1 = 0
7656 00:26:07.042093 DQM Delay:
7657 00:26:07.042175 DQM0 = 137, DQM1 = 131
7658 00:26:07.045560 DQ Delay:
7659 00:26:07.048724 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7660 00:26:07.052437 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7661 00:26:07.055204 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7662 00:26:07.058624 DQ12 =135, DQ13 =139, DQ14 =143, DQ15 =135
7663 00:26:07.058729
7664 00:26:07.058814
7665 00:26:07.058904 ==
7666 00:26:07.062208 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 00:26:07.065587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 00:26:07.065662 ==
7669 00:26:07.065727
7670 00:26:07.068586
7671 00:26:07.068658 TX Vref Scan disable
7672 00:26:07.072195 == TX Byte 0 ==
7673 00:26:07.075552 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7674 00:26:07.078413 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7675 00:26:07.081778 == TX Byte 1 ==
7676 00:26:07.085460 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7677 00:26:07.088960 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7678 00:26:07.089066 ==
7679 00:26:07.092190 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 00:26:07.098656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 00:26:07.098760 ==
7682 00:26:07.110584
7683 00:26:07.114084 TX Vref early break, caculate TX vref
7684 00:26:07.117651 TX Vref=16, minBit 0, minWin=23, winSum=378
7685 00:26:07.120486 TX Vref=18, minBit 0, minWin=23, winSum=392
7686 00:26:07.124105 TX Vref=20, minBit 8, minWin=24, winSum=405
7687 00:26:07.127305 TX Vref=22, minBit 4, minWin=25, winSum=414
7688 00:26:07.130389 TX Vref=24, minBit 5, minWin=25, winSum=418
7689 00:26:07.137300 TX Vref=26, minBit 1, minWin=26, winSum=425
7690 00:26:07.140511 TX Vref=28, minBit 6, minWin=25, winSum=425
7691 00:26:07.144014 TX Vref=30, minBit 6, minWin=24, winSum=415
7692 00:26:07.147379 TX Vref=32, minBit 6, minWin=24, winSum=408
7693 00:26:07.150534 TX Vref=34, minBit 2, minWin=24, winSum=399
7694 00:26:07.157288 [TxChooseVref] Worse bit 1, Min win 26, Win sum 425, Final Vref 26
7695 00:26:07.157373
7696 00:26:07.160383 Final TX Range 0 Vref 26
7697 00:26:07.160485
7698 00:26:07.160575 ==
7699 00:26:07.163789 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 00:26:07.167405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 00:26:07.167530 ==
7702 00:26:07.167644
7703 00:26:07.167704
7704 00:26:07.170738 TX Vref Scan disable
7705 00:26:07.177096 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7706 00:26:07.177207 == TX Byte 0 ==
7707 00:26:07.180512 u2DelayCellOfst[0]=10 cells (3 PI)
7708 00:26:07.183877 u2DelayCellOfst[1]=13 cells (4 PI)
7709 00:26:07.187430 u2DelayCellOfst[2]=10 cells (3 PI)
7710 00:26:07.190622 u2DelayCellOfst[3]=10 cells (3 PI)
7711 00:26:07.194279 u2DelayCellOfst[4]=6 cells (2 PI)
7712 00:26:07.197232 u2DelayCellOfst[5]=0 cells (0 PI)
7713 00:26:07.197315 u2DelayCellOfst[6]=20 cells (6 PI)
7714 00:26:07.200473 u2DelayCellOfst[7]=17 cells (5 PI)
7715 00:26:07.207354 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7716 00:26:07.210489 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7717 00:26:07.210574 == TX Byte 1 ==
7718 00:26:07.213829 u2DelayCellOfst[8]=0 cells (0 PI)
7719 00:26:07.217457 u2DelayCellOfst[9]=0 cells (0 PI)
7720 00:26:07.220217 u2DelayCellOfst[10]=6 cells (2 PI)
7721 00:26:07.223713 u2DelayCellOfst[11]=6 cells (2 PI)
7722 00:26:07.227187 u2DelayCellOfst[12]=10 cells (3 PI)
7723 00:26:07.230532 u2DelayCellOfst[13]=13 cells (4 PI)
7724 00:26:07.233920 u2DelayCellOfst[14]=13 cells (4 PI)
7725 00:26:07.237230 u2DelayCellOfst[15]=10 cells (3 PI)
7726 00:26:07.240558 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7727 00:26:07.243794 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7728 00:26:07.247074 DramC Write-DBI on
7729 00:26:07.247157 ==
7730 00:26:07.250500 Dram Type= 6, Freq= 0, CH_0, rank 0
7731 00:26:07.253614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7732 00:26:07.253696 ==
7733 00:26:07.253760
7734 00:26:07.257000
7735 00:26:07.257081 TX Vref Scan disable
7736 00:26:07.260194 == TX Byte 0 ==
7737 00:26:07.263646 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7738 00:26:07.267105 == TX Byte 1 ==
7739 00:26:07.270227 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7740 00:26:07.270372 DramC Write-DBI off
7741 00:26:07.270472
7742 00:26:07.273478 [DATLAT]
7743 00:26:07.273575 Freq=1600, CH0 RK0
7744 00:26:07.273640
7745 00:26:07.277044 DATLAT Default: 0xf
7746 00:26:07.277128 0, 0xFFFF, sum = 0
7747 00:26:07.280518 1, 0xFFFF, sum = 0
7748 00:26:07.280614 2, 0xFFFF, sum = 0
7749 00:26:07.284044 3, 0xFFFF, sum = 0
7750 00:26:07.284126 4, 0xFFFF, sum = 0
7751 00:26:07.286894 5, 0xFFFF, sum = 0
7752 00:26:07.286977 6, 0xFFFF, sum = 0
7753 00:26:07.290177 7, 0xFFFF, sum = 0
7754 00:26:07.293939 8, 0xFFFF, sum = 0
7755 00:26:07.294021 9, 0xFFFF, sum = 0
7756 00:26:07.296939 10, 0xFFFF, sum = 0
7757 00:26:07.297022 11, 0xFFFF, sum = 0
7758 00:26:07.300265 12, 0xFFFF, sum = 0
7759 00:26:07.300347 13, 0xFFFF, sum = 0
7760 00:26:07.303701 14, 0x0, sum = 1
7761 00:26:07.303784 15, 0x0, sum = 2
7762 00:26:07.307036 16, 0x0, sum = 3
7763 00:26:07.307163 17, 0x0, sum = 4
7764 00:26:07.307230 best_step = 15
7765 00:26:07.310412
7766 00:26:07.310494 ==
7767 00:26:07.313908 Dram Type= 6, Freq= 0, CH_0, rank 0
7768 00:26:07.317115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7769 00:26:07.317198 ==
7770 00:26:07.317263 RX Vref Scan: 1
7771 00:26:07.317324
7772 00:26:07.320575 Set Vref Range= 24 -> 127
7773 00:26:07.320657
7774 00:26:07.323850 RX Vref 24 -> 127, step: 1
7775 00:26:07.323931
7776 00:26:07.326801 RX Delay 27 -> 252, step: 4
7777 00:26:07.326882
7778 00:26:07.330385 Set Vref, RX VrefLevel [Byte0]: 24
7779 00:26:07.333917 [Byte1]: 24
7780 00:26:07.333999
7781 00:26:07.337340 Set Vref, RX VrefLevel [Byte0]: 25
7782 00:26:07.340606 [Byte1]: 25
7783 00:26:07.340688
7784 00:26:07.343715 Set Vref, RX VrefLevel [Byte0]: 26
7785 00:26:07.347027 [Byte1]: 26
7786 00:26:07.350353
7787 00:26:07.350460 Set Vref, RX VrefLevel [Byte0]: 27
7788 00:26:07.353644 [Byte1]: 27
7789 00:26:07.357827
7790 00:26:07.357907 Set Vref, RX VrefLevel [Byte0]: 28
7791 00:26:07.361232 [Byte1]: 28
7792 00:26:07.365328
7793 00:26:07.365436 Set Vref, RX VrefLevel [Byte0]: 29
7794 00:26:07.368493 [Byte1]: 29
7795 00:26:07.373206
7796 00:26:07.373307 Set Vref, RX VrefLevel [Byte0]: 30
7797 00:26:07.376367 [Byte1]: 30
7798 00:26:07.380323
7799 00:26:07.380434 Set Vref, RX VrefLevel [Byte0]: 31
7800 00:26:07.383698 [Byte1]: 31
7801 00:26:07.388168
7802 00:26:07.388276 Set Vref, RX VrefLevel [Byte0]: 32
7803 00:26:07.391154 [Byte1]: 32
7804 00:26:07.395693
7805 00:26:07.395790 Set Vref, RX VrefLevel [Byte0]: 33
7806 00:26:07.398527 [Byte1]: 33
7807 00:26:07.403132
7808 00:26:07.403229 Set Vref, RX VrefLevel [Byte0]: 34
7809 00:26:07.406269 [Byte1]: 34
7810 00:26:07.410408
7811 00:26:07.410508 Set Vref, RX VrefLevel [Byte0]: 35
7812 00:26:07.414023 [Byte1]: 35
7813 00:26:07.417986
7814 00:26:07.418096 Set Vref, RX VrefLevel [Byte0]: 36
7815 00:26:07.421126 [Byte1]: 36
7816 00:26:07.425375
7817 00:26:07.425481 Set Vref, RX VrefLevel [Byte0]: 37
7818 00:26:07.428893 [Byte1]: 37
7819 00:26:07.433276
7820 00:26:07.433378 Set Vref, RX VrefLevel [Byte0]: 38
7821 00:26:07.436749 [Byte1]: 38
7822 00:26:07.441005
7823 00:26:07.441107 Set Vref, RX VrefLevel [Byte0]: 39
7824 00:26:07.444016 [Byte1]: 39
7825 00:26:07.448344
7826 00:26:07.448454 Set Vref, RX VrefLevel [Byte0]: 40
7827 00:26:07.451305 [Byte1]: 40
7828 00:26:07.455772
7829 00:26:07.455878 Set Vref, RX VrefLevel [Byte0]: 41
7830 00:26:07.459004 [Byte1]: 41
7831 00:26:07.463479
7832 00:26:07.463603 Set Vref, RX VrefLevel [Byte0]: 42
7833 00:26:07.466636 [Byte1]: 42
7834 00:26:07.471006
7835 00:26:07.471108 Set Vref, RX VrefLevel [Byte0]: 43
7836 00:26:07.474493 [Byte1]: 43
7837 00:26:07.478411
7838 00:26:07.478513 Set Vref, RX VrefLevel [Byte0]: 44
7839 00:26:07.481740 [Byte1]: 44
7840 00:26:07.485836
7841 00:26:07.485938 Set Vref, RX VrefLevel [Byte0]: 45
7842 00:26:07.489199 [Byte1]: 45
7843 00:26:07.493718
7844 00:26:07.493818 Set Vref, RX VrefLevel [Byte0]: 46
7845 00:26:07.496895 [Byte1]: 46
7846 00:26:07.501152
7847 00:26:07.501253 Set Vref, RX VrefLevel [Byte0]: 47
7848 00:26:07.504331 [Byte1]: 47
7849 00:26:07.508566
7850 00:26:07.508682 Set Vref, RX VrefLevel [Byte0]: 48
7851 00:26:07.512032 [Byte1]: 48
7852 00:26:07.516017
7853 00:26:07.516088 Set Vref, RX VrefLevel [Byte0]: 49
7854 00:26:07.519534 [Byte1]: 49
7855 00:26:07.523481
7856 00:26:07.523584 Set Vref, RX VrefLevel [Byte0]: 50
7857 00:26:07.526871 [Byte1]: 50
7858 00:26:07.530933
7859 00:26:07.531025 Set Vref, RX VrefLevel [Byte0]: 51
7860 00:26:07.534147 [Byte1]: 51
7861 00:26:07.538792
7862 00:26:07.538866 Set Vref, RX VrefLevel [Byte0]: 52
7863 00:26:07.542106 [Byte1]: 52
7864 00:26:07.546353
7865 00:26:07.546457 Set Vref, RX VrefLevel [Byte0]: 53
7866 00:26:07.549825 [Byte1]: 53
7867 00:26:07.553585
7868 00:26:07.553658 Set Vref, RX VrefLevel [Byte0]: 54
7869 00:26:07.557096 [Byte1]: 54
7870 00:26:07.561391
7871 00:26:07.561507 Set Vref, RX VrefLevel [Byte0]: 55
7872 00:26:07.564398 [Byte1]: 55
7873 00:26:07.568596
7874 00:26:07.568680 Set Vref, RX VrefLevel [Byte0]: 56
7875 00:26:07.572108 [Byte1]: 56
7876 00:26:07.576132
7877 00:26:07.576218 Set Vref, RX VrefLevel [Byte0]: 57
7878 00:26:07.579872 [Byte1]: 57
7879 00:26:07.583986
7880 00:26:07.584067 Set Vref, RX VrefLevel [Byte0]: 58
7881 00:26:07.586842 [Byte1]: 58
7882 00:26:07.591225
7883 00:26:07.591306 Set Vref, RX VrefLevel [Byte0]: 59
7884 00:26:07.594600 [Byte1]: 59
7885 00:26:07.598951
7886 00:26:07.599030 Set Vref, RX VrefLevel [Byte0]: 60
7887 00:26:07.602452 [Byte1]: 60
7888 00:26:07.606410
7889 00:26:07.606529 Set Vref, RX VrefLevel [Byte0]: 61
7890 00:26:07.609961 [Byte1]: 61
7891 00:26:07.614022
7892 00:26:07.614122 Set Vref, RX VrefLevel [Byte0]: 62
7893 00:26:07.617173 [Byte1]: 62
7894 00:26:07.621768
7895 00:26:07.621871 Set Vref, RX VrefLevel [Byte0]: 63
7896 00:26:07.624632 [Byte1]: 63
7897 00:26:07.629050
7898 00:26:07.629125 Set Vref, RX VrefLevel [Byte0]: 64
7899 00:26:07.632405 [Byte1]: 64
7900 00:26:07.636286
7901 00:26:07.636360 Set Vref, RX VrefLevel [Byte0]: 65
7902 00:26:07.639777 [Byte1]: 65
7903 00:26:07.644190
7904 00:26:07.644269 Set Vref, RX VrefLevel [Byte0]: 66
7905 00:26:07.647776 [Byte1]: 66
7906 00:26:07.651780
7907 00:26:07.651854 Set Vref, RX VrefLevel [Byte0]: 67
7908 00:26:07.655269 [Byte1]: 67
7909 00:26:07.659357
7910 00:26:07.659457 Set Vref, RX VrefLevel [Byte0]: 68
7911 00:26:07.662196 [Byte1]: 68
7912 00:26:07.666834
7913 00:26:07.666908 Set Vref, RX VrefLevel [Byte0]: 69
7914 00:26:07.669954 [Byte1]: 69
7915 00:26:07.674127
7916 00:26:07.674229 Set Vref, RX VrefLevel [Byte0]: 70
7917 00:26:07.677728 [Byte1]: 70
7918 00:26:07.681965
7919 00:26:07.682073 Set Vref, RX VrefLevel [Byte0]: 71
7920 00:26:07.685047 [Byte1]: 71
7921 00:26:07.689108
7922 00:26:07.689210 Set Vref, RX VrefLevel [Byte0]: 72
7923 00:26:07.692565 [Byte1]: 72
7924 00:26:07.696593
7925 00:26:07.696693 Set Vref, RX VrefLevel [Byte0]: 73
7926 00:26:07.699847 [Byte1]: 73
7927 00:26:07.704095
7928 00:26:07.704195 Set Vref, RX VrefLevel [Byte0]: 74
7929 00:26:07.707373 [Byte1]: 74
7930 00:26:07.711932
7931 00:26:07.712009 Final RX Vref Byte 0 = 57 to rank0
7932 00:26:07.715206 Final RX Vref Byte 1 = 63 to rank0
7933 00:26:07.718768 Final RX Vref Byte 0 = 57 to rank1
7934 00:26:07.721912 Final RX Vref Byte 1 = 63 to rank1==
7935 00:26:07.725271 Dram Type= 6, Freq= 0, CH_0, rank 0
7936 00:26:07.731919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7937 00:26:07.732005 ==
7938 00:26:07.732092 DQS Delay:
7939 00:26:07.732174 DQS0 = 0, DQS1 = 0
7940 00:26:07.735172 DQM Delay:
7941 00:26:07.735284 DQM0 = 133, DQM1 = 127
7942 00:26:07.738581 DQ Delay:
7943 00:26:07.741941 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7944 00:26:07.744896 DQ4 =132, DQ5 =124, DQ6 =138, DQ7 =138
7945 00:26:07.748326 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7946 00:26:07.751453 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7947 00:26:07.751572
7948 00:26:07.751637
7949 00:26:07.751697
7950 00:26:07.755018 [DramC_TX_OE_Calibration] TA2
7951 00:26:07.758526 Original DQ_B0 (3 6) =30, OEN = 27
7952 00:26:07.761483 Original DQ_B1 (3 6) =30, OEN = 27
7953 00:26:07.765096 24, 0x0, End_B0=24 End_B1=24
7954 00:26:07.765179 25, 0x0, End_B0=25 End_B1=25
7955 00:26:07.768613 26, 0x0, End_B0=26 End_B1=26
7956 00:26:07.771925 27, 0x0, End_B0=27 End_B1=27
7957 00:26:07.774745 28, 0x0, End_B0=28 End_B1=28
7958 00:26:07.778245 29, 0x0, End_B0=29 End_B1=29
7959 00:26:07.778334 30, 0x0, End_B0=30 End_B1=30
7960 00:26:07.781288 31, 0x4141, End_B0=30 End_B1=30
7961 00:26:07.784817 Byte0 end_step=30 best_step=27
7962 00:26:07.788282 Byte1 end_step=30 best_step=27
7963 00:26:07.791645 Byte0 TX OE(2T, 0.5T) = (3, 3)
7964 00:26:07.795164 Byte1 TX OE(2T, 0.5T) = (3, 3)
7965 00:26:07.795264
7966 00:26:07.795375
7967 00:26:07.801519 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7968 00:26:07.804761 CH0 RK0: MR19=303, MR18=2723
7969 00:26:07.811943 CH0_RK0: MR19=0x303, MR18=0x2723, DQSOSC=390, MR23=63, INC=24, DEC=16
7970 00:26:07.812049
7971 00:26:07.814599 ----->DramcWriteLeveling(PI) begin...
7972 00:26:07.814690 ==
7973 00:26:07.818176 Dram Type= 6, Freq= 0, CH_0, rank 1
7974 00:26:07.821732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7975 00:26:07.821836 ==
7976 00:26:07.824847 Write leveling (Byte 0): 34 => 34
7977 00:26:07.828193 Write leveling (Byte 1): 28 => 28
7978 00:26:07.831614 DramcWriteLeveling(PI) end<-----
7979 00:26:07.831689
7980 00:26:07.831751 ==
7981 00:26:07.834864 Dram Type= 6, Freq= 0, CH_0, rank 1
7982 00:26:07.838088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7983 00:26:07.838165 ==
7984 00:26:07.841375 [Gating] SW mode calibration
7985 00:26:07.848316 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7986 00:26:07.854680 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7987 00:26:07.857988 1 4 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7988 00:26:07.861275 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7989 00:26:07.868216 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7990 00:26:07.871231 1 4 12 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7991 00:26:07.874559 1 4 16 | B1->B0 | 3030 3635 | 0 1 | (0 0) (0 0)
7992 00:26:07.881645 1 4 20 | B1->B0 | 3434 3c3b | 1 1 | (1 1) (1 1)
7993 00:26:07.884699 1 4 24 | B1->B0 | 3434 3c3b | 1 1 | (1 1) (0 0)
7994 00:26:07.887844 1 4 28 | B1->B0 | 3434 3737 | 1 1 | (1 1) (0 0)
7995 00:26:07.894821 1 5 0 | B1->B0 | 3434 3938 | 1 1 | (1 1) (1 1)
7996 00:26:07.898246 1 5 4 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0)
7997 00:26:07.901316 1 5 8 | B1->B0 | 3434 3a39 | 1 1 | (1 1) (1 1)
7998 00:26:07.907763 1 5 12 | B1->B0 | 3434 3636 | 1 1 | (1 0) (0 1)
7999 00:26:07.911290 1 5 16 | B1->B0 | 2b2b 2f2e | 0 1 | (0 1) (1 0)
8000 00:26:07.914555 1 5 20 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
8001 00:26:07.920903 1 5 24 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
8002 00:26:07.924589 1 5 28 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
8003 00:26:07.928017 1 6 0 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
8004 00:26:07.934127 1 6 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8005 00:26:07.937720 1 6 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
8006 00:26:07.940887 1 6 12 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
8007 00:26:07.947902 1 6 16 | B1->B0 | 3f3f 4645 | 0 1 | (0 0) (1 1)
8008 00:26:07.951367 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8009 00:26:07.954585 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8010 00:26:07.957679 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 00:26:07.964493 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 00:26:07.967918 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 00:26:07.970896 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 00:26:07.978035 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 00:26:07.981418 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8016 00:26:07.984313 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 00:26:07.991071 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 00:26:07.994354 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 00:26:07.997598 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 00:26:08.004486 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 00:26:08.007444 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 00:26:08.011213 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 00:26:08.017752 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 00:26:08.020860 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 00:26:08.024085 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 00:26:08.030714 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 00:26:08.034262 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 00:26:08.037767 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 00:26:08.044031 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 00:26:08.047389 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8031 00:26:08.050882 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8032 00:26:08.057280 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 00:26:08.057358 Total UI for P1: 0, mck2ui 16
8034 00:26:08.063891 best dqsien dly found for B0: ( 1, 9, 14)
8035 00:26:08.063994 Total UI for P1: 0, mck2ui 16
8036 00:26:08.067602 best dqsien dly found for B1: ( 1, 9, 16)
8037 00:26:08.074085 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8038 00:26:08.077189 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8039 00:26:08.077292
8040 00:26:08.080866 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8041 00:26:08.083773 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8042 00:26:08.087605 [Gating] SW calibration Done
8043 00:26:08.087675 ==
8044 00:26:08.090650 Dram Type= 6, Freq= 0, CH_0, rank 1
8045 00:26:08.093974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8046 00:26:08.094069 ==
8047 00:26:08.097735 RX Vref Scan: 0
8048 00:26:08.097834
8049 00:26:08.097926 RX Vref 0 -> 0, step: 1
8050 00:26:08.098014
8051 00:26:08.100561 RX Delay 0 -> 252, step: 8
8052 00:26:08.104116 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8053 00:26:08.110523 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8054 00:26:08.114086 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8055 00:26:08.117547 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8056 00:26:08.120785 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8057 00:26:08.124097 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8058 00:26:08.127171 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8059 00:26:08.134067 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8060 00:26:08.137065 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8061 00:26:08.140779 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8062 00:26:08.143973 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8063 00:26:08.150200 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8064 00:26:08.153754 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8065 00:26:08.157502 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8066 00:26:08.160690 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8067 00:26:08.164034 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8068 00:26:08.164134 ==
8069 00:26:08.167255 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 00:26:08.173719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 00:26:08.173848 ==
8072 00:26:08.173986 DQS Delay:
8073 00:26:08.177139 DQS0 = 0, DQS1 = 0
8074 00:26:08.177257 DQM Delay:
8075 00:26:08.180553 DQM0 = 137, DQM1 = 130
8076 00:26:08.180656 DQ Delay:
8077 00:26:08.183978 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8078 00:26:08.187004 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8079 00:26:08.190489 DQ8 =123, DQ9 =119, DQ10 =131, DQ11 =119
8080 00:26:08.194016 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8081 00:26:08.194113
8082 00:26:08.194204
8083 00:26:08.194291 ==
8084 00:26:08.196934 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 00:26:08.203987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 00:26:08.204121 ==
8087 00:26:08.204215
8088 00:26:08.204302
8089 00:26:08.204386 TX Vref Scan disable
8090 00:26:08.206912 == TX Byte 0 ==
8091 00:26:08.210035 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8092 00:26:08.217002 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8093 00:26:08.217104 == TX Byte 1 ==
8094 00:26:08.220339 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8095 00:26:08.226945 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8096 00:26:08.227021 ==
8097 00:26:08.230145 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 00:26:08.233349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 00:26:08.233425 ==
8100 00:26:08.247652
8101 00:26:08.251131 TX Vref early break, caculate TX vref
8102 00:26:08.254654 TX Vref=16, minBit 1, minWin=22, winSum=387
8103 00:26:08.257775 TX Vref=18, minBit 1, minWin=23, winSum=397
8104 00:26:08.260758 TX Vref=20, minBit 1, minWin=23, winSum=407
8105 00:26:08.264114 TX Vref=22, minBit 1, minWin=24, winSum=412
8106 00:26:08.267451 TX Vref=24, minBit 7, minWin=24, winSum=420
8107 00:26:08.274240 TX Vref=26, minBit 0, minWin=25, winSum=424
8108 00:26:08.277648 TX Vref=28, minBit 3, minWin=25, winSum=423
8109 00:26:08.280954 TX Vref=30, minBit 0, minWin=25, winSum=415
8110 00:26:08.284400 TX Vref=32, minBit 0, minWin=25, winSum=412
8111 00:26:08.288033 TX Vref=34, minBit 6, minWin=24, winSum=403
8112 00:26:08.290697 TX Vref=36, minBit 0, minWin=23, winSum=388
8113 00:26:08.297549 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 26
8114 00:26:08.297655
8115 00:26:08.300931 Final TX Range 0 Vref 26
8116 00:26:08.301033
8117 00:26:08.301124 ==
8118 00:26:08.304415 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 00:26:08.307431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 00:26:08.307554 ==
8121 00:26:08.307727
8122 00:26:08.307815
8123 00:26:08.310898 TX Vref Scan disable
8124 00:26:08.317846 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8125 00:26:08.317943 == TX Byte 0 ==
8126 00:26:08.321042 u2DelayCellOfst[0]=13 cells (4 PI)
8127 00:26:08.323954 u2DelayCellOfst[1]=17 cells (5 PI)
8128 00:26:08.327461 u2DelayCellOfst[2]=10 cells (3 PI)
8129 00:26:08.330523 u2DelayCellOfst[3]=6 cells (2 PI)
8130 00:26:08.334007 u2DelayCellOfst[4]=6 cells (2 PI)
8131 00:26:08.337485 u2DelayCellOfst[5]=0 cells (0 PI)
8132 00:26:08.340963 u2DelayCellOfst[6]=17 cells (5 PI)
8133 00:26:08.343674 u2DelayCellOfst[7]=13 cells (4 PI)
8134 00:26:08.347409 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8135 00:26:08.350441 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8136 00:26:08.354080 == TX Byte 1 ==
8137 00:26:08.357276 u2DelayCellOfst[8]=3 cells (1 PI)
8138 00:26:08.360670 u2DelayCellOfst[9]=0 cells (0 PI)
8139 00:26:08.360772 u2DelayCellOfst[10]=6 cells (2 PI)
8140 00:26:08.363793 u2DelayCellOfst[11]=3 cells (1 PI)
8141 00:26:08.367194 u2DelayCellOfst[12]=13 cells (4 PI)
8142 00:26:08.370336 u2DelayCellOfst[13]=10 cells (3 PI)
8143 00:26:08.373703 u2DelayCellOfst[14]=13 cells (4 PI)
8144 00:26:08.376836 u2DelayCellOfst[15]=10 cells (3 PI)
8145 00:26:08.380667 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8146 00:26:08.387480 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8147 00:26:08.387592 DramC Write-DBI on
8148 00:26:08.387660 ==
8149 00:26:08.390903 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 00:26:08.397190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 00:26:08.397267 ==
8152 00:26:08.397330
8153 00:26:08.397392
8154 00:26:08.397457 TX Vref Scan disable
8155 00:26:08.401171 == TX Byte 0 ==
8156 00:26:08.404561 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8157 00:26:08.407946 == TX Byte 1 ==
8158 00:26:08.410850 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8159 00:26:08.410951 DramC Write-DBI off
8160 00:26:08.414318
8161 00:26:08.414420 [DATLAT]
8162 00:26:08.414509 Freq=1600, CH0 RK1
8163 00:26:08.414588
8164 00:26:08.417772 DATLAT Default: 0xf
8165 00:26:08.417868 0, 0xFFFF, sum = 0
8166 00:26:08.421354 1, 0xFFFF, sum = 0
8167 00:26:08.421453 2, 0xFFFF, sum = 0
8168 00:26:08.424245 3, 0xFFFF, sum = 0
8169 00:26:08.427704 4, 0xFFFF, sum = 0
8170 00:26:08.427788 5, 0xFFFF, sum = 0
8171 00:26:08.431200 6, 0xFFFF, sum = 0
8172 00:26:08.431296 7, 0xFFFF, sum = 0
8173 00:26:08.434638 8, 0xFFFF, sum = 0
8174 00:26:08.434711 9, 0xFFFF, sum = 0
8175 00:26:08.437515 10, 0xFFFF, sum = 0
8176 00:26:08.437616 11, 0xFFFF, sum = 0
8177 00:26:08.440776 12, 0xFFFF, sum = 0
8178 00:26:08.440860 13, 0xFFFF, sum = 0
8179 00:26:08.444198 14, 0x0, sum = 1
8180 00:26:08.444282 15, 0x0, sum = 2
8181 00:26:08.447407 16, 0x0, sum = 3
8182 00:26:08.447539 17, 0x0, sum = 4
8183 00:26:08.450682 best_step = 15
8184 00:26:08.450763
8185 00:26:08.450854 ==
8186 00:26:08.454449 Dram Type= 6, Freq= 0, CH_0, rank 1
8187 00:26:08.457402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8188 00:26:08.457485 ==
8189 00:26:08.457551 RX Vref Scan: 0
8190 00:26:08.460772
8191 00:26:08.460853 RX Vref 0 -> 0, step: 1
8192 00:26:08.460919
8193 00:26:08.464082 RX Delay 19 -> 252, step: 4
8194 00:26:08.467423 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8195 00:26:08.474282 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8196 00:26:08.477765 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8197 00:26:08.480832 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8198 00:26:08.484093 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8199 00:26:08.487788 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8200 00:26:08.493971 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8201 00:26:08.497425 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8202 00:26:08.500956 iDelay=191, Bit 8, Center 120 (71 ~ 170) 100
8203 00:26:08.503859 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8204 00:26:08.507403 iDelay=191, Bit 10, Center 130 (79 ~ 182) 104
8205 00:26:08.513985 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8206 00:26:08.517597 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8207 00:26:08.520503 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8208 00:26:08.524483 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8209 00:26:08.527231 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8210 00:26:08.530774 ==
8211 00:26:08.530870 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 00:26:08.537487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 00:26:08.537559 ==
8214 00:26:08.537621 DQS Delay:
8215 00:26:08.540600 DQS0 = 0, DQS1 = 0
8216 00:26:08.540693 DQM Delay:
8217 00:26:08.544075 DQM0 = 134, DQM1 = 127
8218 00:26:08.544146 DQ Delay:
8219 00:26:08.547366 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8220 00:26:08.550814 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8221 00:26:08.553932 DQ8 =120, DQ9 =116, DQ10 =130, DQ11 =118
8222 00:26:08.556955 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =136
8223 00:26:08.557052
8224 00:26:08.557140
8225 00:26:08.557236
8226 00:26:08.560533 [DramC_TX_OE_Calibration] TA2
8227 00:26:08.563871 Original DQ_B0 (3 6) =30, OEN = 27
8228 00:26:08.567160 Original DQ_B1 (3 6) =30, OEN = 27
8229 00:26:08.570834 24, 0x0, End_B0=24 End_B1=24
8230 00:26:08.573744 25, 0x0, End_B0=25 End_B1=25
8231 00:26:08.573850 26, 0x0, End_B0=26 End_B1=26
8232 00:26:08.577254 27, 0x0, End_B0=27 End_B1=27
8233 00:26:08.580422 28, 0x0, End_B0=28 End_B1=28
8234 00:26:08.583840 29, 0x0, End_B0=29 End_B1=29
8235 00:26:08.583924 30, 0x0, End_B0=30 End_B1=30
8236 00:26:08.587408 31, 0x4545, End_B0=30 End_B1=30
8237 00:26:08.590716 Byte0 end_step=30 best_step=27
8238 00:26:08.594329 Byte1 end_step=30 best_step=27
8239 00:26:08.597353 Byte0 TX OE(2T, 0.5T) = (3, 3)
8240 00:26:08.600419 Byte1 TX OE(2T, 0.5T) = (3, 3)
8241 00:26:08.600503
8242 00:26:08.600569
8243 00:26:08.606862 [DQSOSCAuto] RK1, (LSB)MR18= 0x230c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
8244 00:26:08.610372 CH0 RK1: MR19=303, MR18=230C
8245 00:26:08.617081 CH0_RK1: MR19=0x303, MR18=0x230C, DQSOSC=392, MR23=63, INC=24, DEC=16
8246 00:26:08.620400 [RxdqsGatingPostProcess] freq 1600
8247 00:26:08.624109 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8248 00:26:08.626978 best DQS0 dly(2T, 0.5T) = (1, 1)
8249 00:26:08.630261 best DQS1 dly(2T, 0.5T) = (1, 1)
8250 00:26:08.633671 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8251 00:26:08.636960 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8252 00:26:08.640596 best DQS0 dly(2T, 0.5T) = (1, 1)
8253 00:26:08.644032 best DQS1 dly(2T, 0.5T) = (1, 1)
8254 00:26:08.647014 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8255 00:26:08.650365 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8256 00:26:08.653882 Pre-setting of DQS Precalculation
8257 00:26:08.657370 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8258 00:26:08.657462 ==
8259 00:26:08.660706 Dram Type= 6, Freq= 0, CH_1, rank 0
8260 00:26:08.663896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8261 00:26:08.667214 ==
8262 00:26:08.670596 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8263 00:26:08.673651 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8264 00:26:08.680577 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8265 00:26:08.686865 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8266 00:26:08.694105 [CA 0] Center 42 (12~72) winsize 61
8267 00:26:08.697619 [CA 1] Center 42 (12~72) winsize 61
8268 00:26:08.700744 [CA 2] Center 39 (10~69) winsize 60
8269 00:26:08.704002 [CA 3] Center 38 (9~67) winsize 59
8270 00:26:08.707314 [CA 4] Center 38 (9~68) winsize 60
8271 00:26:08.710854 [CA 5] Center 37 (7~67) winsize 61
8272 00:26:08.710932
8273 00:26:08.714183 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8274 00:26:08.714257
8275 00:26:08.717205 [CATrainingPosCal] consider 1 rank data
8276 00:26:08.720668 u2DelayCellTimex100 = 285/100 ps
8277 00:26:08.724084 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8278 00:26:08.730490 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8279 00:26:08.734070 CA2 delay=39 (10~69),Diff = 2 PI (6 cell)
8280 00:26:08.737500 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8281 00:26:08.740900 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8282 00:26:08.748402 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8283 00:26:08.748519
8284 00:26:08.748616 CA PerBit enable=1, Macro0, CA PI delay=37
8285 00:26:08.748743
8286 00:26:08.750366 [CBTSetCACLKResult] CA Dly = 37
8287 00:26:08.753809 CS Dly: 10 (0~41)
8288 00:26:08.757230 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8289 00:26:08.760368 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8290 00:26:08.760471 ==
8291 00:26:08.763980 Dram Type= 6, Freq= 0, CH_1, rank 1
8292 00:26:08.767398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 00:26:08.770586 ==
8294 00:26:08.773760 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8295 00:26:08.777018 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8296 00:26:08.783972 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8297 00:26:08.787353 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8298 00:26:08.797392 [CA 0] Center 42 (13~72) winsize 60
8299 00:26:08.800847 [CA 1] Center 42 (13~72) winsize 60
8300 00:26:08.804233 [CA 2] Center 39 (9~69) winsize 61
8301 00:26:08.807129 [CA 3] Center 38 (9~68) winsize 60
8302 00:26:08.810364 [CA 4] Center 39 (9~69) winsize 61
8303 00:26:08.813853 [CA 5] Center 37 (8~67) winsize 60
8304 00:26:08.813929
8305 00:26:08.817314 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8306 00:26:08.817389
8307 00:26:08.820578 [CATrainingPosCal] consider 2 rank data
8308 00:26:08.823615 u2DelayCellTimex100 = 285/100 ps
8309 00:26:08.827513 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8310 00:26:08.834149 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8311 00:26:08.837579 CA2 delay=39 (10~69),Diff = 2 PI (6 cell)
8312 00:26:08.840407 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8313 00:26:08.843935 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8314 00:26:08.847291 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8315 00:26:08.847405
8316 00:26:08.850387 CA PerBit enable=1, Macro0, CA PI delay=37
8317 00:26:08.850469
8318 00:26:08.853947 [CBTSetCACLKResult] CA Dly = 37
8319 00:26:08.857394 CS Dly: 11 (0~44)
8320 00:26:08.860483 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8321 00:26:08.863624 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8322 00:26:08.863706
8323 00:26:08.867017 ----->DramcWriteLeveling(PI) begin...
8324 00:26:08.867100 ==
8325 00:26:08.870562 Dram Type= 6, Freq= 0, CH_1, rank 0
8326 00:26:08.876745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8327 00:26:08.876828 ==
8328 00:26:08.880446 Write leveling (Byte 0): 26 => 26
8329 00:26:08.880528 Write leveling (Byte 1): 26 => 26
8330 00:26:08.883368 DramcWriteLeveling(PI) end<-----
8331 00:26:08.883478
8332 00:26:08.883576 ==
8333 00:26:08.886858 Dram Type= 6, Freq= 0, CH_1, rank 0
8334 00:26:08.893935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 00:26:08.894017 ==
8336 00:26:08.896877 [Gating] SW mode calibration
8337 00:26:08.903788 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8338 00:26:08.907297 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8339 00:26:08.913662 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 00:26:08.917025 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 00:26:08.920408 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8342 00:26:08.927531 1 4 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
8343 00:26:08.930071 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8344 00:26:08.933787 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 00:26:08.940395 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 00:26:08.943695 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 00:26:08.947077 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 00:26:08.950244 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 00:26:08.957137 1 5 8 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 1)
8350 00:26:08.960252 1 5 12 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (1 0)
8351 00:26:08.963740 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 00:26:08.970120 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 00:26:08.973538 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 00:26:08.977122 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 00:26:08.983847 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 00:26:08.986743 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 00:26:08.990344 1 6 8 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8358 00:26:08.996842 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8359 00:26:09.000271 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 00:26:09.003589 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 00:26:09.010071 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 00:26:09.013491 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 00:26:09.016368 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 00:26:09.023152 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 00:26:09.026713 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8366 00:26:09.030053 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8367 00:26:09.036427 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8368 00:26:09.039686 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 00:26:09.042873 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 00:26:09.049679 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 00:26:09.053228 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 00:26:09.056112 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 00:26:09.063190 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 00:26:09.066388 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 00:26:09.069460 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 00:26:09.076110 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 00:26:09.079588 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 00:26:09.083190 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 00:26:09.090056 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 00:26:09.092895 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 00:26:09.095963 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8382 00:26:09.099471 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8383 00:26:09.105908 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 00:26:09.109507 Total UI for P1: 0, mck2ui 16
8385 00:26:09.112848 best dqsien dly found for B0: ( 1, 9, 10)
8386 00:26:09.115895 Total UI for P1: 0, mck2ui 16
8387 00:26:09.119142 best dqsien dly found for B1: ( 1, 9, 10)
8388 00:26:09.122723 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8389 00:26:09.126367 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8390 00:26:09.126451
8391 00:26:09.129086 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8392 00:26:09.132820 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8393 00:26:09.135964 [Gating] SW calibration Done
8394 00:26:09.136041 ==
8395 00:26:09.139622 Dram Type= 6, Freq= 0, CH_1, rank 0
8396 00:26:09.142358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8397 00:26:09.142440 ==
8398 00:26:09.145935 RX Vref Scan: 0
8399 00:26:09.146044
8400 00:26:09.149100 RX Vref 0 -> 0, step: 1
8401 00:26:09.149171
8402 00:26:09.149256 RX Delay 0 -> 252, step: 8
8403 00:26:09.155933 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8404 00:26:09.159088 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8405 00:26:09.162412 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8406 00:26:09.165947 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8407 00:26:09.169572 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8408 00:26:09.175662 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8409 00:26:09.179113 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8410 00:26:09.182519 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8411 00:26:09.186038 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8412 00:26:09.189132 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8413 00:26:09.195931 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8414 00:26:09.199243 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8415 00:26:09.202615 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8416 00:26:09.206115 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8417 00:26:09.209376 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8418 00:26:09.215727 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8419 00:26:09.215813 ==
8420 00:26:09.219181 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 00:26:09.222181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 00:26:09.222284 ==
8423 00:26:09.222375 DQS Delay:
8424 00:26:09.225586 DQS0 = 0, DQS1 = 0
8425 00:26:09.225691 DQM Delay:
8426 00:26:09.228988 DQM0 = 136, DQM1 = 132
8427 00:26:09.229087 DQ Delay:
8428 00:26:09.232414 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8429 00:26:09.235935 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8430 00:26:09.238692 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8431 00:26:09.242488 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8432 00:26:09.242590
8433 00:26:09.242654
8434 00:26:09.245629 ==
8435 00:26:09.249110 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 00:26:09.252362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 00:26:09.252470 ==
8438 00:26:09.252569
8439 00:26:09.252666
8440 00:26:09.255646 TX Vref Scan disable
8441 00:26:09.255719 == TX Byte 0 ==
8442 00:26:09.258990 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8443 00:26:09.265633 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8444 00:26:09.265747 == TX Byte 1 ==
8445 00:26:09.268523 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8446 00:26:09.275536 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8447 00:26:09.275618 ==
8448 00:26:09.278477 Dram Type= 6, Freq= 0, CH_1, rank 0
8449 00:26:09.281948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8450 00:26:09.282060 ==
8451 00:26:09.294981
8452 00:26:09.298451 TX Vref early break, caculate TX vref
8453 00:26:09.301215 TX Vref=16, minBit 1, minWin=23, winSum=377
8454 00:26:09.305058 TX Vref=18, minBit 6, minWin=23, winSum=390
8455 00:26:09.308125 TX Vref=20, minBit 0, minWin=23, winSum=394
8456 00:26:09.311525 TX Vref=22, minBit 0, minWin=24, winSum=407
8457 00:26:09.315018 TX Vref=24, minBit 1, minWin=24, winSum=415
8458 00:26:09.321235 TX Vref=26, minBit 0, minWin=25, winSum=425
8459 00:26:09.324685 TX Vref=28, minBit 0, minWin=25, winSum=428
8460 00:26:09.327896 TX Vref=30, minBit 0, minWin=25, winSum=423
8461 00:26:09.331435 TX Vref=32, minBit 6, minWin=24, winSum=412
8462 00:26:09.334929 TX Vref=34, minBit 0, minWin=24, winSum=404
8463 00:26:09.341197 [TxChooseVref] Worse bit 0, Min win 25, Win sum 428, Final Vref 28
8464 00:26:09.341274
8465 00:26:09.344620 Final TX Range 0 Vref 28
8466 00:26:09.344690
8467 00:26:09.344749 ==
8468 00:26:09.347932 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 00:26:09.351140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 00:26:09.351223 ==
8471 00:26:09.351288
8472 00:26:09.351348
8473 00:26:09.354821 TX Vref Scan disable
8474 00:26:09.361292 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8475 00:26:09.361375 == TX Byte 0 ==
8476 00:26:09.365195 u2DelayCellOfst[0]=17 cells (5 PI)
8477 00:26:09.367837 u2DelayCellOfst[1]=10 cells (3 PI)
8478 00:26:09.371449 u2DelayCellOfst[2]=0 cells (0 PI)
8479 00:26:09.374933 u2DelayCellOfst[3]=3 cells (1 PI)
8480 00:26:09.378385 u2DelayCellOfst[4]=6 cells (2 PI)
8481 00:26:09.381192 u2DelayCellOfst[5]=17 cells (5 PI)
8482 00:26:09.381276 u2DelayCellOfst[6]=20 cells (6 PI)
8483 00:26:09.384704 u2DelayCellOfst[7]=6 cells (2 PI)
8484 00:26:09.391477 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8485 00:26:09.394841 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8486 00:26:09.394924 == TX Byte 1 ==
8487 00:26:09.398306 u2DelayCellOfst[8]=0 cells (0 PI)
8488 00:26:09.401178 u2DelayCellOfst[9]=0 cells (0 PI)
8489 00:26:09.404641 u2DelayCellOfst[10]=10 cells (3 PI)
8490 00:26:09.407859 u2DelayCellOfst[11]=3 cells (1 PI)
8491 00:26:09.411195 u2DelayCellOfst[12]=13 cells (4 PI)
8492 00:26:09.414621 u2DelayCellOfst[13]=13 cells (4 PI)
8493 00:26:09.417657 u2DelayCellOfst[14]=13 cells (4 PI)
8494 00:26:09.421243 u2DelayCellOfst[15]=13 cells (4 PI)
8495 00:26:09.424422 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8496 00:26:09.431202 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8497 00:26:09.431277 DramC Write-DBI on
8498 00:26:09.431339 ==
8499 00:26:09.434577 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 00:26:09.437557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 00:26:09.437628 ==
8502 00:26:09.437687
8503 00:26:09.440796
8504 00:26:09.440895 TX Vref Scan disable
8505 00:26:09.444147 == TX Byte 0 ==
8506 00:26:09.447656 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8507 00:26:09.451014 == TX Byte 1 ==
8508 00:26:09.454521 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8509 00:26:09.454602 DramC Write-DBI off
8510 00:26:09.454666
8511 00:26:09.457809 [DATLAT]
8512 00:26:09.457889 Freq=1600, CH1 RK0
8513 00:26:09.457953
8514 00:26:09.460882 DATLAT Default: 0xf
8515 00:26:09.460963 0, 0xFFFF, sum = 0
8516 00:26:09.464369 1, 0xFFFF, sum = 0
8517 00:26:09.464451 2, 0xFFFF, sum = 0
8518 00:26:09.467428 3, 0xFFFF, sum = 0
8519 00:26:09.467558 4, 0xFFFF, sum = 0
8520 00:26:09.470974 5, 0xFFFF, sum = 0
8521 00:26:09.471056 6, 0xFFFF, sum = 0
8522 00:26:09.474022 7, 0xFFFF, sum = 0
8523 00:26:09.474104 8, 0xFFFF, sum = 0
8524 00:26:09.477571 9, 0xFFFF, sum = 0
8525 00:26:09.481321 10, 0xFFFF, sum = 0
8526 00:26:09.481441 11, 0xFFFF, sum = 0
8527 00:26:09.483966 12, 0xFFFF, sum = 0
8528 00:26:09.484049 13, 0xFFFF, sum = 0
8529 00:26:09.487552 14, 0x0, sum = 1
8530 00:26:09.487638 15, 0x0, sum = 2
8531 00:26:09.490968 16, 0x0, sum = 3
8532 00:26:09.491050 17, 0x0, sum = 4
8533 00:26:09.491114 best_step = 15
8534 00:26:09.494536
8535 00:26:09.494616 ==
8536 00:26:09.497238 Dram Type= 6, Freq= 0, CH_1, rank 0
8537 00:26:09.500729 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8538 00:26:09.500810 ==
8539 00:26:09.500875 RX Vref Scan: 1
8540 00:26:09.500935
8541 00:26:09.504284 Set Vref Range= 24 -> 127
8542 00:26:09.504365
8543 00:26:09.507665 RX Vref 24 -> 127, step: 1
8544 00:26:09.507746
8545 00:26:09.510743 RX Delay 27 -> 252, step: 4
8546 00:26:09.510824
8547 00:26:09.514122 Set Vref, RX VrefLevel [Byte0]: 24
8548 00:26:09.517231 [Byte1]: 24
8549 00:26:09.517353
8550 00:26:09.520651 Set Vref, RX VrefLevel [Byte0]: 25
8551 00:26:09.524214 [Byte1]: 25
8552 00:26:09.524290
8553 00:26:09.527127 Set Vref, RX VrefLevel [Byte0]: 26
8554 00:26:09.530876 [Byte1]: 26
8555 00:26:09.534338
8556 00:26:09.534420 Set Vref, RX VrefLevel [Byte0]: 27
8557 00:26:09.537550 [Byte1]: 27
8558 00:26:09.541886
8559 00:26:09.541961 Set Vref, RX VrefLevel [Byte0]: 28
8560 00:26:09.545002 [Byte1]: 28
8561 00:26:09.548944
8562 00:26:09.549024 Set Vref, RX VrefLevel [Byte0]: 29
8563 00:26:09.552685 [Byte1]: 29
8564 00:26:09.556582
8565 00:26:09.556663 Set Vref, RX VrefLevel [Byte0]: 30
8566 00:26:09.560059 [Byte1]: 30
8567 00:26:09.564399
8568 00:26:09.564478 Set Vref, RX VrefLevel [Byte0]: 31
8569 00:26:09.567747 [Byte1]: 31
8570 00:26:09.571696
8571 00:26:09.571803 Set Vref, RX VrefLevel [Byte0]: 32
8572 00:26:09.575298 [Byte1]: 32
8573 00:26:09.579355
8574 00:26:09.579466 Set Vref, RX VrefLevel [Byte0]: 33
8575 00:26:09.582422 [Byte1]: 33
8576 00:26:09.587347
8577 00:26:09.587428 Set Vref, RX VrefLevel [Byte0]: 34
8578 00:26:09.590206 [Byte1]: 34
8579 00:26:09.594601
8580 00:26:09.594682 Set Vref, RX VrefLevel [Byte0]: 35
8581 00:26:09.597446 [Byte1]: 35
8582 00:26:09.602271
8583 00:26:09.602352 Set Vref, RX VrefLevel [Byte0]: 36
8584 00:26:09.605118 [Byte1]: 36
8585 00:26:09.609577
8586 00:26:09.609658 Set Vref, RX VrefLevel [Byte0]: 37
8587 00:26:09.612612 [Byte1]: 37
8588 00:26:09.617085
8589 00:26:09.617166 Set Vref, RX VrefLevel [Byte0]: 38
8590 00:26:09.620320 [Byte1]: 38
8591 00:26:09.624464
8592 00:26:09.624545 Set Vref, RX VrefLevel [Byte0]: 39
8593 00:26:09.627889 [Byte1]: 39
8594 00:26:09.632098
8595 00:26:09.632179 Set Vref, RX VrefLevel [Byte0]: 40
8596 00:26:09.635625 [Byte1]: 40
8597 00:26:09.639664
8598 00:26:09.639745 Set Vref, RX VrefLevel [Byte0]: 41
8599 00:26:09.642915 [Byte1]: 41
8600 00:26:09.647088
8601 00:26:09.647172 Set Vref, RX VrefLevel [Byte0]: 42
8602 00:26:09.650188 [Byte1]: 42
8603 00:26:09.654815
8604 00:26:09.654895 Set Vref, RX VrefLevel [Byte0]: 43
8605 00:26:09.658056 [Byte1]: 43
8606 00:26:09.661944
8607 00:26:09.662025 Set Vref, RX VrefLevel [Byte0]: 44
8608 00:26:09.665238 [Byte1]: 44
8609 00:26:09.669507
8610 00:26:09.669588 Set Vref, RX VrefLevel [Byte0]: 45
8611 00:26:09.673190 [Byte1]: 45
8612 00:26:09.677390
8613 00:26:09.677473 Set Vref, RX VrefLevel [Byte0]: 46
8614 00:26:09.680654 [Byte1]: 46
8615 00:26:09.684589
8616 00:26:09.684672 Set Vref, RX VrefLevel [Byte0]: 47
8617 00:26:09.687813 [Byte1]: 47
8618 00:26:09.692194
8619 00:26:09.692279 Set Vref, RX VrefLevel [Byte0]: 48
8620 00:26:09.695794 [Byte1]: 48
8621 00:26:09.699627
8622 00:26:09.699708 Set Vref, RX VrefLevel [Byte0]: 49
8623 00:26:09.703193 [Byte1]: 49
8624 00:26:09.707474
8625 00:26:09.707577 Set Vref, RX VrefLevel [Byte0]: 50
8626 00:26:09.710535 [Byte1]: 50
8627 00:26:09.714618
8628 00:26:09.714699 Set Vref, RX VrefLevel [Byte0]: 51
8629 00:26:09.718096 [Byte1]: 51
8630 00:26:09.722686
8631 00:26:09.722767 Set Vref, RX VrefLevel [Byte0]: 52
8632 00:26:09.725682 [Byte1]: 52
8633 00:26:09.730085
8634 00:26:09.730166 Set Vref, RX VrefLevel [Byte0]: 53
8635 00:26:09.733077 [Byte1]: 53
8636 00:26:09.737303
8637 00:26:09.737384 Set Vref, RX VrefLevel [Byte0]: 54
8638 00:26:09.740712 [Byte1]: 54
8639 00:26:09.744924
8640 00:26:09.745004 Set Vref, RX VrefLevel [Byte0]: 55
8641 00:26:09.748289 [Byte1]: 55
8642 00:26:09.752668
8643 00:26:09.752750 Set Vref, RX VrefLevel [Byte0]: 56
8644 00:26:09.756033 [Byte1]: 56
8645 00:26:09.759901
8646 00:26:09.759982 Set Vref, RX VrefLevel [Byte0]: 57
8647 00:26:09.763328 [Byte1]: 57
8648 00:26:09.767404
8649 00:26:09.767481 Set Vref, RX VrefLevel [Byte0]: 58
8650 00:26:09.770893 [Byte1]: 58
8651 00:26:09.775340
8652 00:26:09.775438 Set Vref, RX VrefLevel [Byte0]: 59
8653 00:26:09.778518 [Byte1]: 59
8654 00:26:09.782749
8655 00:26:09.782831 Set Vref, RX VrefLevel [Byte0]: 60
8656 00:26:09.785987 [Byte1]: 60
8657 00:26:09.790258
8658 00:26:09.790342 Set Vref, RX VrefLevel [Byte0]: 61
8659 00:26:09.793493 [Byte1]: 61
8660 00:26:09.797793
8661 00:26:09.797875 Set Vref, RX VrefLevel [Byte0]: 62
8662 00:26:09.801108 [Byte1]: 62
8663 00:26:09.805762
8664 00:26:09.805843 Set Vref, RX VrefLevel [Byte0]: 63
8665 00:26:09.808474 [Byte1]: 63
8666 00:26:09.812608
8667 00:26:09.812691 Set Vref, RX VrefLevel [Byte0]: 64
8668 00:26:09.815994 [Byte1]: 64
8669 00:26:09.820045
8670 00:26:09.820126 Set Vref, RX VrefLevel [Byte0]: 65
8671 00:26:09.823567 [Byte1]: 65
8672 00:26:09.827726
8673 00:26:09.827822 Set Vref, RX VrefLevel [Byte0]: 66
8674 00:26:09.831082 [Byte1]: 66
8675 00:26:09.835099
8676 00:26:09.835271 Set Vref, RX VrefLevel [Byte0]: 67
8677 00:26:09.838559 [Byte1]: 67
8678 00:26:09.842903
8679 00:26:09.843021 Set Vref, RX VrefLevel [Byte0]: 68
8680 00:26:09.846119 [Byte1]: 68
8681 00:26:09.850572
8682 00:26:09.850676 Set Vref, RX VrefLevel [Byte0]: 69
8683 00:26:09.853773 [Byte1]: 69
8684 00:26:09.857998
8685 00:26:09.858095 Set Vref, RX VrefLevel [Byte0]: 70
8686 00:26:09.861275 [Byte1]: 70
8687 00:26:09.865429
8688 00:26:09.865510 Set Vref, RX VrefLevel [Byte0]: 71
8689 00:26:09.868830 [Byte1]: 71
8690 00:26:09.873006
8691 00:26:09.873087 Set Vref, RX VrefLevel [Byte0]: 72
8692 00:26:09.876398 [Byte1]: 72
8693 00:26:09.880545
8694 00:26:09.880653 Set Vref, RX VrefLevel [Byte0]: 73
8695 00:26:09.883814 [Byte1]: 73
8696 00:26:09.888367
8697 00:26:09.888444 Set Vref, RX VrefLevel [Byte0]: 74
8698 00:26:09.891715 [Byte1]: 74
8699 00:26:09.895581
8700 00:26:09.895663 Set Vref, RX VrefLevel [Byte0]: 75
8701 00:26:09.899074 [Byte1]: 75
8702 00:26:09.903374
8703 00:26:09.903455 Set Vref, RX VrefLevel [Byte0]: 76
8704 00:26:09.906609 [Byte1]: 76
8705 00:26:09.910885
8706 00:26:09.910961 Final RX Vref Byte 0 = 58 to rank0
8707 00:26:09.914263 Final RX Vref Byte 1 = 58 to rank0
8708 00:26:09.917138 Final RX Vref Byte 0 = 58 to rank1
8709 00:26:09.920740 Final RX Vref Byte 1 = 58 to rank1==
8710 00:26:09.924273 Dram Type= 6, Freq= 0, CH_1, rank 0
8711 00:26:09.930757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8712 00:26:09.930833 ==
8713 00:26:09.930901 DQS Delay:
8714 00:26:09.930964 DQS0 = 0, DQS1 = 0
8715 00:26:09.934084 DQM Delay:
8716 00:26:09.934154 DQM0 = 134, DQM1 = 131
8717 00:26:09.937484 DQ Delay:
8718 00:26:09.940747 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8719 00:26:09.944380 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132
8720 00:26:09.947358 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8721 00:26:09.950591 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8722 00:26:09.950664
8723 00:26:09.950729
8724 00:26:09.950790
8725 00:26:09.954053 [DramC_TX_OE_Calibration] TA2
8726 00:26:09.957388 Original DQ_B0 (3 6) =30, OEN = 27
8727 00:26:09.960986 Original DQ_B1 (3 6) =30, OEN = 27
8728 00:26:09.964194 24, 0x0, End_B0=24 End_B1=24
8729 00:26:09.964265 25, 0x0, End_B0=25 End_B1=25
8730 00:26:09.967671 26, 0x0, End_B0=26 End_B1=26
8731 00:26:09.970684 27, 0x0, End_B0=27 End_B1=27
8732 00:26:09.974098 28, 0x0, End_B0=28 End_B1=28
8733 00:26:09.974187 29, 0x0, End_B0=29 End_B1=29
8734 00:26:09.977737 30, 0x0, End_B0=30 End_B1=30
8735 00:26:09.980532 31, 0x4141, End_B0=30 End_B1=30
8736 00:26:09.984187 Byte0 end_step=30 best_step=27
8737 00:26:09.987788 Byte1 end_step=30 best_step=27
8738 00:26:09.990624 Byte0 TX OE(2T, 0.5T) = (3, 3)
8739 00:26:09.990695 Byte1 TX OE(2T, 0.5T) = (3, 3)
8740 00:26:09.990760
8741 00:26:09.994007
8742 00:26:10.000554 [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8743 00:26:10.004030 CH1 RK0: MR19=303, MR18=1624
8744 00:26:10.010611 CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16
8745 00:26:10.010692
8746 00:26:10.014197 ----->DramcWriteLeveling(PI) begin...
8747 00:26:10.014278 ==
8748 00:26:10.017477 Dram Type= 6, Freq= 0, CH_1, rank 1
8749 00:26:10.020833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8750 00:26:10.020906 ==
8751 00:26:10.023800 Write leveling (Byte 0): 25 => 25
8752 00:26:10.027157 Write leveling (Byte 1): 28 => 28
8753 00:26:10.030885 DramcWriteLeveling(PI) end<-----
8754 00:26:10.030959
8755 00:26:10.031025 ==
8756 00:26:10.033776 Dram Type= 6, Freq= 0, CH_1, rank 1
8757 00:26:10.037309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8758 00:26:10.037394 ==
8759 00:26:10.040711 [Gating] SW mode calibration
8760 00:26:10.046937 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8761 00:26:10.053911 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8762 00:26:10.056888 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 00:26:10.060300 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 00:26:10.067272 1 4 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8765 00:26:10.070318 1 4 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8766 00:26:10.073569 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 00:26:10.080481 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 00:26:10.083754 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 00:26:10.087067 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 00:26:10.093462 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 00:26:10.096874 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8772 00:26:10.100133 1 5 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
8773 00:26:10.106936 1 5 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8774 00:26:10.109991 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 00:26:10.113648 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 00:26:10.120132 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 00:26:10.123687 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 00:26:10.126644 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 00:26:10.133265 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8780 00:26:10.136680 1 6 8 | B1->B0 | 3f3e 2525 | 1 0 | (0 0) (0 0)
8781 00:26:10.140011 1 6 12 | B1->B0 | 4646 4444 | 0 1 | (0 0) (0 0)
8782 00:26:10.146695 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 00:26:10.149807 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 00:26:10.153191 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 00:26:10.156792 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 00:26:10.163548 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 00:26:10.166845 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8788 00:26:10.169766 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8789 00:26:10.176521 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8790 00:26:10.179742 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 00:26:10.183109 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 00:26:10.190192 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 00:26:10.192999 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 00:26:10.196560 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 00:26:10.202884 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 00:26:10.206454 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 00:26:10.209975 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 00:26:10.216368 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 00:26:10.219963 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 00:26:10.223259 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 00:26:10.229809 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 00:26:10.232992 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 00:26:10.236517 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8804 00:26:10.242904 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8805 00:26:10.246341 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8806 00:26:10.249662 Total UI for P1: 0, mck2ui 16
8807 00:26:10.253583 best dqsien dly found for B1: ( 1, 9, 6)
8808 00:26:10.256555 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 00:26:10.260056 Total UI for P1: 0, mck2ui 16
8810 00:26:10.263043 best dqsien dly found for B0: ( 1, 9, 12)
8811 00:26:10.266213 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8812 00:26:10.269454 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8813 00:26:10.269535
8814 00:26:10.272741 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8815 00:26:10.279896 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8816 00:26:10.279992 [Gating] SW calibration Done
8817 00:26:10.280059 ==
8818 00:26:10.283010 Dram Type= 6, Freq= 0, CH_1, rank 1
8819 00:26:10.289981 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8820 00:26:10.290059 ==
8821 00:26:10.290127 RX Vref Scan: 0
8822 00:26:10.290189
8823 00:26:10.293184 RX Vref 0 -> 0, step: 1
8824 00:26:10.293260
8825 00:26:10.296132 RX Delay 0 -> 252, step: 8
8826 00:26:10.299957 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8827 00:26:10.303101 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8828 00:26:10.306497 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8829 00:26:10.313088 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8830 00:26:10.315944 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8831 00:26:10.319591 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8832 00:26:10.322997 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8833 00:26:10.326291 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8834 00:26:10.333051 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8835 00:26:10.336044 iDelay=208, Bit 9, Center 123 (64 ~ 183) 120
8836 00:26:10.339287 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8837 00:26:10.342791 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8838 00:26:10.346258 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8839 00:26:10.352617 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8840 00:26:10.355878 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8841 00:26:10.359598 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8842 00:26:10.359672 ==
8843 00:26:10.362942 Dram Type= 6, Freq= 0, CH_1, rank 1
8844 00:26:10.366227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8845 00:26:10.366300 ==
8846 00:26:10.369237 DQS Delay:
8847 00:26:10.369308 DQS0 = 0, DQS1 = 0
8848 00:26:10.372668 DQM Delay:
8849 00:26:10.372745 DQM0 = 136, DQM1 = 134
8850 00:26:10.372807 DQ Delay:
8851 00:26:10.375746 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8852 00:26:10.382367 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8853 00:26:10.386009 DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =127
8854 00:26:10.389404 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8855 00:26:10.389488
8856 00:26:10.389554
8857 00:26:10.389616 ==
8858 00:26:10.392707 Dram Type= 6, Freq= 0, CH_1, rank 1
8859 00:26:10.395776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8860 00:26:10.395860 ==
8861 00:26:10.395927
8862 00:26:10.395988
8863 00:26:10.399134 TX Vref Scan disable
8864 00:26:10.402331 == TX Byte 0 ==
8865 00:26:10.405823 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8866 00:26:10.408971 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8867 00:26:10.412519 == TX Byte 1 ==
8868 00:26:10.416024 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8869 00:26:10.419017 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8870 00:26:10.419091 ==
8871 00:26:10.422485 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 00:26:10.426113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 00:26:10.428875 ==
8874 00:26:10.440001
8875 00:26:10.443387 TX Vref early break, caculate TX vref
8876 00:26:10.446837 TX Vref=16, minBit 0, minWin=23, winSum=382
8877 00:26:10.449985 TX Vref=18, minBit 0, minWin=23, winSum=394
8878 00:26:10.453213 TX Vref=20, minBit 5, minWin=24, winSum=402
8879 00:26:10.456735 TX Vref=22, minBit 0, minWin=24, winSum=411
8880 00:26:10.460040 TX Vref=24, minBit 0, minWin=25, winSum=419
8881 00:26:10.466610 TX Vref=26, minBit 6, minWin=25, winSum=424
8882 00:26:10.469877 TX Vref=28, minBit 0, minWin=26, winSum=427
8883 00:26:10.473313 TX Vref=30, minBit 0, minWin=25, winSum=423
8884 00:26:10.476780 TX Vref=32, minBit 1, minWin=25, winSum=416
8885 00:26:10.480196 TX Vref=34, minBit 6, minWin=23, winSum=404
8886 00:26:10.486884 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
8887 00:26:10.486963
8888 00:26:10.490325 Final TX Range 0 Vref 28
8889 00:26:10.490418
8890 00:26:10.490485 ==
8891 00:26:10.493158 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 00:26:10.496924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 00:26:10.497032 ==
8894 00:26:10.497126
8895 00:26:10.497240
8896 00:26:10.499856 TX Vref Scan disable
8897 00:26:10.506534 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8898 00:26:10.506676 == TX Byte 0 ==
8899 00:26:10.509883 u2DelayCellOfst[0]=17 cells (5 PI)
8900 00:26:10.513080 u2DelayCellOfst[1]=10 cells (3 PI)
8901 00:26:10.516722 u2DelayCellOfst[2]=0 cells (0 PI)
8902 00:26:10.520051 u2DelayCellOfst[3]=6 cells (2 PI)
8903 00:26:10.522820 u2DelayCellOfst[4]=10 cells (3 PI)
8904 00:26:10.526652 u2DelayCellOfst[5]=17 cells (5 PI)
8905 00:26:10.529635 u2DelayCellOfst[6]=20 cells (6 PI)
8906 00:26:10.529740 u2DelayCellOfst[7]=6 cells (2 PI)
8907 00:26:10.536375 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8908 00:26:10.539806 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8909 00:26:10.539887 == TX Byte 1 ==
8910 00:26:10.542968 u2DelayCellOfst[8]=0 cells (0 PI)
8911 00:26:10.546655 u2DelayCellOfst[9]=3 cells (1 PI)
8912 00:26:10.550357 u2DelayCellOfst[10]=10 cells (3 PI)
8913 00:26:10.553033 u2DelayCellOfst[11]=6 cells (2 PI)
8914 00:26:10.556711 u2DelayCellOfst[12]=13 cells (4 PI)
8915 00:26:10.560204 u2DelayCellOfst[13]=17 cells (5 PI)
8916 00:26:10.563091 u2DelayCellOfst[14]=17 cells (5 PI)
8917 00:26:10.566501 u2DelayCellOfst[15]=17 cells (5 PI)
8918 00:26:10.569910 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8919 00:26:10.576289 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8920 00:26:10.576386 DramC Write-DBI on
8921 00:26:10.576451 ==
8922 00:26:10.579713 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 00:26:10.583068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 00:26:10.583157 ==
8925 00:26:10.583234
8926 00:26:10.586549
8927 00:26:10.586622 TX Vref Scan disable
8928 00:26:10.589565 == TX Byte 0 ==
8929 00:26:10.593327 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8930 00:26:10.596434 == TX Byte 1 ==
8931 00:26:10.599411 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8932 00:26:10.599523 DramC Write-DBI off
8933 00:26:10.599604
8934 00:26:10.602882 [DATLAT]
8935 00:26:10.602960 Freq=1600, CH1 RK1
8936 00:26:10.603023
8937 00:26:10.606159 DATLAT Default: 0xf
8938 00:26:10.606230 0, 0xFFFF, sum = 0
8939 00:26:10.609316 1, 0xFFFF, sum = 0
8940 00:26:10.609392 2, 0xFFFF, sum = 0
8941 00:26:10.612709 3, 0xFFFF, sum = 0
8942 00:26:10.612783 4, 0xFFFF, sum = 0
8943 00:26:10.616194 5, 0xFFFF, sum = 0
8944 00:26:10.616268 6, 0xFFFF, sum = 0
8945 00:26:10.619461 7, 0xFFFF, sum = 0
8946 00:26:10.623144 8, 0xFFFF, sum = 0
8947 00:26:10.623222 9, 0xFFFF, sum = 0
8948 00:26:10.626386 10, 0xFFFF, sum = 0
8949 00:26:10.626469 11, 0xFFFF, sum = 0
8950 00:26:10.629748 12, 0xFFFF, sum = 0
8951 00:26:10.629831 13, 0xFFFF, sum = 0
8952 00:26:10.633111 14, 0x0, sum = 1
8953 00:26:10.633194 15, 0x0, sum = 2
8954 00:26:10.636497 16, 0x0, sum = 3
8955 00:26:10.636580 17, 0x0, sum = 4
8956 00:26:10.636646 best_step = 15
8957 00:26:10.639529
8958 00:26:10.639611 ==
8959 00:26:10.642908 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 00:26:10.646334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 00:26:10.646416 ==
8962 00:26:10.646481 RX Vref Scan: 0
8963 00:26:10.646541
8964 00:26:10.649515 RX Vref 0 -> 0, step: 1
8965 00:26:10.649598
8966 00:26:10.653022 RX Delay 19 -> 252, step: 4
8967 00:26:10.656110 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8968 00:26:10.659610 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8969 00:26:10.666007 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8970 00:26:10.669434 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8971 00:26:10.672821 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8972 00:26:10.676188 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8973 00:26:10.679448 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8974 00:26:10.686061 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8975 00:26:10.689479 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8976 00:26:10.692937 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8977 00:26:10.695856 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8978 00:26:10.699430 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8979 00:26:10.705953 iDelay=195, Bit 12, Center 142 (91 ~ 194) 104
8980 00:26:10.709295 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8981 00:26:10.712651 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8982 00:26:10.716119 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8983 00:26:10.716202 ==
8984 00:26:10.719529 Dram Type= 6, Freq= 0, CH_1, rank 1
8985 00:26:10.726009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8986 00:26:10.726092 ==
8987 00:26:10.726157 DQS Delay:
8988 00:26:10.726218 DQS0 = 0, DQS1 = 0
8989 00:26:10.729364 DQM Delay:
8990 00:26:10.729448 DQM0 = 134, DQM1 = 131
8991 00:26:10.732897 DQ Delay:
8992 00:26:10.736055 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8993 00:26:10.739077 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8994 00:26:10.742497 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8995 00:26:10.745894 DQ12 =142, DQ13 =138, DQ14 =136, DQ15 =140
8996 00:26:10.745976
8997 00:26:10.746040
8998 00:26:10.746099
8999 00:26:10.749495 [DramC_TX_OE_Calibration] TA2
9000 00:26:10.752824 Original DQ_B0 (3 6) =30, OEN = 27
9001 00:26:10.755823 Original DQ_B1 (3 6) =30, OEN = 27
9002 00:26:10.759511 24, 0x0, End_B0=24 End_B1=24
9003 00:26:10.759603 25, 0x0, End_B0=25 End_B1=25
9004 00:26:10.762577 26, 0x0, End_B0=26 End_B1=26
9005 00:26:10.766142 27, 0x0, End_B0=27 End_B1=27
9006 00:26:10.769307 28, 0x0, End_B0=28 End_B1=28
9007 00:26:10.769391 29, 0x0, End_B0=29 End_B1=29
9008 00:26:10.772361 30, 0x0, End_B0=30 End_B1=30
9009 00:26:10.775979 31, 0x4141, End_B0=30 End_B1=30
9010 00:26:10.779279 Byte0 end_step=30 best_step=27
9011 00:26:10.782922 Byte1 end_step=30 best_step=27
9012 00:26:10.785747 Byte0 TX OE(2T, 0.5T) = (3, 3)
9013 00:26:10.785830 Byte1 TX OE(2T, 0.5T) = (3, 3)
9014 00:26:10.789530
9015 00:26:10.789611
9016 00:26:10.796174 [DQSOSCAuto] RK1, (LSB)MR18= 0x2409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
9017 00:26:10.799427 CH1 RK1: MR19=303, MR18=2409
9018 00:26:10.805790 CH1_RK1: MR19=0x303, MR18=0x2409, DQSOSC=391, MR23=63, INC=24, DEC=16
9019 00:26:10.809472 [RxdqsGatingPostProcess] freq 1600
9020 00:26:10.812523 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9021 00:26:10.816056 best DQS0 dly(2T, 0.5T) = (1, 1)
9022 00:26:10.819467 best DQS1 dly(2T, 0.5T) = (1, 1)
9023 00:26:10.822887 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9024 00:26:10.825814 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9025 00:26:10.829140 best DQS0 dly(2T, 0.5T) = (1, 1)
9026 00:26:10.832523 best DQS1 dly(2T, 0.5T) = (1, 1)
9027 00:26:10.836007 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9028 00:26:10.839399 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9029 00:26:10.839481 Pre-setting of DQS Precalculation
9030 00:26:10.846038 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9031 00:26:10.852668 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9032 00:26:10.859488 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9033 00:26:10.859605
9034 00:26:10.859698
9035 00:26:10.862437 [Calibration Summary] 3200 Mbps
9036 00:26:10.865714 CH 0, Rank 0
9037 00:26:10.865786 SW Impedance : PASS
9038 00:26:10.869141 DUTY Scan : NO K
9039 00:26:10.872547 ZQ Calibration : PASS
9040 00:26:10.872630 Jitter Meter : NO K
9041 00:26:10.875950 CBT Training : PASS
9042 00:26:10.878908 Write leveling : PASS
9043 00:26:10.878990 RX DQS gating : PASS
9044 00:26:10.882425 RX DQ/DQS(RDDQC) : PASS
9045 00:26:10.882508 TX DQ/DQS : PASS
9046 00:26:10.885919 RX DATLAT : PASS
9047 00:26:10.889201 RX DQ/DQS(Engine): PASS
9048 00:26:10.889284 TX OE : PASS
9049 00:26:10.892207 All Pass.
9050 00:26:10.892289
9051 00:26:10.892354 CH 0, Rank 1
9052 00:26:10.895490 SW Impedance : PASS
9053 00:26:10.895590 DUTY Scan : NO K
9054 00:26:10.899188 ZQ Calibration : PASS
9055 00:26:10.902060 Jitter Meter : NO K
9056 00:26:10.902143 CBT Training : PASS
9057 00:26:10.905616 Write leveling : PASS
9058 00:26:10.908997 RX DQS gating : PASS
9059 00:26:10.909107 RX DQ/DQS(RDDQC) : PASS
9060 00:26:10.912387 TX DQ/DQS : PASS
9061 00:26:10.915853 RX DATLAT : PASS
9062 00:26:10.915936 RX DQ/DQS(Engine): PASS
9063 00:26:10.919095 TX OE : PASS
9064 00:26:10.919177 All Pass.
9065 00:26:10.919242
9066 00:26:10.922672 CH 1, Rank 0
9067 00:26:10.922743 SW Impedance : PASS
9068 00:26:10.925459 DUTY Scan : NO K
9069 00:26:10.928786 ZQ Calibration : PASS
9070 00:26:10.928868 Jitter Meter : NO K
9071 00:26:10.931829 CBT Training : PASS
9072 00:26:10.935632 Write leveling : PASS
9073 00:26:10.935714 RX DQS gating : PASS
9074 00:26:10.938663 RX DQ/DQS(RDDQC) : PASS
9075 00:26:10.938744 TX DQ/DQS : PASS
9076 00:26:10.942335 RX DATLAT : PASS
9077 00:26:10.945452 RX DQ/DQS(Engine): PASS
9078 00:26:10.945544 TX OE : PASS
9079 00:26:10.948707 All Pass.
9080 00:26:10.948789
9081 00:26:10.948854 CH 1, Rank 1
9082 00:26:10.951903 SW Impedance : PASS
9083 00:26:10.951985 DUTY Scan : NO K
9084 00:26:10.955355 ZQ Calibration : PASS
9085 00:26:10.958801 Jitter Meter : NO K
9086 00:26:10.958884 CBT Training : PASS
9087 00:26:10.962367 Write leveling : PASS
9088 00:26:10.965274 RX DQS gating : PASS
9089 00:26:10.965357 RX DQ/DQS(RDDQC) : PASS
9090 00:26:10.968954 TX DQ/DQS : PASS
9091 00:26:10.971879 RX DATLAT : PASS
9092 00:26:10.971960 RX DQ/DQS(Engine): PASS
9093 00:26:10.975263 TX OE : PASS
9094 00:26:10.975346 All Pass.
9095 00:26:10.975411
9096 00:26:10.978430 DramC Write-DBI on
9097 00:26:10.981992 PER_BANK_REFRESH: Hybrid Mode
9098 00:26:10.982076 TX_TRACKING: ON
9099 00:26:10.991855 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9100 00:26:10.998299 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9101 00:26:11.004963 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9102 00:26:11.008563 [FAST_K] Save calibration result to emmc
9103 00:26:11.011901 sync common calibartion params.
9104 00:26:11.015024 sync cbt_mode0:1, 1:1
9105 00:26:11.018540 dram_init: ddr_geometry: 2
9106 00:26:11.018620 dram_init: ddr_geometry: 2
9107 00:26:11.021878 dram_init: ddr_geometry: 2
9108 00:26:11.025090 0:dram_rank_size:100000000
9109 00:26:11.028486 1:dram_rank_size:100000000
9110 00:26:11.031754 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9111 00:26:11.035152 DFS_SHUFFLE_HW_MODE: ON
9112 00:26:11.038117 dramc_set_vcore_voltage set vcore to 725000
9113 00:26:11.041869 Read voltage for 1600, 0
9114 00:26:11.041957 Vio18 = 0
9115 00:26:11.042051 Vcore = 725000
9116 00:26:11.044764 Vdram = 0
9117 00:26:11.044872 Vddq = 0
9118 00:26:11.044978 Vmddr = 0
9119 00:26:11.048422 switch to 3200 Mbps bootup
9120 00:26:11.048531 [DramcRunTimeConfig]
9121 00:26:11.051760 PHYPLL
9122 00:26:11.051896 DPM_CONTROL_AFTERK: ON
9123 00:26:11.054897 PER_BANK_REFRESH: ON
9124 00:26:11.058109 REFRESH_OVERHEAD_REDUCTION: ON
9125 00:26:11.058196 CMD_PICG_NEW_MODE: OFF
9126 00:26:11.061548 XRTWTW_NEW_MODE: ON
9127 00:26:11.061630 XRTRTR_NEW_MODE: ON
9128 00:26:11.064796 TX_TRACKING: ON
9129 00:26:11.064899 RDSEL_TRACKING: OFF
9130 00:26:11.067894 DQS Precalculation for DVFS: ON
9131 00:26:11.071791 RX_TRACKING: OFF
9132 00:26:11.071867 HW_GATING DBG: ON
9133 00:26:11.074631 ZQCS_ENABLE_LP4: ON
9134 00:26:11.074728 RX_PICG_NEW_MODE: ON
9135 00:26:11.078219 TX_PICG_NEW_MODE: ON
9136 00:26:11.081619 ENABLE_RX_DCM_DPHY: ON
9137 00:26:11.081732 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9138 00:26:11.084402 DUMMY_READ_FOR_TRACKING: OFF
9139 00:26:11.088014 !!! SPM_CONTROL_AFTERK: OFF
9140 00:26:11.091241 !!! SPM could not control APHY
9141 00:26:11.091345 IMPEDANCE_TRACKING: ON
9142 00:26:11.094518 TEMP_SENSOR: ON
9143 00:26:11.094603 HW_SAVE_FOR_SR: OFF
9144 00:26:11.097956 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9145 00:26:11.101294 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9146 00:26:11.104852 Read ODT Tracking: ON
9147 00:26:11.108094 Refresh Rate DeBounce: ON
9148 00:26:11.108197 DFS_NO_QUEUE_FLUSH: ON
9149 00:26:11.111285 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9150 00:26:11.114472 ENABLE_DFS_RUNTIME_MRW: OFF
9151 00:26:11.118139 DDR_RESERVE_NEW_MODE: ON
9152 00:26:11.118240 MR_CBT_SWITCH_FREQ: ON
9153 00:26:11.121006 =========================
9154 00:26:11.140662 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9155 00:26:11.143742 dram_init: ddr_geometry: 2
9156 00:26:11.161805 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9157 00:26:11.165160 dram_init: dram init end (result: 0)
9158 00:26:11.172078 DRAM-K: Full calibration passed in 24458 msecs
9159 00:26:11.175389 MRC: failed to locate region type 0.
9160 00:26:11.175491 DRAM rank0 size:0x100000000,
9161 00:26:11.178960 DRAM rank1 size=0x100000000
9162 00:26:11.188685 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9163 00:26:11.195330 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9164 00:26:11.202100 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9165 00:26:11.208373 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9166 00:26:11.211875 DRAM rank0 size:0x100000000,
9167 00:26:11.215280 DRAM rank1 size=0x100000000
9168 00:26:11.215381 CBMEM:
9169 00:26:11.218499 IMD: root @ 0xfffff000 254 entries.
9170 00:26:11.221814 IMD: root @ 0xffffec00 62 entries.
9171 00:26:11.225194 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9172 00:26:11.228663 WARNING: RO_VPD is uninitialized or empty.
9173 00:26:11.235311 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9174 00:26:11.242202 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9175 00:26:11.254851 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9176 00:26:11.266044 BS: romstage times (exec / console): total (unknown) / 23991 ms
9177 00:26:11.266149
9178 00:26:11.266240
9179 00:26:11.276088 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9180 00:26:11.279652 ARM64: Exception handlers installed.
9181 00:26:11.282537 ARM64: Testing exception
9182 00:26:11.286190 ARM64: Done test exception
9183 00:26:11.286298 Enumerating buses...
9184 00:26:11.289523 Show all devs... Before device enumeration.
9185 00:26:11.293072 Root Device: enabled 1
9186 00:26:11.296271 CPU_CLUSTER: 0: enabled 1
9187 00:26:11.296369 CPU: 00: enabled 1
9188 00:26:11.299657 Compare with tree...
9189 00:26:11.299743 Root Device: enabled 1
9190 00:26:11.302640 CPU_CLUSTER: 0: enabled 1
9191 00:26:11.306493 CPU: 00: enabled 1
9192 00:26:11.306592 Root Device scanning...
9193 00:26:11.309705 scan_static_bus for Root Device
9194 00:26:11.313176 CPU_CLUSTER: 0 enabled
9195 00:26:11.316529 scan_static_bus for Root Device done
9196 00:26:11.319571 scan_bus: bus Root Device finished in 8 msecs
9197 00:26:11.319646 done
9198 00:26:11.326486 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9199 00:26:11.329707 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9200 00:26:11.335967 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9201 00:26:11.339741 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9202 00:26:11.343096 Allocating resources...
9203 00:26:11.343213 Reading resources...
9204 00:26:11.349376 Root Device read_resources bus 0 link: 0
9205 00:26:11.349482 DRAM rank0 size:0x100000000,
9206 00:26:11.352918 DRAM rank1 size=0x100000000
9207 00:26:11.356276 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9208 00:26:11.359543 CPU: 00 missing read_resources
9209 00:26:11.362865 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9210 00:26:11.369294 Root Device read_resources bus 0 link: 0 done
9211 00:26:11.369397 Done reading resources.
9212 00:26:11.376028 Show resources in subtree (Root Device)...After reading.
9213 00:26:11.379664 Root Device child on link 0 CPU_CLUSTER: 0
9214 00:26:11.382737 CPU_CLUSTER: 0 child on link 0 CPU: 00
9215 00:26:11.392829 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9216 00:26:11.392928 CPU: 00
9217 00:26:11.396364 Root Device assign_resources, bus 0 link: 0
9218 00:26:11.399802 CPU_CLUSTER: 0 missing set_resources
9219 00:26:11.402708 Root Device assign_resources, bus 0 link: 0 done
9220 00:26:11.406177 Done setting resources.
9221 00:26:11.412581 Show resources in subtree (Root Device)...After assigning values.
9222 00:26:11.415908 Root Device child on link 0 CPU_CLUSTER: 0
9223 00:26:11.419420 CPU_CLUSTER: 0 child on link 0 CPU: 00
9224 00:26:11.429462 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9225 00:26:11.429570 CPU: 00
9226 00:26:11.432820 Done allocating resources.
9227 00:26:11.435759 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9228 00:26:11.439689 Enabling resources...
9229 00:26:11.439791 done.
9230 00:26:11.445852 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9231 00:26:11.445956 Initializing devices...
9232 00:26:11.448997 Root Device init
9233 00:26:11.449104 init hardware done!
9234 00:26:11.452524 0x00000018: ctrlr->caps
9235 00:26:11.455723 52.000 MHz: ctrlr->f_max
9236 00:26:11.455823 0.400 MHz: ctrlr->f_min
9237 00:26:11.459295 0x40ff8080: ctrlr->voltages
9238 00:26:11.459401 sclk: 390625
9239 00:26:11.462573 Bus Width = 1
9240 00:26:11.462680 sclk: 390625
9241 00:26:11.462773 Bus Width = 1
9242 00:26:11.466003 Early init status = 3
9243 00:26:11.469227 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9244 00:26:11.474362 in-header: 03 fc 00 00 01 00 00 00
9245 00:26:11.476846 in-data: 00
9246 00:26:11.480293 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9247 00:26:11.485307 in-header: 03 fd 00 00 00 00 00 00
9248 00:26:11.488317 in-data:
9249 00:26:11.491750 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9250 00:26:11.495095 in-header: 03 fc 00 00 01 00 00 00
9251 00:26:11.498191 in-data: 00
9252 00:26:11.501715 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9253 00:26:11.506232 in-header: 03 fd 00 00 00 00 00 00
9254 00:26:11.509572 in-data:
9255 00:26:11.513146 [SSUSB] Setting up USB HOST controller...
9256 00:26:11.516048 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9257 00:26:11.519580 [SSUSB] phy power-on done.
9258 00:26:11.522660 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9259 00:26:11.529487 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9260 00:26:11.532879 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9261 00:26:11.539362 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9262 00:26:11.546300 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9263 00:26:11.552549 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9264 00:26:11.559494 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9265 00:26:11.566043 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9266 00:26:11.569042 SPM: binary array size = 0x9dc
9267 00:26:11.572796 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9268 00:26:11.579700 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9269 00:26:11.585837 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9270 00:26:11.589189 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9271 00:26:11.595650 configure_display: Starting display init
9272 00:26:11.629495 anx7625_power_on_init: Init interface.
9273 00:26:11.632953 anx7625_disable_pd_protocol: Disabled PD feature.
9274 00:26:11.636272 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9275 00:26:11.663832 anx7625_start_dp_work: Secure OCM version=00
9276 00:26:11.667248 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9277 00:26:11.681835 sp_tx_get_edid_block: EDID Block = 1
9278 00:26:11.784510 Extracted contents:
9279 00:26:11.788066 header: 00 ff ff ff ff ff ff 00
9280 00:26:11.791328 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9281 00:26:11.794764 version: 01 04
9282 00:26:11.798096 basic params: 95 1f 11 78 0a
9283 00:26:11.801127 chroma info: 76 90 94 55 54 90 27 21 50 54
9284 00:26:11.804353 established: 00 00 00
9285 00:26:11.811255 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9286 00:26:11.814483 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9287 00:26:11.820849 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9288 00:26:11.827454 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9289 00:26:11.834225 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9290 00:26:11.837599 extensions: 00
9291 00:26:11.837701 checksum: fb
9292 00:26:11.837803
9293 00:26:11.841015 Manufacturer: IVO Model 57d Serial Number 0
9294 00:26:11.844227 Made week 0 of 2020
9295 00:26:11.844364 EDID version: 1.4
9296 00:26:11.847639 Digital display
9297 00:26:11.851027 6 bits per primary color channel
9298 00:26:11.851125 DisplayPort interface
9299 00:26:11.854015 Maximum image size: 31 cm x 17 cm
9300 00:26:11.857456 Gamma: 220%
9301 00:26:11.857566 Check DPMS levels
9302 00:26:11.860986 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9303 00:26:11.864340 First detailed timing is preferred timing
9304 00:26:11.867555 Established timings supported:
9305 00:26:11.870596 Standard timings supported:
9306 00:26:11.870696 Detailed timings
9307 00:26:11.877486 Hex of detail: 383680a07038204018303c0035ae10000019
9308 00:26:11.881004 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9309 00:26:11.887091 0780 0798 07c8 0820 hborder 0
9310 00:26:11.890581 0438 043b 0447 0458 vborder 0
9311 00:26:11.894067 -hsync -vsync
9312 00:26:11.894169 Did detailed timing
9313 00:26:11.900825 Hex of detail: 000000000000000000000000000000000000
9314 00:26:11.900965 Manufacturer-specified data, tag 0
9315 00:26:11.907616 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9316 00:26:11.907719 ASCII string: InfoVision
9317 00:26:11.913820 Hex of detail: 000000fe00523134304e574635205248200a
9318 00:26:11.917234 ASCII string: R140NWF5 RH
9319 00:26:11.917354 Checksum
9320 00:26:11.917454 Checksum: 0xfb (valid)
9321 00:26:11.924186 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9322 00:26:11.927150 DSI data_rate: 832800000 bps
9323 00:26:11.930729 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9324 00:26:11.937460 anx7625_parse_edid: pixelclock(138800).
9325 00:26:11.940529 hactive(1920), hsync(48), hfp(24), hbp(88)
9326 00:26:11.943870 vactive(1080), vsync(12), vfp(3), vbp(17)
9327 00:26:11.947500 anx7625_dsi_config: config dsi.
9328 00:26:11.953756 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9329 00:26:11.967014 anx7625_dsi_config: success to config DSI
9330 00:26:11.969805 anx7625_dp_start: MIPI phy setup OK.
9331 00:26:11.973249 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9332 00:26:11.976578 mtk_ddp_mode_set invalid vrefresh 60
9333 00:26:11.979759 main_disp_path_setup
9334 00:26:11.979865 ovl_layer_smi_id_en
9335 00:26:11.983372 ovl_layer_smi_id_en
9336 00:26:11.983477 ccorr_config
9337 00:26:11.983579 aal_config
9338 00:26:11.986712 gamma_config
9339 00:26:11.986790 postmask_config
9340 00:26:11.989987 dither_config
9341 00:26:11.993314 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9342 00:26:11.999892 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9343 00:26:12.003347 Root Device init finished in 551 msecs
9344 00:26:12.003447 CPU_CLUSTER: 0 init
9345 00:26:12.013105 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9346 00:26:12.016616 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9347 00:26:12.019706 APU_MBOX 0x190000b0 = 0x10001
9348 00:26:12.022903 APU_MBOX 0x190001b0 = 0x10001
9349 00:26:12.026287 APU_MBOX 0x190005b0 = 0x10001
9350 00:26:12.029492 APU_MBOX 0x190006b0 = 0x10001
9351 00:26:12.032936 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9352 00:26:12.045664 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9353 00:26:12.057791 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9354 00:26:12.064788 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9355 00:26:12.076480 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9356 00:26:12.085160 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9357 00:26:12.088692 CPU_CLUSTER: 0 init finished in 81 msecs
9358 00:26:12.092209 Devices initialized
9359 00:26:12.095417 Show all devs... After init.
9360 00:26:12.095525 Root Device: enabled 1
9361 00:26:12.098735 CPU_CLUSTER: 0: enabled 1
9362 00:26:12.101932 CPU: 00: enabled 1
9363 00:26:12.105289 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9364 00:26:12.108432 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9365 00:26:12.112095 ELOG: NV offset 0x57f000 size 0x1000
9366 00:26:12.118564 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9367 00:26:12.125095 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9368 00:26:12.128549 ELOG: Event(17) added with size 13 at 2023-08-14 00:25:39 UTC
9369 00:26:12.132020 out: cmd=0x121: 03 db 21 01 00 00 00 00
9370 00:26:12.135560 in-header: 03 a9 00 00 2c 00 00 00
9371 00:26:12.149031 in-data: b6 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9372 00:26:12.155655 ELOG: Event(A1) added with size 10 at 2023-08-14 00:25:39 UTC
9373 00:26:12.162034 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9374 00:26:12.168734 ELOG: Event(A0) added with size 9 at 2023-08-14 00:25:39 UTC
9375 00:26:12.172141 elog_add_boot_reason: Logged dev mode boot
9376 00:26:12.175642 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9377 00:26:12.178961 Finalize devices...
9378 00:26:12.179065 Devices finalized
9379 00:26:12.185760 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9380 00:26:12.188832 Writing coreboot table at 0xffe64000
9381 00:26:12.192008 0. 000000000010a000-0000000000113fff: RAMSTAGE
9382 00:26:12.195364 1. 0000000040000000-00000000400fffff: RAM
9383 00:26:12.199033 2. 0000000040100000-000000004032afff: RAMSTAGE
9384 00:26:12.205267 3. 000000004032b000-00000000545fffff: RAM
9385 00:26:12.208835 4. 0000000054600000-000000005465ffff: BL31
9386 00:26:12.212349 5. 0000000054660000-00000000ffe63fff: RAM
9387 00:26:12.215762 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9388 00:26:12.222318 7. 0000000100000000-000000023fffffff: RAM
9389 00:26:12.222422 Passing 5 GPIOs to payload:
9390 00:26:12.228851 NAME | PORT | POLARITY | VALUE
9391 00:26:12.232079 EC in RW | 0x000000aa | low | undefined
9392 00:26:12.238842 EC interrupt | 0x00000005 | low | undefined
9393 00:26:12.242567 TPM interrupt | 0x000000ab | high | undefined
9394 00:26:12.245853 SD card detect | 0x00000011 | high | undefined
9395 00:26:12.252047 speaker enable | 0x00000093 | high | undefined
9396 00:26:12.255501 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9397 00:26:12.259081 in-header: 03 f9 00 00 02 00 00 00
9398 00:26:12.259188 in-data: 02 00
9399 00:26:12.262563 ADC[4]: Raw value=904726 ID=7
9400 00:26:12.265225 ADC[3]: Raw value=213441 ID=1
9401 00:26:12.265321 RAM Code: 0x71
9402 00:26:12.268492 ADC[6]: Raw value=75701 ID=0
9403 00:26:12.272265 ADC[5]: Raw value=212703 ID=1
9404 00:26:12.272342 SKU Code: 0x1
9405 00:26:12.278458 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3790
9406 00:26:12.281834 coreboot table: 964 bytes.
9407 00:26:12.285264 IMD ROOT 0. 0xfffff000 0x00001000
9408 00:26:12.288751 IMD SMALL 1. 0xffffe000 0x00001000
9409 00:26:12.292144 RO MCACHE 2. 0xffffc000 0x00001104
9410 00:26:12.295650 CONSOLE 3. 0xfff7c000 0x00080000
9411 00:26:12.298788 FMAP 4. 0xfff7b000 0x00000452
9412 00:26:12.301840 TIME STAMP 5. 0xfff7a000 0x00000910
9413 00:26:12.305357 VBOOT WORK 6. 0xfff66000 0x00014000
9414 00:26:12.308760 RAMOOPS 7. 0xffe66000 0x00100000
9415 00:26:12.312181 COREBOOT 8. 0xffe64000 0x00002000
9416 00:26:12.312255 IMD small region:
9417 00:26:12.315325 IMD ROOT 0. 0xffffec00 0x00000400
9418 00:26:12.318364 VPD 1. 0xffffeba0 0x0000004c
9419 00:26:12.321941 MMC STATUS 2. 0xffffeb80 0x00000004
9420 00:26:12.328646 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9421 00:26:12.328746 Probing TPM: done!
9422 00:26:12.335090 Connected to device vid:did:rid of 1ae0:0028:00
9423 00:26:12.342047 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9424 00:26:12.348975 Initialized TPM device CR50 revision 0
9425 00:26:12.349048 Checking cr50 for pending updates
9426 00:26:12.355356 Reading cr50 TPM mode
9427 00:26:12.364070 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9428 00:26:12.370632 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9429 00:26:12.410495 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9430 00:26:12.413696 Checking segment from ROM address 0x40100000
9431 00:26:12.416942 Checking segment from ROM address 0x4010001c
9432 00:26:12.423847 Loading segment from ROM address 0x40100000
9433 00:26:12.423926 code (compression=0)
9434 00:26:12.430418 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9435 00:26:12.440677 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9436 00:26:12.440784 it's not compressed!
9437 00:26:12.447615 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9438 00:26:12.450573 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9439 00:26:12.470635 Loading segment from ROM address 0x4010001c
9440 00:26:12.470738 Entry Point 0x80000000
9441 00:26:12.474253 Loaded segments
9442 00:26:12.477521 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9443 00:26:12.484114 Jumping to boot code at 0x80000000(0xffe64000)
9444 00:26:12.490875 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9445 00:26:12.497225 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9446 00:26:12.505504 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9447 00:26:12.508955 Checking segment from ROM address 0x40100000
9448 00:26:12.512266 Checking segment from ROM address 0x4010001c
9449 00:26:12.518482 Loading segment from ROM address 0x40100000
9450 00:26:12.518557 code (compression=1)
9451 00:26:12.525358 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9452 00:26:12.535370 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9453 00:26:12.535477 using LZMA
9454 00:26:12.543484 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9455 00:26:12.550425 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9456 00:26:12.553811 Loading segment from ROM address 0x4010001c
9457 00:26:12.553908 Entry Point 0x54601000
9458 00:26:12.556759 Loaded segments
9459 00:26:12.560501 NOTICE: MT8192 bl31_setup
9460 00:26:12.567429 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9461 00:26:12.570838 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9462 00:26:12.573798 WARNING: region 0:
9463 00:26:12.577395 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 00:26:12.577492 WARNING: region 1:
9465 00:26:12.584212 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9466 00:26:12.587798 WARNING: region 2:
9467 00:26:12.591021 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9468 00:26:12.593813 WARNING: region 3:
9469 00:26:12.597311 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9470 00:26:12.600670 WARNING: region 4:
9471 00:26:12.604100 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9472 00:26:12.607475 WARNING: region 5:
9473 00:26:12.611165 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 00:26:12.614480 WARNING: region 6:
9475 00:26:12.617310 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9476 00:26:12.617419 WARNING: region 7:
9477 00:26:12.624349 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9478 00:26:12.630675 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9479 00:26:12.633822 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9480 00:26:12.637240 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9481 00:26:12.643921 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9482 00:26:12.647526 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9483 00:26:12.650846 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9484 00:26:12.657364 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9485 00:26:12.660587 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9486 00:26:12.664332 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9487 00:26:12.670733 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9488 00:26:12.674013 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9489 00:26:12.681228 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9490 00:26:12.684561 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9491 00:26:12.687531 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9492 00:26:12.694151 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9493 00:26:12.697746 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9494 00:26:12.701224 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9495 00:26:12.707396 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9496 00:26:12.711094 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9497 00:26:12.714176 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9498 00:26:12.720926 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9499 00:26:12.724112 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9500 00:26:12.731082 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9501 00:26:12.734454 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9502 00:26:12.737520 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9503 00:26:12.744243 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9504 00:26:12.747774 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9505 00:26:12.754135 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9506 00:26:12.757535 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9507 00:26:12.761172 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9508 00:26:12.767733 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9509 00:26:12.771172 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9510 00:26:12.774128 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9511 00:26:12.780891 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9512 00:26:12.784392 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9513 00:26:12.787624 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9514 00:26:12.791311 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9515 00:26:12.797835 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9516 00:26:12.801083 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9517 00:26:12.804486 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9518 00:26:12.807886 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9519 00:26:12.814263 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9520 00:26:12.817800 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9521 00:26:12.821358 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9522 00:26:12.824795 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9523 00:26:12.831137 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9524 00:26:12.834200 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9525 00:26:12.838014 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9526 00:26:12.844562 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9527 00:26:12.847946 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9528 00:26:12.850915 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9529 00:26:12.857711 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9530 00:26:12.861095 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9531 00:26:12.867918 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9532 00:26:12.871204 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9533 00:26:12.878168 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9534 00:26:12.881584 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9535 00:26:12.884654 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9536 00:26:12.891543 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9537 00:26:12.895075 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9538 00:26:12.901308 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9539 00:26:12.904419 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9540 00:26:12.911268 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9541 00:26:12.915642 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9542 00:26:12.917879 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9543 00:26:12.924917 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9544 00:26:12.928521 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9545 00:26:12.934673 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9546 00:26:12.938196 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9547 00:26:12.944722 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9548 00:26:12.947949 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9549 00:26:12.951329 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9550 00:26:12.957842 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9551 00:26:12.961206 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9552 00:26:12.967973 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9553 00:26:12.971405 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9554 00:26:12.978055 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9555 00:26:12.981640 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9556 00:26:12.985099 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9557 00:26:12.991555 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9558 00:26:12.995130 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9559 00:26:13.001904 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9560 00:26:13.005453 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9561 00:26:13.008248 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9562 00:26:13.015058 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9563 00:26:13.018760 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9564 00:26:13.025427 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9565 00:26:13.028536 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9566 00:26:13.035117 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9567 00:26:13.038166 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9568 00:26:13.042003 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9569 00:26:13.048257 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9570 00:26:13.051769 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9571 00:26:13.058668 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9572 00:26:13.061907 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9573 00:26:13.068978 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9574 00:26:13.072216 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9575 00:26:13.075700 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9576 00:26:13.078888 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9577 00:26:13.085138 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9578 00:26:13.088862 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9579 00:26:13.092025 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9580 00:26:13.098807 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9581 00:26:13.101900 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9582 00:26:13.108678 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9583 00:26:13.112179 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9584 00:26:13.115250 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9585 00:26:13.121827 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9586 00:26:13.125363 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9587 00:26:13.128906 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9588 00:26:13.135414 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9589 00:26:13.138544 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9590 00:26:13.145608 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9591 00:26:13.148361 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9592 00:26:13.151905 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9593 00:26:13.158688 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9594 00:26:13.162403 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9595 00:26:13.165314 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9596 00:26:13.172236 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9597 00:26:13.175404 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9598 00:26:13.179374 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9599 00:26:13.182500 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9600 00:26:13.185541 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9601 00:26:13.192053 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9602 00:26:13.195677 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9603 00:26:13.202081 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9604 00:26:13.205761 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9605 00:26:13.208900 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9606 00:26:13.215415 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9607 00:26:13.219125 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9608 00:26:13.225591 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9609 00:26:13.229091 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9610 00:26:13.232008 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9611 00:26:13.238915 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9612 00:26:13.242320 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9613 00:26:13.245531 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9614 00:26:13.252600 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9615 00:26:13.255457 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9616 00:26:13.262459 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9617 00:26:13.265644 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9618 00:26:13.268875 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9619 00:26:13.275787 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9620 00:26:13.278907 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9621 00:26:13.282777 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9622 00:26:13.288925 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9623 00:26:13.292518 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9624 00:26:13.298949 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9625 00:26:13.302709 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9626 00:26:13.305842 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9627 00:26:13.312676 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9628 00:26:13.315526 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9629 00:26:13.322596 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9630 00:26:13.325962 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9631 00:26:13.329175 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9632 00:26:13.335447 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9633 00:26:13.338918 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9634 00:26:13.345532 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9635 00:26:13.348772 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9636 00:26:13.352189 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9637 00:26:13.359072 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9638 00:26:13.362548 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9639 00:26:13.365410 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9640 00:26:13.372307 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9641 00:26:13.375545 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9642 00:26:13.382390 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9643 00:26:13.385594 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9644 00:26:13.388920 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9645 00:26:13.395678 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9646 00:26:13.399065 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9647 00:26:13.405545 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9648 00:26:13.408836 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9649 00:26:13.412169 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9650 00:26:13.418736 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9651 00:26:13.422384 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9652 00:26:13.425620 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9653 00:26:13.431969 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9654 00:26:13.435253 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9655 00:26:13.442118 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9656 00:26:13.445610 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9657 00:26:13.448912 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9658 00:26:13.455440 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9659 00:26:13.458431 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9660 00:26:13.465305 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9661 00:26:13.468686 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9662 00:26:13.472188 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9663 00:26:13.478480 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9664 00:26:13.481915 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9665 00:26:13.488672 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9666 00:26:13.491772 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9667 00:26:13.495270 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9668 00:26:13.501797 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9669 00:26:13.505342 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9670 00:26:13.511502 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9671 00:26:13.515396 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9672 00:26:13.518525 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9673 00:26:13.524915 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9674 00:26:13.528533 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9675 00:26:13.535310 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9676 00:26:13.538419 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9677 00:26:13.545032 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9678 00:26:13.548069 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9679 00:26:13.551783 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9680 00:26:13.558499 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9681 00:26:13.562048 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9682 00:26:13.568342 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9683 00:26:13.571862 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9684 00:26:13.578236 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9685 00:26:13.581378 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9686 00:26:13.584979 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9687 00:26:13.591611 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9688 00:26:13.594907 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9689 00:26:13.601115 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9690 00:26:13.604871 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9691 00:26:13.608351 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9692 00:26:13.614621 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9693 00:26:13.618052 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9694 00:26:13.624822 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9695 00:26:13.628278 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9696 00:26:13.631716 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9697 00:26:13.637786 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9698 00:26:13.641430 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9699 00:26:13.648004 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9700 00:26:13.651310 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9701 00:26:13.658240 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9702 00:26:13.661466 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9703 00:26:13.664537 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9704 00:26:13.671348 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9705 00:26:13.674338 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9706 00:26:13.681216 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9707 00:26:13.684771 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9708 00:26:13.687748 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9709 00:26:13.691034 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9710 00:26:13.694189 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9711 00:26:13.700835 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9712 00:26:13.704608 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9713 00:26:13.710902 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9714 00:26:13.714306 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9715 00:26:13.717702 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9716 00:26:13.724227 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9717 00:26:13.727658 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9718 00:26:13.730923 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9719 00:26:13.737045 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9720 00:26:13.740678 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9721 00:26:13.744024 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9722 00:26:13.750623 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9723 00:26:13.754158 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9724 00:26:13.760358 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9725 00:26:13.763945 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9726 00:26:13.766996 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9727 00:26:13.773712 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9728 00:26:13.777052 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9729 00:26:13.780754 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9730 00:26:13.787000 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9731 00:26:13.790371 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9732 00:26:13.793964 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9733 00:26:13.800264 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9734 00:26:13.803740 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9735 00:26:13.810303 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9736 00:26:13.813613 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9737 00:26:13.817155 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9738 00:26:13.823834 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9739 00:26:13.826930 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9740 00:26:13.830455 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9741 00:26:13.837231 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9742 00:26:13.840630 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9743 00:26:13.844003 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9744 00:26:13.850460 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9745 00:26:13.853651 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9746 00:26:13.857021 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9747 00:26:13.864008 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9748 00:26:13.867001 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9749 00:26:13.870438 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9750 00:26:13.873832 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9751 00:26:13.877219 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9752 00:26:13.883799 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9753 00:26:13.886768 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9754 00:26:13.890445 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9755 00:26:13.896882 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9756 00:26:13.900333 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9757 00:26:13.903695 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9758 00:26:13.907235 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9759 00:26:13.913888 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9760 00:26:13.916902 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9761 00:26:13.923825 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9762 00:26:13.926757 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9763 00:26:13.930170 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9764 00:26:13.936505 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9765 00:26:13.939839 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9766 00:26:13.946932 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9767 00:26:13.950255 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9768 00:26:13.953616 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9769 00:26:13.960050 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9770 00:26:13.963654 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9771 00:26:13.970036 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9772 00:26:13.973770 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9773 00:26:13.979851 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9774 00:26:13.983264 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9775 00:26:13.986810 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9776 00:26:13.993715 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9777 00:26:13.996532 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9778 00:26:13.999922 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9779 00:26:14.007089 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9780 00:26:14.010371 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9781 00:26:14.016729 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9782 00:26:14.020275 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9783 00:26:14.023441 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9784 00:26:14.029795 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9785 00:26:14.033349 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9786 00:26:14.040190 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9787 00:26:14.043214 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9788 00:26:14.049871 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9789 00:26:14.053395 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9790 00:26:14.056274 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9791 00:26:14.063052 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9792 00:26:14.066620 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9793 00:26:14.072945 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9794 00:26:14.076363 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9795 00:26:14.079606 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9796 00:26:14.086176 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9797 00:26:14.089605 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9798 00:26:14.096941 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9799 00:26:14.099650 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9800 00:26:14.102994 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9801 00:26:14.109901 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9802 00:26:14.113326 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9803 00:26:14.120254 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9804 00:26:14.123071 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9805 00:26:14.129321 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9806 00:26:14.132788 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9807 00:26:14.136377 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9808 00:26:14.142993 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9809 00:26:14.146428 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9810 00:26:14.152415 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9811 00:26:14.156221 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9812 00:26:14.159158 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9813 00:26:14.165616 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9814 00:26:14.169060 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9815 00:26:14.176007 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9816 00:26:14.179090 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9817 00:26:14.182105 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9818 00:26:14.188751 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9819 00:26:14.191973 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9820 00:26:14.198940 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9821 00:26:14.202358 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9822 00:26:14.208787 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9823 00:26:14.212420 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9824 00:26:14.215303 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9825 00:26:14.222084 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9826 00:26:14.225682 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9827 00:26:14.232418 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9828 00:26:14.235237 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9829 00:26:14.238735 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9830 00:26:14.245259 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9831 00:26:14.248958 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9832 00:26:14.255785 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9833 00:26:14.258903 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9834 00:26:14.262089 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9835 00:26:14.268512 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9836 00:26:14.272151 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9837 00:26:14.278946 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9838 00:26:14.281818 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9839 00:26:14.288735 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9840 00:26:14.291842 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9841 00:26:14.295422 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9842 00:26:14.302199 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9843 00:26:14.305331 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9844 00:26:14.311786 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9845 00:26:14.315412 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9846 00:26:14.322005 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9847 00:26:14.325464 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9848 00:26:14.328781 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9849 00:26:14.335363 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9850 00:26:14.338691 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9851 00:26:14.345615 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9852 00:26:14.348591 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9853 00:26:14.355030 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9854 00:26:14.358494 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9855 00:26:14.361988 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9856 00:26:14.368357 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9857 00:26:14.372152 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9858 00:26:14.378991 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9859 00:26:14.381910 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9860 00:26:14.388668 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9861 00:26:14.391799 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9862 00:26:14.398337 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9863 00:26:14.401668 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9864 00:26:14.405012 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9865 00:26:14.412030 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9866 00:26:14.415286 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9867 00:26:14.421708 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9868 00:26:14.424895 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9869 00:26:14.431943 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9870 00:26:14.434774 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9871 00:26:14.438200 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9872 00:26:14.445000 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9873 00:26:14.448414 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9874 00:26:14.455287 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9875 00:26:14.458072 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9876 00:26:14.464653 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9877 00:26:14.468378 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9878 00:26:14.474580 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9879 00:26:14.478217 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9880 00:26:14.481563 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9881 00:26:14.488416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9882 00:26:14.491856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9883 00:26:14.497966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9884 00:26:14.501658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9885 00:26:14.504739 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9886 00:26:14.511416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9887 00:26:14.514955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9888 00:26:14.521691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9889 00:26:14.524592 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9890 00:26:14.531667 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9891 00:26:14.535023 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9892 00:26:14.541362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9893 00:26:14.544793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9894 00:26:14.551652 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9895 00:26:14.554868 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9896 00:26:14.561527 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9897 00:26:14.564502 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9898 00:26:14.571140 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9899 00:26:14.574434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9900 00:26:14.581315 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9901 00:26:14.584600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9902 00:26:14.591112 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9903 00:26:14.594360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9904 00:26:14.601206 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9905 00:26:14.604594 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9906 00:26:14.611456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9907 00:26:14.614461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9908 00:26:14.620970 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9909 00:26:14.624154 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9910 00:26:14.630855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9911 00:26:14.634302 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9912 00:26:14.640686 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9913 00:26:14.640768 INFO: [APUAPC] vio 0
9914 00:26:14.647264 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9915 00:26:14.650807 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9916 00:26:14.654200 INFO: [APUAPC] D0_APC_0: 0x400510
9917 00:26:14.657163 INFO: [APUAPC] D0_APC_1: 0x0
9918 00:26:14.660492 INFO: [APUAPC] D0_APC_2: 0x1540
9919 00:26:14.663845 INFO: [APUAPC] D0_APC_3: 0x0
9920 00:26:14.667367 INFO: [APUAPC] D1_APC_0: 0xffffffff
9921 00:26:14.670780 INFO: [APUAPC] D1_APC_1: 0xffffffff
9922 00:26:14.674068 INFO: [APUAPC] D1_APC_2: 0x3fffff
9923 00:26:14.677223 INFO: [APUAPC] D1_APC_3: 0x0
9924 00:26:14.680317 INFO: [APUAPC] D2_APC_0: 0xffffffff
9925 00:26:14.683712 INFO: [APUAPC] D2_APC_1: 0xffffffff
9926 00:26:14.687181 INFO: [APUAPC] D2_APC_2: 0x3fffff
9927 00:26:14.690702 INFO: [APUAPC] D2_APC_3: 0x0
9928 00:26:14.694201 INFO: [APUAPC] D3_APC_0: 0xffffffff
9929 00:26:14.697589 INFO: [APUAPC] D3_APC_1: 0xffffffff
9930 00:26:14.700415 INFO: [APUAPC] D3_APC_2: 0x3fffff
9931 00:26:14.700489 INFO: [APUAPC] D3_APC_3: 0x0
9932 00:26:14.707010 INFO: [APUAPC] D4_APC_0: 0xffffffff
9933 00:26:14.710307 INFO: [APUAPC] D4_APC_1: 0xffffffff
9934 00:26:14.713574 INFO: [APUAPC] D4_APC_2: 0x3fffff
9935 00:26:14.713683 INFO: [APUAPC] D4_APC_3: 0x0
9936 00:26:14.717322 INFO: [APUAPC] D5_APC_0: 0xffffffff
9937 00:26:14.720289 INFO: [APUAPC] D5_APC_1: 0xffffffff
9938 00:26:14.723779 INFO: [APUAPC] D5_APC_2: 0x3fffff
9939 00:26:14.727179 INFO: [APUAPC] D5_APC_3: 0x0
9940 00:26:14.730209 INFO: [APUAPC] D6_APC_0: 0xffffffff
9941 00:26:14.733732 INFO: [APUAPC] D6_APC_1: 0xffffffff
9942 00:26:14.736957 INFO: [APUAPC] D6_APC_2: 0x3fffff
9943 00:26:14.740302 INFO: [APUAPC] D6_APC_3: 0x0
9944 00:26:14.743629 INFO: [APUAPC] D7_APC_0: 0xffffffff
9945 00:26:14.747113 INFO: [APUAPC] D7_APC_1: 0xffffffff
9946 00:26:14.750394 INFO: [APUAPC] D7_APC_2: 0x3fffff
9947 00:26:14.753544 INFO: [APUAPC] D7_APC_3: 0x0
9948 00:26:14.756847 INFO: [APUAPC] D8_APC_0: 0xffffffff
9949 00:26:14.760148 INFO: [APUAPC] D8_APC_1: 0xffffffff
9950 00:26:14.763809 INFO: [APUAPC] D8_APC_2: 0x3fffff
9951 00:26:14.767063 INFO: [APUAPC] D8_APC_3: 0x0
9952 00:26:14.770531 INFO: [APUAPC] D9_APC_0: 0xffffffff
9953 00:26:14.773548 INFO: [APUAPC] D9_APC_1: 0xffffffff
9954 00:26:14.776867 INFO: [APUAPC] D9_APC_2: 0x3fffff
9955 00:26:14.780278 INFO: [APUAPC] D9_APC_3: 0x0
9956 00:26:14.783589 INFO: [APUAPC] D10_APC_0: 0xffffffff
9957 00:26:14.786903 INFO: [APUAPC] D10_APC_1: 0xffffffff
9958 00:26:14.790435 INFO: [APUAPC] D10_APC_2: 0x3fffff
9959 00:26:14.793277 INFO: [APUAPC] D10_APC_3: 0x0
9960 00:26:14.796961 INFO: [APUAPC] D11_APC_0: 0xffffffff
9961 00:26:14.800100 INFO: [APUAPC] D11_APC_1: 0xffffffff
9962 00:26:14.803178 INFO: [APUAPC] D11_APC_2: 0x3fffff
9963 00:26:14.807280 INFO: [APUAPC] D11_APC_3: 0x0
9964 00:26:14.810223 INFO: [APUAPC] D12_APC_0: 0xffffffff
9965 00:26:14.813724 INFO: [APUAPC] D12_APC_1: 0xffffffff
9966 00:26:14.816918 INFO: [APUAPC] D12_APC_2: 0x3fffff
9967 00:26:14.820203 INFO: [APUAPC] D12_APC_3: 0x0
9968 00:26:14.823410 INFO: [APUAPC] D13_APC_0: 0xffffffff
9969 00:26:14.826695 INFO: [APUAPC] D13_APC_1: 0xffffffff
9970 00:26:14.830322 INFO: [APUAPC] D13_APC_2: 0x3fffff
9971 00:26:14.833124 INFO: [APUAPC] D13_APC_3: 0x0
9972 00:26:14.836465 INFO: [APUAPC] D14_APC_0: 0xffffffff
9973 00:26:14.840316 INFO: [APUAPC] D14_APC_1: 0xffffffff
9974 00:26:14.843355 INFO: [APUAPC] D14_APC_2: 0x3fffff
9975 00:26:14.847162 INFO: [APUAPC] D14_APC_3: 0x0
9976 00:26:14.849772 INFO: [APUAPC] D15_APC_0: 0xffffffff
9977 00:26:14.853450 INFO: [APUAPC] D15_APC_1: 0xffffffff
9978 00:26:14.856710 INFO: [APUAPC] D15_APC_2: 0x3fffff
9979 00:26:14.859624 INFO: [APUAPC] D15_APC_3: 0x0
9980 00:26:14.863407 INFO: [APUAPC] APC_CON: 0x4
9981 00:26:14.866404 INFO: [NOCDAPC] D0_APC_0: 0x0
9982 00:26:14.869750 INFO: [NOCDAPC] D0_APC_1: 0x0
9983 00:26:14.872942 INFO: [NOCDAPC] D1_APC_0: 0x0
9984 00:26:14.876765 INFO: [NOCDAPC] D1_APC_1: 0xfff
9985 00:26:14.876846 INFO: [NOCDAPC] D2_APC_0: 0x0
9986 00:26:14.879819 INFO: [NOCDAPC] D2_APC_1: 0xfff
9987 00:26:14.883162 INFO: [NOCDAPC] D3_APC_0: 0x0
9988 00:26:14.886391 INFO: [NOCDAPC] D3_APC_1: 0xfff
9989 00:26:14.889620 INFO: [NOCDAPC] D4_APC_0: 0x0
9990 00:26:14.893120 INFO: [NOCDAPC] D4_APC_1: 0xfff
9991 00:26:14.896551 INFO: [NOCDAPC] D5_APC_0: 0x0
9992 00:26:14.899805 INFO: [NOCDAPC] D5_APC_1: 0xfff
9993 00:26:14.903167 INFO: [NOCDAPC] D6_APC_0: 0x0
9994 00:26:14.906385 INFO: [NOCDAPC] D6_APC_1: 0xfff
9995 00:26:14.906458 INFO: [NOCDAPC] D7_APC_0: 0x0
9996 00:26:14.909603 INFO: [NOCDAPC] D7_APC_1: 0xfff
9997 00:26:14.913230 INFO: [NOCDAPC] D8_APC_0: 0x0
9998 00:26:14.916539 INFO: [NOCDAPC] D8_APC_1: 0xfff
9999 00:26:14.919869 INFO: [NOCDAPC] D9_APC_0: 0x0
10000 00:26:14.923606 INFO: [NOCDAPC] D9_APC_1: 0xfff
10001 00:26:14.926797 INFO: [NOCDAPC] D10_APC_0: 0x0
10002 00:26:14.929986 INFO: [NOCDAPC] D10_APC_1: 0xfff
10003 00:26:14.933007 INFO: [NOCDAPC] D11_APC_0: 0x0
10004 00:26:14.936369 INFO: [NOCDAPC] D11_APC_1: 0xfff
10005 00:26:14.939967 INFO: [NOCDAPC] D12_APC_0: 0x0
10006 00:26:14.943109 INFO: [NOCDAPC] D12_APC_1: 0xfff
10007 00:26:14.946457 INFO: [NOCDAPC] D13_APC_0: 0x0
10008 00:26:14.946538 INFO: [NOCDAPC] D13_APC_1: 0xfff
10009 00:26:14.949667 INFO: [NOCDAPC] D14_APC_0: 0x0
10010 00:26:14.953246 INFO: [NOCDAPC] D14_APC_1: 0xfff
10011 00:26:14.956316 INFO: [NOCDAPC] D15_APC_0: 0x0
10012 00:26:14.959866 INFO: [NOCDAPC] D15_APC_1: 0xfff
10013 00:26:14.963502 INFO: [NOCDAPC] APC_CON: 0x4
10014 00:26:14.966839 INFO: [APUAPC] set_apusys_apc done
10015 00:26:14.969759 INFO: [DEVAPC] devapc_init done
10016 00:26:14.973141 INFO: GICv3 without legacy support detected.
10017 00:26:14.976479 INFO: ARM GICv3 driver initialized in EL3
10018 00:26:14.983172 INFO: Maximum SPI INTID supported: 639
10019 00:26:14.986277 INFO: BL31: Initializing runtime services
10020 00:26:14.992946 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10021 00:26:14.993029 INFO: SPM: enable CPC mode
10022 00:26:14.999323 INFO: mcdi ready for mcusys-off-idle and system suspend
10023 00:26:15.002733 INFO: BL31: Preparing for EL3 exit to normal world
10024 00:26:15.006141 INFO: Entry point address = 0x80000000
10025 00:26:15.009875 INFO: SPSR = 0x8
10026 00:26:15.015237
10027 00:26:15.015321
10028 00:26:15.015387
10029 00:26:15.018585 Starting depthcharge on Spherion...
10030 00:26:15.018687
10031 00:26:15.018778 Wipe memory regions:
10032 00:26:15.018867
10033 00:26:15.019839 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10034 00:26:15.020010 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10035 00:26:15.020121 Setting prompt string to ['asurada:']
10036 00:26:15.020280 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10037 00:26:15.022137 [0x00000040000000, 0x00000054600000)
10038 00:26:15.144178
10039 00:26:15.144331 [0x00000054660000, 0x00000080000000)
10040 00:26:15.404903
10041 00:26:15.405061 [0x000000821a7280, 0x000000ffe64000)
10042 00:26:16.149697
10043 00:26:16.149870 [0x00000100000000, 0x00000240000000)
10044 00:26:18.040028
10045 00:26:18.043437 Initializing XHCI USB controller at 0x11200000.
10046 00:26:19.081878
10047 00:26:19.084754 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10048 00:26:19.084845
10049 00:26:19.084928
10050 00:26:19.085006
10051 00:26:19.085303 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10053 00:26:19.185703 asurada: tftpboot 192.168.201.1 11280962/tftp-deploy-apdiwvfj/kernel/image.itb 11280962/tftp-deploy-apdiwvfj/kernel/cmdline
10054 00:26:19.185840 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10055 00:26:19.185943 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10056 00:26:19.190193 tftpboot 192.168.201.1 11280962/tftp-deploy-apdiwvfj/kernel/image.ittp-deploy-apdiwvfj/kernel/cmdline
10057 00:26:19.190279
10058 00:26:19.190362 Waiting for link
10059 00:26:19.348355
10060 00:26:19.348478 R8152: Initializing
10061 00:26:19.348570
10062 00:26:19.351953 Version 9 (ocp_data = 6010)
10063 00:26:19.352042
10064 00:26:19.355125 R8152: Done initializing
10065 00:26:19.355226
10066 00:26:19.355308 Adding net device
10067 00:26:21.230441
10068 00:26:21.230935 done.
10069 00:26:21.231275
10070 00:26:21.231706 MAC: 00:e0:4c:78:7a:aa
10071 00:26:21.232030
10072 00:26:21.233690 Sending DHCP discover... done.
10073 00:26:21.234124
10074 00:26:21.237012 Waiting for reply... done.
10075 00:26:21.237432
10076 00:26:21.240296 Sending DHCP request... done.
10077 00:26:21.240715
10078 00:26:21.246664 Waiting for reply... done.
10079 00:26:21.247083
10080 00:26:21.247416 My ip is 192.168.201.12
10081 00:26:21.247752
10082 00:26:21.249469 The DHCP server ip is 192.168.201.1
10083 00:26:21.249890
10084 00:26:21.255987 TFTP server IP predefined by user: 192.168.201.1
10085 00:26:21.256407
10086 00:26:21.262853 Bootfile predefined by user: 11280962/tftp-deploy-apdiwvfj/kernel/image.itb
10087 00:26:21.263274
10088 00:26:21.265765 Sending tftp read request... done.
10089 00:26:21.266183
10090 00:26:21.272608 Waiting for the transfer...
10091 00:26:21.273025
10092 00:26:21.559672 00000000 ################################################################
10093 00:26:21.559806
10094 00:26:21.823707 00080000 ################################################################
10095 00:26:21.823846
10096 00:26:22.070572 00100000 ################################################################
10097 00:26:22.070709
10098 00:26:22.332342 00180000 ################################################################
10099 00:26:22.332515
10100 00:26:22.579449 00200000 ################################################################
10101 00:26:22.579629
10102 00:26:22.846607 00280000 ################################################################
10103 00:26:22.846743
10104 00:26:23.120153 00300000 ################################################################
10105 00:26:23.120289
10106 00:26:23.367459 00380000 ################################################################
10107 00:26:23.367595
10108 00:26:23.617271 00400000 ################################################################
10109 00:26:23.617406
10110 00:26:23.863381 00480000 ################################################################
10111 00:26:23.863535
10112 00:26:24.113923 00500000 ################################################################
10113 00:26:24.114069
10114 00:26:24.366249 00580000 ################################################################
10115 00:26:24.366394
10116 00:26:24.614209 00600000 ################################################################
10117 00:26:24.614353
10118 00:26:24.863693 00680000 ################################################################
10119 00:26:24.863834
10120 00:26:25.107468 00700000 ################################################################
10121 00:26:25.107651
10122 00:26:25.352553 00780000 ################################################################
10123 00:26:25.352694
10124 00:26:25.596213 00800000 ################################################################
10125 00:26:25.596350
10126 00:26:25.841297 00880000 ################################################################
10127 00:26:25.841435
10128 00:26:26.089042 00900000 ################################################################
10129 00:26:26.089174
10130 00:26:26.341926 00980000 ################################################################
10131 00:26:26.342063
10132 00:26:26.591108 00a00000 ################################################################
10133 00:26:26.591235
10134 00:26:26.842903 00a80000 ################################################################
10135 00:26:26.843033
10136 00:26:27.089471 00b00000 ################################################################
10137 00:26:27.089596
10138 00:26:27.339699 00b80000 ################################################################
10139 00:26:27.339859
10140 00:26:27.589323 00c00000 ################################################################
10141 00:26:27.589456
10142 00:26:27.833241 00c80000 ################################################################
10143 00:26:27.833389
10144 00:26:28.080505 00d00000 ################################################################
10145 00:26:28.080650
10146 00:26:28.326621 00d80000 ################################################################
10147 00:26:28.326788
10148 00:26:28.576440 00e00000 ################################################################
10149 00:26:28.576588
10150 00:26:28.831581 00e80000 ################################################################
10151 00:26:28.831730
10152 00:26:29.081055 00f00000 ################################################################
10153 00:26:29.081190
10154 00:26:29.329446 00f80000 ################################################################
10155 00:26:29.329590
10156 00:26:29.578957 01000000 ################################################################
10157 00:26:29.579094
10158 00:26:29.827426 01080000 ################################################################
10159 00:26:29.827612
10160 00:26:30.075188 01100000 ################################################################
10161 00:26:30.075329
10162 00:26:30.337149 01180000 ################################################################
10163 00:26:30.337287
10164 00:26:30.618206 01200000 ################################################################
10165 00:26:30.618340
10166 00:26:30.893527 01280000 ################################################################
10167 00:26:30.893667
10168 00:26:31.179996 01300000 ################################################################
10169 00:26:31.180202
10170 00:26:31.465436 01380000 ################################################################
10171 00:26:31.465574
10172 00:26:31.742298 01400000 ################################################################
10173 00:26:31.742435
10174 00:26:32.023728 01480000 ################################################################
10175 00:26:32.023859
10176 00:26:32.275808 01500000 ################################################################
10177 00:26:32.275949
10178 00:26:32.532240 01580000 ################################################################
10179 00:26:32.532374
10180 00:26:32.811173 01600000 ################################################################
10181 00:26:32.811306
10182 00:26:33.092323 01680000 ################################################################
10183 00:26:33.092460
10184 00:26:33.343098 01700000 ################################################################
10185 00:26:33.343225
10186 00:26:33.598183 01780000 ################################################################
10187 00:26:33.598312
10188 00:26:33.864012 01800000 ################################################################
10189 00:26:33.864147
10190 00:26:34.143338 01880000 ################################################################
10191 00:26:34.143472
10192 00:26:34.408236 01900000 ################################################################
10193 00:26:34.408364
10194 00:26:34.671956 01980000 ################################################################
10195 00:26:34.672092
10196 00:26:34.961694 01a00000 ################################################################
10197 00:26:34.961825
10198 00:26:35.227486 01a80000 ################################################################
10199 00:26:35.227678
10200 00:26:35.486259 01b00000 ################################################################
10201 00:26:35.486387
10202 00:26:35.744915 01b80000 ################################################################
10203 00:26:35.745050
10204 00:26:36.004485 01c00000 ################################################################
10205 00:26:36.004617
10206 00:26:36.268357 01c80000 ################################################################
10207 00:26:36.268483
10208 00:26:36.532227 01d00000 ################################################################
10209 00:26:36.532352
10210 00:26:36.792180 01d80000 ################################################################
10211 00:26:36.792317
10212 00:26:37.058366 01e00000 ################################################################
10213 00:26:37.058544
10214 00:26:37.244453 01e80000 ############################################## done.
10215 00:26:37.244584
10216 00:26:37.247915 The bootfile was 32358182 bytes long.
10217 00:26:37.248005
10218 00:26:37.251208 Sending tftp read request... done.
10219 00:26:37.251334
10220 00:26:37.251448 Waiting for the transfer...
10221 00:26:37.251568
10222 00:26:37.254585 00000000 # done.
10223 00:26:37.254683
10224 00:26:37.260849 Command line loaded dynamically from TFTP file: 11280962/tftp-deploy-apdiwvfj/kernel/cmdline
10225 00:26:37.260964
10226 00:26:37.274469 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10227 00:26:37.274609
10228 00:26:37.277538 Loading FIT.
10229 00:26:37.277691
10230 00:26:37.280997 Image ramdisk-1 has 21271556 bytes.
10231 00:26:37.281172
10232 00:26:37.281350 Image fdt-1 has 47278 bytes.
10233 00:26:37.281517
10234 00:26:37.284359 Image kernel-1 has 11037315 bytes.
10235 00:26:37.284533
10236 00:26:37.294460 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10237 00:26:37.294775
10238 00:26:37.311288 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10239 00:26:37.311887
10240 00:26:37.317835 Choosing best match conf-1 for compat google,spherion-rev2.
10241 00:26:37.322222
10242 00:26:37.326658 Connected to device vid:did:rid of 1ae0:0028:00
10243 00:26:37.334800
10244 00:26:37.338248 tpm_get_response: command 0x17b, return code 0x0
10245 00:26:37.338775
10246 00:26:37.341003 ec_init: CrosEC protocol v3 supported (256, 248)
10247 00:26:37.345460
10248 00:26:37.349139 tpm_cleanup: add release locality here.
10249 00:26:37.349666
10250 00:26:37.350103 Shutting down all USB controllers.
10251 00:26:37.350517
10252 00:26:37.352007 Removing current net device
10253 00:26:37.352378
10254 00:26:37.358988 Exiting depthcharge with code 4 at timestamp: 51668564
10255 00:26:37.359585
10256 00:26:37.362023 LZMA decompressing kernel-1 to 0x821a6718
10257 00:26:37.362450
10258 00:26:37.365127 LZMA decompressing kernel-1 to 0x40000000
10259 00:26:38.753097
10260 00:26:38.753586 jumping to kernel
10261 00:26:38.755664 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10262 00:26:38.756345 start: 2.2.5 auto-login-action (timeout 00:04:01) [common]
10263 00:26:38.756867 Setting prompt string to ['Linux version [0-9]']
10264 00:26:38.757352 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10265 00:26:38.757872 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10266 00:26:38.835775
10267 00:26:38.838622 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10268 00:26:38.842641 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10269 00:26:38.843114 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10270 00:26:38.843815 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10271 00:26:38.844328 Using line separator: #'\n'#
10272 00:26:38.844665 No login prompt set.
10273 00:26:38.844984 Parsing kernel messages
10274 00:26:38.845266 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10275 00:26:38.845825 [login-action] Waiting for messages, (timeout 00:04:01)
10276 00:26:38.862568 [ 0.000000] Linux version 6.1.45-cip3 (KernelCI@build-j12530-arm64-gcc-10-defconfig-arm64-chromebook-5rwxg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Aug 14 00:09:07 UTC 2023
10277 00:26:38.866096 [ 0.000000] random: crng init done
10278 00:26:38.868615 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10279 00:26:38.872330 [ 0.000000] efi: UEFI not found.
10280 00:26:38.882484 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10281 00:26:38.889206 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10282 00:26:38.898993 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10283 00:26:38.908704 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10284 00:26:38.915633 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10285 00:26:38.918873 [ 0.000000] printk: bootconsole [mtk8250] enabled
10286 00:26:38.927483 [ 0.000000] NUMA: No NUMA configuration found
10287 00:26:38.933721 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10288 00:26:38.940972 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10289 00:26:38.941432 [ 0.000000] Zone ranges:
10290 00:26:38.947616 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10291 00:26:38.950620 [ 0.000000] DMA32 empty
10292 00:26:38.957311 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10293 00:26:38.960519 [ 0.000000] Movable zone start for each node
10294 00:26:38.963710 [ 0.000000] Early memory node ranges
10295 00:26:38.970724 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10296 00:26:38.977066 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10297 00:26:38.984042 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10298 00:26:38.990844 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10299 00:26:38.997295 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10300 00:26:39.003576 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10301 00:26:39.059721 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10302 00:26:39.066340 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10303 00:26:39.073109 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10304 00:26:39.076155 [ 0.000000] psci: probing for conduit method from DT.
10305 00:26:39.083060 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10306 00:26:39.086551 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10307 00:26:39.093144 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10308 00:26:39.096632 [ 0.000000] psci: SMC Calling Convention v1.2
10309 00:26:39.102882 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10310 00:26:39.106697 [ 0.000000] Detected VIPT I-cache on CPU0
10311 00:26:39.113059 [ 0.000000] CPU features: detected: GIC system register CPU interface
10312 00:26:39.119874 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10313 00:26:39.126180 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10314 00:26:39.133212 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10315 00:26:39.139845 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10316 00:26:39.146123 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10317 00:26:39.153014 [ 0.000000] alternatives: applying boot alternatives
10318 00:26:39.156672 [ 0.000000] Fallback order for Node 0: 0
10319 00:26:39.166428 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10320 00:26:39.166947 [ 0.000000] Policy zone: Normal
10321 00:26:39.182510 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10322 00:26:39.192283 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10323 00:26:39.204037 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10324 00:26:39.214510 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10325 00:26:39.221026 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10326 00:26:39.224440 <6>[ 0.000000] software IO TLB: area num 8.
10327 00:26:39.280970 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10328 00:26:39.430127 <6>[ 0.000000] Memory: 7948784K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 403984K reserved, 32768K cma-reserved)
10329 00:26:39.436974 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10330 00:26:39.443646 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10331 00:26:39.446742 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10332 00:26:39.453849 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10333 00:26:39.460252 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10334 00:26:39.463675 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10335 00:26:39.473537 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10336 00:26:39.480398 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10337 00:26:39.484065 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10338 00:26:39.491458 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10339 00:26:39.494669 <6>[ 0.000000] GICv3: 608 SPIs implemented
10340 00:26:39.500994 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10341 00:26:39.504612 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10342 00:26:39.507267 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10343 00:26:39.517893 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10344 00:26:39.527638 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10345 00:26:39.540919 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10346 00:26:39.547451 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10347 00:26:39.556678 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10348 00:26:39.570195 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10349 00:26:39.576747 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10350 00:26:39.583610 <6>[ 0.009233] Console: colour dummy device 80x25
10351 00:26:39.593000 <6>[ 0.013957] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10352 00:26:39.599762 <6>[ 0.024399] pid_max: default: 32768 minimum: 301
10353 00:26:39.603315 <6>[ 0.029301] LSM: Security Framework initializing
10354 00:26:39.610337 <6>[ 0.034268] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10355 00:26:39.619495 <6>[ 0.042129] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10356 00:26:39.629515 <6>[ 0.051561] cblist_init_generic: Setting adjustable number of callback queues.
10357 00:26:39.632940 <6>[ 0.059052] cblist_init_generic: Setting shift to 3 and lim to 1.
10358 00:26:39.642877 <6>[ 0.065390] cblist_init_generic: Setting adjustable number of callback queues.
10359 00:26:39.649542 <6>[ 0.072862] cblist_init_generic: Setting shift to 3 and lim to 1.
10360 00:26:39.652682 <6>[ 0.079260] rcu: Hierarchical SRCU implementation.
10361 00:26:39.659614 <6>[ 0.084304] rcu: Max phase no-delay instances is 1000.
10362 00:26:39.666221 <6>[ 0.091336] EFI services will not be available.
10363 00:26:39.669688 <6>[ 0.096308] smp: Bringing up secondary CPUs ...
10364 00:26:39.677909 <6>[ 0.101366] Detected VIPT I-cache on CPU1
10365 00:26:39.684385 <6>[ 0.101435] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10366 00:26:39.691255 <6>[ 0.101466] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10367 00:26:39.694671 <6>[ 0.101798] Detected VIPT I-cache on CPU2
10368 00:26:39.701026 <6>[ 0.101849] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10369 00:26:39.707961 <6>[ 0.101865] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10370 00:26:39.714743 <6>[ 0.102123] Detected VIPT I-cache on CPU3
10371 00:26:39.720948 <6>[ 0.102172] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10372 00:26:39.728039 <6>[ 0.102186] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10373 00:26:39.731667 <6>[ 0.102491] CPU features: detected: Spectre-v4
10374 00:26:39.738185 <6>[ 0.102497] CPU features: detected: Spectre-BHB
10375 00:26:39.741336 <6>[ 0.102501] Detected PIPT I-cache on CPU4
10376 00:26:39.747786 <6>[ 0.102559] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10377 00:26:39.754788 <6>[ 0.102577] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10378 00:26:39.757490 <6>[ 0.102871] Detected PIPT I-cache on CPU5
10379 00:26:39.767827 <6>[ 0.102934] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10380 00:26:39.773825 <6>[ 0.102951] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10381 00:26:39.777021 <6>[ 0.103234] Detected PIPT I-cache on CPU6
10382 00:26:39.783860 <6>[ 0.103296] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10383 00:26:39.790440 <6>[ 0.103313] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10384 00:26:39.797236 <6>[ 0.103614] Detected PIPT I-cache on CPU7
10385 00:26:39.803527 <6>[ 0.103679] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10386 00:26:39.810409 <6>[ 0.103695] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10387 00:26:39.813741 <6>[ 0.103742] smp: Brought up 1 node, 8 CPUs
10388 00:26:39.820089 <6>[ 0.245123] SMP: Total of 8 processors activated.
10389 00:26:39.823717 <6>[ 0.250044] CPU features: detected: 32-bit EL0 Support
10390 00:26:39.833463 <6>[ 0.255407] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10391 00:26:39.839870 <6>[ 0.264262] CPU features: detected: Common not Private translations
10392 00:26:39.843321 <6>[ 0.270738] CPU features: detected: CRC32 instructions
10393 00:26:39.850118 <6>[ 0.276089] CPU features: detected: RCpc load-acquire (LDAPR)
10394 00:26:39.857053 <6>[ 0.282079] CPU features: detected: LSE atomic instructions
10395 00:26:39.863297 <6>[ 0.287896] CPU features: detected: Privileged Access Never
10396 00:26:39.866611 <6>[ 0.293676] CPU features: detected: RAS Extension Support
10397 00:26:39.876853 <6>[ 0.299285] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10398 00:26:39.880112 <6>[ 0.306506] CPU: All CPU(s) started at EL2
10399 00:26:39.886857 <6>[ 0.310823] alternatives: applying system-wide alternatives
10400 00:26:39.895468 <6>[ 0.321540] devtmpfs: initialized
10401 00:26:39.907653 <6>[ 0.330387] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10402 00:26:39.917569 <6>[ 0.340349] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10403 00:26:39.923985 <6>[ 0.348496] pinctrl core: initialized pinctrl subsystem
10404 00:26:39.927751 <6>[ 0.355176] DMI not present or invalid.
10405 00:26:39.934008 <6>[ 0.359494] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10406 00:26:39.944093 <6>[ 0.366342] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10407 00:26:39.950721 <6>[ 0.373920] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10408 00:26:39.960926 <6>[ 0.382139] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10409 00:26:39.964095 <6>[ 0.390382] audit: initializing netlink subsys (disabled)
10410 00:26:39.973777 <5>[ 0.396077] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10411 00:26:39.980050 <6>[ 0.396790] thermal_sys: Registered thermal governor 'step_wise'
10412 00:26:39.986946 <6>[ 0.404046] thermal_sys: Registered thermal governor 'power_allocator'
10413 00:26:39.990052 <6>[ 0.410303] cpuidle: using governor menu
10414 00:26:39.997120 <6>[ 0.421263] NET: Registered PF_QIPCRTR protocol family
10415 00:26:40.003845 <6>[ 0.426733] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10416 00:26:40.006792 <6>[ 0.433837] ASID allocator initialised with 32768 entries
10417 00:26:40.013824 <6>[ 0.440408] Serial: AMBA PL011 UART driver
10418 00:26:40.022675 <4>[ 0.449227] Trying to register duplicate clock ID: 134
10419 00:26:40.076972 <6>[ 0.506753] KASLR enabled
10420 00:26:40.091297 <6>[ 0.514482] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10421 00:26:40.098286 <6>[ 0.521497] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10422 00:26:40.105080 <6>[ 0.527988] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10423 00:26:40.111559 <6>[ 0.534994] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10424 00:26:40.117815 <6>[ 0.541479] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10425 00:26:40.124424 <6>[ 0.548484] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10426 00:26:40.131149 <6>[ 0.554970] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10427 00:26:40.138019 <6>[ 0.561977] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10428 00:26:40.141208 <6>[ 0.569487] ACPI: Interpreter disabled.
10429 00:26:40.149416 <6>[ 0.575891] iommu: Default domain type: Translated
10430 00:26:40.156346 <6>[ 0.581004] iommu: DMA domain TLB invalidation policy: strict mode
10431 00:26:40.159650 <5>[ 0.587658] SCSI subsystem initialized
10432 00:26:40.166061 <6>[ 0.591820] usbcore: registered new interface driver usbfs
10433 00:26:40.172400 <6>[ 0.597550] usbcore: registered new interface driver hub
10434 00:26:40.175909 <6>[ 0.603101] usbcore: registered new device driver usb
10435 00:26:40.182900 <6>[ 0.609193] pps_core: LinuxPPS API ver. 1 registered
10436 00:26:40.192667 <6>[ 0.614386] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10437 00:26:40.195947 <6>[ 0.623731] PTP clock support registered
10438 00:26:40.199464 <6>[ 0.627977] EDAC MC: Ver: 3.0.0
10439 00:26:40.207029 <6>[ 0.633130] FPGA manager framework
10440 00:26:40.210352 <6>[ 0.636809] Advanced Linux Sound Architecture Driver Initialized.
10441 00:26:40.213709 <6>[ 0.643580] vgaarb: loaded
10442 00:26:40.220543 <6>[ 0.646751] clocksource: Switched to clocksource arch_sys_counter
10443 00:26:40.227196 <5>[ 0.653179] VFS: Disk quotas dquot_6.6.0
10444 00:26:40.234040 <6>[ 0.657364] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10445 00:26:40.237063 <6>[ 0.664555] pnp: PnP ACPI: disabled
10446 00:26:40.244651 <6>[ 0.671208] NET: Registered PF_INET protocol family
10447 00:26:40.254735 <6>[ 0.676795] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10448 00:26:40.266230 <6>[ 0.689100] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10449 00:26:40.276070 <6>[ 0.697918] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10450 00:26:40.282855 <6>[ 0.705889] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10451 00:26:40.289303 <6>[ 0.714589] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10452 00:26:40.301669 <6>[ 0.724333] TCP: Hash tables configured (established 65536 bind 65536)
10453 00:26:40.308165 <6>[ 0.731193] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10454 00:26:40.314693 <6>[ 0.738394] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10455 00:26:40.321616 <6>[ 0.746093] NET: Registered PF_UNIX/PF_LOCAL protocol family
10456 00:26:40.328081 <6>[ 0.752260] RPC: Registered named UNIX socket transport module.
10457 00:26:40.331291 <6>[ 0.758414] RPC: Registered udp transport module.
10458 00:26:40.338332 <6>[ 0.763347] RPC: Registered tcp transport module.
10459 00:26:40.344692 <6>[ 0.768279] RPC: Registered tcp NFSv4.1 backchannel transport module.
10460 00:26:40.347498 <6>[ 0.774949] PCI: CLS 0 bytes, default 64
10461 00:26:40.351365 <6>[ 0.779355] Unpacking initramfs...
10462 00:26:40.372301 <6>[ 0.795232] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10463 00:26:40.382160 <6>[ 0.803881] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10464 00:26:40.385589 <6>[ 0.812736] kvm [1]: IPA Size Limit: 40 bits
10465 00:26:40.392025 <6>[ 0.817264] kvm [1]: GICv3: no GICV resource entry
10466 00:26:40.395194 <6>[ 0.822286] kvm [1]: disabling GICv2 emulation
10467 00:26:40.402536 <6>[ 0.826971] kvm [1]: GIC system register CPU interface enabled
10468 00:26:40.405204 <6>[ 0.833135] kvm [1]: vgic interrupt IRQ18
10469 00:26:40.412294 <6>[ 0.837486] kvm [1]: VHE mode initialized successfully
10470 00:26:40.418761 <5>[ 0.843984] Initialise system trusted keyrings
10471 00:26:40.425206 <6>[ 0.848800] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10472 00:26:40.432721 <6>[ 0.858791] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10473 00:26:40.439200 <5>[ 0.865170] NFS: Registering the id_resolver key type
10474 00:26:40.442568 <5>[ 0.870471] Key type id_resolver registered
10475 00:26:40.448797 <5>[ 0.874887] Key type id_legacy registered
10476 00:26:40.455591 <6>[ 0.879170] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10477 00:26:40.462394 <6>[ 0.886091] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10478 00:26:40.468819 <6>[ 0.893806] 9p: Installing v9fs 9p2000 file system support
10479 00:26:40.505688 <5>[ 0.932150] Key type asymmetric registered
10480 00:26:40.509120 <5>[ 0.936480] Asymmetric key parser 'x509' registered
10481 00:26:40.518856 <6>[ 0.941626] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10482 00:26:40.522112 <6>[ 0.949242] io scheduler mq-deadline registered
10483 00:26:40.525392 <6>[ 0.954005] io scheduler kyber registered
10484 00:26:40.544694 <6>[ 0.971223] EINJ: ACPI disabled.
10485 00:26:40.577251 <4>[ 0.996824] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10486 00:26:40.586877 <4>[ 1.007449] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10487 00:26:40.602072 <6>[ 1.028293] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10488 00:26:40.609933 <6>[ 1.036263] printk: console [ttyS0] disabled
10489 00:26:40.638004 <6>[ 1.060924] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10490 00:26:40.644431 <6>[ 1.070419] printk: console [ttyS0] enabled
10491 00:26:40.647967 <6>[ 1.070419] printk: console [ttyS0] enabled
10492 00:26:40.654773 <6>[ 1.079315] printk: bootconsole [mtk8250] disabled
10493 00:26:40.657605 <6>[ 1.079315] printk: bootconsole [mtk8250] disabled
10494 00:26:40.664676 <6>[ 1.090602] SuperH (H)SCI(F) driver initialized
10495 00:26:40.667978 <6>[ 1.095897] msm_serial: driver initialized
10496 00:26:40.681832 <6>[ 1.104931] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10497 00:26:40.691977 <6>[ 1.113476] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10498 00:26:40.698992 <6>[ 1.122017] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10499 00:26:40.708337 <6>[ 1.130646] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10500 00:26:40.715153 <6>[ 1.139353] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10501 00:26:40.725022 <6>[ 1.148066] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10502 00:26:40.734868 <6>[ 1.156616] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10503 00:26:40.741602 <6>[ 1.165429] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10504 00:26:40.751361 <6>[ 1.173974] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10505 00:26:40.763177 <6>[ 1.189574] loop: module loaded
10506 00:26:40.769665 <6>[ 1.195624] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10507 00:26:40.792687 <4>[ 1.219115] mtk-pmic-keys: Failed to locate of_node [id: -1]
10508 00:26:40.799572 <6>[ 1.226166] megasas: 07.719.03.00-rc1
10509 00:26:40.809463 <6>[ 1.235982] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10510 00:26:40.816277 <6>[ 1.242137] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10511 00:26:40.832425 <6>[ 1.258928] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10512 00:26:40.889263 <6>[ 1.309274] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10513 00:26:41.266207 <6>[ 1.692769] Freeing initrd memory: 20768K
10514 00:26:41.281998 <6>[ 1.708655] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10515 00:26:41.293350 <6>[ 1.719712] tun: Universal TUN/TAP device driver, 1.6
10516 00:26:41.296784 <6>[ 1.725771] thunder_xcv, ver 1.0
10517 00:26:41.299706 <6>[ 1.729273] thunder_bgx, ver 1.0
10518 00:26:41.303102 <6>[ 1.732770] nicpf, ver 1.0
10519 00:26:41.313762 <6>[ 1.736792] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10520 00:26:41.316894 <6>[ 1.744268] hns3: Copyright (c) 2017 Huawei Corporation.
10521 00:26:41.320187 <6>[ 1.749855] hclge is initializing
10522 00:26:41.327132 <6>[ 1.753433] e1000: Intel(R) PRO/1000 Network Driver
10523 00:26:41.333596 <6>[ 1.758563] e1000: Copyright (c) 1999-2006 Intel Corporation.
10524 00:26:41.337765 <6>[ 1.764578] e1000e: Intel(R) PRO/1000 Network Driver
10525 00:26:41.343718 <6>[ 1.769794] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10526 00:26:41.350436 <6>[ 1.775979] igb: Intel(R) Gigabit Ethernet Network Driver
10527 00:26:41.356941 <6>[ 1.781629] igb: Copyright (c) 2007-2014 Intel Corporation.
10528 00:26:41.363760 <6>[ 1.787465] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10529 00:26:41.367415 <6>[ 1.793983] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10530 00:26:41.374009 <6>[ 1.800449] sky2: driver version 1.30
10531 00:26:41.380833 <6>[ 1.805442] VFIO - User Level meta-driver version: 0.3
10532 00:26:41.387320 <6>[ 1.813690] usbcore: registered new interface driver usb-storage
10533 00:26:41.393910 <6>[ 1.820140] usbcore: registered new device driver onboard-usb-hub
10534 00:26:41.402689 <6>[ 1.829270] mt6397-rtc mt6359-rtc: registered as rtc0
10535 00:26:41.412902 <6>[ 1.834731] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-14T00:26:08 UTC (1691972768)
10536 00:26:41.416305 <6>[ 1.844306] i2c_dev: i2c /dev entries driver
10537 00:26:41.433182 <6>[ 1.856114] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10538 00:26:41.452552 <6>[ 1.879105] cpu cpu0: EM: created perf domain
10539 00:26:41.455878 <6>[ 1.884094] cpu cpu4: EM: created perf domain
10540 00:26:41.463249 <6>[ 1.889717] sdhci: Secure Digital Host Controller Interface driver
10541 00:26:41.469640 <6>[ 1.896150] sdhci: Copyright(c) Pierre Ossman
10542 00:26:41.476992 <6>[ 1.901096] Synopsys Designware Multimedia Card Interface Driver
10543 00:26:41.483068 <6>[ 1.907742] sdhci-pltfm: SDHCI platform and OF driver helper
10544 00:26:41.486480 <6>[ 1.907845] mmc0: CQHCI version 5.10
10545 00:26:41.493324 <6>[ 1.917718] ledtrig-cpu: registered to indicate activity on CPUs
10546 00:26:41.500181 <6>[ 1.924657] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10547 00:26:41.507055 <6>[ 1.931709] usbcore: registered new interface driver usbhid
10548 00:26:41.510365 <6>[ 1.937531] usbhid: USB HID core driver
10549 00:26:41.516934 <6>[ 1.941737] spi_master spi0: will run message pump with realtime priority
10550 00:26:41.561529 <6>[ 1.981577] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10551 00:26:41.577433 <6>[ 1.997135] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10552 00:26:41.585001 <6>[ 2.010732] mmc0: Command Queue Engine enabled
10553 00:26:41.591507 <6>[ 2.015534] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10554 00:26:41.597959 <6>[ 2.022683] cros-ec-spi spi0.0: Chrome EC device registered
10555 00:26:41.601530 <6>[ 2.023068] mmcblk0: mmc0:0001 DA4128 116 GiB
10556 00:26:41.612147 <6>[ 2.038484] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10557 00:26:41.619722 <6>[ 2.045997] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10558 00:26:41.626616 <6>[ 2.051941] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10559 00:26:41.632679 <6>[ 2.058041] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10560 00:26:41.646063 <6>[ 2.069255] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10561 00:26:41.653777 <6>[ 2.079929] NET: Registered PF_PACKET protocol family
10562 00:26:41.656805 <6>[ 2.085329] 9pnet: Installing 9P2000 support
10563 00:26:41.663508 <5>[ 2.089903] Key type dns_resolver registered
10564 00:26:41.666717 <6>[ 2.095026] registered taskstats version 1
10565 00:26:41.673242 <5>[ 2.099436] Loading compiled-in X.509 certificates
10566 00:26:41.703140 <4>[ 2.122803] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10567 00:26:41.712873 <4>[ 2.133589] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10568 00:26:41.719338 <3>[ 2.144177] debugfs: File 'uA_load' in directory '/' already present!
10569 00:26:41.726129 <3>[ 2.150929] debugfs: File 'min_uV' in directory '/' already present!
10570 00:26:41.732548 <3>[ 2.157538] debugfs: File 'max_uV' in directory '/' already present!
10571 00:26:41.739361 <3>[ 2.164149] debugfs: File 'constraint_flags' in directory '/' already present!
10572 00:26:41.750587 <3>[ 2.173842] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10573 00:26:41.763676 <6>[ 2.190426] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10574 00:26:41.770829 <6>[ 2.197218] xhci-mtk 11200000.usb: xHCI Host Controller
10575 00:26:41.777630 <6>[ 2.202716] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10576 00:26:41.787536 <6>[ 2.210646] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10577 00:26:41.794291 <6>[ 2.220100] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10578 00:26:41.800596 <6>[ 2.226291] xhci-mtk 11200000.usb: xHCI Host Controller
10579 00:26:41.807870 <6>[ 2.231790] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10580 00:26:41.814330 <6>[ 2.239445] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10581 00:26:41.820689 <6>[ 2.247406] hub 1-0:1.0: USB hub found
10582 00:26:41.824052 <6>[ 2.251438] hub 1-0:1.0: 1 port detected
10583 00:26:41.830882 <6>[ 2.255759] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10584 00:26:41.838069 <6>[ 2.264562] hub 2-0:1.0: USB hub found
10585 00:26:41.841511 <6>[ 2.268588] hub 2-0:1.0: 1 port detected
10586 00:26:41.850232 <6>[ 2.276585] mtk-msdc 11f70000.mmc: Got CD GPIO
10587 00:26:41.860059 <6>[ 2.282708] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10588 00:26:41.867012 <6>[ 2.290799] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10589 00:26:41.877139 <4>[ 2.298752] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10590 00:26:41.883187 <6>[ 2.308284] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10591 00:26:41.893495 <6>[ 2.316362] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10592 00:26:41.900005 <6>[ 2.324362] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10593 00:26:41.909889 <6>[ 2.332275] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10594 00:26:41.916555 <6>[ 2.340091] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10595 00:26:41.926707 <6>[ 2.347907] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10596 00:26:41.936808 <6>[ 2.358406] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10597 00:26:41.942787 <6>[ 2.366763] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10598 00:26:41.952984 <6>[ 2.375106] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10599 00:26:41.960205 <6>[ 2.383445] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10600 00:26:41.969946 <6>[ 2.391783] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10601 00:26:41.976606 <6>[ 2.400122] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10602 00:26:41.986254 <6>[ 2.408460] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10603 00:26:41.993000 <6>[ 2.416798] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10604 00:26:42.003204 <6>[ 2.425137] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10605 00:26:42.009590 <6>[ 2.433474] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10606 00:26:42.019650 <6>[ 2.441813] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10607 00:26:42.026442 <6>[ 2.450153] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10608 00:26:42.036300 <6>[ 2.458492] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10609 00:26:42.042663 <6>[ 2.466830] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10610 00:26:42.053084 <6>[ 2.475168] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10611 00:26:42.059552 <6>[ 2.483973] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10612 00:26:42.066297 <6>[ 2.491167] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10613 00:26:42.072717 <6>[ 2.497953] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10614 00:26:42.079427 <6>[ 2.504711] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10615 00:26:42.085917 <6>[ 2.511648] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10616 00:26:42.095875 <6>[ 2.518509] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10617 00:26:42.105975 <6>[ 2.527640] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10618 00:26:42.116291 <6>[ 2.536759] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10619 00:26:42.126056 <6>[ 2.546052] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10620 00:26:42.132617 <6>[ 2.555520] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10621 00:26:42.142665 <6>[ 2.564987] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10622 00:26:42.152978 <6>[ 2.574106] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10623 00:26:42.162473 <6>[ 2.583573] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10624 00:26:42.169068 <6>[ 2.592691] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10625 00:26:42.182610 <6>[ 2.601986] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10626 00:26:42.192437 <6>[ 2.612146] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10627 00:26:42.202130 <6>[ 2.623668] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10628 00:26:42.232215 <6>[ 2.655253] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10629 00:26:42.259532 <6>[ 2.686088] hub 2-1:1.0: USB hub found
10630 00:26:42.263066 <6>[ 2.690531] hub 2-1:1.0: 3 ports detected
10631 00:26:42.383766 <6>[ 2.807040] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10632 00:26:42.537706 <6>[ 2.964200] hub 1-1:1.0: USB hub found
10633 00:26:42.541023 <6>[ 2.968657] hub 1-1:1.0: 4 ports detected
10634 00:26:42.616208 <6>[ 3.039334] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10635 00:26:42.863648 <6>[ 3.287071] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10636 00:26:42.996732 <6>[ 3.422883] hub 1-1.4:1.0: USB hub found
10637 00:26:42.999981 <6>[ 3.427558] hub 1-1.4:1.0: 2 ports detected
10638 00:26:43.295404 <6>[ 3.719046] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10639 00:26:43.487413 <6>[ 3.911046] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10640 00:26:54.497468 <6>[ 14.928054] ALSA device list:
10641 00:26:54.503550 <6>[ 14.931347] No soundcards found.
10642 00:26:54.511746 <6>[ 14.939272] Freeing unused kernel memory: 8384K
10643 00:26:54.515099 <6>[ 14.944279] Run /init as init process
10644 00:26:54.548279 Starting syslogd: OK
10645 00:26:54.552730 Starting klogd: OK
10646 00:26:54.561941 Running sysctl: OK
10647 00:26:54.568469 Populating /dev using udev: <30>[ 14.997932] udevd[184]: starting version 3.2.9
10648 00:26:54.577882 <27>[ 15.005048] udevd[184]: specified user 'tss' unknown
10649 00:26:54.584445 <27>[ 15.010436] udevd[184]: specified group 'tss' unknown
10650 00:26:54.587480 <30>[ 15.016770] udevd[185]: starting eudev-3.2.9
10651 00:26:54.607324 <27>[ 15.034497] udevd[185]: specified user 'tss' unknown
10652 00:26:54.613756 <27>[ 15.039899] udevd[185]: specified group 'tss' unknown
10653 00:26:54.762278 <6>[ 15.186581] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10654 00:26:54.769151 <6>[ 15.196364] usbcore: registered new interface driver r8152
10655 00:26:54.780165 <6>[ 15.204355] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10656 00:26:54.786986 <6>[ 15.212188] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10657 00:26:54.796520 <6>[ 15.220920] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10658 00:26:54.803167 <6>[ 15.221472] mc: Linux media interface: v0.10
10659 00:26:54.806672 <6>[ 15.227122] remoteproc remoteproc0: scp is available
10660 00:26:54.813270 <6>[ 15.227247] remoteproc remoteproc0: powering up scp
10661 00:26:54.820026 <6>[ 15.227261] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10662 00:26:54.826723 <6>[ 15.227307] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10663 00:26:54.833699 <4>[ 15.237301] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10664 00:26:54.839635 <4>[ 15.266228] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10665 00:26:54.867948 <6>[ 15.292074] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10666 00:26:54.885277 <3>[ 15.309577] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10667 00:26:54.892088 <6>[ 15.310710] videodev: Linux video capture interface: v2.00
10668 00:26:54.902205 <6>[ 15.311381] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10669 00:26:54.908367 <6>[ 15.313487] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10670 00:26:54.919707 <6>[ 15.314668] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10671 00:26:54.926180 <3>[ 15.317747] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10672 00:26:54.936498 <4>[ 15.330336] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10673 00:26:54.942438 <3>[ 15.333597] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10674 00:26:54.952286 <4>[ 15.336963] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10675 00:26:54.955598 <4>[ 15.336963] Fallback method does not support PEC.
10676 00:26:54.965864 <4>[ 15.342647] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10677 00:26:54.972328 <3>[ 15.350439] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10678 00:26:54.979087 <6>[ 15.352164] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10679 00:26:54.985730 <6>[ 15.352171] pci_bus 0000:00: root bus resource [bus 00-ff]
10680 00:26:54.992099 <6>[ 15.352179] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10681 00:26:55.001700 <6>[ 15.352184] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10682 00:26:55.008703 <6>[ 15.352216] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10683 00:26:55.015468 <6>[ 15.352237] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10684 00:26:55.022355 <6>[ 15.352317] pci 0000:00:00.0: supports D1 D2
10685 00:26:55.029081 <6>[ 15.352320] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10686 00:26:55.035723 <3>[ 15.352378] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10687 00:26:55.043154 <6>[ 15.353328] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10688 00:26:55.052781 <6>[ 15.353574] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10689 00:26:55.058865 <6>[ 15.353594] remoteproc remoteproc0: remote processor scp is now up
10690 00:26:55.065978 <6>[ 15.354166] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10691 00:26:55.072044 <6>[ 15.354306] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10692 00:26:55.079630 <6>[ 15.354339] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10693 00:26:55.089380 <6>[ 15.354360] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10694 00:26:55.096173 <6>[ 15.354379] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10695 00:26:55.099034 <6>[ 15.354504] pci 0000:01:00.0: supports D1 D2
10696 00:26:55.105942 <6>[ 15.354507] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10697 00:26:55.112233 <6>[ 15.366909] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10698 00:26:55.122096 <3>[ 15.367688] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 00:26:55.140601 <6>[ 15.375619] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10700 00:26:55.141164 <3>[ 15.389170] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10701 00:26:55.145290 <3>[ 15.389177] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10702 00:26:55.155375 <3>[ 15.389180] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 00:26:55.162086 <3>[ 15.389285] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10704 00:26:55.171717 <6>[ 15.397376] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10705 00:26:55.178781 <3>[ 15.405386] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10706 00:26:55.185299 <3>[ 15.405390] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10707 00:26:55.194809 <6>[ 15.412680] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10708 00:26:55.205245 <6>[ 15.415841] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10709 00:26:55.211809 <3>[ 15.418319] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 00:26:55.218637 <6>[ 15.425358] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10711 00:26:55.228548 <3>[ 15.435443] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 00:26:55.235190 <6>[ 15.436336] usbcore: registered new interface driver cdc_ether
10713 00:26:55.241703 <6>[ 15.442692] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10714 00:26:55.248087 <6>[ 15.444957] usbcore: registered new interface driver r8153_ecm
10715 00:26:55.255154 <3>[ 15.448952] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 00:26:55.261022 <6>[ 15.453527] pci 0000:00:00.0: PCI bridge to [bus 01]
10717 00:26:55.264664 <6>[ 15.454083] Bluetooth: Core ver 2.22
10718 00:26:55.271272 <6>[ 15.454143] NET: Registered PF_BLUETOOTH protocol family
10719 00:26:55.277498 <6>[ 15.454145] Bluetooth: HCI device and connection manager initialized
10720 00:26:55.280799 <6>[ 15.454157] Bluetooth: HCI socket layer initialized
10721 00:26:55.287550 <6>[ 15.454161] Bluetooth: L2CAP socket layer initialized
10722 00:26:55.294279 <6>[ 15.454167] Bluetooth: SCO socket layer initialized
10723 00:26:55.300810 <3>[ 15.460357] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 00:26:55.304029 <6>[ 15.469340] r8152 2-1.3:1.0 eth0: v1.12.13
10725 00:26:55.314067 <6>[ 15.469381] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10726 00:26:55.320838 <6>[ 15.470659] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10727 00:26:55.323570 <6>[ 15.473694] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10728 00:26:55.333777 <3>[ 15.476166] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 00:26:55.340415 <6>[ 15.484996] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10730 00:26:55.347063 <3>[ 15.486248] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10731 00:26:55.357141 <3>[ 15.491112] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 00:26:55.363891 <3>[ 15.491178] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 00:26:55.373429 <6>[ 15.492813] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10734 00:26:55.380450 <6>[ 15.495242] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10735 00:26:55.386955 <6>[ 15.500958] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10736 00:26:55.393589 <6>[ 15.513827] usbcore: registered new interface driver btusb
10737 00:26:55.403188 <4>[ 15.514337] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10738 00:26:55.410389 <3>[ 15.514347] Bluetooth: hci0: Failed to load firmware file (-2)
10739 00:26:55.417088 <3>[ 15.514351] Bluetooth: hci0: Failed to set up firmware (-2)
10740 00:26:55.426537 <4>[ 15.514354] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10741 00:26:55.439711 <6>[ 15.521950] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10742 00:26:55.446133 <5>[ 15.523987] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10743 00:26:55.452736 <6>[ 15.540156] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10744 00:26:55.459306 <6>[ 15.546605] usbcore: registered new interface driver uvcvideo
10745 00:26:55.465752 <5>[ 15.547310] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10746 00:26:55.475997 <4>[ 15.547406] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10747 00:26:55.479377 <6>[ 15.547416] cfg80211: failed to load regulatory.db
10748 00:26:55.485995 <6>[ 15.663000] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10749 00:26:55.492666 <6>[ 15.920361] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10750 00:26:55.518800 <6>[ 15.946959] mt7921e 0000:01:00.0: ASIC revision: 79610010
10751 00:26:55.625406 <4>[ 16.046792] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10752 00:26:55.625545 done
10753 00:26:55.647353 Saving random seed: OK
10754 00:26:55.662922 Starting network: OK
10755 00:26:55.699297 Starting dropbear sshd: <6>[ 16.127172] NET: Registered PF_INET6 protocol family
10756 00:26:55.706053 <6>[ 16.133660] Segment Routing with IPv6
10757 00:26:55.709356 <6>[ 16.137616] In-situ OAM (IOAM) with IPv6
10758 00:26:55.712561 OK
10759 00:26:55.724975 /bin/sh: can't access tty; job control turned off
10760 00:26:55.725294 Matched prompt #10: / #
10762 00:26:55.725498 Setting prompt string to ['/ #']
10763 00:26:55.725590 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10765 00:26:55.725781 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10766 00:26:55.725867 start: 2.2.6 expect-shell-connection (timeout 00:03:44) [common]
10767 00:26:55.725936 Setting prompt string to ['/ #']
10768 00:26:55.725999 Forcing a shell prompt, looking for ['/ #']
10770 00:26:55.776316 / #
10771 00:26:55.776509 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10772 00:26:55.776604 Waiting using forced prompt support (timeout 00:02:30)
10773 00:26:55.776733 <4>[ 16.165420] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10774 00:26:55.782302
10775 00:26:55.782684 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10776 00:26:55.782822 start: 2.2.7 export-device-env (timeout 00:03:44) [common]
10777 00:26:55.782938 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10778 00:26:55.783045 end: 2.2 depthcharge-retry (duration 00:01:16) [common]
10779 00:26:55.783144 end: 2 depthcharge-action (duration 00:01:16) [common]
10780 00:26:55.783239 start: 3 lava-test-retry (timeout 00:01:00) [common]
10781 00:26:55.783328 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10782 00:26:55.783409 Using namespace: common
10784 00:26:55.884211 / # #
10785 00:26:55.884867 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10786 00:26:55.885454 #<4>[ 16.285142] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10787 00:26:55.890336
10788 00:26:55.891111 Using /lava-11280962
10790 00:26:55.992385 / # export SHELL=/bin/sh
10791 00:26:55.993078 export SHELL=/bin/sh<4>[ 16.405932] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10792 00:26:55.999407
10794 00:26:56.101018 / # . /lava-11280962/environment
10795 00:26:56.105080 . /lava-11280962/environment<4>[ 16.525592] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10796 00:26:56.147986
10798 00:26:56.249673 / # /lava-11280962/bin/lava-test-runner /lava-11280962/0
10799 00:26:56.249891 Test shell timeout: 10s (minimum of the action and connection timeout)
10800 00:26:56.250329 /lava-11280962/bin/lava-test-runner /lava-11280962/0<4>[ 16.645861] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10801 00:26:56.255386
10802 00:26:56.296019 + export 'TESTRUN_ID=0_dmesg'
10803 00:26:56.296585 +<8>[ 16.708166] <LAVA_SIGNAL_STARTRUN 0_dmesg 11280962_1.5.2.3.1>
10804 00:26:56.296967 cd /lava-11280962/0/tests/0_dmesg
10805 00:26:56.297306 + cat uuid
10806 00:26:56.297639 + UUID=11280962_1.5.2.3.1
10807 00:26:56.297965 + set +x
10808 00:26:56.298580 Received signal: <STARTRUN> 0_dmesg 11280962_1.5.2.3.1
10809 00:26:56.298947 Starting test lava.0_dmesg (11280962_1.5.2.3.1)
10810 00:26:56.299359 Skipping test definition patterns.
10811 00:26:56.299976 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10812 00:26:56.306252 <8>[ 16.730763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10813 00:26:56.306981 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10815 00:26:56.332327 <8>[ 16.756347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10816 00:26:56.333331 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10818 00:26:56.345117 <4>[ 16.765735] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10819 00:26:56.356250 <8>[ 16.780594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10820 00:26:56.356986 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10822 00:26:56.361074 + set +x
10823 00:26:56.364775 Received signal: <ENDRUN> 0_dmesg 11280962_1.5.2.3.1
10824 00:26:56.365311 Ending use of test pattern.
10825 00:26:56.365680 Ending test lava.0_dmesg (11280962_1.5.2.3.1), duration 0.07
10827 00:26:56.367216 <8>[ 16.792187] <LAVA_SIGNAL_ENDRUN 0_dmesg 11280962_1.5.2.3.1>
10828 00:26:56.367935 ok: lava_test_shell seems to have completed
10829 00:26:56.368468 alert: pass
crit: pass
emerg: pass
10830 00:26:56.368869 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10831 00:26:56.369287 end: 3 lava-test-retry (duration 00:00:01) [common]
10832 00:26:56.369715 start: 4 lava-test-retry (timeout 00:01:00) [common]
10833 00:26:56.370126 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10834 00:26:56.370517 Using namespace: common
10836 00:26:56.421517 <LAVA_TEST_RUNNER EXIT>
10837 00:26:56.472312 #
10838 00:26:56.472930 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10839 00:26:56.473605
10840 00:26:56.473991 / # #<4>[ 16.885845] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10841 00:26:56.474694 Using /lava-11280962
10843 00:26:56.575771 export SHELL=/bin/sh
10844 00:26:56.576562
10846 00:26:56.677939 / # export SHELL=/bin/sh<4>[ 17.005626] mt7921e 0000:01:00.0:. /lava-11280962/environment
10847 00:26:56.678252 Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10848 00:26:56.678408
10850 00:26:56.779361 / # . /lava-11280962/environment/lava-11280962/bin/lava-test-runner /lava-11280962/1
10851 00:26:56.780169 Test shell timeout: 10s (minimum of the action and connection timeout)
10852 00:26:56.780861
10853 00:26:56.781251 / # <4>[ 17.125712] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10854 00:26:56.786812 /lava-11280962/bin/lava-test-runner /lava-11280962/1
10855 00:26:56.828092 + export 'TESTRU<3>[ 17.244693] mt7921e 0000:01:00.0: hardware init failed
10856 00:26:56.828660 N_ID=1_bootrr'
10857 00:26:56.829066 <8>[ 17.251514] <LAVA_SIGNAL_STARTRUN 1_bootrr 11280962_1.5.2.3.5>
10858 00:26:56.829762 Received signal: <STARTRUN> 1_bootrr 11280962_1.5.2.3.5
10859 00:26:56.830133 Starting test lava.1_bootrr (11280962_1.5.2.3.5)
10860 00:26:56.830547 Skipping test definition patterns.
10861 00:26:56.831067 + cd /lava-11280962/1/tests/1_bootrr
10862 00:26:56.831437 + cat uuid
10863 00:26:56.832467 + UUID=11280962_1.5.2.3.5
10864 00:26:56.832933 + set +x
10865 00:26:56.842777 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11280962/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10866 00:26:56.849054 <8>[ 17.273640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10867 00:26:56.849610
10868 00:26:56.850255 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10870 00:26:56.852143 + cd /opt/bootrr/libexec/bootrr
10871 00:26:56.855900 + sh helpers/bootrr-auto
10872 00:26:56.858740 /lava-11280962/1/../bin/lava-test-case
10873 00:26:56.862244 /lava-11280962/1/../bin/lava-test-case
10874 00:26:56.868918 <8>[ 17.293771] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10875 00:26:56.869780 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10877 00:26:56.874804 /usr/bin/tpm2_getcap
10878 00:26:56.908814 /lava-11280962/1/../bin/lava-test-case
10879 00:26:56.915408 <8>[ 17.341180] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10880 00:26:56.916281 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10882 00:26:56.941126 /lava-11280962/1/../bin/lava-tes<8>[ 17.364749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10883 00:26:56.941674 t-case
10884 00:26:56.942309 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10886 00:26:56.959728 /lava-11280962/1/../bin/lava-tes<8>[ 17.383317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10887 00:26:56.960283 t-case
10888 00:26:56.960924 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10890 00:26:56.971645 /lava-11280962/1/../bin/lava-test-case
10891 00:26:56.978473 <8>[ 17.402256] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10892 00:26:56.979331 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10894 00:26:56.990508 /lava-11280962/1/../bin/lava-test-case
10895 00:26:56.997278 <8>[ 17.421641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10896 00:26:56.998115 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10898 00:26:57.008253 /lava-11280962/1/../bin/lava-test-case
10899 00:26:57.015084 <8>[ 17.439356] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10900 00:26:57.015997 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10902 00:26:57.024689 /lava-11280962/1/../bin/lava-test-case
10903 00:26:57.031937 <8>[ 17.455709] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10904 00:26:57.032786 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10906 00:26:57.043662 /lava-11280962/1/../bin/lava-test-case
10907 00:26:57.050514 <8>[ 17.474682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10908 00:26:57.051362 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10910 00:26:57.059865 /lava-11280962/1/../bin/lava-test-case
10911 00:26:57.066182 <8>[ 17.490288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10912 00:26:57.067038 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10914 00:26:57.078342 /lava-11280962/1/../bin/lava-test-case
10915 00:26:57.085171 <8>[ 17.509357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10916 00:26:57.085998 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10918 00:26:57.097697 /lava-11280962/1/../bin/lava-test-case
10919 00:26:57.104731 <8>[ 17.528976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10920 00:26:57.105585 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10922 00:26:57.117617 /lava-11280962/1/../bin/lava-test-case
10923 00:26:57.123598 <8>[ 17.549191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10924 00:26:57.124359 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10926 00:26:57.137357 /lava-11280962/1/../bin/lava-test-case
10927 00:26:57.144116 <8>[ 17.568262] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10928 00:26:57.144959 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10930 00:26:57.153324 /lava-11280962/1/../bin/lava-test-case
10931 00:26:57.160148 <8>[ 17.583571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10932 00:26:57.160995 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10934 00:26:57.174194 /lava-11280962/1/../bin/lava-test-case
10935 00:26:57.180523 <8>[ 17.605808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10936 00:26:57.181384 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10938 00:26:57.191424 /lava-11280962/1/../bin/lava-test-case
10939 00:26:57.197112 <8>[ 17.621931] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10940 00:26:57.197943 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10942 00:26:57.209182 /lava-11280962/1/../bin/lava-test-case
10943 00:26:57.216475 <8>[ 17.640685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10944 00:26:57.217322 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10946 00:26:57.224149 /lava-11280962/1/../bin/lava-test-case
10947 00:26:57.231281 <8>[ 17.655410] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10948 00:26:57.232240 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10950 00:26:57.241728 /lava-11280962/1/../bin/lava-test-case
10951 00:26:57.248535 <8>[ 17.674391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10952 00:26:57.249272 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10954 00:26:57.264505 /lava-11280962/1/../bin/lava-tes<8>[ 17.688606] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10955 00:26:57.265064 t-case
10956 00:26:57.265701 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10958 00:26:57.286832 /lava-11280962/1/../bin/lava-tes<8>[ 17.709809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10959 00:26:57.287404 t-case
10960 00:26:57.288091 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10962 00:26:57.294966 /lava-11280962/1/../bin/lava-test-case
10963 00:26:57.301796 <8>[ 17.725817] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10964 00:26:57.302651 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10966 00:26:57.319779 /lava-11280962/1/../bin/lava-tes<8>[ 17.743466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10967 00:26:57.320341 t-case
10968 00:26:57.320981 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10970 00:26:57.331578 /lava-11280962/1/../bin/lava-test-case
10971 00:26:57.338234 <8>[ 17.762164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10972 00:26:57.339084 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10974 00:26:57.355311 /lava-11280962/1/../bin/lava-tes<8>[ 17.778812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10975 00:26:57.355985 t-case
10976 00:26:57.356681 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10978 00:26:57.366184 /lava-11280962/1/../bin/lava-test-case
10979 00:26:57.376420 <8>[ 17.800523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10980 00:26:57.377312 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10982 00:26:57.384633 /lava-11280962/1/../bin/lava-test-case
10983 00:26:57.391327 <8>[ 17.816587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10984 00:26:57.392260 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10986 00:26:57.410527 /lava-11280962/1/../bin/lava-tes<8>[ 17.834084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10987 00:26:57.411097 t-case
10988 00:26:57.411730 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10990 00:26:57.420304 /lava-11280962/1/../bin/lava-test-case
10991 00:26:57.426952 <8>[ 17.851279] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10992 00:26:57.427858 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10994 00:26:57.439683 /lava-11280962/1/../bin/lava-test-case
10995 00:26:57.449401 <8>[ 17.873539] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10996 00:26:57.450252 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10998 00:26:57.462609 /lava-11280962/1/../bin/lava-test-case
10999 00:26:57.468872 <8>[ 17.892724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11000 00:26:57.469720 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11002 00:26:57.478773 /lava-11280962/1/../bin/lava-test-case
11003 00:26:57.485439 <8>[ 17.909479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11004 00:26:57.486264 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11006 00:26:57.497355 /lava-11280962/1/../bin/lava-test-case
11007 00:26:57.503613 <8>[ 17.928202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11008 00:26:57.504460 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11010 00:26:57.514755 /lava-11280962/1/../bin/lava-test-case
11011 00:26:57.521619 <8>[ 17.945667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11012 00:26:57.522476 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11014 00:26:57.529863 /lava-11280962/1/../bin/lava-test-case
11015 00:26:57.536425 <8>[ 17.960405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11016 00:26:57.537255 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11018 00:26:57.548833 /lava-11280962/1/../bin/lava-test-case
11019 00:26:57.555376 <8>[ 17.979800] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11020 00:26:57.556246 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11022 00:26:57.563587 /lava-11280962/1/../bin/lava-test-case
11023 00:26:57.573452 <8>[ 17.996546] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11024 00:26:57.574299 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11026 00:26:57.591690 /lava-11280962/1/../bin/lava-tes<8>[ 18.015227] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11027 00:26:57.592265 t-case
11028 00:26:57.592910 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11030 00:26:57.599887 /lava-11280962/1/../bin/lava-test-case
11031 00:26:57.606862 <8>[ 18.031264] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11032 00:26:57.607726 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11034 00:26:57.618701 /lava-11280962/1/../bin/lava-test-case
11035 00:26:57.625531 <8>[ 18.049668] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11036 00:26:57.626356 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11038 00:26:57.633584 /lava-11280962/1/../bin/lava-test-case
11039 00:26:57.640384 <8>[ 18.065649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11040 00:26:57.641256 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11042 00:26:57.654533 /lava-11280962/1/../bin/lava-test-case
11043 00:26:57.661225 <8>[ 18.086385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11044 00:26:57.662068 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11046 00:26:57.677305 /lava-11280962/1/../bin/lava-tes<8>[ 18.100879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11047 00:26:57.677864 t-case
11048 00:26:57.678507 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11050 00:26:57.688526 /lava-11280962/1/../bin/lava-test-case
11051 00:26:57.694961 <8>[ 18.121454] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11052 00:26:57.695844 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11054 00:26:57.706754 /lava-11280962/1/../bin/lava-test-case
11055 00:26:57.713146 <8>[ 18.137178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11056 00:26:57.713995 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11058 00:26:57.728206 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11060 00:26:57.730784 /lava-11280962/1/../bin/lava-tes<8>[ 18.154829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11061 00:26:57.731357 t-case
11062 00:26:57.745883 /lava-11280962/1/../bin/lava-tes<8>[ 18.169751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11063 00:26:57.746752 t-case
11064 00:26:57.747750 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11066 00:26:57.757484 /lava-11280962/1/../bin/lava-test-case
11067 00:26:57.767669 <8>[ 18.192209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11068 00:26:57.768496 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11070 00:26:57.778053 /lava-11280962/1/../bin/lava-test-case
11071 00:26:57.784569 <8>[ 18.208914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11072 00:26:57.785418 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11074 00:26:57.800465 /lava-11280962/1/../bin/lava-tes<8>[ 18.224140] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11075 00:26:57.801037 t-case
11076 00:26:57.801686 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11078 00:26:57.817802 /lava-11280962/1/../bin/lava-tes<8>[ 18.241549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11079 00:26:57.818376 t-case
11080 00:26:57.819023 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11082 00:26:57.834113 /lava-11280962/1/../bin/lava-tes<8>[ 18.257481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11083 00:26:57.834689 t-case
11084 00:26:57.835338 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11086 00:26:57.845068 /lava-11280962/1/../bin/lava-test-case
11087 00:26:57.851504 <8>[ 18.276128] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11088 00:26:57.852357 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11090 00:26:57.858018 /lava-11280962/1/../bin/lava-test-case
11091 00:26:57.868766 <8>[ 18.293206] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11092 00:26:57.869594 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11094 00:26:57.886398 /lava-11280962/1/../bin/lava-tes<8>[ 18.309924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11095 00:26:57.886959 t-case
11096 00:26:57.887633 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11098 00:26:57.897441 /lava-11280962/1/../bin/lava-test-case
11099 00:26:57.904227 <8>[ 18.328786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11100 00:26:57.905079 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11102 00:26:57.915790 /lava-11280962/1/../bin/lava-test-case
11103 00:26:57.922053 <8>[ 18.347272] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11104 00:26:57.922903 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11106 00:26:57.937040 /lava-11280962/1/../bin/lava-tes<8>[ 18.361030] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11107 00:26:57.937616 t-case
11108 00:26:57.938261 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11110 00:26:57.949751 /lava-11280962/1/../bin/lava-test-case
11111 00:26:57.956387 <8>[ 18.381611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11112 00:26:57.957236 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11114 00:26:57.966403 /lava-11280962/1/../bin/lava-test-case
11115 00:26:57.972760 <8>[ 18.398502] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11116 00:26:57.973508 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11118 00:26:57.982533 /lava-11280962/1/../bin/lava-test-case
11119 00:26:57.989314 <8>[ 18.413671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11120 00:26:57.989746 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11122 00:26:58.000590 /lava-11280962/1/../bin/lava-test-case
11123 00:26:58.007024 <8>[ 18.432308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11124 00:26:58.007319 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11126 00:26:58.016367 /lava-11280962/1/../bin/lava-test-case
11127 00:26:58.022496 <8>[ 18.447880] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11128 00:26:58.022758 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11130 00:26:58.033408 /lava-11280962/1/../bin/lava-test-case
11131 00:26:58.039834 <8>[ 18.465473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11132 00:26:58.040092 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11134 00:26:58.051582 /lava-11280962/1/../bin/lava-test-case
11135 00:26:58.057962 <8>[ 18.482412] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11136 00:26:58.058221 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11138 00:26:58.068268 /lava-11280962/1/../bin/lava-test-case
11139 00:26:58.074728 <8>[ 18.500991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11140 00:26:58.074990 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11142 00:26:58.085971 /lava-11280962/1/../bin/lava-test-case
11143 00:26:58.092416 <8>[ 18.518152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11144 00:26:58.092703 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11146 00:26:58.103077 /lava-11280962/1/../bin/lava-test-case
11147 00:26:58.113226 <8>[ 18.538298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11148 00:26:58.113488 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11150 00:26:58.130980 /lava-11280962/1/../bin/lava-tes<8>[ 18.555427] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11151 00:26:58.131074 t-case
11152 00:26:58.131311 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11154 00:26:58.142451 /lava-11280962/1/../bin/lava-test-case
11155 00:26:58.148636 <8>[ 18.573177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11156 00:26:58.148979 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11158 00:26:58.162354 /lava-11280962/1/../bin/lava-test-case
11159 00:26:58.168848 <8>[ 18.594626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11160 00:26:58.169584 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11162 00:26:58.181149 /lava-11280962/1/../bin/lava-test-case
11163 00:26:58.191149 <8>[ 18.615042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11164 00:26:58.192009 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11166 00:26:58.202112 /lava-11280962/1/../bin/lava-test-case
11167 00:26:58.208449 <8>[ 18.633151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11168 00:26:58.209276 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11170 00:26:58.219188 /lava-11280962/1/../bin/lava-test-case
11171 00:26:58.225865 <8>[ 18.650177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11172 00:26:58.226701 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11174 00:26:58.242691 /lava-11280962/1/../bin/lava-tes<8>[ 18.666962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11175 00:26:58.243246 t-case
11176 00:26:58.243916 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11178 00:26:58.253071 /lava-11280962/1/../bin/lava-test-case
11179 00:26:58.259650 <8>[ 18.684005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11180 00:26:58.260506 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11182 00:26:58.277854 /lava-11280962/1/../bin/lava-tes<8>[ 18.701785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11183 00:26:58.278400 t-case
11184 00:26:58.279038 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11186 00:26:58.295626 /lava-11280962/1/../bin/lava-tes<8>[ 18.719488] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11187 00:26:58.296205 t-case
11188 00:26:58.296845 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11190 00:26:58.306467 /lava-11280962/1/../bin/lava-test-case
11191 00:26:58.313269 <8>[ 18.737674] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11192 00:26:58.314085 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11194 00:26:58.323473 /lava-11280962/1/../bin/lava-test-case
11195 00:26:58.329520 <8>[ 18.755472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11196 00:26:58.330327 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11198 00:26:58.339630 /lava-11280962/1/../bin/lava-test-case
11199 00:26:58.346234 <8>[ 18.771695] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11200 00:26:58.346960 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11202 00:26:58.357573 /lava-11280962/1/../bin/lava-test-case
11203 00:26:58.367298 <8>[ 18.791875] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11204 00:26:58.368156 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11206 00:26:58.375580 /lava-11280962/1/../bin/lava-test-case
11207 00:26:58.381840 <8>[ 18.806722] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11208 00:26:58.382287 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11210 00:26:58.393934 /lava-11280962/1/../bin/lava-test-case
11211 00:26:58.400154 <8>[ 18.826452] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11212 00:26:58.400504 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11214 00:26:58.409736 /lava-11280962/1/../bin/lava-test-case
11215 00:26:58.415632 <8>[ 18.841183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11216 00:26:58.415989 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11218 00:26:58.427412 /lava-11280962/1/../bin/lava-test-case
11219 00:26:58.433832 <8>[ 18.858590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11220 00:26:58.434182 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11222 00:26:58.451763 /lava-11280962/1/../bin/lava-tes<8>[ 18.876040] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11223 00:26:58.451947 t-case
11224 00:26:58.452234 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11226 00:26:58.463929 /lava-11280962/1/../bin/lava-test-case
11227 00:26:58.470465 <8>[ 18.896990] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11228 00:26:58.470913 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11230 00:26:58.481846 /lava-11280962/1/../bin/lava-test-case
11231 00:26:58.488657 <8>[ 18.913055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11232 00:26:58.489254 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11234 00:26:58.498783 /lava-11280962/1/../bin/lava-test-case
11235 00:26:58.505385 <8>[ 18.930727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11236 00:26:58.506222 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11238 00:26:58.515676 /lava-11280962/1/../bin/lava-test-case
11239 00:26:58.522225 <8>[ 18.946447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11240 00:26:58.523066 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11242 00:26:58.532854 /lava-11280962/1/../bin/lava-test-case
11243 00:26:58.539424 <8>[ 18.964234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11244 00:26:58.540298 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11246 00:26:58.550743 /lava-11280962/1/../bin/lava-test-case
11247 00:26:58.556927 <8>[ 18.981525] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11248 00:26:58.557771 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11250 00:26:58.565456 /lava-11280962/1/../bin/lava-test-case
11251 00:26:58.572427 <8>[ 18.997737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11252 00:26:58.573261 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11254 00:26:58.585135 /lava-11280962/1/../bin/lava-test-case
11255 00:26:58.590912 <8>[ 19.016583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11256 00:26:58.591727 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11258 00:26:58.600404 /lava-11280962/1/../bin/lava-test-case
11259 00:26:58.606497 <8>[ 19.031449] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11260 00:26:58.607322 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11262 00:26:58.616601 /lava-11280962/1/../bin/lava-test-case
11263 00:26:58.623264 <8>[ 19.048278] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11264 00:26:58.624161 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11266 00:26:58.632415 /lava-11280962/1/../bin/lava-test-case
11267 00:26:58.639289 <8>[ 19.063411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11268 00:26:58.640173 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11270 00:26:59.652150 /lava-11280962/1/../bin/lava-test-case
11271 00:26:59.658273 <8>[ 20.084618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11272 00:26:59.658531 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11274 00:26:59.668898 /lava-11280962/1/../bin/lava-test-case
11275 00:26:59.675763 <8>[ 20.100526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11276 00:26:59.676120 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11278 00:27:00.692968 /lava-11280962/1/../bin/lava-test-case
11279 00:27:00.698868 <8>[ 21.124911] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11280 00:27:00.699132 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11282 00:27:00.713004 /lava-11280962/1/../bin/lava-test-case
11283 00:27:00.719692 <8>[ 21.144532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11284 00:27:00.720069 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11286 00:27:01.734959 /lava-11280962/1/../bin/lava-test-case
11287 00:27:01.741204 <8>[ 22.166176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11288 00:27:01.742042 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11290 00:27:01.759951 /lava-11280962/1/../bin/lava-tes<8>[ 22.183829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11291 00:27:01.760514 t-case
11292 00:27:01.761158 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11294 00:27:02.774089 /lava-11280962/1/../bin/lava-test-case
11295 00:27:02.780549 <8>[ 23.205802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11296 00:27:02.781379 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11298 00:27:02.797833 /lava-11280962/1/../bin/lava-tes<8>[ 23.222466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11299 00:27:02.798393 t-case
11300 00:27:02.799024 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11302 00:27:03.811031 /lava-11280962/1/../bin/lava-test-case
11303 00:27:03.817688 <8>[ 24.242281] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11304 00:27:03.818516 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11306 00:27:03.834709 /lava-11280962/1/../bin/lava-tes<8>[ 24.259343] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11307 00:27:03.835266 t-case
11308 00:27:03.835967 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11310 00:27:04.848438 /lava-11280962/1/../bin/lava-test-case
11311 00:27:04.854982 <8>[ 25.280333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11312 00:27:04.855716 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11314 00:27:04.875042 /lava-11280962/1/../bin/lava-tes<8>[ 25.299376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11315 00:27:04.875645 t-case
11316 00:27:04.876293 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11318 00:27:05.887652 /lava-11280962/1/../bin/lava-test-case
11319 00:27:05.895075 <8>[ 26.319673] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11320 00:27:05.895971 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11322 00:27:05.912470 /lava-11280962/1/../bin/lava-tes<8>[ 26.337123] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11323 00:27:05.913037 t-case
11324 00:27:05.913680 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11326 00:27:05.921536 /lava-11280962/1/../bin/lava-test-case
11327 00:27:05.928184 <8>[ 26.353600] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11328 00:27:05.928923 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11330 00:27:06.943153 /lava-11280962/1/../bin/lava-test-case
11331 00:27:06.949918 <8>[ 27.376216] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11332 00:27:06.950757 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11334 00:27:06.959602 /lava-11280962/1/../bin/lava-test-case
11335 00:27:06.966115 <8>[ 27.391080] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11336 00:27:06.966966 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11338 00:27:06.981487 /lava-11280962/1/../bin/lava-test-case
11339 00:27:06.987818 <8>[ 27.413055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11340 00:27:06.988687 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11342 00:27:06.996257 /lava-11280962/1/../bin/lava-test-case
11343 00:27:07.002972 <8>[ 27.428490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11344 00:27:07.003894 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11346 00:27:07.025292 /lava-11280962/1/../bin/lava-tes<8>[ 27.450408] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11347 00:27:07.025858 t-case
11348 00:27:07.026506 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11350 00:27:07.036756 /lava-11280962/1/../bin/lava-test-case
11351 00:27:07.043278 <8>[ 27.468933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11352 00:27:07.044193 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11354 00:27:07.061610 /lava-11280962/1/../bin/lava-tes<8>[ 27.486442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11355 00:27:07.062171 t-case
11356 00:27:07.062813 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11358 00:27:07.080681 /lava-11280962/1/../bin/lava-tes<8>[ 27.505648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11359 00:27:07.081242 t-case
11360 00:27:07.081884 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11362 00:27:07.093368 /lava-11280962/1/../bin/lava-test-case
11363 00:27:07.100011 <8>[ 27.525478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11364 00:27:07.100853 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11366 00:27:07.112257 /lava-11280962/1/../bin/lava-test-case
11367 00:27:07.122218 <8>[ 27.546369] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11368 00:27:07.123071 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11370 00:27:07.130829 /lava-11280962/1/../bin/lava-test-case
11371 00:27:07.137353 <8>[ 27.562759] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11372 00:27:07.138189 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11374 00:27:07.149684 /lava-11280962/1/../bin/lava-test-case
11375 00:27:07.155882 <8>[ 27.582519] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11376 00:27:07.156703 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11378 00:27:07.165337 /lava-11280962/1/../bin/lava-test-case
11379 00:27:07.172402 <8>[ 27.597398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11380 00:27:07.173242 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11382 00:27:07.184613 /lava-11280962/1/../bin/lava-test-case
11383 00:27:07.191269 <8>[ 27.616371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11384 00:27:07.192168 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11386 00:27:07.200364 /lava-11280962/1/../bin/lava-test-case
11387 00:27:07.210546 <8>[ 27.635388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11388 00:27:07.211381 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11390 00:27:07.222644 /lava-11280962/1/../bin/lava-test-case
11391 00:27:07.229337 <8>[ 27.654530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11392 00:27:07.230173 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11394 00:27:07.237840 /lava-11280962/1/../bin/lava-test-case
11395 00:27:07.247942 <8>[ 27.673563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11396 00:27:07.248757 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11398 00:27:07.261538 /lava-11280962/1/../bin/lava-test-case
11399 00:27:07.267839 <8>[ 27.693422] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11400 00:27:07.268662 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11402 00:27:07.277021 /lava-11280962/1/../bin/lava-test-case
11403 00:27:07.287192 <8>[ 27.712674] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11404 00:27:07.288082 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11406 00:27:07.297685 /lava-11280962/1/../bin/lava-test-case
11407 00:27:07.304435 <8>[ 27.730630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11408 00:27:07.305275 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11410 00:27:07.314911 /lava-11280962/1/../bin/lava-test-case
11411 00:27:07.321248 <8>[ 27.746293] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11412 00:27:07.322087 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11414 00:27:08.333550 /lava-11280962/1/../bin/lava-test-case
11415 00:27:08.339671 <8>[ 28.766702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11416 00:27:08.340552 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11418 00:27:09.356729 /lava-11280962/1/../bin/lava-test-case
11419 00:27:09.363452 <8>[ 29.790423] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11420 00:27:09.364336 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11422 00:27:09.372239 /lava-11280962/1/../bin/lava-test-case
11423 00:27:09.379270 <8>[ 29.805034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11424 00:27:09.380214 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11426 00:27:09.394348 /lava-11280962/1/../bin/lava-test-case
11427 00:27:09.400553 <8>[ 29.828207] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11428 00:27:09.401368 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11430 00:27:09.411158 /lava-11280962/1/../bin/lava-test-case
11431 00:27:09.417569 <8>[ 29.843978] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11432 00:27:09.418402 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11434 00:27:09.430374 /lava-11280962/1/../bin/lava-test-case
11435 00:27:09.437518 <8>[ 29.863745] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11436 00:27:09.438409 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11438 00:27:09.446081 /lava-11280962/1/../bin/lava-test-case
11439 00:27:09.452917 <8>[ 29.879427] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11440 00:27:09.453750 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11442 00:27:09.464643 /lava-11280962/1/../bin/lava-test-case
11443 00:27:09.471689 <8>[ 29.898509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11444 00:27:09.472522 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11446 00:27:09.480115 /lava-11280962/1/../bin/lava-test-case
11447 00:27:09.487031 <8>[ 29.912694] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11448 00:27:09.487920 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11450 00:27:09.500235 /lava-11280962/1/../bin/lava-test-case
11451 00:27:09.507079 <8>[ 29.932332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11452 00:27:09.507964 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11454 00:27:09.523195 /lava-11280962/1/../bin/lava-tes<8>[ 29.947962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11455 00:27:09.523809 t-case
11456 00:27:09.524458 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11458 00:27:09.534509 /lava-11280962/1/../bin/lava-test-case
11459 00:27:09.541415 <8>[ 29.968808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11460 00:27:09.542247 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11462 00:27:09.551107 /lava-11280962/1/../bin/lava-test-case
11463 00:27:09.557720 <8>[ 29.983109] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11464 00:27:09.558558 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11466 00:27:09.570685 /lava-11280962/1/../bin/lava-test-case
11467 00:27:09.577634 <8>[ 30.004115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11468 00:27:09.578472 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11470 00:27:09.592844 /lava-11280962/1/../bin/lava-tes<8>[ 30.018093] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11471 00:27:09.593400 t-case
11472 00:27:09.594044 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11474 00:27:09.605496 /lava-11280962/1/../bin/lava-test-case
11475 00:27:09.611891 <8>[ 30.037445] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11476 00:27:09.612724 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11478 00:27:09.620039 /lava-11280962/1/../bin/lava-test-case
11479 00:27:09.626830 <8>[ 30.053526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11480 00:27:09.627667 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11482 00:27:09.638440 /lava-11280962/1/../bin/lava-test-case
11483 00:27:09.645617 <8>[ 30.070919] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11484 00:27:09.646466 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11486 00:27:09.653463 /lava-11280962/1/../bin/lava-test-case
11487 00:27:09.659809 <8>[ 30.085888] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11488 00:27:09.660641 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11490 00:27:09.673006 /lava-11280962/1/../bin/lava-test-case
11491 00:27:09.679369 <8>[ 30.105062] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11492 00:27:09.680247 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11494 00:27:09.696168 /lava-11280962/1/../bin/lava-tes<8>[ 30.121293] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11495 00:27:09.696729 t-case
11496 00:27:09.697374 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11498 00:27:09.707562 /lava-11280962/1/../bin/lava-test-case
11499 00:27:09.713968 <8>[ 30.139899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11500 00:27:09.714811 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11502 00:27:10.726410 /lava-11280962/1/../bin/lava-test-case
11503 00:27:10.735962 <8>[ 31.161861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11504 00:27:10.736313 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11506 00:27:11.748397 /lava-11280962/1/../bin/lava-test-case
11507 00:27:11.755236 <8>[ 32.182210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11508 00:27:11.756144 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11509 00:27:11.756615 Bad test result: blocked
11510 00:27:11.765323 /lava-11280962/1/../bin/lava-test-case
11511 00:27:11.772076 <8>[ 32.197984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11512 00:27:11.772928 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11514 00:27:12.786573 /lava-11280962/1/../bin/lava-test-case
11515 00:27:12.792967 <8>[ 33.220578] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11516 00:27:12.793732 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11518 00:27:12.801831 /lava-11280962/1/../bin/lava-test-case
11519 00:27:12.808594 <8>[ 33.234889] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11520 00:27:12.809352 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11522 00:27:12.823245 /lava-11280962/1/../bin/lava-test-case
11523 00:27:12.829905 <8>[ 33.255884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11524 00:27:12.830737 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11526 00:27:12.839485 /lava-11280962/1/../bin/lava-test-case
11527 00:27:12.845822 <8>[ 33.271887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11528 00:27:12.846661 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11530 00:27:12.862622 /lava-11280962/1/../bin/lava-tes<8>[ 33.288014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11531 00:27:12.863188 t-case
11532 00:27:12.863881 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11534 00:27:12.869415 /lava-11280962/1/../bin/lava-test-case
11535 00:27:12.880327 <8>[ 33.306632] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11536 00:27:12.881162 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11538 00:27:12.889902 /lava-11280962/1/../bin/lava-test-case
11539 00:27:12.896742 <8>[ 33.322788] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11540 00:27:12.897577 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11542 00:27:13.909898 /lava-11280962/1/../bin/lava-test-case
11543 00:27:13.916689 <8>[ 34.342801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11544 00:27:13.917526 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11546 00:27:13.933742 /lava-11280962/1/../bin/lava-tes<8>[ 34.358980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11547 00:27:13.934303 t-case
11548 00:27:13.934946 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11550 00:27:14.947130 /lava-11280962/1/../bin/lava-test-case
11551 00:27:14.953546 <8>[ 35.380126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11552 00:27:14.954382 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11554 00:27:14.964120 /lava-11280962/1/../bin/lava-test-case
11555 00:27:14.971030 <8>[ 35.398338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11556 00:27:14.971914 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11558 00:27:15.983787 /lava-11280962/1/../bin/lava-test-case
11559 00:27:15.990164 <8>[ 36.417054] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11560 00:27:15.990905 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11562 00:27:15.999967 /lava-11280962/1/../bin/lava-test-case
11563 00:27:16.006686 <8>[ 36.433237] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11564 00:27:16.007556 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11566 00:27:17.024387 /lava-11280962/1/../bin/lava-test-case
11567 00:27:17.030346 <8>[ 37.456975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11568 00:27:17.031081 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11570 00:27:17.048217 /lava-11280962/1/../bin/lava-tes<8>[ 37.474197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11571 00:27:17.048775 t-case
11572 00:27:17.049425 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11574 00:27:17.062312 /lava-11280962/1/../bin/lava-tes<8>[ 37.490924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11575 00:27:17.063165 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11577 00:27:17.064592 t-case
11578 00:27:17.076816 /lava-11280962/1/../bin/lava-test-case
11579 00:27:17.083948 <8>[ 37.511139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11580 00:27:17.084782 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11582 00:27:17.092187 /lava-11280962/1/../bin/lava-test-case
11583 00:27:17.098411 <8>[ 37.524818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11584 00:27:17.099227 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11586 00:27:17.110599 /lava-11280962/1/../bin/lava-test-case
11587 00:27:17.116834 <8>[ 37.543964] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11588 00:27:17.117563 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11590 00:27:17.136351 /lava-11280962/1/../bin/lava-tes<8>[ 37.562077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11591 00:27:17.136914 t-case
11592 00:27:17.137550 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11594 00:27:17.147456 /lava-11280962/1/../bin/lava-test-case
11595 00:27:17.153494 <8>[ 37.580263] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11596 00:27:17.154317 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11598 00:27:17.163449 /lava-11280962/1/../bin/lava-test-case
11599 00:27:17.169921 <8>[ 37.597029] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11600 00:27:17.170776 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11602 00:27:17.188544 /lava-11280962/1/../bin/lava-tes<8>[ 37.614456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11603 00:27:17.189113 t-case
11604 00:27:17.189764 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11606 00:27:17.192131 + set +x
11607 00:27:17.194960 <8>[ 37.624957] <LAVA_SIGNAL_ENDRUN 1_bootrr 11280962_1.5.2.3.5>
11608 00:27:17.195684 Received signal: <ENDRUN> 1_bootrr 11280962_1.5.2.3.5
11609 00:27:17.196105 Ending use of test pattern.
11610 00:27:17.196456 Ending test lava.1_bootrr (11280962_1.5.2.3.5), duration 20.37
11612 00:27:17.199447 <LAVA_TEST_RUNNER EXIT>
11613 00:27:17.200178 ok: lava_test_shell seems to have completed
11614 00:27:17.205781 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11615 00:27:17.206580 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11616 00:27:17.207065 end: 4 lava-test-retry (duration 00:00:21) [common]
11617 00:27:17.207587 start: 5 finalize (timeout 00:08:05) [common]
11618 00:27:17.208104 start: 5.1 power-off (timeout 00:00:30) [common]
11619 00:27:17.209287 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11620 00:27:17.332654 >> Command sent successfully.
11621 00:27:17.343987 Returned 0 in 0 seconds
11622 00:27:17.445246 end: 5.1 power-off (duration 00:00:00) [common]
11624 00:27:17.446643 start: 5.2 read-feedback (timeout 00:08:05) [common]
11625 00:27:17.447975 Listened to connection for namespace 'common' for up to 1s
11626 00:27:18.447866 Finalising connection for namespace 'common'
11627 00:27:18.448619 Disconnecting from shell: Finalise
11628 00:27:18.449091 / #
11629 00:27:18.550132 end: 5.2 read-feedback (duration 00:00:01) [common]
11630 00:27:18.550903 end: 5 finalize (duration 00:00:01) [common]
11631 00:27:18.551625 Cleaning after the job
11632 00:27:18.552199 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11280962/tftp-deploy-apdiwvfj/ramdisk
11633 00:27:18.568145 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11280962/tftp-deploy-apdiwvfj/kernel
11634 00:27:18.594935 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11280962/tftp-deploy-apdiwvfj/dtb
11635 00:27:18.595299 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11280962/tftp-deploy-apdiwvfj/modules
11636 00:27:18.606552 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11280962
11637 00:27:18.654211 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11280962
11638 00:27:18.654386 Job finished correctly