Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 27
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 38
- Errors: 1
1 00:23:48.005763 lava-dispatcher, installed at version: 2023.05.1
2 00:23:48.005973 start: 0 validate
3 00:23:48.006102 Start time: 2023-08-14 00:23:48.006095+00:00 (UTC)
4 00:23:48.006223 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:23:48.006353 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 00:23:48.276844 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:23:48.277659 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:24:11.297853 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:24:11.298602 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:24:11.561118 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:24:11.561844 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:24:12.083241 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:24:12.083979 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:24:14.091825 validate duration: 26.09
16 00:24:14.092126 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:24:14.092222 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:24:14.092305 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:24:14.092430 Not decompressing ramdisk as can be used compressed.
20 00:24:14.092515 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 00:24:14.092576 saving as /var/lib/lava/dispatcher/tmp/11280948/tftp-deploy-u7bwdy0v/ramdisk/initrd.cpio.gz
22 00:24:14.092634 total size: 4665412 (4MB)
23 00:24:14.355423 progress 0% (0MB)
24 00:24:14.357000 progress 5% (0MB)
25 00:24:14.358268 progress 10% (0MB)
26 00:24:14.359565 progress 15% (0MB)
27 00:24:14.360854 progress 20% (0MB)
28 00:24:14.362083 progress 25% (1MB)
29 00:24:14.363314 progress 30% (1MB)
30 00:24:14.364606 progress 35% (1MB)
31 00:24:14.365831 progress 40% (1MB)
32 00:24:14.367210 progress 45% (2MB)
33 00:24:14.368473 progress 50% (2MB)
34 00:24:14.369702 progress 55% (2MB)
35 00:24:14.370924 progress 60% (2MB)
36 00:24:14.372191 progress 65% (2MB)
37 00:24:14.373417 progress 70% (3MB)
38 00:24:14.374637 progress 75% (3MB)
39 00:24:14.375850 progress 80% (3MB)
40 00:24:14.377322 progress 85% (3MB)
41 00:24:14.378569 progress 90% (4MB)
42 00:24:14.379789 progress 95% (4MB)
43 00:24:14.381064 progress 100% (4MB)
44 00:24:14.381215 4MB downloaded in 0.29s (15.42MB/s)
45 00:24:14.381362 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:24:14.381600 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:24:14.381686 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:24:14.381769 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:24:14.381904 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:24:14.381972 saving as /var/lib/lava/dispatcher/tmp/11280948/tftp-deploy-u7bwdy0v/kernel/Image
52 00:24:14.382030 total size: 49220096 (46MB)
53 00:24:14.382088 No compression specified
54 00:24:14.383162 progress 0% (0MB)
55 00:24:14.396283 progress 5% (2MB)
56 00:24:14.409224 progress 10% (4MB)
57 00:24:14.421895 progress 15% (7MB)
58 00:24:14.434581 progress 20% (9MB)
59 00:24:14.447462 progress 25% (11MB)
60 00:24:14.460266 progress 30% (14MB)
61 00:24:14.473099 progress 35% (16MB)
62 00:24:14.485947 progress 40% (18MB)
63 00:24:14.498955 progress 45% (21MB)
64 00:24:14.512047 progress 50% (23MB)
65 00:24:14.524745 progress 55% (25MB)
66 00:24:14.537596 progress 60% (28MB)
67 00:24:14.550386 progress 65% (30MB)
68 00:24:14.563094 progress 70% (32MB)
69 00:24:14.575750 progress 75% (35MB)
70 00:24:14.588650 progress 80% (37MB)
71 00:24:14.601540 progress 85% (39MB)
72 00:24:14.614221 progress 90% (42MB)
73 00:24:14.626997 progress 95% (44MB)
74 00:24:14.639591 progress 100% (46MB)
75 00:24:14.639748 46MB downloaded in 0.26s (182.14MB/s)
76 00:24:14.639901 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:24:14.640137 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:24:14.640222 start: 1.3 download-retry (timeout 00:09:59) [common]
80 00:24:14.640313 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 00:24:14.640452 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:24:14.640520 saving as /var/lib/lava/dispatcher/tmp/11280948/tftp-deploy-u7bwdy0v/dtb/mt8192-asurada-spherion-r0.dtb
83 00:24:14.640580 total size: 47278 (0MB)
84 00:24:14.640638 No compression specified
85 00:24:14.641759 progress 69% (0MB)
86 00:24:14.642034 progress 100% (0MB)
87 00:24:14.642189 0MB downloaded in 0.00s (28.08MB/s)
88 00:24:14.642307 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:24:14.642526 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:24:14.642610 start: 1.4 download-retry (timeout 00:09:59) [common]
92 00:24:14.642691 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 00:24:14.642803 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 00:24:14.642869 saving as /var/lib/lava/dispatcher/tmp/11280948/tftp-deploy-u7bwdy0v/nfsrootfs/full.rootfs.tar
95 00:24:14.642928 total size: 125290964 (119MB)
96 00:24:14.642986 Using unxz to decompress xz
97 00:24:14.647103 progress 0% (0MB)
98 00:24:14.973188 progress 5% (6MB)
99 00:24:15.304612 progress 10% (11MB)
100 00:24:15.632662 progress 15% (17MB)
101 00:24:15.816486 progress 20% (23MB)
102 00:24:15.990364 progress 25% (29MB)
103 00:24:16.338569 progress 30% (35MB)
104 00:24:16.690810 progress 35% (41MB)
105 00:24:17.077182 progress 40% (47MB)
106 00:24:17.450702 progress 45% (53MB)
107 00:24:17.831723 progress 50% (59MB)
108 00:24:18.193378 progress 55% (65MB)
109 00:24:18.569738 progress 60% (71MB)
110 00:24:18.924770 progress 65% (77MB)
111 00:24:19.299813 progress 70% (83MB)
112 00:24:19.685310 progress 75% (89MB)
113 00:24:20.105562 progress 80% (95MB)
114 00:24:20.527174 progress 85% (101MB)
115 00:24:20.771226 progress 90% (107MB)
116 00:24:21.114217 progress 95% (113MB)
117 00:24:21.490494 progress 100% (119MB)
118 00:24:21.496281 119MB downloaded in 6.85s (17.43MB/s)
119 00:24:21.496740 end: 1.4.1 http-download (duration 00:00:07) [common]
121 00:24:21.497139 end: 1.4 download-retry (duration 00:00:07) [common]
122 00:24:21.497269 start: 1.5 download-retry (timeout 00:09:53) [common]
123 00:24:21.497393 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 00:24:21.497601 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:24:21.497701 saving as /var/lib/lava/dispatcher/tmp/11280948/tftp-deploy-u7bwdy0v/modules/modules.tar
126 00:24:21.497795 total size: 8562896 (8MB)
127 00:24:21.497888 Using unxz to decompress xz
128 00:24:21.503374 progress 0% (0MB)
129 00:24:21.525186 progress 5% (0MB)
130 00:24:21.547412 progress 10% (0MB)
131 00:24:21.574102 progress 15% (1MB)
132 00:24:21.600036 progress 20% (1MB)
133 00:24:21.626321 progress 25% (2MB)
134 00:24:21.652762 progress 30% (2MB)
135 00:24:21.678056 progress 35% (2MB)
136 00:24:21.703365 progress 40% (3MB)
137 00:24:21.728544 progress 45% (3MB)
138 00:24:21.754994 progress 50% (4MB)
139 00:24:21.780483 progress 55% (4MB)
140 00:24:21.805443 progress 60% (4MB)
141 00:24:21.828794 progress 65% (5MB)
142 00:24:21.854430 progress 70% (5MB)
143 00:24:21.878839 progress 75% (6MB)
144 00:24:21.907120 progress 80% (6MB)
145 00:24:21.937536 progress 85% (6MB)
146 00:24:21.963835 progress 90% (7MB)
147 00:24:21.988846 progress 95% (7MB)
148 00:24:22.012627 progress 100% (8MB)
149 00:24:22.017727 8MB downloaded in 0.52s (15.71MB/s)
150 00:24:22.018060 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:24:22.018333 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:24:22.018428 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 00:24:22.018519 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 00:24:24.173986 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11280948/extract-nfsrootfs-rrkj3bk2
156 00:24:24.174201 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 00:24:24.174300 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 00:24:24.174476 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy
159 00:24:24.174606 makedir: /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin
160 00:24:24.174705 makedir: /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/tests
161 00:24:24.174801 makedir: /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/results
162 00:24:24.174902 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-add-keys
163 00:24:24.175044 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-add-sources
164 00:24:24.175173 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-background-process-start
165 00:24:24.175298 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-background-process-stop
166 00:24:24.175422 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-common-functions
167 00:24:24.175544 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-echo-ipv4
168 00:24:24.175666 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-install-packages
169 00:24:24.175789 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-installed-packages
170 00:24:24.176159 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-os-build
171 00:24:24.176286 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-probe-channel
172 00:24:24.176408 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-probe-ip
173 00:24:24.176528 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-target-ip
174 00:24:24.176650 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-target-mac
175 00:24:24.176769 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-target-storage
176 00:24:24.176892 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-test-case
177 00:24:24.177017 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-test-event
178 00:24:24.177136 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-test-feedback
179 00:24:24.177256 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-test-raise
180 00:24:24.177393 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-test-reference
181 00:24:24.177513 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-test-runner
182 00:24:24.177634 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-test-set
183 00:24:24.177755 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-test-shell
184 00:24:24.177879 Updating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-install-packages (oe)
185 00:24:24.178031 Updating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/bin/lava-installed-packages (oe)
186 00:24:24.178152 Creating /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/environment
187 00:24:24.178248 LAVA metadata
188 00:24:24.178318 - LAVA_JOB_ID=11280948
189 00:24:24.178380 - LAVA_DISPATCHER_IP=192.168.201.1
190 00:24:24.178485 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 00:24:24.178551 skipped lava-vland-overlay
192 00:24:24.178624 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 00:24:24.178701 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 00:24:24.178761 skipped lava-multinode-overlay
195 00:24:24.178831 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 00:24:24.178906 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 00:24:24.178980 Loading test definitions
198 00:24:24.179068 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 00:24:24.179137 Using /lava-11280948 at stage 0
200 00:24:24.179463 uuid=11280948_1.6.2.3.1 testdef=None
201 00:24:24.179596 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 00:24:24.179717 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 00:24:24.180247 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 00:24:24.180465 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 00:24:24.181105 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 00:24:24.181331 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 00:24:24.181943 runner path: /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/0/tests/0_dmesg test_uuid 11280948_1.6.2.3.1
210 00:24:24.182097 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 00:24:24.182318 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:50) [common]
213 00:24:24.182388 Using /lava-11280948 at stage 1
214 00:24:24.182690 uuid=11280948_1.6.2.3.5 testdef=None
215 00:24:24.182777 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 00:24:24.182860 start: 1.6.2.3.6 test-overlay (timeout 00:09:50) [common]
217 00:24:24.183323 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 00:24:24.183534 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:50) [common]
220 00:24:24.184178 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 00:24:24.184405 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
223 00:24:24.185020 runner path: /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/1/tests/1_bootrr test_uuid 11280948_1.6.2.3.5
224 00:24:24.185170 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 00:24:24.185370 Creating lava-test-runner.conf files
227 00:24:24.185432 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/0 for stage 0
228 00:24:24.185520 - 0_dmesg
229 00:24:24.185598 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11280948/lava-overlay-kb7iw_sy/lava-11280948/1 for stage 1
230 00:24:24.185687 - 1_bootrr
231 00:24:24.185780 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 00:24:24.185864 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
233 00:24:24.193101 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 00:24:24.193254 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
235 00:24:24.193345 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 00:24:24.193431 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 00:24:24.193515 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
238 00:24:24.314919 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 00:24:24.315302 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
240 00:24:24.315468 extracting modules file /var/lib/lava/dispatcher/tmp/11280948/tftp-deploy-u7bwdy0v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11280948/extract-nfsrootfs-rrkj3bk2
241 00:24:24.536060 extracting modules file /var/lib/lava/dispatcher/tmp/11280948/tftp-deploy-u7bwdy0v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11280948/extract-overlay-ramdisk-omru0rn1/ramdisk
242 00:24:24.761586 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 00:24:24.761771 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 00:24:24.761859 [common] Applying overlay to NFS
245 00:24:24.761926 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11280948/compress-overlay-yp523mpp/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11280948/extract-nfsrootfs-rrkj3bk2
246 00:24:24.770003 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 00:24:24.770172 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 00:24:24.770272 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 00:24:24.770363 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 00:24:24.770445 Building ramdisk /var/lib/lava/dispatcher/tmp/11280948/extract-overlay-ramdisk-omru0rn1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11280948/extract-overlay-ramdisk-omru0rn1/ramdisk
251 00:24:25.097270 >> 118004 blocks
252 00:24:26.999494 rename /var/lib/lava/dispatcher/tmp/11280948/extract-overlay-ramdisk-omru0rn1/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11280948/tftp-deploy-u7bwdy0v/ramdisk/ramdisk.cpio.gz
253 00:24:26.999985 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 00:24:27.000106 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 00:24:27.000206 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 00:24:27.000314 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11280948/tftp-deploy-u7bwdy0v/kernel/Image'
257 00:24:39.439433 Returned 0 in 12 seconds
258 00:24:39.540642 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11280948/tftp-deploy-u7bwdy0v/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11280948/tftp-deploy-u7bwdy0v/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11280948/tftp-deploy-u7bwdy0v/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11280948/tftp-deploy-u7bwdy0v/kernel/image.itb
259 00:24:39.917054 output: FIT description: Kernel Image image with one or more FDT blobs
260 00:24:39.917417 output: Created: Mon Aug 14 01:24:39 2023
261 00:24:39.917499 output: Image 0 (kernel-1)
262 00:24:39.917569 output: Description:
263 00:24:39.917636 output: Created: Mon Aug 14 01:24:39 2023
264 00:24:39.917702 output: Type: Kernel Image
265 00:24:39.917761 output: Compression: lzma compressed
266 00:24:39.917819 output: Data Size: 11037315 Bytes = 10778.63 KiB = 10.53 MiB
267 00:24:39.917874 output: Architecture: AArch64
268 00:24:39.917934 output: OS: Linux
269 00:24:39.917988 output: Load Address: 0x00000000
270 00:24:39.918044 output: Entry Point: 0x00000000
271 00:24:39.918100 output: Hash algo: crc32
272 00:24:39.918155 output: Hash value: e7f77b4c
273 00:24:39.918207 output: Image 1 (fdt-1)
274 00:24:39.918259 output: Description: mt8192-asurada-spherion-r0
275 00:24:39.918310 output: Created: Mon Aug 14 01:24:39 2023
276 00:24:39.918362 output: Type: Flat Device Tree
277 00:24:39.918423 output: Compression: uncompressed
278 00:24:39.918547 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 00:24:39.918603 output: Architecture: AArch64
280 00:24:39.918656 output: Hash algo: crc32
281 00:24:39.918708 output: Hash value: cc4352de
282 00:24:39.918759 output: Image 2 (ramdisk-1)
283 00:24:39.918811 output: Description: unavailable
284 00:24:39.918862 output: Created: Mon Aug 14 01:24:39 2023
285 00:24:39.918914 output: Type: RAMDisk Image
286 00:24:39.918965 output: Compression: Unknown Compression
287 00:24:39.919017 output: Data Size: 17665145 Bytes = 17251.12 KiB = 16.85 MiB
288 00:24:39.919069 output: Architecture: AArch64
289 00:24:39.919121 output: OS: Linux
290 00:24:39.919172 output: Load Address: unavailable
291 00:24:39.919224 output: Entry Point: unavailable
292 00:24:39.919275 output: Hash algo: crc32
293 00:24:39.919327 output: Hash value: 3a7b58e2
294 00:24:39.919378 output: Default Configuration: 'conf-1'
295 00:24:39.919429 output: Configuration 0 (conf-1)
296 00:24:39.919480 output: Description: mt8192-asurada-spherion-r0
297 00:24:39.919532 output: Kernel: kernel-1
298 00:24:39.919584 output: Init Ramdisk: ramdisk-1
299 00:24:39.919635 output: FDT: fdt-1
300 00:24:39.919686 output: Loadables: kernel-1
301 00:24:39.919737 output:
302 00:24:39.919982 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 00:24:39.920083 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 00:24:39.920189 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
305 00:24:39.920280 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:34) [common]
306 00:24:39.920358 No LXC device requested
307 00:24:39.920435 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 00:24:39.920519 start: 1.8 deploy-device-env (timeout 00:09:34) [common]
309 00:24:39.920593 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 00:24:39.920662 Checking files for TFTP limit of 4294967296 bytes.
311 00:24:39.921161 end: 1 tftp-deploy (duration 00:00:26) [common]
312 00:24:39.921262 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 00:24:39.921353 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 00:24:39.921475 substitutions:
315 00:24:39.921543 - {DTB}: 11280948/tftp-deploy-u7bwdy0v/dtb/mt8192-asurada-spherion-r0.dtb
316 00:24:39.921605 - {INITRD}: 11280948/tftp-deploy-u7bwdy0v/ramdisk/ramdisk.cpio.gz
317 00:24:39.921663 - {KERNEL}: 11280948/tftp-deploy-u7bwdy0v/kernel/Image
318 00:24:39.921721 - {LAVA_MAC}: None
319 00:24:39.921776 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11280948/extract-nfsrootfs-rrkj3bk2
320 00:24:39.921831 - {NFS_SERVER_IP}: 192.168.201.1
321 00:24:39.921885 - {PRESEED_CONFIG}: None
322 00:24:39.921938 - {PRESEED_LOCAL}: None
323 00:24:39.921991 - {RAMDISK}: 11280948/tftp-deploy-u7bwdy0v/ramdisk/ramdisk.cpio.gz
324 00:24:39.922045 - {ROOT_PART}: None
325 00:24:39.922097 - {ROOT}: None
326 00:24:39.922151 - {SERVER_IP}: 192.168.201.1
327 00:24:39.922204 - {TEE}: None
328 00:24:39.922258 Parsed boot commands:
329 00:24:39.922310 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 00:24:39.922489 Parsed boot commands: tftpboot 192.168.201.1 11280948/tftp-deploy-u7bwdy0v/kernel/image.itb 11280948/tftp-deploy-u7bwdy0v/kernel/cmdline
331 00:24:39.922574 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 00:24:39.922656 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 00:24:39.922748 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 00:24:39.922831 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 00:24:39.922900 Not connected, no need to disconnect.
336 00:24:39.922972 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 00:24:39.923051 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 00:24:39.923116 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
339 00:24:39.927093 Setting prompt string to ['lava-test: # ']
340 00:24:39.927463 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 00:24:39.927576 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 00:24:39.927674 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 00:24:39.927763 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 00:24:39.928004 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
345 00:24:45.066461 >> Command sent successfully.
346 00:24:45.068940 Returned 0 in 5 seconds
347 00:24:45.169338 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 00:24:45.169756 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 00:24:45.169889 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 00:24:45.170006 Setting prompt string to 'Starting depthcharge on Spherion...'
352 00:24:45.170102 Changing prompt to 'Starting depthcharge on Spherion...'
353 00:24:45.170196 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 00:24:45.170559 [Enter `^Ec?' for help]
355 00:24:45.343517
356 00:24:45.343696
357 00:24:45.343795 F0: 102B 0000
358 00:24:45.343919
359 00:24:45.344010 F3: 1001 0000 [0200]
360 00:24:45.346403
361 00:24:45.346492 F3: 1001 0000
362 00:24:45.346558
363 00:24:45.346619 F7: 102D 0000
364 00:24:45.346725
365 00:24:45.349598 F1: 0000 0000
366 00:24:45.349680
367 00:24:45.349745 V0: 0000 0000 [0001]
368 00:24:45.349809
369 00:24:45.353010 00: 0007 8000
370 00:24:45.353096
371 00:24:45.353161 01: 0000 0000
372 00:24:45.353222
373 00:24:45.356277 BP: 0C00 0209 [0000]
374 00:24:45.356359
375 00:24:45.356424 G0: 1182 0000
376 00:24:45.356485
377 00:24:45.359898 EC: 0000 0021 [4000]
378 00:24:45.360018
379 00:24:45.360096 S7: 0000 0000 [0000]
380 00:24:45.360158
381 00:24:45.364252 CC: 0000 0000 [0001]
382 00:24:45.364333
383 00:24:45.364398 T0: 0000 0040 [010F]
384 00:24:45.364461
385 00:24:45.364519 Jump to BL
386 00:24:45.364576
387 00:24:45.390633
388 00:24:45.390721
389 00:24:45.390786
390 00:24:45.397753 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 00:24:45.401126 ARM64: Exception handlers installed.
392 00:24:45.404504 ARM64: Testing exception
393 00:24:45.407949 ARM64: Done test exception
394 00:24:45.415247 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 00:24:45.425261 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 00:24:45.431824 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 00:24:45.441356 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 00:24:45.448276 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 00:24:45.454780 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 00:24:45.467191 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 00:24:45.473843 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 00:24:45.493382 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 00:24:45.496687 WDT: Last reset was cold boot
404 00:24:45.500032 SPI1(PAD0) initialized at 2873684 Hz
405 00:24:45.503065 SPI5(PAD0) initialized at 992727 Hz
406 00:24:45.506667 VBOOT: Loading verstage.
407 00:24:45.513005 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 00:24:45.516535 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 00:24:45.520563 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 00:24:45.522796 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 00:24:45.530642 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 00:24:45.536965 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 00:24:45.548617 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
414 00:24:45.548727
415 00:24:45.548835
416 00:24:45.557853 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 00:24:45.561177 ARM64: Exception handlers installed.
418 00:24:45.564680 ARM64: Testing exception
419 00:24:45.564762 ARM64: Done test exception
420 00:24:45.571850 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 00:24:45.575193 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 00:24:45.588820 Probing TPM: . done!
423 00:24:45.588901 TPM ready after 0 ms
424 00:24:45.596293 Connected to device vid:did:rid of 1ae0:0028:00
425 00:24:45.603601 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
426 00:24:45.661427 Initialized TPM device CR50 revision 0
427 00:24:45.673239 tlcl_send_startup: Startup return code is 0
428 00:24:45.673338 TPM: setup succeeded
429 00:24:45.684804 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 00:24:45.693561 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 00:24:45.705774 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 00:24:45.715798 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 00:24:45.719254 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 00:24:45.722842 in-header: 03 07 00 00 08 00 00 00
435 00:24:45.726596 in-data: aa e4 47 04 13 02 00 00
436 00:24:45.729872 Chrome EC: UHEPI supported
437 00:24:45.737023 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 00:24:45.741268 in-header: 03 95 00 00 08 00 00 00
439 00:24:45.744591 in-data: 18 20 20 08 00 00 00 00
440 00:24:45.744669 Phase 1
441 00:24:45.748281 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 00:24:45.752230 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 00:24:45.760305 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 00:24:45.763006 Recovery requested (1009000e)
445 00:24:45.771313 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 00:24:45.776872 tlcl_extend: response is 0
447 00:24:45.786108 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 00:24:45.791508 tlcl_extend: response is 0
449 00:24:45.798412 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 00:24:45.818747 read SPI 0x210d4 0x2173b: 15142 us, 9048 KB/s, 72.384 Mbps
451 00:24:45.824846 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 00:24:45.824935
453 00:24:45.825037
454 00:24:45.835190 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 00:24:45.838228 ARM64: Exception handlers installed.
456 00:24:45.841856 ARM64: Testing exception
457 00:24:45.841935 ARM64: Done test exception
458 00:24:45.863842 pmic_efuse_setting: Set efuses in 11 msecs
459 00:24:45.867350 pmwrap_interface_init: Select PMIF_VLD_RDY
460 00:24:45.873905 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 00:24:45.877374 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 00:24:45.884163 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 00:24:45.888060 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 00:24:45.892082 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 00:24:45.899509 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 00:24:45.903090 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 00:24:45.907327 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 00:24:45.910247 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 00:24:45.917764 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 00:24:45.921734 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 00:24:45.924929 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 00:24:45.928545 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 00:24:45.936617 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 00:24:45.943964 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 00:24:45.947600 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 00:24:45.954744 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 00:24:45.958022 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 00:24:45.965801 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 00:24:45.969332 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 00:24:45.976975 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 00:24:45.980396 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 00:24:45.987655 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 00:24:45.991468 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 00:24:45.998963 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 00:24:46.001797 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 00:24:46.009311 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 00:24:46.012937 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 00:24:46.016616 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 00:24:46.023809 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 00:24:46.027579 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 00:24:46.034852 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 00:24:46.038362 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 00:24:46.042551 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 00:24:46.048774 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 00:24:46.052198 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 00:24:46.059213 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 00:24:46.063006 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 00:24:46.066781 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 00:24:46.070317 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 00:24:46.077473 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 00:24:46.081295 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 00:24:46.085240 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 00:24:46.088956 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 00:24:46.092696 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 00:24:46.100140 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 00:24:46.103239 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 00:24:46.106668 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 00:24:46.110875 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 00:24:46.114173 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 00:24:46.117609 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 00:24:46.125326 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 00:24:46.136559 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 00:24:46.139869 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 00:24:46.147071 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 00:24:46.159206 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 00:24:46.162336 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 00:24:46.165960 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 00:24:46.169241 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 00:24:46.176948 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x17
520 00:24:46.184423 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 00:24:46.188356 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
522 00:24:46.191086 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 00:24:46.201492 [RTC]rtc_get_frequency_meter,154: input=15, output=853
524 00:24:46.211613 [RTC]rtc_get_frequency_meter,154: input=7, output=725
525 00:24:46.220153 [RTC]rtc_get_frequency_meter,154: input=11, output=790
526 00:24:46.229829 [RTC]rtc_get_frequency_meter,154: input=13, output=822
527 00:24:46.239869 [RTC]rtc_get_frequency_meter,154: input=12, output=806
528 00:24:46.249126 [RTC]rtc_get_frequency_meter,154: input=11, output=789
529 00:24:46.258208 [RTC]rtc_get_frequency_meter,154: input=12, output=805
530 00:24:46.261731 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
531 00:24:46.269688 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
532 00:24:46.273617 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 00:24:46.276751 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 00:24:46.280581 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 00:24:46.284203 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 00:24:46.287497 ADC[4]: Raw value=904064 ID=7
537 00:24:46.291460 ADC[3]: Raw value=213546 ID=1
538 00:24:46.291538 RAM Code: 0x71
539 00:24:46.294914 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 00:24:46.302342 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 00:24:46.309807 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 00:24:46.317644 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 00:24:46.320890 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 00:24:46.324474 in-header: 03 07 00 00 08 00 00 00
545 00:24:46.324562 in-data: aa e4 47 04 13 02 00 00
546 00:24:46.328299 Chrome EC: UHEPI supported
547 00:24:46.335879 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 00:24:46.338779 in-header: 03 95 00 00 08 00 00 00
549 00:24:46.342857 in-data: 18 20 20 08 00 00 00 00
550 00:24:46.346158 MRC: failed to locate region type 0.
551 00:24:46.354005 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 00:24:46.354097 DRAM-K: Running full calibration
553 00:24:46.361702 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 00:24:46.365281 header.status = 0x0
555 00:24:46.365384 header.version = 0x6 (expected: 0x6)
556 00:24:46.368800 header.size = 0xd00 (expected: 0xd00)
557 00:24:46.372430 header.flags = 0x0
558 00:24:46.379547 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 00:24:46.396429 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
560 00:24:46.403870 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 00:24:46.404002 dram_init: ddr_geometry: 2
562 00:24:46.407607 [EMI] MDL number = 2
563 00:24:46.407689 [EMI] Get MDL freq = 0
564 00:24:46.410953 dram_init: ddr_type: 0
565 00:24:46.414968 is_discrete_lpddr4: 1
566 00:24:46.419160 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 00:24:46.419242
568 00:24:46.419306
569 00:24:46.419366 [Bian_co] ETT version 0.0.0.1
570 00:24:46.426081 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 00:24:46.426163
572 00:24:46.429539 dramc_set_vcore_voltage set vcore to 650000
573 00:24:46.429620 Read voltage for 800, 4
574 00:24:46.429685 Vio18 = 0
575 00:24:46.433119 Vcore = 650000
576 00:24:46.433233 Vdram = 0
577 00:24:46.433298 Vddq = 0
578 00:24:46.436670 Vmddr = 0
579 00:24:46.436754 dram_init: config_dvfs: 1
580 00:24:46.443908 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 00:24:46.447238 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 00:24:46.450515 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
583 00:24:46.456669 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
584 00:24:46.460379 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
585 00:24:46.463898 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
586 00:24:46.464008 MEM_TYPE=3, freq_sel=18
587 00:24:46.467580 sv_algorithm_assistance_LP4_1600
588 00:24:46.471453 ============ PULL DRAM RESETB DOWN ============
589 00:24:46.478437 ========== PULL DRAM RESETB DOWN end =========
590 00:24:46.482078 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 00:24:46.485663 ===================================
592 00:24:46.485745 LPDDR4 DRAM CONFIGURATION
593 00:24:46.488823 ===================================
594 00:24:46.492870 EX_ROW_EN[0] = 0x0
595 00:24:46.496225 EX_ROW_EN[1] = 0x0
596 00:24:46.496307 LP4Y_EN = 0x0
597 00:24:46.498994 WORK_FSP = 0x0
598 00:24:46.499139 WL = 0x2
599 00:24:46.502095 RL = 0x2
600 00:24:46.502178 BL = 0x2
601 00:24:46.505733 RPST = 0x0
602 00:24:46.505815 RD_PRE = 0x0
603 00:24:46.508880 WR_PRE = 0x1
604 00:24:46.508962 WR_PST = 0x0
605 00:24:46.512355 DBI_WR = 0x0
606 00:24:46.512437 DBI_RD = 0x0
607 00:24:46.515273 OTF = 0x1
608 00:24:46.518705 ===================================
609 00:24:46.521764 ===================================
610 00:24:46.521846 ANA top config
611 00:24:46.525468 ===================================
612 00:24:46.528654 DLL_ASYNC_EN = 0
613 00:24:46.531886 ALL_SLAVE_EN = 1
614 00:24:46.535895 NEW_RANK_MODE = 1
615 00:24:46.536017 DLL_IDLE_MODE = 1
616 00:24:46.538518 LP45_APHY_COMB_EN = 1
617 00:24:46.541886 TX_ODT_DIS = 1
618 00:24:46.545862 NEW_8X_MODE = 1
619 00:24:46.548642 ===================================
620 00:24:46.551798 ===================================
621 00:24:46.555425 data_rate = 1600
622 00:24:46.555507 CKR = 1
623 00:24:46.558377 DQ_P2S_RATIO = 8
624 00:24:46.561987 ===================================
625 00:24:46.565362 CA_P2S_RATIO = 8
626 00:24:46.569217 DQ_CA_OPEN = 0
627 00:24:46.572866 DQ_SEMI_OPEN = 0
628 00:24:46.572990 CA_SEMI_OPEN = 0
629 00:24:46.576266 CA_FULL_RATE = 0
630 00:24:46.579163 DQ_CKDIV4_EN = 1
631 00:24:46.582752 CA_CKDIV4_EN = 1
632 00:24:46.585989 CA_PREDIV_EN = 0
633 00:24:46.586064 PH8_DLY = 0
634 00:24:46.588896 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 00:24:46.592493 DQ_AAMCK_DIV = 4
636 00:24:46.595649 CA_AAMCK_DIV = 4
637 00:24:46.598914 CA_ADMCK_DIV = 4
638 00:24:46.602478 DQ_TRACK_CA_EN = 0
639 00:24:46.602559 CA_PICK = 800
640 00:24:46.605893 CA_MCKIO = 800
641 00:24:46.608911 MCKIO_SEMI = 0
642 00:24:46.613472 PLL_FREQ = 3068
643 00:24:46.617044 DQ_UI_PI_RATIO = 32
644 00:24:46.620611 CA_UI_PI_RATIO = 0
645 00:24:46.620697 ===================================
646 00:24:46.624095 ===================================
647 00:24:46.627653 memory_type:LPDDR4
648 00:24:46.632079 GP_NUM : 10
649 00:24:46.632163 SRAM_EN : 1
650 00:24:46.635300 MD32_EN : 0
651 00:24:46.638736 ===================================
652 00:24:46.638816 [ANA_INIT] >>>>>>>>>>>>>>
653 00:24:46.642841 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 00:24:46.645852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 00:24:46.649172 ===================================
656 00:24:46.652516 data_rate = 1600,PCW = 0X7600
657 00:24:46.656561 ===================================
658 00:24:46.659129 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 00:24:46.662643 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 00:24:46.669273 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 00:24:46.672661 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 00:24:46.675725 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 00:24:46.679414 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 00:24:46.682533 [ANA_INIT] flow start
665 00:24:46.685711 [ANA_INIT] PLL >>>>>>>>
666 00:24:46.685788 [ANA_INIT] PLL <<<<<<<<
667 00:24:46.689379 [ANA_INIT] MIDPI >>>>>>>>
668 00:24:46.692934 [ANA_INIT] MIDPI <<<<<<<<
669 00:24:46.695865 [ANA_INIT] DLL >>>>>>>>
670 00:24:46.695990 [ANA_INIT] flow end
671 00:24:46.699146 ============ LP4 DIFF to SE enter ============
672 00:24:46.705688 ============ LP4 DIFF to SE exit ============
673 00:24:46.705769 [ANA_INIT] <<<<<<<<<<<<<
674 00:24:46.709277 [Flow] Enable top DCM control >>>>>
675 00:24:46.712302 [Flow] Enable top DCM control <<<<<
676 00:24:46.715582 Enable DLL master slave shuffle
677 00:24:46.722326 ==============================================================
678 00:24:46.722403 Gating Mode config
679 00:24:46.729126 ==============================================================
680 00:24:46.732540 Config description:
681 00:24:46.738998 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 00:24:46.748879 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 00:24:46.752480 SELPH_MODE 0: By rank 1: By Phase
684 00:24:46.758783 ==============================================================
685 00:24:46.762025 GAT_TRACK_EN = 1
686 00:24:46.762100 RX_GATING_MODE = 2
687 00:24:46.765427 RX_GATING_TRACK_MODE = 2
688 00:24:46.768786 SELPH_MODE = 1
689 00:24:46.771984 PICG_EARLY_EN = 1
690 00:24:46.775406 VALID_LAT_VALUE = 1
691 00:24:46.782407 ==============================================================
692 00:24:46.785331 Enter into Gating configuration >>>>
693 00:24:46.788804 Exit from Gating configuration <<<<
694 00:24:46.791873 Enter into DVFS_PRE_config >>>>>
695 00:24:46.802484 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 00:24:46.805711 Exit from DVFS_PRE_config <<<<<
697 00:24:46.808727 Enter into PICG configuration >>>>
698 00:24:46.812073 Exit from PICG configuration <<<<
699 00:24:46.815563 [RX_INPUT] configuration >>>>>
700 00:24:46.818706 [RX_INPUT] configuration <<<<<
701 00:24:46.822129 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 00:24:46.828653 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 00:24:46.835505 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 00:24:46.838452 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 00:24:46.845647 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 00:24:46.851894 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 00:24:46.855419 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 00:24:46.861728 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 00:24:46.865149 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 00:24:46.868425 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 00:24:46.871655 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 00:24:46.878447 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 00:24:46.882056 ===================================
714 00:24:46.882143 LPDDR4 DRAM CONFIGURATION
715 00:24:46.884955 ===================================
716 00:24:46.888200 EX_ROW_EN[0] = 0x0
717 00:24:46.892013 EX_ROW_EN[1] = 0x0
718 00:24:46.892096 LP4Y_EN = 0x0
719 00:24:46.895408 WORK_FSP = 0x0
720 00:24:46.895482 WL = 0x2
721 00:24:46.898319 RL = 0x2
722 00:24:46.898393 BL = 0x2
723 00:24:46.901894 RPST = 0x0
724 00:24:46.901967 RD_PRE = 0x0
725 00:24:46.905044 WR_PRE = 0x1
726 00:24:46.905117 WR_PST = 0x0
727 00:24:46.908324 DBI_WR = 0x0
728 00:24:46.908401 DBI_RD = 0x0
729 00:24:46.911599 OTF = 0x1
730 00:24:46.915339 ===================================
731 00:24:46.917973 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 00:24:46.921614 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 00:24:46.928038 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 00:24:46.931148 ===================================
735 00:24:46.931225 LPDDR4 DRAM CONFIGURATION
736 00:24:46.934404 ===================================
737 00:24:46.938030 EX_ROW_EN[0] = 0x10
738 00:24:46.941500 EX_ROW_EN[1] = 0x0
739 00:24:46.941577 LP4Y_EN = 0x0
740 00:24:46.944657 WORK_FSP = 0x0
741 00:24:46.944759 WL = 0x2
742 00:24:46.947703 RL = 0x2
743 00:24:46.947782 BL = 0x2
744 00:24:46.951215 RPST = 0x0
745 00:24:46.951289 RD_PRE = 0x0
746 00:24:46.954631 WR_PRE = 0x1
747 00:24:46.954715 WR_PST = 0x0
748 00:24:46.958161 DBI_WR = 0x0
749 00:24:46.958271 DBI_RD = 0x0
750 00:24:46.961346 OTF = 0x1
751 00:24:46.964574 ===================================
752 00:24:46.971056 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 00:24:46.974119 nWR fixed to 40
754 00:24:46.974199 [ModeRegInit_LP4] CH0 RK0
755 00:24:46.977610 [ModeRegInit_LP4] CH0 RK1
756 00:24:46.981494 [ModeRegInit_LP4] CH1 RK0
757 00:24:46.984558 [ModeRegInit_LP4] CH1 RK1
758 00:24:46.984635 match AC timing 13
759 00:24:46.991195 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 00:24:46.994683 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 00:24:46.997650 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 00:24:47.004137 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 00:24:47.007450 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 00:24:47.007532 [EMI DOE] emi_dcm 0
765 00:24:47.014063 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 00:24:47.014142 ==
767 00:24:47.017616 Dram Type= 6, Freq= 0, CH_0, rank 0
768 00:24:47.020810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 00:24:47.020894 ==
770 00:24:47.027122 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 00:24:47.030566 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 00:24:47.041004 [CA 0] Center 37 (7~68) winsize 62
773 00:24:47.044318 [CA 1] Center 37 (7~68) winsize 62
774 00:24:47.047854 [CA 2] Center 34 (4~65) winsize 62
775 00:24:47.050937 [CA 3] Center 34 (4~65) winsize 62
776 00:24:47.054325 [CA 4] Center 33 (3~64) winsize 62
777 00:24:47.057462 [CA 5] Center 33 (3~64) winsize 62
778 00:24:47.057543
779 00:24:47.061041 [CmdBusTrainingLP45] Vref(ca) range 1: 32
780 00:24:47.061118
781 00:24:47.064390 [CATrainingPosCal] consider 1 rank data
782 00:24:47.067828 u2DelayCellTimex100 = 270/100 ps
783 00:24:47.071084 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
784 00:24:47.077635 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
785 00:24:47.080884 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
786 00:24:47.084021 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
787 00:24:47.087308 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
788 00:24:47.090886 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
789 00:24:47.090962
790 00:24:47.094195 CA PerBit enable=1, Macro0, CA PI delay=33
791 00:24:47.094271
792 00:24:47.097841 [CBTSetCACLKResult] CA Dly = 33
793 00:24:47.097969 CS Dly: 5 (0~36)
794 00:24:47.101137 ==
795 00:24:47.104367 Dram Type= 6, Freq= 0, CH_0, rank 1
796 00:24:47.107828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 00:24:47.107944 ==
798 00:24:47.111222 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 00:24:47.117217 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 00:24:47.127803 [CA 0] Center 38 (7~69) winsize 63
801 00:24:47.130861 [CA 1] Center 37 (7~68) winsize 62
802 00:24:47.134007 [CA 2] Center 35 (4~66) winsize 63
803 00:24:47.137701 [CA 3] Center 35 (4~66) winsize 63
804 00:24:47.140780 [CA 4] Center 34 (3~65) winsize 63
805 00:24:47.144169 [CA 5] Center 33 (3~64) winsize 62
806 00:24:47.144247
807 00:24:47.147683 [CmdBusTrainingLP45] Vref(ca) range 1: 34
808 00:24:47.147764
809 00:24:47.150708 [CATrainingPosCal] consider 2 rank data
810 00:24:47.154050 u2DelayCellTimex100 = 270/100 ps
811 00:24:47.157787 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
812 00:24:47.160529 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
813 00:24:47.167577 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
814 00:24:47.170656 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
815 00:24:47.173935 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
816 00:24:47.177228 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
817 00:24:47.177312
818 00:24:47.180361 CA PerBit enable=1, Macro0, CA PI delay=33
819 00:24:47.180441
820 00:24:47.184297 [CBTSetCACLKResult] CA Dly = 33
821 00:24:47.184375 CS Dly: 6 (0~38)
822 00:24:47.184440
823 00:24:47.187335 ----->DramcWriteLeveling(PI) begin...
824 00:24:47.190253 ==
825 00:24:47.194582 Dram Type= 6, Freq= 0, CH_0, rank 0
826 00:24:47.198208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 00:24:47.198288 ==
828 00:24:47.201868 Write leveling (Byte 0): 31 => 31
829 00:24:47.201946 Write leveling (Byte 1): 27 => 27
830 00:24:47.206087 DramcWriteLeveling(PI) end<-----
831 00:24:47.206169
832 00:24:47.206234 ==
833 00:24:47.209202 Dram Type= 6, Freq= 0, CH_0, rank 0
834 00:24:47.212638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 00:24:47.212717 ==
836 00:24:47.215829 [Gating] SW mode calibration
837 00:24:47.222987 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 00:24:47.229382 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 00:24:47.232642 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 00:24:47.236546 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
841 00:24:47.242890 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
842 00:24:47.245868 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
843 00:24:47.249391 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 00:24:47.255799 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 00:24:47.259222 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 00:24:47.262859 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 00:24:47.269147 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 00:24:47.272771 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 00:24:47.276697 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 00:24:47.283141 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 00:24:47.285970 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 00:24:47.289169 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 00:24:47.295836 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 00:24:47.299036 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 00:24:47.303206 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
856 00:24:47.309765 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
857 00:24:47.312281 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
858 00:24:47.315625 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:24:47.322577 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:24:47.325581 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:24:47.329221 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:24:47.336019 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:24:47.339239 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 00:24:47.343015 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 00:24:47.346008 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
866 00:24:47.352339 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
867 00:24:47.356137 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 00:24:47.359034 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 00:24:47.365796 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 00:24:47.368988 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 00:24:47.372579 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 00:24:47.378918 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
873 00:24:47.382213 0 10 8 | B1->B0 | 3131 2727 | 1 1 | (1 1) (1 0)
874 00:24:47.385499 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
875 00:24:47.392041 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 00:24:47.395342 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 00:24:47.399301 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 00:24:47.405716 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 00:24:47.408512 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 00:24:47.411966 0 11 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
881 00:24:47.418263 0 11 8 | B1->B0 | 2828 4545 | 0 0 | (0 0) (0 0)
882 00:24:47.421856 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
883 00:24:47.425222 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 00:24:47.431683 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 00:24:47.434877 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 00:24:47.438608 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 00:24:47.445084 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 00:24:47.448905 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
889 00:24:47.451474 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
890 00:24:47.458669 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 00:24:47.461298 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 00:24:47.464796 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 00:24:47.471417 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 00:24:47.475279 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 00:24:47.477673 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 00:24:47.484654 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 00:24:47.487709 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 00:24:47.491087 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 00:24:47.498064 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 00:24:47.501782 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 00:24:47.504433 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 00:24:47.511584 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 00:24:47.514269 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 00:24:47.517886 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
905 00:24:47.524304 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
906 00:24:47.524389 Total UI for P1: 0, mck2ui 16
907 00:24:47.531142 best dqsien dly found for B0: ( 0, 14, 4)
908 00:24:47.534649 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
909 00:24:47.537497 Total UI for P1: 0, mck2ui 16
910 00:24:47.541354 best dqsien dly found for B1: ( 0, 14, 10)
911 00:24:47.544218 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
912 00:24:47.547423 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
913 00:24:47.547510
914 00:24:47.551217 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
915 00:24:47.554212 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
916 00:24:47.557442 [Gating] SW calibration Done
917 00:24:47.557515 ==
918 00:24:47.560629 Dram Type= 6, Freq= 0, CH_0, rank 0
919 00:24:47.563832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 00:24:47.568064 ==
921 00:24:47.568210 RX Vref Scan: 0
922 00:24:47.568328
923 00:24:47.571563 RX Vref 0 -> 0, step: 1
924 00:24:47.571674
925 00:24:47.571768 RX Delay -130 -> 252, step: 16
926 00:24:47.578547 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
927 00:24:47.581764 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
928 00:24:47.584869 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
929 00:24:47.588162 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
930 00:24:47.591693 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
931 00:24:47.597968 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
932 00:24:47.601064 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
933 00:24:47.604565 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
934 00:24:47.607793 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
935 00:24:47.611446 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
936 00:24:47.618201 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
937 00:24:47.621302 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
938 00:24:47.624743 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
939 00:24:47.627691 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
940 00:24:47.631233 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
941 00:24:47.637868 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
942 00:24:47.637951 ==
943 00:24:47.640986 Dram Type= 6, Freq= 0, CH_0, rank 0
944 00:24:47.644381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
945 00:24:47.644464 ==
946 00:24:47.644529 DQS Delay:
947 00:24:47.648155 DQS0 = 0, DQS1 = 0
948 00:24:47.648263 DQM Delay:
949 00:24:47.651230 DQM0 = 89, DQM1 = 75
950 00:24:47.651311 DQ Delay:
951 00:24:47.654830 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
952 00:24:47.657579 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
953 00:24:47.661262 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
954 00:24:47.664842 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
955 00:24:47.664924
956 00:24:47.664989
957 00:24:47.665048 ==
958 00:24:47.667806 Dram Type= 6, Freq= 0, CH_0, rank 0
959 00:24:47.670920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 00:24:47.674534 ==
961 00:24:47.674612
962 00:24:47.674677
963 00:24:47.674746 TX Vref Scan disable
964 00:24:47.677773 == TX Byte 0 ==
965 00:24:47.680947 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
966 00:24:47.684401 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
967 00:24:47.687477 == TX Byte 1 ==
968 00:24:47.691756 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
969 00:24:47.694464 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
970 00:24:47.694546 ==
971 00:24:47.697934 Dram Type= 6, Freq= 0, CH_0, rank 0
972 00:24:47.704382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 00:24:47.704464 ==
974 00:24:47.716902 TX Vref=22, minBit 9, minWin=26, winSum=439
975 00:24:47.720061 TX Vref=24, minBit 0, minWin=27, winSum=443
976 00:24:47.723537 TX Vref=26, minBit 1, minWin=27, winSum=445
977 00:24:47.726495 TX Vref=28, minBit 1, minWin=27, winSum=446
978 00:24:47.729879 TX Vref=30, minBit 8, minWin=27, winSum=451
979 00:24:47.733301 TX Vref=32, minBit 9, minWin=27, winSum=450
980 00:24:47.740441 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 30
981 00:24:47.740520
982 00:24:47.743820 Final TX Range 1 Vref 30
983 00:24:47.743937
984 00:24:47.744032 ==
985 00:24:47.746863 Dram Type= 6, Freq= 0, CH_0, rank 0
986 00:24:47.749972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 00:24:47.750088 ==
988 00:24:47.753419
989 00:24:47.753502
990 00:24:47.753560 TX Vref Scan disable
991 00:24:47.757041 == TX Byte 0 ==
992 00:24:47.760507 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
993 00:24:47.763321 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
994 00:24:47.766736 == TX Byte 1 ==
995 00:24:47.770502 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
996 00:24:47.773718 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
997 00:24:47.776897
998 00:24:47.776977 [DATLAT]
999 00:24:47.777040 Freq=800, CH0 RK0
1000 00:24:47.777100
1001 00:24:47.780787 DATLAT Default: 0xa
1002 00:24:47.780867 0, 0xFFFF, sum = 0
1003 00:24:47.783157 1, 0xFFFF, sum = 0
1004 00:24:47.783240 2, 0xFFFF, sum = 0
1005 00:24:47.786951 3, 0xFFFF, sum = 0
1006 00:24:47.787033 4, 0xFFFF, sum = 0
1007 00:24:47.790049 5, 0xFFFF, sum = 0
1008 00:24:47.793575 6, 0xFFFF, sum = 0
1009 00:24:47.793698 7, 0xFFFF, sum = 0
1010 00:24:47.796740 8, 0xFFFF, sum = 0
1011 00:24:47.796823 9, 0x0, sum = 1
1012 00:24:47.796901 10, 0x0, sum = 2
1013 00:24:47.800347 11, 0x0, sum = 3
1014 00:24:47.800447 12, 0x0, sum = 4
1015 00:24:47.803393 best_step = 10
1016 00:24:47.803473
1017 00:24:47.803536 ==
1018 00:24:47.807127 Dram Type= 6, Freq= 0, CH_0, rank 0
1019 00:24:47.809996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1020 00:24:47.810091 ==
1021 00:24:47.813029 RX Vref Scan: 1
1022 00:24:47.813104
1023 00:24:47.813190 Set Vref Range= 32 -> 127
1024 00:24:47.817005
1025 00:24:47.817085 RX Vref 32 -> 127, step: 1
1026 00:24:47.817153
1027 00:24:47.820130 RX Delay -111 -> 252, step: 8
1028 00:24:47.820207
1029 00:24:47.823107 Set Vref, RX VrefLevel [Byte0]: 32
1030 00:24:47.826751 [Byte1]: 32
1031 00:24:47.826825
1032 00:24:47.829793 Set Vref, RX VrefLevel [Byte0]: 33
1033 00:24:47.833205 [Byte1]: 33
1034 00:24:47.837602
1035 00:24:47.837684 Set Vref, RX VrefLevel [Byte0]: 34
1036 00:24:47.840258 [Byte1]: 34
1037 00:24:47.844692
1038 00:24:47.844769 Set Vref, RX VrefLevel [Byte0]: 35
1039 00:24:47.847977 [Byte1]: 35
1040 00:24:47.852124
1041 00:24:47.852198 Set Vref, RX VrefLevel [Byte0]: 36
1042 00:24:47.855890 [Byte1]: 36
1043 00:24:47.860896
1044 00:24:47.860973 Set Vref, RX VrefLevel [Byte0]: 37
1045 00:24:47.863833 [Byte1]: 37
1046 00:24:47.868376
1047 00:24:47.868453 Set Vref, RX VrefLevel [Byte0]: 38
1048 00:24:47.871390 [Byte1]: 38
1049 00:24:47.875500
1050 00:24:47.875573 Set Vref, RX VrefLevel [Byte0]: 39
1051 00:24:47.879167 [Byte1]: 39
1052 00:24:47.883304
1053 00:24:47.883378 Set Vref, RX VrefLevel [Byte0]: 40
1054 00:24:47.886853 [Byte1]: 40
1055 00:24:47.890804
1056 00:24:47.890881 Set Vref, RX VrefLevel [Byte0]: 41
1057 00:24:47.894087 [Byte1]: 41
1058 00:24:47.898231
1059 00:24:47.898308 Set Vref, RX VrefLevel [Byte0]: 42
1060 00:24:47.902215 [Byte1]: 42
1061 00:24:47.905733
1062 00:24:47.909196 Set Vref, RX VrefLevel [Byte0]: 43
1063 00:24:47.909278 [Byte1]: 43
1064 00:24:47.913456
1065 00:24:47.913527 Set Vref, RX VrefLevel [Byte0]: 44
1066 00:24:47.917237 [Byte1]: 44
1067 00:24:47.921029
1068 00:24:47.921134 Set Vref, RX VrefLevel [Byte0]: 45
1069 00:24:47.924343 [Byte1]: 45
1070 00:24:47.929751
1071 00:24:47.929828 Set Vref, RX VrefLevel [Byte0]: 46
1072 00:24:47.932439 [Byte1]: 46
1073 00:24:47.936691
1074 00:24:47.936777 Set Vref, RX VrefLevel [Byte0]: 47
1075 00:24:47.939651 [Byte1]: 47
1076 00:24:47.944543
1077 00:24:47.944632 Set Vref, RX VrefLevel [Byte0]: 48
1078 00:24:47.947677 [Byte1]: 48
1079 00:24:47.951646
1080 00:24:47.951724 Set Vref, RX VrefLevel [Byte0]: 49
1081 00:24:47.955321 [Byte1]: 49
1082 00:24:47.959693
1083 00:24:47.959767 Set Vref, RX VrefLevel [Byte0]: 50
1084 00:24:47.962982 [Byte1]: 50
1085 00:24:47.967242
1086 00:24:47.967313 Set Vref, RX VrefLevel [Byte0]: 51
1087 00:24:47.970457 [Byte1]: 51
1088 00:24:47.974760
1089 00:24:47.974837 Set Vref, RX VrefLevel [Byte0]: 52
1090 00:24:47.978581 [Byte1]: 52
1091 00:24:47.982367
1092 00:24:47.982441 Set Vref, RX VrefLevel [Byte0]: 53
1093 00:24:47.985719 [Byte1]: 53
1094 00:24:47.990279
1095 00:24:47.990352 Set Vref, RX VrefLevel [Byte0]: 54
1096 00:24:47.993566 [Byte1]: 54
1097 00:24:47.998709
1098 00:24:47.998788 Set Vref, RX VrefLevel [Byte0]: 55
1099 00:24:48.001036 [Byte1]: 55
1100 00:24:48.005656
1101 00:24:48.005730 Set Vref, RX VrefLevel [Byte0]: 56
1102 00:24:48.009098 [Byte1]: 56
1103 00:24:48.013000
1104 00:24:48.013090 Set Vref, RX VrefLevel [Byte0]: 57
1105 00:24:48.016425 [Byte1]: 57
1106 00:24:48.021578
1107 00:24:48.021657 Set Vref, RX VrefLevel [Byte0]: 58
1108 00:24:48.024244 [Byte1]: 58
1109 00:24:48.028291
1110 00:24:48.028381 Set Vref, RX VrefLevel [Byte0]: 59
1111 00:24:48.031866 [Byte1]: 59
1112 00:24:48.036052
1113 00:24:48.036127 Set Vref, RX VrefLevel [Byte0]: 60
1114 00:24:48.039365 [Byte1]: 60
1115 00:24:48.043659
1116 00:24:48.043733 Set Vref, RX VrefLevel [Byte0]: 61
1117 00:24:48.046575 [Byte1]: 61
1118 00:24:48.051179
1119 00:24:48.051253 Set Vref, RX VrefLevel [Byte0]: 62
1120 00:24:48.054690 [Byte1]: 62
1121 00:24:48.058604
1122 00:24:48.058679 Set Vref, RX VrefLevel [Byte0]: 63
1123 00:24:48.062067 [Byte1]: 63
1124 00:24:48.066354
1125 00:24:48.066441 Set Vref, RX VrefLevel [Byte0]: 64
1126 00:24:48.069969 [Byte1]: 64
1127 00:24:48.073965
1128 00:24:48.074047 Set Vref, RX VrefLevel [Byte0]: 65
1129 00:24:48.077260 [Byte1]: 65
1130 00:24:48.081538
1131 00:24:48.081620 Set Vref, RX VrefLevel [Byte0]: 66
1132 00:24:48.084935 [Byte1]: 66
1133 00:24:48.089499
1134 00:24:48.089575 Set Vref, RX VrefLevel [Byte0]: 67
1135 00:24:48.092581 [Byte1]: 67
1136 00:24:48.097432
1137 00:24:48.097516 Set Vref, RX VrefLevel [Byte0]: 68
1138 00:24:48.100858 [Byte1]: 68
1139 00:24:48.105057
1140 00:24:48.105135 Set Vref, RX VrefLevel [Byte0]: 69
1141 00:24:48.107840 [Byte1]: 69
1142 00:24:48.112309
1143 00:24:48.112388 Set Vref, RX VrefLevel [Byte0]: 70
1144 00:24:48.115858 [Byte1]: 70
1145 00:24:48.119803
1146 00:24:48.119909 Set Vref, RX VrefLevel [Byte0]: 71
1147 00:24:48.123139 [Byte1]: 71
1148 00:24:48.127537
1149 00:24:48.127616 Set Vref, RX VrefLevel [Byte0]: 72
1150 00:24:48.130911 [Byte1]: 72
1151 00:24:48.135676
1152 00:24:48.135757 Final RX Vref Byte 0 = 55 to rank0
1153 00:24:48.138313 Final RX Vref Byte 1 = 60 to rank0
1154 00:24:48.142208 Final RX Vref Byte 0 = 55 to rank1
1155 00:24:48.145299 Final RX Vref Byte 1 = 60 to rank1==
1156 00:24:48.148552 Dram Type= 6, Freq= 0, CH_0, rank 0
1157 00:24:48.155229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1158 00:24:48.155303 ==
1159 00:24:48.155371 DQS Delay:
1160 00:24:48.155431 DQS0 = 0, DQS1 = 0
1161 00:24:48.158404 DQM Delay:
1162 00:24:48.158473 DQM0 = 88, DQM1 = 76
1163 00:24:48.161930 DQ Delay:
1164 00:24:48.165004 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =88
1165 00:24:48.168582 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1166 00:24:48.171496 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1167 00:24:48.176288 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1168 00:24:48.176390
1169 00:24:48.176475
1170 00:24:48.181826 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f29, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1171 00:24:48.185383 CH0 RK0: MR19=606, MR18=2F29
1172 00:24:48.191533 CH0_RK0: MR19=0x606, MR18=0x2F29, DQSOSC=397, MR23=63, INC=93, DEC=62
1173 00:24:48.191640
1174 00:24:48.195099 ----->DramcWriteLeveling(PI) begin...
1175 00:24:48.195178 ==
1176 00:24:48.198977 Dram Type= 6, Freq= 0, CH_0, rank 1
1177 00:24:48.201791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1178 00:24:48.201864 ==
1179 00:24:48.205356 Write leveling (Byte 0): 31 => 31
1180 00:24:48.208157 Write leveling (Byte 1): 25 => 25
1181 00:24:48.211842 DramcWriteLeveling(PI) end<-----
1182 00:24:48.211940
1183 00:24:48.212003 ==
1184 00:24:48.214995 Dram Type= 6, Freq= 0, CH_0, rank 1
1185 00:24:48.218204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1186 00:24:48.218277 ==
1187 00:24:48.221732 [Gating] SW mode calibration
1188 00:24:48.228655 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1189 00:24:48.235023 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1190 00:24:48.238066 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1191 00:24:48.241409 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1192 00:24:48.247909 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 00:24:48.251112 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 00:24:48.254704 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 00:24:48.302105 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 00:24:48.302202 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 00:24:48.302853 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 00:24:48.303103 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 00:24:48.303866 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 00:24:48.304164 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 00:24:48.304231 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 00:24:48.304302 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 00:24:48.304410 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 00:24:48.305001 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 00:24:48.346269 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 00:24:48.346364 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 00:24:48.346846 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1208 00:24:48.347351 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1209 00:24:48.347738 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 00:24:48.348435 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 00:24:48.348503 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 00:24:48.348936 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 00:24:48.349294 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 00:24:48.349722 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 00:24:48.390247 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
1216 00:24:48.390333 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
1217 00:24:48.390837 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1218 00:24:48.391548 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 00:24:48.391842 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 00:24:48.392348 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 00:24:48.392451 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 00:24:48.392727 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1223 00:24:48.392797 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
1224 00:24:48.392857 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
1225 00:24:48.409086 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 00:24:48.409168 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 00:24:48.409924 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 00:24:48.410214 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 00:24:48.412332 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 00:24:48.415429 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 00:24:48.418822 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
1232 00:24:48.422133 0 11 8 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
1233 00:24:48.428712 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1234 00:24:48.432198 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 00:24:48.435349 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 00:24:48.442827 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 00:24:48.446382 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 00:24:48.449735 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 00:24:48.453595 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 00:24:48.457247 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1241 00:24:48.464097 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 00:24:48.467113 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 00:24:48.471139 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 00:24:48.474303 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 00:24:48.481163 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 00:24:48.484264 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 00:24:48.487761 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 00:24:48.494367 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 00:24:48.497952 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 00:24:48.501132 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 00:24:48.507720 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 00:24:48.510849 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 00:24:48.514219 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 00:24:48.520779 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 00:24:48.524353 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1256 00:24:48.527140 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 00:24:48.530729 Total UI for P1: 0, mck2ui 16
1258 00:24:48.534331 best dqsien dly found for B0: ( 0, 14, 4)
1259 00:24:48.537552 Total UI for P1: 0, mck2ui 16
1260 00:24:48.540366 best dqsien dly found for B1: ( 0, 14, 6)
1261 00:24:48.543739 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1262 00:24:48.546933 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1263 00:24:48.547002
1264 00:24:48.553941 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1265 00:24:48.557008 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1266 00:24:48.557089 [Gating] SW calibration Done
1267 00:24:48.560587 ==
1268 00:24:48.563628 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 00:24:48.567183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 00:24:48.567256 ==
1271 00:24:48.567318 RX Vref Scan: 0
1272 00:24:48.567380
1273 00:24:48.570383 RX Vref 0 -> 0, step: 1
1274 00:24:48.570465
1275 00:24:48.573558 RX Delay -130 -> 252, step: 16
1276 00:24:48.577080 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1277 00:24:48.580656 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1278 00:24:48.587129 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1279 00:24:48.590874 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1280 00:24:48.593503 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1281 00:24:48.597089 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1282 00:24:48.600916 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1283 00:24:48.607304 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1284 00:24:48.610657 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1285 00:24:48.613428 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1286 00:24:48.616620 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1287 00:24:48.620390 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1288 00:24:48.626873 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1289 00:24:48.630122 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1290 00:24:48.633428 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1291 00:24:48.636781 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1292 00:24:48.636863 ==
1293 00:24:48.640424 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 00:24:48.646596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 00:24:48.646676 ==
1296 00:24:48.646769 DQS Delay:
1297 00:24:48.650017 DQS0 = 0, DQS1 = 0
1298 00:24:48.650100 DQM Delay:
1299 00:24:48.650164 DQM0 = 86, DQM1 = 77
1300 00:24:48.653516 DQ Delay:
1301 00:24:48.656648 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1302 00:24:48.659732 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1303 00:24:48.663049 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1304 00:24:48.666381 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1305 00:24:48.666460
1306 00:24:48.666524
1307 00:24:48.666581 ==
1308 00:24:48.669918 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 00:24:48.673617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 00:24:48.673718 ==
1311 00:24:48.673782
1312 00:24:48.673841
1313 00:24:48.676828 TX Vref Scan disable
1314 00:24:48.676908 == TX Byte 0 ==
1315 00:24:48.683373 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1316 00:24:48.686394 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1317 00:24:48.686473 == TX Byte 1 ==
1318 00:24:48.693013 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1319 00:24:48.696416 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1320 00:24:48.696495 ==
1321 00:24:48.700239 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 00:24:48.703471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 00:24:48.703576 ==
1324 00:24:48.717770 TX Vref=22, minBit 2, minWin=26, winSum=441
1325 00:24:48.721176 TX Vref=24, minBit 1, minWin=27, winSum=444
1326 00:24:48.724567 TX Vref=26, minBit 1, minWin=27, winSum=447
1327 00:24:48.727930 TX Vref=28, minBit 2, minWin=27, winSum=450
1328 00:24:48.731765 TX Vref=30, minBit 1, minWin=27, winSum=450
1329 00:24:48.737407 TX Vref=32, minBit 9, minWin=27, winSum=451
1330 00:24:48.740688 [TxChooseVref] Worse bit 9, Min win 27, Win sum 451, Final Vref 32
1331 00:24:48.740768
1332 00:24:48.744159 Final TX Range 1 Vref 32
1333 00:24:48.744239
1334 00:24:48.744302 ==
1335 00:24:48.747820 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 00:24:48.751175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 00:24:48.751254 ==
1338 00:24:48.753907
1339 00:24:48.753986
1340 00:24:48.754048 TX Vref Scan disable
1341 00:24:48.757661 == TX Byte 0 ==
1342 00:24:48.761323 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1343 00:24:48.768075 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1344 00:24:48.768201 == TX Byte 1 ==
1345 00:24:48.770905 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1346 00:24:48.777432 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1347 00:24:48.777516
1348 00:24:48.777578 [DATLAT]
1349 00:24:48.777636 Freq=800, CH0 RK1
1350 00:24:48.777692
1351 00:24:48.780693 DATLAT Default: 0xa
1352 00:24:48.780773 0, 0xFFFF, sum = 0
1353 00:24:48.784472 1, 0xFFFF, sum = 0
1354 00:24:48.788187 2, 0xFFFF, sum = 0
1355 00:24:48.788271 3, 0xFFFF, sum = 0
1356 00:24:48.790937 4, 0xFFFF, sum = 0
1357 00:24:48.791033 5, 0xFFFF, sum = 0
1358 00:24:48.794826 6, 0xFFFF, sum = 0
1359 00:24:48.794906 7, 0xFFFF, sum = 0
1360 00:24:48.797636 8, 0xFFFF, sum = 0
1361 00:24:48.797717 9, 0x0, sum = 1
1362 00:24:48.801244 10, 0x0, sum = 2
1363 00:24:48.801324 11, 0x0, sum = 3
1364 00:24:48.801427 12, 0x0, sum = 4
1365 00:24:48.804041 best_step = 10
1366 00:24:48.804144
1367 00:24:48.804208 ==
1368 00:24:48.807620 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 00:24:48.811283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 00:24:48.811363 ==
1371 00:24:48.814154 RX Vref Scan: 0
1372 00:24:48.814232
1373 00:24:48.817350 RX Vref 0 -> 0, step: 1
1374 00:24:48.817429
1375 00:24:48.817497 RX Delay -95 -> 252, step: 8
1376 00:24:48.824622 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1377 00:24:48.827786 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1378 00:24:48.830885 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1379 00:24:48.834281 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1380 00:24:48.837752 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1381 00:24:48.844300 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1382 00:24:48.847668 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1383 00:24:48.851131 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1384 00:24:48.854493 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1385 00:24:48.857477 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1386 00:24:48.863952 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1387 00:24:48.867399 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1388 00:24:48.870982 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1389 00:24:48.874076 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1390 00:24:48.881088 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1391 00:24:48.883826 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1392 00:24:48.883962 ==
1393 00:24:48.887444 Dram Type= 6, Freq= 0, CH_0, rank 1
1394 00:24:48.890861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 00:24:48.890970 ==
1396 00:24:48.894254 DQS Delay:
1397 00:24:48.894357 DQS0 = 0, DQS1 = 0
1398 00:24:48.894453 DQM Delay:
1399 00:24:48.897396 DQM0 = 86, DQM1 = 77
1400 00:24:48.897474 DQ Delay:
1401 00:24:48.900662 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1402 00:24:48.904733 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1403 00:24:48.907254 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1404 00:24:48.910387 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1405 00:24:48.910465
1406 00:24:48.910528
1407 00:24:48.920257 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1408 00:24:48.920338 CH0 RK1: MR19=606, MR18=2A26
1409 00:24:48.927596 CH0_RK1: MR19=0x606, MR18=0x2A26, DQSOSC=399, MR23=63, INC=92, DEC=61
1410 00:24:48.930617 [RxdqsGatingPostProcess] freq 800
1411 00:24:48.937010 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1412 00:24:48.940006 Pre-setting of DQS Precalculation
1413 00:24:48.943648 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1414 00:24:48.943768 ==
1415 00:24:48.947388 Dram Type= 6, Freq= 0, CH_1, rank 0
1416 00:24:48.953606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1417 00:24:48.953726 ==
1418 00:24:48.957282 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1419 00:24:48.963417 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1420 00:24:48.972526 [CA 0] Center 36 (6~67) winsize 62
1421 00:24:48.975877 [CA 1] Center 37 (6~68) winsize 63
1422 00:24:48.979225 [CA 2] Center 35 (5~65) winsize 61
1423 00:24:48.982697 [CA 3] Center 34 (4~65) winsize 62
1424 00:24:48.985912 [CA 4] Center 34 (4~65) winsize 62
1425 00:24:48.989141 [CA 5] Center 33 (3~64) winsize 62
1426 00:24:48.989257
1427 00:24:48.992520 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1428 00:24:48.992654
1429 00:24:48.996303 [CATrainingPosCal] consider 1 rank data
1430 00:24:48.999490 u2DelayCellTimex100 = 270/100 ps
1431 00:24:49.002562 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1432 00:24:49.009134 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1433 00:24:49.012455 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1434 00:24:49.015631 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1435 00:24:49.018918 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1436 00:24:49.022833 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1437 00:24:49.022940
1438 00:24:49.025931 CA PerBit enable=1, Macro0, CA PI delay=33
1439 00:24:49.026061
1440 00:24:49.029180 [CBTSetCACLKResult] CA Dly = 33
1441 00:24:49.029290 CS Dly: 4 (0~35)
1442 00:24:49.032952 ==
1443 00:24:49.035846 Dram Type= 6, Freq= 0, CH_1, rank 1
1444 00:24:49.039098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 00:24:49.039205 ==
1446 00:24:49.042206 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1447 00:24:49.049193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1448 00:24:49.059287 [CA 0] Center 36 (6~67) winsize 62
1449 00:24:49.062536 [CA 1] Center 36 (6~67) winsize 62
1450 00:24:49.065640 [CA 2] Center 34 (4~65) winsize 62
1451 00:24:49.068837 [CA 3] Center 34 (3~65) winsize 63
1452 00:24:49.072283 [CA 4] Center 34 (3~65) winsize 63
1453 00:24:49.075437 [CA 5] Center 34 (3~65) winsize 63
1454 00:24:49.075515
1455 00:24:49.079300 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1456 00:24:49.079390
1457 00:24:49.082455 [CATrainingPosCal] consider 2 rank data
1458 00:24:49.085365 u2DelayCellTimex100 = 270/100 ps
1459 00:24:49.089152 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1460 00:24:49.092251 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1461 00:24:49.098550 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1462 00:24:49.102318 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1463 00:24:49.106172 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1464 00:24:49.109909 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1465 00:24:49.109990
1466 00:24:49.113382 CA PerBit enable=1, Macro0, CA PI delay=33
1467 00:24:49.113460
1468 00:24:49.116959 [CBTSetCACLKResult] CA Dly = 33
1469 00:24:49.117094 CS Dly: 5 (0~37)
1470 00:24:49.117218
1471 00:24:49.120851 ----->DramcWriteLeveling(PI) begin...
1472 00:24:49.120984 ==
1473 00:24:49.124769 Dram Type= 6, Freq= 0, CH_1, rank 0
1474 00:24:49.128159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 00:24:49.128267 ==
1476 00:24:49.132596 Write leveling (Byte 0): 26 => 26
1477 00:24:49.135207 Write leveling (Byte 1): 26 => 26
1478 00:24:49.139361 DramcWriteLeveling(PI) end<-----
1479 00:24:49.139487
1480 00:24:49.139604 ==
1481 00:24:49.142419 Dram Type= 6, Freq= 0, CH_1, rank 0
1482 00:24:49.146488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1483 00:24:49.146596 ==
1484 00:24:49.149317 [Gating] SW mode calibration
1485 00:24:49.155862 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1486 00:24:49.159627 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1487 00:24:49.166406 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1488 00:24:49.169551 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1489 00:24:49.172530 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 00:24:49.179488 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 00:24:49.183009 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 00:24:49.186353 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 00:24:49.192693 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 00:24:49.195812 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 00:24:49.199063 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 00:24:49.205526 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 00:24:49.209046 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 00:24:49.212034 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 00:24:49.219409 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 00:24:49.222496 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 00:24:49.225611 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 00:24:49.232011 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 00:24:49.235727 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 00:24:49.239269 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1505 00:24:49.245388 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 00:24:49.249096 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 00:24:49.252189 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 00:24:49.258630 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 00:24:49.261778 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 00:24:49.265565 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 00:24:49.268509 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 00:24:49.275657 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
1513 00:24:49.278963 0 9 8 | B1->B0 | 2e2e 3434 | 1 0 | (1 1) (0 0)
1514 00:24:49.282152 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1515 00:24:49.288867 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 00:24:49.291979 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 00:24:49.295596 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 00:24:49.302077 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 00:24:49.305234 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 00:24:49.308505 0 10 4 | B1->B0 | 3232 2f2f | 1 1 | (1 0) (1 0)
1521 00:24:49.315455 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 00:24:49.318968 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 00:24:49.321788 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 00:24:49.328765 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 00:24:49.331786 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 00:24:49.335065 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 00:24:49.341829 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 00:24:49.345450 0 11 4 | B1->B0 | 2626 3131 | 0 0 | (0 0) (0 0)
1529 00:24:49.348115 0 11 8 | B1->B0 | 3a3a 4444 | 0 0 | (0 0) (0 0)
1530 00:24:49.354893 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 00:24:49.358252 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 00:24:49.362257 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 00:24:49.368085 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 00:24:49.371238 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 00:24:49.374622 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 00:24:49.381455 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1537 00:24:49.384942 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 00:24:49.387872 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1539 00:24:49.394528 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 00:24:49.398053 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 00:24:49.401261 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 00:24:49.407852 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 00:24:49.411112 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 00:24:49.414881 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 00:24:49.421090 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 00:24:49.424554 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 00:24:49.427710 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 00:24:49.434353 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 00:24:49.437976 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 00:24:49.441376 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 00:24:49.444620 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1552 00:24:49.450884 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1553 00:24:49.454144 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1554 00:24:49.457731 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 00:24:49.461255 Total UI for P1: 0, mck2ui 16
1556 00:24:49.464699 best dqsien dly found for B0: ( 0, 14, 4)
1557 00:24:49.467586 Total UI for P1: 0, mck2ui 16
1558 00:24:49.471341 best dqsien dly found for B1: ( 0, 14, 6)
1559 00:24:49.474438 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1560 00:24:49.480850 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1561 00:24:49.480936
1562 00:24:49.484013 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1563 00:24:49.487301 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1564 00:24:49.490805 [Gating] SW calibration Done
1565 00:24:49.490890 ==
1566 00:24:49.494862 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 00:24:49.497289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 00:24:49.497374 ==
1569 00:24:49.497459 RX Vref Scan: 0
1570 00:24:49.497540
1571 00:24:49.500826 RX Vref 0 -> 0, step: 1
1572 00:24:49.500910
1573 00:24:49.504056 RX Delay -130 -> 252, step: 16
1574 00:24:49.507157 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1575 00:24:49.510854 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1576 00:24:49.517351 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1577 00:24:49.520811 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1578 00:24:49.523854 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1579 00:24:49.527540 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1580 00:24:49.530604 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1581 00:24:49.537106 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1582 00:24:49.540599 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1583 00:24:49.544142 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1584 00:24:49.547060 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1585 00:24:49.550850 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1586 00:24:49.556936 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1587 00:24:49.560496 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1588 00:24:49.563802 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1589 00:24:49.567052 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1590 00:24:49.567204 ==
1591 00:24:49.570498 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 00:24:49.576801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 00:24:49.576887 ==
1594 00:24:49.576952 DQS Delay:
1595 00:24:49.580579 DQS0 = 0, DQS1 = 0
1596 00:24:49.580654 DQM Delay:
1597 00:24:49.583335 DQM0 = 87, DQM1 = 79
1598 00:24:49.583405 DQ Delay:
1599 00:24:49.587380 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1600 00:24:49.590263 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1601 00:24:49.593549 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1602 00:24:49.596735 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1603 00:24:49.596806
1604 00:24:49.596867
1605 00:24:49.596925 ==
1606 00:24:49.599976 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 00:24:49.603289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 00:24:49.603369 ==
1609 00:24:49.603431
1610 00:24:49.603490
1611 00:24:49.607611 TX Vref Scan disable
1612 00:24:49.610433 == TX Byte 0 ==
1613 00:24:49.613816 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1614 00:24:49.617195 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1615 00:24:49.621054 == TX Byte 1 ==
1616 00:24:49.623501 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1617 00:24:49.626510 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1618 00:24:49.626587 ==
1619 00:24:49.629977 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 00:24:49.633435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 00:24:49.636896 ==
1622 00:24:49.648198 TX Vref=22, minBit 0, minWin=27, winSum=444
1623 00:24:49.651275 TX Vref=24, minBit 2, minWin=27, winSum=448
1624 00:24:49.654680 TX Vref=26, minBit 2, minWin=27, winSum=451
1625 00:24:49.657870 TX Vref=28, minBit 5, minWin=27, winSum=456
1626 00:24:49.661106 TX Vref=30, minBit 4, minWin=27, winSum=453
1627 00:24:49.664670 TX Vref=32, minBit 0, minWin=27, winSum=453
1628 00:24:49.671116 [TxChooseVref] Worse bit 5, Min win 27, Win sum 456, Final Vref 28
1629 00:24:49.671194
1630 00:24:49.675301 Final TX Range 1 Vref 28
1631 00:24:49.675378
1632 00:24:49.675446 ==
1633 00:24:49.677692 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 00:24:49.681292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 00:24:49.681369 ==
1636 00:24:49.681438
1637 00:24:49.684403
1638 00:24:49.684476 TX Vref Scan disable
1639 00:24:49.687957 == TX Byte 0 ==
1640 00:24:49.691449 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1641 00:24:49.695122 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1642 00:24:49.698182 == TX Byte 1 ==
1643 00:24:49.701600 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1644 00:24:49.704761 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1645 00:24:49.704831
1646 00:24:49.708742 [DATLAT]
1647 00:24:49.708816 Freq=800, CH1 RK0
1648 00:24:49.708876
1649 00:24:49.711653 DATLAT Default: 0xa
1650 00:24:49.711718 0, 0xFFFF, sum = 0
1651 00:24:49.714743 1, 0xFFFF, sum = 0
1652 00:24:49.714815 2, 0xFFFF, sum = 0
1653 00:24:49.718443 3, 0xFFFF, sum = 0
1654 00:24:49.718516 4, 0xFFFF, sum = 0
1655 00:24:49.722277 5, 0xFFFF, sum = 0
1656 00:24:49.722345 6, 0xFFFF, sum = 0
1657 00:24:49.725184 7, 0xFFFF, sum = 0
1658 00:24:49.725260 8, 0xFFFF, sum = 0
1659 00:24:49.728548 9, 0x0, sum = 1
1660 00:24:49.728617 10, 0x0, sum = 2
1661 00:24:49.731617 11, 0x0, sum = 3
1662 00:24:49.731689 12, 0x0, sum = 4
1663 00:24:49.734945 best_step = 10
1664 00:24:49.735019
1665 00:24:49.735080 ==
1666 00:24:49.738226 Dram Type= 6, Freq= 0, CH_1, rank 0
1667 00:24:49.741794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1668 00:24:49.741870 ==
1669 00:24:49.744612 RX Vref Scan: 1
1670 00:24:49.744687
1671 00:24:49.744748 Set Vref Range= 32 -> 127
1672 00:24:49.744806
1673 00:24:49.748126 RX Vref 32 -> 127, step: 1
1674 00:24:49.748202
1675 00:24:49.751278 RX Delay -95 -> 252, step: 8
1676 00:24:49.751376
1677 00:24:49.754500 Set Vref, RX VrefLevel [Byte0]: 32
1678 00:24:49.758428 [Byte1]: 32
1679 00:24:49.758527
1680 00:24:49.761519 Set Vref, RX VrefLevel [Byte0]: 33
1681 00:24:49.764794 [Byte1]: 33
1682 00:24:49.767957
1683 00:24:49.768059 Set Vref, RX VrefLevel [Byte0]: 34
1684 00:24:49.771206 [Byte1]: 34
1685 00:24:49.775479
1686 00:24:49.775554 Set Vref, RX VrefLevel [Byte0]: 35
1687 00:24:49.779642 [Byte1]: 35
1688 00:24:49.783337
1689 00:24:49.783412 Set Vref, RX VrefLevel [Byte0]: 36
1690 00:24:49.786347 [Byte1]: 36
1691 00:24:49.790798
1692 00:24:49.790866 Set Vref, RX VrefLevel [Byte0]: 37
1693 00:24:49.793843 [Byte1]: 37
1694 00:24:49.798169
1695 00:24:49.798241 Set Vref, RX VrefLevel [Byte0]: 38
1696 00:24:49.801874 [Byte1]: 38
1697 00:24:49.806052
1698 00:24:49.806122 Set Vref, RX VrefLevel [Byte0]: 39
1699 00:24:49.809336 [Byte1]: 39
1700 00:24:49.813842
1701 00:24:49.813911 Set Vref, RX VrefLevel [Byte0]: 40
1702 00:24:49.816918 [Byte1]: 40
1703 00:24:49.821009
1704 00:24:49.821081 Set Vref, RX VrefLevel [Byte0]: 41
1705 00:24:49.827985 [Byte1]: 41
1706 00:24:49.828065
1707 00:24:49.830802 Set Vref, RX VrefLevel [Byte0]: 42
1708 00:24:49.834103 [Byte1]: 42
1709 00:24:49.834263
1710 00:24:49.837948 Set Vref, RX VrefLevel [Byte0]: 43
1711 00:24:49.841463 [Byte1]: 43
1712 00:24:49.841539
1713 00:24:49.844473 Set Vref, RX VrefLevel [Byte0]: 44
1714 00:24:49.847984 [Byte1]: 44
1715 00:24:49.851744
1716 00:24:49.851844 Set Vref, RX VrefLevel [Byte0]: 45
1717 00:24:49.855044 [Byte1]: 45
1718 00:24:49.858942
1719 00:24:49.859019 Set Vref, RX VrefLevel [Byte0]: 46
1720 00:24:49.862418 [Byte1]: 46
1721 00:24:49.866653
1722 00:24:49.866733 Set Vref, RX VrefLevel [Byte0]: 47
1723 00:24:49.869956 [Byte1]: 47
1724 00:24:49.874453
1725 00:24:49.874526 Set Vref, RX VrefLevel [Byte0]: 48
1726 00:24:49.877571 [Byte1]: 48
1727 00:24:49.882228
1728 00:24:49.882304 Set Vref, RX VrefLevel [Byte0]: 49
1729 00:24:49.885428 [Byte1]: 49
1730 00:24:49.889360
1731 00:24:49.889434 Set Vref, RX VrefLevel [Byte0]: 50
1732 00:24:49.893002 [Byte1]: 50
1733 00:24:49.897000
1734 00:24:49.897082 Set Vref, RX VrefLevel [Byte0]: 51
1735 00:24:49.900596 [Byte1]: 51
1736 00:24:49.904999
1737 00:24:49.905073 Set Vref, RX VrefLevel [Byte0]: 52
1738 00:24:49.907933 [Byte1]: 52
1739 00:24:49.912515
1740 00:24:49.912594 Set Vref, RX VrefLevel [Byte0]: 53
1741 00:24:49.915966 [Byte1]: 53
1742 00:24:49.919893
1743 00:24:49.920007 Set Vref, RX VrefLevel [Byte0]: 54
1744 00:24:49.926151 [Byte1]: 54
1745 00:24:49.926230
1746 00:24:49.929334 Set Vref, RX VrefLevel [Byte0]: 55
1747 00:24:49.932947 [Byte1]: 55
1748 00:24:49.933023
1749 00:24:49.936374 Set Vref, RX VrefLevel [Byte0]: 56
1750 00:24:49.939855 [Byte1]: 56
1751 00:24:49.942863
1752 00:24:49.942941 Set Vref, RX VrefLevel [Byte0]: 57
1753 00:24:49.946178 [Byte1]: 57
1754 00:24:49.950229
1755 00:24:49.950304 Set Vref, RX VrefLevel [Byte0]: 58
1756 00:24:49.953341 [Byte1]: 58
1757 00:24:49.958177
1758 00:24:49.958251 Set Vref, RX VrefLevel [Byte0]: 59
1759 00:24:49.961078 [Byte1]: 59
1760 00:24:49.965414
1761 00:24:49.965492 Set Vref, RX VrefLevel [Byte0]: 60
1762 00:24:49.969100 [Byte1]: 60
1763 00:24:49.973002
1764 00:24:49.973078 Set Vref, RX VrefLevel [Byte0]: 61
1765 00:24:49.976169 [Byte1]: 61
1766 00:24:49.980585
1767 00:24:49.980667 Set Vref, RX VrefLevel [Byte0]: 62
1768 00:24:49.983936 [Byte1]: 62
1769 00:24:49.988406
1770 00:24:49.988480 Set Vref, RX VrefLevel [Byte0]: 63
1771 00:24:49.991995 [Byte1]: 63
1772 00:24:49.995872
1773 00:24:49.996007 Set Vref, RX VrefLevel [Byte0]: 64
1774 00:24:49.998961 [Byte1]: 64
1775 00:24:50.003693
1776 00:24:50.003776 Set Vref, RX VrefLevel [Byte0]: 65
1777 00:24:50.006743 [Byte1]: 65
1778 00:24:50.011498
1779 00:24:50.011576 Set Vref, RX VrefLevel [Byte0]: 66
1780 00:24:50.014081 [Byte1]: 66
1781 00:24:50.018574
1782 00:24:50.018671 Set Vref, RX VrefLevel [Byte0]: 67
1783 00:24:50.025129 [Byte1]: 67
1784 00:24:50.025215
1785 00:24:50.028313 Set Vref, RX VrefLevel [Byte0]: 68
1786 00:24:50.032106 [Byte1]: 68
1787 00:24:50.032184
1788 00:24:50.034919 Set Vref, RX VrefLevel [Byte0]: 69
1789 00:24:50.038744 [Byte1]: 69
1790 00:24:50.038828
1791 00:24:50.041808 Set Vref, RX VrefLevel [Byte0]: 70
1792 00:24:50.045021 [Byte1]: 70
1793 00:24:50.049350
1794 00:24:50.049425 Set Vref, RX VrefLevel [Byte0]: 71
1795 00:24:50.052518 [Byte1]: 71
1796 00:24:50.056798
1797 00:24:50.056873 Set Vref, RX VrefLevel [Byte0]: 72
1798 00:24:50.059817 [Byte1]: 72
1799 00:24:50.064111
1800 00:24:50.064188 Set Vref, RX VrefLevel [Byte0]: 73
1801 00:24:50.067723 [Byte1]: 73
1802 00:24:50.071731
1803 00:24:50.071812 Set Vref, RX VrefLevel [Byte0]: 74
1804 00:24:50.075088 [Byte1]: 74
1805 00:24:50.079599
1806 00:24:50.079677 Set Vref, RX VrefLevel [Byte0]: 75
1807 00:24:50.082804 [Byte1]: 75
1808 00:24:50.087389
1809 00:24:50.087468 Final RX Vref Byte 0 = 56 to rank0
1810 00:24:50.090570 Final RX Vref Byte 1 = 58 to rank0
1811 00:24:50.093849 Final RX Vref Byte 0 = 56 to rank1
1812 00:24:50.097745 Final RX Vref Byte 1 = 58 to rank1==
1813 00:24:50.101338 Dram Type= 6, Freq= 0, CH_1, rank 0
1814 00:24:50.107580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1815 00:24:50.107657 ==
1816 00:24:50.107720 DQS Delay:
1817 00:24:50.107786 DQS0 = 0, DQS1 = 0
1818 00:24:50.110551 DQM Delay:
1819 00:24:50.110626 DQM0 = 85, DQM1 = 80
1820 00:24:50.113613 DQ Delay:
1821 00:24:50.116857 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1822 00:24:50.120219 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1823 00:24:50.120297 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1824 00:24:50.127590 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1825 00:24:50.127679
1826 00:24:50.127742
1827 00:24:50.133603 [DQSOSCAuto] RK0, (LSB)MR18= 0x192c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1828 00:24:50.137842 CH1 RK0: MR19=606, MR18=192C
1829 00:24:50.144235 CH1_RK0: MR19=0x606, MR18=0x192C, DQSOSC=398, MR23=63, INC=93, DEC=62
1830 00:24:50.144312
1831 00:24:50.147353 ----->DramcWriteLeveling(PI) begin...
1832 00:24:50.147433 ==
1833 00:24:50.150289 Dram Type= 6, Freq= 0, CH_1, rank 1
1834 00:24:50.154682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1835 00:24:50.154760 ==
1836 00:24:50.157251 Write leveling (Byte 0): 26 => 26
1837 00:24:50.160572 Write leveling (Byte 1): 26 => 26
1838 00:24:50.163709 DramcWriteLeveling(PI) end<-----
1839 00:24:50.163787
1840 00:24:50.163847 ==
1841 00:24:50.166831 Dram Type= 6, Freq= 0, CH_1, rank 1
1842 00:24:50.170371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1843 00:24:50.170445 ==
1844 00:24:50.173649 [Gating] SW mode calibration
1845 00:24:50.180258 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1846 00:24:50.186691 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1847 00:24:50.190511 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1848 00:24:50.193597 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1849 00:24:50.200444 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1850 00:24:50.203289 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 00:24:50.206608 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 00:24:50.213265 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 00:24:50.216530 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 00:24:50.220065 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 00:24:50.226290 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 00:24:50.229625 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 00:24:50.233199 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 00:24:50.239520 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 00:24:50.243123 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 00:24:50.246276 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 00:24:50.252709 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 00:24:50.256308 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 00:24:50.259381 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1864 00:24:50.266186 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 00:24:50.269273 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 00:24:50.272668 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 00:24:50.279662 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 00:24:50.283145 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 00:24:50.286159 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 00:24:50.292999 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 00:24:50.295873 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 00:24:50.299793 0 9 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
1873 00:24:50.305878 0 9 8 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
1874 00:24:50.309972 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 00:24:50.312648 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1876 00:24:50.319278 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1877 00:24:50.322574 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1878 00:24:50.326416 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1879 00:24:50.332821 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1880 00:24:50.336084 0 10 4 | B1->B0 | 3232 2727 | 0 0 | (0 1) (1 1)
1881 00:24:50.339546 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1882 00:24:50.345939 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 00:24:50.349101 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 00:24:50.352841 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 00:24:50.355628 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 00:24:50.362773 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 00:24:50.365922 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 00:24:50.368953 0 11 4 | B1->B0 | 2828 4040 | 0 1 | (0 0) (0 0)
1889 00:24:50.375467 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
1890 00:24:50.379605 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 00:24:50.382774 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 00:24:50.388908 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 00:24:50.392301 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 00:24:50.395811 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1895 00:24:50.402116 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1896 00:24:50.406001 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1897 00:24:50.409072 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 00:24:50.416377 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 00:24:50.419191 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 00:24:50.422212 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 00:24:50.429027 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 00:24:50.432482 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 00:24:50.435862 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 00:24:50.442360 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 00:24:50.445542 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 00:24:50.448779 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 00:24:50.455463 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 00:24:50.458648 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 00:24:50.461990 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 00:24:50.468459 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 00:24:50.472060 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 00:24:50.475258 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1913 00:24:50.478644 Total UI for P1: 0, mck2ui 16
1914 00:24:50.481844 best dqsien dly found for B0: ( 0, 14, 2)
1915 00:24:50.485442 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1916 00:24:50.491598 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 00:24:50.494932 Total UI for P1: 0, mck2ui 16
1918 00:24:50.498433 best dqsien dly found for B1: ( 0, 14, 6)
1919 00:24:50.501965 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1920 00:24:50.504898 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1921 00:24:50.504981
1922 00:24:50.509050 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1923 00:24:50.512139 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1924 00:24:50.515097 [Gating] SW calibration Done
1925 00:24:50.515174 ==
1926 00:24:50.518245 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 00:24:50.521759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 00:24:50.521836 ==
1929 00:24:50.525579 RX Vref Scan: 0
1930 00:24:50.525655
1931 00:24:50.525718 RX Vref 0 -> 0, step: 1
1932 00:24:50.528530
1933 00:24:50.528601 RX Delay -130 -> 252, step: 16
1934 00:24:50.534952 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1935 00:24:50.538610 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1936 00:24:50.542279 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1937 00:24:50.545116 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
1938 00:24:50.547978 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1939 00:24:50.554938 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1940 00:24:50.558540 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1941 00:24:50.561430 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1942 00:24:50.565035 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1943 00:24:50.568099 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1944 00:24:50.574544 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1945 00:24:50.578385 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1946 00:24:50.581601 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1947 00:24:50.584413 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1948 00:24:50.591661 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1949 00:24:50.594696 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1950 00:24:50.594790 ==
1951 00:24:50.597970 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 00:24:50.601625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 00:24:50.601715 ==
1954 00:24:50.601778 DQS Delay:
1955 00:24:50.604535 DQS0 = 0, DQS1 = 0
1956 00:24:50.604604 DQM Delay:
1957 00:24:50.608452 DQM0 = 79, DQM1 = 78
1958 00:24:50.608525 DQ Delay:
1959 00:24:50.611283 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1960 00:24:50.614146 DQ4 =77, DQ5 =85, DQ6 =85, DQ7 =77
1961 00:24:50.617329 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1962 00:24:50.620806 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1963 00:24:50.620893
1964 00:24:50.620955
1965 00:24:50.621020 ==
1966 00:24:50.624299 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 00:24:50.630627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 00:24:50.630714 ==
1969 00:24:50.630777
1970 00:24:50.630836
1971 00:24:50.630900 TX Vref Scan disable
1972 00:24:50.634441 == TX Byte 0 ==
1973 00:24:50.637362 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1974 00:24:50.644229 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1975 00:24:50.644352 == TX Byte 1 ==
1976 00:24:50.647192 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1977 00:24:50.653909 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1978 00:24:50.653991 ==
1979 00:24:50.657471 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 00:24:50.660877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 00:24:50.660952 ==
1982 00:24:50.673249 TX Vref=22, minBit 0, minWin=27, winSum=445
1983 00:24:50.676439 TX Vref=24, minBit 1, minWin=27, winSum=449
1984 00:24:50.679882 TX Vref=26, minBit 1, minWin=27, winSum=451
1985 00:24:50.683283 TX Vref=28, minBit 5, minWin=27, winSum=453
1986 00:24:50.687148 TX Vref=30, minBit 6, minWin=27, winSum=455
1987 00:24:50.689880 TX Vref=32, minBit 2, minWin=27, winSum=453
1988 00:24:50.696453 [TxChooseVref] Worse bit 6, Min win 27, Win sum 455, Final Vref 30
1989 00:24:50.696536
1990 00:24:50.699724 Final TX Range 1 Vref 30
1991 00:24:50.699822
1992 00:24:50.699938 ==
1993 00:24:50.703204 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 00:24:50.706735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 00:24:50.706812 ==
1996 00:24:50.706875
1997 00:24:50.709346
1998 00:24:50.709421 TX Vref Scan disable
1999 00:24:50.712763 == TX Byte 0 ==
2000 00:24:50.716405 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2001 00:24:50.719736 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2002 00:24:50.723086 == TX Byte 1 ==
2003 00:24:50.726814 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2004 00:24:50.729718 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2005 00:24:50.732792
2006 00:24:50.732872 [DATLAT]
2007 00:24:50.732935 Freq=800, CH1 RK1
2008 00:24:50.732995
2009 00:24:50.736383 DATLAT Default: 0xa
2010 00:24:50.736464 0, 0xFFFF, sum = 0
2011 00:24:50.739641 1, 0xFFFF, sum = 0
2012 00:24:50.739723 2, 0xFFFF, sum = 0
2013 00:24:50.743132 3, 0xFFFF, sum = 0
2014 00:24:50.743223 4, 0xFFFF, sum = 0
2015 00:24:50.746543 5, 0xFFFF, sum = 0
2016 00:24:50.749404 6, 0xFFFF, sum = 0
2017 00:24:50.749488 7, 0xFFFF, sum = 0
2018 00:24:50.752830 8, 0xFFFF, sum = 0
2019 00:24:50.752909 9, 0x0, sum = 1
2020 00:24:50.752973 10, 0x0, sum = 2
2021 00:24:50.756319 11, 0x0, sum = 3
2022 00:24:50.756390 12, 0x0, sum = 4
2023 00:24:50.759252 best_step = 10
2024 00:24:50.759323
2025 00:24:50.759383 ==
2026 00:24:50.762639 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 00:24:50.766162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 00:24:50.766235 ==
2029 00:24:50.769236 RX Vref Scan: 0
2030 00:24:50.769308
2031 00:24:50.769368 RX Vref 0 -> 0, step: 1
2032 00:24:50.772980
2033 00:24:50.773050 RX Delay -95 -> 252, step: 8
2034 00:24:50.779731 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2035 00:24:50.783135 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
2036 00:24:50.786341 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2037 00:24:50.789518 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2038 00:24:50.793052 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2039 00:24:50.799492 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2040 00:24:50.802980 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2041 00:24:50.806498 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2042 00:24:50.809633 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2043 00:24:50.813015 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2044 00:24:50.819615 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2045 00:24:50.822967 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2046 00:24:50.825884 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2047 00:24:50.829427 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2048 00:24:50.837268 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2049 00:24:50.839240 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2050 00:24:50.839324 ==
2051 00:24:50.842459 Dram Type= 6, Freq= 0, CH_1, rank 1
2052 00:24:50.846151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2053 00:24:50.846236 ==
2054 00:24:50.846300 DQS Delay:
2055 00:24:50.849224 DQS0 = 0, DQS1 = 0
2056 00:24:50.849300 DQM Delay:
2057 00:24:50.852876 DQM0 = 86, DQM1 = 81
2058 00:24:50.852950 DQ Delay:
2059 00:24:50.856139 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2060 00:24:50.859511 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2061 00:24:50.862509 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =72
2062 00:24:50.865838 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2063 00:24:50.865911
2064 00:24:50.865973
2065 00:24:50.876007 [DQSOSCAuto] RK1, (LSB)MR18= 0x203b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2066 00:24:50.876136 CH1 RK1: MR19=606, MR18=203B
2067 00:24:50.882805 CH1_RK1: MR19=0x606, MR18=0x203B, DQSOSC=394, MR23=63, INC=95, DEC=63
2068 00:24:50.886404 [RxdqsGatingPostProcess] freq 800
2069 00:24:50.892324 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2070 00:24:50.895704 Pre-setting of DQS Precalculation
2071 00:24:50.898794 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2072 00:24:50.905610 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2073 00:24:50.915577 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2074 00:24:50.915661
2075 00:24:50.915735
2076 00:24:50.919200 [Calibration Summary] 1600 Mbps
2077 00:24:50.919278 CH 0, Rank 0
2078 00:24:50.922152 SW Impedance : PASS
2079 00:24:50.922228 DUTY Scan : NO K
2080 00:24:50.925740 ZQ Calibration : PASS
2081 00:24:50.928663 Jitter Meter : NO K
2082 00:24:50.928744 CBT Training : PASS
2083 00:24:50.932147 Write leveling : PASS
2084 00:24:50.932231 RX DQS gating : PASS
2085 00:24:50.935920 RX DQ/DQS(RDDQC) : PASS
2086 00:24:50.938405 TX DQ/DQS : PASS
2087 00:24:50.938485 RX DATLAT : PASS
2088 00:24:50.942409 RX DQ/DQS(Engine): PASS
2089 00:24:50.945223 TX OE : NO K
2090 00:24:50.945300 All Pass.
2091 00:24:50.945371
2092 00:24:50.945435 CH 0, Rank 1
2093 00:24:50.949237 SW Impedance : PASS
2094 00:24:50.951683 DUTY Scan : NO K
2095 00:24:50.951762 ZQ Calibration : PASS
2096 00:24:50.955073 Jitter Meter : NO K
2097 00:24:50.959187 CBT Training : PASS
2098 00:24:50.959262 Write leveling : PASS
2099 00:24:50.961671 RX DQS gating : PASS
2100 00:24:50.965462 RX DQ/DQS(RDDQC) : PASS
2101 00:24:50.965544 TX DQ/DQS : PASS
2102 00:24:50.968547 RX DATLAT : PASS
2103 00:24:50.971861 RX DQ/DQS(Engine): PASS
2104 00:24:50.971962 TX OE : NO K
2105 00:24:50.972028 All Pass.
2106 00:24:50.974924
2107 00:24:50.975001 CH 1, Rank 0
2108 00:24:50.978440 SW Impedance : PASS
2109 00:24:50.978517 DUTY Scan : NO K
2110 00:24:50.982264 ZQ Calibration : PASS
2111 00:24:50.985207 Jitter Meter : NO K
2112 00:24:50.985314 CBT Training : PASS
2113 00:24:50.988600 Write leveling : PASS
2114 00:24:50.988672 RX DQS gating : PASS
2115 00:24:50.991926 RX DQ/DQS(RDDQC) : PASS
2116 00:24:50.995036 TX DQ/DQS : PASS
2117 00:24:50.995114 RX DATLAT : PASS
2118 00:24:50.998671 RX DQ/DQS(Engine): PASS
2119 00:24:51.002064 TX OE : NO K
2120 00:24:51.002141 All Pass.
2121 00:24:51.002210
2122 00:24:51.002270 CH 1, Rank 1
2123 00:24:51.004665 SW Impedance : PASS
2124 00:24:51.008944 DUTY Scan : NO K
2125 00:24:51.009016 ZQ Calibration : PASS
2126 00:24:51.012154 Jitter Meter : NO K
2127 00:24:51.014574 CBT Training : PASS
2128 00:24:51.014645 Write leveling : PASS
2129 00:24:51.018110 RX DQS gating : PASS
2130 00:24:51.021227 RX DQ/DQS(RDDQC) : PASS
2131 00:24:51.021301 TX DQ/DQS : PASS
2132 00:24:51.024528 RX DATLAT : PASS
2133 00:24:51.028154 RX DQ/DQS(Engine): PASS
2134 00:24:51.028234 TX OE : NO K
2135 00:24:51.031378 All Pass.
2136 00:24:51.031457
2137 00:24:51.031521 DramC Write-DBI off
2138 00:24:51.034514 PER_BANK_REFRESH: Hybrid Mode
2139 00:24:51.034595 TX_TRACKING: ON
2140 00:24:51.037907 [GetDramInforAfterCalByMRR] Vendor 6.
2141 00:24:51.045007 [GetDramInforAfterCalByMRR] Revision 606.
2142 00:24:51.048303 [GetDramInforAfterCalByMRR] Revision 2 0.
2143 00:24:51.048431 MR0 0x3b3b
2144 00:24:51.048495 MR8 0x5151
2145 00:24:51.051814 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2146 00:24:51.051896
2147 00:24:51.054996 MR0 0x3b3b
2148 00:24:51.055075 MR8 0x5151
2149 00:24:51.058197 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2150 00:24:51.058293
2151 00:24:51.068053 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2152 00:24:51.071557 [FAST_K] Save calibration result to emmc
2153 00:24:51.074890 [FAST_K] Save calibration result to emmc
2154 00:24:51.078238 dram_init: config_dvfs: 1
2155 00:24:51.081655 dramc_set_vcore_voltage set vcore to 662500
2156 00:24:51.084709 Read voltage for 1200, 2
2157 00:24:51.084790 Vio18 = 0
2158 00:24:51.084860 Vcore = 662500
2159 00:24:51.088048 Vdram = 0
2160 00:24:51.088116 Vddq = 0
2161 00:24:51.088224 Vmddr = 0
2162 00:24:51.095064 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2163 00:24:51.097740 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2164 00:24:51.101537 MEM_TYPE=3, freq_sel=15
2165 00:24:51.105019 sv_algorithm_assistance_LP4_1600
2166 00:24:51.108633 ============ PULL DRAM RESETB DOWN ============
2167 00:24:51.111322 ========== PULL DRAM RESETB DOWN end =========
2168 00:24:51.118051 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2169 00:24:51.121023 ===================================
2170 00:24:51.121100 LPDDR4 DRAM CONFIGURATION
2171 00:24:51.124592 ===================================
2172 00:24:51.128012 EX_ROW_EN[0] = 0x0
2173 00:24:51.130920 EX_ROW_EN[1] = 0x0
2174 00:24:51.130991 LP4Y_EN = 0x0
2175 00:24:51.134328 WORK_FSP = 0x0
2176 00:24:51.134399 WL = 0x4
2177 00:24:51.137849 RL = 0x4
2178 00:24:51.137919 BL = 0x2
2179 00:24:51.141472 RPST = 0x0
2180 00:24:51.141583 RD_PRE = 0x0
2181 00:24:51.145646 WR_PRE = 0x1
2182 00:24:51.145732 WR_PST = 0x0
2183 00:24:51.148070 DBI_WR = 0x0
2184 00:24:51.148145 DBI_RD = 0x0
2185 00:24:51.151240 OTF = 0x1
2186 00:24:51.154578 ===================================
2187 00:24:51.157928 ===================================
2188 00:24:51.158006 ANA top config
2189 00:24:51.162066 ===================================
2190 00:24:51.164554 DLL_ASYNC_EN = 0
2191 00:24:51.167805 ALL_SLAVE_EN = 0
2192 00:24:51.167875 NEW_RANK_MODE = 1
2193 00:24:51.171026 DLL_IDLE_MODE = 1
2194 00:24:51.174510 LP45_APHY_COMB_EN = 1
2195 00:24:51.177896 TX_ODT_DIS = 1
2196 00:24:51.181429 NEW_8X_MODE = 1
2197 00:24:51.184724 ===================================
2198 00:24:51.187738 ===================================
2199 00:24:51.187808 data_rate = 2400
2200 00:24:51.191663 CKR = 1
2201 00:24:51.194503 DQ_P2S_RATIO = 8
2202 00:24:51.197988 ===================================
2203 00:24:51.201312 CA_P2S_RATIO = 8
2204 00:24:51.204185 DQ_CA_OPEN = 0
2205 00:24:51.208126 DQ_SEMI_OPEN = 0
2206 00:24:51.208198 CA_SEMI_OPEN = 0
2207 00:24:51.211306 CA_FULL_RATE = 0
2208 00:24:51.214229 DQ_CKDIV4_EN = 0
2209 00:24:51.217816 CA_CKDIV4_EN = 0
2210 00:24:51.220933 CA_PREDIV_EN = 0
2211 00:24:51.224216 PH8_DLY = 17
2212 00:24:51.224291 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2213 00:24:51.227388 DQ_AAMCK_DIV = 4
2214 00:24:51.230971 CA_AAMCK_DIV = 4
2215 00:24:51.234447 CA_ADMCK_DIV = 4
2216 00:24:51.237958 DQ_TRACK_CA_EN = 0
2217 00:24:51.241153 CA_PICK = 1200
2218 00:24:51.244070 CA_MCKIO = 1200
2219 00:24:51.244141 MCKIO_SEMI = 0
2220 00:24:51.247686 PLL_FREQ = 2366
2221 00:24:51.251303 DQ_UI_PI_RATIO = 32
2222 00:24:51.254198 CA_UI_PI_RATIO = 0
2223 00:24:51.257527 ===================================
2224 00:24:51.260724 ===================================
2225 00:24:51.264271 memory_type:LPDDR4
2226 00:24:51.264350 GP_NUM : 10
2227 00:24:51.267208 SRAM_EN : 1
2228 00:24:51.271607 MD32_EN : 0
2229 00:24:51.274079 ===================================
2230 00:24:51.274154 [ANA_INIT] >>>>>>>>>>>>>>
2231 00:24:51.277890 <<<<<< [CONFIGURE PHASE]: ANA_TX
2232 00:24:51.280656 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2233 00:24:51.283681 ===================================
2234 00:24:51.287331 data_rate = 2400,PCW = 0X5b00
2235 00:24:51.290485 ===================================
2236 00:24:51.293925 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2237 00:24:51.300786 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2238 00:24:51.303820 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2239 00:24:51.310332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2240 00:24:51.313706 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2241 00:24:51.316979 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2242 00:24:51.317098 [ANA_INIT] flow start
2243 00:24:51.320079 [ANA_INIT] PLL >>>>>>>>
2244 00:24:51.323451 [ANA_INIT] PLL <<<<<<<<
2245 00:24:51.326678 [ANA_INIT] MIDPI >>>>>>>>
2246 00:24:51.326758 [ANA_INIT] MIDPI <<<<<<<<
2247 00:24:51.330115 [ANA_INIT] DLL >>>>>>>>
2248 00:24:51.334071 [ANA_INIT] DLL <<<<<<<<
2249 00:24:51.334151 [ANA_INIT] flow end
2250 00:24:51.337259 ============ LP4 DIFF to SE enter ============
2251 00:24:51.343398 ============ LP4 DIFF to SE exit ============
2252 00:24:51.343490 [ANA_INIT] <<<<<<<<<<<<<
2253 00:24:51.346997 [Flow] Enable top DCM control >>>>>
2254 00:24:51.350312 [Flow] Enable top DCM control <<<<<
2255 00:24:51.353710 Enable DLL master slave shuffle
2256 00:24:51.360094 ==============================================================
2257 00:24:51.360175 Gating Mode config
2258 00:24:51.366546 ==============================================================
2259 00:24:51.370448 Config description:
2260 00:24:51.379704 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2261 00:24:51.387237 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2262 00:24:51.389958 SELPH_MODE 0: By rank 1: By Phase
2263 00:24:51.396344 ==============================================================
2264 00:24:51.399817 GAT_TRACK_EN = 1
2265 00:24:51.403077 RX_GATING_MODE = 2
2266 00:24:51.403153 RX_GATING_TRACK_MODE = 2
2267 00:24:51.406415 SELPH_MODE = 1
2268 00:24:51.409697 PICG_EARLY_EN = 1
2269 00:24:51.412948 VALID_LAT_VALUE = 1
2270 00:24:51.419558 ==============================================================
2271 00:24:51.422990 Enter into Gating configuration >>>>
2272 00:24:51.426415 Exit from Gating configuration <<<<
2273 00:24:51.430067 Enter into DVFS_PRE_config >>>>>
2274 00:24:51.439522 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2275 00:24:51.442848 Exit from DVFS_PRE_config <<<<<
2276 00:24:51.446321 Enter into PICG configuration >>>>
2277 00:24:51.449753 Exit from PICG configuration <<<<
2278 00:24:51.452819 [RX_INPUT] configuration >>>>>
2279 00:24:51.456025 [RX_INPUT] configuration <<<<<
2280 00:24:51.459533 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2281 00:24:51.466028 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2282 00:24:51.472921 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2283 00:24:51.479124 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2284 00:24:51.482598 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2285 00:24:51.489338 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2286 00:24:51.492654 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2287 00:24:51.498956 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2288 00:24:51.503029 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2289 00:24:51.505861 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2290 00:24:51.509333 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2291 00:24:51.515798 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2292 00:24:51.519173 ===================================
2293 00:24:51.522927 LPDDR4 DRAM CONFIGURATION
2294 00:24:51.525537 ===================================
2295 00:24:51.525619 EX_ROW_EN[0] = 0x0
2296 00:24:51.529386 EX_ROW_EN[1] = 0x0
2297 00:24:51.529467 LP4Y_EN = 0x0
2298 00:24:51.533031 WORK_FSP = 0x0
2299 00:24:51.533111 WL = 0x4
2300 00:24:51.535850 RL = 0x4
2301 00:24:51.535945 BL = 0x2
2302 00:24:51.538896 RPST = 0x0
2303 00:24:51.538976 RD_PRE = 0x0
2304 00:24:51.542931 WR_PRE = 0x1
2305 00:24:51.543011 WR_PST = 0x0
2306 00:24:51.545756 DBI_WR = 0x0
2307 00:24:51.545836 DBI_RD = 0x0
2308 00:24:51.549088 OTF = 0x1
2309 00:24:51.552366 ===================================
2310 00:24:51.555759 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2311 00:24:51.559592 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2312 00:24:51.565800 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2313 00:24:51.568903 ===================================
2314 00:24:51.568984 LPDDR4 DRAM CONFIGURATION
2315 00:24:51.572441 ===================================
2316 00:24:51.575536 EX_ROW_EN[0] = 0x10
2317 00:24:51.579277 EX_ROW_EN[1] = 0x0
2318 00:24:51.579357 LP4Y_EN = 0x0
2319 00:24:51.582969 WORK_FSP = 0x0
2320 00:24:51.583064 WL = 0x4
2321 00:24:51.585497 RL = 0x4
2322 00:24:51.585577 BL = 0x2
2323 00:24:51.588889 RPST = 0x0
2324 00:24:51.588969 RD_PRE = 0x0
2325 00:24:51.592148 WR_PRE = 0x1
2326 00:24:51.592229 WR_PST = 0x0
2327 00:24:51.595367 DBI_WR = 0x0
2328 00:24:51.595477 DBI_RD = 0x0
2329 00:24:51.598879 OTF = 0x1
2330 00:24:51.602195 ===================================
2331 00:24:51.609141 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2332 00:24:51.609223 ==
2333 00:24:51.612784 Dram Type= 6, Freq= 0, CH_0, rank 0
2334 00:24:51.615835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2335 00:24:51.615947 ==
2336 00:24:51.618969 [Duty_Offset_Calibration]
2337 00:24:51.619049 B0:2 B1:0 CA:4
2338 00:24:51.619114
2339 00:24:51.622367 [DutyScan_Calibration_Flow] k_type=0
2340 00:24:51.631708
2341 00:24:51.631822 ==CLK 0==
2342 00:24:51.635134 Final CLK duty delay cell = -4
2343 00:24:51.638384 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2344 00:24:51.641479 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2345 00:24:51.644622 [-4] AVG Duty = 4937%(X100)
2346 00:24:51.644704
2347 00:24:51.648057 CH0 CLK Duty spec in!! Max-Min= 187%
2348 00:24:51.651764 [DutyScan_Calibration_Flow] ====Done====
2349 00:24:51.651869
2350 00:24:51.654951 [DutyScan_Calibration_Flow] k_type=1
2351 00:24:51.671070
2352 00:24:51.671150 ==DQS 0 ==
2353 00:24:51.674819 Final DQS duty delay cell = 0
2354 00:24:51.677688 [0] MAX Duty = 5156%(X100), DQS PI = 10
2355 00:24:51.681362 [0] MIN Duty = 5093%(X100), DQS PI = 0
2356 00:24:51.684638 [0] AVG Duty = 5124%(X100)
2357 00:24:51.684718
2358 00:24:51.684781 ==DQS 1 ==
2359 00:24:51.687500 Final DQS duty delay cell = 0
2360 00:24:51.691422 [0] MAX Duty = 5125%(X100), DQS PI = 4
2361 00:24:51.694722 [0] MIN Duty = 4969%(X100), DQS PI = 14
2362 00:24:51.694802 [0] AVG Duty = 5047%(X100)
2363 00:24:51.697742
2364 00:24:51.701188 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2365 00:24:51.701268
2366 00:24:51.704283 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2367 00:24:51.707729 [DutyScan_Calibration_Flow] ====Done====
2368 00:24:51.707833
2369 00:24:51.710666 [DutyScan_Calibration_Flow] k_type=3
2370 00:24:51.727434
2371 00:24:51.727516 ==DQM 0 ==
2372 00:24:51.731059 Final DQM duty delay cell = 0
2373 00:24:51.734145 [0] MAX Duty = 5125%(X100), DQS PI = 20
2374 00:24:51.737333 [0] MIN Duty = 4844%(X100), DQS PI = 54
2375 00:24:51.740562 [0] AVG Duty = 4984%(X100)
2376 00:24:51.740636
2377 00:24:51.740706 ==DQM 1 ==
2378 00:24:51.744083 Final DQM duty delay cell = 0
2379 00:24:51.747147 [0] MAX Duty = 4969%(X100), DQS PI = 2
2380 00:24:51.750615 [0] MIN Duty = 4875%(X100), DQS PI = 20
2381 00:24:51.753873 [0] AVG Duty = 4922%(X100)
2382 00:24:51.753957
2383 00:24:51.757311 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2384 00:24:51.757392
2385 00:24:51.760565 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2386 00:24:51.765063 [DutyScan_Calibration_Flow] ====Done====
2387 00:24:51.765134
2388 00:24:51.767059 [DutyScan_Calibration_Flow] k_type=2
2389 00:24:51.784023
2390 00:24:51.784104 ==DQ 0 ==
2391 00:24:51.786868 Final DQ duty delay cell = 0
2392 00:24:51.790711 [0] MAX Duty = 5156%(X100), DQS PI = 18
2393 00:24:51.793884 [0] MIN Duty = 4969%(X100), DQS PI = 50
2394 00:24:51.793956 [0] AVG Duty = 5062%(X100)
2395 00:24:51.797204
2396 00:24:51.797277 ==DQ 1 ==
2397 00:24:51.800417 Final DQ duty delay cell = 0
2398 00:24:51.804002 [0] MAX Duty = 5125%(X100), DQS PI = 4
2399 00:24:51.806987 [0] MIN Duty = 4938%(X100), DQS PI = 14
2400 00:24:51.807060 [0] AVG Duty = 5031%(X100)
2401 00:24:51.807130
2402 00:24:51.810358 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2403 00:24:51.813901
2404 00:24:51.817048 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2405 00:24:51.820927 [DutyScan_Calibration_Flow] ====Done====
2406 00:24:51.821002 ==
2407 00:24:51.824219 Dram Type= 6, Freq= 0, CH_1, rank 0
2408 00:24:51.827153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2409 00:24:51.827223 ==
2410 00:24:51.830231 [Duty_Offset_Calibration]
2411 00:24:51.830308 B0:0 B1:-1 CA:3
2412 00:24:51.830369
2413 00:24:51.833464 [DutyScan_Calibration_Flow] k_type=0
2414 00:24:51.843159
2415 00:24:51.843242 ==CLK 0==
2416 00:24:51.846099 Final CLK duty delay cell = -4
2417 00:24:51.849427 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2418 00:24:51.852697 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2419 00:24:51.856028 [-4] AVG Duty = 4938%(X100)
2420 00:24:51.856107
2421 00:24:51.859661 CH1 CLK Duty spec in!! Max-Min= 124%
2422 00:24:51.862807 [DutyScan_Calibration_Flow] ====Done====
2423 00:24:51.862880
2424 00:24:51.866208 [DutyScan_Calibration_Flow] k_type=1
2425 00:24:51.882283
2426 00:24:51.882360 ==DQS 0 ==
2427 00:24:51.886103 Final DQS duty delay cell = 0
2428 00:24:51.889149 [0] MAX Duty = 5187%(X100), DQS PI = 18
2429 00:24:51.892199 [0] MIN Duty = 4907%(X100), DQS PI = 38
2430 00:24:51.895610 [0] AVG Duty = 5047%(X100)
2431 00:24:51.895685
2432 00:24:51.895748 ==DQS 1 ==
2433 00:24:51.898892 Final DQS duty delay cell = 0
2434 00:24:51.902703 [0] MAX Duty = 5156%(X100), DQS PI = 8
2435 00:24:51.905603 [0] MIN Duty = 5000%(X100), DQS PI = 24
2436 00:24:51.909445 [0] AVG Duty = 5078%(X100)
2437 00:24:51.909525
2438 00:24:51.912402 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2439 00:24:51.912471
2440 00:24:51.915636 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2441 00:24:51.918939 [DutyScan_Calibration_Flow] ====Done====
2442 00:24:51.919013
2443 00:24:51.922821 [DutyScan_Calibration_Flow] k_type=3
2444 00:24:51.939539
2445 00:24:51.939620 ==DQM 0 ==
2446 00:24:51.942821 Final DQM duty delay cell = 0
2447 00:24:51.945913 [0] MAX Duty = 5031%(X100), DQS PI = 28
2448 00:24:51.949094 [0] MIN Duty = 4813%(X100), DQS PI = 38
2449 00:24:51.952594 [0] AVG Duty = 4922%(X100)
2450 00:24:51.952678
2451 00:24:51.952744 ==DQM 1 ==
2452 00:24:51.955882 Final DQM duty delay cell = 0
2453 00:24:51.958759 [0] MAX Duty = 5000%(X100), DQS PI = 34
2454 00:24:51.962004 [0] MIN Duty = 4844%(X100), DQS PI = 0
2455 00:24:51.965580 [0] AVG Duty = 4922%(X100)
2456 00:24:51.965663
2457 00:24:51.968642 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2458 00:24:51.968725
2459 00:24:51.971917 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2460 00:24:51.975741 [DutyScan_Calibration_Flow] ====Done====
2461 00:24:51.975848
2462 00:24:51.978512 [DutyScan_Calibration_Flow] k_type=2
2463 00:24:51.994706
2464 00:24:51.994816 ==DQ 0 ==
2465 00:24:51.998143 Final DQ duty delay cell = -4
2466 00:24:52.001284 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2467 00:24:52.004538 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2468 00:24:52.007966 [-4] AVG Duty = 4937%(X100)
2469 00:24:52.008068
2470 00:24:52.008169 ==DQ 1 ==
2471 00:24:52.011297 Final DQ duty delay cell = 0
2472 00:24:52.015063 [0] MAX Duty = 5031%(X100), DQS PI = 32
2473 00:24:52.017690 [0] MIN Duty = 4876%(X100), DQS PI = 0
2474 00:24:52.021191 [0] AVG Duty = 4953%(X100)
2475 00:24:52.021289
2476 00:24:52.024418 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2477 00:24:52.024515
2478 00:24:52.027793 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2479 00:24:52.031072 [DutyScan_Calibration_Flow] ====Done====
2480 00:24:52.034483 nWR fixed to 30
2481 00:24:52.038187 [ModeRegInit_LP4] CH0 RK0
2482 00:24:52.038262 [ModeRegInit_LP4] CH0 RK1
2483 00:24:52.040711 [ModeRegInit_LP4] CH1 RK0
2484 00:24:52.044594 [ModeRegInit_LP4] CH1 RK1
2485 00:24:52.044678 match AC timing 7
2486 00:24:52.050644 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2487 00:24:52.054972 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2488 00:24:52.057305 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2489 00:24:52.064061 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2490 00:24:52.067639 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2491 00:24:52.067763 ==
2492 00:24:52.070755 Dram Type= 6, Freq= 0, CH_0, rank 0
2493 00:24:52.074382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2494 00:24:52.074500 ==
2495 00:24:52.080755 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2496 00:24:52.087027 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2497 00:24:52.094938 [CA 0] Center 39 (9~70) winsize 62
2498 00:24:52.098257 [CA 1] Center 39 (9~69) winsize 61
2499 00:24:52.101596 [CA 2] Center 35 (5~66) winsize 62
2500 00:24:52.105161 [CA 3] Center 35 (5~66) winsize 62
2501 00:24:52.108695 [CA 4] Center 33 (3~64) winsize 62
2502 00:24:52.111778 [CA 5] Center 33 (3~63) winsize 61
2503 00:24:52.111847
2504 00:24:52.115339 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2505 00:24:52.115413
2506 00:24:52.118264 [CATrainingPosCal] consider 1 rank data
2507 00:24:52.121354 u2DelayCellTimex100 = 270/100 ps
2508 00:24:52.125253 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2509 00:24:52.128623 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2510 00:24:52.135219 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2511 00:24:52.138285 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2512 00:24:52.142064 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2513 00:24:52.144995 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2514 00:24:52.145069
2515 00:24:52.148015 CA PerBit enable=1, Macro0, CA PI delay=33
2516 00:24:52.148086
2517 00:24:52.151763 [CBTSetCACLKResult] CA Dly = 33
2518 00:24:52.151840 CS Dly: 7 (0~38)
2519 00:24:52.154865 ==
2520 00:24:52.154936 Dram Type= 6, Freq= 0, CH_0, rank 1
2521 00:24:52.161230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 00:24:52.161303 ==
2523 00:24:52.164638 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2524 00:24:52.171293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2525 00:24:52.180890 [CA 0] Center 39 (9~70) winsize 62
2526 00:24:52.184192 [CA 1] Center 39 (9~70) winsize 62
2527 00:24:52.187509 [CA 2] Center 35 (5~66) winsize 62
2528 00:24:52.190870 [CA 3] Center 35 (5~66) winsize 62
2529 00:24:52.194513 [CA 4] Center 34 (4~65) winsize 62
2530 00:24:52.197416 [CA 5] Center 33 (3~64) winsize 62
2531 00:24:52.197490
2532 00:24:52.200646 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2533 00:24:52.200719
2534 00:24:52.203740 [CATrainingPosCal] consider 2 rank data
2535 00:24:52.207326 u2DelayCellTimex100 = 270/100 ps
2536 00:24:52.210630 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2537 00:24:52.217046 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2538 00:24:52.220523 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2539 00:24:52.223997 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2540 00:24:52.227026 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2541 00:24:52.230583 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2542 00:24:52.230690
2543 00:24:52.233943 CA PerBit enable=1, Macro0, CA PI delay=33
2544 00:24:52.234017
2545 00:24:52.237630 [CBTSetCACLKResult] CA Dly = 33
2546 00:24:52.237706 CS Dly: 8 (0~41)
2547 00:24:52.237805
2548 00:24:52.240801 ----->DramcWriteLeveling(PI) begin...
2549 00:24:52.243688 ==
2550 00:24:52.247612 Dram Type= 6, Freq= 0, CH_0, rank 0
2551 00:24:52.250323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2552 00:24:52.250398 ==
2553 00:24:52.253820 Write leveling (Byte 0): 30 => 30
2554 00:24:52.257124 Write leveling (Byte 1): 27 => 27
2555 00:24:52.260341 DramcWriteLeveling(PI) end<-----
2556 00:24:52.260424
2557 00:24:52.260490 ==
2558 00:24:52.263647 Dram Type= 6, Freq= 0, CH_0, rank 0
2559 00:24:52.266834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2560 00:24:52.266918 ==
2561 00:24:52.270412 [Gating] SW mode calibration
2562 00:24:52.276953 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2563 00:24:52.283450 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2564 00:24:52.287015 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2565 00:24:52.290373 0 15 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
2566 00:24:52.296928 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2567 00:24:52.300559 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2568 00:24:52.303522 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2569 00:24:52.310233 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2570 00:24:52.313680 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2571 00:24:52.316384 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)
2572 00:24:52.323094 1 0 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
2573 00:24:52.326824 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2574 00:24:52.330212 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2575 00:24:52.336906 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2576 00:24:52.339796 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2577 00:24:52.343085 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2578 00:24:52.346315 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2579 00:24:52.353321 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2580 00:24:52.356253 1 1 0 | B1->B0 | 2a2a 4646 | 1 0 | (0 0) (0 0)
2581 00:24:52.360055 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
2582 00:24:52.366166 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 00:24:52.370012 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 00:24:52.372686 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 00:24:52.379803 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2586 00:24:52.382807 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 00:24:52.385972 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2588 00:24:52.392912 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2589 00:24:52.396057 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2590 00:24:52.399388 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 00:24:52.406024 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 00:24:52.410015 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 00:24:52.412989 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 00:24:52.419588 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 00:24:52.423312 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 00:24:52.426652 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 00:24:52.432606 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 00:24:52.436151 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 00:24:52.439531 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 00:24:52.445928 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 00:24:52.449425 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 00:24:52.454232 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2603 00:24:52.459197 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2604 00:24:52.462428 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2605 00:24:52.465955 Total UI for P1: 0, mck2ui 16
2606 00:24:52.469215 best dqsien dly found for B0: ( 1, 3, 26)
2607 00:24:52.472708 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 00:24:52.475965 Total UI for P1: 0, mck2ui 16
2609 00:24:52.479804 best dqsien dly found for B1: ( 1, 4, 0)
2610 00:24:52.482525 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2611 00:24:52.486820 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2612 00:24:52.486897
2613 00:24:52.489532 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2614 00:24:52.492632 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2615 00:24:52.495835 [Gating] SW calibration Done
2616 00:24:52.495953 ==
2617 00:24:52.499208 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 00:24:52.506346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 00:24:52.506427 ==
2620 00:24:52.506491 RX Vref Scan: 0
2621 00:24:52.506552
2622 00:24:52.509399 RX Vref 0 -> 0, step: 1
2623 00:24:52.509490
2624 00:24:52.512582 RX Delay -40 -> 252, step: 8
2625 00:24:52.515942 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2626 00:24:52.519092 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2627 00:24:52.522466 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2628 00:24:52.525961 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2629 00:24:52.532601 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2630 00:24:52.536436 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2631 00:24:52.539349 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2632 00:24:52.542578 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2633 00:24:52.545820 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2634 00:24:52.552708 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2635 00:24:52.555805 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2636 00:24:52.559160 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2637 00:24:52.562457 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2638 00:24:52.565716 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2639 00:24:52.572504 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2640 00:24:52.575882 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2641 00:24:52.575998 ==
2642 00:24:52.579159 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 00:24:52.582539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 00:24:52.582608 ==
2645 00:24:52.585979 DQS Delay:
2646 00:24:52.586048 DQS0 = 0, DQS1 = 0
2647 00:24:52.586108 DQM Delay:
2648 00:24:52.589141 DQM0 = 117, DQM1 = 108
2649 00:24:52.589209 DQ Delay:
2650 00:24:52.592369 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =111
2651 00:24:52.595887 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2652 00:24:52.598940 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2653 00:24:52.605610 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =115
2654 00:24:52.605720
2655 00:24:52.605781
2656 00:24:52.605838 ==
2657 00:24:52.609279 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 00:24:52.613111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 00:24:52.613187 ==
2660 00:24:52.613249
2661 00:24:52.613307
2662 00:24:52.615981 TX Vref Scan disable
2663 00:24:52.616061 == TX Byte 0 ==
2664 00:24:52.622632 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2665 00:24:52.625720 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2666 00:24:52.625798 == TX Byte 1 ==
2667 00:24:52.632482 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2668 00:24:52.635589 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2669 00:24:52.635695 ==
2670 00:24:52.639181 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 00:24:52.642420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 00:24:52.642521 ==
2673 00:24:52.655386 TX Vref=22, minBit 10, minWin=24, winSum=412
2674 00:24:52.658626 TX Vref=24, minBit 0, minWin=25, winSum=414
2675 00:24:52.661617 TX Vref=26, minBit 1, minWin=26, winSum=422
2676 00:24:52.665233 TX Vref=28, minBit 1, minWin=26, winSum=428
2677 00:24:52.669239 TX Vref=30, minBit 13, minWin=25, winSum=423
2678 00:24:52.674949 TX Vref=32, minBit 0, minWin=26, winSum=425
2679 00:24:52.678250 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
2680 00:24:52.678327
2681 00:24:52.681938 Final TX Range 1 Vref 28
2682 00:24:52.682012
2683 00:24:52.682075 ==
2684 00:24:52.685074 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 00:24:52.687918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 00:24:52.691343 ==
2687 00:24:52.691442
2688 00:24:52.691539
2689 00:24:52.691631 TX Vref Scan disable
2690 00:24:52.694752 == TX Byte 0 ==
2691 00:24:52.698395 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2692 00:24:52.704757 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2693 00:24:52.704836 == TX Byte 1 ==
2694 00:24:52.708417 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2695 00:24:52.714605 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2696 00:24:52.714678
2697 00:24:52.714765 [DATLAT]
2698 00:24:52.714843 Freq=1200, CH0 RK0
2699 00:24:52.714904
2700 00:24:52.718304 DATLAT Default: 0xd
2701 00:24:52.718377 0, 0xFFFF, sum = 0
2702 00:24:52.721234 1, 0xFFFF, sum = 0
2703 00:24:52.724630 2, 0xFFFF, sum = 0
2704 00:24:52.724726 3, 0xFFFF, sum = 0
2705 00:24:52.728240 4, 0xFFFF, sum = 0
2706 00:24:52.728332 5, 0xFFFF, sum = 0
2707 00:24:52.731390 6, 0xFFFF, sum = 0
2708 00:24:52.731510 7, 0xFFFF, sum = 0
2709 00:24:52.734983 8, 0xFFFF, sum = 0
2710 00:24:52.735083 9, 0xFFFF, sum = 0
2711 00:24:52.737943 10, 0xFFFF, sum = 0
2712 00:24:52.738022 11, 0xFFFF, sum = 0
2713 00:24:52.741140 12, 0x0, sum = 1
2714 00:24:52.741222 13, 0x0, sum = 2
2715 00:24:52.744869 14, 0x0, sum = 3
2716 00:24:52.744941 15, 0x0, sum = 4
2717 00:24:52.748018 best_step = 13
2718 00:24:52.748118
2719 00:24:52.748216 ==
2720 00:24:52.751315 Dram Type= 6, Freq= 0, CH_0, rank 0
2721 00:24:52.754513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2722 00:24:52.754592 ==
2723 00:24:52.758102 RX Vref Scan: 1
2724 00:24:52.758177
2725 00:24:52.758239 Set Vref Range= 32 -> 127
2726 00:24:52.758299
2727 00:24:52.761180 RX Vref 32 -> 127, step: 1
2728 00:24:52.761256
2729 00:24:52.764309 RX Delay -21 -> 252, step: 4
2730 00:24:52.764385
2731 00:24:52.767491 Set Vref, RX VrefLevel [Byte0]: 32
2732 00:24:52.771071 [Byte1]: 32
2733 00:24:52.771154
2734 00:24:52.774688 Set Vref, RX VrefLevel [Byte0]: 33
2735 00:24:52.777458 [Byte1]: 33
2736 00:24:52.781653
2737 00:24:52.781723 Set Vref, RX VrefLevel [Byte0]: 34
2738 00:24:52.785012 [Byte1]: 34
2739 00:24:52.789166
2740 00:24:52.789243 Set Vref, RX VrefLevel [Byte0]: 35
2741 00:24:52.792618 [Byte1]: 35
2742 00:24:52.797138
2743 00:24:52.797225 Set Vref, RX VrefLevel [Byte0]: 36
2744 00:24:52.800642 [Byte1]: 36
2745 00:24:52.805611
2746 00:24:52.805685 Set Vref, RX VrefLevel [Byte0]: 37
2747 00:24:52.808452 [Byte1]: 37
2748 00:24:52.812914
2749 00:24:52.812993 Set Vref, RX VrefLevel [Byte0]: 38
2750 00:24:52.816188 [Byte1]: 38
2751 00:24:52.821636
2752 00:24:52.821711 Set Vref, RX VrefLevel [Byte0]: 39
2753 00:24:52.824270 [Byte1]: 39
2754 00:24:52.829031
2755 00:24:52.829107 Set Vref, RX VrefLevel [Byte0]: 40
2756 00:24:52.831997 [Byte1]: 40
2757 00:24:52.836828
2758 00:24:52.836900 Set Vref, RX VrefLevel [Byte0]: 41
2759 00:24:52.840016 [Byte1]: 41
2760 00:24:52.844956
2761 00:24:52.845065 Set Vref, RX VrefLevel [Byte0]: 42
2762 00:24:52.847846 [Byte1]: 42
2763 00:24:52.852859
2764 00:24:52.852969 Set Vref, RX VrefLevel [Byte0]: 43
2765 00:24:52.856046 [Byte1]: 43
2766 00:24:52.860682
2767 00:24:52.860781 Set Vref, RX VrefLevel [Byte0]: 44
2768 00:24:52.863978 [Byte1]: 44
2769 00:24:52.869173
2770 00:24:52.869254 Set Vref, RX VrefLevel [Byte0]: 45
2771 00:24:52.872092 [Byte1]: 45
2772 00:24:52.876362
2773 00:24:52.876470 Set Vref, RX VrefLevel [Byte0]: 46
2774 00:24:52.879860 [Byte1]: 46
2775 00:24:52.884351
2776 00:24:52.884433 Set Vref, RX VrefLevel [Byte0]: 47
2777 00:24:52.888297 [Byte1]: 47
2778 00:24:52.892352
2779 00:24:52.892424 Set Vref, RX VrefLevel [Byte0]: 48
2780 00:24:52.896000 [Byte1]: 48
2781 00:24:52.900553
2782 00:24:52.900629 Set Vref, RX VrefLevel [Byte0]: 49
2783 00:24:52.903567 [Byte1]: 49
2784 00:24:52.908387
2785 00:24:52.908460 Set Vref, RX VrefLevel [Byte0]: 50
2786 00:24:52.911363 [Byte1]: 50
2787 00:24:52.916333
2788 00:24:52.916412 Set Vref, RX VrefLevel [Byte0]: 51
2789 00:24:52.919612 [Byte1]: 51
2790 00:24:52.923985
2791 00:24:52.924057 Set Vref, RX VrefLevel [Byte0]: 52
2792 00:24:52.927668 [Byte1]: 52
2793 00:24:52.931910
2794 00:24:52.931984 Set Vref, RX VrefLevel [Byte0]: 53
2795 00:24:52.935432 [Byte1]: 53
2796 00:24:52.939797
2797 00:24:52.939897 Set Vref, RX VrefLevel [Byte0]: 54
2798 00:24:52.943742 [Byte1]: 54
2799 00:24:52.947845
2800 00:24:52.947966 Set Vref, RX VrefLevel [Byte0]: 55
2801 00:24:52.951298 [Byte1]: 55
2802 00:24:52.955607
2803 00:24:52.955711 Set Vref, RX VrefLevel [Byte0]: 56
2804 00:24:52.959330 [Byte1]: 56
2805 00:24:52.963758
2806 00:24:52.963844 Set Vref, RX VrefLevel [Byte0]: 57
2807 00:24:52.966975 [Byte1]: 57
2808 00:24:52.971809
2809 00:24:52.971930 Set Vref, RX VrefLevel [Byte0]: 58
2810 00:24:52.975105 [Byte1]: 58
2811 00:24:52.979717
2812 00:24:52.979796 Set Vref, RX VrefLevel [Byte0]: 59
2813 00:24:52.983048 [Byte1]: 59
2814 00:24:52.987662
2815 00:24:52.987742 Set Vref, RX VrefLevel [Byte0]: 60
2816 00:24:52.990741 [Byte1]: 60
2817 00:24:52.995724
2818 00:24:52.995798 Set Vref, RX VrefLevel [Byte0]: 61
2819 00:24:52.999227 [Byte1]: 61
2820 00:24:53.003439
2821 00:24:53.003529 Set Vref, RX VrefLevel [Byte0]: 62
2822 00:24:53.006800 [Byte1]: 62
2823 00:24:53.011055
2824 00:24:53.011162 Set Vref, RX VrefLevel [Byte0]: 63
2825 00:24:53.014359 [Byte1]: 63
2826 00:24:53.019592
2827 00:24:53.019677 Set Vref, RX VrefLevel [Byte0]: 64
2828 00:24:53.022945 [Byte1]: 64
2829 00:24:53.026868
2830 00:24:53.026944 Set Vref, RX VrefLevel [Byte0]: 65
2831 00:24:53.030641 [Byte1]: 65
2832 00:24:53.035139
2833 00:24:53.035254 Set Vref, RX VrefLevel [Byte0]: 66
2834 00:24:53.038333 [Byte1]: 66
2835 00:24:53.042983
2836 00:24:53.043084 Set Vref, RX VrefLevel [Byte0]: 67
2837 00:24:53.046376 [Byte1]: 67
2838 00:24:53.050686
2839 00:24:53.050769 Set Vref, RX VrefLevel [Byte0]: 68
2840 00:24:53.053903 [Byte1]: 68
2841 00:24:53.058715
2842 00:24:53.058798 Final RX Vref Byte 0 = 52 to rank0
2843 00:24:53.062066 Final RX Vref Byte 1 = 49 to rank0
2844 00:24:53.065298 Final RX Vref Byte 0 = 52 to rank1
2845 00:24:53.068690 Final RX Vref Byte 1 = 49 to rank1==
2846 00:24:53.071892 Dram Type= 6, Freq= 0, CH_0, rank 0
2847 00:24:53.078651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 00:24:53.078765 ==
2849 00:24:53.078854 DQS Delay:
2850 00:24:53.078952 DQS0 = 0, DQS1 = 0
2851 00:24:53.082143 DQM Delay:
2852 00:24:53.082224 DQM0 = 117, DQM1 = 105
2853 00:24:53.085467 DQ Delay:
2854 00:24:53.088756 DQ0 =118, DQ1 =118, DQ2 =114, DQ3 =114
2855 00:24:53.092316 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2856 00:24:53.095311 DQ8 =96, DQ9 =90, DQ10 =104, DQ11 =100
2857 00:24:53.098503 DQ12 =112, DQ13 =110, DQ14 =116, DQ15 =112
2858 00:24:53.098595
2859 00:24:53.098663
2860 00:24:53.104965 [DQSOSCAuto] RK0, (LSB)MR18= 0xfc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
2861 00:24:53.108805 CH0 RK0: MR19=403, MR18=FC
2862 00:24:53.115493 CH0_RK0: MR19=0x403, MR18=0xFC, DQSOSC=410, MR23=63, INC=39, DEC=26
2863 00:24:53.115590
2864 00:24:53.118090 ----->DramcWriteLeveling(PI) begin...
2865 00:24:53.118191 ==
2866 00:24:53.121564 Dram Type= 6, Freq= 0, CH_0, rank 1
2867 00:24:53.124951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2868 00:24:53.128358 ==
2869 00:24:53.128436 Write leveling (Byte 0): 32 => 32
2870 00:24:53.131539 Write leveling (Byte 1): 28 => 28
2871 00:24:53.134682 DramcWriteLeveling(PI) end<-----
2872 00:24:53.134851
2873 00:24:53.134942 ==
2874 00:24:53.138535 Dram Type= 6, Freq= 0, CH_0, rank 1
2875 00:24:53.144926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2876 00:24:53.145037 ==
2877 00:24:53.145130 [Gating] SW mode calibration
2878 00:24:53.154599 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2879 00:24:53.158306 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2880 00:24:53.165016 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2881 00:24:53.168200 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2882 00:24:53.171465 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2883 00:24:53.174724 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2884 00:24:53.181138 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2885 00:24:53.184645 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 00:24:53.188270 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2887 00:24:53.195220 0 15 28 | B1->B0 | 3434 2525 | 0 0 | (0 0) (0 0)
2888 00:24:53.197920 1 0 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
2889 00:24:53.201224 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 00:24:53.208027 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 00:24:53.211201 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 00:24:53.214602 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 00:24:53.221778 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 00:24:53.224629 1 0 24 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
2895 00:24:53.228026 1 0 28 | B1->B0 | 2a2a 4545 | 0 0 | (1 1) (0 0)
2896 00:24:53.234851 1 1 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2897 00:24:53.237659 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 00:24:53.241300 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 00:24:53.247765 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 00:24:53.251231 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 00:24:53.254498 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 00:24:53.260780 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2903 00:24:53.264310 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2904 00:24:53.267360 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2905 00:24:53.274635 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 00:24:53.277489 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 00:24:53.280842 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 00:24:53.287428 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 00:24:53.290972 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 00:24:53.294677 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 00:24:53.300942 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 00:24:53.304443 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 00:24:53.307339 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 00:24:53.313970 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 00:24:53.317250 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 00:24:53.320507 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 00:24:53.327217 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 00:24:53.330843 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2919 00:24:53.334003 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2920 00:24:53.340541 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2921 00:24:53.340624 Total UI for P1: 0, mck2ui 16
2922 00:24:53.344025 best dqsien dly found for B0: ( 1, 3, 26)
2923 00:24:53.350545 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 00:24:53.353786 Total UI for P1: 0, mck2ui 16
2925 00:24:53.357580 best dqsien dly found for B1: ( 1, 4, 0)
2926 00:24:53.360575 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2927 00:24:53.363597 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2928 00:24:53.363677
2929 00:24:53.367110 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2930 00:24:53.370406 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2931 00:24:53.373478 [Gating] SW calibration Done
2932 00:24:53.373554 ==
2933 00:24:53.376966 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 00:24:53.380620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 00:24:53.380704 ==
2936 00:24:53.383694 RX Vref Scan: 0
2937 00:24:53.383796
2938 00:24:53.383898 RX Vref 0 -> 0, step: 1
2939 00:24:53.387233
2940 00:24:53.387344 RX Delay -40 -> 252, step: 8
2941 00:24:53.394053 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2942 00:24:53.397459 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2943 00:24:53.400483 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2944 00:24:53.403871 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2945 00:24:53.406842 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2946 00:24:53.413411 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2947 00:24:53.416851 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2948 00:24:53.420075 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2949 00:24:53.423344 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2950 00:24:53.426958 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2951 00:24:53.430109 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2952 00:24:53.436919 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2953 00:24:53.440035 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2954 00:24:53.443527 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2955 00:24:53.446386 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2956 00:24:53.453310 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2957 00:24:53.453391 ==
2958 00:24:53.456321 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 00:24:53.459636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 00:24:53.459710 ==
2961 00:24:53.459779 DQS Delay:
2962 00:24:53.462947 DQS0 = 0, DQS1 = 0
2963 00:24:53.463025 DQM Delay:
2964 00:24:53.466607 DQM0 = 115, DQM1 = 106
2965 00:24:53.466680 DQ Delay:
2966 00:24:53.469550 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2967 00:24:53.473431 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =119
2968 00:24:53.476588 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2969 00:24:53.479662 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2970 00:24:53.479738
2971 00:24:53.479800
2972 00:24:53.483195 ==
2973 00:24:53.483270 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 00:24:53.489657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 00:24:53.489737 ==
2976 00:24:53.489799
2977 00:24:53.489859
2978 00:24:53.493440 TX Vref Scan disable
2979 00:24:53.493512 == TX Byte 0 ==
2980 00:24:53.496236 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2981 00:24:53.503121 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2982 00:24:53.503203 == TX Byte 1 ==
2983 00:24:53.506216 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2984 00:24:53.513317 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2985 00:24:53.513398 ==
2986 00:24:53.516112 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 00:24:53.519728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 00:24:53.519809 ==
2989 00:24:53.531692 TX Vref=22, minBit 13, minWin=25, winSum=419
2990 00:24:53.534981 TX Vref=24, minBit 1, minWin=26, winSum=425
2991 00:24:53.538613 TX Vref=26, minBit 2, minWin=26, winSum=430
2992 00:24:53.542346 TX Vref=28, minBit 4, minWin=26, winSum=429
2993 00:24:53.545532 TX Vref=30, minBit 4, minWin=26, winSum=430
2994 00:24:53.551811 TX Vref=32, minBit 4, minWin=26, winSum=429
2995 00:24:53.555136 [TxChooseVref] Worse bit 2, Min win 26, Win sum 430, Final Vref 26
2996 00:24:53.555234
2997 00:24:53.558413 Final TX Range 1 Vref 26
2998 00:24:53.558487
2999 00:24:53.558560 ==
3000 00:24:53.561766 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 00:24:53.565608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 00:24:53.565681 ==
3003 00:24:53.568336
3004 00:24:53.568438
3005 00:24:53.568525 TX Vref Scan disable
3006 00:24:53.571443 == TX Byte 0 ==
3007 00:24:53.574757 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3008 00:24:53.578769 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3009 00:24:53.581840 == TX Byte 1 ==
3010 00:24:53.585077 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3011 00:24:53.588051 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3012 00:24:53.591969
3013 00:24:53.592043 [DATLAT]
3014 00:24:53.592112 Freq=1200, CH0 RK1
3015 00:24:53.592173
3016 00:24:53.595072 DATLAT Default: 0xd
3017 00:24:53.595150 0, 0xFFFF, sum = 0
3018 00:24:53.598616 1, 0xFFFF, sum = 0
3019 00:24:53.598692 2, 0xFFFF, sum = 0
3020 00:24:53.601662 3, 0xFFFF, sum = 0
3021 00:24:53.601732 4, 0xFFFF, sum = 0
3022 00:24:53.604837 5, 0xFFFF, sum = 0
3023 00:24:53.608749 6, 0xFFFF, sum = 0
3024 00:24:53.608825 7, 0xFFFF, sum = 0
3025 00:24:53.611572 8, 0xFFFF, sum = 0
3026 00:24:53.611650 9, 0xFFFF, sum = 0
3027 00:24:53.614865 10, 0xFFFF, sum = 0
3028 00:24:53.614942 11, 0xFFFF, sum = 0
3029 00:24:53.618775 12, 0x0, sum = 1
3030 00:24:53.618851 13, 0x0, sum = 2
3031 00:24:53.621600 14, 0x0, sum = 3
3032 00:24:53.621675 15, 0x0, sum = 4
3033 00:24:53.621741 best_step = 13
3034 00:24:53.624703
3035 00:24:53.624780 ==
3036 00:24:53.628205 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 00:24:53.631507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 00:24:53.631581 ==
3039 00:24:53.631648 RX Vref Scan: 0
3040 00:24:53.631713
3041 00:24:53.635038 RX Vref 0 -> 0, step: 1
3042 00:24:53.635111
3043 00:24:53.638282 RX Delay -21 -> 252, step: 4
3044 00:24:53.641983 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3045 00:24:53.648723 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3046 00:24:53.651438 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3047 00:24:53.655049 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3048 00:24:53.658496 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3049 00:24:53.661188 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3050 00:24:53.668231 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3051 00:24:53.671318 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3052 00:24:53.674480 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3053 00:24:53.677818 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3054 00:24:53.681610 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3055 00:24:53.687795 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3056 00:24:53.691427 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3057 00:24:53.694555 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3058 00:24:53.698347 iDelay=195, Bit 14, Center 118 (51 ~ 186) 136
3059 00:24:53.701208 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3060 00:24:53.701287 ==
3061 00:24:53.704668 Dram Type= 6, Freq= 0, CH_0, rank 1
3062 00:24:53.711036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 00:24:53.711116 ==
3064 00:24:53.711187 DQS Delay:
3065 00:24:53.714769 DQS0 = 0, DQS1 = 0
3066 00:24:53.714845 DQM Delay:
3067 00:24:53.717918 DQM0 = 115, DQM1 = 105
3068 00:24:53.717987 DQ Delay:
3069 00:24:53.721154 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3070 00:24:53.725009 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3071 00:24:53.727765 DQ8 =96, DQ9 =94, DQ10 =106, DQ11 =98
3072 00:24:53.731076 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =112
3073 00:24:53.731152
3074 00:24:53.731213
3075 00:24:53.741190 [DQSOSCAuto] RK1, (LSB)MR18= 0xfdfa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
3076 00:24:53.741277 CH0 RK1: MR19=303, MR18=FDFA
3077 00:24:53.748060 CH0_RK1: MR19=0x303, MR18=0xFDFA, DQSOSC=411, MR23=63, INC=38, DEC=25
3078 00:24:53.750977 [RxdqsGatingPostProcess] freq 1200
3079 00:24:53.758105 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3080 00:24:53.761395 best DQS0 dly(2T, 0.5T) = (0, 11)
3081 00:24:53.764184 best DQS1 dly(2T, 0.5T) = (0, 12)
3082 00:24:53.767786 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3083 00:24:53.770644 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3084 00:24:53.774565 best DQS0 dly(2T, 0.5T) = (0, 11)
3085 00:24:53.774645 best DQS1 dly(2T, 0.5T) = (0, 12)
3086 00:24:53.778432 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3087 00:24:53.780716 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3088 00:24:53.784060 Pre-setting of DQS Precalculation
3089 00:24:53.790793 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3090 00:24:53.790890 ==
3091 00:24:53.794317 Dram Type= 6, Freq= 0, CH_1, rank 0
3092 00:24:53.797601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 00:24:53.797681 ==
3094 00:24:53.804088 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3095 00:24:53.810424 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3096 00:24:53.817570 [CA 0] Center 38 (8~68) winsize 61
3097 00:24:53.821198 [CA 1] Center 37 (7~68) winsize 62
3098 00:24:53.824477 [CA 2] Center 35 (5~65) winsize 61
3099 00:24:53.827557 [CA 3] Center 34 (4~64) winsize 61
3100 00:24:53.830954 [CA 4] Center 34 (4~65) winsize 62
3101 00:24:53.834617 [CA 5] Center 33 (3~63) winsize 61
3102 00:24:53.834697
3103 00:24:53.837568 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3104 00:24:53.837641
3105 00:24:53.841571 [CATrainingPosCal] consider 1 rank data
3106 00:24:53.844139 u2DelayCellTimex100 = 270/100 ps
3107 00:24:53.847802 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3108 00:24:53.851034 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3109 00:24:53.857954 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3110 00:24:53.860926 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3111 00:24:53.864212 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3112 00:24:53.867772 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3113 00:24:53.867877
3114 00:24:53.871016 CA PerBit enable=1, Macro0, CA PI delay=33
3115 00:24:53.871089
3116 00:24:53.874470 [CBTSetCACLKResult] CA Dly = 33
3117 00:24:53.874546 CS Dly: 4 (0~35)
3118 00:24:53.878338 ==
3119 00:24:53.878417 Dram Type= 6, Freq= 0, CH_1, rank 1
3120 00:24:53.884343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 00:24:53.884423 ==
3122 00:24:53.887502 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3123 00:24:53.894251 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3124 00:24:53.903245 [CA 0] Center 37 (7~68) winsize 62
3125 00:24:53.906893 [CA 1] Center 38 (7~69) winsize 63
3126 00:24:53.910028 [CA 2] Center 34 (4~65) winsize 62
3127 00:24:53.913081 [CA 3] Center 33 (3~64) winsize 62
3128 00:24:53.916773 [CA 4] Center 33 (4~63) winsize 60
3129 00:24:53.920133 [CA 5] Center 33 (3~63) winsize 61
3130 00:24:53.920227
3131 00:24:53.923325 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3132 00:24:53.923405
3133 00:24:53.926285 [CATrainingPosCal] consider 2 rank data
3134 00:24:53.929575 u2DelayCellTimex100 = 270/100 ps
3135 00:24:53.932860 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3136 00:24:53.939350 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3137 00:24:53.942959 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3138 00:24:53.947350 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3139 00:24:53.950391 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
3140 00:24:53.953433 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3141 00:24:53.953518
3142 00:24:53.955958 CA PerBit enable=1, Macro0, CA PI delay=33
3143 00:24:53.956032
3144 00:24:53.959751 [CBTSetCACLKResult] CA Dly = 33
3145 00:24:53.962800 CS Dly: 6 (0~39)
3146 00:24:53.962924
3147 00:24:53.966038 ----->DramcWriteLeveling(PI) begin...
3148 00:24:53.966119 ==
3149 00:24:53.969112 Dram Type= 6, Freq= 0, CH_1, rank 0
3150 00:24:53.972573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3151 00:24:53.972643 ==
3152 00:24:53.976347 Write leveling (Byte 0): 24 => 24
3153 00:24:53.979514 Write leveling (Byte 1): 26 => 26
3154 00:24:53.982881 DramcWriteLeveling(PI) end<-----
3155 00:24:53.982961
3156 00:24:53.983022 ==
3157 00:24:53.985913 Dram Type= 6, Freq= 0, CH_1, rank 0
3158 00:24:53.989641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3159 00:24:53.989721 ==
3160 00:24:53.993298 [Gating] SW mode calibration
3161 00:24:53.999254 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3162 00:24:54.005905 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3163 00:24:54.009542 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3164 00:24:54.012593 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 00:24:54.019310 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3166 00:24:54.023061 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 00:24:54.026409 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 00:24:54.032454 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 00:24:54.036126 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3170 00:24:54.039124 0 15 28 | B1->B0 | 2d2d 2525 | 0 0 | (0 1) (1 1)
3171 00:24:54.045872 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 00:24:54.048917 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 00:24:54.052347 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3174 00:24:54.058935 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 00:24:54.062735 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 00:24:54.065386 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 00:24:54.072802 1 0 24 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
3178 00:24:54.075875 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3179 00:24:54.079034 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 00:24:54.082575 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 00:24:54.089229 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 00:24:54.092685 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 00:24:54.095747 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 00:24:54.102886 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 00:24:54.105374 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3186 00:24:54.109279 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3187 00:24:54.115452 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 00:24:54.119113 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 00:24:54.122595 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 00:24:54.128840 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 00:24:54.131967 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 00:24:54.135697 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 00:24:54.142309 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 00:24:54.145884 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 00:24:54.149103 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 00:24:54.155547 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 00:24:54.158850 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 00:24:54.161982 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 00:24:54.169395 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 00:24:54.171729 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 00:24:54.175197 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 00:24:54.181719 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3203 00:24:54.181797 Total UI for P1: 0, mck2ui 16
3204 00:24:54.188665 best dqsien dly found for B1: ( 1, 3, 26)
3205 00:24:54.192666 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 00:24:54.195679 Total UI for P1: 0, mck2ui 16
3207 00:24:54.198792 best dqsien dly found for B0: ( 1, 3, 28)
3208 00:24:54.201759 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3209 00:24:54.205976 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3210 00:24:54.206056
3211 00:24:54.208383 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3212 00:24:54.211742 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3213 00:24:54.215288 [Gating] SW calibration Done
3214 00:24:54.215396 ==
3215 00:24:54.218431 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 00:24:54.221865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 00:24:54.221946 ==
3218 00:24:54.225052 RX Vref Scan: 0
3219 00:24:54.225132
3220 00:24:54.228223 RX Vref 0 -> 0, step: 1
3221 00:24:54.228302
3222 00:24:54.228367 RX Delay -40 -> 252, step: 8
3223 00:24:54.235251 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3224 00:24:54.238619 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3225 00:24:54.241989 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3226 00:24:54.245080 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3227 00:24:54.248535 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3228 00:24:54.255434 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3229 00:24:54.258514 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3230 00:24:54.261814 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3231 00:24:54.265161 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3232 00:24:54.268450 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3233 00:24:54.274806 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3234 00:24:54.278076 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3235 00:24:54.281627 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3236 00:24:54.285026 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3237 00:24:54.288518 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3238 00:24:54.295522 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3239 00:24:54.295602 ==
3240 00:24:54.298661 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 00:24:54.301433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 00:24:54.301521 ==
3243 00:24:54.301624 DQS Delay:
3244 00:24:54.304767 DQS0 = 0, DQS1 = 0
3245 00:24:54.304842 DQM Delay:
3246 00:24:54.308068 DQM0 = 116, DQM1 = 112
3247 00:24:54.308140 DQ Delay:
3248 00:24:54.311620 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3249 00:24:54.315046 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3250 00:24:54.318259 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3251 00:24:54.321590 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3252 00:24:54.321681
3253 00:24:54.325049
3254 00:24:54.325173 ==
3255 00:24:54.328405 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 00:24:54.331435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 00:24:54.331547 ==
3258 00:24:54.331639
3259 00:24:54.331736
3260 00:24:54.334720 TX Vref Scan disable
3261 00:24:54.334805 == TX Byte 0 ==
3262 00:24:54.341092 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3263 00:24:54.344731 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3264 00:24:54.344813 == TX Byte 1 ==
3265 00:24:54.351687 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3266 00:24:54.354527 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3267 00:24:54.354610 ==
3268 00:24:54.357966 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 00:24:54.360964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 00:24:54.361076 ==
3271 00:24:54.373621 TX Vref=22, minBit 9, minWin=23, winSum=407
3272 00:24:54.377569 TX Vref=24, minBit 9, minWin=24, winSum=413
3273 00:24:54.380119 TX Vref=26, minBit 2, minWin=25, winSum=419
3274 00:24:54.383345 TX Vref=28, minBit 3, minWin=25, winSum=423
3275 00:24:54.386734 TX Vref=30, minBit 9, minWin=24, winSum=425
3276 00:24:54.390017 TX Vref=32, minBit 9, minWin=25, winSum=428
3277 00:24:54.396640 [TxChooseVref] Worse bit 9, Min win 25, Win sum 428, Final Vref 32
3278 00:24:54.396749
3279 00:24:54.399791 Final TX Range 1 Vref 32
3280 00:24:54.399891
3281 00:24:54.399970 ==
3282 00:24:54.403349 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 00:24:54.406765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 00:24:54.406867 ==
3285 00:24:54.410114
3286 00:24:54.410210
3287 00:24:54.410299 TX Vref Scan disable
3288 00:24:54.413288 == TX Byte 0 ==
3289 00:24:54.416960 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3290 00:24:54.420429 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3291 00:24:54.423892 == TX Byte 1 ==
3292 00:24:54.426496 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3293 00:24:54.429966 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3294 00:24:54.433150
3295 00:24:54.433232 [DATLAT]
3296 00:24:54.433317 Freq=1200, CH1 RK0
3297 00:24:54.433398
3298 00:24:54.436714 DATLAT Default: 0xd
3299 00:24:54.436797 0, 0xFFFF, sum = 0
3300 00:24:54.440087 1, 0xFFFF, sum = 0
3301 00:24:54.440168 2, 0xFFFF, sum = 0
3302 00:24:54.443468 3, 0xFFFF, sum = 0
3303 00:24:54.443550 4, 0xFFFF, sum = 0
3304 00:24:54.446832 5, 0xFFFF, sum = 0
3305 00:24:54.450010 6, 0xFFFF, sum = 0
3306 00:24:54.450093 7, 0xFFFF, sum = 0
3307 00:24:54.453287 8, 0xFFFF, sum = 0
3308 00:24:54.453369 9, 0xFFFF, sum = 0
3309 00:24:54.456501 10, 0xFFFF, sum = 0
3310 00:24:54.456583 11, 0xFFFF, sum = 0
3311 00:24:54.459922 12, 0x0, sum = 1
3312 00:24:54.460017 13, 0x0, sum = 2
3313 00:24:54.463237 14, 0x0, sum = 3
3314 00:24:54.463313 15, 0x0, sum = 4
3315 00:24:54.463395 best_step = 13
3316 00:24:54.463486
3317 00:24:54.466796 ==
3318 00:24:54.470378 Dram Type= 6, Freq= 0, CH_1, rank 0
3319 00:24:54.473687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3320 00:24:54.473769 ==
3321 00:24:54.473833 RX Vref Scan: 1
3322 00:24:54.473893
3323 00:24:54.476689 Set Vref Range= 32 -> 127
3324 00:24:54.476769
3325 00:24:54.480662 RX Vref 32 -> 127, step: 1
3326 00:24:54.480743
3327 00:24:54.483318 RX Delay -13 -> 252, step: 4
3328 00:24:54.483421
3329 00:24:54.486806 Set Vref, RX VrefLevel [Byte0]: 32
3330 00:24:54.489995 [Byte1]: 32
3331 00:24:54.490072
3332 00:24:54.493373 Set Vref, RX VrefLevel [Byte0]: 33
3333 00:24:54.496964 [Byte1]: 33
3334 00:24:54.497044
3335 00:24:54.500101 Set Vref, RX VrefLevel [Byte0]: 34
3336 00:24:54.503081 [Byte1]: 34
3337 00:24:54.507265
3338 00:24:54.507347 Set Vref, RX VrefLevel [Byte0]: 35
3339 00:24:54.510762 [Byte1]: 35
3340 00:24:54.515199
3341 00:24:54.515280 Set Vref, RX VrefLevel [Byte0]: 36
3342 00:24:54.518595 [Byte1]: 36
3343 00:24:54.523117
3344 00:24:54.523198 Set Vref, RX VrefLevel [Byte0]: 37
3345 00:24:54.526507 [Byte1]: 37
3346 00:24:54.531246
3347 00:24:54.531327 Set Vref, RX VrefLevel [Byte0]: 38
3348 00:24:54.534812 [Byte1]: 38
3349 00:24:54.539136
3350 00:24:54.539218 Set Vref, RX VrefLevel [Byte0]: 39
3351 00:24:54.542243 [Byte1]: 39
3352 00:24:54.546761
3353 00:24:54.546840 Set Vref, RX VrefLevel [Byte0]: 40
3354 00:24:54.550338 [Byte1]: 40
3355 00:24:54.554784
3356 00:24:54.554863 Set Vref, RX VrefLevel [Byte0]: 41
3357 00:24:54.557899 [Byte1]: 41
3358 00:24:54.562548
3359 00:24:54.562629 Set Vref, RX VrefLevel [Byte0]: 42
3360 00:24:54.566019 [Byte1]: 42
3361 00:24:54.570623
3362 00:24:54.570703 Set Vref, RX VrefLevel [Byte0]: 43
3363 00:24:54.573783 [Byte1]: 43
3364 00:24:54.578664
3365 00:24:54.578776 Set Vref, RX VrefLevel [Byte0]: 44
3366 00:24:54.581877 [Byte1]: 44
3367 00:24:54.586913
3368 00:24:54.587009 Set Vref, RX VrefLevel [Byte0]: 45
3369 00:24:54.589880 [Byte1]: 45
3370 00:24:54.594512
3371 00:24:54.594593 Set Vref, RX VrefLevel [Byte0]: 46
3372 00:24:54.597907 [Byte1]: 46
3373 00:24:54.601920
3374 00:24:54.602001 Set Vref, RX VrefLevel [Byte0]: 47
3375 00:24:54.605293 [Byte1]: 47
3376 00:24:54.609803
3377 00:24:54.609883 Set Vref, RX VrefLevel [Byte0]: 48
3378 00:24:54.613020 [Byte1]: 48
3379 00:24:54.618281
3380 00:24:54.618361 Set Vref, RX VrefLevel [Byte0]: 49
3381 00:24:54.621032 [Byte1]: 49
3382 00:24:54.625644
3383 00:24:54.625726 Set Vref, RX VrefLevel [Byte0]: 50
3384 00:24:54.628874 [Byte1]: 50
3385 00:24:54.633535
3386 00:24:54.633648 Set Vref, RX VrefLevel [Byte0]: 51
3387 00:24:54.636621 [Byte1]: 51
3388 00:24:54.641252
3389 00:24:54.641356 Set Vref, RX VrefLevel [Byte0]: 52
3390 00:24:54.644994 [Byte1]: 52
3391 00:24:54.649483
3392 00:24:54.649588 Set Vref, RX VrefLevel [Byte0]: 53
3393 00:24:54.652813 [Byte1]: 53
3394 00:24:54.657629
3395 00:24:54.657759 Set Vref, RX VrefLevel [Byte0]: 54
3396 00:24:54.660249 [Byte1]: 54
3397 00:24:54.664985
3398 00:24:54.665111 Set Vref, RX VrefLevel [Byte0]: 55
3399 00:24:54.668447 [Byte1]: 55
3400 00:24:54.673291
3401 00:24:54.673411 Set Vref, RX VrefLevel [Byte0]: 56
3402 00:24:54.676503 [Byte1]: 56
3403 00:24:54.681082
3404 00:24:54.681198 Set Vref, RX VrefLevel [Byte0]: 57
3405 00:24:54.683887 [Byte1]: 57
3406 00:24:54.688664
3407 00:24:54.688759 Set Vref, RX VrefLevel [Byte0]: 58
3408 00:24:54.691818 [Byte1]: 58
3409 00:24:54.696747
3410 00:24:54.696861 Set Vref, RX VrefLevel [Byte0]: 59
3411 00:24:54.700145 [Byte1]: 59
3412 00:24:54.704304
3413 00:24:54.704385 Set Vref, RX VrefLevel [Byte0]: 60
3414 00:24:54.707935 [Byte1]: 60
3415 00:24:54.712344
3416 00:24:54.712426 Set Vref, RX VrefLevel [Byte0]: 61
3417 00:24:54.715372 [Byte1]: 61
3418 00:24:54.720316
3419 00:24:54.720399 Set Vref, RX VrefLevel [Byte0]: 62
3420 00:24:54.723276 [Byte1]: 62
3421 00:24:54.727887
3422 00:24:54.727978 Set Vref, RX VrefLevel [Byte0]: 63
3423 00:24:54.731114 [Byte1]: 63
3424 00:24:54.735918
3425 00:24:54.736003 Set Vref, RX VrefLevel [Byte0]: 64
3426 00:24:54.739191 [Byte1]: 64
3427 00:24:54.743869
3428 00:24:54.743972 Set Vref, RX VrefLevel [Byte0]: 65
3429 00:24:54.747354 [Byte1]: 65
3430 00:24:54.751714
3431 00:24:54.751802 Final RX Vref Byte 0 = 53 to rank0
3432 00:24:54.755840 Final RX Vref Byte 1 = 51 to rank0
3433 00:24:54.758410 Final RX Vref Byte 0 = 53 to rank1
3434 00:24:54.762014 Final RX Vref Byte 1 = 51 to rank1==
3435 00:24:54.765271 Dram Type= 6, Freq= 0, CH_1, rank 0
3436 00:24:54.771941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3437 00:24:54.772031 ==
3438 00:24:54.772100 DQS Delay:
3439 00:24:54.772172 DQS0 = 0, DQS1 = 0
3440 00:24:54.775807 DQM Delay:
3441 00:24:54.775879 DQM0 = 114, DQM1 = 113
3442 00:24:54.778750 DQ Delay:
3443 00:24:54.781571 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3444 00:24:54.784778 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3445 00:24:54.788248 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3446 00:24:54.791631 DQ12 =120, DQ13 =122, DQ14 =120, DQ15 =122
3447 00:24:54.791715
3448 00:24:54.791779
3449 00:24:54.801387 [DQSOSCAuto] RK0, (LSB)MR18= 0xf2ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3450 00:24:54.801470 CH1 RK0: MR19=303, MR18=F2FF
3451 00:24:54.808035 CH1_RK0: MR19=0x303, MR18=0xF2FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3452 00:24:54.808122
3453 00:24:54.811353 ----->DramcWriteLeveling(PI) begin...
3454 00:24:54.811429 ==
3455 00:24:54.814794 Dram Type= 6, Freq= 0, CH_1, rank 1
3456 00:24:54.821367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3457 00:24:54.821462 ==
3458 00:24:54.825103 Write leveling (Byte 0): 24 => 24
3459 00:24:54.825181 Write leveling (Byte 1): 27 => 27
3460 00:24:54.827754 DramcWriteLeveling(PI) end<-----
3461 00:24:54.827828
3462 00:24:54.831660 ==
3463 00:24:54.831759 Dram Type= 6, Freq= 0, CH_1, rank 1
3464 00:24:54.838028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3465 00:24:54.838104 ==
3466 00:24:54.841229 [Gating] SW mode calibration
3467 00:24:54.848293 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3468 00:24:54.851281 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3469 00:24:54.857687 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 00:24:54.860873 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 00:24:54.864206 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3472 00:24:54.870771 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3473 00:24:54.874110 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3474 00:24:54.877398 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
3475 00:24:54.884013 0 15 24 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
3476 00:24:54.887691 0 15 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
3477 00:24:54.890959 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 00:24:54.897265 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 00:24:54.900908 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3480 00:24:54.904578 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3481 00:24:54.910785 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3482 00:24:54.914242 1 0 20 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
3483 00:24:54.917382 1 0 24 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
3484 00:24:54.924058 1 0 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
3485 00:24:54.927236 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 00:24:54.930429 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 00:24:54.937556 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 00:24:54.940387 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 00:24:54.944261 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 00:24:54.950461 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 00:24:54.953755 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3492 00:24:54.957308 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3493 00:24:54.964078 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 00:24:54.967656 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 00:24:54.970198 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 00:24:54.977185 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 00:24:54.980092 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 00:24:54.983437 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 00:24:54.990324 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 00:24:54.993316 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 00:24:54.996866 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 00:24:55.003810 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 00:24:55.006477 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 00:24:55.010210 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 00:24:55.016527 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 00:24:55.020518 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3507 00:24:55.023193 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3508 00:24:55.030211 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3509 00:24:55.030298 Total UI for P1: 0, mck2ui 16
3510 00:24:55.033039 best dqsien dly found for B0: ( 1, 3, 22)
3511 00:24:55.039264 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 00:24:55.042884 Total UI for P1: 0, mck2ui 16
3513 00:24:55.046265 best dqsien dly found for B1: ( 1, 3, 26)
3514 00:24:55.049669 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3515 00:24:55.053083 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3516 00:24:55.053172
3517 00:24:55.055773 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3518 00:24:55.059127 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3519 00:24:55.062478 [Gating] SW calibration Done
3520 00:24:55.062583 ==
3521 00:24:55.066024 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 00:24:55.069412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 00:24:55.072776 ==
3524 00:24:55.072862 RX Vref Scan: 0
3525 00:24:55.072950
3526 00:24:55.075668 RX Vref 0 -> 0, step: 1
3527 00:24:55.075754
3528 00:24:55.078849 RX Delay -40 -> 252, step: 8
3529 00:24:55.082716 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3530 00:24:55.085749 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3531 00:24:55.089227 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3532 00:24:55.092155 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3533 00:24:55.099232 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3534 00:24:55.102130 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3535 00:24:55.105233 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3536 00:24:55.108859 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3537 00:24:55.112067 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3538 00:24:55.118521 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3539 00:24:55.122173 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3540 00:24:55.125168 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3541 00:24:55.128423 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3542 00:24:55.131562 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3543 00:24:55.138698 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3544 00:24:55.141768 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3545 00:24:55.141849 ==
3546 00:24:55.144691 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 00:24:55.148408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 00:24:55.148484 ==
3549 00:24:55.151539 DQS Delay:
3550 00:24:55.151612 DQS0 = 0, DQS1 = 0
3551 00:24:55.154555 DQM Delay:
3552 00:24:55.154629 DQM0 = 115, DQM1 = 111
3553 00:24:55.154693 DQ Delay:
3554 00:24:55.158201 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3555 00:24:55.164982 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3556 00:24:55.167593 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3557 00:24:55.171331 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3558 00:24:55.171416
3559 00:24:55.171521
3560 00:24:55.171613 ==
3561 00:24:55.174326 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 00:24:55.177457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 00:24:55.177535 ==
3564 00:24:55.177599
3565 00:24:55.177659
3566 00:24:55.180737 TX Vref Scan disable
3567 00:24:55.184337 == TX Byte 0 ==
3568 00:24:55.188044 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3569 00:24:55.191044 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3570 00:24:55.194026 == TX Byte 1 ==
3571 00:24:55.198030 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3572 00:24:55.200760 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3573 00:24:55.200837 ==
3574 00:24:55.204340 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 00:24:55.210543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 00:24:55.210648 ==
3577 00:24:55.221153 TX Vref=22, minBit 9, minWin=24, winSum=415
3578 00:24:55.224526 TX Vref=24, minBit 9, minWin=23, winSum=418
3579 00:24:55.228176 TX Vref=26, minBit 9, minWin=25, winSum=425
3580 00:24:55.231557 TX Vref=28, minBit 9, minWin=25, winSum=428
3581 00:24:55.234449 TX Vref=30, minBit 9, minWin=25, winSum=431
3582 00:24:55.240591 TX Vref=32, minBit 9, minWin=25, winSum=433
3583 00:24:55.244018 [TxChooseVref] Worse bit 9, Min win 25, Win sum 433, Final Vref 32
3584 00:24:55.244123
3585 00:24:55.247373 Final TX Range 1 Vref 32
3586 00:24:55.247442
3587 00:24:55.247571 ==
3588 00:24:55.250393 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 00:24:55.254567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 00:24:55.257526 ==
3591 00:24:55.257603
3592 00:24:55.257673
3593 00:24:55.257733 TX Vref Scan disable
3594 00:24:55.260647 == TX Byte 0 ==
3595 00:24:55.264307 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3596 00:24:55.270566 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3597 00:24:55.270685 == TX Byte 1 ==
3598 00:24:55.274462 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3599 00:24:55.280578 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3600 00:24:55.280661
3601 00:24:55.280725 [DATLAT]
3602 00:24:55.280784 Freq=1200, CH1 RK1
3603 00:24:55.280843
3604 00:24:55.283534 DATLAT Default: 0xd
3605 00:24:55.286674 0, 0xFFFF, sum = 0
3606 00:24:55.286769 1, 0xFFFF, sum = 0
3607 00:24:55.290264 2, 0xFFFF, sum = 0
3608 00:24:55.290350 3, 0xFFFF, sum = 0
3609 00:24:55.293978 4, 0xFFFF, sum = 0
3610 00:24:55.294064 5, 0xFFFF, sum = 0
3611 00:24:55.297083 6, 0xFFFF, sum = 0
3612 00:24:55.297165 7, 0xFFFF, sum = 0
3613 00:24:55.300094 8, 0xFFFF, sum = 0
3614 00:24:55.300175 9, 0xFFFF, sum = 0
3615 00:24:55.303678 10, 0xFFFF, sum = 0
3616 00:24:55.303761 11, 0xFFFF, sum = 0
3617 00:24:55.307099 12, 0x0, sum = 1
3618 00:24:55.307180 13, 0x0, sum = 2
3619 00:24:55.310143 14, 0x0, sum = 3
3620 00:24:55.310273 15, 0x0, sum = 4
3621 00:24:55.313117 best_step = 13
3622 00:24:55.313197
3623 00:24:55.313261 ==
3624 00:24:55.316718 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 00:24:55.320147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 00:24:55.320228 ==
3627 00:24:55.323405 RX Vref Scan: 0
3628 00:24:55.323485
3629 00:24:55.323582 RX Vref 0 -> 0, step: 1
3630 00:24:55.323642
3631 00:24:55.326757 RX Delay -13 -> 252, step: 4
3632 00:24:55.333441 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3633 00:24:55.337123 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3634 00:24:55.339697 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3635 00:24:55.343260 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3636 00:24:55.346231 iDelay=195, Bit 4, Center 114 (43 ~ 186) 144
3637 00:24:55.353337 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3638 00:24:55.357101 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3639 00:24:55.359842 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3640 00:24:55.363040 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3641 00:24:55.366485 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3642 00:24:55.372745 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3643 00:24:55.375873 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3644 00:24:55.379284 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3645 00:24:55.382922 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3646 00:24:55.389179 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3647 00:24:55.392703 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3648 00:24:55.392787 ==
3649 00:24:55.395881 Dram Type= 6, Freq= 0, CH_1, rank 1
3650 00:24:55.399192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3651 00:24:55.399277 ==
3652 00:24:55.399361 DQS Delay:
3653 00:24:55.402507 DQS0 = 0, DQS1 = 0
3654 00:24:55.402590 DQM Delay:
3655 00:24:55.406164 DQM0 = 115, DQM1 = 111
3656 00:24:55.406255 DQ Delay:
3657 00:24:55.409261 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =114
3658 00:24:55.412776 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3659 00:24:55.416037 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3660 00:24:55.422405 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =120
3661 00:24:55.422505
3662 00:24:55.422607
3663 00:24:55.429594 [DQSOSCAuto] RK1, (LSB)MR18= 0xfc0e, (MSB)MR19= 0x304, tDQSOscB0 = 404 ps tDQSOscB1 = 411 ps
3664 00:24:55.432276 CH1 RK1: MR19=304, MR18=FC0E
3665 00:24:55.438634 CH1_RK1: MR19=0x304, MR18=0xFC0E, DQSOSC=404, MR23=63, INC=40, DEC=26
3666 00:24:55.442009 [RxdqsGatingPostProcess] freq 1200
3667 00:24:55.445483 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3668 00:24:55.448526 best DQS0 dly(2T, 0.5T) = (0, 11)
3669 00:24:55.452223 best DQS1 dly(2T, 0.5T) = (0, 11)
3670 00:24:55.455146 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3671 00:24:55.458976 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3672 00:24:55.461950 best DQS0 dly(2T, 0.5T) = (0, 11)
3673 00:24:55.465352 best DQS1 dly(2T, 0.5T) = (0, 11)
3674 00:24:55.468661 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3675 00:24:55.472595 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3676 00:24:55.475240 Pre-setting of DQS Precalculation
3677 00:24:55.478390 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3678 00:24:55.488269 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3679 00:24:55.495141 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3680 00:24:55.495278
3681 00:24:55.495407
3682 00:24:55.498053 [Calibration Summary] 2400 Mbps
3683 00:24:55.498133 CH 0, Rank 0
3684 00:24:55.501283 SW Impedance : PASS
3685 00:24:55.504697 DUTY Scan : NO K
3686 00:24:55.504780 ZQ Calibration : PASS
3687 00:24:55.508161 Jitter Meter : NO K
3688 00:24:55.511459 CBT Training : PASS
3689 00:24:55.511542 Write leveling : PASS
3690 00:24:55.514626 RX DQS gating : PASS
3691 00:24:55.514705 RX DQ/DQS(RDDQC) : PASS
3692 00:24:55.518394 TX DQ/DQS : PASS
3693 00:24:55.520818 RX DATLAT : PASS
3694 00:24:55.520889 RX DQ/DQS(Engine): PASS
3695 00:24:55.524666 TX OE : NO K
3696 00:24:55.524744 All Pass.
3697 00:24:55.524812
3698 00:24:55.527605 CH 0, Rank 1
3699 00:24:55.527691 SW Impedance : PASS
3700 00:24:55.531324 DUTY Scan : NO K
3701 00:24:55.534550 ZQ Calibration : PASS
3702 00:24:55.534635 Jitter Meter : NO K
3703 00:24:55.537654 CBT Training : PASS
3704 00:24:55.540690 Write leveling : PASS
3705 00:24:55.540776 RX DQS gating : PASS
3706 00:24:55.544378 RX DQ/DQS(RDDQC) : PASS
3707 00:24:55.547318 TX DQ/DQS : PASS
3708 00:24:55.547400 RX DATLAT : PASS
3709 00:24:55.550786 RX DQ/DQS(Engine): PASS
3710 00:24:55.554304 TX OE : NO K
3711 00:24:55.554387 All Pass.
3712 00:24:55.554453
3713 00:24:55.554514 CH 1, Rank 0
3714 00:24:55.557618 SW Impedance : PASS
3715 00:24:55.560846 DUTY Scan : NO K
3716 00:24:55.560928 ZQ Calibration : PASS
3717 00:24:55.564155 Jitter Meter : NO K
3718 00:24:55.567123 CBT Training : PASS
3719 00:24:55.567201 Write leveling : PASS
3720 00:24:55.570642 RX DQS gating : PASS
3721 00:24:55.574058 RX DQ/DQS(RDDQC) : PASS
3722 00:24:55.574140 TX DQ/DQS : PASS
3723 00:24:55.577280 RX DATLAT : PASS
3724 00:24:55.580132 RX DQ/DQS(Engine): PASS
3725 00:24:55.580214 TX OE : NO K
3726 00:24:55.580280 All Pass.
3727 00:24:55.583806
3728 00:24:55.583895 CH 1, Rank 1
3729 00:24:55.587276 SW Impedance : PASS
3730 00:24:55.587362 DUTY Scan : NO K
3731 00:24:55.590887 ZQ Calibration : PASS
3732 00:24:55.590972 Jitter Meter : NO K
3733 00:24:55.593962 CBT Training : PASS
3734 00:24:55.596830 Write leveling : PASS
3735 00:24:55.596914 RX DQS gating : PASS
3736 00:24:55.600285 RX DQ/DQS(RDDQC) : PASS
3737 00:24:55.603339 TX DQ/DQS : PASS
3738 00:24:55.603414 RX DATLAT : PASS
3739 00:24:55.607054 RX DQ/DQS(Engine): PASS
3740 00:24:55.610214 TX OE : NO K
3741 00:24:55.610290 All Pass.
3742 00:24:55.610354
3743 00:24:55.613332 DramC Write-DBI off
3744 00:24:55.613406 PER_BANK_REFRESH: Hybrid Mode
3745 00:24:55.616526 TX_TRACKING: ON
3746 00:24:55.626220 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3747 00:24:55.629905 [FAST_K] Save calibration result to emmc
3748 00:24:55.633093 dramc_set_vcore_voltage set vcore to 650000
3749 00:24:55.636790 Read voltage for 600, 5
3750 00:24:55.636876 Vio18 = 0
3751 00:24:55.636943 Vcore = 650000
3752 00:24:55.640007 Vdram = 0
3753 00:24:55.640077 Vddq = 0
3754 00:24:55.640149 Vmddr = 0
3755 00:24:55.646243 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3756 00:24:55.649458 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3757 00:24:55.653066 MEM_TYPE=3, freq_sel=19
3758 00:24:55.655993 sv_algorithm_assistance_LP4_1600
3759 00:24:55.659342 ============ PULL DRAM RESETB DOWN ============
3760 00:24:55.662688 ========== PULL DRAM RESETB DOWN end =========
3761 00:24:55.669650 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3762 00:24:55.672796 ===================================
3763 00:24:55.672880 LPDDR4 DRAM CONFIGURATION
3764 00:24:55.676030 ===================================
3765 00:24:55.679138 EX_ROW_EN[0] = 0x0
3766 00:24:55.683333 EX_ROW_EN[1] = 0x0
3767 00:24:55.683412 LP4Y_EN = 0x0
3768 00:24:55.686122 WORK_FSP = 0x0
3769 00:24:55.686200 WL = 0x2
3770 00:24:55.689298 RL = 0x2
3771 00:24:55.689373 BL = 0x2
3772 00:24:55.692748 RPST = 0x0
3773 00:24:55.692823 RD_PRE = 0x0
3774 00:24:55.696000 WR_PRE = 0x1
3775 00:24:55.696077 WR_PST = 0x0
3776 00:24:55.699210 DBI_WR = 0x0
3777 00:24:55.699282 DBI_RD = 0x0
3778 00:24:55.702255 OTF = 0x1
3779 00:24:55.705511 ===================================
3780 00:24:55.709389 ===================================
3781 00:24:55.709469 ANA top config
3782 00:24:55.712741 ===================================
3783 00:24:55.716090 DLL_ASYNC_EN = 0
3784 00:24:55.718700 ALL_SLAVE_EN = 1
3785 00:24:55.722185 NEW_RANK_MODE = 1
3786 00:24:55.722269 DLL_IDLE_MODE = 1
3787 00:24:55.725452 LP45_APHY_COMB_EN = 1
3788 00:24:55.728670 TX_ODT_DIS = 1
3789 00:24:55.732183 NEW_8X_MODE = 1
3790 00:24:55.735425 ===================================
3791 00:24:55.738458 ===================================
3792 00:24:55.742533 data_rate = 1200
3793 00:24:55.742644 CKR = 1
3794 00:24:55.745686 DQ_P2S_RATIO = 8
3795 00:24:55.748937 ===================================
3796 00:24:55.751838 CA_P2S_RATIO = 8
3797 00:24:55.755172 DQ_CA_OPEN = 0
3798 00:24:55.758852 DQ_SEMI_OPEN = 0
3799 00:24:55.762520 CA_SEMI_OPEN = 0
3800 00:24:55.762601 CA_FULL_RATE = 0
3801 00:24:55.765037 DQ_CKDIV4_EN = 1
3802 00:24:55.768551 CA_CKDIV4_EN = 1
3803 00:24:55.772269 CA_PREDIV_EN = 0
3804 00:24:55.775277 PH8_DLY = 0
3805 00:24:55.778526 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3806 00:24:55.778607 DQ_AAMCK_DIV = 4
3807 00:24:55.781624 CA_AAMCK_DIV = 4
3808 00:24:55.784787 CA_ADMCK_DIV = 4
3809 00:24:55.788401 DQ_TRACK_CA_EN = 0
3810 00:24:55.792583 CA_PICK = 600
3811 00:24:55.794890 CA_MCKIO = 600
3812 00:24:55.798052 MCKIO_SEMI = 0
3813 00:24:55.801712 PLL_FREQ = 2288
3814 00:24:55.801793 DQ_UI_PI_RATIO = 32
3815 00:24:55.804488 CA_UI_PI_RATIO = 0
3816 00:24:55.808455 ===================================
3817 00:24:55.812390 ===================================
3818 00:24:55.814525 memory_type:LPDDR4
3819 00:24:55.817798 GP_NUM : 10
3820 00:24:55.817875 SRAM_EN : 1
3821 00:24:55.821303 MD32_EN : 0
3822 00:24:55.824944 ===================================
3823 00:24:55.827790 [ANA_INIT] >>>>>>>>>>>>>>
3824 00:24:55.827871 <<<<<< [CONFIGURE PHASE]: ANA_TX
3825 00:24:55.831204 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3826 00:24:55.834483 ===================================
3827 00:24:55.837523 data_rate = 1200,PCW = 0X5800
3828 00:24:55.840864 ===================================
3829 00:24:55.844381 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3830 00:24:55.850919 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3831 00:24:55.857405 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3832 00:24:55.860566 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3833 00:24:55.864625 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3834 00:24:55.867431 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3835 00:24:55.871120 [ANA_INIT] flow start
3836 00:24:55.871205 [ANA_INIT] PLL >>>>>>>>
3837 00:24:55.873809 [ANA_INIT] PLL <<<<<<<<
3838 00:24:55.877504 [ANA_INIT] MIDPI >>>>>>>>
3839 00:24:55.880426 [ANA_INIT] MIDPI <<<<<<<<
3840 00:24:55.880511 [ANA_INIT] DLL >>>>>>>>
3841 00:24:55.883878 [ANA_INIT] flow end
3842 00:24:55.887686 ============ LP4 DIFF to SE enter ============
3843 00:24:55.890716 ============ LP4 DIFF to SE exit ============
3844 00:24:55.893751 [ANA_INIT] <<<<<<<<<<<<<
3845 00:24:55.897422 [Flow] Enable top DCM control >>>>>
3846 00:24:55.900422 [Flow] Enable top DCM control <<<<<
3847 00:24:55.903736 Enable DLL master slave shuffle
3848 00:24:55.910730 ==============================================================
3849 00:24:55.910816 Gating Mode config
3850 00:24:55.917486 ==============================================================
3851 00:24:55.917572 Config description:
3852 00:24:55.926890 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3853 00:24:55.933451 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3854 00:24:55.939885 SELPH_MODE 0: By rank 1: By Phase
3855 00:24:55.943258 ==============================================================
3856 00:24:55.947125 GAT_TRACK_EN = 1
3857 00:24:55.950017 RX_GATING_MODE = 2
3858 00:24:55.953450 RX_GATING_TRACK_MODE = 2
3859 00:24:55.956735 SELPH_MODE = 1
3860 00:24:55.959974 PICG_EARLY_EN = 1
3861 00:24:55.963448 VALID_LAT_VALUE = 1
3862 00:24:55.969926 ==============================================================
3863 00:24:55.972898 Enter into Gating configuration >>>>
3864 00:24:55.976353 Exit from Gating configuration <<<<
3865 00:24:55.979446 Enter into DVFS_PRE_config >>>>>
3866 00:24:55.989652 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3867 00:24:55.992775 Exit from DVFS_PRE_config <<<<<
3868 00:24:55.996234 Enter into PICG configuration >>>>
3869 00:24:55.999240 Exit from PICG configuration <<<<
3870 00:24:56.002659 [RX_INPUT] configuration >>>>>
3871 00:24:56.002744 [RX_INPUT] configuration <<<<<
3872 00:24:56.009475 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3873 00:24:56.015668 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3874 00:24:56.019553 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3875 00:24:56.025772 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3876 00:24:56.032542 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3877 00:24:56.039152 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3878 00:24:56.042488 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3879 00:24:56.045637 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3880 00:24:56.052076 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3881 00:24:56.055479 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3882 00:24:56.058644 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3883 00:24:56.065113 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3884 00:24:56.068710 ===================================
3885 00:24:56.068823 LPDDR4 DRAM CONFIGURATION
3886 00:24:56.072155 ===================================
3887 00:24:56.075019 EX_ROW_EN[0] = 0x0
3888 00:24:56.078374 EX_ROW_EN[1] = 0x0
3889 00:24:56.078453 LP4Y_EN = 0x0
3890 00:24:56.082051 WORK_FSP = 0x0
3891 00:24:56.082127 WL = 0x2
3892 00:24:56.085303 RL = 0x2
3893 00:24:56.085388 BL = 0x2
3894 00:24:56.088157 RPST = 0x0
3895 00:24:56.088239 RD_PRE = 0x0
3896 00:24:56.091874 WR_PRE = 0x1
3897 00:24:56.092019 WR_PST = 0x0
3898 00:24:56.094929 DBI_WR = 0x0
3899 00:24:56.095012 DBI_RD = 0x0
3900 00:24:56.098054 OTF = 0x1
3901 00:24:56.101509 ===================================
3902 00:24:56.104947 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3903 00:24:56.108304 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3904 00:24:56.114750 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3905 00:24:56.118254 ===================================
3906 00:24:56.118338 LPDDR4 DRAM CONFIGURATION
3907 00:24:56.121549 ===================================
3908 00:24:56.124771 EX_ROW_EN[0] = 0x10
3909 00:24:56.127916 EX_ROW_EN[1] = 0x0
3910 00:24:56.128014 LP4Y_EN = 0x0
3911 00:24:56.131235 WORK_FSP = 0x0
3912 00:24:56.131335 WL = 0x2
3913 00:24:56.134546 RL = 0x2
3914 00:24:56.134629 BL = 0x2
3915 00:24:56.137862 RPST = 0x0
3916 00:24:56.137945 RD_PRE = 0x0
3917 00:24:56.141493 WR_PRE = 0x1
3918 00:24:56.141607 WR_PST = 0x0
3919 00:24:56.144594 DBI_WR = 0x0
3920 00:24:56.144707 DBI_RD = 0x0
3921 00:24:56.147732 OTF = 0x1
3922 00:24:56.150819 ===================================
3923 00:24:56.157826 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3924 00:24:56.160866 nWR fixed to 30
3925 00:24:56.164798 [ModeRegInit_LP4] CH0 RK0
3926 00:24:56.164896 [ModeRegInit_LP4] CH0 RK1
3927 00:24:56.167911 [ModeRegInit_LP4] CH1 RK0
3928 00:24:56.170903 [ModeRegInit_LP4] CH1 RK1
3929 00:24:56.170986 match AC timing 17
3930 00:24:56.177210 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3931 00:24:56.180345 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3932 00:24:56.184035 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3933 00:24:56.190117 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3934 00:24:56.193575 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3935 00:24:56.193697 ==
3936 00:24:56.197373 Dram Type= 6, Freq= 0, CH_0, rank 0
3937 00:24:56.200254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3938 00:24:56.200337 ==
3939 00:24:56.207027 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3940 00:24:56.213394 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3941 00:24:56.216616 [CA 0] Center 36 (6~67) winsize 62
3942 00:24:56.219973 [CA 1] Center 36 (5~67) winsize 63
3943 00:24:56.223392 [CA 2] Center 34 (4~65) winsize 62
3944 00:24:56.226874 [CA 3] Center 34 (4~65) winsize 62
3945 00:24:56.229741 [CA 4] Center 33 (3~64) winsize 62
3946 00:24:56.233483 [CA 5] Center 33 (3~64) winsize 62
3947 00:24:56.233564
3948 00:24:56.236497 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3949 00:24:56.236578
3950 00:24:56.239907 [CATrainingPosCal] consider 1 rank data
3951 00:24:56.242901 u2DelayCellTimex100 = 270/100 ps
3952 00:24:56.246228 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3953 00:24:56.249950 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3954 00:24:56.252929 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3955 00:24:56.259738 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3956 00:24:56.262740 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3957 00:24:56.266076 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3958 00:24:56.266155
3959 00:24:56.269344 CA PerBit enable=1, Macro0, CA PI delay=33
3960 00:24:56.269444
3961 00:24:56.273097 [CBTSetCACLKResult] CA Dly = 33
3962 00:24:56.273172 CS Dly: 5 (0~36)
3963 00:24:56.273257 ==
3964 00:24:56.276117 Dram Type= 6, Freq= 0, CH_0, rank 1
3965 00:24:56.282875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 00:24:56.282954 ==
3967 00:24:56.285958 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3968 00:24:56.292340 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3969 00:24:56.296105 [CA 0] Center 36 (6~67) winsize 62
3970 00:24:56.299212 [CA 1] Center 36 (6~67) winsize 62
3971 00:24:56.302477 [CA 2] Center 34 (4~65) winsize 62
3972 00:24:56.305887 [CA 3] Center 34 (4~65) winsize 62
3973 00:24:56.309455 [CA 4] Center 34 (4~64) winsize 61
3974 00:24:56.312873 [CA 5] Center 33 (3~64) winsize 62
3975 00:24:56.312968
3976 00:24:56.315753 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3977 00:24:56.315822
3978 00:24:56.318668 [CATrainingPosCal] consider 2 rank data
3979 00:24:56.322578 u2DelayCellTimex100 = 270/100 ps
3980 00:24:56.325660 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3981 00:24:56.332025 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3982 00:24:56.335508 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3983 00:24:56.339096 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3984 00:24:56.342604 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3985 00:24:56.345216 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3986 00:24:56.345313
3987 00:24:56.348880 CA PerBit enable=1, Macro0, CA PI delay=33
3988 00:24:56.348960
3989 00:24:56.352082 [CBTSetCACLKResult] CA Dly = 33
3990 00:24:56.355355 CS Dly: 5 (0~37)
3991 00:24:56.355452
3992 00:24:56.358701 ----->DramcWriteLeveling(PI) begin...
3993 00:24:56.358784 ==
3994 00:24:56.361728 Dram Type= 6, Freq= 0, CH_0, rank 0
3995 00:24:56.365350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3996 00:24:56.365431 ==
3997 00:24:56.368876 Write leveling (Byte 0): 35 => 35
3998 00:24:56.371665 Write leveling (Byte 1): 28 => 28
3999 00:24:56.374995 DramcWriteLeveling(PI) end<-----
4000 00:24:56.375076
4001 00:24:56.375141 ==
4002 00:24:56.378315 Dram Type= 6, Freq= 0, CH_0, rank 0
4003 00:24:56.382072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 00:24:56.382151 ==
4005 00:24:56.384690 [Gating] SW mode calibration
4006 00:24:56.391169 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4007 00:24:56.397986 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4008 00:24:56.401223 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4009 00:24:56.405114 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4010 00:24:56.411099 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4011 00:24:56.415056 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4012 00:24:56.421241 0 9 16 | B1->B0 | 2d2d 2424 | 0 0 | (0 0) (0 0)
4013 00:24:56.424388 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 00:24:56.428178 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 00:24:56.431600 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 00:24:56.438433 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 00:24:56.440986 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 00:24:56.444818 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 00:24:56.450890 0 10 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
4020 00:24:56.454158 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4021 00:24:56.460626 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 00:24:56.463880 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 00:24:56.467222 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 00:24:56.474155 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 00:24:56.477051 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 00:24:56.480581 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 00:24:56.487645 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 00:24:56.490015 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 00:24:56.493623 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4030 00:24:56.500388 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 00:24:56.503575 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 00:24:56.507032 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 00:24:56.513179 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 00:24:56.516560 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 00:24:56.519586 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 00:24:56.526813 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 00:24:56.529582 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 00:24:56.533100 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 00:24:56.539468 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 00:24:56.542755 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 00:24:56.546379 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 00:24:56.552693 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 00:24:56.555986 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 00:24:56.559003 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4045 00:24:56.562511 Total UI for P1: 0, mck2ui 16
4046 00:24:56.565654 best dqsien dly found for B0: ( 0, 13, 14)
4047 00:24:56.572366 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 00:24:56.572447 Total UI for P1: 0, mck2ui 16
4049 00:24:56.579162 best dqsien dly found for B1: ( 0, 13, 16)
4050 00:24:56.582343 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4051 00:24:56.585546 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4052 00:24:56.585627
4053 00:24:56.588704 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4054 00:24:56.592053 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4055 00:24:56.595214 [Gating] SW calibration Done
4056 00:24:56.595294 ==
4057 00:24:56.598590 Dram Type= 6, Freq= 0, CH_0, rank 0
4058 00:24:56.601892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4059 00:24:56.601974 ==
4060 00:24:56.605204 RX Vref Scan: 0
4061 00:24:56.605285
4062 00:24:56.605349 RX Vref 0 -> 0, step: 1
4063 00:24:56.605410
4064 00:24:56.608797 RX Delay -230 -> 252, step: 16
4065 00:24:56.615353 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4066 00:24:56.619079 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4067 00:24:56.622090 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4068 00:24:56.624928 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4069 00:24:56.628796 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4070 00:24:56.635113 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4071 00:24:56.638168 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4072 00:24:56.641791 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4073 00:24:56.645528 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4074 00:24:56.651654 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4075 00:24:56.655015 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4076 00:24:56.658215 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4077 00:24:56.661962 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4078 00:24:56.667929 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4079 00:24:56.671147 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4080 00:24:56.674533 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4081 00:24:56.674611 ==
4082 00:24:56.677886 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 00:24:56.681121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 00:24:56.684199 ==
4085 00:24:56.684274 DQS Delay:
4086 00:24:56.684357 DQS0 = 0, DQS1 = 0
4087 00:24:56.688155 DQM Delay:
4088 00:24:56.688237 DQM0 = 47, DQM1 = 35
4089 00:24:56.690954 DQ Delay:
4090 00:24:56.694367 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4091 00:24:56.697707 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4092 00:24:56.697788 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =33
4093 00:24:56.704353 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4094 00:24:56.704434
4095 00:24:56.704499
4096 00:24:56.704559 ==
4097 00:24:56.707538 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 00:24:56.710594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 00:24:56.710676 ==
4100 00:24:56.710740
4101 00:24:56.710799
4102 00:24:56.715076 TX Vref Scan disable
4103 00:24:56.715157 == TX Byte 0 ==
4104 00:24:56.720432 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4105 00:24:56.724152 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4106 00:24:56.727394 == TX Byte 1 ==
4107 00:24:56.730806 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4108 00:24:56.734246 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4109 00:24:56.734328 ==
4110 00:24:56.737075 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 00:24:56.740503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 00:24:56.744026 ==
4113 00:24:56.744107
4114 00:24:56.744170
4115 00:24:56.744231 TX Vref Scan disable
4116 00:24:56.747766 == TX Byte 0 ==
4117 00:24:56.751679 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4118 00:24:56.757710 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4119 00:24:56.757795 == TX Byte 1 ==
4120 00:24:56.761288 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4121 00:24:56.767518 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4122 00:24:56.767623
4123 00:24:56.767722 [DATLAT]
4124 00:24:56.767822 Freq=600, CH0 RK0
4125 00:24:56.767970
4126 00:24:56.770849 DATLAT Default: 0x9
4127 00:24:56.770948 0, 0xFFFF, sum = 0
4128 00:24:56.774382 1, 0xFFFF, sum = 0
4129 00:24:56.777188 2, 0xFFFF, sum = 0
4130 00:24:56.777273 3, 0xFFFF, sum = 0
4131 00:24:56.781076 4, 0xFFFF, sum = 0
4132 00:24:56.781161 5, 0xFFFF, sum = 0
4133 00:24:56.783734 6, 0xFFFF, sum = 0
4134 00:24:56.783843 7, 0xFFFF, sum = 0
4135 00:24:56.787353 8, 0x0, sum = 1
4136 00:24:56.787436 9, 0x0, sum = 2
4137 00:24:56.790617 10, 0x0, sum = 3
4138 00:24:56.790699 11, 0x0, sum = 4
4139 00:24:56.790783 best_step = 9
4140 00:24:56.790858
4141 00:24:56.793970 ==
4142 00:24:56.797213 Dram Type= 6, Freq= 0, CH_0, rank 0
4143 00:24:56.800285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 00:24:56.800367 ==
4145 00:24:56.800432 RX Vref Scan: 1
4146 00:24:56.800492
4147 00:24:56.803835 RX Vref 0 -> 0, step: 1
4148 00:24:56.803941
4149 00:24:56.807021 RX Delay -195 -> 252, step: 8
4150 00:24:56.807101
4151 00:24:56.810698 Set Vref, RX VrefLevel [Byte0]: 52
4152 00:24:56.814023 [Byte1]: 49
4153 00:24:56.814115
4154 00:24:56.817076 Final RX Vref Byte 0 = 52 to rank0
4155 00:24:56.819983 Final RX Vref Byte 1 = 49 to rank0
4156 00:24:56.823175 Final RX Vref Byte 0 = 52 to rank1
4157 00:24:56.826952 Final RX Vref Byte 1 = 49 to rank1==
4158 00:24:56.830167 Dram Type= 6, Freq= 0, CH_0, rank 0
4159 00:24:56.833265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 00:24:56.836626 ==
4161 00:24:56.836707 DQS Delay:
4162 00:24:56.836772 DQS0 = 0, DQS1 = 0
4163 00:24:56.840231 DQM Delay:
4164 00:24:56.840313 DQM0 = 41, DQM1 = 34
4165 00:24:56.843177 DQ Delay:
4166 00:24:56.847000 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4167 00:24:56.847097 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4168 00:24:56.849663 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4169 00:24:56.856851 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4170 00:24:56.856941
4171 00:24:56.857017
4172 00:24:56.862814 [DQSOSCAuto] RK0, (LSB)MR18= 0x5249, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
4173 00:24:56.866158 CH0 RK0: MR19=808, MR18=5249
4174 00:24:56.873535 CH0_RK0: MR19=0x808, MR18=0x5249, DQSOSC=394, MR23=63, INC=168, DEC=112
4175 00:24:56.873650
4176 00:24:56.876322 ----->DramcWriteLeveling(PI) begin...
4177 00:24:56.876405 ==
4178 00:24:56.879454 Dram Type= 6, Freq= 0, CH_0, rank 1
4179 00:24:56.883016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 00:24:56.883098 ==
4181 00:24:56.886062 Write leveling (Byte 0): 33 => 33
4182 00:24:56.889412 Write leveling (Byte 1): 29 => 29
4183 00:24:56.892672 DramcWriteLeveling(PI) end<-----
4184 00:24:56.892753
4185 00:24:56.892818 ==
4186 00:24:56.895766 Dram Type= 6, Freq= 0, CH_0, rank 1
4187 00:24:56.899383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 00:24:56.899466 ==
4189 00:24:56.902529 [Gating] SW mode calibration
4190 00:24:56.909050 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4191 00:24:56.916393 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4192 00:24:56.919149 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4193 00:24:56.925496 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4194 00:24:56.928775 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4195 00:24:56.931880 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (0 1) (0 1)
4196 00:24:56.939139 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
4197 00:24:56.942044 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 00:24:56.945315 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 00:24:56.951736 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 00:24:56.954961 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 00:24:56.958713 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 00:24:56.965017 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 00:24:56.968570 0 10 12 | B1->B0 | 2929 3535 | 0 0 | (0 0) (0 0)
4204 00:24:56.971441 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4205 00:24:56.978183 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 00:24:56.982292 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 00:24:56.985024 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 00:24:56.991374 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 00:24:56.994562 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 00:24:56.997974 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 00:24:57.004316 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4212 00:24:57.007832 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 00:24:57.011248 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 00:24:57.017663 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 00:24:57.021020 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 00:24:57.024718 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 00:24:57.031169 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 00:24:57.034286 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 00:24:57.037471 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 00:24:57.044445 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 00:24:57.047749 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 00:24:57.050578 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 00:24:57.057734 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 00:24:57.061072 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 00:24:57.063622 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 00:24:57.070136 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 00:24:57.073498 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4228 00:24:57.076954 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4229 00:24:57.081009 Total UI for P1: 0, mck2ui 16
4230 00:24:57.083564 best dqsien dly found for B0: ( 0, 13, 12)
4231 00:24:57.090048 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 00:24:57.090132 Total UI for P1: 0, mck2ui 16
4233 00:24:57.096950 best dqsien dly found for B1: ( 0, 13, 16)
4234 00:24:57.100040 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4235 00:24:57.103828 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4236 00:24:57.103948
4237 00:24:57.107388 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4238 00:24:57.109829 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4239 00:24:57.113131 [Gating] SW calibration Done
4240 00:24:57.113207 ==
4241 00:24:57.116433 Dram Type= 6, Freq= 0, CH_0, rank 1
4242 00:24:57.119913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 00:24:57.120002 ==
4244 00:24:57.123401 RX Vref Scan: 0
4245 00:24:57.123475
4246 00:24:57.123553 RX Vref 0 -> 0, step: 1
4247 00:24:57.126892
4248 00:24:57.126965 RX Delay -230 -> 252, step: 16
4249 00:24:57.133730 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4250 00:24:57.136195 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4251 00:24:57.140221 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4252 00:24:57.142986 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4253 00:24:57.149939 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4254 00:24:57.153058 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4255 00:24:57.156165 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4256 00:24:57.159325 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4257 00:24:57.163154 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4258 00:24:57.169177 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4259 00:24:57.172829 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4260 00:24:57.176334 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4261 00:24:57.179092 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4262 00:24:57.185780 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4263 00:24:57.189161 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4264 00:24:57.192660 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4265 00:24:57.192740 ==
4266 00:24:57.196053 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 00:24:57.202455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 00:24:57.202535 ==
4269 00:24:57.202619 DQS Delay:
4270 00:24:57.202700 DQS0 = 0, DQS1 = 0
4271 00:24:57.205482 DQM Delay:
4272 00:24:57.205579 DQM0 = 40, DQM1 = 32
4273 00:24:57.209269 DQ Delay:
4274 00:24:57.212749 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4275 00:24:57.215515 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4276 00:24:57.218845 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4277 00:24:57.222174 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =33
4278 00:24:57.222251
4279 00:24:57.222329
4280 00:24:57.222404 ==
4281 00:24:57.225704 Dram Type= 6, Freq= 0, CH_0, rank 1
4282 00:24:57.228638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 00:24:57.228714 ==
4284 00:24:57.228797
4285 00:24:57.228873
4286 00:24:57.232343 TX Vref Scan disable
4287 00:24:57.235218 == TX Byte 0 ==
4288 00:24:57.239174 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4289 00:24:57.242019 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4290 00:24:57.244987 == TX Byte 1 ==
4291 00:24:57.248342 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4292 00:24:57.251719 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4293 00:24:57.251798 ==
4294 00:24:57.255172 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 00:24:57.258558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 00:24:57.261770 ==
4297 00:24:57.261844
4298 00:24:57.261923
4299 00:24:57.262001 TX Vref Scan disable
4300 00:24:57.266040 == TX Byte 0 ==
4301 00:24:57.269139 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4302 00:24:57.275857 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4303 00:24:57.275943 == TX Byte 1 ==
4304 00:24:57.278602 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4305 00:24:57.285510 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4306 00:24:57.285592
4307 00:24:57.285657 [DATLAT]
4308 00:24:57.285718 Freq=600, CH0 RK1
4309 00:24:57.285777
4310 00:24:57.288581 DATLAT Default: 0x9
4311 00:24:57.292186 0, 0xFFFF, sum = 0
4312 00:24:57.292269 1, 0xFFFF, sum = 0
4313 00:24:57.295327 2, 0xFFFF, sum = 0
4314 00:24:57.295424 3, 0xFFFF, sum = 0
4315 00:24:57.298916 4, 0xFFFF, sum = 0
4316 00:24:57.298998 5, 0xFFFF, sum = 0
4317 00:24:57.302406 6, 0xFFFF, sum = 0
4318 00:24:57.302489 7, 0xFFFF, sum = 0
4319 00:24:57.305025 8, 0x0, sum = 1
4320 00:24:57.305108 9, 0x0, sum = 2
4321 00:24:57.308693 10, 0x0, sum = 3
4322 00:24:57.308775 11, 0x0, sum = 4
4323 00:24:57.308874 best_step = 9
4324 00:24:57.308935
4325 00:24:57.312299 ==
4326 00:24:57.315095 Dram Type= 6, Freq= 0, CH_0, rank 1
4327 00:24:57.318296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4328 00:24:57.318393 ==
4329 00:24:57.318458 RX Vref Scan: 0
4330 00:24:57.318519
4331 00:24:57.321420 RX Vref 0 -> 0, step: 1
4332 00:24:57.321524
4333 00:24:57.325003 RX Delay -195 -> 252, step: 8
4334 00:24:57.331732 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4335 00:24:57.334474 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4336 00:24:57.338127 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4337 00:24:57.341270 iDelay=197, Bit 3, Center 36 (-115 ~ 188) 304
4338 00:24:57.348112 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4339 00:24:57.350901 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4340 00:24:57.354283 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4341 00:24:57.357781 iDelay=197, Bit 7, Center 48 (-99 ~ 196) 296
4342 00:24:57.361488 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4343 00:24:57.368091 iDelay=197, Bit 9, Center 20 (-139 ~ 180) 320
4344 00:24:57.370908 iDelay=197, Bit 10, Center 36 (-115 ~ 188) 304
4345 00:24:57.374470 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4346 00:24:57.377715 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4347 00:24:57.384659 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4348 00:24:57.387454 iDelay=197, Bit 14, Center 44 (-107 ~ 196) 304
4349 00:24:57.390986 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4350 00:24:57.391080 ==
4351 00:24:57.394265 Dram Type= 6, Freq= 0, CH_0, rank 1
4352 00:24:57.397340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4353 00:24:57.400683 ==
4354 00:24:57.400754 DQS Delay:
4355 00:24:57.400815 DQS0 = 0, DQS1 = 0
4356 00:24:57.404583 DQM Delay:
4357 00:24:57.404653 DQM0 = 40, DQM1 = 34
4358 00:24:57.407323 DQ Delay:
4359 00:24:57.407399 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4360 00:24:57.410597 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48
4361 00:24:57.414083 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4362 00:24:57.417378 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4363 00:24:57.420429
4364 00:24:57.420517
4365 00:24:57.427006 [DQSOSCAuto] RK1, (LSB)MR18= 0x413d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4366 00:24:57.430458 CH0 RK1: MR19=808, MR18=413D
4367 00:24:57.436981 CH0_RK1: MR19=0x808, MR18=0x413D, DQSOSC=397, MR23=63, INC=166, DEC=110
4368 00:24:57.440637 [RxdqsGatingPostProcess] freq 600
4369 00:24:57.444173 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4370 00:24:57.446929 Pre-setting of DQS Precalculation
4371 00:24:57.453589 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4372 00:24:57.453671 ==
4373 00:24:57.457388 Dram Type= 6, Freq= 0, CH_1, rank 0
4374 00:24:57.460926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4375 00:24:57.461007 ==
4376 00:24:57.467037 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4377 00:24:57.469858 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4378 00:24:57.474939 [CA 0] Center 35 (5~66) winsize 62
4379 00:24:57.477993 [CA 1] Center 35 (5~66) winsize 62
4380 00:24:57.481002 [CA 2] Center 34 (4~65) winsize 62
4381 00:24:57.484429 [CA 3] Center 34 (3~65) winsize 63
4382 00:24:57.488085 [CA 4] Center 34 (4~65) winsize 62
4383 00:24:57.491176 [CA 5] Center 34 (3~65) winsize 63
4384 00:24:57.491274
4385 00:24:57.493995 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4386 00:24:57.494075
4387 00:24:57.497668 [CATrainingPosCal] consider 1 rank data
4388 00:24:57.500776 u2DelayCellTimex100 = 270/100 ps
4389 00:24:57.504217 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4390 00:24:57.510555 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4391 00:24:57.514214 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4392 00:24:57.517141 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4393 00:24:57.520790 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4394 00:24:57.523869 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4395 00:24:57.523973
4396 00:24:57.527433 CA PerBit enable=1, Macro0, CA PI delay=34
4397 00:24:57.527514
4398 00:24:57.530394 [CBTSetCACLKResult] CA Dly = 34
4399 00:24:57.533483 CS Dly: 4 (0~35)
4400 00:24:57.533578 ==
4401 00:24:57.536949 Dram Type= 6, Freq= 0, CH_1, rank 1
4402 00:24:57.540264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 00:24:57.540336 ==
4404 00:24:57.546694 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4405 00:24:57.550002 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4406 00:24:57.554378 [CA 0] Center 36 (6~66) winsize 61
4407 00:24:57.557822 [CA 1] Center 35 (5~66) winsize 62
4408 00:24:57.560949 [CA 2] Center 34 (4~65) winsize 62
4409 00:24:57.564585 [CA 3] Center 33 (3~64) winsize 62
4410 00:24:57.567387 [CA 4] Center 34 (4~65) winsize 62
4411 00:24:57.570744 [CA 5] Center 33 (3~64) winsize 62
4412 00:24:57.570839
4413 00:24:57.574321 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4414 00:24:57.574417
4415 00:24:57.578105 [CATrainingPosCal] consider 2 rank data
4416 00:24:57.581112 u2DelayCellTimex100 = 270/100 ps
4417 00:24:57.584763 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4418 00:24:57.590552 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4419 00:24:57.593827 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4420 00:24:57.597210 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4421 00:24:57.601132 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4422 00:24:57.603868 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4423 00:24:57.603976
4424 00:24:57.607092 CA PerBit enable=1, Macro0, CA PI delay=33
4425 00:24:57.607187
4426 00:24:57.610442 [CBTSetCACLKResult] CA Dly = 33
4427 00:24:57.613555 CS Dly: 4 (0~35)
4428 00:24:57.613665
4429 00:24:57.616884 ----->DramcWriteLeveling(PI) begin...
4430 00:24:57.616965 ==
4431 00:24:57.620528 Dram Type= 6, Freq= 0, CH_1, rank 0
4432 00:24:57.623374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4433 00:24:57.623459 ==
4434 00:24:57.626773 Write leveling (Byte 0): 27 => 27
4435 00:24:57.630631 Write leveling (Byte 1): 28 => 28
4436 00:24:57.633607 DramcWriteLeveling(PI) end<-----
4437 00:24:57.633689
4438 00:24:57.633753 ==
4439 00:24:57.636696 Dram Type= 6, Freq= 0, CH_1, rank 0
4440 00:24:57.639891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4441 00:24:57.639995 ==
4442 00:24:57.643325 [Gating] SW mode calibration
4443 00:24:57.650022 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4444 00:24:57.656361 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4445 00:24:57.660001 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4446 00:24:57.663427 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4447 00:24:57.669867 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4448 00:24:57.672840 0 9 12 | B1->B0 | 3131 2d2d | 0 0 | (0 1) (1 0)
4449 00:24:57.676036 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 00:24:57.682883 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 00:24:57.685963 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 00:24:57.690053 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 00:24:57.696311 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 00:24:57.699244 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 00:24:57.703073 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 00:24:57.708812 0 10 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (0 0)
4457 00:24:57.712301 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 00:24:57.719019 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 00:24:57.722346 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 00:24:57.725922 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 00:24:57.732120 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 00:24:57.735291 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 00:24:57.738729 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 00:24:57.745134 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4465 00:24:57.748176 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 00:24:57.751829 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 00:24:57.759115 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 00:24:57.761832 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 00:24:57.765268 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 00:24:57.771524 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 00:24:57.774689 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 00:24:57.777849 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 00:24:57.784587 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 00:24:57.787912 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 00:24:57.791242 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 00:24:57.797776 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 00:24:57.801477 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 00:24:57.804279 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 00:24:57.810692 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4480 00:24:57.813861 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4481 00:24:57.817349 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4482 00:24:57.820849 Total UI for P1: 0, mck2ui 16
4483 00:24:57.824292 best dqsien dly found for B0: ( 0, 13, 10)
4484 00:24:57.831204 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 00:24:57.831304 Total UI for P1: 0, mck2ui 16
4486 00:24:57.837827 best dqsien dly found for B1: ( 0, 13, 16)
4487 00:24:57.840536 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4488 00:24:57.843846 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4489 00:24:57.843964
4490 00:24:57.847347 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4491 00:24:57.850330 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4492 00:24:57.854225 [Gating] SW calibration Done
4493 00:24:57.854326 ==
4494 00:24:57.857654 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 00:24:57.860737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 00:24:57.860849 ==
4497 00:24:57.863894 RX Vref Scan: 0
4498 00:24:57.864048
4499 00:24:57.864138 RX Vref 0 -> 0, step: 1
4500 00:24:57.864240
4501 00:24:57.866734 RX Delay -230 -> 252, step: 16
4502 00:24:57.873283 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4503 00:24:57.876671 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4504 00:24:57.880483 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4505 00:24:57.883683 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4506 00:24:57.889487 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4507 00:24:57.892918 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4508 00:24:57.896625 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4509 00:24:57.899474 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4510 00:24:57.902824 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4511 00:24:57.909575 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4512 00:24:57.912855 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4513 00:24:57.916351 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4514 00:24:57.919783 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4515 00:24:57.926235 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4516 00:24:57.930368 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4517 00:24:57.932953 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4518 00:24:57.933054 ==
4519 00:24:57.935998 Dram Type= 6, Freq= 0, CH_1, rank 0
4520 00:24:57.939747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4521 00:24:57.943080 ==
4522 00:24:57.943183 DQS Delay:
4523 00:24:57.943280 DQS0 = 0, DQS1 = 0
4524 00:24:57.946446 DQM Delay:
4525 00:24:57.946545 DQM0 = 46, DQM1 = 41
4526 00:24:57.949405 DQ Delay:
4527 00:24:57.952600 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4528 00:24:57.952698 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4529 00:24:57.956155 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4530 00:24:57.962827 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =49
4531 00:24:57.962931
4532 00:24:57.963024
4533 00:24:57.963115 ==
4534 00:24:57.965810 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 00:24:57.969432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 00:24:57.969516 ==
4537 00:24:57.969607
4538 00:24:57.969695
4539 00:24:57.972382 TX Vref Scan disable
4540 00:24:57.972453 == TX Byte 0 ==
4541 00:24:57.978897 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4542 00:24:57.982240 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4543 00:24:57.982320 == TX Byte 1 ==
4544 00:24:57.988538 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4545 00:24:57.992403 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4546 00:24:57.992510 ==
4547 00:24:57.995372 Dram Type= 6, Freq= 0, CH_1, rank 0
4548 00:24:57.999243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4549 00:24:58.001837 ==
4550 00:24:58.001943
4551 00:24:58.002035
4552 00:24:58.002126 TX Vref Scan disable
4553 00:24:58.005488 == TX Byte 0 ==
4554 00:24:58.008870 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4555 00:24:58.015459 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4556 00:24:58.015567 == TX Byte 1 ==
4557 00:24:58.018842 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4558 00:24:58.025399 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4559 00:24:58.025512
4560 00:24:58.025602 [DATLAT]
4561 00:24:58.025699 Freq=600, CH1 RK0
4562 00:24:58.025785
4563 00:24:58.029236 DATLAT Default: 0x9
4564 00:24:58.029325 0, 0xFFFF, sum = 0
4565 00:24:58.032090 1, 0xFFFF, sum = 0
4566 00:24:58.035868 2, 0xFFFF, sum = 0
4567 00:24:58.036003 3, 0xFFFF, sum = 0
4568 00:24:58.039027 4, 0xFFFF, sum = 0
4569 00:24:58.039124 5, 0xFFFF, sum = 0
4570 00:24:58.042210 6, 0xFFFF, sum = 0
4571 00:24:58.042308 7, 0xFFFF, sum = 0
4572 00:24:58.045206 8, 0x0, sum = 1
4573 00:24:58.045318 9, 0x0, sum = 2
4574 00:24:58.048557 10, 0x0, sum = 3
4575 00:24:58.048679 11, 0x0, sum = 4
4576 00:24:58.048790 best_step = 9
4577 00:24:58.048878
4578 00:24:58.051620 ==
4579 00:24:58.055361 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 00:24:58.058265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 00:24:58.058345 ==
4582 00:24:58.058409 RX Vref Scan: 1
4583 00:24:58.058469
4584 00:24:58.061898 RX Vref 0 -> 0, step: 1
4585 00:24:58.061978
4586 00:24:58.064952 RX Delay -179 -> 252, step: 8
4587 00:24:58.065032
4588 00:24:58.068661 Set Vref, RX VrefLevel [Byte0]: 53
4589 00:24:58.071563 [Byte1]: 51
4590 00:24:58.071657
4591 00:24:58.074820 Final RX Vref Byte 0 = 53 to rank0
4592 00:24:58.078033 Final RX Vref Byte 1 = 51 to rank0
4593 00:24:58.081289 Final RX Vref Byte 0 = 53 to rank1
4594 00:24:58.084407 Final RX Vref Byte 1 = 51 to rank1==
4595 00:24:58.088390 Dram Type= 6, Freq= 0, CH_1, rank 0
4596 00:24:58.091147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 00:24:58.094562 ==
4598 00:24:58.094667 DQS Delay:
4599 00:24:58.094798 DQS0 = 0, DQS1 = 0
4600 00:24:58.097756 DQM Delay:
4601 00:24:58.097865 DQM0 = 41, DQM1 = 33
4602 00:24:58.100870 DQ Delay:
4603 00:24:58.104392 DQ0 =48, DQ1 =40, DQ2 =28, DQ3 =40
4604 00:24:58.104463 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4605 00:24:58.107614 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =28
4606 00:24:58.114391 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4607 00:24:58.114491
4608 00:24:58.114589
4609 00:24:58.121070 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c47, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4610 00:24:58.123990 CH1 RK0: MR19=808, MR18=2C47
4611 00:24:58.130611 CH1_RK0: MR19=0x808, MR18=0x2C47, DQSOSC=396, MR23=63, INC=167, DEC=111
4612 00:24:58.130727
4613 00:24:58.134017 ----->DramcWriteLeveling(PI) begin...
4614 00:24:58.134132 ==
4615 00:24:58.137329 Dram Type= 6, Freq= 0, CH_1, rank 1
4616 00:24:58.140466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 00:24:58.140581 ==
4618 00:24:58.144484 Write leveling (Byte 0): 29 => 29
4619 00:24:58.147413 Write leveling (Byte 1): 28 => 28
4620 00:24:58.150670 DramcWriteLeveling(PI) end<-----
4621 00:24:58.150791
4622 00:24:58.150880 ==
4623 00:24:58.153723 Dram Type= 6, Freq= 0, CH_1, rank 1
4624 00:24:58.157004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4625 00:24:58.157104 ==
4626 00:24:58.160486 [Gating] SW mode calibration
4627 00:24:58.166953 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4628 00:24:58.173718 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4629 00:24:58.177218 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4630 00:24:58.183679 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4631 00:24:58.187181 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4632 00:24:58.190829 0 9 12 | B1->B0 | 2f2f 2828 | 0 0 | (0 0) (0 0)
4633 00:24:58.197015 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 00:24:58.200284 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4635 00:24:58.203695 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 00:24:58.210039 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4637 00:24:58.213310 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4638 00:24:58.216429 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 00:24:58.223270 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4640 00:24:58.226722 0 10 12 | B1->B0 | 3030 3a3a | 0 0 | (0 0) (1 1)
4641 00:24:58.229610 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 00:24:58.236470 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 00:24:58.239534 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 00:24:58.242957 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 00:24:58.249951 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 00:24:58.252599 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 00:24:58.256097 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 00:24:58.262877 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4649 00:24:58.266269 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 00:24:58.269338 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 00:24:58.275727 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 00:24:58.279403 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 00:24:58.282394 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 00:24:58.288968 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 00:24:58.292961 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 00:24:58.295709 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 00:24:58.302390 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 00:24:58.305931 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 00:24:58.308680 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 00:24:58.315761 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 00:24:58.318871 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 00:24:58.322368 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 00:24:58.328741 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 00:24:58.332040 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4665 00:24:58.335171 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 00:24:58.338680 Total UI for P1: 0, mck2ui 16
4667 00:24:58.342023 best dqsien dly found for B0: ( 0, 13, 12)
4668 00:24:58.345086 Total UI for P1: 0, mck2ui 16
4669 00:24:58.348753 best dqsien dly found for B1: ( 0, 13, 12)
4670 00:24:58.351773 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4671 00:24:58.355053 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4672 00:24:58.355151
4673 00:24:58.361636 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4674 00:24:58.365105 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4675 00:24:58.365184 [Gating] SW calibration Done
4676 00:24:58.368196 ==
4677 00:24:58.371913 Dram Type= 6, Freq= 0, CH_1, rank 1
4678 00:24:58.375314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4679 00:24:58.375384 ==
4680 00:24:58.375445 RX Vref Scan: 0
4681 00:24:58.375517
4682 00:24:58.378240 RX Vref 0 -> 0, step: 1
4683 00:24:58.378333
4684 00:24:58.381920 RX Delay -230 -> 252, step: 16
4685 00:24:58.385165 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4686 00:24:58.387900 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4687 00:24:58.394543 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4688 00:24:58.397918 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4689 00:24:58.401451 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4690 00:24:58.404381 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4691 00:24:58.411285 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4692 00:24:58.414385 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4693 00:24:58.417706 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4694 00:24:58.421259 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4695 00:24:58.427737 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4696 00:24:58.430801 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4697 00:24:58.434482 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4698 00:24:58.437567 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4699 00:24:58.444376 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4700 00:24:58.447283 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4701 00:24:58.447360 ==
4702 00:24:58.450516 Dram Type= 6, Freq= 0, CH_1, rank 1
4703 00:24:58.453814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4704 00:24:58.453901 ==
4705 00:24:58.457018 DQS Delay:
4706 00:24:58.457105 DQS0 = 0, DQS1 = 0
4707 00:24:58.457168 DQM Delay:
4708 00:24:58.460423 DQM0 = 42, DQM1 = 39
4709 00:24:58.460512 DQ Delay:
4710 00:24:58.463661 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4711 00:24:58.466985 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4712 00:24:58.470529 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4713 00:24:58.473500 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4714 00:24:58.473595
4715 00:24:58.473683
4716 00:24:58.473779 ==
4717 00:24:58.476936 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 00:24:58.483330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 00:24:58.483437 ==
4720 00:24:58.483537
4721 00:24:58.483642
4722 00:24:58.483812 TX Vref Scan disable
4723 00:24:58.487545 == TX Byte 0 ==
4724 00:24:58.490734 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4725 00:24:58.497192 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4726 00:24:58.497295 == TX Byte 1 ==
4727 00:24:58.500844 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4728 00:24:58.506965 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4729 00:24:58.507068 ==
4730 00:24:58.510058 Dram Type= 6, Freq= 0, CH_1, rank 1
4731 00:24:58.513766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4732 00:24:58.513868 ==
4733 00:24:58.513958
4734 00:24:58.514043
4735 00:24:58.516881 TX Vref Scan disable
4736 00:24:58.521000 == TX Byte 0 ==
4737 00:24:58.523701 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4738 00:24:58.526420 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4739 00:24:58.529921 == TX Byte 1 ==
4740 00:24:58.533669 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4741 00:24:58.536575 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4742 00:24:58.536678
4743 00:24:58.540196 [DATLAT]
4744 00:24:58.540299 Freq=600, CH1 RK1
4745 00:24:58.540390
4746 00:24:58.543051 DATLAT Default: 0x9
4747 00:24:58.543166 0, 0xFFFF, sum = 0
4748 00:24:58.547081 1, 0xFFFF, sum = 0
4749 00:24:58.547195 2, 0xFFFF, sum = 0
4750 00:24:58.550310 3, 0xFFFF, sum = 0
4751 00:24:58.550412 4, 0xFFFF, sum = 0
4752 00:24:58.553012 5, 0xFFFF, sum = 0
4753 00:24:58.553108 6, 0xFFFF, sum = 0
4754 00:24:58.556849 7, 0xFFFF, sum = 0
4755 00:24:58.556944 8, 0x0, sum = 1
4756 00:24:58.559912 9, 0x0, sum = 2
4757 00:24:58.560025 10, 0x0, sum = 3
4758 00:24:58.563033 11, 0x0, sum = 4
4759 00:24:58.563138 best_step = 9
4760 00:24:58.563226
4761 00:24:58.563311 ==
4762 00:24:58.566525 Dram Type= 6, Freq= 0, CH_1, rank 1
4763 00:24:58.569387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4764 00:24:58.574085 ==
4765 00:24:58.574180 RX Vref Scan: 0
4766 00:24:58.574315
4767 00:24:58.576586 RX Vref 0 -> 0, step: 1
4768 00:24:58.576655
4769 00:24:58.579739 RX Delay -179 -> 252, step: 8
4770 00:24:58.582655 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4771 00:24:58.586710 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4772 00:24:58.592847 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4773 00:24:58.596047 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4774 00:24:58.599386 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4775 00:24:58.602596 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4776 00:24:58.609815 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4777 00:24:58.612435 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4778 00:24:58.616167 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4779 00:24:58.619469 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4780 00:24:58.622687 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4781 00:24:58.628960 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4782 00:24:58.632417 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4783 00:24:58.635768 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4784 00:24:58.639027 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4785 00:24:58.645703 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4786 00:24:58.645779 ==
4787 00:24:58.648901 Dram Type= 6, Freq= 0, CH_1, rank 1
4788 00:24:58.652507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4789 00:24:58.652624 ==
4790 00:24:58.652687 DQS Delay:
4791 00:24:58.655562 DQS0 = 0, DQS1 = 0
4792 00:24:58.655671 DQM Delay:
4793 00:24:58.658603 DQM0 = 38, DQM1 = 35
4794 00:24:58.658711 DQ Delay:
4795 00:24:58.662518 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4796 00:24:58.665333 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4797 00:24:58.668992 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4798 00:24:58.672209 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4799 00:24:58.672306
4800 00:24:58.672393
4801 00:24:58.681912 [DQSOSCAuto] RK1, (LSB)MR18= 0x385d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4802 00:24:58.682022 CH1 RK1: MR19=808, MR18=385D
4803 00:24:58.688610 CH1_RK1: MR19=0x808, MR18=0x385D, DQSOSC=392, MR23=63, INC=170, DEC=113
4804 00:24:58.692094 [RxdqsGatingPostProcess] freq 600
4805 00:24:58.698235 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4806 00:24:58.702032 Pre-setting of DQS Precalculation
4807 00:24:58.704979 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4808 00:24:58.711753 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4809 00:24:58.721534 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4810 00:24:58.721615
4811 00:24:58.721678
4812 00:24:58.724844 [Calibration Summary] 1200 Mbps
4813 00:24:58.724924 CH 0, Rank 0
4814 00:24:58.728121 SW Impedance : PASS
4815 00:24:58.728202 DUTY Scan : NO K
4816 00:24:58.731603 ZQ Calibration : PASS
4817 00:24:58.734445 Jitter Meter : NO K
4818 00:24:58.734568 CBT Training : PASS
4819 00:24:58.738542 Write leveling : PASS
4820 00:24:58.741446 RX DQS gating : PASS
4821 00:24:58.741572 RX DQ/DQS(RDDQC) : PASS
4822 00:24:58.744481 TX DQ/DQS : PASS
4823 00:24:58.747720 RX DATLAT : PASS
4824 00:24:58.747816 RX DQ/DQS(Engine): PASS
4825 00:24:58.751339 TX OE : NO K
4826 00:24:58.751436 All Pass.
4827 00:24:58.751526
4828 00:24:58.754293 CH 0, Rank 1
4829 00:24:58.754385 SW Impedance : PASS
4830 00:24:58.758550 DUTY Scan : NO K
4831 00:24:58.761234 ZQ Calibration : PASS
4832 00:24:58.761329 Jitter Meter : NO K
4833 00:24:58.764221 CBT Training : PASS
4834 00:24:58.764319 Write leveling : PASS
4835 00:24:58.767893 RX DQS gating : PASS
4836 00:24:58.771167 RX DQ/DQS(RDDQC) : PASS
4837 00:24:58.771276 TX DQ/DQS : PASS
4838 00:24:58.774120 RX DATLAT : PASS
4839 00:24:58.777554 RX DQ/DQS(Engine): PASS
4840 00:24:58.777662 TX OE : NO K
4841 00:24:58.780926 All Pass.
4842 00:24:58.781032
4843 00:24:58.781140 CH 1, Rank 0
4844 00:24:58.784262 SW Impedance : PASS
4845 00:24:58.784364 DUTY Scan : NO K
4846 00:24:58.787235 ZQ Calibration : PASS
4847 00:24:58.790822 Jitter Meter : NO K
4848 00:24:58.790931 CBT Training : PASS
4849 00:24:58.794135 Write leveling : PASS
4850 00:24:58.797083 RX DQS gating : PASS
4851 00:24:58.797169 RX DQ/DQS(RDDQC) : PASS
4852 00:24:58.800399 TX DQ/DQS : PASS
4853 00:24:58.803739 RX DATLAT : PASS
4854 00:24:58.803844 RX DQ/DQS(Engine): PASS
4855 00:24:58.807319 TX OE : NO K
4856 00:24:58.807419 All Pass.
4857 00:24:58.807516
4858 00:24:58.810242 CH 1, Rank 1
4859 00:24:58.810340 SW Impedance : PASS
4860 00:24:58.813854 DUTY Scan : NO K
4861 00:24:58.817169 ZQ Calibration : PASS
4862 00:24:58.817260 Jitter Meter : NO K
4863 00:24:58.821067 CBT Training : PASS
4864 00:24:58.823397 Write leveling : PASS
4865 00:24:58.823496 RX DQS gating : PASS
4866 00:24:58.827243 RX DQ/DQS(RDDQC) : PASS
4867 00:24:58.829891 TX DQ/DQS : PASS
4868 00:24:58.829992 RX DATLAT : PASS
4869 00:24:58.833239 RX DQ/DQS(Engine): PASS
4870 00:24:58.837623 TX OE : NO K
4871 00:24:58.837725 All Pass.
4872 00:24:58.837827
4873 00:24:58.837915 DramC Write-DBI off
4874 00:24:58.840064 PER_BANK_REFRESH: Hybrid Mode
4875 00:24:58.843415 TX_TRACKING: ON
4876 00:24:58.850050 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4877 00:24:58.853078 [FAST_K] Save calibration result to emmc
4878 00:24:58.859679 dramc_set_vcore_voltage set vcore to 662500
4879 00:24:58.859779 Read voltage for 933, 3
4880 00:24:58.863020 Vio18 = 0
4881 00:24:58.863116 Vcore = 662500
4882 00:24:58.863203 Vdram = 0
4883 00:24:58.866505 Vddq = 0
4884 00:24:58.866601 Vmddr = 0
4885 00:24:58.869889 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4886 00:24:58.876305 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4887 00:24:58.879190 MEM_TYPE=3, freq_sel=17
4888 00:24:58.882701 sv_algorithm_assistance_LP4_1600
4889 00:24:58.886457 ============ PULL DRAM RESETB DOWN ============
4890 00:24:58.889554 ========== PULL DRAM RESETB DOWN end =========
4891 00:24:58.896154 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4892 00:24:58.899432 ===================================
4893 00:24:58.899538 LPDDR4 DRAM CONFIGURATION
4894 00:24:58.902606 ===================================
4895 00:24:58.905976 EX_ROW_EN[0] = 0x0
4896 00:24:58.906082 EX_ROW_EN[1] = 0x0
4897 00:24:58.909239 LP4Y_EN = 0x0
4898 00:24:58.909335 WORK_FSP = 0x0
4899 00:24:58.912138 WL = 0x3
4900 00:24:58.912224 RL = 0x3
4901 00:24:58.916141 BL = 0x2
4902 00:24:58.918907 RPST = 0x0
4903 00:24:58.918981 RD_PRE = 0x0
4904 00:24:58.922077 WR_PRE = 0x1
4905 00:24:58.922146 WR_PST = 0x0
4906 00:24:58.925593 DBI_WR = 0x0
4907 00:24:58.925659 DBI_RD = 0x0
4908 00:24:58.928819 OTF = 0x1
4909 00:24:58.932092 ===================================
4910 00:24:58.935269 ===================================
4911 00:24:58.935348 ANA top config
4912 00:24:58.938498 ===================================
4913 00:24:58.941835 DLL_ASYNC_EN = 0
4914 00:24:58.945337 ALL_SLAVE_EN = 1
4915 00:24:58.945412 NEW_RANK_MODE = 1
4916 00:24:58.949155 DLL_IDLE_MODE = 1
4917 00:24:58.952431 LP45_APHY_COMB_EN = 1
4918 00:24:58.955227 TX_ODT_DIS = 1
4919 00:24:58.958535 NEW_8X_MODE = 1
4920 00:24:58.962113 ===================================
4921 00:24:58.964810 ===================================
4922 00:24:58.964891 data_rate = 1866
4923 00:24:58.968197 CKR = 1
4924 00:24:58.971619 DQ_P2S_RATIO = 8
4925 00:24:58.974884 ===================================
4926 00:24:58.978134 CA_P2S_RATIO = 8
4927 00:24:58.981601 DQ_CA_OPEN = 0
4928 00:24:58.985243 DQ_SEMI_OPEN = 0
4929 00:24:58.988147 CA_SEMI_OPEN = 0
4930 00:24:58.988225 CA_FULL_RATE = 0
4931 00:24:58.991882 DQ_CKDIV4_EN = 1
4932 00:24:58.994553 CA_CKDIV4_EN = 1
4933 00:24:58.998470 CA_PREDIV_EN = 0
4934 00:24:59.001130 PH8_DLY = 0
4935 00:24:59.004464 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4936 00:24:59.004554 DQ_AAMCK_DIV = 4
4937 00:24:59.008456 CA_AAMCK_DIV = 4
4938 00:24:59.011328 CA_ADMCK_DIV = 4
4939 00:24:59.014215 DQ_TRACK_CA_EN = 0
4940 00:24:59.018560 CA_PICK = 933
4941 00:24:59.021105 CA_MCKIO = 933
4942 00:24:59.024089 MCKIO_SEMI = 0
4943 00:24:59.024163 PLL_FREQ = 3732
4944 00:24:59.027248 DQ_UI_PI_RATIO = 32
4945 00:24:59.030658 CA_UI_PI_RATIO = 0
4946 00:24:59.034190 ===================================
4947 00:24:59.037093 ===================================
4948 00:24:59.040531 memory_type:LPDDR4
4949 00:24:59.043835 GP_NUM : 10
4950 00:24:59.043972 SRAM_EN : 1
4951 00:24:59.047453 MD32_EN : 0
4952 00:24:59.050586 ===================================
4953 00:24:59.050707 [ANA_INIT] >>>>>>>>>>>>>>
4954 00:24:59.053632 <<<<<< [CONFIGURE PHASE]: ANA_TX
4955 00:24:59.057081 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4956 00:24:59.060154 ===================================
4957 00:24:59.063348 data_rate = 1866,PCW = 0X8f00
4958 00:24:59.066713 ===================================
4959 00:24:59.070149 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4960 00:24:59.076605 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4961 00:24:59.083228 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4962 00:24:59.086674 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4963 00:24:59.089792 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4964 00:24:59.093011 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4965 00:24:59.096455 [ANA_INIT] flow start
4966 00:24:59.096557 [ANA_INIT] PLL >>>>>>>>
4967 00:24:59.099931 [ANA_INIT] PLL <<<<<<<<
4968 00:24:59.103269 [ANA_INIT] MIDPI >>>>>>>>
4969 00:24:59.106449 [ANA_INIT] MIDPI <<<<<<<<
4970 00:24:59.106559 [ANA_INIT] DLL >>>>>>>>
4971 00:24:59.110159 [ANA_INIT] flow end
4972 00:24:59.113164 ============ LP4 DIFF to SE enter ============
4973 00:24:59.115936 ============ LP4 DIFF to SE exit ============
4974 00:24:59.119390 [ANA_INIT] <<<<<<<<<<<<<
4975 00:24:59.122432 [Flow] Enable top DCM control >>>>>
4976 00:24:59.126345 [Flow] Enable top DCM control <<<<<
4977 00:24:59.129246 Enable DLL master slave shuffle
4978 00:24:59.135808 ==============================================================
4979 00:24:59.135937 Gating Mode config
4980 00:24:59.142723 ==============================================================
4981 00:24:59.142822 Config description:
4982 00:24:59.152478 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4983 00:24:59.159172 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4984 00:24:59.165505 SELPH_MODE 0: By rank 1: By Phase
4985 00:24:59.168823 ==============================================================
4986 00:24:59.172331 GAT_TRACK_EN = 1
4987 00:24:59.175792 RX_GATING_MODE = 2
4988 00:24:59.178627 RX_GATING_TRACK_MODE = 2
4989 00:24:59.182021 SELPH_MODE = 1
4990 00:24:59.185168 PICG_EARLY_EN = 1
4991 00:24:59.188504 VALID_LAT_VALUE = 1
4992 00:24:59.195317 ==============================================================
4993 00:24:59.198753 Enter into Gating configuration >>>>
4994 00:24:59.201734 Exit from Gating configuration <<<<
4995 00:24:59.205064 Enter into DVFS_PRE_config >>>>>
4996 00:24:59.215137 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4997 00:24:59.218729 Exit from DVFS_PRE_config <<<<<
4998 00:24:59.221743 Enter into PICG configuration >>>>
4999 00:24:59.225184 Exit from PICG configuration <<<<
5000 00:24:59.228122 [RX_INPUT] configuration >>>>>
5001 00:24:59.231066 [RX_INPUT] configuration <<<<<
5002 00:24:59.234468 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5003 00:24:59.243057 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5004 00:24:59.248417 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5005 00:24:59.251439 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5006 00:24:59.257966 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5007 00:24:59.264708 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5008 00:24:59.267685 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5009 00:24:59.274109 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5010 00:24:59.277888 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5011 00:24:59.280758 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5012 00:24:59.284169 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5013 00:24:59.290624 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5014 00:24:59.294141 ===================================
5015 00:24:59.294222 LPDDR4 DRAM CONFIGURATION
5016 00:24:59.297971 ===================================
5017 00:24:59.300853 EX_ROW_EN[0] = 0x0
5018 00:24:59.304194 EX_ROW_EN[1] = 0x0
5019 00:24:59.304283 LP4Y_EN = 0x0
5020 00:24:59.307473 WORK_FSP = 0x0
5021 00:24:59.307578 WL = 0x3
5022 00:24:59.310305 RL = 0x3
5023 00:24:59.310417 BL = 0x2
5024 00:24:59.314123 RPST = 0x0
5025 00:24:59.314223 RD_PRE = 0x0
5026 00:24:59.317049 WR_PRE = 0x1
5027 00:24:59.317146 WR_PST = 0x0
5028 00:24:59.320215 DBI_WR = 0x0
5029 00:24:59.320315 DBI_RD = 0x0
5030 00:24:59.323700 OTF = 0x1
5031 00:24:59.327142 ===================================
5032 00:24:59.330252 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5033 00:24:59.333272 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5034 00:24:59.340030 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5035 00:24:59.343278 ===================================
5036 00:24:59.346530 LPDDR4 DRAM CONFIGURATION
5037 00:24:59.350025 ===================================
5038 00:24:59.350125 EX_ROW_EN[0] = 0x10
5039 00:24:59.353268 EX_ROW_EN[1] = 0x0
5040 00:24:59.353367 LP4Y_EN = 0x0
5041 00:24:59.356252 WORK_FSP = 0x0
5042 00:24:59.356324 WL = 0x3
5043 00:24:59.359729 RL = 0x3
5044 00:24:59.359830 BL = 0x2
5045 00:24:59.362960 RPST = 0x0
5046 00:24:59.363066 RD_PRE = 0x0
5047 00:24:59.366290 WR_PRE = 0x1
5048 00:24:59.369541 WR_PST = 0x0
5049 00:24:59.369626 DBI_WR = 0x0
5050 00:24:59.373227 DBI_RD = 0x0
5051 00:24:59.373327 OTF = 0x1
5052 00:24:59.376133 ===================================
5053 00:24:59.382506 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5054 00:24:59.387021 nWR fixed to 30
5055 00:24:59.389811 [ModeRegInit_LP4] CH0 RK0
5056 00:24:59.389910 [ModeRegInit_LP4] CH0 RK1
5057 00:24:59.393244 [ModeRegInit_LP4] CH1 RK0
5058 00:24:59.396627 [ModeRegInit_LP4] CH1 RK1
5059 00:24:59.396716 match AC timing 9
5060 00:24:59.402874 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5061 00:24:59.406686 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5062 00:24:59.409737 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5063 00:24:59.416248 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5064 00:24:59.419688 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5065 00:24:59.419783 ==
5066 00:24:59.422964 Dram Type= 6, Freq= 0, CH_0, rank 0
5067 00:24:59.426064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5068 00:24:59.426158 ==
5069 00:24:59.432690 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5070 00:24:59.439348 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5071 00:24:59.442134 [CA 0] Center 37 (7~68) winsize 62
5072 00:24:59.445720 [CA 1] Center 37 (7~68) winsize 62
5073 00:24:59.448868 [CA 2] Center 34 (4~65) winsize 62
5074 00:24:59.452495 [CA 3] Center 34 (3~65) winsize 63
5075 00:24:59.455878 [CA 4] Center 33 (3~63) winsize 61
5076 00:24:59.458531 [CA 5] Center 32 (2~63) winsize 62
5077 00:24:59.458627
5078 00:24:59.462258 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5079 00:24:59.462366
5080 00:24:59.465142 [CATrainingPosCal] consider 1 rank data
5081 00:24:59.468651 u2DelayCellTimex100 = 270/100 ps
5082 00:24:59.471678 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5083 00:24:59.475038 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5084 00:24:59.478771 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5085 00:24:59.485036 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5086 00:24:59.488237 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5087 00:24:59.492445 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5088 00:24:59.492518
5089 00:24:59.495309 CA PerBit enable=1, Macro0, CA PI delay=32
5090 00:24:59.495414
5091 00:24:59.498397 [CBTSetCACLKResult] CA Dly = 32
5092 00:24:59.498491 CS Dly: 6 (0~37)
5093 00:24:59.501350 ==
5094 00:24:59.504800 Dram Type= 6, Freq= 0, CH_0, rank 1
5095 00:24:59.507792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5096 00:24:59.507897 ==
5097 00:24:59.511431 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5098 00:24:59.518391 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5099 00:24:59.522044 [CA 0] Center 37 (7~68) winsize 62
5100 00:24:59.524977 [CA 1] Center 37 (7~68) winsize 62
5101 00:24:59.528157 [CA 2] Center 34 (4~65) winsize 62
5102 00:24:59.531451 [CA 3] Center 34 (4~65) winsize 62
5103 00:24:59.534950 [CA 4] Center 33 (3~64) winsize 62
5104 00:24:59.538229 [CA 5] Center 32 (2~63) winsize 62
5105 00:24:59.538329
5106 00:24:59.541692 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5107 00:24:59.541799
5108 00:24:59.544383 [CATrainingPosCal] consider 2 rank data
5109 00:24:59.547666 u2DelayCellTimex100 = 270/100 ps
5110 00:24:59.551225 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5111 00:24:59.557532 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5112 00:24:59.561126 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5113 00:24:59.564614 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5114 00:24:59.567856 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5115 00:24:59.571176 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5116 00:24:59.571279
5117 00:24:59.574221 CA PerBit enable=1, Macro0, CA PI delay=32
5118 00:24:59.574328
5119 00:24:59.577743 [CBTSetCACLKResult] CA Dly = 32
5120 00:24:59.580668 CS Dly: 7 (0~39)
5121 00:24:59.580778
5122 00:24:59.584122 ----->DramcWriteLeveling(PI) begin...
5123 00:24:59.584203 ==
5124 00:24:59.587203 Dram Type= 6, Freq= 0, CH_0, rank 0
5125 00:24:59.590816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5126 00:24:59.590927 ==
5127 00:24:59.594549 Write leveling (Byte 0): 33 => 33
5128 00:24:59.597545 Write leveling (Byte 1): 29 => 29
5129 00:24:59.600458 DramcWriteLeveling(PI) end<-----
5130 00:24:59.600531
5131 00:24:59.600605 ==
5132 00:24:59.603635 Dram Type= 6, Freq= 0, CH_0, rank 0
5133 00:24:59.608176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5134 00:24:59.608251 ==
5135 00:24:59.610349 [Gating] SW mode calibration
5136 00:24:59.617490 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5137 00:24:59.623551 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5138 00:24:59.627410 0 14 0 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
5139 00:24:59.634024 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 00:24:59.636724 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5141 00:24:59.640195 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 00:24:59.647309 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 00:24:59.650607 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 00:24:59.653804 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5145 00:24:59.659817 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5146 00:24:59.663381 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
5147 00:24:59.666591 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 00:24:59.673436 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 00:24:59.676686 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 00:24:59.679908 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 00:24:59.686527 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 00:24:59.690099 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 00:24:59.692985 0 15 28 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
5154 00:24:59.699230 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5155 00:24:59.702589 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 00:24:59.706188 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 00:24:59.712425 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 00:24:59.716140 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 00:24:59.719130 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 00:24:59.725938 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5161 00:24:59.729117 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5162 00:24:59.732313 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5163 00:24:59.739105 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5164 00:24:59.742067 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 00:24:59.745622 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 00:24:59.752214 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 00:24:59.755394 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 00:24:59.758850 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 00:24:59.765187 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 00:24:59.768449 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 00:24:59.771878 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 00:24:59.778887 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 00:24:59.781959 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 00:24:59.785421 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 00:24:59.791957 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 00:24:59.794927 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 00:24:59.798475 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5178 00:24:59.801587 Total UI for P1: 0, mck2ui 16
5179 00:24:59.805555 best dqsien dly found for B0: ( 1, 2, 26)
5180 00:24:59.811372 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5181 00:24:59.815127 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 00:24:59.817893 Total UI for P1: 0, mck2ui 16
5183 00:24:59.821174 best dqsien dly found for B1: ( 1, 2, 30)
5184 00:24:59.825085 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5185 00:24:59.828476 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5186 00:24:59.828548
5187 00:24:59.831518 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5188 00:24:59.834718 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5189 00:24:59.837971 [Gating] SW calibration Done
5190 00:24:59.838043 ==
5191 00:24:59.841848 Dram Type= 6, Freq= 0, CH_0, rank 0
5192 00:24:59.844579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5193 00:24:59.847776 ==
5194 00:24:59.847875 RX Vref Scan: 0
5195 00:24:59.847987
5196 00:24:59.850990 RX Vref 0 -> 0, step: 1
5197 00:24:59.851056
5198 00:24:59.851115 RX Delay -80 -> 252, step: 8
5199 00:24:59.858467 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5200 00:24:59.861776 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5201 00:24:59.864413 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5202 00:24:59.868339 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5203 00:24:59.871503 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5204 00:24:59.874899 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5205 00:24:59.881740 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5206 00:24:59.884626 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5207 00:24:59.887796 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5208 00:24:59.891267 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5209 00:24:59.894233 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5210 00:24:59.900849 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5211 00:24:59.904806 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5212 00:24:59.907430 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5213 00:24:59.911424 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5214 00:24:59.914207 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5215 00:24:59.914287 ==
5216 00:24:59.917378 Dram Type= 6, Freq= 0, CH_0, rank 0
5217 00:24:59.924498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5218 00:24:59.924578 ==
5219 00:24:59.924641 DQS Delay:
5220 00:24:59.924700 DQS0 = 0, DQS1 = 0
5221 00:24:59.927646 DQM Delay:
5222 00:24:59.927725 DQM0 = 100, DQM1 = 89
5223 00:24:59.930463 DQ Delay:
5224 00:24:59.933973 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5225 00:24:59.937185 DQ4 =103, DQ5 =91, DQ6 =111, DQ7 =111
5226 00:24:59.940430 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =83
5227 00:24:59.943788 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5228 00:24:59.943885
5229 00:24:59.944013
5230 00:24:59.944101 ==
5231 00:24:59.947138 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 00:24:59.950262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 00:24:59.950340 ==
5234 00:24:59.950431
5235 00:24:59.950528
5236 00:24:59.953736 TX Vref Scan disable
5237 00:24:59.957346 == TX Byte 0 ==
5238 00:24:59.960129 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5239 00:24:59.963693 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5240 00:24:59.966864 == TX Byte 1 ==
5241 00:24:59.970132 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5242 00:24:59.973556 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5243 00:24:59.973653 ==
5244 00:24:59.976747 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 00:24:59.983265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 00:24:59.983371 ==
5247 00:24:59.983462
5248 00:24:59.983551
5249 00:24:59.983638 TX Vref Scan disable
5250 00:24:59.987262 == TX Byte 0 ==
5251 00:24:59.990670 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5252 00:24:59.997058 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5253 00:24:59.997160 == TX Byte 1 ==
5254 00:25:00.001197 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5255 00:25:00.006789 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5256 00:25:00.006888
5257 00:25:00.006977 [DATLAT]
5258 00:25:00.007064 Freq=933, CH0 RK0
5259 00:25:00.007147
5260 00:25:00.010316 DATLAT Default: 0xd
5261 00:25:00.013530 0, 0xFFFF, sum = 0
5262 00:25:00.013606 1, 0xFFFF, sum = 0
5263 00:25:00.016814 2, 0xFFFF, sum = 0
5264 00:25:00.016887 3, 0xFFFF, sum = 0
5265 00:25:00.020246 4, 0xFFFF, sum = 0
5266 00:25:00.020344 5, 0xFFFF, sum = 0
5267 00:25:00.023385 6, 0xFFFF, sum = 0
5268 00:25:00.023453 7, 0xFFFF, sum = 0
5269 00:25:00.027098 8, 0xFFFF, sum = 0
5270 00:25:00.027192 9, 0xFFFF, sum = 0
5271 00:25:00.030190 10, 0x0, sum = 1
5272 00:25:00.030286 11, 0x0, sum = 2
5273 00:25:00.033064 12, 0x0, sum = 3
5274 00:25:00.033132 13, 0x0, sum = 4
5275 00:25:00.036339 best_step = 11
5276 00:25:00.036410
5277 00:25:00.036473 ==
5278 00:25:00.039925 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 00:25:00.042924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 00:25:00.043019 ==
5281 00:25:00.043107 RX Vref Scan: 1
5282 00:25:00.046162
5283 00:25:00.046260 RX Vref 0 -> 0, step: 1
5284 00:25:00.046349
5285 00:25:00.049873 RX Delay -61 -> 252, step: 4
5286 00:25:00.049965
5287 00:25:00.053547 Set Vref, RX VrefLevel [Byte0]: 52
5288 00:25:00.056561 [Byte1]: 49
5289 00:25:00.059649
5290 00:25:00.059719 Final RX Vref Byte 0 = 52 to rank0
5291 00:25:00.063345 Final RX Vref Byte 1 = 49 to rank0
5292 00:25:00.066464 Final RX Vref Byte 0 = 52 to rank1
5293 00:25:00.069878 Final RX Vref Byte 1 = 49 to rank1==
5294 00:25:00.073098 Dram Type= 6, Freq= 0, CH_0, rank 0
5295 00:25:00.079461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 00:25:00.079558 ==
5297 00:25:00.079649 DQS Delay:
5298 00:25:00.082911 DQS0 = 0, DQS1 = 0
5299 00:25:00.083005 DQM Delay:
5300 00:25:00.083089 DQM0 = 99, DQM1 = 87
5301 00:25:00.086209 DQ Delay:
5302 00:25:00.089402 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =96
5303 00:25:00.093802 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =106
5304 00:25:00.096109 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =84
5305 00:25:00.099690 DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =94
5306 00:25:00.099786
5307 00:25:00.099909
5308 00:25:00.106057 [DQSOSCAuto] RK0, (LSB)MR18= 0x201a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 411 ps
5309 00:25:00.109383 CH0 RK0: MR19=505, MR18=201A
5310 00:25:00.115716 CH0_RK0: MR19=0x505, MR18=0x201A, DQSOSC=411, MR23=63, INC=64, DEC=42
5311 00:25:00.115814
5312 00:25:00.119231 ----->DramcWriteLeveling(PI) begin...
5313 00:25:00.119302 ==
5314 00:25:00.122302 Dram Type= 6, Freq= 0, CH_0, rank 1
5315 00:25:00.125796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 00:25:00.125889 ==
5317 00:25:00.128785 Write leveling (Byte 0): 33 => 33
5318 00:25:00.132193 Write leveling (Byte 1): 28 => 28
5319 00:25:00.135612 DramcWriteLeveling(PI) end<-----
5320 00:25:00.135707
5321 00:25:00.135794 ==
5322 00:25:00.139294 Dram Type= 6, Freq= 0, CH_0, rank 1
5323 00:25:00.145488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5324 00:25:00.145605 ==
5325 00:25:00.145710 [Gating] SW mode calibration
5326 00:25:00.155309 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5327 00:25:00.158380 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5328 00:25:00.162182 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5329 00:25:00.168738 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 00:25:00.172166 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 00:25:00.178295 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 00:25:00.181923 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 00:25:00.184724 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 00:25:00.191889 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5335 00:25:00.194690 0 14 28 | B1->B0 | 3333 2a2a | 0 0 | (0 1) (1 0)
5336 00:25:00.197988 0 15 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
5337 00:25:00.204873 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 00:25:00.208085 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 00:25:00.211116 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 00:25:00.217920 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 00:25:00.220977 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 00:25:00.224593 0 15 24 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
5343 00:25:00.231050 0 15 28 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
5344 00:25:00.234284 1 0 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5345 00:25:00.237291 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 00:25:00.244236 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 00:25:00.247242 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 00:25:00.250756 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 00:25:00.257228 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 00:25:00.260729 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5351 00:25:00.263774 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5352 00:25:00.270278 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5353 00:25:00.273457 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 00:25:00.276766 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 00:25:00.283707 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 00:25:00.287083 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 00:25:00.289851 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 00:25:00.296680 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 00:25:00.299855 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 00:25:00.303404 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 00:25:00.309551 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 00:25:00.312934 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 00:25:00.316784 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 00:25:00.322999 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 00:25:00.326538 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 00:25:00.329792 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 00:25:00.336584 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5368 00:25:00.339192 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5369 00:25:00.342806 Total UI for P1: 0, mck2ui 16
5370 00:25:00.346608 best dqsien dly found for B0: ( 1, 2, 28)
5371 00:25:00.349256 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 00:25:00.352706 Total UI for P1: 0, mck2ui 16
5373 00:25:00.356076 best dqsien dly found for B1: ( 1, 2, 30)
5374 00:25:00.360090 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5375 00:25:00.362376 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5376 00:25:00.362450
5377 00:25:00.368980 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5378 00:25:00.372560 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5379 00:25:00.372636 [Gating] SW calibration Done
5380 00:25:00.376370 ==
5381 00:25:00.379307 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 00:25:00.382002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 00:25:00.382110 ==
5384 00:25:00.382204 RX Vref Scan: 0
5385 00:25:00.382292
5386 00:25:00.385688 RX Vref 0 -> 0, step: 1
5387 00:25:00.385798
5388 00:25:00.389015 RX Delay -80 -> 252, step: 8
5389 00:25:00.392170 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5390 00:25:00.395636 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5391 00:25:00.398612 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5392 00:25:00.405117 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5393 00:25:00.408807 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5394 00:25:00.411911 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5395 00:25:00.414936 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5396 00:25:00.418393 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5397 00:25:00.424784 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5398 00:25:00.427886 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5399 00:25:00.432514 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5400 00:25:00.434843 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5401 00:25:00.438470 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5402 00:25:00.441573 iDelay=200, Bit 13, Center 91 (0 ~ 183) 184
5403 00:25:00.447824 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5404 00:25:00.451397 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5405 00:25:00.451494 ==
5406 00:25:00.454584 Dram Type= 6, Freq= 0, CH_0, rank 1
5407 00:25:00.458505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 00:25:00.458604 ==
5409 00:25:00.461503 DQS Delay:
5410 00:25:00.461602 DQS0 = 0, DQS1 = 0
5411 00:25:00.461690 DQM Delay:
5412 00:25:00.464440 DQM0 = 97, DQM1 = 89
5413 00:25:00.464508 DQ Delay:
5414 00:25:00.467830 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5415 00:25:00.470971 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5416 00:25:00.474133 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5417 00:25:00.477607 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =91
5418 00:25:00.477702
5419 00:25:00.477789
5420 00:25:00.477876 ==
5421 00:25:00.481469 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 00:25:00.487737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 00:25:00.487833 ==
5424 00:25:00.487945
5425 00:25:00.488056
5426 00:25:00.490684 TX Vref Scan disable
5427 00:25:00.490780 == TX Byte 0 ==
5428 00:25:00.494022 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5429 00:25:00.500738 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5430 00:25:00.500838 == TX Byte 1 ==
5431 00:25:00.504102 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5432 00:25:00.510526 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5433 00:25:00.510622 ==
5434 00:25:00.514059 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 00:25:00.517500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 00:25:00.517594 ==
5437 00:25:00.517684
5438 00:25:00.517768
5439 00:25:00.520431 TX Vref Scan disable
5440 00:25:00.523406 == TX Byte 0 ==
5441 00:25:00.527793 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5442 00:25:00.530237 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5443 00:25:00.533342 == TX Byte 1 ==
5444 00:25:00.537254 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5445 00:25:00.539989 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5446 00:25:00.540088
5447 00:25:00.543686 [DATLAT]
5448 00:25:00.543794 Freq=933, CH0 RK1
5449 00:25:00.543884
5450 00:25:00.546635 DATLAT Default: 0xb
5451 00:25:00.546736 0, 0xFFFF, sum = 0
5452 00:25:00.549685 1, 0xFFFF, sum = 0
5453 00:25:00.549786 2, 0xFFFF, sum = 0
5454 00:25:00.553447 3, 0xFFFF, sum = 0
5455 00:25:00.553520 4, 0xFFFF, sum = 0
5456 00:25:00.556825 5, 0xFFFF, sum = 0
5457 00:25:00.556931 6, 0xFFFF, sum = 0
5458 00:25:00.559837 7, 0xFFFF, sum = 0
5459 00:25:00.559977 8, 0xFFFF, sum = 0
5460 00:25:00.562854 9, 0xFFFF, sum = 0
5461 00:25:00.562957 10, 0x0, sum = 1
5462 00:25:00.567231 11, 0x0, sum = 2
5463 00:25:00.567308 12, 0x0, sum = 3
5464 00:25:00.569995 13, 0x0, sum = 4
5465 00:25:00.570082 best_step = 11
5466 00:25:00.570180
5467 00:25:00.570269 ==
5468 00:25:00.572779 Dram Type= 6, Freq= 0, CH_0, rank 1
5469 00:25:00.579669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5470 00:25:00.579771 ==
5471 00:25:00.579864 RX Vref Scan: 0
5472 00:25:00.579981
5473 00:25:00.583019 RX Vref 0 -> 0, step: 1
5474 00:25:00.583115
5475 00:25:00.586083 RX Delay -53 -> 252, step: 4
5476 00:25:00.589793 iDelay=195, Bit 0, Center 98 (11 ~ 186) 176
5477 00:25:00.596076 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5478 00:25:00.599293 iDelay=195, Bit 2, Center 92 (3 ~ 182) 180
5479 00:25:00.602619 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5480 00:25:00.605867 iDelay=195, Bit 4, Center 100 (11 ~ 190) 180
5481 00:25:00.609309 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5482 00:25:00.612589 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
5483 00:25:00.619110 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5484 00:25:00.622424 iDelay=195, Bit 8, Center 80 (-9 ~ 170) 180
5485 00:25:00.626048 iDelay=195, Bit 9, Center 76 (-13 ~ 166) 180
5486 00:25:00.629492 iDelay=195, Bit 10, Center 86 (-5 ~ 178) 184
5487 00:25:00.631916 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5488 00:25:00.639036 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5489 00:25:00.642814 iDelay=195, Bit 13, Center 92 (3 ~ 182) 180
5490 00:25:00.645912 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5491 00:25:00.648690 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5492 00:25:00.648770 ==
5493 00:25:00.651750 Dram Type= 6, Freq= 0, CH_0, rank 1
5494 00:25:00.656115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5495 00:25:00.658550 ==
5496 00:25:00.658656 DQS Delay:
5497 00:25:00.658748 DQS0 = 0, DQS1 = 0
5498 00:25:00.662184 DQM Delay:
5499 00:25:00.662283 DQM0 = 97, DQM1 = 88
5500 00:25:00.665305 DQ Delay:
5501 00:25:00.668281 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5502 00:25:00.671686 DQ4 =100, DQ5 =86, DQ6 =104, DQ7 =104
5503 00:25:00.675923 DQ8 =80, DQ9 =76, DQ10 =86, DQ11 =82
5504 00:25:00.677937 DQ12 =94, DQ13 =92, DQ14 =100, DQ15 =94
5505 00:25:00.678010
5506 00:25:00.678072
5507 00:25:00.685209 [DQSOSCAuto] RK1, (LSB)MR18= 0x1310, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5508 00:25:00.688633 CH0 RK1: MR19=505, MR18=1310
5509 00:25:00.694710 CH0_RK1: MR19=0x505, MR18=0x1310, DQSOSC=415, MR23=63, INC=62, DEC=41
5510 00:25:00.698211 [RxdqsGatingPostProcess] freq 933
5511 00:25:00.701078 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5512 00:25:00.704787 best DQS0 dly(2T, 0.5T) = (0, 10)
5513 00:25:00.707811 best DQS1 dly(2T, 0.5T) = (0, 10)
5514 00:25:00.711057 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5515 00:25:00.714594 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5516 00:25:00.718267 best DQS0 dly(2T, 0.5T) = (0, 10)
5517 00:25:00.721100 best DQS1 dly(2T, 0.5T) = (0, 10)
5518 00:25:00.724376 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5519 00:25:00.727833 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5520 00:25:00.731359 Pre-setting of DQS Precalculation
5521 00:25:00.734847 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5522 00:25:00.737884 ==
5523 00:25:00.740918 Dram Type= 6, Freq= 0, CH_1, rank 0
5524 00:25:00.744203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5525 00:25:00.744299 ==
5526 00:25:00.747927 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5527 00:25:00.754615 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5528 00:25:00.757940 [CA 0] Center 36 (6~67) winsize 62
5529 00:25:00.761217 [CA 1] Center 36 (6~67) winsize 62
5530 00:25:00.764285 [CA 2] Center 34 (4~65) winsize 62
5531 00:25:00.768054 [CA 3] Center 34 (3~65) winsize 63
5532 00:25:00.771752 [CA 4] Center 34 (4~65) winsize 62
5533 00:25:00.774298 [CA 5] Center 33 (3~64) winsize 62
5534 00:25:00.774371
5535 00:25:00.777473 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5536 00:25:00.777569
5537 00:25:00.781322 [CATrainingPosCal] consider 1 rank data
5538 00:25:00.784578 u2DelayCellTimex100 = 270/100 ps
5539 00:25:00.787512 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5540 00:25:00.794070 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5541 00:25:00.797382 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5542 00:25:00.800781 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5543 00:25:00.803826 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5544 00:25:00.807476 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5545 00:25:00.807573
5546 00:25:00.811180 CA PerBit enable=1, Macro0, CA PI delay=33
5547 00:25:00.811278
5548 00:25:00.813671 [CBTSetCACLKResult] CA Dly = 33
5549 00:25:00.816924 CS Dly: 5 (0~36)
5550 00:25:00.816994 ==
5551 00:25:00.820305 Dram Type= 6, Freq= 0, CH_1, rank 1
5552 00:25:00.823788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 00:25:00.823885 ==
5554 00:25:00.830227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5555 00:25:00.833321 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5556 00:25:00.837882 [CA 0] Center 36 (6~66) winsize 61
5557 00:25:00.841347 [CA 1] Center 36 (6~67) winsize 62
5558 00:25:00.844506 [CA 2] Center 34 (4~65) winsize 62
5559 00:25:00.848496 [CA 3] Center 33 (3~64) winsize 62
5560 00:25:00.850657 [CA 4] Center 34 (4~64) winsize 61
5561 00:25:00.854315 [CA 5] Center 33 (3~64) winsize 62
5562 00:25:00.854410
5563 00:25:00.857521 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5564 00:25:00.857617
5565 00:25:00.864055 [CATrainingPosCal] consider 2 rank data
5566 00:25:00.864131 u2DelayCellTimex100 = 270/100 ps
5567 00:25:00.870605 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5568 00:25:00.873718 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5569 00:25:00.877357 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5570 00:25:00.880574 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5571 00:25:00.883861 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5572 00:25:00.887121 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5573 00:25:00.887191
5574 00:25:00.890266 CA PerBit enable=1, Macro0, CA PI delay=33
5575 00:25:00.890345
5576 00:25:00.893522 [CBTSetCACLKResult] CA Dly = 33
5577 00:25:00.896694 CS Dly: 6 (0~38)
5578 00:25:00.896792
5579 00:25:00.900410 ----->DramcWriteLeveling(PI) begin...
5580 00:25:00.900483 ==
5581 00:25:00.903481 Dram Type= 6, Freq= 0, CH_1, rank 0
5582 00:25:00.906717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 00:25:00.906786 ==
5584 00:25:00.909886 Write leveling (Byte 0): 27 => 27
5585 00:25:00.913409 Write leveling (Byte 1): 29 => 29
5586 00:25:00.916630 DramcWriteLeveling(PI) end<-----
5587 00:25:00.916722
5588 00:25:00.916811 ==
5589 00:25:00.920033 Dram Type= 6, Freq= 0, CH_1, rank 0
5590 00:25:00.923366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5591 00:25:00.923461 ==
5592 00:25:00.926595 [Gating] SW mode calibration
5593 00:25:00.933104 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5594 00:25:00.939689 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5595 00:25:00.942987 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 00:25:00.949695 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 00:25:00.953070 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 00:25:00.956085 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 00:25:00.962925 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 00:25:00.966340 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 00:25:00.969166 0 14 24 | B1->B0 | 3333 3131 | 1 1 | (1 1) (1 0)
5602 00:25:00.975772 0 14 28 | B1->B0 | 2f2f 2828 | 0 0 | (1 1) (0 0)
5603 00:25:00.979703 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 00:25:00.982315 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 00:25:00.989244 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 00:25:00.992726 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 00:25:00.995776 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 00:25:01.002142 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 00:25:01.005285 0 15 24 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
5610 00:25:01.009292 0 15 28 | B1->B0 | 3434 4040 | 0 0 | (0 0) (0 0)
5611 00:25:01.015256 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 00:25:01.018723 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 00:25:01.022354 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 00:25:01.028769 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 00:25:01.032192 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 00:25:01.035676 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 00:25:01.041857 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5618 00:25:01.045395 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5619 00:25:01.048558 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5620 00:25:01.055052 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 00:25:01.058591 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 00:25:01.061623 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 00:25:01.068358 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 00:25:01.071970 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 00:25:01.075185 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 00:25:01.081014 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 00:25:01.084302 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 00:25:01.087849 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 00:25:01.094601 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 00:25:01.097779 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 00:25:01.100688 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 00:25:01.107840 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 00:25:01.110771 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 00:25:01.114368 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5635 00:25:01.120599 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 00:25:01.120674 Total UI for P1: 0, mck2ui 16
5637 00:25:01.127045 best dqsien dly found for B0: ( 1, 2, 28)
5638 00:25:01.127117 Total UI for P1: 0, mck2ui 16
5639 00:25:01.133918 best dqsien dly found for B1: ( 1, 2, 28)
5640 00:25:01.137307 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5641 00:25:01.140929 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5642 00:25:01.141002
5643 00:25:01.144002 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5644 00:25:01.146918 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5645 00:25:01.150505 [Gating] SW calibration Done
5646 00:25:01.150602 ==
5647 00:25:01.153894 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 00:25:01.156711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 00:25:01.156808 ==
5650 00:25:01.160290 RX Vref Scan: 0
5651 00:25:01.160366
5652 00:25:01.160428 RX Vref 0 -> 0, step: 1
5653 00:25:01.160487
5654 00:25:01.163477 RX Delay -80 -> 252, step: 8
5655 00:25:01.170022 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5656 00:25:01.173589 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5657 00:25:01.177063 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5658 00:25:01.180007 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5659 00:25:01.183317 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5660 00:25:01.186818 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5661 00:25:01.193101 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5662 00:25:01.196349 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5663 00:25:01.199697 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5664 00:25:01.203379 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5665 00:25:01.206146 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5666 00:25:01.209558 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5667 00:25:01.216001 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5668 00:25:01.219978 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5669 00:25:01.222648 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5670 00:25:01.225962 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5671 00:25:01.226058 ==
5672 00:25:01.229440 Dram Type= 6, Freq= 0, CH_1, rank 0
5673 00:25:01.236168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5674 00:25:01.236273 ==
5675 00:25:01.236342 DQS Delay:
5676 00:25:01.239287 DQS0 = 0, DQS1 = 0
5677 00:25:01.239383 DQM Delay:
5678 00:25:01.239471 DQM0 = 100, DQM1 = 96
5679 00:25:01.243834 DQ Delay:
5680 00:25:01.246050 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5681 00:25:01.249198 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5682 00:25:01.252551 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5683 00:25:01.256051 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5684 00:25:01.256152
5685 00:25:01.256243
5686 00:25:01.256329 ==
5687 00:25:01.258893 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 00:25:01.262614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 00:25:01.262721 ==
5690 00:25:01.262811
5691 00:25:01.262903
5692 00:25:01.265684 TX Vref Scan disable
5693 00:25:01.268890 == TX Byte 0 ==
5694 00:25:01.272272 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5695 00:25:01.275814 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5696 00:25:01.279468 == TX Byte 1 ==
5697 00:25:01.282681 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5698 00:25:01.285747 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5699 00:25:01.285850 ==
5700 00:25:01.288998 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 00:25:01.295417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 00:25:01.295521 ==
5703 00:25:01.295610
5704 00:25:01.295695
5705 00:25:01.295791 TX Vref Scan disable
5706 00:25:01.299251 == TX Byte 0 ==
5707 00:25:01.302415 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5708 00:25:01.309886 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5709 00:25:01.309967 == TX Byte 1 ==
5710 00:25:01.312838 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5711 00:25:01.319422 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5712 00:25:01.319523
5713 00:25:01.319613 [DATLAT]
5714 00:25:01.319712 Freq=933, CH1 RK0
5715 00:25:01.319800
5716 00:25:01.322181 DATLAT Default: 0xd
5717 00:25:01.322275 0, 0xFFFF, sum = 0
5718 00:25:01.325892 1, 0xFFFF, sum = 0
5719 00:25:01.329278 2, 0xFFFF, sum = 0
5720 00:25:01.329378 3, 0xFFFF, sum = 0
5721 00:25:01.332302 4, 0xFFFF, sum = 0
5722 00:25:01.332405 5, 0xFFFF, sum = 0
5723 00:25:01.335649 6, 0xFFFF, sum = 0
5724 00:25:01.335743 7, 0xFFFF, sum = 0
5725 00:25:01.339131 8, 0xFFFF, sum = 0
5726 00:25:01.339225 9, 0xFFFF, sum = 0
5727 00:25:01.342461 10, 0x0, sum = 1
5728 00:25:01.342558 11, 0x0, sum = 2
5729 00:25:01.345462 12, 0x0, sum = 3
5730 00:25:01.345564 13, 0x0, sum = 4
5731 00:25:01.348744 best_step = 11
5732 00:25:01.348816
5733 00:25:01.348879 ==
5734 00:25:01.351729 Dram Type= 6, Freq= 0, CH_1, rank 0
5735 00:25:01.355017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 00:25:01.355120 ==
5737 00:25:01.355210 RX Vref Scan: 1
5738 00:25:01.359013
5739 00:25:01.359112 RX Vref 0 -> 0, step: 1
5740 00:25:01.359200
5741 00:25:01.362384 RX Delay -53 -> 252, step: 4
5742 00:25:01.362455
5743 00:25:01.365512 Set Vref, RX VrefLevel [Byte0]: 53
5744 00:25:01.368118 [Byte1]: 51
5745 00:25:01.371840
5746 00:25:01.371981 Final RX Vref Byte 0 = 53 to rank0
5747 00:25:01.375036 Final RX Vref Byte 1 = 51 to rank0
5748 00:25:01.378285 Final RX Vref Byte 0 = 53 to rank1
5749 00:25:01.381734 Final RX Vref Byte 1 = 51 to rank1==
5750 00:25:01.385708 Dram Type= 6, Freq= 0, CH_1, rank 0
5751 00:25:01.391744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 00:25:01.391847 ==
5753 00:25:01.391975 DQS Delay:
5754 00:25:01.392047 DQS0 = 0, DQS1 = 0
5755 00:25:01.395007 DQM Delay:
5756 00:25:01.395100 DQM0 = 98, DQM1 = 94
5757 00:25:01.399026 DQ Delay:
5758 00:25:01.402002 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =98
5759 00:25:01.404814 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5760 00:25:01.408308 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5761 00:25:01.411642 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =102
5762 00:25:01.411736
5763 00:25:01.411832
5764 00:25:01.418134 [DQSOSCAuto] RK0, (LSB)MR18= 0x616, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 420 ps
5765 00:25:01.421113 CH1 RK0: MR19=505, MR18=616
5766 00:25:01.428439 CH1_RK0: MR19=0x505, MR18=0x616, DQSOSC=414, MR23=63, INC=63, DEC=42
5767 00:25:01.428516
5768 00:25:01.431590 ----->DramcWriteLeveling(PI) begin...
5769 00:25:01.431694 ==
5770 00:25:01.434447 Dram Type= 6, Freq= 0, CH_1, rank 1
5771 00:25:01.437682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 00:25:01.437777 ==
5773 00:25:01.441521 Write leveling (Byte 0): 28 => 28
5774 00:25:01.444484 Write leveling (Byte 1): 31 => 31
5775 00:25:01.447639 DramcWriteLeveling(PI) end<-----
5776 00:25:01.447711
5777 00:25:01.447799 ==
5778 00:25:01.450996 Dram Type= 6, Freq= 0, CH_1, rank 1
5779 00:25:01.457649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 00:25:01.457750 ==
5781 00:25:01.457840 [Gating] SW mode calibration
5782 00:25:01.467341 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5783 00:25:01.470597 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5784 00:25:01.474530 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 00:25:01.480456 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 00:25:01.484067 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 00:25:01.487039 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 00:25:01.493924 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 00:25:01.497234 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 00:25:01.503792 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
5791 00:25:01.507020 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
5792 00:25:01.510593 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5793 00:25:01.517097 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 00:25:01.520054 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 00:25:01.523067 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 00:25:01.529887 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 00:25:01.533120 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 00:25:01.536398 0 15 24 | B1->B0 | 2727 3333 | 0 1 | (0 0) (1 1)
5799 00:25:01.542697 0 15 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5800 00:25:01.546155 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 00:25:01.549407 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 00:25:01.556556 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 00:25:01.559227 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 00:25:01.562995 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 00:25:01.569174 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 00:25:01.572515 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 00:25:01.576117 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5808 00:25:01.582445 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 00:25:01.585365 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 00:25:01.588764 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 00:25:01.595606 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 00:25:01.598669 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 00:25:01.602642 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 00:25:01.609128 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 00:25:01.612564 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 00:25:01.615322 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 00:25:01.621859 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 00:25:01.625385 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 00:25:01.628459 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 00:25:01.635019 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 00:25:01.638291 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 00:25:01.641857 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5823 00:25:01.648703 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5824 00:25:01.651873 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5825 00:25:01.654977 Total UI for P1: 0, mck2ui 16
5826 00:25:01.658167 best dqsien dly found for B0: ( 1, 2, 26)
5827 00:25:01.661587 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 00:25:01.664697 Total UI for P1: 0, mck2ui 16
5829 00:25:01.668029 best dqsien dly found for B1: ( 1, 2, 30)
5830 00:25:01.671240 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5831 00:25:01.674684 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5832 00:25:01.674782
5833 00:25:01.678397 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5834 00:25:01.684869 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5835 00:25:01.684946 [Gating] SW calibration Done
5836 00:25:01.688502 ==
5837 00:25:01.688576 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 00:25:01.694664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 00:25:01.694742 ==
5840 00:25:01.694805 RX Vref Scan: 0
5841 00:25:01.694865
5842 00:25:01.697868 RX Vref 0 -> 0, step: 1
5843 00:25:01.697969
5844 00:25:01.701164 RX Delay -80 -> 252, step: 8
5845 00:25:01.704215 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5846 00:25:01.707891 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5847 00:25:01.711164 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5848 00:25:01.717926 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5849 00:25:01.720683 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5850 00:25:01.724375 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5851 00:25:01.727680 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5852 00:25:01.730974 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5853 00:25:01.734316 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5854 00:25:01.740487 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5855 00:25:01.743808 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5856 00:25:01.747143 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5857 00:25:01.750739 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5858 00:25:01.753809 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5859 00:25:01.760400 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5860 00:25:01.763450 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5861 00:25:01.763525 ==
5862 00:25:01.766834 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 00:25:01.770323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 00:25:01.770420 ==
5865 00:25:01.773990 DQS Delay:
5866 00:25:01.774089 DQS0 = 0, DQS1 = 0
5867 00:25:01.774178 DQM Delay:
5868 00:25:01.776720 DQM0 = 97, DQM1 = 94
5869 00:25:01.776826 DQ Delay:
5870 00:25:01.779948 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5871 00:25:01.783552 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5872 00:25:01.786583 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5873 00:25:01.790356 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5874 00:25:01.790461
5875 00:25:01.790552
5876 00:25:01.793088 ==
5877 00:25:01.793192 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 00:25:01.799695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 00:25:01.799804 ==
5880 00:25:01.799950
5881 00:25:01.800077
5882 00:25:01.803227 TX Vref Scan disable
5883 00:25:01.803330 == TX Byte 0 ==
5884 00:25:01.806830 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5885 00:25:01.813693 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5886 00:25:01.813798 == TX Byte 1 ==
5887 00:25:01.817006 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5888 00:25:01.823019 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5889 00:25:01.823151 ==
5890 00:25:01.826522 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 00:25:01.829867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 00:25:01.829984 ==
5893 00:25:01.830096
5894 00:25:01.830184
5895 00:25:01.832966 TX Vref Scan disable
5896 00:25:01.836303 == TX Byte 0 ==
5897 00:25:01.839795 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5898 00:25:01.842802 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5899 00:25:01.846192 == TX Byte 1 ==
5900 00:25:01.850070 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5901 00:25:01.852576 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5902 00:25:01.852680
5903 00:25:01.856039 [DATLAT]
5904 00:25:01.856155 Freq=933, CH1 RK1
5905 00:25:01.856290
5906 00:25:01.859332 DATLAT Default: 0xb
5907 00:25:01.859454 0, 0xFFFF, sum = 0
5908 00:25:01.862801 1, 0xFFFF, sum = 0
5909 00:25:01.862906 2, 0xFFFF, sum = 0
5910 00:25:01.865914 3, 0xFFFF, sum = 0
5911 00:25:01.866023 4, 0xFFFF, sum = 0
5912 00:25:01.869155 5, 0xFFFF, sum = 0
5913 00:25:01.869263 6, 0xFFFF, sum = 0
5914 00:25:01.872586 7, 0xFFFF, sum = 0
5915 00:25:01.872664 8, 0xFFFF, sum = 0
5916 00:25:01.875976 9, 0xFFFF, sum = 0
5917 00:25:01.876083 10, 0x0, sum = 1
5918 00:25:01.879262 11, 0x0, sum = 2
5919 00:25:01.879367 12, 0x0, sum = 3
5920 00:25:01.882542 13, 0x0, sum = 4
5921 00:25:01.882639 best_step = 11
5922 00:25:01.882726
5923 00:25:01.882826 ==
5924 00:25:01.885872 Dram Type= 6, Freq= 0, CH_1, rank 1
5925 00:25:01.892570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5926 00:25:01.892679 ==
5927 00:25:01.892749 RX Vref Scan: 0
5928 00:25:01.892811
5929 00:25:01.895595 RX Vref 0 -> 0, step: 1
5930 00:25:01.895717
5931 00:25:01.898960 RX Delay -53 -> 252, step: 4
5932 00:25:01.902323 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5933 00:25:01.905637 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5934 00:25:01.912282 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5935 00:25:01.915614 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5936 00:25:01.918979 iDelay=199, Bit 4, Center 98 (3 ~ 194) 192
5937 00:25:01.921985 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5938 00:25:01.925558 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5939 00:25:01.932280 iDelay=199, Bit 7, Center 96 (3 ~ 190) 188
5940 00:25:01.935306 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5941 00:25:01.938442 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5942 00:25:01.942213 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5943 00:25:01.945299 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5944 00:25:01.948526 iDelay=199, Bit 12, Center 98 (7 ~ 190) 184
5945 00:25:01.955459 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5946 00:25:01.959010 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5947 00:25:01.961956 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5948 00:25:01.962032 ==
5949 00:25:01.964814 Dram Type= 6, Freq= 0, CH_1, rank 1
5950 00:25:01.968366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5951 00:25:01.968440 ==
5952 00:25:01.971845 DQS Delay:
5953 00:25:01.971948 DQS0 = 0, DQS1 = 0
5954 00:25:01.974722 DQM Delay:
5955 00:25:01.974827 DQM0 = 97, DQM1 = 92
5956 00:25:01.974921 DQ Delay:
5957 00:25:01.978094 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =92
5958 00:25:01.981773 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =96
5959 00:25:01.984984 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =86
5960 00:25:01.991560 DQ12 =98, DQ13 =100, DQ14 =98, DQ15 =100
5961 00:25:01.991643
5962 00:25:01.991708
5963 00:25:01.997760 [DQSOSCAuto] RK1, (LSB)MR18= 0xc22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5964 00:25:02.001072 CH1 RK1: MR19=505, MR18=C22
5965 00:25:02.007901 CH1_RK1: MR19=0x505, MR18=0xC22, DQSOSC=411, MR23=63, INC=64, DEC=42
5966 00:25:02.011028 [RxdqsGatingPostProcess] freq 933
5967 00:25:02.014187 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5968 00:25:02.017811 best DQS0 dly(2T, 0.5T) = (0, 10)
5969 00:25:02.021112 best DQS1 dly(2T, 0.5T) = (0, 10)
5970 00:25:02.024530 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5971 00:25:02.027314 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5972 00:25:02.030664 best DQS0 dly(2T, 0.5T) = (0, 10)
5973 00:25:02.033988 best DQS1 dly(2T, 0.5T) = (0, 10)
5974 00:25:02.037352 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5975 00:25:02.040807 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5976 00:25:02.044002 Pre-setting of DQS Precalculation
5977 00:25:02.047546 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5978 00:25:02.057303 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5979 00:25:02.063742 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5980 00:25:02.063850
5981 00:25:02.063975
5982 00:25:02.067030 [Calibration Summary] 1866 Mbps
5983 00:25:02.067125 CH 0, Rank 0
5984 00:25:02.070348 SW Impedance : PASS
5985 00:25:02.070452 DUTY Scan : NO K
5986 00:25:02.074440 ZQ Calibration : PASS
5987 00:25:02.077128 Jitter Meter : NO K
5988 00:25:02.077232 CBT Training : PASS
5989 00:25:02.080286 Write leveling : PASS
5990 00:25:02.084136 RX DQS gating : PASS
5991 00:25:02.084213 RX DQ/DQS(RDDQC) : PASS
5992 00:25:02.086673 TX DQ/DQS : PASS
5993 00:25:02.090482 RX DATLAT : PASS
5994 00:25:02.090552 RX DQ/DQS(Engine): PASS
5995 00:25:02.093969 TX OE : NO K
5996 00:25:02.094067 All Pass.
5997 00:25:02.094156
5998 00:25:02.096563 CH 0, Rank 1
5999 00:25:02.096665 SW Impedance : PASS
6000 00:25:02.099990 DUTY Scan : NO K
6001 00:25:02.103148 ZQ Calibration : PASS
6002 00:25:02.103257 Jitter Meter : NO K
6003 00:25:02.106270 CBT Training : PASS
6004 00:25:02.110097 Write leveling : PASS
6005 00:25:02.110172 RX DQS gating : PASS
6006 00:25:02.113152 RX DQ/DQS(RDDQC) : PASS
6007 00:25:02.113222 TX DQ/DQS : PASS
6008 00:25:02.116226 RX DATLAT : PASS
6009 00:25:02.120061 RX DQ/DQS(Engine): PASS
6010 00:25:02.120133 TX OE : NO K
6011 00:25:02.122959 All Pass.
6012 00:25:02.123053
6013 00:25:02.123151 CH 1, Rank 0
6014 00:25:02.127239 SW Impedance : PASS
6015 00:25:02.127345 DUTY Scan : NO K
6016 00:25:02.130318 ZQ Calibration : PASS
6017 00:25:02.133494 Jitter Meter : NO K
6018 00:25:02.133601 CBT Training : PASS
6019 00:25:02.136510 Write leveling : PASS
6020 00:25:02.139594 RX DQS gating : PASS
6021 00:25:02.139669 RX DQ/DQS(RDDQC) : PASS
6022 00:25:02.143034 TX DQ/DQS : PASS
6023 00:25:02.145980 RX DATLAT : PASS
6024 00:25:02.146052 RX DQ/DQS(Engine): PASS
6025 00:25:02.149713 TX OE : NO K
6026 00:25:02.149791 All Pass.
6027 00:25:02.149861
6028 00:25:02.152653 CH 1, Rank 1
6029 00:25:02.152752 SW Impedance : PASS
6030 00:25:02.156356 DUTY Scan : NO K
6031 00:25:02.159392 ZQ Calibration : PASS
6032 00:25:02.159470 Jitter Meter : NO K
6033 00:25:02.162702 CBT Training : PASS
6034 00:25:02.166072 Write leveling : PASS
6035 00:25:02.166160 RX DQS gating : PASS
6036 00:25:02.169442 RX DQ/DQS(RDDQC) : PASS
6037 00:25:02.173034 TX DQ/DQS : PASS
6038 00:25:02.173116 RX DATLAT : PASS
6039 00:25:02.175664 RX DQ/DQS(Engine): PASS
6040 00:25:02.179261 TX OE : NO K
6041 00:25:02.179343 All Pass.
6042 00:25:02.179408
6043 00:25:02.179469 DramC Write-DBI off
6044 00:25:02.182700 PER_BANK_REFRESH: Hybrid Mode
6045 00:25:02.185676 TX_TRACKING: ON
6046 00:25:02.192620 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6047 00:25:02.195590 [FAST_K] Save calibration result to emmc
6048 00:25:02.202120 dramc_set_vcore_voltage set vcore to 650000
6049 00:25:02.202202 Read voltage for 400, 6
6050 00:25:02.205286 Vio18 = 0
6051 00:25:02.205367 Vcore = 650000
6052 00:25:02.205432 Vdram = 0
6053 00:25:02.208724 Vddq = 0
6054 00:25:02.208805 Vmddr = 0
6055 00:25:02.212094 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6056 00:25:02.219155 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6057 00:25:02.222022 MEM_TYPE=3, freq_sel=20
6058 00:25:02.225635 sv_algorithm_assistance_LP4_800
6059 00:25:02.229171 ============ PULL DRAM RESETB DOWN ============
6060 00:25:02.232004 ========== PULL DRAM RESETB DOWN end =========
6061 00:25:02.235243 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6062 00:25:02.239163 ===================================
6063 00:25:02.242101 LPDDR4 DRAM CONFIGURATION
6064 00:25:02.245073 ===================================
6065 00:25:02.248393 EX_ROW_EN[0] = 0x0
6066 00:25:02.248484 EX_ROW_EN[1] = 0x0
6067 00:25:02.251491 LP4Y_EN = 0x0
6068 00:25:02.251572 WORK_FSP = 0x0
6069 00:25:02.254719 WL = 0x2
6070 00:25:02.254800 RL = 0x2
6071 00:25:02.258068 BL = 0x2
6072 00:25:02.261677 RPST = 0x0
6073 00:25:02.261758 RD_PRE = 0x0
6074 00:25:02.264700 WR_PRE = 0x1
6075 00:25:02.264781 WR_PST = 0x0
6076 00:25:02.268068 DBI_WR = 0x0
6077 00:25:02.268149 DBI_RD = 0x0
6078 00:25:02.271165 OTF = 0x1
6079 00:25:02.275152 ===================================
6080 00:25:02.277967 ===================================
6081 00:25:02.278073 ANA top config
6082 00:25:02.281473 ===================================
6083 00:25:02.284549 DLL_ASYNC_EN = 0
6084 00:25:02.288221 ALL_SLAVE_EN = 1
6085 00:25:02.288302 NEW_RANK_MODE = 1
6086 00:25:02.291619 DLL_IDLE_MODE = 1
6087 00:25:02.294718 LP45_APHY_COMB_EN = 1
6088 00:25:02.297991 TX_ODT_DIS = 1
6089 00:25:02.298073 NEW_8X_MODE = 1
6090 00:25:02.301634 ===================================
6091 00:25:02.304629 ===================================
6092 00:25:02.307701 data_rate = 800
6093 00:25:02.311045 CKR = 1
6094 00:25:02.314503 DQ_P2S_RATIO = 4
6095 00:25:02.317645 ===================================
6096 00:25:02.321159 CA_P2S_RATIO = 4
6097 00:25:02.324474 DQ_CA_OPEN = 0
6098 00:25:02.327632 DQ_SEMI_OPEN = 1
6099 00:25:02.327714 CA_SEMI_OPEN = 1
6100 00:25:02.330729 CA_FULL_RATE = 0
6101 00:25:02.334330 DQ_CKDIV4_EN = 0
6102 00:25:02.337545 CA_CKDIV4_EN = 1
6103 00:25:02.340729 CA_PREDIV_EN = 0
6104 00:25:02.344628 PH8_DLY = 0
6105 00:25:02.344707 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6106 00:25:02.347676 DQ_AAMCK_DIV = 0
6107 00:25:02.350976 CA_AAMCK_DIV = 0
6108 00:25:02.354148 CA_ADMCK_DIV = 4
6109 00:25:02.357481 DQ_TRACK_CA_EN = 0
6110 00:25:02.361197 CA_PICK = 800
6111 00:25:02.363847 CA_MCKIO = 400
6112 00:25:02.363963 MCKIO_SEMI = 400
6113 00:25:02.367202 PLL_FREQ = 3016
6114 00:25:02.370558 DQ_UI_PI_RATIO = 32
6115 00:25:02.373950 CA_UI_PI_RATIO = 32
6116 00:25:02.377020 ===================================
6117 00:25:02.380166 ===================================
6118 00:25:02.383633 memory_type:LPDDR4
6119 00:25:02.383740 GP_NUM : 10
6120 00:25:02.387206 SRAM_EN : 1
6121 00:25:02.390542 MD32_EN : 0
6122 00:25:02.393778 ===================================
6123 00:25:02.393886 [ANA_INIT] >>>>>>>>>>>>>>
6124 00:25:02.396672 <<<<<< [CONFIGURE PHASE]: ANA_TX
6125 00:25:02.400171 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6126 00:25:02.403470 ===================================
6127 00:25:02.406559 data_rate = 800,PCW = 0X7400
6128 00:25:02.410555 ===================================
6129 00:25:02.413599 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6130 00:25:02.419795 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6131 00:25:02.429889 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6132 00:25:02.436155 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6133 00:25:02.439540 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6134 00:25:02.443126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6135 00:25:02.443213 [ANA_INIT] flow start
6136 00:25:02.446249 [ANA_INIT] PLL >>>>>>>>
6137 00:25:02.449477 [ANA_INIT] PLL <<<<<<<<
6138 00:25:02.449580 [ANA_INIT] MIDPI >>>>>>>>
6139 00:25:02.452807 [ANA_INIT] MIDPI <<<<<<<<
6140 00:25:02.456387 [ANA_INIT] DLL >>>>>>>>
6141 00:25:02.456491 [ANA_INIT] flow end
6142 00:25:02.462745 ============ LP4 DIFF to SE enter ============
6143 00:25:02.466271 ============ LP4 DIFF to SE exit ============
6144 00:25:02.469288 [ANA_INIT] <<<<<<<<<<<<<
6145 00:25:02.472489 [Flow] Enable top DCM control >>>>>
6146 00:25:02.475752 [Flow] Enable top DCM control <<<<<
6147 00:25:02.479555 Enable DLL master slave shuffle
6148 00:25:02.482528 ==============================================================
6149 00:25:02.485856 Gating Mode config
6150 00:25:02.489112 ==============================================================
6151 00:25:02.492556 Config description:
6152 00:25:02.502716 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6153 00:25:02.509292 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6154 00:25:02.512136 SELPH_MODE 0: By rank 1: By Phase
6155 00:25:02.518502 ==============================================================
6156 00:25:02.521891 GAT_TRACK_EN = 0
6157 00:25:02.525820 RX_GATING_MODE = 2
6158 00:25:02.528975 RX_GATING_TRACK_MODE = 2
6159 00:25:02.531898 SELPH_MODE = 1
6160 00:25:02.535435 PICG_EARLY_EN = 1
6161 00:25:02.538306 VALID_LAT_VALUE = 1
6162 00:25:02.541761 ==============================================================
6163 00:25:02.544964 Enter into Gating configuration >>>>
6164 00:25:02.548208 Exit from Gating configuration <<<<
6165 00:25:02.551922 Enter into DVFS_PRE_config >>>>>
6166 00:25:02.564789 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6167 00:25:02.568106 Exit from DVFS_PRE_config <<<<<
6168 00:25:02.571624 Enter into PICG configuration >>>>
6169 00:25:02.571727 Exit from PICG configuration <<<<
6170 00:25:02.574316 [RX_INPUT] configuration >>>>>
6171 00:25:02.577575 [RX_INPUT] configuration <<<<<
6172 00:25:02.584431 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6173 00:25:02.587591 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6174 00:25:02.594248 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6175 00:25:02.600900 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6176 00:25:02.607223 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6177 00:25:02.614136 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6178 00:25:02.617448 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6179 00:25:02.620581 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6180 00:25:02.627632 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6181 00:25:02.630428 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6182 00:25:02.633945 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6183 00:25:02.637122 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6184 00:25:02.641026 ===================================
6185 00:25:02.644189 LPDDR4 DRAM CONFIGURATION
6186 00:25:02.647187 ===================================
6187 00:25:02.650583 EX_ROW_EN[0] = 0x0
6188 00:25:02.650657 EX_ROW_EN[1] = 0x0
6189 00:25:02.653912 LP4Y_EN = 0x0
6190 00:25:02.654009 WORK_FSP = 0x0
6191 00:25:02.656910 WL = 0x2
6192 00:25:02.656989 RL = 0x2
6193 00:25:02.659879 BL = 0x2
6194 00:25:02.663485 RPST = 0x0
6195 00:25:02.663558 RD_PRE = 0x0
6196 00:25:02.666524 WR_PRE = 0x1
6197 00:25:02.666591 WR_PST = 0x0
6198 00:25:02.670435 DBI_WR = 0x0
6199 00:25:02.670515 DBI_RD = 0x0
6200 00:25:02.673589 OTF = 0x1
6201 00:25:02.676761 ===================================
6202 00:25:02.680080 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6203 00:25:02.683534 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6204 00:25:02.686558 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6205 00:25:02.690129 ===================================
6206 00:25:02.693029 LPDDR4 DRAM CONFIGURATION
6207 00:25:02.696458 ===================================
6208 00:25:02.699812 EX_ROW_EN[0] = 0x10
6209 00:25:02.699900 EX_ROW_EN[1] = 0x0
6210 00:25:02.703226 LP4Y_EN = 0x0
6211 00:25:02.706351 WORK_FSP = 0x0
6212 00:25:02.706456 WL = 0x2
6213 00:25:02.709638 RL = 0x2
6214 00:25:02.709740 BL = 0x2
6215 00:25:02.713065 RPST = 0x0
6216 00:25:02.713163 RD_PRE = 0x0
6217 00:25:02.715970 WR_PRE = 0x1
6218 00:25:02.716051 WR_PST = 0x0
6219 00:25:02.719062 DBI_WR = 0x0
6220 00:25:02.719164 DBI_RD = 0x0
6221 00:25:02.722727 OTF = 0x1
6222 00:25:02.726070 ===================================
6223 00:25:02.732557 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6224 00:25:02.735754 nWR fixed to 30
6225 00:25:02.735836 [ModeRegInit_LP4] CH0 RK0
6226 00:25:02.739353 [ModeRegInit_LP4] CH0 RK1
6227 00:25:02.742590 [ModeRegInit_LP4] CH1 RK0
6228 00:25:02.745803 [ModeRegInit_LP4] CH1 RK1
6229 00:25:02.745874 match AC timing 19
6230 00:25:02.752670 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6231 00:25:02.756235 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6232 00:25:02.759057 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6233 00:25:02.765397 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6234 00:25:02.768957 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6235 00:25:02.769055 ==
6236 00:25:02.772048 Dram Type= 6, Freq= 0, CH_0, rank 0
6237 00:25:02.776230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6238 00:25:02.776333 ==
6239 00:25:02.781808 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6240 00:25:02.788908 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6241 00:25:02.791791 [CA 0] Center 36 (8~64) winsize 57
6242 00:25:02.795134 [CA 1] Center 36 (8~64) winsize 57
6243 00:25:02.795250 [CA 2] Center 36 (8~64) winsize 57
6244 00:25:02.798847 [CA 3] Center 36 (8~64) winsize 57
6245 00:25:02.801653 [CA 4] Center 36 (8~64) winsize 57
6246 00:25:02.805406 [CA 5] Center 36 (8~64) winsize 57
6247 00:25:02.805489
6248 00:25:02.808303 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6249 00:25:02.811473
6250 00:25:02.815063 [CATrainingPosCal] consider 1 rank data
6251 00:25:02.818346 u2DelayCellTimex100 = 270/100 ps
6252 00:25:02.821664 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 00:25:02.824613 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 00:25:02.827858 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 00:25:02.831419 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 00:25:02.834838 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 00:25:02.838097 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 00:25:02.838209
6259 00:25:02.841193 CA PerBit enable=1, Macro0, CA PI delay=36
6260 00:25:02.841295
6261 00:25:02.844323 [CBTSetCACLKResult] CA Dly = 36
6262 00:25:02.848107 CS Dly: 1 (0~32)
6263 00:25:02.848219 ==
6264 00:25:02.851191 Dram Type= 6, Freq= 0, CH_0, rank 1
6265 00:25:02.854480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 00:25:02.854562 ==
6267 00:25:02.861155 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6268 00:25:02.867395 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6269 00:25:02.871347 [CA 0] Center 36 (8~64) winsize 57
6270 00:25:02.871431 [CA 1] Center 36 (8~64) winsize 57
6271 00:25:02.874146 [CA 2] Center 36 (8~64) winsize 57
6272 00:25:02.877605 [CA 3] Center 36 (8~64) winsize 57
6273 00:25:02.881083 [CA 4] Center 36 (8~64) winsize 57
6274 00:25:02.883955 [CA 5] Center 36 (8~64) winsize 57
6275 00:25:02.884038
6276 00:25:02.887487 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6277 00:25:02.887571
6278 00:25:02.893986 [CATrainingPosCal] consider 2 rank data
6279 00:25:02.894069 u2DelayCellTimex100 = 270/100 ps
6280 00:25:02.900428 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 00:25:02.903896 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 00:25:02.907009 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 00:25:02.910130 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 00:25:02.914236 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 00:25:02.917153 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 00:25:02.917258
6287 00:25:02.920831 CA PerBit enable=1, Macro0, CA PI delay=36
6288 00:25:02.920943
6289 00:25:02.924165 [CBTSetCACLKResult] CA Dly = 36
6290 00:25:02.926621 CS Dly: 1 (0~32)
6291 00:25:02.926761
6292 00:25:02.930338 ----->DramcWriteLeveling(PI) begin...
6293 00:25:02.930431 ==
6294 00:25:02.933554 Dram Type= 6, Freq= 0, CH_0, rank 0
6295 00:25:02.936878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 00:25:02.936965 ==
6297 00:25:02.940089 Write leveling (Byte 0): 40 => 8
6298 00:25:02.943447 Write leveling (Byte 1): 40 => 8
6299 00:25:02.947688 DramcWriteLeveling(PI) end<-----
6300 00:25:02.947787
6301 00:25:02.947878 ==
6302 00:25:02.949732 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 00:25:02.953276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 00:25:02.953373 ==
6305 00:25:02.956278 [Gating] SW mode calibration
6306 00:25:02.963213 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6307 00:25:02.969832 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6308 00:25:02.972874 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6309 00:25:02.976479 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6310 00:25:02.983153 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6311 00:25:02.986549 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6312 00:25:02.989868 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6313 00:25:02.995875 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6314 00:25:02.999447 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6315 00:25:03.002772 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6316 00:25:03.009050 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6317 00:25:03.012849 Total UI for P1: 0, mck2ui 16
6318 00:25:03.015846 best dqsien dly found for B0: ( 0, 14, 24)
6319 00:25:03.019208 Total UI for P1: 0, mck2ui 16
6320 00:25:03.022224 best dqsien dly found for B1: ( 0, 14, 24)
6321 00:25:03.025632 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6322 00:25:03.029188 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6323 00:25:03.029263
6324 00:25:03.032764 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6325 00:25:03.035729 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6326 00:25:03.039168 [Gating] SW calibration Done
6327 00:25:03.039280 ==
6328 00:25:03.042167 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 00:25:03.045601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 00:25:03.045705 ==
6331 00:25:03.048870 RX Vref Scan: 0
6332 00:25:03.048948
6333 00:25:03.052360 RX Vref 0 -> 0, step: 1
6334 00:25:03.052430
6335 00:25:03.055125 RX Delay -410 -> 252, step: 16
6336 00:25:03.059110 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6337 00:25:03.061839 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6338 00:25:03.065214 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6339 00:25:03.072145 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6340 00:25:03.075554 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6341 00:25:03.078295 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6342 00:25:03.081881 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6343 00:25:03.088588 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6344 00:25:03.091156 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6345 00:25:03.094592 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6346 00:25:03.098051 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6347 00:25:03.104515 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6348 00:25:03.107881 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6349 00:25:03.111799 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6350 00:25:03.117841 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6351 00:25:03.121181 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6352 00:25:03.121264 ==
6353 00:25:03.125038 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 00:25:03.128385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 00:25:03.128468 ==
6356 00:25:03.130739 DQS Delay:
6357 00:25:03.130822 DQS0 = 35, DQS1 = 51
6358 00:25:03.130886 DQM Delay:
6359 00:25:03.134630 DQM0 = 5, DQM1 = 9
6360 00:25:03.134713 DQ Delay:
6361 00:25:03.137579 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6362 00:25:03.141091 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6363 00:25:03.144679 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6364 00:25:03.148063 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6365 00:25:03.148171
6366 00:25:03.148263
6367 00:25:03.148352 ==
6368 00:25:03.150816 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 00:25:03.154203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 00:25:03.157442 ==
6371 00:25:03.157551
6372 00:25:03.157642
6373 00:25:03.157738 TX Vref Scan disable
6374 00:25:03.160962 == TX Byte 0 ==
6375 00:25:03.163983 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 00:25:03.167474 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 00:25:03.170777 == TX Byte 1 ==
6378 00:25:03.174280 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6379 00:25:03.177655 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6380 00:25:03.177756 ==
6381 00:25:03.180329 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 00:25:03.186953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 00:25:03.187070 ==
6384 00:25:03.187164
6385 00:25:03.187252
6386 00:25:03.187341 TX Vref Scan disable
6387 00:25:03.190507 == TX Byte 0 ==
6388 00:25:03.193360 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6389 00:25:03.196815 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6390 00:25:03.200086 == TX Byte 1 ==
6391 00:25:03.203714 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6392 00:25:03.206404 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6393 00:25:03.206493
6394 00:25:03.210494 [DATLAT]
6395 00:25:03.210567 Freq=400, CH0 RK0
6396 00:25:03.210628
6397 00:25:03.213040 DATLAT Default: 0xf
6398 00:25:03.213111 0, 0xFFFF, sum = 0
6399 00:25:03.217095 1, 0xFFFF, sum = 0
6400 00:25:03.217181 2, 0xFFFF, sum = 0
6401 00:25:03.220036 3, 0xFFFF, sum = 0
6402 00:25:03.220160 4, 0xFFFF, sum = 0
6403 00:25:03.222923 5, 0xFFFF, sum = 0
6404 00:25:03.223004 6, 0xFFFF, sum = 0
6405 00:25:03.227068 7, 0xFFFF, sum = 0
6406 00:25:03.227214 8, 0xFFFF, sum = 0
6407 00:25:03.230040 9, 0xFFFF, sum = 0
6408 00:25:03.233349 10, 0xFFFF, sum = 0
6409 00:25:03.233431 11, 0xFFFF, sum = 0
6410 00:25:03.236501 12, 0xFFFF, sum = 0
6411 00:25:03.236582 13, 0x0, sum = 1
6412 00:25:03.239799 14, 0x0, sum = 2
6413 00:25:03.239931 15, 0x0, sum = 3
6414 00:25:03.242875 16, 0x0, sum = 4
6415 00:25:03.242987 best_step = 14
6416 00:25:03.243051
6417 00:25:03.243111 ==
6418 00:25:03.246615 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 00:25:03.249743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 00:25:03.249824 ==
6421 00:25:03.252889 RX Vref Scan: 1
6422 00:25:03.252977
6423 00:25:03.255926 RX Vref 0 -> 0, step: 1
6424 00:25:03.256056
6425 00:25:03.256149 RX Delay -343 -> 252, step: 8
6426 00:25:03.256238
6427 00:25:03.259551 Set Vref, RX VrefLevel [Byte0]: 52
6428 00:25:03.262667 [Byte1]: 49
6429 00:25:03.268128
6430 00:25:03.268208 Final RX Vref Byte 0 = 52 to rank0
6431 00:25:03.272067 Final RX Vref Byte 1 = 49 to rank0
6432 00:25:03.274798 Final RX Vref Byte 0 = 52 to rank1
6433 00:25:03.277954 Final RX Vref Byte 1 = 49 to rank1==
6434 00:25:03.281516 Dram Type= 6, Freq= 0, CH_0, rank 0
6435 00:25:03.287816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 00:25:03.287943 ==
6437 00:25:03.288025 DQS Delay:
6438 00:25:03.291590 DQS0 = 44, DQS1 = 56
6439 00:25:03.291670 DQM Delay:
6440 00:25:03.291734 DQM0 = 10, DQM1 = 13
6441 00:25:03.294645 DQ Delay:
6442 00:25:03.297966 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6443 00:25:03.301357 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6444 00:25:03.301474 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6445 00:25:03.304949 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6446 00:25:03.307700
6447 00:25:03.307800
6448 00:25:03.314927 [DQSOSCAuto] RK0, (LSB)MR18= 0x9a8d, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6449 00:25:03.317686 CH0 RK0: MR19=C0C, MR18=9A8D
6450 00:25:03.324568 CH0_RK0: MR19=0xC0C, MR18=0x9A8D, DQSOSC=390, MR23=63, INC=388, DEC=258
6451 00:25:03.324650 ==
6452 00:25:03.327328 Dram Type= 6, Freq= 0, CH_0, rank 1
6453 00:25:03.330774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 00:25:03.330855 ==
6455 00:25:03.334099 [Gating] SW mode calibration
6456 00:25:03.341483 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6457 00:25:03.347814 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6458 00:25:03.350574 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6459 00:25:03.354315 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6460 00:25:03.361317 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6461 00:25:03.363857 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6462 00:25:03.367274 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6463 00:25:03.373384 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6464 00:25:03.376953 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6465 00:25:03.380348 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6466 00:25:03.386851 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6467 00:25:03.390192 Total UI for P1: 0, mck2ui 16
6468 00:25:03.393522 best dqsien dly found for B0: ( 0, 14, 24)
6469 00:25:03.396905 Total UI for P1: 0, mck2ui 16
6470 00:25:03.400251 best dqsien dly found for B1: ( 0, 14, 24)
6471 00:25:03.403252 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6472 00:25:03.406553 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6473 00:25:03.406633
6474 00:25:03.410579 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6475 00:25:03.413099 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6476 00:25:03.416523 [Gating] SW calibration Done
6477 00:25:03.416604 ==
6478 00:25:03.419854 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 00:25:03.423465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 00:25:03.423546 ==
6481 00:25:03.426346 RX Vref Scan: 0
6482 00:25:03.426427
6483 00:25:03.430059 RX Vref 0 -> 0, step: 1
6484 00:25:03.430140
6485 00:25:03.430205 RX Delay -410 -> 252, step: 16
6486 00:25:03.436300 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6487 00:25:03.439756 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6488 00:25:03.443368 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6489 00:25:03.449584 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6490 00:25:03.452818 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6491 00:25:03.456087 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6492 00:25:03.459778 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6493 00:25:03.466518 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6494 00:25:03.469277 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6495 00:25:03.472811 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6496 00:25:03.476044 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6497 00:25:03.482728 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6498 00:25:03.486305 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6499 00:25:03.488969 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6500 00:25:03.492336 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6501 00:25:03.499113 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6502 00:25:03.499201 ==
6503 00:25:03.502573 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 00:25:03.505690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 00:25:03.505769 ==
6506 00:25:03.505832 DQS Delay:
6507 00:25:03.509270 DQS0 = 35, DQS1 = 51
6508 00:25:03.509340 DQM Delay:
6509 00:25:03.512140 DQM0 = 8, DQM1 = 10
6510 00:25:03.512220 DQ Delay:
6511 00:25:03.515412 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6512 00:25:03.519565 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6513 00:25:03.522265 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6514 00:25:03.525504 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6515 00:25:03.525590
6516 00:25:03.525653
6517 00:25:03.525712 ==
6518 00:25:03.528871 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 00:25:03.531935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 00:25:03.532055 ==
6521 00:25:03.535800
6522 00:25:03.535911
6523 00:25:03.535979 TX Vref Scan disable
6524 00:25:03.538418 == TX Byte 0 ==
6525 00:25:03.541684 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6526 00:25:03.545015 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6527 00:25:03.548255 == TX Byte 1 ==
6528 00:25:03.551462 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6529 00:25:03.555206 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6530 00:25:03.555307 ==
6531 00:25:03.558569 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 00:25:03.561950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 00:25:03.565338 ==
6534 00:25:03.565418
6535 00:25:03.565481
6536 00:25:03.565540 TX Vref Scan disable
6537 00:25:03.568166 == TX Byte 0 ==
6538 00:25:03.572064 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6539 00:25:03.574712 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6540 00:25:03.578128 == TX Byte 1 ==
6541 00:25:03.582326 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6542 00:25:03.585068 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6543 00:25:03.585148
6544 00:25:03.588149 [DATLAT]
6545 00:25:03.588228 Freq=400, CH0 RK1
6546 00:25:03.588291
6547 00:25:03.591411 DATLAT Default: 0xe
6548 00:25:03.591490 0, 0xFFFF, sum = 0
6549 00:25:03.594586 1, 0xFFFF, sum = 0
6550 00:25:03.594667 2, 0xFFFF, sum = 0
6551 00:25:03.598100 3, 0xFFFF, sum = 0
6552 00:25:03.598181 4, 0xFFFF, sum = 0
6553 00:25:03.601624 5, 0xFFFF, sum = 0
6554 00:25:03.601705 6, 0xFFFF, sum = 0
6555 00:25:03.604410 7, 0xFFFF, sum = 0
6556 00:25:03.604491 8, 0xFFFF, sum = 0
6557 00:25:03.608058 9, 0xFFFF, sum = 0
6558 00:25:03.608138 10, 0xFFFF, sum = 0
6559 00:25:03.610929 11, 0xFFFF, sum = 0
6560 00:25:03.614035 12, 0xFFFF, sum = 0
6561 00:25:03.614143 13, 0x0, sum = 1
6562 00:25:03.614236 14, 0x0, sum = 2
6563 00:25:03.617703 15, 0x0, sum = 3
6564 00:25:03.617784 16, 0x0, sum = 4
6565 00:25:03.620940 best_step = 14
6566 00:25:03.621020
6567 00:25:03.621083 ==
6568 00:25:03.624317 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 00:25:03.627437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 00:25:03.627546 ==
6571 00:25:03.630593 RX Vref Scan: 0
6572 00:25:03.630695
6573 00:25:03.630787 RX Vref 0 -> 0, step: 1
6574 00:25:03.634005
6575 00:25:03.634106 RX Delay -343 -> 252, step: 8
6576 00:25:03.642752 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6577 00:25:03.645722 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6578 00:25:03.649117 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6579 00:25:03.655934 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6580 00:25:03.658779 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6581 00:25:03.662029 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6582 00:25:03.665662 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6583 00:25:03.672147 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6584 00:25:03.675293 iDelay=209, Bit 8, Center -56 (-303 ~ 192) 496
6585 00:25:03.678815 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6586 00:25:03.682615 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6587 00:25:03.688560 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6588 00:25:03.691968 iDelay=209, Bit 12, Center -40 (-279 ~ 200) 480
6589 00:25:03.695321 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6590 00:25:03.698453 iDelay=209, Bit 14, Center -32 (-271 ~ 208) 480
6591 00:25:03.704925 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6592 00:25:03.705003 ==
6593 00:25:03.708813 Dram Type= 6, Freq= 0, CH_0, rank 1
6594 00:25:03.711616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 00:25:03.711723 ==
6596 00:25:03.711814 DQS Delay:
6597 00:25:03.715096 DQS0 = 44, DQS1 = 60
6598 00:25:03.715195 DQM Delay:
6599 00:25:03.718609 DQM0 = 9, DQM1 = 14
6600 00:25:03.718711 DQ Delay:
6601 00:25:03.721256 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6602 00:25:03.724680 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6603 00:25:03.727690 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6604 00:25:03.731317 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =20
6605 00:25:03.731420
6606 00:25:03.731487
6607 00:25:03.741260 [DQSOSCAuto] RK1, (LSB)MR18= 0x8680, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6608 00:25:03.741355 CH0 RK1: MR19=C0C, MR18=8680
6609 00:25:03.748143 CH0_RK1: MR19=0xC0C, MR18=0x8680, DQSOSC=393, MR23=63, INC=382, DEC=254
6610 00:25:03.750829 [RxdqsGatingPostProcess] freq 400
6611 00:25:03.757603 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6612 00:25:03.760980 best DQS0 dly(2T, 0.5T) = (0, 10)
6613 00:25:03.764084 best DQS1 dly(2T, 0.5T) = (0, 10)
6614 00:25:03.767483 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6615 00:25:03.770459 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6616 00:25:03.774748 best DQS0 dly(2T, 0.5T) = (0, 10)
6617 00:25:03.776963 best DQS1 dly(2T, 0.5T) = (0, 10)
6618 00:25:03.780581 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6619 00:25:03.783914 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6620 00:25:03.784034 Pre-setting of DQS Precalculation
6621 00:25:03.790950 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6622 00:25:03.791050 ==
6623 00:25:03.793972 Dram Type= 6, Freq= 0, CH_1, rank 0
6624 00:25:03.796853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 00:25:03.796971 ==
6626 00:25:03.803461 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6627 00:25:03.810097 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6628 00:25:03.813695 [CA 0] Center 36 (8~64) winsize 57
6629 00:25:03.816747 [CA 1] Center 36 (8~64) winsize 57
6630 00:25:03.820463 [CA 2] Center 36 (8~64) winsize 57
6631 00:25:03.823894 [CA 3] Center 36 (8~64) winsize 57
6632 00:25:03.826937 [CA 4] Center 36 (8~64) winsize 57
6633 00:25:03.827009 [CA 5] Center 36 (8~64) winsize 57
6634 00:25:03.829953
6635 00:25:03.833584 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6636 00:25:03.833686
6637 00:25:03.836797 [CATrainingPosCal] consider 1 rank data
6638 00:25:03.839474 u2DelayCellTimex100 = 270/100 ps
6639 00:25:03.843100 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 00:25:03.847183 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 00:25:03.849392 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 00:25:03.852978 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 00:25:03.856161 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 00:25:03.859294 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 00:25:03.859398
6646 00:25:03.863037 CA PerBit enable=1, Macro0, CA PI delay=36
6647 00:25:03.866218
6648 00:25:03.866299 [CBTSetCACLKResult] CA Dly = 36
6649 00:25:03.869231 CS Dly: 1 (0~32)
6650 00:25:03.869332 ==
6651 00:25:03.872919 Dram Type= 6, Freq= 0, CH_1, rank 1
6652 00:25:03.876273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 00:25:03.876350 ==
6654 00:25:03.882491 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6655 00:25:03.888864 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6656 00:25:03.892194 [CA 0] Center 36 (8~64) winsize 57
6657 00:25:03.895814 [CA 1] Center 36 (8~64) winsize 57
6658 00:25:03.898877 [CA 2] Center 36 (8~64) winsize 57
6659 00:25:03.902393 [CA 3] Center 36 (8~64) winsize 57
6660 00:25:03.905922 [CA 4] Center 36 (8~64) winsize 57
6661 00:25:03.906006 [CA 5] Center 36 (8~64) winsize 57
6662 00:25:03.908890
6663 00:25:03.911838 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6664 00:25:03.911981
6665 00:25:03.915564 [CATrainingPosCal] consider 2 rank data
6666 00:25:03.918765 u2DelayCellTimex100 = 270/100 ps
6667 00:25:03.922030 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 00:25:03.925781 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 00:25:03.928884 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 00:25:03.931778 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 00:25:03.934957 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 00:25:03.938506 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 00:25:03.938601
6674 00:25:03.941604 CA PerBit enable=1, Macro0, CA PI delay=36
6675 00:25:03.941712
6676 00:25:03.945189 [CBTSetCACLKResult] CA Dly = 36
6677 00:25:03.948509 CS Dly: 1 (0~32)
6678 00:25:03.948581
6679 00:25:03.951705 ----->DramcWriteLeveling(PI) begin...
6680 00:25:03.951806 ==
6681 00:25:03.955086 Dram Type= 6, Freq= 0, CH_1, rank 0
6682 00:25:03.958146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 00:25:03.958257 ==
6684 00:25:03.961503 Write leveling (Byte 0): 40 => 8
6685 00:25:03.964899 Write leveling (Byte 1): 40 => 8
6686 00:25:03.968430 DramcWriteLeveling(PI) end<-----
6687 00:25:03.968506
6688 00:25:03.968578 ==
6689 00:25:03.971795 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 00:25:03.974633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 00:25:03.974734 ==
6692 00:25:03.978606 [Gating] SW mode calibration
6693 00:25:03.985010 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6694 00:25:03.991230 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6695 00:25:03.994557 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6696 00:25:04.001078 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6697 00:25:04.004471 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6698 00:25:04.007839 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6699 00:25:04.014379 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6700 00:25:04.017784 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6701 00:25:04.021304 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6702 00:25:04.027362 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6703 00:25:04.030706 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6704 00:25:04.034061 Total UI for P1: 0, mck2ui 16
6705 00:25:04.037383 best dqsien dly found for B0: ( 0, 14, 24)
6706 00:25:04.040611 Total UI for P1: 0, mck2ui 16
6707 00:25:04.043833 best dqsien dly found for B1: ( 0, 14, 24)
6708 00:25:04.047251 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6709 00:25:04.050908 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6710 00:25:04.051013
6711 00:25:04.054420 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6712 00:25:04.057401 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6713 00:25:04.060491 [Gating] SW calibration Done
6714 00:25:04.060591 ==
6715 00:25:04.064020 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 00:25:04.070489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 00:25:04.070590 ==
6718 00:25:04.070680 RX Vref Scan: 0
6719 00:25:04.070780
6720 00:25:04.073614 RX Vref 0 -> 0, step: 1
6721 00:25:04.073718
6722 00:25:04.076969 RX Delay -410 -> 252, step: 16
6723 00:25:04.080121 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6724 00:25:04.083378 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6725 00:25:04.087339 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6726 00:25:04.093668 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6727 00:25:04.097109 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6728 00:25:04.100324 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6729 00:25:04.106513 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6730 00:25:04.109852 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6731 00:25:04.113140 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6732 00:25:04.116519 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6733 00:25:04.123462 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6734 00:25:04.126605 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6735 00:25:04.130256 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6736 00:25:04.133240 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6737 00:25:04.139839 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6738 00:25:04.143372 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6739 00:25:04.143484 ==
6740 00:25:04.147001 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 00:25:04.149744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 00:25:04.149827 ==
6743 00:25:04.153428 DQS Delay:
6744 00:25:04.153508 DQS0 = 35, DQS1 = 51
6745 00:25:04.153572 DQM Delay:
6746 00:25:04.156900 DQM0 = 6, DQM1 = 13
6747 00:25:04.156984 DQ Delay:
6748 00:25:04.159672 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6749 00:25:04.163179 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6750 00:25:04.166383 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6751 00:25:04.169575 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6752 00:25:04.169655
6753 00:25:04.169718
6754 00:25:04.169776 ==
6755 00:25:04.173348 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 00:25:04.177095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 00:25:04.179558 ==
6758 00:25:04.179662
6759 00:25:04.179757
6760 00:25:04.179857 TX Vref Scan disable
6761 00:25:04.183008 == TX Byte 0 ==
6762 00:25:04.186009 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 00:25:04.189470 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 00:25:04.192438 == TX Byte 1 ==
6765 00:25:04.195703 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 00:25:04.199237 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 00:25:04.199315 ==
6768 00:25:04.202397 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 00:25:04.209240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 00:25:04.209331 ==
6771 00:25:04.209405
6772 00:25:04.209554
6773 00:25:04.209643 TX Vref Scan disable
6774 00:25:04.212214 == TX Byte 0 ==
6775 00:25:04.215844 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 00:25:04.219247 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 00:25:04.222376 == TX Byte 1 ==
6778 00:25:04.226311 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 00:25:04.228683 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 00:25:04.232304
6781 00:25:04.232398 [DATLAT]
6782 00:25:04.232462 Freq=400, CH1 RK0
6783 00:25:04.232522
6784 00:25:04.235277 DATLAT Default: 0xf
6785 00:25:04.235357 0, 0xFFFF, sum = 0
6786 00:25:04.238564 1, 0xFFFF, sum = 0
6787 00:25:04.238645 2, 0xFFFF, sum = 0
6788 00:25:04.242117 3, 0xFFFF, sum = 0
6789 00:25:04.242255 4, 0xFFFF, sum = 0
6790 00:25:04.245441 5, 0xFFFF, sum = 0
6791 00:25:04.248867 6, 0xFFFF, sum = 0
6792 00:25:04.248996 7, 0xFFFF, sum = 0
6793 00:25:04.251723 8, 0xFFFF, sum = 0
6794 00:25:04.251804 9, 0xFFFF, sum = 0
6795 00:25:04.254740 10, 0xFFFF, sum = 0
6796 00:25:04.254866 11, 0xFFFF, sum = 0
6797 00:25:04.258647 12, 0xFFFF, sum = 0
6798 00:25:04.258728 13, 0x0, sum = 1
6799 00:25:04.261462 14, 0x0, sum = 2
6800 00:25:04.261544 15, 0x0, sum = 3
6801 00:25:04.264864 16, 0x0, sum = 4
6802 00:25:04.264959 best_step = 14
6803 00:25:04.265037
6804 00:25:04.265126 ==
6805 00:25:04.268147 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 00:25:04.272089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 00:25:04.274631 ==
6808 00:25:04.274711 RX Vref Scan: 1
6809 00:25:04.274776
6810 00:25:04.278555 RX Vref 0 -> 0, step: 1
6811 00:25:04.278634
6812 00:25:04.281771 RX Delay -343 -> 252, step: 8
6813 00:25:04.281877
6814 00:25:04.284692 Set Vref, RX VrefLevel [Byte0]: 53
6815 00:25:04.288059 [Byte1]: 51
6816 00:25:04.288139
6817 00:25:04.291256 Final RX Vref Byte 0 = 53 to rank0
6818 00:25:04.294766 Final RX Vref Byte 1 = 51 to rank0
6819 00:25:04.298145 Final RX Vref Byte 0 = 53 to rank1
6820 00:25:04.301395 Final RX Vref Byte 1 = 51 to rank1==
6821 00:25:04.304646 Dram Type= 6, Freq= 0, CH_1, rank 0
6822 00:25:04.307682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 00:25:04.307763 ==
6824 00:25:04.310892 DQS Delay:
6825 00:25:04.310981 DQS0 = 44, DQS1 = 52
6826 00:25:04.314789 DQM Delay:
6827 00:25:04.314869 DQM0 = 10, DQM1 = 10
6828 00:25:04.317600 DQ Delay:
6829 00:25:04.317680 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6830 00:25:04.320802 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6831 00:25:04.324455 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6832 00:25:04.327819 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6833 00:25:04.327923
6834 00:25:04.328005
6835 00:25:04.337808 [DQSOSCAuto] RK0, (LSB)MR18= 0x668d, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 396 ps
6836 00:25:04.340707 CH1 RK0: MR19=C0C, MR18=668D
6837 00:25:04.344182 CH1_RK0: MR19=0xC0C, MR18=0x668D, DQSOSC=392, MR23=63, INC=384, DEC=256
6838 00:25:04.347719 ==
6839 00:25:04.350625 Dram Type= 6, Freq= 0, CH_1, rank 1
6840 00:25:04.354056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 00:25:04.354148 ==
6842 00:25:04.357289 [Gating] SW mode calibration
6843 00:25:04.364189 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6844 00:25:04.367253 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6845 00:25:04.373664 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6846 00:25:04.377408 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6847 00:25:04.381235 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6848 00:25:04.386986 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6849 00:25:04.390265 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6850 00:25:04.393804 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6851 00:25:04.400200 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6852 00:25:04.403949 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6853 00:25:04.407430 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6854 00:25:04.411150 Total UI for P1: 0, mck2ui 16
6855 00:25:04.413703 best dqsien dly found for B0: ( 0, 14, 24)
6856 00:25:04.416963 Total UI for P1: 0, mck2ui 16
6857 00:25:04.420394 best dqsien dly found for B1: ( 0, 14, 24)
6858 00:25:04.423353 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6859 00:25:04.426758 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6860 00:25:04.430003
6861 00:25:04.433450 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6862 00:25:04.436752 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6863 00:25:04.440478 [Gating] SW calibration Done
6864 00:25:04.440558 ==
6865 00:25:04.443117 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 00:25:04.447259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 00:25:04.447340 ==
6868 00:25:04.449908 RX Vref Scan: 0
6869 00:25:04.450024
6870 00:25:04.450106 RX Vref 0 -> 0, step: 1
6871 00:25:04.450167
6872 00:25:04.453415 RX Delay -410 -> 252, step: 16
6873 00:25:04.456119 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6874 00:25:04.462731 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6875 00:25:04.466341 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6876 00:25:04.469369 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6877 00:25:04.475739 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6878 00:25:04.479385 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6879 00:25:04.483048 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6880 00:25:04.486024 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6881 00:25:04.492727 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6882 00:25:04.496317 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6883 00:25:04.499330 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6884 00:25:04.502497 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6885 00:25:04.508928 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6886 00:25:04.512362 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6887 00:25:04.515590 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6888 00:25:04.518716 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6889 00:25:04.522475 ==
6890 00:25:04.526025 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 00:25:04.529062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 00:25:04.529142 ==
6893 00:25:04.529205 DQS Delay:
6894 00:25:04.531861 DQS0 = 43, DQS1 = 51
6895 00:25:04.531980 DQM Delay:
6896 00:25:04.535594 DQM0 = 11, DQM1 = 14
6897 00:25:04.535673 DQ Delay:
6898 00:25:04.539099 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6899 00:25:04.541918 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6900 00:25:04.545365 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6901 00:25:04.548383 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6902 00:25:04.548467
6903 00:25:04.548551
6904 00:25:04.548613 ==
6905 00:25:04.551844 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 00:25:04.554985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 00:25:04.555066 ==
6908 00:25:04.555130
6909 00:25:04.555189
6910 00:25:04.558639 TX Vref Scan disable
6911 00:25:04.558719 == TX Byte 0 ==
6912 00:25:04.565309 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6913 00:25:04.568409 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6914 00:25:04.568499 == TX Byte 1 ==
6915 00:25:04.574944 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6916 00:25:04.578235 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6917 00:25:04.578315 ==
6918 00:25:04.581792 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 00:25:04.584879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 00:25:04.584960 ==
6921 00:25:04.585024
6922 00:25:04.585083
6923 00:25:04.587934 TX Vref Scan disable
6924 00:25:04.591256 == TX Byte 0 ==
6925 00:25:04.594607 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6926 00:25:04.598174 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6927 00:25:04.598252 == TX Byte 1 ==
6928 00:25:04.604656 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6929 00:25:04.608038 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6930 00:25:04.608111
6931 00:25:04.608175 [DATLAT]
6932 00:25:04.611203 Freq=400, CH1 RK1
6933 00:25:04.611276
6934 00:25:04.611337 DATLAT Default: 0xe
6935 00:25:04.614108 0, 0xFFFF, sum = 0
6936 00:25:04.614188 1, 0xFFFF, sum = 0
6937 00:25:04.618016 2, 0xFFFF, sum = 0
6938 00:25:04.618125 3, 0xFFFF, sum = 0
6939 00:25:04.621044 4, 0xFFFF, sum = 0
6940 00:25:04.624895 5, 0xFFFF, sum = 0
6941 00:25:04.624977 6, 0xFFFF, sum = 0
6942 00:25:04.627624 7, 0xFFFF, sum = 0
6943 00:25:04.627742 8, 0xFFFF, sum = 0
6944 00:25:04.630915 9, 0xFFFF, sum = 0
6945 00:25:04.631025 10, 0xFFFF, sum = 0
6946 00:25:04.634272 11, 0xFFFF, sum = 0
6947 00:25:04.634408 12, 0xFFFF, sum = 0
6948 00:25:04.637716 13, 0x0, sum = 1
6949 00:25:04.637798 14, 0x0, sum = 2
6950 00:25:04.640760 15, 0x0, sum = 3
6951 00:25:04.640832 16, 0x0, sum = 4
6952 00:25:04.643848 best_step = 14
6953 00:25:04.643982
6954 00:25:04.644046 ==
6955 00:25:04.647285 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 00:25:04.650466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 00:25:04.650588 ==
6958 00:25:04.653752 RX Vref Scan: 0
6959 00:25:04.653824
6960 00:25:04.653926 RX Vref 0 -> 0, step: 1
6961 00:25:04.653992
6962 00:25:04.656924 RX Delay -343 -> 252, step: 8
6963 00:25:04.664999 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6964 00:25:04.668230 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6965 00:25:04.671346 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6966 00:25:04.678076 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6967 00:25:04.681363 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6968 00:25:04.684654 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6969 00:25:04.687633 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6970 00:25:04.694545 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6971 00:25:04.697450 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6972 00:25:04.701117 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6973 00:25:04.704156 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6974 00:25:04.710858 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6975 00:25:04.714702 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6976 00:25:04.717406 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6977 00:25:04.720596 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6978 00:25:04.727730 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6979 00:25:04.727838 ==
6980 00:25:04.730521 Dram Type= 6, Freq= 0, CH_1, rank 1
6981 00:25:04.733701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6982 00:25:04.733810 ==
6983 00:25:04.733905 DQS Delay:
6984 00:25:04.737370 DQS0 = 48, DQS1 = 52
6985 00:25:04.737451 DQM Delay:
6986 00:25:04.740520 DQM0 = 11, DQM1 = 11
6987 00:25:04.740602 DQ Delay:
6988 00:25:04.744081 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6989 00:25:04.747386 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
6990 00:25:04.750466 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6991 00:25:04.754097 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6992 00:25:04.754206
6993 00:25:04.754299
6994 00:25:04.763746 [DQSOSCAuto] RK1, (LSB)MR18= 0x7fb6, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
6995 00:25:04.763840 CH1 RK1: MR19=C0C, MR18=7FB6
6996 00:25:04.770240 CH1_RK1: MR19=0xC0C, MR18=0x7FB6, DQSOSC=387, MR23=63, INC=394, DEC=262
6997 00:25:04.773496 [RxdqsGatingPostProcess] freq 400
6998 00:25:04.779786 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6999 00:25:04.783085 best DQS0 dly(2T, 0.5T) = (0, 10)
7000 00:25:04.786702 best DQS1 dly(2T, 0.5T) = (0, 10)
7001 00:25:04.790196 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7002 00:25:04.793027 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7003 00:25:04.796386 best DQS0 dly(2T, 0.5T) = (0, 10)
7004 00:25:04.799697 best DQS1 dly(2T, 0.5T) = (0, 10)
7005 00:25:04.803150 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7006 00:25:04.806176 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7007 00:25:04.806284 Pre-setting of DQS Precalculation
7008 00:25:04.812618 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7009 00:25:04.819773 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7010 00:25:04.826088 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7011 00:25:04.826170
7012 00:25:04.826233
7013 00:25:04.829419 [Calibration Summary] 800 Mbps
7014 00:25:04.833010 CH 0, Rank 0
7015 00:25:04.833090 SW Impedance : PASS
7016 00:25:04.836100 DUTY Scan : NO K
7017 00:25:04.839194 ZQ Calibration : PASS
7018 00:25:04.839331 Jitter Meter : NO K
7019 00:25:04.842384 CBT Training : PASS
7020 00:25:04.846092 Write leveling : PASS
7021 00:25:04.846201 RX DQS gating : PASS
7022 00:25:04.849302 RX DQ/DQS(RDDQC) : PASS
7023 00:25:04.849424 TX DQ/DQS : PASS
7024 00:25:04.852265 RX DATLAT : PASS
7025 00:25:04.855812 RX DQ/DQS(Engine): PASS
7026 00:25:04.855977 TX OE : NO K
7027 00:25:04.859493 All Pass.
7028 00:25:04.859573
7029 00:25:04.859638 CH 0, Rank 1
7030 00:25:04.862381 SW Impedance : PASS
7031 00:25:04.862491 DUTY Scan : NO K
7032 00:25:04.866051 ZQ Calibration : PASS
7033 00:25:04.869707 Jitter Meter : NO K
7034 00:25:04.869876 CBT Training : PASS
7035 00:25:04.872207 Write leveling : NO K
7036 00:25:04.876075 RX DQS gating : PASS
7037 00:25:04.876181 RX DQ/DQS(RDDQC) : PASS
7038 00:25:04.878748 TX DQ/DQS : PASS
7039 00:25:04.882085 RX DATLAT : PASS
7040 00:25:04.882193 RX DQ/DQS(Engine): PASS
7041 00:25:04.885258 TX OE : NO K
7042 00:25:04.885366 All Pass.
7043 00:25:04.885440
7044 00:25:04.888844 CH 1, Rank 0
7045 00:25:04.888950 SW Impedance : PASS
7046 00:25:04.892054 DUTY Scan : NO K
7047 00:25:04.895308 ZQ Calibration : PASS
7048 00:25:04.895412 Jitter Meter : NO K
7049 00:25:04.898558 CBT Training : PASS
7050 00:25:04.901745 Write leveling : PASS
7051 00:25:04.901857 RX DQS gating : PASS
7052 00:25:04.905431 RX DQ/DQS(RDDQC) : PASS
7053 00:25:04.908527 TX DQ/DQS : PASS
7054 00:25:04.908600 RX DATLAT : PASS
7055 00:25:04.912201 RX DQ/DQS(Engine): PASS
7056 00:25:04.915196 TX OE : NO K
7057 00:25:04.915274 All Pass.
7058 00:25:04.915338
7059 00:25:04.915403 CH 1, Rank 1
7060 00:25:04.918297 SW Impedance : PASS
7061 00:25:04.921461 DUTY Scan : NO K
7062 00:25:04.921538 ZQ Calibration : PASS
7063 00:25:04.924996 Jitter Meter : NO K
7064 00:25:04.928688 CBT Training : PASS
7065 00:25:04.928764 Write leveling : NO K
7066 00:25:04.931550 RX DQS gating : PASS
7067 00:25:04.931627 RX DQ/DQS(RDDQC) : PASS
7068 00:25:04.935488 TX DQ/DQS : PASS
7069 00:25:04.938188 RX DATLAT : PASS
7070 00:25:04.938272 RX DQ/DQS(Engine): PASS
7071 00:25:04.942036 TX OE : NO K
7072 00:25:04.942114 All Pass.
7073 00:25:04.942183
7074 00:25:04.945456 DramC Write-DBI off
7075 00:25:04.948539 PER_BANK_REFRESH: Hybrid Mode
7076 00:25:04.948618 TX_TRACKING: ON
7077 00:25:04.958067 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7078 00:25:04.961221 [FAST_K] Save calibration result to emmc
7079 00:25:04.964936 dramc_set_vcore_voltage set vcore to 725000
7080 00:25:04.968046 Read voltage for 1600, 0
7081 00:25:04.968121 Vio18 = 0
7082 00:25:04.971097 Vcore = 725000
7083 00:25:04.971169 Vdram = 0
7084 00:25:04.971231 Vddq = 0
7085 00:25:04.971294 Vmddr = 0
7086 00:25:04.977637 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7087 00:25:04.984732 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7088 00:25:04.984824 MEM_TYPE=3, freq_sel=13
7089 00:25:04.987723 sv_algorithm_assistance_LP4_3733
7090 00:25:04.991088 ============ PULL DRAM RESETB DOWN ============
7091 00:25:04.997886 ========== PULL DRAM RESETB DOWN end =========
7092 00:25:05.000767 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7093 00:25:05.004535 ===================================
7094 00:25:05.007756 LPDDR4 DRAM CONFIGURATION
7095 00:25:05.010438 ===================================
7096 00:25:05.010515 EX_ROW_EN[0] = 0x0
7097 00:25:05.014055 EX_ROW_EN[1] = 0x0
7098 00:25:05.014151 LP4Y_EN = 0x0
7099 00:25:05.017611 WORK_FSP = 0x1
7100 00:25:05.020958 WL = 0x5
7101 00:25:05.021063 RL = 0x5
7102 00:25:05.023712 BL = 0x2
7103 00:25:05.023816 RPST = 0x0
7104 00:25:05.027631 RD_PRE = 0x0
7105 00:25:05.027737 WR_PRE = 0x1
7106 00:25:05.030798 WR_PST = 0x1
7107 00:25:05.030905 DBI_WR = 0x0
7108 00:25:05.034391 DBI_RD = 0x0
7109 00:25:05.034501 OTF = 0x1
7110 00:25:05.036915 ===================================
7111 00:25:05.040285 ===================================
7112 00:25:05.043752 ANA top config
7113 00:25:05.046912 ===================================
7114 00:25:05.047104 DLL_ASYNC_EN = 0
7115 00:25:05.050459 ALL_SLAVE_EN = 0
7116 00:25:05.053614 NEW_RANK_MODE = 1
7117 00:25:05.056780 DLL_IDLE_MODE = 1
7118 00:25:05.060027 LP45_APHY_COMB_EN = 1
7119 00:25:05.060127 TX_ODT_DIS = 0
7120 00:25:05.063638 NEW_8X_MODE = 1
7121 00:25:05.066773 ===================================
7122 00:25:05.070110 ===================================
7123 00:25:05.072980 data_rate = 3200
7124 00:25:05.076647 CKR = 1
7125 00:25:05.079654 DQ_P2S_RATIO = 8
7126 00:25:05.083121 ===================================
7127 00:25:05.086276 CA_P2S_RATIO = 8
7128 00:25:05.086378 DQ_CA_OPEN = 0
7129 00:25:05.089772 DQ_SEMI_OPEN = 0
7130 00:25:05.093337 CA_SEMI_OPEN = 0
7131 00:25:05.096256 CA_FULL_RATE = 0
7132 00:25:05.099709 DQ_CKDIV4_EN = 0
7133 00:25:05.103714 CA_CKDIV4_EN = 0
7134 00:25:05.103824 CA_PREDIV_EN = 0
7135 00:25:05.106207 PH8_DLY = 12
7136 00:25:05.109652 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7137 00:25:05.112930 DQ_AAMCK_DIV = 4
7138 00:25:05.116244 CA_AAMCK_DIV = 4
7139 00:25:05.119410 CA_ADMCK_DIV = 4
7140 00:25:05.119511 DQ_TRACK_CA_EN = 0
7141 00:25:05.122757 CA_PICK = 1600
7142 00:25:05.125714 CA_MCKIO = 1600
7143 00:25:05.129269 MCKIO_SEMI = 0
7144 00:25:05.132706 PLL_FREQ = 3068
7145 00:25:05.136060 DQ_UI_PI_RATIO = 32
7146 00:25:05.138823 CA_UI_PI_RATIO = 0
7147 00:25:05.142855 ===================================
7148 00:25:05.145712 ===================================
7149 00:25:05.148988 memory_type:LPDDR4
7150 00:25:05.149062 GP_NUM : 10
7151 00:25:05.152046 SRAM_EN : 1
7152 00:25:05.152117 MD32_EN : 0
7153 00:25:05.155837 ===================================
7154 00:25:05.159135 [ANA_INIT] >>>>>>>>>>>>>>
7155 00:25:05.162013 <<<<<< [CONFIGURE PHASE]: ANA_TX
7156 00:25:05.165539 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7157 00:25:05.168713 ===================================
7158 00:25:05.172203 data_rate = 3200,PCW = 0X7600
7159 00:25:05.175076 ===================================
7160 00:25:05.178624 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7161 00:25:05.185078 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7162 00:25:05.188207 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7163 00:25:05.195067 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7164 00:25:05.198075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7165 00:25:05.201654 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7166 00:25:05.201730 [ANA_INIT] flow start
7167 00:25:05.205324 [ANA_INIT] PLL >>>>>>>>
7168 00:25:05.208454 [ANA_INIT] PLL <<<<<<<<
7169 00:25:05.208530 [ANA_INIT] MIDPI >>>>>>>>
7170 00:25:05.211497 [ANA_INIT] MIDPI <<<<<<<<
7171 00:25:05.214955 [ANA_INIT] DLL >>>>>>>>
7172 00:25:05.218183 [ANA_INIT] DLL <<<<<<<<
7173 00:25:05.218264 [ANA_INIT] flow end
7174 00:25:05.221847 ============ LP4 DIFF to SE enter ============
7175 00:25:05.228100 ============ LP4 DIFF to SE exit ============
7176 00:25:05.228182 [ANA_INIT] <<<<<<<<<<<<<
7177 00:25:05.231126 [Flow] Enable top DCM control >>>>>
7178 00:25:05.234475 [Flow] Enable top DCM control <<<<<
7179 00:25:05.238070 Enable DLL master slave shuffle
7180 00:25:05.244627 ==============================================================
7181 00:25:05.244710 Gating Mode config
7182 00:25:05.250887 ==============================================================
7183 00:25:05.254301 Config description:
7184 00:25:05.264719 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7185 00:25:05.270505 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7186 00:25:05.273807 SELPH_MODE 0: By rank 1: By Phase
7187 00:25:05.280390 ==============================================================
7188 00:25:05.283921 GAT_TRACK_EN = 1
7189 00:25:05.287164 RX_GATING_MODE = 2
7190 00:25:05.290326 RX_GATING_TRACK_MODE = 2
7191 00:25:05.290411 SELPH_MODE = 1
7192 00:25:05.293920 PICG_EARLY_EN = 1
7193 00:25:05.297361 VALID_LAT_VALUE = 1
7194 00:25:05.303877 ==============================================================
7195 00:25:05.306438 Enter into Gating configuration >>>>
7196 00:25:05.310074 Exit from Gating configuration <<<<
7197 00:25:05.313659 Enter into DVFS_PRE_config >>>>>
7198 00:25:05.323205 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7199 00:25:05.326560 Exit from DVFS_PRE_config <<<<<
7200 00:25:05.330233 Enter into PICG configuration >>>>
7201 00:25:05.333228 Exit from PICG configuration <<<<
7202 00:25:05.336741 [RX_INPUT] configuration >>>>>
7203 00:25:05.339926 [RX_INPUT] configuration <<<<<
7204 00:25:05.343013 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7205 00:25:05.349708 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7206 00:25:05.356349 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7207 00:25:05.362672 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7208 00:25:05.369241 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7209 00:25:05.376396 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7210 00:25:05.379197 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7211 00:25:05.382697 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7212 00:25:05.385671 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7213 00:25:05.392279 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7214 00:25:05.396097 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7215 00:25:05.399074 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7216 00:25:05.402436 ===================================
7217 00:25:05.405642 LPDDR4 DRAM CONFIGURATION
7218 00:25:05.409525 ===================================
7219 00:25:05.409605 EX_ROW_EN[0] = 0x0
7220 00:25:05.412432 EX_ROW_EN[1] = 0x0
7221 00:25:05.415943 LP4Y_EN = 0x0
7222 00:25:05.416069 WORK_FSP = 0x1
7223 00:25:05.418823 WL = 0x5
7224 00:25:05.418927 RL = 0x5
7225 00:25:05.422374 BL = 0x2
7226 00:25:05.422454 RPST = 0x0
7227 00:25:05.425548 RD_PRE = 0x0
7228 00:25:05.425628 WR_PRE = 0x1
7229 00:25:05.429239 WR_PST = 0x1
7230 00:25:05.429318 DBI_WR = 0x0
7231 00:25:05.432234 DBI_RD = 0x0
7232 00:25:05.432313 OTF = 0x1
7233 00:25:05.435856 ===================================
7234 00:25:05.438836 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7235 00:25:05.445240 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7236 00:25:05.448884 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7237 00:25:05.452586 ===================================
7238 00:25:05.455418 LPDDR4 DRAM CONFIGURATION
7239 00:25:05.458661 ===================================
7240 00:25:05.458747 EX_ROW_EN[0] = 0x10
7241 00:25:05.462163 EX_ROW_EN[1] = 0x0
7242 00:25:05.465150 LP4Y_EN = 0x0
7243 00:25:05.465229 WORK_FSP = 0x1
7244 00:25:05.468703 WL = 0x5
7245 00:25:05.468783 RL = 0x5
7246 00:25:05.471646 BL = 0x2
7247 00:25:05.471725 RPST = 0x0
7248 00:25:05.474953 RD_PRE = 0x0
7249 00:25:05.475033 WR_PRE = 0x1
7250 00:25:05.478132 WR_PST = 0x1
7251 00:25:05.478212 DBI_WR = 0x0
7252 00:25:05.481899 DBI_RD = 0x0
7253 00:25:05.481979 OTF = 0x1
7254 00:25:05.485432 ===================================
7255 00:25:05.491797 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7256 00:25:05.491880 ==
7257 00:25:05.495695 Dram Type= 6, Freq= 0, CH_0, rank 0
7258 00:25:05.498007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7259 00:25:05.501552 ==
7260 00:25:05.501632 [Duty_Offset_Calibration]
7261 00:25:05.504583 B0:2 B1:0 CA:4
7262 00:25:05.504662
7263 00:25:05.508094 [DutyScan_Calibration_Flow] k_type=0
7264 00:25:05.516145
7265 00:25:05.516224 ==CLK 0==
7266 00:25:05.519372 Final CLK duty delay cell = -4
7267 00:25:05.522699 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7268 00:25:05.525851 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7269 00:25:05.529069 [-4] AVG Duty = 4937%(X100)
7270 00:25:05.529149
7271 00:25:05.532342 CH0 CLK Duty spec in!! Max-Min= 187%
7272 00:25:05.536235 [DutyScan_Calibration_Flow] ====Done====
7273 00:25:05.536315
7274 00:25:05.539127 [DutyScan_Calibration_Flow] k_type=1
7275 00:25:05.556643
7276 00:25:05.556723 ==DQS 0 ==
7277 00:25:05.559658 Final DQS duty delay cell = 0
7278 00:25:05.563556 [0] MAX Duty = 5218%(X100), DQS PI = 22
7279 00:25:05.566338 [0] MIN Duty = 5093%(X100), DQS PI = 12
7280 00:25:05.569492 [0] AVG Duty = 5155%(X100)
7281 00:25:05.569589
7282 00:25:05.569653 ==DQS 1 ==
7283 00:25:05.572721 Final DQS duty delay cell = 0
7284 00:25:05.576254 [0] MAX Duty = 5156%(X100), DQS PI = 0
7285 00:25:05.579539 [0] MIN Duty = 4969%(X100), DQS PI = 10
7286 00:25:05.583206 [0] AVG Duty = 5062%(X100)
7287 00:25:05.583286
7288 00:25:05.585836 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7289 00:25:05.585916
7290 00:25:05.589205 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7291 00:25:05.593072 [DutyScan_Calibration_Flow] ====Done====
7292 00:25:05.593151
7293 00:25:05.595882 [DutyScan_Calibration_Flow] k_type=3
7294 00:25:05.613579
7295 00:25:05.613659 ==DQM 0 ==
7296 00:25:05.616675 Final DQM duty delay cell = 0
7297 00:25:05.620355 [0] MAX Duty = 5124%(X100), DQS PI = 20
7298 00:25:05.623528 [0] MIN Duty = 4875%(X100), DQS PI = 56
7299 00:25:05.627216 [0] AVG Duty = 4999%(X100)
7300 00:25:05.627295
7301 00:25:05.627362 ==DQM 1 ==
7302 00:25:05.630301 Final DQM duty delay cell = 0
7303 00:25:05.633593 [0] MAX Duty = 5000%(X100), DQS PI = 2
7304 00:25:05.636682 [0] MIN Duty = 4844%(X100), DQS PI = 14
7305 00:25:05.639633 [0] AVG Duty = 4922%(X100)
7306 00:25:05.639737
7307 00:25:05.642970 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7308 00:25:05.643049
7309 00:25:05.646800 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7310 00:25:05.649529 [DutyScan_Calibration_Flow] ====Done====
7311 00:25:05.649609
7312 00:25:05.653024 [DutyScan_Calibration_Flow] k_type=2
7313 00:25:05.671588
7314 00:25:05.671698 ==DQ 0 ==
7315 00:25:05.673784 Final DQ duty delay cell = 0
7316 00:25:05.677540 [0] MAX Duty = 5124%(X100), DQS PI = 20
7317 00:25:05.680959 [0] MIN Duty = 4938%(X100), DQS PI = 14
7318 00:25:05.683835 [0] AVG Duty = 5031%(X100)
7319 00:25:05.683952
7320 00:25:05.684018 ==DQ 1 ==
7321 00:25:05.687459 Final DQ duty delay cell = 0
7322 00:25:05.690556 [0] MAX Duty = 5187%(X100), DQS PI = 2
7323 00:25:05.693765 [0] MIN Duty = 4907%(X100), DQS PI = 32
7324 00:25:05.693845 [0] AVG Duty = 5047%(X100)
7325 00:25:05.697245
7326 00:25:05.700258 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7327 00:25:05.700339
7328 00:25:05.703524 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7329 00:25:05.706805 [DutyScan_Calibration_Flow] ====Done====
7330 00:25:05.706885 ==
7331 00:25:05.710369 Dram Type= 6, Freq= 0, CH_1, rank 0
7332 00:25:05.713819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7333 00:25:05.713900 ==
7334 00:25:05.717265 [Duty_Offset_Calibration]
7335 00:25:05.717345 B0:0 B1:-1 CA:3
7336 00:25:05.717409
7337 00:25:05.720966 [DutyScan_Calibration_Flow] k_type=0
7338 00:25:05.730072
7339 00:25:05.730151 ==CLK 0==
7340 00:25:05.733512 Final CLK duty delay cell = -4
7341 00:25:05.736889 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7342 00:25:05.740093 [-4] MIN Duty = 4875%(X100), DQS PI = 10
7343 00:25:05.743546 [-4] AVG Duty = 4937%(X100)
7344 00:25:05.743666
7345 00:25:05.746405 CH1 CLK Duty spec in!! Max-Min= 125%
7346 00:25:05.750254 [DutyScan_Calibration_Flow] ====Done====
7347 00:25:05.750333
7348 00:25:05.753260 [DutyScan_Calibration_Flow] k_type=1
7349 00:25:05.768972
7350 00:25:05.769050 ==DQS 0 ==
7351 00:25:05.772996 Final DQS duty delay cell = 0
7352 00:25:05.776242 [0] MAX Duty = 5250%(X100), DQS PI = 30
7353 00:25:05.779839 [0] MIN Duty = 4907%(X100), DQS PI = 58
7354 00:25:05.782974 [0] AVG Duty = 5078%(X100)
7355 00:25:05.783054
7356 00:25:05.783118 ==DQS 1 ==
7357 00:25:05.786057 Final DQS duty delay cell = -4
7358 00:25:05.789450 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7359 00:25:05.792734 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7360 00:25:05.795678 [-4] AVG Duty = 4906%(X100)
7361 00:25:05.795759
7362 00:25:05.798889 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7363 00:25:05.798972
7364 00:25:05.802543 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7365 00:25:05.805426 [DutyScan_Calibration_Flow] ====Done====
7366 00:25:05.805506
7367 00:25:05.808631 [DutyScan_Calibration_Flow] k_type=3
7368 00:25:05.826277
7369 00:25:05.826358 ==DQM 0 ==
7370 00:25:05.829958 Final DQM duty delay cell = 0
7371 00:25:05.833278 [0] MAX Duty = 5062%(X100), DQS PI = 30
7372 00:25:05.836862 [0] MIN Duty = 4782%(X100), DQS PI = 40
7373 00:25:05.840186 [0] AVG Duty = 4922%(X100)
7374 00:25:05.840266
7375 00:25:05.840330 ==DQM 1 ==
7376 00:25:05.842772 Final DQM duty delay cell = 0
7377 00:25:05.846298 [0] MAX Duty = 5000%(X100), DQS PI = 30
7378 00:25:05.849766 [0] MIN Duty = 4813%(X100), DQS PI = 0
7379 00:25:05.853119 [0] AVG Duty = 4906%(X100)
7380 00:25:05.853200
7381 00:25:05.855888 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7382 00:25:05.855991
7383 00:25:05.859577 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7384 00:25:05.862875 [DutyScan_Calibration_Flow] ====Done====
7385 00:25:05.862956
7386 00:25:05.866139 [DutyScan_Calibration_Flow] k_type=2
7387 00:25:05.882644
7388 00:25:05.882723 ==DQ 0 ==
7389 00:25:05.885993 Final DQ duty delay cell = -4
7390 00:25:05.889364 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7391 00:25:05.892506 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7392 00:25:05.895646 [-4] AVG Duty = 4891%(X100)
7393 00:25:05.895726
7394 00:25:05.895789 ==DQ 1 ==
7395 00:25:05.899146 Final DQ duty delay cell = 0
7396 00:25:05.902230 [0] MAX Duty = 5062%(X100), DQS PI = 30
7397 00:25:05.905905 [0] MIN Duty = 4875%(X100), DQS PI = 0
7398 00:25:05.908809 [0] AVG Duty = 4968%(X100)
7399 00:25:05.908890
7400 00:25:05.912423 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7401 00:25:05.912503
7402 00:25:05.915782 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7403 00:25:05.918946 [DutyScan_Calibration_Flow] ====Done====
7404 00:25:05.922748 nWR fixed to 30
7405 00:25:05.925288 [ModeRegInit_LP4] CH0 RK0
7406 00:25:05.925369 [ModeRegInit_LP4] CH0 RK1
7407 00:25:05.928491 [ModeRegInit_LP4] CH1 RK0
7408 00:25:05.931783 [ModeRegInit_LP4] CH1 RK1
7409 00:25:05.931880 match AC timing 5
7410 00:25:05.938296 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7411 00:25:05.941903 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7412 00:25:05.944781 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7413 00:25:05.951647 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7414 00:25:05.955383 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7415 00:25:05.958220 [MiockJmeterHQA]
7416 00:25:05.958300
7417 00:25:05.961636 [DramcMiockJmeter] u1RxGatingPI = 0
7418 00:25:05.961717 0 : 4363, 4137
7419 00:25:05.961783 4 : 4253, 4027
7420 00:25:05.964662 8 : 4363, 4137
7421 00:25:05.964744 12 : 4255, 4029
7422 00:25:05.968162 16 : 4252, 4026
7423 00:25:05.968243 20 : 4363, 4137
7424 00:25:05.972245 24 : 4252, 4027
7425 00:25:05.972327 28 : 4363, 4138
7426 00:25:05.972392 32 : 4253, 4027
7427 00:25:05.974578 36 : 4252, 4027
7428 00:25:05.974659 40 : 4255, 4029
7429 00:25:05.978260 44 : 4252, 4026
7430 00:25:05.978343 48 : 4365, 4140
7431 00:25:05.981092 52 : 4365, 4140
7432 00:25:05.981174 56 : 4255, 4029
7433 00:25:05.985127 60 : 4255, 4029
7434 00:25:05.985209 64 : 4363, 4140
7435 00:25:05.985275 68 : 4250, 4026
7436 00:25:05.987837 72 : 4363, 4140
7437 00:25:05.987960 76 : 4250, 4027
7438 00:25:05.991153 80 : 4250, 4027
7439 00:25:05.991235 84 : 4250, 4027
7440 00:25:05.994387 88 : 4250, 4027
7441 00:25:05.994469 92 : 4250, 4027
7442 00:25:05.997851 96 : 4250, 3159
7443 00:25:05.997934 100 : 4363, 0
7444 00:25:05.997999 104 : 4249, 0
7445 00:25:06.001369 108 : 4361, 0
7446 00:25:06.001474 112 : 4361, 0
7447 00:25:06.004407 116 : 4250, 0
7448 00:25:06.004488 120 : 4249, 0
7449 00:25:06.004554 124 : 4255, 0
7450 00:25:06.007744 128 : 4250, 0
7451 00:25:06.007842 132 : 4250, 0
7452 00:25:06.007919 136 : 4250, 0
7453 00:25:06.011627 140 : 4252, 0
7454 00:25:06.011709 144 : 4361, 0
7455 00:25:06.014946 148 : 4252, 0
7456 00:25:06.015028 152 : 4250, 0
7457 00:25:06.015094 156 : 4249, 0
7458 00:25:06.017565 160 : 4366, 0
7459 00:25:06.017648 164 : 4361, 0
7460 00:25:06.020846 168 : 4250, 0
7461 00:25:06.020928 172 : 4250, 0
7462 00:25:06.020994 176 : 4250, 0
7463 00:25:06.024191 180 : 4252, 0
7464 00:25:06.024273 184 : 4250, 0
7465 00:25:06.027477 188 : 4250, 0
7466 00:25:06.027558 192 : 4255, 0
7467 00:25:06.027624 196 : 4361, 0
7468 00:25:06.030979 200 : 4360, 0
7469 00:25:06.031050 204 : 4250, 0
7470 00:25:06.034116 208 : 4248, 0
7471 00:25:06.034187 212 : 4250, 0
7472 00:25:06.034246 216 : 4363, 0
7473 00:25:06.037486 220 : 4257, 525
7474 00:25:06.037566 224 : 4255, 3950
7475 00:25:06.040686 228 : 4361, 4137
7476 00:25:06.040767 232 : 4361, 4137
7477 00:25:06.044267 236 : 4247, 4025
7478 00:25:06.044347 240 : 4250, 4027
7479 00:25:06.047009 244 : 4363, 4140
7480 00:25:06.047089 248 : 4361, 4137
7481 00:25:06.050279 252 : 4249, 4027
7482 00:25:06.050360 256 : 4250, 4027
7483 00:25:06.050425 260 : 4250, 4026
7484 00:25:06.054225 264 : 4250, 4027
7485 00:25:06.054333 268 : 4252, 4030
7486 00:25:06.057132 272 : 4253, 4029
7487 00:25:06.057213 276 : 4252, 4029
7488 00:25:06.060237 280 : 4361, 4137
7489 00:25:06.060317 284 : 4255, 4029
7490 00:25:06.063660 288 : 4250, 4027
7491 00:25:06.063741 292 : 4250, 4027
7492 00:25:06.067003 296 : 4363, 4140
7493 00:25:06.067084 300 : 4362, 4137
7494 00:25:06.070584 304 : 4247, 4024
7495 00:25:06.070671 308 : 4365, 4140
7496 00:25:06.073632 312 : 4252, 4030
7497 00:25:06.073713 316 : 4250, 4027
7498 00:25:06.077319 320 : 4252, 4030
7499 00:25:06.077402 324 : 4253, 4029
7500 00:25:06.079933 328 : 4252, 4030
7501 00:25:06.080074 332 : 4363, 4095
7502 00:25:06.080187 336 : 4255, 1993
7503 00:25:06.083214
7504 00:25:06.083337 MIOCK jitter meter ch=0
7505 00:25:06.083451
7506 00:25:06.087095 1T = (336-100) = 236 dly cells
7507 00:25:06.093373 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7508 00:25:06.093458 ==
7509 00:25:06.097251 Dram Type= 6, Freq= 0, CH_0, rank 0
7510 00:25:06.099865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7511 00:25:06.099996 ==
7512 00:25:06.106248 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7513 00:25:06.110551 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7514 00:25:06.113480 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7515 00:25:06.120151 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7516 00:25:06.129214 [CA 0] Center 43 (13~74) winsize 62
7517 00:25:06.132384 [CA 1] Center 42 (12~73) winsize 62
7518 00:25:06.136148 [CA 2] Center 37 (8~67) winsize 60
7519 00:25:06.139321 [CA 3] Center 37 (8~67) winsize 60
7520 00:25:06.142612 [CA 4] Center 36 (6~66) winsize 61
7521 00:25:06.145809 [CA 5] Center 35 (5~66) winsize 62
7522 00:25:06.145889
7523 00:25:06.148684 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7524 00:25:06.148764
7525 00:25:06.155209 [CATrainingPosCal] consider 1 rank data
7526 00:25:06.155290 u2DelayCellTimex100 = 275/100 ps
7527 00:25:06.161723 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7528 00:25:06.164948 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7529 00:25:06.168228 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7530 00:25:06.172360 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7531 00:25:06.175063 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7532 00:25:06.178602 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7533 00:25:06.178682
7534 00:25:06.181605 CA PerBit enable=1, Macro0, CA PI delay=35
7535 00:25:06.181685
7536 00:25:06.185056 [CBTSetCACLKResult] CA Dly = 35
7537 00:25:06.188324 CS Dly: 10 (0~41)
7538 00:25:06.192018 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7539 00:25:06.195198 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7540 00:25:06.195279 ==
7541 00:25:06.198156 Dram Type= 6, Freq= 0, CH_0, rank 1
7542 00:25:06.205017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7543 00:25:06.205098 ==
7544 00:25:06.208009 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7545 00:25:06.214622 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7546 00:25:06.218202 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7547 00:25:06.224567 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7548 00:25:06.232508 [CA 0] Center 44 (14~75) winsize 62
7549 00:25:06.235831 [CA 1] Center 44 (14~74) winsize 61
7550 00:25:06.238973 [CA 2] Center 39 (10~69) winsize 60
7551 00:25:06.242836 [CA 3] Center 39 (10~68) winsize 59
7552 00:25:06.245488 [CA 4] Center 37 (7~67) winsize 61
7553 00:25:06.249236 [CA 5] Center 36 (7~66) winsize 60
7554 00:25:06.249316
7555 00:25:06.252126 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7556 00:25:06.252220
7557 00:25:06.258836 [CATrainingPosCal] consider 2 rank data
7558 00:25:06.258916 u2DelayCellTimex100 = 275/100 ps
7559 00:25:06.265573 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7560 00:25:06.268693 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7561 00:25:06.272119 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7562 00:25:06.275244 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7563 00:25:06.278609 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7564 00:25:06.281975 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7565 00:25:06.282055
7566 00:25:06.285473 CA PerBit enable=1, Macro0, CA PI delay=36
7567 00:25:06.285553
7568 00:25:06.288511 [CBTSetCACLKResult] CA Dly = 36
7569 00:25:06.292175 CS Dly: 11 (0~43)
7570 00:25:06.294953 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7571 00:25:06.298438 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7572 00:25:06.298518
7573 00:25:06.301659 ----->DramcWriteLeveling(PI) begin...
7574 00:25:06.305314 ==
7575 00:25:06.305394 Dram Type= 6, Freq= 0, CH_0, rank 0
7576 00:25:06.311468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7577 00:25:06.311550 ==
7578 00:25:06.314964 Write leveling (Byte 0): 33 => 33
7579 00:25:06.318157 Write leveling (Byte 1): 25 => 25
7580 00:25:06.322082 DramcWriteLeveling(PI) end<-----
7581 00:25:06.322180
7582 00:25:06.322257 ==
7583 00:25:06.324986 Dram Type= 6, Freq= 0, CH_0, rank 0
7584 00:25:06.328225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7585 00:25:06.328331 ==
7586 00:25:06.331461 [Gating] SW mode calibration
7587 00:25:06.338043 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7588 00:25:06.344812 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7589 00:25:06.347803 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 00:25:06.351342 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 00:25:06.357492 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7592 00:25:06.361149 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7593 00:25:06.364182 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7594 00:25:06.370518 1 4 20 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
7595 00:25:06.374034 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 00:25:06.377525 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 00:25:06.383784 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7598 00:25:06.387296 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7599 00:25:06.390512 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7600 00:25:06.396778 1 5 12 | B1->B0 | 3434 2626 | 1 1 | (1 1) (1 0)
7601 00:25:06.400380 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7602 00:25:06.403713 1 5 20 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
7603 00:25:06.410197 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 00:25:06.413429 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 00:25:06.416870 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 00:25:06.423807 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 00:25:06.426596 1 6 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7608 00:25:06.429920 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7609 00:25:06.436599 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7610 00:25:06.439823 1 6 20 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7611 00:25:06.443199 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 00:25:06.450391 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 00:25:06.453464 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 00:25:06.456300 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 00:25:06.462907 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7616 00:25:06.466375 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7617 00:25:06.469530 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7618 00:25:06.476089 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7619 00:25:06.479878 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7620 00:25:06.482996 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 00:25:06.489511 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 00:25:06.492461 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 00:25:06.495872 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 00:25:06.502427 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 00:25:06.505864 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 00:25:06.509380 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 00:25:06.515593 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 00:25:06.519031 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 00:25:06.522001 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 00:25:06.528783 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 00:25:06.532475 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7632 00:25:06.536110 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7633 00:25:06.539374 Total UI for P1: 0, mck2ui 16
7634 00:25:06.541999 best dqsien dly found for B0: ( 1, 9, 8)
7635 00:25:06.548816 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7636 00:25:06.552033 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7637 00:25:06.555605 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7638 00:25:06.562436 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 00:25:06.562515 Total UI for P1: 0, mck2ui 16
7640 00:25:06.568368 best dqsien dly found for B1: ( 1, 9, 24)
7641 00:25:06.571552 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7642 00:25:06.574876 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7643 00:25:06.574950
7644 00:25:06.578369 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7645 00:25:06.581883 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7646 00:25:06.584911 [Gating] SW calibration Done
7647 00:25:06.584992 ==
7648 00:25:06.588143 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 00:25:06.591598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 00:25:06.591678 ==
7651 00:25:06.594562 RX Vref Scan: 0
7652 00:25:06.594660
7653 00:25:06.594787 RX Vref 0 -> 0, step: 1
7654 00:25:06.594874
7655 00:25:06.598329 RX Delay 0 -> 252, step: 8
7656 00:25:06.601294 iDelay=192, Bit 0, Center 135 (80 ~ 191) 112
7657 00:25:06.608082 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7658 00:25:06.611100 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7659 00:25:06.614532 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7660 00:25:06.618429 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7661 00:25:06.621600 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7662 00:25:06.627710 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7663 00:25:06.631510 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7664 00:25:06.634224 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7665 00:25:06.637983 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7666 00:25:06.640918 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7667 00:25:06.647360 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7668 00:25:06.650575 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7669 00:25:06.654113 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7670 00:25:06.657773 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7671 00:25:06.663811 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7672 00:25:06.663913 ==
7673 00:25:06.667405 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 00:25:06.670838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 00:25:06.670919 ==
7676 00:25:06.670988 DQS Delay:
7677 00:25:06.674019 DQS0 = 0, DQS1 = 0
7678 00:25:06.674098 DQM Delay:
7679 00:25:06.677408 DQM0 = 131, DQM1 = 127
7680 00:25:06.677488 DQ Delay:
7681 00:25:06.680590 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =123
7682 00:25:06.683915 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7683 00:25:06.687502 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
7684 00:25:06.690283 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7685 00:25:06.690363
7686 00:25:06.693812
7687 00:25:06.693891 ==
7688 00:25:06.696887 Dram Type= 6, Freq= 0, CH_0, rank 0
7689 00:25:06.700366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7690 00:25:06.700442 ==
7691 00:25:06.700559
7692 00:25:06.700677
7693 00:25:06.703692 TX Vref Scan disable
7694 00:25:06.703794 == TX Byte 0 ==
7695 00:25:06.710545 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7696 00:25:06.713571 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7697 00:25:06.713654 == TX Byte 1 ==
7698 00:25:06.720447 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7699 00:25:06.723518 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7700 00:25:06.723598 ==
7701 00:25:06.726953 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 00:25:06.730125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 00:25:06.730206 ==
7704 00:25:06.744493
7705 00:25:06.747659 TX Vref early break, caculate TX vref
7706 00:25:06.751129 TX Vref=16, minBit 1, minWin=22, winSum=366
7707 00:25:06.754004 TX Vref=18, minBit 4, minWin=23, winSum=380
7708 00:25:06.757932 TX Vref=20, minBit 7, minWin=23, winSum=388
7709 00:25:06.760710 TX Vref=22, minBit 8, minWin=23, winSum=397
7710 00:25:06.763744 TX Vref=24, minBit 0, minWin=25, winSum=408
7711 00:25:06.770736 TX Vref=26, minBit 1, minWin=25, winSum=418
7712 00:25:06.774208 TX Vref=28, minBit 2, minWin=25, winSum=419
7713 00:25:06.776969 TX Vref=30, minBit 1, minWin=25, winSum=414
7714 00:25:06.780523 TX Vref=32, minBit 4, minWin=24, winSum=410
7715 00:25:06.783301 TX Vref=34, minBit 0, minWin=24, winSum=395
7716 00:25:06.790497 [TxChooseVref] Worse bit 2, Min win 25, Win sum 419, Final Vref 28
7717 00:25:06.790578
7718 00:25:06.793470 Final TX Range 0 Vref 28
7719 00:25:06.793550
7720 00:25:06.793613 ==
7721 00:25:06.797189 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 00:25:06.800000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 00:25:06.800080 ==
7724 00:25:06.800149
7725 00:25:06.803452
7726 00:25:06.803531 TX Vref Scan disable
7727 00:25:06.809646 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7728 00:25:06.809727 == TX Byte 0 ==
7729 00:25:06.813267 u2DelayCellOfst[0]=14 cells (4 PI)
7730 00:25:06.817359 u2DelayCellOfst[1]=17 cells (5 PI)
7731 00:25:06.819808 u2DelayCellOfst[2]=14 cells (4 PI)
7732 00:25:06.823192 u2DelayCellOfst[3]=10 cells (3 PI)
7733 00:25:06.826983 u2DelayCellOfst[4]=10 cells (3 PI)
7734 00:25:06.829775 u2DelayCellOfst[5]=0 cells (0 PI)
7735 00:25:06.832953 u2DelayCellOfst[6]=17 cells (5 PI)
7736 00:25:06.836849 u2DelayCellOfst[7]=17 cells (5 PI)
7737 00:25:06.839602 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7738 00:25:06.842959 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7739 00:25:06.845912 == TX Byte 1 ==
7740 00:25:06.849236 u2DelayCellOfst[8]=0 cells (0 PI)
7741 00:25:06.852625 u2DelayCellOfst[9]=0 cells (0 PI)
7742 00:25:06.856379 u2DelayCellOfst[10]=3 cells (1 PI)
7743 00:25:06.859567 u2DelayCellOfst[11]=0 cells (0 PI)
7744 00:25:06.862686 u2DelayCellOfst[12]=7 cells (2 PI)
7745 00:25:06.865857 u2DelayCellOfst[13]=7 cells (2 PI)
7746 00:25:06.865938 u2DelayCellOfst[14]=14 cells (4 PI)
7747 00:25:06.869081 u2DelayCellOfst[15]=7 cells (2 PI)
7748 00:25:06.875843 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7749 00:25:06.878909 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7750 00:25:06.882188 DramC Write-DBI on
7751 00:25:06.882268 ==
7752 00:25:06.885582 Dram Type= 6, Freq= 0, CH_0, rank 0
7753 00:25:06.888549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7754 00:25:06.888630 ==
7755 00:25:06.888694
7756 00:25:06.888752
7757 00:25:06.892090 TX Vref Scan disable
7758 00:25:06.892169 == TX Byte 0 ==
7759 00:25:06.898424 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
7760 00:25:06.898504 == TX Byte 1 ==
7761 00:25:06.905531 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7762 00:25:06.905611 DramC Write-DBI off
7763 00:25:06.905674
7764 00:25:06.905732 [DATLAT]
7765 00:25:06.908507 Freq=1600, CH0 RK0
7766 00:25:06.908607
7767 00:25:06.908689 DATLAT Default: 0xf
7768 00:25:06.912243 0, 0xFFFF, sum = 0
7769 00:25:06.915215 1, 0xFFFF, sum = 0
7770 00:25:06.915299 2, 0xFFFF, sum = 0
7771 00:25:06.918583 3, 0xFFFF, sum = 0
7772 00:25:06.918665 4, 0xFFFF, sum = 0
7773 00:25:06.921612 5, 0xFFFF, sum = 0
7774 00:25:06.921695 6, 0xFFFF, sum = 0
7775 00:25:06.925239 7, 0xFFFF, sum = 0
7776 00:25:06.925322 8, 0xFFFF, sum = 0
7777 00:25:06.928047 9, 0xFFFF, sum = 0
7778 00:25:06.928130 10, 0xFFFF, sum = 0
7779 00:25:06.931790 11, 0xFFFF, sum = 0
7780 00:25:06.931873 12, 0xFFFF, sum = 0
7781 00:25:06.935129 13, 0xFFFF, sum = 0
7782 00:25:06.935231 14, 0x0, sum = 1
7783 00:25:06.937919 15, 0x0, sum = 2
7784 00:25:06.938002 16, 0x0, sum = 3
7785 00:25:06.941521 17, 0x0, sum = 4
7786 00:25:06.941604 best_step = 15
7787 00:25:06.941688
7788 00:25:06.941766 ==
7789 00:25:06.944576 Dram Type= 6, Freq= 0, CH_0, rank 0
7790 00:25:06.951338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7791 00:25:06.951418 ==
7792 00:25:06.951481 RX Vref Scan: 1
7793 00:25:06.951540
7794 00:25:06.954613 Set Vref Range= 24 -> 127
7795 00:25:06.954693
7796 00:25:06.957854 RX Vref 24 -> 127, step: 1
7797 00:25:06.957934
7798 00:25:06.960975 RX Delay 19 -> 252, step: 4
7799 00:25:06.961055
7800 00:25:06.964855 Set Vref, RX VrefLevel [Byte0]: 24
7801 00:25:06.964935 [Byte1]: 24
7802 00:25:06.968859
7803 00:25:06.968966 Set Vref, RX VrefLevel [Byte0]: 25
7804 00:25:06.972251 [Byte1]: 25
7805 00:25:06.976607
7806 00:25:06.976686 Set Vref, RX VrefLevel [Byte0]: 26
7807 00:25:06.979875 [Byte1]: 26
7808 00:25:06.983779
7809 00:25:06.983859 Set Vref, RX VrefLevel [Byte0]: 27
7810 00:25:06.987615 [Byte1]: 27
7811 00:25:06.991848
7812 00:25:06.991967 Set Vref, RX VrefLevel [Byte0]: 28
7813 00:25:06.995318 [Byte1]: 28
7814 00:25:06.999432
7815 00:25:06.999512 Set Vref, RX VrefLevel [Byte0]: 29
7816 00:25:07.002855 [Byte1]: 29
7817 00:25:07.006704
7818 00:25:07.006784 Set Vref, RX VrefLevel [Byte0]: 30
7819 00:25:07.010161 [Byte1]: 30
7820 00:25:07.014413
7821 00:25:07.014492 Set Vref, RX VrefLevel [Byte0]: 31
7822 00:25:07.017948 [Byte1]: 31
7823 00:25:07.021684
7824 00:25:07.021764 Set Vref, RX VrefLevel [Byte0]: 32
7825 00:25:07.025303 [Byte1]: 32
7826 00:25:07.029592
7827 00:25:07.029672 Set Vref, RX VrefLevel [Byte0]: 33
7828 00:25:07.032860 [Byte1]: 33
7829 00:25:07.036875
7830 00:25:07.036955 Set Vref, RX VrefLevel [Byte0]: 34
7831 00:25:07.040055 [Byte1]: 34
7832 00:25:07.044570
7833 00:25:07.044649 Set Vref, RX VrefLevel [Byte0]: 35
7834 00:25:07.047707 [Byte1]: 35
7835 00:25:07.052311
7836 00:25:07.052407 Set Vref, RX VrefLevel [Byte0]: 36
7837 00:25:07.055394 [Byte1]: 36
7838 00:25:07.059831
7839 00:25:07.059934 Set Vref, RX VrefLevel [Byte0]: 37
7840 00:25:07.063202 [Byte1]: 37
7841 00:25:07.067221
7842 00:25:07.067303 Set Vref, RX VrefLevel [Byte0]: 38
7843 00:25:07.070569 [Byte1]: 38
7844 00:25:07.075088
7845 00:25:07.075167 Set Vref, RX VrefLevel [Byte0]: 39
7846 00:25:07.077900 [Byte1]: 39
7847 00:25:07.082243
7848 00:25:07.082324 Set Vref, RX VrefLevel [Byte0]: 40
7849 00:25:07.085472 [Byte1]: 40
7850 00:25:07.090272
7851 00:25:07.090352 Set Vref, RX VrefLevel [Byte0]: 41
7852 00:25:07.092924 [Byte1]: 41
7853 00:25:07.097578
7854 00:25:07.097658 Set Vref, RX VrefLevel [Byte0]: 42
7855 00:25:07.101064 [Byte1]: 42
7856 00:25:07.104874
7857 00:25:07.104954 Set Vref, RX VrefLevel [Byte0]: 43
7858 00:25:07.108158 [Byte1]: 43
7859 00:25:07.112500
7860 00:25:07.112580 Set Vref, RX VrefLevel [Byte0]: 44
7861 00:25:07.115671 [Byte1]: 44
7862 00:25:07.120100
7863 00:25:07.120180 Set Vref, RX VrefLevel [Byte0]: 45
7864 00:25:07.123216 [Byte1]: 45
7865 00:25:07.127481
7866 00:25:07.127561 Set Vref, RX VrefLevel [Byte0]: 46
7867 00:25:07.131656 [Byte1]: 46
7868 00:25:07.135250
7869 00:25:07.135330 Set Vref, RX VrefLevel [Byte0]: 47
7870 00:25:07.138757 [Byte1]: 47
7871 00:25:07.142985
7872 00:25:07.143065 Set Vref, RX VrefLevel [Byte0]: 48
7873 00:25:07.146026 [Byte1]: 48
7874 00:25:07.150773
7875 00:25:07.150868 Set Vref, RX VrefLevel [Byte0]: 49
7876 00:25:07.154041 [Byte1]: 49
7877 00:25:07.158072
7878 00:25:07.158152 Set Vref, RX VrefLevel [Byte0]: 50
7879 00:25:07.161212 [Byte1]: 50
7880 00:25:07.165626
7881 00:25:07.165705 Set Vref, RX VrefLevel [Byte0]: 51
7882 00:25:07.172391 [Byte1]: 51
7883 00:25:07.172472
7884 00:25:07.175621 Set Vref, RX VrefLevel [Byte0]: 52
7885 00:25:07.179019 [Byte1]: 52
7886 00:25:07.179099
7887 00:25:07.181840 Set Vref, RX VrefLevel [Byte0]: 53
7888 00:25:07.185363 [Byte1]: 53
7889 00:25:07.185444
7890 00:25:07.188714 Set Vref, RX VrefLevel [Byte0]: 54
7891 00:25:07.191848 [Byte1]: 54
7892 00:25:07.196148
7893 00:25:07.196228 Set Vref, RX VrefLevel [Byte0]: 55
7894 00:25:07.199471 [Byte1]: 55
7895 00:25:07.203320
7896 00:25:07.203400 Set Vref, RX VrefLevel [Byte0]: 56
7897 00:25:07.206994 [Byte1]: 56
7898 00:25:07.211366
7899 00:25:07.211447 Set Vref, RX VrefLevel [Byte0]: 57
7900 00:25:07.214558 [Byte1]: 57
7901 00:25:07.218601
7902 00:25:07.218680 Set Vref, RX VrefLevel [Byte0]: 58
7903 00:25:07.222189 [Byte1]: 58
7904 00:25:07.226123
7905 00:25:07.226203 Set Vref, RX VrefLevel [Byte0]: 59
7906 00:25:07.229473 [Byte1]: 59
7907 00:25:07.233744
7908 00:25:07.233823 Set Vref, RX VrefLevel [Byte0]: 60
7909 00:25:07.237089 [Byte1]: 60
7910 00:25:07.241481
7911 00:25:07.241560 Set Vref, RX VrefLevel [Byte0]: 61
7912 00:25:07.244928 [Byte1]: 61
7913 00:25:07.249636
7914 00:25:07.249715 Set Vref, RX VrefLevel [Byte0]: 62
7915 00:25:07.252076 [Byte1]: 62
7916 00:25:07.256743
7917 00:25:07.256823 Set Vref, RX VrefLevel [Byte0]: 63
7918 00:25:07.259564 [Byte1]: 63
7919 00:25:07.264186
7920 00:25:07.264266 Set Vref, RX VrefLevel [Byte0]: 64
7921 00:25:07.270749 [Byte1]: 64
7922 00:25:07.270829
7923 00:25:07.273536 Set Vref, RX VrefLevel [Byte0]: 65
7924 00:25:07.277128 [Byte1]: 65
7925 00:25:07.277208
7926 00:25:07.280748 Set Vref, RX VrefLevel [Byte0]: 66
7927 00:25:07.283489 [Byte1]: 66
7928 00:25:07.283570
7929 00:25:07.287212 Set Vref, RX VrefLevel [Byte0]: 67
7930 00:25:07.290345 [Byte1]: 67
7931 00:25:07.294433
7932 00:25:07.294512 Set Vref, RX VrefLevel [Byte0]: 68
7933 00:25:07.298188 [Byte1]: 68
7934 00:25:07.301616
7935 00:25:07.301696 Set Vref, RX VrefLevel [Byte0]: 69
7936 00:25:07.304974 [Byte1]: 69
7937 00:25:07.309222
7938 00:25:07.309303 Set Vref, RX VrefLevel [Byte0]: 70
7939 00:25:07.312583 [Byte1]: 70
7940 00:25:07.316818
7941 00:25:07.316898 Set Vref, RX VrefLevel [Byte0]: 71
7942 00:25:07.320099 [Byte1]: 71
7943 00:25:07.324574
7944 00:25:07.324654 Set Vref, RX VrefLevel [Byte0]: 72
7945 00:25:07.327672 [Byte1]: 72
7946 00:25:07.332030
7947 00:25:07.332111 Set Vref, RX VrefLevel [Byte0]: 73
7948 00:25:07.335683 [Byte1]: 73
7949 00:25:07.339618
7950 00:25:07.339699 Set Vref, RX VrefLevel [Byte0]: 74
7951 00:25:07.342823 [Byte1]: 74
7952 00:25:07.347487
7953 00:25:07.347568 Set Vref, RX VrefLevel [Byte0]: 75
7954 00:25:07.350701 [Byte1]: 75
7955 00:25:07.355108
7956 00:25:07.355188 Set Vref, RX VrefLevel [Byte0]: 76
7957 00:25:07.358582 [Byte1]: 76
7958 00:25:07.362582
7959 00:25:07.362663 Final RX Vref Byte 0 = 57 to rank0
7960 00:25:07.365691 Final RX Vref Byte 1 = 60 to rank0
7961 00:25:07.369348 Final RX Vref Byte 0 = 57 to rank1
7962 00:25:07.372432 Final RX Vref Byte 1 = 60 to rank1==
7963 00:25:07.376149 Dram Type= 6, Freq= 0, CH_0, rank 0
7964 00:25:07.382749 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7965 00:25:07.382831 ==
7966 00:25:07.382895 DQS Delay:
7967 00:25:07.382956 DQS0 = 0, DQS1 = 0
7968 00:25:07.385412 DQM Delay:
7969 00:25:07.385494 DQM0 = 128, DQM1 = 124
7970 00:25:07.388910 DQ Delay:
7971 00:25:07.392131 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7972 00:25:07.395737 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =134
7973 00:25:07.399533 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =120
7974 00:25:07.401954 DQ12 =130, DQ13 =128, DQ14 =134, DQ15 =130
7975 00:25:07.402035
7976 00:25:07.402098
7977 00:25:07.402158
7978 00:25:07.405771 [DramC_TX_OE_Calibration] TA2
7979 00:25:07.408563 Original DQ_B0 (3 6) =30, OEN = 27
7980 00:25:07.411799 Original DQ_B1 (3 6) =30, OEN = 27
7981 00:25:07.415068 24, 0x0, End_B0=24 End_B1=24
7982 00:25:07.415150 25, 0x0, End_B0=25 End_B1=25
7983 00:25:07.418808 26, 0x0, End_B0=26 End_B1=26
7984 00:25:07.422104 27, 0x0, End_B0=27 End_B1=27
7985 00:25:07.425107 28, 0x0, End_B0=28 End_B1=28
7986 00:25:07.428478 29, 0x0, End_B0=29 End_B1=29
7987 00:25:07.428559 30, 0x0, End_B0=30 End_B1=30
7988 00:25:07.431556 31, 0x4141, End_B0=30 End_B1=30
7989 00:25:07.435249 Byte0 end_step=30 best_step=27
7990 00:25:07.438202 Byte1 end_step=30 best_step=27
7991 00:25:07.441883 Byte0 TX OE(2T, 0.5T) = (3, 3)
7992 00:25:07.444914 Byte1 TX OE(2T, 0.5T) = (3, 3)
7993 00:25:07.444995
7994 00:25:07.445058
7995 00:25:07.451463 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7996 00:25:07.454958 CH0 RK0: MR19=303, MR18=1A17
7997 00:25:07.461387 CH0_RK0: MR19=0x303, MR18=0x1A17, DQSOSC=396, MR23=63, INC=23, DEC=15
7998 00:25:07.461468
7999 00:25:07.464729 ----->DramcWriteLeveling(PI) begin...
8000 00:25:07.464811 ==
8001 00:25:07.468242 Dram Type= 6, Freq= 0, CH_0, rank 1
8002 00:25:07.471166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8003 00:25:07.471248 ==
8004 00:25:07.474804 Write leveling (Byte 0): 36 => 36
8005 00:25:07.477878 Write leveling (Byte 1): 25 => 25
8006 00:25:07.481130 DramcWriteLeveling(PI) end<-----
8007 00:25:07.481210
8008 00:25:07.481290 ==
8009 00:25:07.484572 Dram Type= 6, Freq= 0, CH_0, rank 1
8010 00:25:07.487809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8011 00:25:07.490871 ==
8012 00:25:07.490951 [Gating] SW mode calibration
8013 00:25:07.500794 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8014 00:25:07.504613 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8015 00:25:07.507474 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 00:25:07.514140 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 00:25:07.517375 1 4 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
8018 00:25:07.520623 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
8019 00:25:07.527023 1 4 16 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
8020 00:25:07.530491 1 4 20 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8021 00:25:07.534167 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8022 00:25:07.540640 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8023 00:25:07.544063 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8024 00:25:07.547138 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8025 00:25:07.553747 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
8026 00:25:07.557318 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
8027 00:25:07.560286 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8028 00:25:07.566936 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8029 00:25:07.570187 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 00:25:07.573533 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 00:25:07.580028 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 00:25:07.583551 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8033 00:25:07.586519 1 6 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8034 00:25:07.593565 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8035 00:25:07.596625 1 6 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8036 00:25:07.599858 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 00:25:07.606696 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 00:25:07.609778 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 00:25:07.613153 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 00:25:07.619821 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 00:25:07.623431 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8042 00:25:07.626804 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8043 00:25:07.632816 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8044 00:25:07.636144 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8045 00:25:07.639580 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 00:25:07.646118 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 00:25:07.649450 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 00:25:07.652458 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 00:25:07.659621 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 00:25:07.662781 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 00:25:07.665486 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 00:25:07.672296 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 00:25:07.675847 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 00:25:07.678728 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 00:25:07.685518 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 00:25:07.688663 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8057 00:25:07.692243 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8058 00:25:07.698530 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8059 00:25:07.701872 Total UI for P1: 0, mck2ui 16
8060 00:25:07.705141 best dqsien dly found for B0: ( 1, 9, 6)
8061 00:25:07.708715 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8062 00:25:07.712090 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8063 00:25:07.718363 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8064 00:25:07.721796 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 00:25:07.725105 Total UI for P1: 0, mck2ui 16
8066 00:25:07.727912 best dqsien dly found for B1: ( 1, 9, 20)
8067 00:25:07.732209 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8068 00:25:07.734609 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8069 00:25:07.734689
8070 00:25:07.738112 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8071 00:25:07.744844 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8072 00:25:07.744925 [Gating] SW calibration Done
8073 00:25:07.744990 ==
8074 00:25:07.748308 Dram Type= 6, Freq= 0, CH_0, rank 1
8075 00:25:07.754461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8076 00:25:07.754542 ==
8077 00:25:07.754607 RX Vref Scan: 0
8078 00:25:07.754667
8079 00:25:07.758074 RX Vref 0 -> 0, step: 1
8080 00:25:07.758154
8081 00:25:07.761196 RX Delay 0 -> 252, step: 8
8082 00:25:07.764506 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8083 00:25:07.767784 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8084 00:25:07.770921 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8085 00:25:07.777820 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8086 00:25:07.780966 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8087 00:25:07.784181 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8088 00:25:07.787939 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8089 00:25:07.790767 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8090 00:25:07.797303 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8091 00:25:07.800524 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8092 00:25:07.804020 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8093 00:25:07.807028 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8094 00:25:07.813684 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8095 00:25:07.816790 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8096 00:25:07.820279 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8097 00:25:07.824178 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8098 00:25:07.824259 ==
8099 00:25:07.827206 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 00:25:07.833496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 00:25:07.833578 ==
8102 00:25:07.833642 DQS Delay:
8103 00:25:07.833702 DQS0 = 0, DQS1 = 0
8104 00:25:07.837438 DQM Delay:
8105 00:25:07.837519 DQM0 = 132, DQM1 = 127
8106 00:25:07.840647 DQ Delay:
8107 00:25:07.843953 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8108 00:25:07.847171 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8109 00:25:07.849837 DQ8 =119, DQ9 =111, DQ10 =131, DQ11 =119
8110 00:25:07.853245 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8111 00:25:07.853326
8112 00:25:07.853390
8113 00:25:07.853449 ==
8114 00:25:07.856786 Dram Type= 6, Freq= 0, CH_0, rank 1
8115 00:25:07.859980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8116 00:25:07.863215 ==
8117 00:25:07.863296
8118 00:25:07.863360
8119 00:25:07.863419 TX Vref Scan disable
8120 00:25:07.866698 == TX Byte 0 ==
8121 00:25:07.869942 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8122 00:25:07.872991 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8123 00:25:07.876577 == TX Byte 1 ==
8124 00:25:07.879836 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8125 00:25:07.883878 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8126 00:25:07.886593 ==
8127 00:25:07.889713 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 00:25:07.893236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 00:25:07.893317 ==
8130 00:25:07.906665
8131 00:25:07.909919 TX Vref early break, caculate TX vref
8132 00:25:07.912819 TX Vref=16, minBit 9, minWin=22, winSum=381
8133 00:25:07.916664 TX Vref=18, minBit 8, minWin=23, winSum=388
8134 00:25:07.919616 TX Vref=20, minBit 4, minWin=24, winSum=397
8135 00:25:07.923169 TX Vref=22, minBit 10, minWin=24, winSum=401
8136 00:25:07.926148 TX Vref=24, minBit 10, minWin=24, winSum=408
8137 00:25:07.932654 TX Vref=26, minBit 4, minWin=25, winSum=414
8138 00:25:07.936778 TX Vref=28, minBit 8, minWin=25, winSum=418
8139 00:25:07.939358 TX Vref=30, minBit 1, minWin=25, winSum=412
8140 00:25:07.942614 TX Vref=32, minBit 8, minWin=24, winSum=403
8141 00:25:07.946012 TX Vref=34, minBit 0, minWin=24, winSum=395
8142 00:25:07.952279 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 28
8143 00:25:07.952361
8144 00:25:07.955753 Final TX Range 0 Vref 28
8145 00:25:07.955835
8146 00:25:07.955898 ==
8147 00:25:07.958965 Dram Type= 6, Freq= 0, CH_0, rank 1
8148 00:25:07.962572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8149 00:25:07.962654 ==
8150 00:25:07.962719
8151 00:25:07.965978
8152 00:25:07.966058 TX Vref Scan disable
8153 00:25:07.972387 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8154 00:25:07.972468 == TX Byte 0 ==
8155 00:25:07.975780 u2DelayCellOfst[0]=14 cells (4 PI)
8156 00:25:07.978609 u2DelayCellOfst[1]=17 cells (5 PI)
8157 00:25:07.982512 u2DelayCellOfst[2]=10 cells (3 PI)
8158 00:25:07.986060 u2DelayCellOfst[3]=14 cells (4 PI)
8159 00:25:07.988995 u2DelayCellOfst[4]=10 cells (3 PI)
8160 00:25:07.992205 u2DelayCellOfst[5]=0 cells (0 PI)
8161 00:25:07.995630 u2DelayCellOfst[6]=17 cells (5 PI)
8162 00:25:07.998516 u2DelayCellOfst[7]=17 cells (5 PI)
8163 00:25:08.001904 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8164 00:25:08.004959 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8165 00:25:08.008303 == TX Byte 1 ==
8166 00:25:08.012027 u2DelayCellOfst[8]=0 cells (0 PI)
8167 00:25:08.014736 u2DelayCellOfst[9]=0 cells (0 PI)
8168 00:25:08.018341 u2DelayCellOfst[10]=3 cells (1 PI)
8169 00:25:08.021452 u2DelayCellOfst[11]=0 cells (0 PI)
8170 00:25:08.025120 u2DelayCellOfst[12]=10 cells (3 PI)
8171 00:25:08.028247 u2DelayCellOfst[13]=10 cells (3 PI)
8172 00:25:08.032498 u2DelayCellOfst[14]=14 cells (4 PI)
8173 00:25:08.032583 u2DelayCellOfst[15]=10 cells (3 PI)
8174 00:25:08.038226 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8175 00:25:08.041226 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8176 00:25:08.044919 DramC Write-DBI on
8177 00:25:08.045003 ==
8178 00:25:08.048386 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 00:25:08.051442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 00:25:08.051527 ==
8181 00:25:08.051613
8182 00:25:08.051693
8183 00:25:08.054530 TX Vref Scan disable
8184 00:25:08.057699 == TX Byte 0 ==
8185 00:25:08.061277 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8186 00:25:08.061361 == TX Byte 1 ==
8187 00:25:08.067795 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8188 00:25:08.067878 DramC Write-DBI off
8189 00:25:08.068004
8190 00:25:08.068086 [DATLAT]
8191 00:25:08.071562 Freq=1600, CH0 RK1
8192 00:25:08.071637
8193 00:25:08.074224 DATLAT Default: 0xf
8194 00:25:08.074309 0, 0xFFFF, sum = 0
8195 00:25:08.077660 1, 0xFFFF, sum = 0
8196 00:25:08.077746 2, 0xFFFF, sum = 0
8197 00:25:08.081426 3, 0xFFFF, sum = 0
8198 00:25:08.081511 4, 0xFFFF, sum = 0
8199 00:25:08.084261 5, 0xFFFF, sum = 0
8200 00:25:08.084346 6, 0xFFFF, sum = 0
8201 00:25:08.088104 7, 0xFFFF, sum = 0
8202 00:25:08.088189 8, 0xFFFF, sum = 0
8203 00:25:08.090581 9, 0xFFFF, sum = 0
8204 00:25:08.090666 10, 0xFFFF, sum = 0
8205 00:25:08.093891 11, 0xFFFF, sum = 0
8206 00:25:08.093977 12, 0xFFFF, sum = 0
8207 00:25:08.098073 13, 0xFFFF, sum = 0
8208 00:25:08.098157 14, 0x0, sum = 1
8209 00:25:08.100803 15, 0x0, sum = 2
8210 00:25:08.100891 16, 0x0, sum = 3
8211 00:25:08.104084 17, 0x0, sum = 4
8212 00:25:08.104172 best_step = 15
8213 00:25:08.104274
8214 00:25:08.104426 ==
8215 00:25:08.107816 Dram Type= 6, Freq= 0, CH_0, rank 1
8216 00:25:08.113694 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8217 00:25:08.113779 ==
8218 00:25:08.113864 RX Vref Scan: 0
8219 00:25:08.113945
8220 00:25:08.117563 RX Vref 0 -> 0, step: 1
8221 00:25:08.117647
8222 00:25:08.120143 RX Delay 11 -> 252, step: 4
8223 00:25:08.124022 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8224 00:25:08.126831 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8225 00:25:08.133522 iDelay=191, Bit 2, Center 126 (75 ~ 178) 104
8226 00:25:08.137112 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8227 00:25:08.139968 iDelay=191, Bit 4, Center 130 (83 ~ 178) 96
8228 00:25:08.143337 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8229 00:25:08.146524 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8230 00:25:08.153495 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8231 00:25:08.156473 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8232 00:25:08.159584 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8233 00:25:08.163118 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8234 00:25:08.166232 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8235 00:25:08.172893 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8236 00:25:08.176149 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8237 00:25:08.179391 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8238 00:25:08.182739 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8239 00:25:08.182820 ==
8240 00:25:08.185944 Dram Type= 6, Freq= 0, CH_0, rank 1
8241 00:25:08.192883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8242 00:25:08.192964 ==
8243 00:25:08.193028 DQS Delay:
8244 00:25:08.195802 DQS0 = 0, DQS1 = 0
8245 00:25:08.195882 DQM Delay:
8246 00:25:08.199284 DQM0 = 128, DQM1 = 123
8247 00:25:08.199365 DQ Delay:
8248 00:25:08.202873 DQ0 =126, DQ1 =132, DQ2 =126, DQ3 =126
8249 00:25:08.205686 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =134
8250 00:25:08.209237 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8251 00:25:08.212713 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8252 00:25:08.212794
8253 00:25:08.212858
8254 00:25:08.212917
8255 00:25:08.216553 [DramC_TX_OE_Calibration] TA2
8256 00:25:08.219250 Original DQ_B0 (3 6) =30, OEN = 27
8257 00:25:08.222493 Original DQ_B1 (3 6) =30, OEN = 27
8258 00:25:08.225808 24, 0x0, End_B0=24 End_B1=24
8259 00:25:08.229151 25, 0x0, End_B0=25 End_B1=25
8260 00:25:08.229232 26, 0x0, End_B0=26 End_B1=26
8261 00:25:08.232546 27, 0x0, End_B0=27 End_B1=27
8262 00:25:08.235800 28, 0x0, End_B0=28 End_B1=28
8263 00:25:08.239276 29, 0x0, End_B0=29 End_B1=29
8264 00:25:08.239358 30, 0x0, End_B0=30 End_B1=30
8265 00:25:08.242097 31, 0x4141, End_B0=30 End_B1=30
8266 00:25:08.245491 Byte0 end_step=30 best_step=27
8267 00:25:08.248797 Byte1 end_step=30 best_step=27
8268 00:25:08.252169 Byte0 TX OE(2T, 0.5T) = (3, 3)
8269 00:25:08.255476 Byte1 TX OE(2T, 0.5T) = (3, 3)
8270 00:25:08.255556
8271 00:25:08.255620
8272 00:25:08.261944 [DQSOSCAuto] RK1, (LSB)MR18= 0x1614, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
8273 00:25:08.265192 CH0 RK1: MR19=303, MR18=1614
8274 00:25:08.271938 CH0_RK1: MR19=0x303, MR18=0x1614, DQSOSC=398, MR23=63, INC=23, DEC=15
8275 00:25:08.275251 [RxdqsGatingPostProcess] freq 1600
8276 00:25:08.281719 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8277 00:25:08.285096 best DQS0 dly(2T, 0.5T) = (1, 1)
8278 00:25:08.285177 best DQS1 dly(2T, 0.5T) = (1, 1)
8279 00:25:08.288987 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8280 00:25:08.291471 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8281 00:25:08.294805 best DQS0 dly(2T, 0.5T) = (1, 1)
8282 00:25:08.298430 best DQS1 dly(2T, 0.5T) = (1, 1)
8283 00:25:08.301794 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8284 00:25:08.305149 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8285 00:25:08.308349 Pre-setting of DQS Precalculation
8286 00:25:08.311657 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8287 00:25:08.314814 ==
8288 00:25:08.318112 Dram Type= 6, Freq= 0, CH_1, rank 0
8289 00:25:08.321396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8290 00:25:08.321477 ==
8291 00:25:08.328110 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8292 00:25:08.330893 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8293 00:25:08.334255 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8294 00:25:08.341109 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8295 00:25:08.349925 [CA 0] Center 41 (12~71) winsize 60
8296 00:25:08.353223 [CA 1] Center 42 (12~72) winsize 61
8297 00:25:08.356136 [CA 2] Center 38 (9~67) winsize 59
8298 00:25:08.359348 [CA 3] Center 37 (8~66) winsize 59
8299 00:25:08.362616 [CA 4] Center 38 (8~68) winsize 61
8300 00:25:08.365905 [CA 5] Center 36 (7~66) winsize 60
8301 00:25:08.365985
8302 00:25:08.369265 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8303 00:25:08.369346
8304 00:25:08.372481 [CATrainingPosCal] consider 1 rank data
8305 00:25:08.375871 u2DelayCellTimex100 = 275/100 ps
8306 00:25:08.379623 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8307 00:25:08.386012 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8308 00:25:08.389075 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8309 00:25:08.392785 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8310 00:25:08.395425 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8311 00:25:08.399324 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8312 00:25:08.399404
8313 00:25:08.402801 CA PerBit enable=1, Macro0, CA PI delay=36
8314 00:25:08.402880
8315 00:25:08.406138 [CBTSetCACLKResult] CA Dly = 36
8316 00:25:08.409452 CS Dly: 8 (0~39)
8317 00:25:08.412412 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8318 00:25:08.416000 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8319 00:25:08.416080 ==
8320 00:25:08.418487 Dram Type= 6, Freq= 0, CH_1, rank 1
8321 00:25:08.422173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8322 00:25:08.425626 ==
8323 00:25:08.429009 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8324 00:25:08.432027 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8325 00:25:08.438689 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8326 00:25:08.445464 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8327 00:25:08.452727 [CA 0] Center 41 (11~71) winsize 61
8328 00:25:08.456086 [CA 1] Center 41 (12~71) winsize 60
8329 00:25:08.459920 [CA 2] Center 37 (8~67) winsize 60
8330 00:25:08.462388 [CA 3] Center 36 (7~65) winsize 59
8331 00:25:08.465602 [CA 4] Center 37 (7~67) winsize 61
8332 00:25:08.469131 [CA 5] Center 35 (6~65) winsize 60
8333 00:25:08.469211
8334 00:25:08.472586 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8335 00:25:08.472681
8336 00:25:08.476041 [CATrainingPosCal] consider 2 rank data
8337 00:25:08.479110 u2DelayCellTimex100 = 275/100 ps
8338 00:25:08.482429 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8339 00:25:08.489178 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8340 00:25:08.492560 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8341 00:25:08.495500 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8342 00:25:08.499901 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8343 00:25:08.502722 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8344 00:25:08.503135
8345 00:25:08.505514 CA PerBit enable=1, Macro0, CA PI delay=36
8346 00:25:08.505925
8347 00:25:08.509049 [CBTSetCACLKResult] CA Dly = 36
8348 00:25:08.511801 CS Dly: 10 (0~43)
8349 00:25:08.515222 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8350 00:25:08.518276 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8351 00:25:08.518367
8352 00:25:08.521760 ----->DramcWriteLeveling(PI) begin...
8353 00:25:08.521940 ==
8354 00:25:08.525212 Dram Type= 6, Freq= 0, CH_1, rank 0
8355 00:25:08.531550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8356 00:25:08.531711 ==
8357 00:25:08.535133 Write leveling (Byte 0): 23 => 23
8358 00:25:08.538473 Write leveling (Byte 1): 28 => 28
8359 00:25:08.538593 DramcWriteLeveling(PI) end<-----
8360 00:25:08.538688
8361 00:25:08.541599 ==
8362 00:25:08.545121 Dram Type= 6, Freq= 0, CH_1, rank 0
8363 00:25:08.548098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8364 00:25:08.548246 ==
8365 00:25:08.551542 [Gating] SW mode calibration
8366 00:25:08.558279 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8367 00:25:08.562043 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8368 00:25:08.567889 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 00:25:08.571603 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 00:25:08.575117 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 00:25:08.581245 1 4 12 | B1->B0 | 2626 3333 | 0 1 | (0 0) (1 1)
8372 00:25:08.584737 1 4 16 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8373 00:25:08.588172 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 00:25:08.594863 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 00:25:08.598609 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 00:25:08.601045 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 00:25:08.607586 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 00:25:08.611583 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
8379 00:25:08.617661 1 5 12 | B1->B0 | 3030 2323 | 1 0 | (1 0) (1 0)
8380 00:25:08.621001 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8381 00:25:08.624277 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 00:25:08.630889 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 00:25:08.634267 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 00:25:08.637797 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 00:25:08.644041 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 00:25:08.647202 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8387 00:25:08.650942 1 6 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
8388 00:25:08.653909 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 00:25:08.660391 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 00:25:08.663856 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 00:25:08.670360 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 00:25:08.674031 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 00:25:08.676797 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 00:25:08.683822 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8395 00:25:08.686986 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8396 00:25:08.690036 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8397 00:25:08.693639 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 00:25:08.700020 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 00:25:08.703451 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 00:25:08.706436 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 00:25:08.712897 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 00:25:08.716285 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 00:25:08.723432 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 00:25:08.726206 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 00:25:08.729743 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 00:25:08.736212 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 00:25:08.739422 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 00:25:08.742767 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 00:25:08.749513 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 00:25:08.752472 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8411 00:25:08.755836 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8412 00:25:08.759690 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8413 00:25:08.762373 Total UI for P1: 0, mck2ui 16
8414 00:25:08.766416 best dqsien dly found for B0: ( 1, 9, 10)
8415 00:25:08.772392 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 00:25:08.775582 Total UI for P1: 0, mck2ui 16
8417 00:25:08.779208 best dqsien dly found for B1: ( 1, 9, 14)
8418 00:25:08.782224 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8419 00:25:08.786443 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8420 00:25:08.786859
8421 00:25:08.789661 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8422 00:25:08.792248 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8423 00:25:08.795087 [Gating] SW calibration Done
8424 00:25:08.795498 ==
8425 00:25:08.798965 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 00:25:08.802785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 00:25:08.805362 ==
8428 00:25:08.805775 RX Vref Scan: 0
8429 00:25:08.806104
8430 00:25:08.808433 RX Vref 0 -> 0, step: 1
8431 00:25:08.808855
8432 00:25:08.812006 RX Delay 0 -> 252, step: 8
8433 00:25:08.815274 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8434 00:25:08.818656 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8435 00:25:08.821661 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8436 00:25:08.825119 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8437 00:25:08.831657 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8438 00:25:08.834779 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8439 00:25:08.837959 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8440 00:25:08.841396 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8441 00:25:08.844799 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8442 00:25:08.851323 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8443 00:25:08.854809 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8444 00:25:08.858133 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8445 00:25:08.860948 iDelay=200, Bit 12, Center 143 (96 ~ 191) 96
8446 00:25:08.864325 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8447 00:25:08.870998 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8448 00:25:08.874614 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8449 00:25:08.875135 ==
8450 00:25:08.877903 Dram Type= 6, Freq= 0, CH_1, rank 0
8451 00:25:08.881248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8452 00:25:08.881781 ==
8453 00:25:08.884326 DQS Delay:
8454 00:25:08.884825 DQS0 = 0, DQS1 = 0
8455 00:25:08.887994 DQM Delay:
8456 00:25:08.888518 DQM0 = 136, DQM1 = 132
8457 00:25:08.888853 DQ Delay:
8458 00:25:08.891028 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8459 00:25:08.898038 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =131
8460 00:25:08.901143 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8461 00:25:08.904521 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =139
8462 00:25:08.905103
8463 00:25:08.905486
8464 00:25:08.905829 ==
8465 00:25:08.907371 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 00:25:08.910868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8467 00:25:08.911316 ==
8468 00:25:08.911646
8469 00:25:08.911986
8470 00:25:08.914140 TX Vref Scan disable
8471 00:25:08.917533 == TX Byte 0 ==
8472 00:25:08.920632 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8473 00:25:08.924019 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8474 00:25:08.927033 == TX Byte 1 ==
8475 00:25:08.930302 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8476 00:25:08.933805 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8477 00:25:08.934218 ==
8478 00:25:08.937048 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 00:25:08.943750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 00:25:08.944343 ==
8481 00:25:08.955794
8482 00:25:08.958535 TX Vref early break, caculate TX vref
8483 00:25:08.961578 TX Vref=16, minBit 8, minWin=21, winSum=366
8484 00:25:08.965135 TX Vref=18, minBit 8, minWin=22, winSum=376
8485 00:25:08.968522 TX Vref=20, minBit 8, minWin=23, winSum=386
8486 00:25:08.972157 TX Vref=22, minBit 0, minWin=24, winSum=395
8487 00:25:08.975243 TX Vref=24, minBit 8, minWin=24, winSum=407
8488 00:25:08.981855 TX Vref=26, minBit 8, minWin=24, winSum=413
8489 00:25:08.985145 TX Vref=28, minBit 0, minWin=26, winSum=421
8490 00:25:08.988617 TX Vref=30, minBit 0, minWin=25, winSum=417
8491 00:25:08.991635 TX Vref=32, minBit 0, minWin=24, winSum=406
8492 00:25:08.995202 TX Vref=34, minBit 0, minWin=24, winSum=397
8493 00:25:09.001808 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 28
8494 00:25:09.002360
8495 00:25:09.004691 Final TX Range 0 Vref 28
8496 00:25:09.005243
8497 00:25:09.005612 ==
8498 00:25:09.008232 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 00:25:09.011296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 00:25:09.011761 ==
8501 00:25:09.012186
8502 00:25:09.012563
8503 00:25:09.014570 TX Vref Scan disable
8504 00:25:09.021954 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8505 00:25:09.022699 == TX Byte 0 ==
8506 00:25:09.024327 u2DelayCellOfst[0]=14 cells (4 PI)
8507 00:25:09.027996 u2DelayCellOfst[1]=10 cells (3 PI)
8508 00:25:09.031065 u2DelayCellOfst[2]=0 cells (0 PI)
8509 00:25:09.034323 u2DelayCellOfst[3]=7 cells (2 PI)
8510 00:25:09.038566 u2DelayCellOfst[4]=10 cells (3 PI)
8511 00:25:09.041681 u2DelayCellOfst[5]=17 cells (5 PI)
8512 00:25:09.044716 u2DelayCellOfst[6]=14 cells (4 PI)
8513 00:25:09.047695 u2DelayCellOfst[7]=7 cells (2 PI)
8514 00:25:09.050837 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8515 00:25:09.054170 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8516 00:25:09.057391 == TX Byte 1 ==
8517 00:25:09.060697 u2DelayCellOfst[8]=0 cells (0 PI)
8518 00:25:09.064227 u2DelayCellOfst[9]=3 cells (1 PI)
8519 00:25:09.067801 u2DelayCellOfst[10]=7 cells (2 PI)
8520 00:25:09.068399 u2DelayCellOfst[11]=3 cells (1 PI)
8521 00:25:09.070755 u2DelayCellOfst[12]=10 cells (3 PI)
8522 00:25:09.073776 u2DelayCellOfst[13]=14 cells (4 PI)
8523 00:25:09.077291 u2DelayCellOfst[14]=14 cells (4 PI)
8524 00:25:09.080453 u2DelayCellOfst[15]=14 cells (4 PI)
8525 00:25:09.087222 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8526 00:25:09.090644 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8527 00:25:09.091204 DramC Write-DBI on
8528 00:25:09.094103 ==
8529 00:25:09.094663 Dram Type= 6, Freq= 0, CH_1, rank 0
8530 00:25:09.100653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8531 00:25:09.101215 ==
8532 00:25:09.101584
8533 00:25:09.101924
8534 00:25:09.103896 TX Vref Scan disable
8535 00:25:09.104501 == TX Byte 0 ==
8536 00:25:09.110105 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8537 00:25:09.110579 == TX Byte 1 ==
8538 00:25:09.113565 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8539 00:25:09.116556 DramC Write-DBI off
8540 00:25:09.117013
8541 00:25:09.117377 [DATLAT]
8542 00:25:09.120151 Freq=1600, CH1 RK0
8543 00:25:09.120668
8544 00:25:09.121032 DATLAT Default: 0xf
8545 00:25:09.123576 0, 0xFFFF, sum = 0
8546 00:25:09.124090 1, 0xFFFF, sum = 0
8547 00:25:09.126536 2, 0xFFFF, sum = 0
8548 00:25:09.126953 3, 0xFFFF, sum = 0
8549 00:25:09.130452 4, 0xFFFF, sum = 0
8550 00:25:09.130874 5, 0xFFFF, sum = 0
8551 00:25:09.132861 6, 0xFFFF, sum = 0
8552 00:25:09.136270 7, 0xFFFF, sum = 0
8553 00:25:09.136711 8, 0xFFFF, sum = 0
8554 00:25:09.139741 9, 0xFFFF, sum = 0
8555 00:25:09.140213 10, 0xFFFF, sum = 0
8556 00:25:09.142812 11, 0xFFFF, sum = 0
8557 00:25:09.143229 12, 0xFFFF, sum = 0
8558 00:25:09.146156 13, 0xFFFF, sum = 0
8559 00:25:09.146693 14, 0x0, sum = 1
8560 00:25:09.149374 15, 0x0, sum = 2
8561 00:25:09.149796 16, 0x0, sum = 3
8562 00:25:09.152958 17, 0x0, sum = 4
8563 00:25:09.153378 best_step = 15
8564 00:25:09.153709
8565 00:25:09.154015 ==
8566 00:25:09.156180 Dram Type= 6, Freq= 0, CH_1, rank 0
8567 00:25:09.160076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8568 00:25:09.163040 ==
8569 00:25:09.163558 RX Vref Scan: 1
8570 00:25:09.163894
8571 00:25:09.166132 Set Vref Range= 24 -> 127
8572 00:25:09.166548
8573 00:25:09.169429 RX Vref 24 -> 127, step: 1
8574 00:25:09.169948
8575 00:25:09.170295 RX Delay 19 -> 252, step: 4
8576 00:25:09.170611
8577 00:25:09.172977 Set Vref, RX VrefLevel [Byte0]: 24
8578 00:25:09.175749 [Byte1]: 24
8579 00:25:09.179662
8580 00:25:09.180240 Set Vref, RX VrefLevel [Byte0]: 25
8581 00:25:09.182970 [Byte1]: 25
8582 00:25:09.187424
8583 00:25:09.187979 Set Vref, RX VrefLevel [Byte0]: 26
8584 00:25:09.190764 [Byte1]: 26
8585 00:25:09.195059
8586 00:25:09.195658 Set Vref, RX VrefLevel [Byte0]: 27
8587 00:25:09.198405 [Byte1]: 27
8588 00:25:09.203243
8589 00:25:09.203802 Set Vref, RX VrefLevel [Byte0]: 28
8590 00:25:09.206207 [Byte1]: 28
8591 00:25:09.210329
8592 00:25:09.210788 Set Vref, RX VrefLevel [Byte0]: 29
8593 00:25:09.213207 [Byte1]: 29
8594 00:25:09.217708
8595 00:25:09.218408 Set Vref, RX VrefLevel [Byte0]: 30
8596 00:25:09.221156 [Byte1]: 30
8597 00:25:09.225417
8598 00:25:09.225959 Set Vref, RX VrefLevel [Byte0]: 31
8599 00:25:09.228512 [Byte1]: 31
8600 00:25:09.232472
8601 00:25:09.233042 Set Vref, RX VrefLevel [Byte0]: 32
8602 00:25:09.236283 [Byte1]: 32
8603 00:25:09.240505
8604 00:25:09.241061 Set Vref, RX VrefLevel [Byte0]: 33
8605 00:25:09.243820 [Byte1]: 33
8606 00:25:09.248328
8607 00:25:09.248921 Set Vref, RX VrefLevel [Byte0]: 34
8608 00:25:09.251527 [Byte1]: 34
8609 00:25:09.255322
8610 00:25:09.256115 Set Vref, RX VrefLevel [Byte0]: 35
8611 00:25:09.258579 [Byte1]: 35
8612 00:25:09.263046
8613 00:25:09.263500 Set Vref, RX VrefLevel [Byte0]: 36
8614 00:25:09.266519 [Byte1]: 36
8615 00:25:09.270537
8616 00:25:09.271090 Set Vref, RX VrefLevel [Byte0]: 37
8617 00:25:09.274021 [Byte1]: 37
8618 00:25:09.278084
8619 00:25:09.278639 Set Vref, RX VrefLevel [Byte0]: 38
8620 00:25:09.281373 [Byte1]: 38
8621 00:25:09.285724
8622 00:25:09.286294 Set Vref, RX VrefLevel [Byte0]: 39
8623 00:25:09.289526 [Byte1]: 39
8624 00:25:09.293440
8625 00:25:09.293893 Set Vref, RX VrefLevel [Byte0]: 40
8626 00:25:09.296373 [Byte1]: 40
8627 00:25:09.300873
8628 00:25:09.301404 Set Vref, RX VrefLevel [Byte0]: 41
8629 00:25:09.304554 [Byte1]: 41
8630 00:25:09.308838
8631 00:25:09.309266 Set Vref, RX VrefLevel [Byte0]: 42
8632 00:25:09.311655 [Byte1]: 42
8633 00:25:09.316001
8634 00:25:09.316418 Set Vref, RX VrefLevel [Byte0]: 43
8635 00:25:09.319647 [Byte1]: 43
8636 00:25:09.323543
8637 00:25:09.324127 Set Vref, RX VrefLevel [Byte0]: 44
8638 00:25:09.326898 [Byte1]: 44
8639 00:25:09.331452
8640 00:25:09.332012 Set Vref, RX VrefLevel [Byte0]: 45
8641 00:25:09.334679 [Byte1]: 45
8642 00:25:09.338972
8643 00:25:09.339530 Set Vref, RX VrefLevel [Byte0]: 46
8644 00:25:09.342457 [Byte1]: 46
8645 00:25:09.346493
8646 00:25:09.346954 Set Vref, RX VrefLevel [Byte0]: 47
8647 00:25:09.349621 [Byte1]: 47
8648 00:25:09.353918
8649 00:25:09.354477 Set Vref, RX VrefLevel [Byte0]: 48
8650 00:25:09.357271 [Byte1]: 48
8651 00:25:09.361757
8652 00:25:09.362243 Set Vref, RX VrefLevel [Byte0]: 49
8653 00:25:09.365340 [Byte1]: 49
8654 00:25:09.368853
8655 00:25:09.369329 Set Vref, RX VrefLevel [Byte0]: 50
8656 00:25:09.372523 [Byte1]: 50
8657 00:25:09.376788
8658 00:25:09.377342 Set Vref, RX VrefLevel [Byte0]: 51
8659 00:25:09.380326 [Byte1]: 51
8660 00:25:09.384598
8661 00:25:09.385155 Set Vref, RX VrefLevel [Byte0]: 52
8662 00:25:09.387753 [Byte1]: 52
8663 00:25:09.392362
8664 00:25:09.392913 Set Vref, RX VrefLevel [Byte0]: 53
8665 00:25:09.395129 [Byte1]: 53
8666 00:25:09.399879
8667 00:25:09.400530 Set Vref, RX VrefLevel [Byte0]: 54
8668 00:25:09.402837 [Byte1]: 54
8669 00:25:09.407109
8670 00:25:09.407663 Set Vref, RX VrefLevel [Byte0]: 55
8671 00:25:09.410416 [Byte1]: 55
8672 00:25:09.414987
8673 00:25:09.415541 Set Vref, RX VrefLevel [Byte0]: 56
8674 00:25:09.418212 [Byte1]: 56
8675 00:25:09.422069
8676 00:25:09.422540 Set Vref, RX VrefLevel [Byte0]: 57
8677 00:25:09.425279 [Byte1]: 57
8678 00:25:09.429878
8679 00:25:09.430502 Set Vref, RX VrefLevel [Byte0]: 58
8680 00:25:09.432871 [Byte1]: 58
8681 00:25:09.437520
8682 00:25:09.437971 Set Vref, RX VrefLevel [Byte0]: 59
8683 00:25:09.443604 [Byte1]: 59
8684 00:25:09.444110
8685 00:25:09.447362 Set Vref, RX VrefLevel [Byte0]: 60
8686 00:25:09.450822 [Byte1]: 60
8687 00:25:09.451412
8688 00:25:09.453955 Set Vref, RX VrefLevel [Byte0]: 61
8689 00:25:09.456474 [Byte1]: 61
8690 00:25:09.456997
8691 00:25:09.460744 Set Vref, RX VrefLevel [Byte0]: 62
8692 00:25:09.463118 [Byte1]: 62
8693 00:25:09.467579
8694 00:25:09.468128 Set Vref, RX VrefLevel [Byte0]: 63
8695 00:25:09.470874 [Byte1]: 63
8696 00:25:09.474958
8697 00:25:09.475370 Set Vref, RX VrefLevel [Byte0]: 64
8698 00:25:09.478643 [Byte1]: 64
8699 00:25:09.482596
8700 00:25:09.483051 Set Vref, RX VrefLevel [Byte0]: 65
8701 00:25:09.485935 [Byte1]: 65
8702 00:25:09.490459
8703 00:25:09.490975 Set Vref, RX VrefLevel [Byte0]: 66
8704 00:25:09.494210 [Byte1]: 66
8705 00:25:09.497867
8706 00:25:09.498458 Set Vref, RX VrefLevel [Byte0]: 67
8707 00:25:09.501360 [Byte1]: 67
8708 00:25:09.505156
8709 00:25:09.505612 Set Vref, RX VrefLevel [Byte0]: 68
8710 00:25:09.508526 [Byte1]: 68
8711 00:25:09.512930
8712 00:25:09.513383 Set Vref, RX VrefLevel [Byte0]: 69
8713 00:25:09.516005 [Byte1]: 69
8714 00:25:09.520529
8715 00:25:09.521043 Set Vref, RX VrefLevel [Byte0]: 70
8716 00:25:09.523752 [Byte1]: 70
8717 00:25:09.528391
8718 00:25:09.528804 Final RX Vref Byte 0 = 59 to rank0
8719 00:25:09.531499 Final RX Vref Byte 1 = 59 to rank0
8720 00:25:09.534608 Final RX Vref Byte 0 = 59 to rank1
8721 00:25:09.537823 Final RX Vref Byte 1 = 59 to rank1==
8722 00:25:09.541241 Dram Type= 6, Freq= 0, CH_1, rank 0
8723 00:25:09.547586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8724 00:25:09.548171 ==
8725 00:25:09.548519 DQS Delay:
8726 00:25:09.551142 DQS0 = 0, DQS1 = 0
8727 00:25:09.551554 DQM Delay:
8728 00:25:09.554248 DQM0 = 132, DQM1 = 130
8729 00:25:09.554700 DQ Delay:
8730 00:25:09.558009 DQ0 =138, DQ1 =130, DQ2 =118, DQ3 =132
8731 00:25:09.560782 DQ4 =130, DQ5 =142, DQ6 =146, DQ7 =126
8732 00:25:09.564568 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =122
8733 00:25:09.567379 DQ12 =140, DQ13 =140, DQ14 =138, DQ15 =138
8734 00:25:09.567997
8735 00:25:09.568344
8736 00:25:09.568656
8737 00:25:09.570849 [DramC_TX_OE_Calibration] TA2
8738 00:25:09.574104 Original DQ_B0 (3 6) =30, OEN = 27
8739 00:25:09.577536 Original DQ_B1 (3 6) =30, OEN = 27
8740 00:25:09.580555 24, 0x0, End_B0=24 End_B1=24
8741 00:25:09.583802 25, 0x0, End_B0=25 End_B1=25
8742 00:25:09.584257 26, 0x0, End_B0=26 End_B1=26
8743 00:25:09.587141 27, 0x0, End_B0=27 End_B1=27
8744 00:25:09.590789 28, 0x0, End_B0=28 End_B1=28
8745 00:25:09.593894 29, 0x0, End_B0=29 End_B1=29
8746 00:25:09.597181 30, 0x0, End_B0=30 End_B1=30
8747 00:25:09.597706 31, 0x4141, End_B0=30 End_B1=30
8748 00:25:09.600793 Byte0 end_step=30 best_step=27
8749 00:25:09.604234 Byte1 end_step=30 best_step=27
8750 00:25:09.606919 Byte0 TX OE(2T, 0.5T) = (3, 3)
8751 00:25:09.610442 Byte1 TX OE(2T, 0.5T) = (3, 3)
8752 00:25:09.610876
8753 00:25:09.611321
8754 00:25:09.616854 [DQSOSCAuto] RK0, (LSB)MR18= 0xf19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
8755 00:25:09.619582 CH1 RK0: MR19=303, MR18=F19
8756 00:25:09.626407 CH1_RK0: MR19=0x303, MR18=0xF19, DQSOSC=397, MR23=63, INC=23, DEC=15
8757 00:25:09.626822
8758 00:25:09.630222 ----->DramcWriteLeveling(PI) begin...
8759 00:25:09.630643 ==
8760 00:25:09.633282 Dram Type= 6, Freq= 0, CH_1, rank 1
8761 00:25:09.636264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8762 00:25:09.636677 ==
8763 00:25:09.639749 Write leveling (Byte 0): 24 => 24
8764 00:25:09.643177 Write leveling (Byte 1): 25 => 25
8765 00:25:09.646456 DramcWriteLeveling(PI) end<-----
8766 00:25:09.646868
8767 00:25:09.647195 ==
8768 00:25:09.649497 Dram Type= 6, Freq= 0, CH_1, rank 1
8769 00:25:09.656038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8770 00:25:09.656456 ==
8771 00:25:09.656807 [Gating] SW mode calibration
8772 00:25:09.665874 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8773 00:25:09.669250 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8774 00:25:09.672892 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 00:25:09.679335 1 4 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8776 00:25:09.682385 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8777 00:25:09.685986 1 4 12 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8778 00:25:09.692796 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 00:25:09.695599 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 00:25:09.699014 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 00:25:09.706390 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 00:25:09.708911 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 00:25:09.712419 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8784 00:25:09.718718 1 5 8 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8785 00:25:09.721882 1 5 12 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
8786 00:25:09.725353 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 00:25:09.731609 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 00:25:09.735266 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 00:25:09.738392 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 00:25:09.745209 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 00:25:09.748506 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8792 00:25:09.755047 1 6 8 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8793 00:25:09.758203 1 6 12 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
8794 00:25:09.761318 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 00:25:09.768189 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 00:25:09.771674 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 00:25:09.774690 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 00:25:09.781086 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 00:25:09.784662 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 00:25:09.787670 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8801 00:25:09.794308 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8802 00:25:09.797731 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8803 00:25:09.801059 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 00:25:09.807450 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 00:25:09.810675 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 00:25:09.814582 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 00:25:09.820552 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 00:25:09.824295 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 00:25:09.827440 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 00:25:09.834504 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 00:25:09.837587 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 00:25:09.841098 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 00:25:09.846899 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 00:25:09.850269 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 00:25:09.853516 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 00:25:09.860380 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8817 00:25:09.860841 Total UI for P1: 0, mck2ui 16
8818 00:25:09.867478 best dqsien dly found for B0: ( 1, 9, 6)
8819 00:25:09.870012 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8820 00:25:09.873899 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 00:25:09.877246 Total UI for P1: 0, mck2ui 16
8822 00:25:09.880302 best dqsien dly found for B1: ( 1, 9, 10)
8823 00:25:09.883803 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8824 00:25:09.886730 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8825 00:25:09.887152
8826 00:25:09.890100 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8827 00:25:09.896605 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8828 00:25:09.897119 [Gating] SW calibration Done
8829 00:25:09.900355 ==
8830 00:25:09.900863 Dram Type= 6, Freq= 0, CH_1, rank 1
8831 00:25:09.906850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8832 00:25:09.907361 ==
8833 00:25:09.907706 RX Vref Scan: 0
8834 00:25:09.908080
8835 00:25:09.909962 RX Vref 0 -> 0, step: 1
8836 00:25:09.910379
8837 00:25:09.912817 RX Delay 0 -> 252, step: 8
8838 00:25:09.916505 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8839 00:25:09.919478 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8840 00:25:09.923151 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8841 00:25:09.929792 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8842 00:25:09.932995 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8843 00:25:09.936423 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8844 00:25:09.939453 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8845 00:25:09.943005 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8846 00:25:09.949535 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8847 00:25:09.952813 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8848 00:25:09.955619 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8849 00:25:09.958927 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8850 00:25:09.965923 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8851 00:25:09.969232 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8852 00:25:09.972462 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8853 00:25:09.975466 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8854 00:25:09.975883 ==
8855 00:25:09.979145 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 00:25:09.985880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 00:25:09.986396 ==
8858 00:25:09.986734 DQS Delay:
8859 00:25:09.987048 DQS0 = 0, DQS1 = 0
8860 00:25:09.989030 DQM Delay:
8861 00:25:09.989461 DQM0 = 136, DQM1 = 130
8862 00:25:09.992132 DQ Delay:
8863 00:25:09.996090 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =131
8864 00:25:09.999499 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =135
8865 00:25:10.002326 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8866 00:25:10.005424 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8867 00:25:10.005899
8868 00:25:10.006228
8869 00:25:10.006534 ==
8870 00:25:10.008805 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 00:25:10.012298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 00:25:10.015502 ==
8873 00:25:10.015953
8874 00:25:10.016508
8875 00:25:10.016851 TX Vref Scan disable
8876 00:25:10.018334 == TX Byte 0 ==
8877 00:25:10.021582 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8878 00:25:10.025133 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8879 00:25:10.028418 == TX Byte 1 ==
8880 00:25:10.032030 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8881 00:25:10.035442 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8882 00:25:10.038470 ==
8883 00:25:10.041599 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 00:25:10.045361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 00:25:10.045891 ==
8886 00:25:10.058396
8887 00:25:10.062151 TX Vref early break, caculate TX vref
8888 00:25:10.064956 TX Vref=16, minBit 9, minWin=22, winSum=376
8889 00:25:10.068174 TX Vref=18, minBit 9, minWin=22, winSum=390
8890 00:25:10.071409 TX Vref=20, minBit 9, minWin=22, winSum=391
8891 00:25:10.074722 TX Vref=22, minBit 9, minWin=23, winSum=404
8892 00:25:10.078105 TX Vref=24, minBit 9, minWin=24, winSum=409
8893 00:25:10.084382 TX Vref=26, minBit 9, minWin=24, winSum=413
8894 00:25:10.088089 TX Vref=28, minBit 9, minWin=24, winSum=420
8895 00:25:10.091550 TX Vref=30, minBit 1, minWin=25, winSum=418
8896 00:25:10.094287 TX Vref=32, minBit 0, minWin=24, winSum=409
8897 00:25:10.097660 TX Vref=34, minBit 9, minWin=23, winSum=400
8898 00:25:10.104316 TX Vref=36, minBit 8, minWin=23, winSum=398
8899 00:25:10.107582 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 30
8900 00:25:10.108193
8901 00:25:10.110593 Final TX Range 0 Vref 30
8902 00:25:10.111150
8903 00:25:10.111516 ==
8904 00:25:10.113632 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 00:25:10.117589 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 00:25:10.120605 ==
8907 00:25:10.121061
8908 00:25:10.121421
8909 00:25:10.121756 TX Vref Scan disable
8910 00:25:10.126907 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8911 00:25:10.127324 == TX Byte 0 ==
8912 00:25:10.130712 u2DelayCellOfst[0]=14 cells (4 PI)
8913 00:25:10.133776 u2DelayCellOfst[1]=10 cells (3 PI)
8914 00:25:10.136983 u2DelayCellOfst[2]=0 cells (0 PI)
8915 00:25:10.140032 u2DelayCellOfst[3]=7 cells (2 PI)
8916 00:25:10.143453 u2DelayCellOfst[4]=7 cells (2 PI)
8917 00:25:10.146781 u2DelayCellOfst[5]=14 cells (4 PI)
8918 00:25:10.150326 u2DelayCellOfst[6]=14 cells (4 PI)
8919 00:25:10.153604 u2DelayCellOfst[7]=7 cells (2 PI)
8920 00:25:10.156526 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8921 00:25:10.159991 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8922 00:25:10.163111 == TX Byte 1 ==
8923 00:25:10.166628 u2DelayCellOfst[8]=0 cells (0 PI)
8924 00:25:10.169764 u2DelayCellOfst[9]=0 cells (0 PI)
8925 00:25:10.173116 u2DelayCellOfst[10]=10 cells (3 PI)
8926 00:25:10.176392 u2DelayCellOfst[11]=3 cells (1 PI)
8927 00:25:10.179682 u2DelayCellOfst[12]=14 cells (4 PI)
8928 00:25:10.183031 u2DelayCellOfst[13]=14 cells (4 PI)
8929 00:25:10.186528 u2DelayCellOfst[14]=17 cells (5 PI)
8930 00:25:10.189612 u2DelayCellOfst[15]=17 cells (5 PI)
8931 00:25:10.192837 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8932 00:25:10.196002 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8933 00:25:10.199517 DramC Write-DBI on
8934 00:25:10.200000 ==
8935 00:25:10.202617 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 00:25:10.206337 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 00:25:10.206849 ==
8938 00:25:10.207176
8939 00:25:10.207508
8940 00:25:10.209529 TX Vref Scan disable
8941 00:25:10.209963 == TX Byte 0 ==
8942 00:25:10.215968 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8943 00:25:10.216395 == TX Byte 1 ==
8944 00:25:10.222417 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8945 00:25:10.222831 DramC Write-DBI off
8946 00:25:10.223159
8947 00:25:10.223465 [DATLAT]
8948 00:25:10.225507 Freq=1600, CH1 RK1
8949 00:25:10.225945
8950 00:25:10.229590 DATLAT Default: 0xf
8951 00:25:10.230116 0, 0xFFFF, sum = 0
8952 00:25:10.232394 1, 0xFFFF, sum = 0
8953 00:25:10.232808 2, 0xFFFF, sum = 0
8954 00:25:10.235602 3, 0xFFFF, sum = 0
8955 00:25:10.236295 4, 0xFFFF, sum = 0
8956 00:25:10.238612 5, 0xFFFF, sum = 0
8957 00:25:10.239029 6, 0xFFFF, sum = 0
8958 00:25:10.242120 7, 0xFFFF, sum = 0
8959 00:25:10.242538 8, 0xFFFF, sum = 0
8960 00:25:10.245446 9, 0xFFFF, sum = 0
8961 00:25:10.245864 10, 0xFFFF, sum = 0
8962 00:25:10.248622 11, 0xFFFF, sum = 0
8963 00:25:10.249040 12, 0xFFFF, sum = 0
8964 00:25:10.251966 13, 0xFFFF, sum = 0
8965 00:25:10.252383 14, 0x0, sum = 1
8966 00:25:10.255873 15, 0x0, sum = 2
8967 00:25:10.256334 16, 0x0, sum = 3
8968 00:25:10.259248 17, 0x0, sum = 4
8969 00:25:10.259662 best_step = 15
8970 00:25:10.260058
8971 00:25:10.260375 ==
8972 00:25:10.262179 Dram Type= 6, Freq= 0, CH_1, rank 1
8973 00:25:10.269114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8974 00:25:10.269528 ==
8975 00:25:10.269857 RX Vref Scan: 0
8976 00:25:10.270161
8977 00:25:10.271795 RX Vref 0 -> 0, step: 1
8978 00:25:10.272255
8979 00:25:10.275575 RX Delay 19 -> 252, step: 4
8980 00:25:10.278555 iDelay=195, Bit 0, Center 138 (87 ~ 190) 104
8981 00:25:10.282388 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8982 00:25:10.288520 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8983 00:25:10.291555 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8984 00:25:10.295620 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8985 00:25:10.298318 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8986 00:25:10.301661 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8987 00:25:10.308238 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8988 00:25:10.311417 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8989 00:25:10.314630 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8990 00:25:10.318588 iDelay=195, Bit 10, Center 130 (75 ~ 186) 112
8991 00:25:10.321164 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8992 00:25:10.328271 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8993 00:25:10.331327 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8994 00:25:10.334499 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8995 00:25:10.338084 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8996 00:25:10.338588 ==
8997 00:25:10.341362 Dram Type= 6, Freq= 0, CH_1, rank 1
8998 00:25:10.347964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8999 00:25:10.348433 ==
9000 00:25:10.348766 DQS Delay:
9001 00:25:10.350938 DQS0 = 0, DQS1 = 0
9002 00:25:10.351474 DQM Delay:
9003 00:25:10.351980 DQM0 = 133, DQM1 = 127
9004 00:25:10.354189 DQ Delay:
9005 00:25:10.357403 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =128
9006 00:25:10.361485 DQ4 =132, DQ5 =144, DQ6 =140, DQ7 =130
9007 00:25:10.364170 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =120
9008 00:25:10.368001 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =136
9009 00:25:10.368477
9010 00:25:10.368960
9011 00:25:10.369279
9012 00:25:10.371207 [DramC_TX_OE_Calibration] TA2
9013 00:25:10.374631 Original DQ_B0 (3 6) =30, OEN = 27
9014 00:25:10.377586 Original DQ_B1 (3 6) =30, OEN = 27
9015 00:25:10.380616 24, 0x0, End_B0=24 End_B1=24
9016 00:25:10.383874 25, 0x0, End_B0=25 End_B1=25
9017 00:25:10.384345 26, 0x0, End_B0=26 End_B1=26
9018 00:25:10.387369 27, 0x0, End_B0=27 End_B1=27
9019 00:25:10.390421 28, 0x0, End_B0=28 End_B1=28
9020 00:25:10.394295 29, 0x0, End_B0=29 End_B1=29
9021 00:25:10.394713 30, 0x0, End_B0=30 End_B1=30
9022 00:25:10.397487 31, 0x4141, End_B0=30 End_B1=30
9023 00:25:10.400485 Byte0 end_step=30 best_step=27
9024 00:25:10.403895 Byte1 end_step=30 best_step=27
9025 00:25:10.407582 Byte0 TX OE(2T, 0.5T) = (3, 3)
9026 00:25:10.410753 Byte1 TX OE(2T, 0.5T) = (3, 3)
9027 00:25:10.411162
9028 00:25:10.411480
9029 00:25:10.417258 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
9030 00:25:10.420260 CH1 RK1: MR19=303, MR18=E1C
9031 00:25:10.426760 CH1_RK1: MR19=0x303, MR18=0xE1C, DQSOSC=395, MR23=63, INC=23, DEC=15
9032 00:25:10.429892 [RxdqsGatingPostProcess] freq 1600
9033 00:25:10.433590 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9034 00:25:10.437034 best DQS0 dly(2T, 0.5T) = (1, 1)
9035 00:25:10.440227 best DQS1 dly(2T, 0.5T) = (1, 1)
9036 00:25:10.443485 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9037 00:25:10.446336 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9038 00:25:10.449902 best DQS0 dly(2T, 0.5T) = (1, 1)
9039 00:25:10.453403 best DQS1 dly(2T, 0.5T) = (1, 1)
9040 00:25:10.456701 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9041 00:25:10.460485 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9042 00:25:10.463081 Pre-setting of DQS Precalculation
9043 00:25:10.466347 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9044 00:25:10.476156 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9045 00:25:10.482880 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9046 00:25:10.483292
9047 00:25:10.483618
9048 00:25:10.485869 [Calibration Summary] 3200 Mbps
9049 00:25:10.486279 CH 0, Rank 0
9050 00:25:10.489746 SW Impedance : PASS
9051 00:25:10.490237 DUTY Scan : NO K
9052 00:25:10.492776 ZQ Calibration : PASS
9053 00:25:10.496062 Jitter Meter : NO K
9054 00:25:10.496478 CBT Training : PASS
9055 00:25:10.499235 Write leveling : PASS
9056 00:25:10.502979 RX DQS gating : PASS
9057 00:25:10.503650 RX DQ/DQS(RDDQC) : PASS
9058 00:25:10.505891 TX DQ/DQS : PASS
9059 00:25:10.509161 RX DATLAT : PASS
9060 00:25:10.509704 RX DQ/DQS(Engine): PASS
9061 00:25:10.512423 TX OE : PASS
9062 00:25:10.512956 All Pass.
9063 00:25:10.513296
9064 00:25:10.516775 CH 0, Rank 1
9065 00:25:10.517234 SW Impedance : PASS
9066 00:25:10.519534 DUTY Scan : NO K
9067 00:25:10.522161 ZQ Calibration : PASS
9068 00:25:10.522585 Jitter Meter : NO K
9069 00:25:10.525589 CBT Training : PASS
9070 00:25:10.529474 Write leveling : PASS
9071 00:25:10.529917 RX DQS gating : PASS
9072 00:25:10.532304 RX DQ/DQS(RDDQC) : PASS
9073 00:25:10.535557 TX DQ/DQS : PASS
9074 00:25:10.536039 RX DATLAT : PASS
9075 00:25:10.538869 RX DQ/DQS(Engine): PASS
9076 00:25:10.539280 TX OE : PASS
9077 00:25:10.542720 All Pass.
9078 00:25:10.543132
9079 00:25:10.543460 CH 1, Rank 0
9080 00:25:10.545427 SW Impedance : PASS
9081 00:25:10.545868 DUTY Scan : NO K
9082 00:25:10.549056 ZQ Calibration : PASS
9083 00:25:10.552064 Jitter Meter : NO K
9084 00:25:10.552479 CBT Training : PASS
9085 00:25:10.555147 Write leveling : PASS
9086 00:25:10.558608 RX DQS gating : PASS
9087 00:25:10.559024 RX DQ/DQS(RDDQC) : PASS
9088 00:25:10.561781 TX DQ/DQS : PASS
9089 00:25:10.565231 RX DATLAT : PASS
9090 00:25:10.565646 RX DQ/DQS(Engine): PASS
9091 00:25:10.568563 TX OE : PASS
9092 00:25:10.568975 All Pass.
9093 00:25:10.569304
9094 00:25:10.571706 CH 1, Rank 1
9095 00:25:10.572194 SW Impedance : PASS
9096 00:25:10.575257 DUTY Scan : NO K
9097 00:25:10.578232 ZQ Calibration : PASS
9098 00:25:10.578650 Jitter Meter : NO K
9099 00:25:10.581623 CBT Training : PASS
9100 00:25:10.585270 Write leveling : PASS
9101 00:25:10.585690 RX DQS gating : PASS
9102 00:25:10.588425 RX DQ/DQS(RDDQC) : PASS
9103 00:25:10.591451 TX DQ/DQS : PASS
9104 00:25:10.591885 RX DATLAT : PASS
9105 00:25:10.594773 RX DQ/DQS(Engine): PASS
9106 00:25:10.598068 TX OE : PASS
9107 00:25:10.598482 All Pass.
9108 00:25:10.598810
9109 00:25:10.599116 DramC Write-DBI on
9110 00:25:10.601225 PER_BANK_REFRESH: Hybrid Mode
9111 00:25:10.604351 TX_TRACKING: ON
9112 00:25:10.614248 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9113 00:25:10.621102 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9114 00:25:10.628023 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9115 00:25:10.631172 [FAST_K] Save calibration result to emmc
9116 00:25:10.634424 sync common calibartion params.
9117 00:25:10.637720 sync cbt_mode0:1, 1:1
9118 00:25:10.638133 dram_init: ddr_geometry: 2
9119 00:25:10.642254 dram_init: ddr_geometry: 2
9120 00:25:10.644187 dram_init: ddr_geometry: 2
9121 00:25:10.647246 0:dram_rank_size:100000000
9122 00:25:10.647660 1:dram_rank_size:100000000
9123 00:25:10.653925 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9124 00:25:10.656935 DFS_SHUFFLE_HW_MODE: ON
9125 00:25:10.660459 dramc_set_vcore_voltage set vcore to 725000
9126 00:25:10.663855 Read voltage for 1600, 0
9127 00:25:10.664300 Vio18 = 0
9128 00:25:10.664631 Vcore = 725000
9129 00:25:10.666838 Vdram = 0
9130 00:25:10.667246 Vddq = 0
9131 00:25:10.667570 Vmddr = 0
9132 00:25:10.670360 switch to 3200 Mbps bootup
9133 00:25:10.670773 [DramcRunTimeConfig]
9134 00:25:10.673946 PHYPLL
9135 00:25:10.674355 DPM_CONTROL_AFTERK: ON
9136 00:25:10.676700 PER_BANK_REFRESH: ON
9137 00:25:10.680164 REFRESH_OVERHEAD_REDUCTION: ON
9138 00:25:10.680575 CMD_PICG_NEW_MODE: OFF
9139 00:25:10.683741 XRTWTW_NEW_MODE: ON
9140 00:25:10.684185 XRTRTR_NEW_MODE: ON
9141 00:25:10.687417 TX_TRACKING: ON
9142 00:25:10.687844 RDSEL_TRACKING: OFF
9143 00:25:10.690033 DQS Precalculation for DVFS: ON
9144 00:25:10.693403 RX_TRACKING: OFF
9145 00:25:10.693810 HW_GATING DBG: ON
9146 00:25:10.696585 ZQCS_ENABLE_LP4: ON
9147 00:25:10.696999 RX_PICG_NEW_MODE: ON
9148 00:25:10.700239 TX_PICG_NEW_MODE: ON
9149 00:25:10.703143 ENABLE_RX_DCM_DPHY: ON
9150 00:25:10.703556 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9151 00:25:10.706536 DUMMY_READ_FOR_TRACKING: OFF
9152 00:25:10.710298 !!! SPM_CONTROL_AFTERK: OFF
9153 00:25:10.713433 !!! SPM could not control APHY
9154 00:25:10.713893 IMPEDANCE_TRACKING: ON
9155 00:25:10.716422 TEMP_SENSOR: ON
9156 00:25:10.716833 HW_SAVE_FOR_SR: OFF
9157 00:25:10.719707 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9158 00:25:10.723312 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9159 00:25:10.726391 Read ODT Tracking: ON
9160 00:25:10.730195 Refresh Rate DeBounce: ON
9161 00:25:10.730803 DFS_NO_QUEUE_FLUSH: ON
9162 00:25:10.732997 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9163 00:25:10.736407 ENABLE_DFS_RUNTIME_MRW: OFF
9164 00:25:10.739878 DDR_RESERVE_NEW_MODE: ON
9165 00:25:10.740334 MR_CBT_SWITCH_FREQ: ON
9166 00:25:10.742678 =========================
9167 00:25:10.762535 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9168 00:25:10.765723 dram_init: ddr_geometry: 2
9169 00:25:10.784121 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9170 00:25:10.787053 dram_init: dram init end (result: 0)
9171 00:25:10.794205 DRAM-K: Full calibration passed in 24426 msecs
9172 00:25:10.797120 MRC: failed to locate region type 0.
9173 00:25:10.797580 DRAM rank0 size:0x100000000,
9174 00:25:10.800368 DRAM rank1 size=0x100000000
9175 00:25:10.810279 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9176 00:25:10.816558 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9177 00:25:10.823447 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9178 00:25:10.833331 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9179 00:25:10.833805 DRAM rank0 size:0x100000000,
9180 00:25:10.836824 DRAM rank1 size=0x100000000
9181 00:25:10.837243 CBMEM:
9182 00:25:10.839664 IMD: root @ 0xfffff000 254 entries.
9183 00:25:10.843329 IMD: root @ 0xffffec00 62 entries.
9184 00:25:10.846443 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9185 00:25:10.852940 WARNING: RO_VPD is uninitialized or empty.
9186 00:25:10.856339 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9187 00:25:10.863880 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9188 00:25:10.876732 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9189 00:25:10.887739 BS: romstage times (exec / console): total (unknown) / 23960 ms
9190 00:25:10.888371
9191 00:25:10.888725
9192 00:25:10.898262 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9193 00:25:10.901178 ARM64: Exception handlers installed.
9194 00:25:10.904418 ARM64: Testing exception
9195 00:25:10.908467 ARM64: Done test exception
9196 00:25:10.908884 Enumerating buses...
9197 00:25:10.911305 Show all devs... Before device enumeration.
9198 00:25:10.914002 Root Device: enabled 1
9199 00:25:10.917723 CPU_CLUSTER: 0: enabled 1
9200 00:25:10.918143 CPU: 00: enabled 1
9201 00:25:10.920943 Compare with tree...
9202 00:25:10.921361 Root Device: enabled 1
9203 00:25:10.924132 CPU_CLUSTER: 0: enabled 1
9204 00:25:10.927308 CPU: 00: enabled 1
9205 00:25:10.927899 Root Device scanning...
9206 00:25:10.930674 scan_static_bus for Root Device
9207 00:25:10.933709 CPU_CLUSTER: 0 enabled
9208 00:25:10.936888 scan_static_bus for Root Device done
9209 00:25:10.940166 scan_bus: bus Root Device finished in 8 msecs
9210 00:25:10.940584 done
9211 00:25:10.946863 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9212 00:25:10.950177 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9213 00:25:10.956614 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9214 00:25:10.963447 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9215 00:25:10.963866 Allocating resources...
9216 00:25:10.966568 Reading resources...
9217 00:25:10.970021 Root Device read_resources bus 0 link: 0
9218 00:25:10.973743 DRAM rank0 size:0x100000000,
9219 00:25:10.974167 DRAM rank1 size=0x100000000
9220 00:25:10.980373 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9221 00:25:10.980789 CPU: 00 missing read_resources
9222 00:25:10.986726 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9223 00:25:10.989676 Root Device read_resources bus 0 link: 0 done
9224 00:25:10.992862 Done reading resources.
9225 00:25:10.996878 Show resources in subtree (Root Device)...After reading.
9226 00:25:10.999900 Root Device child on link 0 CPU_CLUSTER: 0
9227 00:25:11.003049 CPU_CLUSTER: 0 child on link 0 CPU: 00
9228 00:25:11.012802 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9229 00:25:11.013224 CPU: 00
9230 00:25:11.019157 Root Device assign_resources, bus 0 link: 0
9231 00:25:11.022634 CPU_CLUSTER: 0 missing set_resources
9232 00:25:11.025842 Root Device assign_resources, bus 0 link: 0 done
9233 00:25:11.028901 Done setting resources.
9234 00:25:11.032594 Show resources in subtree (Root Device)...After assigning values.
9235 00:25:11.039408 Root Device child on link 0 CPU_CLUSTER: 0
9236 00:25:11.042662 CPU_CLUSTER: 0 child on link 0 CPU: 00
9237 00:25:11.049051 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9238 00:25:11.052588 CPU: 00
9239 00:25:11.053008 Done allocating resources.
9240 00:25:11.059190 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9241 00:25:11.061998 Enabling resources...
9242 00:25:11.062418 done.
9243 00:25:11.065241 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9244 00:25:11.068553 Initializing devices...
9245 00:25:11.069103 Root Device init
9246 00:25:11.072144 init hardware done!
9247 00:25:11.075580 0x00000018: ctrlr->caps
9248 00:25:11.076117 52.000 MHz: ctrlr->f_max
9249 00:25:11.078985 0.400 MHz: ctrlr->f_min
9250 00:25:11.082183 0x40ff8080: ctrlr->voltages
9251 00:25:11.082705 sclk: 390625
9252 00:25:11.083134 Bus Width = 1
9253 00:25:11.085467 sclk: 390625
9254 00:25:11.085885 Bus Width = 1
9255 00:25:11.088204 Early init status = 3
9256 00:25:11.092038 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9257 00:25:11.095686 in-header: 03 fc 00 00 01 00 00 00
9258 00:25:11.098770 in-data: 00
9259 00:25:11.102045 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9260 00:25:11.107318 in-header: 03 fd 00 00 00 00 00 00
9261 00:25:11.110050 in-data:
9262 00:25:11.113151 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9263 00:25:11.116727 in-header: 03 fc 00 00 01 00 00 00
9264 00:25:11.119784 in-data: 00
9265 00:25:11.123195 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9266 00:25:11.127823 in-header: 03 fd 00 00 00 00 00 00
9267 00:25:11.131148 in-data:
9268 00:25:11.134947 [SSUSB] Setting up USB HOST controller...
9269 00:25:11.138099 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9270 00:25:11.141524 [SSUSB] phy power-on done.
9271 00:25:11.144461 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9272 00:25:11.151426 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9273 00:25:11.154367 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9274 00:25:11.160861 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9275 00:25:11.167333 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9276 00:25:11.174563 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9277 00:25:11.180836 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9278 00:25:11.187339 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9279 00:25:11.190776 SPM: binary array size = 0x9dc
9280 00:25:11.193922 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9281 00:25:11.200676 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9282 00:25:11.206930 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9283 00:25:11.213440 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9284 00:25:11.217028 configure_display: Starting display init
9285 00:25:11.251068 anx7625_power_on_init: Init interface.
9286 00:25:11.254985 anx7625_disable_pd_protocol: Disabled PD feature.
9287 00:25:11.257625 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9288 00:25:11.286278 anx7625_start_dp_work: Secure OCM version=00
9289 00:25:11.288987 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9290 00:25:11.303998 sp_tx_get_edid_block: EDID Block = 1
9291 00:25:11.406979 Extracted contents:
9292 00:25:11.410095 header: 00 ff ff ff ff ff ff 00
9293 00:25:11.412889 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9294 00:25:11.416932 version: 01 04
9295 00:25:11.419696 basic params: 95 1f 11 78 0a
9296 00:25:11.423038 chroma info: 76 90 94 55 54 90 27 21 50 54
9297 00:25:11.426408 established: 00 00 00
9298 00:25:11.433082 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9299 00:25:11.435825 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9300 00:25:11.442547 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9301 00:25:11.449488 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9302 00:25:11.456258 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9303 00:25:11.459172 extensions: 00
9304 00:25:11.459626 checksum: fb
9305 00:25:11.460218
9306 00:25:11.462372 Manufacturer: IVO Model 57d Serial Number 0
9307 00:25:11.466373 Made week 0 of 2020
9308 00:25:11.466883 EDID version: 1.4
9309 00:25:11.469706 Digital display
9310 00:25:11.472281 6 bits per primary color channel
9311 00:25:11.472713 DisplayPort interface
9312 00:25:11.476410 Maximum image size: 31 cm x 17 cm
9313 00:25:11.478883 Gamma: 220%
9314 00:25:11.479299 Check DPMS levels
9315 00:25:11.482445 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9316 00:25:11.488776 First detailed timing is preferred timing
9317 00:25:11.489200 Established timings supported:
9318 00:25:11.492201 Standard timings supported:
9319 00:25:11.495586 Detailed timings
9320 00:25:11.499209 Hex of detail: 383680a07038204018303c0035ae10000019
9321 00:25:11.505278 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9322 00:25:11.508725 0780 0798 07c8 0820 hborder 0
9323 00:25:11.512222 0438 043b 0447 0458 vborder 0
9324 00:25:11.515002 -hsync -vsync
9325 00:25:11.515420 Did detailed timing
9326 00:25:11.521410 Hex of detail: 000000000000000000000000000000000000
9327 00:25:11.524913 Manufacturer-specified data, tag 0
9328 00:25:11.528434 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9329 00:25:11.531459 ASCII string: InfoVision
9330 00:25:11.535385 Hex of detail: 000000fe00523134304e574635205248200a
9331 00:25:11.538782 ASCII string: R140NWF5 RH
9332 00:25:11.539294 Checksum
9333 00:25:11.541596 Checksum: 0xfb (valid)
9334 00:25:11.544870 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9335 00:25:11.548219 DSI data_rate: 832800000 bps
9336 00:25:11.554764 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9337 00:25:11.558362 anx7625_parse_edid: pixelclock(138800).
9338 00:25:11.561412 hactive(1920), hsync(48), hfp(24), hbp(88)
9339 00:25:11.565026 vactive(1080), vsync(12), vfp(3), vbp(17)
9340 00:25:11.568478 anx7625_dsi_config: config dsi.
9341 00:25:11.574416 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9342 00:25:11.588775 anx7625_dsi_config: success to config DSI
9343 00:25:11.591626 anx7625_dp_start: MIPI phy setup OK.
9344 00:25:11.594901 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9345 00:25:11.598487 mtk_ddp_mode_set invalid vrefresh 60
9346 00:25:11.601478 main_disp_path_setup
9347 00:25:11.601894 ovl_layer_smi_id_en
9348 00:25:11.604980 ovl_layer_smi_id_en
9349 00:25:11.605396 ccorr_config
9350 00:25:11.605727 aal_config
9351 00:25:11.608269 gamma_config
9352 00:25:11.608682 postmask_config
9353 00:25:11.611777 dither_config
9354 00:25:11.614686 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9355 00:25:11.621220 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9356 00:25:11.625122 Root Device init finished in 551 msecs
9357 00:25:11.628401 CPU_CLUSTER: 0 init
9358 00:25:11.634515 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9359 00:25:11.640903 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9360 00:25:11.641319 APU_MBOX 0x190000b0 = 0x10001
9361 00:25:11.644752 APU_MBOX 0x190001b0 = 0x10001
9362 00:25:11.647669 APU_MBOX 0x190005b0 = 0x10001
9363 00:25:11.651213 APU_MBOX 0x190006b0 = 0x10001
9364 00:25:11.657592 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9365 00:25:11.667300 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9366 00:25:11.680204 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9367 00:25:11.686322 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9368 00:25:11.698357 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9369 00:25:11.707742 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9370 00:25:11.710488 CPU_CLUSTER: 0 init finished in 81 msecs
9371 00:25:11.713660 Devices initialized
9372 00:25:11.717307 Show all devs... After init.
9373 00:25:11.717839 Root Device: enabled 1
9374 00:25:11.720167 CPU_CLUSTER: 0: enabled 1
9375 00:25:11.723742 CPU: 00: enabled 1
9376 00:25:11.727058 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9377 00:25:11.730281 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9378 00:25:11.733756 ELOG: NV offset 0x57f000 size 0x1000
9379 00:25:11.740609 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9380 00:25:11.746924 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9381 00:25:11.750538 ELOG: Event(17) added with size 13 at 2023-08-14 00:25:13 UTC
9382 00:25:11.756868 out: cmd=0x121: 03 db 21 01 00 00 00 00
9383 00:25:11.760305 in-header: 03 34 00 00 2c 00 00 00
9384 00:25:11.770414 in-data: 2b 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9385 00:25:11.776486 ELOG: Event(A1) added with size 10 at 2023-08-14 00:25:13 UTC
9386 00:25:11.783504 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9387 00:25:11.789686 ELOG: Event(A0) added with size 9 at 2023-08-14 00:25:13 UTC
9388 00:25:11.793227 elog_add_boot_reason: Logged dev mode boot
9389 00:25:11.800251 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9390 00:25:11.800759 Finalize devices...
9391 00:25:11.803760 Devices finalized
9392 00:25:11.806546 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9393 00:25:11.809376 Writing coreboot table at 0xffe64000
9394 00:25:11.812754 0. 000000000010a000-0000000000113fff: RAMSTAGE
9395 00:25:11.818955 1. 0000000040000000-00000000400fffff: RAM
9396 00:25:11.822472 2. 0000000040100000-000000004032afff: RAMSTAGE
9397 00:25:11.826300 3. 000000004032b000-00000000545fffff: RAM
9398 00:25:11.828936 4. 0000000054600000-000000005465ffff: BL31
9399 00:25:11.832760 5. 0000000054660000-00000000ffe63fff: RAM
9400 00:25:11.839138 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9401 00:25:11.841702 7. 0000000100000000-000000023fffffff: RAM
9402 00:25:11.845304 Passing 5 GPIOs to payload:
9403 00:25:11.848623 NAME | PORT | POLARITY | VALUE
9404 00:25:11.855126 EC in RW | 0x000000aa | low | undefined
9405 00:25:11.858568 EC interrupt | 0x00000005 | low | undefined
9406 00:25:11.865893 TPM interrupt | 0x000000ab | high | undefined
9407 00:25:11.868487 SD card detect | 0x00000011 | high | undefined
9408 00:25:11.872756 speaker enable | 0x00000093 | high | undefined
9409 00:25:11.874996 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9410 00:25:11.878784 in-header: 03 f9 00 00 02 00 00 00
9411 00:25:11.882854 in-data: 02 00
9412 00:25:11.885845 ADC[4]: Raw value=902955 ID=7
9413 00:25:11.888780 ADC[3]: Raw value=213177 ID=1
9414 00:25:11.889193 RAM Code: 0x71
9415 00:25:11.892254 ADC[6]: Raw value=74630 ID=0
9416 00:25:11.896205 ADC[5]: Raw value=213916 ID=1
9417 00:25:11.896724 SKU Code: 0x1
9418 00:25:11.902972 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 951a
9419 00:25:11.903533 coreboot table: 964 bytes.
9420 00:25:11.905179 IMD ROOT 0. 0xfffff000 0x00001000
9421 00:25:11.908877 IMD SMALL 1. 0xffffe000 0x00001000
9422 00:25:11.912073 RO MCACHE 2. 0xffffc000 0x00001104
9423 00:25:11.916094 CONSOLE 3. 0xfff7c000 0x00080000
9424 00:25:11.919172 FMAP 4. 0xfff7b000 0x00000452
9425 00:25:11.922401 TIME STAMP 5. 0xfff7a000 0x00000910
9426 00:25:11.925317 VBOOT WORK 6. 0xfff66000 0x00014000
9427 00:25:11.928204 RAMOOPS 7. 0xffe66000 0x00100000
9428 00:25:11.931524 COREBOOT 8. 0xffe64000 0x00002000
9429 00:25:11.935032 IMD small region:
9430 00:25:11.938421 IMD ROOT 0. 0xffffec00 0x00000400
9431 00:25:11.941580 VPD 1. 0xffffeba0 0x0000004c
9432 00:25:11.944717 MMC STATUS 2. 0xffffeb80 0x00000004
9433 00:25:11.951692 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9434 00:25:11.952272 Probing TPM: done!
9435 00:25:11.958883 Connected to device vid:did:rid of 1ae0:0028:00
9436 00:25:11.964733 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9437 00:25:11.968547 Initialized TPM device CR50 revision 0
9438 00:25:11.972358 Checking cr50 for pending updates
9439 00:25:11.977410 Reading cr50 TPM mode
9440 00:25:11.986477 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9441 00:25:11.993416 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9442 00:25:12.032560 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9443 00:25:12.036009 Checking segment from ROM address 0x40100000
9444 00:25:12.039288 Checking segment from ROM address 0x4010001c
9445 00:25:12.045913 Loading segment from ROM address 0x40100000
9446 00:25:12.046345 code (compression=0)
9447 00:25:12.056426 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9448 00:25:12.062855 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9449 00:25:12.063276 it's not compressed!
9450 00:25:12.069461 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9451 00:25:12.075881 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9452 00:25:12.093162 Loading segment from ROM address 0x4010001c
9453 00:25:12.093668 Entry Point 0x80000000
9454 00:25:12.096462 Loaded segments
9455 00:25:12.100113 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9456 00:25:12.106270 Jumping to boot code at 0x80000000(0xffe64000)
9457 00:25:12.113925 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9458 00:25:12.119566 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9459 00:25:12.127831 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9460 00:25:12.130867 Checking segment from ROM address 0x40100000
9461 00:25:12.134487 Checking segment from ROM address 0x4010001c
9462 00:25:12.141124 Loading segment from ROM address 0x40100000
9463 00:25:12.141659 code (compression=1)
9464 00:25:12.147765 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9465 00:25:12.157193 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9466 00:25:12.157702 using LZMA
9467 00:25:12.165770 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9468 00:25:12.172520 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9469 00:25:12.175818 Loading segment from ROM address 0x4010001c
9470 00:25:12.176299 Entry Point 0x54601000
9471 00:25:12.180000 Loaded segments
9472 00:25:12.182516 NOTICE: MT8192 bl31_setup
9473 00:25:12.189489 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9474 00:25:12.193253 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9475 00:25:12.196310 WARNING: region 0:
9476 00:25:12.199405 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 00:25:12.199843 WARNING: region 1:
9478 00:25:12.206337 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9479 00:25:12.209666 WARNING: region 2:
9480 00:25:12.212749 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9481 00:25:12.216352 WARNING: region 3:
9482 00:25:12.219761 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9483 00:25:12.223168 WARNING: region 4:
9484 00:25:12.229741 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9485 00:25:12.230201 WARNING: region 5:
9486 00:25:12.232922 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 00:25:12.236128 WARNING: region 6:
9488 00:25:12.239741 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 00:25:12.242819 WARNING: region 7:
9490 00:25:12.246330 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 00:25:12.253000 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9492 00:25:12.256245 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9493 00:25:12.259588 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9494 00:25:12.266345 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9495 00:25:12.269090 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9496 00:25:12.273352 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9497 00:25:12.279046 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9498 00:25:12.282381 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9499 00:25:12.289243 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9500 00:25:12.292410 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9501 00:25:12.296198 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9502 00:25:12.303365 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9503 00:25:12.306039 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9504 00:25:12.309333 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9505 00:25:12.315748 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9506 00:25:12.319479 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9507 00:25:12.326072 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9508 00:25:12.329384 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9509 00:25:12.332464 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9510 00:25:12.339428 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9511 00:25:12.342525 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9512 00:25:12.346309 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9513 00:25:12.352705 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9514 00:25:12.356232 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9515 00:25:12.363020 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9516 00:25:12.366251 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9517 00:25:12.372526 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9518 00:25:12.375716 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9519 00:25:12.378827 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9520 00:25:12.385890 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9521 00:25:12.388791 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9522 00:25:12.392004 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9523 00:25:12.398862 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9524 00:25:12.402468 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9525 00:25:12.405587 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9526 00:25:12.408723 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9527 00:25:12.415863 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9528 00:25:12.419178 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9529 00:25:12.422371 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9530 00:25:12.425376 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9531 00:25:12.432081 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9532 00:25:12.435404 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9533 00:25:12.438809 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9534 00:25:12.445644 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9535 00:25:12.448548 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9536 00:25:12.452437 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9537 00:25:12.455138 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9538 00:25:12.461626 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9539 00:25:12.465288 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9540 00:25:12.468488 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9541 00:25:12.475417 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9542 00:25:12.479087 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9543 00:25:12.485114 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9544 00:25:12.488754 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9545 00:25:12.495595 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9546 00:25:12.498683 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9547 00:25:12.502148 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9548 00:25:12.508586 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9549 00:25:12.512292 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9550 00:25:12.518657 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9551 00:25:12.521644 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9552 00:25:12.528653 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9553 00:25:12.531695 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9554 00:25:12.538187 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9555 00:25:12.542272 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9556 00:25:12.545172 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9557 00:25:12.552591 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9558 00:25:12.555292 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9559 00:25:12.561532 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9560 00:25:12.564995 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9561 00:25:12.571747 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9562 00:25:12.575070 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9563 00:25:12.578847 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9564 00:25:12.585313 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9565 00:25:12.588565 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9566 00:25:12.595279 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9567 00:25:12.598244 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9568 00:25:12.604823 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9569 00:25:12.607928 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9570 00:25:12.614719 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9571 00:25:12.618113 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9572 00:25:12.621352 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9573 00:25:12.628193 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9574 00:25:12.631226 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9575 00:25:12.638233 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9576 00:25:12.641189 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9577 00:25:12.648029 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9578 00:25:12.651292 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9579 00:25:12.655063 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9580 00:25:12.661564 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9581 00:25:12.664945 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9582 00:25:12.671556 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9583 00:25:12.675305 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9584 00:25:12.681037 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9585 00:25:12.684483 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9586 00:25:12.691209 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9587 00:25:12.694908 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9588 00:25:12.698162 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9589 00:25:12.701990 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9590 00:25:12.708160 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9591 00:25:12.711667 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9592 00:25:12.714543 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9593 00:25:12.722158 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9594 00:25:12.724502 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9595 00:25:12.727627 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9596 00:25:12.734581 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9597 00:25:12.737298 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9598 00:25:12.744417 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9599 00:25:12.747603 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9600 00:25:12.754317 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9601 00:25:12.757501 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9602 00:25:12.760682 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9603 00:25:12.767551 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9604 00:25:12.770499 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9605 00:25:12.777292 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9606 00:25:12.780922 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9607 00:25:12.783992 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9608 00:25:12.787656 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9609 00:25:12.794177 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9610 00:25:12.797964 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9611 00:25:12.800877 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9612 00:25:12.803998 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9613 00:25:12.810841 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9614 00:25:12.814303 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9615 00:25:12.817502 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9616 00:25:12.824550 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9617 00:25:12.828165 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9618 00:25:12.833566 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9619 00:25:12.837188 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9620 00:25:12.840437 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9621 00:25:12.846982 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9622 00:25:12.850373 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9623 00:25:12.856794 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9624 00:25:12.860182 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9625 00:25:12.863622 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9626 00:25:12.870061 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9627 00:25:12.873159 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9628 00:25:12.877053 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9629 00:25:12.884203 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9630 00:25:12.886832 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9631 00:25:12.893726 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9632 00:25:12.896648 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9633 00:25:12.900132 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9634 00:25:12.906496 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9635 00:25:12.910099 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9636 00:25:12.916486 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9637 00:25:12.920264 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9638 00:25:12.923059 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9639 00:25:12.929586 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9640 00:25:12.933080 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9641 00:25:12.939493 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9642 00:25:12.942930 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9643 00:25:12.945954 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9644 00:25:12.952789 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9645 00:25:12.956356 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9646 00:25:12.962585 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9647 00:25:12.965875 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9648 00:25:12.969939 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9649 00:25:12.976177 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9650 00:25:12.979036 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9651 00:25:12.985645 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9652 00:25:12.989233 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9653 00:25:12.992706 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9654 00:25:12.998928 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9655 00:25:13.002120 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9656 00:25:13.008701 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9657 00:25:13.012077 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9658 00:25:13.015972 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9659 00:25:13.022059 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9660 00:25:13.025415 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9661 00:25:13.031836 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9662 00:25:13.035016 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9663 00:25:13.038373 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9664 00:25:13.045082 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9665 00:25:13.048223 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9666 00:25:13.055221 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9667 00:25:13.058694 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9668 00:25:13.065004 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9669 00:25:13.067789 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9670 00:25:13.071159 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9671 00:25:13.077540 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9672 00:25:13.080546 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9673 00:25:13.087286 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9674 00:25:13.091424 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9675 00:25:13.094177 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9676 00:25:13.100766 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9677 00:25:13.104461 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9678 00:25:13.110702 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9679 00:25:13.113601 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9680 00:25:13.117600 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9681 00:25:13.123803 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9682 00:25:13.127020 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9683 00:25:13.133819 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9684 00:25:13.137127 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9685 00:25:13.143727 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9686 00:25:13.146617 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9687 00:25:13.150226 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9688 00:25:13.156639 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9689 00:25:13.160152 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9690 00:25:13.166397 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9691 00:25:13.169891 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9692 00:25:13.176816 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9693 00:25:13.179998 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9694 00:25:13.182861 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9695 00:25:13.189343 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9696 00:25:13.192991 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9697 00:25:13.199712 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9698 00:25:13.202514 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9699 00:25:13.209630 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9700 00:25:13.212709 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9701 00:25:13.215842 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9702 00:25:13.222692 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9703 00:25:13.226235 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9704 00:25:13.232582 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9705 00:25:13.235440 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9706 00:25:13.242159 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9707 00:25:13.245837 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9708 00:25:13.248671 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9709 00:25:13.255777 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9710 00:25:13.259049 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9711 00:25:13.265018 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9712 00:25:13.268459 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9713 00:25:13.275473 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9714 00:25:13.278502 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9715 00:25:13.282084 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9716 00:25:13.288506 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9717 00:25:13.291785 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9718 00:25:13.298424 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9719 00:25:13.301870 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9720 00:25:13.305489 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9721 00:25:13.311869 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9722 00:25:13.315125 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9723 00:25:13.318233 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9724 00:25:13.321289 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9725 00:25:13.327884 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9726 00:25:13.331228 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9727 00:25:13.338107 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9728 00:25:13.340858 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9729 00:25:13.344478 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9730 00:25:13.351287 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9731 00:25:13.354317 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9732 00:25:13.357250 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9733 00:25:13.363707 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9734 00:25:13.367147 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9735 00:25:13.370476 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9736 00:25:13.377434 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9737 00:25:13.380661 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9738 00:25:13.387369 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9739 00:25:13.390486 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9740 00:25:13.393542 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9741 00:25:13.400443 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9742 00:25:13.403361 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9743 00:25:13.410000 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9744 00:25:13.413598 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9745 00:25:13.417274 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9746 00:25:13.423808 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9747 00:25:13.426356 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9748 00:25:13.433208 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9749 00:25:13.436191 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9750 00:25:13.439790 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9751 00:25:13.446060 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9752 00:25:13.449959 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9753 00:25:13.452914 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9754 00:25:13.459455 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9755 00:25:13.463061 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9756 00:25:13.465833 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9757 00:25:13.473240 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9758 00:25:13.476412 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9759 00:25:13.482174 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9760 00:25:13.485956 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9761 00:25:13.489243 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9762 00:25:13.492540 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9763 00:25:13.495633 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9764 00:25:13.502101 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9765 00:25:13.506243 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9766 00:25:13.509504 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9767 00:25:13.512106 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9768 00:25:13.518671 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9769 00:25:13.521781 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9770 00:25:13.525487 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9771 00:25:13.532349 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9772 00:25:13.535539 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9773 00:25:13.538522 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9774 00:25:13.545125 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9775 00:25:13.548822 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9776 00:25:13.555251 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9777 00:25:13.558204 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9778 00:25:13.562304 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9779 00:25:13.567985 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9780 00:25:13.571236 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9781 00:25:13.578641 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9782 00:25:13.581168 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9783 00:25:13.584929 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9784 00:25:13.591226 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9785 00:25:13.594702 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9786 00:25:13.601422 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9787 00:25:13.604465 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9788 00:25:13.611480 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9789 00:25:13.614452 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9790 00:25:13.617963 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9791 00:25:13.624538 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9792 00:25:13.627792 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9793 00:25:13.634374 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9794 00:25:13.637242 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9795 00:25:13.643780 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9796 00:25:13.647447 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9797 00:25:13.650802 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9798 00:25:13.658580 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9799 00:25:13.662240 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9800 00:25:13.667253 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9801 00:25:13.670584 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9802 00:25:13.673990 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9803 00:25:13.680165 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9804 00:25:13.683675 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9805 00:25:13.690267 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9806 00:25:13.693220 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9807 00:25:13.700313 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9808 00:25:13.703558 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9809 00:25:13.706564 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9810 00:25:13.713175 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9811 00:25:13.716610 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9812 00:25:13.722683 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9813 00:25:13.726276 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9814 00:25:13.733029 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9815 00:25:13.736019 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9816 00:25:13.739725 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9817 00:25:13.746142 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9818 00:25:13.749741 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9819 00:25:13.756225 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9820 00:25:13.759298 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9821 00:25:13.762395 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9822 00:25:13.769203 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9823 00:25:13.772361 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9824 00:25:13.779047 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9825 00:25:13.782228 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9826 00:25:13.788860 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9827 00:25:13.792168 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9828 00:25:13.795332 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9829 00:25:13.801994 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9830 00:25:13.805158 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9831 00:25:13.812265 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9832 00:25:13.815175 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9833 00:25:13.821697 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9834 00:25:13.824896 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9835 00:25:13.828542 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9836 00:25:13.835079 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9837 00:25:13.837846 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9838 00:25:13.845159 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9839 00:25:13.848188 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9840 00:25:13.851793 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9841 00:25:13.857927 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9842 00:25:13.860869 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9843 00:25:13.867767 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9844 00:25:13.871091 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9845 00:25:13.877656 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9846 00:25:13.881107 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9847 00:25:13.884268 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9848 00:25:13.890687 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9849 00:25:13.894895 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9850 00:25:13.901094 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9851 00:25:13.904064 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9852 00:25:13.910613 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9853 00:25:13.913527 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9854 00:25:13.920382 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9855 00:25:13.923892 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9856 00:25:13.930014 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9857 00:25:13.933585 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9858 00:25:13.937098 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9859 00:25:13.943402 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9860 00:25:13.946808 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9861 00:25:13.953284 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9862 00:25:13.956633 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9863 00:25:13.963380 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9864 00:25:13.966242 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9865 00:25:13.973103 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9866 00:25:13.976287 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9867 00:25:13.979597 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9868 00:25:13.986504 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9869 00:25:13.989933 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9870 00:25:13.996552 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9871 00:25:13.999376 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9872 00:25:14.006448 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9873 00:25:14.009106 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9874 00:25:14.016534 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9875 00:25:14.019120 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9876 00:25:14.022867 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9877 00:25:14.029021 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9878 00:25:14.031984 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9879 00:25:14.038528 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9880 00:25:14.042471 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9881 00:25:14.048595 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9882 00:25:14.052140 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9883 00:25:14.058539 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9884 00:25:14.061712 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9885 00:25:14.065515 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9886 00:25:14.072012 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9887 00:25:14.075624 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9888 00:25:14.081565 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9889 00:25:14.084911 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9890 00:25:14.092248 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9891 00:25:14.094967 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9892 00:25:14.098730 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9893 00:25:14.106176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9894 00:25:14.108349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9895 00:25:14.114769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9896 00:25:14.118134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9897 00:25:14.125103 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9898 00:25:14.128076 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9899 00:25:14.134536 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9900 00:25:14.138330 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9901 00:25:14.144884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9902 00:25:14.148032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9903 00:25:14.154072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9904 00:25:14.157251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9905 00:25:14.164253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9906 00:25:14.167483 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9907 00:25:14.174490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9908 00:25:14.177647 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9909 00:25:14.184127 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9910 00:25:14.187952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9911 00:25:14.193564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9912 00:25:14.196921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9913 00:25:14.203658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9914 00:25:14.206915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9915 00:25:14.214026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9916 00:25:14.216659 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9917 00:25:14.224236 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9918 00:25:14.227001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9919 00:25:14.233258 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9920 00:25:14.236962 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9921 00:25:14.243626 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9922 00:25:14.246571 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9923 00:25:14.253413 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9924 00:25:14.256254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9925 00:25:14.263061 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9926 00:25:14.263711 INFO: [APUAPC] vio 0
9927 00:25:14.269472 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9928 00:25:14.273346 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9929 00:25:14.276542 INFO: [APUAPC] D0_APC_0: 0x400510
9930 00:25:14.279544 INFO: [APUAPC] D0_APC_1: 0x0
9931 00:25:14.282503 INFO: [APUAPC] D0_APC_2: 0x1540
9932 00:25:14.286268 INFO: [APUAPC] D0_APC_3: 0x0
9933 00:25:14.289156 INFO: [APUAPC] D1_APC_0: 0xffffffff
9934 00:25:14.292687 INFO: [APUAPC] D1_APC_1: 0xffffffff
9935 00:25:14.295674 INFO: [APUAPC] D1_APC_2: 0x3fffff
9936 00:25:14.299366 INFO: [APUAPC] D1_APC_3: 0x0
9937 00:25:14.302659 INFO: [APUAPC] D2_APC_0: 0xffffffff
9938 00:25:14.305842 INFO: [APUAPC] D2_APC_1: 0xffffffff
9939 00:25:14.308899 INFO: [APUAPC] D2_APC_2: 0x3fffff
9940 00:25:14.312293 INFO: [APUAPC] D2_APC_3: 0x0
9941 00:25:14.316402 INFO: [APUAPC] D3_APC_0: 0xffffffff
9942 00:25:14.319320 INFO: [APUAPC] D3_APC_1: 0xffffffff
9943 00:25:14.322317 INFO: [APUAPC] D3_APC_2: 0x3fffff
9944 00:25:14.325710 INFO: [APUAPC] D3_APC_3: 0x0
9945 00:25:14.328786 INFO: [APUAPC] D4_APC_0: 0xffffffff
9946 00:25:14.333048 INFO: [APUAPC] D4_APC_1: 0xffffffff
9947 00:25:14.335577 INFO: [APUAPC] D4_APC_2: 0x3fffff
9948 00:25:14.338757 INFO: [APUAPC] D4_APC_3: 0x0
9949 00:25:14.342294 INFO: [APUAPC] D5_APC_0: 0xffffffff
9950 00:25:14.345677 INFO: [APUAPC] D5_APC_1: 0xffffffff
9951 00:25:14.348579 INFO: [APUAPC] D5_APC_2: 0x3fffff
9952 00:25:14.352221 INFO: [APUAPC] D5_APC_3: 0x0
9953 00:25:14.355011 INFO: [APUAPC] D6_APC_0: 0xffffffff
9954 00:25:14.358228 INFO: [APUAPC] D6_APC_1: 0xffffffff
9955 00:25:14.361451 INFO: [APUAPC] D6_APC_2: 0x3fffff
9956 00:25:14.361864 INFO: [APUAPC] D6_APC_3: 0x0
9957 00:25:14.368723 INFO: [APUAPC] D7_APC_0: 0xffffffff
9958 00:25:14.371837 INFO: [APUAPC] D7_APC_1: 0xffffffff
9959 00:25:14.375318 INFO: [APUAPC] D7_APC_2: 0x3fffff
9960 00:25:14.375832 INFO: [APUAPC] D7_APC_3: 0x0
9961 00:25:14.378257 INFO: [APUAPC] D8_APC_0: 0xffffffff
9962 00:25:14.385551 INFO: [APUAPC] D8_APC_1: 0xffffffff
9963 00:25:14.388264 INFO: [APUAPC] D8_APC_2: 0x3fffff
9964 00:25:14.388782 INFO: [APUAPC] D8_APC_3: 0x0
9965 00:25:14.391443 INFO: [APUAPC] D9_APC_0: 0xffffffff
9966 00:25:14.394664 INFO: [APUAPC] D9_APC_1: 0xffffffff
9967 00:25:14.398136 INFO: [APUAPC] D9_APC_2: 0x3fffff
9968 00:25:14.401297 INFO: [APUAPC] D9_APC_3: 0x0
9969 00:25:14.404516 INFO: [APUAPC] D10_APC_0: 0xffffffff
9970 00:25:14.407662 INFO: [APUAPC] D10_APC_1: 0xffffffff
9971 00:25:14.411164 INFO: [APUAPC] D10_APC_2: 0x3fffff
9972 00:25:14.414677 INFO: [APUAPC] D10_APC_3: 0x0
9973 00:25:14.417808 INFO: [APUAPC] D11_APC_0: 0xffffffff
9974 00:25:14.421550 INFO: [APUAPC] D11_APC_1: 0xffffffff
9975 00:25:14.425355 INFO: [APUAPC] D11_APC_2: 0x3fffff
9976 00:25:14.428303 INFO: [APUAPC] D11_APC_3: 0x0
9977 00:25:14.431960 INFO: [APUAPC] D12_APC_0: 0xffffffff
9978 00:25:14.438231 INFO: [APUAPC] D12_APC_1: 0xffffffff
9979 00:25:14.441291 INFO: [APUAPC] D12_APC_2: 0x3fffff
9980 00:25:14.441767 INFO: [APUAPC] D12_APC_3: 0x0
9981 00:25:14.445108 INFO: [APUAPC] D13_APC_0: 0xffffffff
9982 00:25:14.451086 INFO: [APUAPC] D13_APC_1: 0xffffffff
9983 00:25:14.454476 INFO: [APUAPC] D13_APC_2: 0x3fffff
9984 00:25:14.455037 INFO: [APUAPC] D13_APC_3: 0x0
9985 00:25:14.460846 INFO: [APUAPC] D14_APC_0: 0xffffffff
9986 00:25:14.464139 INFO: [APUAPC] D14_APC_1: 0xffffffff
9987 00:25:14.467252 INFO: [APUAPC] D14_APC_2: 0x3fffff
9988 00:25:14.471083 INFO: [APUAPC] D14_APC_3: 0x0
9989 00:25:14.474178 INFO: [APUAPC] D15_APC_0: 0xffffffff
9990 00:25:14.477333 INFO: [APUAPC] D15_APC_1: 0xffffffff
9991 00:25:14.480184 INFO: [APUAPC] D15_APC_2: 0x3fffff
9992 00:25:14.483436 INFO: [APUAPC] D15_APC_3: 0x0
9993 00:25:14.483976 INFO: [APUAPC] APC_CON: 0x4
9994 00:25:14.487277 INFO: [NOCDAPC] D0_APC_0: 0x0
9995 00:25:14.490868 INFO: [NOCDAPC] D0_APC_1: 0x0
9996 00:25:14.493840 INFO: [NOCDAPC] D1_APC_0: 0x0
9997 00:25:14.497029 INFO: [NOCDAPC] D1_APC_1: 0xfff
9998 00:25:14.500246 INFO: [NOCDAPC] D2_APC_0: 0x0
9999 00:25:14.503723 INFO: [NOCDAPC] D2_APC_1: 0xfff
10000 00:25:14.507117 INFO: [NOCDAPC] D3_APC_0: 0x0
10001 00:25:14.509883 INFO: [NOCDAPC] D3_APC_1: 0xfff
10002 00:25:14.513305 INFO: [NOCDAPC] D4_APC_0: 0x0
10003 00:25:14.516702 INFO: [NOCDAPC] D4_APC_1: 0xfff
10004 00:25:14.517135 INFO: [NOCDAPC] D5_APC_0: 0x0
10005 00:25:14.519747 INFO: [NOCDAPC] D5_APC_1: 0xfff
10006 00:25:14.523344 INFO: [NOCDAPC] D6_APC_0: 0x0
10007 00:25:14.526391 INFO: [NOCDAPC] D6_APC_1: 0xfff
10008 00:25:14.530499 INFO: [NOCDAPC] D7_APC_0: 0x0
10009 00:25:14.533283 INFO: [NOCDAPC] D7_APC_1: 0xfff
10010 00:25:14.536023 INFO: [NOCDAPC] D8_APC_0: 0x0
10011 00:25:14.539764 INFO: [NOCDAPC] D8_APC_1: 0xfff
10012 00:25:14.542660 INFO: [NOCDAPC] D9_APC_0: 0x0
10013 00:25:14.546600 INFO: [NOCDAPC] D9_APC_1: 0xfff
10014 00:25:14.549277 INFO: [NOCDAPC] D10_APC_0: 0x0
10015 00:25:14.552810 INFO: [NOCDAPC] D10_APC_1: 0xfff
10016 00:25:14.556380 INFO: [NOCDAPC] D11_APC_0: 0x0
10017 00:25:14.560378 INFO: [NOCDAPC] D11_APC_1: 0xfff
10018 00:25:14.560936 INFO: [NOCDAPC] D12_APC_0: 0x0
10019 00:25:14.563298 INFO: [NOCDAPC] D12_APC_1: 0xfff
10020 00:25:14.566031 INFO: [NOCDAPC] D13_APC_0: 0x0
10021 00:25:14.569593 INFO: [NOCDAPC] D13_APC_1: 0xfff
10022 00:25:14.572254 INFO: [NOCDAPC] D14_APC_0: 0x0
10023 00:25:14.576151 INFO: [NOCDAPC] D14_APC_1: 0xfff
10024 00:25:14.579193 INFO: [NOCDAPC] D15_APC_0: 0x0
10025 00:25:14.582509 INFO: [NOCDAPC] D15_APC_1: 0xfff
10026 00:25:14.585645 INFO: [NOCDAPC] APC_CON: 0x4
10027 00:25:14.589107 INFO: [APUAPC] set_apusys_apc done
10028 00:25:14.592305 INFO: [DEVAPC] devapc_init done
10029 00:25:14.595419 INFO: GICv3 without legacy support detected.
10030 00:25:14.599308 INFO: ARM GICv3 driver initialized in EL3
10031 00:25:14.602400 INFO: Maximum SPI INTID supported: 639
10032 00:25:14.609355 INFO: BL31: Initializing runtime services
10033 00:25:14.612752 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10034 00:25:14.615965 INFO: SPM: enable CPC mode
10035 00:25:14.622382 INFO: mcdi ready for mcusys-off-idle and system suspend
10036 00:25:14.625356 INFO: BL31: Preparing for EL3 exit to normal world
10037 00:25:14.628594 INFO: Entry point address = 0x80000000
10038 00:25:14.632107 INFO: SPSR = 0x8
10039 00:25:14.637627
10040 00:25:14.638249
10041 00:25:14.638863
10042 00:25:14.641115 Starting depthcharge on Spherion...
10043 00:25:14.641573
10044 00:25:14.641935 Wipe memory regions:
10045 00:25:14.642270
10046 00:25:14.644955 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10047 00:25:14.645675 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10048 00:25:14.646145 Setting prompt string to ['asurada:']
10049 00:25:14.647676 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10050 00:25:14.648470 [0x00000040000000, 0x00000054600000)
10051 00:25:14.766717
10052 00:25:14.767269 [0x00000054660000, 0x00000080000000)
10053 00:25:15.026860
10054 00:25:15.027246 [0x000000821a7280, 0x000000ffe64000)
10055 00:25:15.772127
10056 00:25:15.772673 [0x00000100000000, 0x00000240000000)
10057 00:25:17.662898
10058 00:25:17.665176 Initializing XHCI USB controller at 0x11200000.
10059 00:25:18.703991
10060 00:25:18.707230 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10061 00:25:18.707772
10062 00:25:18.708300
10063 00:25:18.708623
10064 00:25:18.709349 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10066 00:25:18.810487 asurada: tftpboot 192.168.201.1 11280948/tftp-deploy-u7bwdy0v/kernel/image.itb 11280948/tftp-deploy-u7bwdy0v/kernel/cmdline
10067 00:25:18.811138 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10068 00:25:18.811702 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10069 00:25:18.816892 tftpboot 192.168.201.1 11280948/tftp-deploy-u7bwdy0v/kernel/image.itp-deploy-u7bwdy0v/kernel/cmdline
10070 00:25:18.817451
10071 00:25:18.817813 Waiting for link
10072 00:25:18.977185
10073 00:25:18.977741 R8152: Initializing
10074 00:25:18.978106
10075 00:25:18.980353 Version 6 (ocp_data = 5c30)
10076 00:25:18.980804
10077 00:25:18.983648 R8152: Done initializing
10078 00:25:18.984132
10079 00:25:18.984492 Adding net device
10080 00:25:20.851352
10081 00:25:20.852033 done.
10082 00:25:20.852528
10083 00:25:20.853068 MAC: 00:24:32:30:7c:7b
10084 00:25:20.853520
10085 00:25:20.854679 Sending DHCP discover... done.
10086 00:25:20.855146
10087 00:25:20.857761 Waiting for reply... done.
10088 00:25:20.858503
10089 00:25:20.861013 Sending DHCP request... done.
10090 00:25:20.861471
10091 00:25:20.866848 Waiting for reply... done.
10092 00:25:20.867455
10093 00:25:20.867834 My ip is 192.168.201.14
10094 00:25:20.868225
10095 00:25:20.870591 The DHCP server ip is 192.168.201.1
10096 00:25:20.871151
10097 00:25:20.876545 TFTP server IP predefined by user: 192.168.201.1
10098 00:25:20.877092
10099 00:25:20.882900 Bootfile predefined by user: 11280948/tftp-deploy-u7bwdy0v/kernel/image.itb
10100 00:25:20.883357
10101 00:25:20.886368 Sending tftp read request... done.
10102 00:25:20.886823
10103 00:25:20.893393 Waiting for the transfer...
10104 00:25:20.894037
10105 00:25:21.600308 00000000 ################################################################
10106 00:25:21.600846
10107 00:25:22.234840 00080000 ################################################################
10108 00:25:22.235371
10109 00:25:22.952630 00100000 ################################################################
10110 00:25:22.953165
10111 00:25:23.657399 00180000 ################################################################
10112 00:25:23.657899
10113 00:25:24.371018 00200000 ################################################################
10114 00:25:24.371543
10115 00:25:25.099634 00280000 ################################################################
10116 00:25:25.100196
10117 00:25:25.831123 00300000 ################################################################
10118 00:25:25.831696
10119 00:25:26.554934 00380000 ################################################################
10120 00:25:26.555436
10121 00:25:27.282655 00400000 ################################################################
10122 00:25:27.283179
10123 00:25:27.964197 00480000 ################################################################
10124 00:25:27.964703
10125 00:25:28.652130 00500000 ################################################################
10126 00:25:28.652613
10127 00:25:29.348448 00580000 ################################################################
10128 00:25:29.348933
10129 00:25:30.052065 00600000 ################################################################
10130 00:25:30.052547
10131 00:25:30.751393 00680000 ################################################################
10132 00:25:30.752084
10133 00:25:31.468812 00700000 ################################################################
10134 00:25:31.469330
10135 00:25:32.189173 00780000 ################################################################
10136 00:25:32.189686
10137 00:25:32.912624 00800000 ################################################################
10138 00:25:32.913133
10139 00:25:33.641457 00880000 ################################################################
10140 00:25:33.642035
10141 00:25:34.377134 00900000 ################################################################
10142 00:25:34.377613
10143 00:25:35.051480 00980000 ################################################################
10144 00:25:35.052134
10145 00:25:35.807045 00a00000 ################################################################
10146 00:25:35.807582
10147 00:25:36.489825 00a80000 ################################################################
10148 00:25:36.489975
10149 00:25:37.191402 00b00000 ################################################################
10150 00:25:37.191960
10151 00:25:37.873456 00b80000 ################################################################
10152 00:25:37.873971
10153 00:25:38.597878 00c00000 ################################################################
10154 00:25:38.598391
10155 00:25:39.300336 00c80000 ################################################################
10156 00:25:39.300864
10157 00:25:39.986378 00d00000 ################################################################
10158 00:25:39.986868
10159 00:25:40.697944 00d80000 ################################################################
10160 00:25:40.698438
10161 00:25:41.399072 00e00000 ################################################################
10162 00:25:41.399565
10163 00:25:42.079594 00e80000 ################################################################
10164 00:25:42.080126
10165 00:25:42.777600 00f00000 ################################################################
10166 00:25:42.778303
10167 00:25:43.493512 00f80000 ################################################################
10168 00:25:43.493655
10169 00:25:44.201129 01000000 ################################################################
10170 00:25:44.201673
10171 00:25:44.933287 01080000 ################################################################
10172 00:25:44.933806
10173 00:25:45.644921 01100000 ################################################################
10174 00:25:45.645460
10175 00:25:46.360598 01180000 ################################################################
10176 00:25:46.361193
10177 00:25:47.078982 01200000 ################################################################
10178 00:25:47.079490
10179 00:25:47.761701 01280000 ################################################################
10180 00:25:47.762215
10181 00:25:48.468994 01300000 ################################################################
10182 00:25:48.469506
10183 00:25:49.147181 01380000 ################################################################
10184 00:25:49.147696
10185 00:25:49.875341 01400000 ################################################################
10186 00:25:49.875862
10187 00:25:50.602811 01480000 ################################################################
10188 00:25:50.603335
10189 00:25:51.332857 01500000 ################################################################
10190 00:25:51.333362
10191 00:25:52.035989 01580000 ################################################################
10192 00:25:52.036534
10193 00:25:52.762747 01600000 ################################################################
10194 00:25:52.763273
10195 00:25:53.504429 01680000 ################################################################
10196 00:25:53.504950
10197 00:25:54.237007 01700000 ################################################################
10198 00:25:54.237614
10199 00:25:54.950152 01780000 ################################################################
10200 00:25:54.950662
10201 00:25:55.651070 01800000 ################################################################
10202 00:25:55.651610
10203 00:25:56.363406 01880000 ################################################################
10204 00:25:56.363965
10205 00:25:57.094356 01900000 ################################################################
10206 00:25:57.094880
10207 00:25:57.808514 01980000 ################################################################
10208 00:25:57.809060
10209 00:25:58.527294 01a00000 ################################################################
10210 00:25:58.527853
10211 00:25:59.258510 01a80000 ################################################################
10212 00:25:59.259029
10213 00:25:59.870016 01b00000 ###################################################### done.
10214 00:25:59.870521
10215 00:25:59.873067 The bootfile was 28751774 bytes long.
10216 00:25:59.873486
10217 00:25:59.876609 Sending tftp read request... done.
10218 00:25:59.877069
10219 00:25:59.880739 Waiting for the transfer...
10220 00:25:59.881147
10221 00:25:59.881470 00000000 # done.
10222 00:25:59.881777
10223 00:25:59.886700 Command line loaded dynamically from TFTP file: 11280948/tftp-deploy-u7bwdy0v/kernel/cmdline
10224 00:25:59.890225
10225 00:25:59.911029 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11280948/extract-nfsrootfs-rrkj3bk2,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10226 00:25:59.911604
10227 00:25:59.911986 Loading FIT.
10228 00:25:59.913658
10229 00:25:59.914159 Image ramdisk-1 has 17665145 bytes.
10230 00:25:59.916437
10231 00:25:59.916843 Image fdt-1 has 47278 bytes.
10232 00:25:59.917169
10233 00:25:59.919842 Image kernel-1 has 11037315 bytes.
10234 00:25:59.920443
10235 00:25:59.929585 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10236 00:25:59.930096
10237 00:25:59.946590 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10238 00:25:59.947128
10239 00:25:59.952224 Choosing best match conf-1 for compat google,spherion-rev2.
10240 00:25:59.956654
10241 00:25:59.961263 Connected to device vid:did:rid of 1ae0:0028:00
10242 00:25:59.969072
10243 00:25:59.972037 tpm_get_response: command 0x17b, return code 0x0
10244 00:25:59.972454
10245 00:25:59.975984 ec_init: CrosEC protocol v3 supported (256, 248)
10246 00:25:59.980063
10247 00:25:59.983382 tpm_cleanup: add release locality here.
10248 00:25:59.983892
10249 00:25:59.984281 Shutting down all USB controllers.
10250 00:25:59.986673
10251 00:25:59.987176 Removing current net device
10252 00:25:59.987504
10253 00:25:59.993847 Exiting depthcharge with code 4 at timestamp: 74598706
10254 00:25:59.994365
10255 00:25:59.996817 LZMA decompressing kernel-1 to 0x821a6718
10256 00:25:59.997229
10257 00:25:59.999987 LZMA decompressing kernel-1 to 0x40000000
10258 00:26:01.387174
10259 00:26:01.387720 jumping to kernel
10260 00:26:01.389251 end: 2.2.4 bootloader-commands (duration 00:00:47) [common]
10261 00:26:01.389787 start: 2.2.5 auto-login-action (timeout 00:03:39) [common]
10262 00:26:01.390187 Setting prompt string to ['Linux version [0-9]']
10263 00:26:01.390580 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10264 00:26:01.390957 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10265 00:26:01.468834
10266 00:26:01.472173 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10267 00:26:01.476874 start: 2.2.5.1 login-action (timeout 00:03:38) [common]
10268 00:26:01.477432 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10269 00:26:01.477919 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10270 00:26:01.478330 Using line separator: #'\n'#
10271 00:26:01.478723 No login prompt set.
10272 00:26:01.479085 Parsing kernel messages
10273 00:26:01.479396 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10274 00:26:01.480026 [login-action] Waiting for messages, (timeout 00:03:38)
10275 00:26:01.495751 [ 0.000000] Linux version 6.1.45-cip3 (KernelCI@build-j12530-arm64-gcc-10-defconfig-arm64-chromebook-5rwxg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Aug 14 00:09:07 UTC 2023
10276 00:26:01.498293 [ 0.000000] random: crng init done
10277 00:26:01.504888 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10278 00:26:01.508419 [ 0.000000] efi: UEFI not found.
10279 00:26:01.515335 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10280 00:26:01.521671 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10281 00:26:01.531819 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10282 00:26:01.541543 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10283 00:26:01.549446 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10284 00:26:01.554411 [ 0.000000] printk: bootconsole [mtk8250] enabled
10285 00:26:01.560794 [ 0.000000] NUMA: No NUMA configuration found
10286 00:26:01.567139 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10287 00:26:01.570699 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10288 00:26:01.573960 [ 0.000000] Zone ranges:
10289 00:26:01.580957 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10290 00:26:01.583870 [ 0.000000] DMA32 empty
10291 00:26:01.592094 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10292 00:26:01.593910 [ 0.000000] Movable zone start for each node
10293 00:26:01.597208 [ 0.000000] Early memory node ranges
10294 00:26:01.604000 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10295 00:26:01.610429 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10296 00:26:01.617665 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10297 00:26:01.623871 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10298 00:26:01.630162 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10299 00:26:01.637383 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10300 00:26:01.693539 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10301 00:26:01.699616 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10302 00:26:01.706391 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10303 00:26:01.709451 [ 0.000000] psci: probing for conduit method from DT.
10304 00:26:01.716382 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10305 00:26:01.719442 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10306 00:26:01.725798 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10307 00:26:01.729661 [ 0.000000] psci: SMC Calling Convention v1.2
10308 00:26:01.735799 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10309 00:26:01.740402 [ 0.000000] Detected VIPT I-cache on CPU0
10310 00:26:01.745506 [ 0.000000] CPU features: detected: GIC system register CPU interface
10311 00:26:01.753589 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10312 00:26:01.759034 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10313 00:26:01.765727 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10314 00:26:01.775574 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10315 00:26:01.781774 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10316 00:26:01.785556 [ 0.000000] alternatives: applying boot alternatives
10317 00:26:01.791424 [ 0.000000] Fallback order for Node 0: 0
10318 00:26:01.798881 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10319 00:26:01.801503 [ 0.000000] Policy zone: Normal
10320 00:26:01.824584 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11280948/extract-nfsrootfs-rrkj3bk2,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10321 00:26:01.834689 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10322 00:26:01.845020 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10323 00:26:01.854678 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10324 00:26:01.861012 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10325 00:26:01.864631 <6>[ 0.000000] software IO TLB: area num 8.
10326 00:26:01.921430 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10327 00:26:02.070652 <6>[ 0.000000] Memory: 7952304K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 400464K reserved, 32768K cma-reserved)
10328 00:26:02.076884 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10329 00:26:02.083634 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10330 00:26:02.087398 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10331 00:26:02.094084 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10332 00:26:02.099970 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10333 00:26:02.104693 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10334 00:26:02.113041 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10335 00:26:02.119963 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10336 00:26:02.126533 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10337 00:26:02.133064 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10338 00:26:02.136863 <6>[ 0.000000] GICv3: 608 SPIs implemented
10339 00:26:02.139787 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10340 00:26:02.146481 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10341 00:26:02.149290 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10342 00:26:02.156500 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10343 00:26:02.169377 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10344 00:26:02.182269 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10345 00:26:02.189117 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10346 00:26:02.197144 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10347 00:26:02.210567 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10348 00:26:02.216702 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10349 00:26:02.223686 <6>[ 0.009188] Console: colour dummy device 80x25
10350 00:26:02.233725 <6>[ 0.013916] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10351 00:26:02.240317 <6>[ 0.024359] pid_max: default: 32768 minimum: 301
10352 00:26:02.243498 <6>[ 0.029254] LSM: Security Framework initializing
10353 00:26:02.250011 <6>[ 0.034190] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10354 00:26:02.260320 <6>[ 0.042004] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10355 00:26:02.270258 <6>[ 0.051423] cblist_init_generic: Setting adjustable number of callback queues.
10356 00:26:02.276486 <6>[ 0.058867] cblist_init_generic: Setting shift to 3 and lim to 1.
10357 00:26:02.282831 <6>[ 0.065205] cblist_init_generic: Setting adjustable number of callback queues.
10358 00:26:02.289570 <6>[ 0.072677] cblist_init_generic: Setting shift to 3 and lim to 1.
10359 00:26:02.292660 <6>[ 0.079076] rcu: Hierarchical SRCU implementation.
10360 00:26:02.299385 <6>[ 0.084120] rcu: Max phase no-delay instances is 1000.
10361 00:26:02.306209 <6>[ 0.091185] EFI services will not be available.
10362 00:26:02.309455 <6>[ 0.096132] smp: Bringing up secondary CPUs ...
10363 00:26:02.318261 <6>[ 0.101188] Detected VIPT I-cache on CPU1
10364 00:26:02.324706 <6>[ 0.101258] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10365 00:26:02.331191 <6>[ 0.101289] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10366 00:26:02.335053 <6>[ 0.101622] Detected VIPT I-cache on CPU2
10367 00:26:02.344131 <6>[ 0.101674] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10368 00:26:02.350744 <6>[ 0.101691] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10369 00:26:02.354782 <6>[ 0.101949] Detected VIPT I-cache on CPU3
10370 00:26:02.360649 <6>[ 0.101996] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10371 00:26:02.367662 <6>[ 0.102009] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10372 00:26:02.373783 <6>[ 0.102313] CPU features: detected: Spectre-v4
10373 00:26:02.377217 <6>[ 0.102319] CPU features: detected: Spectre-BHB
10374 00:26:02.380863 <6>[ 0.102324] Detected PIPT I-cache on CPU4
10375 00:26:02.390441 <6>[ 0.102379] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10376 00:26:02.396638 <6>[ 0.102396] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10377 00:26:02.399790 <6>[ 0.102692] Detected PIPT I-cache on CPU5
10378 00:26:02.407035 <6>[ 0.102754] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10379 00:26:02.413698 <6>[ 0.102771] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10380 00:26:02.417099 <6>[ 0.103055] Detected PIPT I-cache on CPU6
10381 00:26:02.426710 <6>[ 0.103121] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10382 00:26:02.433497 <6>[ 0.103138] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10383 00:26:02.436593 <6>[ 0.103433] Detected PIPT I-cache on CPU7
10384 00:26:02.442941 <6>[ 0.103499] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10385 00:26:02.449530 <6>[ 0.103515] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10386 00:26:02.452972 <6>[ 0.103563] smp: Brought up 1 node, 8 CPUs
10387 00:26:02.459799 <6>[ 0.244938] SMP: Total of 8 processors activated.
10388 00:26:02.466581 <6>[ 0.249859] CPU features: detected: 32-bit EL0 Support
10389 00:26:02.472906 <6>[ 0.255256] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10390 00:26:02.479493 <6>[ 0.264111] CPU features: detected: Common not Private translations
10391 00:26:02.486168 <6>[ 0.270627] CPU features: detected: CRC32 instructions
10392 00:26:02.492667 <6>[ 0.276011] CPU features: detected: RCpc load-acquire (LDAPR)
10393 00:26:02.496433 <6>[ 0.282008] CPU features: detected: LSE atomic instructions
10394 00:26:02.503269 <6>[ 0.287825] CPU features: detected: Privileged Access Never
10395 00:26:02.508778 <6>[ 0.293605] CPU features: detected: RAS Extension Support
10396 00:26:02.515635 <6>[ 0.299214] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10397 00:26:02.518788 <6>[ 0.306482] CPU: All CPU(s) started at EL2
10398 00:26:02.525929 <6>[ 0.310799] alternatives: applying system-wide alternatives
10399 00:26:02.536356 <6>[ 0.321497] devtmpfs: initialized
10400 00:26:02.552071 <6>[ 0.330501] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10401 00:26:02.558164 <6>[ 0.340465] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10402 00:26:02.565856 <6>[ 0.348376] pinctrl core: initialized pinctrl subsystem
10403 00:26:02.568212 <6>[ 0.355058] DMI not present or invalid.
10404 00:26:02.574675 <6>[ 0.359479] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10405 00:26:02.584601 <6>[ 0.366356] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10406 00:26:02.590878 <6>[ 0.373940] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10407 00:26:02.601955 <6>[ 0.382169] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10408 00:26:02.604655 <6>[ 0.390414] audit: initializing netlink subsys (disabled)
10409 00:26:02.614105 <5>[ 0.396111] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10410 00:26:02.620526 <6>[ 0.396822] thermal_sys: Registered thermal governor 'step_wise'
10411 00:26:02.627646 <6>[ 0.404081] thermal_sys: Registered thermal governor 'power_allocator'
10412 00:26:02.630732 <6>[ 0.410338] cpuidle: using governor menu
10413 00:26:02.637346 <6>[ 0.421302] NET: Registered PF_QIPCRTR protocol family
10414 00:26:02.644163 <6>[ 0.426798] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10415 00:26:02.650671 <6>[ 0.433905] ASID allocator initialised with 32768 entries
10416 00:26:02.653860 <6>[ 0.440486] Serial: AMBA PL011 UART driver
10417 00:26:02.663454 <4>[ 0.449283] Trying to register duplicate clock ID: 134
10418 00:26:02.719945 <6>[ 0.508670] KASLR enabled
10419 00:26:02.734953 <6>[ 0.516428] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10420 00:26:02.741074 <6>[ 0.523443] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10421 00:26:02.747614 <6>[ 0.529936] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10422 00:26:02.754198 <6>[ 0.536942] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10423 00:26:02.760557 <6>[ 0.543431] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10424 00:26:02.768042 <6>[ 0.550438] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10425 00:26:02.773866 <6>[ 0.556928] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10426 00:26:02.780151 <6>[ 0.563937] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10427 00:26:02.783638 <6>[ 0.571443] ACPI: Interpreter disabled.
10428 00:26:02.792471 <6>[ 0.577867] iommu: Default domain type: Translated
10429 00:26:02.798914 <6>[ 0.582981] iommu: DMA domain TLB invalidation policy: strict mode
10430 00:26:02.801981 <5>[ 0.589638] SCSI subsystem initialized
10431 00:26:02.808572 <6>[ 0.593807] usbcore: registered new interface driver usbfs
10432 00:26:02.815478 <6>[ 0.599540] usbcore: registered new interface driver hub
10433 00:26:02.819142 <6>[ 0.605094] usbcore: registered new device driver usb
10434 00:26:02.825447 <6>[ 0.611194] pps_core: LinuxPPS API ver. 1 registered
10435 00:26:02.835617 <6>[ 0.616391] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10436 00:26:02.838569 <6>[ 0.625743] PTP clock support registered
10437 00:26:02.841873 <6>[ 0.629986] EDAC MC: Ver: 3.0.0
10438 00:26:02.849693 <6>[ 0.635144] FPGA manager framework
10439 00:26:02.856462 <6>[ 0.638826] Advanced Linux Sound Architecture Driver Initialized.
10440 00:26:02.859005 <6>[ 0.645601] vgaarb: loaded
10441 00:26:02.865858 <6>[ 0.648788] clocksource: Switched to clocksource arch_sys_counter
10442 00:26:02.869348 <5>[ 0.655229] VFS: Disk quotas dquot_6.6.0
10443 00:26:02.875880 <6>[ 0.659417] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10444 00:26:02.879688 <6>[ 0.666610] pnp: PnP ACPI: disabled
10445 00:26:02.888301 <6>[ 0.673325] NET: Registered PF_INET protocol family
10446 00:26:02.897489 <6>[ 0.678927] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10447 00:26:02.909118 <6>[ 0.691268] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10448 00:26:02.920047 <6>[ 0.700089] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10449 00:26:02.925492 <6>[ 0.708061] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10450 00:26:02.935360 <6>[ 0.716764] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10451 00:26:02.941994 <6>[ 0.726514] TCP: Hash tables configured (established 65536 bind 65536)
10452 00:26:02.948617 <6>[ 0.733378] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10453 00:26:02.958568 <6>[ 0.740579] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10454 00:26:02.965039 <6>[ 0.748284] NET: Registered PF_UNIX/PF_LOCAL protocol family
10455 00:26:02.972406 <6>[ 0.754442] RPC: Registered named UNIX socket transport module.
10456 00:26:02.974987 <6>[ 0.760597] RPC: Registered udp transport module.
10457 00:26:02.981164 <6>[ 0.765533] RPC: Registered tcp transport module.
10458 00:26:02.988386 <6>[ 0.770466] RPC: Registered tcp NFSv4.1 backchannel transport module.
10459 00:26:02.991481 <6>[ 0.777135] PCI: CLS 0 bytes, default 64
10460 00:26:02.995127 <6>[ 0.781499] Unpacking initramfs...
10461 00:26:03.004131 <6>[ 0.785579] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10462 00:26:03.011200 <6>[ 0.794219] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10463 00:26:03.017739 <6>[ 0.803065] kvm [1]: IPA Size Limit: 40 bits
10464 00:26:03.022237 <6>[ 0.807596] kvm [1]: GICv3: no GICV resource entry
10465 00:26:03.027576 <6>[ 0.812621] kvm [1]: disabling GICv2 emulation
10466 00:26:03.034540 <6>[ 0.817308] kvm [1]: GIC system register CPU interface enabled
10467 00:26:03.038338 <6>[ 0.823484] kvm [1]: vgic interrupt IRQ18
10468 00:26:03.044161 <6>[ 0.828856] kvm [1]: VHE mode initialized successfully
10469 00:26:03.050528 <5>[ 0.835284] Initialise system trusted keyrings
10470 00:26:03.058237 <6>[ 0.840147] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10471 00:26:03.064940 <6>[ 0.850175] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10472 00:26:03.071449 <5>[ 0.856571] NFS: Registering the id_resolver key type
10473 00:26:03.074609 <5>[ 0.861874] Key type id_resolver registered
10474 00:26:03.080871 <5>[ 0.866290] Key type id_legacy registered
10475 00:26:03.088305 <6>[ 0.870569] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10476 00:26:03.094606 <6>[ 0.877491] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10477 00:26:03.101078 <6>[ 0.885204] 9p: Installing v9fs 9p2000 file system support
10478 00:26:03.137347 <5>[ 0.922706] Key type asymmetric registered
10479 00:26:03.140689 <5>[ 0.927039] Asymmetric key parser 'x509' registered
10480 00:26:03.150205 <6>[ 0.932173] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10481 00:26:03.153817 <6>[ 0.939792] io scheduler mq-deadline registered
10482 00:26:03.157447 <6>[ 0.944556] io scheduler kyber registered
10483 00:26:03.176344 <6>[ 0.961521] EINJ: ACPI disabled.
10484 00:26:03.208726 <4>[ 0.987542] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10485 00:26:03.218969 <4>[ 0.998165] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10486 00:26:03.234184 <6>[ 1.019131] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10487 00:26:03.241785 <6>[ 1.027175] printk: console [ttyS0] disabled
10488 00:26:03.269624 <6>[ 1.051849] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10489 00:26:03.276383 <6>[ 1.061363] printk: console [ttyS0] enabled
10490 00:26:03.279482 <6>[ 1.061363] printk: console [ttyS0] enabled
10491 00:26:03.286303 <6>[ 1.070258] printk: bootconsole [mtk8250] disabled
10492 00:26:03.288943 <6>[ 1.070258] printk: bootconsole [mtk8250] disabled
10493 00:26:03.295792 <6>[ 1.081673] SuperH (H)SCI(F) driver initialized
10494 00:26:03.299459 <6>[ 1.086960] msm_serial: driver initialized
10495 00:26:03.313791 <6>[ 1.095992] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10496 00:26:03.324363 <6>[ 1.104542] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10497 00:26:03.330920 <6>[ 1.113084] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10498 00:26:03.340512 <6>[ 1.121714] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10499 00:26:03.347003 <6>[ 1.130426] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10500 00:26:03.357470 <6>[ 1.139139] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10501 00:26:03.367218 <6>[ 1.147687] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10502 00:26:03.373616 <6>[ 1.156503] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10503 00:26:03.383528 <6>[ 1.165048] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10504 00:26:03.395355 <6>[ 1.180797] loop: module loaded
10505 00:26:03.402852 <6>[ 1.186708] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10506 00:26:03.424856 <4>[ 1.210167] mtk-pmic-keys: Failed to locate of_node [id: -1]
10507 00:26:03.431347 <6>[ 1.217042] megasas: 07.719.03.00-rc1
10508 00:26:03.440815 <6>[ 1.226613] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10509 00:26:03.450754 <6>[ 1.236179] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10510 00:26:03.467236 <6>[ 1.252752] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10511 00:26:03.524004 <6>[ 1.302286] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10512 00:26:03.736352 <6>[ 1.521825] Freeing initrd memory: 17248K
10513 00:26:03.746443 <6>[ 1.532223] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10514 00:26:03.757387 <6>[ 1.543442] tun: Universal TUN/TAP device driver, 1.6
10515 00:26:03.761041 <6>[ 1.549555] thunder_xcv, ver 1.0
10516 00:26:03.764419 <6>[ 1.553059] thunder_bgx, ver 1.0
10517 00:26:03.767896 <6>[ 1.556549] nicpf, ver 1.0
10518 00:26:03.778473 <6>[ 1.560582] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10519 00:26:03.781941 <6>[ 1.568060] hns3: Copyright (c) 2017 Huawei Corporation.
10520 00:26:03.784809 <6>[ 1.573646] hclge is initializing
10521 00:26:03.791703 <6>[ 1.577226] e1000: Intel(R) PRO/1000 Network Driver
10522 00:26:03.799229 <6>[ 1.582355] e1000: Copyright (c) 1999-2006 Intel Corporation.
10523 00:26:03.801540 <6>[ 1.588367] e1000e: Intel(R) PRO/1000 Network Driver
10524 00:26:03.808646 <6>[ 1.593582] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10525 00:26:03.815209 <6>[ 1.599770] igb: Intel(R) Gigabit Ethernet Network Driver
10526 00:26:03.821260 <6>[ 1.605420] igb: Copyright (c) 2007-2014 Intel Corporation.
10527 00:26:03.828056 <6>[ 1.611257] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10528 00:26:03.835202 <6>[ 1.617774] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10529 00:26:03.838227 <6>[ 1.624240] sky2: driver version 1.30
10530 00:26:03.844498 <6>[ 1.629262] VFIO - User Level meta-driver version: 0.3
10531 00:26:03.852038 <6>[ 1.637574] usbcore: registered new interface driver usb-storage
10532 00:26:03.858595 <6>[ 1.644016] usbcore: registered new device driver onboard-usb-hub
10533 00:26:03.867533 <6>[ 1.653142] mt6397-rtc mt6359-rtc: registered as rtc0
10534 00:26:03.878433 <6>[ 1.658609] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-14T00:26:05 UTC (1691972765)
10535 00:26:03.880481 <6>[ 1.668189] i2c_dev: i2c /dev entries driver
10536 00:26:03.897924 <6>[ 1.679948] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10537 00:26:03.918594 <6>[ 1.703951] cpu cpu0: EM: created perf domain
10538 00:26:03.921924 <6>[ 1.708977] cpu cpu4: EM: created perf domain
10539 00:26:03.928900 <6>[ 1.714608] sdhci: Secure Digital Host Controller Interface driver
10540 00:26:03.936599 <6>[ 1.721042] sdhci: Copyright(c) Pierre Ossman
10541 00:26:03.942916 <6>[ 1.725988] Synopsys Designware Multimedia Card Interface Driver
10542 00:26:03.949344 <6>[ 1.732628] sdhci-pltfm: SDHCI platform and OF driver helper
10543 00:26:03.952452 <6>[ 1.732734] mmc0: CQHCI version 5.10
10544 00:26:03.959096 <6>[ 1.742992] ledtrig-cpu: registered to indicate activity on CPUs
10545 00:26:03.965268 <6>[ 1.750135] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10546 00:26:03.972691 <6>[ 1.757214] usbcore: registered new interface driver usbhid
10547 00:26:03.975519 <6>[ 1.763036] usbhid: USB HID core driver
10548 00:26:03.982351 <6>[ 1.767227] spi_master spi0: will run message pump with realtime priority
10549 00:26:04.026697 <6>[ 1.805320] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10550 00:26:04.044938 <6>[ 1.820367] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10551 00:26:04.051524 <6>[ 1.835251] cros-ec-spi spi0.0: Chrome EC device registered
10552 00:26:04.055255 <6>[ 1.841282] mmc0: Command Queue Engine enabled
10553 00:26:04.062370 <6>[ 1.846044] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10554 00:26:04.068781 <6>[ 1.853680] mmcblk0: mmc0:0001 DA4128 116 GiB
10555 00:26:04.079022 <6>[ 1.864702] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10556 00:26:04.086335 <6>[ 1.871872] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10557 00:26:04.096621 <6>[ 1.876677] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10558 00:26:04.099974 <6>[ 1.877806] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10559 00:26:04.106225 <6>[ 1.887672] NET: Registered PF_PACKET protocol family
10560 00:26:04.112596 <6>[ 1.892341] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10561 00:26:04.116244 <6>[ 1.897009] 9pnet: Installing 9P2000 support
10562 00:26:04.123634 <5>[ 1.908037] Key type dns_resolver registered
10563 00:26:04.127059 <6>[ 1.913001] registered taskstats version 1
10564 00:26:04.132874 <5>[ 1.917385] Loading compiled-in X.509 certificates
10565 00:26:04.163674 <4>[ 1.942486] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10566 00:26:04.173874 <4>[ 1.953256] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10567 00:26:04.180454 <3>[ 1.963810] debugfs: File 'uA_load' in directory '/' already present!
10568 00:26:04.186399 <3>[ 1.970582] debugfs: File 'min_uV' in directory '/' already present!
10569 00:26:04.193740 <3>[ 1.977209] debugfs: File 'max_uV' in directory '/' already present!
10570 00:26:04.200024 <3>[ 1.983838] debugfs: File 'constraint_flags' in directory '/' already present!
10571 00:26:04.211358 <3>[ 1.993753] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10572 00:26:04.221437 <6>[ 2.006391] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10573 00:26:04.227540 <6>[ 2.013178] xhci-mtk 11200000.usb: xHCI Host Controller
10574 00:26:04.233950 <6>[ 2.018665] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10575 00:26:04.244500 <6>[ 2.026494] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10576 00:26:04.250888 <6>[ 2.035911] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10577 00:26:04.257080 <6>[ 2.041952] xhci-mtk 11200000.usb: xHCI Host Controller
10578 00:26:04.264847 <6>[ 2.047426] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10579 00:26:04.271801 <6>[ 2.055072] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10580 00:26:04.277642 <6>[ 2.062698] hub 1-0:1.0: USB hub found
10581 00:26:04.280836 <6>[ 2.066709] hub 1-0:1.0: 1 port detected
10582 00:26:04.287037 <6>[ 2.070962] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10583 00:26:04.294291 <6>[ 2.079501] hub 2-0:1.0: USB hub found
10584 00:26:04.296788 <6>[ 2.083505] hub 2-0:1.0: 1 port detected
10585 00:26:04.305336 <6>[ 2.091289] mtk-msdc 11f70000.mmc: Got CD GPIO
10586 00:26:04.315586 <6>[ 2.096633] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10587 00:26:04.322103 <6>[ 2.104933] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10588 00:26:04.331898 <4>[ 2.113034] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10589 00:26:04.338589 <6>[ 2.122672] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10590 00:26:04.348684 <6>[ 2.130752] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10591 00:26:04.355949 <6>[ 2.138833] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10592 00:26:04.365128 <6>[ 2.146762] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10593 00:26:04.372069 <6>[ 2.154580] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10594 00:26:04.382540 <6>[ 2.162398] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10595 00:26:04.391958 <6>[ 2.173163] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10596 00:26:04.398314 <6>[ 2.181531] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10597 00:26:04.409148 <6>[ 2.189870] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10598 00:26:04.415351 <6>[ 2.198209] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10599 00:26:04.425022 <6>[ 2.206546] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10600 00:26:04.431554 <6>[ 2.214885] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10601 00:26:04.442507 <6>[ 2.223224] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10602 00:26:04.448598 <6>[ 2.231562] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10603 00:26:04.458367 <6>[ 2.239900] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10604 00:26:04.464415 <6>[ 2.248238] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10605 00:26:04.475199 <6>[ 2.256587] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10606 00:26:04.481411 <6>[ 2.264925] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10607 00:26:04.491670 <6>[ 2.273263] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10608 00:26:04.497878 <6>[ 2.281602] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10609 00:26:04.507766 <6>[ 2.289940] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10610 00:26:04.514383 <6>[ 2.298824] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10611 00:26:04.521229 <6>[ 2.306015] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10612 00:26:04.527714 <6>[ 2.312793] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10613 00:26:04.534572 <6>[ 2.319550] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10614 00:26:04.540809 <6>[ 2.326487] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10615 00:26:04.551549 <6>[ 2.333355] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10616 00:26:04.560562 <6>[ 2.342487] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10617 00:26:04.570674 <6>[ 2.351609] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10618 00:26:04.580896 <6>[ 2.360929] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10619 00:26:04.590408 <6>[ 2.370398] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10620 00:26:04.597517 <6>[ 2.379867] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10621 00:26:04.607313 <6>[ 2.388987] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10622 00:26:04.616841 <6>[ 2.398453] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10623 00:26:04.626856 <6>[ 2.407571] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10624 00:26:04.637230 <6>[ 2.416867] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10625 00:26:04.646713 <6>[ 2.427027] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10626 00:26:04.656251 <6>[ 2.438539] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10627 00:26:04.662937 <6>[ 2.448152] Trying to probe devices needed for running init ...
10628 00:26:04.686605 <6>[ 2.469249] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10629 00:26:04.713780 <6>[ 2.499792] hub 2-1:1.0: USB hub found
10630 00:26:04.717466 <6>[ 2.504244] hub 2-1:1.0: 3 ports detected
10631 00:26:04.839466 <6>[ 2.621055] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10632 00:26:04.993178 <6>[ 2.779223] hub 1-1:1.0: USB hub found
10633 00:26:04.996993 <6>[ 2.783735] hub 1-1:1.0: 4 ports detected
10634 00:26:05.071177 <6>[ 2.853391] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10635 00:26:05.318554 <6>[ 3.101108] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10636 00:26:05.451394 <6>[ 3.237140] hub 1-1.4:1.0: USB hub found
10637 00:26:05.454844 <6>[ 3.241815] hub 1-1.4:1.0: 2 ports detected
10638 00:26:05.754763 <6>[ 3.537095] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10639 00:26:05.946555 <6>[ 3.729093] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10640 00:26:16.943242 <6>[ 14.734058] ALSA device list:
10641 00:26:16.949559 <6>[ 14.737352] No soundcards found.
10642 00:26:16.958678 <6>[ 14.745293] Freeing unused kernel memory: 8384K
10643 00:26:16.960672 <6>[ 14.750297] Run /init as init process
10644 00:26:16.972991 Loading, please wait...
10645 00:26:16.993972 Starting version 247.3-7+deb11u2
10646 00:26:17.190353 <6>[ 14.974692] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10647 00:26:17.203762 <3>[ 14.987792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10648 00:26:17.213148 <3>[ 14.996458] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10649 00:26:17.219837 <3>[ 15.004827] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10650 00:26:17.231676 <6>[ 15.019468] remoteproc remoteproc0: scp is available
10651 00:26:17.238141 <3>[ 15.020860] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10652 00:26:17.245434 <6>[ 15.024840] remoteproc remoteproc0: powering up scp
10653 00:26:17.251717 <3>[ 15.032813] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10654 00:26:17.262354 <6>[ 15.037950] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10655 00:26:17.267961 <6>[ 15.037984] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10656 00:26:17.274885 <6>[ 15.038743] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10657 00:26:17.284607 <6>[ 15.038764] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10658 00:26:17.290846 <6>[ 15.038769] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10659 00:26:17.300888 <3>[ 15.046039] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10660 00:26:17.303914 <6>[ 15.076984] mc: Linux media interface: v0.10
10661 00:26:17.314225 <3>[ 15.085060] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10662 00:26:17.320970 <3>[ 15.085066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10663 00:26:17.330313 <4>[ 15.089916] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10664 00:26:17.337220 <3>[ 15.095114] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10665 00:26:17.343650 <6>[ 15.117251] videodev: Linux video capture interface: v2.00
10666 00:26:17.350850 <4>[ 15.117508] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10667 00:26:17.357239 <6>[ 15.117687] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10668 00:26:17.366695 <3>[ 15.123260] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10669 00:26:17.373315 <6>[ 15.131664] usbcore: registered new interface driver r8152
10670 00:26:17.379896 <3>[ 15.135739] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10671 00:26:17.386955 <3>[ 15.135760] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10672 00:26:17.396564 <6>[ 15.166278] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10673 00:26:17.403742 <3>[ 15.173267] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10674 00:26:17.409452 <6>[ 15.179710] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10675 00:26:17.416646 <6>[ 15.180844] pci_bus 0000:00: root bus resource [bus 00-ff]
10676 00:26:17.424623 <6>[ 15.187707] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10677 00:26:17.432747 <3>[ 15.187916] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10678 00:26:17.440399 <3>[ 15.187927] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10679 00:26:17.449727 <3>[ 15.187939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10680 00:26:17.456213 <3>[ 15.187949] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10681 00:26:17.466078 <3>[ 15.188001] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10682 00:26:17.472565 <6>[ 15.188970] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10683 00:26:17.482373 <6>[ 15.190856] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10684 00:26:17.489183 <6>[ 15.195754] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10685 00:26:17.495668 <6>[ 15.202797] remoteproc remoteproc0: remote processor scp is now up
10686 00:26:17.505491 <6>[ 15.211648] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10687 00:26:17.511854 <4>[ 15.214215] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10688 00:26:17.518841 <4>[ 15.214215] Fallback method does not support PEC.
10689 00:26:17.528697 <6>[ 15.217052] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10690 00:26:17.535553 <6>[ 15.217094] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10691 00:26:17.541816 <6>[ 15.220997] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10692 00:26:17.552440 <6>[ 15.225538] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10693 00:26:17.558978 <6>[ 15.233309] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10694 00:26:17.568162 <6>[ 15.239935] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10695 00:26:17.575400 <3>[ 15.240096] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10696 00:26:17.581644 <6>[ 15.274786] usbcore: registered new interface driver cdc_ether
10697 00:26:17.584643 <6>[ 15.274881] Bluetooth: Core ver 2.22
10698 00:26:17.591596 <6>[ 15.274969] NET: Registered PF_BLUETOOTH protocol family
10699 00:26:17.598086 <6>[ 15.274978] Bluetooth: HCI device and connection manager initialized
10700 00:26:17.604735 <6>[ 15.275012] Bluetooth: HCI socket layer initialized
10701 00:26:17.607687 <6>[ 15.275023] Bluetooth: L2CAP socket layer initialized
10702 00:26:17.614444 <6>[ 15.275055] Bluetooth: SCO socket layer initialized
10703 00:26:17.618067 <6>[ 15.281372] pci 0000:00:00.0: supports D1 D2
10704 00:26:17.624472 <6>[ 15.298803] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10705 00:26:17.631561 <6>[ 15.311431] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10706 00:26:17.637635 <6>[ 15.311846] usbcore: registered new interface driver r8153_ecm
10707 00:26:17.647792 <4>[ 15.315294] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10708 00:26:17.654290 <4>[ 15.315299] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10709 00:26:17.667715 <6>[ 15.322858] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10710 00:26:17.677486 <6>[ 15.329106] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10711 00:26:17.680787 <6>[ 15.334914] usbcore: registered new interface driver uvcvideo
10712 00:26:17.689053 <6>[ 15.335402] usbcore: registered new interface driver btusb
10713 00:26:17.694644 <6>[ 15.335523] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10714 00:26:17.704417 <4>[ 15.336179] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10715 00:26:17.710815 <3>[ 15.336186] Bluetooth: hci0: Failed to load firmware file (-2)
10716 00:26:17.718376 <3>[ 15.336188] Bluetooth: hci0: Failed to set up firmware (-2)
10717 00:26:17.728096 <4>[ 15.336192] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10718 00:26:17.734631 <6>[ 15.343887] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10719 00:26:17.738712 <6>[ 15.373079] r8152 2-1.3:1.0 eth0: v1.12.13
10720 00:26:17.744166 <6>[ 15.375430] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10721 00:26:17.750781 <6>[ 15.389413] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10722 00:26:17.761042 <6>[ 15.391462] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10723 00:26:17.767176 <3>[ 15.538598] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10724 00:26:17.773690 <6>[ 15.544640] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10725 00:26:17.780789 <6>[ 15.568380] pci 0000:01:00.0: supports D1 D2
10726 00:26:17.787000 <6>[ 15.572899] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10727 00:26:17.804626 <6>[ 15.589092] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10728 00:26:17.810972 <6>[ 15.595997] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10729 00:26:17.818046 <6>[ 15.604076] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10730 00:26:17.827765 <6>[ 15.612072] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10731 00:26:17.834517 <6>[ 15.620077] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10732 00:26:17.844497 <6>[ 15.628077] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10733 00:26:17.847421 <6>[ 15.636078] pci 0000:00:00.0: PCI bridge to [bus 01]
10734 00:26:17.857245 <6>[ 15.641296] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10735 00:26:17.864232 <6>[ 15.649430] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10736 00:26:17.870649 <6>[ 15.656270] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10737 00:26:17.877095 <6>[ 15.662859] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10738 00:26:17.898278 <5>[ 15.682831] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10739 00:26:17.917737 <5>[ 15.701890] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10740 00:26:17.923649 <4>[ 15.708896] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10741 00:26:17.930941 <6>[ 15.717808] cfg80211: failed to load regulatory.db
10742 00:26:17.982166 <6>[ 15.766009] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10743 00:26:17.988554 <6>[ 15.773676] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10744 00:26:18.012880 <6>[ 15.800393] mt7921e 0000:01:00.0: ASIC revision: 79610010
10745 00:26:18.119537 <4>[ 15.900968] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10746 00:26:18.127945 Begin: Loading essential drivers ... done.
10747 00:26:18.131051 Begin: Running /scripts/init-premount ... done.
10748 00:26:18.138236 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10749 00:26:18.148571 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10750 00:26:18.151235 Device /sys/class/net/enx002432307c7b found
10751 00:26:18.151317 done.
10752 00:26:18.212578 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10753 00:26:18.239244 <4>[ 16.020571] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10754 00:26:18.359166 <4>[ 16.140656] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10755 00:26:18.479219 <4>[ 16.260435] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10756 00:26:18.599190 <4>[ 16.380423] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10757 00:26:18.719192 <4>[ 16.500336] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10758 00:26:18.838812 <4>[ 16.620429] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10759 00:26:18.958595 <4>[ 16.740256] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10760 00:26:19.078778 <4>[ 16.860252] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10761 00:26:19.199325 <4>[ 16.980202] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10762 00:26:19.269359 <6>[ 17.057530] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10763 00:26:19.309946 <3>[ 17.098245] mt7921e 0000:01:00.0: hardware init failed
10764 00:26:19.370564 IP-Config: no response after 2 secs - giving up
10765 00:26:19.408250 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10766 00:26:19.411603 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10767 00:26:19.418104 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10768 00:26:19.427953 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10769 00:26:19.434785 host : mt8192-asurada-spherion-r0-cbg-2
10770 00:26:19.441023 domain : lava-rack
10771 00:26:19.445202 rootserver: 192.168.201.1 rootpath:
10772 00:26:19.445283 filename :
10773 00:26:19.491786 done.
10774 00:26:19.499880 Begin: Running /scripts/nfs-bottom ... done.
10775 00:26:19.520834 Begin: Running /scripts/init-bottom ... done.
10776 00:26:20.728702 <6>[ 18.516534] NET: Registered PF_INET6 protocol family
10777 00:26:20.735106 <6>[ 18.523491] Segment Routing with IPv6
10778 00:26:20.738438 <6>[ 18.527479] In-situ OAM (IOAM) with IPv6
10779 00:26:20.865191 <30>[ 18.633758] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10780 00:26:20.868467 <30>[ 18.658156] systemd[1]: Detected architecture arm64.
10781 00:26:20.891421
10782 00:26:20.893602 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10783 00:26:20.893694
10784 00:26:20.911127 <30>[ 18.699580] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10785 00:26:21.827090 <30>[ 19.611921] systemd[1]: Queued start job for default target Graphical Interface.
10786 00:26:21.864114 <30>[ 19.651536] systemd[1]: Created slice system-getty.slice.
10787 00:26:21.870090 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10788 00:26:21.886641 <30>[ 19.674585] systemd[1]: Created slice system-modprobe.slice.
10789 00:26:21.892617 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10790 00:26:21.911268 <30>[ 19.699133] systemd[1]: Created slice system-serial\x2dgetty.slice.
10791 00:26:21.921643 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10792 00:26:21.934382 <30>[ 19.722187] systemd[1]: Created slice User and Session Slice.
10793 00:26:21.940894 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10794 00:26:21.961222 <30>[ 19.745812] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10795 00:26:21.970870 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10796 00:26:21.989677 <30>[ 19.773836] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10797 00:26:21.995939 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10798 00:26:22.020231 <30>[ 19.801222] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10799 00:26:22.026469 <30>[ 19.813360] systemd[1]: Reached target Local Encrypted Volumes.
10800 00:26:22.033339 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10801 00:26:22.049892 <30>[ 19.837619] systemd[1]: Reached target Paths.
10802 00:26:22.057639 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10803 00:26:22.069181 <30>[ 19.857065] systemd[1]: Reached target Remote File Systems.
10804 00:26:22.077045 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10805 00:26:22.093448 <30>[ 19.881446] systemd[1]: Reached target Slices.
10806 00:26:22.100752 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10807 00:26:22.113278 <30>[ 19.901098] systemd[1]: Reached target Swap.
10808 00:26:22.116361 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10809 00:26:22.136773 <30>[ 19.921612] systemd[1]: Listening on initctl Compatibility Named Pipe.
10810 00:26:22.142964 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10811 00:26:22.150018 <30>[ 19.937884] systemd[1]: Listening on Journal Audit Socket.
10812 00:26:22.156538 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10813 00:26:22.174027 <30>[ 19.962586] systemd[1]: Listening on Journal Socket (/dev/log).
10814 00:26:22.180657 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10815 00:26:22.197782 <30>[ 19.985648] systemd[1]: Listening on Journal Socket.
10816 00:26:22.203541 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10817 00:26:22.222049 <30>[ 20.006584] systemd[1]: Listening on Network Service Netlink Socket.
10818 00:26:22.228604 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10819 00:26:22.243994 <30>[ 20.032165] systemd[1]: Listening on udev Control Socket.
10820 00:26:22.251431 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10821 00:26:22.265515 <30>[ 20.053595] systemd[1]: Listening on udev Kernel Socket.
10822 00:26:22.272056 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10823 00:26:22.318163 <30>[ 20.105287] systemd[1]: Mounting Huge Pages File System...
10824 00:26:22.323746 Mounting [0;1;39mHuge Pages File System[0m...
10825 00:26:22.341301 <30>[ 20.129383] systemd[1]: Mounting POSIX Message Queue File System...
10826 00:26:22.348060 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10827 00:26:22.369605 <30>[ 20.157649] systemd[1]: Mounting Kernel Debug File System...
10828 00:26:22.376049 Mounting [0;1;39mKernel Debug File System[0m...
10829 00:26:22.392815 <30>[ 20.177675] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10830 00:26:22.404904 <30>[ 20.189866] systemd[1]: Starting Create list of static device nodes for the current kernel...
10831 00:26:22.411371 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10832 00:26:22.433620 <30>[ 20.221087] systemd[1]: Starting Load Kernel Module configfs...
10833 00:26:22.439673 Starting [0;1;39mLoad Kernel Module configfs[0m...
10834 00:26:22.485531 <30>[ 20.273811] systemd[1]: Starting Load Kernel Module drm...
10835 00:26:22.492834 Starting [0;1;39mLoad Kernel Module drm[0m...
10836 00:26:22.510137 <30>[ 20.298126] systemd[1]: Starting Load Kernel Module fuse...
10837 00:26:22.516448 Starting [0;1;39mLoad Kernel Module fuse[0m...
10838 00:26:22.553558 <30>[ 20.338748] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10839 00:26:22.560706 <6>[ 20.348980] fuse: init (API version 7.37)
10840 00:26:22.609724 <30>[ 20.397901] systemd[1]: Starting Journal Service...
10841 00:26:22.616364 Starting [0;1;39mJournal Service[0m...
10842 00:26:22.640624 <30>[ 20.429040] systemd[1]: Starting Load Kernel Modules...
10843 00:26:22.647032 Starting [0;1;39mLoad Kernel Modules[0m...
10844 00:26:22.666767 <30>[ 20.451975] systemd[1]: Starting Remount Root and Kernel File Systems...
10845 00:26:22.673146 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10846 00:26:22.692307 <30>[ 20.480392] systemd[1]: Starting Coldplug All udev Devices...
10847 00:26:22.698730 Starting [0;1;39mColdplug All udev Devices[0m...
10848 00:26:22.716623 <30>[ 20.505044] systemd[1]: Mounted Huge Pages File System.
10849 00:26:22.723420 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10850 00:26:22.737240 <30>[ 20.525602] systemd[1]: Mounted POSIX Message Queue File System.
10851 00:26:22.743733 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10852 00:26:22.758238 <3>[ 20.543244] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10853 00:26:22.764956 <30>[ 20.552548] systemd[1]: Mounted Kernel Debug File System.
10854 00:26:22.771554 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10855 00:26:22.789724 <30>[ 20.574294] systemd[1]: Finished Create list of static device nodes for the current kernel.
10856 00:26:22.800141 [[0;32m OK [<3>[ 20.583926] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10857 00:26:22.805952 0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10858 00:26:22.827005 <30>[ 20.615156] systemd[1]: modprobe@configfs.service: Succeeded.
10859 00:26:22.834532 <30>[ 20.622554] systemd[1]: Finished Load Kernel Module configfs.
10860 00:26:22.840714 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10861 00:26:22.852607 <3>[ 20.637145] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10862 00:26:22.862232 <30>[ 20.650236] systemd[1]: modprobe@drm.service: Succeeded.
10863 00:26:22.868969 <30>[ 20.657206] systemd[1]: Finished Load Kernel Module drm.
10864 00:26:22.875295 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10865 00:26:22.892413 <3>[ 20.677223] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10866 00:26:22.899643 <30>[ 20.687506] systemd[1]: modprobe@fuse.service: Succeeded.
10867 00:26:22.906940 <30>[ 20.694553] systemd[1]: Finished Load Kernel Module fuse.
10868 00:26:22.913410 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10869 00:26:22.923248 <3>[ 20.706822] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10870 00:26:22.930439 <30>[ 20.718112] systemd[1]: Finished Load Kernel Modules.
10871 00:26:22.936951 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10872 00:26:22.952170 <3>[ 20.736769] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10873 00:26:22.962659 <30>[ 20.747747] systemd[1]: Finished Remount Root and Kernel File Systems.
10874 00:26:22.970432 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10875 00:26:22.985385 <3>[ 20.770149] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10876 00:26:23.014255 <3>[ 20.799527] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10877 00:26:23.033782 <30>[ 20.821957] systemd[1]: Mounting FUSE Control File System...
10878 00:26:23.040691 Mounting [0;1;39mFUSE Control File System[0m...
10879 00:26:23.050758 <3>[ 20.834650] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10880 00:26:23.061484 <30>[ 20.846729] systemd[1]: Mounting Kernel Configuration File System...
10881 00:26:23.064630 Mounting [0;1;39mKernel Configuration File System[0m...
10882 00:26:23.080127 <3>[ 20.865009] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 00:26:23.096452 <30>[ 20.881167] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10884 00:26:23.106421 <30>[ 20.890266] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10885 00:26:23.137836 <30>[ 20.925844] systemd[1]: Starting Load/Save Random Seed...
10886 00:26:23.144301 Starting [0;1;39mLoad/Save Random Seed[0m...
10887 00:26:23.159488 <30>[ 20.948040] systemd[1]: Starting Apply Kernel Variables...
10888 00:26:23.166075 Starting [0;1;39mApply Kernel Variables[0m...
10889 00:26:23.185659 <30>[ 20.974103] systemd[1]: Starting Create System Users...
10890 00:26:23.193223 Starting [0;1;39mCreate System Users[0m...
10891 00:26:23.209554 <4>[ 20.985666] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10892 00:26:23.215982 <3>[ 21.001482] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10893 00:26:23.219455 <30>[ 21.003253] systemd[1]: Started Journal Service.
10894 00:26:23.225776 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10895 00:26:23.248606 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10896 00:26:23.260691 See 'systemctl status systemd-udev-trigger.service' for details.
10897 00:26:23.277522 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10898 00:26:23.293762 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10899 00:26:23.310057 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10900 00:26:23.326010 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10901 00:26:23.341548 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10902 00:26:23.378966 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10903 00:26:23.395699 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10904 00:26:23.444450 <46>[ 21.227937] systemd-journald[301]: Received client request to flush runtime journal.
10905 00:26:24.532596 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10906 00:26:24.545418 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10907 00:26:24.560489 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10908 00:26:24.628910 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10909 00:26:24.840623 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10910 00:26:24.881955 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10911 00:26:24.999118 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10912 00:26:25.046501 Starting [0;1;39mNetwork Service[0m...
10913 00:26:25.356564 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10914 00:26:25.380124 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10915 00:26:25.425091 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10916 00:26:25.770509 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10917 00:26:25.788564 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10918 00:26:25.805504 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10919 00:26:25.821523 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10920 00:26:25.842249 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10921 00:26:25.922375 Starting [0;1;39mNetwork Name Resolution[0m...
10922 00:26:25.940025 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10923 00:26:25.967073 Starting [0;1;39mNetwork Time Synchronization[0m...
10924 00:26:25.991892 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10925 00:26:26.014014 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10926 00:26:26.050588 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10927 00:26:26.206909 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10928 00:26:26.229828 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10929 00:26:26.248480 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10930 00:26:26.264865 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10931 00:26:26.284850 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10932 00:26:26.426077 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10933 00:26:26.457370 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10934 00:26:26.483574 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10935 00:26:26.594140 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10936 00:26:26.609078 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10937 00:26:26.950403 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10938 00:26:26.964445 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10939 00:26:26.980814 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10940 00:26:27.028739 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10941 00:26:27.250471 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10942 00:26:27.622510 Starting [0;1;39mUser Login Management[0m...
10943 00:26:27.643226 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10944 00:26:27.670995 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10945 00:26:27.692309 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10946 00:26:27.733923 Starting [0;1;39mPermit User Sessions[0m...
10947 00:26:27.855523 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10948 00:26:27.880572 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10949 00:26:27.928791 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10950 00:26:27.965083 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10951 00:26:27.980246 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10952 00:26:27.998036 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10953 00:26:28.018303 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10954 00:26:28.041192 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10955 00:26:28.085598 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10956 00:26:28.142037 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10957 00:26:28.254815
10958 00:26:28.254952
10959 00:26:28.257999 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10960 00:26:28.258081
10961 00:26:28.261415 debian-bullseye-arm64 login: root (automatic login)
10962 00:26:28.261529
10963 00:26:28.261608
10964 00:26:28.592159 Linux debian-bullseye-arm64 6.1.45-cip3 #1 SMP PREEMPT Mon Aug 14 00:09:07 UTC 2023 aarch64
10965 00:26:28.592299
10966 00:26:28.598265 The programs included with the Debian GNU/Linux system are free software;
10967 00:26:28.605418 the exact distribution terms for each program are described in the
10968 00:26:28.608641 individual files in /usr/share/doc/*/copyright.
10969 00:26:28.608725
10970 00:26:28.614896 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10971 00:26:28.617997 permitted by applicable law.
10972 00:26:28.699572 Matched prompt #10: / #
10974 00:26:28.699868 Setting prompt string to ['/ #']
10975 00:26:28.700003 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10977 00:26:28.700223 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10978 00:26:28.700361 start: 2.2.6 expect-shell-connection (timeout 00:03:11) [common]
10979 00:26:28.700462 Setting prompt string to ['/ #']
10980 00:26:28.700526 Forcing a shell prompt, looking for ['/ #']
10982 00:26:28.750741 / #
10983 00:26:28.750839 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10984 00:26:28.750944 Waiting using forced prompt support (timeout 00:02:30)
10985 00:26:28.755692
10986 00:26:28.755996 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10987 00:26:28.756105 start: 2.2.7 export-device-env (timeout 00:03:11) [common]
10989 00:26:28.856462 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11280948/extract-nfsrootfs-rrkj3bk2'
10990 00:26:28.862062 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11280948/extract-nfsrootfs-rrkj3bk2'
10992 00:26:28.962588 / # export NFS_SERVER_IP='192.168.201.1'
10993 00:26:28.967929 export NFS_SERVER_IP='192.168.201.1'
10994 00:26:28.968228 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10995 00:26:28.968339 end: 2.2 depthcharge-retry (duration 00:01:49) [common]
10996 00:26:28.968444 end: 2 depthcharge-action (duration 00:01:49) [common]
10997 00:26:28.968532 start: 3 lava-test-retry (timeout 00:01:00) [common]
10998 00:26:28.968619 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10999 00:26:28.968693 Using namespace: common
11001 00:26:29.069022 / # #
11002 00:26:29.069144 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11003 00:26:29.074133 #
11004 00:26:29.074397 Using /lava-11280948
11006 00:26:29.174727 / # export SHELL=/bin/sh
11007 00:26:29.180257 export SHELL=/bin/sh
11009 00:26:29.280786 / # . /lava-11280948/environment
11010 00:26:29.285914 . /lava-11280948/environment
11012 00:26:29.392978 / # /lava-11280948/bin/lava-test-runner /lava-11280948/0
11013 00:26:29.393100 Test shell timeout: 10s (minimum of the action and connection timeout)
11014 00:26:29.398294 /lava-11280948/bin/lava-test-runner /lava-11280948/0
11015 00:26:29.672223 + export TESTRUN_ID=0_dmesg
11016 00:26:29.676240 + cd /lava-11280948/0/tests/0_dmesg
11017 00:26:29.678636 + cat uuid
11018 00:26:29.694358 + UUID=11280948_<8>[ 27.480229] <LAVA_SIGNAL_STARTRUN 0_dmesg 11280948_1.6.2.3.1>
11019 00:26:29.694466 1.6.2.3.1
11020 00:26:29.694560 + set +x
11021 00:26:29.694824 Received signal: <STARTRUN> 0_dmesg 11280948_1.6.2.3.1
11022 00:26:29.694919 Starting test lava.0_dmesg (11280948_1.6.2.3.1)
11023 00:26:29.695033 Skipping test definition patterns.
11024 00:26:29.700948 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11025 00:26:29.809462 <8>[ 27.595553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11026 00:26:29.809757 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11028 00:26:29.894110 <8>[ 27.680057] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11029 00:26:29.894388 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11031 00:26:29.981499 <8>[ 27.767630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11032 00:26:29.981787 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11034 00:26:29.985456 + set +x
11035 00:26:29.989114 Received signal: <ENDRUN> 0_dmesg 11280948_1.6.2.3.1
11036 00:26:29.989207 Ending use of test pattern.
11037 00:26:29.989271 Ending test lava.0_dmesg (11280948_1.6.2.3.1), duration 0.29
11039 00:26:29.992303 <8>[ 27.778266] <LAVA_SIGNAL_ENDRUN 0_dmesg 11280948_1.6.2.3.1>
11040 00:26:29.996168 <LAVA_TEST_RUNNER EXIT>
11041 00:26:29.996418 ok: lava_test_shell seems to have completed
11042 00:26:29.996519 alert: pass
crit: pass
emerg: pass
11043 00:26:29.996608 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11044 00:26:29.996690 end: 3 lava-test-retry (duration 00:00:01) [common]
11045 00:26:29.996773 start: 4 lava-test-retry (timeout 00:01:00) [common]
11046 00:26:29.996853 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11047 00:26:29.996916 Using namespace: common
11049 00:26:30.097255 / # #
11050 00:26:30.097390 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11051 00:26:30.097503 Using /lava-11280948
11053 00:26:30.197828 export SHELL=/bin/sh
11054 00:26:30.198024 #
11056 00:26:30.298559 / # export SHELL=/bin/sh. /lava-11280948/environment
11057 00:26:30.298736
11059 00:26:30.399249 / # . /lava-11280948/environment/lava-11280948/bin/lava-test-runner /lava-11280948/1
11060 00:26:30.399378 Test shell timeout: 10s (minimum of the action and connection timeout)
11061 00:26:30.399520
11062 00:26:30.404931 / # /lava-11280948/bin/lava-test-runner /lava-11280948/1
11063 00:26:30.549694 + export TESTRUN_ID=1_bootrr
11064 00:26:30.552443 + cd /lava-11280948/1/tests/1_bootrr
11065 00:26:30.556264 + cat uuid
11066 00:26:30.573260 + UUID=11280948_<8>[ 28.359163] <LAVA_SIGNAL_STARTRUN 1_bootrr 11280948_1.6.2.3.5>
11067 00:26:30.573371 1.6.2.3.5
11068 00:26:30.573466 + set +x
11069 00:26:30.573732 Received signal: <STARTRUN> 1_bootrr 11280948_1.6.2.3.5
11070 00:26:30.573824 Starting test lava.1_bootrr (11280948_1.6.2.3.5)
11071 00:26:30.573932 Skipping test definition patterns.
11072 00:26:30.586131 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11280948/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11073 00:26:30.589232 + cd /opt/bootrr/libexec/bootrr
11074 00:26:30.589339 + sh helpers/bootrr-auto
11075 00:26:30.669070 /lava-11280948/1/../bin/lava-test-case
11076 00:26:30.704498 <8>[ 28.490080] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11077 00:26:30.704799 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11079 00:26:30.755957 /lava-11280948/1/../bin/lava-test-case
11080 00:26:30.785684 <8>[ 28.571680] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11081 00:26:30.785955 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11083 00:26:30.813173 /lava-11280948/1/../bin/lava-test-case
11084 00:26:30.843607 <8>[ 28.629904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11085 00:26:30.843862 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11087 00:26:30.914673 /lava-11280948/1/../bin/lava-test-case
11088 00:26:30.946252 <8>[ 28.732210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11089 00:26:30.946518 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11091 00:26:30.987440 /lava-11280948/1/../bin/lava-test-case
11092 00:26:31.025429 <8>[ 28.811565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11093 00:26:31.025693 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11095 00:26:31.066532 /lava-11280948/1/../bin/lava-test-case
11096 00:26:31.098671 <8>[ 28.884912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11097 00:26:31.098935 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11099 00:26:31.140612 /lava-11280948/1/../bin/lava-test-case
11100 00:26:31.171755 <8>[ 28.957837] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11101 00:26:31.172013 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11103 00:26:31.212578 /lava-11280948/1/../bin/lava-test-case
11104 00:26:31.245181 <8>[ 29.031449] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11105 00:26:31.245435 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11107 00:26:31.281353 /lava-11280948/1/../bin/lava-test-case
11108 00:26:31.317529 <8>[ 29.103819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11109 00:26:31.317798 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11111 00:26:31.360877 /lava-11280948/1/../bin/lava-test-case
11112 00:26:31.397675 <8>[ 29.183822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11113 00:26:31.397939 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11115 00:26:31.426054 /lava-11280948/1/../bin/lava-test-case
11116 00:26:31.464683 <8>[ 29.250349] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11117 00:26:31.464938 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11119 00:26:31.510757 /lava-11280948/1/../bin/lava-test-case
11120 00:26:31.545235 <8>[ 29.331093] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11121 00:26:31.545503 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11123 00:26:31.590093 /lava-11280948/1/../bin/lava-test-case
11124 00:26:31.627961 <8>[ 29.413941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11125 00:26:31.628232 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11127 00:26:31.674131 /lava-11280948/1/../bin/lava-test-case
11128 00:26:31.710425 <8>[ 29.495298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11129 00:26:31.710695 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11131 00:26:31.750114 /lava-11280948/1/../bin/lava-test-case
11132 00:26:31.783515 <8>[ 29.569528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11133 00:26:31.783781 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11135 00:26:31.812319 /lava-11280948/1/../bin/lava-test-case
11136 00:26:31.849247 <8>[ 29.635330] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11137 00:26:31.849508 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11139 00:26:31.890259 /lava-11280948/1/../bin/lava-test-case
11140 00:26:31.922244 <8>[ 29.707939] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11141 00:26:31.922507 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11143 00:26:31.947988 /lava-11280948/1/../bin/lava-test-case
11144 00:26:31.979065 <8>[ 29.765474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11145 00:26:31.979331 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11147 00:26:32.025146 /lava-11280948/1/../bin/lava-test-case
11148 00:26:32.061036 <8>[ 29.846560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11149 00:26:32.061327 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11151 00:26:32.085991 /lava-11280948/1/../bin/lava-test-case
11152 00:26:32.119707 <8>[ 29.906148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11153 00:26:32.120006 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11155 00:26:32.160871 /lava-11280948/1/../bin/lava-test-case
11156 00:26:32.194012 <8>[ 29.980168] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11157 00:26:32.194280 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11159 00:26:32.220241 /lava-11280948/1/../bin/lava-test-case
11160 00:26:32.256186 <8>[ 30.041904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11161 00:26:32.256446 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11163 00:26:32.300333 /lava-11280948/1/../bin/lava-test-case
11164 00:26:32.331862 <8>[ 30.118286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11165 00:26:32.332131 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11167 00:26:32.360606 /lava-11280948/1/../bin/lava-test-case
11168 00:26:32.395218 <8>[ 30.181737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11169 00:26:32.395481 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11171 00:26:32.439355 /lava-11280948/1/../bin/lava-test-case
11172 00:26:32.473133 <8>[ 30.259375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11173 00:26:32.473398 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11175 00:26:32.516832 /lava-11280948/1/../bin/lava-test-case
11176 00:26:32.547710 <8>[ 30.334088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11177 00:26:32.547927 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11179 00:26:32.574324 /lava-11280948/1/../bin/lava-test-case
11180 00:26:32.605661 <8>[ 30.391961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11181 00:26:32.605926 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11183 00:26:32.645629 /lava-11280948/1/../bin/lava-test-case
11184 00:26:32.677168 <8>[ 30.463411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11185 00:26:32.677434 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11187 00:26:32.710460 /lava-11280948/1/../bin/lava-test-case
11188 00:26:32.747273 <8>[ 30.533591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11189 00:26:32.747555 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11191 00:26:32.786737 /lava-11280948/1/../bin/lava-test-case
11192 00:26:32.818725 <8>[ 30.605122] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11193 00:26:32.818987 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11195 00:26:32.857120 /lava-11280948/1/../bin/lava-test-case
11196 00:26:32.887705 <8>[ 30.674229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11197 00:26:32.887997 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11199 00:26:32.932730 /lava-11280948/1/../bin/lava-test-case
11200 00:26:32.964409 <8>[ 30.750799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11201 00:26:32.964670 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11203 00:26:33.006732 /lava-11280948/1/../bin/lava-test-case
11204 00:26:33.040388 <8>[ 30.825219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11205 00:26:33.040649 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11207 00:26:33.071177 /lava-11280948/1/../bin/lava-test-case
11208 00:26:33.102855 <8>[ 30.888987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11209 00:26:33.103118 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11211 00:26:33.143619 /lava-11280948/1/../bin/lava-test-case
11212 00:26:33.176233 <8>[ 30.962026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11213 00:26:33.176491 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11215 00:26:33.220708 /lava-11280948/1/../bin/lava-test-case
11216 00:26:33.254477 <8>[ 31.040811] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11217 00:26:33.254736 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11219 00:26:33.279925 /lava-11280948/1/../bin/lava-test-case
11220 00:26:33.310872 <8>[ 31.097163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11221 00:26:33.311134 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11223 00:26:33.356711 /lava-11280948/1/../bin/lava-test-case
11224 00:26:33.392852 <8>[ 31.179092] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11225 00:26:33.393118 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11227 00:26:33.424712 /lava-11280948/1/../bin/lava-test-case
11228 00:26:33.454753 <8>[ 31.241278] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11229 00:26:33.455009 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11231 00:26:33.495791 /lava-11280948/1/../bin/lava-test-case
11232 00:26:33.526857 <8>[ 31.313595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11233 00:26:33.527118 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11235 00:26:33.554565 /lava-11280948/1/../bin/lava-test-case
11236 00:26:33.585606 <8>[ 31.371580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11237 00:26:33.585864 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11239 00:26:33.626835 /lava-11280948/1/../bin/lava-test-case
11240 00:26:33.662167 <8>[ 31.448597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11241 00:26:33.662430 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11243 00:26:33.688261 /lava-11280948/1/../bin/lava-test-case
11244 00:26:33.724307 <8>[ 31.510656] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11245 00:26:33.724565 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11247 00:26:33.774805 /lava-11280948/1/../bin/lava-test-case
11248 00:26:33.812283 <8>[ 31.598385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11249 00:26:33.812551 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11251 00:26:33.838322 /lava-11280948/1/../bin/lava-test-case
11252 00:26:33.869868 <8>[ 31.656410] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11253 00:26:33.870125 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11255 00:26:33.915226 /lava-11280948/1/../bin/lava-test-case
11256 00:26:33.949814 <8>[ 31.735774] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11257 00:26:33.950074 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11259 00:26:33.976956 /lava-11280948/1/../bin/lava-test-case
11260 00:26:34.010197 <8>[ 31.796219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11261 00:26:34.010461 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11263 00:26:34.051620 /lava-11280948/1/../bin/lava-test-case
11264 00:26:34.087768 <8>[ 31.874376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11265 00:26:34.088031 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11267 00:26:34.121028 /lava-11280948/1/../bin/lava-test-case
11268 00:26:34.152856 <8>[ 31.939523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11269 00:26:34.153118 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11271 00:26:34.197811 /lava-11280948/1/../bin/lava-test-case
11272 00:26:34.233309 <8>[ 32.019366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11273 00:26:34.233567 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11275 00:26:34.273262 /lava-11280948/1/../bin/lava-test-case
11276 00:26:34.305319 <8>[ 32.091889] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11277 00:26:34.305582 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11279 00:26:34.331664 /lava-11280948/1/../bin/lava-test-case
11280 00:26:34.363845 <8>[ 32.150022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11281 00:26:34.364138 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11283 00:26:34.406678 /lava-11280948/1/../bin/lava-test-case
11284 00:26:34.442241 <8>[ 32.228191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11285 00:26:34.442507 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11287 00:26:34.478046 /lava-11280948/1/../bin/lava-test-case
11288 00:26:34.513300 <8>[ 32.299950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11289 00:26:34.513615 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11291 00:26:34.555512 /lava-11280948/1/../bin/lava-test-case
11292 00:26:34.588432 <8>[ 32.374876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11293 00:26:34.588749 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11295 00:26:34.633367 /lava-11280948/1/../bin/lava-test-case
11296 00:26:34.668228 <8>[ 32.454996] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11297 00:26:34.668505 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11299 00:26:34.711894 /lava-11280948/1/../bin/lava-test-case
11300 00:26:34.748186 <8>[ 32.534593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11301 00:26:34.748505 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11303 00:26:34.787806 /lava-11280948/1/../bin/lava-test-case
11304 00:26:34.817912 <8>[ 32.604204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11305 00:26:34.818283 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11307 00:26:34.863506 /lava-11280948/1/../bin/lava-test-case
11308 00:26:34.895611 <8>[ 32.682233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11309 00:26:34.895891 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11311 00:26:34.923268 /lava-11280948/1/../bin/lava-test-case
11312 00:26:34.959824 <8>[ 32.746539] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11313 00:26:34.960150 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11315 00:26:35.001174 /lava-11280948/1/../bin/lava-test-case
11316 00:26:35.032509 <8>[ 32.819160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11317 00:26:35.032835 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11319 00:26:35.073743 /lava-11280948/1/../bin/lava-test-case
11320 00:26:35.104951 <8>[ 32.891365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11321 00:26:35.105229 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11323 00:26:35.129934 /lava-11280948/1/../bin/lava-test-case
11324 00:26:35.161822 <8>[ 32.948078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11325 00:26:35.162082 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11327 00:26:35.209078 /lava-11280948/1/../bin/lava-test-case
11328 00:26:35.242096 <8>[ 33.028772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11329 00:26:35.242359 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11331 00:26:35.269655 /lava-11280948/1/../bin/lava-test-case
11332 00:26:35.305466 <8>[ 33.092023] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11333 00:26:35.305729 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11335 00:26:35.346872 /lava-11280948/1/../bin/lava-test-case
11336 00:26:35.382552 <8>[ 33.168702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11337 00:26:35.382828 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11339 00:26:35.407786 /lava-11280948/1/../bin/lava-test-case
11340 00:26:35.441918 <8>[ 33.228250] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11341 00:26:35.442195 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11343 00:26:35.484354 /lava-11280948/1/../bin/lava-test-case
11344 00:26:35.519451 <8>[ 33.305886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11345 00:26:35.519771 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11347 00:26:35.567440 /lava-11280948/1/../bin/lava-test-case
11348 00:26:35.599669 <8>[ 33.386225] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11349 00:26:35.600006 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11351 00:26:35.644669 /lava-11280948/1/../bin/lava-test-case
11352 00:26:35.681328 <8>[ 33.467878] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11353 00:26:35.681644 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11355 00:26:35.723250 /lava-11280948/1/../bin/lava-test-case
11356 00:26:35.757167 <8>[ 33.544010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11357 00:26:35.757475 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11359 00:26:35.801670 /lava-11280948/1/../bin/lava-test-case
11360 00:26:35.838826 <8>[ 33.624598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11361 00:26:35.839133 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11363 00:26:35.878213 /lava-11280948/1/../bin/lava-test-case
11364 00:26:35.910114 <8>[ 33.696871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11365 00:26:35.910424 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11367 00:26:35.961895 /lava-11280948/1/../bin/lava-test-case
11368 00:26:35.998039 <8>[ 33.784768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11369 00:26:35.998360 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11371 00:26:36.041546 /lava-11280948/1/../bin/lava-test-case
11372 00:26:36.081257 <8>[ 33.867268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11373 00:26:36.081573 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11375 00:26:36.124106 /lava-11280948/1/../bin/lava-test-case
11376 00:26:36.159711 <8>[ 33.946351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11377 00:26:36.160047 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11379 00:26:36.204908 /lava-11280948/1/../bin/lava-test-case
11380 00:26:36.243147 <8>[ 34.029678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11381 00:26:36.243471 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11383 00:26:36.288788 /lava-11280948/1/../bin/lava-test-case
11384 00:26:36.330645 <8>[ 34.116653] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11385 00:26:36.331494 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11387 00:26:36.378437 /lava-11280948/1/../bin/lava-test-case
11388 00:26:36.409818 <8>[ 34.196420] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11389 00:26:36.410086 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11391 00:26:36.453224 /lava-11280948/1/../bin/lava-test-case
11392 00:26:36.488572 <8>[ 34.275655] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11393 00:26:36.488866 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11395 00:26:36.534567 /lava-11280948/1/../bin/lava-test-case
11396 00:26:36.570254 <8>[ 34.356642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11397 00:26:36.570521 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11399 00:26:36.613823 /lava-11280948/1/../bin/lava-test-case
11400 00:26:36.649124 <8>[ 34.434380] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11401 00:26:36.649385 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11403 00:26:36.676418 /lava-11280948/1/../bin/lava-test-case
11404 00:26:36.714347 <8>[ 34.501095] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11405 00:26:36.714613 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11407 00:26:36.765573 /lava-11280948/1/../bin/lava-test-case
11408 00:26:36.799137 <8>[ 34.585420] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11409 00:26:36.799411 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11411 00:26:36.824914 /lava-11280948/1/../bin/lava-test-case
11412 00:26:36.862795 <8>[ 34.649720] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11413 00:26:36.863050 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11415 00:26:36.909744 /lava-11280948/1/../bin/lava-test-case
11416 00:26:36.944886 <8>[ 34.731839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11417 00:26:36.945150 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11419 00:26:36.972009 /lava-11280948/1/../bin/lava-test-case
11420 00:26:37.005755 <8>[ 34.792047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11421 00:26:37.006020 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11423 00:26:37.049344 /lava-11280948/1/../bin/lava-test-case
11424 00:26:37.086059 <8>[ 34.872662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11425 00:26:37.086325 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11427 00:26:37.121603 /lava-11280948/1/../bin/lava-test-case
11428 00:26:37.160796 <8>[ 34.947369] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11429 00:26:37.161053 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11431 00:26:37.206569 /lava-11280948/1/../bin/lava-test-case
11432 00:26:37.240573 <8>[ 35.027229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11433 00:26:37.240835 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11435 00:26:37.269738 /lava-11280948/1/../bin/lava-test-case
11436 00:26:37.307004 <8>[ 35.093752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11437 00:26:37.307266 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11439 00:26:37.354286 /lava-11280948/1/../bin/lava-test-case
11440 00:26:37.386800 <8>[ 35.173471] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11441 00:26:37.387057 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11443 00:26:37.414611 /lava-11280948/1/../bin/lava-test-case
11444 00:26:37.447091 <8>[ 35.233692] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11445 00:26:37.447362 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11447 00:26:37.498135 /lava-11280948/1/../bin/lava-test-case
11448 00:26:37.530190 <8>[ 35.317294] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11449 00:26:37.530450 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11451 00:26:37.571466 /lava-11280948/1/../bin/lava-test-case
11452 00:26:37.602909 <8>[ 35.389395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11453 00:26:37.603170 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11455 00:26:37.629743 /lava-11280948/1/../bin/lava-test-case
11456 00:26:37.661969 <8>[ 35.447984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11457 00:26:37.662264 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11459 00:26:37.701036 /lava-11280948/1/../bin/lava-test-case
11460 00:26:37.733285 <8>[ 35.520141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11461 00:26:37.733552 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11463 00:26:37.757679 /lava-11280948/1/../bin/lava-test-case
11464 00:26:37.792495 <8>[ 35.579356] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11465 00:26:37.792800 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11467 00:26:37.838098 /lava-11280948/1/../bin/lava-test-case
11468 00:26:37.870906 <8>[ 35.657857] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11469 00:26:37.871191 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11471 00:26:37.894934 /lava-11280948/1/../bin/lava-test-case
11472 00:26:37.928726 <8>[ 35.715625] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11473 00:26:37.928983 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11475 00:26:38.990362 /lava-11280948/1/../bin/lava-test-case
11476 00:26:39.022132 <8>[ 36.809110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11477 00:26:39.022458 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11479 00:26:39.048811 /lava-11280948/1/../bin/lava-test-case
11480 00:26:39.082311 <8>[ 36.869308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11481 00:26:39.082633 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11483 00:26:40.138205 /lava-11280948/1/../bin/lava-test-case
11484 00:26:40.175185 <8>[ 37.962254] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11485 00:26:40.175518 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11487 00:26:40.201231 /lava-11280948/1/../bin/lava-test-case
11488 00:26:40.232152 <8>[ 38.019466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11489 00:26:40.232480 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11491 00:26:41.286895 /lava-11280948/1/../bin/lava-test-case
11492 00:26:41.322376 <8>[ 39.108674] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11493 00:26:41.322702 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11495 00:26:41.345282 /lava-11280948/1/../bin/lava-test-case
11496 00:26:41.374769 <8>[ 39.161929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11497 00:26:41.375099 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11499 00:26:42.432881 /lava-11280948/1/../bin/lava-test-case
11500 00:26:42.471078 <8>[ 40.258364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11501 00:26:42.471400 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11503 00:26:42.496330 /lava-11280948/1/../bin/lava-test-case
11504 00:26:42.529488 <8>[ 40.317052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11505 00:26:42.529822 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11507 00:26:43.584857 /lava-11280948/1/../bin/lava-test-case
11508 00:26:43.618607 <8>[ 41.406264] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11509 00:26:43.618927 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11511 00:26:43.643274 /lava-11280948/1/../bin/lava-test-case
11512 00:26:43.677135 <8>[ 41.464413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11513 00:26:43.677511 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11515 00:26:44.729468 /lava-11280948/1/../bin/lava-test-case
11516 00:26:44.761688 <8>[ 42.549394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11517 00:26:44.762050 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11519 00:26:44.785538 /lava-11280948/1/../bin/lava-test-case
11520 00:26:44.816984 <8>[ 42.604470] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11521 00:26:44.817339 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11523 00:26:45.868666 /lava-11280948/1/../bin/lava-test-case
11524 00:26:45.904097 <8>[ 43.691765] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11525 00:26:45.904455 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11527 00:26:45.929057 /lava-11280948/1/../bin/lava-test-case
11528 00:26:45.959615 <8>[ 43.747651] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11529 00:26:45.959937 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11531 00:26:45.984644 /lava-11280948/1/../bin/lava-test-case
11532 00:26:46.014688 <8>[ 43.802631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11533 00:26:46.015012 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11535 00:26:47.065967 /lava-11280948/1/../bin/lava-test-case
11536 00:26:47.100277 <8>[ 44.888343] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11537 00:26:47.100612 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11539 00:26:47.124998 /lava-11280948/1/../bin/lava-test-case
11540 00:26:47.156423 <8>[ 44.944432] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11541 00:26:47.156791 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11543 00:26:47.194502 /lava-11280948/1/../bin/lava-test-case
11544 00:26:47.227179 <8>[ 45.015214] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11545 00:26:47.227499 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11547 00:26:47.251351 /lava-11280948/1/../bin/lava-test-case
11548 00:26:47.284345 <8>[ 45.072513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11549 00:26:47.284665 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11551 00:26:47.324151 /lava-11280948/1/../bin/lava-test-case
11552 00:26:47.356397 <8>[ 45.144370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11553 00:26:47.356731 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11555 00:26:47.401803 /lava-11280948/1/../bin/lava-test-case
11556 00:26:47.433209 <8>[ 45.221466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11557 00:26:47.433541 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11559 00:26:47.473124 /lava-11280948/1/../bin/lava-test-case
11560 00:26:47.502037 <8>[ 45.289841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11561 00:26:47.502358 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11563 00:26:47.530615 /lava-11280948/1/../bin/lava-test-case
11564 00:26:47.561457 <8>[ 45.349282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11565 00:26:47.561789 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11567 00:26:47.601466 /lava-11280948/1/../bin/lava-test-case
11568 00:26:47.634073 <8>[ 45.421320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11569 00:26:47.634420 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11571 00:26:47.672749 /lava-11280948/1/../bin/lava-test-case
11572 00:26:47.705969 <8>[ 45.494227] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11573 00:26:47.706270 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11575 00:26:47.737135 /lava-11280948/1/../bin/lava-test-case
11576 00:26:47.768497 <8>[ 45.556449] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11577 00:26:47.768799 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11579 00:26:47.810034 /lava-11280948/1/../bin/lava-test-case
11580 00:26:47.847014 <8>[ 45.634450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11581 00:26:47.847323 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11583 00:26:47.872783 /lava-11280948/1/../bin/lava-test-case
11584 00:26:47.906759 <8>[ 45.694476] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11585 00:26:47.907064 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11587 00:26:47.948771 /lava-11280948/1/../bin/lava-test-case
11588 00:26:47.984945 <8>[ 45.773226] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11589 00:26:47.985253 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11591 00:26:48.010558 /lava-11280948/1/../bin/lava-test-case
11592 00:26:48.043104 <8>[ 45.831296] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11593 00:26:48.043417 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11595 00:26:48.090875 /lava-11280948/1/../bin/lava-test-case
11596 00:26:48.124341 <8>[ 45.912416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11597 00:26:48.124650 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11599 00:26:48.151427 /lava-11280948/1/../bin/lava-test-case
11600 00:26:48.184041 <8>[ 45.972277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11601 00:26:48.184371 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11603 00:26:48.222777 /lava-11280948/1/../bin/lava-test-case
11604 00:26:48.254629 <8>[ 46.042272] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11605 00:26:48.254925 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11607 00:26:48.278929 /lava-11280948/1/../bin/lava-test-case
11608 00:26:48.309534 <8>[ 46.097159] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11609 00:26:48.309837 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11611 00:26:48.349784 /lava-11280948/1/../bin/lava-test-case
11612 00:26:48.362534 <6>[ 46.157098] vpu: disabling
11613 00:26:48.365555 <6>[ 46.160333] vproc2: disabling
11614 00:26:48.369492 <6>[ 46.163786] vproc1: disabling
11615 00:26:48.372426 <6>[ 46.167224] vaud18: disabling
11616 00:26:48.379435 <6>[ 46.170892] vsram_others: disabling
11617 00:26:48.382484 <6>[ 46.174983] va09: disabling
11618 00:26:48.385845 <6>[ 46.180471] vsram_md: disabling
11619 00:26:48.390675 <6>[ 46.185160] Vgpu: disabling
11620 00:26:48.410002 <8>[ 46.198358] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11621 00:26:48.410291 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11623 00:26:48.435498 /lava-11280948/1/../bin/lava-test-case
11624 00:26:48.467196 <8>[ 46.254927] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11625 00:26:48.467490 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11627 00:26:49.517694 /lava-11280948/1/../bin/lava-test-case
11628 00:26:49.548841 <8>[ 47.337317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11629 00:26:49.549143 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11631 00:26:50.602260 /lava-11280948/1/../bin/lava-test-case
11632 00:26:50.636984 <8>[ 48.425468] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11633 00:26:50.637325 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11635 00:26:50.664109 /lava-11280948/1/../bin/lava-test-case
11636 00:26:50.707022 <8>[ 48.494356] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11637 00:26:50.707808 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11639 00:26:50.752699 /lava-11280948/1/../bin/lava-test-case
11640 00:26:50.792879 <8>[ 48.580964] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11641 00:26:50.793624 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11643 00:26:50.821359 /lava-11280948/1/../bin/lava-test-case
11644 00:26:50.861374 <8>[ 48.649301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11645 00:26:50.862158 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11647 00:26:50.907343 /lava-11280948/1/../bin/lava-test-case
11648 00:26:50.948393 <8>[ 48.736105] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11649 00:26:50.949340 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11651 00:26:50.983293 /lava-11280948/1/../bin/lava-test-case
11652 00:26:51.022860 <8>[ 48.810205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11653 00:26:51.023641 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11655 00:26:51.072341 /lava-11280948/1/../bin/lava-test-case
11656 00:26:51.111677 <8>[ 48.899383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11657 00:26:51.112540 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11659 00:26:51.139288 /lava-11280948/1/../bin/lava-test-case
11660 00:26:51.179575 <8>[ 48.967642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11661 00:26:51.180434 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11663 00:26:51.223790 /lava-11280948/1/../bin/lava-test-case
11664 00:26:51.264067 <8>[ 49.052145] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11665 00:26:51.264858 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11667 00:26:51.293066 /lava-11280948/1/../bin/lava-test-case
11668 00:26:51.331218 <8>[ 49.119060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11669 00:26:51.332167 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11671 00:26:51.386522 /lava-11280948/1/../bin/lava-test-case
11672 00:26:51.429791 <8>[ 49.217281] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11673 00:26:51.430627 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11675 00:26:51.458151 /lava-11280948/1/../bin/lava-test-case
11676 00:26:51.497305 <8>[ 49.285440] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11677 00:26:51.498074 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11679 00:26:51.544390 /lava-11280948/1/../bin/lava-test-case
11680 00:26:51.587326 <8>[ 49.375181] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11681 00:26:51.588104 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11683 00:26:51.615514 /lava-11280948/1/../bin/lava-test-case
11684 00:26:51.656733 <8>[ 49.444418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11685 00:26:51.657620 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11687 00:26:51.708251 /lava-11280948/1/../bin/lava-test-case
11688 00:26:51.750558 <8>[ 49.538500] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11689 00:26:51.751532 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11691 00:26:51.786477 /lava-11280948/1/../bin/lava-test-case
11692 00:26:51.827565 <8>[ 49.615456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11693 00:26:51.828462 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11695 00:26:51.876425 /lava-11280948/1/../bin/lava-test-case
11696 00:26:51.918593 <8>[ 49.706469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11697 00:26:51.919399 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11699 00:26:51.947870 /lava-11280948/1/../bin/lava-test-case
11700 00:26:51.987576 <8>[ 49.775094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11701 00:26:51.988400 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11703 00:26:52.034012 /lava-11280948/1/../bin/lava-test-case
11704 00:26:52.072575 <8>[ 49.860178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11705 00:26:52.073353 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11707 00:26:52.100768 /lava-11280948/1/../bin/lava-test-case
11708 00:26:52.143637 <8>[ 49.931171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11709 00:26:52.144373 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11711 00:26:52.194033 /lava-11280948/1/../bin/lava-test-case
11712 00:26:52.233946 <8>[ 50.021932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11713 00:26:52.234724 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11715 00:26:53.280726 /lava-11280948/1/../bin/lava-test-case
11716 00:26:53.318512 <8>[ 51.106989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11717 00:26:53.318946 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11719 00:26:54.364411 /lava-11280948/1/../bin/lava-test-case
11720 00:26:54.399043 <8>[ 52.187866] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11721 00:26:54.399391 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11722 00:26:54.399518 Bad test result: blocked
11723 00:26:54.424984 /lava-11280948/1/../bin/lava-test-case
11724 00:26:54.455524 <8>[ 52.244001] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11725 00:26:54.455941 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11727 00:26:55.503616 /lava-11280948/1/../bin/lava-test-case
11728 00:26:55.545272 <8>[ 53.334021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11729 00:26:55.546030 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11731 00:26:55.575049 /lava-11280948/1/../bin/lava-test-case
11732 00:26:55.614462 <8>[ 53.402828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11733 00:26:55.615251 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11735 00:26:55.659204 /lava-11280948/1/../bin/lava-test-case
11736 00:26:55.698892 <8>[ 53.487425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11737 00:26:55.699683 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11739 00:26:55.744637 /lava-11280948/1/../bin/lava-test-case
11740 00:26:55.783824 <8>[ 53.572472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11741 00:26:55.784630 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11743 00:26:55.812625 /lava-11280948/1/../bin/lava-test-case
11744 00:26:55.852419 <8>[ 53.640835] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11745 00:26:55.853104 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11747 00:26:55.904151 /lava-11280948/1/../bin/lava-test-case
11748 00:26:55.943199 <8>[ 53.731702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11749 00:26:55.944002 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11751 00:26:55.971319 /lava-11280948/1/../bin/lava-test-case
11752 00:26:56.007271 <8>[ 53.795861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11753 00:26:56.008061 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11755 00:26:57.066923 /lava-11280948/1/../bin/lava-test-case
11756 00:26:57.105767 <8>[ 54.894164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11757 00:26:57.106543 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11759 00:26:57.133155 /lava-11280948/1/../bin/lava-test-case
11760 00:26:57.170460 <8>[ 54.959236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11761 00:26:57.171278 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11763 00:26:58.232853 /lava-11280948/1/../bin/lava-test-case
11764 00:26:58.274239 <8>[ 56.062844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11765 00:26:58.275079 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11767 00:26:58.301422 /lava-11280948/1/../bin/lava-test-case
11768 00:26:58.339257 <8>[ 56.128240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11769 00:26:58.340049 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11771 00:26:59.402564 /lava-11280948/1/../bin/lava-test-case
11772 00:26:59.449038 <8>[ 57.237409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11773 00:26:59.449806 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11775 00:26:59.474654 /lava-11280948/1/../bin/lava-test-case
11776 00:26:59.512012 <8>[ 57.300931] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11777 00:26:59.512819 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11779 00:27:00.577567 /lava-11280948/1/../bin/lava-test-case
11780 00:27:00.610029 <8>[ 58.399697] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11781 00:27:00.610365 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11783 00:27:00.634927 /lava-11280948/1/../bin/lava-test-case
11784 00:27:00.664675 <8>[ 58.454324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11785 00:27:00.664968 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11787 00:27:00.700221 /lava-11280948/1/../bin/lava-test-case
11788 00:27:00.730582 <8>[ 58.520364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11789 00:27:00.730868 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11791 00:27:00.767669 /lava-11280948/1/../bin/lava-test-case
11792 00:27:00.798399 <8>[ 58.587627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11793 00:27:00.798689 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11795 00:27:00.822334 /lava-11280948/1/../bin/lava-test-case
11796 00:27:00.850118 <8>[ 58.639575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11797 00:27:00.850383 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11799 00:27:00.893491 /lava-11280948/1/../bin/lava-test-case
11800 00:27:00.923838 <8>[ 58.713406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11801 00:27:00.924108 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11803 00:27:00.950486 /lava-11280948/1/../bin/lava-test-case
11804 00:27:00.981381 <8>[ 58.770093] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11805 00:27:00.981646 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11807 00:27:01.018708 /lava-11280948/1/../bin/lava-test-case
11808 00:27:01.051301 <8>[ 58.840823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11809 00:27:01.051560 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11811 00:27:01.076218 /lava-11280948/1/../bin/lava-test-case
11812 00:27:01.106571 <8>[ 58.896107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11813 00:27:01.106833 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11815 00:27:01.144520 /lava-11280948/1/../bin/lava-test-case
11816 00:27:01.176120 <8>[ 58.965906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11817 00:27:01.176388 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11819 00:27:01.186993 + set +x<8>[ 58.979796] <LAVA_SIGNAL_ENDRUN 1_bootrr 11280948_1.6.2.3.5>
11820 00:27:01.187247 Received signal: <ENDRUN> 1_bootrr 11280948_1.6.2.3.5
11821 00:27:01.187325 Ending use of test pattern.
11822 00:27:01.187388 Ending test lava.1_bootrr (11280948_1.6.2.3.5), duration 30.61
11824 00:27:01.189982
11825 00:27:01.195559 <LAVA_TEST_RUNNER EXIT>
11826 00:27:01.195808 ok: lava_test_shell seems to have completed
11827 00:27:01.196799 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11828 00:27:01.196942 end: 4.1 lava-test-shell (duration 00:00:31) [common]
11829 00:27:01.197029 end: 4 lava-test-retry (duration 00:00:31) [common]
11830 00:27:01.197111 start: 5 finalize (timeout 00:07:13) [common]
11831 00:27:01.197198 start: 5.1 power-off (timeout 00:00:30) [common]
11832 00:27:01.197361 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11833 00:27:01.272907 >> Command sent successfully.
11834 00:27:01.275269 Returned 0 in 0 seconds
11835 00:27:01.375706 end: 5.1 power-off (duration 00:00:00) [common]
11837 00:27:01.376121 start: 5.2 read-feedback (timeout 00:07:13) [common]
11838 00:27:01.376413 Listened to connection for namespace 'common' for up to 1s
11839 00:27:02.377363 Finalising connection for namespace 'common'
11840 00:27:02.377526 Disconnecting from shell: Finalise
11841 00:27:02.377613 / #
11842 00:27:02.477933 end: 5.2 read-feedback (duration 00:00:01) [common]
11843 00:27:02.478095 end: 5 finalize (duration 00:00:01) [common]
11844 00:27:02.478208 Cleaning after the job
11845 00:27:02.478308 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11280948/tftp-deploy-u7bwdy0v/ramdisk
11846 00:27:02.481063 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11280948/tftp-deploy-u7bwdy0v/kernel
11847 00:27:02.493575 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11280948/tftp-deploy-u7bwdy0v/dtb
11848 00:27:02.493758 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11280948/tftp-deploy-u7bwdy0v/nfsrootfs
11849 00:27:02.566360 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11280948/tftp-deploy-u7bwdy0v/modules
11850 00:27:02.573891 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11280948
11851 00:27:02.950583 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11280948
11852 00:27:02.950769 Job finished correctly