Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 24
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 35
- Errors: 1
1 00:23:31.656151 lava-dispatcher, installed at version: 2023.05.1
2 00:23:31.656361 start: 0 validate
3 00:23:31.656489 Start time: 2023-08-14 00:23:31.656482+00:00 (UTC)
4 00:23:31.656620 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:23:31.656750 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 00:23:31.925396 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:23:31.925653 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:23:47.699736 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:23:47.700478 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:23:47.971218 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:23:47.972146 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:23:57.740204 validate duration: 26.08
14 00:23:57.740912 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:23:57.741222 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:23:57.741502 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:23:57.741738 Not decompressing ramdisk as can be used compressed.
18 00:23:57.741822 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 00:23:57.741885 saving as /var/lib/lava/dispatcher/tmp/11280974/tftp-deploy-im_133ae/ramdisk/rootfs.cpio.gz
20 00:23:57.741950 total size: 34390042 (32MB)
21 00:23:57.999742 progress 0% (0MB)
22 00:23:58.009201 progress 5% (1MB)
23 00:23:58.018565 progress 10% (3MB)
24 00:23:58.028050 progress 15% (4MB)
25 00:23:58.037259 progress 20% (6MB)
26 00:23:58.046751 progress 25% (8MB)
27 00:23:58.056043 progress 30% (9MB)
28 00:23:58.065333 progress 35% (11MB)
29 00:23:58.074598 progress 40% (13MB)
30 00:23:58.084004 progress 45% (14MB)
31 00:23:58.093206 progress 50% (16MB)
32 00:23:58.102516 progress 55% (18MB)
33 00:23:58.111785 progress 60% (19MB)
34 00:23:58.121579 progress 65% (21MB)
35 00:23:58.131255 progress 70% (22MB)
36 00:23:58.141090 progress 75% (24MB)
37 00:23:58.150696 progress 80% (26MB)
38 00:23:58.160322 progress 85% (27MB)
39 00:23:58.169488 progress 90% (29MB)
40 00:23:58.178675 progress 95% (31MB)
41 00:23:58.187771 progress 100% (32MB)
42 00:23:58.187970 32MB downloaded in 0.45s (73.53MB/s)
43 00:23:58.188124 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:23:58.188370 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:23:58.188456 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:23:58.188539 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:23:58.188687 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:23:58.188755 saving as /var/lib/lava/dispatcher/tmp/11280974/tftp-deploy-im_133ae/kernel/Image
50 00:23:58.188822 total size: 49220096 (46MB)
51 00:23:58.188889 No compression specified
52 00:23:58.454773 progress 0% (0MB)
53 00:23:58.467934 progress 5% (2MB)
54 00:23:58.480955 progress 10% (4MB)
55 00:23:58.494002 progress 15% (7MB)
56 00:23:58.507075 progress 20% (9MB)
57 00:23:58.520921 progress 25% (11MB)
58 00:23:58.534583 progress 30% (14MB)
59 00:23:58.548531 progress 35% (16MB)
60 00:23:58.561746 progress 40% (18MB)
61 00:23:58.574865 progress 45% (21MB)
62 00:23:58.588078 progress 50% (23MB)
63 00:23:58.601196 progress 55% (25MB)
64 00:23:58.614305 progress 60% (28MB)
65 00:23:58.627749 progress 65% (30MB)
66 00:23:58.640813 progress 70% (32MB)
67 00:23:58.653632 progress 75% (35MB)
68 00:23:58.666620 progress 80% (37MB)
69 00:23:58.679549 progress 85% (39MB)
70 00:23:58.692616 progress 90% (42MB)
71 00:23:58.705489 progress 95% (44MB)
72 00:23:58.718779 progress 100% (46MB)
73 00:23:58.718920 46MB downloaded in 0.53s (88.55MB/s)
74 00:23:58.719071 end: 1.2.1 http-download (duration 00:00:01) [common]
76 00:23:58.719397 end: 1.2 download-retry (duration 00:00:01) [common]
77 00:23:58.719490 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:23:58.719578 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:23:58.719716 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:23:58.719792 saving as /var/lib/lava/dispatcher/tmp/11280974/tftp-deploy-im_133ae/dtb/mt8192-asurada-spherion-r0.dtb
81 00:23:58.719855 total size: 47278 (0MB)
82 00:23:58.719914 No compression specified
83 00:23:58.986295 progress 69% (0MB)
84 00:23:58.986635 progress 100% (0MB)
85 00:23:58.986845 0MB downloaded in 0.27s (0.17MB/s)
86 00:23:58.987044 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:23:58.987460 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:23:58.987548 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:23:58.987633 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:23:58.987821 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:23:58.987891 saving as /var/lib/lava/dispatcher/tmp/11280974/tftp-deploy-im_133ae/modules/modules.tar
93 00:23:58.987971 total size: 8562896 (8MB)
94 00:23:58.988034 Using unxz to decompress xz
95 00:23:58.992638 progress 0% (0MB)
96 00:23:59.015949 progress 5% (0MB)
97 00:23:59.040392 progress 10% (0MB)
98 00:23:59.067130 progress 15% (1MB)
99 00:23:59.093095 progress 20% (1MB)
100 00:23:59.119528 progress 25% (2MB)
101 00:23:59.146407 progress 30% (2MB)
102 00:23:59.171777 progress 35% (2MB)
103 00:23:59.197202 progress 40% (3MB)
104 00:23:59.222064 progress 45% (3MB)
105 00:23:59.248965 progress 50% (4MB)
106 00:23:59.274737 progress 55% (4MB)
107 00:23:59.299844 progress 60% (4MB)
108 00:23:59.323182 progress 65% (5MB)
109 00:23:59.349210 progress 70% (5MB)
110 00:23:59.374331 progress 75% (6MB)
111 00:23:59.402928 progress 80% (6MB)
112 00:23:59.433680 progress 85% (6MB)
113 00:23:59.459973 progress 90% (7MB)
114 00:23:59.485111 progress 95% (7MB)
115 00:23:59.508851 progress 100% (8MB)
116 00:23:59.514008 8MB downloaded in 0.53s (15.52MB/s)
117 00:23:59.514324 end: 1.4.1 http-download (duration 00:00:01) [common]
119 00:23:59.514602 end: 1.4 download-retry (duration 00:00:01) [common]
120 00:23:59.514698 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 00:23:59.514794 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 00:23:59.514879 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:23:59.514967 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 00:23:59.515209 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y
125 00:23:59.515351 makedir: /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin
126 00:23:59.515513 makedir: /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/tests
127 00:23:59.515622 makedir: /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/results
128 00:23:59.515741 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-add-keys
129 00:23:59.515897 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-add-sources
130 00:23:59.516035 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-background-process-start
131 00:23:59.516172 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-background-process-stop
132 00:23:59.516303 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-common-functions
133 00:23:59.516434 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-echo-ipv4
134 00:23:59.516565 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-install-packages
135 00:23:59.516695 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-installed-packages
136 00:23:59.516824 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-os-build
137 00:23:59.516952 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-probe-channel
138 00:23:59.517083 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-probe-ip
139 00:23:59.517215 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-target-ip
140 00:23:59.517346 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-target-mac
141 00:23:59.517474 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-target-storage
142 00:23:59.517606 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-test-case
143 00:23:59.517736 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-test-event
144 00:23:59.517863 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-test-feedback
145 00:23:59.517993 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-test-raise
146 00:23:59.518124 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-test-reference
147 00:23:59.518254 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-test-runner
148 00:23:59.518384 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-test-set
149 00:23:59.518515 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-test-shell
150 00:23:59.518647 Updating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-install-packages (oe)
151 00:23:59.518806 Updating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/bin/lava-installed-packages (oe)
152 00:23:59.518935 Creating /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/environment
153 00:23:59.519039 LAVA metadata
154 00:23:59.519115 - LAVA_JOB_ID=11280974
155 00:23:59.519183 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:23:59.519295 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:58) [common]
157 00:23:59.519365 skipped lava-vland-overlay
158 00:23:59.519454 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:23:59.519539 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:58) [common]
160 00:23:59.519603 skipped lava-multinode-overlay
161 00:23:59.519677 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:23:59.519763 start: 1.5.2.3 test-definition (timeout 00:09:58) [common]
163 00:23:59.519841 Loading test definitions
164 00:23:59.519936 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:58) [common]
165 00:23:59.520015 Using /lava-11280974 at stage 0
166 00:23:59.520345 uuid=11280974_1.5.2.3.1 testdef=None
167 00:23:59.520435 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:23:59.520523 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
169 00:23:59.521062 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:23:59.521286 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
172 00:23:59.521917 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:23:59.522155 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
175 00:23:59.522768 runner path: /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/0/tests/0_cros-ec test_uuid 11280974_1.5.2.3.1
176 00:23:59.522927 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:23:59.523139 Creating lava-test-runner.conf files
179 00:23:59.523204 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11280974/lava-overlay-elvcnc7y/lava-11280974/0 for stage 0
180 00:23:59.523296 - 0_cros-ec
181 00:23:59.523405 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:23:59.523492 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
183 00:23:59.530283 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:23:59.530398 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
185 00:23:59.530488 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:23:59.530577 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:23:59.530672 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
188 00:24:00.557033 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 00:24:00.557605 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 00:24:00.557808 extracting modules file /var/lib/lava/dispatcher/tmp/11280974/tftp-deploy-im_133ae/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11280974/extract-overlay-ramdisk-ci3deq6z/ramdisk
191 00:24:00.813858 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:24:00.814027 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 00:24:00.814154 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11280974/compress-overlay-3jwuy4jw/overlay-1.5.2.4.tar.gz to ramdisk
194 00:24:00.814258 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11280974/compress-overlay-3jwuy4jw/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11280974/extract-overlay-ramdisk-ci3deq6z/ramdisk
195 00:24:00.821342 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:24:00.821468 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 00:24:00.821589 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:24:00.821692 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 00:24:00.821776 Building ramdisk /var/lib/lava/dispatcher/tmp/11280974/extract-overlay-ramdisk-ci3deq6z/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11280974/extract-overlay-ramdisk-ci3deq6z/ramdisk
200 00:24:01.598056 >> 269673 blocks
201 00:24:06.340723 rename /var/lib/lava/dispatcher/tmp/11280974/extract-overlay-ramdisk-ci3deq6z/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11280974/tftp-deploy-im_133ae/ramdisk/ramdisk.cpio.gz
202 00:24:06.341231 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 00:24:06.341419 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 00:24:06.341545 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 00:24:06.341694 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11280974/tftp-deploy-im_133ae/kernel/Image'
206 00:24:19.466738 Returned 0 in 13 seconds
207 00:24:19.567419 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11280974/tftp-deploy-im_133ae/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11280974/tftp-deploy-im_133ae/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11280974/tftp-deploy-im_133ae/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11280974/tftp-deploy-im_133ae/kernel/image.itb
208 00:24:20.303416 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:24:20.303810 output: Created: Mon Aug 14 01:24:20 2023
210 00:24:20.303890 output: Image 0 (kernel-1)
211 00:24:20.303957 output: Description:
212 00:24:20.304019 output: Created: Mon Aug 14 01:24:20 2023
213 00:24:20.304080 output: Type: Kernel Image
214 00:24:20.304139 output: Compression: lzma compressed
215 00:24:20.304214 output: Data Size: 11037315 Bytes = 10778.63 KiB = 10.53 MiB
216 00:24:20.304275 output: Architecture: AArch64
217 00:24:20.304337 output: OS: Linux
218 00:24:20.304394 output: Load Address: 0x00000000
219 00:24:20.304451 output: Entry Point: 0x00000000
220 00:24:20.304509 output: Hash algo: crc32
221 00:24:20.304563 output: Hash value: e7f77b4c
222 00:24:20.304616 output: Image 1 (fdt-1)
223 00:24:20.304669 output: Description: mt8192-asurada-spherion-r0
224 00:24:20.304724 output: Created: Mon Aug 14 01:24:20 2023
225 00:24:20.304777 output: Type: Flat Device Tree
226 00:24:20.304830 output: Compression: uncompressed
227 00:24:20.304882 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 00:24:20.304934 output: Architecture: AArch64
229 00:24:20.304987 output: Hash algo: crc32
230 00:24:20.305040 output: Hash value: cc4352de
231 00:24:20.305092 output: Image 2 (ramdisk-1)
232 00:24:20.305144 output: Description: unavailable
233 00:24:20.305196 output: Created: Mon Aug 14 01:24:20 2023
234 00:24:20.305249 output: Type: RAMDisk Image
235 00:24:20.305301 output: Compression: Unknown Compression
236 00:24:20.305354 output: Data Size: 47396437 Bytes = 46285.58 KiB = 45.20 MiB
237 00:24:20.305406 output: Architecture: AArch64
238 00:24:20.305476 output: OS: Linux
239 00:24:20.305644 output: Load Address: unavailable
240 00:24:20.305751 output: Entry Point: unavailable
241 00:24:20.305814 output: Hash algo: crc32
242 00:24:20.305869 output: Hash value: f437d7e2
243 00:24:20.305923 output: Default Configuration: 'conf-1'
244 00:24:20.305976 output: Configuration 0 (conf-1)
245 00:24:20.306030 output: Description: mt8192-asurada-spherion-r0
246 00:24:20.306083 output: Kernel: kernel-1
247 00:24:20.306136 output: Init Ramdisk: ramdisk-1
248 00:24:20.306188 output: FDT: fdt-1
249 00:24:20.306240 output: Loadables: kernel-1
250 00:24:20.306293 output:
251 00:24:20.306491 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 00:24:20.306594 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 00:24:20.306707 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 00:24:20.306802 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 00:24:20.306876 No LXC device requested
256 00:24:20.306955 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:24:20.307044 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 00:24:20.307123 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:24:20.307191 Checking files for TFTP limit of 4294967296 bytes.
260 00:24:20.307731 end: 1 tftp-deploy (duration 00:00:23) [common]
261 00:24:20.307837 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:24:20.307928 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:24:20.308050 substitutions:
264 00:24:20.308118 - {DTB}: 11280974/tftp-deploy-im_133ae/dtb/mt8192-asurada-spherion-r0.dtb
265 00:24:20.308183 - {INITRD}: 11280974/tftp-deploy-im_133ae/ramdisk/ramdisk.cpio.gz
266 00:24:20.308242 - {KERNEL}: 11280974/tftp-deploy-im_133ae/kernel/Image
267 00:24:20.308300 - {LAVA_MAC}: None
268 00:24:20.308357 - {PRESEED_CONFIG}: None
269 00:24:20.308412 - {PRESEED_LOCAL}: None
270 00:24:20.308466 - {RAMDISK}: 11280974/tftp-deploy-im_133ae/ramdisk/ramdisk.cpio.gz
271 00:24:20.308521 - {ROOT_PART}: None
272 00:24:20.308576 - {ROOT}: None
273 00:24:20.308629 - {SERVER_IP}: 192.168.201.1
274 00:24:20.308682 - {TEE}: None
275 00:24:20.308736 Parsed boot commands:
276 00:24:20.308790 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:24:20.308966 Parsed boot commands: tftpboot 192.168.201.1 11280974/tftp-deploy-im_133ae/kernel/image.itb 11280974/tftp-deploy-im_133ae/kernel/cmdline
278 00:24:20.309056 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:24:20.309141 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:24:20.309234 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:24:20.309318 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:24:20.309390 Not connected, no need to disconnect.
283 00:24:20.309465 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:24:20.309546 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:24:20.309614 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 00:24:20.313632 Setting prompt string to ['lava-test: # ']
287 00:24:20.313992 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:24:20.314103 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:24:20.314199 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:24:20.314291 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:24:20.314513 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 00:24:25.449532 >> Command sent successfully.
293 00:24:25.452013 Returned 0 in 5 seconds
294 00:24:25.552377 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 00:24:25.553101 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 00:24:25.553283 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 00:24:25.553377 Setting prompt string to 'Starting depthcharge on Spherion...'
299 00:24:25.553447 Changing prompt to 'Starting depthcharge on Spherion...'
300 00:24:25.553516 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 00:24:25.553836 [Enter `^Ec?' for help]
302 00:24:25.725252
303 00:24:25.725401
304 00:24:25.725476 F0: 102B 0000
305 00:24:25.725541
306 00:24:25.725600 F3: 1001 0000 [0200]
307 00:24:25.728832
308 00:24:25.728914 F3: 1001 0000
309 00:24:25.728980
310 00:24:25.729039 F7: 102D 0000
311 00:24:25.729097
312 00:24:25.732336 F1: 0000 0000
313 00:24:25.732419
314 00:24:25.732484 V0: 0000 0000 [0001]
315 00:24:25.732547
316 00:24:25.735983 00: 0007 8000
317 00:24:25.736069
318 00:24:25.736133 01: 0000 0000
319 00:24:25.736194
320 00:24:25.738517 BP: 0C00 0209 [0000]
321 00:24:25.738598
322 00:24:25.738663 G0: 1182 0000
323 00:24:25.738723
324 00:24:25.742509 EC: 0000 0021 [4000]
325 00:24:25.742590
326 00:24:25.742655 S7: 0000 0000 [0000]
327 00:24:25.742715
328 00:24:25.745917 CC: 0000 0000 [0001]
329 00:24:25.745998
330 00:24:25.746062 T0: 0000 0040 [010F]
331 00:24:25.746122
332 00:24:25.746179 Jump to BL
333 00:24:25.748735
334 00:24:25.772432
335 00:24:25.772520
336 00:24:25.772585
337 00:24:25.779158 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 00:24:25.783243 ARM64: Exception handlers installed.
339 00:24:25.786744 ARM64: Testing exception
340 00:24:25.790063 ARM64: Done test exception
341 00:24:25.796891 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 00:24:25.806726 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 00:24:25.813686 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 00:24:25.823881 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 00:24:25.830435 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 00:24:25.837054 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 00:24:25.849447 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 00:24:25.856021 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 00:24:25.875134 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 00:24:25.878634 WDT: Last reset was cold boot
351 00:24:25.882147 SPI1(PAD0) initialized at 2873684 Hz
352 00:24:25.885080 SPI5(PAD0) initialized at 992727 Hz
353 00:24:25.888509 VBOOT: Loading verstage.
354 00:24:25.895595 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 00:24:25.899092 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 00:24:25.901950 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 00:24:25.904862 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 00:24:25.912601 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 00:24:25.919400 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 00:24:25.930651 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 00:24:25.930803
362 00:24:25.930924
363 00:24:25.940428 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 00:24:25.943663 ARM64: Exception handlers installed.
365 00:24:25.947112 ARM64: Testing exception
366 00:24:25.947215 ARM64: Done test exception
367 00:24:25.954927 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 00:24:25.958175 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 00:24:25.971313 Probing TPM: . done!
370 00:24:25.971441 TPM ready after 0 ms
371 00:24:25.978087 Connected to device vid:did:rid of 1ae0:0028:00
372 00:24:26.207009 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 00:24:26.207157 Initialized TPM device CR50 revision 0
374 00:24:26.210834 tlcl_send_startup: Startup return code is 0
375 00:24:26.218767 TPM: setup succeeded
376 00:24:26.233938 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 00:24:26.241577 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 00:24:26.253095 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 00:24:26.263155 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 00:24:26.266883 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 00:24:26.270046 in-header: 03 07 00 00 08 00 00 00
382 00:24:26.273312 in-data: aa e4 47 04 13 02 00 00
383 00:24:26.276679 Chrome EC: UHEPI supported
384 00:24:26.283578 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 00:24:26.287187 in-header: 03 95 00 00 08 00 00 00
386 00:24:26.290021 in-data: 18 20 20 08 00 00 00 00
387 00:24:26.290105 Phase 1
388 00:24:26.293673 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 00:24:26.300037 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 00:24:26.306922 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 00:24:26.307005 Recovery requested (1009000e)
392 00:24:26.316313 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 00:24:26.321331 tlcl_extend: response is 0
394 00:24:26.331043 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 00:24:26.337130 tlcl_extend: response is 0
396 00:24:26.343895 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 00:24:26.363220 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 00:24:26.370680 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 00:24:26.370782
400 00:24:26.370878
401 00:24:26.380922 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 00:24:26.384291 ARM64: Exception handlers installed.
403 00:24:26.384374 ARM64: Testing exception
404 00:24:26.387597 ARM64: Done test exception
405 00:24:26.409263 pmic_efuse_setting: Set efuses in 11 msecs
406 00:24:26.413202 pmwrap_interface_init: Select PMIF_VLD_RDY
407 00:24:26.419704 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 00:24:26.422954 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 00:24:26.426212 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 00:24:26.433200 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 00:24:26.436257 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 00:24:26.443115 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 00:24:26.446582 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 00:24:26.452636 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 00:24:26.455958 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 00:24:26.459633 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 00:24:26.466408 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 00:24:26.469580 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 00:24:26.476205 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 00:24:26.479565 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 00:24:26.486620 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 00:24:26.492752 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 00:24:26.500046 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 00:24:26.503326 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 00:24:26.509468 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 00:24:26.516034 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 00:24:26.519847 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 00:24:26.526232 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 00:24:26.533096 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 00:24:26.536015 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 00:24:26.542823 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 00:24:26.549313 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 00:24:26.552756 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 00:24:26.559699 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 00:24:26.563034 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 00:24:26.566055 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 00:24:26.572941 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 00:24:26.576105 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 00:24:26.583147 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 00:24:26.586504 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 00:24:26.593021 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 00:24:26.596546 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 00:24:26.602720 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 00:24:26.606198 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 00:24:26.613959 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 00:24:26.617134 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 00:24:26.620165 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 00:24:26.626995 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 00:24:26.630229 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 00:24:26.633964 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 00:24:26.637563 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 00:24:26.645104 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 00:24:26.648278 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 00:24:26.652244 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 00:24:26.656092 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 00:24:26.659122 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 00:24:26.662199 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 00:24:26.672509 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 00:24:26.680019 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 00:24:26.683763 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 00:24:26.693394 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 00:24:26.700172 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 00:24:26.706847 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 00:24:26.710720 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:24:26.714209 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 00:24:26.722109 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x10
467 00:24:26.726042 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 00:24:26.733971 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 00:24:26.737645 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 00:24:26.746962 [RTC]rtc_get_frequency_meter,154: input=15, output=794
471 00:24:26.750195 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 00:24:26.753830 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 00:24:26.761360 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 00:24:26.765537 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 00:24:26.769070 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 00:24:26.769167 ADC[4]: Raw value=894821 ID=7
477 00:24:26.772807 ADC[3]: Raw value=213070 ID=1
478 00:24:26.772890 RAM Code: 0x71
479 00:24:26.780203 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 00:24:26.783850 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 00:24:26.791140 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 00:24:26.798307 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 00:24:26.801928 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 00:24:26.805023 in-header: 03 07 00 00 08 00 00 00
485 00:24:26.808323 in-data: aa e4 47 04 13 02 00 00
486 00:24:26.811869 Chrome EC: UHEPI supported
487 00:24:26.818440 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 00:24:26.822138 in-header: 03 d5 00 00 08 00 00 00
489 00:24:26.825198 in-data: 98 20 60 08 00 00 00 00
490 00:24:26.828468 MRC: failed to locate region type 0.
491 00:24:26.835392 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 00:24:26.838445 DRAM-K: Running full calibration
493 00:24:26.844941 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 00:24:26.845040 header.status = 0x0
495 00:24:26.848610 header.version = 0x6 (expected: 0x6)
496 00:24:26.852055 header.size = 0xd00 (expected: 0xd00)
497 00:24:26.855227 header.flags = 0x0
498 00:24:26.861876 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 00:24:26.878067 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
500 00:24:26.884717 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 00:24:26.888088 dram_init: ddr_geometry: 2
502 00:24:26.891489 [EMI] MDL number = 2
503 00:24:26.891576 [EMI] Get MDL freq = 0
504 00:24:26.894812 dram_init: ddr_type: 0
505 00:24:26.894898 is_discrete_lpddr4: 1
506 00:24:26.898206 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 00:24:26.898293
508 00:24:26.898380
509 00:24:26.901863 [Bian_co] ETT version 0.0.0.1
510 00:24:26.908227 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 00:24:26.908320
512 00:24:26.911569 dramc_set_vcore_voltage set vcore to 650000
513 00:24:26.911688 Read voltage for 800, 4
514 00:24:26.915248 Vio18 = 0
515 00:24:26.915383 Vcore = 650000
516 00:24:26.915484 Vdram = 0
517 00:24:26.918303 Vddq = 0
518 00:24:26.918441 Vmddr = 0
519 00:24:26.921764 dram_init: config_dvfs: 1
520 00:24:26.925087 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 00:24:26.931628 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 00:24:26.935102 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 00:24:26.938736 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 00:24:26.941816 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 00:24:26.945004 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 00:24:26.948365 MEM_TYPE=3, freq_sel=18
527 00:24:26.952084 sv_algorithm_assistance_LP4_1600
528 00:24:26.955204 ============ PULL DRAM RESETB DOWN ============
529 00:24:26.958584 ========== PULL DRAM RESETB DOWN end =========
530 00:24:26.965135 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 00:24:26.968647 ===================================
532 00:24:26.969094 LPDDR4 DRAM CONFIGURATION
533 00:24:26.972117 ===================================
534 00:24:26.975708 EX_ROW_EN[0] = 0x0
535 00:24:26.978858 EX_ROW_EN[1] = 0x0
536 00:24:26.979286 LP4Y_EN = 0x0
537 00:24:26.982696 WORK_FSP = 0x0
538 00:24:26.983125 WL = 0x2
539 00:24:26.983528 RL = 0x2
540 00:24:26.986348 BL = 0x2
541 00:24:26.986776 RPST = 0x0
542 00:24:26.990627 RD_PRE = 0x0
543 00:24:26.991058 WR_PRE = 0x1
544 00:24:26.994242 WR_PST = 0x0
545 00:24:26.994672 DBI_WR = 0x0
546 00:24:26.997558 DBI_RD = 0x0
547 00:24:26.998139 OTF = 0x1
548 00:24:27.001618 ===================================
549 00:24:27.004894 ===================================
550 00:24:27.005323 ANA top config
551 00:24:27.008837 ===================================
552 00:24:27.012743 DLL_ASYNC_EN = 0
553 00:24:27.016487 ALL_SLAVE_EN = 1
554 00:24:27.016916 NEW_RANK_MODE = 1
555 00:24:27.020558 DLL_IDLE_MODE = 1
556 00:24:27.023851 LP45_APHY_COMB_EN = 1
557 00:24:27.024296 TX_ODT_DIS = 1
558 00:24:27.027009 NEW_8X_MODE = 1
559 00:24:27.030547 ===================================
560 00:24:27.033875 ===================================
561 00:24:27.037066 data_rate = 1600
562 00:24:27.041136 CKR = 1
563 00:24:27.041219 DQ_P2S_RATIO = 8
564 00:24:27.044654 ===================================
565 00:24:27.048153 CA_P2S_RATIO = 8
566 00:24:27.051500 DQ_CA_OPEN = 0
567 00:24:27.055096 DQ_SEMI_OPEN = 0
568 00:24:27.055180 CA_SEMI_OPEN = 0
569 00:24:27.058673 CA_FULL_RATE = 0
570 00:24:27.062533 DQ_CKDIV4_EN = 1
571 00:24:27.066359 CA_CKDIV4_EN = 1
572 00:24:27.066441 CA_PREDIV_EN = 0
573 00:24:27.069563 PH8_DLY = 0
574 00:24:27.073278 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 00:24:27.076567 DQ_AAMCK_DIV = 4
576 00:24:27.080146 CA_AAMCK_DIV = 4
577 00:24:27.080230 CA_ADMCK_DIV = 4
578 00:24:27.084046 DQ_TRACK_CA_EN = 0
579 00:24:27.086955 CA_PICK = 800
580 00:24:27.090853 CA_MCKIO = 800
581 00:24:27.094407 MCKIO_SEMI = 0
582 00:24:27.094490 PLL_FREQ = 3068
583 00:24:27.098101 DQ_UI_PI_RATIO = 32
584 00:24:27.101923 CA_UI_PI_RATIO = 0
585 00:24:27.105698 ===================================
586 00:24:27.109675 ===================================
587 00:24:27.109759 memory_type:LPDDR4
588 00:24:27.113027 GP_NUM : 10
589 00:24:27.113110 SRAM_EN : 1
590 00:24:27.117011 MD32_EN : 0
591 00:24:27.120417 ===================================
592 00:24:27.120501 [ANA_INIT] >>>>>>>>>>>>>>
593 00:24:27.124229 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 00:24:27.127589 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 00:24:27.131771 ===================================
596 00:24:27.135698 data_rate = 1600,PCW = 0X7600
597 00:24:27.139304 ===================================
598 00:24:27.142817 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 00:24:27.146472 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 00:24:27.153694 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 00:24:27.157542 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 00:24:27.160917 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 00:24:27.164783 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 00:24:27.164881 [ANA_INIT] flow start
605 00:24:27.168905 [ANA_INIT] PLL >>>>>>>>
606 00:24:27.168991 [ANA_INIT] PLL <<<<<<<<
607 00:24:27.172398 [ANA_INIT] MIDPI >>>>>>>>
608 00:24:27.176266 [ANA_INIT] MIDPI <<<<<<<<
609 00:24:27.176378 [ANA_INIT] DLL >>>>>>>>
610 00:24:27.179842 [ANA_INIT] flow end
611 00:24:27.183559 ============ LP4 DIFF to SE enter ============
612 00:24:27.187685 ============ LP4 DIFF to SE exit ============
613 00:24:27.191286 [ANA_INIT] <<<<<<<<<<<<<
614 00:24:27.194641 [Flow] Enable top DCM control >>>>>
615 00:24:27.194725 [Flow] Enable top DCM control <<<<<
616 00:24:27.198754 Enable DLL master slave shuffle
617 00:24:27.206400 ==============================================================
618 00:24:27.206485 Gating Mode config
619 00:24:27.213638 ==============================================================
620 00:24:27.213723 Config description:
621 00:24:27.224684 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 00:24:27.231377 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 00:24:27.235618 SELPH_MODE 0: By rank 1: By Phase
624 00:24:27.239162 ==============================================================
625 00:24:27.242476 GAT_TRACK_EN = 1
626 00:24:27.246242 RX_GATING_MODE = 2
627 00:24:27.249554 RX_GATING_TRACK_MODE = 2
628 00:24:27.253582 SELPH_MODE = 1
629 00:24:27.257695 PICG_EARLY_EN = 1
630 00:24:27.257778 VALID_LAT_VALUE = 1
631 00:24:27.264973 ==============================================================
632 00:24:27.268578 Enter into Gating configuration >>>>
633 00:24:27.273102 Exit from Gating configuration <<<<
634 00:24:27.273186 Enter into DVFS_PRE_config >>>>>
635 00:24:27.283920 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 00:24:27.287067 Exit from DVFS_PRE_config <<<<<
637 00:24:27.290829 Enter into PICG configuration >>>>
638 00:24:27.294417 Exit from PICG configuration <<<<
639 00:24:27.298089 [RX_INPUT] configuration >>>>>
640 00:24:27.298184 [RX_INPUT] configuration <<<<<
641 00:24:27.305999 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 00:24:27.309701 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 00:24:27.317206 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 00:24:27.324266 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 00:24:27.327936 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 00:24:27.335789 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 00:24:27.339496 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 00:24:27.342596 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 00:24:27.345471 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 00:24:27.351979 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 00:24:27.355532 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 00:24:27.359053 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 00:24:27.362476 ===================================
654 00:24:27.365628 LPDDR4 DRAM CONFIGURATION
655 00:24:27.369149 ===================================
656 00:24:27.372170 EX_ROW_EN[0] = 0x0
657 00:24:27.372255 EX_ROW_EN[1] = 0x0
658 00:24:27.375568 LP4Y_EN = 0x0
659 00:24:27.375653 WORK_FSP = 0x0
660 00:24:27.378634 WL = 0x2
661 00:24:27.378719 RL = 0x2
662 00:24:27.382158 BL = 0x2
663 00:24:27.382243 RPST = 0x0
664 00:24:27.385915 RD_PRE = 0x0
665 00:24:27.386000 WR_PRE = 0x1
666 00:24:27.389011 WR_PST = 0x0
667 00:24:27.389096 DBI_WR = 0x0
668 00:24:27.392458 DBI_RD = 0x0
669 00:24:27.392543 OTF = 0x1
670 00:24:27.395367 ===================================
671 00:24:27.402167 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 00:24:27.405590 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 00:24:27.408504 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 00:24:27.411969 ===================================
675 00:24:27.416080 LPDDR4 DRAM CONFIGURATION
676 00:24:27.418903 ===================================
677 00:24:27.418986 EX_ROW_EN[0] = 0x10
678 00:24:27.422483 EX_ROW_EN[1] = 0x0
679 00:24:27.425510 LP4Y_EN = 0x0
680 00:24:27.425613 WORK_FSP = 0x0
681 00:24:27.428988 WL = 0x2
682 00:24:27.429076 RL = 0x2
683 00:24:27.431874 BL = 0x2
684 00:24:27.431984 RPST = 0x0
685 00:24:27.435570 RD_PRE = 0x0
686 00:24:27.435680 WR_PRE = 0x1
687 00:24:27.438784 WR_PST = 0x0
688 00:24:27.438892 DBI_WR = 0x0
689 00:24:27.442227 DBI_RD = 0x0
690 00:24:27.442311 OTF = 0x1
691 00:24:27.445485 ===================================
692 00:24:27.452074 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 00:24:27.456709 nWR fixed to 40
694 00:24:27.459793 [ModeRegInit_LP4] CH0 RK0
695 00:24:27.459895 [ModeRegInit_LP4] CH0 RK1
696 00:24:27.462970 [ModeRegInit_LP4] CH1 RK0
697 00:24:27.466537 [ModeRegInit_LP4] CH1 RK1
698 00:24:27.466619 match AC timing 13
699 00:24:27.472818 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 00:24:27.476304 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 00:24:27.479754 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 00:24:27.486535 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 00:24:27.489489 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 00:24:27.489598 [EMI DOE] emi_dcm 0
705 00:24:27.496659 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 00:24:27.496741 ==
707 00:24:27.499593 Dram Type= 6, Freq= 0, CH_0, rank 0
708 00:24:27.503041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 00:24:27.503149 ==
710 00:24:27.510016 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 00:24:27.516340 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 00:24:27.523606 [CA 0] Center 38 (7~69) winsize 63
713 00:24:27.526984 [CA 1] Center 37 (7~68) winsize 62
714 00:24:27.530284 [CA 2] Center 35 (5~66) winsize 62
715 00:24:27.534106 [CA 3] Center 35 (5~65) winsize 61
716 00:24:27.537059 [CA 4] Center 34 (4~65) winsize 62
717 00:24:27.540371 [CA 5] Center 34 (4~65) winsize 62
718 00:24:27.540496
719 00:24:27.544194 [CmdBusTrainingLP45] Vref(ca) range 1: 30
720 00:24:27.544275
721 00:24:27.546981 [CATrainingPosCal] consider 1 rank data
722 00:24:27.550340 u2DelayCellTimex100 = 270/100 ps
723 00:24:27.553649 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 00:24:27.556899 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 00:24:27.564092 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 00:24:27.567685 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
727 00:24:27.571985 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 00:24:27.572068 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
729 00:24:27.572133
730 00:24:27.579025 CA PerBit enable=1, Macro0, CA PI delay=34
731 00:24:27.579138
732 00:24:27.579233 [CBTSetCACLKResult] CA Dly = 34
733 00:24:27.582447 CS Dly: 6 (0~37)
734 00:24:27.582530 ==
735 00:24:27.585758 Dram Type= 6, Freq= 0, CH_0, rank 1
736 00:24:27.589392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 00:24:27.589474 ==
738 00:24:27.596418 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 00:24:27.599927 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 00:24:27.610259 [CA 0] Center 37 (7~68) winsize 62
741 00:24:27.613344 [CA 1] Center 38 (7~69) winsize 63
742 00:24:27.616792 [CA 2] Center 35 (5~66) winsize 62
743 00:24:27.620419 [CA 3] Center 35 (5~66) winsize 62
744 00:24:27.623699 [CA 4] Center 34 (4~65) winsize 62
745 00:24:27.627331 [CA 5] Center 34 (4~65) winsize 62
746 00:24:27.627424
747 00:24:27.630261 [CmdBusTrainingLP45] Vref(ca) range 1: 32
748 00:24:27.630344
749 00:24:27.633427 [CATrainingPosCal] consider 2 rank data
750 00:24:27.636518 u2DelayCellTimex100 = 270/100 ps
751 00:24:27.639936 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
752 00:24:27.644125 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 00:24:27.649977 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 00:24:27.653530 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
755 00:24:27.656525 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 00:24:27.660173 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
757 00:24:27.660256
758 00:24:27.663123 CA PerBit enable=1, Macro0, CA PI delay=34
759 00:24:27.663205
760 00:24:27.666525 [CBTSetCACLKResult] CA Dly = 34
761 00:24:27.666607 CS Dly: 6 (0~37)
762 00:24:27.666672
763 00:24:27.670102 ----->DramcWriteLeveling(PI) begin...
764 00:24:27.673472 ==
765 00:24:27.676859 Dram Type= 6, Freq= 0, CH_0, rank 0
766 00:24:27.679884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 00:24:27.679967 ==
768 00:24:27.683957 Write leveling (Byte 0): 33 => 33
769 00:24:27.686693 Write leveling (Byte 1): 31 => 31
770 00:24:27.690119 DramcWriteLeveling(PI) end<-----
771 00:24:27.690201
772 00:24:27.690266 ==
773 00:24:27.693128 Dram Type= 6, Freq= 0, CH_0, rank 0
774 00:24:27.696757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 00:24:27.696840 ==
776 00:24:27.700371 [Gating] SW mode calibration
777 00:24:27.706420 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 00:24:27.709947 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 00:24:27.716670 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 00:24:27.719997 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 00:24:27.723397 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
782 00:24:27.730357 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
783 00:24:27.733070 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 00:24:27.736506 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 00:24:27.743805 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 00:24:27.746755 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 00:24:27.750064 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 00:24:27.756618 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 00:24:27.760195 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:24:27.763630 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:24:27.770177 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:24:27.773510 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:24:27.776474 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:24:27.783177 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 00:24:27.786447 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 00:24:27.789813 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 00:24:27.796802 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
798 00:24:27.800016 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
799 00:24:27.803338 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:24:27.806700 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:24:27.813650 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:24:27.816514 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 00:24:27.820076 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 00:24:27.826579 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 00:24:27.829698 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
806 00:24:27.833083 0 9 12 | B1->B0 | 2c2c 2f2f | 1 1 | (1 1) (1 1)
807 00:24:27.840024 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 00:24:27.843008 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 00:24:27.846607 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 00:24:27.853258 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 00:24:27.856314 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 00:24:27.859949 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 00:24:27.866561 0 10 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
814 00:24:27.869635 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
815 00:24:27.872973 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 00:24:27.880067 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 00:24:27.883205 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 00:24:27.886263 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 00:24:27.892968 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 00:24:27.896856 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 00:24:27.899491 0 11 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
822 00:24:27.906400 0 11 12 | B1->B0 | 3030 3c3c | 0 0 | (0 0) (1 1)
823 00:24:27.909789 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 00:24:27.913014 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 00:24:27.916417 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 00:24:27.923066 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 00:24:27.926644 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 00:24:27.930053 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 00:24:27.936428 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 00:24:27.939834 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 00:24:27.943516 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 00:24:27.949798 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 00:24:27.953269 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 00:24:27.956745 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 00:24:27.963445 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 00:24:27.966468 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 00:24:27.969750 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 00:24:27.974035 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 00:24:27.981381 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 00:24:27.984233 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 00:24:27.987691 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:24:27.994439 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:24:27.997217 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:24:28.000678 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
845 00:24:28.007499 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 00:24:28.010606 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 00:24:28.014536 Total UI for P1: 0, mck2ui 16
848 00:24:28.017347 best dqsien dly found for B0: ( 0, 14, 10)
849 00:24:28.020708 Total UI for P1: 0, mck2ui 16
850 00:24:28.024010 best dqsien dly found for B1: ( 0, 14, 10)
851 00:24:28.027365 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
852 00:24:28.030858 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
853 00:24:28.030940
854 00:24:28.034125 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
855 00:24:28.037818 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
856 00:24:28.040760 [Gating] SW calibration Done
857 00:24:28.040842 ==
858 00:24:28.044544 Dram Type= 6, Freq= 0, CH_0, rank 0
859 00:24:28.047864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
860 00:24:28.047949 ==
861 00:24:28.050621 RX Vref Scan: 0
862 00:24:28.050703
863 00:24:28.054046 RX Vref 0 -> 0, step: 1
864 00:24:28.054128
865 00:24:28.054193 RX Delay -130 -> 252, step: 16
866 00:24:28.060613 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
867 00:24:28.064270 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
868 00:24:28.067491 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
869 00:24:28.070800 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
870 00:24:28.073778 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
871 00:24:28.080850 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
872 00:24:28.084038 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
873 00:24:28.087812 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
874 00:24:28.090423 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
875 00:24:28.093945 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
876 00:24:28.100967 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
877 00:24:28.103733 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
878 00:24:28.107453 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
879 00:24:28.110685 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
880 00:24:28.114071 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
881 00:24:28.120935 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
882 00:24:28.121017 ==
883 00:24:28.123895 Dram Type= 6, Freq= 0, CH_0, rank 0
884 00:24:28.127301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
885 00:24:28.127389 ==
886 00:24:28.127454 DQS Delay:
887 00:24:28.130698 DQS0 = 0, DQS1 = 0
888 00:24:28.130779 DQM Delay:
889 00:24:28.134101 DQM0 = 82, DQM1 = 70
890 00:24:28.134183 DQ Delay:
891 00:24:28.137457 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
892 00:24:28.141016 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
893 00:24:28.143891 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
894 00:24:28.147492 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
895 00:24:28.147574
896 00:24:28.147638
897 00:24:28.147699 ==
898 00:24:28.151012 Dram Type= 6, Freq= 0, CH_0, rank 0
899 00:24:28.154003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 00:24:28.154103 ==
901 00:24:28.154170
902 00:24:28.157572
903 00:24:28.157654 TX Vref Scan disable
904 00:24:28.160885 == TX Byte 0 ==
905 00:24:28.163848 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
906 00:24:28.167246 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
907 00:24:28.170772 == TX Byte 1 ==
908 00:24:28.174124 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
909 00:24:28.177639 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
910 00:24:28.177721 ==
911 00:24:28.180502 Dram Type= 6, Freq= 0, CH_0, rank 0
912 00:24:28.187325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 00:24:28.187449 ==
914 00:24:28.199160 TX Vref=22, minBit 10, minWin=26, winSum=433
915 00:24:28.202556 TX Vref=24, minBit 8, minWin=26, winSum=434
916 00:24:28.205895 TX Vref=26, minBit 0, minWin=27, winSum=441
917 00:24:28.209266 TX Vref=28, minBit 0, minWin=27, winSum=440
918 00:24:28.213037 TX Vref=30, minBit 12, minWin=26, winSum=440
919 00:24:28.219054 TX Vref=32, minBit 9, minWin=26, winSum=436
920 00:24:28.222628 [TxChooseVref] Worse bit 0, Min win 27, Win sum 441, Final Vref 26
921 00:24:28.222710
922 00:24:28.225740 Final TX Range 1 Vref 26
923 00:24:28.225822
924 00:24:28.225887 ==
925 00:24:28.229467 Dram Type= 6, Freq= 0, CH_0, rank 0
926 00:24:28.233074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 00:24:28.233156 ==
928 00:24:28.233221
929 00:24:28.233280
930 00:24:28.237220 TX Vref Scan disable
931 00:24:28.240271 == TX Byte 0 ==
932 00:24:28.244170 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
933 00:24:28.247750 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
934 00:24:28.247832 == TX Byte 1 ==
935 00:24:28.255160 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
936 00:24:28.259023 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
937 00:24:28.259107
938 00:24:28.259173 [DATLAT]
939 00:24:28.259234 Freq=800, CH0 RK0
940 00:24:28.259293
941 00:24:28.262358 DATLAT Default: 0xa
942 00:24:28.262441 0, 0xFFFF, sum = 0
943 00:24:28.265780 1, 0xFFFF, sum = 0
944 00:24:28.265867 2, 0xFFFF, sum = 0
945 00:24:28.269104 3, 0xFFFF, sum = 0
946 00:24:28.269188 4, 0xFFFF, sum = 0
947 00:24:28.272374 5, 0xFFFF, sum = 0
948 00:24:28.276246 6, 0xFFFF, sum = 0
949 00:24:28.276330 7, 0xFFFF, sum = 0
950 00:24:28.279197 8, 0xFFFF, sum = 0
951 00:24:28.279319 9, 0x0, sum = 1
952 00:24:28.279446 10, 0x0, sum = 2
953 00:24:28.282867 11, 0x0, sum = 3
954 00:24:28.282951 12, 0x0, sum = 4
955 00:24:28.285748 best_step = 10
956 00:24:28.285830
957 00:24:28.285895 ==
958 00:24:28.289275 Dram Type= 6, Freq= 0, CH_0, rank 0
959 00:24:28.292570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 00:24:28.292653 ==
961 00:24:28.296005 RX Vref Scan: 1
962 00:24:28.296087
963 00:24:28.296154 Set Vref Range= 32 -> 127
964 00:24:28.296216
965 00:24:28.299261 RX Vref 32 -> 127, step: 1
966 00:24:28.299392
967 00:24:28.302370 RX Delay -111 -> 252, step: 8
968 00:24:28.302452
969 00:24:28.305697 Set Vref, RX VrefLevel [Byte0]: 32
970 00:24:28.309355 [Byte1]: 32
971 00:24:28.309437
972 00:24:28.312719 Set Vref, RX VrefLevel [Byte0]: 33
973 00:24:28.316243 [Byte1]: 33
974 00:24:28.319642
975 00:24:28.319724 Set Vref, RX VrefLevel [Byte0]: 34
976 00:24:28.323126 [Byte1]: 34
977 00:24:28.327302
978 00:24:28.327391 Set Vref, RX VrefLevel [Byte0]: 35
979 00:24:28.330701 [Byte1]: 35
980 00:24:28.335186
981 00:24:28.335268 Set Vref, RX VrefLevel [Byte0]: 36
982 00:24:28.338177 [Byte1]: 36
983 00:24:28.342722
984 00:24:28.342804 Set Vref, RX VrefLevel [Byte0]: 37
985 00:24:28.346176 [Byte1]: 37
986 00:24:28.350414
987 00:24:28.350496 Set Vref, RX VrefLevel [Byte0]: 38
988 00:24:28.353445 [Byte1]: 38
989 00:24:28.357972
990 00:24:28.358053 Set Vref, RX VrefLevel [Byte0]: 39
991 00:24:28.364295 [Byte1]: 39
992 00:24:28.364377
993 00:24:28.367998 Set Vref, RX VrefLevel [Byte0]: 40
994 00:24:28.371344 [Byte1]: 40
995 00:24:28.371468
996 00:24:28.374692 Set Vref, RX VrefLevel [Byte0]: 41
997 00:24:28.377536 [Byte1]: 41
998 00:24:28.377619
999 00:24:28.380928 Set Vref, RX VrefLevel [Byte0]: 42
1000 00:24:28.384255 [Byte1]: 42
1001 00:24:28.388572
1002 00:24:28.388654 Set Vref, RX VrefLevel [Byte0]: 43
1003 00:24:28.391660 [Byte1]: 43
1004 00:24:28.396204
1005 00:24:28.396286 Set Vref, RX VrefLevel [Byte0]: 44
1006 00:24:28.399563 [Byte1]: 44
1007 00:24:28.403749
1008 00:24:28.403832 Set Vref, RX VrefLevel [Byte0]: 45
1009 00:24:28.407447 [Byte1]: 45
1010 00:24:28.411568
1011 00:24:28.411649 Set Vref, RX VrefLevel [Byte0]: 46
1012 00:24:28.414711 [Byte1]: 46
1013 00:24:28.419017
1014 00:24:28.419099 Set Vref, RX VrefLevel [Byte0]: 47
1015 00:24:28.422197 [Byte1]: 47
1016 00:24:28.426811
1017 00:24:28.426894 Set Vref, RX VrefLevel [Byte0]: 48
1018 00:24:28.430070 [Byte1]: 48
1019 00:24:28.434572
1020 00:24:28.434654 Set Vref, RX VrefLevel [Byte0]: 49
1021 00:24:28.437913 [Byte1]: 49
1022 00:24:28.441981
1023 00:24:28.442062 Set Vref, RX VrefLevel [Byte0]: 50
1024 00:24:28.445409 [Byte1]: 50
1025 00:24:28.450089
1026 00:24:28.450170 Set Vref, RX VrefLevel [Byte0]: 51
1027 00:24:28.452883 [Byte1]: 51
1028 00:24:28.457431
1029 00:24:28.457512 Set Vref, RX VrefLevel [Byte0]: 52
1030 00:24:28.460654 [Byte1]: 52
1031 00:24:28.464767
1032 00:24:28.464847 Set Vref, RX VrefLevel [Byte0]: 53
1033 00:24:28.468202 [Byte1]: 53
1034 00:24:28.472632
1035 00:24:28.472713 Set Vref, RX VrefLevel [Byte0]: 54
1036 00:24:28.475768 [Byte1]: 54
1037 00:24:28.480073
1038 00:24:28.480154 Set Vref, RX VrefLevel [Byte0]: 55
1039 00:24:28.483844 [Byte1]: 55
1040 00:24:28.488017
1041 00:24:28.488097 Set Vref, RX VrefLevel [Byte0]: 56
1042 00:24:28.491178 [Byte1]: 56
1043 00:24:28.495801
1044 00:24:28.495882 Set Vref, RX VrefLevel [Byte0]: 57
1045 00:24:28.499087 [Byte1]: 57
1046 00:24:28.503223
1047 00:24:28.503334 Set Vref, RX VrefLevel [Byte0]: 58
1048 00:24:28.506629 [Byte1]: 58
1049 00:24:28.511150
1050 00:24:28.511257 Set Vref, RX VrefLevel [Byte0]: 59
1051 00:24:28.514232 [Byte1]: 59
1052 00:24:28.518527
1053 00:24:28.518608 Set Vref, RX VrefLevel [Byte0]: 60
1054 00:24:28.521988 [Byte1]: 60
1055 00:24:28.526446
1056 00:24:28.526527 Set Vref, RX VrefLevel [Byte0]: 61
1057 00:24:28.529361 [Byte1]: 61
1058 00:24:28.533787
1059 00:24:28.533868 Set Vref, RX VrefLevel [Byte0]: 62
1060 00:24:28.537060 [Byte1]: 62
1061 00:24:28.541548
1062 00:24:28.541628 Set Vref, RX VrefLevel [Byte0]: 63
1063 00:24:28.544789 [Byte1]: 63
1064 00:24:28.549461
1065 00:24:28.549542 Set Vref, RX VrefLevel [Byte0]: 64
1066 00:24:28.552205 [Byte1]: 64
1067 00:24:28.557045
1068 00:24:28.557126 Set Vref, RX VrefLevel [Byte0]: 65
1069 00:24:28.560210 [Byte1]: 65
1070 00:24:28.564785
1071 00:24:28.564865 Set Vref, RX VrefLevel [Byte0]: 66
1072 00:24:28.567637 [Byte1]: 66
1073 00:24:28.571890
1074 00:24:28.571972 Set Vref, RX VrefLevel [Byte0]: 67
1075 00:24:28.575262 [Byte1]: 67
1076 00:24:28.580195
1077 00:24:28.580319 Set Vref, RX VrefLevel [Byte0]: 68
1078 00:24:28.582827 [Byte1]: 68
1079 00:24:28.587526
1080 00:24:28.587607 Set Vref, RX VrefLevel [Byte0]: 69
1081 00:24:28.591170 [Byte1]: 69
1082 00:24:28.594873
1083 00:24:28.594954 Set Vref, RX VrefLevel [Byte0]: 70
1084 00:24:28.598250 [Byte1]: 70
1085 00:24:28.603009
1086 00:24:28.603090 Set Vref, RX VrefLevel [Byte0]: 71
1087 00:24:28.605753 [Byte1]: 71
1088 00:24:28.610414
1089 00:24:28.610494 Set Vref, RX VrefLevel [Byte0]: 72
1090 00:24:28.613683 [Byte1]: 72
1091 00:24:28.617902
1092 00:24:28.617982 Set Vref, RX VrefLevel [Byte0]: 73
1093 00:24:28.621054 [Byte1]: 73
1094 00:24:28.625652
1095 00:24:28.625733 Set Vref, RX VrefLevel [Byte0]: 74
1096 00:24:28.628663 [Byte1]: 74
1097 00:24:28.633213
1098 00:24:28.633293 Set Vref, RX VrefLevel [Byte0]: 75
1099 00:24:28.636354 [Byte1]: 75
1100 00:24:28.640989
1101 00:24:28.641070 Set Vref, RX VrefLevel [Byte0]: 76
1102 00:24:28.644440 [Byte1]: 76
1103 00:24:28.648527
1104 00:24:28.648607 Set Vref, RX VrefLevel [Byte0]: 77
1105 00:24:28.699040 [Byte1]: 77
1106 00:24:28.699133
1107 00:24:28.699199 Set Vref, RX VrefLevel [Byte0]: 78
1108 00:24:28.699403 [Byte1]: 78
1109 00:24:28.699469
1110 00:24:28.699526 Set Vref, RX VrefLevel [Byte0]: 79
1111 00:24:28.700134 [Byte1]: 79
1112 00:24:28.700214
1113 00:24:28.700277 Final RX Vref Byte 0 = 58 to rank0
1114 00:24:28.700517 Final RX Vref Byte 1 = 60 to rank0
1115 00:24:28.700985 Final RX Vref Byte 0 = 58 to rank1
1116 00:24:28.701066 Final RX Vref Byte 1 = 60 to rank1==
1117 00:24:28.701310 Dram Type= 6, Freq= 0, CH_0, rank 0
1118 00:24:28.701557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1119 00:24:28.701626 ==
1120 00:24:28.701684 DQS Delay:
1121 00:24:28.701740 DQS0 = 0, DQS1 = 0
1122 00:24:28.701794 DQM Delay:
1123 00:24:28.701860 DQM0 = 82, DQM1 = 68
1124 00:24:28.701916 DQ Delay:
1125 00:24:28.701970 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1126 00:24:28.743154 DQ4 =84, DQ5 =68, DQ6 =88, DQ7 =92
1127 00:24:28.743731 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1128 00:24:28.743814 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1129 00:24:28.743878
1130 00:24:28.743936
1131 00:24:28.744711 [DQSOSCAuto] RK0, (LSB)MR18= 0x2929, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1132 00:24:28.744794 CH0 RK0: MR19=606, MR18=2929
1133 00:24:28.745195 CH0_RK0: MR19=0x606, MR18=0x2929, DQSOSC=399, MR23=63, INC=92, DEC=61
1134 00:24:28.745276
1135 00:24:28.745721 ----->DramcWriteLeveling(PI) begin...
1136 00:24:28.745803 ==
1137 00:24:28.746046 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 00:24:28.746117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 00:24:28.746182 ==
1140 00:24:28.746251 Write leveling (Byte 0): 31 => 31
1141 00:24:28.746311 Write leveling (Byte 1): 31 => 31
1142 00:24:28.787416 DramcWriteLeveling(PI) end<-----
1143 00:24:28.787508
1144 00:24:28.787573 ==
1145 00:24:28.787815 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 00:24:28.787882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 00:24:28.787942 ==
1148 00:24:28.788009 [Gating] SW mode calibration
1149 00:24:28.788248 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1150 00:24:28.788312 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1151 00:24:28.789081 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1152 00:24:28.789344 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1153 00:24:28.789593 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1154 00:24:28.789659 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 00:24:28.801097 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 00:24:28.801358 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 00:24:28.804214 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 00:24:28.807716 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 00:24:28.811502 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 00:24:28.814910 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 00:24:28.818143 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 00:24:28.822018 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 00:24:28.828893 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 00:24:28.832069 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 00:24:28.835882 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 00:24:28.839180 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 00:24:28.845679 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 00:24:28.848976 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1169 00:24:28.852389 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1170 00:24:28.859197 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 00:24:28.862450 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 00:24:28.865861 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 00:24:28.872754 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 00:24:28.876167 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:24:28.879683 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:24:28.885939 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 00:24:28.889972 0 9 8 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
1178 00:24:28.892510 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1179 00:24:28.899109 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 00:24:28.902463 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 00:24:28.905718 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 00:24:28.912384 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 00:24:28.915694 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 00:24:28.919327 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
1185 00:24:28.925552 0 10 8 | B1->B0 | 2f2f 2424 | 1 0 | (1 1) (0 0)
1186 00:24:28.929437 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1187 00:24:28.932825 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 00:24:28.935814 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 00:24:28.942486 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 00:24:28.945648 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 00:24:28.949121 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 00:24:28.955973 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1193 00:24:28.958932 0 11 8 | B1->B0 | 2b2b 4242 | 0 1 | (0 0) (0 0)
1194 00:24:28.962388 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1195 00:24:28.969252 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 00:24:28.972821 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 00:24:28.975731 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 00:24:28.982849 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 00:24:28.985641 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 00:24:28.989234 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 00:24:28.995810 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1202 00:24:28.999215 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 00:24:29.002303 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 00:24:29.008872 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 00:24:29.012168 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 00:24:29.015542 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 00:24:29.022315 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 00:24:29.025414 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 00:24:29.028961 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 00:24:29.035711 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 00:24:29.038651 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 00:24:29.041927 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 00:24:29.045642 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 00:24:29.051989 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 00:24:29.055541 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 00:24:29.058589 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1217 00:24:29.065347 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1218 00:24:29.068668 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 00:24:29.072086 Total UI for P1: 0, mck2ui 16
1220 00:24:29.075392 best dqsien dly found for B0: ( 0, 14, 6)
1221 00:24:29.078976 Total UI for P1: 0, mck2ui 16
1222 00:24:29.082486 best dqsien dly found for B1: ( 0, 14, 8)
1223 00:24:29.085969 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1224 00:24:29.088923 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1225 00:24:29.089005
1226 00:24:29.092091 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1227 00:24:29.095678 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1228 00:24:29.099153 [Gating] SW calibration Done
1229 00:24:29.099235 ==
1230 00:24:29.102219 Dram Type= 6, Freq= 0, CH_0, rank 1
1231 00:24:29.105799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1232 00:24:29.109140 ==
1233 00:24:29.109222 RX Vref Scan: 0
1234 00:24:29.109286
1235 00:24:29.112634 RX Vref 0 -> 0, step: 1
1236 00:24:29.112716
1237 00:24:29.115923 RX Delay -130 -> 252, step: 16
1238 00:24:29.119128 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1239 00:24:29.122461 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1240 00:24:29.125465 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1241 00:24:29.129237 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1242 00:24:29.132454 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1243 00:24:29.138913 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1244 00:24:29.142359 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1245 00:24:29.146051 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1246 00:24:29.149430 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1247 00:24:29.152488 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1248 00:24:29.159225 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1249 00:24:29.162296 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1250 00:24:29.166133 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1251 00:24:29.168939 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1252 00:24:29.172593 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1253 00:24:29.178998 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1254 00:24:29.179082 ==
1255 00:24:29.182569 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 00:24:29.185658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1257 00:24:29.185741 ==
1258 00:24:29.185807 DQS Delay:
1259 00:24:29.189511 DQS0 = 0, DQS1 = 0
1260 00:24:29.189594 DQM Delay:
1261 00:24:29.192350 DQM0 = 77, DQM1 = 70
1262 00:24:29.192431 DQ Delay:
1263 00:24:29.195712 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1264 00:24:29.199191 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
1265 00:24:29.202623 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1266 00:24:29.206100 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1267 00:24:29.206182
1268 00:24:29.206247
1269 00:24:29.206307 ==
1270 00:24:29.209178 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 00:24:29.212822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 00:24:29.212904 ==
1273 00:24:29.212969
1274 00:24:29.216161
1275 00:24:29.216243 TX Vref Scan disable
1276 00:24:29.219153 == TX Byte 0 ==
1277 00:24:29.222805 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1278 00:24:29.226272 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1279 00:24:29.229090 == TX Byte 1 ==
1280 00:24:29.232517 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1281 00:24:29.235868 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1282 00:24:29.235942 ==
1283 00:24:29.239559 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 00:24:29.245973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 00:24:29.246057 ==
1286 00:24:29.257284 TX Vref=22, minBit 9, minWin=26, winSum=432
1287 00:24:29.261074 TX Vref=24, minBit 11, minWin=26, winSum=437
1288 00:24:29.264271 TX Vref=26, minBit 1, minWin=27, winSum=440
1289 00:24:29.267677 TX Vref=28, minBit 1, minWin=27, winSum=440
1290 00:24:29.270883 TX Vref=30, minBit 11, minWin=26, winSum=440
1291 00:24:29.278043 TX Vref=32, minBit 11, minWin=26, winSum=439
1292 00:24:29.281069 [TxChooseVref] Worse bit 1, Min win 27, Win sum 440, Final Vref 26
1293 00:24:29.281153
1294 00:24:29.284754 Final TX Range 1 Vref 26
1295 00:24:29.284838
1296 00:24:29.284902 ==
1297 00:24:29.287727 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 00:24:29.291090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 00:24:29.291171 ==
1300 00:24:29.294096
1301 00:24:29.294177
1302 00:24:29.294240 TX Vref Scan disable
1303 00:24:29.297379 == TX Byte 0 ==
1304 00:24:29.301296 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1305 00:24:29.304028 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1306 00:24:29.307772 == TX Byte 1 ==
1307 00:24:29.311090 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1308 00:24:29.314463 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1309 00:24:29.317768
1310 00:24:29.317877 [DATLAT]
1311 00:24:29.317963 Freq=800, CH0 RK1
1312 00:24:29.318046
1313 00:24:29.321308 DATLAT Default: 0xa
1314 00:24:29.321417 0, 0xFFFF, sum = 0
1315 00:24:29.324665 1, 0xFFFF, sum = 0
1316 00:24:29.324789 2, 0xFFFF, sum = 0
1317 00:24:29.327817 3, 0xFFFF, sum = 0
1318 00:24:29.327954 4, 0xFFFF, sum = 0
1319 00:24:29.331271 5, 0xFFFF, sum = 0
1320 00:24:29.331422 6, 0xFFFF, sum = 0
1321 00:24:29.335056 7, 0xFFFF, sum = 0
1322 00:24:29.335215 8, 0xFFFF, sum = 0
1323 00:24:29.338299 9, 0x0, sum = 1
1324 00:24:29.338473 10, 0x0, sum = 2
1325 00:24:29.340947 11, 0x0, sum = 3
1326 00:24:29.341121 12, 0x0, sum = 4
1327 00:24:29.344583 best_step = 10
1328 00:24:29.344784
1329 00:24:29.344942 ==
1330 00:24:29.348146 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 00:24:29.351344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 00:24:29.351609 ==
1333 00:24:29.354960 RX Vref Scan: 0
1334 00:24:29.355257
1335 00:24:29.355572 RX Vref 0 -> 0, step: 1
1336 00:24:29.355888
1337 00:24:29.358259 RX Delay -111 -> 252, step: 8
1338 00:24:29.364617 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1339 00:24:29.367723 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1340 00:24:29.371350 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1341 00:24:29.374816 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1342 00:24:29.378176 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1343 00:24:29.384693 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1344 00:24:29.388236 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1345 00:24:29.392010 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1346 00:24:29.394527 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1347 00:24:29.397815 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1348 00:24:29.404409 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1349 00:24:29.407872 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1350 00:24:29.411278 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1351 00:24:29.414615 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1352 00:24:29.417996 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1353 00:24:29.424862 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1354 00:24:29.425377 ==
1355 00:24:29.427672 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 00:24:29.431643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 00:24:29.432066 ==
1358 00:24:29.432400 DQS Delay:
1359 00:24:29.434823 DQS0 = 0, DQS1 = 0
1360 00:24:29.435239 DQM Delay:
1361 00:24:29.438327 DQM0 = 78, DQM1 = 70
1362 00:24:29.438741 DQ Delay:
1363 00:24:29.441176 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1364 00:24:29.444698 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =88
1365 00:24:29.447966 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1366 00:24:29.451662 DQ12 =72, DQ13 =72, DQ14 =80, DQ15 =80
1367 00:24:29.452082
1368 00:24:29.452413
1369 00:24:29.458145 [DQSOSCAuto] RK1, (LSB)MR18= 0x4722, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1370 00:24:29.461521 CH0 RK1: MR19=606, MR18=4722
1371 00:24:29.468516 CH0_RK1: MR19=0x606, MR18=0x4722, DQSOSC=392, MR23=63, INC=96, DEC=64
1372 00:24:29.472348 [RxdqsGatingPostProcess] freq 800
1373 00:24:29.475603 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1374 00:24:29.479643 Pre-setting of DQS Precalculation
1375 00:24:29.486961 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1376 00:24:29.487617 ==
1377 00:24:29.490475 Dram Type= 6, Freq= 0, CH_1, rank 0
1378 00:24:29.493564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1379 00:24:29.494072 ==
1380 00:24:29.497688 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1381 00:24:29.504443 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1382 00:24:29.512834 [CA 0] Center 36 (6~66) winsize 61
1383 00:24:29.516323 [CA 1] Center 36 (6~67) winsize 62
1384 00:24:29.519714 [CA 2] Center 34 (5~64) winsize 60
1385 00:24:29.523209 [CA 3] Center 34 (4~64) winsize 61
1386 00:24:29.526343 [CA 4] Center 34 (4~65) winsize 62
1387 00:24:29.529223 [CA 5] Center 33 (3~64) winsize 62
1388 00:24:29.529677
1389 00:24:29.532708 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1390 00:24:29.533161
1391 00:24:29.536087 [CATrainingPosCal] consider 1 rank data
1392 00:24:29.539743 u2DelayCellTimex100 = 270/100 ps
1393 00:24:29.542752 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1394 00:24:29.549567 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1395 00:24:29.552831 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1396 00:24:29.556145 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1397 00:24:29.559127 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1398 00:24:29.563063 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1399 00:24:29.563580
1400 00:24:29.566580 CA PerBit enable=1, Macro0, CA PI delay=33
1401 00:24:29.567093
1402 00:24:29.569167 [CBTSetCACLKResult] CA Dly = 33
1403 00:24:29.569629 CS Dly: 5 (0~36)
1404 00:24:29.572961 ==
1405 00:24:29.576418 Dram Type= 6, Freq= 0, CH_1, rank 1
1406 00:24:29.579193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 00:24:29.579654 ==
1408 00:24:29.582725 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1409 00:24:29.589707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1410 00:24:29.599053 [CA 0] Center 36 (6~67) winsize 62
1411 00:24:29.602476 [CA 1] Center 36 (6~67) winsize 62
1412 00:24:29.606339 [CA 2] Center 34 (4~65) winsize 62
1413 00:24:29.608900 [CA 3] Center 34 (4~64) winsize 61
1414 00:24:29.612381 [CA 4] Center 34 (4~65) winsize 62
1415 00:24:29.615982 [CA 5] Center 33 (3~64) winsize 62
1416 00:24:29.616443
1417 00:24:29.619291 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1418 00:24:29.619792
1419 00:24:29.622323 [CATrainingPosCal] consider 2 rank data
1420 00:24:29.625721 u2DelayCellTimex100 = 270/100 ps
1421 00:24:29.629070 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1422 00:24:29.632424 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1423 00:24:29.639321 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1424 00:24:29.642555 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1425 00:24:29.645887 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1426 00:24:29.649313 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1427 00:24:29.649765
1428 00:24:29.652261 CA PerBit enable=1, Macro0, CA PI delay=33
1429 00:24:29.652749
1430 00:24:29.655702 [CBTSetCACLKResult] CA Dly = 33
1431 00:24:29.656168 CS Dly: 5 (0~37)
1432 00:24:29.656545
1433 00:24:29.659235 ----->DramcWriteLeveling(PI) begin...
1434 00:24:29.659907 ==
1435 00:24:29.662924 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 00:24:29.668963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 00:24:29.669485 ==
1438 00:24:29.672463 Write leveling (Byte 0): 27 => 27
1439 00:24:29.676205 Write leveling (Byte 1): 32 => 32
1440 00:24:29.676663 DramcWriteLeveling(PI) end<-----
1441 00:24:29.679285
1442 00:24:29.679975 ==
1443 00:24:29.682682 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 00:24:29.685896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 00:24:29.685980 ==
1446 00:24:29.689198 [Gating] SW mode calibration
1447 00:24:29.695813 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1448 00:24:29.699335 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1449 00:24:29.705869 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1450 00:24:29.709066 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 00:24:29.712424 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 00:24:29.719013 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 00:24:29.722579 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 00:24:29.725638 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 00:24:29.732263 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 00:24:29.735954 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 00:24:29.739338 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 00:24:29.745563 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 00:24:29.749139 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 00:24:29.752443 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 00:24:29.755858 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 00:24:29.762412 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 00:24:29.765704 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 00:24:29.769063 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 00:24:29.775617 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 00:24:29.778866 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1467 00:24:29.782627 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1468 00:24:29.788967 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 00:24:29.792515 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 00:24:29.795975 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 00:24:29.802396 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 00:24:29.805623 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 00:24:29.809329 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 00:24:29.815816 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 00:24:29.819209 0 9 8 | B1->B0 | 2c2c 2c2c | 0 0 | (0 0) (0 0)
1476 00:24:29.822686 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 00:24:29.829045 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 00:24:29.832587 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 00:24:29.835843 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 00:24:29.839437 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 00:24:29.846124 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 00:24:29.849643 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 00:24:29.852516 0 10 8 | B1->B0 | 2525 2424 | 0 0 | (1 0) (0 0)
1484 00:24:29.859929 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 00:24:29.862631 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 00:24:29.866103 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 00:24:29.872470 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 00:24:29.876139 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 00:24:29.879338 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 00:24:29.886213 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1491 00:24:29.889767 0 11 8 | B1->B0 | 3737 3232 | 1 0 | (0 0) (0 0)
1492 00:24:29.892742 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 00:24:29.899484 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 00:24:29.903127 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 00:24:29.906055 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 00:24:29.912564 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 00:24:29.916178 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 00:24:29.919431 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 00:24:29.926273 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1500 00:24:29.929397 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 00:24:29.932828 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 00:24:29.938924 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 00:24:29.942770 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 00:24:29.945670 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 00:24:29.949194 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 00:24:29.956101 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 00:24:29.958755 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 00:24:29.962305 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 00:24:29.968960 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 00:24:29.972224 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 00:24:29.976227 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 00:24:29.982851 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 00:24:29.985546 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 00:24:29.989068 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 00:24:29.995526 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1516 00:24:29.995602 Total UI for P1: 0, mck2ui 16
1517 00:24:30.002201 best dqsien dly found for B1: ( 0, 14, 6)
1518 00:24:30.005636 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 00:24:30.008978 Total UI for P1: 0, mck2ui 16
1520 00:24:30.011994 best dqsien dly found for B0: ( 0, 14, 8)
1521 00:24:30.015309 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1522 00:24:30.019247 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1523 00:24:30.019344
1524 00:24:30.022749 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1525 00:24:30.025817 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1526 00:24:30.029153 [Gating] SW calibration Done
1527 00:24:30.029223 ==
1528 00:24:30.032573 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 00:24:30.035591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 00:24:30.035662 ==
1531 00:24:30.039255 RX Vref Scan: 0
1532 00:24:30.039350
1533 00:24:30.042307 RX Vref 0 -> 0, step: 1
1534 00:24:30.042377
1535 00:24:30.042436 RX Delay -130 -> 252, step: 16
1536 00:24:30.049573 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1537 00:24:30.052829 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1538 00:24:30.056308 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1539 00:24:30.059672 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1540 00:24:30.062981 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1541 00:24:30.066136 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1542 00:24:30.072792 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1543 00:24:30.076195 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1544 00:24:30.079335 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1545 00:24:30.083084 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1546 00:24:30.086035 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1547 00:24:30.092725 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1548 00:24:30.096276 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1549 00:24:30.099681 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1550 00:24:30.102788 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1551 00:24:30.106277 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1552 00:24:30.109425 ==
1553 00:24:30.112837 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 00:24:30.116195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 00:24:30.116267 ==
1556 00:24:30.116327 DQS Delay:
1557 00:24:30.119628 DQS0 = 0, DQS1 = 0
1558 00:24:30.119698 DQM Delay:
1559 00:24:30.122992 DQM0 = 80, DQM1 = 73
1560 00:24:30.123067 DQ Delay:
1561 00:24:30.126103 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =77
1562 00:24:30.129826 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1563 00:24:30.133115 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1564 00:24:30.136275 DQ12 =85, DQ13 =77, DQ14 =77, DQ15 =77
1565 00:24:30.136345
1566 00:24:30.136404
1567 00:24:30.136460 ==
1568 00:24:30.139734 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 00:24:30.143390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 00:24:30.143461 ==
1571 00:24:30.143521
1572 00:24:30.143578
1573 00:24:30.146205 TX Vref Scan disable
1574 00:24:30.149798 == TX Byte 0 ==
1575 00:24:30.152842 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1576 00:24:30.156237 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1577 00:24:30.159845 == TX Byte 1 ==
1578 00:24:30.162777 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1579 00:24:30.166349 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1580 00:24:30.166419 ==
1581 00:24:30.169762 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 00:24:30.173475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 00:24:30.173546 ==
1584 00:24:30.187957 TX Vref=22, minBit 8, minWin=27, winSum=447
1585 00:24:30.191318 TX Vref=24, minBit 8, minWin=27, winSum=450
1586 00:24:30.194823 TX Vref=26, minBit 1, minWin=28, winSum=457
1587 00:24:30.198282 TX Vref=28, minBit 8, minWin=28, winSum=459
1588 00:24:30.201635 TX Vref=30, minBit 1, minWin=28, winSum=456
1589 00:24:30.204413 TX Vref=32, minBit 11, minWin=27, winSum=456
1590 00:24:30.211004 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 28
1591 00:24:30.211084
1592 00:24:30.214424 Final TX Range 1 Vref 28
1593 00:24:30.214495
1594 00:24:30.214554 ==
1595 00:24:30.218412 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 00:24:30.220913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 00:24:30.220984 ==
1598 00:24:30.221051
1599 00:24:30.224544
1600 00:24:30.224613 TX Vref Scan disable
1601 00:24:30.228211 == TX Byte 0 ==
1602 00:24:30.230975 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1603 00:24:30.237986 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1604 00:24:30.238059 == TX Byte 1 ==
1605 00:24:30.241224 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1606 00:24:30.247581 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1607 00:24:30.247660
1608 00:24:30.247721 [DATLAT]
1609 00:24:30.247779 Freq=800, CH1 RK0
1610 00:24:30.247835
1611 00:24:30.250964 DATLAT Default: 0xa
1612 00:24:30.251032 0, 0xFFFF, sum = 0
1613 00:24:30.254233 1, 0xFFFF, sum = 0
1614 00:24:30.254330 2, 0xFFFF, sum = 0
1615 00:24:30.257473 3, 0xFFFF, sum = 0
1616 00:24:30.261307 4, 0xFFFF, sum = 0
1617 00:24:30.261382 5, 0xFFFF, sum = 0
1618 00:24:30.264058 6, 0xFFFF, sum = 0
1619 00:24:30.264129 7, 0xFFFF, sum = 0
1620 00:24:30.267874 8, 0xFFFF, sum = 0
1621 00:24:30.267944 9, 0x0, sum = 1
1622 00:24:30.268004 10, 0x0, sum = 2
1623 00:24:30.271340 11, 0x0, sum = 3
1624 00:24:30.271472 12, 0x0, sum = 4
1625 00:24:30.274896 best_step = 10
1626 00:24:30.274985
1627 00:24:30.275050 ==
1628 00:24:30.277944 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 00:24:30.281209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 00:24:30.281291 ==
1631 00:24:30.284693 RX Vref Scan: 1
1632 00:24:30.284775
1633 00:24:30.284841 Set Vref Range= 32 -> 127
1634 00:24:30.284902
1635 00:24:30.288067 RX Vref 32 -> 127, step: 1
1636 00:24:30.288148
1637 00:24:30.291411 RX Delay -111 -> 252, step: 8
1638 00:24:30.291507
1639 00:24:30.294279 Set Vref, RX VrefLevel [Byte0]: 32
1640 00:24:30.297778 [Byte1]: 32
1641 00:24:30.297860
1642 00:24:30.301206 Set Vref, RX VrefLevel [Byte0]: 33
1643 00:24:30.304234 [Byte1]: 33
1644 00:24:30.308272
1645 00:24:30.308354 Set Vref, RX VrefLevel [Byte0]: 34
1646 00:24:30.312188 [Byte1]: 34
1647 00:24:30.316044
1648 00:24:30.316125 Set Vref, RX VrefLevel [Byte0]: 35
1649 00:24:30.319352 [Byte1]: 35
1650 00:24:30.323474
1651 00:24:30.323556 Set Vref, RX VrefLevel [Byte0]: 36
1652 00:24:30.326909 [Byte1]: 36
1653 00:24:30.331230
1654 00:24:30.331311 Set Vref, RX VrefLevel [Byte0]: 37
1655 00:24:30.334514 [Byte1]: 37
1656 00:24:30.339425
1657 00:24:30.339504 Set Vref, RX VrefLevel [Byte0]: 38
1658 00:24:30.342374 [Byte1]: 38
1659 00:24:30.346703
1660 00:24:30.346775 Set Vref, RX VrefLevel [Byte0]: 39
1661 00:24:30.349833 [Byte1]: 39
1662 00:24:30.354420
1663 00:24:30.354522 Set Vref, RX VrefLevel [Byte0]: 40
1664 00:24:30.357288 [Byte1]: 40
1665 00:24:30.361731
1666 00:24:30.361803 Set Vref, RX VrefLevel [Byte0]: 41
1667 00:24:30.364996 [Byte1]: 41
1668 00:24:30.369388
1669 00:24:30.369460 Set Vref, RX VrefLevel [Byte0]: 42
1670 00:24:30.372633 [Byte1]: 42
1671 00:24:30.377462
1672 00:24:30.377534 Set Vref, RX VrefLevel [Byte0]: 43
1673 00:24:30.380576 [Byte1]: 43
1674 00:24:30.384669
1675 00:24:30.384742 Set Vref, RX VrefLevel [Byte0]: 44
1676 00:24:30.388187 [Byte1]: 44
1677 00:24:30.392531
1678 00:24:30.392605 Set Vref, RX VrefLevel [Byte0]: 45
1679 00:24:30.395968 [Byte1]: 45
1680 00:24:30.400332
1681 00:24:30.400403 Set Vref, RX VrefLevel [Byte0]: 46
1682 00:24:30.403200 [Byte1]: 46
1683 00:24:30.408154
1684 00:24:30.408231 Set Vref, RX VrefLevel [Byte0]: 47
1685 00:24:30.410911 [Byte1]: 47
1686 00:24:30.415586
1687 00:24:30.415656 Set Vref, RX VrefLevel [Byte0]: 48
1688 00:24:30.419130 [Byte1]: 48
1689 00:24:30.423239
1690 00:24:30.423315 Set Vref, RX VrefLevel [Byte0]: 49
1691 00:24:30.426264 [Byte1]: 49
1692 00:24:30.430526
1693 00:24:30.430596 Set Vref, RX VrefLevel [Byte0]: 50
1694 00:24:30.434048 [Byte1]: 50
1695 00:24:30.438229
1696 00:24:30.438305 Set Vref, RX VrefLevel [Byte0]: 51
1697 00:24:30.441766 [Byte1]: 51
1698 00:24:30.445991
1699 00:24:30.446062 Set Vref, RX VrefLevel [Byte0]: 52
1700 00:24:30.449520 [Byte1]: 52
1701 00:24:30.453409
1702 00:24:30.453479 Set Vref, RX VrefLevel [Byte0]: 53
1703 00:24:30.456954 [Byte1]: 53
1704 00:24:30.461570
1705 00:24:30.461641 Set Vref, RX VrefLevel [Byte0]: 54
1706 00:24:30.464442 [Byte1]: 54
1707 00:24:30.469166
1708 00:24:30.469236 Set Vref, RX VrefLevel [Byte0]: 55
1709 00:24:30.472296 [Byte1]: 55
1710 00:24:30.476536
1711 00:24:30.476611 Set Vref, RX VrefLevel [Byte0]: 56
1712 00:24:30.479580 [Byte1]: 56
1713 00:24:30.484218
1714 00:24:30.484290 Set Vref, RX VrefLevel [Byte0]: 57
1715 00:24:30.487516 [Byte1]: 57
1716 00:24:30.492135
1717 00:24:30.492206 Set Vref, RX VrefLevel [Byte0]: 58
1718 00:24:30.495032 [Byte1]: 58
1719 00:24:30.499590
1720 00:24:30.499665 Set Vref, RX VrefLevel [Byte0]: 59
1721 00:24:30.502870 [Byte1]: 59
1722 00:24:30.507460
1723 00:24:30.507537 Set Vref, RX VrefLevel [Byte0]: 60
1724 00:24:30.510307 [Byte1]: 60
1725 00:24:30.515110
1726 00:24:30.515180 Set Vref, RX VrefLevel [Byte0]: 61
1727 00:24:30.518718 [Byte1]: 61
1728 00:24:30.522492
1729 00:24:30.522569 Set Vref, RX VrefLevel [Byte0]: 62
1730 00:24:30.525976 [Byte1]: 62
1731 00:24:30.530021
1732 00:24:30.530091 Set Vref, RX VrefLevel [Byte0]: 63
1733 00:24:30.533727 [Byte1]: 63
1734 00:24:30.537996
1735 00:24:30.538073 Set Vref, RX VrefLevel [Byte0]: 64
1736 00:24:30.540962 [Byte1]: 64
1737 00:24:30.545474
1738 00:24:30.545551 Set Vref, RX VrefLevel [Byte0]: 65
1739 00:24:30.548845 [Byte1]: 65
1740 00:24:30.553044
1741 00:24:30.553113 Set Vref, RX VrefLevel [Byte0]: 66
1742 00:24:30.556193 [Byte1]: 66
1743 00:24:30.560416
1744 00:24:30.560497 Set Vref, RX VrefLevel [Byte0]: 67
1745 00:24:30.563806 [Byte1]: 67
1746 00:24:30.568795
1747 00:24:30.568867 Set Vref, RX VrefLevel [Byte0]: 68
1748 00:24:30.571400 [Byte1]: 68
1749 00:24:30.575959
1750 00:24:30.576043 Set Vref, RX VrefLevel [Byte0]: 69
1751 00:24:30.579494 [Byte1]: 69
1752 00:24:30.583484
1753 00:24:30.583584 Set Vref, RX VrefLevel [Byte0]: 70
1754 00:24:30.586959 [Byte1]: 70
1755 00:24:30.591589
1756 00:24:30.591686 Set Vref, RX VrefLevel [Byte0]: 71
1757 00:24:30.594519 [Byte1]: 71
1758 00:24:30.598958
1759 00:24:30.599079 Set Vref, RX VrefLevel [Byte0]: 72
1760 00:24:30.602461 [Byte1]: 72
1761 00:24:30.607003
1762 00:24:30.607191 Set Vref, RX VrefLevel [Byte0]: 73
1763 00:24:30.610003 [Byte1]: 73
1764 00:24:30.614271
1765 00:24:30.614454 Set Vref, RX VrefLevel [Byte0]: 74
1766 00:24:30.617671 [Byte1]: 74
1767 00:24:30.622379
1768 00:24:30.622645 Set Vref, RX VrefLevel [Byte0]: 75
1769 00:24:30.625242 [Byte1]: 75
1770 00:24:30.629920
1771 00:24:30.630259 Set Vref, RX VrefLevel [Byte0]: 76
1772 00:24:30.633139 [Byte1]: 76
1773 00:24:30.637511
1774 00:24:30.637908 Final RX Vref Byte 0 = 51 to rank0
1775 00:24:30.640859 Final RX Vref Byte 1 = 56 to rank0
1776 00:24:30.644422 Final RX Vref Byte 0 = 51 to rank1
1777 00:24:30.647701 Final RX Vref Byte 1 = 56 to rank1==
1778 00:24:30.650822 Dram Type= 6, Freq= 0, CH_1, rank 0
1779 00:24:30.657550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1780 00:24:30.657975 ==
1781 00:24:30.658333 DQS Delay:
1782 00:24:30.658675 DQS0 = 0, DQS1 = 0
1783 00:24:30.661455 DQM Delay:
1784 00:24:30.661911 DQM0 = 80, DQM1 = 71
1785 00:24:30.663992 DQ Delay:
1786 00:24:30.667291 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1787 00:24:30.667381 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1788 00:24:30.670426 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =64
1789 00:24:30.673624 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =76
1790 00:24:30.676967
1791 00:24:30.677074
1792 00:24:30.683666 [DQSOSCAuto] RK0, (LSB)MR18= 0x1721, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
1793 00:24:30.687061 CH1 RK0: MR19=606, MR18=1721
1794 00:24:30.693558 CH1_RK0: MR19=0x606, MR18=0x1721, DQSOSC=401, MR23=63, INC=91, DEC=61
1795 00:24:30.693640
1796 00:24:30.697612 ----->DramcWriteLeveling(PI) begin...
1797 00:24:30.697703 ==
1798 00:24:30.700123 Dram Type= 6, Freq= 0, CH_1, rank 1
1799 00:24:30.704310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1800 00:24:30.704382 ==
1801 00:24:30.706996 Write leveling (Byte 0): 29 => 29
1802 00:24:30.710363 Write leveling (Byte 1): 30 => 30
1803 00:24:30.714107 DramcWriteLeveling(PI) end<-----
1804 00:24:30.714179
1805 00:24:30.714238 ==
1806 00:24:30.717106 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 00:24:30.720195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 00:24:30.720270 ==
1809 00:24:30.723678 [Gating] SW mode calibration
1810 00:24:30.730624 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1811 00:24:30.736983 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1812 00:24:30.740747 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1813 00:24:30.744037 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1814 00:24:30.750302 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 00:24:30.753716 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 00:24:30.756858 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 00:24:30.763749 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 00:24:30.767108 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 00:24:30.770587 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 00:24:30.777133 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 00:24:30.780503 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 00:24:30.783407 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 00:24:30.790369 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 00:24:30.793363 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 00:24:30.796794 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 00:24:30.803507 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 00:24:30.807298 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 00:24:30.810162 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 00:24:30.813377 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1830 00:24:30.820408 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 00:24:30.823795 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 00:24:30.826801 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 00:24:30.833570 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 00:24:30.836896 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 00:24:30.840247 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 00:24:30.847207 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 00:24:30.850514 0 9 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1838 00:24:30.853968 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1839 00:24:30.860356 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 00:24:30.863864 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 00:24:30.867086 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 00:24:30.874007 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 00:24:30.876842 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 00:24:30.879973 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 00:24:30.886882 0 10 4 | B1->B0 | 3030 2828 | 1 1 | (1 1) (1 1)
1846 00:24:30.890191 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
1847 00:24:30.893366 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 00:24:30.900053 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 00:24:30.903744 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 00:24:30.906959 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 00:24:30.913950 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 00:24:30.916831 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1853 00:24:30.919929 0 11 4 | B1->B0 | 3232 3838 | 0 0 | (0 0) (0 0)
1854 00:24:30.923670 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 00:24:30.930596 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 00:24:30.933460 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 00:24:30.937019 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 00:24:30.944109 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 00:24:30.947368 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 00:24:30.950089 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 00:24:30.957130 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1862 00:24:30.960441 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 00:24:30.964078 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 00:24:30.970683 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 00:24:30.974066 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 00:24:30.976768 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 00:24:30.983637 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 00:24:30.987106 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 00:24:30.990057 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 00:24:30.996803 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 00:24:31.000659 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 00:24:31.003313 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 00:24:31.010495 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 00:24:31.013794 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 00:24:31.017079 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 00:24:31.020181 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 00:24:31.026860 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1878 00:24:31.030144 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1879 00:24:31.034081 Total UI for P1: 0, mck2ui 16
1880 00:24:31.036853 best dqsien dly found for B0: ( 0, 14, 4)
1881 00:24:31.040308 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 00:24:31.043143 Total UI for P1: 0, mck2ui 16
1883 00:24:31.046855 best dqsien dly found for B1: ( 0, 14, 6)
1884 00:24:31.049886 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1885 00:24:31.053503 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1886 00:24:31.053574
1887 00:24:31.060141 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1888 00:24:31.063638 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1889 00:24:31.063711 [Gating] SW calibration Done
1890 00:24:31.067168 ==
1891 00:24:31.070496 Dram Type= 6, Freq= 0, CH_1, rank 1
1892 00:24:31.073392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1893 00:24:31.073475 ==
1894 00:24:31.073545 RX Vref Scan: 0
1895 00:24:31.073611
1896 00:24:31.076866 RX Vref 0 -> 0, step: 1
1897 00:24:31.076955
1898 00:24:31.080225 RX Delay -130 -> 252, step: 16
1899 00:24:31.083929 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1900 00:24:31.086803 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1901 00:24:31.090272 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1902 00:24:31.096869 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1903 00:24:31.100312 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1904 00:24:31.103657 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1905 00:24:31.107238 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1906 00:24:31.110923 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1907 00:24:31.117684 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1908 00:24:31.120296 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1909 00:24:31.123654 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1910 00:24:31.127338 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1911 00:24:31.130578 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1912 00:24:31.136997 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1913 00:24:31.140833 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1914 00:24:31.143692 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1915 00:24:31.144116 ==
1916 00:24:31.146897 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 00:24:31.150388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 00:24:31.153734 ==
1919 00:24:31.154223 DQS Delay:
1920 00:24:31.154560 DQS0 = 0, DQS1 = 0
1921 00:24:31.157150 DQM Delay:
1922 00:24:31.157600 DQM0 = 79, DQM1 = 74
1923 00:24:31.160464 DQ Delay:
1924 00:24:31.160917 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =69
1925 00:24:31.163937 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1926 00:24:31.167037 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1927 00:24:31.170081 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =77
1928 00:24:31.173433
1929 00:24:31.173897
1930 00:24:31.174265 ==
1931 00:24:31.176747 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 00:24:31.180313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 00:24:31.180910 ==
1934 00:24:31.181281
1935 00:24:31.181597
1936 00:24:31.183750 TX Vref Scan disable
1937 00:24:31.184197 == TX Byte 0 ==
1938 00:24:31.190271 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1939 00:24:31.193448 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1940 00:24:31.193900 == TX Byte 1 ==
1941 00:24:31.199946 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1942 00:24:31.203164 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1943 00:24:31.203658 ==
1944 00:24:31.206743 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 00:24:31.210037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 00:24:31.210505 ==
1947 00:24:31.223587 TX Vref=22, minBit 9, minWin=27, winSum=448
1948 00:24:31.226388 TX Vref=24, minBit 0, minWin=28, winSum=456
1949 00:24:31.230197 TX Vref=26, minBit 6, minWin=28, winSum=461
1950 00:24:31.233093 TX Vref=28, minBit 8, minWin=28, winSum=460
1951 00:24:31.236841 TX Vref=30, minBit 8, minWin=28, winSum=460
1952 00:24:31.239761 TX Vref=32, minBit 8, minWin=28, winSum=460
1953 00:24:31.246614 [TxChooseVref] Worse bit 6, Min win 28, Win sum 461, Final Vref 26
1954 00:24:31.246698
1955 00:24:31.249989 Final TX Range 1 Vref 26
1956 00:24:31.250059
1957 00:24:31.250119 ==
1958 00:24:31.253361 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 00:24:31.256806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 00:24:31.256878 ==
1961 00:24:31.256938
1962 00:24:31.259613
1963 00:24:31.259686 TX Vref Scan disable
1964 00:24:31.263076 == TX Byte 0 ==
1965 00:24:31.266484 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1966 00:24:31.269852 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1967 00:24:31.273257 == TX Byte 1 ==
1968 00:24:31.276521 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1969 00:24:31.280010 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1970 00:24:31.283170
1971 00:24:31.283244 [DATLAT]
1972 00:24:31.283307 Freq=800, CH1 RK1
1973 00:24:31.283365
1974 00:24:31.286561 DATLAT Default: 0xa
1975 00:24:31.286633 0, 0xFFFF, sum = 0
1976 00:24:31.289982 1, 0xFFFF, sum = 0
1977 00:24:31.290051 2, 0xFFFF, sum = 0
1978 00:24:31.293363 3, 0xFFFF, sum = 0
1979 00:24:31.293439 4, 0xFFFF, sum = 0
1980 00:24:31.297042 5, 0xFFFF, sum = 0
1981 00:24:31.297111 6, 0xFFFF, sum = 0
1982 00:24:31.299682 7, 0xFFFF, sum = 0
1983 00:24:31.299757 8, 0xFFFF, sum = 0
1984 00:24:31.303186 9, 0x0, sum = 1
1985 00:24:31.303262 10, 0x0, sum = 2
1986 00:24:31.306675 11, 0x0, sum = 3
1987 00:24:31.306744 12, 0x0, sum = 4
1988 00:24:31.310311 best_step = 10
1989 00:24:31.310385
1990 00:24:31.310446 ==
1991 00:24:31.313019 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 00:24:31.316487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 00:24:31.316556 ==
1994 00:24:31.319961 RX Vref Scan: 0
1995 00:24:31.320028
1996 00:24:31.320086 RX Vref 0 -> 0, step: 1
1997 00:24:31.320147
1998 00:24:31.323005 RX Delay -111 -> 252, step: 8
1999 00:24:31.330024 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2000 00:24:31.333203 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2001 00:24:31.336453 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2002 00:24:31.340062 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2003 00:24:31.343064 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2004 00:24:31.349885 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2005 00:24:31.353048 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2006 00:24:31.356482 iDelay=209, Bit 7, Center 72 (-47 ~ 192) 240
2007 00:24:31.359894 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2008 00:24:31.363349 iDelay=209, Bit 9, Center 60 (-63 ~ 184) 248
2009 00:24:31.369782 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2010 00:24:31.372810 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
2011 00:24:31.376550 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2012 00:24:31.379728 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2013 00:24:31.382966 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2014 00:24:31.389943 iDelay=209, Bit 15, Center 76 (-47 ~ 200) 248
2015 00:24:31.390020 ==
2016 00:24:31.393108 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 00:24:31.396735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 00:24:31.396808 ==
2019 00:24:31.396868 DQS Delay:
2020 00:24:31.399610 DQS0 = 0, DQS1 = 0
2021 00:24:31.399683 DQM Delay:
2022 00:24:31.402953 DQM0 = 77, DQM1 = 72
2023 00:24:31.403030 DQ Delay:
2024 00:24:31.406381 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2025 00:24:31.409656 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =72
2026 00:24:31.413083 DQ8 =60, DQ9 =60, DQ10 =80, DQ11 =64
2027 00:24:31.416289 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =76
2028 00:24:31.416361
2029 00:24:31.416429
2030 00:24:31.423136 [DQSOSCAuto] RK1, (LSB)MR18= 0x243d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2031 00:24:31.426386 CH1 RK1: MR19=606, MR18=243D
2032 00:24:31.433041 CH1_RK1: MR19=0x606, MR18=0x243D, DQSOSC=394, MR23=63, INC=95, DEC=63
2033 00:24:31.436572 [RxdqsGatingPostProcess] freq 800
2034 00:24:31.443067 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2035 00:24:31.446429 Pre-setting of DQS Precalculation
2036 00:24:31.449598 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2037 00:24:31.456497 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2038 00:24:31.463158 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2039 00:24:31.463233
2040 00:24:31.463296
2041 00:24:31.466541 [Calibration Summary] 1600 Mbps
2042 00:24:31.469767 CH 0, Rank 0
2043 00:24:31.469838 SW Impedance : PASS
2044 00:24:31.473319 DUTY Scan : NO K
2045 00:24:31.476098 ZQ Calibration : PASS
2046 00:24:31.476174 Jitter Meter : NO K
2047 00:24:31.479775 CBT Training : PASS
2048 00:24:31.482984 Write leveling : PASS
2049 00:24:31.483058 RX DQS gating : PASS
2050 00:24:31.486443 RX DQ/DQS(RDDQC) : PASS
2051 00:24:31.489541 TX DQ/DQS : PASS
2052 00:24:31.489613 RX DATLAT : PASS
2053 00:24:31.492977 RX DQ/DQS(Engine): PASS
2054 00:24:31.493047 TX OE : NO K
2055 00:24:31.496028 All Pass.
2056 00:24:31.496101
2057 00:24:31.496162 CH 0, Rank 1
2058 00:24:31.500297 SW Impedance : PASS
2059 00:24:31.500367 DUTY Scan : NO K
2060 00:24:31.503098 ZQ Calibration : PASS
2061 00:24:31.506428 Jitter Meter : NO K
2062 00:24:31.506499 CBT Training : PASS
2063 00:24:31.509639 Write leveling : PASS
2064 00:24:31.512993 RX DQS gating : PASS
2065 00:24:31.513066 RX DQ/DQS(RDDQC) : PASS
2066 00:24:31.516445 TX DQ/DQS : PASS
2067 00:24:31.519820 RX DATLAT : PASS
2068 00:24:31.519893 RX DQ/DQS(Engine): PASS
2069 00:24:31.523323 TX OE : NO K
2070 00:24:31.523435 All Pass.
2071 00:24:31.523495
2072 00:24:31.526249 CH 1, Rank 0
2073 00:24:31.526319 SW Impedance : PASS
2074 00:24:31.529650 DUTY Scan : NO K
2075 00:24:31.533153 ZQ Calibration : PASS
2076 00:24:31.533235 Jitter Meter : NO K
2077 00:24:31.536799 CBT Training : PASS
2078 00:24:31.536884 Write leveling : PASS
2079 00:24:31.539586 RX DQS gating : PASS
2080 00:24:31.542922 RX DQ/DQS(RDDQC) : PASS
2081 00:24:31.543025 TX DQ/DQS : PASS
2082 00:24:31.546415 RX DATLAT : PASS
2083 00:24:31.549666 RX DQ/DQS(Engine): PASS
2084 00:24:31.549785 TX OE : NO K
2085 00:24:31.553280 All Pass.
2086 00:24:31.553396
2087 00:24:31.553495 CH 1, Rank 1
2088 00:24:31.556414 SW Impedance : PASS
2089 00:24:31.556580 DUTY Scan : NO K
2090 00:24:31.559656 ZQ Calibration : PASS
2091 00:24:31.563486 Jitter Meter : NO K
2092 00:24:31.563561 CBT Training : PASS
2093 00:24:31.566540 Write leveling : PASS
2094 00:24:31.569883 RX DQS gating : PASS
2095 00:24:31.569956 RX DQ/DQS(RDDQC) : PASS
2096 00:24:31.573098 TX DQ/DQS : PASS
2097 00:24:31.576187 RX DATLAT : PASS
2098 00:24:31.576261 RX DQ/DQS(Engine): PASS
2099 00:24:31.580031 TX OE : NO K
2100 00:24:31.580108 All Pass.
2101 00:24:31.580170
2102 00:24:31.582762 DramC Write-DBI off
2103 00:24:31.586281 PER_BANK_REFRESH: Hybrid Mode
2104 00:24:31.586382 TX_TRACKING: ON
2105 00:24:31.589831 [GetDramInforAfterCalByMRR] Vendor 6.
2106 00:24:31.593308 [GetDramInforAfterCalByMRR] Revision 606.
2107 00:24:31.596058 [GetDramInforAfterCalByMRR] Revision 2 0.
2108 00:24:31.599752 MR0 0x3b3b
2109 00:24:31.599826 MR8 0x5151
2110 00:24:31.602797 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 00:24:31.602870
2112 00:24:31.602931 MR0 0x3b3b
2113 00:24:31.606208 MR8 0x5151
2114 00:24:31.609481 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 00:24:31.609581
2116 00:24:31.616062 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2117 00:24:31.623006 [FAST_K] Save calibration result to emmc
2118 00:24:31.626239 [FAST_K] Save calibration result to emmc
2119 00:24:31.626312 dram_init: config_dvfs: 1
2120 00:24:31.632795 dramc_set_vcore_voltage set vcore to 662500
2121 00:24:31.632873 Read voltage for 1200, 2
2122 00:24:31.632937 Vio18 = 0
2123 00:24:31.636377 Vcore = 662500
2124 00:24:31.636472 Vdram = 0
2125 00:24:31.636548 Vddq = 0
2126 00:24:31.639210 Vmddr = 0
2127 00:24:31.642580 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2128 00:24:31.649230 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2129 00:24:31.653284 MEM_TYPE=3, freq_sel=15
2130 00:24:31.653378 sv_algorithm_assistance_LP4_1600
2131 00:24:31.659488 ============ PULL DRAM RESETB DOWN ============
2132 00:24:31.662893 ========== PULL DRAM RESETB DOWN end =========
2133 00:24:31.666229 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2134 00:24:31.669360 ===================================
2135 00:24:31.673120 LPDDR4 DRAM CONFIGURATION
2136 00:24:31.676623 ===================================
2137 00:24:31.679628 EX_ROW_EN[0] = 0x0
2138 00:24:31.679835 EX_ROW_EN[1] = 0x0
2139 00:24:31.682974 LP4Y_EN = 0x0
2140 00:24:31.683218 WORK_FSP = 0x0
2141 00:24:31.686320 WL = 0x4
2142 00:24:31.686527 RL = 0x4
2143 00:24:31.689390 BL = 0x2
2144 00:24:31.689679 RPST = 0x0
2145 00:24:31.692845 RD_PRE = 0x0
2146 00:24:31.693113 WR_PRE = 0x1
2147 00:24:31.696353 WR_PST = 0x0
2148 00:24:31.696606 DBI_WR = 0x0
2149 00:24:31.699971 DBI_RD = 0x0
2150 00:24:31.700315 OTF = 0x1
2151 00:24:31.703345 ===================================
2152 00:24:31.705927 ===================================
2153 00:24:31.709360 ANA top config
2154 00:24:31.712835 ===================================
2155 00:24:31.716092 DLL_ASYNC_EN = 0
2156 00:24:31.716162 ALL_SLAVE_EN = 0
2157 00:24:31.719242 NEW_RANK_MODE = 1
2158 00:24:31.723075 DLL_IDLE_MODE = 1
2159 00:24:31.725823 LP45_APHY_COMB_EN = 1
2160 00:24:31.725893 TX_ODT_DIS = 1
2161 00:24:31.729302 NEW_8X_MODE = 1
2162 00:24:31.732549 ===================================
2163 00:24:31.735977 ===================================
2164 00:24:31.739406 data_rate = 2400
2165 00:24:31.742669 CKR = 1
2166 00:24:31.746045 DQ_P2S_RATIO = 8
2167 00:24:31.749250 ===================================
2168 00:24:31.749322 CA_P2S_RATIO = 8
2169 00:24:31.752884 DQ_CA_OPEN = 0
2170 00:24:31.756519 DQ_SEMI_OPEN = 0
2171 00:24:31.759337 CA_SEMI_OPEN = 0
2172 00:24:31.763057 CA_FULL_RATE = 0
2173 00:24:31.766545 DQ_CKDIV4_EN = 0
2174 00:24:31.766618 CA_CKDIV4_EN = 0
2175 00:24:31.769938 CA_PREDIV_EN = 0
2176 00:24:31.773411 PH8_DLY = 17
2177 00:24:31.776464 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2178 00:24:31.779664 DQ_AAMCK_DIV = 4
2179 00:24:31.783224 CA_AAMCK_DIV = 4
2180 00:24:31.783324 CA_ADMCK_DIV = 4
2181 00:24:31.786211 DQ_TRACK_CA_EN = 0
2182 00:24:31.789530 CA_PICK = 1200
2183 00:24:31.793074 CA_MCKIO = 1200
2184 00:24:31.796428 MCKIO_SEMI = 0
2185 00:24:31.799839 PLL_FREQ = 2366
2186 00:24:31.803068 DQ_UI_PI_RATIO = 32
2187 00:24:31.803140 CA_UI_PI_RATIO = 0
2188 00:24:31.806217 ===================================
2189 00:24:31.809778 ===================================
2190 00:24:31.812605 memory_type:LPDDR4
2191 00:24:31.816260 GP_NUM : 10
2192 00:24:31.816332 SRAM_EN : 1
2193 00:24:31.819464 MD32_EN : 0
2194 00:24:31.822724 ===================================
2195 00:24:31.826258 [ANA_INIT] >>>>>>>>>>>>>>
2196 00:24:31.829193 <<<<<< [CONFIGURE PHASE]: ANA_TX
2197 00:24:31.832788 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2198 00:24:31.836346 ===================================
2199 00:24:31.836425 data_rate = 2400,PCW = 0X5b00
2200 00:24:31.840126 ===================================
2201 00:24:31.842645 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2202 00:24:31.849413 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 00:24:31.856299 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 00:24:31.859508 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2205 00:24:31.862825 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2206 00:24:31.866325 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2207 00:24:31.869587 [ANA_INIT] flow start
2208 00:24:31.869664 [ANA_INIT] PLL >>>>>>>>
2209 00:24:31.872498 [ANA_INIT] PLL <<<<<<<<
2210 00:24:31.876127 [ANA_INIT] MIDPI >>>>>>>>
2211 00:24:31.879655 [ANA_INIT] MIDPI <<<<<<<<
2212 00:24:31.879754 [ANA_INIT] DLL >>>>>>>>
2213 00:24:31.882957 [ANA_INIT] DLL <<<<<<<<
2214 00:24:31.883031 [ANA_INIT] flow end
2215 00:24:31.889498 ============ LP4 DIFF to SE enter ============
2216 00:24:31.892719 ============ LP4 DIFF to SE exit ============
2217 00:24:31.895998 [ANA_INIT] <<<<<<<<<<<<<
2218 00:24:31.899605 [Flow] Enable top DCM control >>>>>
2219 00:24:31.902971 [Flow] Enable top DCM control <<<<<
2220 00:24:31.906139 Enable DLL master slave shuffle
2221 00:24:31.909218 ==============================================================
2222 00:24:31.912773 Gating Mode config
2223 00:24:31.916090 ==============================================================
2224 00:24:31.919746 Config description:
2225 00:24:31.929641 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2226 00:24:31.936276 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2227 00:24:31.939541 SELPH_MODE 0: By rank 1: By Phase
2228 00:24:31.946161 ==============================================================
2229 00:24:31.949526 GAT_TRACK_EN = 1
2230 00:24:31.952719 RX_GATING_MODE = 2
2231 00:24:31.956275 RX_GATING_TRACK_MODE = 2
2232 00:24:31.959595 SELPH_MODE = 1
2233 00:24:31.959669 PICG_EARLY_EN = 1
2234 00:24:31.962840 VALID_LAT_VALUE = 1
2235 00:24:31.969503 ==============================================================
2236 00:24:31.973269 Enter into Gating configuration >>>>
2237 00:24:31.976399 Exit from Gating configuration <<<<
2238 00:24:31.979195 Enter into DVFS_PRE_config >>>>>
2239 00:24:31.989605 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2240 00:24:31.992858 Exit from DVFS_PRE_config <<<<<
2241 00:24:31.996116 Enter into PICG configuration >>>>
2242 00:24:31.999320 Exit from PICG configuration <<<<
2243 00:24:32.002879 [RX_INPUT] configuration >>>>>
2244 00:24:32.005938 [RX_INPUT] configuration <<<<<
2245 00:24:32.009928 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2246 00:24:32.016273 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2247 00:24:32.022984 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 00:24:32.029103 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 00:24:32.036058 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 00:24:32.039129 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 00:24:32.045733 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2252 00:24:32.049170 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2253 00:24:32.052560 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2254 00:24:32.056625 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2255 00:24:32.059083 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2256 00:24:32.066178 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2257 00:24:32.069244 ===================================
2258 00:24:32.072494 LPDDR4 DRAM CONFIGURATION
2259 00:24:32.075681 ===================================
2260 00:24:32.075770 EX_ROW_EN[0] = 0x0
2261 00:24:32.079646 EX_ROW_EN[1] = 0x0
2262 00:24:32.079722 LP4Y_EN = 0x0
2263 00:24:32.082903 WORK_FSP = 0x0
2264 00:24:32.083018 WL = 0x4
2265 00:24:32.086043 RL = 0x4
2266 00:24:32.086134 BL = 0x2
2267 00:24:32.089040 RPST = 0x0
2268 00:24:32.089139 RD_PRE = 0x0
2269 00:24:32.092607 WR_PRE = 0x1
2270 00:24:32.092679 WR_PST = 0x0
2271 00:24:32.095918 DBI_WR = 0x0
2272 00:24:32.095992 DBI_RD = 0x0
2273 00:24:32.099440 OTF = 0x1
2274 00:24:32.102887 ===================================
2275 00:24:32.105601 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2276 00:24:32.109098 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2277 00:24:32.115775 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2278 00:24:32.119052 ===================================
2279 00:24:32.119128 LPDDR4 DRAM CONFIGURATION
2280 00:24:32.122451 ===================================
2281 00:24:32.125925 EX_ROW_EN[0] = 0x10
2282 00:24:32.128988 EX_ROW_EN[1] = 0x0
2283 00:24:32.129059 LP4Y_EN = 0x0
2284 00:24:32.132507 WORK_FSP = 0x0
2285 00:24:32.132577 WL = 0x4
2286 00:24:32.136057 RL = 0x4
2287 00:24:32.136127 BL = 0x2
2288 00:24:32.138741 RPST = 0x0
2289 00:24:32.138809 RD_PRE = 0x0
2290 00:24:32.142102 WR_PRE = 0x1
2291 00:24:32.142172 WR_PST = 0x0
2292 00:24:32.145519 DBI_WR = 0x0
2293 00:24:32.145587 DBI_RD = 0x0
2294 00:24:32.148952 OTF = 0x1
2295 00:24:32.152413 ===================================
2296 00:24:32.159094 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2297 00:24:32.159170 ==
2298 00:24:32.162384 Dram Type= 6, Freq= 0, CH_0, rank 0
2299 00:24:32.165644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2300 00:24:32.165719 ==
2301 00:24:32.168885 [Duty_Offset_Calibration]
2302 00:24:32.168956 B0:2 B1:0 CA:3
2303 00:24:32.169023
2304 00:24:32.172552 [DutyScan_Calibration_Flow] k_type=0
2305 00:24:32.182219
2306 00:24:32.182326 ==CLK 0==
2307 00:24:32.185951 Final CLK duty delay cell = 0
2308 00:24:32.189284 [0] MAX Duty = 5062%(X100), DQS PI = 12
2309 00:24:32.192840 [0] MIN Duty = 4906%(X100), DQS PI = 54
2310 00:24:32.192912 [0] AVG Duty = 4984%(X100)
2311 00:24:32.195781
2312 00:24:32.198938 CH0 CLK Duty spec in!! Max-Min= 156%
2313 00:24:32.202590 [DutyScan_Calibration_Flow] ====Done====
2314 00:24:32.202668
2315 00:24:32.205958 [DutyScan_Calibration_Flow] k_type=1
2316 00:24:32.221159
2317 00:24:32.221236 ==DQS 0 ==
2318 00:24:32.224720 Final DQS duty delay cell = 0
2319 00:24:32.227619 [0] MAX Duty = 5093%(X100), DQS PI = 28
2320 00:24:32.231255 [0] MIN Duty = 4907%(X100), DQS PI = 44
2321 00:24:32.234455 [0] AVG Duty = 5000%(X100)
2322 00:24:32.234527
2323 00:24:32.234588 ==DQS 1 ==
2324 00:24:32.237573 Final DQS duty delay cell = -4
2325 00:24:32.241004 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2326 00:24:32.244480 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2327 00:24:32.247844 [-4] AVG Duty = 4922%(X100)
2328 00:24:32.247914
2329 00:24:32.251347 CH0 DQS 0 Duty spec in!! Max-Min= 186%
2330 00:24:32.251438
2331 00:24:32.254207 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2332 00:24:32.257679 [DutyScan_Calibration_Flow] ====Done====
2333 00:24:32.257752
2334 00:24:32.261387 [DutyScan_Calibration_Flow] k_type=3
2335 00:24:32.278330
2336 00:24:32.278405 ==DQM 0 ==
2337 00:24:32.281609 Final DQM duty delay cell = 0
2338 00:24:32.285113 [0] MAX Duty = 5124%(X100), DQS PI = 28
2339 00:24:32.288663 [0] MIN Duty = 4876%(X100), DQS PI = 48
2340 00:24:32.288736 [0] AVG Duty = 5000%(X100)
2341 00:24:32.291673
2342 00:24:32.291743 ==DQM 1 ==
2343 00:24:32.294894 Final DQM duty delay cell = 4
2344 00:24:32.298318 [4] MAX Duty = 5156%(X100), DQS PI = 50
2345 00:24:32.301815 [4] MIN Duty = 5031%(X100), DQS PI = 12
2346 00:24:32.304791 [4] AVG Duty = 5093%(X100)
2347 00:24:32.304867
2348 00:24:32.308534 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2349 00:24:32.308605
2350 00:24:32.311932 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2351 00:24:32.315349 [DutyScan_Calibration_Flow] ====Done====
2352 00:24:32.315440
2353 00:24:32.318625 [DutyScan_Calibration_Flow] k_type=2
2354 00:24:32.333454
2355 00:24:32.333546 ==DQ 0 ==
2356 00:24:32.336855 Final DQ duty delay cell = -4
2357 00:24:32.340056 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2358 00:24:32.343280 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2359 00:24:32.346430 [-4] AVG Duty = 4969%(X100)
2360 00:24:32.346506
2361 00:24:32.346568 ==DQ 1 ==
2362 00:24:32.349889 Final DQ duty delay cell = -4
2363 00:24:32.353107 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2364 00:24:32.357242 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2365 00:24:32.359931 [-4] AVG Duty = 4938%(X100)
2366 00:24:32.360014
2367 00:24:32.363256 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2368 00:24:32.363355
2369 00:24:32.366763 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2370 00:24:32.370309 [DutyScan_Calibration_Flow] ====Done====
2371 00:24:32.370387 ==
2372 00:24:32.373498 Dram Type= 6, Freq= 0, CH_1, rank 0
2373 00:24:32.376605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2374 00:24:32.376677 ==
2375 00:24:32.380071 [Duty_Offset_Calibration]
2376 00:24:32.380149 B0:1 B1:-2 CA:0
2377 00:24:32.380211
2378 00:24:32.383324 [DutyScan_Calibration_Flow] k_type=0
2379 00:24:32.393922
2380 00:24:32.394017 ==CLK 0==
2381 00:24:32.397117 Final CLK duty delay cell = 0
2382 00:24:32.400516 [0] MAX Duty = 5062%(X100), DQS PI = 30
2383 00:24:32.404266 [0] MIN Duty = 4876%(X100), DQS PI = 2
2384 00:24:32.404346 [0] AVG Duty = 4969%(X100)
2385 00:24:32.407578
2386 00:24:32.410414 CH1 CLK Duty spec in!! Max-Min= 186%
2387 00:24:32.413946 [DutyScan_Calibration_Flow] ====Done====
2388 00:24:32.414026
2389 00:24:32.417000 [DutyScan_Calibration_Flow] k_type=1
2390 00:24:32.432177
2391 00:24:32.432259 ==DQS 0 ==
2392 00:24:32.436044 Final DQS duty delay cell = -4
2393 00:24:32.439162 [-4] MAX Duty = 5000%(X100), DQS PI = 22
2394 00:24:32.442156 [-4] MIN Duty = 4907%(X100), DQS PI = 4
2395 00:24:32.445549 [-4] AVG Duty = 4953%(X100)
2396 00:24:32.445648
2397 00:24:32.445745 ==DQS 1 ==
2398 00:24:32.449111 Final DQS duty delay cell = 0
2399 00:24:32.452265 [0] MAX Duty = 5093%(X100), DQS PI = 0
2400 00:24:32.455701 [0] MIN Duty = 4844%(X100), DQS PI = 26
2401 00:24:32.459049 [0] AVG Duty = 4968%(X100)
2402 00:24:32.459123
2403 00:24:32.462277 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2404 00:24:32.462349
2405 00:24:32.465693 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2406 00:24:32.469037 [DutyScan_Calibration_Flow] ====Done====
2407 00:24:32.469110
2408 00:24:32.472540 [DutyScan_Calibration_Flow] k_type=3
2409 00:24:32.488985
2410 00:24:32.489071 ==DQM 0 ==
2411 00:24:32.492586 Final DQM duty delay cell = 0
2412 00:24:32.495380 [0] MAX Duty = 5000%(X100), DQS PI = 22
2413 00:24:32.499266 [0] MIN Duty = 4844%(X100), DQS PI = 58
2414 00:24:32.499345 [0] AVG Duty = 4922%(X100)
2415 00:24:32.502530
2416 00:24:32.502601 ==DQM 1 ==
2417 00:24:32.505848 Final DQM duty delay cell = 0
2418 00:24:32.508890 [0] MAX Duty = 5031%(X100), DQS PI = 36
2419 00:24:32.512442 [0] MIN Duty = 4907%(X100), DQS PI = 0
2420 00:24:32.512541 [0] AVG Duty = 4969%(X100)
2421 00:24:32.515786
2422 00:24:32.519129 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2423 00:24:32.519237
2424 00:24:32.522218 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2425 00:24:32.525872 [DutyScan_Calibration_Flow] ====Done====
2426 00:24:32.525980
2427 00:24:32.528866 [DutyScan_Calibration_Flow] k_type=2
2428 00:24:32.545300
2429 00:24:32.545434 ==DQ 0 ==
2430 00:24:32.549095 Final DQ duty delay cell = 0
2431 00:24:32.552205 [0] MAX Duty = 5062%(X100), DQS PI = 12
2432 00:24:32.555338 [0] MIN Duty = 4938%(X100), DQS PI = 54
2433 00:24:32.555486 [0] AVG Duty = 5000%(X100)
2434 00:24:32.555586
2435 00:24:32.558918 ==DQ 1 ==
2436 00:24:32.562044 Final DQ duty delay cell = 0
2437 00:24:32.565300 [0] MAX Duty = 5125%(X100), DQS PI = 36
2438 00:24:32.569460 [0] MIN Duty = 4969%(X100), DQS PI = 26
2439 00:24:32.569546 [0] AVG Duty = 5047%(X100)
2440 00:24:32.569612
2441 00:24:32.572018 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2442 00:24:32.572092
2443 00:24:32.578673 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2444 00:24:32.581779 [DutyScan_Calibration_Flow] ====Done====
2445 00:24:32.585260 nWR fixed to 30
2446 00:24:32.585345 [ModeRegInit_LP4] CH0 RK0
2447 00:24:32.588770 [ModeRegInit_LP4] CH0 RK1
2448 00:24:32.592354 [ModeRegInit_LP4] CH1 RK0
2449 00:24:32.592443 [ModeRegInit_LP4] CH1 RK1
2450 00:24:32.595595 match AC timing 7
2451 00:24:32.598946 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2452 00:24:32.602570 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2453 00:24:32.608531 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2454 00:24:32.611989 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2455 00:24:32.618579 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2456 00:24:32.618703 ==
2457 00:24:32.621805 Dram Type= 6, Freq= 0, CH_0, rank 0
2458 00:24:32.625338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2459 00:24:32.625421 ==
2460 00:24:32.632197 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2461 00:24:32.635266 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2462 00:24:32.645238 [CA 0] Center 40 (10~71) winsize 62
2463 00:24:32.648683 [CA 1] Center 39 (9~70) winsize 62
2464 00:24:32.652175 [CA 2] Center 36 (6~66) winsize 61
2465 00:24:32.655713 [CA 3] Center 35 (5~66) winsize 62
2466 00:24:32.659235 [CA 4] Center 34 (4~65) winsize 62
2467 00:24:32.662535 [CA 5] Center 33 (3~63) winsize 61
2468 00:24:32.662616
2469 00:24:32.665295 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2470 00:24:32.665372
2471 00:24:32.669119 [CATrainingPosCal] consider 1 rank data
2472 00:24:32.672022 u2DelayCellTimex100 = 270/100 ps
2473 00:24:32.675475 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2474 00:24:32.682061 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2475 00:24:32.685105 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2476 00:24:32.688713 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2477 00:24:32.692021 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2478 00:24:32.695277 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2479 00:24:32.695352
2480 00:24:32.698945 CA PerBit enable=1, Macro0, CA PI delay=33
2481 00:24:32.699050
2482 00:24:32.702028 [CBTSetCACLKResult] CA Dly = 33
2483 00:24:32.702104 CS Dly: 7 (0~38)
2484 00:24:32.705621 ==
2485 00:24:32.705694 Dram Type= 6, Freq= 0, CH_0, rank 1
2486 00:24:32.712054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2487 00:24:32.712149 ==
2488 00:24:32.715572 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2489 00:24:32.721885 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2490 00:24:32.731588 [CA 0] Center 40 (10~71) winsize 62
2491 00:24:32.734898 [CA 1] Center 39 (9~70) winsize 62
2492 00:24:32.738173 [CA 2] Center 35 (5~66) winsize 62
2493 00:24:32.741263 [CA 3] Center 35 (5~66) winsize 62
2494 00:24:32.744702 [CA 4] Center 34 (4~65) winsize 62
2495 00:24:32.748277 [CA 5] Center 33 (3~63) winsize 61
2496 00:24:32.748360
2497 00:24:32.751882 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2498 00:24:32.751963
2499 00:24:32.755039 [CATrainingPosCal] consider 2 rank data
2500 00:24:32.758159 u2DelayCellTimex100 = 270/100 ps
2501 00:24:32.761601 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2502 00:24:32.768678 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2503 00:24:32.771394 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2504 00:24:32.774668 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2505 00:24:32.778270 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2506 00:24:32.781567 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2507 00:24:32.781654
2508 00:24:32.785281 CA PerBit enable=1, Macro0, CA PI delay=33
2509 00:24:32.785418
2510 00:24:32.788290 [CBTSetCACLKResult] CA Dly = 33
2511 00:24:32.788368 CS Dly: 7 (0~39)
2512 00:24:32.791716
2513 00:24:32.794800 ----->DramcWriteLeveling(PI) begin...
2514 00:24:32.794877 ==
2515 00:24:32.798077 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 00:24:32.801059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 00:24:32.801135 ==
2518 00:24:32.804410 Write leveling (Byte 0): 33 => 33
2519 00:24:32.807856 Write leveling (Byte 1): 30 => 30
2520 00:24:32.811060 DramcWriteLeveling(PI) end<-----
2521 00:24:32.811135
2522 00:24:32.811208 ==
2523 00:24:32.814396 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 00:24:32.817676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 00:24:32.817754 ==
2526 00:24:32.821413 [Gating] SW mode calibration
2527 00:24:32.827515 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2528 00:24:32.834432 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2529 00:24:32.837849 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 00:24:32.841505 0 15 4 | B1->B0 | 2a2a 3434 | 1 0 | (0 0) (0 0)
2531 00:24:32.847665 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 00:24:32.851118 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 00:24:32.854503 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 00:24:32.860964 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 00:24:32.864811 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 00:24:32.867861 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2537 00:24:32.871273 1 0 0 | B1->B0 | 3232 2a2a | 1 0 | (1 0) (0 0)
2538 00:24:32.878452 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 00:24:32.881636 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 00:24:32.884349 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 00:24:32.891223 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 00:24:32.894484 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 00:24:32.898067 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 00:24:32.904578 1 0 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2545 00:24:32.907941 1 1 0 | B1->B0 | 2424 2f2e | 0 1 | (0 0) (1 1)
2546 00:24:32.911473 1 1 4 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
2547 00:24:32.918049 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 00:24:32.921173 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 00:24:32.924450 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 00:24:32.931016 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 00:24:32.934635 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 00:24:32.938216 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2553 00:24:32.944707 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2554 00:24:32.947967 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 00:24:32.951299 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 00:24:32.958076 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 00:24:32.960940 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 00:24:32.964767 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 00:24:32.967941 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 00:24:32.974671 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 00:24:32.977940 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 00:24:32.981193 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 00:24:32.988127 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 00:24:32.991049 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 00:24:32.994508 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 00:24:33.001486 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 00:24:33.004525 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 00:24:33.008258 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2569 00:24:33.014928 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2570 00:24:33.017784 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2571 00:24:33.021265 Total UI for P1: 0, mck2ui 16
2572 00:24:33.024734 best dqsien dly found for B0: ( 1, 3, 30)
2573 00:24:33.027868 Total UI for P1: 0, mck2ui 16
2574 00:24:33.031179 best dqsien dly found for B1: ( 1, 4, 0)
2575 00:24:33.034522 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2576 00:24:33.038417 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2577 00:24:33.038490
2578 00:24:33.041182 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2579 00:24:33.044926 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2580 00:24:33.048324 [Gating] SW calibration Done
2581 00:24:33.048403 ==
2582 00:24:33.051170 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 00:24:33.054467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 00:24:33.054541 ==
2585 00:24:33.057774 RX Vref Scan: 0
2586 00:24:33.057903
2587 00:24:33.061070 RX Vref 0 -> 0, step: 1
2588 00:24:33.061178
2589 00:24:33.061268 RX Delay -40 -> 252, step: 8
2590 00:24:33.068076 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2591 00:24:33.071173 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2592 00:24:33.074452 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2593 00:24:33.077936 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2594 00:24:33.081683 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2595 00:24:33.084655 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2596 00:24:33.091605 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2597 00:24:33.094666 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2598 00:24:33.098269 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2599 00:24:33.101624 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2600 00:24:33.104763 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2601 00:24:33.111504 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2602 00:24:33.114484 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2603 00:24:33.117919 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2604 00:24:33.121473 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2605 00:24:33.124814 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2606 00:24:33.124896 ==
2607 00:24:33.128254 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 00:24:33.135260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2609 00:24:33.135367 ==
2610 00:24:33.135460 DQS Delay:
2611 00:24:33.138917 DQS0 = 0, DQS1 = 0
2612 00:24:33.138998 DQM Delay:
2613 00:24:33.141653 DQM0 = 112, DQM1 = 103
2614 00:24:33.141722 DQ Delay:
2615 00:24:33.145226 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2616 00:24:33.148299 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2617 00:24:33.151971 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
2618 00:24:33.155252 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2619 00:24:33.155375
2620 00:24:33.155455
2621 00:24:33.155516 ==
2622 00:24:33.158260 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 00:24:33.161463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 00:24:33.164912 ==
2625 00:24:33.164988
2626 00:24:33.165062
2627 00:24:33.165123 TX Vref Scan disable
2628 00:24:33.168269 == TX Byte 0 ==
2629 00:24:33.171553 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2630 00:24:33.175049 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2631 00:24:33.178526 == TX Byte 1 ==
2632 00:24:33.181708 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2633 00:24:33.184993 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2634 00:24:33.185072 ==
2635 00:24:33.188525 Dram Type= 6, Freq= 0, CH_0, rank 0
2636 00:24:33.194916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2637 00:24:33.194996 ==
2638 00:24:33.206145 TX Vref=22, minBit 6, minWin=25, winSum=413
2639 00:24:33.209577 TX Vref=24, minBit 1, minWin=26, winSum=425
2640 00:24:33.212521 TX Vref=26, minBit 3, minWin=26, winSum=426
2641 00:24:33.215618 TX Vref=28, minBit 7, minWin=26, winSum=433
2642 00:24:33.219209 TX Vref=30, minBit 6, minWin=26, winSum=433
2643 00:24:33.222554 TX Vref=32, minBit 2, minWin=26, winSum=429
2644 00:24:33.229034 [TxChooseVref] Worse bit 7, Min win 26, Win sum 433, Final Vref 28
2645 00:24:33.229120
2646 00:24:33.232650 Final TX Range 1 Vref 28
2647 00:24:33.232725
2648 00:24:33.232788 ==
2649 00:24:33.235870 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 00:24:33.239292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 00:24:33.239416 ==
2652 00:24:33.239481
2653 00:24:33.242234
2654 00:24:33.242316 TX Vref Scan disable
2655 00:24:33.245725 == TX Byte 0 ==
2656 00:24:33.249129 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2657 00:24:33.252645 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2658 00:24:33.256065 == TX Byte 1 ==
2659 00:24:33.258925 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2660 00:24:33.262361 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2661 00:24:33.262438
2662 00:24:33.265665 [DATLAT]
2663 00:24:33.265737 Freq=1200, CH0 RK0
2664 00:24:33.265798
2665 00:24:33.269049 DATLAT Default: 0xd
2666 00:24:33.269131 0, 0xFFFF, sum = 0
2667 00:24:33.272536 1, 0xFFFF, sum = 0
2668 00:24:33.272610 2, 0xFFFF, sum = 0
2669 00:24:33.275714 3, 0xFFFF, sum = 0
2670 00:24:33.275785 4, 0xFFFF, sum = 0
2671 00:24:33.279226 5, 0xFFFF, sum = 0
2672 00:24:33.279327 6, 0xFFFF, sum = 0
2673 00:24:33.282645 7, 0xFFFF, sum = 0
2674 00:24:33.285660 8, 0xFFFF, sum = 0
2675 00:24:33.285742 9, 0xFFFF, sum = 0
2676 00:24:33.288921 10, 0xFFFF, sum = 0
2677 00:24:33.288998 11, 0xFFFF, sum = 0
2678 00:24:33.292082 12, 0x0, sum = 1
2679 00:24:33.292160 13, 0x0, sum = 2
2680 00:24:33.295495 14, 0x0, sum = 3
2681 00:24:33.295569 15, 0x0, sum = 4
2682 00:24:33.295632 best_step = 13
2683 00:24:33.295692
2684 00:24:33.298841 ==
2685 00:24:33.302095 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 00:24:33.305469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 00:24:33.305545 ==
2688 00:24:33.305614 RX Vref Scan: 1
2689 00:24:33.305675
2690 00:24:33.309237 Set Vref Range= 32 -> 127
2691 00:24:33.309308
2692 00:24:33.312299 RX Vref 32 -> 127, step: 1
2693 00:24:33.312376
2694 00:24:33.315871 RX Delay -37 -> 252, step: 4
2695 00:24:33.315952
2696 00:24:33.318815 Set Vref, RX VrefLevel [Byte0]: 32
2697 00:24:33.322326 [Byte1]: 32
2698 00:24:33.322427
2699 00:24:33.325472 Set Vref, RX VrefLevel [Byte0]: 33
2700 00:24:33.329042 [Byte1]: 33
2701 00:24:33.332234
2702 00:24:33.332310 Set Vref, RX VrefLevel [Byte0]: 34
2703 00:24:33.335791 [Byte1]: 34
2704 00:24:33.340086
2705 00:24:33.340164 Set Vref, RX VrefLevel [Byte0]: 35
2706 00:24:33.343344 [Byte1]: 35
2707 00:24:33.348005
2708 00:24:33.348082 Set Vref, RX VrefLevel [Byte0]: 36
2709 00:24:33.351488 [Byte1]: 36
2710 00:24:33.356106
2711 00:24:33.356182 Set Vref, RX VrefLevel [Byte0]: 37
2712 00:24:33.359591 [Byte1]: 37
2713 00:24:33.364358
2714 00:24:33.364435 Set Vref, RX VrefLevel [Byte0]: 38
2715 00:24:33.367460 [Byte1]: 38
2716 00:24:33.372489
2717 00:24:33.372580 Set Vref, RX VrefLevel [Byte0]: 39
2718 00:24:33.375245 [Byte1]: 39
2719 00:24:33.380202
2720 00:24:33.380280 Set Vref, RX VrefLevel [Byte0]: 40
2721 00:24:33.383774 [Byte1]: 40
2722 00:24:33.388372
2723 00:24:33.388449 Set Vref, RX VrefLevel [Byte0]: 41
2724 00:24:33.391940 [Byte1]: 41
2725 00:24:33.396348
2726 00:24:33.396423 Set Vref, RX VrefLevel [Byte0]: 42
2727 00:24:33.399478 [Byte1]: 42
2728 00:24:33.404187
2729 00:24:33.404261 Set Vref, RX VrefLevel [Byte0]: 43
2730 00:24:33.407565 [Byte1]: 43
2731 00:24:33.411935
2732 00:24:33.412033 Set Vref, RX VrefLevel [Byte0]: 44
2733 00:24:33.415647 [Byte1]: 44
2734 00:24:33.420049
2735 00:24:33.420151 Set Vref, RX VrefLevel [Byte0]: 45
2736 00:24:33.423460 [Byte1]: 45
2737 00:24:33.428226
2738 00:24:33.428306 Set Vref, RX VrefLevel [Byte0]: 46
2739 00:24:33.431580 [Byte1]: 46
2740 00:24:33.436360
2741 00:24:33.436459 Set Vref, RX VrefLevel [Byte0]: 47
2742 00:24:33.439392 [Byte1]: 47
2743 00:24:33.444089
2744 00:24:33.444192 Set Vref, RX VrefLevel [Byte0]: 48
2745 00:24:33.447212 [Byte1]: 48
2746 00:24:33.452298
2747 00:24:33.452414 Set Vref, RX VrefLevel [Byte0]: 49
2748 00:24:33.455308 [Byte1]: 49
2749 00:24:33.460080
2750 00:24:33.460183 Set Vref, RX VrefLevel [Byte0]: 50
2751 00:24:33.463650 [Byte1]: 50
2752 00:24:33.468293
2753 00:24:33.468410 Set Vref, RX VrefLevel [Byte0]: 51
2754 00:24:33.471622 [Byte1]: 51
2755 00:24:33.476210
2756 00:24:33.476286 Set Vref, RX VrefLevel [Byte0]: 52
2757 00:24:33.479568 [Byte1]: 52
2758 00:24:33.484550
2759 00:24:33.484634 Set Vref, RX VrefLevel [Byte0]: 53
2760 00:24:33.487388 [Byte1]: 53
2761 00:24:33.492713
2762 00:24:33.492790 Set Vref, RX VrefLevel [Byte0]: 54
2763 00:24:33.495456 [Byte1]: 54
2764 00:24:33.500398
2765 00:24:33.500477 Set Vref, RX VrefLevel [Byte0]: 55
2766 00:24:33.503693 [Byte1]: 55
2767 00:24:33.508476
2768 00:24:33.508551 Set Vref, RX VrefLevel [Byte0]: 56
2769 00:24:33.511461 [Byte1]: 56
2770 00:24:33.516140
2771 00:24:33.516222 Set Vref, RX VrefLevel [Byte0]: 57
2772 00:24:33.519543 [Byte1]: 57
2773 00:24:33.523946
2774 00:24:33.524021 Set Vref, RX VrefLevel [Byte0]: 58
2775 00:24:33.527502 [Byte1]: 58
2776 00:24:33.532069
2777 00:24:33.532173 Set Vref, RX VrefLevel [Byte0]: 59
2778 00:24:33.535682 [Byte1]: 59
2779 00:24:33.540074
2780 00:24:33.540151 Set Vref, RX VrefLevel [Byte0]: 60
2781 00:24:33.543502 [Byte1]: 60
2782 00:24:33.548270
2783 00:24:33.548344 Set Vref, RX VrefLevel [Byte0]: 61
2784 00:24:33.551611 [Byte1]: 61
2785 00:24:33.556072
2786 00:24:33.556155 Set Vref, RX VrefLevel [Byte0]: 62
2787 00:24:33.559484 [Byte1]: 62
2788 00:24:33.564405
2789 00:24:33.564486 Set Vref, RX VrefLevel [Byte0]: 63
2790 00:24:33.567421 [Byte1]: 63
2791 00:24:33.572144
2792 00:24:33.572226 Set Vref, RX VrefLevel [Byte0]: 64
2793 00:24:33.575452 [Byte1]: 64
2794 00:24:33.580247
2795 00:24:33.580326 Set Vref, RX VrefLevel [Byte0]: 65
2796 00:24:33.583518 [Byte1]: 65
2797 00:24:33.588532
2798 00:24:33.588622 Set Vref, RX VrefLevel [Byte0]: 66
2799 00:24:33.591852 [Byte1]: 66
2800 00:24:33.596365
2801 00:24:33.596447 Set Vref, RX VrefLevel [Byte0]: 67
2802 00:24:33.600049 [Byte1]: 67
2803 00:24:33.603975
2804 00:24:33.604051 Set Vref, RX VrefLevel [Byte0]: 68
2805 00:24:33.607723 [Byte1]: 68
2806 00:24:33.612458
2807 00:24:33.612559 Set Vref, RX VrefLevel [Byte0]: 69
2808 00:24:33.615314 [Byte1]: 69
2809 00:24:33.620366
2810 00:24:33.620441 Set Vref, RX VrefLevel [Byte0]: 70
2811 00:24:33.623269 [Byte1]: 70
2812 00:24:33.627955
2813 00:24:33.628032 Set Vref, RX VrefLevel [Byte0]: 71
2814 00:24:33.631392 [Byte1]: 71
2815 00:24:33.636434
2816 00:24:33.636535 Set Vref, RX VrefLevel [Byte0]: 72
2817 00:24:33.639494 [Byte1]: 72
2818 00:24:33.643987
2819 00:24:33.644066 Set Vref, RX VrefLevel [Byte0]: 73
2820 00:24:33.647352 [Byte1]: 73
2821 00:24:33.651991
2822 00:24:33.652092 Set Vref, RX VrefLevel [Byte0]: 74
2823 00:24:33.655839 [Byte1]: 74
2824 00:24:33.660435
2825 00:24:33.660538 Final RX Vref Byte 0 = 61 to rank0
2826 00:24:33.663864 Final RX Vref Byte 1 = 54 to rank0
2827 00:24:33.666755 Final RX Vref Byte 0 = 61 to rank1
2828 00:24:33.670305 Final RX Vref Byte 1 = 54 to rank1==
2829 00:24:33.673841 Dram Type= 6, Freq= 0, CH_0, rank 0
2830 00:24:33.680205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2831 00:24:33.680294 ==
2832 00:24:33.680361 DQS Delay:
2833 00:24:33.680456 DQS0 = 0, DQS1 = 0
2834 00:24:33.683822 DQM Delay:
2835 00:24:33.683895 DQM0 = 112, DQM1 = 101
2836 00:24:33.686969 DQ Delay:
2837 00:24:33.690544 DQ0 =112, DQ1 =112, DQ2 =112, DQ3 =108
2838 00:24:33.693604 DQ4 =112, DQ5 =104, DQ6 =120, DQ7 =120
2839 00:24:33.696986 DQ8 =92, DQ9 =86, DQ10 =104, DQ11 =94
2840 00:24:33.700151 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2841 00:24:33.700247
2842 00:24:33.700315
2843 00:24:33.706886 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdfd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
2844 00:24:33.709986 CH0 RK0: MR19=303, MR18=FDFD
2845 00:24:33.717162 CH0_RK0: MR19=0x303, MR18=0xFDFD, DQSOSC=411, MR23=63, INC=38, DEC=25
2846 00:24:33.717243
2847 00:24:33.720138 ----->DramcWriteLeveling(PI) begin...
2848 00:24:33.720231 ==
2849 00:24:33.723366 Dram Type= 6, Freq= 0, CH_0, rank 1
2850 00:24:33.726482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2851 00:24:33.729766 ==
2852 00:24:33.729843 Write leveling (Byte 0): 33 => 33
2853 00:24:33.733224 Write leveling (Byte 1): 28 => 28
2854 00:24:33.736484 DramcWriteLeveling(PI) end<-----
2855 00:24:33.736561
2856 00:24:33.736647 ==
2857 00:24:33.739757 Dram Type= 6, Freq= 0, CH_0, rank 1
2858 00:24:33.746738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2859 00:24:33.746842 ==
2860 00:24:33.746933 [Gating] SW mode calibration
2861 00:24:33.757265 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2862 00:24:33.759861 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2863 00:24:33.766521 0 15 0 | B1->B0 | 2929 3434 | 1 1 | (1 1) (0 0)
2864 00:24:33.770395 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 00:24:33.773670 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 00:24:33.776373 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2867 00:24:33.783243 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2868 00:24:33.786714 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2869 00:24:33.789753 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
2870 00:24:33.796741 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
2871 00:24:33.799896 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2872 00:24:33.802819 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 00:24:33.809538 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 00:24:33.813162 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2875 00:24:33.816522 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 00:24:33.823223 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2877 00:24:33.826364 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2878 00:24:33.829932 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2879 00:24:33.836601 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2880 00:24:33.839847 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 00:24:33.843385 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 00:24:33.849709 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 00:24:33.852902 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 00:24:33.856293 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 00:24:33.863160 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2886 00:24:33.866887 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2887 00:24:33.870148 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2888 00:24:33.876204 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 00:24:33.879799 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 00:24:33.883130 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 00:24:33.886620 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 00:24:33.893005 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 00:24:33.896651 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 00:24:33.899622 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 00:24:33.906425 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 00:24:33.909677 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 00:24:33.913250 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 00:24:33.919458 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 00:24:33.923200 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 00:24:33.926236 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 00:24:33.933045 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 00:24:33.936713 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2903 00:24:33.939487 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2904 00:24:33.942611 Total UI for P1: 0, mck2ui 16
2905 00:24:33.945989 best dqsien dly found for B0: ( 1, 3, 28)
2906 00:24:33.952607 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 00:24:33.952687 Total UI for P1: 0, mck2ui 16
2908 00:24:33.959773 best dqsien dly found for B1: ( 1, 4, 0)
2909 00:24:33.963233 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2910 00:24:33.966057 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2911 00:24:33.966143
2912 00:24:33.969492 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2913 00:24:33.973112 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2914 00:24:33.976638 [Gating] SW calibration Done
2915 00:24:33.976715 ==
2916 00:24:33.979848 Dram Type= 6, Freq= 0, CH_0, rank 1
2917 00:24:33.983374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2918 00:24:33.983495 ==
2919 00:24:33.986514 RX Vref Scan: 0
2920 00:24:33.986627
2921 00:24:33.986719 RX Vref 0 -> 0, step: 1
2922 00:24:33.986806
2923 00:24:33.989510 RX Delay -40 -> 252, step: 8
2924 00:24:33.992923 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2925 00:24:33.996619 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2926 00:24:34.002778 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2927 00:24:34.006213 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2928 00:24:34.009408 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2929 00:24:34.012787 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2930 00:24:34.016047 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2931 00:24:34.022949 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2932 00:24:34.026111 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2933 00:24:34.029824 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2934 00:24:34.032729 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2935 00:24:34.036085 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2936 00:24:34.039465 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2937 00:24:34.046407 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2938 00:24:34.049752 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2939 00:24:34.053252 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2940 00:24:34.053333 ==
2941 00:24:34.056447 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 00:24:34.059901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 00:24:34.063008 ==
2944 00:24:34.063112 DQS Delay:
2945 00:24:34.063216 DQS0 = 0, DQS1 = 0
2946 00:24:34.066296 DQM Delay:
2947 00:24:34.066394 DQM0 = 111, DQM1 = 101
2948 00:24:34.069914 DQ Delay:
2949 00:24:34.073372 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2950 00:24:34.076930 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =119
2951 00:24:34.080037 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2952 00:24:34.083046 DQ12 =107, DQ13 =111, DQ14 =111, DQ15 =107
2953 00:24:34.083123
2954 00:24:34.083185
2955 00:24:34.083244 ==
2956 00:24:34.086322 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 00:24:34.089561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 00:24:34.089636 ==
2959 00:24:34.089704
2960 00:24:34.089763
2961 00:24:34.093132 TX Vref Scan disable
2962 00:24:34.096570 == TX Byte 0 ==
2963 00:24:34.099503 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2964 00:24:34.102940 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2965 00:24:34.106510 == TX Byte 1 ==
2966 00:24:34.110009 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2967 00:24:34.113168 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2968 00:24:34.113287 ==
2969 00:24:34.116554 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 00:24:34.119762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 00:24:34.122675 ==
2972 00:24:34.133292 TX Vref=22, minBit 1, minWin=26, winSum=424
2973 00:24:34.136597 TX Vref=24, minBit 1, minWin=26, winSum=426
2974 00:24:34.140113 TX Vref=26, minBit 8, minWin=26, winSum=432
2975 00:24:34.143420 TX Vref=28, minBit 9, minWin=26, winSum=435
2976 00:24:34.146702 TX Vref=30, minBit 8, minWin=25, winSum=435
2977 00:24:34.150286 TX Vref=32, minBit 8, minWin=26, winSum=436
2978 00:24:34.156595 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 32
2979 00:24:34.156676
2980 00:24:34.159973 Final TX Range 1 Vref 32
2981 00:24:34.160055
2982 00:24:34.160119 ==
2983 00:24:34.163410 Dram Type= 6, Freq= 0, CH_0, rank 1
2984 00:24:34.166812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2985 00:24:34.166919 ==
2986 00:24:34.167010
2987 00:24:34.170112
2988 00:24:34.170192 TX Vref Scan disable
2989 00:24:34.173440 == TX Byte 0 ==
2990 00:24:34.176909 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2991 00:24:34.179882 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2992 00:24:34.183746 == TX Byte 1 ==
2993 00:24:34.186688 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2994 00:24:34.190034 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2995 00:24:34.190143
2996 00:24:34.193714 [DATLAT]
2997 00:24:34.193793 Freq=1200, CH0 RK1
2998 00:24:34.193856
2999 00:24:34.197242 DATLAT Default: 0xd
3000 00:24:34.197310 0, 0xFFFF, sum = 0
3001 00:24:34.200062 1, 0xFFFF, sum = 0
3002 00:24:34.200165 2, 0xFFFF, sum = 0
3003 00:24:34.204063 3, 0xFFFF, sum = 0
3004 00:24:34.204138 4, 0xFFFF, sum = 0
3005 00:24:34.206751 5, 0xFFFF, sum = 0
3006 00:24:34.206826 6, 0xFFFF, sum = 0
3007 00:24:34.210222 7, 0xFFFF, sum = 0
3008 00:24:34.210321 8, 0xFFFF, sum = 0
3009 00:24:34.213343 9, 0xFFFF, sum = 0
3010 00:24:34.216743 10, 0xFFFF, sum = 0
3011 00:24:34.216817 11, 0xFFFF, sum = 0
3012 00:24:34.220236 12, 0x0, sum = 1
3013 00:24:34.220318 13, 0x0, sum = 2
3014 00:24:34.220383 14, 0x0, sum = 3
3015 00:24:34.223628 15, 0x0, sum = 4
3016 00:24:34.223708 best_step = 13
3017 00:24:34.223791
3018 00:24:34.223852 ==
3019 00:24:34.227140 Dram Type= 6, Freq= 0, CH_0, rank 1
3020 00:24:34.233395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3021 00:24:34.233498 ==
3022 00:24:34.233595 RX Vref Scan: 0
3023 00:24:34.233696
3024 00:24:34.236717 RX Vref 0 -> 0, step: 1
3025 00:24:34.236804
3026 00:24:34.240381 RX Delay -37 -> 252, step: 4
3027 00:24:34.243660 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3028 00:24:34.246969 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3029 00:24:34.253381 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3030 00:24:34.257011 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3031 00:24:34.260257 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3032 00:24:34.263500 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3033 00:24:34.266483 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3034 00:24:34.273301 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3035 00:24:34.276641 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3036 00:24:34.280028 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3037 00:24:34.283462 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3038 00:24:34.286825 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3039 00:24:34.293523 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3040 00:24:34.296588 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3041 00:24:34.300007 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3042 00:24:34.303406 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3043 00:24:34.303501 ==
3044 00:24:34.306759 Dram Type= 6, Freq= 0, CH_0, rank 1
3045 00:24:34.313616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 00:24:34.313697 ==
3047 00:24:34.313761 DQS Delay:
3048 00:24:34.313820 DQS0 = 0, DQS1 = 0
3049 00:24:34.317170 DQM Delay:
3050 00:24:34.317250 DQM0 = 110, DQM1 = 101
3051 00:24:34.320014 DQ Delay:
3052 00:24:34.323563 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3053 00:24:34.327134 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3054 00:24:34.329906 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3055 00:24:34.333359 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3056 00:24:34.333440
3057 00:24:34.333503
3058 00:24:34.339951 [DQSOSCAuto] RK1, (LSB)MR18= 0x17ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 401 ps
3059 00:24:34.343831 CH0 RK1: MR19=403, MR18=17FF
3060 00:24:34.350169 CH0_RK1: MR19=0x403, MR18=0x17FF, DQSOSC=401, MR23=63, INC=40, DEC=27
3061 00:24:34.353466 [RxdqsGatingPostProcess] freq 1200
3062 00:24:34.360013 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3063 00:24:34.363301 best DQS0 dly(2T, 0.5T) = (0, 11)
3064 00:24:34.363448 best DQS1 dly(2T, 0.5T) = (0, 12)
3065 00:24:34.366515 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3066 00:24:34.370176 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3067 00:24:34.373516 best DQS0 dly(2T, 0.5T) = (0, 11)
3068 00:24:34.376374 best DQS1 dly(2T, 0.5T) = (0, 12)
3069 00:24:34.380241 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3070 00:24:34.383098 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3071 00:24:34.386523 Pre-setting of DQS Precalculation
3072 00:24:34.393446 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3073 00:24:34.393528 ==
3074 00:24:34.396431 Dram Type= 6, Freq= 0, CH_1, rank 0
3075 00:24:34.400639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 00:24:34.400720 ==
3077 00:24:34.406548 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3078 00:24:34.409841 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3079 00:24:34.419593 [CA 0] Center 37 (8~67) winsize 60
3080 00:24:34.422535 [CA 1] Center 37 (7~68) winsize 62
3081 00:24:34.426109 [CA 2] Center 34 (4~64) winsize 61
3082 00:24:34.429394 [CA 3] Center 33 (3~64) winsize 62
3083 00:24:34.432811 [CA 4] Center 34 (4~64) winsize 61
3084 00:24:34.436036 [CA 5] Center 33 (3~63) winsize 61
3085 00:24:34.436116
3086 00:24:34.439597 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3087 00:24:34.439678
3088 00:24:34.443188 [CATrainingPosCal] consider 1 rank data
3089 00:24:34.446255 u2DelayCellTimex100 = 270/100 ps
3090 00:24:34.449364 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3091 00:24:34.452755 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3092 00:24:34.459420 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3093 00:24:34.462882 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3094 00:24:34.466342 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3095 00:24:34.469504 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3096 00:24:34.469584
3097 00:24:34.472595 CA PerBit enable=1, Macro0, CA PI delay=33
3098 00:24:34.472676
3099 00:24:34.476072 [CBTSetCACLKResult] CA Dly = 33
3100 00:24:34.476152 CS Dly: 6 (0~37)
3101 00:24:34.476215 ==
3102 00:24:34.479604 Dram Type= 6, Freq= 0, CH_1, rank 1
3103 00:24:34.485770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 00:24:34.485852 ==
3105 00:24:34.489195 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3106 00:24:34.496216 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3107 00:24:34.505282 [CA 0] Center 37 (7~67) winsize 61
3108 00:24:34.508383 [CA 1] Center 37 (7~68) winsize 62
3109 00:24:34.511678 [CA 2] Center 34 (4~65) winsize 62
3110 00:24:34.515328 [CA 3] Center 33 (3~64) winsize 62
3111 00:24:34.518550 [CA 4] Center 34 (4~64) winsize 61
3112 00:24:34.522120 [CA 5] Center 33 (3~64) winsize 62
3113 00:24:34.522205
3114 00:24:34.524767 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3115 00:24:34.524847
3116 00:24:34.528182 [CATrainingPosCal] consider 2 rank data
3117 00:24:34.531687 u2DelayCellTimex100 = 270/100 ps
3118 00:24:34.535208 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3119 00:24:34.538762 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3120 00:24:34.545055 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3121 00:24:34.548468 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3122 00:24:34.551829 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3123 00:24:34.555128 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3124 00:24:34.555226
3125 00:24:34.558642 CA PerBit enable=1, Macro0, CA PI delay=33
3126 00:24:34.558739
3127 00:24:34.561751 [CBTSetCACLKResult] CA Dly = 33
3128 00:24:34.561838 CS Dly: 7 (0~39)
3129 00:24:34.561900
3130 00:24:34.565305 ----->DramcWriteLeveling(PI) begin...
3131 00:24:34.565388 ==
3132 00:24:34.568213 Dram Type= 6, Freq= 0, CH_1, rank 0
3133 00:24:34.574965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 00:24:34.575039 ==
3135 00:24:34.578577 Write leveling (Byte 0): 26 => 26
3136 00:24:34.581466 Write leveling (Byte 1): 27 => 27
3137 00:24:34.584655 DramcWriteLeveling(PI) end<-----
3138 00:24:34.584735
3139 00:24:34.584798 ==
3140 00:24:34.588395 Dram Type= 6, Freq= 0, CH_1, rank 0
3141 00:24:34.591887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3142 00:24:34.591969 ==
3143 00:24:34.594935 [Gating] SW mode calibration
3144 00:24:34.601596 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3145 00:24:34.604548 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3146 00:24:34.611853 0 15 0 | B1->B0 | 2d2d 2828 | 1 0 | (1 1) (0 0)
3147 00:24:34.614460 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 00:24:34.618267 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 00:24:34.624460 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 00:24:34.627939 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 00:24:34.631225 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3152 00:24:34.638017 0 15 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3153 00:24:34.640920 0 15 28 | B1->B0 | 2c2c 3131 | 0 0 | (0 1) (0 1)
3154 00:24:34.644333 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 00:24:34.651414 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 00:24:34.654277 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 00:24:34.658037 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 00:24:34.664448 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 00:24:34.667667 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 00:24:34.671567 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3161 00:24:34.678112 1 0 28 | B1->B0 | 3b3b 3d3d | 0 1 | (0 0) (0 0)
3162 00:24:34.680906 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 00:24:34.684474 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 00:24:34.691292 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 00:24:34.694222 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 00:24:34.697672 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 00:24:34.704316 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 00:24:34.707553 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 00:24:34.710816 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 00:24:34.717570 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 00:24:34.721057 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 00:24:34.724352 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 00:24:34.730846 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 00:24:34.734451 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 00:24:34.737809 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 00:24:34.741312 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 00:24:34.747630 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 00:24:34.751119 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 00:24:34.754586 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 00:24:34.761366 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 00:24:34.764725 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 00:24:34.768251 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 00:24:34.774876 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 00:24:34.778354 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3185 00:24:34.781216 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3186 00:24:34.788259 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 00:24:34.788342 Total UI for P1: 0, mck2ui 16
3188 00:24:34.791215 best dqsien dly found for B0: ( 1, 3, 28)
3189 00:24:34.794646 Total UI for P1: 0, mck2ui 16
3190 00:24:34.798384 best dqsien dly found for B1: ( 1, 3, 26)
3191 00:24:34.801624 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3192 00:24:34.808161 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3193 00:24:34.808242
3194 00:24:34.811824 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3195 00:24:34.815117 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3196 00:24:34.818577 [Gating] SW calibration Done
3197 00:24:34.818659 ==
3198 00:24:34.821324 Dram Type= 6, Freq= 0, CH_1, rank 0
3199 00:24:34.825270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3200 00:24:34.825367 ==
3201 00:24:34.825432 RX Vref Scan: 0
3202 00:24:34.825492
3203 00:24:34.827938 RX Vref 0 -> 0, step: 1
3204 00:24:34.828018
3205 00:24:34.831539 RX Delay -40 -> 252, step: 8
3206 00:24:34.834879 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3207 00:24:34.838120 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3208 00:24:34.844682 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3209 00:24:34.848714 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3210 00:24:34.851838 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3211 00:24:34.854663 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3212 00:24:34.858312 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3213 00:24:34.864804 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3214 00:24:34.867970 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3215 00:24:34.871568 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3216 00:24:34.874669 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3217 00:24:34.877876 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3218 00:24:34.881300 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3219 00:24:34.888168 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3220 00:24:34.891153 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3221 00:24:34.894589 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3222 00:24:34.894688 ==
3223 00:24:34.897974 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 00:24:34.901256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 00:24:34.904437 ==
3226 00:24:34.904510 DQS Delay:
3227 00:24:34.904574 DQS0 = 0, DQS1 = 0
3228 00:24:34.908199 DQM Delay:
3229 00:24:34.908282 DQM0 = 113, DQM1 = 106
3230 00:24:34.911190 DQ Delay:
3231 00:24:34.914623 DQ0 =115, DQ1 =111, DQ2 =99, DQ3 =115
3232 00:24:34.918034 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3233 00:24:34.921429 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3234 00:24:34.924979 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3235 00:24:34.925054
3236 00:24:34.925116
3237 00:24:34.925176 ==
3238 00:24:34.928366 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 00:24:34.931794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 00:24:34.931867 ==
3241 00:24:34.931928
3242 00:24:34.931991
3243 00:24:34.934482 TX Vref Scan disable
3244 00:24:34.938001 == TX Byte 0 ==
3245 00:24:34.941612 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3246 00:24:34.944657 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3247 00:24:34.948156 == TX Byte 1 ==
3248 00:24:34.951006 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3249 00:24:34.954475 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3250 00:24:34.954551 ==
3251 00:24:34.957816 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 00:24:34.961070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 00:24:34.964705 ==
3254 00:24:34.975054 TX Vref=22, minBit 11, minWin=24, winSum=406
3255 00:24:34.978309 TX Vref=24, minBit 10, minWin=24, winSum=409
3256 00:24:34.982159 TX Vref=26, minBit 8, minWin=25, winSum=416
3257 00:24:34.984683 TX Vref=28, minBit 9, minWin=25, winSum=421
3258 00:24:34.988337 TX Vref=30, minBit 9, minWin=25, winSum=421
3259 00:24:34.994504 TX Vref=32, minBit 9, minWin=25, winSum=418
3260 00:24:34.998296 [TxChooseVref] Worse bit 9, Min win 25, Win sum 421, Final Vref 28
3261 00:24:34.998376
3262 00:24:35.001576 Final TX Range 1 Vref 28
3263 00:24:35.001649
3264 00:24:35.001710 ==
3265 00:24:35.004649 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 00:24:35.008194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 00:24:35.008291 ==
3268 00:24:35.011141
3269 00:24:35.011237
3270 00:24:35.011327 TX Vref Scan disable
3271 00:24:35.014671 == TX Byte 0 ==
3272 00:24:35.017986 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3273 00:24:35.021455 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3274 00:24:35.024417 == TX Byte 1 ==
3275 00:24:35.027789 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3276 00:24:35.031552 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3277 00:24:35.034871
3278 00:24:35.034944 [DATLAT]
3279 00:24:35.035005 Freq=1200, CH1 RK0
3280 00:24:35.035064
3281 00:24:35.037799 DATLAT Default: 0xd
3282 00:24:35.037868 0, 0xFFFF, sum = 0
3283 00:24:35.041523 1, 0xFFFF, sum = 0
3284 00:24:35.041589 2, 0xFFFF, sum = 0
3285 00:24:35.044660 3, 0xFFFF, sum = 0
3286 00:24:35.044744 4, 0xFFFF, sum = 0
3287 00:24:35.048088 5, 0xFFFF, sum = 0
3288 00:24:35.051224 6, 0xFFFF, sum = 0
3289 00:24:35.051332 7, 0xFFFF, sum = 0
3290 00:24:35.054739 8, 0xFFFF, sum = 0
3291 00:24:35.054817 9, 0xFFFF, sum = 0
3292 00:24:35.058470 10, 0xFFFF, sum = 0
3293 00:24:35.058575 11, 0xFFFF, sum = 0
3294 00:24:35.061220 12, 0x0, sum = 1
3295 00:24:35.061295 13, 0x0, sum = 2
3296 00:24:35.064656 14, 0x0, sum = 3
3297 00:24:35.064732 15, 0x0, sum = 4
3298 00:24:35.064795 best_step = 13
3299 00:24:35.064863
3300 00:24:35.067871 ==
3301 00:24:35.071276 Dram Type= 6, Freq= 0, CH_1, rank 0
3302 00:24:35.074761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3303 00:24:35.074864 ==
3304 00:24:35.074954 RX Vref Scan: 1
3305 00:24:35.075040
3306 00:24:35.078054 Set Vref Range= 32 -> 127
3307 00:24:35.078153
3308 00:24:35.081249 RX Vref 32 -> 127, step: 1
3309 00:24:35.081348
3310 00:24:35.084482 RX Delay -21 -> 252, step: 4
3311 00:24:35.084582
3312 00:24:35.087891 Set Vref, RX VrefLevel [Byte0]: 32
3313 00:24:35.091197 [Byte1]: 32
3314 00:24:35.091269
3315 00:24:35.094878 Set Vref, RX VrefLevel [Byte0]: 33
3316 00:24:35.098033 [Byte1]: 33
3317 00:24:35.098110
3318 00:24:35.101524 Set Vref, RX VrefLevel [Byte0]: 34
3319 00:24:35.104974 [Byte1]: 34
3320 00:24:35.109227
3321 00:24:35.109302 Set Vref, RX VrefLevel [Byte0]: 35
3322 00:24:35.112598 [Byte1]: 35
3323 00:24:35.117181
3324 00:24:35.117257 Set Vref, RX VrefLevel [Byte0]: 36
3325 00:24:35.120302 [Byte1]: 36
3326 00:24:35.125046
3327 00:24:35.125121 Set Vref, RX VrefLevel [Byte0]: 37
3328 00:24:35.127976 [Byte1]: 37
3329 00:24:35.132991
3330 00:24:35.133062 Set Vref, RX VrefLevel [Byte0]: 38
3331 00:24:35.135813 [Byte1]: 38
3332 00:24:35.140746
3333 00:24:35.140822 Set Vref, RX VrefLevel [Byte0]: 39
3334 00:24:35.144331 [Byte1]: 39
3335 00:24:35.148792
3336 00:24:35.148867 Set Vref, RX VrefLevel [Byte0]: 40
3337 00:24:35.151672 [Byte1]: 40
3338 00:24:35.156276
3339 00:24:35.156351 Set Vref, RX VrefLevel [Byte0]: 41
3340 00:24:35.160435 [Byte1]: 41
3341 00:24:35.164302
3342 00:24:35.164403 Set Vref, RX VrefLevel [Byte0]: 42
3343 00:24:35.167811 [Byte1]: 42
3344 00:24:35.172887
3345 00:24:35.172963 Set Vref, RX VrefLevel [Byte0]: 43
3346 00:24:35.175819 [Byte1]: 43
3347 00:24:35.180388
3348 00:24:35.180461 Set Vref, RX VrefLevel [Byte0]: 44
3349 00:24:35.183333 [Byte1]: 44
3350 00:24:35.188783
3351 00:24:35.188856 Set Vref, RX VrefLevel [Byte0]: 45
3352 00:24:35.191280 [Byte1]: 45
3353 00:24:35.196276
3354 00:24:35.196348 Set Vref, RX VrefLevel [Byte0]: 46
3355 00:24:35.199366 [Byte1]: 46
3356 00:24:35.204181
3357 00:24:35.204256 Set Vref, RX VrefLevel [Byte0]: 47
3358 00:24:35.207202 [Byte1]: 47
3359 00:24:35.212321
3360 00:24:35.212392 Set Vref, RX VrefLevel [Byte0]: 48
3361 00:24:35.215501 [Byte1]: 48
3362 00:24:35.219826
3363 00:24:35.219898 Set Vref, RX VrefLevel [Byte0]: 49
3364 00:24:35.223350 [Byte1]: 49
3365 00:24:35.227698
3366 00:24:35.227772 Set Vref, RX VrefLevel [Byte0]: 50
3367 00:24:35.231049 [Byte1]: 50
3368 00:24:35.235738
3369 00:24:35.235811 Set Vref, RX VrefLevel [Byte0]: 51
3370 00:24:35.239165 [Byte1]: 51
3371 00:24:35.243605
3372 00:24:35.243679 Set Vref, RX VrefLevel [Byte0]: 52
3373 00:24:35.247482 [Byte1]: 52
3374 00:24:35.251485
3375 00:24:35.251587 Set Vref, RX VrefLevel [Byte0]: 53
3376 00:24:35.255083 [Byte1]: 53
3377 00:24:35.259623
3378 00:24:35.259697 Set Vref, RX VrefLevel [Byte0]: 54
3379 00:24:35.262544 [Byte1]: 54
3380 00:24:35.267590
3381 00:24:35.267690 Set Vref, RX VrefLevel [Byte0]: 55
3382 00:24:35.271121 [Byte1]: 55
3383 00:24:35.275517
3384 00:24:35.275598 Set Vref, RX VrefLevel [Byte0]: 56
3385 00:24:35.278784 [Byte1]: 56
3386 00:24:35.283497
3387 00:24:35.283573 Set Vref, RX VrefLevel [Byte0]: 57
3388 00:24:35.286375 [Byte1]: 57
3389 00:24:35.291060
3390 00:24:35.291132 Set Vref, RX VrefLevel [Byte0]: 58
3391 00:24:35.294450 [Byte1]: 58
3392 00:24:35.299374
3393 00:24:35.299484 Set Vref, RX VrefLevel [Byte0]: 59
3394 00:24:35.302627 [Byte1]: 59
3395 00:24:35.307205
3396 00:24:35.307276 Set Vref, RX VrefLevel [Byte0]: 60
3397 00:24:35.310176 [Byte1]: 60
3398 00:24:35.315142
3399 00:24:35.315215 Set Vref, RX VrefLevel [Byte0]: 61
3400 00:24:35.318126 [Byte1]: 61
3401 00:24:35.322709
3402 00:24:35.322781 Set Vref, RX VrefLevel [Byte0]: 62
3403 00:24:35.326025 [Byte1]: 62
3404 00:24:35.330965
3405 00:24:35.331037 Set Vref, RX VrefLevel [Byte0]: 63
3406 00:24:35.334142 [Byte1]: 63
3407 00:24:35.338732
3408 00:24:35.338804 Set Vref, RX VrefLevel [Byte0]: 64
3409 00:24:35.341827 [Byte1]: 64
3410 00:24:35.346939
3411 00:24:35.347043 Final RX Vref Byte 0 = 55 to rank0
3412 00:24:35.349981 Final RX Vref Byte 1 = 50 to rank0
3413 00:24:35.353429 Final RX Vref Byte 0 = 55 to rank1
3414 00:24:35.356760 Final RX Vref Byte 1 = 50 to rank1==
3415 00:24:35.360133 Dram Type= 6, Freq= 0, CH_1, rank 0
3416 00:24:35.366618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3417 00:24:35.366703 ==
3418 00:24:35.366796 DQS Delay:
3419 00:24:35.366883 DQS0 = 0, DQS1 = 0
3420 00:24:35.370212 DQM Delay:
3421 00:24:35.370284 DQM0 = 114, DQM1 = 105
3422 00:24:35.373659 DQ Delay:
3423 00:24:35.376557 DQ0 =118, DQ1 =110, DQ2 =104, DQ3 =110
3424 00:24:35.380093 DQ4 =112, DQ5 =122, DQ6 =126, DQ7 =110
3425 00:24:35.383186 DQ8 =92, DQ9 =100, DQ10 =104, DQ11 =100
3426 00:24:35.386689 DQ12 =114, DQ13 =110, DQ14 =114, DQ15 =112
3427 00:24:35.386765
3428 00:24:35.386828
3429 00:24:35.396384 [DQSOSCAuto] RK0, (LSB)MR18= 0xedf4, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 417 ps
3430 00:24:35.396479 CH1 RK0: MR19=303, MR18=EDF4
3431 00:24:35.403268 CH1_RK0: MR19=0x303, MR18=0xEDF4, DQSOSC=415, MR23=63, INC=38, DEC=25
3432 00:24:35.403389
3433 00:24:35.406493 ----->DramcWriteLeveling(PI) begin...
3434 00:24:35.406594 ==
3435 00:24:35.409896 Dram Type= 6, Freq= 0, CH_1, rank 1
3436 00:24:35.413362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3437 00:24:35.416239 ==
3438 00:24:35.419647 Write leveling (Byte 0): 24 => 24
3439 00:24:35.419721 Write leveling (Byte 1): 26 => 26
3440 00:24:35.423180 DramcWriteLeveling(PI) end<-----
3441 00:24:35.423251
3442 00:24:35.423313 ==
3443 00:24:35.426075 Dram Type= 6, Freq= 0, CH_1, rank 1
3444 00:24:35.432957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3445 00:24:35.433034 ==
3446 00:24:35.436123 [Gating] SW mode calibration
3447 00:24:35.442868 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3448 00:24:35.445936 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3449 00:24:35.453044 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 00:24:35.456591 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 00:24:35.459484 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 00:24:35.466071 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 00:24:35.469508 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 00:24:35.473095 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3455 00:24:35.479165 0 15 24 | B1->B0 | 3333 2525 | 1 0 | (1 0) (0 0)
3456 00:24:35.483069 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
3457 00:24:35.485889 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 00:24:35.492544 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 00:24:35.495859 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 00:24:35.499225 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 00:24:35.503239 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 00:24:35.509358 1 0 20 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
3463 00:24:35.513077 1 0 24 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
3464 00:24:35.516309 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 00:24:35.522777 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 00:24:35.526053 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 00:24:35.529693 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 00:24:35.535806 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 00:24:35.538979 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 00:24:35.542512 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 00:24:35.549263 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3472 00:24:35.552490 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 00:24:35.555776 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 00:24:35.562418 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 00:24:35.565810 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 00:24:35.569068 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 00:24:35.575871 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 00:24:35.579407 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 00:24:35.582163 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 00:24:35.589096 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 00:24:35.592260 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 00:24:35.595759 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 00:24:35.602464 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 00:24:35.605206 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 00:24:35.609083 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 00:24:35.615346 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 00:24:35.618517 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3488 00:24:35.622006 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3489 00:24:35.625499 Total UI for P1: 0, mck2ui 16
3490 00:24:35.628911 best dqsien dly found for B0: ( 1, 3, 24)
3491 00:24:35.635261 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 00:24:35.635368 Total UI for P1: 0, mck2ui 16
3493 00:24:35.638852 best dqsien dly found for B1: ( 1, 3, 26)
3494 00:24:35.645517 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3495 00:24:35.648653 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3496 00:24:35.648734
3497 00:24:35.652159 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3498 00:24:35.655584 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3499 00:24:35.658738 [Gating] SW calibration Done
3500 00:24:35.658843 ==
3501 00:24:35.661845 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 00:24:35.665400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 00:24:35.665481 ==
3504 00:24:35.668314 RX Vref Scan: 0
3505 00:24:35.668394
3506 00:24:35.668457 RX Vref 0 -> 0, step: 1
3507 00:24:35.668515
3508 00:24:35.671882 RX Delay -40 -> 252, step: 8
3509 00:24:35.675555 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3510 00:24:35.681647 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3511 00:24:35.684902 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3512 00:24:35.688627 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3513 00:24:35.691514 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3514 00:24:35.694897 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3515 00:24:35.698182 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3516 00:24:35.704886 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3517 00:24:35.708480 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3518 00:24:35.711941 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3519 00:24:35.714795 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3520 00:24:35.718317 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3521 00:24:35.725099 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3522 00:24:35.728382 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3523 00:24:35.731518 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3524 00:24:35.734903 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3525 00:24:35.734983 ==
3526 00:24:35.738007 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 00:24:35.744742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 00:24:35.744825 ==
3529 00:24:35.744891 DQS Delay:
3530 00:24:35.747829 DQS0 = 0, DQS1 = 0
3531 00:24:35.747905 DQM Delay:
3532 00:24:35.751270 DQM0 = 110, DQM1 = 108
3533 00:24:35.751394 DQ Delay:
3534 00:24:35.755219 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3535 00:24:35.758036 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3536 00:24:35.761257 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3537 00:24:35.764580 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =115
3538 00:24:35.764652
3539 00:24:35.764713
3540 00:24:35.764770 ==
3541 00:24:35.767821 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 00:24:35.771456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 00:24:35.774700 ==
3544 00:24:35.774775
3545 00:24:35.774834
3546 00:24:35.774895 TX Vref Scan disable
3547 00:24:35.777733 == TX Byte 0 ==
3548 00:24:35.781053 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3549 00:24:35.784711 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3550 00:24:35.787764 == TX Byte 1 ==
3551 00:24:35.791486 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3552 00:24:35.794290 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3553 00:24:35.797645 ==
3554 00:24:35.801247 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 00:24:35.804682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 00:24:35.804763 ==
3557 00:24:35.815662 TX Vref=22, minBit 0, minWin=26, winSum=421
3558 00:24:35.819235 TX Vref=24, minBit 9, minWin=25, winSum=422
3559 00:24:35.822740 TX Vref=26, minBit 3, minWin=26, winSum=427
3560 00:24:35.825464 TX Vref=28, minBit 1, minWin=26, winSum=429
3561 00:24:35.828943 TX Vref=30, minBit 9, minWin=25, winSum=424
3562 00:24:35.835850 TX Vref=32, minBit 4, minWin=26, winSum=429
3563 00:24:35.838805 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
3564 00:24:35.838886
3565 00:24:35.842205 Final TX Range 1 Vref 28
3566 00:24:35.842285
3567 00:24:35.842347 ==
3568 00:24:35.845544 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 00:24:35.848758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 00:24:35.848839 ==
3571 00:24:35.852048
3572 00:24:35.852127
3573 00:24:35.852190 TX Vref Scan disable
3574 00:24:35.855376 == TX Byte 0 ==
3575 00:24:35.858737 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3576 00:24:35.862032 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3577 00:24:35.865447 == TX Byte 1 ==
3578 00:24:35.868809 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3579 00:24:35.872033 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3580 00:24:35.875353
3581 00:24:35.875469 [DATLAT]
3582 00:24:35.875584 Freq=1200, CH1 RK1
3583 00:24:35.875675
3584 00:24:35.878902 DATLAT Default: 0xd
3585 00:24:35.878982 0, 0xFFFF, sum = 0
3586 00:24:35.882116 1, 0xFFFF, sum = 0
3587 00:24:35.882198 2, 0xFFFF, sum = 0
3588 00:24:35.885626 3, 0xFFFF, sum = 0
3589 00:24:35.885729 4, 0xFFFF, sum = 0
3590 00:24:35.888896 5, 0xFFFF, sum = 0
3591 00:24:35.888978 6, 0xFFFF, sum = 0
3592 00:24:35.892319 7, 0xFFFF, sum = 0
3593 00:24:35.895547 8, 0xFFFF, sum = 0
3594 00:24:35.895643 9, 0xFFFF, sum = 0
3595 00:24:35.898875 10, 0xFFFF, sum = 0
3596 00:24:35.898956 11, 0xFFFF, sum = 0
3597 00:24:35.902086 12, 0x0, sum = 1
3598 00:24:35.902167 13, 0x0, sum = 2
3599 00:24:35.905313 14, 0x0, sum = 3
3600 00:24:35.905395 15, 0x0, sum = 4
3601 00:24:35.905460 best_step = 13
3602 00:24:35.905519
3603 00:24:35.908500 ==
3604 00:24:35.911769 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 00:24:35.915279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 00:24:35.915359 ==
3607 00:24:35.915464 RX Vref Scan: 0
3608 00:24:35.915525
3609 00:24:35.918791 RX Vref 0 -> 0, step: 1
3610 00:24:35.918871
3611 00:24:35.921598 RX Delay -21 -> 252, step: 4
3612 00:24:35.925399 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3613 00:24:35.932123 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3614 00:24:35.935256 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3615 00:24:35.938447 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3616 00:24:35.942038 iDelay=195, Bit 4, Center 110 (39 ~ 182) 144
3617 00:24:35.945693 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3618 00:24:35.951879 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3619 00:24:35.954818 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3620 00:24:35.958221 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3621 00:24:35.961580 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3622 00:24:35.965135 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3623 00:24:35.971849 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3624 00:24:35.975537 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3625 00:24:35.978381 iDelay=195, Bit 13, Center 114 (47 ~ 182) 136
3626 00:24:35.981901 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3627 00:24:35.985066 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3628 00:24:35.988209 ==
3629 00:24:35.991348 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 00:24:35.994827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 00:24:35.994905 ==
3632 00:24:35.994968 DQS Delay:
3633 00:24:35.997964 DQS0 = 0, DQS1 = 0
3634 00:24:35.998034 DQM Delay:
3635 00:24:36.001379 DQM0 = 111, DQM1 = 109
3636 00:24:36.001450 DQ Delay:
3637 00:24:36.004513 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3638 00:24:36.008027 DQ4 =110, DQ5 =120, DQ6 =122, DQ7 =110
3639 00:24:36.011441 DQ8 =96, DQ9 =102, DQ10 =110, DQ11 =104
3640 00:24:36.014555 DQ12 =116, DQ13 =114, DQ14 =116, DQ15 =116
3641 00:24:36.014628
3642 00:24:36.014689
3643 00:24:36.024762 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb0a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3644 00:24:36.027939 CH1 RK1: MR19=304, MR18=FB0A
3645 00:24:36.030836 CH1_RK1: MR19=0x304, MR18=0xFB0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3646 00:24:36.034382 [RxdqsGatingPostProcess] freq 1200
3647 00:24:36.040770 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3648 00:24:36.044174 best DQS0 dly(2T, 0.5T) = (0, 11)
3649 00:24:36.047644 best DQS1 dly(2T, 0.5T) = (0, 11)
3650 00:24:36.051206 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3651 00:24:36.054264 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3652 00:24:36.057475 best DQS0 dly(2T, 0.5T) = (0, 11)
3653 00:24:36.061214 best DQS1 dly(2T, 0.5T) = (0, 11)
3654 00:24:36.063903 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3655 00:24:36.067221 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3656 00:24:36.070567 Pre-setting of DQS Precalculation
3657 00:24:36.073792 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3658 00:24:36.081037 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3659 00:24:36.090511 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3660 00:24:36.090595
3661 00:24:36.090660
3662 00:24:36.090720 [Calibration Summary] 2400 Mbps
3663 00:24:36.094165 CH 0, Rank 0
3664 00:24:36.096850 SW Impedance : PASS
3665 00:24:36.096921 DUTY Scan : NO K
3666 00:24:36.100523 ZQ Calibration : PASS
3667 00:24:36.100591 Jitter Meter : NO K
3668 00:24:36.103538 CBT Training : PASS
3669 00:24:36.107491 Write leveling : PASS
3670 00:24:36.107559 RX DQS gating : PASS
3671 00:24:36.110157 RX DQ/DQS(RDDQC) : PASS
3672 00:24:36.113612 TX DQ/DQS : PASS
3673 00:24:36.113683 RX DATLAT : PASS
3674 00:24:36.117121 RX DQ/DQS(Engine): PASS
3675 00:24:36.120292 TX OE : NO K
3676 00:24:36.120365 All Pass.
3677 00:24:36.120424
3678 00:24:36.120481 CH 0, Rank 1
3679 00:24:36.123691 SW Impedance : PASS
3680 00:24:36.126861 DUTY Scan : NO K
3681 00:24:36.126927 ZQ Calibration : PASS
3682 00:24:36.130016 Jitter Meter : NO K
3683 00:24:36.133715 CBT Training : PASS
3684 00:24:36.133787 Write leveling : PASS
3685 00:24:36.136596 RX DQS gating : PASS
3686 00:24:36.140197 RX DQ/DQS(RDDQC) : PASS
3687 00:24:36.140268 TX DQ/DQS : PASS
3688 00:24:36.143313 RX DATLAT : PASS
3689 00:24:36.146884 RX DQ/DQS(Engine): PASS
3690 00:24:36.146955 TX OE : NO K
3691 00:24:36.147017 All Pass.
3692 00:24:36.147103
3693 00:24:36.150136 CH 1, Rank 0
3694 00:24:36.153740 SW Impedance : PASS
3695 00:24:36.153807 DUTY Scan : NO K
3696 00:24:36.156649 ZQ Calibration : PASS
3697 00:24:36.156719 Jitter Meter : NO K
3698 00:24:36.160166 CBT Training : PASS
3699 00:24:36.163626 Write leveling : PASS
3700 00:24:36.163700 RX DQS gating : PASS
3701 00:24:36.166972 RX DQ/DQS(RDDQC) : PASS
3702 00:24:36.170024 TX DQ/DQS : PASS
3703 00:24:36.170092 RX DATLAT : PASS
3704 00:24:36.173332 RX DQ/DQS(Engine): PASS
3705 00:24:36.176816 TX OE : NO K
3706 00:24:36.176887 All Pass.
3707 00:24:36.176949
3708 00:24:36.177004 CH 1, Rank 1
3709 00:24:36.180137 SW Impedance : PASS
3710 00:24:36.183390 DUTY Scan : NO K
3711 00:24:36.183478 ZQ Calibration : PASS
3712 00:24:36.186992 Jitter Meter : NO K
3713 00:24:36.189998 CBT Training : PASS
3714 00:24:36.190076 Write leveling : PASS
3715 00:24:36.193571 RX DQS gating : PASS
3716 00:24:36.193646 RX DQ/DQS(RDDQC) : PASS
3717 00:24:36.196787 TX DQ/DQS : PASS
3718 00:24:36.200288 RX DATLAT : PASS
3719 00:24:36.200359 RX DQ/DQS(Engine): PASS
3720 00:24:36.203294 TX OE : NO K
3721 00:24:36.203427 All Pass.
3722 00:24:36.203491
3723 00:24:36.206707 DramC Write-DBI off
3724 00:24:36.210114 PER_BANK_REFRESH: Hybrid Mode
3725 00:24:36.210182 TX_TRACKING: ON
3726 00:24:36.220169 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3727 00:24:36.223157 [FAST_K] Save calibration result to emmc
3728 00:24:36.226773 dramc_set_vcore_voltage set vcore to 650000
3729 00:24:36.230017 Read voltage for 600, 5
3730 00:24:36.230103 Vio18 = 0
3731 00:24:36.230199 Vcore = 650000
3732 00:24:36.233391 Vdram = 0
3733 00:24:36.233458 Vddq = 0
3734 00:24:36.233516 Vmddr = 0
3735 00:24:36.239639 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3736 00:24:36.243223 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3737 00:24:36.246727 MEM_TYPE=3, freq_sel=19
3738 00:24:36.249865 sv_algorithm_assistance_LP4_1600
3739 00:24:36.253025 ============ PULL DRAM RESETB DOWN ============
3740 00:24:36.259850 ========== PULL DRAM RESETB DOWN end =========
3741 00:24:36.263285 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3742 00:24:36.266689 ===================================
3743 00:24:36.269901 LPDDR4 DRAM CONFIGURATION
3744 00:24:36.273025 ===================================
3745 00:24:36.273098 EX_ROW_EN[0] = 0x0
3746 00:24:36.276653 EX_ROW_EN[1] = 0x0
3747 00:24:36.276724 LP4Y_EN = 0x0
3748 00:24:36.279934 WORK_FSP = 0x0
3749 00:24:36.280006 WL = 0x2
3750 00:24:36.283291 RL = 0x2
3751 00:24:36.283418 BL = 0x2
3752 00:24:36.286180 RPST = 0x0
3753 00:24:36.286253 RD_PRE = 0x0
3754 00:24:36.289687 WR_PRE = 0x1
3755 00:24:36.289769 WR_PST = 0x0
3756 00:24:36.292972 DBI_WR = 0x0
3757 00:24:36.296276 DBI_RD = 0x0
3758 00:24:36.296356 OTF = 0x1
3759 00:24:36.299884 ===================================
3760 00:24:36.302777 ===================================
3761 00:24:36.302858 ANA top config
3762 00:24:36.306382 ===================================
3763 00:24:36.309844 DLL_ASYNC_EN = 0
3764 00:24:36.312825 ALL_SLAVE_EN = 1
3765 00:24:36.316373 NEW_RANK_MODE = 1
3766 00:24:36.319366 DLL_IDLE_MODE = 1
3767 00:24:36.319484 LP45_APHY_COMB_EN = 1
3768 00:24:36.323035 TX_ODT_DIS = 1
3769 00:24:36.326371 NEW_8X_MODE = 1
3770 00:24:36.329775 ===================================
3771 00:24:36.333401 ===================================
3772 00:24:36.336060 data_rate = 1200
3773 00:24:36.339845 CKR = 1
3774 00:24:36.339918 DQ_P2S_RATIO = 8
3775 00:24:36.343135 ===================================
3776 00:24:36.346088 CA_P2S_RATIO = 8
3777 00:24:36.349449 DQ_CA_OPEN = 0
3778 00:24:36.352629 DQ_SEMI_OPEN = 0
3779 00:24:36.356039 CA_SEMI_OPEN = 0
3780 00:24:36.359151 CA_FULL_RATE = 0
3781 00:24:36.359230 DQ_CKDIV4_EN = 1
3782 00:24:36.362824 CA_CKDIV4_EN = 1
3783 00:24:36.365762 CA_PREDIV_EN = 0
3784 00:24:36.369377 PH8_DLY = 0
3785 00:24:36.372579 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3786 00:24:36.375968 DQ_AAMCK_DIV = 4
3787 00:24:36.376045 CA_AAMCK_DIV = 4
3788 00:24:36.379303 CA_ADMCK_DIV = 4
3789 00:24:36.382342 DQ_TRACK_CA_EN = 0
3790 00:24:36.385744 CA_PICK = 600
3791 00:24:36.389270 CA_MCKIO = 600
3792 00:24:36.392176 MCKIO_SEMI = 0
3793 00:24:36.395499 PLL_FREQ = 2288
3794 00:24:36.395579 DQ_UI_PI_RATIO = 32
3795 00:24:36.398833 CA_UI_PI_RATIO = 0
3796 00:24:36.402480 ===================================
3797 00:24:36.405708 ===================================
3798 00:24:36.408745 memory_type:LPDDR4
3799 00:24:36.412241 GP_NUM : 10
3800 00:24:36.412328 SRAM_EN : 1
3801 00:24:36.415649 MD32_EN : 0
3802 00:24:36.419148 ===================================
3803 00:24:36.422269 [ANA_INIT] >>>>>>>>>>>>>>
3804 00:24:36.422353 <<<<<< [CONFIGURE PHASE]: ANA_TX
3805 00:24:36.425445 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3806 00:24:36.429219 ===================================
3807 00:24:36.432116 data_rate = 1200,PCW = 0X5800
3808 00:24:36.435556 ===================================
3809 00:24:36.438476 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3810 00:24:36.445360 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3811 00:24:36.452066 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3812 00:24:36.455649 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3813 00:24:36.458688 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3814 00:24:36.462065 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3815 00:24:36.465442 [ANA_INIT] flow start
3816 00:24:36.465522 [ANA_INIT] PLL >>>>>>>>
3817 00:24:36.468895 [ANA_INIT] PLL <<<<<<<<
3818 00:24:36.471771 [ANA_INIT] MIDPI >>>>>>>>
3819 00:24:36.475132 [ANA_INIT] MIDPI <<<<<<<<
3820 00:24:36.475211 [ANA_INIT] DLL >>>>>>>>
3821 00:24:36.478259 [ANA_INIT] flow end
3822 00:24:36.481938 ============ LP4 DIFF to SE enter ============
3823 00:24:36.485478 ============ LP4 DIFF to SE exit ============
3824 00:24:36.488379 [ANA_INIT] <<<<<<<<<<<<<
3825 00:24:36.491947 [Flow] Enable top DCM control >>>>>
3826 00:24:36.495072 [Flow] Enable top DCM control <<<<<
3827 00:24:36.498406 Enable DLL master slave shuffle
3828 00:24:36.504927 ==============================================================
3829 00:24:36.505006 Gating Mode config
3830 00:24:36.511520 ==============================================================
3831 00:24:36.511592 Config description:
3832 00:24:36.521429 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3833 00:24:36.528136 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3834 00:24:36.534516 SELPH_MODE 0: By rank 1: By Phase
3835 00:24:36.538034 ==============================================================
3836 00:24:36.541258 GAT_TRACK_EN = 1
3837 00:24:36.544909 RX_GATING_MODE = 2
3838 00:24:36.548351 RX_GATING_TRACK_MODE = 2
3839 00:24:36.552101 SELPH_MODE = 1
3840 00:24:36.554619 PICG_EARLY_EN = 1
3841 00:24:36.558168 VALID_LAT_VALUE = 1
3842 00:24:36.561235 ==============================================================
3843 00:24:36.567823 Enter into Gating configuration >>>>
3844 00:24:36.571338 Exit from Gating configuration <<<<
3845 00:24:36.571437 Enter into DVFS_PRE_config >>>>>
3846 00:24:36.584727 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3847 00:24:36.587824 Exit from DVFS_PRE_config <<<<<
3848 00:24:36.590999 Enter into PICG configuration >>>>
3849 00:24:36.594458 Exit from PICG configuration <<<<
3850 00:24:36.594563 [RX_INPUT] configuration >>>>>
3851 00:24:36.597520 [RX_INPUT] configuration <<<<<
3852 00:24:36.604054 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3853 00:24:36.607804 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3854 00:24:36.614494 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3855 00:24:36.620821 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3856 00:24:36.627696 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3857 00:24:36.633977 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3858 00:24:36.637204 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3859 00:24:36.640775 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3860 00:24:36.647496 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3861 00:24:36.650900 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3862 00:24:36.654019 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3863 00:24:36.657599 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3864 00:24:36.661022 ===================================
3865 00:24:36.664268 LPDDR4 DRAM CONFIGURATION
3866 00:24:36.667072 ===================================
3867 00:24:36.670815 EX_ROW_EN[0] = 0x0
3868 00:24:36.670896 EX_ROW_EN[1] = 0x0
3869 00:24:36.673918 LP4Y_EN = 0x0
3870 00:24:36.673998 WORK_FSP = 0x0
3871 00:24:36.677243 WL = 0x2
3872 00:24:36.677324 RL = 0x2
3873 00:24:36.680682 BL = 0x2
3874 00:24:36.680762 RPST = 0x0
3875 00:24:36.684308 RD_PRE = 0x0
3876 00:24:36.684404 WR_PRE = 0x1
3877 00:24:36.686961 WR_PST = 0x0
3878 00:24:36.690491 DBI_WR = 0x0
3879 00:24:36.690623 DBI_RD = 0x0
3880 00:24:36.694042 OTF = 0x1
3881 00:24:36.696796 ===================================
3882 00:24:36.700390 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3883 00:24:36.704548 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3884 00:24:36.707185 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3885 00:24:36.710391 ===================================
3886 00:24:36.713543 LPDDR4 DRAM CONFIGURATION
3887 00:24:36.717300 ===================================
3888 00:24:36.720112 EX_ROW_EN[0] = 0x10
3889 00:24:36.720192 EX_ROW_EN[1] = 0x0
3890 00:24:36.723607 LP4Y_EN = 0x0
3891 00:24:36.723687 WORK_FSP = 0x0
3892 00:24:36.726944 WL = 0x2
3893 00:24:36.727024 RL = 0x2
3894 00:24:36.730040 BL = 0x2
3895 00:24:36.730120 RPST = 0x0
3896 00:24:36.733780 RD_PRE = 0x0
3897 00:24:36.733860 WR_PRE = 0x1
3898 00:24:36.736706 WR_PST = 0x0
3899 00:24:36.736786 DBI_WR = 0x0
3900 00:24:36.739982 DBI_RD = 0x0
3901 00:24:36.743866 OTF = 0x1
3902 00:24:36.746749 ===================================
3903 00:24:36.750038 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3904 00:24:36.755117 nWR fixed to 30
3905 00:24:36.758659 [ModeRegInit_LP4] CH0 RK0
3906 00:24:36.758754 [ModeRegInit_LP4] CH0 RK1
3907 00:24:36.762001 [ModeRegInit_LP4] CH1 RK0
3908 00:24:36.765431 [ModeRegInit_LP4] CH1 RK1
3909 00:24:36.765511 match AC timing 17
3910 00:24:36.772305 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3911 00:24:36.775553 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3912 00:24:36.778609 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3913 00:24:36.785352 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3914 00:24:36.789031 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3915 00:24:36.789111 ==
3916 00:24:36.791776 Dram Type= 6, Freq= 0, CH_0, rank 0
3917 00:24:36.795265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3918 00:24:36.795393 ==
3919 00:24:36.801870 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3920 00:24:36.808471 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3921 00:24:36.812101 [CA 0] Center 37 (7~67) winsize 61
3922 00:24:36.815497 [CA 1] Center 37 (7~67) winsize 61
3923 00:24:36.818690 [CA 2] Center 35 (5~65) winsize 61
3924 00:24:36.821646 [CA 3] Center 35 (5~65) winsize 61
3925 00:24:36.825219 [CA 4] Center 34 (4~65) winsize 62
3926 00:24:36.828549 [CA 5] Center 33 (3~64) winsize 62
3927 00:24:36.828624
3928 00:24:36.831772 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3929 00:24:36.831841
3930 00:24:36.835218 [CATrainingPosCal] consider 1 rank data
3931 00:24:36.838218 u2DelayCellTimex100 = 270/100 ps
3932 00:24:36.841722 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3933 00:24:36.845348 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
3934 00:24:36.848172 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3935 00:24:36.851491 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3936 00:24:36.855098 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3937 00:24:36.858863 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3938 00:24:36.861870
3939 00:24:36.864745 CA PerBit enable=1, Macro0, CA PI delay=33
3940 00:24:36.864819
3941 00:24:36.868167 [CBTSetCACLKResult] CA Dly = 33
3942 00:24:36.868234 CS Dly: 4 (0~35)
3943 00:24:36.868296 ==
3944 00:24:36.871561 Dram Type= 6, Freq= 0, CH_0, rank 1
3945 00:24:36.874811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3946 00:24:36.878168 ==
3947 00:24:36.881598 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3948 00:24:36.888435 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3949 00:24:36.891709 [CA 0] Center 37 (7~67) winsize 61
3950 00:24:36.894869 [CA 1] Center 36 (6~67) winsize 62
3951 00:24:36.898403 [CA 2] Center 35 (5~65) winsize 61
3952 00:24:36.901201 [CA 3] Center 35 (5~65) winsize 61
3953 00:24:36.904683 [CA 4] Center 34 (3~65) winsize 63
3954 00:24:36.908370 [CA 5] Center 33 (3~64) winsize 62
3955 00:24:36.908437
3956 00:24:36.911070 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3957 00:24:36.911139
3958 00:24:36.915143 [CATrainingPosCal] consider 2 rank data
3959 00:24:36.918089 u2DelayCellTimex100 = 270/100 ps
3960 00:24:36.921474 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3961 00:24:36.924933 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
3962 00:24:36.927886 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3963 00:24:36.934613 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3964 00:24:36.938021 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3965 00:24:36.941170 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3966 00:24:36.941242
3967 00:24:36.944367 CA PerBit enable=1, Macro0, CA PI delay=33
3968 00:24:36.944435
3969 00:24:36.947477 [CBTSetCACLKResult] CA Dly = 33
3970 00:24:36.947559 CS Dly: 5 (0~37)
3971 00:24:36.947635
3972 00:24:36.950995 ----->DramcWriteLeveling(PI) begin...
3973 00:24:36.951080 ==
3974 00:24:36.954410 Dram Type= 6, Freq= 0, CH_0, rank 0
3975 00:24:36.960816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 00:24:36.960890 ==
3977 00:24:36.964402 Write leveling (Byte 0): 35 => 35
3978 00:24:36.967716 Write leveling (Byte 1): 31 => 31
3979 00:24:36.967787 DramcWriteLeveling(PI) end<-----
3980 00:24:36.970763
3981 00:24:36.970830 ==
3982 00:24:36.974259 Dram Type= 6, Freq= 0, CH_0, rank 0
3983 00:24:36.977617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3984 00:24:36.977688 ==
3985 00:24:36.980811 [Gating] SW mode calibration
3986 00:24:36.987798 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3987 00:24:36.990901 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3988 00:24:36.997850 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3989 00:24:37.000598 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3990 00:24:37.004066 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 00:24:37.010926 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
3992 00:24:37.013929 0 9 16 | B1->B0 | 3131 2c2c | 0 1 | (1 1) (1 1)
3993 00:24:37.017298 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3994 00:24:37.024361 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 00:24:37.027625 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 00:24:37.030491 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 00:24:37.037682 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 00:24:37.040631 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 00:24:37.043797 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4000 00:24:37.050619 0 10 16 | B1->B0 | 3636 3939 | 0 0 | (0 0) (0 0)
4001 00:24:37.053832 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 00:24:37.057169 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 00:24:37.064078 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 00:24:37.067337 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 00:24:37.070376 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 00:24:37.077465 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 00:24:37.080250 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 00:24:37.083603 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4009 00:24:37.090342 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 00:24:37.093670 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 00:24:37.096934 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 00:24:37.103871 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 00:24:37.106881 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 00:24:37.110258 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 00:24:37.114329 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 00:24:37.120402 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 00:24:37.123959 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 00:24:37.127069 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 00:24:37.133777 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 00:24:37.137065 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 00:24:37.140685 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 00:24:37.147271 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 00:24:37.150210 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4024 00:24:37.153864 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4025 00:24:37.157121 Total UI for P1: 0, mck2ui 16
4026 00:24:37.160344 best dqsien dly found for B0: ( 0, 13, 12)
4027 00:24:37.166729 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 00:24:37.166809 Total UI for P1: 0, mck2ui 16
4029 00:24:37.174019 best dqsien dly found for B1: ( 0, 13, 16)
4030 00:24:37.176939 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4031 00:24:37.180483 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4032 00:24:37.180555
4033 00:24:37.183339 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4034 00:24:37.186829 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4035 00:24:37.190279 [Gating] SW calibration Done
4036 00:24:37.190352 ==
4037 00:24:37.193401 Dram Type= 6, Freq= 0, CH_0, rank 0
4038 00:24:37.196892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 00:24:37.196983 ==
4040 00:24:37.200027 RX Vref Scan: 0
4041 00:24:37.200099
4042 00:24:37.200244 RX Vref 0 -> 0, step: 1
4043 00:24:37.200353
4044 00:24:37.203127 RX Delay -230 -> 252, step: 16
4045 00:24:37.209858 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4046 00:24:37.213620 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4047 00:24:37.216478 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4048 00:24:37.219855 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4049 00:24:37.226914 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4050 00:24:37.230072 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4051 00:24:37.233190 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4052 00:24:37.236290 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4053 00:24:37.239889 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4054 00:24:37.246559 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4055 00:24:37.250101 iDelay=218, Bit 10, Center 25 (-150 ~ 201) 352
4056 00:24:37.252894 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4057 00:24:37.256526 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4058 00:24:37.262881 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4059 00:24:37.266168 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4060 00:24:37.269405 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4061 00:24:37.269486 ==
4062 00:24:37.272579 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 00:24:37.276035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 00:24:37.279664 ==
4065 00:24:37.279745 DQS Delay:
4066 00:24:37.279809 DQS0 = 0, DQS1 = 0
4067 00:24:37.282928 DQM Delay:
4068 00:24:37.283008 DQM0 = 37, DQM1 = 28
4069 00:24:37.285943 DQ Delay:
4070 00:24:37.289693 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4071 00:24:37.289775 DQ4 =41, DQ5 =17, DQ6 =49, DQ7 =49
4072 00:24:37.292977 DQ8 =17, DQ9 =17, DQ10 =25, DQ11 =17
4073 00:24:37.295964 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4074 00:24:37.299520
4075 00:24:37.299601
4076 00:24:37.299665 ==
4077 00:24:37.302285 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 00:24:37.306065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 00:24:37.306147 ==
4080 00:24:37.306212
4081 00:24:37.306275
4082 00:24:37.309031 TX Vref Scan disable
4083 00:24:37.309112 == TX Byte 0 ==
4084 00:24:37.315939 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4085 00:24:37.318853 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4086 00:24:37.318934 == TX Byte 1 ==
4087 00:24:37.325601 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4088 00:24:37.329084 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4089 00:24:37.329165 ==
4090 00:24:37.332397 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 00:24:37.335585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 00:24:37.335667 ==
4093 00:24:37.335731
4094 00:24:37.335791
4095 00:24:37.339245 TX Vref Scan disable
4096 00:24:37.342471 == TX Byte 0 ==
4097 00:24:37.345642 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4098 00:24:37.352597 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4099 00:24:37.352679 == TX Byte 1 ==
4100 00:24:37.355681 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4101 00:24:37.362381 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4102 00:24:37.362463
4103 00:24:37.362527 [DATLAT]
4104 00:24:37.362587 Freq=600, CH0 RK0
4105 00:24:37.362644
4106 00:24:37.365336 DATLAT Default: 0x9
4107 00:24:37.365416 0, 0xFFFF, sum = 0
4108 00:24:37.368807 1, 0xFFFF, sum = 0
4109 00:24:37.368906 2, 0xFFFF, sum = 0
4110 00:24:37.372095 3, 0xFFFF, sum = 0
4111 00:24:37.375522 4, 0xFFFF, sum = 0
4112 00:24:37.375632 5, 0xFFFF, sum = 0
4113 00:24:37.378752 6, 0xFFFF, sum = 0
4114 00:24:37.378834 7, 0xFFFF, sum = 0
4115 00:24:37.382223 8, 0x0, sum = 1
4116 00:24:37.382305 9, 0x0, sum = 2
4117 00:24:37.382370 10, 0x0, sum = 3
4118 00:24:37.385301 11, 0x0, sum = 4
4119 00:24:37.385387 best_step = 9
4120 00:24:37.385451
4121 00:24:37.388488 ==
4122 00:24:37.388569 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 00:24:37.395340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 00:24:37.395470 ==
4125 00:24:37.395536 RX Vref Scan: 1
4126 00:24:37.395595
4127 00:24:37.398869 RX Vref 0 -> 0, step: 1
4128 00:24:37.398951
4129 00:24:37.401873 RX Delay -195 -> 252, step: 8
4130 00:24:37.401954
4131 00:24:37.405306 Set Vref, RX VrefLevel [Byte0]: 61
4132 00:24:37.408211 [Byte1]: 54
4133 00:24:37.408293
4134 00:24:37.411620 Final RX Vref Byte 0 = 61 to rank0
4135 00:24:37.414868 Final RX Vref Byte 1 = 54 to rank0
4136 00:24:37.418703 Final RX Vref Byte 0 = 61 to rank1
4137 00:24:37.421510 Final RX Vref Byte 1 = 54 to rank1==
4138 00:24:37.425434 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 00:24:37.428126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 00:24:37.431441 ==
4141 00:24:37.431526 DQS Delay:
4142 00:24:37.431591 DQS0 = 0, DQS1 = 0
4143 00:24:37.434784 DQM Delay:
4144 00:24:37.434865 DQM0 = 34, DQM1 = 28
4145 00:24:37.438112 DQ Delay:
4146 00:24:37.438194 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =28
4147 00:24:37.441373 DQ4 =36, DQ5 =20, DQ6 =40, DQ7 =44
4148 00:24:37.444759 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4149 00:24:37.448181 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4150 00:24:37.448263
4151 00:24:37.451045
4152 00:24:37.457815 [DQSOSCAuto] RK0, (LSB)MR18= 0x4040, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4153 00:24:37.461270 CH0 RK0: MR19=808, MR18=4040
4154 00:24:37.467610 CH0_RK0: MR19=0x808, MR18=0x4040, DQSOSC=397, MR23=63, INC=166, DEC=110
4155 00:24:37.467705
4156 00:24:37.470879 ----->DramcWriteLeveling(PI) begin...
4157 00:24:37.470962 ==
4158 00:24:37.474485 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 00:24:37.477663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 00:24:37.477768 ==
4161 00:24:37.480935 Write leveling (Byte 0): 32 => 32
4162 00:24:37.484318 Write leveling (Byte 1): 31 => 31
4163 00:24:37.487737 DramcWriteLeveling(PI) end<-----
4164 00:24:37.487818
4165 00:24:37.487882 ==
4166 00:24:37.490804 Dram Type= 6, Freq= 0, CH_0, rank 1
4167 00:24:37.494105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 00:24:37.494187 ==
4169 00:24:37.497503 [Gating] SW mode calibration
4170 00:24:37.504548 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4171 00:24:37.510985 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4172 00:24:37.514204 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4173 00:24:37.520543 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4174 00:24:37.523744 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 00:24:37.527506 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4176 00:24:37.534098 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4177 00:24:37.537078 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 00:24:37.540578 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 00:24:37.544011 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 00:24:37.550114 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 00:24:37.553869 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 00:24:37.560071 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 00:24:37.563684 0 10 12 | B1->B0 | 2828 3333 | 0 1 | (0 0) (0 0)
4184 00:24:37.567123 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4185 00:24:37.570078 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 00:24:37.576942 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 00:24:37.580515 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 00:24:37.583690 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 00:24:37.590876 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 00:24:37.593775 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 00:24:37.596499 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 00:24:37.603225 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4193 00:24:37.607094 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 00:24:37.609871 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 00:24:37.616509 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 00:24:37.620005 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 00:24:37.623215 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 00:24:37.629812 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 00:24:37.632841 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 00:24:37.636745 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 00:24:37.643019 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 00:24:37.646365 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 00:24:37.649644 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 00:24:37.656448 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 00:24:37.659683 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 00:24:37.662938 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 00:24:37.669866 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4208 00:24:37.669949 Total UI for P1: 0, mck2ui 16
4209 00:24:37.676306 best dqsien dly found for B0: ( 0, 13, 10)
4210 00:24:37.679855 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 00:24:37.683209 Total UI for P1: 0, mck2ui 16
4212 00:24:37.686441 best dqsien dly found for B1: ( 0, 13, 14)
4213 00:24:37.689968 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4214 00:24:37.692874 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4215 00:24:37.692956
4216 00:24:37.696221 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4217 00:24:37.699561 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4218 00:24:37.703627 [Gating] SW calibration Done
4219 00:24:37.703709 ==
4220 00:24:37.706332 Dram Type= 6, Freq= 0, CH_0, rank 1
4221 00:24:37.709597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 00:24:37.712688 ==
4223 00:24:37.712771 RX Vref Scan: 0
4224 00:24:37.712835
4225 00:24:37.716469 RX Vref 0 -> 0, step: 1
4226 00:24:37.716551
4227 00:24:37.719809 RX Delay -230 -> 252, step: 16
4228 00:24:37.722665 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4229 00:24:37.726005 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4230 00:24:37.729460 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4231 00:24:37.735987 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4232 00:24:37.739246 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4233 00:24:37.742565 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4234 00:24:37.746028 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4235 00:24:37.749256 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4236 00:24:37.756103 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4237 00:24:37.759417 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4238 00:24:37.762714 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4239 00:24:37.765772 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4240 00:24:37.772394 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4241 00:24:37.775730 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4242 00:24:37.779239 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4243 00:24:37.782651 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4244 00:24:37.782733 ==
4245 00:24:37.786105 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 00:24:37.792986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 00:24:37.793070 ==
4248 00:24:37.793135 DQS Delay:
4249 00:24:37.795876 DQS0 = 0, DQS1 = 0
4250 00:24:37.795958 DQM Delay:
4251 00:24:37.796044 DQM0 = 35, DQM1 = 28
4252 00:24:37.799134 DQ Delay:
4253 00:24:37.802660 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4254 00:24:37.806217 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4255 00:24:37.808958 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4256 00:24:37.812564 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4257 00:24:37.812646
4258 00:24:37.812710
4259 00:24:37.812770 ==
4260 00:24:37.815746 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 00:24:37.818957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 00:24:37.819039 ==
4263 00:24:37.819104
4264 00:24:37.819164
4265 00:24:37.822185 TX Vref Scan disable
4266 00:24:37.825855 == TX Byte 0 ==
4267 00:24:37.829169 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4268 00:24:37.832573 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4269 00:24:37.835557 == TX Byte 1 ==
4270 00:24:37.839230 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4271 00:24:37.842435 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4272 00:24:37.842516 ==
4273 00:24:37.845506 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 00:24:37.849019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 00:24:37.849100 ==
4276 00:24:37.852383
4277 00:24:37.852478
4278 00:24:37.852542 TX Vref Scan disable
4279 00:24:37.855928 == TX Byte 0 ==
4280 00:24:37.859110 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4281 00:24:37.865965 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4282 00:24:37.866047 == TX Byte 1 ==
4283 00:24:37.869386 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4284 00:24:37.875723 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4285 00:24:37.875803
4286 00:24:37.875867 [DATLAT]
4287 00:24:37.875926 Freq=600, CH0 RK1
4288 00:24:37.875984
4289 00:24:37.878891 DATLAT Default: 0x9
4290 00:24:37.878972 0, 0xFFFF, sum = 0
4291 00:24:37.882716 1, 0xFFFF, sum = 0
4292 00:24:37.882799 2, 0xFFFF, sum = 0
4293 00:24:37.886001 3, 0xFFFF, sum = 0
4294 00:24:37.886083 4, 0xFFFF, sum = 0
4295 00:24:37.888896 5, 0xFFFF, sum = 0
4296 00:24:37.892646 6, 0xFFFF, sum = 0
4297 00:24:37.892727 7, 0xFFFF, sum = 0
4298 00:24:37.892810 8, 0x0, sum = 1
4299 00:24:37.896014 9, 0x0, sum = 2
4300 00:24:37.896095 10, 0x0, sum = 3
4301 00:24:37.899286 11, 0x0, sum = 4
4302 00:24:37.899414 best_step = 9
4303 00:24:37.899481
4304 00:24:37.899540 ==
4305 00:24:37.902226 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 00:24:37.909035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 00:24:37.909116 ==
4308 00:24:37.909180 RX Vref Scan: 0
4309 00:24:37.909239
4310 00:24:37.912106 RX Vref 0 -> 0, step: 1
4311 00:24:37.912186
4312 00:24:37.915420 RX Delay -195 -> 252, step: 8
4313 00:24:37.918850 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4314 00:24:37.925884 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4315 00:24:37.928627 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4316 00:24:37.932471 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4317 00:24:37.935460 iDelay=205, Bit 4, Center 28 (-131 ~ 188) 320
4318 00:24:37.942534 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4319 00:24:37.946163 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4320 00:24:37.949290 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4321 00:24:37.951909 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4322 00:24:37.955343 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4323 00:24:37.962221 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4324 00:24:37.965358 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4325 00:24:37.968931 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4326 00:24:37.972127 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4327 00:24:37.978988 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4328 00:24:37.982254 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4329 00:24:37.982334 ==
4330 00:24:37.985621 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 00:24:37.988593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 00:24:37.988673 ==
4333 00:24:37.992279 DQS Delay:
4334 00:24:37.992360 DQS0 = 0, DQS1 = 0
4335 00:24:37.992424 DQM Delay:
4336 00:24:37.995614 DQM0 = 33, DQM1 = 27
4337 00:24:37.995694 DQ Delay:
4338 00:24:37.998904 DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =28
4339 00:24:38.002759 DQ4 =28, DQ5 =24, DQ6 =44, DQ7 =44
4340 00:24:38.005356 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4341 00:24:38.008782 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4342 00:24:38.008861
4343 00:24:38.008924
4344 00:24:38.018922 [DQSOSCAuto] RK1, (LSB)MR18= 0x713f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 388 ps
4345 00:24:38.019003 CH0 RK1: MR19=808, MR18=713F
4346 00:24:38.025753 CH0_RK1: MR19=0x808, MR18=0x713F, DQSOSC=388, MR23=63, INC=174, DEC=116
4347 00:24:38.028859 [RxdqsGatingPostProcess] freq 600
4348 00:24:38.035225 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4349 00:24:38.038833 Pre-setting of DQS Precalculation
4350 00:24:38.042260 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4351 00:24:38.042340 ==
4352 00:24:38.045223 Dram Type= 6, Freq= 0, CH_1, rank 0
4353 00:24:38.052403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4354 00:24:38.052482 ==
4355 00:24:38.055130 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4356 00:24:38.062121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4357 00:24:38.065252 [CA 0] Center 35 (5~66) winsize 62
4358 00:24:38.068735 [CA 1] Center 35 (5~66) winsize 62
4359 00:24:38.072081 [CA 2] Center 34 (4~65) winsize 62
4360 00:24:38.075361 [CA 3] Center 34 (4~65) winsize 62
4361 00:24:38.078245 [CA 4] Center 34 (4~65) winsize 62
4362 00:24:38.081681 [CA 5] Center 33 (3~64) winsize 62
4363 00:24:38.081762
4364 00:24:38.085174 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4365 00:24:38.085255
4366 00:24:38.088062 [CATrainingPosCal] consider 1 rank data
4367 00:24:38.091385 u2DelayCellTimex100 = 270/100 ps
4368 00:24:38.094783 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4369 00:24:38.098676 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4370 00:24:38.104944 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4371 00:24:38.108468 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4372 00:24:38.111926 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4373 00:24:38.114852 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4374 00:24:38.114932
4375 00:24:38.118269 CA PerBit enable=1, Macro0, CA PI delay=33
4376 00:24:38.118349
4377 00:24:38.121170 [CBTSetCACLKResult] CA Dly = 33
4378 00:24:38.121286 CS Dly: 4 (0~35)
4379 00:24:38.124517 ==
4380 00:24:38.124624 Dram Type= 6, Freq= 0, CH_1, rank 1
4381 00:24:38.131514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4382 00:24:38.131590 ==
4383 00:24:38.134927 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4384 00:24:38.141044 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4385 00:24:38.144774 [CA 0] Center 35 (5~66) winsize 62
4386 00:24:38.148789 [CA 1] Center 35 (5~66) winsize 62
4387 00:24:38.151481 [CA 2] Center 34 (4~65) winsize 62
4388 00:24:38.154896 [CA 3] Center 34 (3~65) winsize 63
4389 00:24:38.158308 [CA 4] Center 34 (4~65) winsize 62
4390 00:24:38.162001 [CA 5] Center 33 (3~64) winsize 62
4391 00:24:38.162103
4392 00:24:38.165201 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4393 00:24:38.165299
4394 00:24:38.168067 [CATrainingPosCal] consider 2 rank data
4395 00:24:38.171345 u2DelayCellTimex100 = 270/100 ps
4396 00:24:38.174687 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4397 00:24:38.181372 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4398 00:24:38.184537 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4399 00:24:38.188063 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4400 00:24:38.191339 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4401 00:24:38.194399 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4402 00:24:38.194483
4403 00:24:38.197832 CA PerBit enable=1, Macro0, CA PI delay=33
4404 00:24:38.197936
4405 00:24:38.201325 [CBTSetCACLKResult] CA Dly = 33
4406 00:24:38.201407 CS Dly: 4 (0~36)
4407 00:24:38.204578
4408 00:24:38.208081 ----->DramcWriteLeveling(PI) begin...
4409 00:24:38.208162 ==
4410 00:24:38.211520 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 00:24:38.214811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 00:24:38.214892 ==
4413 00:24:38.218013 Write leveling (Byte 0): 28 => 28
4414 00:24:38.221493 Write leveling (Byte 1): 29 => 29
4415 00:24:38.224488 DramcWriteLeveling(PI) end<-----
4416 00:24:38.224568
4417 00:24:38.224631 ==
4418 00:24:38.228299 Dram Type= 6, Freq= 0, CH_1, rank 0
4419 00:24:38.231062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 00:24:38.231143 ==
4421 00:24:38.234503 [Gating] SW mode calibration
4422 00:24:38.241350 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4423 00:24:38.247555 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4424 00:24:38.251025 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4425 00:24:38.254590 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4426 00:24:38.261127 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4427 00:24:38.264217 0 9 12 | B1->B0 | 3131 3232 | 0 0 | (0 1) (1 0)
4428 00:24:38.267476 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4429 00:24:38.274280 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 00:24:38.277531 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 00:24:38.281001 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 00:24:38.284305 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 00:24:38.291055 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 00:24:38.293935 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 00:24:38.297404 0 10 12 | B1->B0 | 2626 2f2f | 0 1 | (0 0) (0 0)
4436 00:24:38.304106 0 10 16 | B1->B0 | 4242 4040 | 0 0 | (0 0) (0 0)
4437 00:24:38.307391 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 00:24:38.310641 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 00:24:38.317705 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 00:24:38.320581 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 00:24:38.324195 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 00:24:38.330483 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 00:24:38.334215 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 00:24:38.337068 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 00:24:38.343673 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 00:24:38.346984 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 00:24:38.350396 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 00:24:38.357029 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 00:24:38.360247 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 00:24:38.363719 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 00:24:38.370452 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 00:24:38.374056 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 00:24:38.376936 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 00:24:38.383430 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 00:24:38.387017 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 00:24:38.390524 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 00:24:38.396993 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 00:24:38.400095 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 00:24:38.403858 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4460 00:24:38.410213 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 00:24:38.410293 Total UI for P1: 0, mck2ui 16
4462 00:24:38.417531 best dqsien dly found for B0: ( 0, 13, 12)
4463 00:24:38.417621 Total UI for P1: 0, mck2ui 16
4464 00:24:38.420336 best dqsien dly found for B1: ( 0, 13, 12)
4465 00:24:38.426994 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4466 00:24:38.430252 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4467 00:24:38.430332
4468 00:24:38.433724 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4469 00:24:38.437111 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4470 00:24:38.440150 [Gating] SW calibration Done
4471 00:24:38.440231 ==
4472 00:24:38.443339 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 00:24:38.446899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 00:24:38.446979 ==
4475 00:24:38.450479 RX Vref Scan: 0
4476 00:24:38.450559
4477 00:24:38.450623 RX Vref 0 -> 0, step: 1
4478 00:24:38.450683
4479 00:24:38.453786 RX Delay -230 -> 252, step: 16
4480 00:24:38.456645 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4481 00:24:38.463134 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4482 00:24:38.466841 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4483 00:24:38.470195 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4484 00:24:38.473103 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4485 00:24:38.479988 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4486 00:24:38.483478 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4487 00:24:38.487123 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4488 00:24:38.489681 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4489 00:24:38.496643 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4490 00:24:38.499809 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4491 00:24:38.502865 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4492 00:24:38.506306 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4493 00:24:38.513054 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4494 00:24:38.516237 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4495 00:24:38.519405 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4496 00:24:38.519500 ==
4497 00:24:38.522685 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 00:24:38.526138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 00:24:38.526219 ==
4500 00:24:38.529298 DQS Delay:
4501 00:24:38.529422 DQS0 = 0, DQS1 = 0
4502 00:24:38.532605 DQM Delay:
4503 00:24:38.532685 DQM0 = 39, DQM1 = 28
4504 00:24:38.532749 DQ Delay:
4505 00:24:38.535857 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4506 00:24:38.539595 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4507 00:24:38.542786 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4508 00:24:38.546293 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4509 00:24:38.546373
4510 00:24:38.546436
4511 00:24:38.549105 ==
4512 00:24:38.552523 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 00:24:38.555861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 00:24:38.555942 ==
4515 00:24:38.556006
4516 00:24:38.556065
4517 00:24:38.559318 TX Vref Scan disable
4518 00:24:38.559457 == TX Byte 0 ==
4519 00:24:38.566054 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4520 00:24:38.569364 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4521 00:24:38.569463 == TX Byte 1 ==
4522 00:24:38.575692 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4523 00:24:38.579206 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4524 00:24:38.579296 ==
4525 00:24:38.582839 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 00:24:38.586032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 00:24:38.586105 ==
4528 00:24:38.586166
4529 00:24:38.586224
4530 00:24:38.589233 TX Vref Scan disable
4531 00:24:38.592379 == TX Byte 0 ==
4532 00:24:38.595635 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4533 00:24:38.599094 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4534 00:24:38.602221 == TX Byte 1 ==
4535 00:24:38.605461 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4536 00:24:38.609425 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4537 00:24:38.609511
4538 00:24:38.612449 [DATLAT]
4539 00:24:38.612529 Freq=600, CH1 RK0
4540 00:24:38.612594
4541 00:24:38.615572 DATLAT Default: 0x9
4542 00:24:38.615653 0, 0xFFFF, sum = 0
4543 00:24:38.619084 1, 0xFFFF, sum = 0
4544 00:24:38.619165 2, 0xFFFF, sum = 0
4545 00:24:38.622447 3, 0xFFFF, sum = 0
4546 00:24:38.622527 4, 0xFFFF, sum = 0
4547 00:24:38.625693 5, 0xFFFF, sum = 0
4548 00:24:38.625774 6, 0xFFFF, sum = 0
4549 00:24:38.628686 7, 0xFFFF, sum = 0
4550 00:24:38.628768 8, 0x0, sum = 1
4551 00:24:38.632351 9, 0x0, sum = 2
4552 00:24:38.632432 10, 0x0, sum = 3
4553 00:24:38.635339 11, 0x0, sum = 4
4554 00:24:38.635437 best_step = 9
4555 00:24:38.635502
4556 00:24:38.635561 ==
4557 00:24:38.638937 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 00:24:38.642090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 00:24:38.645646 ==
4560 00:24:38.645726 RX Vref Scan: 1
4561 00:24:38.645789
4562 00:24:38.648974 RX Vref 0 -> 0, step: 1
4563 00:24:38.649054
4564 00:24:38.652396 RX Delay -195 -> 252, step: 8
4565 00:24:38.652477
4566 00:24:38.655588 Set Vref, RX VrefLevel [Byte0]: 55
4567 00:24:38.658954 [Byte1]: 50
4568 00:24:38.659033
4569 00:24:38.661915 Final RX Vref Byte 0 = 55 to rank0
4570 00:24:38.665483 Final RX Vref Byte 1 = 50 to rank0
4571 00:24:38.668688 Final RX Vref Byte 0 = 55 to rank1
4572 00:24:38.671963 Final RX Vref Byte 1 = 50 to rank1==
4573 00:24:38.675766 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 00:24:38.679141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 00:24:38.679221 ==
4576 00:24:38.682064 DQS Delay:
4577 00:24:38.682143 DQS0 = 0, DQS1 = 0
4578 00:24:38.682207 DQM Delay:
4579 00:24:38.685334 DQM0 = 38, DQM1 = 28
4580 00:24:38.685429 DQ Delay:
4581 00:24:38.688622 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4582 00:24:38.692298 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4583 00:24:38.695048 DQ8 =16, DQ9 =16, DQ10 =28, DQ11 =20
4584 00:24:38.699075 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4585 00:24:38.699156
4586 00:24:38.699219
4587 00:24:38.708604 [DQSOSCAuto] RK0, (LSB)MR18= 0x212e, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
4588 00:24:38.708685 CH1 RK0: MR19=808, MR18=212E
4589 00:24:38.714940 CH1_RK0: MR19=0x808, MR18=0x212E, DQSOSC=401, MR23=63, INC=163, DEC=108
4590 00:24:38.715020
4591 00:24:38.718709 ----->DramcWriteLeveling(PI) begin...
4592 00:24:38.721805 ==
4593 00:24:38.721924 Dram Type= 6, Freq= 0, CH_1, rank 1
4594 00:24:38.728021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 00:24:38.728102 ==
4596 00:24:38.731554 Write leveling (Byte 0): 31 => 31
4597 00:24:38.734685 Write leveling (Byte 1): 31 => 31
4598 00:24:38.738506 DramcWriteLeveling(PI) end<-----
4599 00:24:38.738595
4600 00:24:38.738693 ==
4601 00:24:38.741394 Dram Type= 6, Freq= 0, CH_1, rank 1
4602 00:24:38.744513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 00:24:38.744613 ==
4604 00:24:38.748114 [Gating] SW mode calibration
4605 00:24:38.754953 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4606 00:24:38.761275 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4607 00:24:38.764739 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4608 00:24:38.767938 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4609 00:24:38.774347 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4610 00:24:38.777715 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
4611 00:24:38.781135 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4612 00:24:38.784951 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 00:24:38.790855 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 00:24:38.794280 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 00:24:38.797543 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 00:24:38.804106 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 00:24:38.807263 0 10 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4618 00:24:38.810996 0 10 12 | B1->B0 | 3030 4242 | 1 0 | (0 0) (0 0)
4619 00:24:38.817465 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
4620 00:24:38.820898 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 00:24:38.824125 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 00:24:38.830906 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 00:24:38.833997 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 00:24:38.837358 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 00:24:38.844213 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 00:24:38.847646 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 00:24:38.851088 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 00:24:38.857252 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 00:24:38.861147 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 00:24:38.864097 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 00:24:38.870696 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 00:24:38.873917 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 00:24:38.877038 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 00:24:38.884070 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 00:24:38.887540 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 00:24:38.890435 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 00:24:38.897642 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 00:24:38.900223 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 00:24:38.903664 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 00:24:38.910272 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 00:24:38.913648 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 00:24:38.917008 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4643 00:24:38.920248 Total UI for P1: 0, mck2ui 16
4644 00:24:38.923916 best dqsien dly found for B0: ( 0, 13, 10)
4645 00:24:38.930201 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 00:24:38.930302 Total UI for P1: 0, mck2ui 16
4647 00:24:38.936885 best dqsien dly found for B1: ( 0, 13, 12)
4648 00:24:38.940033 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4649 00:24:38.943177 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4650 00:24:38.943250
4651 00:24:38.946803 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4652 00:24:38.949944 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4653 00:24:38.953429 [Gating] SW calibration Done
4654 00:24:38.953514 ==
4655 00:24:38.956848 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 00:24:38.959841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 00:24:38.959917 ==
4658 00:24:38.963232 RX Vref Scan: 0
4659 00:24:38.963327
4660 00:24:38.963444 RX Vref 0 -> 0, step: 1
4661 00:24:38.963503
4662 00:24:38.966825 RX Delay -230 -> 252, step: 16
4663 00:24:38.972958 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4664 00:24:38.976446 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4665 00:24:38.979797 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4666 00:24:38.983162 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4667 00:24:38.989787 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4668 00:24:38.993112 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4669 00:24:38.996573 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4670 00:24:38.999291 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4671 00:24:39.003145 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4672 00:24:39.009260 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4673 00:24:39.012979 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4674 00:24:39.016202 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4675 00:24:39.019248 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4676 00:24:39.026306 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4677 00:24:39.029473 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4678 00:24:39.032727 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4679 00:24:39.032798 ==
4680 00:24:39.035923 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 00:24:39.039243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 00:24:39.042621 ==
4683 00:24:39.042718 DQS Delay:
4684 00:24:39.042806 DQS0 = 0, DQS1 = 0
4685 00:24:39.045596 DQM Delay:
4686 00:24:39.045665 DQM0 = 35, DQM1 = 29
4687 00:24:39.049042 DQ Delay:
4688 00:24:39.052457 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4689 00:24:39.052529 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4690 00:24:39.055565 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4691 00:24:39.059060 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4692 00:24:39.062865
4693 00:24:39.062986
4694 00:24:39.063099 ==
4695 00:24:39.066092 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 00:24:39.069020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 00:24:39.069094 ==
4698 00:24:39.069155
4699 00:24:39.069212
4700 00:24:39.072119 TX Vref Scan disable
4701 00:24:39.072214 == TX Byte 0 ==
4702 00:24:39.078720 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4703 00:24:39.082304 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4704 00:24:39.082377 == TX Byte 1 ==
4705 00:24:39.088677 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4706 00:24:39.092381 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4707 00:24:39.092479 ==
4708 00:24:39.095306 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 00:24:39.098820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 00:24:39.098922 ==
4711 00:24:39.099011
4712 00:24:39.099096
4713 00:24:39.101646 TX Vref Scan disable
4714 00:24:39.104970 == TX Byte 0 ==
4715 00:24:39.108404 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4716 00:24:39.115267 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4717 00:24:39.115365 == TX Byte 1 ==
4718 00:24:39.118807 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4719 00:24:39.125198 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4720 00:24:39.125278
4721 00:24:39.125340 [DATLAT]
4722 00:24:39.125398 Freq=600, CH1 RK1
4723 00:24:39.125454
4724 00:24:39.128241 DATLAT Default: 0x9
4725 00:24:39.128309 0, 0xFFFF, sum = 0
4726 00:24:39.131918 1, 0xFFFF, sum = 0
4727 00:24:39.131992 2, 0xFFFF, sum = 0
4728 00:24:39.135098 3, 0xFFFF, sum = 0
4729 00:24:39.138688 4, 0xFFFF, sum = 0
4730 00:24:39.138760 5, 0xFFFF, sum = 0
4731 00:24:39.141681 6, 0xFFFF, sum = 0
4732 00:24:39.141755 7, 0xFFFF, sum = 0
4733 00:24:39.145071 8, 0x0, sum = 1
4734 00:24:39.145145 9, 0x0, sum = 2
4735 00:24:39.145206 10, 0x0, sum = 3
4736 00:24:39.148179 11, 0x0, sum = 4
4737 00:24:39.148258 best_step = 9
4738 00:24:39.148321
4739 00:24:39.151469 ==
4740 00:24:39.151548 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 00:24:39.158345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 00:24:39.158426 ==
4743 00:24:39.158489 RX Vref Scan: 0
4744 00:24:39.158548
4745 00:24:39.161466 RX Vref 0 -> 0, step: 1
4746 00:24:39.161546
4747 00:24:39.164434 RX Delay -195 -> 252, step: 8
4748 00:24:39.171028 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4749 00:24:39.174736 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4750 00:24:39.177901 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4751 00:24:39.181150 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4752 00:24:39.184641 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4753 00:24:39.190917 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4754 00:24:39.194307 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4755 00:24:39.197761 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4756 00:24:39.201128 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4757 00:24:39.207302 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4758 00:24:39.210798 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4759 00:24:39.214254 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4760 00:24:39.217683 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4761 00:24:39.224256 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4762 00:24:39.227978 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4763 00:24:39.230653 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4764 00:24:39.230734 ==
4765 00:24:39.234214 Dram Type= 6, Freq= 0, CH_1, rank 1
4766 00:24:39.237551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4767 00:24:39.240563 ==
4768 00:24:39.240643 DQS Delay:
4769 00:24:39.240708 DQS0 = 0, DQS1 = 0
4770 00:24:39.243987 DQM Delay:
4771 00:24:39.244067 DQM0 = 36, DQM1 = 28
4772 00:24:39.247416 DQ Delay:
4773 00:24:39.247497 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4774 00:24:39.250782 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4775 00:24:39.253872 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =20
4776 00:24:39.257057 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4777 00:24:39.257137
4778 00:24:39.260453
4779 00:24:39.267215 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a59, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 398 ps
4780 00:24:39.270539 CH1 RK1: MR19=808, MR18=3A59
4781 00:24:39.277063 CH1_RK1: MR19=0x808, MR18=0x3A59, DQSOSC=393, MR23=63, INC=169, DEC=113
4782 00:24:39.280425 [RxdqsGatingPostProcess] freq 600
4783 00:24:39.283669 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4784 00:24:39.286912 Pre-setting of DQS Precalculation
4785 00:24:39.293777 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4786 00:24:39.300278 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4787 00:24:39.307061 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4788 00:24:39.307164
4789 00:24:39.307257
4790 00:24:39.310165 [Calibration Summary] 1200 Mbps
4791 00:24:39.310263 CH 0, Rank 0
4792 00:24:39.313526 SW Impedance : PASS
4793 00:24:39.316650 DUTY Scan : NO K
4794 00:24:39.316723 ZQ Calibration : PASS
4795 00:24:39.320248 Jitter Meter : NO K
4796 00:24:39.320320 CBT Training : PASS
4797 00:24:39.323351 Write leveling : PASS
4798 00:24:39.326663 RX DQS gating : PASS
4799 00:24:39.326739 RX DQ/DQS(RDDQC) : PASS
4800 00:24:39.330121 TX DQ/DQS : PASS
4801 00:24:39.333068 RX DATLAT : PASS
4802 00:24:39.333139 RX DQ/DQS(Engine): PASS
4803 00:24:39.336510 TX OE : NO K
4804 00:24:39.336580 All Pass.
4805 00:24:39.336643
4806 00:24:39.339944 CH 0, Rank 1
4807 00:24:39.340011 SW Impedance : PASS
4808 00:24:39.343301 DUTY Scan : NO K
4809 00:24:39.346716 ZQ Calibration : PASS
4810 00:24:39.346811 Jitter Meter : NO K
4811 00:24:39.350218 CBT Training : PASS
4812 00:24:39.353103 Write leveling : PASS
4813 00:24:39.353174 RX DQS gating : PASS
4814 00:24:39.356980 RX DQ/DQS(RDDQC) : PASS
4815 00:24:39.359976 TX DQ/DQS : PASS
4816 00:24:39.360045 RX DATLAT : PASS
4817 00:24:39.363288 RX DQ/DQS(Engine): PASS
4818 00:24:39.366413 TX OE : NO K
4819 00:24:39.366510 All Pass.
4820 00:24:39.366597
4821 00:24:39.366682 CH 1, Rank 0
4822 00:24:39.369844 SW Impedance : PASS
4823 00:24:39.373336 DUTY Scan : NO K
4824 00:24:39.373436 ZQ Calibration : PASS
4825 00:24:39.376728 Jitter Meter : NO K
4826 00:24:39.376798 CBT Training : PASS
4827 00:24:39.380178 Write leveling : PASS
4828 00:24:39.382978 RX DQS gating : PASS
4829 00:24:39.383051 RX DQ/DQS(RDDQC) : PASS
4830 00:24:39.386471 TX DQ/DQS : PASS
4831 00:24:39.389771 RX DATLAT : PASS
4832 00:24:39.389841 RX DQ/DQS(Engine): PASS
4833 00:24:39.393027 TX OE : NO K
4834 00:24:39.393123 All Pass.
4835 00:24:39.393210
4836 00:24:39.396392 CH 1, Rank 1
4837 00:24:39.396465 SW Impedance : PASS
4838 00:24:39.399646 DUTY Scan : NO K
4839 00:24:39.402896 ZQ Calibration : PASS
4840 00:24:39.402970 Jitter Meter : NO K
4841 00:24:39.406530 CBT Training : PASS
4842 00:24:39.409478 Write leveling : PASS
4843 00:24:39.409549 RX DQS gating : PASS
4844 00:24:39.413157 RX DQ/DQS(RDDQC) : PASS
4845 00:24:39.416662 TX DQ/DQS : PASS
4846 00:24:39.416732 RX DATLAT : PASS
4847 00:24:39.420011 RX DQ/DQS(Engine): PASS
4848 00:24:39.422899 TX OE : NO K
4849 00:24:39.422972 All Pass.
4850 00:24:39.423038
4851 00:24:39.423097 DramC Write-DBI off
4852 00:24:39.426168 PER_BANK_REFRESH: Hybrid Mode
4853 00:24:39.429526 TX_TRACKING: ON
4854 00:24:39.436215 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4855 00:24:39.439777 [FAST_K] Save calibration result to emmc
4856 00:24:39.446190 dramc_set_vcore_voltage set vcore to 662500
4857 00:24:39.446265 Read voltage for 933, 3
4858 00:24:39.446327 Vio18 = 0
4859 00:24:39.449676 Vcore = 662500
4860 00:24:39.449749 Vdram = 0
4861 00:24:39.449809 Vddq = 0
4862 00:24:39.452719 Vmddr = 0
4863 00:24:39.456190 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4864 00:24:39.463462 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4865 00:24:39.465937 MEM_TYPE=3, freq_sel=17
4866 00:24:39.466008 sv_algorithm_assistance_LP4_1600
4867 00:24:39.472566 ============ PULL DRAM RESETB DOWN ============
4868 00:24:39.476144 ========== PULL DRAM RESETB DOWN end =========
4869 00:24:39.479521 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4870 00:24:39.482750 ===================================
4871 00:24:39.486098 LPDDR4 DRAM CONFIGURATION
4872 00:24:39.489624 ===================================
4873 00:24:39.492431 EX_ROW_EN[0] = 0x0
4874 00:24:39.492528 EX_ROW_EN[1] = 0x0
4875 00:24:39.495910 LP4Y_EN = 0x0
4876 00:24:39.495983 WORK_FSP = 0x0
4877 00:24:39.499492 WL = 0x3
4878 00:24:39.499563 RL = 0x3
4879 00:24:39.503050 BL = 0x2
4880 00:24:39.503146 RPST = 0x0
4881 00:24:39.505887 RD_PRE = 0x0
4882 00:24:39.505984 WR_PRE = 0x1
4883 00:24:39.508912 WR_PST = 0x0
4884 00:24:39.508997 DBI_WR = 0x0
4885 00:24:39.512208 DBI_RD = 0x0
4886 00:24:39.512282 OTF = 0x1
4887 00:24:39.515595 ===================================
4888 00:24:39.519176 ===================================
4889 00:24:39.522521 ANA top config
4890 00:24:39.525728 ===================================
4891 00:24:39.529317 DLL_ASYNC_EN = 0
4892 00:24:39.529389 ALL_SLAVE_EN = 1
4893 00:24:39.532503 NEW_RANK_MODE = 1
4894 00:24:39.535742 DLL_IDLE_MODE = 1
4895 00:24:39.539148 LP45_APHY_COMB_EN = 1
4896 00:24:39.542053 TX_ODT_DIS = 1
4897 00:24:39.542128 NEW_8X_MODE = 1
4898 00:24:39.545507 ===================================
4899 00:24:39.548715 ===================================
4900 00:24:39.552426 data_rate = 1866
4901 00:24:39.555556 CKR = 1
4902 00:24:39.559067 DQ_P2S_RATIO = 8
4903 00:24:39.562159 ===================================
4904 00:24:39.565537 CA_P2S_RATIO = 8
4905 00:24:39.565615 DQ_CA_OPEN = 0
4906 00:24:39.569010 DQ_SEMI_OPEN = 0
4907 00:24:39.572512 CA_SEMI_OPEN = 0
4908 00:24:39.575657 CA_FULL_RATE = 0
4909 00:24:39.578714 DQ_CKDIV4_EN = 1
4910 00:24:39.581729 CA_CKDIV4_EN = 1
4911 00:24:39.585358 CA_PREDIV_EN = 0
4912 00:24:39.585441 PH8_DLY = 0
4913 00:24:39.588683 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4914 00:24:39.592252 DQ_AAMCK_DIV = 4
4915 00:24:39.595032 CA_AAMCK_DIV = 4
4916 00:24:39.598956 CA_ADMCK_DIV = 4
4917 00:24:39.599054 DQ_TRACK_CA_EN = 0
4918 00:24:39.602266 CA_PICK = 933
4919 00:24:39.605086 CA_MCKIO = 933
4920 00:24:39.608730 MCKIO_SEMI = 0
4921 00:24:39.612112 PLL_FREQ = 3732
4922 00:24:39.615283 DQ_UI_PI_RATIO = 32
4923 00:24:39.618299 CA_UI_PI_RATIO = 0
4924 00:24:39.621697 ===================================
4925 00:24:39.625103 ===================================
4926 00:24:39.625201 memory_type:LPDDR4
4927 00:24:39.628248 GP_NUM : 10
4928 00:24:39.631922 SRAM_EN : 1
4929 00:24:39.631990 MD32_EN : 0
4930 00:24:39.635321 ===================================
4931 00:24:39.638196 [ANA_INIT] >>>>>>>>>>>>>>
4932 00:24:39.641391 <<<<<< [CONFIGURE PHASE]: ANA_TX
4933 00:24:39.645307 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4934 00:24:39.648301 ===================================
4935 00:24:39.652054 data_rate = 1866,PCW = 0X8f00
4936 00:24:39.654817 ===================================
4937 00:24:39.658799 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4938 00:24:39.661568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4939 00:24:39.668058 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4940 00:24:39.671911 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4941 00:24:39.674501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4942 00:24:39.681500 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4943 00:24:39.681579 [ANA_INIT] flow start
4944 00:24:39.684652 [ANA_INIT] PLL >>>>>>>>
4945 00:24:39.684767 [ANA_INIT] PLL <<<<<<<<
4946 00:24:39.688460 [ANA_INIT] MIDPI >>>>>>>>
4947 00:24:39.691287 [ANA_INIT] MIDPI <<<<<<<<
4948 00:24:39.694531 [ANA_INIT] DLL >>>>>>>>
4949 00:24:39.694647 [ANA_INIT] flow end
4950 00:24:39.698329 ============ LP4 DIFF to SE enter ============
4951 00:24:39.704971 ============ LP4 DIFF to SE exit ============
4952 00:24:39.705072 [ANA_INIT] <<<<<<<<<<<<<
4953 00:24:39.707880 [Flow] Enable top DCM control >>>>>
4954 00:24:39.711152 [Flow] Enable top DCM control <<<<<
4955 00:24:39.714800 Enable DLL master slave shuffle
4956 00:24:39.721220 ==============================================================
4957 00:24:39.721308 Gating Mode config
4958 00:24:39.728178 ==============================================================
4959 00:24:39.730967 Config description:
4960 00:24:39.741306 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4961 00:24:39.748147 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4962 00:24:39.751196 SELPH_MODE 0: By rank 1: By Phase
4963 00:24:39.757533 ==============================================================
4964 00:24:39.761287 GAT_TRACK_EN = 1
4965 00:24:39.764403 RX_GATING_MODE = 2
4966 00:24:39.764478 RX_GATING_TRACK_MODE = 2
4967 00:24:39.767339 SELPH_MODE = 1
4968 00:24:39.770787 PICG_EARLY_EN = 1
4969 00:24:39.774177 VALID_LAT_VALUE = 1
4970 00:24:39.781307 ==============================================================
4971 00:24:39.784220 Enter into Gating configuration >>>>
4972 00:24:39.787426 Exit from Gating configuration <<<<
4973 00:24:39.790919 Enter into DVFS_PRE_config >>>>>
4974 00:24:39.801283 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4975 00:24:39.804179 Exit from DVFS_PRE_config <<<<<
4976 00:24:39.807652 Enter into PICG configuration >>>>
4977 00:24:39.810682 Exit from PICG configuration <<<<
4978 00:24:39.814070 [RX_INPUT] configuration >>>>>
4979 00:24:39.817186 [RX_INPUT] configuration <<<<<
4980 00:24:39.820551 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4981 00:24:39.827291 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4982 00:24:39.833481 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4983 00:24:39.840147 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4984 00:24:39.846642 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4985 00:24:39.849919 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4986 00:24:39.856691 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4987 00:24:39.860631 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4988 00:24:39.863649 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4989 00:24:39.867008 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4990 00:24:39.869988 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4991 00:24:39.876847 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4992 00:24:39.879784 ===================================
4993 00:24:39.883519 LPDDR4 DRAM CONFIGURATION
4994 00:24:39.886725 ===================================
4995 00:24:39.886822 EX_ROW_EN[0] = 0x0
4996 00:24:39.889842 EX_ROW_EN[1] = 0x0
4997 00:24:39.889947 LP4Y_EN = 0x0
4998 00:24:39.893948 WORK_FSP = 0x0
4999 00:24:39.894046 WL = 0x3
5000 00:24:39.896515 RL = 0x3
5001 00:24:39.896597 BL = 0x2
5002 00:24:39.899805 RPST = 0x0
5003 00:24:39.899888 RD_PRE = 0x0
5004 00:24:39.903158 WR_PRE = 0x1
5005 00:24:39.903251 WR_PST = 0x0
5006 00:24:39.906935 DBI_WR = 0x0
5007 00:24:39.907036 DBI_RD = 0x0
5008 00:24:39.909773 OTF = 0x1
5009 00:24:39.913335 ===================================
5010 00:24:39.917085 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5011 00:24:39.920033 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5012 00:24:39.927061 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5013 00:24:39.930045 ===================================
5014 00:24:39.930124 LPDDR4 DRAM CONFIGURATION
5015 00:24:39.933744 ===================================
5016 00:24:39.936372 EX_ROW_EN[0] = 0x10
5017 00:24:39.940158 EX_ROW_EN[1] = 0x0
5018 00:24:39.940237 LP4Y_EN = 0x0
5019 00:24:39.943184 WORK_FSP = 0x0
5020 00:24:39.943263 WL = 0x3
5021 00:24:39.946666 RL = 0x3
5022 00:24:39.946745 BL = 0x2
5023 00:24:39.950106 RPST = 0x0
5024 00:24:39.950184 RD_PRE = 0x0
5025 00:24:39.953399 WR_PRE = 0x1
5026 00:24:39.953477 WR_PST = 0x0
5027 00:24:39.956798 DBI_WR = 0x0
5028 00:24:39.956877 DBI_RD = 0x0
5029 00:24:39.959552 OTF = 0x1
5030 00:24:39.963154 ===================================
5031 00:24:39.969499 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5032 00:24:39.973020 nWR fixed to 30
5033 00:24:39.976415 [ModeRegInit_LP4] CH0 RK0
5034 00:24:39.976493 [ModeRegInit_LP4] CH0 RK1
5035 00:24:39.979850 [ModeRegInit_LP4] CH1 RK0
5036 00:24:39.983037 [ModeRegInit_LP4] CH1 RK1
5037 00:24:39.983115 match AC timing 9
5038 00:24:39.989422 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5039 00:24:39.992801 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5040 00:24:39.995981 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5041 00:24:40.002685 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5042 00:24:40.006080 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5043 00:24:40.006179 ==
5044 00:24:40.009060 Dram Type= 6, Freq= 0, CH_0, rank 0
5045 00:24:40.012396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5046 00:24:40.012467 ==
5047 00:24:40.019310 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5048 00:24:40.026182 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5049 00:24:40.029165 [CA 0] Center 38 (7~69) winsize 63
5050 00:24:40.032795 [CA 1] Center 38 (7~69) winsize 63
5051 00:24:40.035979 [CA 2] Center 35 (5~65) winsize 61
5052 00:24:40.039286 [CA 3] Center 35 (5~65) winsize 61
5053 00:24:40.042297 [CA 4] Center 34 (4~65) winsize 62
5054 00:24:40.045610 [CA 5] Center 33 (3~64) winsize 62
5055 00:24:40.045679
5056 00:24:40.048815 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5057 00:24:40.048897
5058 00:24:40.052230 [CATrainingPosCal] consider 1 rank data
5059 00:24:40.055734 u2DelayCellTimex100 = 270/100 ps
5060 00:24:40.059108 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5061 00:24:40.062330 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5062 00:24:40.065550 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5063 00:24:40.069146 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5064 00:24:40.072161 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5065 00:24:40.075559 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5066 00:24:40.079089
5067 00:24:40.082707 CA PerBit enable=1, Macro0, CA PI delay=33
5068 00:24:40.082785
5069 00:24:40.085748 [CBTSetCACLKResult] CA Dly = 33
5070 00:24:40.085846 CS Dly: 6 (0~37)
5071 00:24:40.085943 ==
5072 00:24:40.088986 Dram Type= 6, Freq= 0, CH_0, rank 1
5073 00:24:40.092396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5074 00:24:40.092464 ==
5075 00:24:40.099180 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5076 00:24:40.105684 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5077 00:24:40.108756 [CA 0] Center 38 (8~69) winsize 62
5078 00:24:40.112585 [CA 1] Center 38 (8~69) winsize 62
5079 00:24:40.115426 [CA 2] Center 35 (5~66) winsize 62
5080 00:24:40.118700 [CA 3] Center 35 (5~66) winsize 62
5081 00:24:40.122034 [CA 4] Center 34 (4~65) winsize 62
5082 00:24:40.125249 [CA 5] Center 33 (3~64) winsize 62
5083 00:24:40.125322
5084 00:24:40.128530 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5085 00:24:40.128601
5086 00:24:40.131943 [CATrainingPosCal] consider 2 rank data
5087 00:24:40.135304 u2DelayCellTimex100 = 270/100 ps
5088 00:24:40.138561 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5089 00:24:40.141487 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5090 00:24:40.144907 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5091 00:24:40.151897 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5092 00:24:40.155267 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5093 00:24:40.158604 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5094 00:24:40.158704
5095 00:24:40.161549 CA PerBit enable=1, Macro0, CA PI delay=33
5096 00:24:40.161645
5097 00:24:40.164872 [CBTSetCACLKResult] CA Dly = 33
5098 00:24:40.164948 CS Dly: 7 (0~39)
5099 00:24:40.165044
5100 00:24:40.168013 ----->DramcWriteLeveling(PI) begin...
5101 00:24:40.168112 ==
5102 00:24:40.171511 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 00:24:40.178338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 00:24:40.178438 ==
5105 00:24:40.181209 Write leveling (Byte 0): 30 => 30
5106 00:24:40.184886 Write leveling (Byte 1): 32 => 32
5107 00:24:40.187795 DramcWriteLeveling(PI) end<-----
5108 00:24:40.187896
5109 00:24:40.187986 ==
5110 00:24:40.191460 Dram Type= 6, Freq= 0, CH_0, rank 0
5111 00:24:40.194608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5112 00:24:40.194708 ==
5113 00:24:40.198330 [Gating] SW mode calibration
5114 00:24:40.204484 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5115 00:24:40.207857 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5116 00:24:40.214528 0 14 0 | B1->B0 | 2323 3131 | 1 1 | (0 0) (0 0)
5117 00:24:40.217943 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5118 00:24:40.220933 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 00:24:40.228113 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 00:24:40.231049 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 00:24:40.237892 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 00:24:40.241134 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 00:24:40.244320 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5124 00:24:40.250767 0 15 0 | B1->B0 | 3434 2b2b | 0 0 | (0 1) (0 0)
5125 00:24:40.254196 0 15 4 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
5126 00:24:40.257658 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 00:24:40.263888 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 00:24:40.267243 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 00:24:40.270461 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 00:24:40.276941 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 00:24:40.280626 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5132 00:24:40.283903 1 0 0 | B1->B0 | 2828 3939 | 1 0 | (0 0) (0 0)
5133 00:24:40.287484 1 0 4 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
5134 00:24:40.294061 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 00:24:40.296759 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 00:24:40.300419 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 00:24:40.307257 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 00:24:40.310334 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 00:24:40.313769 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 00:24:40.320134 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5141 00:24:40.323479 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5142 00:24:40.326594 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 00:24:40.333390 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 00:24:40.336411 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 00:24:40.340075 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 00:24:40.346859 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 00:24:40.349776 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 00:24:40.353219 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 00:24:40.359605 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 00:24:40.363099 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 00:24:40.366073 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 00:24:40.372670 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 00:24:40.376265 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 00:24:40.379712 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 00:24:40.386662 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5156 00:24:40.389394 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5157 00:24:40.392628 Total UI for P1: 0, mck2ui 16
5158 00:24:40.396075 best dqsien dly found for B0: ( 1, 2, 28)
5159 00:24:40.399688 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5160 00:24:40.406260 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 00:24:40.409227 Total UI for P1: 0, mck2ui 16
5162 00:24:40.412667 best dqsien dly found for B1: ( 1, 3, 2)
5163 00:24:40.416093 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5164 00:24:40.419013 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5165 00:24:40.419117
5166 00:24:40.422292 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5167 00:24:40.426091 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5168 00:24:40.428989 [Gating] SW calibration Done
5169 00:24:40.429075 ==
5170 00:24:40.432238 Dram Type= 6, Freq= 0, CH_0, rank 0
5171 00:24:40.436029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5172 00:24:40.436140 ==
5173 00:24:40.438867 RX Vref Scan: 0
5174 00:24:40.438972
5175 00:24:40.439060 RX Vref 0 -> 0, step: 1
5176 00:24:40.442281
5177 00:24:40.442389 RX Delay -80 -> 252, step: 8
5178 00:24:40.448923 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5179 00:24:40.452259 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5180 00:24:40.455326 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5181 00:24:40.458933 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5182 00:24:40.462002 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5183 00:24:40.465281 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5184 00:24:40.471728 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5185 00:24:40.475223 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5186 00:24:40.478655 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5187 00:24:40.481904 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5188 00:24:40.485000 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5189 00:24:40.491830 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5190 00:24:40.495534 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5191 00:24:40.498203 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5192 00:24:40.501744 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5193 00:24:40.505117 iDelay=208, Bit 15, Center 87 (-16 ~ 191) 208
5194 00:24:40.508471 ==
5195 00:24:40.511423 Dram Type= 6, Freq= 0, CH_0, rank 0
5196 00:24:40.514951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5197 00:24:40.515024 ==
5198 00:24:40.515086 DQS Delay:
5199 00:24:40.518675 DQS0 = 0, DQS1 = 0
5200 00:24:40.518758 DQM Delay:
5201 00:24:40.521405 DQM0 = 94, DQM1 = 82
5202 00:24:40.521507 DQ Delay:
5203 00:24:40.524765 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5204 00:24:40.528069 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5205 00:24:40.531713 DQ8 =79, DQ9 =67, DQ10 =83, DQ11 =79
5206 00:24:40.534615 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =87
5207 00:24:40.534713
5208 00:24:40.534802
5209 00:24:40.534899 ==
5210 00:24:40.537820 Dram Type= 6, Freq= 0, CH_0, rank 0
5211 00:24:40.541186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5212 00:24:40.541261 ==
5213 00:24:40.541323
5214 00:24:40.541403
5215 00:24:40.544997 TX Vref Scan disable
5216 00:24:40.547830 == TX Byte 0 ==
5217 00:24:40.551405 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5218 00:24:40.554632 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5219 00:24:40.557807 == TX Byte 1 ==
5220 00:24:40.561251 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5221 00:24:40.564457 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5222 00:24:40.564563 ==
5223 00:24:40.567577 Dram Type= 6, Freq= 0, CH_0, rank 0
5224 00:24:40.574079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5225 00:24:40.574182 ==
5226 00:24:40.574272
5227 00:24:40.574359
5228 00:24:40.574419 TX Vref Scan disable
5229 00:24:40.578371 == TX Byte 0 ==
5230 00:24:40.582076 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5231 00:24:40.585234 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5232 00:24:40.588237 == TX Byte 1 ==
5233 00:24:40.591817 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5234 00:24:40.598283 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5235 00:24:40.598385
5236 00:24:40.598477 [DATLAT]
5237 00:24:40.598540 Freq=933, CH0 RK0
5238 00:24:40.598598
5239 00:24:40.602009 DATLAT Default: 0xd
5240 00:24:40.602108 0, 0xFFFF, sum = 0
5241 00:24:40.605375 1, 0xFFFF, sum = 0
5242 00:24:40.605478 2, 0xFFFF, sum = 0
5243 00:24:40.608597 3, 0xFFFF, sum = 0
5244 00:24:40.611768 4, 0xFFFF, sum = 0
5245 00:24:40.611843 5, 0xFFFF, sum = 0
5246 00:24:40.614674 6, 0xFFFF, sum = 0
5247 00:24:40.614764 7, 0xFFFF, sum = 0
5248 00:24:40.618097 8, 0xFFFF, sum = 0
5249 00:24:40.618175 9, 0xFFFF, sum = 0
5250 00:24:40.621550 10, 0x0, sum = 1
5251 00:24:40.621624 11, 0x0, sum = 2
5252 00:24:40.624962 12, 0x0, sum = 3
5253 00:24:40.625039 13, 0x0, sum = 4
5254 00:24:40.625101 best_step = 11
5255 00:24:40.625159
5256 00:24:40.628401 ==
5257 00:24:40.631638 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 00:24:40.634777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 00:24:40.634875 ==
5260 00:24:40.634963 RX Vref Scan: 1
5261 00:24:40.635049
5262 00:24:40.638777 RX Vref 0 -> 0, step: 1
5263 00:24:40.638880
5264 00:24:40.641409 RX Delay -77 -> 252, step: 4
5265 00:24:40.641482
5266 00:24:40.645022 Set Vref, RX VrefLevel [Byte0]: 61
5267 00:24:40.648016 [Byte1]: 54
5268 00:24:40.648092
5269 00:24:40.651509 Final RX Vref Byte 0 = 61 to rank0
5270 00:24:40.655213 Final RX Vref Byte 1 = 54 to rank0
5271 00:24:40.657910 Final RX Vref Byte 0 = 61 to rank1
5272 00:24:40.661347 Final RX Vref Byte 1 = 54 to rank1==
5273 00:24:40.664923 Dram Type= 6, Freq= 0, CH_0, rank 0
5274 00:24:40.668049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 00:24:40.671346 ==
5276 00:24:40.671463 DQS Delay:
5277 00:24:40.671526 DQS0 = 0, DQS1 = 0
5278 00:24:40.674702 DQM Delay:
5279 00:24:40.674788 DQM0 = 95, DQM1 = 83
5280 00:24:40.678067 DQ Delay:
5281 00:24:40.678140 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5282 00:24:40.681529 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =108
5283 00:24:40.684845 DQ8 =76, DQ9 =70, DQ10 =82, DQ11 =78
5284 00:24:40.691025 DQ12 =88, DQ13 =86, DQ14 =96, DQ15 =90
5285 00:24:40.691130
5286 00:24:40.691220
5287 00:24:40.697561 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5288 00:24:40.701416 CH0 RK0: MR19=505, MR18=1414
5289 00:24:40.707676 CH0_RK0: MR19=0x505, MR18=0x1414, DQSOSC=415, MR23=63, INC=62, DEC=41
5290 00:24:40.707769
5291 00:24:40.710916 ----->DramcWriteLeveling(PI) begin...
5292 00:24:40.710989 ==
5293 00:24:40.714691 Dram Type= 6, Freq= 0, CH_0, rank 1
5294 00:24:40.717605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 00:24:40.717676 ==
5296 00:24:40.721034 Write leveling (Byte 0): 31 => 31
5297 00:24:40.724375 Write leveling (Byte 1): 26 => 26
5298 00:24:40.727548 DramcWriteLeveling(PI) end<-----
5299 00:24:40.727621
5300 00:24:40.727682 ==
5301 00:24:40.731107 Dram Type= 6, Freq= 0, CH_0, rank 1
5302 00:24:40.734325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 00:24:40.734397 ==
5304 00:24:40.737546 [Gating] SW mode calibration
5305 00:24:40.744457 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5306 00:24:40.750882 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5307 00:24:40.754140 0 14 0 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
5308 00:24:40.760630 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 00:24:40.764109 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 00:24:40.767550 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 00:24:40.770972 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 00:24:40.777430 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 00:24:40.780803 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 00:24:40.784225 0 14 28 | B1->B0 | 3131 2828 | 1 0 | (1 1) (0 0)
5315 00:24:40.790547 0 15 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
5316 00:24:40.794082 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 00:24:40.797458 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 00:24:40.804530 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 00:24:40.807172 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 00:24:40.810669 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 00:24:40.817098 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 00:24:40.820405 0 15 28 | B1->B0 | 2424 3332 | 0 1 | (0 0) (0 0)
5323 00:24:40.823910 1 0 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5324 00:24:40.830666 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 00:24:40.834042 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 00:24:40.837081 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 00:24:40.843759 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 00:24:40.846974 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 00:24:40.850985 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 00:24:40.857453 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5331 00:24:40.860133 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5332 00:24:40.863355 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5333 00:24:40.870059 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 00:24:40.873330 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 00:24:40.876697 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 00:24:40.883765 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 00:24:40.887002 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 00:24:40.890154 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 00:24:40.896850 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 00:24:40.900434 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 00:24:40.903361 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 00:24:40.910037 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 00:24:40.913681 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 00:24:40.916723 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 00:24:40.919906 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5346 00:24:40.926526 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5347 00:24:40.930248 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5348 00:24:40.933263 Total UI for P1: 0, mck2ui 16
5349 00:24:40.936825 best dqsien dly found for B0: ( 1, 2, 26)
5350 00:24:40.940213 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 00:24:40.943131 Total UI for P1: 0, mck2ui 16
5352 00:24:40.946417 best dqsien dly found for B1: ( 1, 2, 30)
5353 00:24:40.950266 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5354 00:24:40.953382 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5355 00:24:40.956837
5356 00:24:40.959883 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5357 00:24:40.963318 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5358 00:24:40.966410 [Gating] SW calibration Done
5359 00:24:40.966490 ==
5360 00:24:40.970078 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 00:24:40.973207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 00:24:40.973288 ==
5363 00:24:40.973353 RX Vref Scan: 0
5364 00:24:40.976355
5365 00:24:40.976443 RX Vref 0 -> 0, step: 1
5366 00:24:40.976540
5367 00:24:40.979630 RX Delay -80 -> 252, step: 8
5368 00:24:40.982967 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5369 00:24:40.986674 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5370 00:24:40.992880 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5371 00:24:40.996186 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5372 00:24:40.999654 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5373 00:24:41.003134 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5374 00:24:41.006558 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5375 00:24:41.009460 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5376 00:24:41.016528 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5377 00:24:41.019379 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5378 00:24:41.023105 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5379 00:24:41.026221 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5380 00:24:41.032624 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5381 00:24:41.036080 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5382 00:24:41.039547 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5383 00:24:41.042954 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5384 00:24:41.043033 ==
5385 00:24:41.046196 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 00:24:41.049180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 00:24:41.052771 ==
5388 00:24:41.052851 DQS Delay:
5389 00:24:41.052915 DQS0 = 0, DQS1 = 0
5390 00:24:41.056072 DQM Delay:
5391 00:24:41.056154 DQM0 = 91, DQM1 = 83
5392 00:24:41.059099 DQ Delay:
5393 00:24:41.059179 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5394 00:24:41.062673 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5395 00:24:41.066052 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5396 00:24:41.069531 DQ12 =91, DQ13 =87, DQ14 =91, DQ15 =91
5397 00:24:41.072404
5398 00:24:41.072502
5399 00:24:41.072580 ==
5400 00:24:41.075861 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 00:24:41.079215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 00:24:41.079312 ==
5403 00:24:41.079383
5404 00:24:41.079456
5405 00:24:41.082578 TX Vref Scan disable
5406 00:24:41.082674 == TX Byte 0 ==
5407 00:24:41.089754 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5408 00:24:41.092534 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5409 00:24:41.092614 == TX Byte 1 ==
5410 00:24:41.099594 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5411 00:24:41.102342 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5412 00:24:41.102422 ==
5413 00:24:41.105871 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 00:24:41.109017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 00:24:41.109097 ==
5416 00:24:41.109162
5417 00:24:41.109236
5418 00:24:41.112495 TX Vref Scan disable
5419 00:24:41.116218 == TX Byte 0 ==
5420 00:24:41.119345 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5421 00:24:41.122867 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5422 00:24:41.125782 == TX Byte 1 ==
5423 00:24:41.129298 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5424 00:24:41.133017 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5425 00:24:41.133097
5426 00:24:41.135893 [DATLAT]
5427 00:24:41.135972 Freq=933, CH0 RK1
5428 00:24:41.136036
5429 00:24:41.139489 DATLAT Default: 0xb
5430 00:24:41.139568 0, 0xFFFF, sum = 0
5431 00:24:41.142715 1, 0xFFFF, sum = 0
5432 00:24:41.142842 2, 0xFFFF, sum = 0
5433 00:24:41.146197 3, 0xFFFF, sum = 0
5434 00:24:41.146277 4, 0xFFFF, sum = 0
5435 00:24:41.148868 5, 0xFFFF, sum = 0
5436 00:24:41.148981 6, 0xFFFF, sum = 0
5437 00:24:41.152200 7, 0xFFFF, sum = 0
5438 00:24:41.152281 8, 0xFFFF, sum = 0
5439 00:24:41.155690 9, 0xFFFF, sum = 0
5440 00:24:41.155770 10, 0x0, sum = 1
5441 00:24:41.158695 11, 0x0, sum = 2
5442 00:24:41.158774 12, 0x0, sum = 3
5443 00:24:41.162165 13, 0x0, sum = 4
5444 00:24:41.162245 best_step = 11
5445 00:24:41.162309
5446 00:24:41.162367 ==
5447 00:24:41.165525 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 00:24:41.171820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 00:24:41.171900 ==
5450 00:24:41.171963 RX Vref Scan: 0
5451 00:24:41.172022
5452 00:24:41.175616 RX Vref 0 -> 0, step: 1
5453 00:24:41.175712
5454 00:24:41.178583 RX Delay -69 -> 252, step: 4
5455 00:24:41.181785 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5456 00:24:41.188444 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5457 00:24:41.191834 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5458 00:24:41.195278 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5459 00:24:41.198701 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5460 00:24:41.201914 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5461 00:24:41.205031 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5462 00:24:41.211726 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5463 00:24:41.215238 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5464 00:24:41.218347 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5465 00:24:41.221567 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5466 00:24:41.225002 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5467 00:24:41.231695 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5468 00:24:41.235250 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5469 00:24:41.238243 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5470 00:24:41.241532 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5471 00:24:41.241613 ==
5472 00:24:41.244870 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 00:24:41.251573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 00:24:41.251653 ==
5475 00:24:41.251717 DQS Delay:
5476 00:24:41.251776 DQS0 = 0, DQS1 = 0
5477 00:24:41.254751 DQM Delay:
5478 00:24:41.254830 DQM0 = 93, DQM1 = 84
5479 00:24:41.258391 DQ Delay:
5480 00:24:41.261654 DQ0 =92, DQ1 =94, DQ2 =90, DQ3 =88
5481 00:24:41.264666 DQ4 =92, DQ5 =80, DQ6 =106, DQ7 =104
5482 00:24:41.268049 DQ8 =78, DQ9 =68, DQ10 =84, DQ11 =78
5483 00:24:41.271551 DQ12 =92, DQ13 =92, DQ14 =94, DQ15 =92
5484 00:24:41.271657
5485 00:24:41.271740
5486 00:24:41.278411 [DQSOSCAuto] RK1, (LSB)MR18= 0x3213, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5487 00:24:41.281201 CH0 RK1: MR19=505, MR18=3213
5488 00:24:41.288419 CH0_RK1: MR19=0x505, MR18=0x3213, DQSOSC=406, MR23=63, INC=65, DEC=43
5489 00:24:41.291132 [RxdqsGatingPostProcess] freq 933
5490 00:24:41.294568 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5491 00:24:41.298176 best DQS0 dly(2T, 0.5T) = (0, 10)
5492 00:24:41.300915 best DQS1 dly(2T, 0.5T) = (0, 11)
5493 00:24:41.304424 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5494 00:24:41.307688 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5495 00:24:41.311494 best DQS0 dly(2T, 0.5T) = (0, 10)
5496 00:24:41.314146 best DQS1 dly(2T, 0.5T) = (0, 10)
5497 00:24:41.317577 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5498 00:24:41.321205 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5499 00:24:41.324157 Pre-setting of DQS Precalculation
5500 00:24:41.327645 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5501 00:24:41.327725 ==
5502 00:24:41.331191 Dram Type= 6, Freq= 0, CH_1, rank 0
5503 00:24:41.338142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 00:24:41.338223 ==
5505 00:24:41.340786 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5506 00:24:41.347363 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5507 00:24:41.351017 [CA 0] Center 37 (7~67) winsize 61
5508 00:24:41.354082 [CA 1] Center 37 (7~67) winsize 61
5509 00:24:41.357195 [CA 2] Center 34 (5~64) winsize 60
5510 00:24:41.360651 [CA 3] Center 34 (4~64) winsize 61
5511 00:24:41.363921 [CA 4] Center 34 (5~64) winsize 60
5512 00:24:41.367223 [CA 5] Center 33 (4~63) winsize 60
5513 00:24:41.367347
5514 00:24:41.370884 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5515 00:24:41.370993
5516 00:24:41.373857 [CATrainingPosCal] consider 1 rank data
5517 00:24:41.377014 u2DelayCellTimex100 = 270/100 ps
5518 00:24:41.381057 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5519 00:24:41.387198 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5520 00:24:41.390366 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5521 00:24:41.394324 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5522 00:24:41.397194 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5523 00:24:41.400616 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5524 00:24:41.400695
5525 00:24:41.403608 CA PerBit enable=1, Macro0, CA PI delay=33
5526 00:24:41.403688
5527 00:24:41.407160 [CBTSetCACLKResult] CA Dly = 33
5528 00:24:41.407239 CS Dly: 5 (0~36)
5529 00:24:41.410495 ==
5530 00:24:41.413811 Dram Type= 6, Freq= 0, CH_1, rank 1
5531 00:24:41.417093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 00:24:41.417173 ==
5533 00:24:41.423377 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5534 00:24:41.426880 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5535 00:24:41.430863 [CA 0] Center 37 (7~68) winsize 62
5536 00:24:41.434063 [CA 1] Center 37 (7~68) winsize 62
5537 00:24:41.437240 [CA 2] Center 34 (5~64) winsize 60
5538 00:24:41.441057 [CA 3] Center 34 (4~64) winsize 61
5539 00:24:41.443850 [CA 4] Center 34 (4~64) winsize 61
5540 00:24:41.447597 [CA 5] Center 33 (3~64) winsize 62
5541 00:24:41.447668
5542 00:24:41.450491 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5543 00:24:41.450595
5544 00:24:41.453902 [CATrainingPosCal] consider 2 rank data
5545 00:24:41.457327 u2DelayCellTimex100 = 270/100 ps
5546 00:24:41.460873 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5547 00:24:41.467245 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5548 00:24:41.470744 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5549 00:24:41.473934 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5550 00:24:41.477649 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5551 00:24:41.480672 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5552 00:24:41.480744
5553 00:24:41.483963 CA PerBit enable=1, Macro0, CA PI delay=33
5554 00:24:41.484033
5555 00:24:41.487225 [CBTSetCACLKResult] CA Dly = 33
5556 00:24:41.487311 CS Dly: 6 (0~39)
5557 00:24:41.490400
5558 00:24:41.493663 ----->DramcWriteLeveling(PI) begin...
5559 00:24:41.493745 ==
5560 00:24:41.497132 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 00:24:41.500103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 00:24:41.500177 ==
5563 00:24:41.503575 Write leveling (Byte 0): 25 => 25
5564 00:24:41.506903 Write leveling (Byte 1): 26 => 26
5565 00:24:41.510528 DramcWriteLeveling(PI) end<-----
5566 00:24:41.510608
5567 00:24:41.510670 ==
5568 00:24:41.513457 Dram Type= 6, Freq= 0, CH_1, rank 0
5569 00:24:41.516795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5570 00:24:41.516876 ==
5571 00:24:41.520176 [Gating] SW mode calibration
5572 00:24:41.526717 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5573 00:24:41.534025 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5574 00:24:41.537105 0 14 0 | B1->B0 | 3232 2d2d | 1 0 | (0 0) (0 0)
5575 00:24:41.540120 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 00:24:41.546879 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 00:24:41.550508 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 00:24:41.553636 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 00:24:41.559896 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 00:24:41.563543 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5581 00:24:41.566672 0 14 28 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
5582 00:24:41.573430 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5583 00:24:41.576648 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 00:24:41.580345 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 00:24:41.587030 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 00:24:41.589815 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 00:24:41.593003 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 00:24:41.596562 0 15 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5589 00:24:41.603088 0 15 28 | B1->B0 | 3737 3131 | 1 0 | (0 0) (0 0)
5590 00:24:41.606492 1 0 0 | B1->B0 | 4545 3f3f | 0 1 | (0 0) (0 0)
5591 00:24:41.610025 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 00:24:41.616688 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 00:24:41.619878 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 00:24:41.622970 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 00:24:41.629634 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 00:24:41.632846 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 00:24:41.636327 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5598 00:24:41.642660 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5599 00:24:41.646068 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 00:24:41.649250 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 00:24:41.656416 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 00:24:41.659567 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 00:24:41.663238 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 00:24:41.669085 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 00:24:41.672691 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 00:24:41.675943 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 00:24:41.682520 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 00:24:41.685662 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 00:24:41.688879 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 00:24:41.695658 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 00:24:41.698849 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 00:24:41.702501 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 00:24:41.709257 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5614 00:24:41.712517 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5615 00:24:41.715969 Total UI for P1: 0, mck2ui 16
5616 00:24:41.718920 best dqsien dly found for B0: ( 1, 2, 28)
5617 00:24:41.722386 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 00:24:41.725494 Total UI for P1: 0, mck2ui 16
5619 00:24:41.729153 best dqsien dly found for B1: ( 1, 2, 30)
5620 00:24:41.732181 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5621 00:24:41.735719 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5622 00:24:41.735798
5623 00:24:41.742745 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5624 00:24:41.745517 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5625 00:24:41.745597 [Gating] SW calibration Done
5626 00:24:41.749044 ==
5627 00:24:41.752053 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 00:24:41.755534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 00:24:41.755614 ==
5630 00:24:41.755677 RX Vref Scan: 0
5631 00:24:41.755736
5632 00:24:41.759226 RX Vref 0 -> 0, step: 1
5633 00:24:41.759305
5634 00:24:41.762155 RX Delay -80 -> 252, step: 8
5635 00:24:41.765518 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5636 00:24:41.768899 iDelay=208, Bit 1, Center 87 (-16 ~ 191) 208
5637 00:24:41.772523 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5638 00:24:41.778668 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5639 00:24:41.782007 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5640 00:24:41.785395 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5641 00:24:41.788903 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5642 00:24:41.792032 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5643 00:24:41.795267 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5644 00:24:41.802261 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5645 00:24:41.805863 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5646 00:24:41.809265 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5647 00:24:41.812533 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5648 00:24:41.815362 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5649 00:24:41.818704 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5650 00:24:41.825529 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5651 00:24:41.825704 ==
5652 00:24:41.828710 Dram Type= 6, Freq= 0, CH_1, rank 0
5653 00:24:41.832134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5654 00:24:41.832211 ==
5655 00:24:41.832276 DQS Delay:
5656 00:24:41.835914 DQS0 = 0, DQS1 = 0
5657 00:24:41.835987 DQM Delay:
5658 00:24:41.838517 DQM0 = 95, DQM1 = 89
5659 00:24:41.838588 DQ Delay:
5660 00:24:41.842354 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =91
5661 00:24:41.845516 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5662 00:24:41.848560 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5663 00:24:41.852127 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5664 00:24:41.852205
5665 00:24:41.852270
5666 00:24:41.852328 ==
5667 00:24:41.855100 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 00:24:41.858613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 00:24:41.861814 ==
5670 00:24:41.861930
5671 00:24:41.861992
5672 00:24:41.862049 TX Vref Scan disable
5673 00:24:41.865172 == TX Byte 0 ==
5674 00:24:41.868680 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5675 00:24:41.871864 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5676 00:24:41.875363 == TX Byte 1 ==
5677 00:24:41.878628 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5678 00:24:41.882427 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5679 00:24:41.882528 ==
5680 00:24:41.885335 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 00:24:41.892185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 00:24:41.892259 ==
5683 00:24:41.892325
5684 00:24:41.892382
5685 00:24:41.892438 TX Vref Scan disable
5686 00:24:41.896305 == TX Byte 0 ==
5687 00:24:41.900081 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5688 00:24:41.906086 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5689 00:24:41.906163 == TX Byte 1 ==
5690 00:24:41.909601 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5691 00:24:41.916155 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5692 00:24:41.916234
5693 00:24:41.916298 [DATLAT]
5694 00:24:41.916357 Freq=933, CH1 RK0
5695 00:24:41.916414
5696 00:24:41.919519 DATLAT Default: 0xd
5697 00:24:41.919598 0, 0xFFFF, sum = 0
5698 00:24:41.922830 1, 0xFFFF, sum = 0
5699 00:24:41.922910 2, 0xFFFF, sum = 0
5700 00:24:41.926047 3, 0xFFFF, sum = 0
5701 00:24:41.929651 4, 0xFFFF, sum = 0
5702 00:24:41.929732 5, 0xFFFF, sum = 0
5703 00:24:41.932661 6, 0xFFFF, sum = 0
5704 00:24:41.932741 7, 0xFFFF, sum = 0
5705 00:24:41.936081 8, 0xFFFF, sum = 0
5706 00:24:41.936162 9, 0xFFFF, sum = 0
5707 00:24:41.939503 10, 0x0, sum = 1
5708 00:24:41.939584 11, 0x0, sum = 2
5709 00:24:41.943027 12, 0x0, sum = 3
5710 00:24:41.943108 13, 0x0, sum = 4
5711 00:24:41.943172 best_step = 11
5712 00:24:41.943231
5713 00:24:41.945930 ==
5714 00:24:41.949310 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 00:24:41.952280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 00:24:41.952360 ==
5717 00:24:41.952423 RX Vref Scan: 1
5718 00:24:41.952483
5719 00:24:41.955720 RX Vref 0 -> 0, step: 1
5720 00:24:41.955798
5721 00:24:41.959011 RX Delay -61 -> 252, step: 4
5722 00:24:41.959090
5723 00:24:41.962519 Set Vref, RX VrefLevel [Byte0]: 55
5724 00:24:41.965719 [Byte1]: 50
5725 00:24:41.965799
5726 00:24:41.969355 Final RX Vref Byte 0 = 55 to rank0
5727 00:24:41.972466 Final RX Vref Byte 1 = 50 to rank0
5728 00:24:41.976008 Final RX Vref Byte 0 = 55 to rank1
5729 00:24:41.979147 Final RX Vref Byte 1 = 50 to rank1==
5730 00:24:41.982852 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 00:24:41.985805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 00:24:41.988935 ==
5733 00:24:41.989014 DQS Delay:
5734 00:24:41.989078 DQS0 = 0, DQS1 = 0
5735 00:24:41.992355 DQM Delay:
5736 00:24:41.992434 DQM0 = 95, DQM1 = 87
5737 00:24:41.995470 DQ Delay:
5738 00:24:41.995550 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =92
5739 00:24:41.999307 DQ4 =94, DQ5 =104, DQ6 =106, DQ7 =94
5740 00:24:42.002147 DQ8 =74, DQ9 =80, DQ10 =88, DQ11 =80
5741 00:24:42.008980 DQ12 =96, DQ13 =94, DQ14 =94, DQ15 =94
5742 00:24:42.009077
5743 00:24:42.009173
5744 00:24:42.015752 [DQSOSCAuto] RK0, (LSB)MR18= 0x50e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 420 ps
5745 00:24:42.018812 CH1 RK0: MR19=505, MR18=50E
5746 00:24:42.025709 CH1_RK0: MR19=0x505, MR18=0x50E, DQSOSC=417, MR23=63, INC=62, DEC=41
5747 00:24:42.025789
5748 00:24:42.028701 ----->DramcWriteLeveling(PI) begin...
5749 00:24:42.028782 ==
5750 00:24:42.032090 Dram Type= 6, Freq= 0, CH_1, rank 1
5751 00:24:42.035813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 00:24:42.035894 ==
5753 00:24:42.039101 Write leveling (Byte 0): 27 => 27
5754 00:24:42.042006 Write leveling (Byte 1): 27 => 27
5755 00:24:42.045260 DramcWriteLeveling(PI) end<-----
5756 00:24:42.045339
5757 00:24:42.045440 ==
5758 00:24:42.048414 Dram Type= 6, Freq= 0, CH_1, rank 1
5759 00:24:42.051801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 00:24:42.051880 ==
5761 00:24:42.055789 [Gating] SW mode calibration
5762 00:24:42.061960 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5763 00:24:42.068893 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5764 00:24:42.071881 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (1 1) (1 1)
5765 00:24:42.075231 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 00:24:42.082035 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 00:24:42.085646 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 00:24:42.088559 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 00:24:42.094999 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5770 00:24:42.098228 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (1 1) (1 0)
5771 00:24:42.102097 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
5772 00:24:42.108392 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 00:24:42.111536 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 00:24:42.114814 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 00:24:42.121910 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 00:24:42.124955 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 00:24:42.128645 0 15 20 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
5778 00:24:42.135278 0 15 24 | B1->B0 | 2727 3534 | 1 1 | (0 0) (0 0)
5779 00:24:42.138439 0 15 28 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
5780 00:24:42.141455 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 00:24:42.147975 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 00:24:42.151313 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 00:24:42.154933 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 00:24:42.161404 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 00:24:42.164479 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 00:24:42.168008 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5787 00:24:42.174743 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5788 00:24:42.177953 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 00:24:42.181245 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 00:24:42.187822 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 00:24:42.191222 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 00:24:42.194658 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 00:24:42.201371 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 00:24:42.204275 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 00:24:42.207750 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 00:24:42.211296 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 00:24:42.218106 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 00:24:42.221468 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 00:24:42.224464 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 00:24:42.231246 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 00:24:42.234570 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 00:24:42.237473 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5803 00:24:42.244249 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 00:24:42.247696 Total UI for P1: 0, mck2ui 16
5805 00:24:42.251063 best dqsien dly found for B0: ( 1, 2, 24)
5806 00:24:42.253945 Total UI for P1: 0, mck2ui 16
5807 00:24:42.257433 best dqsien dly found for B1: ( 1, 2, 26)
5808 00:24:42.260731 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5809 00:24:42.264140 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5810 00:24:42.264220
5811 00:24:42.267716 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5812 00:24:42.270728 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5813 00:24:42.274285 [Gating] SW calibration Done
5814 00:24:42.274358 ==
5815 00:24:42.277761 Dram Type= 6, Freq= 0, CH_1, rank 1
5816 00:24:42.280490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5817 00:24:42.280567 ==
5818 00:24:42.285127 RX Vref Scan: 0
5819 00:24:42.285200
5820 00:24:42.285265 RX Vref 0 -> 0, step: 1
5821 00:24:42.287293
5822 00:24:42.287426 RX Delay -80 -> 252, step: 8
5823 00:24:42.293959 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5824 00:24:42.297348 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5825 00:24:42.300582 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5826 00:24:42.303616 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5827 00:24:42.307443 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5828 00:24:42.310387 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5829 00:24:42.317306 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5830 00:24:42.320344 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5831 00:24:42.323569 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5832 00:24:42.327144 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5833 00:24:42.330253 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5834 00:24:42.336868 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5835 00:24:42.340248 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5836 00:24:42.343749 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5837 00:24:42.347021 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5838 00:24:42.350035 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5839 00:24:42.350115 ==
5840 00:24:42.353408 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 00:24:42.359870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 00:24:42.359950 ==
5843 00:24:42.360013 DQS Delay:
5844 00:24:42.363170 DQS0 = 0, DQS1 = 0
5845 00:24:42.363267 DQM Delay:
5846 00:24:42.363331 DQM0 = 94, DQM1 = 88
5847 00:24:42.366506 DQ Delay:
5848 00:24:42.370035 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5849 00:24:42.373263 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5850 00:24:42.377043 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =87
5851 00:24:42.379764 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5852 00:24:42.379860
5853 00:24:42.379936
5854 00:24:42.379994 ==
5855 00:24:42.383707 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 00:24:42.386493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 00:24:42.386573 ==
5858 00:24:42.386674
5859 00:24:42.386731
5860 00:24:42.390301 TX Vref Scan disable
5861 00:24:42.390397 == TX Byte 0 ==
5862 00:24:42.397345 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5863 00:24:42.400233 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5864 00:24:42.400312 == TX Byte 1 ==
5865 00:24:42.406335 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5866 00:24:42.409708 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5867 00:24:42.409788 ==
5868 00:24:42.413094 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 00:24:42.416636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 00:24:42.416734 ==
5871 00:24:42.419837
5872 00:24:42.419916
5873 00:24:42.420012 TX Vref Scan disable
5874 00:24:42.423191 == TX Byte 0 ==
5875 00:24:42.426403 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5876 00:24:42.432836 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5877 00:24:42.432916 == TX Byte 1 ==
5878 00:24:42.436385 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5879 00:24:42.442805 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5880 00:24:42.442913
5881 00:24:42.442981 [DATLAT]
5882 00:24:42.443040 Freq=933, CH1 RK1
5883 00:24:42.443114
5884 00:24:42.446017 DATLAT Default: 0xb
5885 00:24:42.446096 0, 0xFFFF, sum = 0
5886 00:24:42.449286 1, 0xFFFF, sum = 0
5887 00:24:42.452687 2, 0xFFFF, sum = 0
5888 00:24:42.452767 3, 0xFFFF, sum = 0
5889 00:24:42.456099 4, 0xFFFF, sum = 0
5890 00:24:42.456179 5, 0xFFFF, sum = 0
5891 00:24:42.459437 6, 0xFFFF, sum = 0
5892 00:24:42.459517 7, 0xFFFF, sum = 0
5893 00:24:42.463038 8, 0xFFFF, sum = 0
5894 00:24:42.463118 9, 0xFFFF, sum = 0
5895 00:24:42.465893 10, 0x0, sum = 1
5896 00:24:42.465990 11, 0x0, sum = 2
5897 00:24:42.469815 12, 0x0, sum = 3
5898 00:24:42.469896 13, 0x0, sum = 4
5899 00:24:42.469960 best_step = 11
5900 00:24:42.470018
5901 00:24:42.472943 ==
5902 00:24:42.476098 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 00:24:42.479549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 00:24:42.479628 ==
5905 00:24:42.479692 RX Vref Scan: 0
5906 00:24:42.479750
5907 00:24:42.482645 RX Vref 0 -> 0, step: 1
5908 00:24:42.482741
5909 00:24:42.486106 RX Delay -69 -> 252, step: 4
5910 00:24:42.489440 iDelay=203, Bit 0, Center 98 (3 ~ 194) 192
5911 00:24:42.495984 iDelay=203, Bit 1, Center 88 (-5 ~ 182) 188
5912 00:24:42.499196 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5913 00:24:42.502640 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5914 00:24:42.506358 iDelay=203, Bit 4, Center 92 (-5 ~ 190) 196
5915 00:24:42.509414 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5916 00:24:42.516015 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5917 00:24:42.519267 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5918 00:24:42.522499 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5919 00:24:42.525809 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5920 00:24:42.529233 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5921 00:24:42.532594 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5922 00:24:42.538919 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5923 00:24:42.542405 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5924 00:24:42.545837 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5925 00:24:42.549395 iDelay=203, Bit 15, Center 94 (-1 ~ 190) 192
5926 00:24:42.549505 ==
5927 00:24:42.552426 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 00:24:42.559157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 00:24:42.559237 ==
5930 00:24:42.559300 DQS Delay:
5931 00:24:42.559359 DQS0 = 0, DQS1 = 0
5932 00:24:42.562110 DQM Delay:
5933 00:24:42.562206 DQM0 = 93, DQM1 = 90
5934 00:24:42.565850 DQ Delay:
5935 00:24:42.569287 DQ0 =98, DQ1 =88, DQ2 =82, DQ3 =90
5936 00:24:42.572332 DQ4 =92, DQ5 =102, DQ6 =104, DQ7 =90
5937 00:24:42.575561 DQ8 =78, DQ9 =82, DQ10 =92, DQ11 =84
5938 00:24:42.578937 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =94
5939 00:24:42.579016
5940 00:24:42.579078
5941 00:24:42.585525 [DQSOSCAuto] RK1, (LSB)MR18= 0x1024, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
5942 00:24:42.588437 CH1 RK1: MR19=505, MR18=1024
5943 00:24:42.595523 CH1_RK1: MR19=0x505, MR18=0x1024, DQSOSC=410, MR23=63, INC=64, DEC=42
5944 00:24:42.598377 [RxdqsGatingPostProcess] freq 933
5945 00:24:42.601809 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5946 00:24:42.605234 best DQS0 dly(2T, 0.5T) = (0, 10)
5947 00:24:42.608735 best DQS1 dly(2T, 0.5T) = (0, 10)
5948 00:24:42.611881 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5949 00:24:42.615376 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5950 00:24:42.618687 best DQS0 dly(2T, 0.5T) = (0, 10)
5951 00:24:42.621626 best DQS1 dly(2T, 0.5T) = (0, 10)
5952 00:24:42.625023 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5953 00:24:42.628491 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5954 00:24:42.631570 Pre-setting of DQS Precalculation
5955 00:24:42.634628 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5956 00:24:42.644746 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5957 00:24:42.651909 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5958 00:24:42.651990
5959 00:24:42.652053
5960 00:24:42.654658 [Calibration Summary] 1866 Mbps
5961 00:24:42.654738 CH 0, Rank 0
5962 00:24:42.658016 SW Impedance : PASS
5963 00:24:42.658096 DUTY Scan : NO K
5964 00:24:42.661611 ZQ Calibration : PASS
5965 00:24:42.664840 Jitter Meter : NO K
5966 00:24:42.664919 CBT Training : PASS
5967 00:24:42.668348 Write leveling : PASS
5968 00:24:42.671103 RX DQS gating : PASS
5969 00:24:42.671183 RX DQ/DQS(RDDQC) : PASS
5970 00:24:42.674541 TX DQ/DQS : PASS
5971 00:24:42.677953 RX DATLAT : PASS
5972 00:24:42.678033 RX DQ/DQS(Engine): PASS
5973 00:24:42.680860 TX OE : NO K
5974 00:24:42.680940 All Pass.
5975 00:24:42.681003
5976 00:24:42.684399 CH 0, Rank 1
5977 00:24:42.684478 SW Impedance : PASS
5978 00:24:42.687770 DUTY Scan : NO K
5979 00:24:42.691494 ZQ Calibration : PASS
5980 00:24:42.691589 Jitter Meter : NO K
5981 00:24:42.694528 CBT Training : PASS
5982 00:24:42.697686 Write leveling : PASS
5983 00:24:42.697766 RX DQS gating : PASS
5984 00:24:42.700947 RX DQ/DQS(RDDQC) : PASS
5985 00:24:42.701026 TX DQ/DQS : PASS
5986 00:24:42.704421 RX DATLAT : PASS
5987 00:24:42.707486 RX DQ/DQS(Engine): PASS
5988 00:24:42.707566 TX OE : NO K
5989 00:24:42.710866 All Pass.
5990 00:24:42.710945
5991 00:24:42.711008 CH 1, Rank 0
5992 00:24:42.714320 SW Impedance : PASS
5993 00:24:42.714429 DUTY Scan : NO K
5994 00:24:42.717829 ZQ Calibration : PASS
5995 00:24:42.721305 Jitter Meter : NO K
5996 00:24:42.721384 CBT Training : PASS
5997 00:24:42.724077 Write leveling : PASS
5998 00:24:42.727572 RX DQS gating : PASS
5999 00:24:42.727651 RX DQ/DQS(RDDQC) : PASS
6000 00:24:42.730865 TX DQ/DQS : PASS
6001 00:24:42.734327 RX DATLAT : PASS
6002 00:24:42.734407 RX DQ/DQS(Engine): PASS
6003 00:24:42.737473 TX OE : NO K
6004 00:24:42.737554 All Pass.
6005 00:24:42.737617
6006 00:24:42.740817 CH 1, Rank 1
6007 00:24:42.740896 SW Impedance : PASS
6008 00:24:42.744135 DUTY Scan : NO K
6009 00:24:42.747769 ZQ Calibration : PASS
6010 00:24:42.747848 Jitter Meter : NO K
6011 00:24:42.750339 CBT Training : PASS
6012 00:24:42.753646 Write leveling : PASS
6013 00:24:42.753726 RX DQS gating : PASS
6014 00:24:42.756886 RX DQ/DQS(RDDQC) : PASS
6015 00:24:42.760579 TX DQ/DQS : PASS
6016 00:24:42.760659 RX DATLAT : PASS
6017 00:24:42.763954 RX DQ/DQS(Engine): PASS
6018 00:24:42.764031 TX OE : NO K
6019 00:24:42.766998 All Pass.
6020 00:24:42.767073
6021 00:24:42.767138 DramC Write-DBI off
6022 00:24:42.770259 PER_BANK_REFRESH: Hybrid Mode
6023 00:24:42.774139 TX_TRACKING: ON
6024 00:24:42.780187 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6025 00:24:42.783339 [FAST_K] Save calibration result to emmc
6026 00:24:42.790347 dramc_set_vcore_voltage set vcore to 650000
6027 00:24:42.790433 Read voltage for 400, 6
6028 00:24:42.793486 Vio18 = 0
6029 00:24:42.793563 Vcore = 650000
6030 00:24:42.793624 Vdram = 0
6031 00:24:42.793682 Vddq = 0
6032 00:24:42.796593 Vmddr = 0
6033 00:24:42.800288 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6034 00:24:42.806592 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6035 00:24:42.809751 MEM_TYPE=3, freq_sel=20
6036 00:24:42.813228 sv_algorithm_assistance_LP4_800
6037 00:24:42.816346 ============ PULL DRAM RESETB DOWN ============
6038 00:24:42.820012 ========== PULL DRAM RESETB DOWN end =========
6039 00:24:42.822956 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6040 00:24:42.826310 ===================================
6041 00:24:42.829852 LPDDR4 DRAM CONFIGURATION
6042 00:24:42.832758 ===================================
6043 00:24:42.836360 EX_ROW_EN[0] = 0x0
6044 00:24:42.836482 EX_ROW_EN[1] = 0x0
6045 00:24:42.839693 LP4Y_EN = 0x0
6046 00:24:42.839772 WORK_FSP = 0x0
6047 00:24:42.843124 WL = 0x2
6048 00:24:42.843203 RL = 0x2
6049 00:24:42.846124 BL = 0x2
6050 00:24:42.846203 RPST = 0x0
6051 00:24:42.849571 RD_PRE = 0x0
6052 00:24:42.853100 WR_PRE = 0x1
6053 00:24:42.853204 WR_PST = 0x0
6054 00:24:42.856045 DBI_WR = 0x0
6055 00:24:42.856124 DBI_RD = 0x0
6056 00:24:42.859315 OTF = 0x1
6057 00:24:42.862742 ===================================
6058 00:24:42.865835 ===================================
6059 00:24:42.865915 ANA top config
6060 00:24:42.868984 ===================================
6061 00:24:42.872547 DLL_ASYNC_EN = 0
6062 00:24:42.875867 ALL_SLAVE_EN = 1
6063 00:24:42.875947 NEW_RANK_MODE = 1
6064 00:24:42.879111 DLL_IDLE_MODE = 1
6065 00:24:42.882504 LP45_APHY_COMB_EN = 1
6066 00:24:42.885810 TX_ODT_DIS = 1
6067 00:24:42.885889 NEW_8X_MODE = 1
6068 00:24:42.889302 ===================================
6069 00:24:42.892200 ===================================
6070 00:24:42.895663 data_rate = 800
6071 00:24:42.899149 CKR = 1
6072 00:24:42.902573 DQ_P2S_RATIO = 4
6073 00:24:42.905759 ===================================
6074 00:24:42.908957 CA_P2S_RATIO = 4
6075 00:24:42.912074 DQ_CA_OPEN = 0
6076 00:24:42.915492 DQ_SEMI_OPEN = 1
6077 00:24:42.915572 CA_SEMI_OPEN = 1
6078 00:24:42.919059 CA_FULL_RATE = 0
6079 00:24:42.922018 DQ_CKDIV4_EN = 0
6080 00:24:42.925768 CA_CKDIV4_EN = 1
6081 00:24:42.928624 CA_PREDIV_EN = 0
6082 00:24:42.932223 PH8_DLY = 0
6083 00:24:42.932304 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6084 00:24:42.935757 DQ_AAMCK_DIV = 0
6085 00:24:42.938882 CA_AAMCK_DIV = 0
6086 00:24:42.942028 CA_ADMCK_DIV = 4
6087 00:24:42.945477 DQ_TRACK_CA_EN = 0
6088 00:24:42.948503 CA_PICK = 800
6089 00:24:42.948582 CA_MCKIO = 400
6090 00:24:42.952004 MCKIO_SEMI = 400
6091 00:24:42.955287 PLL_FREQ = 3016
6092 00:24:42.958321 DQ_UI_PI_RATIO = 32
6093 00:24:42.962124 CA_UI_PI_RATIO = 32
6094 00:24:42.964943 ===================================
6095 00:24:42.968225 ===================================
6096 00:24:42.971663 memory_type:LPDDR4
6097 00:24:42.971742 GP_NUM : 10
6098 00:24:42.975190 SRAM_EN : 1
6099 00:24:42.978703 MD32_EN : 0
6100 00:24:42.981575 ===================================
6101 00:24:42.981659 [ANA_INIT] >>>>>>>>>>>>>>
6102 00:24:42.985044 <<<<<< [CONFIGURE PHASE]: ANA_TX
6103 00:24:42.988632 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6104 00:24:42.992162 ===================================
6105 00:24:42.995334 data_rate = 800,PCW = 0X7400
6106 00:24:42.998428 ===================================
6107 00:24:43.001571 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6108 00:24:43.008538 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6109 00:24:43.018156 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6110 00:24:43.021698 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6111 00:24:43.025073 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6112 00:24:43.031570 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6113 00:24:43.031651 [ANA_INIT] flow start
6114 00:24:43.035214 [ANA_INIT] PLL >>>>>>>>
6115 00:24:43.038347 [ANA_INIT] PLL <<<<<<<<
6116 00:24:43.038470 [ANA_INIT] MIDPI >>>>>>>>
6117 00:24:43.041319 [ANA_INIT] MIDPI <<<<<<<<
6118 00:24:43.044973 [ANA_INIT] DLL >>>>>>>>
6119 00:24:43.045051 [ANA_INIT] flow end
6120 00:24:43.048116 ============ LP4 DIFF to SE enter ============
6121 00:24:43.054712 ============ LP4 DIFF to SE exit ============
6122 00:24:43.054798 [ANA_INIT] <<<<<<<<<<<<<
6123 00:24:43.057838 [Flow] Enable top DCM control >>>>>
6124 00:24:43.061163 [Flow] Enable top DCM control <<<<<
6125 00:24:43.064570 Enable DLL master slave shuffle
6126 00:24:43.071273 ==============================================================
6127 00:24:43.074567 Gating Mode config
6128 00:24:43.078124 ==============================================================
6129 00:24:43.081035 Config description:
6130 00:24:43.091443 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6131 00:24:43.097822 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6132 00:24:43.101019 SELPH_MODE 0: By rank 1: By Phase
6133 00:24:43.107962 ==============================================================
6134 00:24:43.110968 GAT_TRACK_EN = 0
6135 00:24:43.114623 RX_GATING_MODE = 2
6136 00:24:43.114704 RX_GATING_TRACK_MODE = 2
6137 00:24:43.117694 SELPH_MODE = 1
6138 00:24:43.120952 PICG_EARLY_EN = 1
6139 00:24:43.124580 VALID_LAT_VALUE = 1
6140 00:24:43.130771 ==============================================================
6141 00:24:43.134246 Enter into Gating configuration >>>>
6142 00:24:43.138396 Exit from Gating configuration <<<<
6143 00:24:43.141357 Enter into DVFS_PRE_config >>>>>
6144 00:24:43.151217 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6145 00:24:43.154183 Exit from DVFS_PRE_config <<<<<
6146 00:24:43.157900 Enter into PICG configuration >>>>
6147 00:24:43.161082 Exit from PICG configuration <<<<
6148 00:24:43.164245 [RX_INPUT] configuration >>>>>
6149 00:24:43.167688 [RX_INPUT] configuration <<<<<
6150 00:24:43.170922 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6151 00:24:43.177577 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6152 00:24:43.184252 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6153 00:24:43.190956 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6154 00:24:43.194251 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6155 00:24:43.200835 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6156 00:24:43.204098 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6157 00:24:43.210440 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6158 00:24:43.213860 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6159 00:24:43.217368 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6160 00:24:43.220717 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6161 00:24:43.227250 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6162 00:24:43.230753 ===================================
6163 00:24:43.230834 LPDDR4 DRAM CONFIGURATION
6164 00:24:43.233825 ===================================
6165 00:24:43.237248 EX_ROW_EN[0] = 0x0
6166 00:24:43.240394 EX_ROW_EN[1] = 0x0
6167 00:24:43.240474 LP4Y_EN = 0x0
6168 00:24:43.243869 WORK_FSP = 0x0
6169 00:24:43.243948 WL = 0x2
6170 00:24:43.247267 RL = 0x2
6171 00:24:43.247381 BL = 0x2
6172 00:24:43.250755 RPST = 0x0
6173 00:24:43.250834 RD_PRE = 0x0
6174 00:24:43.253755 WR_PRE = 0x1
6175 00:24:43.253835 WR_PST = 0x0
6176 00:24:43.257196 DBI_WR = 0x0
6177 00:24:43.257275 DBI_RD = 0x0
6178 00:24:43.260126 OTF = 0x1
6179 00:24:43.263852 ===================================
6180 00:24:43.266858 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6181 00:24:43.270236 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6182 00:24:43.277115 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6183 00:24:43.280262 ===================================
6184 00:24:43.280342 LPDDR4 DRAM CONFIGURATION
6185 00:24:43.283272 ===================================
6186 00:24:43.286608 EX_ROW_EN[0] = 0x10
6187 00:24:43.290018 EX_ROW_EN[1] = 0x0
6188 00:24:43.290097 LP4Y_EN = 0x0
6189 00:24:43.293575 WORK_FSP = 0x0
6190 00:24:43.293681 WL = 0x2
6191 00:24:43.297160 RL = 0x2
6192 00:24:43.297239 BL = 0x2
6193 00:24:43.300383 RPST = 0x0
6194 00:24:43.300463 RD_PRE = 0x0
6195 00:24:43.303267 WR_PRE = 0x1
6196 00:24:43.303393 WR_PST = 0x0
6197 00:24:43.306698 DBI_WR = 0x0
6198 00:24:43.306792 DBI_RD = 0x0
6199 00:24:43.310440 OTF = 0x1
6200 00:24:43.313224 ===================================
6201 00:24:43.320013 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6202 00:24:43.323516 nWR fixed to 30
6203 00:24:43.326566 [ModeRegInit_LP4] CH0 RK0
6204 00:24:43.326645 [ModeRegInit_LP4] CH0 RK1
6205 00:24:43.329777 [ModeRegInit_LP4] CH1 RK0
6206 00:24:43.333201 [ModeRegInit_LP4] CH1 RK1
6207 00:24:43.333281 match AC timing 19
6208 00:24:43.339899 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6209 00:24:43.343600 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6210 00:24:43.346489 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6211 00:24:43.353076 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6212 00:24:43.356271 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6213 00:24:43.356355 ==
6214 00:24:43.359451 Dram Type= 6, Freq= 0, CH_0, rank 0
6215 00:24:43.363537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6216 00:24:43.363624 ==
6217 00:24:43.369655 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6218 00:24:43.376459 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6219 00:24:43.379539 [CA 0] Center 36 (8~64) winsize 57
6220 00:24:43.383354 [CA 1] Center 36 (8~64) winsize 57
6221 00:24:43.386100 [CA 2] Center 36 (8~64) winsize 57
6222 00:24:43.386174 [CA 3] Center 36 (8~64) winsize 57
6223 00:24:43.389580 [CA 4] Center 36 (8~64) winsize 57
6224 00:24:43.392992 [CA 5] Center 36 (8~64) winsize 57
6225 00:24:43.393063
6226 00:24:43.399703 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6227 00:24:43.399781
6228 00:24:43.402483 [CATrainingPosCal] consider 1 rank data
6229 00:24:43.405725 u2DelayCellTimex100 = 270/100 ps
6230 00:24:43.409556 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 00:24:43.412364 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 00:24:43.415827 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 00:24:43.418955 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 00:24:43.422287 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 00:24:43.425636 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 00:24:43.425711
6237 00:24:43.429084 CA PerBit enable=1, Macro0, CA PI delay=36
6238 00:24:43.429159
6239 00:24:43.432669 [CBTSetCACLKResult] CA Dly = 36
6240 00:24:43.435501 CS Dly: 1 (0~32)
6241 00:24:43.435580 ==
6242 00:24:43.439039 Dram Type= 6, Freq= 0, CH_0, rank 1
6243 00:24:43.442422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6244 00:24:43.442492 ==
6245 00:24:43.448714 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6246 00:24:43.455658 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6247 00:24:43.455735 [CA 0] Center 36 (8~64) winsize 57
6248 00:24:43.458890 [CA 1] Center 36 (8~64) winsize 57
6249 00:24:43.462291 [CA 2] Center 36 (8~64) winsize 57
6250 00:24:43.465808 [CA 3] Center 36 (8~64) winsize 57
6251 00:24:43.468624 [CA 4] Center 36 (8~64) winsize 57
6252 00:24:43.472226 [CA 5] Center 36 (8~64) winsize 57
6253 00:24:43.472298
6254 00:24:43.475665 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6255 00:24:43.475736
6256 00:24:43.478541 [CATrainingPosCal] consider 2 rank data
6257 00:24:43.482100 u2DelayCellTimex100 = 270/100 ps
6258 00:24:43.485377 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 00:24:43.488539 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 00:24:43.495672 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 00:24:43.498659 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 00:24:43.501986 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 00:24:43.505221 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 00:24:43.505296
6265 00:24:43.508578 CA PerBit enable=1, Macro0, CA PI delay=36
6266 00:24:43.508655
6267 00:24:43.511943 [CBTSetCACLKResult] CA Dly = 36
6268 00:24:43.512019 CS Dly: 1 (0~32)
6269 00:24:43.515312
6270 00:24:43.518450 ----->DramcWriteLeveling(PI) begin...
6271 00:24:43.518522 ==
6272 00:24:43.521695 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 00:24:43.525127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 00:24:43.525200 ==
6275 00:24:43.528593 Write leveling (Byte 0): 40 => 8
6276 00:24:43.531582 Write leveling (Byte 1): 40 => 8
6277 00:24:43.534915 DramcWriteLeveling(PI) end<-----
6278 00:24:43.534991
6279 00:24:43.535086 ==
6280 00:24:43.538869 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 00:24:43.541716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 00:24:43.541794 ==
6283 00:24:43.545086 [Gating] SW mode calibration
6284 00:24:43.551507 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6285 00:24:43.557990 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6286 00:24:43.561679 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6287 00:24:43.564948 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6288 00:24:43.571883 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 00:24:43.574484 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6290 00:24:43.578092 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 00:24:43.584866 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 00:24:43.588019 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 00:24:43.591295 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6294 00:24:43.594666 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6295 00:24:43.598084 Total UI for P1: 0, mck2ui 16
6296 00:24:43.601337 best dqsien dly found for B0: ( 0, 14, 24)
6297 00:24:43.605021 Total UI for P1: 0, mck2ui 16
6298 00:24:43.607933 best dqsien dly found for B1: ( 0, 14, 24)
6299 00:24:43.611329 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6300 00:24:43.618029 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6301 00:24:43.618104
6302 00:24:43.621748 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6303 00:24:43.624531 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6304 00:24:43.628167 [Gating] SW calibration Done
6305 00:24:43.628238 ==
6306 00:24:43.631128 Dram Type= 6, Freq= 0, CH_0, rank 0
6307 00:24:43.634518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6308 00:24:43.634585 ==
6309 00:24:43.637966 RX Vref Scan: 0
6310 00:24:43.638031
6311 00:24:43.638091 RX Vref 0 -> 0, step: 1
6312 00:24:43.638146
6313 00:24:43.641409 RX Delay -410 -> 252, step: 16
6314 00:24:43.644804 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6315 00:24:43.651365 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6316 00:24:43.654834 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6317 00:24:43.657975 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6318 00:24:43.660951 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6319 00:24:43.667883 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6320 00:24:43.671230 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6321 00:24:43.674356 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6322 00:24:43.677439 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6323 00:24:43.684304 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6324 00:24:43.687526 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6325 00:24:43.690982 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6326 00:24:43.694523 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6327 00:24:43.701031 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6328 00:24:43.704540 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6329 00:24:43.707486 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6330 00:24:43.707586 ==
6331 00:24:43.711272 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 00:24:43.717417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 00:24:43.717491 ==
6334 00:24:43.717551 DQS Delay:
6335 00:24:43.720730 DQS0 = 59, DQS1 = 59
6336 00:24:43.720796 DQM Delay:
6337 00:24:43.720852 DQM0 = 18, DQM1 = 10
6338 00:24:43.724562 DQ Delay:
6339 00:24:43.727862 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6340 00:24:43.730653 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6341 00:24:43.730722 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6342 00:24:43.737696 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6343 00:24:43.737769
6344 00:24:43.737832
6345 00:24:43.737887 ==
6346 00:24:43.740920 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 00:24:43.743841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 00:24:43.743908 ==
6349 00:24:43.743969
6350 00:24:43.744024
6351 00:24:43.747238 TX Vref Scan disable
6352 00:24:43.747328 == TX Byte 0 ==
6353 00:24:43.751062 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 00:24:43.757561 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 00:24:43.757642 == TX Byte 1 ==
6356 00:24:43.760456 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6357 00:24:43.767295 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6358 00:24:43.767381 ==
6359 00:24:43.770554 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 00:24:43.774183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 00:24:43.774294 ==
6362 00:24:43.774392
6363 00:24:43.774483
6364 00:24:43.777299 TX Vref Scan disable
6365 00:24:43.777407 == TX Byte 0 ==
6366 00:24:43.783697 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6367 00:24:43.787030 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6368 00:24:43.787106 == TX Byte 1 ==
6369 00:24:43.794055 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6370 00:24:43.797021 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6371 00:24:43.797101
6372 00:24:43.797164 [DATLAT]
6373 00:24:43.800449 Freq=400, CH0 RK0
6374 00:24:43.800521
6375 00:24:43.800586 DATLAT Default: 0xf
6376 00:24:43.803990 0, 0xFFFF, sum = 0
6377 00:24:43.804067 1, 0xFFFF, sum = 0
6378 00:24:43.806782 2, 0xFFFF, sum = 0
6379 00:24:43.806860 3, 0xFFFF, sum = 0
6380 00:24:43.810314 4, 0xFFFF, sum = 0
6381 00:24:43.810386 5, 0xFFFF, sum = 0
6382 00:24:43.814096 6, 0xFFFF, sum = 0
6383 00:24:43.814176 7, 0xFFFF, sum = 0
6384 00:24:43.817311 8, 0xFFFF, sum = 0
6385 00:24:43.817389 9, 0xFFFF, sum = 0
6386 00:24:43.820200 10, 0xFFFF, sum = 0
6387 00:24:43.820273 11, 0xFFFF, sum = 0
6388 00:24:43.823717 12, 0xFFFF, sum = 0
6389 00:24:43.823789 13, 0x0, sum = 1
6390 00:24:43.827177 14, 0x0, sum = 2
6391 00:24:43.827282 15, 0x0, sum = 3
6392 00:24:43.830053 16, 0x0, sum = 4
6393 00:24:43.830130 best_step = 14
6394 00:24:43.830196
6395 00:24:43.830254 ==
6396 00:24:43.833494 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 00:24:43.840082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 00:24:43.840164 ==
6399 00:24:43.840247 RX Vref Scan: 1
6400 00:24:43.840322
6401 00:24:43.843498 RX Vref 0 -> 0, step: 1
6402 00:24:43.843568
6403 00:24:43.846575 RX Delay -359 -> 252, step: 8
6404 00:24:43.846649
6405 00:24:43.849984 Set Vref, RX VrefLevel [Byte0]: 61
6406 00:24:43.853550 [Byte1]: 54
6407 00:24:43.857035
6408 00:24:43.857105 Final RX Vref Byte 0 = 61 to rank0
6409 00:24:43.860487 Final RX Vref Byte 1 = 54 to rank0
6410 00:24:43.863252 Final RX Vref Byte 0 = 61 to rank1
6411 00:24:43.866757 Final RX Vref Byte 1 = 54 to rank1==
6412 00:24:43.870235 Dram Type= 6, Freq= 0, CH_0, rank 0
6413 00:24:43.876903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 00:24:43.876984 ==
6415 00:24:43.877049 DQS Delay:
6416 00:24:43.880272 DQS0 = 60, DQS1 = 68
6417 00:24:43.880351 DQM Delay:
6418 00:24:43.880425 DQM0 = 14, DQM1 = 13
6419 00:24:43.883643 DQ Delay:
6420 00:24:43.886708 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6421 00:24:43.890033 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6422 00:24:43.890137 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6423 00:24:43.893229 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6424 00:24:43.897032
6425 00:24:43.897106
6426 00:24:43.902930 [DQSOSCAuto] RK0, (LSB)MR18= 0x8685, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6427 00:24:43.906396 CH0 RK0: MR19=C0C, MR18=8685
6428 00:24:43.913340 CH0_RK0: MR19=0xC0C, MR18=0x8685, DQSOSC=393, MR23=63, INC=382, DEC=254
6429 00:24:43.913421 ==
6430 00:24:43.916777 Dram Type= 6, Freq= 0, CH_0, rank 1
6431 00:24:43.919654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 00:24:43.919733 ==
6433 00:24:43.923046 [Gating] SW mode calibration
6434 00:24:43.929508 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6435 00:24:43.936470 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6436 00:24:43.939661 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6437 00:24:43.943093 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6438 00:24:43.949518 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 00:24:43.953114 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6440 00:24:43.956346 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 00:24:43.963305 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 00:24:43.966022 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 00:24:43.969346 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 00:24:43.976028 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 00:24:43.976107 Total UI for P1: 0, mck2ui 16
6446 00:24:43.979391 best dqsien dly found for B0: ( 0, 14, 24)
6447 00:24:43.982874 Total UI for P1: 0, mck2ui 16
6448 00:24:43.985833 best dqsien dly found for B1: ( 0, 14, 24)
6449 00:24:43.992655 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6450 00:24:43.996067 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6451 00:24:43.996141
6452 00:24:43.999275 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6453 00:24:44.002748 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6454 00:24:44.006232 [Gating] SW calibration Done
6455 00:24:44.006348 ==
6456 00:24:44.009585 Dram Type= 6, Freq= 0, CH_0, rank 1
6457 00:24:44.012643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 00:24:44.012716 ==
6459 00:24:44.015982 RX Vref Scan: 0
6460 00:24:44.016065
6461 00:24:44.016128 RX Vref 0 -> 0, step: 1
6462 00:24:44.016185
6463 00:24:44.019227 RX Delay -410 -> 252, step: 16
6464 00:24:44.022541 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6465 00:24:44.029472 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6466 00:24:44.032485 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6467 00:24:44.035970 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6468 00:24:44.039090 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6469 00:24:44.045805 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6470 00:24:44.049184 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6471 00:24:44.052423 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6472 00:24:44.055933 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6473 00:24:44.062210 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6474 00:24:44.065559 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6475 00:24:44.069152 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6476 00:24:44.075490 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6477 00:24:44.078940 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6478 00:24:44.082325 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6479 00:24:44.085944 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6480 00:24:44.086056 ==
6481 00:24:44.088668 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 00:24:44.095851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 00:24:44.095932 ==
6484 00:24:44.095995 DQS Delay:
6485 00:24:44.098795 DQS0 = 59, DQS1 = 59
6486 00:24:44.098865 DQM Delay:
6487 00:24:44.102234 DQM0 = 17, DQM1 = 10
6488 00:24:44.102338 DQ Delay:
6489 00:24:44.105552 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6490 00:24:44.109297 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6491 00:24:44.112062 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6492 00:24:44.115360 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6493 00:24:44.115487
6494 00:24:44.115552
6495 00:24:44.115609 ==
6496 00:24:44.118679 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 00:24:44.121990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 00:24:44.122091 ==
6499 00:24:44.122201
6500 00:24:44.122298
6501 00:24:44.125105 TX Vref Scan disable
6502 00:24:44.125215 == TX Byte 0 ==
6503 00:24:44.132498 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6504 00:24:44.135083 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6505 00:24:44.135183 == TX Byte 1 ==
6506 00:24:44.142153 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6507 00:24:44.145058 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6508 00:24:44.145138 ==
6509 00:24:44.148436 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 00:24:44.151984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 00:24:44.152062 ==
6512 00:24:44.152123
6513 00:24:44.152185
6514 00:24:44.154966 TX Vref Scan disable
6515 00:24:44.155030 == TX Byte 0 ==
6516 00:24:44.161875 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6517 00:24:44.165044 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6518 00:24:44.165150 == TX Byte 1 ==
6519 00:24:44.171666 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6520 00:24:44.175038 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6521 00:24:44.175109
6522 00:24:44.175186 [DATLAT]
6523 00:24:44.178597 Freq=400, CH0 RK1
6524 00:24:44.178666
6525 00:24:44.178728 DATLAT Default: 0xe
6526 00:24:44.181621 0, 0xFFFF, sum = 0
6527 00:24:44.181686 1, 0xFFFF, sum = 0
6528 00:24:44.184835 2, 0xFFFF, sum = 0
6529 00:24:44.184910 3, 0xFFFF, sum = 0
6530 00:24:44.188366 4, 0xFFFF, sum = 0
6531 00:24:44.188435 5, 0xFFFF, sum = 0
6532 00:24:44.191777 6, 0xFFFF, sum = 0
6533 00:24:44.191845 7, 0xFFFF, sum = 0
6534 00:24:44.195396 8, 0xFFFF, sum = 0
6535 00:24:44.195471 9, 0xFFFF, sum = 0
6536 00:24:44.198646 10, 0xFFFF, sum = 0
6537 00:24:44.198748 11, 0xFFFF, sum = 0
6538 00:24:44.201671 12, 0xFFFF, sum = 0
6539 00:24:44.201786 13, 0x0, sum = 1
6540 00:24:44.205077 14, 0x0, sum = 2
6541 00:24:44.205181 15, 0x0, sum = 3
6542 00:24:44.208687 16, 0x0, sum = 4
6543 00:24:44.208767 best_step = 14
6544 00:24:44.208836
6545 00:24:44.208895 ==
6546 00:24:44.211660 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 00:24:44.218267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 00:24:44.218363 ==
6549 00:24:44.218452 RX Vref Scan: 0
6550 00:24:44.218538
6551 00:24:44.222198 RX Vref 0 -> 0, step: 1
6552 00:24:44.222295
6553 00:24:44.225092 RX Delay -359 -> 252, step: 8
6554 00:24:44.231992 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6555 00:24:44.235126 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6556 00:24:44.238711 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6557 00:24:44.241483 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6558 00:24:44.248195 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6559 00:24:44.251802 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6560 00:24:44.254784 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6561 00:24:44.258668 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6562 00:24:44.265106 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6563 00:24:44.268061 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6564 00:24:44.271332 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6565 00:24:44.275087 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6566 00:24:44.281803 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6567 00:24:44.284875 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6568 00:24:44.287957 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6569 00:24:44.294981 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6570 00:24:44.295055 ==
6571 00:24:44.298330 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 00:24:44.301434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 00:24:44.301527 ==
6574 00:24:44.301617 DQS Delay:
6575 00:24:44.305094 DQS0 = 60, DQS1 = 72
6576 00:24:44.305198 DQM Delay:
6577 00:24:44.307990 DQM0 = 12, DQM1 = 18
6578 00:24:44.308071 DQ Delay:
6579 00:24:44.311250 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6580 00:24:44.314557 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6581 00:24:44.318544 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =12
6582 00:24:44.321412 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6583 00:24:44.321483
6584 00:24:44.321545
6585 00:24:44.328011 [DQSOSCAuto] RK1, (LSB)MR18= 0xcc84, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6586 00:24:44.331309 CH0 RK1: MR19=C0C, MR18=CC84
6587 00:24:44.338224 CH0_RK1: MR19=0xC0C, MR18=0xCC84, DQSOSC=384, MR23=63, INC=400, DEC=267
6588 00:24:44.341645 [RxdqsGatingPostProcess] freq 400
6589 00:24:44.345154 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6590 00:24:44.348022 best DQS0 dly(2T, 0.5T) = (0, 10)
6591 00:24:44.351417 best DQS1 dly(2T, 0.5T) = (0, 10)
6592 00:24:44.354832 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6593 00:24:44.358132 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6594 00:24:44.361518 best DQS0 dly(2T, 0.5T) = (0, 10)
6595 00:24:44.364559 best DQS1 dly(2T, 0.5T) = (0, 10)
6596 00:24:44.368026 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6597 00:24:44.371570 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6598 00:24:44.374987 Pre-setting of DQS Precalculation
6599 00:24:44.378187 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6600 00:24:44.380998 ==
6601 00:24:44.384551 Dram Type= 6, Freq= 0, CH_1, rank 0
6602 00:24:44.387991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 00:24:44.388071 ==
6604 00:24:44.394405 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6605 00:24:44.397825 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6606 00:24:44.400889 [CA 0] Center 36 (8~64) winsize 57
6607 00:24:44.404766 [CA 1] Center 36 (8~64) winsize 57
6608 00:24:44.407574 [CA 2] Center 36 (8~64) winsize 57
6609 00:24:44.410933 [CA 3] Center 36 (8~64) winsize 57
6610 00:24:44.413990 [CA 4] Center 36 (8~64) winsize 57
6611 00:24:44.417395 [CA 5] Center 36 (8~64) winsize 57
6612 00:24:44.417466
6613 00:24:44.421159 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6614 00:24:44.421230
6615 00:24:44.423936 [CATrainingPosCal] consider 1 rank data
6616 00:24:44.427363 u2DelayCellTimex100 = 270/100 ps
6617 00:24:44.430551 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 00:24:44.434022 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 00:24:44.437724 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 00:24:44.444408 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 00:24:44.447196 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 00:24:44.450662 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 00:24:44.450741
6624 00:24:44.454142 CA PerBit enable=1, Macro0, CA PI delay=36
6625 00:24:44.454213
6626 00:24:44.457546 [CBTSetCACLKResult] CA Dly = 36
6627 00:24:44.457615 CS Dly: 1 (0~32)
6628 00:24:44.457674 ==
6629 00:24:44.460402 Dram Type= 6, Freq= 0, CH_1, rank 1
6630 00:24:44.467288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 00:24:44.467401 ==
6632 00:24:44.470537 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6633 00:24:44.476928 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6634 00:24:44.480231 [CA 0] Center 36 (8~64) winsize 57
6635 00:24:44.484054 [CA 1] Center 36 (8~64) winsize 57
6636 00:24:44.486990 [CA 2] Center 36 (8~64) winsize 57
6637 00:24:44.490535 [CA 3] Center 36 (8~64) winsize 57
6638 00:24:44.493519 [CA 4] Center 36 (8~64) winsize 57
6639 00:24:44.497297 [CA 5] Center 36 (8~64) winsize 57
6640 00:24:44.497370
6641 00:24:44.500473 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6642 00:24:44.500559
6643 00:24:44.503825 [CATrainingPosCal] consider 2 rank data
6644 00:24:44.507086 u2DelayCellTimex100 = 270/100 ps
6645 00:24:44.510467 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 00:24:44.513372 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 00:24:44.516965 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 00:24:44.520055 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 00:24:44.523563 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 00:24:44.527074 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 00:24:44.530392
6652 00:24:44.533220 CA PerBit enable=1, Macro0, CA PI delay=36
6653 00:24:44.533296
6654 00:24:44.537253 [CBTSetCACLKResult] CA Dly = 36
6655 00:24:44.537328 CS Dly: 1 (0~32)
6656 00:24:44.537406
6657 00:24:44.539950 ----->DramcWriteLeveling(PI) begin...
6658 00:24:44.540021 ==
6659 00:24:44.543441 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 00:24:44.546916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 00:24:44.546993 ==
6662 00:24:44.550134 Write leveling (Byte 0): 40 => 8
6663 00:24:44.553212 Write leveling (Byte 1): 40 => 8
6664 00:24:44.556855 DramcWriteLeveling(PI) end<-----
6665 00:24:44.556930
6666 00:24:44.557013 ==
6667 00:24:44.560013 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 00:24:44.566861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 00:24:44.566939 ==
6670 00:24:44.567019 [Gating] SW mode calibration
6671 00:24:44.576470 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6672 00:24:44.579956 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6673 00:24:44.583333 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6674 00:24:44.589897 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6675 00:24:44.593178 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6676 00:24:44.596371 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6677 00:24:44.603296 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 00:24:44.606708 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 00:24:44.610058 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 00:24:44.616574 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6681 00:24:44.619974 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6682 00:24:44.622792 Total UI for P1: 0, mck2ui 16
6683 00:24:44.626215 best dqsien dly found for B0: ( 0, 14, 24)
6684 00:24:44.629373 Total UI for P1: 0, mck2ui 16
6685 00:24:44.633129 best dqsien dly found for B1: ( 0, 14, 24)
6686 00:24:44.636121 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6687 00:24:44.639519 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6688 00:24:44.639594
6689 00:24:44.643143 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6690 00:24:44.646186 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6691 00:24:44.649765 [Gating] SW calibration Done
6692 00:24:44.649840 ==
6693 00:24:44.652730 Dram Type= 6, Freq= 0, CH_1, rank 0
6694 00:24:44.659462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6695 00:24:44.659541 ==
6696 00:24:44.659626 RX Vref Scan: 0
6697 00:24:44.659704
6698 00:24:44.662689 RX Vref 0 -> 0, step: 1
6699 00:24:44.662758
6700 00:24:44.665954 RX Delay -410 -> 252, step: 16
6701 00:24:44.669536 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6702 00:24:44.673684 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6703 00:24:44.679285 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6704 00:24:44.682682 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6705 00:24:44.685826 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6706 00:24:44.689104 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6707 00:24:44.695966 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6708 00:24:44.699240 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6709 00:24:44.703028 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6710 00:24:44.705670 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6711 00:24:44.712499 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6712 00:24:44.715661 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6713 00:24:44.718850 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6714 00:24:44.722546 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6715 00:24:44.729075 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6716 00:24:44.732480 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6717 00:24:44.732550 ==
6718 00:24:44.735594 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 00:24:44.739041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 00:24:44.739144 ==
6721 00:24:44.742421 DQS Delay:
6722 00:24:44.742490 DQS0 = 51, DQS1 = 67
6723 00:24:44.742557 DQM Delay:
6724 00:24:44.745868 DQM0 = 12, DQM1 = 17
6725 00:24:44.745935 DQ Delay:
6726 00:24:44.749019 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6727 00:24:44.752609 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6728 00:24:44.756045 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6729 00:24:44.759266 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6730 00:24:44.759359
6731 00:24:44.759477
6732 00:24:44.759535 ==
6733 00:24:44.762428 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 00:24:44.765789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 00:24:44.768850 ==
6736 00:24:44.768936
6737 00:24:44.768998
6738 00:24:44.769063 TX Vref Scan disable
6739 00:24:44.772853 == TX Byte 0 ==
6740 00:24:44.775952 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 00:24:44.779027 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 00:24:44.782466 == TX Byte 1 ==
6743 00:24:44.785530 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6744 00:24:44.789325 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6745 00:24:44.789399 ==
6746 00:24:44.792221 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 00:24:44.798905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 00:24:44.798985 ==
6749 00:24:44.799056
6750 00:24:44.799114
6751 00:24:44.799169 TX Vref Scan disable
6752 00:24:44.802433 == TX Byte 0 ==
6753 00:24:44.805529 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 00:24:44.809168 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 00:24:44.812973 == TX Byte 1 ==
6756 00:24:44.815621 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6757 00:24:44.819179 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6758 00:24:44.819272
6759 00:24:44.822247 [DATLAT]
6760 00:24:44.822318 Freq=400, CH1 RK0
6761 00:24:44.822385
6762 00:24:44.825669 DATLAT Default: 0xf
6763 00:24:44.825736 0, 0xFFFF, sum = 0
6764 00:24:44.828784 1, 0xFFFF, sum = 0
6765 00:24:44.828852 2, 0xFFFF, sum = 0
6766 00:24:44.831897 3, 0xFFFF, sum = 0
6767 00:24:44.831971 4, 0xFFFF, sum = 0
6768 00:24:44.835367 5, 0xFFFF, sum = 0
6769 00:24:44.835484 6, 0xFFFF, sum = 0
6770 00:24:44.838625 7, 0xFFFF, sum = 0
6771 00:24:44.838691 8, 0xFFFF, sum = 0
6772 00:24:44.842245 9, 0xFFFF, sum = 0
6773 00:24:44.842312 10, 0xFFFF, sum = 0
6774 00:24:44.845703 11, 0xFFFF, sum = 0
6775 00:24:44.845769 12, 0xFFFF, sum = 0
6776 00:24:44.849175 13, 0x0, sum = 1
6777 00:24:44.849242 14, 0x0, sum = 2
6778 00:24:44.852089 15, 0x0, sum = 3
6779 00:24:44.852157 16, 0x0, sum = 4
6780 00:24:44.855405 best_step = 14
6781 00:24:44.855489
6782 00:24:44.855547 ==
6783 00:24:44.858549 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 00:24:44.861964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 00:24:44.862033 ==
6786 00:24:44.865384 RX Vref Scan: 1
6787 00:24:44.865449
6788 00:24:44.865507 RX Vref 0 -> 0, step: 1
6789 00:24:44.865563
6790 00:24:44.868640 RX Delay -375 -> 252, step: 8
6791 00:24:44.868705
6792 00:24:44.872133 Set Vref, RX VrefLevel [Byte0]: 55
6793 00:24:44.875450 [Byte1]: 50
6794 00:24:44.880327
6795 00:24:44.880408 Final RX Vref Byte 0 = 55 to rank0
6796 00:24:44.883604 Final RX Vref Byte 1 = 50 to rank0
6797 00:24:44.886519 Final RX Vref Byte 0 = 55 to rank1
6798 00:24:44.890146 Final RX Vref Byte 1 = 50 to rank1==
6799 00:24:44.893350 Dram Type= 6, Freq= 0, CH_1, rank 0
6800 00:24:44.899885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 00:24:44.899959 ==
6802 00:24:44.900027 DQS Delay:
6803 00:24:44.903694 DQS0 = 56, DQS1 = 64
6804 00:24:44.903767 DQM Delay:
6805 00:24:44.903827 DQM0 = 12, DQM1 = 10
6806 00:24:44.906800 DQ Delay:
6807 00:24:44.909832 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6808 00:24:44.909907 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6809 00:24:44.913472 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6810 00:24:44.916978 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6811 00:24:44.917046
6812 00:24:44.920044
6813 00:24:44.926554 [DQSOSCAuto] RK0, (LSB)MR18= 0x596c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6814 00:24:44.929703 CH1 RK0: MR19=C0C, MR18=596C
6815 00:24:44.936307 CH1_RK0: MR19=0xC0C, MR18=0x596C, DQSOSC=396, MR23=63, INC=376, DEC=251
6816 00:24:44.936381 ==
6817 00:24:44.940033 Dram Type= 6, Freq= 0, CH_1, rank 1
6818 00:24:44.943047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 00:24:44.943115 ==
6820 00:24:44.946585 [Gating] SW mode calibration
6821 00:24:44.953272 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6822 00:24:44.959595 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6823 00:24:44.962793 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6824 00:24:44.966215 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6825 00:24:44.972970 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6826 00:24:44.976203 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6827 00:24:44.979455 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 00:24:44.986087 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 00:24:44.989562 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 00:24:44.992898 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6831 00:24:44.999215 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6832 00:24:44.999292 Total UI for P1: 0, mck2ui 16
6833 00:24:45.006253 best dqsien dly found for B0: ( 0, 14, 24)
6834 00:24:45.006338 Total UI for P1: 0, mck2ui 16
6835 00:24:45.009077 best dqsien dly found for B1: ( 0, 14, 24)
6836 00:24:45.015720 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6837 00:24:45.019264 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6838 00:24:45.019336
6839 00:24:45.022676 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6840 00:24:45.025570 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6841 00:24:45.029274 [Gating] SW calibration Done
6842 00:24:45.029345 ==
6843 00:24:45.032147 Dram Type= 6, Freq= 0, CH_1, rank 1
6844 00:24:45.036250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 00:24:45.036324 ==
6846 00:24:45.039382 RX Vref Scan: 0
6847 00:24:45.039453
6848 00:24:45.039528 RX Vref 0 -> 0, step: 1
6849 00:24:45.039605
6850 00:24:45.042159 RX Delay -410 -> 252, step: 16
6851 00:24:45.049356 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6852 00:24:45.052370 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6853 00:24:45.055934 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6854 00:24:45.059119 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6855 00:24:45.062129 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6856 00:24:45.068676 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6857 00:24:45.072013 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6858 00:24:45.075821 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6859 00:24:45.078913 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6860 00:24:45.085317 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6861 00:24:45.089290 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6862 00:24:45.092608 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6863 00:24:45.098930 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6864 00:24:45.102297 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6865 00:24:45.105408 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6866 00:24:45.108733 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6867 00:24:45.108811 ==
6868 00:24:45.112277 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 00:24:45.119495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 00:24:45.119585 ==
6871 00:24:45.119669 DQS Delay:
6872 00:24:45.121908 DQS0 = 59, DQS1 = 59
6873 00:24:45.121979 DQM Delay:
6874 00:24:45.125574 DQM0 = 19, DQM1 = 13
6875 00:24:45.125644 DQ Delay:
6876 00:24:45.128934 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6877 00:24:45.131955 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6878 00:24:45.135281 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6879 00:24:45.138976 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6880 00:24:45.139046
6881 00:24:45.139124
6882 00:24:45.139197 ==
6883 00:24:45.141832 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 00:24:45.145410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 00:24:45.145481 ==
6886 00:24:45.145557
6887 00:24:45.145629
6888 00:24:45.148718 TX Vref Scan disable
6889 00:24:45.148787 == TX Byte 0 ==
6890 00:24:45.155027 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6891 00:24:45.158718 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6892 00:24:45.158794 == TX Byte 1 ==
6893 00:24:45.164905 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6894 00:24:45.168237 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6895 00:24:45.168312 ==
6896 00:24:45.172036 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 00:24:45.175042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 00:24:45.175114 ==
6899 00:24:45.175196
6900 00:24:45.175289
6901 00:24:45.178282 TX Vref Scan disable
6902 00:24:45.178354 == TX Byte 0 ==
6903 00:24:45.185157 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6904 00:24:45.188642 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6905 00:24:45.188718 == TX Byte 1 ==
6906 00:24:45.194974 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6907 00:24:45.198403 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6908 00:24:45.198478
6909 00:24:45.198555 [DATLAT]
6910 00:24:45.201553 Freq=400, CH1 RK1
6911 00:24:45.201624
6912 00:24:45.201702 DATLAT Default: 0xe
6913 00:24:45.204792 0, 0xFFFF, sum = 0
6914 00:24:45.204873 1, 0xFFFF, sum = 0
6915 00:24:45.208170 2, 0xFFFF, sum = 0
6916 00:24:45.208249 3, 0xFFFF, sum = 0
6917 00:24:45.211959 4, 0xFFFF, sum = 0
6918 00:24:45.212033 5, 0xFFFF, sum = 0
6919 00:24:45.215234 6, 0xFFFF, sum = 0
6920 00:24:45.215309 7, 0xFFFF, sum = 0
6921 00:24:45.218334 8, 0xFFFF, sum = 0
6922 00:24:45.218406 9, 0xFFFF, sum = 0
6923 00:24:45.221460 10, 0xFFFF, sum = 0
6924 00:24:45.221545 11, 0xFFFF, sum = 0
6925 00:24:45.224805 12, 0xFFFF, sum = 0
6926 00:24:45.224875 13, 0x0, sum = 1
6927 00:24:45.228645 14, 0x0, sum = 2
6928 00:24:45.228736 15, 0x0, sum = 3
6929 00:24:45.231493 16, 0x0, sum = 4
6930 00:24:45.231565 best_step = 14
6931 00:24:45.231643
6932 00:24:45.231717 ==
6933 00:24:45.234901 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 00:24:45.241698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 00:24:45.241770 ==
6936 00:24:45.241848 RX Vref Scan: 0
6937 00:24:45.241922
6938 00:24:45.244924 RX Vref 0 -> 0, step: 1
6939 00:24:45.244996
6940 00:24:45.248107 RX Delay -359 -> 252, step: 8
6941 00:24:45.255048 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6942 00:24:45.257860 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6943 00:24:45.261712 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6944 00:24:45.264918 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6945 00:24:45.271615 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6946 00:24:45.274646 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6947 00:24:45.278068 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6948 00:24:45.281435 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6949 00:24:45.287848 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6950 00:24:45.291313 iDelay=217, Bit 9, Center -60 (-319 ~ 200) 520
6951 00:24:45.294460 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6952 00:24:45.301436 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6953 00:24:45.304685 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6954 00:24:45.307949 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6955 00:24:45.311062 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6956 00:24:45.317902 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6957 00:24:45.317977 ==
6958 00:24:45.320975 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 00:24:45.324208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 00:24:45.324284 ==
6961 00:24:45.324363 DQS Delay:
6962 00:24:45.327923 DQS0 = 60, DQS1 = 64
6963 00:24:45.327994 DQM Delay:
6964 00:24:45.330946 DQM0 = 13, DQM1 = 11
6965 00:24:45.331015 DQ Delay:
6966 00:24:45.334513 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6967 00:24:45.337500 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6968 00:24:45.340733 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6969 00:24:45.344077 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6970 00:24:45.344147
6971 00:24:45.344224
6972 00:24:45.351056 [DQSOSCAuto] RK1, (LSB)MR18= 0x7dad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6973 00:24:45.354093 CH1 RK1: MR19=C0C, MR18=7DAD
6974 00:24:45.361067 CH1_RK1: MR19=0xC0C, MR18=0x7DAD, DQSOSC=388, MR23=63, INC=392, DEC=261
6975 00:24:45.364341 [RxdqsGatingPostProcess] freq 400
6976 00:24:45.370683 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6977 00:24:45.374209 best DQS0 dly(2T, 0.5T) = (0, 10)
6978 00:24:45.374283 best DQS1 dly(2T, 0.5T) = (0, 10)
6979 00:24:45.377735 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6980 00:24:45.380883 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6981 00:24:45.384232 best DQS0 dly(2T, 0.5T) = (0, 10)
6982 00:24:45.387670 best DQS1 dly(2T, 0.5T) = (0, 10)
6983 00:24:45.390478 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6984 00:24:45.394195 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6985 00:24:45.397150 Pre-setting of DQS Precalculation
6986 00:24:45.404088 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6987 00:24:45.410521 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6988 00:24:45.417068 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6989 00:24:45.417147
6990 00:24:45.417226
6991 00:24:45.420597 [Calibration Summary] 800 Mbps
6992 00:24:45.420680 CH 0, Rank 0
6993 00:24:45.423963 SW Impedance : PASS
6994 00:24:45.426959 DUTY Scan : NO K
6995 00:24:45.427058 ZQ Calibration : PASS
6996 00:24:45.430449 Jitter Meter : NO K
6997 00:24:45.430553 CBT Training : PASS
6998 00:24:45.433781 Write leveling : PASS
6999 00:24:45.437098 RX DQS gating : PASS
7000 00:24:45.437174 RX DQ/DQS(RDDQC) : PASS
7001 00:24:45.440302 TX DQ/DQS : PASS
7002 00:24:45.443530 RX DATLAT : PASS
7003 00:24:45.443605 RX DQ/DQS(Engine): PASS
7004 00:24:45.446941 TX OE : NO K
7005 00:24:45.447009 All Pass.
7006 00:24:45.447074
7007 00:24:45.450496 CH 0, Rank 1
7008 00:24:45.450565 SW Impedance : PASS
7009 00:24:45.453903 DUTY Scan : NO K
7010 00:24:45.456847 ZQ Calibration : PASS
7011 00:24:45.456920 Jitter Meter : NO K
7012 00:24:45.460323 CBT Training : PASS
7013 00:24:45.463948 Write leveling : NO K
7014 00:24:45.464022 RX DQS gating : PASS
7015 00:24:45.466788 RX DQ/DQS(RDDQC) : PASS
7016 00:24:45.469901 TX DQ/DQS : PASS
7017 00:24:45.469969 RX DATLAT : PASS
7018 00:24:45.474013 RX DQ/DQS(Engine): PASS
7019 00:24:45.476784 TX OE : NO K
7020 00:24:45.476860 All Pass.
7021 00:24:45.476920
7022 00:24:45.476977 CH 1, Rank 0
7023 00:24:45.480379 SW Impedance : PASS
7024 00:24:45.483738 DUTY Scan : NO K
7025 00:24:45.483814 ZQ Calibration : PASS
7026 00:24:45.486770 Jitter Meter : NO K
7027 00:24:45.490196 CBT Training : PASS
7028 00:24:45.490292 Write leveling : PASS
7029 00:24:45.493343 RX DQS gating : PASS
7030 00:24:45.493432 RX DQ/DQS(RDDQC) : PASS
7031 00:24:45.496898 TX DQ/DQS : PASS
7032 00:24:45.500276 RX DATLAT : PASS
7033 00:24:45.500345 RX DQ/DQS(Engine): PASS
7034 00:24:45.503379 TX OE : NO K
7035 00:24:45.503485 All Pass.
7036 00:24:45.503544
7037 00:24:45.506619 CH 1, Rank 1
7038 00:24:45.506691 SW Impedance : PASS
7039 00:24:45.510049 DUTY Scan : NO K
7040 00:24:45.513516 ZQ Calibration : PASS
7041 00:24:45.513591 Jitter Meter : NO K
7042 00:24:45.516624 CBT Training : PASS
7043 00:24:45.519959 Write leveling : NO K
7044 00:24:45.520029 RX DQS gating : PASS
7045 00:24:45.523113 RX DQ/DQS(RDDQC) : PASS
7046 00:24:45.526501 TX DQ/DQS : PASS
7047 00:24:45.526583 RX DATLAT : PASS
7048 00:24:45.529832 RX DQ/DQS(Engine): PASS
7049 00:24:45.533312 TX OE : NO K
7050 00:24:45.533416 All Pass.
7051 00:24:45.533506
7052 00:24:45.533592 DramC Write-DBI off
7053 00:24:45.536652 PER_BANK_REFRESH: Hybrid Mode
7054 00:24:45.539858 TX_TRACKING: ON
7055 00:24:45.546330 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7056 00:24:45.550187 [FAST_K] Save calibration result to emmc
7057 00:24:45.556417 dramc_set_vcore_voltage set vcore to 725000
7058 00:24:45.556493 Read voltage for 1600, 0
7059 00:24:45.560231 Vio18 = 0
7060 00:24:45.560318 Vcore = 725000
7061 00:24:45.560380 Vdram = 0
7062 00:24:45.560438 Vddq = 0
7063 00:24:45.563591 Vmddr = 0
7064 00:24:45.566519 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7065 00:24:45.573188 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7066 00:24:45.576634 MEM_TYPE=3, freq_sel=13
7067 00:24:45.576706 sv_algorithm_assistance_LP4_3733
7068 00:24:45.582933 ============ PULL DRAM RESETB DOWN ============
7069 00:24:45.586295 ========== PULL DRAM RESETB DOWN end =========
7070 00:24:45.589617 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7071 00:24:45.592886 ===================================
7072 00:24:45.596405 LPDDR4 DRAM CONFIGURATION
7073 00:24:45.599993 ===================================
7074 00:24:45.602831 EX_ROW_EN[0] = 0x0
7075 00:24:45.602901 EX_ROW_EN[1] = 0x0
7076 00:24:45.606220 LP4Y_EN = 0x0
7077 00:24:45.606288 WORK_FSP = 0x1
7078 00:24:45.609684 WL = 0x5
7079 00:24:45.609769 RL = 0x5
7080 00:24:45.612884 BL = 0x2
7081 00:24:45.612961 RPST = 0x0
7082 00:24:45.616455 RD_PRE = 0x0
7083 00:24:45.616527 WR_PRE = 0x1
7084 00:24:45.620070 WR_PST = 0x1
7085 00:24:45.620145 DBI_WR = 0x0
7086 00:24:45.623230 DBI_RD = 0x0
7087 00:24:45.623304 OTF = 0x1
7088 00:24:45.626425 ===================================
7089 00:24:45.629865 ===================================
7090 00:24:45.633063 ANA top config
7091 00:24:45.636809 ===================================
7092 00:24:45.640240 DLL_ASYNC_EN = 0
7093 00:24:45.640316 ALL_SLAVE_EN = 0
7094 00:24:45.643234 NEW_RANK_MODE = 1
7095 00:24:45.646202 DLL_IDLE_MODE = 1
7096 00:24:45.649756 LP45_APHY_COMB_EN = 1
7097 00:24:45.649828 TX_ODT_DIS = 0
7098 00:24:45.653127 NEW_8X_MODE = 1
7099 00:24:45.656378 ===================================
7100 00:24:45.659596 ===================================
7101 00:24:45.663186 data_rate = 3200
7102 00:24:45.666214 CKR = 1
7103 00:24:45.669670 DQ_P2S_RATIO = 8
7104 00:24:45.673024 ===================================
7105 00:24:45.676227 CA_P2S_RATIO = 8
7106 00:24:45.676303 DQ_CA_OPEN = 0
7107 00:24:45.679959 DQ_SEMI_OPEN = 0
7108 00:24:45.683006 CA_SEMI_OPEN = 0
7109 00:24:45.686557 CA_FULL_RATE = 0
7110 00:24:45.689221 DQ_CKDIV4_EN = 0
7111 00:24:45.692946 CA_CKDIV4_EN = 0
7112 00:24:45.693020 CA_PREDIV_EN = 0
7113 00:24:45.696112 PH8_DLY = 12
7114 00:24:45.699546 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7115 00:24:45.702574 DQ_AAMCK_DIV = 4
7116 00:24:45.706085 CA_AAMCK_DIV = 4
7117 00:24:45.709466 CA_ADMCK_DIV = 4
7118 00:24:45.709543 DQ_TRACK_CA_EN = 0
7119 00:24:45.712990 CA_PICK = 1600
7120 00:24:45.715876 CA_MCKIO = 1600
7121 00:24:45.719488 MCKIO_SEMI = 0
7122 00:24:45.722551 PLL_FREQ = 3068
7123 00:24:45.726347 DQ_UI_PI_RATIO = 32
7124 00:24:45.729205 CA_UI_PI_RATIO = 0
7125 00:24:45.732489 ===================================
7126 00:24:45.736232 ===================================
7127 00:24:45.736303 memory_type:LPDDR4
7128 00:24:45.739086 GP_NUM : 10
7129 00:24:45.742985 SRAM_EN : 1
7130 00:24:45.743057 MD32_EN : 0
7131 00:24:45.746130 ===================================
7132 00:24:45.749357 [ANA_INIT] >>>>>>>>>>>>>>
7133 00:24:45.752745 <<<<<< [CONFIGURE PHASE]: ANA_TX
7134 00:24:45.755974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7135 00:24:45.759249 ===================================
7136 00:24:45.762709 data_rate = 3200,PCW = 0X7600
7137 00:24:45.765998 ===================================
7138 00:24:45.769262 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7139 00:24:45.772829 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7140 00:24:45.779183 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7141 00:24:45.782400 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7142 00:24:45.785794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7143 00:24:45.789034 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7144 00:24:45.792207 [ANA_INIT] flow start
7145 00:24:45.795678 [ANA_INIT] PLL >>>>>>>>
7146 00:24:45.795756 [ANA_INIT] PLL <<<<<<<<
7147 00:24:45.799352 [ANA_INIT] MIDPI >>>>>>>>
7148 00:24:45.802605 [ANA_INIT] MIDPI <<<<<<<<
7149 00:24:45.805945 [ANA_INIT] DLL >>>>>>>>
7150 00:24:45.806015 [ANA_INIT] DLL <<<<<<<<
7151 00:24:45.808728 [ANA_INIT] flow end
7152 00:24:45.812160 ============ LP4 DIFF to SE enter ============
7153 00:24:45.815506 ============ LP4 DIFF to SE exit ============
7154 00:24:45.819192 [ANA_INIT] <<<<<<<<<<<<<
7155 00:24:45.822486 [Flow] Enable top DCM control >>>>>
7156 00:24:45.825752 [Flow] Enable top DCM control <<<<<
7157 00:24:45.829163 Enable DLL master slave shuffle
7158 00:24:45.835781 ==============================================================
7159 00:24:45.835857 Gating Mode config
7160 00:24:45.842046 ==============================================================
7161 00:24:45.842127 Config description:
7162 00:24:45.852186 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7163 00:24:45.858896 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7164 00:24:45.865640 SELPH_MODE 0: By rank 1: By Phase
7165 00:24:45.868629 ==============================================================
7166 00:24:45.872223 GAT_TRACK_EN = 1
7167 00:24:45.875116 RX_GATING_MODE = 2
7168 00:24:45.878572 RX_GATING_TRACK_MODE = 2
7169 00:24:45.881881 SELPH_MODE = 1
7170 00:24:45.885142 PICG_EARLY_EN = 1
7171 00:24:45.888792 VALID_LAT_VALUE = 1
7172 00:24:45.895002 ==============================================================
7173 00:24:45.898276 Enter into Gating configuration >>>>
7174 00:24:45.901918 Exit from Gating configuration <<<<
7175 00:24:45.901991 Enter into DVFS_PRE_config >>>>>
7176 00:24:45.914948 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7177 00:24:45.918182 Exit from DVFS_PRE_config <<<<<
7178 00:24:45.921576 Enter into PICG configuration >>>>
7179 00:24:45.924778 Exit from PICG configuration <<<<
7180 00:24:45.924850 [RX_INPUT] configuration >>>>>
7181 00:24:45.928545 [RX_INPUT] configuration <<<<<
7182 00:24:45.935045 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7183 00:24:45.938256 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7184 00:24:45.944672 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7185 00:24:45.951502 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7186 00:24:45.957923 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7187 00:24:45.965219 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7188 00:24:45.968038 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7189 00:24:45.971289 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7190 00:24:45.977828 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7191 00:24:45.981600 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7192 00:24:45.984688 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7193 00:24:45.987798 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7194 00:24:45.991365 ===================================
7195 00:24:45.994544 LPDDR4 DRAM CONFIGURATION
7196 00:24:45.998271 ===================================
7197 00:24:46.001703 EX_ROW_EN[0] = 0x0
7198 00:24:46.001774 EX_ROW_EN[1] = 0x0
7199 00:24:46.004646 LP4Y_EN = 0x0
7200 00:24:46.004718 WORK_FSP = 0x1
7201 00:24:46.007741 WL = 0x5
7202 00:24:46.007812 RL = 0x5
7203 00:24:46.010900 BL = 0x2
7204 00:24:46.010973 RPST = 0x0
7205 00:24:46.014666 RD_PRE = 0x0
7206 00:24:46.017557 WR_PRE = 0x1
7207 00:24:46.017623 WR_PST = 0x1
7208 00:24:46.021009 DBI_WR = 0x0
7209 00:24:46.021078 DBI_RD = 0x0
7210 00:24:46.024220 OTF = 0x1
7211 00:24:46.027699 ===================================
7212 00:24:46.030768 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7213 00:24:46.034177 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7214 00:24:46.037688 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7215 00:24:46.040893 ===================================
7216 00:24:46.044071 LPDDR4 DRAM CONFIGURATION
7217 00:24:46.047520 ===================================
7218 00:24:46.050988 EX_ROW_EN[0] = 0x10
7219 00:24:46.051060 EX_ROW_EN[1] = 0x0
7220 00:24:46.054414 LP4Y_EN = 0x0
7221 00:24:46.054483 WORK_FSP = 0x1
7222 00:24:46.057205 WL = 0x5
7223 00:24:46.057275 RL = 0x5
7224 00:24:46.060677 BL = 0x2
7225 00:24:46.060772 RPST = 0x0
7226 00:24:46.064180 RD_PRE = 0x0
7227 00:24:46.064249 WR_PRE = 0x1
7228 00:24:46.067680 WR_PST = 0x1
7229 00:24:46.070656 DBI_WR = 0x0
7230 00:24:46.070723 DBI_RD = 0x0
7231 00:24:46.073983 OTF = 0x1
7232 00:24:46.077153 ===================================
7233 00:24:46.080615 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7234 00:24:46.083966 ==
7235 00:24:46.084047 Dram Type= 6, Freq= 0, CH_0, rank 0
7236 00:24:46.090467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7237 00:24:46.090548 ==
7238 00:24:46.093942 [Duty_Offset_Calibration]
7239 00:24:46.094043 B0:2 B1:0 CA:3
7240 00:24:46.094135
7241 00:24:46.097170 [DutyScan_Calibration_Flow] k_type=0
7242 00:24:46.106890
7243 00:24:46.106997 ==CLK 0==
7244 00:24:46.110358 Final CLK duty delay cell = 0
7245 00:24:46.113420 [0] MAX Duty = 5031%(X100), DQS PI = 12
7246 00:24:46.117115 [0] MIN Duty = 4875%(X100), DQS PI = 54
7247 00:24:46.117203 [0] AVG Duty = 4953%(X100)
7248 00:24:46.120197
7249 00:24:46.123602 CH0 CLK Duty spec in!! Max-Min= 156%
7250 00:24:46.127160 [DutyScan_Calibration_Flow] ====Done====
7251 00:24:46.127265
7252 00:24:46.130053 [DutyScan_Calibration_Flow] k_type=1
7253 00:24:46.146982
7254 00:24:46.147092 ==DQS 0 ==
7255 00:24:46.150184 Final DQS duty delay cell = 0
7256 00:24:46.153434 [0] MAX Duty = 5125%(X100), DQS PI = 30
7257 00:24:46.156977 [0] MIN Duty = 4906%(X100), DQS PI = 46
7258 00:24:46.160423 [0] AVG Duty = 5015%(X100)
7259 00:24:46.160497
7260 00:24:46.160577 ==DQS 1 ==
7261 00:24:46.163511 Final DQS duty delay cell = 0
7262 00:24:46.166730 [0] MAX Duty = 5156%(X100), DQS PI = 30
7263 00:24:46.170293 [0] MIN Duty = 5031%(X100), DQS PI = 14
7264 00:24:46.173705 [0] AVG Duty = 5093%(X100)
7265 00:24:46.173779
7266 00:24:46.176695 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7267 00:24:46.176766
7268 00:24:46.180263 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7269 00:24:46.184101 [DutyScan_Calibration_Flow] ====Done====
7270 00:24:46.184173
7271 00:24:46.186889 [DutyScan_Calibration_Flow] k_type=3
7272 00:24:46.204958
7273 00:24:46.205073 ==DQM 0 ==
7274 00:24:46.208958 Final DQM duty delay cell = 0
7275 00:24:46.211792 [0] MAX Duty = 5187%(X100), DQS PI = 30
7276 00:24:46.215193 [0] MIN Duty = 4875%(X100), DQS PI = 0
7277 00:24:46.215291 [0] AVG Duty = 5031%(X100)
7278 00:24:46.218120
7279 00:24:46.218220 ==DQM 1 ==
7280 00:24:46.221522 Final DQM duty delay cell = 4
7281 00:24:46.224746 [4] MAX Duty = 5187%(X100), DQS PI = 0
7282 00:24:46.228401 [4] MIN Duty = 5031%(X100), DQS PI = 22
7283 00:24:46.228499 [4] AVG Duty = 5109%(X100)
7284 00:24:46.231934
7285 00:24:46.234976 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7286 00:24:46.235045
7287 00:24:46.238641 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7288 00:24:46.241950 [DutyScan_Calibration_Flow] ====Done====
7289 00:24:46.242021
7290 00:24:46.244699 [DutyScan_Calibration_Flow] k_type=2
7291 00:24:46.261455
7292 00:24:46.261536 ==DQ 0 ==
7293 00:24:46.264933 Final DQ duty delay cell = -4
7294 00:24:46.267895 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7295 00:24:46.271264 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7296 00:24:46.274635 [-4] AVG Duty = 4938%(X100)
7297 00:24:46.274713
7298 00:24:46.274773 ==DQ 1 ==
7299 00:24:46.278247 Final DQ duty delay cell = 0
7300 00:24:46.281800 [0] MAX Duty = 5156%(X100), DQS PI = 58
7301 00:24:46.284469 [0] MIN Duty = 5000%(X100), DQS PI = 16
7302 00:24:46.287963 [0] AVG Duty = 5078%(X100)
7303 00:24:46.288035
7304 00:24:46.291243 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7305 00:24:46.291338
7306 00:24:46.294869 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7307 00:24:46.297859 [DutyScan_Calibration_Flow] ====Done====
7308 00:24:46.297931 ==
7309 00:24:46.301396 Dram Type= 6, Freq= 0, CH_1, rank 0
7310 00:24:46.304286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7311 00:24:46.304387 ==
7312 00:24:46.307673 [Duty_Offset_Calibration]
7313 00:24:46.307773 B0:1 B1:-2 CA:0
7314 00:24:46.307860
7315 00:24:46.310981 [DutyScan_Calibration_Flow] k_type=0
7316 00:24:46.321662
7317 00:24:46.321743 ==CLK 0==
7318 00:24:46.325352 Final CLK duty delay cell = 0
7319 00:24:46.328722 [0] MAX Duty = 5062%(X100), DQS PI = 20
7320 00:24:46.331843 [0] MIN Duty = 4813%(X100), DQS PI = 60
7321 00:24:46.331914 [0] AVG Duty = 4937%(X100)
7322 00:24:46.335046
7323 00:24:46.338620 CH1 CLK Duty spec in!! Max-Min= 249%
7324 00:24:46.341759 [DutyScan_Calibration_Flow] ====Done====
7325 00:24:46.341831
7326 00:24:46.344835 [DutyScan_Calibration_Flow] k_type=1
7327 00:24:46.361579
7328 00:24:46.361685 ==DQS 0 ==
7329 00:24:46.365211 Final DQS duty delay cell = 0
7330 00:24:46.368348 [0] MAX Duty = 5187%(X100), DQS PI = 22
7331 00:24:46.371480 [0] MIN Duty = 5062%(X100), DQS PI = 52
7332 00:24:46.374952 [0] AVG Duty = 5124%(X100)
7333 00:24:46.375022
7334 00:24:46.375092 ==DQS 1 ==
7335 00:24:46.378387 Final DQS duty delay cell = 0
7336 00:24:46.381506 [0] MAX Duty = 5093%(X100), DQS PI = 0
7337 00:24:46.384950 [0] MIN Duty = 4844%(X100), DQS PI = 24
7338 00:24:46.385021 [0] AVG Duty = 4968%(X100)
7339 00:24:46.388230
7340 00:24:46.391674 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7341 00:24:46.391744
7342 00:24:46.395247 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7343 00:24:46.398170 [DutyScan_Calibration_Flow] ====Done====
7344 00:24:46.398238
7345 00:24:46.401830 [DutyScan_Calibration_Flow] k_type=3
7346 00:24:46.418699
7347 00:24:46.418778 ==DQM 0 ==
7348 00:24:46.421993 Final DQM duty delay cell = 0
7349 00:24:46.424857 [0] MAX Duty = 5031%(X100), DQS PI = 22
7350 00:24:46.428359 [0] MIN Duty = 4813%(X100), DQS PI = 56
7351 00:24:46.431847 [0] AVG Duty = 4922%(X100)
7352 00:24:46.431922
7353 00:24:46.431983 ==DQM 1 ==
7354 00:24:46.435012 Final DQM duty delay cell = 0
7355 00:24:46.438180 [0] MAX Duty = 5062%(X100), DQS PI = 34
7356 00:24:46.441444 [0] MIN Duty = 4875%(X100), DQS PI = 24
7357 00:24:46.445014 [0] AVG Duty = 4968%(X100)
7358 00:24:46.445091
7359 00:24:46.448445 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7360 00:24:46.448551
7361 00:24:46.451691 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7362 00:24:46.454948 [DutyScan_Calibration_Flow] ====Done====
7363 00:24:46.455021
7364 00:24:46.458516 [DutyScan_Calibration_Flow] k_type=2
7365 00:24:46.475277
7366 00:24:46.475357 ==DQ 0 ==
7367 00:24:46.478873 Final DQ duty delay cell = 0
7368 00:24:46.481953 [0] MAX Duty = 5093%(X100), DQS PI = 22
7369 00:24:46.485675 [0] MIN Duty = 4938%(X100), DQS PI = 0
7370 00:24:46.485754 [0] AVG Duty = 5015%(X100)
7371 00:24:46.488664
7372 00:24:46.488743 ==DQ 1 ==
7373 00:24:46.492187 Final DQ duty delay cell = 0
7374 00:24:46.495563 [0] MAX Duty = 5156%(X100), DQS PI = 36
7375 00:24:46.498563 [0] MIN Duty = 4969%(X100), DQS PI = 24
7376 00:24:46.498642 [0] AVG Duty = 5062%(X100)
7377 00:24:46.498705
7378 00:24:46.501996 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7379 00:24:46.505253
7380 00:24:46.508398 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7381 00:24:46.512214 [DutyScan_Calibration_Flow] ====Done====
7382 00:24:46.515864 nWR fixed to 30
7383 00:24:46.515945 [ModeRegInit_LP4] CH0 RK0
7384 00:24:46.518503 [ModeRegInit_LP4] CH0 RK1
7385 00:24:46.521939 [ModeRegInit_LP4] CH1 RK0
7386 00:24:46.525183 [ModeRegInit_LP4] CH1 RK1
7387 00:24:46.525265 match AC timing 5
7388 00:24:46.528292 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7389 00:24:46.535076 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7390 00:24:46.538277 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7391 00:24:46.545336 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7392 00:24:46.548802 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7393 00:24:46.548879 [MiockJmeterHQA]
7394 00:24:46.548962
7395 00:24:46.551467 [DramcMiockJmeter] u1RxGatingPI = 0
7396 00:24:46.555451 0 : 4253, 4026
7397 00:24:46.555531 4 : 4363, 4138
7398 00:24:46.555610 8 : 4252, 4027
7399 00:24:46.558734 12 : 4363, 4138
7400 00:24:46.558827 16 : 4363, 4137
7401 00:24:46.561810 20 : 4252, 4027
7402 00:24:46.561904 24 : 4252, 4027
7403 00:24:46.564815 28 : 4253, 4026
7404 00:24:46.564891 32 : 4363, 4137
7405 00:24:46.568078 36 : 4253, 4027
7406 00:24:46.568158 40 : 4360, 4138
7407 00:24:46.568239 44 : 4249, 4027
7408 00:24:46.571718 48 : 4250, 4027
7409 00:24:46.571796 52 : 4249, 4027
7410 00:24:46.574786 56 : 4250, 4026
7411 00:24:46.574860 60 : 4360, 4138
7412 00:24:46.578267 64 : 4250, 4026
7413 00:24:46.578337 68 : 4361, 4137
7414 00:24:46.581438 72 : 4250, 4027
7415 00:24:46.581517 76 : 4250, 4027
7416 00:24:46.581596 80 : 4250, 4027
7417 00:24:46.584783 84 : 4360, 4137
7418 00:24:46.584862 88 : 4250, 4027
7419 00:24:46.588201 92 : 4360, 4138
7420 00:24:46.588273 96 : 4249, 4027
7421 00:24:46.591699 100 : 4250, 4027
7422 00:24:46.591772 104 : 4360, 3995
7423 00:24:46.594705 108 : 4361, 5
7424 00:24:46.594777 112 : 4249, 0
7425 00:24:46.594873 116 : 4250, 0
7426 00:24:46.598205 120 : 4360, 0
7427 00:24:46.598281 124 : 4360, 0
7428 00:24:46.598358 128 : 4361, 0
7429 00:24:46.601537 132 : 4249, 0
7430 00:24:46.601606 136 : 4250, 0
7431 00:24:46.604487 140 : 4250, 0
7432 00:24:46.604557 144 : 4250, 0
7433 00:24:46.604637 148 : 4250, 0
7434 00:24:46.608037 152 : 4250, 0
7435 00:24:46.608116 156 : 4250, 0
7436 00:24:46.611505 160 : 4361, 0
7437 00:24:46.611584 164 : 4250, 0
7438 00:24:46.611664 168 : 4250, 0
7439 00:24:46.614448 172 : 4249, 0
7440 00:24:46.614524 176 : 4361, 0
7441 00:24:46.618007 180 : 4361, 0
7442 00:24:46.618078 184 : 4250, 0
7443 00:24:46.618156 188 : 4252, 0
7444 00:24:46.621507 192 : 4249, 0
7445 00:24:46.621607 196 : 4250, 0
7446 00:24:46.621708 200 : 4250, 0
7447 00:24:46.624574 204 : 4250, 0
7448 00:24:46.624654 208 : 4250, 0
7449 00:24:46.627962 212 : 4361, 0
7450 00:24:46.628067 216 : 4249, 0
7451 00:24:46.628148 220 : 4250, 0
7452 00:24:46.631252 224 : 4250, 0
7453 00:24:46.631363 228 : 4363, 0
7454 00:24:46.634418 232 : 4361, 0
7455 00:24:46.634500 236 : 4249, 906
7456 00:24:46.637982 240 : 4250, 4027
7457 00:24:46.638064 244 : 4360, 4138
7458 00:24:46.638129 248 : 4360, 4137
7459 00:24:46.641507 252 : 4248, 4024
7460 00:24:46.641587 256 : 4361, 4137
7461 00:24:46.644856 260 : 4360, 4138
7462 00:24:46.644938 264 : 4250, 4027
7463 00:24:46.647960 268 : 4250, 4026
7464 00:24:46.648041 272 : 4250, 4027
7465 00:24:46.651072 276 : 4250, 4027
7466 00:24:46.651153 280 : 4249, 4027
7467 00:24:46.654654 284 : 4250, 4026
7468 00:24:46.654735 288 : 4250, 4026
7469 00:24:46.657827 292 : 4250, 4027
7470 00:24:46.657908 296 : 4360, 4138
7471 00:24:46.661388 300 : 4360, 4137
7472 00:24:46.661469 304 : 4248, 4024
7473 00:24:46.661547 308 : 4361, 4137
7474 00:24:46.664727 312 : 4360, 4138
7475 00:24:46.664809 316 : 4250, 4027
7476 00:24:46.668093 320 : 4249, 4027
7477 00:24:46.668175 324 : 4250, 4027
7478 00:24:46.671197 328 : 4250, 4027
7479 00:24:46.671278 332 : 4250, 4027
7480 00:24:46.674808 336 : 4250, 4026
7481 00:24:46.674890 340 : 4250, 4027
7482 00:24:46.677813 344 : 4250, 4027
7483 00:24:46.677894 348 : 4360, 4138
7484 00:24:46.681422 352 : 4361, 4137
7485 00:24:46.681504 356 : 4248, 2951
7486 00:24:46.681587 360 : 4361, 5
7487 00:24:46.681662
7488 00:24:46.684591 MIOCK jitter meter ch=0
7489 00:24:46.684671
7490 00:24:46.687801 1T = (360-108) = 252 dly cells
7491 00:24:46.694759 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7492 00:24:46.694840 ==
7493 00:24:46.697867 Dram Type= 6, Freq= 0, CH_0, rank 0
7494 00:24:46.701057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7495 00:24:46.701138 ==
7496 00:24:46.708070 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7497 00:24:46.711086 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7498 00:24:46.714373 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7499 00:24:46.721632 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7500 00:24:46.730702 [CA 0] Center 44 (14~75) winsize 62
7501 00:24:46.733554 [CA 1] Center 43 (13~74) winsize 62
7502 00:24:46.737108 [CA 2] Center 39 (10~69) winsize 60
7503 00:24:46.740218 [CA 3] Center 39 (10~68) winsize 59
7504 00:24:46.743171 [CA 4] Center 37 (8~67) winsize 60
7505 00:24:46.746878 [CA 5] Center 37 (7~67) winsize 61
7506 00:24:46.746988
7507 00:24:46.749862 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7508 00:24:46.749960
7509 00:24:46.756625 [CATrainingPosCal] consider 1 rank data
7510 00:24:46.756737 u2DelayCellTimex100 = 258/100 ps
7511 00:24:46.763491 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7512 00:24:46.766602 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7513 00:24:46.769979 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7514 00:24:46.773578 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7515 00:24:46.776698 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7516 00:24:46.779899 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7517 00:24:46.779976
7518 00:24:46.783072 CA PerBit enable=1, Macro0, CA PI delay=37
7519 00:24:46.783169
7520 00:24:46.786254 [CBTSetCACLKResult] CA Dly = 37
7521 00:24:46.789581 CS Dly: 11 (0~42)
7522 00:24:46.792769 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7523 00:24:46.796323 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7524 00:24:46.796400 ==
7525 00:24:46.799705 Dram Type= 6, Freq= 0, CH_0, rank 1
7526 00:24:46.806284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 00:24:46.806424 ==
7528 00:24:46.810017 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7529 00:24:46.816503 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7530 00:24:46.819999 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7531 00:24:46.826241 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7532 00:24:46.834262 [CA 0] Center 44 (13~75) winsize 63
7533 00:24:46.837172 [CA 1] Center 43 (13~74) winsize 62
7534 00:24:46.840556 [CA 2] Center 39 (10~69) winsize 60
7535 00:24:46.843767 [CA 3] Center 39 (10~68) winsize 59
7536 00:24:46.847534 [CA 4] Center 37 (8~66) winsize 59
7537 00:24:46.850359 [CA 5] Center 37 (8~66) winsize 59
7538 00:24:46.850439
7539 00:24:46.853889 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7540 00:24:46.853968
7541 00:24:46.860938 [CATrainingPosCal] consider 2 rank data
7542 00:24:46.861018 u2DelayCellTimex100 = 258/100 ps
7543 00:24:46.867333 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7544 00:24:46.870673 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7545 00:24:46.874031 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7546 00:24:46.877271 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7547 00:24:46.880589 CA4 delay=37 (8~66),Diff = 0 PI (0 cell)
7548 00:24:46.884072 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7549 00:24:46.884171
7550 00:24:46.886974 CA PerBit enable=1, Macro0, CA PI delay=37
7551 00:24:46.887054
7552 00:24:46.890649 [CBTSetCACLKResult] CA Dly = 37
7553 00:24:46.894012 CS Dly: 11 (0~42)
7554 00:24:46.896772 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7555 00:24:46.900083 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7556 00:24:46.900163
7557 00:24:46.903545 ----->DramcWriteLeveling(PI) begin...
7558 00:24:46.903672 ==
7559 00:24:46.907299 Dram Type= 6, Freq= 0, CH_0, rank 0
7560 00:24:46.913519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 00:24:46.913601 ==
7562 00:24:46.916856 Write leveling (Byte 0): 34 => 34
7563 00:24:46.920241 Write leveling (Byte 1): 27 => 27
7564 00:24:46.920316 DramcWriteLeveling(PI) end<-----
7565 00:24:46.920410
7566 00:24:46.923344 ==
7567 00:24:46.926876 Dram Type= 6, Freq= 0, CH_0, rank 0
7568 00:24:46.930358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 00:24:46.930439 ==
7570 00:24:46.933228 [Gating] SW mode calibration
7571 00:24:46.940357 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7572 00:24:46.943230 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7573 00:24:46.949888 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 00:24:46.953082 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 00:24:46.956298 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 00:24:46.962903 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 00:24:46.966434 1 4 16 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
7578 00:24:46.969636 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7579 00:24:46.976310 1 4 24 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7580 00:24:46.979947 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7581 00:24:46.982824 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7582 00:24:46.989598 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7583 00:24:46.992503 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7584 00:24:46.996032 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7585 00:24:47.002733 1 5 16 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 0)
7586 00:24:47.006167 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7587 00:24:47.009218 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
7588 00:24:47.016087 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 00:24:47.019336 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 00:24:47.022380 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 00:24:47.028984 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 00:24:47.032547 1 6 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
7593 00:24:47.035711 1 6 16 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7594 00:24:47.042161 1 6 20 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7595 00:24:47.045635 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
7596 00:24:47.049277 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 00:24:47.055665 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 00:24:47.058995 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 00:24:47.062081 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 00:24:47.068708 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 00:24:47.072380 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7602 00:24:47.075625 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7603 00:24:47.082000 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7604 00:24:47.085150 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7605 00:24:47.088567 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 00:24:47.095288 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 00:24:47.098745 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 00:24:47.102329 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 00:24:47.108341 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 00:24:47.111806 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 00:24:47.115171 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 00:24:47.121925 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 00:24:47.125518 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 00:24:47.128799 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 00:24:47.134967 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 00:24:47.138674 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7617 00:24:47.141794 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7618 00:24:47.144878 Total UI for P1: 0, mck2ui 16
7619 00:24:47.148254 best dqsien dly found for B0: ( 1, 9, 12)
7620 00:24:47.152131 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7621 00:24:47.158660 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7622 00:24:47.161614 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 00:24:47.165046 Total UI for P1: 0, mck2ui 16
7624 00:24:47.168314 best dqsien dly found for B1: ( 1, 9, 24)
7625 00:24:47.171830 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7626 00:24:47.175005 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7627 00:24:47.175085
7628 00:24:47.177965 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7629 00:24:47.185146 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7630 00:24:47.185222 [Gating] SW calibration Done
7631 00:24:47.185285 ==
7632 00:24:47.188620 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 00:24:47.194688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 00:24:47.194821 ==
7635 00:24:47.194922 RX Vref Scan: 0
7636 00:24:47.195011
7637 00:24:47.198445 RX Vref 0 -> 0, step: 1
7638 00:24:47.198557
7639 00:24:47.201540 RX Delay 0 -> 252, step: 8
7640 00:24:47.204587 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7641 00:24:47.208252 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7642 00:24:47.211214 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7643 00:24:47.218061 iDelay=200, Bit 3, Center 119 (64 ~ 175) 112
7644 00:24:47.221136 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7645 00:24:47.224687 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7646 00:24:47.228187 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7647 00:24:47.231219 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7648 00:24:47.237885 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7649 00:24:47.241111 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7650 00:24:47.244689 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7651 00:24:47.247919 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7652 00:24:47.251242 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7653 00:24:47.257488 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7654 00:24:47.260966 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7655 00:24:47.264862 iDelay=200, Bit 15, Center 127 (72 ~ 183) 112
7656 00:24:47.264971 ==
7657 00:24:47.267460 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 00:24:47.271046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 00:24:47.271143 ==
7660 00:24:47.274424 DQS Delay:
7661 00:24:47.274506 DQS0 = 0, DQS1 = 0
7662 00:24:47.277604 DQM Delay:
7663 00:24:47.277684 DQM0 = 128, DQM1 = 123
7664 00:24:47.280818 DQ Delay:
7665 00:24:47.284167 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7666 00:24:47.287588 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =143
7667 00:24:47.291092 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7668 00:24:47.294211 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =127
7669 00:24:47.294291
7670 00:24:47.294354
7671 00:24:47.294413 ==
7672 00:24:47.297510 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 00:24:47.301105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 00:24:47.301186 ==
7675 00:24:47.301297
7676 00:24:47.301358
7677 00:24:47.303857 TX Vref Scan disable
7678 00:24:47.307851 == TX Byte 0 ==
7679 00:24:47.310901 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7680 00:24:47.314111 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7681 00:24:47.317283 == TX Byte 1 ==
7682 00:24:47.320734 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7683 00:24:47.323892 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7684 00:24:47.323973 ==
7685 00:24:47.327354 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 00:24:47.334127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 00:24:47.334208 ==
7688 00:24:47.346139
7689 00:24:47.349893 TX Vref early break, caculate TX vref
7690 00:24:47.353496 TX Vref=16, minBit 9, minWin=21, winSum=353
7691 00:24:47.356093 TX Vref=18, minBit 8, minWin=21, winSum=363
7692 00:24:47.359940 TX Vref=20, minBit 0, minWin=22, winSum=371
7693 00:24:47.362722 TX Vref=22, minBit 8, minWin=23, winSum=382
7694 00:24:47.366529 TX Vref=24, minBit 8, minWin=24, winSum=397
7695 00:24:47.372414 TX Vref=26, minBit 4, minWin=24, winSum=401
7696 00:24:47.375971 TX Vref=28, minBit 8, minWin=24, winSum=403
7697 00:24:47.379525 TX Vref=30, minBit 8, minWin=23, winSum=394
7698 00:24:47.382607 TX Vref=32, minBit 8, minWin=22, winSum=385
7699 00:24:47.386021 TX Vref=34, minBit 8, minWin=21, winSum=374
7700 00:24:47.392434 [TxChooseVref] Worse bit 8, Min win 24, Win sum 403, Final Vref 28
7701 00:24:47.392516
7702 00:24:47.395879 Final TX Range 0 Vref 28
7703 00:24:47.395960
7704 00:24:47.396023 ==
7705 00:24:47.399367 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 00:24:47.402334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 00:24:47.402414 ==
7708 00:24:47.402477
7709 00:24:47.402535
7710 00:24:47.405822 TX Vref Scan disable
7711 00:24:47.412304 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7712 00:24:47.412385 == TX Byte 0 ==
7713 00:24:47.416033 u2DelayCellOfst[0]=15 cells (4 PI)
7714 00:24:47.418898 u2DelayCellOfst[1]=18 cells (5 PI)
7715 00:24:47.422468 u2DelayCellOfst[2]=11 cells (3 PI)
7716 00:24:47.425577 u2DelayCellOfst[3]=15 cells (4 PI)
7717 00:24:47.429363 u2DelayCellOfst[4]=11 cells (3 PI)
7718 00:24:47.432437 u2DelayCellOfst[5]=0 cells (0 PI)
7719 00:24:47.435690 u2DelayCellOfst[6]=22 cells (6 PI)
7720 00:24:47.439194 u2DelayCellOfst[7]=22 cells (6 PI)
7721 00:24:47.442231 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7722 00:24:47.445703 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7723 00:24:47.448677 == TX Byte 1 ==
7724 00:24:47.452214 u2DelayCellOfst[8]=0 cells (0 PI)
7725 00:24:47.452294 u2DelayCellOfst[9]=3 cells (1 PI)
7726 00:24:47.455676 u2DelayCellOfst[10]=11 cells (3 PI)
7727 00:24:47.458928 u2DelayCellOfst[11]=7 cells (2 PI)
7728 00:24:47.462365 u2DelayCellOfst[12]=15 cells (4 PI)
7729 00:24:47.465734 u2DelayCellOfst[13]=15 cells (4 PI)
7730 00:24:47.468902 u2DelayCellOfst[14]=18 cells (5 PI)
7731 00:24:47.472443 u2DelayCellOfst[15]=15 cells (4 PI)
7732 00:24:47.475353 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7733 00:24:47.482094 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7734 00:24:47.482175 DramC Write-DBI on
7735 00:24:47.482239 ==
7736 00:24:47.485609 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 00:24:47.489093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 00:24:47.492130 ==
7739 00:24:47.492210
7740 00:24:47.492273
7741 00:24:47.492332 TX Vref Scan disable
7742 00:24:47.495640 == TX Byte 0 ==
7743 00:24:47.499259 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7744 00:24:47.502361 == TX Byte 1 ==
7745 00:24:47.505868 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7746 00:24:47.509462 DramC Write-DBI off
7747 00:24:47.509542
7748 00:24:47.509606 [DATLAT]
7749 00:24:47.509664 Freq=1600, CH0 RK0
7750 00:24:47.509721
7751 00:24:47.512676 DATLAT Default: 0xf
7752 00:24:47.512803 0, 0xFFFF, sum = 0
7753 00:24:47.516236 1, 0xFFFF, sum = 0
7754 00:24:47.516318 2, 0xFFFF, sum = 0
7755 00:24:47.519012 3, 0xFFFF, sum = 0
7756 00:24:47.522326 4, 0xFFFF, sum = 0
7757 00:24:47.522423 5, 0xFFFF, sum = 0
7758 00:24:47.526098 6, 0xFFFF, sum = 0
7759 00:24:47.526180 7, 0xFFFF, sum = 0
7760 00:24:47.529095 8, 0xFFFF, sum = 0
7761 00:24:47.529176 9, 0xFFFF, sum = 0
7762 00:24:47.532619 10, 0xFFFF, sum = 0
7763 00:24:47.532700 11, 0xFFFF, sum = 0
7764 00:24:47.535749 12, 0xFFFF, sum = 0
7765 00:24:47.535831 13, 0xEFFF, sum = 0
7766 00:24:47.538979 14, 0x0, sum = 1
7767 00:24:47.539060 15, 0x0, sum = 2
7768 00:24:47.542611 16, 0x0, sum = 3
7769 00:24:47.542692 17, 0x0, sum = 4
7770 00:24:47.545775 best_step = 15
7771 00:24:47.545855
7772 00:24:47.545919 ==
7773 00:24:47.549227 Dram Type= 6, Freq= 0, CH_0, rank 0
7774 00:24:47.552841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7775 00:24:47.552922 ==
7776 00:24:47.552986 RX Vref Scan: 1
7777 00:24:47.555700
7778 00:24:47.555779 Set Vref Range= 24 -> 127
7779 00:24:47.555864
7780 00:24:47.559198 RX Vref 24 -> 127, step: 1
7781 00:24:47.559278
7782 00:24:47.562525 RX Delay 11 -> 252, step: 4
7783 00:24:47.562605
7784 00:24:47.565427 Set Vref, RX VrefLevel [Byte0]: 24
7785 00:24:47.568993 [Byte1]: 24
7786 00:24:47.569087
7787 00:24:47.572266 Set Vref, RX VrefLevel [Byte0]: 25
7788 00:24:47.575593 [Byte1]: 25
7789 00:24:47.579298
7790 00:24:47.579388 Set Vref, RX VrefLevel [Byte0]: 26
7791 00:24:47.582574 [Byte1]: 26
7792 00:24:47.586211
7793 00:24:47.586304 Set Vref, RX VrefLevel [Byte0]: 27
7794 00:24:47.589328 [Byte1]: 27
7795 00:24:47.593757
7796 00:24:47.593841 Set Vref, RX VrefLevel [Byte0]: 28
7797 00:24:47.597129 [Byte1]: 28
7798 00:24:47.601578
7799 00:24:47.601658 Set Vref, RX VrefLevel [Byte0]: 29
7800 00:24:47.604809 [Byte1]: 29
7801 00:24:47.608966
7802 00:24:47.609071 Set Vref, RX VrefLevel [Byte0]: 30
7803 00:24:47.612389 [Byte1]: 30
7804 00:24:47.616913
7805 00:24:47.617010 Set Vref, RX VrefLevel [Byte0]: 31
7806 00:24:47.619861 [Byte1]: 31
7807 00:24:47.624395
7808 00:24:47.624503 Set Vref, RX VrefLevel [Byte0]: 32
7809 00:24:47.627440 [Byte1]: 32
7810 00:24:47.632160
7811 00:24:47.632240 Set Vref, RX VrefLevel [Byte0]: 33
7812 00:24:47.635066 [Byte1]: 33
7813 00:24:47.639643
7814 00:24:47.639747 Set Vref, RX VrefLevel [Byte0]: 34
7815 00:24:47.643352 [Byte1]: 34
7816 00:24:47.646962
7817 00:24:47.647103 Set Vref, RX VrefLevel [Byte0]: 35
7818 00:24:47.650614 [Byte1]: 35
7819 00:24:47.655028
7820 00:24:47.655140 Set Vref, RX VrefLevel [Byte0]: 36
7821 00:24:47.657877 [Byte1]: 36
7822 00:24:47.662660
7823 00:24:47.662815 Set Vref, RX VrefLevel [Byte0]: 37
7824 00:24:47.665903 [Byte1]: 37
7825 00:24:47.669809
7826 00:24:47.669975 Set Vref, RX VrefLevel [Byte0]: 38
7827 00:24:47.673123 [Byte1]: 38
7828 00:24:47.677696
7829 00:24:47.677775 Set Vref, RX VrefLevel [Byte0]: 39
7830 00:24:47.681002 [Byte1]: 39
7831 00:24:47.685203
7832 00:24:47.685283 Set Vref, RX VrefLevel [Byte0]: 40
7833 00:24:47.689013 [Byte1]: 40
7834 00:24:47.693021
7835 00:24:47.693100 Set Vref, RX VrefLevel [Byte0]: 41
7836 00:24:47.696003 [Byte1]: 41
7837 00:24:47.700321
7838 00:24:47.700401 Set Vref, RX VrefLevel [Byte0]: 42
7839 00:24:47.703618 [Byte1]: 42
7840 00:24:47.708083
7841 00:24:47.708178 Set Vref, RX VrefLevel [Byte0]: 43
7842 00:24:47.711473 [Byte1]: 43
7843 00:24:47.715675
7844 00:24:47.715782 Set Vref, RX VrefLevel [Byte0]: 44
7845 00:24:47.718906 [Byte1]: 44
7846 00:24:47.723608
7847 00:24:47.723688 Set Vref, RX VrefLevel [Byte0]: 45
7848 00:24:47.726368 [Byte1]: 45
7849 00:24:47.730894
7850 00:24:47.730974 Set Vref, RX VrefLevel [Byte0]: 46
7851 00:24:47.734410 [Byte1]: 46
7852 00:24:47.738408
7853 00:24:47.738488 Set Vref, RX VrefLevel [Byte0]: 47
7854 00:24:47.741812 [Byte1]: 47
7855 00:24:47.746583
7856 00:24:47.746664 Set Vref, RX VrefLevel [Byte0]: 48
7857 00:24:47.749297 [Byte1]: 48
7858 00:24:47.753621
7859 00:24:47.753703 Set Vref, RX VrefLevel [Byte0]: 49
7860 00:24:47.756925 [Byte1]: 49
7861 00:24:47.761141
7862 00:24:47.761223 Set Vref, RX VrefLevel [Byte0]: 50
7863 00:24:47.764483 [Byte1]: 50
7864 00:24:47.769150
7865 00:24:47.769231 Set Vref, RX VrefLevel [Byte0]: 51
7866 00:24:47.772567 [Byte1]: 51
7867 00:24:47.776642
7868 00:24:47.776723 Set Vref, RX VrefLevel [Byte0]: 52
7869 00:24:47.779600 [Byte1]: 52
7870 00:24:47.784790
7871 00:24:47.784872 Set Vref, RX VrefLevel [Byte0]: 53
7872 00:24:47.787678 [Byte1]: 53
7873 00:24:47.791905
7874 00:24:47.791986 Set Vref, RX VrefLevel [Byte0]: 54
7875 00:24:47.795217 [Byte1]: 54
7876 00:24:47.799262
7877 00:24:47.799344 Set Vref, RX VrefLevel [Byte0]: 55
7878 00:24:47.802744 [Byte1]: 55
7879 00:24:47.806774
7880 00:24:47.806855 Set Vref, RX VrefLevel [Byte0]: 56
7881 00:24:47.810389 [Byte1]: 56
7882 00:24:47.814363
7883 00:24:47.814446 Set Vref, RX VrefLevel [Byte0]: 57
7884 00:24:47.817844 [Byte1]: 57
7885 00:24:47.822019
7886 00:24:47.822100 Set Vref, RX VrefLevel [Byte0]: 58
7887 00:24:47.825755 [Byte1]: 58
7888 00:24:47.830081
7889 00:24:47.830163 Set Vref, RX VrefLevel [Byte0]: 59
7890 00:24:47.832919 [Byte1]: 59
7891 00:24:47.837401
7892 00:24:47.837483 Set Vref, RX VrefLevel [Byte0]: 60
7893 00:24:47.840983 [Byte1]: 60
7894 00:24:47.845035
7895 00:24:47.845115 Set Vref, RX VrefLevel [Byte0]: 61
7896 00:24:47.848481 [Byte1]: 61
7897 00:24:47.852709
7898 00:24:47.852789 Set Vref, RX VrefLevel [Byte0]: 62
7899 00:24:47.855954 [Byte1]: 62
7900 00:24:47.860006
7901 00:24:47.860087 Set Vref, RX VrefLevel [Byte0]: 63
7902 00:24:47.863599 [Byte1]: 63
7903 00:24:47.867862
7904 00:24:47.867942 Set Vref, RX VrefLevel [Byte0]: 64
7905 00:24:47.871010 [Byte1]: 64
7906 00:24:47.875628
7907 00:24:47.875707 Set Vref, RX VrefLevel [Byte0]: 65
7908 00:24:47.879058 [Byte1]: 65
7909 00:24:47.883173
7910 00:24:47.883253 Set Vref, RX VrefLevel [Byte0]: 66
7911 00:24:47.886417 [Byte1]: 66
7912 00:24:47.890970
7913 00:24:47.891050 Set Vref, RX VrefLevel [Byte0]: 67
7914 00:24:47.894280 [Byte1]: 67
7915 00:24:47.898131
7916 00:24:47.898267 Set Vref, RX VrefLevel [Byte0]: 68
7917 00:24:47.901437 [Byte1]: 68
7918 00:24:47.906119
7919 00:24:47.906198 Set Vref, RX VrefLevel [Byte0]: 69
7920 00:24:47.909030 [Byte1]: 69
7921 00:24:47.913632
7922 00:24:47.913746 Set Vref, RX VrefLevel [Byte0]: 70
7923 00:24:47.917094 [Byte1]: 70
7924 00:24:47.921276
7925 00:24:47.921356 Set Vref, RX VrefLevel [Byte0]: 71
7926 00:24:47.924754 [Byte1]: 71
7927 00:24:47.928761
7928 00:24:47.928841 Set Vref, RX VrefLevel [Byte0]: 72
7929 00:24:47.932271 [Byte1]: 72
7930 00:24:47.936861
7931 00:24:47.936941 Set Vref, RX VrefLevel [Byte0]: 73
7932 00:24:47.939827 [Byte1]: 73
7933 00:24:47.944262
7934 00:24:47.944371 Set Vref, RX VrefLevel [Byte0]: 74
7935 00:24:47.947173 [Byte1]: 74
7936 00:24:47.951545
7937 00:24:47.951653 Set Vref, RX VrefLevel [Byte0]: 75
7938 00:24:47.954926 [Byte1]: 75
7939 00:24:47.959306
7940 00:24:47.959448 Set Vref, RX VrefLevel [Byte0]: 76
7941 00:24:47.962737 [Byte1]: 76
7942 00:24:47.966799
7943 00:24:47.966880 Final RX Vref Byte 0 = 65 to rank0
7944 00:24:47.970400 Final RX Vref Byte 1 = 62 to rank0
7945 00:24:47.973237 Final RX Vref Byte 0 = 65 to rank1
7946 00:24:47.976635 Final RX Vref Byte 1 = 62 to rank1==
7947 00:24:47.980231 Dram Type= 6, Freq= 0, CH_0, rank 0
7948 00:24:47.987201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7949 00:24:47.987283 ==
7950 00:24:47.987365 DQS Delay:
7951 00:24:47.989839 DQS0 = 0, DQS1 = 0
7952 00:24:47.989919 DQM Delay:
7953 00:24:47.989983 DQM0 = 126, DQM1 = 119
7954 00:24:47.993474 DQ Delay:
7955 00:24:47.996560 DQ0 =126, DQ1 =126, DQ2 =126, DQ3 =122
7956 00:24:47.999812 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7957 00:24:48.003253 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7958 00:24:48.006378 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
7959 00:24:48.006459
7960 00:24:48.006522
7961 00:24:48.006580
7962 00:24:48.009491 [DramC_TX_OE_Calibration] TA2
7963 00:24:48.013043 Original DQ_B0 (3 6) =30, OEN = 27
7964 00:24:48.016537 Original DQ_B1 (3 6) =30, OEN = 27
7965 00:24:48.019544 24, 0x0, End_B0=24 End_B1=24
7966 00:24:48.023152 25, 0x0, End_B0=25 End_B1=25
7967 00:24:48.023234 26, 0x0, End_B0=26 End_B1=26
7968 00:24:48.026038 27, 0x0, End_B0=27 End_B1=27
7969 00:24:48.029589 28, 0x0, End_B0=28 End_B1=28
7970 00:24:48.032939 29, 0x0, End_B0=29 End_B1=29
7971 00:24:48.033048 30, 0x0, End_B0=30 End_B1=30
7972 00:24:48.036344 31, 0x4141, End_B0=30 End_B1=30
7973 00:24:48.039291 Byte0 end_step=30 best_step=27
7974 00:24:48.043078 Byte1 end_step=30 best_step=27
7975 00:24:48.046083 Byte0 TX OE(2T, 0.5T) = (3, 3)
7976 00:24:48.049625 Byte1 TX OE(2T, 0.5T) = (3, 3)
7977 00:24:48.049735
7978 00:24:48.049832
7979 00:24:48.056050 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
7980 00:24:48.059798 CH0 RK0: MR19=303, MR18=1414
7981 00:24:48.066170 CH0_RK0: MR19=0x303, MR18=0x1414, DQSOSC=399, MR23=63, INC=23, DEC=15
7982 00:24:48.066281
7983 00:24:48.069450 ----->DramcWriteLeveling(PI) begin...
7984 00:24:48.069532 ==
7985 00:24:48.073158 Dram Type= 6, Freq= 0, CH_0, rank 1
7986 00:24:48.076193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 00:24:48.076300 ==
7988 00:24:48.079209 Write leveling (Byte 0): 32 => 32
7989 00:24:48.082453 Write leveling (Byte 1): 27 => 27
7990 00:24:48.086021 DramcWriteLeveling(PI) end<-----
7991 00:24:48.086101
7992 00:24:48.086165 ==
7993 00:24:48.089442 Dram Type= 6, Freq= 0, CH_0, rank 1
7994 00:24:48.092802 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7995 00:24:48.092913 ==
7996 00:24:48.096153 [Gating] SW mode calibration
7997 00:24:48.102601 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7998 00:24:48.109649 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7999 00:24:48.112906 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 00:24:48.119186 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 00:24:48.122727 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 00:24:48.125908 1 4 12 | B1->B0 | 2323 3130 | 0 1 | (0 0) (1 1)
8003 00:24:48.132484 1 4 16 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8004 00:24:48.136054 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
8005 00:24:48.139368 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8006 00:24:48.145984 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8007 00:24:48.148893 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8008 00:24:48.152260 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 00:24:48.155863 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8010 00:24:48.162362 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
8011 00:24:48.165371 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8012 00:24:48.169132 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8013 00:24:48.175482 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 00:24:48.178962 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 00:24:48.182401 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 00:24:48.189085 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 00:24:48.192017 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8018 00:24:48.195359 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8019 00:24:48.202340 1 6 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
8020 00:24:48.205661 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 00:24:48.208495 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 00:24:48.215162 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8023 00:24:48.218522 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 00:24:48.222119 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 00:24:48.228581 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8026 00:24:48.232136 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8027 00:24:48.235111 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8028 00:24:48.241935 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8029 00:24:48.245127 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 00:24:48.248321 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 00:24:48.255075 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 00:24:48.258527 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 00:24:48.261465 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 00:24:48.268106 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 00:24:48.271503 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 00:24:48.274977 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 00:24:48.281368 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 00:24:48.284822 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 00:24:48.288247 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 00:24:48.294512 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 00:24:48.297922 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8042 00:24:48.301433 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8043 00:24:48.308260 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8044 00:24:48.308340 Total UI for P1: 0, mck2ui 16
8045 00:24:48.314700 best dqsien dly found for B0: ( 1, 9, 10)
8046 00:24:48.318213 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8047 00:24:48.321257 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 00:24:48.324754 Total UI for P1: 0, mck2ui 16
8049 00:24:48.327982 best dqsien dly found for B1: ( 1, 9, 18)
8050 00:24:48.331085 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8051 00:24:48.334614 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8052 00:24:48.334712
8053 00:24:48.337913 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8054 00:24:48.344892 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8055 00:24:48.345001 [Gating] SW calibration Done
8056 00:24:48.347720 ==
8057 00:24:48.347816 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 00:24:48.354276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 00:24:48.354374 ==
8060 00:24:48.354460 RX Vref Scan: 0
8061 00:24:48.354547
8062 00:24:48.357956 RX Vref 0 -> 0, step: 1
8063 00:24:48.358024
8064 00:24:48.361231 RX Delay 0 -> 252, step: 8
8065 00:24:48.364829 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8066 00:24:48.368275 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8067 00:24:48.371173 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8068 00:24:48.377935 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8069 00:24:48.381315 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8070 00:24:48.384199 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8071 00:24:48.388068 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8072 00:24:48.391097 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8073 00:24:48.398056 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8074 00:24:48.401085 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8075 00:24:48.404207 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8076 00:24:48.407965 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8077 00:24:48.410894 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8078 00:24:48.417764 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
8079 00:24:48.421190 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8080 00:24:48.424546 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8081 00:24:48.424615 ==
8082 00:24:48.428032 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 00:24:48.431109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 00:24:48.431175 ==
8085 00:24:48.434070 DQS Delay:
8086 00:24:48.434134 DQS0 = 0, DQS1 = 0
8087 00:24:48.437743 DQM Delay:
8088 00:24:48.437811 DQM0 = 128, DQM1 = 121
8089 00:24:48.440975 DQ Delay:
8090 00:24:48.444457 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8091 00:24:48.447305 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8092 00:24:48.450621 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8093 00:24:48.453940 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8094 00:24:48.454005
8095 00:24:48.454065
8096 00:24:48.454120 ==
8097 00:24:48.457679 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 00:24:48.460895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 00:24:48.460957 ==
8100 00:24:48.461017
8101 00:24:48.461087
8102 00:24:48.463995 TX Vref Scan disable
8103 00:24:48.467381 == TX Byte 0 ==
8104 00:24:48.470893 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8105 00:24:48.473922 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8106 00:24:48.477489 == TX Byte 1 ==
8107 00:24:48.480879 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8108 00:24:48.484461 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8109 00:24:48.484527 ==
8110 00:24:48.487666 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 00:24:48.494354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 00:24:48.494422 ==
8113 00:24:48.505615
8114 00:24:48.509015 TX Vref early break, caculate TX vref
8115 00:24:48.512354 TX Vref=16, minBit 8, minWin=21, winSum=361
8116 00:24:48.515638 TX Vref=18, minBit 1, minWin=22, winSum=373
8117 00:24:48.519359 TX Vref=20, minBit 9, minWin=22, winSum=380
8118 00:24:48.522097 TX Vref=22, minBit 0, minWin=24, winSum=395
8119 00:24:48.525692 TX Vref=24, minBit 0, minWin=24, winSum=400
8120 00:24:48.532113 TX Vref=26, minBit 9, minWin=24, winSum=405
8121 00:24:48.535657 TX Vref=28, minBit 8, minWin=24, winSum=410
8122 00:24:48.538950 TX Vref=30, minBit 8, minWin=24, winSum=405
8123 00:24:48.542537 TX Vref=32, minBit 8, minWin=23, winSum=396
8124 00:24:48.545388 TX Vref=34, minBit 8, minWin=23, winSum=388
8125 00:24:48.552324 [TxChooseVref] Worse bit 8, Min win 24, Win sum 410, Final Vref 28
8126 00:24:48.552406
8127 00:24:48.555630 Final TX Range 0 Vref 28
8128 00:24:48.555710
8129 00:24:48.555774 ==
8130 00:24:48.559071 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 00:24:48.562737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 00:24:48.562827 ==
8133 00:24:48.562892
8134 00:24:48.562951
8135 00:24:48.565602 TX Vref Scan disable
8136 00:24:48.572244 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8137 00:24:48.572325 == TX Byte 0 ==
8138 00:24:48.575699 u2DelayCellOfst[0]=11 cells (3 PI)
8139 00:24:48.578866 u2DelayCellOfst[1]=18 cells (5 PI)
8140 00:24:48.582123 u2DelayCellOfst[2]=11 cells (3 PI)
8141 00:24:48.585524 u2DelayCellOfst[3]=11 cells (3 PI)
8142 00:24:48.588891 u2DelayCellOfst[4]=7 cells (2 PI)
8143 00:24:48.592241 u2DelayCellOfst[5]=0 cells (0 PI)
8144 00:24:48.595683 u2DelayCellOfst[6]=18 cells (5 PI)
8145 00:24:48.595764 u2DelayCellOfst[7]=18 cells (5 PI)
8146 00:24:48.601975 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8147 00:24:48.605413 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8148 00:24:48.605494 == TX Byte 1 ==
8149 00:24:48.608886 u2DelayCellOfst[8]=0 cells (0 PI)
8150 00:24:48.612389 u2DelayCellOfst[9]=0 cells (0 PI)
8151 00:24:48.615553 u2DelayCellOfst[10]=7 cells (2 PI)
8152 00:24:48.618740 u2DelayCellOfst[11]=3 cells (1 PI)
8153 00:24:48.622027 u2DelayCellOfst[12]=11 cells (3 PI)
8154 00:24:48.625378 u2DelayCellOfst[13]=11 cells (3 PI)
8155 00:24:48.628602 u2DelayCellOfst[14]=15 cells (4 PI)
8156 00:24:48.632258 u2DelayCellOfst[15]=11 cells (3 PI)
8157 00:24:48.635322 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8158 00:24:48.642036 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8159 00:24:48.642115 DramC Write-DBI on
8160 00:24:48.642179 ==
8161 00:24:48.645293 Dram Type= 6, Freq= 0, CH_0, rank 1
8162 00:24:48.648708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8163 00:24:48.651936 ==
8164 00:24:48.652005
8165 00:24:48.652068
8166 00:24:48.652125 TX Vref Scan disable
8167 00:24:48.655132 == TX Byte 0 ==
8168 00:24:48.658652 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8169 00:24:48.662086 == TX Byte 1 ==
8170 00:24:48.665567 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8171 00:24:48.668323 DramC Write-DBI off
8172 00:24:48.668393
8173 00:24:48.668451 [DATLAT]
8174 00:24:48.668506 Freq=1600, CH0 RK1
8175 00:24:48.668565
8176 00:24:48.672031 DATLAT Default: 0xf
8177 00:24:48.672098 0, 0xFFFF, sum = 0
8178 00:24:48.674907 1, 0xFFFF, sum = 0
8179 00:24:48.674977 2, 0xFFFF, sum = 0
8180 00:24:48.678340 3, 0xFFFF, sum = 0
8181 00:24:48.681964 4, 0xFFFF, sum = 0
8182 00:24:48.682034 5, 0xFFFF, sum = 0
8183 00:24:48.685016 6, 0xFFFF, sum = 0
8184 00:24:48.685090 7, 0xFFFF, sum = 0
8185 00:24:48.688135 8, 0xFFFF, sum = 0
8186 00:24:48.688203 9, 0xFFFF, sum = 0
8187 00:24:48.691443 10, 0xFFFF, sum = 0
8188 00:24:48.691513 11, 0xFFFF, sum = 0
8189 00:24:48.695217 12, 0xFFFF, sum = 0
8190 00:24:48.695284 13, 0xCFFF, sum = 0
8191 00:24:48.698024 14, 0x0, sum = 1
8192 00:24:48.698109 15, 0x0, sum = 2
8193 00:24:48.701670 16, 0x0, sum = 3
8194 00:24:48.701747 17, 0x0, sum = 4
8195 00:24:48.705111 best_step = 15
8196 00:24:48.705178
8197 00:24:48.705238 ==
8198 00:24:48.708340 Dram Type= 6, Freq= 0, CH_0, rank 1
8199 00:24:48.711857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8200 00:24:48.711935 ==
8201 00:24:48.714693 RX Vref Scan: 0
8202 00:24:48.714769
8203 00:24:48.714829 RX Vref 0 -> 0, step: 1
8204 00:24:48.714888
8205 00:24:48.718155 RX Delay 3 -> 252, step: 4
8206 00:24:48.721521 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8207 00:24:48.728240 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8208 00:24:48.731495 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8209 00:24:48.734626 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8210 00:24:48.738245 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8211 00:24:48.741892 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8212 00:24:48.747800 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8213 00:24:48.751180 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8214 00:24:48.754818 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8215 00:24:48.757794 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8216 00:24:48.761472 iDelay=191, Bit 10, Center 118 (63 ~ 174) 112
8217 00:24:48.767855 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8218 00:24:48.771267 iDelay=191, Bit 12, Center 122 (67 ~ 178) 112
8219 00:24:48.774685 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8220 00:24:48.778130 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8221 00:24:48.784470 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8222 00:24:48.784537 ==
8223 00:24:48.787865 Dram Type= 6, Freq= 0, CH_0, rank 1
8224 00:24:48.791704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8225 00:24:48.791771 ==
8226 00:24:48.791829 DQS Delay:
8227 00:24:48.794534 DQS0 = 0, DQS1 = 0
8228 00:24:48.794600 DQM Delay:
8229 00:24:48.797686 DQM0 = 124, DQM1 = 117
8230 00:24:48.797749 DQ Delay:
8231 00:24:48.801334 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8232 00:24:48.804407 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8233 00:24:48.807780 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8234 00:24:48.810973 DQ12 =122, DQ13 =122, DQ14 =128, DQ15 =124
8235 00:24:48.811071
8236 00:24:48.811158
8237 00:24:48.814450
8238 00:24:48.814527 [DramC_TX_OE_Calibration] TA2
8239 00:24:48.817432 Original DQ_B0 (3 6) =30, OEN = 27
8240 00:24:48.820791 Original DQ_B1 (3 6) =30, OEN = 27
8241 00:24:48.823992 24, 0x0, End_B0=24 End_B1=24
8242 00:24:48.827541 25, 0x0, End_B0=25 End_B1=25
8243 00:24:48.830794 26, 0x0, End_B0=26 End_B1=26
8244 00:24:48.830862 27, 0x0, End_B0=27 End_B1=27
8245 00:24:48.834024 28, 0x0, End_B0=28 End_B1=28
8246 00:24:48.837849 29, 0x0, End_B0=29 End_B1=29
8247 00:24:48.840538 30, 0x0, End_B0=30 End_B1=30
8248 00:24:48.840605 31, 0x4141, End_B0=30 End_B1=30
8249 00:24:48.844164 Byte0 end_step=30 best_step=27
8250 00:24:48.847222 Byte1 end_step=30 best_step=27
8251 00:24:48.850555 Byte0 TX OE(2T, 0.5T) = (3, 3)
8252 00:24:48.854141 Byte1 TX OE(2T, 0.5T) = (3, 3)
8253 00:24:48.854211
8254 00:24:48.854271
8255 00:24:48.860659 [DQSOSCAuto] RK1, (LSB)MR18= 0x2715, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
8256 00:24:48.863997 CH0 RK1: MR19=303, MR18=2715
8257 00:24:48.870283 CH0_RK1: MR19=0x303, MR18=0x2715, DQSOSC=390, MR23=63, INC=24, DEC=16
8258 00:24:48.874141 [RxdqsGatingPostProcess] freq 1600
8259 00:24:48.880410 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8260 00:24:48.884017 best DQS0 dly(2T, 0.5T) = (1, 1)
8261 00:24:48.884086 best DQS1 dly(2T, 0.5T) = (1, 1)
8262 00:24:48.887257 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8263 00:24:48.890659 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8264 00:24:48.893564 best DQS0 dly(2T, 0.5T) = (1, 1)
8265 00:24:48.896968 best DQS1 dly(2T, 0.5T) = (1, 1)
8266 00:24:48.900506 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8267 00:24:48.904310 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8268 00:24:48.907164 Pre-setting of DQS Precalculation
8269 00:24:48.910392 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8270 00:24:48.913685 ==
8271 00:24:48.917148 Dram Type= 6, Freq= 0, CH_1, rank 0
8272 00:24:48.920400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8273 00:24:48.920473 ==
8274 00:24:48.923469 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8275 00:24:48.930050 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8276 00:24:48.933375 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8277 00:24:48.939930 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8278 00:24:48.948159 [CA 0] Center 42 (13~71) winsize 59
8279 00:24:48.951338 [CA 1] Center 42 (12~72) winsize 61
8280 00:24:48.955768 [CA 2] Center 38 (9~67) winsize 59
8281 00:24:48.958468 [CA 3] Center 36 (7~66) winsize 60
8282 00:24:48.961443 [CA 4] Center 37 (8~67) winsize 60
8283 00:24:48.964755 [CA 5] Center 36 (7~66) winsize 60
8284 00:24:48.964824
8285 00:24:48.968058 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8286 00:24:48.968126
8287 00:24:48.971316 [CATrainingPosCal] consider 1 rank data
8288 00:24:48.974501 u2DelayCellTimex100 = 258/100 ps
8289 00:24:48.977829 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8290 00:24:48.984728 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8291 00:24:48.987955 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8292 00:24:48.992006 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8293 00:24:48.994408 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8294 00:24:48.997981 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8295 00:24:48.998047
8296 00:24:49.001457 CA PerBit enable=1, Macro0, CA PI delay=36
8297 00:24:49.001538
8298 00:24:49.004349 [CBTSetCACLKResult] CA Dly = 36
8299 00:24:49.007892 CS Dly: 10 (0~41)
8300 00:24:49.011488 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8301 00:24:49.014473 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8302 00:24:49.014552 ==
8303 00:24:49.017971 Dram Type= 6, Freq= 0, CH_1, rank 1
8304 00:24:49.021354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8305 00:24:49.024585 ==
8306 00:24:49.027989 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8307 00:24:49.031024 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8308 00:24:49.037970 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8309 00:24:49.044202 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8310 00:24:49.051538 [CA 0] Center 41 (12~71) winsize 60
8311 00:24:49.054951 [CA 1] Center 42 (13~72) winsize 60
8312 00:24:49.058244 [CA 2] Center 37 (8~67) winsize 60
8313 00:24:49.061568 [CA 3] Center 36 (7~66) winsize 60
8314 00:24:49.064609 [CA 4] Center 37 (7~67) winsize 61
8315 00:24:49.067970 [CA 5] Center 36 (6~66) winsize 61
8316 00:24:49.068049
8317 00:24:49.071303 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8318 00:24:49.071414
8319 00:24:49.075057 [CATrainingPosCal] consider 2 rank data
8320 00:24:49.077960 u2DelayCellTimex100 = 258/100 ps
8321 00:24:49.081366 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8322 00:24:49.087639 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8323 00:24:49.091097 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8324 00:24:49.094223 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8325 00:24:49.097876 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8326 00:24:49.101227 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8327 00:24:49.101332
8328 00:24:49.104267 CA PerBit enable=1, Macro0, CA PI delay=36
8329 00:24:49.104346
8330 00:24:49.107954 [CBTSetCACLKResult] CA Dly = 36
8331 00:24:49.110820 CS Dly: 11 (0~43)
8332 00:24:49.114424 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8333 00:24:49.117366 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8334 00:24:49.117435
8335 00:24:49.120878 ----->DramcWriteLeveling(PI) begin...
8336 00:24:49.120947 ==
8337 00:24:49.124248 Dram Type= 6, Freq= 0, CH_1, rank 0
8338 00:24:49.131030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8339 00:24:49.131128 ==
8340 00:24:49.133968 Write leveling (Byte 0): 25 => 25
8341 00:24:49.134060 Write leveling (Byte 1): 29 => 29
8342 00:24:49.137445 DramcWriteLeveling(PI) end<-----
8343 00:24:49.137512
8344 00:24:49.140831 ==
8345 00:24:49.140918 Dram Type= 6, Freq= 0, CH_1, rank 0
8346 00:24:49.147340 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8347 00:24:49.147460 ==
8348 00:24:49.150784 [Gating] SW mode calibration
8349 00:24:49.157749 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8350 00:24:49.161007 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8351 00:24:49.167583 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 00:24:49.170448 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 00:24:49.174019 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 00:24:49.180386 1 4 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8355 00:24:49.183652 1 4 16 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 1)
8356 00:24:49.187474 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8357 00:24:49.193688 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8358 00:24:49.196933 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8359 00:24:49.200628 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 00:24:49.206837 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 00:24:49.210740 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 00:24:49.213591 1 5 12 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8363 00:24:49.220078 1 5 16 | B1->B0 | 2929 2828 | 0 0 | (0 1) (0 1)
8364 00:24:49.223707 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 00:24:49.226927 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 00:24:49.233434 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 00:24:49.237005 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 00:24:49.240327 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 00:24:49.246816 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 00:24:49.250334 1 6 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8371 00:24:49.253304 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 00:24:49.260175 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 00:24:49.263802 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 00:24:49.267057 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 00:24:49.270287 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 00:24:49.276592 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 00:24:49.280159 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 00:24:49.283568 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 00:24:49.289957 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8380 00:24:49.293545 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8381 00:24:49.296823 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 00:24:49.303582 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 00:24:49.306480 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 00:24:49.309793 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 00:24:49.316358 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 00:24:49.319884 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 00:24:49.322905 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 00:24:49.329895 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 00:24:49.333242 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 00:24:49.336682 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 00:24:49.342910 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 00:24:49.346261 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 00:24:49.349465 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 00:24:49.356082 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8395 00:24:49.359510 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8396 00:24:49.362948 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 00:24:49.366470 Total UI for P1: 0, mck2ui 16
8398 00:24:49.369623 best dqsien dly found for B0: ( 1, 9, 14)
8399 00:24:49.373201 Total UI for P1: 0, mck2ui 16
8400 00:24:49.376467 best dqsien dly found for B1: ( 1, 9, 14)
8401 00:24:49.380051 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8402 00:24:49.382916 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8403 00:24:49.383041
8404 00:24:49.389553 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8405 00:24:49.392971 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8406 00:24:49.393052 [Gating] SW calibration Done
8407 00:24:49.396354 ==
8408 00:24:49.399367 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 00:24:49.402756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 00:24:49.402864 ==
8411 00:24:49.402928 RX Vref Scan: 0
8412 00:24:49.403005
8413 00:24:49.406354 RX Vref 0 -> 0, step: 1
8414 00:24:49.406436
8415 00:24:49.409288 RX Delay 0 -> 252, step: 8
8416 00:24:49.412734 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8417 00:24:49.415787 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8418 00:24:49.419668 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8419 00:24:49.425820 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8420 00:24:49.429050 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8421 00:24:49.432583 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8422 00:24:49.435830 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8423 00:24:49.439351 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8424 00:24:49.445715 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8425 00:24:49.449338 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8426 00:24:49.452615 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8427 00:24:49.455540 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8428 00:24:49.459140 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8429 00:24:49.465938 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8430 00:24:49.469281 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8431 00:24:49.472490 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8432 00:24:49.472621 ==
8433 00:24:49.475818 Dram Type= 6, Freq= 0, CH_1, rank 0
8434 00:24:49.479397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8435 00:24:49.482639 ==
8436 00:24:49.482746 DQS Delay:
8437 00:24:49.482840 DQS0 = 0, DQS1 = 0
8438 00:24:49.485965 DQM Delay:
8439 00:24:49.486073 DQM0 = 132, DQM1 = 126
8440 00:24:49.489006 DQ Delay:
8441 00:24:49.492729 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8442 00:24:49.495696 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8443 00:24:49.499065 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8444 00:24:49.502796 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8445 00:24:49.502901
8446 00:24:49.502992
8447 00:24:49.503079 ==
8448 00:24:49.505494 Dram Type= 6, Freq= 0, CH_1, rank 0
8449 00:24:49.509027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8450 00:24:49.509108 ==
8451 00:24:49.509172
8452 00:24:49.509232
8453 00:24:49.512213 TX Vref Scan disable
8454 00:24:49.515476 == TX Byte 0 ==
8455 00:24:49.518821 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8456 00:24:49.522309 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8457 00:24:49.525848 == TX Byte 1 ==
8458 00:24:49.528755 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8459 00:24:49.532624 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8460 00:24:49.532761 ==
8461 00:24:49.535702 Dram Type= 6, Freq= 0, CH_1, rank 0
8462 00:24:49.541924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8463 00:24:49.542006 ==
8464 00:24:49.553425
8465 00:24:49.556916 TX Vref early break, caculate TX vref
8466 00:24:49.560417 TX Vref=16, minBit 8, minWin=21, winSum=364
8467 00:24:49.563831 TX Vref=18, minBit 11, minWin=21, winSum=372
8468 00:24:49.566667 TX Vref=20, minBit 8, minWin=22, winSum=381
8469 00:24:49.570445 TX Vref=22, minBit 11, minWin=22, winSum=393
8470 00:24:49.573978 TX Vref=24, minBit 11, minWin=23, winSum=404
8471 00:24:49.579920 TX Vref=26, minBit 1, minWin=25, winSum=417
8472 00:24:49.583403 TX Vref=28, minBit 1, minWin=25, winSum=416
8473 00:24:49.586438 TX Vref=30, minBit 1, minWin=25, winSum=413
8474 00:24:49.589926 TX Vref=32, minBit 0, minWin=24, winSum=403
8475 00:24:49.593169 TX Vref=34, minBit 8, minWin=23, winSum=390
8476 00:24:49.599721 [TxChooseVref] Worse bit 1, Min win 25, Win sum 417, Final Vref 26
8477 00:24:49.599827
8478 00:24:49.603100 Final TX Range 0 Vref 26
8479 00:24:49.603200
8480 00:24:49.603301 ==
8481 00:24:49.606805 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 00:24:49.609806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 00:24:49.609885 ==
8484 00:24:49.609948
8485 00:24:49.610008
8486 00:24:49.613256 TX Vref Scan disable
8487 00:24:49.619885 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8488 00:24:49.619962 == TX Byte 0 ==
8489 00:24:49.623406 u2DelayCellOfst[0]=18 cells (5 PI)
8490 00:24:49.626374 u2DelayCellOfst[1]=11 cells (3 PI)
8491 00:24:49.629899 u2DelayCellOfst[2]=0 cells (0 PI)
8492 00:24:49.632860 u2DelayCellOfst[3]=3 cells (1 PI)
8493 00:24:49.636116 u2DelayCellOfst[4]=7 cells (2 PI)
8494 00:24:49.639493 u2DelayCellOfst[5]=22 cells (6 PI)
8495 00:24:49.642690 u2DelayCellOfst[6]=18 cells (5 PI)
8496 00:24:49.646738 u2DelayCellOfst[7]=7 cells (2 PI)
8497 00:24:49.649297 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8498 00:24:49.653043 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8499 00:24:49.656211 == TX Byte 1 ==
8500 00:24:49.659380 u2DelayCellOfst[8]=0 cells (0 PI)
8501 00:24:49.663110 u2DelayCellOfst[9]=11 cells (3 PI)
8502 00:24:49.663218 u2DelayCellOfst[10]=11 cells (3 PI)
8503 00:24:49.666164 u2DelayCellOfst[11]=7 cells (2 PI)
8504 00:24:49.669684 u2DelayCellOfst[12]=15 cells (4 PI)
8505 00:24:49.672530 u2DelayCellOfst[13]=18 cells (5 PI)
8506 00:24:49.675895 u2DelayCellOfst[14]=18 cells (5 PI)
8507 00:24:49.679535 u2DelayCellOfst[15]=18 cells (5 PI)
8508 00:24:49.686316 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8509 00:24:49.689379 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8510 00:24:49.689459 DramC Write-DBI on
8511 00:24:49.689524 ==
8512 00:24:49.692940 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 00:24:49.699121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 00:24:49.699227 ==
8515 00:24:49.699318
8516 00:24:49.699450
8517 00:24:49.699542 TX Vref Scan disable
8518 00:24:49.703550 == TX Byte 0 ==
8519 00:24:49.706415 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8520 00:24:49.709668 == TX Byte 1 ==
8521 00:24:49.713271 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8522 00:24:49.716793 DramC Write-DBI off
8523 00:24:49.716882
8524 00:24:49.716947 [DATLAT]
8525 00:24:49.717006 Freq=1600, CH1 RK0
8526 00:24:49.717063
8527 00:24:49.719756 DATLAT Default: 0xf
8528 00:24:49.719837 0, 0xFFFF, sum = 0
8529 00:24:49.722944 1, 0xFFFF, sum = 0
8530 00:24:49.726537 2, 0xFFFF, sum = 0
8531 00:24:49.726621 3, 0xFFFF, sum = 0
8532 00:24:49.730079 4, 0xFFFF, sum = 0
8533 00:24:49.730189 5, 0xFFFF, sum = 0
8534 00:24:49.733496 6, 0xFFFF, sum = 0
8535 00:24:49.733577 7, 0xFFFF, sum = 0
8536 00:24:49.736577 8, 0xFFFF, sum = 0
8537 00:24:49.736659 9, 0xFFFF, sum = 0
8538 00:24:49.739873 10, 0xFFFF, sum = 0
8539 00:24:49.739955 11, 0xFFFF, sum = 0
8540 00:24:49.743216 12, 0xFFFF, sum = 0
8541 00:24:49.743297 13, 0x8FFF, sum = 0
8542 00:24:49.746656 14, 0x0, sum = 1
8543 00:24:49.746767 15, 0x0, sum = 2
8544 00:24:49.749994 16, 0x0, sum = 3
8545 00:24:49.750138 17, 0x0, sum = 4
8546 00:24:49.753512 best_step = 15
8547 00:24:49.753583
8548 00:24:49.753643 ==
8549 00:24:49.756399 Dram Type= 6, Freq= 0, CH_1, rank 0
8550 00:24:49.760135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8551 00:24:49.760216 ==
8552 00:24:49.760280 RX Vref Scan: 1
8553 00:24:49.763051
8554 00:24:49.763130 Set Vref Range= 24 -> 127
8555 00:24:49.763193
8556 00:24:49.766636 RX Vref 24 -> 127, step: 1
8557 00:24:49.766716
8558 00:24:49.769879 RX Delay 11 -> 252, step: 4
8559 00:24:49.769960
8560 00:24:49.773275 Set Vref, RX VrefLevel [Byte0]: 24
8561 00:24:49.776159 [Byte1]: 24
8562 00:24:49.776239
8563 00:24:49.779529 Set Vref, RX VrefLevel [Byte0]: 25
8564 00:24:49.783034 [Byte1]: 25
8565 00:24:49.783129
8566 00:24:49.786329 Set Vref, RX VrefLevel [Byte0]: 26
8567 00:24:49.789771 [Byte1]: 26
8568 00:24:49.793417
8569 00:24:49.793497 Set Vref, RX VrefLevel [Byte0]: 27
8570 00:24:49.797260 [Byte1]: 27
8571 00:24:49.801220
8572 00:24:49.801300 Set Vref, RX VrefLevel [Byte0]: 28
8573 00:24:49.804495 [Byte1]: 28
8574 00:24:49.809425
8575 00:24:49.809505 Set Vref, RX VrefLevel [Byte0]: 29
8576 00:24:49.812056 [Byte1]: 29
8577 00:24:49.816640
8578 00:24:49.816721 Set Vref, RX VrefLevel [Byte0]: 30
8579 00:24:49.819604 [Byte1]: 30
8580 00:24:49.824363
8581 00:24:49.824444 Set Vref, RX VrefLevel [Byte0]: 31
8582 00:24:49.827614 [Byte1]: 31
8583 00:24:49.831847
8584 00:24:49.831927 Set Vref, RX VrefLevel [Byte0]: 32
8585 00:24:49.835150 [Byte1]: 32
8586 00:24:49.839188
8587 00:24:49.839268 Set Vref, RX VrefLevel [Byte0]: 33
8588 00:24:49.842877 [Byte1]: 33
8589 00:24:49.847223
8590 00:24:49.847303 Set Vref, RX VrefLevel [Byte0]: 34
8591 00:24:49.850027 [Byte1]: 34
8592 00:24:49.854499
8593 00:24:49.854579 Set Vref, RX VrefLevel [Byte0]: 35
8594 00:24:49.858198 [Byte1]: 35
8595 00:24:49.862312
8596 00:24:49.862424 Set Vref, RX VrefLevel [Byte0]: 36
8597 00:24:49.868632 [Byte1]: 36
8598 00:24:49.868713
8599 00:24:49.871890 Set Vref, RX VrefLevel [Byte0]: 37
8600 00:24:49.875283 [Byte1]: 37
8601 00:24:49.875364
8602 00:24:49.878843 Set Vref, RX VrefLevel [Byte0]: 38
8603 00:24:49.881966 [Byte1]: 38
8604 00:24:49.882046
8605 00:24:49.885391 Set Vref, RX VrefLevel [Byte0]: 39
8606 00:24:49.888320 [Byte1]: 39
8607 00:24:49.892642
8608 00:24:49.892722 Set Vref, RX VrefLevel [Byte0]: 40
8609 00:24:49.895888 [Byte1]: 40
8610 00:24:49.900719
8611 00:24:49.900799 Set Vref, RX VrefLevel [Byte0]: 41
8612 00:24:49.903385 [Byte1]: 41
8613 00:24:49.907746
8614 00:24:49.907826 Set Vref, RX VrefLevel [Byte0]: 42
8615 00:24:49.910912 [Byte1]: 42
8616 00:24:49.915771
8617 00:24:49.915851 Set Vref, RX VrefLevel [Byte0]: 43
8618 00:24:49.918546 [Byte1]: 43
8619 00:24:49.922874
8620 00:24:49.922954 Set Vref, RX VrefLevel [Byte0]: 44
8621 00:24:49.926225 [Byte1]: 44
8622 00:24:49.930875
8623 00:24:49.930955 Set Vref, RX VrefLevel [Byte0]: 45
8624 00:24:49.934493 [Byte1]: 45
8625 00:24:49.938598
8626 00:24:49.938677 Set Vref, RX VrefLevel [Byte0]: 46
8627 00:24:49.941786 [Byte1]: 46
8628 00:24:49.946157
8629 00:24:49.946237 Set Vref, RX VrefLevel [Byte0]: 47
8630 00:24:49.949092 [Byte1]: 47
8631 00:24:49.953266
8632 00:24:49.953346 Set Vref, RX VrefLevel [Byte0]: 48
8633 00:24:49.956679 [Byte1]: 48
8634 00:24:49.961318
8635 00:24:49.961398 Set Vref, RX VrefLevel [Byte0]: 49
8636 00:24:49.964411 [Byte1]: 49
8637 00:24:49.968876
8638 00:24:49.968956 Set Vref, RX VrefLevel [Byte0]: 50
8639 00:24:49.971943 [Byte1]: 50
8640 00:24:49.976642
8641 00:24:49.976748 Set Vref, RX VrefLevel [Byte0]: 51
8642 00:24:49.979570 [Byte1]: 51
8643 00:24:49.984470
8644 00:24:49.984549 Set Vref, RX VrefLevel [Byte0]: 52
8645 00:24:49.987133 [Byte1]: 52
8646 00:24:49.992032
8647 00:24:49.992112 Set Vref, RX VrefLevel [Byte0]: 53
8648 00:24:49.994733 [Byte1]: 53
8649 00:24:49.999038
8650 00:24:49.999117 Set Vref, RX VrefLevel [Byte0]: 54
8651 00:24:50.002495 [Byte1]: 54
8652 00:24:50.007189
8653 00:24:50.007269 Set Vref, RX VrefLevel [Byte0]: 55
8654 00:24:50.010122 [Byte1]: 55
8655 00:24:50.014181
8656 00:24:50.014262 Set Vref, RX VrefLevel [Byte0]: 56
8657 00:24:50.017627 [Byte1]: 56
8658 00:24:50.022072
8659 00:24:50.022153 Set Vref, RX VrefLevel [Byte0]: 57
8660 00:24:50.025307 [Byte1]: 57
8661 00:24:50.029728
8662 00:24:50.029808 Set Vref, RX VrefLevel [Byte0]: 58
8663 00:24:50.032838 [Byte1]: 58
8664 00:24:50.037355
8665 00:24:50.037435 Set Vref, RX VrefLevel [Byte0]: 59
8666 00:24:50.040857 [Byte1]: 59
8667 00:24:50.045085
8668 00:24:50.045165 Set Vref, RX VrefLevel [Byte0]: 60
8669 00:24:50.048395 [Byte1]: 60
8670 00:24:50.052365
8671 00:24:50.052445 Set Vref, RX VrefLevel [Byte0]: 61
8672 00:24:50.055843 [Byte1]: 61
8673 00:24:50.060319
8674 00:24:50.060398 Set Vref, RX VrefLevel [Byte0]: 62
8675 00:24:50.063167 [Byte1]: 62
8676 00:24:50.067428
8677 00:24:50.067509 Set Vref, RX VrefLevel [Byte0]: 63
8678 00:24:50.071126 [Byte1]: 63
8679 00:24:50.075253
8680 00:24:50.075333 Set Vref, RX VrefLevel [Byte0]: 64
8681 00:24:50.078970 [Byte1]: 64
8682 00:24:50.083270
8683 00:24:50.083350 Set Vref, RX VrefLevel [Byte0]: 65
8684 00:24:50.086039 [Byte1]: 65
8685 00:24:50.090559
8686 00:24:50.090639 Set Vref, RX VrefLevel [Byte0]: 66
8687 00:24:50.093831 [Byte1]: 66
8688 00:24:50.098560
8689 00:24:50.098640 Set Vref, RX VrefLevel [Byte0]: 67
8690 00:24:50.101244 [Byte1]: 67
8691 00:24:50.106027
8692 00:24:50.106107 Set Vref, RX VrefLevel [Byte0]: 68
8693 00:24:50.109356 [Byte1]: 68
8694 00:24:50.113310
8695 00:24:50.113389 Set Vref, RX VrefLevel [Byte0]: 69
8696 00:24:50.117077 [Byte1]: 69
8697 00:24:50.120842
8698 00:24:50.120922 Set Vref, RX VrefLevel [Byte0]: 70
8699 00:24:50.124329 [Byte1]: 70
8700 00:24:50.129178
8701 00:24:50.129258 Final RX Vref Byte 0 = 57 to rank0
8702 00:24:50.132276 Final RX Vref Byte 1 = 54 to rank0
8703 00:24:50.135236 Final RX Vref Byte 0 = 57 to rank1
8704 00:24:50.138339 Final RX Vref Byte 1 = 54 to rank1==
8705 00:24:50.142066 Dram Type= 6, Freq= 0, CH_1, rank 0
8706 00:24:50.148578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8707 00:24:50.148659 ==
8708 00:24:50.148724 DQS Delay:
8709 00:24:50.148783 DQS0 = 0, DQS1 = 0
8710 00:24:50.151865 DQM Delay:
8711 00:24:50.151945 DQM0 = 131, DQM1 = 123
8712 00:24:50.154828 DQ Delay:
8713 00:24:50.158336 DQ0 =138, DQ1 =128, DQ2 =120, DQ3 =128
8714 00:24:50.161808 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8715 00:24:50.165311 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8716 00:24:50.168828 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8717 00:24:50.168908
8718 00:24:50.168971
8719 00:24:50.169030
8720 00:24:50.171713 [DramC_TX_OE_Calibration] TA2
8721 00:24:50.175300 Original DQ_B0 (3 6) =30, OEN = 27
8722 00:24:50.178326 Original DQ_B1 (3 6) =30, OEN = 27
8723 00:24:50.181587 24, 0x0, End_B0=24 End_B1=24
8724 00:24:50.181669 25, 0x0, End_B0=25 End_B1=25
8725 00:24:50.184935 26, 0x0, End_B0=26 End_B1=26
8726 00:24:50.188411 27, 0x0, End_B0=27 End_B1=27
8727 00:24:50.191765 28, 0x0, End_B0=28 End_B1=28
8728 00:24:50.191847 29, 0x0, End_B0=29 End_B1=29
8729 00:24:50.194723 30, 0x0, End_B0=30 End_B1=30
8730 00:24:50.198345 31, 0x4141, End_B0=30 End_B1=30
8731 00:24:50.201740 Byte0 end_step=30 best_step=27
8732 00:24:50.205102 Byte1 end_step=30 best_step=27
8733 00:24:50.208841 Byte0 TX OE(2T, 0.5T) = (3, 3)
8734 00:24:50.211266 Byte1 TX OE(2T, 0.5T) = (3, 3)
8735 00:24:50.211368
8736 00:24:50.211476
8737 00:24:50.217846 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8738 00:24:50.221220 CH1 RK0: MR19=303, MR18=B0F
8739 00:24:50.228221 CH1_RK0: MR19=0x303, MR18=0xB0F, DQSOSC=402, MR23=63, INC=22, DEC=15
8740 00:24:50.228302
8741 00:24:50.231167 ----->DramcWriteLeveling(PI) begin...
8742 00:24:50.231249 ==
8743 00:24:50.234540 Dram Type= 6, Freq= 0, CH_1, rank 1
8744 00:24:50.238106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 00:24:50.238187 ==
8746 00:24:50.241266 Write leveling (Byte 0): 23 => 23
8747 00:24:50.244546 Write leveling (Byte 1): 28 => 28
8748 00:24:50.248236 DramcWriteLeveling(PI) end<-----
8749 00:24:50.248333
8750 00:24:50.248399 ==
8751 00:24:50.251671 Dram Type= 6, Freq= 0, CH_1, rank 1
8752 00:24:50.255110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8753 00:24:50.255220 ==
8754 00:24:50.257908 [Gating] SW mode calibration
8755 00:24:50.264061 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8756 00:24:50.271264 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8757 00:24:50.274628 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 00:24:50.277957 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 00:24:50.284395 1 4 8 | B1->B0 | 2323 3232 | 1 0 | (0 0) (0 0)
8760 00:24:50.287897 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8761 00:24:50.291015 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 00:24:50.297566 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 00:24:50.300646 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 00:24:50.304092 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 00:24:50.311130 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 00:24:50.314098 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8767 00:24:50.317565 1 5 8 | B1->B0 | 3434 2626 | 0 0 | (1 0) (1 0)
8768 00:24:50.324238 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8769 00:24:50.327492 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 00:24:50.330562 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 00:24:50.336963 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 00:24:50.340802 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 00:24:50.343907 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 00:24:50.350668 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
8775 00:24:50.353873 1 6 8 | B1->B0 | 2525 4545 | 1 0 | (0 0) (0 0)
8776 00:24:50.357404 1 6 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8777 00:24:50.363835 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 00:24:50.367265 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 00:24:50.370572 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 00:24:50.377029 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 00:24:50.380470 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 00:24:50.383923 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8783 00:24:50.390372 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8784 00:24:50.393792 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8785 00:24:50.397029 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 00:24:50.403620 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 00:24:50.406896 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 00:24:50.409883 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 00:24:50.416972 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 00:24:50.419940 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 00:24:50.423665 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 00:24:50.430312 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 00:24:50.433711 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 00:24:50.437135 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 00:24:50.443348 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 00:24:50.446508 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 00:24:50.450315 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 00:24:50.456825 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 00:24:50.460144 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8800 00:24:50.463172 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8801 00:24:50.466449 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 00:24:50.470138 Total UI for P1: 0, mck2ui 16
8803 00:24:50.473244 best dqsien dly found for B0: ( 1, 9, 10)
8804 00:24:50.476661 Total UI for P1: 0, mck2ui 16
8805 00:24:50.480158 best dqsien dly found for B1: ( 1, 9, 12)
8806 00:24:50.483068 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8807 00:24:50.489984 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8808 00:24:50.490089
8809 00:24:50.492892 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8810 00:24:50.496329 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8811 00:24:50.499676 [Gating] SW calibration Done
8812 00:24:50.499761 ==
8813 00:24:50.503000 Dram Type= 6, Freq= 0, CH_1, rank 1
8814 00:24:50.506358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8815 00:24:50.506456 ==
8816 00:24:50.509818 RX Vref Scan: 0
8817 00:24:50.509929
8818 00:24:50.510024 RX Vref 0 -> 0, step: 1
8819 00:24:50.510109
8820 00:24:50.513030 RX Delay 0 -> 252, step: 8
8821 00:24:50.516240 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8822 00:24:50.519929 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8823 00:24:50.526062 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8824 00:24:50.529592 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8825 00:24:50.532731 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8826 00:24:50.536174 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8827 00:24:50.539980 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8828 00:24:50.545992 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8829 00:24:50.549330 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8830 00:24:50.552678 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8831 00:24:50.556138 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8832 00:24:50.559884 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8833 00:24:50.566025 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8834 00:24:50.569811 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8835 00:24:50.572462 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8836 00:24:50.575912 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8837 00:24:50.575992 ==
8838 00:24:50.579178 Dram Type= 6, Freq= 0, CH_1, rank 1
8839 00:24:50.585992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8840 00:24:50.586073 ==
8841 00:24:50.586137 DQS Delay:
8842 00:24:50.589334 DQS0 = 0, DQS1 = 0
8843 00:24:50.589415 DQM Delay:
8844 00:24:50.593098 DQM0 = 132, DQM1 = 128
8845 00:24:50.593178 DQ Delay:
8846 00:24:50.596190 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8847 00:24:50.599028 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8848 00:24:50.602598 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8849 00:24:50.605818 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8850 00:24:50.605898
8851 00:24:50.605963
8852 00:24:50.606022 ==
8853 00:24:50.609276 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 00:24:50.615685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 00:24:50.615792 ==
8856 00:24:50.615883
8857 00:24:50.615969
8858 00:24:50.616070 TX Vref Scan disable
8859 00:24:50.619075 == TX Byte 0 ==
8860 00:24:50.622584 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8861 00:24:50.625712 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8862 00:24:50.628819 == TX Byte 1 ==
8863 00:24:50.632864 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8864 00:24:50.639221 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8865 00:24:50.639328 ==
8866 00:24:50.642470 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 00:24:50.645330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 00:24:50.645411 ==
8869 00:24:50.659114
8870 00:24:50.662643 TX Vref early break, caculate TX vref
8871 00:24:50.666138 TX Vref=16, minBit 0, minWin=22, winSum=376
8872 00:24:50.668937 TX Vref=18, minBit 9, minWin=23, winSum=387
8873 00:24:50.672286 TX Vref=20, minBit 0, minWin=24, winSum=397
8874 00:24:50.675601 TX Vref=22, minBit 3, minWin=24, winSum=405
8875 00:24:50.678884 TX Vref=24, minBit 0, minWin=25, winSum=413
8876 00:24:50.685717 TX Vref=26, minBit 0, minWin=25, winSum=418
8877 00:24:50.689051 TX Vref=28, minBit 5, minWin=24, winSum=420
8878 00:24:50.692202 TX Vref=30, minBit 5, minWin=24, winSum=415
8879 00:24:50.695502 TX Vref=32, minBit 1, minWin=24, winSum=409
8880 00:24:50.698882 TX Vref=34, minBit 1, minWin=23, winSum=400
8881 00:24:50.702591 TX Vref=36, minBit 1, minWin=23, winSum=398
8882 00:24:50.709230 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 26
8883 00:24:50.709310
8884 00:24:50.712341 Final TX Range 0 Vref 26
8885 00:24:50.712423
8886 00:24:50.712487 ==
8887 00:24:50.715662 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 00:24:50.719119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 00:24:50.719200 ==
8890 00:24:50.719264
8891 00:24:50.721971
8892 00:24:50.722051 TX Vref Scan disable
8893 00:24:50.728837 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8894 00:24:50.728917 == TX Byte 0 ==
8895 00:24:50.731982 u2DelayCellOfst[0]=18 cells (5 PI)
8896 00:24:50.735551 u2DelayCellOfst[1]=11 cells (3 PI)
8897 00:24:50.739026 u2DelayCellOfst[2]=0 cells (0 PI)
8898 00:24:50.742393 u2DelayCellOfst[3]=3 cells (1 PI)
8899 00:24:50.745508 u2DelayCellOfst[4]=7 cells (2 PI)
8900 00:24:50.748956 u2DelayCellOfst[5]=18 cells (5 PI)
8901 00:24:50.751843 u2DelayCellOfst[6]=15 cells (4 PI)
8902 00:24:50.755407 u2DelayCellOfst[7]=3 cells (1 PI)
8903 00:24:50.758834 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8904 00:24:50.761966 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8905 00:24:50.765208 == TX Byte 1 ==
8906 00:24:50.768682 u2DelayCellOfst[8]=0 cells (0 PI)
8907 00:24:50.772087 u2DelayCellOfst[9]=7 cells (2 PI)
8908 00:24:50.772167 u2DelayCellOfst[10]=11 cells (3 PI)
8909 00:24:50.774992 u2DelayCellOfst[11]=7 cells (2 PI)
8910 00:24:50.779025 u2DelayCellOfst[12]=18 cells (5 PI)
8911 00:24:50.781972 u2DelayCellOfst[13]=18 cells (5 PI)
8912 00:24:50.785248 u2DelayCellOfst[14]=18 cells (5 PI)
8913 00:24:50.788956 u2DelayCellOfst[15]=18 cells (5 PI)
8914 00:24:50.795210 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8915 00:24:50.798666 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8916 00:24:50.798747 DramC Write-DBI on
8917 00:24:50.798811 ==
8918 00:24:50.802158 Dram Type= 6, Freq= 0, CH_1, rank 1
8919 00:24:50.808779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8920 00:24:50.808859 ==
8921 00:24:50.808923
8922 00:24:50.808982
8923 00:24:50.809039 TX Vref Scan disable
8924 00:24:50.812372 == TX Byte 0 ==
8925 00:24:50.816110 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8926 00:24:50.818780 == TX Byte 1 ==
8927 00:24:50.822886 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8928 00:24:50.822967 DramC Write-DBI off
8929 00:24:50.825888
8930 00:24:50.825967 [DATLAT]
8931 00:24:50.826031 Freq=1600, CH1 RK1
8932 00:24:50.826089
8933 00:24:50.829387 DATLAT Default: 0xf
8934 00:24:50.829467 0, 0xFFFF, sum = 0
8935 00:24:50.832414 1, 0xFFFF, sum = 0
8936 00:24:50.832495 2, 0xFFFF, sum = 0
8937 00:24:50.835904 3, 0xFFFF, sum = 0
8938 00:24:50.838971 4, 0xFFFF, sum = 0
8939 00:24:50.839052 5, 0xFFFF, sum = 0
8940 00:24:50.842255 6, 0xFFFF, sum = 0
8941 00:24:50.842337 7, 0xFFFF, sum = 0
8942 00:24:50.845828 8, 0xFFFF, sum = 0
8943 00:24:50.845910 9, 0xFFFF, sum = 0
8944 00:24:50.849270 10, 0xFFFF, sum = 0
8945 00:24:50.849352 11, 0xFFFF, sum = 0
8946 00:24:50.852508 12, 0xFFFF, sum = 0
8947 00:24:50.852589 13, 0x8FFF, sum = 0
8948 00:24:50.856225 14, 0x0, sum = 1
8949 00:24:50.856306 15, 0x0, sum = 2
8950 00:24:50.858737 16, 0x0, sum = 3
8951 00:24:50.858818 17, 0x0, sum = 4
8952 00:24:50.862363 best_step = 15
8953 00:24:50.862444
8954 00:24:50.862507 ==
8955 00:24:50.865721 Dram Type= 6, Freq= 0, CH_1, rank 1
8956 00:24:50.868617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8957 00:24:50.868698 ==
8958 00:24:50.872377 RX Vref Scan: 0
8959 00:24:50.872458
8960 00:24:50.872521 RX Vref 0 -> 0, step: 1
8961 00:24:50.872580
8962 00:24:50.875927 RX Delay 11 -> 252, step: 4
8963 00:24:50.878906 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8964 00:24:50.885983 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8965 00:24:50.888741 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8966 00:24:50.892050 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8967 00:24:50.895287 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8968 00:24:50.898904 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8969 00:24:50.905177 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8970 00:24:50.908848 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8971 00:24:50.911774 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8972 00:24:50.915289 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
8973 00:24:50.918546 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8974 00:24:50.925191 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8975 00:24:50.928330 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8976 00:24:50.931466 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8977 00:24:50.934993 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8978 00:24:50.941525 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8979 00:24:50.941631 ==
8980 00:24:50.944957 Dram Type= 6, Freq= 0, CH_1, rank 1
8981 00:24:50.948373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8982 00:24:50.948454 ==
8983 00:24:50.948519 DQS Delay:
8984 00:24:50.951668 DQS0 = 0, DQS1 = 0
8985 00:24:50.951748 DQM Delay:
8986 00:24:50.954927 DQM0 = 129, DQM1 = 125
8987 00:24:50.955032 DQ Delay:
8988 00:24:50.958406 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =126
8989 00:24:50.961507 DQ4 =126, DQ5 =140, DQ6 =140, DQ7 =126
8990 00:24:50.964498 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =120
8991 00:24:50.968055 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =136
8992 00:24:50.968135
8993 00:24:50.971220
8994 00:24:50.971325
8995 00:24:50.971445 [DramC_TX_OE_Calibration] TA2
8996 00:24:50.974349 Original DQ_B0 (3 6) =30, OEN = 27
8997 00:24:50.977696 Original DQ_B1 (3 6) =30, OEN = 27
8998 00:24:50.981448 24, 0x0, End_B0=24 End_B1=24
8999 00:24:50.984579 25, 0x0, End_B0=25 End_B1=25
9000 00:24:50.987413 26, 0x0, End_B0=26 End_B1=26
9001 00:24:50.987495 27, 0x0, End_B0=27 End_B1=27
9002 00:24:50.991201 28, 0x0, End_B0=28 End_B1=28
9003 00:24:50.994297 29, 0x0, End_B0=29 End_B1=29
9004 00:24:50.997382 30, 0x0, End_B0=30 End_B1=30
9005 00:24:51.000688 31, 0x4141, End_B0=30 End_B1=30
9006 00:24:51.004162 Byte0 end_step=30 best_step=27
9007 00:24:51.004246 Byte1 end_step=30 best_step=27
9008 00:24:51.007284 Byte0 TX OE(2T, 0.5T) = (3, 3)
9009 00:24:51.010837 Byte1 TX OE(2T, 0.5T) = (3, 3)
9010 00:24:51.010917
9011 00:24:51.010981
9012 00:24:51.020556 [DQSOSCAuto] RK1, (LSB)MR18= 0x141f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 399 ps
9013 00:24:51.020643 CH1 RK1: MR19=303, MR18=141F
9014 00:24:51.027539 CH1_RK1: MR19=0x303, MR18=0x141F, DQSOSC=394, MR23=63, INC=23, DEC=15
9015 00:24:51.030562 [RxdqsGatingPostProcess] freq 1600
9016 00:24:51.037097 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9017 00:24:51.040412 best DQS0 dly(2T, 0.5T) = (1, 1)
9018 00:24:51.044303 best DQS1 dly(2T, 0.5T) = (1, 1)
9019 00:24:51.047558 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9020 00:24:51.050473 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9021 00:24:51.050554 best DQS0 dly(2T, 0.5T) = (1, 1)
9022 00:24:51.053967 best DQS1 dly(2T, 0.5T) = (1, 1)
9023 00:24:51.057633 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9024 00:24:51.060207 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9025 00:24:51.063885 Pre-setting of DQS Precalculation
9026 00:24:51.070386 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9027 00:24:51.076921 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9028 00:24:51.083630 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9029 00:24:51.083711
9030 00:24:51.083774
9031 00:24:51.086982 [Calibration Summary] 3200 Mbps
9032 00:24:51.087063 CH 0, Rank 0
9033 00:24:51.090513 SW Impedance : PASS
9034 00:24:51.093490 DUTY Scan : NO K
9035 00:24:51.093570 ZQ Calibration : PASS
9036 00:24:51.096870 Jitter Meter : NO K
9037 00:24:51.099854 CBT Training : PASS
9038 00:24:51.099935 Write leveling : PASS
9039 00:24:51.103623 RX DQS gating : PASS
9040 00:24:51.106838 RX DQ/DQS(RDDQC) : PASS
9041 00:24:51.106918 TX DQ/DQS : PASS
9042 00:24:51.109922 RX DATLAT : PASS
9043 00:24:51.113459 RX DQ/DQS(Engine): PASS
9044 00:24:51.113539 TX OE : PASS
9045 00:24:51.113603 All Pass.
9046 00:24:51.116631
9047 00:24:51.116711 CH 0, Rank 1
9048 00:24:51.120142 SW Impedance : PASS
9049 00:24:51.120223 DUTY Scan : NO K
9050 00:24:51.123251 ZQ Calibration : PASS
9051 00:24:51.126659 Jitter Meter : NO K
9052 00:24:51.126739 CBT Training : PASS
9053 00:24:51.130075 Write leveling : PASS
9054 00:24:51.130155 RX DQS gating : PASS
9055 00:24:51.133026 RX DQ/DQS(RDDQC) : PASS
9056 00:24:51.136560 TX DQ/DQS : PASS
9057 00:24:51.136641 RX DATLAT : PASS
9058 00:24:51.140006 RX DQ/DQS(Engine): PASS
9059 00:24:51.143072 TX OE : PASS
9060 00:24:51.143151 All Pass.
9061 00:24:51.143215
9062 00:24:51.143274 CH 1, Rank 0
9063 00:24:51.146140 SW Impedance : PASS
9064 00:24:51.149581 DUTY Scan : NO K
9065 00:24:51.149661 ZQ Calibration : PASS
9066 00:24:51.153132 Jitter Meter : NO K
9067 00:24:51.156495 CBT Training : PASS
9068 00:24:51.156576 Write leveling : PASS
9069 00:24:51.159641 RX DQS gating : PASS
9070 00:24:51.162998 RX DQ/DQS(RDDQC) : PASS
9071 00:24:51.163077 TX DQ/DQS : PASS
9072 00:24:51.166228 RX DATLAT : PASS
9073 00:24:51.169616 RX DQ/DQS(Engine): PASS
9074 00:24:51.169695 TX OE : PASS
9075 00:24:51.172624 All Pass.
9076 00:24:51.172704
9077 00:24:51.172767 CH 1, Rank 1
9078 00:24:51.176192 SW Impedance : PASS
9079 00:24:51.176273 DUTY Scan : NO K
9080 00:24:51.179943 ZQ Calibration : PASS
9081 00:24:51.182650 Jitter Meter : NO K
9082 00:24:51.182730 CBT Training : PASS
9083 00:24:51.186436 Write leveling : PASS
9084 00:24:51.186519 RX DQS gating : PASS
9085 00:24:51.189342 RX DQ/DQS(RDDQC) : PASS
9086 00:24:51.193136 TX DQ/DQS : PASS
9087 00:24:51.193230 RX DATLAT : PASS
9088 00:24:51.196032 RX DQ/DQS(Engine): PASS
9089 00:24:51.199283 TX OE : PASS
9090 00:24:51.199429 All Pass.
9091 00:24:51.199526
9092 00:24:51.202480 DramC Write-DBI on
9093 00:24:51.202562 PER_BANK_REFRESH: Hybrid Mode
9094 00:24:51.205907 TX_TRACKING: ON
9095 00:24:51.215938 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9096 00:24:51.222514 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9097 00:24:51.229158 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9098 00:24:51.232125 [FAST_K] Save calibration result to emmc
9099 00:24:51.235530 sync common calibartion params.
9100 00:24:51.238821 sync cbt_mode0:1, 1:1
9101 00:24:51.238932 dram_init: ddr_geometry: 2
9102 00:24:51.242358 dram_init: ddr_geometry: 2
9103 00:24:51.245460 dram_init: ddr_geometry: 2
9104 00:24:51.249014 0:dram_rank_size:100000000
9105 00:24:51.249101 1:dram_rank_size:100000000
9106 00:24:51.255158 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9107 00:24:51.258600 DFS_SHUFFLE_HW_MODE: ON
9108 00:24:51.262033 dramc_set_vcore_voltage set vcore to 725000
9109 00:24:51.265125 Read voltage for 1600, 0
9110 00:24:51.265232 Vio18 = 0
9111 00:24:51.265324 Vcore = 725000
9112 00:24:51.268690 Vdram = 0
9113 00:24:51.268798 Vddq = 0
9114 00:24:51.268890 Vmddr = 0
9115 00:24:51.271742 switch to 3200 Mbps bootup
9116 00:24:51.274928 [DramcRunTimeConfig]
9117 00:24:51.275015 PHYPLL
9118 00:24:51.275080 DPM_CONTROL_AFTERK: ON
9119 00:24:51.278696 PER_BANK_REFRESH: ON
9120 00:24:51.281784 REFRESH_OVERHEAD_REDUCTION: ON
9121 00:24:51.281866 CMD_PICG_NEW_MODE: OFF
9122 00:24:51.284943 XRTWTW_NEW_MODE: ON
9123 00:24:51.285065 XRTRTR_NEW_MODE: ON
9124 00:24:51.288205 TX_TRACKING: ON
9125 00:24:51.288326 RDSEL_TRACKING: OFF
9126 00:24:51.291582 DQS Precalculation for DVFS: ON
9127 00:24:51.294975 RX_TRACKING: OFF
9128 00:24:51.295062 HW_GATING DBG: ON
9129 00:24:51.298085 ZQCS_ENABLE_LP4: ON
9130 00:24:51.298167 RX_PICG_NEW_MODE: ON
9131 00:24:51.301426 TX_PICG_NEW_MODE: ON
9132 00:24:51.305067 ENABLE_RX_DCM_DPHY: ON
9133 00:24:51.305162 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9134 00:24:51.308070 DUMMY_READ_FOR_TRACKING: OFF
9135 00:24:51.311757 !!! SPM_CONTROL_AFTERK: OFF
9136 00:24:51.314888 !!! SPM could not control APHY
9137 00:24:51.314998 IMPEDANCE_TRACKING: ON
9138 00:24:51.318524 TEMP_SENSOR: ON
9139 00:24:51.318628 HW_SAVE_FOR_SR: OFF
9140 00:24:51.321416 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9141 00:24:51.328030 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9142 00:24:51.328145 Read ODT Tracking: ON
9143 00:24:51.331596 Refresh Rate DeBounce: ON
9144 00:24:51.331684 DFS_NO_QUEUE_FLUSH: ON
9145 00:24:51.334893 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9146 00:24:51.338326 ENABLE_DFS_RUNTIME_MRW: OFF
9147 00:24:51.341154 DDR_RESERVE_NEW_MODE: ON
9148 00:24:51.341240 MR_CBT_SWITCH_FREQ: ON
9149 00:24:51.344626 =========================
9150 00:24:51.364206 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9151 00:24:51.367715 dram_init: ddr_geometry: 2
9152 00:24:51.385763 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9153 00:24:51.388924 dram_init: dram init end (result: 0)
9154 00:24:51.395199 DRAM-K: Full calibration passed in 24545 msecs
9155 00:24:51.398848 MRC: failed to locate region type 0.
9156 00:24:51.398932 DRAM rank0 size:0x100000000,
9157 00:24:51.402274 DRAM rank1 size=0x100000000
9158 00:24:51.412251 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9159 00:24:51.418558 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9160 00:24:51.425144 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9161 00:24:51.435295 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9162 00:24:51.435405 DRAM rank0 size:0x100000000,
9163 00:24:51.438094 DRAM rank1 size=0x100000000
9164 00:24:51.438175 CBMEM:
9165 00:24:51.441984 IMD: root @ 0xfffff000 254 entries.
9166 00:24:51.445183 IMD: root @ 0xffffec00 62 entries.
9167 00:24:51.448882 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9168 00:24:51.454967 WARNING: RO_VPD is uninitialized or empty.
9169 00:24:51.457987 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9170 00:24:51.465708 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9171 00:24:51.478392 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9172 00:24:51.489660 BS: romstage times (exec / console): total (unknown) / 24014 ms
9173 00:24:51.489764
9174 00:24:51.489864
9175 00:24:51.499901 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9176 00:24:51.503054 ARM64: Exception handlers installed.
9177 00:24:51.506332 ARM64: Testing exception
9178 00:24:51.509609 ARM64: Done test exception
9179 00:24:51.509690 Enumerating buses...
9180 00:24:51.512993 Show all devs... Before device enumeration.
9181 00:24:51.515971 Root Device: enabled 1
9182 00:24:51.519834 CPU_CLUSTER: 0: enabled 1
9183 00:24:51.519915 CPU: 00: enabled 1
9184 00:24:51.523011 Compare with tree...
9185 00:24:51.523117 Root Device: enabled 1
9186 00:24:51.526280 CPU_CLUSTER: 0: enabled 1
9187 00:24:51.529546 CPU: 00: enabled 1
9188 00:24:51.529626 Root Device scanning...
9189 00:24:51.533108 scan_static_bus for Root Device
9190 00:24:51.536412 CPU_CLUSTER: 0 enabled
9191 00:24:51.539681 scan_static_bus for Root Device done
9192 00:24:51.542633 scan_bus: bus Root Device finished in 8 msecs
9193 00:24:51.542739 done
9194 00:24:51.549338 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9195 00:24:51.552692 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9196 00:24:51.559189 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9197 00:24:51.562405 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9198 00:24:51.565929 Allocating resources...
9199 00:24:51.569035 Reading resources...
9200 00:24:51.572665 Root Device read_resources bus 0 link: 0
9201 00:24:51.572746 DRAM rank0 size:0x100000000,
9202 00:24:51.576299 DRAM rank1 size=0x100000000
9203 00:24:51.578930 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9204 00:24:51.582428 CPU: 00 missing read_resources
9205 00:24:51.589281 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9206 00:24:51.592610 Root Device read_resources bus 0 link: 0 done
9207 00:24:51.592691 Done reading resources.
9208 00:24:51.598875 Show resources in subtree (Root Device)...After reading.
9209 00:24:51.602327 Root Device child on link 0 CPU_CLUSTER: 0
9210 00:24:51.605760 CPU_CLUSTER: 0 child on link 0 CPU: 00
9211 00:24:51.615658 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9212 00:24:51.615742 CPU: 00
9213 00:24:51.618923 Root Device assign_resources, bus 0 link: 0
9214 00:24:51.622086 CPU_CLUSTER: 0 missing set_resources
9215 00:24:51.629058 Root Device assign_resources, bus 0 link: 0 done
9216 00:24:51.629139 Done setting resources.
9217 00:24:51.635391 Show resources in subtree (Root Device)...After assigning values.
9218 00:24:51.639157 Root Device child on link 0 CPU_CLUSTER: 0
9219 00:24:51.642303 CPU_CLUSTER: 0 child on link 0 CPU: 00
9220 00:24:51.652080 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9221 00:24:51.652161 CPU: 00
9222 00:24:51.655240 Done allocating resources.
9223 00:24:51.662364 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9224 00:24:51.662445 Enabling resources...
9225 00:24:51.662509 done.
9226 00:24:51.668464 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9227 00:24:51.668544 Initializing devices...
9228 00:24:51.671901 Root Device init
9229 00:24:51.671981 init hardware done!
9230 00:24:51.675757 0x00000018: ctrlr->caps
9231 00:24:51.678339 52.000 MHz: ctrlr->f_max
9232 00:24:51.678421 0.400 MHz: ctrlr->f_min
9233 00:24:51.681915 0x40ff8080: ctrlr->voltages
9234 00:24:51.685499 sclk: 390625
9235 00:24:51.685579 Bus Width = 1
9236 00:24:51.685643 sclk: 390625
9237 00:24:51.688298 Bus Width = 1
9238 00:24:51.688378 Early init status = 3
9239 00:24:51.695117 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9240 00:24:51.698578 in-header: 03 fc 00 00 01 00 00 00
9241 00:24:51.698658 in-data: 00
9242 00:24:51.704976 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9243 00:24:51.708523 in-header: 03 fd 00 00 00 00 00 00
9244 00:24:51.712192 in-data:
9245 00:24:51.714859 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9246 00:24:51.718468 in-header: 03 fc 00 00 01 00 00 00
9247 00:24:51.721926 in-data: 00
9248 00:24:51.725099 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9249 00:24:51.729663 in-header: 03 fd 00 00 00 00 00 00
9250 00:24:51.732982 in-data:
9251 00:24:51.736398 [SSUSB] Setting up USB HOST controller...
9252 00:24:51.739926 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9253 00:24:51.742861 [SSUSB] phy power-on done.
9254 00:24:51.746278 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9255 00:24:51.753397 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9256 00:24:51.756134 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9257 00:24:51.763362 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9258 00:24:51.769445 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9259 00:24:51.776269 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9260 00:24:51.783281 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9261 00:24:51.789761 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9262 00:24:51.789842 SPM: binary array size = 0x9dc
9263 00:24:51.796515 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9264 00:24:51.802844 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9265 00:24:51.809804 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9266 00:24:51.813138 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9267 00:24:51.819407 configure_display: Starting display init
9268 00:24:51.852851 anx7625_power_on_init: Init interface.
9269 00:24:51.856458 anx7625_disable_pd_protocol: Disabled PD feature.
9270 00:24:51.859578 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9271 00:24:51.887748 anx7625_start_dp_work: Secure OCM version=00
9272 00:24:51.890553 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9273 00:24:51.905398 sp_tx_get_edid_block: EDID Block = 1
9274 00:24:52.008101 Extracted contents:
9275 00:24:52.011252 header: 00 ff ff ff ff ff ff 00
9276 00:24:52.014952 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9277 00:24:52.017721 version: 01 04
9278 00:24:52.021266 basic params: 95 1f 11 78 0a
9279 00:24:52.024394 chroma info: 76 90 94 55 54 90 27 21 50 54
9280 00:24:52.027846 established: 00 00 00
9281 00:24:52.034301 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9282 00:24:52.037828 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9283 00:24:52.044745 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9284 00:24:52.051008 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9285 00:24:52.057822 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9286 00:24:52.061337 extensions: 00
9287 00:24:52.061418 checksum: fb
9288 00:24:52.061481
9289 00:24:52.063902 Manufacturer: IVO Model 57d Serial Number 0
9290 00:24:52.067345 Made week 0 of 2020
9291 00:24:52.067451 EDID version: 1.4
9292 00:24:52.070900 Digital display
9293 00:24:52.073904 6 bits per primary color channel
9294 00:24:52.073985 DisplayPort interface
9295 00:24:52.077600 Maximum image size: 31 cm x 17 cm
9296 00:24:52.080652 Gamma: 220%
9297 00:24:52.080733 Check DPMS levels
9298 00:24:52.084105 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9299 00:24:52.091331 First detailed timing is preferred timing
9300 00:24:52.091429 Established timings supported:
9301 00:24:52.093860 Standard timings supported:
9302 00:24:52.097275 Detailed timings
9303 00:24:52.100824 Hex of detail: 383680a07038204018303c0035ae10000019
9304 00:24:52.104118 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9305 00:24:52.110620 0780 0798 07c8 0820 hborder 0
9306 00:24:52.114195 0438 043b 0447 0458 vborder 0
9307 00:24:52.117063 -hsync -vsync
9308 00:24:52.117143 Did detailed timing
9309 00:24:52.124053 Hex of detail: 000000000000000000000000000000000000
9310 00:24:52.127054 Manufacturer-specified data, tag 0
9311 00:24:52.130356 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9312 00:24:52.133706 ASCII string: InfoVision
9313 00:24:52.137304 Hex of detail: 000000fe00523134304e574635205248200a
9314 00:24:52.140749 ASCII string: R140NWF5 RH
9315 00:24:52.140828 Checksum
9316 00:24:52.143734 Checksum: 0xfb (valid)
9317 00:24:52.147266 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9318 00:24:52.150685 DSI data_rate: 832800000 bps
9319 00:24:52.156838 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9320 00:24:52.160293 anx7625_parse_edid: pixelclock(138800).
9321 00:24:52.163993 hactive(1920), hsync(48), hfp(24), hbp(88)
9322 00:24:52.166907 vactive(1080), vsync(12), vfp(3), vbp(17)
9323 00:24:52.170167 anx7625_dsi_config: config dsi.
9324 00:24:52.176887 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9325 00:24:52.190114 anx7625_dsi_config: success to config DSI
9326 00:24:52.193392 anx7625_dp_start: MIPI phy setup OK.
9327 00:24:52.196816 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9328 00:24:52.200221 mtk_ddp_mode_set invalid vrefresh 60
9329 00:24:52.204067 main_disp_path_setup
9330 00:24:52.204146 ovl_layer_smi_id_en
9331 00:24:52.206604 ovl_layer_smi_id_en
9332 00:24:52.206684 ccorr_config
9333 00:24:52.206750 aal_config
9334 00:24:52.210011 gamma_config
9335 00:24:52.210090 postmask_config
9336 00:24:52.213369 dither_config
9337 00:24:52.217107 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9338 00:24:52.223177 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9339 00:24:52.227054 Root Device init finished in 551 msecs
9340 00:24:52.229678 CPU_CLUSTER: 0 init
9341 00:24:52.236622 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9342 00:24:52.240150 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9343 00:24:52.243190 APU_MBOX 0x190000b0 = 0x10001
9344 00:24:52.246689 APU_MBOX 0x190001b0 = 0x10001
9345 00:24:52.249934 APU_MBOX 0x190005b0 = 0x10001
9346 00:24:52.253039 APU_MBOX 0x190006b0 = 0x10001
9347 00:24:52.256136 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9348 00:24:52.269242 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9349 00:24:52.281244 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9350 00:24:52.288065 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9351 00:24:52.300072 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9352 00:24:52.309031 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9353 00:24:52.312448 CPU_CLUSTER: 0 init finished in 81 msecs
9354 00:24:52.315380 Devices initialized
9355 00:24:52.318678 Show all devs... After init.
9356 00:24:52.318777 Root Device: enabled 1
9357 00:24:52.322376 CPU_CLUSTER: 0: enabled 1
9358 00:24:52.325592 CPU: 00: enabled 1
9359 00:24:52.328687 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9360 00:24:52.332165 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9361 00:24:52.335521 ELOG: NV offset 0x57f000 size 0x1000
9362 00:24:52.341683 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9363 00:24:52.348579 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9364 00:24:52.351970 ELOG: Event(17) added with size 13 at 2023-08-14 00:24:53 UTC
9365 00:24:52.358299 out: cmd=0x121: 03 db 21 01 00 00 00 00
9366 00:24:52.361587 in-header: 03 c4 00 00 2c 00 00 00
9367 00:24:52.372055 in-data: 9a 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9368 00:24:52.378306 ELOG: Event(A1) added with size 10 at 2023-08-14 00:24:53 UTC
9369 00:24:52.384888 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9370 00:24:52.391430 ELOG: Event(A0) added with size 9 at 2023-08-14 00:24:53 UTC
9371 00:24:52.394860 elog_add_boot_reason: Logged dev mode boot
9372 00:24:52.401467 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9373 00:24:52.401548 Finalize devices...
9374 00:24:52.404952 Devices finalized
9375 00:24:52.407851 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9376 00:24:52.411348 Writing coreboot table at 0xffe64000
9377 00:24:52.414969 0. 000000000010a000-0000000000113fff: RAMSTAGE
9378 00:24:52.418209 1. 0000000040000000-00000000400fffff: RAM
9379 00:24:52.424612 2. 0000000040100000-000000004032afff: RAMSTAGE
9380 00:24:52.427929 3. 000000004032b000-00000000545fffff: RAM
9381 00:24:52.431560 4. 0000000054600000-000000005465ffff: BL31
9382 00:24:52.434400 5. 0000000054660000-00000000ffe63fff: RAM
9383 00:24:52.441451 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9384 00:24:52.444855 7. 0000000100000000-000000023fffffff: RAM
9385 00:24:52.447687 Passing 5 GPIOs to payload:
9386 00:24:52.451123 NAME | PORT | POLARITY | VALUE
9387 00:24:52.454668 EC in RW | 0x000000aa | low | undefined
9388 00:24:52.460937 EC interrupt | 0x00000005 | low | undefined
9389 00:24:52.464693 TPM interrupt | 0x000000ab | high | undefined
9390 00:24:52.471037 SD card detect | 0x00000011 | high | undefined
9391 00:24:52.474429 speaker enable | 0x00000093 | high | undefined
9392 00:24:52.477663 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9393 00:24:52.481162 in-header: 03 f9 00 00 02 00 00 00
9394 00:24:52.484491 in-data: 02 00
9395 00:24:52.484571 ADC[4]: Raw value=895191 ID=7
9396 00:24:52.488468 ADC[3]: Raw value=212700 ID=1
9397 00:24:52.490720 RAM Code: 0x71
9398 00:24:52.494285 ADC[6]: Raw value=74722 ID=0
9399 00:24:52.494365 ADC[5]: Raw value=211590 ID=1
9400 00:24:52.497468 SKU Code: 0x1
9401 00:24:52.500556 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2dcf
9402 00:24:52.504296 coreboot table: 964 bytes.
9403 00:24:52.507741 IMD ROOT 0. 0xfffff000 0x00001000
9404 00:24:52.511002 IMD SMALL 1. 0xffffe000 0x00001000
9405 00:24:52.513658 RO MCACHE 2. 0xffffc000 0x00001104
9406 00:24:52.517514 CONSOLE 3. 0xfff7c000 0x00080000
9407 00:24:52.520627 FMAP 4. 0xfff7b000 0x00000452
9408 00:24:52.524220 TIME STAMP 5. 0xfff7a000 0x00000910
9409 00:24:52.527219 VBOOT WORK 6. 0xfff66000 0x00014000
9410 00:24:52.530773 RAMOOPS 7. 0xffe66000 0x00100000
9411 00:24:52.534241 COREBOOT 8. 0xffe64000 0x00002000
9412 00:24:52.536955 IMD small region:
9413 00:24:52.540298 IMD ROOT 0. 0xffffec00 0x00000400
9414 00:24:52.543672 VPD 1. 0xffffeba0 0x0000004c
9415 00:24:52.546875 MMC STATUS 2. 0xffffeb80 0x00000004
9416 00:24:52.550197 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9417 00:24:52.553510 Probing TPM: done!
9418 00:24:52.557605 Connected to device vid:did:rid of 1ae0:0028:00
9419 00:24:52.567614 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9420 00:24:52.571337 Initialized TPM device CR50 revision 0
9421 00:24:52.574968 Checking cr50 for pending updates
9422 00:24:52.578545 Reading cr50 TPM mode
9423 00:24:52.587169 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9424 00:24:52.593895 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9425 00:24:52.633566 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9426 00:24:52.637104 Checking segment from ROM address 0x40100000
9427 00:24:52.640554 Checking segment from ROM address 0x4010001c
9428 00:24:52.646996 Loading segment from ROM address 0x40100000
9429 00:24:52.647078 code (compression=0)
9430 00:24:52.657246 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9431 00:24:52.663915 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9432 00:24:52.663996 it's not compressed!
9433 00:24:52.670256 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9434 00:24:52.677386 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9435 00:24:52.694025 Loading segment from ROM address 0x4010001c
9436 00:24:52.694108 Entry Point 0x80000000
9437 00:24:52.698072 Loaded segments
9438 00:24:52.700739 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9439 00:24:52.707313 Jumping to boot code at 0x80000000(0xffe64000)
9440 00:24:52.714111 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9441 00:24:52.721013 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9442 00:24:52.728713 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9443 00:24:52.732055 Checking segment from ROM address 0x40100000
9444 00:24:52.735260 Checking segment from ROM address 0x4010001c
9445 00:24:52.742323 Loading segment from ROM address 0x40100000
9446 00:24:52.742403 code (compression=1)
9447 00:24:52.748681 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9448 00:24:52.758893 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9449 00:24:52.758973 using LZMA
9450 00:24:52.766861 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9451 00:24:52.773960 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9452 00:24:52.777362 Loading segment from ROM address 0x4010001c
9453 00:24:52.777443 Entry Point 0x54601000
9454 00:24:52.780073 Loaded segments
9455 00:24:52.783595 NOTICE: MT8192 bl31_setup
9456 00:24:52.790414 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9457 00:24:52.793681 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9458 00:24:52.797398 WARNING: region 0:
9459 00:24:52.800590 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9460 00:24:52.800670 WARNING: region 1:
9461 00:24:52.806958 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9462 00:24:52.810621 WARNING: region 2:
9463 00:24:52.814282 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9464 00:24:52.817274 WARNING: region 3:
9465 00:24:52.820765 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9466 00:24:52.823755 WARNING: region 4:
9467 00:24:52.830284 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9468 00:24:52.830360 WARNING: region 5:
9469 00:24:52.833900 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9470 00:24:52.837047 WARNING: region 6:
9471 00:24:52.840835 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 00:24:52.843625 WARNING: region 7:
9473 00:24:52.846963 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 00:24:52.854003 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9475 00:24:52.856836 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9476 00:24:52.860223 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9477 00:24:52.866818 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9478 00:24:52.870696 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9479 00:24:52.873877 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9480 00:24:52.880138 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9481 00:24:52.883987 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9482 00:24:52.890257 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9483 00:24:52.893812 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9484 00:24:52.897135 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9485 00:24:52.903623 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9486 00:24:52.906875 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9487 00:24:52.910616 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9488 00:24:52.917086 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9489 00:24:52.920648 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9490 00:24:52.927709 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9491 00:24:52.930374 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9492 00:24:52.933918 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9493 00:24:52.940486 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9494 00:24:52.943562 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9495 00:24:52.946947 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9496 00:24:52.953606 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9497 00:24:52.956942 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9498 00:24:52.963493 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9499 00:24:52.966845 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9500 00:24:52.970301 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9501 00:24:52.977045 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9502 00:24:52.980373 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9503 00:24:52.987068 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9504 00:24:52.990740 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9505 00:24:52.993830 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9506 00:24:53.000580 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9507 00:24:53.003879 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9508 00:24:53.007362 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9509 00:24:53.010248 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9510 00:24:53.016947 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9511 00:24:53.020354 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9512 00:24:53.023619 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9513 00:24:53.026912 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9514 00:24:53.033696 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9515 00:24:53.037037 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9516 00:24:53.040115 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9517 00:24:53.043634 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9518 00:24:53.050098 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9519 00:24:53.054102 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9520 00:24:53.057320 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9521 00:24:53.060674 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9522 00:24:53.067158 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9523 00:24:53.070513 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9524 00:24:53.077087 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9525 00:24:53.080942 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9526 00:24:53.083823 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9527 00:24:53.090655 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9528 00:24:53.093961 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9529 00:24:53.100184 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9530 00:24:53.103558 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9531 00:24:53.110575 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9532 00:24:53.113435 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9533 00:24:53.120243 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9534 00:24:53.123751 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9535 00:24:53.127107 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9536 00:24:53.133447 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9537 00:24:53.136970 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9538 00:24:53.143537 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9539 00:24:53.147234 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9540 00:24:53.153625 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9541 00:24:53.156783 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9542 00:24:53.159956 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9543 00:24:53.166928 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9544 00:24:53.170323 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9545 00:24:53.177035 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9546 00:24:53.180224 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9547 00:24:53.186605 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9548 00:24:53.190145 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9549 00:24:53.193804 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9550 00:24:53.200128 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9551 00:24:53.203246 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9552 00:24:53.210394 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9553 00:24:53.213823 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9554 00:24:53.220332 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9555 00:24:53.223477 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9556 00:24:53.229973 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9557 00:24:53.233580 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9558 00:24:53.237042 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9559 00:24:53.243833 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9560 00:24:53.246732 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9561 00:24:53.253391 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9562 00:24:53.256852 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9563 00:24:53.260123 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9564 00:24:53.267230 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9565 00:24:53.270369 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9566 00:24:53.276805 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9567 00:24:53.280518 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9568 00:24:53.286795 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9569 00:24:53.290280 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9570 00:24:53.293723 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9571 00:24:53.300794 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9572 00:24:53.303951 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9573 00:24:53.306936 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9574 00:24:53.310717 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9575 00:24:53.317054 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9576 00:24:53.320378 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9577 00:24:53.326795 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9578 00:24:53.330642 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9579 00:24:53.334040 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9580 00:24:53.340294 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9581 00:24:53.344050 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9582 00:24:53.350589 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9583 00:24:53.353767 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9584 00:24:53.357204 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9585 00:24:53.363708 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9586 00:24:53.367483 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9587 00:24:53.373508 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9588 00:24:53.377147 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9589 00:24:53.380193 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9590 00:24:53.383739 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9591 00:24:53.390286 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9592 00:24:53.393668 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9593 00:24:53.397346 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9594 00:24:53.403640 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9595 00:24:53.407067 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9596 00:24:53.410292 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9597 00:24:53.413862 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9598 00:24:53.420258 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9599 00:24:53.423999 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9600 00:24:53.427341 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9601 00:24:53.433974 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9602 00:24:53.437514 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9603 00:24:53.443676 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9604 00:24:53.447245 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9605 00:24:53.450879 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9606 00:24:53.457062 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9607 00:24:53.460459 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9608 00:24:53.467234 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9609 00:24:53.470298 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9610 00:24:53.473988 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9611 00:24:53.481038 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9612 00:24:53.484179 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9613 00:24:53.486870 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9614 00:24:53.493920 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9615 00:24:53.496795 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9616 00:24:53.503405 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9617 00:24:53.507213 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9618 00:24:53.510576 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9619 00:24:53.517178 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9620 00:24:53.520637 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9621 00:24:53.526628 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9622 00:24:53.530228 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9623 00:24:53.533621 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9624 00:24:53.540131 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9625 00:24:53.543886 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9626 00:24:53.550260 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9627 00:24:53.553631 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9628 00:24:53.557088 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9629 00:24:53.563381 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9630 00:24:53.566998 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9631 00:24:53.573682 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9632 00:24:53.576876 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9633 00:24:53.580172 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9634 00:24:53.586556 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9635 00:24:53.590238 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9636 00:24:53.593838 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9637 00:24:53.599928 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9638 00:24:53.603281 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9639 00:24:53.610031 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9640 00:24:53.613258 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9641 00:24:53.616560 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9642 00:24:53.623037 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9643 00:24:53.626253 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9644 00:24:53.633119 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9645 00:24:53.636290 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9646 00:24:53.639833 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9647 00:24:53.646845 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9648 00:24:53.649654 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9649 00:24:53.656431 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9650 00:24:53.659633 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9651 00:24:53.662827 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9652 00:24:53.669299 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9653 00:24:53.672804 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9654 00:24:53.679995 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9655 00:24:53.682978 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9656 00:24:53.685975 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9657 00:24:53.692686 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9658 00:24:53.695939 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9659 00:24:53.702392 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9660 00:24:53.705869 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9661 00:24:53.709214 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9662 00:24:53.715711 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9663 00:24:53.718921 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9664 00:24:53.726001 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9665 00:24:53.728882 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9666 00:24:53.735752 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9667 00:24:53.738970 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9668 00:24:53.742589 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9669 00:24:53.749006 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9670 00:24:53.752085 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9671 00:24:53.758985 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9672 00:24:53.762084 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9673 00:24:53.765221 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9674 00:24:53.772116 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9675 00:24:53.775106 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9676 00:24:53.782052 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9677 00:24:53.785601 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9678 00:24:53.791684 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9679 00:24:53.794967 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9680 00:24:53.798513 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9681 00:24:53.805116 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9682 00:24:53.808215 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9683 00:24:53.814943 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9684 00:24:53.818688 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9685 00:24:53.821753 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9686 00:24:53.828264 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9687 00:24:53.831834 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9688 00:24:53.838182 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9689 00:24:53.841598 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9690 00:24:53.848187 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9691 00:24:53.852004 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9692 00:24:53.854601 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9693 00:24:53.861592 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9694 00:24:53.864917 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9695 00:24:53.871188 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9696 00:24:53.874688 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9697 00:24:53.878364 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9698 00:24:53.885001 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9699 00:24:53.888203 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9700 00:24:53.895166 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9701 00:24:53.898494 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9702 00:24:53.905001 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9703 00:24:53.908097 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9704 00:24:53.911155 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9705 00:24:53.914845 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9706 00:24:53.917643 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9707 00:24:53.925194 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9708 00:24:53.928293 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9709 00:24:53.931136 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9710 00:24:53.937834 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9711 00:24:53.941116 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9712 00:24:53.944433 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9713 00:24:53.951772 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9714 00:24:53.954631 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9715 00:24:53.960978 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9716 00:24:53.964917 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9717 00:24:53.968011 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9718 00:24:53.974443 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9719 00:24:53.977817 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9720 00:24:53.981277 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9721 00:24:53.987733 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9722 00:24:53.991160 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9723 00:24:53.994415 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9724 00:24:54.001087 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9725 00:24:54.004451 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9726 00:24:54.011115 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9727 00:24:54.014406 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9728 00:24:54.017890 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9729 00:24:54.024299 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9730 00:24:54.027460 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9731 00:24:54.034413 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9732 00:24:54.037356 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9733 00:24:54.040620 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9734 00:24:54.047491 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9735 00:24:54.050994 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9736 00:24:54.054223 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9737 00:24:54.060949 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9738 00:24:54.064273 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9739 00:24:54.067359 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9740 00:24:54.074150 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9741 00:24:54.077446 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9742 00:24:54.080670 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9743 00:24:54.087108 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9744 00:24:54.090803 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9745 00:24:54.094068 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9746 00:24:54.097272 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9747 00:24:54.100537 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9748 00:24:54.107161 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9749 00:24:54.110838 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9750 00:24:54.113808 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9751 00:24:54.120758 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9752 00:24:54.123876 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9753 00:24:54.127098 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9754 00:24:54.130361 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9755 00:24:54.137143 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9756 00:24:54.140174 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9757 00:24:54.147013 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9758 00:24:54.150814 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9759 00:24:54.153916 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9760 00:24:54.160141 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9761 00:24:54.163888 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9762 00:24:54.170079 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9763 00:24:54.173684 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9764 00:24:54.176684 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9765 00:24:54.184013 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9766 00:24:54.186934 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9767 00:24:54.193568 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9768 00:24:54.196911 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9769 00:24:54.200015 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9770 00:24:54.206583 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9771 00:24:54.210268 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9772 00:24:54.216621 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9773 00:24:54.220141 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9774 00:24:54.223743 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9775 00:24:54.229898 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9776 00:24:54.233078 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9777 00:24:54.240277 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9778 00:24:54.243204 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9779 00:24:54.246486 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9780 00:24:54.253578 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9781 00:24:54.256638 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9782 00:24:54.263281 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9783 00:24:54.266304 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9784 00:24:54.273199 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9785 00:24:54.276534 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9786 00:24:54.280230 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9787 00:24:54.286199 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9788 00:24:54.289613 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9789 00:24:54.296037 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9790 00:24:54.299435 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9791 00:24:54.302853 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9792 00:24:54.309600 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9793 00:24:54.313134 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9794 00:24:54.319810 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9795 00:24:54.323270 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9796 00:24:54.326152 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9797 00:24:54.332654 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9798 00:24:54.336183 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9799 00:24:54.342874 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9800 00:24:54.346037 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9801 00:24:54.352811 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9802 00:24:54.356080 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9803 00:24:54.359270 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9804 00:24:54.365813 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9805 00:24:54.368896 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9806 00:24:54.375571 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9807 00:24:54.379094 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9808 00:24:54.382366 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9809 00:24:54.389000 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9810 00:24:54.392849 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9811 00:24:54.398866 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9812 00:24:54.402003 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9813 00:24:54.405892 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9814 00:24:54.412163 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9815 00:24:54.415555 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9816 00:24:54.422001 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9817 00:24:54.425396 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9818 00:24:54.431842 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9819 00:24:54.434981 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9820 00:24:54.438682 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9821 00:24:54.445142 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9822 00:24:54.448088 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9823 00:24:54.454614 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9824 00:24:54.458337 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9825 00:24:54.464801 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9826 00:24:54.468275 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9827 00:24:54.471528 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9828 00:24:54.478236 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9829 00:24:54.481157 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9830 00:24:54.487882 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9831 00:24:54.491110 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9832 00:24:54.497974 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9833 00:24:54.501495 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9834 00:24:54.504313 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9835 00:24:54.511399 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9836 00:24:54.514432 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9837 00:24:54.520860 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9838 00:24:54.523925 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9839 00:24:54.530698 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9840 00:24:54.533909 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9841 00:24:54.540914 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9842 00:24:54.544306 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9843 00:24:54.547739 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9844 00:24:54.554247 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9845 00:24:54.557367 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9846 00:24:54.564037 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9847 00:24:54.567182 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9848 00:24:54.573863 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9849 00:24:54.577058 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9850 00:24:54.583737 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9851 00:24:54.586915 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9852 00:24:54.590086 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9853 00:24:54.597109 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9854 00:24:54.600525 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9855 00:24:54.607027 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9856 00:24:54.610031 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9857 00:24:54.616962 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9858 00:24:54.620272 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9859 00:24:54.623306 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9860 00:24:54.630326 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9861 00:24:54.633293 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9862 00:24:54.640101 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9863 00:24:54.643556 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9864 00:24:54.649962 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9865 00:24:54.653121 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9866 00:24:54.659585 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9867 00:24:54.663322 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9868 00:24:54.666217 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9869 00:24:54.673066 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9870 00:24:54.676705 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9871 00:24:54.683120 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9872 00:24:54.686149 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9873 00:24:54.693106 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9874 00:24:54.696584 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9875 00:24:54.699957 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9876 00:24:54.706971 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9877 00:24:54.710243 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9878 00:24:54.716453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9879 00:24:54.719364 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9880 00:24:54.726329 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9881 00:24:54.729910 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9882 00:24:54.736124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9883 00:24:54.739343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9884 00:24:54.743149 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9885 00:24:54.749868 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9886 00:24:54.752490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9887 00:24:54.759184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9888 00:24:54.762618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9889 00:24:54.769575 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9890 00:24:54.772402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9891 00:24:54.779494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9892 00:24:54.782391 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9893 00:24:54.789553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9894 00:24:54.792436 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9895 00:24:54.798958 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9896 00:24:54.802328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9897 00:24:54.809531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9898 00:24:54.812257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9899 00:24:54.818984 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9900 00:24:54.822145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9901 00:24:54.829118 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9902 00:24:54.832075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9903 00:24:54.838874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9904 00:24:54.842288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9905 00:24:54.848584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9906 00:24:54.851985 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9907 00:24:54.858925 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9908 00:24:54.862050 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9909 00:24:54.865659 INFO: [APUAPC] vio 0
9910 00:24:54.868659 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9911 00:24:54.875275 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9912 00:24:54.878584 INFO: [APUAPC] D0_APC_0: 0x400510
9913 00:24:54.881945 INFO: [APUAPC] D0_APC_1: 0x0
9914 00:24:54.882013 INFO: [APUAPC] D0_APC_2: 0x1540
9915 00:24:54.885307 INFO: [APUAPC] D0_APC_3: 0x0
9916 00:24:54.888885 INFO: [APUAPC] D1_APC_0: 0xffffffff
9917 00:24:54.892154 INFO: [APUAPC] D1_APC_1: 0xffffffff
9918 00:24:54.895081 INFO: [APUAPC] D1_APC_2: 0x3fffff
9919 00:24:54.898932 INFO: [APUAPC] D1_APC_3: 0x0
9920 00:24:54.902384 INFO: [APUAPC] D2_APC_0: 0xffffffff
9921 00:24:54.905346 INFO: [APUAPC] D2_APC_1: 0xffffffff
9922 00:24:54.908612 INFO: [APUAPC] D2_APC_2: 0x3fffff
9923 00:24:54.912279 INFO: [APUAPC] D2_APC_3: 0x0
9924 00:24:54.915117 INFO: [APUAPC] D3_APC_0: 0xffffffff
9925 00:24:54.918611 INFO: [APUAPC] D3_APC_1: 0xffffffff
9926 00:24:54.921931 INFO: [APUAPC] D3_APC_2: 0x3fffff
9927 00:24:54.924937 INFO: [APUAPC] D3_APC_3: 0x0
9928 00:24:54.928785 INFO: [APUAPC] D4_APC_0: 0xffffffff
9929 00:24:54.932209 INFO: [APUAPC] D4_APC_1: 0xffffffff
9930 00:24:54.935046 INFO: [APUAPC] D4_APC_2: 0x3fffff
9931 00:24:54.938590 INFO: [APUAPC] D4_APC_3: 0x0
9932 00:24:54.941684 INFO: [APUAPC] D5_APC_0: 0xffffffff
9933 00:24:54.945393 INFO: [APUAPC] D5_APC_1: 0xffffffff
9934 00:24:54.948478 INFO: [APUAPC] D5_APC_2: 0x3fffff
9935 00:24:54.951679 INFO: [APUAPC] D5_APC_3: 0x0
9936 00:24:54.955164 INFO: [APUAPC] D6_APC_0: 0xffffffff
9937 00:24:54.958044 INFO: [APUAPC] D6_APC_1: 0xffffffff
9938 00:24:54.961417 INFO: [APUAPC] D6_APC_2: 0x3fffff
9939 00:24:54.964674 INFO: [APUAPC] D6_APC_3: 0x0
9940 00:24:54.968098 INFO: [APUAPC] D7_APC_0: 0xffffffff
9941 00:24:54.971531 INFO: [APUAPC] D7_APC_1: 0xffffffff
9942 00:24:54.975166 INFO: [APUAPC] D7_APC_2: 0x3fffff
9943 00:24:54.977995 INFO: [APUAPC] D7_APC_3: 0x0
9944 00:24:54.981561 INFO: [APUAPC] D8_APC_0: 0xffffffff
9945 00:24:54.984874 INFO: [APUAPC] D8_APC_1: 0xffffffff
9946 00:24:54.988264 INFO: [APUAPC] D8_APC_2: 0x3fffff
9947 00:24:54.991174 INFO: [APUAPC] D8_APC_3: 0x0
9948 00:24:54.994620 INFO: [APUAPC] D9_APC_0: 0xffffffff
9949 00:24:54.997998 INFO: [APUAPC] D9_APC_1: 0xffffffff
9950 00:24:55.001120 INFO: [APUAPC] D9_APC_2: 0x3fffff
9951 00:24:55.004966 INFO: [APUAPC] D9_APC_3: 0x0
9952 00:24:55.008244 INFO: [APUAPC] D10_APC_0: 0xffffffff
9953 00:24:55.011321 INFO: [APUAPC] D10_APC_1: 0xffffffff
9954 00:24:55.014572 INFO: [APUAPC] D10_APC_2: 0x3fffff
9955 00:24:55.018097 INFO: [APUAPC] D10_APC_3: 0x0
9956 00:24:55.021000 INFO: [APUAPC] D11_APC_0: 0xffffffff
9957 00:24:55.024483 INFO: [APUAPC] D11_APC_1: 0xffffffff
9958 00:24:55.027970 INFO: [APUAPC] D11_APC_2: 0x3fffff
9959 00:24:55.031349 INFO: [APUAPC] D11_APC_3: 0x0
9960 00:24:55.034482 INFO: [APUAPC] D12_APC_0: 0xffffffff
9961 00:24:55.037633 INFO: [APUAPC] D12_APC_1: 0xffffffff
9962 00:24:55.041088 INFO: [APUAPC] D12_APC_2: 0x3fffff
9963 00:24:55.044321 INFO: [APUAPC] D12_APC_3: 0x0
9964 00:24:55.047889 INFO: [APUAPC] D13_APC_0: 0xffffffff
9965 00:24:55.051100 INFO: [APUAPC] D13_APC_1: 0xffffffff
9966 00:24:55.054453 INFO: [APUAPC] D13_APC_2: 0x3fffff
9967 00:24:55.057826 INFO: [APUAPC] D13_APC_3: 0x0
9968 00:24:55.061239 INFO: [APUAPC] D14_APC_0: 0xffffffff
9969 00:24:55.064222 INFO: [APUAPC] D14_APC_1: 0xffffffff
9970 00:24:55.068067 INFO: [APUAPC] D14_APC_2: 0x3fffff
9971 00:24:55.070888 INFO: [APUAPC] D14_APC_3: 0x0
9972 00:24:55.074321 INFO: [APUAPC] D15_APC_0: 0xffffffff
9973 00:24:55.077895 INFO: [APUAPC] D15_APC_1: 0xffffffff
9974 00:24:55.081301 INFO: [APUAPC] D15_APC_2: 0x3fffff
9975 00:24:55.084720 INFO: [APUAPC] D15_APC_3: 0x0
9976 00:24:55.087738 INFO: [APUAPC] APC_CON: 0x4
9977 00:24:55.087811 INFO: [NOCDAPC] D0_APC_0: 0x0
9978 00:24:55.090850 INFO: [NOCDAPC] D0_APC_1: 0x0
9979 00:24:55.094329 INFO: [NOCDAPC] D1_APC_0: 0x0
9980 00:24:55.097993 INFO: [NOCDAPC] D1_APC_1: 0xfff
9981 00:24:55.100650 INFO: [NOCDAPC] D2_APC_0: 0x0
9982 00:24:55.104203 INFO: [NOCDAPC] D2_APC_1: 0xfff
9983 00:24:55.107586 INFO: [NOCDAPC] D3_APC_0: 0x0
9984 00:24:55.110726 INFO: [NOCDAPC] D3_APC_1: 0xfff
9985 00:24:55.113853 INFO: [NOCDAPC] D4_APC_0: 0x0
9986 00:24:55.117216 INFO: [NOCDAPC] D4_APC_1: 0xfff
9987 00:24:55.120600 INFO: [NOCDAPC] D5_APC_0: 0x0
9988 00:24:55.120671 INFO: [NOCDAPC] D5_APC_1: 0xfff
9989 00:24:55.124223 INFO: [NOCDAPC] D6_APC_0: 0x0
9990 00:24:55.127584 INFO: [NOCDAPC] D6_APC_1: 0xfff
9991 00:24:55.130571 INFO: [NOCDAPC] D7_APC_0: 0x0
9992 00:24:55.134207 INFO: [NOCDAPC] D7_APC_1: 0xfff
9993 00:24:55.137763 INFO: [NOCDAPC] D8_APC_0: 0x0
9994 00:24:55.140390 INFO: [NOCDAPC] D8_APC_1: 0xfff
9995 00:24:55.143890 INFO: [NOCDAPC] D9_APC_0: 0x0
9996 00:24:55.147484 INFO: [NOCDAPC] D9_APC_1: 0xfff
9997 00:24:55.150429 INFO: [NOCDAPC] D10_APC_0: 0x0
9998 00:24:55.153963 INFO: [NOCDAPC] D10_APC_1: 0xfff
9999 00:24:55.157157 INFO: [NOCDAPC] D11_APC_0: 0x0
10000 00:24:55.160576 INFO: [NOCDAPC] D11_APC_1: 0xfff
10001 00:24:55.160646 INFO: [NOCDAPC] D12_APC_0: 0x0
10002 00:24:55.163552 INFO: [NOCDAPC] D12_APC_1: 0xfff
10003 00:24:55.167195 INFO: [NOCDAPC] D13_APC_0: 0x0
10004 00:24:55.170547 INFO: [NOCDAPC] D13_APC_1: 0xfff
10005 00:24:55.173304 INFO: [NOCDAPC] D14_APC_0: 0x0
10006 00:24:55.176698 INFO: [NOCDAPC] D14_APC_1: 0xfff
10007 00:24:55.180130 INFO: [NOCDAPC] D15_APC_0: 0x0
10008 00:24:55.183935 INFO: [NOCDAPC] D15_APC_1: 0xfff
10009 00:24:55.186581 INFO: [NOCDAPC] APC_CON: 0x4
10010 00:24:55.189970 INFO: [APUAPC] set_apusys_apc done
10011 00:24:55.193386 INFO: [DEVAPC] devapc_init done
10012 00:24:55.196708 INFO: GICv3 without legacy support detected.
10013 00:24:55.200186 INFO: ARM GICv3 driver initialized in EL3
10014 00:24:55.203605 INFO: Maximum SPI INTID supported: 639
10015 00:24:55.209992 INFO: BL31: Initializing runtime services
10016 00:24:55.213498 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10017 00:24:55.216903 INFO: SPM: enable CPC mode
10018 00:24:55.223776 INFO: mcdi ready for mcusys-off-idle and system suspend
10019 00:24:55.226646 INFO: BL31: Preparing for EL3 exit to normal world
10020 00:24:55.230053 INFO: Entry point address = 0x80000000
10021 00:24:55.233359 INFO: SPSR = 0x8
10022 00:24:55.238464
10023 00:24:55.238533
10024 00:24:55.238597
10025 00:24:55.241925 Starting depthcharge on Spherion...
10026 00:24:55.242038
10027 00:24:55.242138 Wipe memory regions:
10028 00:24:55.242235
10029 00:24:55.243090 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10030 00:24:55.243229 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10031 00:24:55.243348 Setting prompt string to ['asurada:']
10032 00:24:55.243469 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10033 00:24:55.244899 [0x00000040000000, 0x00000054600000)
10034 00:24:55.367293
10035 00:24:55.367517 [0x00000054660000, 0x00000080000000)
10036 00:24:55.628123
10037 00:24:55.628324 [0x000000821a7280, 0x000000ffe64000)
10038 00:24:56.372900
10039 00:24:56.373049 [0x00000100000000, 0x00000240000000)
10040 00:24:58.262951
10041 00:24:58.266347 Initializing XHCI USB controller at 0x11200000.
10042 00:24:59.303861
10043 00:24:59.307056 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10044 00:24:59.307146
10045 00:24:59.307210
10046 00:24:59.307269
10047 00:24:59.307537 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10049 00:24:59.407868 asurada: tftpboot 192.168.201.1 11280974/tftp-deploy-im_133ae/kernel/image.itb 11280974/tftp-deploy-im_133ae/kernel/cmdline
10050 00:24:59.408038 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10051 00:24:59.408144 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10052 00:24:59.412721 tftpboot 192.168.201.1 11280974/tftp-deploy-im_133ae/kernel/image.itbtp-deploy-im_133ae/kernel/cmdline
10053 00:24:59.412830
10054 00:24:59.412904 Waiting for link
10055 00:24:59.573510
10056 00:24:59.573645 R8152: Initializing
10057 00:24:59.573715
10058 00:24:59.576506 Version 6 (ocp_data = 5c30)
10059 00:24:59.576577
10060 00:24:59.579696 R8152: Done initializing
10061 00:24:59.579765
10062 00:24:59.579825 Adding net device
10063 00:25:01.483616
10064 00:25:01.483762 done.
10065 00:25:01.483832
10066 00:25:01.483892 MAC: 00:24:32:30:78:ff
10067 00:25:01.483950
10068 00:25:01.486626 Sending DHCP discover... done.
10069 00:25:01.486697
10070 00:25:04.968391 Waiting for reply... done.
10071 00:25:04.968681
10072 00:25:04.968899 Sending DHCP request... done.
10073 00:25:04.972008
10074 00:25:04.975659 Waiting for reply... done.
10075 00:25:04.975890
10076 00:25:04.976089 My ip is 192.168.201.21
10077 00:25:04.976280
10078 00:25:04.978844 The DHCP server ip is 192.168.201.1
10079 00:25:04.979020
10080 00:25:04.985381 TFTP server IP predefined by user: 192.168.201.1
10081 00:25:04.985641
10082 00:25:04.992126 Bootfile predefined by user: 11280974/tftp-deploy-im_133ae/kernel/image.itb
10083 00:25:04.992232
10084 00:25:04.995211 Sending tftp read request... done.
10085 00:25:04.995323
10086 00:25:04.998714 Waiting for the transfer...
10087 00:25:04.998815
10088 00:25:05.588413 00000000 ################################################################
10089 00:25:05.588569
10090 00:25:06.162018 00080000 ################################################################
10091 00:25:06.162542
10092 00:25:06.862401 00100000 ################################################################
10093 00:25:06.862536
10094 00:25:07.506347 00180000 ################################################################
10095 00:25:07.506478
10096 00:25:08.069040 00200000 ################################################################
10097 00:25:08.069199
10098 00:25:08.665511 00280000 ################################################################
10099 00:25:08.665666
10100 00:25:09.296827 00300000 ################################################################
10101 00:25:09.297330
10102 00:25:09.989102 00380000 ################################################################
10103 00:25:09.989597
10104 00:25:10.656550 00400000 ################################################################
10105 00:25:10.657047
10106 00:25:11.352013 00480000 ################################################################
10107 00:25:11.352535
10108 00:25:12.071976 00500000 ################################################################
10109 00:25:12.072542
10110 00:25:12.701830 00580000 ################################################################
10111 00:25:12.701972
10112 00:25:13.274602 00600000 ################################################################
10113 00:25:13.274746
10114 00:25:13.847689 00680000 ################################################################
10115 00:25:13.847846
10116 00:25:14.421414 00700000 ################################################################
10117 00:25:14.421583
10118 00:25:14.988715 00780000 ################################################################
10119 00:25:14.988860
10120 00:25:15.542261 00800000 ################################################################
10121 00:25:15.542423
10122 00:25:16.093726 00880000 ################################################################
10123 00:25:16.093872
10124 00:25:16.633569 00900000 ################################################################
10125 00:25:16.633740
10126 00:25:17.180758 00980000 ################################################################
10127 00:25:17.180903
10128 00:25:17.738058 00a00000 ################################################################
10129 00:25:17.738206
10130 00:25:18.294875 00a80000 ################################################################
10131 00:25:18.295018
10132 00:25:18.830623 00b00000 ################################################################
10133 00:25:18.830768
10134 00:25:19.385064 00b80000 ################################################################
10135 00:25:19.385233
10136 00:25:19.925500 00c00000 ################################################################
10137 00:25:19.925633
10138 00:25:20.558014 00c80000 ################################################################
10139 00:25:20.558547
10140 00:25:21.246603 00d00000 ################################################################
10141 00:25:21.247096
10142 00:25:21.858337 00d80000 ################################################################
10143 00:25:21.858500
10144 00:25:22.460742 00e00000 ################################################################
10145 00:25:22.460874
10146 00:25:23.061501 00e80000 ################################################################
10147 00:25:23.061663
10148 00:25:23.663902 00f00000 ################################################################
10149 00:25:23.664036
10150 00:25:24.287676 00f80000 ################################################################
10151 00:25:24.287829
10152 00:25:25.029580 01000000 ################################################################
10153 00:25:25.030190
10154 00:25:25.745543 01080000 ################################################################
10155 00:25:25.746171
10156 00:25:26.459360 01100000 ################################################################
10157 00:25:26.459877
10158 00:25:27.172793 01180000 ################################################################
10159 00:25:27.173284
10160 00:25:27.811513 01200000 ################################################################
10161 00:25:27.811992
10162 00:25:28.500008 01280000 ################################################################
10163 00:25:28.500527
10164 00:25:29.147808 01300000 ################################################################
10165 00:25:29.147953
10166 00:25:29.718963 01380000 ################################################################
10167 00:25:29.719096
10168 00:25:30.362007 01400000 ################################################################
10169 00:25:30.362510
10170 00:25:30.972094 01480000 ################################################################
10171 00:25:30.972229
10172 00:25:31.536707 01500000 ################################################################
10173 00:25:31.536878
10174 00:25:32.069090 01580000 ################################################################
10175 00:25:32.069237
10176 00:25:32.602333 01600000 ################################################################
10177 00:25:32.602546
10178 00:25:33.148869 01680000 ################################################################
10179 00:25:33.149019
10180 00:25:33.755442 01700000 ################################################################
10181 00:25:33.755961
10182 00:25:34.362848 01780000 ################################################################
10183 00:25:34.362994
10184 00:25:34.997304 01800000 ################################################################
10185 00:25:34.997867
10186 00:25:35.746549 01880000 ################################################################
10187 00:25:35.747157
10188 00:25:36.467999 01900000 ################################################################
10189 00:25:36.468134
10190 00:25:37.070107 01980000 ################################################################
10191 00:25:37.070256
10192 00:25:37.649661 01a00000 ################################################################
10193 00:25:37.649808
10194 00:25:38.332600 01a80000 ################################################################
10195 00:25:38.333291
10196 00:25:38.997080 01b00000 ################################################################
10197 00:25:38.997692
10198 00:25:39.617247 01b80000 ################################################################
10199 00:25:39.617869
10200 00:25:40.280871 01c00000 ################################################################
10201 00:25:40.281007
10202 00:25:40.944936 01c80000 ################################################################
10203 00:25:40.945085
10204 00:25:41.620780 01d00000 ################################################################
10205 00:25:41.621280
10206 00:25:42.360905 01d80000 ################################################################
10207 00:25:42.361487
10208 00:25:43.115549 01e00000 ################################################################
10209 00:25:43.116073
10210 00:25:43.864019 01e80000 ################################################################
10211 00:25:43.864518
10212 00:25:44.616019 01f00000 ################################################################
10213 00:25:44.616515
10214 00:25:45.378408 01f80000 ################################################################
10215 00:25:45.378919
10216 00:25:46.123306 02000000 ################################################################
10217 00:25:46.123857
10218 00:25:46.864259 02080000 ################################################################
10219 00:25:46.864772
10220 00:25:47.597635 02100000 ################################################################
10221 00:25:47.598139
10222 00:25:48.336322 02180000 ################################################################
10223 00:25:48.336836
10224 00:25:49.069487 02200000 ################################################################
10225 00:25:49.070002
10226 00:25:49.812243 02280000 ################################################################
10227 00:25:49.812797
10228 00:25:50.543746 02300000 ################################################################
10229 00:25:50.544265
10230 00:25:51.266945 02380000 ################################################################
10231 00:25:51.267088
10232 00:25:51.981897 02400000 ################################################################
10233 00:25:51.982417
10234 00:25:52.671861 02480000 ################################################################
10235 00:25:52.671995
10236 00:25:53.283476 02500000 ################################################################
10237 00:25:53.283647
10238 00:25:53.887674 02580000 ################################################################
10239 00:25:53.887825
10240 00:25:54.477330 02600000 ################################################################
10241 00:25:54.477482
10242 00:25:55.057901 02680000 ################################################################
10243 00:25:55.058043
10244 00:25:55.639072 02700000 ################################################################
10245 00:25:55.639220
10246 00:25:56.210439 02780000 ################################################################
10247 00:25:56.210643
10248 00:25:56.815491 02800000 ################################################################
10249 00:25:56.815637
10250 00:25:57.422732 02880000 ################################################################
10251 00:25:57.422885
10252 00:25:58.022339 02900000 ################################################################
10253 00:25:58.022481
10254 00:25:58.622360 02980000 ################################################################
10255 00:25:58.622503
10256 00:25:59.231772 02a00000 ################################################################
10257 00:25:59.231920
10258 00:25:59.822276 02a80000 ################################################################
10259 00:25:59.822425
10260 00:26:00.402261 02b00000 ################################################################
10261 00:26:00.402412
10262 00:26:01.002028 02b80000 ################################################################
10263 00:26:01.002181
10264 00:26:01.599538 02c00000 ################################################################
10265 00:26:01.599685
10266 00:26:02.198806 02c80000 ################################################################
10267 00:26:02.198960
10268 00:26:02.804287 02d00000 ################################################################
10269 00:26:02.804441
10270 00:26:03.407766 02d80000 ################################################################
10271 00:26:03.407931
10272 00:26:03.998844 02e00000 ################################################################
10273 00:26:03.999004
10274 00:26:04.602251 02e80000 ################################################################
10275 00:26:04.602410
10276 00:26:05.205578 02f00000 ################################################################
10277 00:26:05.205736
10278 00:26:05.810810 02f80000 ################################################################
10279 00:26:05.810964
10280 00:26:06.416392 03000000 ################################################################
10281 00:26:06.416547
10282 00:26:07.011099 03080000 ################################################################
10283 00:26:07.011255
10284 00:26:07.608270 03100000 ################################################################
10285 00:26:07.608429
10286 00:26:08.207968 03180000 ################################################################
10287 00:26:08.208129
10288 00:26:08.807383 03200000 ################################################################
10289 00:26:08.807550
10290 00:26:09.404839 03280000 ################################################################
10291 00:26:09.404991
10292 00:26:10.009158 03300000 ################################################################
10293 00:26:10.009304
10294 00:26:10.611078 03380000 ################################################################
10295 00:26:10.611237
10296 00:26:11.219288 03400000 ################################################################
10297 00:26:11.219486
10298 00:26:11.817661 03480000 ################################################################
10299 00:26:11.817817
10300 00:26:12.413656 03500000 ################################################################
10301 00:26:12.413806
10302 00:26:13.012744 03580000 ################################################################
10303 00:26:13.012883
10304 00:26:13.617968 03600000 ################################################################
10305 00:26:13.618161
10306 00:26:14.214789 03680000 ################################################################
10307 00:26:14.214975
10308 00:26:14.791567 03700000 ################################################################
10309 00:26:14.791755
10310 00:26:15.112930 03780000 #################################### done.
10311 00:26:15.113168
10312 00:26:15.116515 The bootfile was 58483066 bytes long.
10313 00:26:15.116659
10314 00:26:15.119297 Sending tftp read request... done.
10315 00:26:15.119469
10316 00:26:15.119592 Waiting for the transfer...
10317 00:26:15.119713
10318 00:26:15.123001 00000000 # done.
10319 00:26:15.123138
10320 00:26:15.129522 Command line loaded dynamically from TFTP file: 11280974/tftp-deploy-im_133ae/kernel/cmdline
10321 00:26:15.129660
10322 00:26:15.142687 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10323 00:26:15.142789
10324 00:26:15.146333 Loading FIT.
10325 00:26:15.146423
10326 00:26:15.149304 Image ramdisk-1 has 47396437 bytes.
10327 00:26:15.149442
10328 00:26:15.149558 Image fdt-1 has 47278 bytes.
10329 00:26:15.152659
10330 00:26:15.152798 Image kernel-1 has 11037315 bytes.
10331 00:26:15.152915
10332 00:26:15.163065 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10333 00:26:15.163163
10334 00:26:15.179280 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10335 00:26:15.179404
10336 00:26:15.186024 Choosing best match conf-1 for compat google,spherion-rev2.
10337 00:26:15.190073
10338 00:26:15.194944 Connected to device vid:did:rid of 1ae0:0028:00
10339 00:26:15.201761
10340 00:26:15.205118 tpm_get_response: command 0x17b, return code 0x0
10341 00:26:15.205208
10342 00:26:15.208407 ec_init: CrosEC protocol v3 supported (256, 248)
10343 00:26:15.212252
10344 00:26:15.216064 tpm_cleanup: add release locality here.
10345 00:26:15.216153
10346 00:26:15.216231 Shutting down all USB controllers.
10347 00:26:15.219017
10348 00:26:15.219105 Removing current net device
10349 00:26:15.219183
10350 00:26:15.225979 Exiting depthcharge with code 4 at timestamp: 109449322
10351 00:26:15.226074
10352 00:26:15.228844 LZMA decompressing kernel-1 to 0x821a6718
10353 00:26:15.228933
10354 00:26:15.232388 LZMA decompressing kernel-1 to 0x40000000
10355 00:26:16.620552
10356 00:26:16.620741 jumping to kernel
10357 00:26:16.621288 end: 2.2.4 bootloader-commands (duration 00:01:21) [common]
10358 00:26:16.621433 start: 2.2.5 auto-login-action (timeout 00:03:04) [common]
10359 00:26:16.621540 Setting prompt string to ['Linux version [0-9]']
10360 00:26:16.621636 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10361 00:26:16.621732 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10362 00:26:16.703078
10363 00:26:16.706105 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10364 00:26:16.710101 start: 2.2.5.1 login-action (timeout 00:03:04) [common]
10365 00:26:16.710510 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10366 00:26:16.710912 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10367 00:26:16.711266 Using line separator: #'\n'#
10368 00:26:16.711589 No login prompt set.
10369 00:26:16.711900 Parsing kernel messages
10370 00:26:16.712217 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10371 00:26:16.712682 [login-action] Waiting for messages, (timeout 00:03:04)
10372 00:26:16.729615 [ 0.000000] Linux version 6.1.45-cip3 (KernelCI@build-j12530-arm64-gcc-10-defconfig-arm64-chromebook-5rwxg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Aug 14 00:09:07 UTC 2023
10373 00:26:16.733030 [ 0.000000] random: crng init done
10374 00:26:16.739717 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10375 00:26:16.740184 [ 0.000000] efi: UEFI not found.
10376 00:26:16.749957 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10377 00:26:16.756274 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10378 00:26:16.766326 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10379 00:26:16.776062 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10380 00:26:16.782683 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10381 00:26:16.786071 [ 0.000000] printk: bootconsole [mtk8250] enabled
10382 00:26:16.794960 [ 0.000000] NUMA: No NUMA configuration found
10383 00:26:16.801783 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10384 00:26:16.808218 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10385 00:26:16.808725 [ 0.000000] Zone ranges:
10386 00:26:16.814669 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10387 00:26:16.817824 [ 0.000000] DMA32 empty
10388 00:26:16.825031 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10389 00:26:16.828029 [ 0.000000] Movable zone start for each node
10390 00:26:16.831921 [ 0.000000] Early memory node ranges
10391 00:26:16.838029 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10392 00:26:16.844655 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10393 00:26:16.851273 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10394 00:26:16.857758 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10395 00:26:16.864090 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10396 00:26:16.870907 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10397 00:26:16.927535 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10398 00:26:16.933725 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10399 00:26:16.940387 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10400 00:26:16.943480 [ 0.000000] psci: probing for conduit method from DT.
10401 00:26:16.950354 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10402 00:26:16.953758 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10403 00:26:16.960171 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10404 00:26:16.963799 [ 0.000000] psci: SMC Calling Convention v1.2
10405 00:26:16.969902 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10406 00:26:16.973468 [ 0.000000] Detected VIPT I-cache on CPU0
10407 00:26:16.980042 [ 0.000000] CPU features: detected: GIC system register CPU interface
10408 00:26:16.986716 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10409 00:26:16.993432 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10410 00:26:16.999631 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10411 00:26:17.009463 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10412 00:26:17.016296 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10413 00:26:17.019793 [ 0.000000] alternatives: applying boot alternatives
10414 00:26:17.026405 [ 0.000000] Fallback order for Node 0: 0
10415 00:26:17.032665 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10416 00:26:17.035836 [ 0.000000] Policy zone: Normal
10417 00:26:17.049070 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10418 00:26:17.059350 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10419 00:26:17.071451 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10420 00:26:17.081192 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10421 00:26:17.087844 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10422 00:26:17.091414 <6>[ 0.000000] software IO TLB: area num 8.
10423 00:26:17.149201 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10424 00:26:17.298149 <6>[ 0.000000] Memory: 7923272K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 429496K reserved, 32768K cma-reserved)
10425 00:26:17.305802 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10426 00:26:17.311915 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10427 00:26:17.315046 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10428 00:26:17.322056 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10429 00:26:17.328932 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10430 00:26:17.331543 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10431 00:26:17.341811 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10432 00:26:17.348251 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10433 00:26:17.351930 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10434 00:26:17.359008 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10435 00:26:17.363290 <6>[ 0.000000] GICv3: 608 SPIs implemented
10436 00:26:17.369692 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10437 00:26:17.372459 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10438 00:26:17.375800 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10439 00:26:17.386369 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10440 00:26:17.395703 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10441 00:26:17.409021 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10442 00:26:17.415739 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10443 00:26:17.424925 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10444 00:26:17.438127 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10445 00:26:17.444576 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10446 00:26:17.451404 <6>[ 0.009182] Console: colour dummy device 80x25
10447 00:26:17.461240 <6>[ 0.013936] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10448 00:26:17.467891 <6>[ 0.024379] pid_max: default: 32768 minimum: 301
10449 00:26:17.471444 <6>[ 0.029281] LSM: Security Framework initializing
10450 00:26:17.478042 <6>[ 0.034221] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10451 00:26:17.488086 <6>[ 0.042033] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10452 00:26:17.494619 <6>[ 0.051457] cblist_init_generic: Setting adjustable number of callback queues.
10453 00:26:17.501590 <6>[ 0.058903] cblist_init_generic: Setting shift to 3 and lim to 1.
10454 00:26:17.511211 <6>[ 0.065240] cblist_init_generic: Setting adjustable number of callback queues.
10455 00:26:17.517344 <6>[ 0.072666] cblist_init_generic: Setting shift to 3 and lim to 1.
10456 00:26:17.521091 <6>[ 0.079104] rcu: Hierarchical SRCU implementation.
10457 00:26:17.527268 <6>[ 0.084117] rcu: Max phase no-delay instances is 1000.
10458 00:26:17.534399 <6>[ 0.091142] EFI services will not be available.
10459 00:26:17.537126 <6>[ 0.096118] smp: Bringing up secondary CPUs ...
10460 00:26:17.545423 <6>[ 0.101205] Detected VIPT I-cache on CPU1
10461 00:26:17.552129 <6>[ 0.101273] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10462 00:26:17.558708 <6>[ 0.101305] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10463 00:26:17.562025 <6>[ 0.101638] Detected VIPT I-cache on CPU2
10464 00:26:17.572284 <6>[ 0.101685] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10465 00:26:17.578724 <6>[ 0.101700] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10466 00:26:17.581560 <6>[ 0.101959] Detected VIPT I-cache on CPU3
10467 00:26:17.588976 <6>[ 0.102004] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10468 00:26:17.595564 <6>[ 0.102018] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10469 00:26:17.598980 <6>[ 0.102323] CPU features: detected: Spectre-v4
10470 00:26:17.605139 <6>[ 0.102329] CPU features: detected: Spectre-BHB
10471 00:26:17.608545 <6>[ 0.102333] Detected PIPT I-cache on CPU4
10472 00:26:17.615221 <6>[ 0.102390] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10473 00:26:17.622107 <6>[ 0.102407] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10474 00:26:17.628380 <6>[ 0.102702] Detected PIPT I-cache on CPU5
10475 00:26:17.635316 <6>[ 0.102764] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10476 00:26:17.641370 <6>[ 0.102781] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10477 00:26:17.644698 <6>[ 0.103065] Detected PIPT I-cache on CPU6
10478 00:26:17.651228 <6>[ 0.103129] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10479 00:26:17.657778 <6>[ 0.103146] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10480 00:26:17.665158 <6>[ 0.103444] Detected PIPT I-cache on CPU7
10481 00:26:17.671324 <6>[ 0.103508] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10482 00:26:17.678136 <6>[ 0.103524] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10483 00:26:17.681366 <6>[ 0.103571] smp: Brought up 1 node, 8 CPUs
10484 00:26:17.687960 <6>[ 0.244925] SMP: Total of 8 processors activated.
10485 00:26:17.691189 <6>[ 0.249846] CPU features: detected: 32-bit EL0 Support
10486 00:26:17.700959 <6>[ 0.255209] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10487 00:26:17.707973 <6>[ 0.264064] CPU features: detected: Common not Private translations
10488 00:26:17.713873 <6>[ 0.270540] CPU features: detected: CRC32 instructions
10489 00:26:17.717600 <6>[ 0.275891] CPU features: detected: RCpc load-acquire (LDAPR)
10490 00:26:17.724104 <6>[ 0.281851] CPU features: detected: LSE atomic instructions
10491 00:26:17.730875 <6>[ 0.287669] CPU features: detected: Privileged Access Never
10492 00:26:17.737719 <6>[ 0.293449] CPU features: detected: RAS Extension Support
10493 00:26:17.743938 <6>[ 0.299058] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10494 00:26:17.747753 <6>[ 0.306276] CPU: All CPU(s) started at EL2
10495 00:26:17.754255 <6>[ 0.310620] alternatives: applying system-wide alternatives
10496 00:26:17.763171 <6>[ 0.321318] devtmpfs: initialized
10497 00:26:17.776023 <6>[ 0.330186] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10498 00:26:17.785807 <6>[ 0.340149] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10499 00:26:17.792302 <6>[ 0.348306] pinctrl core: initialized pinctrl subsystem
10500 00:26:17.795558 <6>[ 0.354969] DMI not present or invalid.
10501 00:26:17.802177 <6>[ 0.359377] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10502 00:26:17.812188 <6>[ 0.366240] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10503 00:26:17.818880 <6>[ 0.373828] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10504 00:26:17.828580 <6>[ 0.382046] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10505 00:26:17.832187 <6>[ 0.390289] audit: initializing netlink subsys (disabled)
10506 00:26:17.841966 <5>[ 0.395983] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10507 00:26:17.848287 <6>[ 0.396698] thermal_sys: Registered thermal governor 'step_wise'
10508 00:26:17.854739 <6>[ 0.403950] thermal_sys: Registered thermal governor 'power_allocator'
10509 00:26:17.858586 <6>[ 0.410207] cpuidle: using governor menu
10510 00:26:17.864751 <6>[ 0.421166] NET: Registered PF_QIPCRTR protocol family
10511 00:26:17.871923 <6>[ 0.426649] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10512 00:26:17.874885 <6>[ 0.433756] ASID allocator initialised with 32768 entries
10513 00:26:17.882663 <6>[ 0.440324] Serial: AMBA PL011 UART driver
10514 00:26:17.891570 <4>[ 0.449112] Trying to register duplicate clock ID: 134
10515 00:26:17.945383 <6>[ 0.506479] KASLR enabled
10516 00:26:17.959358 <6>[ 0.514207] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10517 00:26:17.966749 <6>[ 0.521222] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10518 00:26:17.973353 <6>[ 0.527713] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10519 00:26:17.979225 <6>[ 0.534717] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10520 00:26:17.986485 <6>[ 0.541203] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10521 00:26:17.992813 <6>[ 0.548207] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10522 00:26:17.999619 <6>[ 0.554694] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10523 00:26:18.005761 <6>[ 0.561701] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10524 00:26:18.009518 <6>[ 0.569211] ACPI: Interpreter disabled.
10525 00:26:18.017780 <6>[ 0.575619] iommu: Default domain type: Translated
10526 00:26:18.024163 <6>[ 0.580730] iommu: DMA domain TLB invalidation policy: strict mode
10527 00:26:18.027276 <5>[ 0.587380] SCSI subsystem initialized
10528 00:26:18.034504 <6>[ 0.591541] usbcore: registered new interface driver usbfs
10529 00:26:18.040543 <6>[ 0.597274] usbcore: registered new interface driver hub
10530 00:26:18.043912 <6>[ 0.602826] usbcore: registered new device driver usb
10531 00:26:18.050546 <6>[ 0.608921] pps_core: LinuxPPS API ver. 1 registered
10532 00:26:18.060464 <6>[ 0.614115] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10533 00:26:18.063319 <6>[ 0.623463] PTP clock support registered
10534 00:26:18.067181 <6>[ 0.627704] EDAC MC: Ver: 3.0.0
10535 00:26:18.074795 <6>[ 0.632847] FPGA manager framework
10536 00:26:18.081185 <6>[ 0.636526] Advanced Linux Sound Architecture Driver Initialized.
10537 00:26:18.084750 <6>[ 0.643226] vgaarb: loaded
10538 00:26:18.091329 <6>[ 0.646391] clocksource: Switched to clocksource arch_sys_counter
10539 00:26:18.094380 <5>[ 0.652820] VFS: Disk quotas dquot_6.6.0
10540 00:26:18.101186 <6>[ 0.657003] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10541 00:26:18.104404 <6>[ 0.664187] pnp: PnP ACPI: disabled
10542 00:26:18.112416 <6>[ 0.670825] NET: Registered PF_INET protocol family
10543 00:26:18.119211 <6>[ 0.676358] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10544 00:26:18.133991 <6>[ 0.688649] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10545 00:26:18.143790 <6>[ 0.697463] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10546 00:26:18.150173 <6>[ 0.705431] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10547 00:26:18.156911 <6>[ 0.714128] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10548 00:26:18.169316 <6>[ 0.723875] TCP: Hash tables configured (established 65536 bind 65536)
10549 00:26:18.175363 <6>[ 0.730735] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10550 00:26:18.181943 <6>[ 0.737936] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10551 00:26:18.188979 <6>[ 0.745633] NET: Registered PF_UNIX/PF_LOCAL protocol family
10552 00:26:18.195570 <6>[ 0.751801] RPC: Registered named UNIX socket transport module.
10553 00:26:18.198708 <6>[ 0.757953] RPC: Registered udp transport module.
10554 00:26:18.205902 <6>[ 0.762886] RPC: Registered tcp transport module.
10555 00:26:18.212321 <6>[ 0.767818] RPC: Registered tcp NFSv4.1 backchannel transport module.
10556 00:26:18.215515 <6>[ 0.774487] PCI: CLS 0 bytes, default 64
10557 00:26:18.218927 <6>[ 0.778896] Unpacking initramfs...
10558 00:26:18.228911 <6>[ 0.782696] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10559 00:26:18.235120 <6>[ 0.791335] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10560 00:26:18.242336 <6>[ 0.800179] kvm [1]: IPA Size Limit: 40 bits
10561 00:26:18.245674 <6>[ 0.804707] kvm [1]: GICv3: no GICV resource entry
10562 00:26:18.252034 <6>[ 0.809730] kvm [1]: disabling GICv2 emulation
10563 00:26:18.258995 <6>[ 0.814416] kvm [1]: GIC system register CPU interface enabled
10564 00:26:18.262314 <6>[ 0.820578] kvm [1]: vgic interrupt IRQ18
10565 00:26:18.268453 <6>[ 0.826585] kvm [1]: VHE mode initialized successfully
10566 00:26:18.275348 <5>[ 0.832981] Initialise system trusted keyrings
10567 00:26:18.281861 <6>[ 0.837809] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10568 00:26:18.290129 <6>[ 0.847768] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10569 00:26:18.296328 <5>[ 0.854144] NFS: Registering the id_resolver key type
10570 00:26:18.300006 <5>[ 0.859446] Key type id_resolver registered
10571 00:26:18.306327 <5>[ 0.863864] Key type id_legacy registered
10572 00:26:18.313015 <6>[ 0.868149] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10573 00:26:18.319520 <6>[ 0.875070] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10574 00:26:18.326399 <6>[ 0.882773] 9p: Installing v9fs 9p2000 file system support
10575 00:26:18.363305 <5>[ 0.921015] Key type asymmetric registered
10576 00:26:18.366487 <5>[ 0.925347] Asymmetric key parser 'x509' registered
10577 00:26:18.376303 <6>[ 0.930485] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10578 00:26:18.380112 <6>[ 0.938096] io scheduler mq-deadline registered
10579 00:26:18.382995 <6>[ 0.942856] io scheduler kyber registered
10580 00:26:18.402319 <6>[ 0.959906] EINJ: ACPI disabled.
10581 00:26:18.434724 <4>[ 0.985517] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10582 00:26:18.444207 <4>[ 0.996314] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10583 00:26:18.459498 <6>[ 1.017327] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10584 00:26:18.467605 <6>[ 1.025442] printk: console [ttyS0] disabled
10585 00:26:18.495909 <6>[ 1.050091] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10586 00:26:18.502371 <6>[ 1.059580] printk: console [ttyS0] enabled
10587 00:26:18.505532 <6>[ 1.059580] printk: console [ttyS0] enabled
10588 00:26:18.511696 <6>[ 1.068484] printk: bootconsole [mtk8250] disabled
10589 00:26:18.515970 <6>[ 1.068484] printk: bootconsole [mtk8250] disabled
10590 00:26:18.521959 <6>[ 1.079584] SuperH (H)SCI(F) driver initialized
10591 00:26:18.525485 <6>[ 1.084871] msm_serial: driver initialized
10592 00:26:18.538952 <6>[ 1.093909] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10593 00:26:18.549120 <6>[ 1.102460] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10594 00:26:18.555660 <6>[ 1.111003] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10595 00:26:18.565847 <6>[ 1.119641] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10596 00:26:18.575976 <6>[ 1.128351] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10597 00:26:18.582353 <6>[ 1.137064] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10598 00:26:18.592360 <6>[ 1.145605] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10599 00:26:18.598914 <6>[ 1.154427] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10600 00:26:18.608767 <6>[ 1.162972] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10601 00:26:18.620704 <6>[ 1.178749] loop: module loaded
10602 00:26:18.627475 <6>[ 1.184881] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10603 00:26:18.650133 <4>[ 1.208246] mtk-pmic-keys: Failed to locate of_node [id: -1]
10604 00:26:18.657072 <6>[ 1.215099] megasas: 07.719.03.00-rc1
10605 00:26:18.666803 <6>[ 1.224739] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10606 00:26:18.675659 <6>[ 1.233785] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10607 00:26:18.692070 <6>[ 1.249584] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10608 00:26:18.748425 <6>[ 1.299606] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10609 00:26:20.229413 <6>[ 2.788092] Freeing initrd memory: 46280K
10610 00:26:20.239845 <6>[ 2.798348] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10611 00:26:20.250583 <6>[ 2.809123] tun: Universal TUN/TAP device driver, 1.6
10612 00:26:20.253658 <6>[ 2.815194] thunder_xcv, ver 1.0
10613 00:26:20.257074 <6>[ 2.818699] thunder_bgx, ver 1.0
10614 00:26:20.260553 <6>[ 2.822188] nicpf, ver 1.0
10615 00:26:20.270847 <6>[ 2.826209] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10616 00:26:20.274021 <6>[ 2.833685] hns3: Copyright (c) 2017 Huawei Corporation.
10617 00:26:20.280924 <6>[ 2.839288] hclge is initializing
10618 00:26:20.284142 <6>[ 2.842871] e1000: Intel(R) PRO/1000 Network Driver
10619 00:26:20.290715 <6>[ 2.848000] e1000: Copyright (c) 1999-2006 Intel Corporation.
10620 00:26:20.294011 <6>[ 2.854013] e1000e: Intel(R) PRO/1000 Network Driver
10621 00:26:20.300830 <6>[ 2.859228] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10622 00:26:20.307533 <6>[ 2.865414] igb: Intel(R) Gigabit Ethernet Network Driver
10623 00:26:20.314144 <6>[ 2.871065] igb: Copyright (c) 2007-2014 Intel Corporation.
10624 00:26:20.320345 <6>[ 2.876900] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10625 00:26:20.327263 <6>[ 2.883417] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10626 00:26:20.330331 <6>[ 2.889886] sky2: driver version 1.30
10627 00:26:20.336999 <6>[ 2.894917] VFIO - User Level meta-driver version: 0.3
10628 00:26:20.344391 <6>[ 2.903195] usbcore: registered new interface driver usb-storage
10629 00:26:20.351038 <6>[ 2.909641] usbcore: registered new device driver onboard-usb-hub
10630 00:26:20.360058 <6>[ 2.918736] mt6397-rtc mt6359-rtc: registered as rtc0
10631 00:26:20.369984 <6>[ 2.924214] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-14T00:26:21 UTC (1691972781)
10632 00:26:20.373118 <6>[ 2.933815] i2c_dev: i2c /dev entries driver
10633 00:26:20.389986 <6>[ 2.945571] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10634 00:26:20.410012 <6>[ 2.968584] cpu cpu0: EM: created perf domain
10635 00:26:20.413365 <6>[ 2.973575] cpu cpu4: EM: created perf domain
10636 00:26:20.420938 <6>[ 2.979185] sdhci: Secure Digital Host Controller Interface driver
10637 00:26:20.427268 <6>[ 2.985617] sdhci: Copyright(c) Pierre Ossman
10638 00:26:20.433678 <6>[ 2.990570] Synopsys Designware Multimedia Card Interface Driver
10639 00:26:20.437466 <6>[ 2.997202] mmc0: CQHCI version 5.10
10640 00:26:20.443496 <6>[ 2.997206] sdhci-pltfm: SDHCI platform and OF driver helper
10641 00:26:20.450351 <6>[ 3.007298] ledtrig-cpu: registered to indicate activity on CPUs
10642 00:26:20.457224 <6>[ 3.014331] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10643 00:26:20.463616 <6>[ 3.021391] usbcore: registered new interface driver usbhid
10644 00:26:20.466739 <6>[ 3.027216] usbhid: USB HID core driver
10645 00:26:20.473592 <6>[ 3.031421] spi_master spi0: will run message pump with realtime priority
10646 00:26:20.515401 <6>[ 3.067486] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10647 00:26:20.534598 <6>[ 3.083027] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10648 00:26:20.541863 <6>[ 3.097787] cros-ec-spi spi0.0: Chrome EC device registered
10649 00:26:20.545232 <6>[ 3.103870] mmc0: Command Queue Engine enabled
10650 00:26:20.551938 <6>[ 3.108614] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10651 00:26:20.558974 <6>[ 3.116562] mmcblk0: mmc0:0001 DA4128 116 GiB
10652 00:26:20.568541 <6>[ 3.116599] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10653 00:26:20.571287 <6>[ 3.127434] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10654 00:26:20.578346 <6>[ 3.131687] NET: Registered PF_PACKET protocol family
10655 00:26:20.585024 <6>[ 3.137323] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10656 00:26:20.588556 <6>[ 3.141890] 9pnet: Installing 9P2000 support
10657 00:26:20.594772 <6>[ 3.147643] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10658 00:26:20.598383 <5>[ 3.151592] Key type dns_resolver registered
10659 00:26:20.604688 <6>[ 3.157257] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10660 00:26:20.608131 <6>[ 3.161842] registered taskstats version 1
10661 00:26:20.615151 <5>[ 3.172196] Loading compiled-in X.509 certificates
10662 00:26:20.642421 <4>[ 3.193728] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10663 00:26:20.652173 <4>[ 3.204442] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10664 00:26:20.658775 <3>[ 3.214970] debugfs: File 'uA_load' in directory '/' already present!
10665 00:26:20.665462 <3>[ 3.221668] debugfs: File 'min_uV' in directory '/' already present!
10666 00:26:20.671739 <3>[ 3.228331] debugfs: File 'max_uV' in directory '/' already present!
10667 00:26:20.679069 <3>[ 3.234946] debugfs: File 'constraint_flags' in directory '/' already present!
10668 00:26:20.689993 <3>[ 3.244585] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10669 00:26:20.698925 <6>[ 3.256872] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10670 00:26:20.705822 <6>[ 3.263559] xhci-mtk 11200000.usb: xHCI Host Controller
10671 00:26:20.711938 <6>[ 3.269052] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10672 00:26:20.722518 <6>[ 3.276952] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10673 00:26:20.728713 <6>[ 3.286397] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10674 00:26:20.735427 <6>[ 3.292473] xhci-mtk 11200000.usb: xHCI Host Controller
10675 00:26:20.742389 <6>[ 3.297956] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10676 00:26:20.748478 <6>[ 3.305614] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10677 00:26:20.755419 <6>[ 3.313548] hub 1-0:1.0: USB hub found
10678 00:26:20.758445 <6>[ 3.317572] hub 1-0:1.0: 1 port detected
10679 00:26:20.768449 <6>[ 3.321841] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10680 00:26:20.771520 <6>[ 3.330663] hub 2-0:1.0: USB hub found
10681 00:26:20.775342 <6>[ 3.334680] hub 2-0:1.0: 1 port detected
10682 00:26:20.784259 <6>[ 3.342217] mtk-msdc 11f70000.mmc: Got CD GPIO
10683 00:26:20.794157 <6>[ 3.348365] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10684 00:26:20.800466 <6>[ 3.356398] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10685 00:26:20.810305 <4>[ 3.364291] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10686 00:26:20.816775 <6>[ 3.373816] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10687 00:26:20.826913 <6>[ 3.381892] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10688 00:26:20.833327 <6>[ 3.389969] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10689 00:26:20.843325 <6>[ 3.397901] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10690 00:26:20.849958 <6>[ 3.405719] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10691 00:26:20.860424 <6>[ 3.413536] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10692 00:26:20.869761 <6>[ 3.424010] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10693 00:26:20.876390 <6>[ 3.432389] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10694 00:26:20.886324 <6>[ 3.440731] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10695 00:26:20.893277 <6>[ 3.449069] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10696 00:26:20.902904 <6>[ 3.457412] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10697 00:26:20.909983 <6>[ 3.465750] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10698 00:26:20.919571 <6>[ 3.474088] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10699 00:26:20.926228 <6>[ 3.482425] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10700 00:26:20.936181 <6>[ 3.490774] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10701 00:26:20.942776 <6>[ 3.499112] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10702 00:26:20.952691 <6>[ 3.507451] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10703 00:26:20.959732 <6>[ 3.515789] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10704 00:26:20.969237 <6>[ 3.524127] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10705 00:26:20.979037 <6>[ 3.532465] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10706 00:26:20.985731 <6>[ 3.540802] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10707 00:26:20.992252 <6>[ 3.549562] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10708 00:26:20.998579 <6>[ 3.556757] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10709 00:26:21.005212 <6>[ 3.563527] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10710 00:26:21.012059 <6>[ 3.570291] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10711 00:26:21.022465 <6>[ 3.577230] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10712 00:26:21.028572 <6>[ 3.584076] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10713 00:26:21.038418 <6>[ 3.593208] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10714 00:26:21.049109 <6>[ 3.602327] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10715 00:26:21.058357 <6>[ 3.611621] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10716 00:26:21.068967 <6>[ 3.621090] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10717 00:26:21.074973 <6>[ 3.630558] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10718 00:26:21.084925 <6>[ 3.639681] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10719 00:26:21.094987 <6>[ 3.649148] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10720 00:26:21.105055 <6>[ 3.658267] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10721 00:26:21.115067 <6>[ 3.667562] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10722 00:26:21.124698 <6>[ 3.677721] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10723 00:26:21.134435 <6>[ 3.689434] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10724 00:26:21.179211 <6>[ 3.734506] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10725 00:26:21.334302 <6>[ 3.892204] hub 1-1:1.0: USB hub found
10726 00:26:21.337462 <6>[ 3.896680] hub 1-1:1.0: 4 ports detected
10727 00:26:21.459984 <6>[ 4.014799] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10728 00:26:21.485929 <6>[ 4.044185] hub 2-1:1.0: USB hub found
10729 00:26:21.488986 <6>[ 4.048672] hub 2-1:1.0: 3 ports detected
10730 00:26:21.659675 <6>[ 4.214675] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10731 00:26:21.791479 <6>[ 4.349981] hub 1-1.4:1.0: USB hub found
10732 00:26:21.794939 <6>[ 4.354625] hub 1-1.4:1.0: 2 ports detected
10733 00:26:21.871365 <6>[ 4.426729] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10734 00:26:22.091547 <6>[ 4.646721] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10735 00:26:22.283518 <6>[ 4.838723] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10736 00:26:33.420090 <6>[ 15.983783] ALSA device list:
10737 00:26:33.426995 <6>[ 15.987075] No soundcards found.
10738 00:26:33.435300 <6>[ 15.995196] Freeing unused kernel memory: 8384K
10739 00:26:33.438288 <6>[ 16.000250] Run /init as init process
10740 00:26:33.490485 <6>[ 16.050697] NET: Registered PF_INET6 protocol family
10741 00:26:33.497102 <6>[ 16.057158] Segment Routing with IPv6
10742 00:26:33.500079 <6>[ 16.061109] In-situ OAM (IOAM) with IPv6
10743 00:26:33.537111 <30>[ 16.077599] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10744 00:26:33.540489 <30>[ 16.101632] systemd[1]: Detected architecture arm64.
10745 00:26:33.543796
10746 00:26:33.546849 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10747 00:26:33.546929
10748 00:26:33.562642 <30>[ 16.122733] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10749 00:26:33.696601 <30>[ 16.253649] systemd[1]: Queued start job for default target Graphical Interface.
10750 00:26:33.723798 <30>[ 16.283670] systemd[1]: Created slice system-getty.slice.
10751 00:26:33.729999 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10752 00:26:33.746955 <30>[ 16.307206] systemd[1]: Created slice system-modprobe.slice.
10753 00:26:33.753769 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10754 00:26:33.775674 <30>[ 16.335654] systemd[1]: Created slice system-serial\x2dgetty.slice.
10755 00:26:33.785283 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10756 00:26:33.799780 <30>[ 16.359432] systemd[1]: Created slice User and Session Slice.
10757 00:26:33.805665 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10758 00:26:33.826344 <30>[ 16.383459] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10759 00:26:33.836246 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10760 00:26:33.853990 <30>[ 16.410924] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10761 00:26:33.860272 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10762 00:26:33.881018 <30>[ 16.434781] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10763 00:26:33.888208 <30>[ 16.446976] systemd[1]: Reached target Local Encrypted Volumes.
10764 00:26:33.894588 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10765 00:26:33.910979 <30>[ 16.471303] systemd[1]: Reached target Paths.
10766 00:26:33.917682 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10767 00:26:33.930692 <30>[ 16.490689] systemd[1]: Reached target Remote File Systems.
10768 00:26:33.937244 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10769 00:26:33.954402 <30>[ 16.514692] systemd[1]: Reached target Slices.
10770 00:26:33.960990 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10771 00:26:33.974739 <30>[ 16.534708] systemd[1]: Reached target Swap.
10772 00:26:33.977809 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10773 00:26:33.998391 <30>[ 16.555225] systemd[1]: Listening on initctl Compatibility Named Pipe.
10774 00:26:34.004740 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10775 00:26:34.011565 <30>[ 16.570661] systemd[1]: Listening on Journal Audit Socket.
10776 00:26:34.018054 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10777 00:26:34.031196 <30>[ 16.591241] systemd[1]: Listening on Journal Socket (/dev/log).
10778 00:26:34.037380 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10779 00:26:34.055931 <30>[ 16.616013] systemd[1]: Listening on Journal Socket.
10780 00:26:34.062672 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10781 00:26:34.078622 <30>[ 16.635478] systemd[1]: Listening on Network Service Netlink Socket.
10782 00:26:34.085079 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10783 00:26:34.100101 <30>[ 16.659961] systemd[1]: Listening on udev Control Socket.
10784 00:26:34.106255 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10785 00:26:34.123928 <30>[ 16.683829] systemd[1]: Listening on udev Kernel Socket.
10786 00:26:34.130212 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10787 00:26:34.186827 <30>[ 16.746848] systemd[1]: Mounting Huge Pages File System...
10788 00:26:34.193187 Mounting [0;1;39mHuge Pages File System[0m...
10789 00:26:34.210814 <30>[ 16.771154] systemd[1]: Mounting POSIX Message Queue File System...
10790 00:26:34.217986 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10791 00:26:34.239118 <30>[ 16.799204] systemd[1]: Mounting Kernel Debug File System...
10792 00:26:34.245386 Mounting [0;1;39mKernel Debug File System[0m...
10793 00:26:34.262360 <30>[ 16.819187] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10794 00:26:34.289860 <30>[ 16.846920] systemd[1]: Starting Create list of static device nodes for the current kernel...
10795 00:26:34.296333 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10796 00:26:34.319291 <30>[ 16.879625] systemd[1]: Starting Load Kernel Module configfs...
10797 00:26:34.326134 Starting [0;1;39mLoad Kernel Module configfs[0m...
10798 00:26:34.340639 <30>[ 16.900983] systemd[1]: Starting Load Kernel Module drm...
10799 00:26:34.347693 Starting [0;1;39mLoad Kernel Module drm[0m...
10800 00:26:34.366283 <30>[ 16.923066] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10801 00:26:34.399116 <30>[ 16.959206] systemd[1]: Starting Journal Service...
10802 00:26:34.402121 Starting [0;1;39mJournal Service[0m...
10803 00:26:34.421046 <30>[ 16.981509] systemd[1]: Starting Load Kernel Modules...
10804 00:26:34.427901 Starting [0;1;39mLoad Kernel Modules[0m...
10805 00:26:34.447698 <30>[ 17.004894] systemd[1]: Starting Remount Root and Kernel File Systems...
10806 00:26:34.454494 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10807 00:26:34.469806 <30>[ 17.029852] systemd[1]: Starting Coldplug All udev Devices...
10808 00:26:34.475882 Starting [0;1;39mColdplug All udev Devices[0m...
10809 00:26:34.493270 <30>[ 17.053577] systemd[1]: Started Journal Service.
10810 00:26:34.499549 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10811 00:26:34.520267 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10812 00:26:34.540070 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10813 00:26:34.560050 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10814 00:26:34.579591 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10815 00:26:34.596384 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10816 00:26:34.621806 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10817 00:26:34.640546 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10818 00:26:34.660948 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10819 00:26:34.678565 See 'systemctl status systemd-remount-fs.service' for details.
10820 00:26:34.719351 Mounting [0;1;39mKernel Configuration File System[0m...
10821 00:26:34.736788 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10822 00:26:34.754423 <46>[ 17.311060] systemd-journald[178]: Received client request to flush runtime journal.
10823 00:26:34.763273 Starting [0;1;39mLoad/Save Random Seed[0m...
10824 00:26:34.787181 Starting [0;1;39mApply Kernel Variables[0m...
10825 00:26:34.808355 Starting [0;1;39mCreate System Users[0m...
10826 00:26:34.830090 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10827 00:26:34.851580 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10828 00:26:34.872096 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10829 00:26:34.888495 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10830 00:26:34.896490 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10831 00:26:34.916405 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10832 00:26:34.959561 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10833 00:26:34.985148 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10834 00:26:34.998394 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10835 00:26:35.014171 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10836 00:26:35.054913 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10837 00:26:35.079053 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10838 00:26:35.099816 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10839 00:26:35.119527 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10840 00:26:35.161538 Starting [0;1;39mNetwork Service[0m...
10841 00:26:35.195818 Starting [0;1;39mNetwork Time Synchronization[0m...
10842 00:26:35.217681 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10843 00:26:35.248002 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10844 00:26:35.270768 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10845 00:26:35.289396 <6>[ 17.846474] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10846 00:26:35.296027 <6>[ 17.846580] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10847 00:26:35.306014 <6>[ 17.854319] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10848 00:26:35.309444 <6>[ 17.865594] remoteproc remoteproc0: scp is available
10849 00:26:35.319218 <6>[ 17.870677] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10850 00:26:35.322557 <6>[ 17.876134] remoteproc remoteproc0: powering up scp
10851 00:26:35.332556 <4>[ 17.885359] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10852 00:26:35.339067 <6>[ 17.889312] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10853 00:26:35.345891 <6>[ 17.889371] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10854 00:26:35.352374 <6>[ 17.898336] usbcore: registered new interface driver r8152
10855 00:26:35.359239 <4>[ 17.908090] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10856 00:26:35.365245 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10857 00:26:35.388044 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10858 00:26:35.407706 <3>[ 17.964891] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10859 00:26:35.414213 <3>[ 17.973280] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10860 00:26:35.424804 <3>[ 17.981699] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10861 00:26:35.434607 <3>[ 17.991149] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10862 00:26:35.437879 <6>[ 17.995691] mc: Linux media interface: v0.10
10863 00:26:35.447665 <6>[ 17.998214] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10864 00:26:35.457725 <6>[ 17.998526] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10865 00:26:35.464460 <3>[ 18.000050] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10866 00:26:35.474552 <6>[ 18.030529] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10867 00:26:35.480755 <6>[ 18.030542] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10868 00:26:35.490731 <3>[ 18.031138] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10869 00:26:35.497967 <6>[ 18.032194] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10870 00:26:35.504348 <6>[ 18.034192] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10871 00:26:35.510760 <6>[ 18.034199] pci_bus 0000:00: root bus resource [bus 00-ff]
10872 00:26:35.517285 <6>[ 18.034204] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10873 00:26:35.527117 <6>[ 18.034207] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10874 00:26:35.534012 <6>[ 18.034235] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10875 00:26:35.540382 <6>[ 18.034248] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10876 00:26:35.543918 <6>[ 18.034313] pci 0000:00:00.0: supports D1 D2
10877 00:26:35.550609 <6>[ 18.034314] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10878 00:26:35.560893 <6>[ 18.037649] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10879 00:26:35.567571 <6>[ 18.040362] remoteproc remoteproc0: remote processor scp is now up
10880 00:26:35.573866 <6>[ 18.041680] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10881 00:26:35.583797 <6>[ 18.045981] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10882 00:26:35.590359 <6>[ 18.046901] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10883 00:26:35.597293 <3>[ 18.047068] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10884 00:26:35.607134 <3>[ 18.047075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10885 00:26:35.614069 <3>[ 18.047120] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10886 00:26:35.620584 <3>[ 18.047177] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10887 00:26:35.630452 <3>[ 18.047180] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10888 00:26:35.637266 <3>[ 18.047183] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10889 00:26:35.646813 <3>[ 18.047226] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10890 00:26:35.653887 <3>[ 18.047229] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10891 00:26:35.660988 <3>[ 18.047232] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10892 00:26:35.671107 <3>[ 18.047234] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10893 00:26:35.678327 <3>[ 18.047237] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10894 00:26:35.688216 <3>[ 18.047256] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10895 00:26:35.694373 <4>[ 18.056652] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10896 00:26:35.704239 <6>[ 18.062144] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10897 00:26:35.708420 <6>[ 18.064129] videodev: Linux video capture interface: v2.00
10898 00:26:35.718825 <4>[ 18.069071] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10899 00:26:35.726021 <6>[ 18.074764] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10900 00:26:35.732652 <4>[ 18.083979] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10901 00:26:35.739366 <4>[ 18.083979] Fallback method does not support PEC.
10902 00:26:35.746262 <6>[ 18.091797] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10903 00:26:35.756034 <3>[ 18.125655] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 00:26:35.759540 <6>[ 18.126313] pci 0000:01:00.0: supports D1 D2
10905 00:26:35.763038 <6>[ 18.127013] Bluetooth: Core ver 2.22
10906 00:26:35.769922 <6>[ 18.127371] NET: Registered PF_BLUETOOTH protocol family
10907 00:26:35.776638 <6>[ 18.127375] Bluetooth: HCI device and connection manager initialized
10908 00:26:35.779539 <6>[ 18.127393] Bluetooth: HCI socket layer initialized
10909 00:26:35.786139 <6>[ 18.127399] Bluetooth: L2CAP socket layer initialized
10910 00:26:35.789431 <6>[ 18.127415] Bluetooth: SCO socket layer initialized
10911 00:26:35.796673 <6>[ 18.144769] usbcore: registered new interface driver cdc_ether
10912 00:26:35.803358 <6>[ 18.148513] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10913 00:26:35.806423 <6>[ 18.162965] r8152 2-1.3:1.0 eth0: v1.12.13
10914 00:26:35.813144 <6>[ 18.172826] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10915 00:26:35.823219 <6>[ 18.174689] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10916 00:26:35.830314 <6>[ 18.175191] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10917 00:26:35.837093 <6>[ 18.175202] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10918 00:26:35.846608 <6>[ 18.175225] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10919 00:26:35.853604 <6>[ 18.175239] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10920 00:26:35.861227 <6>[ 18.175251] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10921 00:26:35.867112 <6>[ 18.175265] pci 0000:00:00.0: PCI bridge to [bus 01]
10922 00:26:35.873901 <6>[ 18.175272] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10923 00:26:35.880856 <6>[ 18.175594] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10924 00:26:35.887236 <6>[ 18.176344] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10925 00:26:35.893597 <6>[ 18.176650] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10926 00:26:35.900447 <6>[ 18.188115] usbcore: registered new interface driver r8153_ecm
10927 00:26:35.910287 <6>[ 18.214853] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10928 00:26:35.916990 <6>[ 18.240649] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10929 00:26:35.927171 <3>[ 18.244616] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 00:26:35.934249 <6>[ 18.247390] usbcore: registered new interface driver btusb
10931 00:26:35.944016 <4>[ 18.247636] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10932 00:26:35.950785 <3>[ 18.247644] Bluetooth: hci0: Failed to load firmware file (-2)
10933 00:26:35.954212 <3>[ 18.247647] Bluetooth: hci0: Failed to set up firmware (-2)
10934 00:26:35.964713 <4>[ 18.247649] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10935 00:26:35.971146 <6>[ 18.252182] usbcore: registered new interface driver uvcvideo
10936 00:26:35.981702 <6>[ 18.253671] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10937 00:26:35.985782 <6>[ 18.256252] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10938 00:26:35.995406 <6>[ 18.256500] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10939 00:26:36.002708 <3>[ 18.287497] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 00:26:36.012888 <3>[ 18.288251] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
10941 00:26:36.019518 <3>[ 18.295377] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 00:26:36.027187 <5>[ 18.306360] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10943 00:26:36.036559 <3>[ 18.328846] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 00:26:36.043479 <5>[ 18.344454] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10945 00:26:36.053872 <3>[ 18.366168] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 00:26:36.060371 <4>[ 18.368933] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10947 00:26:36.070490 <3>[ 18.393105] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 00:26:36.076581 <6>[ 18.395202] cfg80211: failed to load regulatory.db
10949 00:26:36.083244 <3>[ 18.423620] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 00:26:36.090370 <6>[ 18.473689] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10951 00:26:36.099727 <3>[ 18.497667] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 00:26:36.106440 <6>[ 18.498471] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10953 00:26:36.113301 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10954 00:26:36.133876 [[0;32m OK [<6>[ 18.692168] mt7921e 0000:01:00.0: ASIC revision: 79610010
10955 00:26:36.137183 0m] Reached target [0;1;39mSystem Time Set[0m.
10956 00:26:36.154767 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10957 00:26:36.214733 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10958 00:26:36.238883 <4>[ 18.792843] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10959 00:26:36.252889 Starting [0;1;39mNetwork Name Resolution[0m...
10960 00:26:36.273402 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10961 00:26:36.359044 <4>[ 18.912722] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10962 00:26:36.365287 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10963 00:26:36.465228 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10964 00:26:36.478951 <4>[ 19.032991] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10965 00:26:36.485664 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10966 00:26:36.505452 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10967 00:26:36.518475 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10968 00:26:36.535302 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10969 00:26:36.553751 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10970 00:26:36.566445 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10971 00:26:36.589847 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10972 00:26:36.600046 <4>[ 19.153593] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10973 00:26:36.606305 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10974 00:26:36.622688 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10975 00:26:36.642489 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10976 00:26:36.703642 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10977 00:26:36.724021 <4>[ 19.278047] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10978 00:26:36.752579 Starting [0;1;39mUser Login Management[0m...
10979 00:26:36.771634 Starting [0;1;39mPermit User Sessions[0m...
10980 00:26:36.791325 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10981 00:26:36.812654 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10982 00:26:36.843870 <4>[ 19.397716] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10983 00:26:36.850296 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10984 00:26:36.857468 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10985 00:26:36.874661 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10986 00:26:36.890982 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10987 00:26:36.906420 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10988 00:26:36.923219 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10989 00:26:36.942741 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10990 00:26:36.962759 <4>[ 19.517045] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10991 00:26:37.029147 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10992 00:26:37.084305 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes<4>[ 19.637497] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10993 00:26:37.084411 [0m.
10994 00:26:37.133104
10995 00:26:37.133198
10996 00:26:37.136449 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10997 00:26:37.136533
10998 00:26:37.140040 debian-bullseye-arm64 login: root (automatic login)
10999 00:26:37.140121
11000 00:26:37.140185
11001 00:26:37.168979 Linux debian-bullseye-arm64 6.1.45-cip3 #1 SMP PREEMPT Mon Aug 14 00:09:07 UTC 2023 aarch64
11002 00:26:37.169062
11003 00:26:37.175644 The programs included with the Debian GNU/Linux system are free software;
11004 00:26:37.182346 the exact distribution terms for each program are described in the
11005 00:26:37.185861 individual files in /usr/share/doc/*/copyright.
11006 00:26:37.185957
11007 00:26:37.192606 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11008 00:26:37.205738 permitted by<4>[ 19.757192] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11009 00:26:37.205820 applicable law.
11010 00:26:37.206179 Matched prompt #10: / #
11012 00:26:37.206375 Setting prompt string to ['/ #']
11013 00:26:37.206467 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11015 00:26:37.206656 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11016 00:26:37.206743 start: 2.2.6 expect-shell-connection (timeout 00:02:43) [common]
11017 00:26:37.206813 Setting prompt string to ['/ #']
11018 00:26:37.206872 Forcing a shell prompt, looking for ['/ #']
11020 00:26:37.257071 / #
11021 00:26:37.257180 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11022 00:26:37.257256 Waiting using forced prompt support (timeout 00:02:30)
11023 00:26:37.261683
11024 00:26:37.261953 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11025 00:26:37.262047 start: 2.2.7 export-device-env (timeout 00:02:43) [common]
11026 00:26:37.262140 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11027 00:26:37.262223 end: 2.2 depthcharge-retry (duration 00:02:17) [common]
11028 00:26:37.262304 end: 2 depthcharge-action (duration 00:02:17) [common]
11029 00:26:37.262389 start: 3 lava-test-retry (timeout 00:05:00) [common]
11030 00:26:37.262504 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11031 00:26:37.262601 Using namespace: common
11033 00:26:37.362927 / # <6>#
11034 00:26:37.363052 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11035 00:26:37.363202 [ 19.828846] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
11036 00:26:37.363271 <6>[ 19.836853] r8152 2-1.3:1.0 enx0024323078ff: carrier on
11037 00:26:37.363349 <4>[ 19.877310] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11038 00:26:37.367945 #
11039 00:26:37.368209 Using /lava-11280974
11041 00:26:37.468553 / # export SHELL=/bin/sh
11042 00:26:37.468711 export SHELL=/bin/sh<3>[ 19.994632] mt7921e 0000:01:00.0: hardware init failed
11043 00:26:37.473739
11045 00:26:37.574256 / # . /lava-11280974/environment
11046 00:26:37.579793 . /lava-11280974/environment
11048 00:26:37.680329 / # /lava-11280974/bin/lava-test-runner /lava-11280974/0
11049 00:26:37.680461 Test shell timeout: 10s (minimum of the action and connection timeout)
11050 00:26:37.686099 /lava-11280974/bin/lava-test-runner /lava-11280974/0
11051 00:26:37.705057 + export TESTRUN_ID=0_cros-ec
11052 00:26:37.711404 +<8>[ 20.271576] <LAVA_SIGNAL_STARTRUN 0_cros-ec 11280974_1.5.2.3.1>
11053 00:26:37.711665 Received signal: <STARTRUN> 0_cros-ec 11280974_1.5.2.3.1
11054 00:26:37.711743 Starting test lava.0_cros-ec (11280974_1.5.2.3.1)
11055 00:26:37.711823 Skipping test definition patterns.
11056 00:26:37.714961 cd /lava-11280974/0/tests/0_cros-ec
11057 00:26:37.718210 + cat uuid
11058 00:26:37.718289 + UUID=11280974_1.5.2.3.1
11059 00:26:37.718352 + set +x
11060 00:26:37.724569 + python3 -m cros.runners.lava_runner -v
11061 00:26:38.085908 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11062 00:26:38.092679 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11063 00:26:38.095521
11064 00:26:38.102570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11065 00:26:38.102820 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11067 00:26:38.108861 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11068 00:26:38.119050 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11069 00:26:38.119126
11070 00:26:38.122212 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_ac<8
11071 00:26:38.122299 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'test_cros_ec_ac<8', 'result': 'unknown'}
11072 00:26:38.128695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_ac<8>[ 20.687221] <LAVA_SIGNAL_ENDRUN 0_cros-ec 11280974_1.5.2.3.1>
11073 00:26:38.128944 Received signal: <ENDRUN> 0_cros-ec 11280974_1.5.2.3.1
11074 00:26:38.129021 Ending use of test pattern.
11075 00:26:38.129079 Ending test lava.0_cros-ec (11280974_1.5.2.3.1), duration 0.42
11077 00:26:38.132468 cel_iio_data_is_valid RESULT=skip>
11078 00:26:38.138965 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11079 00:26:38.145372 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11080 00:26:38.145448
11081 00:26:38.151696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11082 00:26:38.151946 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11084 00:26:38.155027 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11085 00:26:38.161873 Checks the standard ABI for the main Embedded Controller. ... ok
11086 00:26:38.161946
11087 00:26:38.168610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11088 00:26:38.168856 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11090 00:26:38.171544 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11091 00:26:38.178326 Checks the main Embedded controller character device. ... ok
11092 00:26:38.178427
11093 00:26:38.184813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11094 00:26:38.185058 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11096 00:26:38.188375 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11097 00:26:38.195125 Checks basic comunication with the main Embedded controller. ... ok
11098 00:26:38.195197
11099 00:26:38.201710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11100 00:26:38.201956 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11102 00:26:38.205141 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11103 00:26:38.214813 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11104 00:26:38.214886
11105 00:26:38.218517 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11107 00:26:38.221627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11108 00:26:38.224454 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11109 00:26:38.234753 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11110 00:26:38.234827
11111 00:26:38.237800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11112 00:26:38.238040 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11114 00:26:38.244683 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11115 00:26:38.251412 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11116 00:26:38.251499
11117 00:26:38.257536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11118 00:26:38.257780 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11120 00:26:38.260768 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11121 00:26:38.270805 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11122 00:26:38.270881
11123 00:26:38.277646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11124 00:26:38.277892 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11126 00:26:38.281216 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11127 00:26:38.290548 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11128 00:26:38.290655
11129 00:26:38.297134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11130 00:26:38.297377 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11132 00:26:38.300836 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11133 00:26:38.306962 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11134 00:26:38.307037
11135 00:26:38.313618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11136 00:26:38.313862 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11138 00:26:38.320711 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11139 00:26:38.326862 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11140 00:26:38.326935
11141 00:26:38.333793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11142 00:26:38.334035 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11144 00:26:38.340094 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11145 00:26:38.347322 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11146 00:26:38.349995
11147 00:26:38.353816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11148 00:26:38.354063 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11150 00:26:38.360483 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11151 00:26:38.366892 Check the cros battery ABI. ... skipped 'No BAT found'
11152 00:26:38.366965
11153 00:26:38.373688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11154 00:26:38.373935 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11156 00:26:38.380039 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11157 00:26:38.386591 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11158 00:26:38.386663
11159 00:26:38.393375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11160 00:26:38.393649 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11162 00:26:38.396696 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11163 00:26:38.406351 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11164 00:26:38.406432
11165 00:26:38.409826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11166 00:26:38.410092 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11168 00:26:38.416555 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11169 00:26:38.422802 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11170 00:26:38.422899
11171 00:26:38.429804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11172 00:26:38.429901
11173 00:26:38.430150 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11175 00:26:38.436076 ----------------------------------------------------------------------
11176 00:26:38.439829 Ran 18 tests in 0.006s
11177 00:26:38.439909
11178 00:26:38.439973 OK (skipped=15)
11179 00:26:38.442714 + set +x
11180 00:26:38.442794 <LAVA_TEST_RUNNER EXIT>
11181 00:26:38.443031 ok: lava_test_shell seems to have completed
11182 00:26:38.443207 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11183 00:26:38.443305 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11184 00:26:38.443427 end: 3 lava-test-retry (duration 00:00:01) [common]
11185 00:26:38.443510 start: 4 finalize (timeout 00:07:19) [common]
11186 00:26:38.443597 start: 4.1 power-off (timeout 00:00:30) [common]
11187 00:26:38.443779 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11188 00:26:38.520097 >> Command sent successfully.
11189 00:26:38.522626 Returned 0 in 0 seconds
11190 00:26:38.623088 end: 4.1 power-off (duration 00:00:00) [common]
11192 00:26:38.623516 start: 4.2 read-feedback (timeout 00:07:19) [common]
11193 00:26:38.623942 Listened to connection for namespace 'common' for up to 1s
11194 00:26:39.624816 Finalising connection for namespace 'common'
11195 00:26:39.625002 Disconnecting from shell: Finalise
11196 00:26:39.625116 / #
11197 00:26:39.725474 end: 4.2 read-feedback (duration 00:00:01) [common]
11198 00:26:39.725636 end: 4 finalize (duration 00:00:01) [common]
11199 00:26:39.725775 Cleaning after the job
11200 00:26:39.725877 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11280974/tftp-deploy-im_133ae/ramdisk
11201 00:26:39.732728 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11280974/tftp-deploy-im_133ae/kernel
11202 00:26:39.741524 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11280974/tftp-deploy-im_133ae/dtb
11203 00:26:39.741713 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11280974/tftp-deploy-im_133ae/modules
11204 00:26:39.749068 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11280974
11205 00:26:39.872076 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11280974
11206 00:26:39.872251 Job finished correctly