Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 22
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 131
- Errors: 0
1 00:23:30.722400 lava-dispatcher, installed at version: 2023.05.1
2 00:23:30.722608 start: 0 validate
3 00:23:30.722737 Start time: 2023-08-14 00:23:30.722729+00:00 (UTC)
4 00:23:30.722854 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:23:30.722979 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 00:23:30.990844 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:23:30.991024 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:24:03.504713 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:24:03.505402 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:24:03.774408 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:24:03.774984 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:24:05.540453 validate duration: 34.82
14 00:24:05.540800 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:24:05.540899 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:24:05.541015 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:24:05.541165 Not decompressing ramdisk as can be used compressed.
18 00:24:05.541251 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 00:24:05.541344 saving as /var/lib/lava/dispatcher/tmp/11280945/tftp-deploy-adx72mtx/ramdisk/rootfs.cpio.gz
20 00:24:05.541404 total size: 84918747 (80MB)
21 00:24:05.840919 progress 0% (0MB)
22 00:24:05.862990 progress 5% (4MB)
23 00:24:05.885004 progress 10% (8MB)
24 00:24:05.906902 progress 15% (12MB)
25 00:24:05.929086 progress 20% (16MB)
26 00:24:05.951031 progress 25% (20MB)
27 00:24:05.973164 progress 30% (24MB)
28 00:24:05.995301 progress 35% (28MB)
29 00:24:06.017578 progress 40% (32MB)
30 00:24:06.039845 progress 45% (36MB)
31 00:24:06.061945 progress 50% (40MB)
32 00:24:06.084000 progress 55% (44MB)
33 00:24:06.105988 progress 60% (48MB)
34 00:24:06.128211 progress 65% (52MB)
35 00:24:06.150519 progress 70% (56MB)
36 00:24:06.172629 progress 75% (60MB)
37 00:24:06.194870 progress 80% (64MB)
38 00:24:06.217071 progress 85% (68MB)
39 00:24:06.239493 progress 90% (72MB)
40 00:24:06.261826 progress 95% (76MB)
41 00:24:06.283893 progress 100% (80MB)
42 00:24:06.284125 80MB downloaded in 0.74s (109.04MB/s)
43 00:24:06.284286 end: 1.1.1 http-download (duration 00:00:01) [common]
45 00:24:06.284523 end: 1.1 download-retry (duration 00:00:01) [common]
46 00:24:06.284608 start: 1.2 download-retry (timeout 00:09:59) [common]
47 00:24:06.284738 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 00:24:06.284877 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:24:06.284947 saving as /var/lib/lava/dispatcher/tmp/11280945/tftp-deploy-adx72mtx/kernel/Image
50 00:24:06.285008 total size: 49220096 (46MB)
51 00:24:06.285068 No compression specified
52 00:24:06.286175 progress 0% (0MB)
53 00:24:06.299124 progress 5% (2MB)
54 00:24:06.312232 progress 10% (4MB)
55 00:24:06.325213 progress 15% (7MB)
56 00:24:06.338128 progress 20% (9MB)
57 00:24:06.351203 progress 25% (11MB)
58 00:24:06.364226 progress 30% (14MB)
59 00:24:06.377359 progress 35% (16MB)
60 00:24:06.390319 progress 40% (18MB)
61 00:24:06.403185 progress 45% (21MB)
62 00:24:06.416345 progress 50% (23MB)
63 00:24:06.429925 progress 55% (25MB)
64 00:24:06.443181 progress 60% (28MB)
65 00:24:06.456113 progress 65% (30MB)
66 00:24:06.469243 progress 70% (32MB)
67 00:24:06.482456 progress 75% (35MB)
68 00:24:06.495638 progress 80% (37MB)
69 00:24:06.508829 progress 85% (39MB)
70 00:24:06.521851 progress 90% (42MB)
71 00:24:06.534970 progress 95% (44MB)
72 00:24:06.548163 progress 100% (46MB)
73 00:24:06.548327 46MB downloaded in 0.26s (178.27MB/s)
74 00:24:06.548484 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:24:06.548777 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:24:06.548867 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:24:06.548970 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:24:06.549117 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:24:06.549187 saving as /var/lib/lava/dispatcher/tmp/11280945/tftp-deploy-adx72mtx/dtb/mt8192-asurada-spherion-r0.dtb
81 00:24:06.549274 total size: 47278 (0MB)
82 00:24:06.549347 No compression specified
83 00:24:06.550526 progress 69% (0MB)
84 00:24:06.550830 progress 100% (0MB)
85 00:24:06.550986 0MB downloaded in 0.00s (26.37MB/s)
86 00:24:06.551106 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:24:06.551327 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:24:06.551411 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:24:06.551494 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:24:06.551607 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:24:06.551675 saving as /var/lib/lava/dispatcher/tmp/11280945/tftp-deploy-adx72mtx/modules/modules.tar
93 00:24:06.551735 total size: 8562896 (8MB)
94 00:24:06.551793 Using unxz to decompress xz
95 00:24:06.555922 progress 0% (0MB)
96 00:24:06.578384 progress 5% (0MB)
97 00:24:06.601240 progress 10% (0MB)
98 00:24:06.628084 progress 15% (1MB)
99 00:24:06.654493 progress 20% (1MB)
100 00:24:06.680982 progress 25% (2MB)
101 00:24:06.709308 progress 30% (2MB)
102 00:24:06.735590 progress 35% (2MB)
103 00:24:06.761348 progress 40% (3MB)
104 00:24:06.786126 progress 45% (3MB)
105 00:24:06.814304 progress 50% (4MB)
106 00:24:06.841300 progress 55% (4MB)
107 00:24:06.867140 progress 60% (4MB)
108 00:24:06.890827 progress 65% (5MB)
109 00:24:06.917518 progress 70% (5MB)
110 00:24:06.942705 progress 75% (6MB)
111 00:24:06.972442 progress 80% (6MB)
112 00:24:07.003821 progress 85% (6MB)
113 00:24:07.029920 progress 90% (7MB)
114 00:24:07.054893 progress 95% (7MB)
115 00:24:07.079511 progress 100% (8MB)
116 00:24:07.084840 8MB downloaded in 0.53s (15.32MB/s)
117 00:24:07.085159 end: 1.4.1 http-download (duration 00:00:01) [common]
119 00:24:07.085516 end: 1.4 download-retry (duration 00:00:01) [common]
120 00:24:07.085608 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 00:24:07.085702 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 00:24:07.085783 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:24:07.085867 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 00:24:07.086103 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk
125 00:24:07.086238 makedir: /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin
126 00:24:07.086343 makedir: /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/tests
127 00:24:07.086442 makedir: /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/results
128 00:24:07.086556 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-add-keys
129 00:24:07.086705 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-add-sources
130 00:24:07.086837 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-background-process-start
131 00:24:07.086968 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-background-process-stop
132 00:24:07.087095 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-common-functions
133 00:24:07.087221 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-echo-ipv4
134 00:24:07.087348 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-install-packages
135 00:24:07.087477 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-installed-packages
136 00:24:07.087602 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-os-build
137 00:24:07.087728 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-probe-channel
138 00:24:07.087855 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-probe-ip
139 00:24:07.087983 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-target-ip
140 00:24:07.088107 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-target-mac
141 00:24:07.088231 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-target-storage
142 00:24:07.088361 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-test-case
143 00:24:07.088487 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-test-event
144 00:24:07.088612 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-test-feedback
145 00:24:07.088781 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-test-raise
146 00:24:07.088908 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-test-reference
147 00:24:07.089033 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-test-runner
148 00:24:07.089157 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-test-set
149 00:24:07.089294 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-test-shell
150 00:24:07.089427 Updating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-install-packages (oe)
151 00:24:07.089579 Updating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/bin/lava-installed-packages (oe)
152 00:24:07.089705 Creating /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/environment
153 00:24:07.089807 LAVA metadata
154 00:24:07.089882 - LAVA_JOB_ID=11280945
155 00:24:07.089945 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:24:07.090049 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:58) [common]
157 00:24:07.090115 skipped lava-vland-overlay
158 00:24:07.090188 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:24:07.090266 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:58) [common]
160 00:24:07.090326 skipped lava-multinode-overlay
161 00:24:07.090400 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:24:07.090482 start: 1.5.2.3 test-definition (timeout 00:09:58) [common]
163 00:24:07.090555 Loading test definitions
164 00:24:07.090643 start: 1.5.2.3.1 git-repo-action (timeout 00:09:58) [common]
165 00:24:07.090716 Using /lava-11280945 at stage 0
166 00:24:07.090818 Fetching tests from https://github.com/kernelci/kernelci-core
167 00:24:07.090900 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/0/tests/0_sleep'
168 00:24:07.751943 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/0/tests/0_sleep
169 00:24:07.753362 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 00:24:07.753771 uuid=11280945_1.5.2.3.1 testdef=None
171 00:24:07.753920 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 00:24:07.754213 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 00:24:07.754782 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 00:24:07.755018 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 00:24:07.755715 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 00:24:07.755950 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 00:24:07.756839 runner path: /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/0/tests/0_sleep test_uuid 11280945_1.5.2.3.1
181 00:24:07.756929 sleep_params='mem freeze'
182 00:24:07.757074 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 00:24:07.757284 Creating lava-test-runner.conf files
185 00:24:07.757348 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11280945/lava-overlay-mig_sldk/lava-11280945/0 for stage 0
186 00:24:07.757442 - 0_sleep
187 00:24:07.757550 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 00:24:07.757637 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 00:24:07.883174 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 00:24:07.883335 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 00:24:07.883429 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 00:24:07.883530 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 00:24:07.883623 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 00:24:10.336474 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 00:24:10.336906 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
196 00:24:10.337025 extracting modules file /var/lib/lava/dispatcher/tmp/11280945/tftp-deploy-adx72mtx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11280945/extract-overlay-ramdisk-4niyb4ix/ramdisk
197 00:24:10.564237 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 00:24:10.564410 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 00:24:10.564504 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11280945/compress-overlay-_3s0tzeb/overlay-1.5.2.4.tar.gz to ramdisk
200 00:24:10.564578 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11280945/compress-overlay-_3s0tzeb/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11280945/extract-overlay-ramdisk-4niyb4ix/ramdisk
201 00:24:10.657974 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 00:24:10.658170 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 00:24:10.658269 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 00:24:10.658358 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 00:24:10.658448 Building ramdisk /var/lib/lava/dispatcher/tmp/11280945/extract-overlay-ramdisk-4niyb4ix/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11280945/extract-overlay-ramdisk-4niyb4ix/ramdisk
206 00:24:12.191402 >> 562061 blocks
207 00:24:22.133940 rename /var/lib/lava/dispatcher/tmp/11280945/extract-overlay-ramdisk-4niyb4ix/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11280945/tftp-deploy-adx72mtx/ramdisk/ramdisk.cpio.gz
208 00:24:22.134392 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 00:24:22.134518 start: 1.5.8 prepare-kernel (timeout 00:09:43) [common]
210 00:24:22.134618 start: 1.5.8.1 prepare-fit (timeout 00:09:43) [common]
211 00:24:22.134728 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11280945/tftp-deploy-adx72mtx/kernel/Image'
212 00:24:34.670473 Returned 0 in 12 seconds
213 00:24:34.771358 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11280945/tftp-deploy-adx72mtx/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11280945/tftp-deploy-adx72mtx/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11280945/tftp-deploy-adx72mtx/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11280945/tftp-deploy-adx72mtx/kernel/image.itb
214 00:24:36.107172 output: FIT description: Kernel Image image with one or more FDT blobs
215 00:24:36.107583 output: Created: Mon Aug 14 01:24:35 2023
216 00:24:36.107660 output: Image 0 (kernel-1)
217 00:24:36.107726 output: Description:
218 00:24:36.107791 output: Created: Mon Aug 14 01:24:35 2023
219 00:24:36.107853 output: Type: Kernel Image
220 00:24:36.107914 output: Compression: lzma compressed
221 00:24:36.107973 output: Data Size: 11037315 Bytes = 10778.63 KiB = 10.53 MiB
222 00:24:36.108033 output: Architecture: AArch64
223 00:24:36.108089 output: OS: Linux
224 00:24:36.108151 output: Load Address: 0x00000000
225 00:24:36.108208 output: Entry Point: 0x00000000
226 00:24:36.108264 output: Hash algo: crc32
227 00:24:36.108317 output: Hash value: e7f77b4c
228 00:24:36.108369 output: Image 1 (fdt-1)
229 00:24:36.108421 output: Description: mt8192-asurada-spherion-r0
230 00:24:36.108473 output: Created: Mon Aug 14 01:24:35 2023
231 00:24:36.108526 output: Type: Flat Device Tree
232 00:24:36.108578 output: Compression: uncompressed
233 00:24:36.108630 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 00:24:36.108705 output: Architecture: AArch64
235 00:24:36.108773 output: Hash algo: crc32
236 00:24:36.108826 output: Hash value: cc4352de
237 00:24:36.108877 output: Image 2 (ramdisk-1)
238 00:24:36.108929 output: Description: unavailable
239 00:24:36.108984 output: Created: Mon Aug 14 01:24:35 2023
240 00:24:36.109038 output: Type: RAMDisk Image
241 00:24:36.109134 output: Compression: Unknown Compression
242 00:24:36.109207 output: Data Size: 98208438 Bytes = 95906.68 KiB = 93.66 MiB
243 00:24:36.109262 output: Architecture: AArch64
244 00:24:36.109315 output: OS: Linux
245 00:24:36.109367 output: Load Address: unavailable
246 00:24:36.109445 output: Entry Point: unavailable
247 00:24:36.109568 output: Hash algo: crc32
248 00:24:36.109663 output: Hash value: e1617705
249 00:24:36.109722 output: Default Configuration: 'conf-1'
250 00:24:36.109776 output: Configuration 0 (conf-1)
251 00:24:36.109829 output: Description: mt8192-asurada-spherion-r0
252 00:24:36.109881 output: Kernel: kernel-1
253 00:24:36.109934 output: Init Ramdisk: ramdisk-1
254 00:24:36.109986 output: FDT: fdt-1
255 00:24:36.110038 output: Loadables: kernel-1
256 00:24:36.110090 output:
257 00:24:36.110287 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
258 00:24:36.110383 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
259 00:24:36.110492 end: 1.5 prepare-tftp-overlay (duration 00:00:29) [common]
260 00:24:36.110590 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:29) [common]
261 00:24:36.110669 No LXC device requested
262 00:24:36.110747 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 00:24:36.110828 start: 1.7 deploy-device-env (timeout 00:09:29) [common]
264 00:24:36.110904 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 00:24:36.110971 Checking files for TFTP limit of 4294967296 bytes.
266 00:24:36.111470 end: 1 tftp-deploy (duration 00:00:31) [common]
267 00:24:36.111577 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 00:24:36.111671 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 00:24:36.111791 substitutions:
270 00:24:36.111859 - {DTB}: 11280945/tftp-deploy-adx72mtx/dtb/mt8192-asurada-spherion-r0.dtb
271 00:24:36.111923 - {INITRD}: 11280945/tftp-deploy-adx72mtx/ramdisk/ramdisk.cpio.gz
272 00:24:36.111981 - {KERNEL}: 11280945/tftp-deploy-adx72mtx/kernel/Image
273 00:24:36.112037 - {LAVA_MAC}: None
274 00:24:36.112093 - {PRESEED_CONFIG}: None
275 00:24:36.112166 - {PRESEED_LOCAL}: None
276 00:24:36.112234 - {RAMDISK}: 11280945/tftp-deploy-adx72mtx/ramdisk/ramdisk.cpio.gz
277 00:24:36.112288 - {ROOT_PART}: None
278 00:24:36.112342 - {ROOT}: None
279 00:24:36.112394 - {SERVER_IP}: 192.168.201.1
280 00:24:36.112448 - {TEE}: None
281 00:24:36.112500 Parsed boot commands:
282 00:24:36.112552 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 00:24:36.112801 Parsed boot commands: tftpboot 192.168.201.1 11280945/tftp-deploy-adx72mtx/kernel/image.itb 11280945/tftp-deploy-adx72mtx/kernel/cmdline
284 00:24:36.112892 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 00:24:36.112977 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 00:24:36.113069 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 00:24:36.113155 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 00:24:36.113229 Not connected, no need to disconnect.
289 00:24:36.113303 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 00:24:36.113385 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 00:24:36.113454 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
292 00:24:36.117352 Setting prompt string to ['lava-test: # ']
293 00:24:36.117762 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 00:24:36.117931 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 00:24:36.118027 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 00:24:36.118135 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 00:24:36.118348 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
298 00:24:41.251663 >> Command sent successfully.
299 00:24:41.254117 Returned 0 in 5 seconds
300 00:24:41.354501 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 00:24:41.354833 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 00:24:41.354941 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 00:24:41.355029 Setting prompt string to 'Starting depthcharge on Spherion...'
305 00:24:41.355104 Changing prompt to 'Starting depthcharge on Spherion...'
306 00:24:41.355184 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 00:24:41.355468 [Enter `^Ec?' for help]
308 00:24:41.529489
309 00:24:41.529628
310 00:24:41.529710 F0: 102B 0000
311 00:24:41.529774
312 00:24:41.529835 F3: 1001 0000 [0200]
313 00:24:41.529893
314 00:24:41.533400 F3: 1001 0000
315 00:24:41.533475
316 00:24:41.533537 F7: 102D 0000
317 00:24:41.533604
318 00:24:41.533663 F1: 0000 0000
319 00:24:41.533720
320 00:24:41.536551 V0: 0000 0000 [0001]
321 00:24:41.536624
322 00:24:41.536738 00: 0007 8000
323 00:24:41.536804
324 00:24:41.540856 01: 0000 0000
325 00:24:41.540936
326 00:24:41.541000 BP: 0C00 0209 [0000]
327 00:24:41.541059
328 00:24:41.544254 G0: 1182 0000
329 00:24:41.544330
330 00:24:41.544391 EC: 0000 0021 [4000]
331 00:24:41.544448
332 00:24:41.548122 S7: 0000 0000 [0000]
333 00:24:41.548204
334 00:24:41.548267 CC: 0000 0000 [0001]
335 00:24:41.548327
336 00:24:41.551442 T0: 0000 0040 [010F]
337 00:24:41.551515
338 00:24:41.551582 Jump to BL
339 00:24:41.551642
340 00:24:41.576360
341 00:24:41.576480
342 00:24:41.576609
343 00:24:41.583676 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 00:24:41.587565 ARM64: Exception handlers installed.
345 00:24:41.590935 ARM64: Testing exception
346 00:24:41.595035 ARM64: Done test exception
347 00:24:41.602049 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 00:24:41.608909 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 00:24:41.616258 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 00:24:41.627310 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 00:24:41.633577 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 00:24:41.643659 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 00:24:41.654444 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 00:24:41.661216 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 00:24:41.679076 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 00:24:41.682416 WDT: Last reset was cold boot
357 00:24:41.685699 SPI1(PAD0) initialized at 2873684 Hz
358 00:24:41.689316 SPI5(PAD0) initialized at 992727 Hz
359 00:24:41.692376 VBOOT: Loading verstage.
360 00:24:41.699274 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 00:24:41.702526 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 00:24:41.705554 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 00:24:41.708963 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 00:24:41.716401 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 00:24:41.723116 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 00:24:41.734263 read SPI 0x96554 0xa1eb: 4596 us, 9018 KB/s, 72.144 Mbps
367 00:24:41.734349
368 00:24:41.734415
369 00:24:41.743791 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 00:24:41.747497 ARM64: Exception handlers installed.
371 00:24:41.750741 ARM64: Testing exception
372 00:24:41.750823 ARM64: Done test exception
373 00:24:41.757334 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 00:24:41.760708 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 00:24:41.774893 Probing TPM: . done!
376 00:24:41.774972 TPM ready after 0 ms
377 00:24:41.781389 Connected to device vid:did:rid of 1ae0:0028:00
378 00:24:41.788608 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 00:24:41.847602 Initialized TPM device CR50 revision 0
380 00:24:41.858999 tlcl_send_startup: Startup return code is 0
381 00:24:41.859099 TPM: setup succeeded
382 00:24:41.870449 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 00:24:41.879153 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 00:24:41.891815 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 00:24:41.899955 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 00:24:41.903288 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 00:24:41.911265 in-header: 03 07 00 00 08 00 00 00
388 00:24:41.914997 in-data: aa e4 47 04 13 02 00 00
389 00:24:41.917809 Chrome EC: UHEPI supported
390 00:24:41.924656 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 00:24:41.928596 in-header: 03 ad 00 00 08 00 00 00
392 00:24:41.932237 in-data: 00 20 20 08 00 00 00 00
393 00:24:41.932320 Phase 1
394 00:24:41.935663 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 00:24:41.943240 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 00:24:41.946746 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 00:24:41.950667 Recovery requested (1009000e)
398 00:24:41.959278 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 00:24:41.964800 tlcl_extend: response is 0
400 00:24:41.974706 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 00:24:41.979837 tlcl_extend: response is 0
402 00:24:41.987258 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 00:24:42.007163 read SPI 0x210d4 0x2173b: 15148 us, 9045 KB/s, 72.360 Mbps
404 00:24:42.013406 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 00:24:42.013494
406 00:24:42.013563
407 00:24:42.024030 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 00:24:42.027685 ARM64: Exception handlers installed.
409 00:24:42.027770 ARM64: Testing exception
410 00:24:42.030806 ARM64: Done test exception
411 00:24:42.052385 pmic_efuse_setting: Set efuses in 11 msecs
412 00:24:42.055864 pmwrap_interface_init: Select PMIF_VLD_RDY
413 00:24:42.062574 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 00:24:42.065937 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 00:24:42.073085 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 00:24:42.076351 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 00:24:42.080111 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 00:24:42.083894 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 00:24:42.091330 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 00:24:42.095234 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 00:24:42.098545 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 00:24:42.106236 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 00:24:42.109752 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 00:24:42.113426 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 00:24:42.116733 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 00:24:42.124515 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 00:24:42.132195 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 00:24:42.135692 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 00:24:42.143391 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 00:24:42.147619 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 00:24:42.151444 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 00:24:42.159050 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 00:24:42.162478 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 00:24:42.170224 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 00:24:42.174016 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 00:24:42.181481 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 00:24:42.185462 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 00:24:42.192716 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 00:24:42.196108 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 00:24:42.200181 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 00:24:42.207023 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 00:24:42.210834 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 00:24:42.214397 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 00:24:42.221719 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 00:24:42.225849 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 00:24:42.233130 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 00:24:42.236884 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 00:24:42.240117 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 00:24:42.247516 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 00:24:42.251093 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 00:24:42.255308 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 00:24:42.258815 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 00:24:42.265865 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 00:24:42.269538 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 00:24:42.273737 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 00:24:42.277437 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 00:24:42.281007 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 00:24:42.288029 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 00:24:42.292013 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 00:24:42.295540 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 00:24:42.300058 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 00:24:42.303219 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 00:24:42.307335 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 00:24:42.314224 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 00:24:42.322169 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 00:24:42.328870 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 00:24:42.336574 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 00:24:42.344474 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 00:24:42.351105 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 00:24:42.355040 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 00:24:42.358330 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 00:24:42.366128 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x2b
473 00:24:42.369312 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 00:24:42.377363 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
475 00:24:42.380878 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 00:24:42.390445 [RTC]rtc_get_frequency_meter,154: input=15, output=789
477 00:24:42.399165 [RTC]rtc_get_frequency_meter,154: input=23, output=980
478 00:24:42.408861 [RTC]rtc_get_frequency_meter,154: input=19, output=885
479 00:24:42.418720 [RTC]rtc_get_frequency_meter,154: input=17, output=837
480 00:24:42.428142 [RTC]rtc_get_frequency_meter,154: input=16, output=814
481 00:24:42.437766 [RTC]rtc_get_frequency_meter,154: input=15, output=790
482 00:24:42.447048 [RTC]rtc_get_frequency_meter,154: input=16, output=814
483 00:24:42.450438 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
484 00:24:42.457771 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
485 00:24:42.461199 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 00:24:42.464861 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 00:24:42.468783 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 00:24:42.472247 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 00:24:42.475841 ADC[4]: Raw value=900959 ID=7
490 00:24:42.480326 ADC[3]: Raw value=213336 ID=1
491 00:24:42.480415 RAM Code: 0x71
492 00:24:42.483713 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 00:24:42.491750 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 00:24:42.498115 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 00:24:42.505408 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 00:24:42.509084 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 00:24:42.512921 in-header: 03 07 00 00 08 00 00 00
498 00:24:42.516565 in-data: aa e4 47 04 13 02 00 00
499 00:24:42.516684 Chrome EC: UHEPI supported
500 00:24:42.523910 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 00:24:42.527786 in-header: 03 ed 00 00 08 00 00 00
502 00:24:42.531260 in-data: 80 20 60 08 00 00 00 00
503 00:24:42.535405 MRC: failed to locate region type 0.
504 00:24:42.539293 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 00:24:42.542900 DRAM-K: Running full calibration
506 00:24:42.550562 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 00:24:42.550646 header.status = 0x0
508 00:24:42.554706 header.version = 0x6 (expected: 0x6)
509 00:24:42.558524 header.size = 0xd00 (expected: 0xd00)
510 00:24:42.558607 header.flags = 0x0
511 00:24:42.565278 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 00:24:42.584421 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
513 00:24:42.592277 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 00:24:42.592404 dram_init: ddr_geometry: 2
515 00:24:42.595959 [EMI] MDL number = 2
516 00:24:42.599372 [EMI] Get MDL freq = 0
517 00:24:42.599480 dram_init: ddr_type: 0
518 00:24:42.602924 is_discrete_lpddr4: 1
519 00:24:42.603028 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 00:24:42.606875
521 00:24:42.606990
522 00:24:42.607090 [Bian_co] ETT version 0.0.0.1
523 00:24:42.614588 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 00:24:42.614700
525 00:24:42.617749 dramc_set_vcore_voltage set vcore to 650000
526 00:24:42.617860 Read voltage for 800, 4
527 00:24:42.617952 Vio18 = 0
528 00:24:42.621745 Vcore = 650000
529 00:24:42.621845 Vdram = 0
530 00:24:42.621942 Vddq = 0
531 00:24:42.625554 Vmddr = 0
532 00:24:42.625656 dram_init: config_dvfs: 1
533 00:24:42.632964 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 00:24:42.636904 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 00:24:42.640939 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
536 00:24:42.643972 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
537 00:24:42.647518 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
538 00:24:42.650660 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
539 00:24:42.653900 MEM_TYPE=3, freq_sel=18
540 00:24:42.657543 sv_algorithm_assistance_LP4_1600
541 00:24:42.660561 ============ PULL DRAM RESETB DOWN ============
542 00:24:42.664218 ========== PULL DRAM RESETB DOWN end =========
543 00:24:42.670895 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 00:24:42.674242 ===================================
545 00:24:42.674350 LPDDR4 DRAM CONFIGURATION
546 00:24:42.677765 ===================================
547 00:24:42.680758 EX_ROW_EN[0] = 0x0
548 00:24:42.684477 EX_ROW_EN[1] = 0x0
549 00:24:42.684586 LP4Y_EN = 0x0
550 00:24:42.687930 WORK_FSP = 0x0
551 00:24:42.688040 WL = 0x2
552 00:24:42.691052 RL = 0x2
553 00:24:42.691163 BL = 0x2
554 00:24:42.694385 RPST = 0x0
555 00:24:42.694486 RD_PRE = 0x0
556 00:24:42.697539 WR_PRE = 0x1
557 00:24:42.697638 WR_PST = 0x0
558 00:24:42.700829 DBI_WR = 0x0
559 00:24:42.700923 DBI_RD = 0x0
560 00:24:42.704295 OTF = 0x1
561 00:24:42.708033 ===================================
562 00:24:42.711430 ===================================
563 00:24:42.711513 ANA top config
564 00:24:42.714294 ===================================
565 00:24:42.717967 DLL_ASYNC_EN = 0
566 00:24:42.721299 ALL_SLAVE_EN = 1
567 00:24:42.721381 NEW_RANK_MODE = 1
568 00:24:42.724374 DLL_IDLE_MODE = 1
569 00:24:42.727887 LP45_APHY_COMB_EN = 1
570 00:24:42.731116 TX_ODT_DIS = 1
571 00:24:42.731224 NEW_8X_MODE = 1
572 00:24:42.734505 ===================================
573 00:24:42.737603 ===================================
574 00:24:42.741306 data_rate = 1600
575 00:24:42.744390 CKR = 1
576 00:24:42.747612 DQ_P2S_RATIO = 8
577 00:24:42.751132 ===================================
578 00:24:42.754660 CA_P2S_RATIO = 8
579 00:24:42.758096 DQ_CA_OPEN = 0
580 00:24:42.758195 DQ_SEMI_OPEN = 0
581 00:24:42.761186 CA_SEMI_OPEN = 0
582 00:24:42.764761 CA_FULL_RATE = 0
583 00:24:42.768492 DQ_CKDIV4_EN = 1
584 00:24:42.771528 CA_CKDIV4_EN = 1
585 00:24:42.771627 CA_PREDIV_EN = 0
586 00:24:42.775012 PH8_DLY = 0
587 00:24:42.777932 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 00:24:42.781453 DQ_AAMCK_DIV = 4
589 00:24:42.784699 CA_AAMCK_DIV = 4
590 00:24:42.788227 CA_ADMCK_DIV = 4
591 00:24:42.788336 DQ_TRACK_CA_EN = 0
592 00:24:42.791847 CA_PICK = 800
593 00:24:42.795017 CA_MCKIO = 800
594 00:24:42.798383 MCKIO_SEMI = 0
595 00:24:42.802011 PLL_FREQ = 3068
596 00:24:42.805599 DQ_UI_PI_RATIO = 32
597 00:24:42.805704 CA_UI_PI_RATIO = 0
598 00:24:42.809540 ===================================
599 00:24:42.813555 ===================================
600 00:24:42.817190 memory_type:LPDDR4
601 00:24:42.817284 GP_NUM : 10
602 00:24:42.821255 SRAM_EN : 1
603 00:24:42.821366 MD32_EN : 0
604 00:24:42.824496 ===================================
605 00:24:42.828507 [ANA_INIT] >>>>>>>>>>>>>>
606 00:24:42.832494 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 00:24:42.835683 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 00:24:42.835788 ===================================
609 00:24:42.839053 data_rate = 1600,PCW = 0X7600
610 00:24:42.842072 ===================================
611 00:24:42.845789 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 00:24:42.852451 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 00:24:42.858940 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 00:24:42.862670 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 00:24:42.865823 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 00:24:42.869473 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 00:24:42.872529 [ANA_INIT] flow start
618 00:24:42.872640 [ANA_INIT] PLL >>>>>>>>
619 00:24:42.876103 [ANA_INIT] PLL <<<<<<<<
620 00:24:42.879222 [ANA_INIT] MIDPI >>>>>>>>
621 00:24:42.879326 [ANA_INIT] MIDPI <<<<<<<<
622 00:24:42.882994 [ANA_INIT] DLL >>>>>>>>
623 00:24:42.885847 [ANA_INIT] flow end
624 00:24:42.889198 ============ LP4 DIFF to SE enter ============
625 00:24:42.892857 ============ LP4 DIFF to SE exit ============
626 00:24:42.896309 [ANA_INIT] <<<<<<<<<<<<<
627 00:24:42.899519 [Flow] Enable top DCM control >>>>>
628 00:24:42.903324 [Flow] Enable top DCM control <<<<<
629 00:24:42.906379 Enable DLL master slave shuffle
630 00:24:42.909509 ==============================================================
631 00:24:42.913177 Gating Mode config
632 00:24:42.916281 ==============================================================
633 00:24:42.919522 Config description:
634 00:24:42.929689 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 00:24:42.936219 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 00:24:42.939422 SELPH_MODE 0: By rank 1: By Phase
637 00:24:42.946269 ==============================================================
638 00:24:42.949730 GAT_TRACK_EN = 1
639 00:24:42.953034 RX_GATING_MODE = 2
640 00:24:42.956256 RX_GATING_TRACK_MODE = 2
641 00:24:42.960223 SELPH_MODE = 1
642 00:24:42.960323 PICG_EARLY_EN = 1
643 00:24:42.963344 VALID_LAT_VALUE = 1
644 00:24:42.969918 ==============================================================
645 00:24:42.972980 Enter into Gating configuration >>>>
646 00:24:42.976489 Exit from Gating configuration <<<<
647 00:24:42.979841 Enter into DVFS_PRE_config >>>>>
648 00:24:42.989983 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 00:24:42.992909 Exit from DVFS_PRE_config <<<<<
650 00:24:42.996452 Enter into PICG configuration >>>>
651 00:24:42.999761 Exit from PICG configuration <<<<
652 00:24:43.003310 [RX_INPUT] configuration >>>>>
653 00:24:43.006485 [RX_INPUT] configuration <<<<<
654 00:24:43.010506 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 00:24:43.016864 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 00:24:43.024239 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 00:24:43.027216 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 00:24:43.033929 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 00:24:43.040383 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 00:24:43.044018 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 00:24:43.047211 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 00:24:43.053879 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 00:24:43.057375 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 00:24:43.060764 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 00:24:43.067227 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 00:24:43.067333 ===================================
667 00:24:43.070934 LPDDR4 DRAM CONFIGURATION
668 00:24:43.074056 ===================================
669 00:24:43.077567 EX_ROW_EN[0] = 0x0
670 00:24:43.077639 EX_ROW_EN[1] = 0x0
671 00:24:43.080790 LP4Y_EN = 0x0
672 00:24:43.080883 WORK_FSP = 0x0
673 00:24:43.084073 WL = 0x2
674 00:24:43.084170 RL = 0x2
675 00:24:43.087404 BL = 0x2
676 00:24:43.087504 RPST = 0x0
677 00:24:43.090880 RD_PRE = 0x0
678 00:24:43.090983 WR_PRE = 0x1
679 00:24:43.094230 WR_PST = 0x0
680 00:24:43.094328 DBI_WR = 0x0
681 00:24:43.097890 DBI_RD = 0x0
682 00:24:43.097989 OTF = 0x1
683 00:24:43.101035 ===================================
684 00:24:43.107703 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 00:24:43.111086 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 00:24:43.114181 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 00:24:43.117453 ===================================
688 00:24:43.120935 LPDDR4 DRAM CONFIGURATION
689 00:24:43.124352 ===================================
690 00:24:43.127567 EX_ROW_EN[0] = 0x10
691 00:24:43.127667 EX_ROW_EN[1] = 0x0
692 00:24:43.130966 LP4Y_EN = 0x0
693 00:24:43.131070 WORK_FSP = 0x0
694 00:24:43.134515 WL = 0x2
695 00:24:43.134614 RL = 0x2
696 00:24:43.137801 BL = 0x2
697 00:24:43.137907 RPST = 0x0
698 00:24:43.141308 RD_PRE = 0x0
699 00:24:43.141379 WR_PRE = 0x1
700 00:24:43.144645 WR_PST = 0x0
701 00:24:43.144782 DBI_WR = 0x0
702 00:24:43.147907 DBI_RD = 0x0
703 00:24:43.148013 OTF = 0x1
704 00:24:43.151182 ===================================
705 00:24:43.158047 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 00:24:43.162172 nWR fixed to 40
707 00:24:43.165743 [ModeRegInit_LP4] CH0 RK0
708 00:24:43.165849 [ModeRegInit_LP4] CH0 RK1
709 00:24:43.168617 [ModeRegInit_LP4] CH1 RK0
710 00:24:43.172142 [ModeRegInit_LP4] CH1 RK1
711 00:24:43.172249 match AC timing 13
712 00:24:43.178971 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 00:24:43.182516 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 00:24:43.185739 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 00:24:43.192187 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 00:24:43.195995 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 00:24:43.196104 [EMI DOE] emi_dcm 0
718 00:24:43.202292 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 00:24:43.202402 ==
720 00:24:43.205959 Dram Type= 6, Freq= 0, CH_0, rank 0
721 00:24:43.209124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 00:24:43.209233 ==
723 00:24:43.215808 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 00:24:43.219313 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 00:24:43.229690 [CA 0] Center 37 (7~68) winsize 62
726 00:24:43.232985 [CA 1] Center 37 (6~68) winsize 63
727 00:24:43.236544 [CA 2] Center 35 (5~66) winsize 62
728 00:24:43.239482 [CA 3] Center 34 (4~65) winsize 62
729 00:24:43.243232 [CA 4] Center 34 (3~65) winsize 63
730 00:24:43.246462 [CA 5] Center 33 (3~64) winsize 62
731 00:24:43.246572
732 00:24:43.249808 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 00:24:43.249890
734 00:24:43.253136 [CATrainingPosCal] consider 1 rank data
735 00:24:43.256861 u2DelayCellTimex100 = 270/100 ps
736 00:24:43.259905 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
737 00:24:43.263161 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
738 00:24:43.266456 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
739 00:24:43.273052 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
740 00:24:43.276559 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
741 00:24:43.279859 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
742 00:24:43.279967
743 00:24:43.283000 CA PerBit enable=1, Macro0, CA PI delay=33
744 00:24:43.283104
745 00:24:43.286438 [CBTSetCACLKResult] CA Dly = 33
746 00:24:43.286542 CS Dly: 5 (0~36)
747 00:24:43.286635 ==
748 00:24:43.290273 Dram Type= 6, Freq= 0, CH_0, rank 1
749 00:24:43.296634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 00:24:43.296768 ==
751 00:24:43.299718 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 00:24:43.307144 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 00:24:43.315974 [CA 0] Center 37 (6~68) winsize 63
754 00:24:43.319173 [CA 1] Center 37 (7~68) winsize 62
755 00:24:43.322392 [CA 2] Center 35 (5~66) winsize 62
756 00:24:43.325589 [CA 3] Center 35 (4~66) winsize 63
757 00:24:43.329226 [CA 4] Center 34 (3~65) winsize 63
758 00:24:43.333151 [CA 5] Center 33 (3~64) winsize 62
759 00:24:43.333228
760 00:24:43.336296 [CmdBusTrainingLP45] Vref(ca) range 1: 34
761 00:24:43.336410
762 00:24:43.339470 [CATrainingPosCal] consider 2 rank data
763 00:24:43.342529 u2DelayCellTimex100 = 270/100 ps
764 00:24:43.345922 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
765 00:24:43.349751 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
766 00:24:43.353120 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
767 00:24:43.359543 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
768 00:24:43.362756 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
769 00:24:43.365919 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 00:24:43.366025
771 00:24:43.369334 CA PerBit enable=1, Macro0, CA PI delay=33
772 00:24:43.369440
773 00:24:43.372598 [CBTSetCACLKResult] CA Dly = 33
774 00:24:43.372705 CS Dly: 6 (0~38)
775 00:24:43.372779
776 00:24:43.376026 ----->DramcWriteLeveling(PI) begin...
777 00:24:43.376130 ==
778 00:24:43.379701 Dram Type= 6, Freq= 0, CH_0, rank 0
779 00:24:43.383392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 00:24:43.386539 ==
781 00:24:43.386645 Write leveling (Byte 0): 30 => 30
782 00:24:43.390397 Write leveling (Byte 1): 29 => 29
783 00:24:43.394114 DramcWriteLeveling(PI) end<-----
784 00:24:43.394205
785 00:24:43.394292 ==
786 00:24:43.398326 Dram Type= 6, Freq= 0, CH_0, rank 0
787 00:24:43.401143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 00:24:43.401225 ==
789 00:24:43.405032 [Gating] SW mode calibration
790 00:24:43.411412 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 00:24:43.419203 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 00:24:43.422018 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 00:24:43.425916 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
794 00:24:43.428933 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
795 00:24:43.435506 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 00:24:43.438882 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 00:24:43.442796 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 00:24:43.448834 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 00:24:43.452626 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:24:43.455740 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:24:43.462606 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:24:43.465967 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 00:24:43.469131 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 00:24:43.476126 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 00:24:43.480232 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 00:24:43.483089 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 00:24:43.485902 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 00:24:43.492697 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 00:24:43.496386 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 00:24:43.499515 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
811 00:24:43.506205 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
812 00:24:43.509596 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 00:24:43.513335 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 00:24:43.520004 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 00:24:43.523032 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 00:24:43.526358 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 00:24:43.533414 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 00:24:43.536314 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 00:24:43.539731 0 9 12 | B1->B0 | 2a2a 3232 | 1 1 | (0 0) (0 0)
820 00:24:43.543013 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 00:24:43.550233 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 00:24:43.553274 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 00:24:43.556812 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 00:24:43.563346 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 00:24:43.566781 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
826 00:24:43.570054 0 10 8 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (0 1)
827 00:24:43.576736 0 10 12 | B1->B0 | 2e2e 2424 | 0 0 | (1 1) (0 0)
828 00:24:43.580450 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 00:24:43.583354 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 00:24:43.590257 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 00:24:43.594083 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 00:24:43.596897 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 00:24:43.600527 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 00:24:43.607183 0 11 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
835 00:24:43.610661 0 11 12 | B1->B0 | 3737 4444 | 0 0 | (1 1) (0 0)
836 00:24:43.613878 0 11 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
837 00:24:43.620428 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 00:24:43.623958 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 00:24:43.627344 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 00:24:43.633962 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 00:24:43.637296 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 00:24:43.641129 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
843 00:24:43.644217 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
844 00:24:43.651181 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 00:24:43.654298 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 00:24:43.657601 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 00:24:43.664096 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 00:24:43.667606 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 00:24:43.670953 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 00:24:43.677783 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 00:24:43.681180 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 00:24:43.684517 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 00:24:43.691117 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 00:24:43.694522 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 00:24:43.697757 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 00:24:43.701453 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 00:24:43.708104 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 00:24:43.711429 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
859 00:24:43.714423 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
860 00:24:43.718207 Total UI for P1: 0, mck2ui 16
861 00:24:43.721534 best dqsien dly found for B0: ( 0, 14, 8)
862 00:24:43.724768 Total UI for P1: 0, mck2ui 16
863 00:24:43.728280 best dqsien dly found for B1: ( 0, 14, 8)
864 00:24:43.731849 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
865 00:24:43.735199 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
866 00:24:43.735298
867 00:24:43.741559 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
868 00:24:43.745330 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 00:24:43.745457 [Gating] SW calibration Done
870 00:24:43.747969 ==
871 00:24:43.748043 Dram Type= 6, Freq= 0, CH_0, rank 0
872 00:24:43.754856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
873 00:24:43.754938 ==
874 00:24:43.755031 RX Vref Scan: 0
875 00:24:43.755110
876 00:24:43.758120 RX Vref 0 -> 0, step: 1
877 00:24:43.758237
878 00:24:43.761584 RX Delay -130 -> 252, step: 16
879 00:24:43.764675 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
880 00:24:43.768746 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
881 00:24:43.771902 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
882 00:24:43.778143 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
883 00:24:43.781879 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
884 00:24:43.785375 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
885 00:24:43.788402 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
886 00:24:43.791733 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
887 00:24:43.794951 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
888 00:24:43.801817 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
889 00:24:43.805036 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
890 00:24:43.808523 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
891 00:24:43.812000 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
892 00:24:43.815558 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
893 00:24:43.822138 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
894 00:24:43.825501 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
895 00:24:43.825620 ==
896 00:24:43.828472 Dram Type= 6, Freq= 0, CH_0, rank 0
897 00:24:43.832191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 00:24:43.832296 ==
899 00:24:43.835655 DQS Delay:
900 00:24:43.835769 DQS0 = 0, DQS1 = 0
901 00:24:43.835864 DQM Delay:
902 00:24:43.838632 DQM0 = 88, DQM1 = 81
903 00:24:43.838729 DQ Delay:
904 00:24:43.842142 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
905 00:24:43.845111 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =101
906 00:24:43.848812 DQ8 =61, DQ9 =69, DQ10 =85, DQ11 =69
907 00:24:43.852208 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =93
908 00:24:43.852306
909 00:24:43.852400
910 00:24:43.852489 ==
911 00:24:43.855315 Dram Type= 6, Freq= 0, CH_0, rank 0
912 00:24:43.862257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 00:24:43.862360 ==
914 00:24:43.862436
915 00:24:43.862498
916 00:24:43.862556 TX Vref Scan disable
917 00:24:43.865673 == TX Byte 0 ==
918 00:24:43.869327 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
919 00:24:43.872853 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
920 00:24:43.875873 == TX Byte 1 ==
921 00:24:43.878906 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
922 00:24:43.882546 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
923 00:24:43.885854 ==
924 00:24:43.889581 Dram Type= 6, Freq= 0, CH_0, rank 0
925 00:24:43.892305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 00:24:43.892408 ==
927 00:24:43.905085 TX Vref=22, minBit 3, minWin=27, winSum=440
928 00:24:43.908139 TX Vref=24, minBit 5, minWin=27, winSum=445
929 00:24:43.911629 TX Vref=26, minBit 5, minWin=27, winSum=443
930 00:24:43.914854 TX Vref=28, minBit 12, minWin=27, winSum=451
931 00:24:43.918261 TX Vref=30, minBit 12, minWin=27, winSum=451
932 00:24:43.921747 TX Vref=32, minBit 2, minWin=28, winSum=454
933 00:24:43.929113 [TxChooseVref] Worse bit 2, Min win 28, Win sum 454, Final Vref 32
934 00:24:43.929217
935 00:24:43.932071 Final TX Range 1 Vref 32
936 00:24:43.932181
937 00:24:43.932270 ==
938 00:24:43.934900 Dram Type= 6, Freq= 0, CH_0, rank 0
939 00:24:43.938995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 00:24:43.939092 ==
941 00:24:43.939183
942 00:24:43.939274
943 00:24:43.941775 TX Vref Scan disable
944 00:24:43.945241 == TX Byte 0 ==
945 00:24:43.948807 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
946 00:24:43.951905 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
947 00:24:43.955718 == TX Byte 1 ==
948 00:24:43.958569 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
949 00:24:43.961917 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
950 00:24:43.961989
951 00:24:43.965260 [DATLAT]
952 00:24:43.965363 Freq=800, CH0 RK0
953 00:24:43.965453
954 00:24:43.968804 DATLAT Default: 0xa
955 00:24:43.968894 0, 0xFFFF, sum = 0
956 00:24:43.972034 1, 0xFFFF, sum = 0
957 00:24:43.972147 2, 0xFFFF, sum = 0
958 00:24:43.975471 3, 0xFFFF, sum = 0
959 00:24:43.975577 4, 0xFFFF, sum = 0
960 00:24:43.979171 5, 0xFFFF, sum = 0
961 00:24:43.979280 6, 0xFFFF, sum = 0
962 00:24:43.982202 7, 0xFFFF, sum = 0
963 00:24:43.982302 8, 0xFFFF, sum = 0
964 00:24:43.985659 9, 0x0, sum = 1
965 00:24:43.985752 10, 0x0, sum = 2
966 00:24:43.988825 11, 0x0, sum = 3
967 00:24:43.988934 12, 0x0, sum = 4
968 00:24:43.992161 best_step = 10
969 00:24:43.992264
970 00:24:43.992359 ==
971 00:24:43.995658 Dram Type= 6, Freq= 0, CH_0, rank 0
972 00:24:43.998976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 00:24:43.999087 ==
974 00:24:43.999188 RX Vref Scan: 1
975 00:24:43.999276
976 00:24:44.002136 Set Vref Range= 32 -> 127
977 00:24:44.002235
978 00:24:44.005698 RX Vref 32 -> 127, step: 1
979 00:24:44.005771
980 00:24:44.009395 RX Delay -95 -> 252, step: 8
981 00:24:44.009501
982 00:24:44.012601 Set Vref, RX VrefLevel [Byte0]: 32
983 00:24:44.016200 [Byte1]: 32
984 00:24:44.016298
985 00:24:44.019064 Set Vref, RX VrefLevel [Byte0]: 33
986 00:24:44.022868 [Byte1]: 33
987 00:24:44.022972
988 00:24:44.026234 Set Vref, RX VrefLevel [Byte0]: 34
989 00:24:44.030245 [Byte1]: 34
990 00:24:44.030360
991 00:24:44.033264 Set Vref, RX VrefLevel [Byte0]: 35
992 00:24:44.036883 [Byte1]: 35
993 00:24:44.040297
994 00:24:44.040392 Set Vref, RX VrefLevel [Byte0]: 36
995 00:24:44.043826 [Byte1]: 36
996 00:24:44.047878
997 00:24:44.047977 Set Vref, RX VrefLevel [Byte0]: 37
998 00:24:44.051285 [Byte1]: 37
999 00:24:44.056062
1000 00:24:44.056174 Set Vref, RX VrefLevel [Byte0]: 38
1001 00:24:44.059373 [Byte1]: 38
1002 00:24:44.064391
1003 00:24:44.064492 Set Vref, RX VrefLevel [Byte0]: 39
1004 00:24:44.067117 [Byte1]: 39
1005 00:24:44.070990
1006 00:24:44.071093 Set Vref, RX VrefLevel [Byte0]: 40
1007 00:24:44.074505 [Byte1]: 40
1008 00:24:44.078862
1009 00:24:44.078981 Set Vref, RX VrefLevel [Byte0]: 41
1010 00:24:44.082289 [Byte1]: 41
1011 00:24:44.086656
1012 00:24:44.086776 Set Vref, RX VrefLevel [Byte0]: 42
1013 00:24:44.089771 [Byte1]: 42
1014 00:24:44.093438
1015 00:24:44.093542 Set Vref, RX VrefLevel [Byte0]: 43
1016 00:24:44.096822 [Byte1]: 43
1017 00:24:44.100987
1018 00:24:44.101088 Set Vref, RX VrefLevel [Byte0]: 44
1019 00:24:44.104246 [Byte1]: 44
1020 00:24:44.108966
1021 00:24:44.109048 Set Vref, RX VrefLevel [Byte0]: 45
1022 00:24:44.112188 [Byte1]: 45
1023 00:24:44.116760
1024 00:24:44.116857 Set Vref, RX VrefLevel [Byte0]: 46
1025 00:24:44.119801 [Byte1]: 46
1026 00:24:44.123997
1027 00:24:44.124095 Set Vref, RX VrefLevel [Byte0]: 47
1028 00:24:44.127455 [Byte1]: 47
1029 00:24:44.131750
1030 00:24:44.131845 Set Vref, RX VrefLevel [Byte0]: 48
1031 00:24:44.135068 [Byte1]: 48
1032 00:24:44.139263
1033 00:24:44.139363 Set Vref, RX VrefLevel [Byte0]: 49
1034 00:24:44.142632 [Byte1]: 49
1035 00:24:44.146846
1036 00:24:44.146917 Set Vref, RX VrefLevel [Byte0]: 50
1037 00:24:44.149967 [Byte1]: 50
1038 00:24:44.154606
1039 00:24:44.154674 Set Vref, RX VrefLevel [Byte0]: 51
1040 00:24:44.157540 [Byte1]: 51
1041 00:24:44.162278
1042 00:24:44.162376 Set Vref, RX VrefLevel [Byte0]: 52
1043 00:24:44.165760 [Byte1]: 52
1044 00:24:44.169423
1045 00:24:44.169506 Set Vref, RX VrefLevel [Byte0]: 53
1046 00:24:44.173156 [Byte1]: 53
1047 00:24:44.177372
1048 00:24:44.177471 Set Vref, RX VrefLevel [Byte0]: 54
1049 00:24:44.180529 [Byte1]: 54
1050 00:24:44.184808
1051 00:24:44.184902 Set Vref, RX VrefLevel [Byte0]: 55
1052 00:24:44.188495 [Byte1]: 55
1053 00:24:44.192233
1054 00:24:44.192334 Set Vref, RX VrefLevel [Byte0]: 56
1055 00:24:44.195364 [Byte1]: 56
1056 00:24:44.200685
1057 00:24:44.200773 Set Vref, RX VrefLevel [Byte0]: 57
1058 00:24:44.203121 [Byte1]: 57
1059 00:24:44.207548
1060 00:24:44.207651 Set Vref, RX VrefLevel [Byte0]: 58
1061 00:24:44.210913 [Byte1]: 58
1062 00:24:44.215063
1063 00:24:44.215157 Set Vref, RX VrefLevel [Byte0]: 59
1064 00:24:44.218438 [Byte1]: 59
1065 00:24:44.222682
1066 00:24:44.222781 Set Vref, RX VrefLevel [Byte0]: 60
1067 00:24:44.226168 [Byte1]: 60
1068 00:24:44.230694
1069 00:24:44.230799 Set Vref, RX VrefLevel [Byte0]: 61
1070 00:24:44.233604 [Byte1]: 61
1071 00:24:44.237845
1072 00:24:44.237946 Set Vref, RX VrefLevel [Byte0]: 62
1073 00:24:44.240996 [Byte1]: 62
1074 00:24:44.245807
1075 00:24:44.245905 Set Vref, RX VrefLevel [Byte0]: 63
1076 00:24:44.248841 [Byte1]: 63
1077 00:24:44.252939
1078 00:24:44.253015 Set Vref, RX VrefLevel [Byte0]: 64
1079 00:24:44.256558 [Byte1]: 64
1080 00:24:44.260570
1081 00:24:44.260679 Set Vref, RX VrefLevel [Byte0]: 65
1082 00:24:44.263739 [Byte1]: 65
1083 00:24:44.268715
1084 00:24:44.268791 Set Vref, RX VrefLevel [Byte0]: 66
1085 00:24:44.271409 [Byte1]: 66
1086 00:24:44.275856
1087 00:24:44.275976 Set Vref, RX VrefLevel [Byte0]: 67
1088 00:24:44.279536 [Byte1]: 67
1089 00:24:44.283498
1090 00:24:44.283605 Set Vref, RX VrefLevel [Byte0]: 68
1091 00:24:44.286851 [Byte1]: 68
1092 00:24:44.290876
1093 00:24:44.290984 Set Vref, RX VrefLevel [Byte0]: 69
1094 00:24:44.294138 [Byte1]: 69
1095 00:24:44.298542
1096 00:24:44.298643 Set Vref, RX VrefLevel [Byte0]: 70
1097 00:24:44.301980 [Byte1]: 70
1098 00:24:44.306026
1099 00:24:44.306123 Set Vref, RX VrefLevel [Byte0]: 71
1100 00:24:44.309507 [Byte1]: 71
1101 00:24:44.313689
1102 00:24:44.313788 Set Vref, RX VrefLevel [Byte0]: 72
1103 00:24:44.317354 [Byte1]: 72
1104 00:24:44.321166
1105 00:24:44.321276 Set Vref, RX VrefLevel [Byte0]: 73
1106 00:24:44.324885 [Byte1]: 73
1107 00:24:44.328931
1108 00:24:44.329006 Set Vref, RX VrefLevel [Byte0]: 74
1109 00:24:44.332244 [Byte1]: 74
1110 00:24:44.336462
1111 00:24:44.336565 Set Vref, RX VrefLevel [Byte0]: 75
1112 00:24:44.339827 [Byte1]: 75
1113 00:24:44.344408
1114 00:24:44.344508 Final RX Vref Byte 0 = 62 to rank0
1115 00:24:44.347324 Final RX Vref Byte 1 = 58 to rank0
1116 00:24:44.350775 Final RX Vref Byte 0 = 62 to rank1
1117 00:24:44.353861 Final RX Vref Byte 1 = 58 to rank1==
1118 00:24:44.357496 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 00:24:44.360860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 00:24:44.364023 ==
1121 00:24:44.364121 DQS Delay:
1122 00:24:44.364215 DQS0 = 0, DQS1 = 0
1123 00:24:44.367414 DQM Delay:
1124 00:24:44.367530 DQM0 = 88, DQM1 = 78
1125 00:24:44.371029 DQ Delay:
1126 00:24:44.374196 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1127 00:24:44.374298 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1128 00:24:44.378080 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1129 00:24:44.381702 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1130 00:24:44.381801
1131 00:24:44.384588
1132 00:24:44.391120 [DQSOSCAuto] RK0, (LSB)MR18= 0x2910, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
1133 00:24:44.394231 CH0 RK0: MR19=606, MR18=2910
1134 00:24:44.401467 CH0_RK0: MR19=0x606, MR18=0x2910, DQSOSC=399, MR23=63, INC=92, DEC=61
1135 00:24:44.401567
1136 00:24:44.404331 ----->DramcWriteLeveling(PI) begin...
1137 00:24:44.404437 ==
1138 00:24:44.407913 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 00:24:44.411015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 00:24:44.411117 ==
1141 00:24:44.414433 Write leveling (Byte 0): 32 => 32
1142 00:24:44.418157 Write leveling (Byte 1): 31 => 31
1143 00:24:44.421428 DramcWriteLeveling(PI) end<-----
1144 00:24:44.421532
1145 00:24:44.421624 ==
1146 00:24:44.424836 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 00:24:44.428258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 00:24:44.428357 ==
1149 00:24:44.431241 [Gating] SW mode calibration
1150 00:24:44.438416 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 00:24:44.441472 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 00:24:44.448269 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 00:24:44.451796 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1154 00:24:44.455205 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 00:24:44.461496 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 00:24:44.465046 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 00:24:44.509212 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 00:24:44.509510 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 00:24:44.510072 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 00:24:44.510187 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 00:24:44.510463 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 00:24:44.510557 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 00:24:44.510977 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 00:24:44.511328 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 00:24:44.511445 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 00:24:44.511730 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 00:24:44.514328 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 00:24:44.517625 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1169 00:24:44.520789 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1170 00:24:44.527444 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1171 00:24:44.531211 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 00:24:44.534156 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 00:24:44.540947 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 00:24:44.544356 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:24:44.547778 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:24:44.554542 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 00:24:44.557868 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 00:24:44.561350 0 9 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
1179 00:24:44.564415 0 9 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1180 00:24:44.571150 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 00:24:44.575020 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 00:24:44.577935 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 00:24:44.584782 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 00:24:44.588086 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 00:24:44.591274 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
1186 00:24:44.598470 0 10 8 | B1->B0 | 2f2f 2424 | 0 0 | (1 1) (0 0)
1187 00:24:44.601575 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1188 00:24:44.604989 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 00:24:44.611744 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 00:24:44.614839 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 00:24:44.618367 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 00:24:44.621910 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 00:24:44.628467 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1194 00:24:44.631822 0 11 8 | B1->B0 | 2f2f 4040 | 0 0 | (0 0) (0 0)
1195 00:24:44.635574 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1196 00:24:44.639580 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 00:24:44.646619 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 00:24:44.650474 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 00:24:44.653876 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 00:24:44.657518 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 00:24:44.664652 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1202 00:24:44.667895 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1203 00:24:44.671486 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 00:24:44.674414 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 00:24:44.681400 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 00:24:44.684586 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 00:24:44.688369 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 00:24:44.694610 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 00:24:44.698223 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 00:24:44.701523 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 00:24:44.708127 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 00:24:44.711258 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 00:24:44.714848 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 00:24:44.721973 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 00:24:44.724911 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 00:24:44.728413 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 00:24:44.731472 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1218 00:24:44.738424 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1219 00:24:44.741793 Total UI for P1: 0, mck2ui 16
1220 00:24:44.745281 best dqsien dly found for B0: ( 0, 14, 4)
1221 00:24:44.748236 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 00:24:44.751834 Total UI for P1: 0, mck2ui 16
1223 00:24:44.755241 best dqsien dly found for B1: ( 0, 14, 6)
1224 00:24:44.758790 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1225 00:24:44.761881 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1226 00:24:44.761978
1227 00:24:44.765031 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1228 00:24:44.768901 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1229 00:24:44.772183 [Gating] SW calibration Done
1230 00:24:44.772292 ==
1231 00:24:44.775235 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 00:24:44.778648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 00:24:44.778749 ==
1234 00:24:44.781981 RX Vref Scan: 0
1235 00:24:44.782092
1236 00:24:44.785464 RX Vref 0 -> 0, step: 1
1237 00:24:44.785574
1238 00:24:44.785665 RX Delay -130 -> 252, step: 16
1239 00:24:44.792204 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1240 00:24:44.795490 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1241 00:24:44.799013 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1242 00:24:44.802150 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1243 00:24:44.805594 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1244 00:24:44.809032 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1245 00:24:44.815622 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1246 00:24:44.818925 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1247 00:24:44.822223 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1248 00:24:44.825995 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1249 00:24:44.829003 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1250 00:24:44.835711 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1251 00:24:44.839121 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1252 00:24:44.842672 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1253 00:24:44.846047 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1254 00:24:44.849488 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1255 00:24:44.852879 ==
1256 00:24:44.856153 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 00:24:44.860015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 00:24:44.860119 ==
1259 00:24:44.860209 DQS Delay:
1260 00:24:44.863155 DQS0 = 0, DQS1 = 0
1261 00:24:44.863283 DQM Delay:
1262 00:24:44.863402 DQM0 = 87, DQM1 = 78
1263 00:24:44.866806 DQ Delay:
1264 00:24:44.869747 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1265 00:24:44.873356 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
1266 00:24:44.876418 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1267 00:24:44.879961 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1268 00:24:44.880062
1269 00:24:44.880151
1270 00:24:44.880242 ==
1271 00:24:44.883171 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 00:24:44.886541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 00:24:44.886642 ==
1274 00:24:44.886763
1275 00:24:44.886846
1276 00:24:44.889549 TX Vref Scan disable
1277 00:24:44.889654 == TX Byte 0 ==
1278 00:24:44.897307 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1279 00:24:44.899985 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1280 00:24:44.900081 == TX Byte 1 ==
1281 00:24:44.906802 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1282 00:24:44.910187 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1283 00:24:44.910297 ==
1284 00:24:44.913498 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 00:24:44.917076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 00:24:44.917158 ==
1287 00:24:44.930417 TX Vref=22, minBit 5, minWin=27, winSum=445
1288 00:24:44.933849 TX Vref=24, minBit 9, minWin=27, winSum=449
1289 00:24:44.937679 TX Vref=26, minBit 9, minWin=27, winSum=449
1290 00:24:44.940468 TX Vref=28, minBit 9, minWin=27, winSum=451
1291 00:24:44.944156 TX Vref=30, minBit 4, minWin=28, winSum=456
1292 00:24:44.947449 TX Vref=32, minBit 4, minWin=28, winSum=457
1293 00:24:44.954193 [TxChooseVref] Worse bit 4, Min win 28, Win sum 457, Final Vref 32
1294 00:24:44.954275
1295 00:24:44.958005 Final TX Range 1 Vref 32
1296 00:24:44.958078
1297 00:24:44.958146 ==
1298 00:24:44.960655 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 00:24:44.964233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 00:24:44.964305 ==
1301 00:24:44.964365
1302 00:24:44.964420
1303 00:24:44.967841 TX Vref Scan disable
1304 00:24:44.971068 == TX Byte 0 ==
1305 00:24:44.974367 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1306 00:24:44.977838 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1307 00:24:44.981200 == TX Byte 1 ==
1308 00:24:44.984493 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1309 00:24:44.988012 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1310 00:24:44.988113
1311 00:24:44.991551 [DATLAT]
1312 00:24:44.991658 Freq=800, CH0 RK1
1313 00:24:44.991750
1314 00:24:44.994378 DATLAT Default: 0xa
1315 00:24:44.994489 0, 0xFFFF, sum = 0
1316 00:24:44.997776 1, 0xFFFF, sum = 0
1317 00:24:44.997877 2, 0xFFFF, sum = 0
1318 00:24:45.001381 3, 0xFFFF, sum = 0
1319 00:24:45.001457 4, 0xFFFF, sum = 0
1320 00:24:45.004833 5, 0xFFFF, sum = 0
1321 00:24:45.004934 6, 0xFFFF, sum = 0
1322 00:24:45.008344 7, 0xFFFF, sum = 0
1323 00:24:45.008456 8, 0xFFFF, sum = 0
1324 00:24:45.011602 9, 0x0, sum = 1
1325 00:24:45.011703 10, 0x0, sum = 2
1326 00:24:45.014777 11, 0x0, sum = 3
1327 00:24:45.014889 12, 0x0, sum = 4
1328 00:24:45.014982 best_step = 10
1329 00:24:45.018218
1330 00:24:45.018321 ==
1331 00:24:45.021913 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 00:24:45.025004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 00:24:45.025076 ==
1334 00:24:45.025138 RX Vref Scan: 0
1335 00:24:45.025211
1336 00:24:45.028348 RX Vref 0 -> 0, step: 1
1337 00:24:45.028474
1338 00:24:45.031524 RX Delay -95 -> 252, step: 8
1339 00:24:45.035508 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1340 00:24:45.038628 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1341 00:24:45.045170 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1342 00:24:45.048654 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1343 00:24:45.052078 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1344 00:24:45.055002 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1345 00:24:45.058722 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1346 00:24:45.065631 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1347 00:24:45.068845 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1348 00:24:45.071934 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1349 00:24:45.075427 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1350 00:24:45.078912 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1351 00:24:45.085576 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1352 00:24:45.088979 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1353 00:24:45.091966 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1354 00:24:45.095436 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1355 00:24:45.095537 ==
1356 00:24:45.099641 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 00:24:45.102679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 00:24:45.102791 ==
1359 00:24:45.105641 DQS Delay:
1360 00:24:45.105741 DQS0 = 0, DQS1 = 0
1361 00:24:45.109347 DQM Delay:
1362 00:24:45.109454 DQM0 = 87, DQM1 = 78
1363 00:24:45.109548 DQ Delay:
1364 00:24:45.112570 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1365 00:24:45.115857 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1366 00:24:45.119372 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1367 00:24:45.122647 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1368 00:24:45.122747
1369 00:24:45.122845
1370 00:24:45.132509 [DQSOSCAuto] RK1, (LSB)MR18= 0x311a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1371 00:24:45.136456 CH0 RK1: MR19=606, MR18=311A
1372 00:24:45.139216 CH0_RK1: MR19=0x606, MR18=0x311A, DQSOSC=397, MR23=63, INC=93, DEC=62
1373 00:24:45.142831 [RxdqsGatingPostProcess] freq 800
1374 00:24:45.149465 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 00:24:45.152965 Pre-setting of DQS Precalculation
1376 00:24:45.155991 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 00:24:45.156120 ==
1378 00:24:45.159469 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 00:24:45.166494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 00:24:45.166627 ==
1381 00:24:45.169640 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 00:24:45.176124 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 00:24:45.185793 [CA 0] Center 36 (6~67) winsize 62
1384 00:24:45.189113 [CA 1] Center 36 (6~67) winsize 62
1385 00:24:45.192258 [CA 2] Center 34 (4~64) winsize 61
1386 00:24:45.195538 [CA 3] Center 33 (3~64) winsize 62
1387 00:24:45.198662 [CA 4] Center 34 (3~65) winsize 63
1388 00:24:45.202143 [CA 5] Center 33 (3~64) winsize 62
1389 00:24:45.202261
1390 00:24:45.205951 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1391 00:24:45.206080
1392 00:24:45.208872 [CATrainingPosCal] consider 1 rank data
1393 00:24:45.212346 u2DelayCellTimex100 = 270/100 ps
1394 00:24:45.215838 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1395 00:24:45.219383 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1396 00:24:45.222383 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1397 00:24:45.229382 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1398 00:24:45.232780 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1399 00:24:45.235928 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1400 00:24:45.236029
1401 00:24:45.239393 CA PerBit enable=1, Macro0, CA PI delay=33
1402 00:24:45.239516
1403 00:24:45.242427 [CBTSetCACLKResult] CA Dly = 33
1404 00:24:45.242536 CS Dly: 4 (0~35)
1405 00:24:45.242625 ==
1406 00:24:45.245993 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 00:24:45.252257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 00:24:45.252361 ==
1409 00:24:45.255809 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 00:24:45.262529 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 00:24:45.271588 [CA 0] Center 36 (5~67) winsize 63
1412 00:24:45.274799 [CA 1] Center 36 (6~67) winsize 62
1413 00:24:45.278159 [CA 2] Center 34 (4~64) winsize 61
1414 00:24:45.281749 [CA 3] Center 33 (3~64) winsize 62
1415 00:24:45.285147 [CA 4] Center 33 (3~64) winsize 62
1416 00:24:45.288451 [CA 5] Center 33 (3~64) winsize 62
1417 00:24:45.288548
1418 00:24:45.291620 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1419 00:24:45.291718
1420 00:24:45.295013 [CATrainingPosCal] consider 2 rank data
1421 00:24:45.298511 u2DelayCellTimex100 = 270/100 ps
1422 00:24:45.302261 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1423 00:24:45.305234 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1424 00:24:45.309028 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1425 00:24:45.313056 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1426 00:24:45.316573 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1427 00:24:45.320187 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1428 00:24:45.320290
1429 00:24:45.323865 CA PerBit enable=1, Macro0, CA PI delay=33
1430 00:24:45.323970
1431 00:24:45.327605 [CBTSetCACLKResult] CA Dly = 33
1432 00:24:45.331257 CS Dly: 5 (0~37)
1433 00:24:45.331364
1434 00:24:45.331468 ----->DramcWriteLeveling(PI) begin...
1435 00:24:45.335006 ==
1436 00:24:45.335119 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 00:24:45.341909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 00:24:45.341992 ==
1439 00:24:45.345550 Write leveling (Byte 0): 25 => 25
1440 00:24:45.345652 Write leveling (Byte 1): 30 => 30
1441 00:24:45.348830 DramcWriteLeveling(PI) end<-----
1442 00:24:45.348927
1443 00:24:45.349015 ==
1444 00:24:45.352480 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 00:24:45.358638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 00:24:45.358716 ==
1447 00:24:45.362320 [Gating] SW mode calibration
1448 00:24:45.368998 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 00:24:45.372211 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 00:24:45.375730 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 00:24:45.382269 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1452 00:24:45.385447 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1453 00:24:45.388833 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 00:24:45.395632 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 00:24:45.399222 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 00:24:45.402485 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 00:24:45.409344 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 00:24:45.412534 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 00:24:45.415680 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 00:24:45.422975 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 00:24:45.425951 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 00:24:45.429153 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 00:24:45.432642 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 00:24:45.439523 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 00:24:45.443107 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 00:24:45.446586 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 00:24:45.453172 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1468 00:24:45.456220 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 00:24:45.459802 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1470 00:24:45.466613 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 00:24:45.469608 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 00:24:45.472996 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 00:24:45.480369 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 00:24:45.483393 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 00:24:45.486473 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 00:24:45.490174 0 9 8 | B1->B0 | 2424 2424 | 0 1 | (0 0) (0 0)
1477 00:24:45.496515 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 00:24:45.499945 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1479 00:24:45.503356 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 00:24:45.509910 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 00:24:45.513346 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 00:24:45.516531 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1483 00:24:45.523467 0 10 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1484 00:24:45.526625 0 10 8 | B1->B0 | 2626 3030 | 0 0 | (1 1) (0 1)
1485 00:24:45.530285 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 00:24:45.536576 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 00:24:45.540566 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 00:24:45.543876 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 00:24:45.546744 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1490 00:24:45.553587 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 00:24:45.557246 0 11 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1492 00:24:45.560413 0 11 8 | B1->B0 | 3838 3939 | 0 0 | (0 0) (0 0)
1493 00:24:45.567465 0 11 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1494 00:24:45.570402 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 00:24:45.573945 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 00:24:45.581046 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 00:24:45.584300 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 00:24:45.587272 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 00:24:45.594500 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1500 00:24:45.597735 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 00:24:45.600817 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1502 00:24:45.604579 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 00:24:45.610967 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 00:24:45.614089 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 00:24:45.617791 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 00:24:45.624378 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 00:24:45.628425 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 00:24:45.631275 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 00:24:45.638170 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 00:24:45.641879 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 00:24:45.644577 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 00:24:45.651383 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 00:24:45.654997 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 00:24:45.657899 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 00:24:45.661569 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1516 00:24:45.668091 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1517 00:24:45.671811 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 00:24:45.674507 Total UI for P1: 0, mck2ui 16
1519 00:24:45.678099 best dqsien dly found for B0: ( 0, 14, 6)
1520 00:24:45.681400 Total UI for P1: 0, mck2ui 16
1521 00:24:45.684732 best dqsien dly found for B1: ( 0, 14, 6)
1522 00:24:45.688651 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1523 00:24:45.691784 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1524 00:24:45.691924
1525 00:24:45.694937 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1526 00:24:45.698094 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1527 00:24:45.701825 [Gating] SW calibration Done
1528 00:24:45.701925 ==
1529 00:24:45.704815 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 00:24:45.708788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 00:24:45.708902 ==
1532 00:24:45.711706 RX Vref Scan: 0
1533 00:24:45.711823
1534 00:24:45.715016 RX Vref 0 -> 0, step: 1
1535 00:24:45.715115
1536 00:24:45.715204 RX Delay -130 -> 252, step: 16
1537 00:24:45.722153 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1538 00:24:45.725282 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1539 00:24:45.728380 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1540 00:24:45.731945 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1541 00:24:45.735309 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1542 00:24:45.738915 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1543 00:24:45.745784 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1544 00:24:45.749151 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1545 00:24:45.752576 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1546 00:24:45.756155 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1547 00:24:45.758871 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1548 00:24:45.765714 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1549 00:24:45.769008 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1550 00:24:45.772467 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1551 00:24:45.776309 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1552 00:24:45.778905 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1553 00:24:45.782557 ==
1554 00:24:45.782639 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 00:24:45.789249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 00:24:45.789351 ==
1557 00:24:45.789435 DQS Delay:
1558 00:24:45.792597 DQS0 = 0, DQS1 = 0
1559 00:24:45.792740 DQM Delay:
1560 00:24:45.792834 DQM0 = 80, DQM1 = 71
1561 00:24:45.795755 DQ Delay:
1562 00:24:45.799121 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1563 00:24:45.802559 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =77
1564 00:24:45.806098 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1565 00:24:45.809098 DQ12 =85, DQ13 =77, DQ14 =77, DQ15 =77
1566 00:24:45.809172
1567 00:24:45.809237
1568 00:24:45.809300 ==
1569 00:24:45.812565 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 00:24:45.816279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 00:24:45.816386 ==
1572 00:24:45.816495
1573 00:24:45.816591
1574 00:24:45.819259 TX Vref Scan disable
1575 00:24:45.819376 == TX Byte 0 ==
1576 00:24:45.825957 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1577 00:24:45.829689 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1578 00:24:45.829764 == TX Byte 1 ==
1579 00:24:45.836089 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1580 00:24:45.839650 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1581 00:24:45.839763 ==
1582 00:24:45.842552 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 00:24:45.846216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 00:24:45.846320 ==
1585 00:24:45.860591 TX Vref=22, minBit 11, minWin=26, winSum=434
1586 00:24:45.863971 TX Vref=24, minBit 11, minWin=26, winSum=437
1587 00:24:45.867256 TX Vref=26, minBit 0, minWin=27, winSum=441
1588 00:24:45.870959 TX Vref=28, minBit 0, minWin=27, winSum=445
1589 00:24:45.874081 TX Vref=30, minBit 0, minWin=27, winSum=446
1590 00:24:45.877297 TX Vref=32, minBit 0, minWin=28, winSum=451
1591 00:24:45.884488 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 32
1592 00:24:45.884591
1593 00:24:45.888548 Final TX Range 1 Vref 32
1594 00:24:45.888657
1595 00:24:45.888785 ==
1596 00:24:45.891519 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 00:24:45.894762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 00:24:45.894861 ==
1599 00:24:45.894952
1600 00:24:45.895080
1601 00:24:45.898286 TX Vref Scan disable
1602 00:24:45.901927 == TX Byte 0 ==
1603 00:24:45.904845 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1604 00:24:45.908572 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1605 00:24:45.911879 == TX Byte 1 ==
1606 00:24:45.914809 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1607 00:24:45.918591 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1608 00:24:45.918698
1609 00:24:45.921857 [DATLAT]
1610 00:24:45.921958 Freq=800, CH1 RK0
1611 00:24:45.922064
1612 00:24:45.925033 DATLAT Default: 0xa
1613 00:24:45.925113 0, 0xFFFF, sum = 0
1614 00:24:45.928450 1, 0xFFFF, sum = 0
1615 00:24:45.928553 2, 0xFFFF, sum = 0
1616 00:24:45.931689 3, 0xFFFF, sum = 0
1617 00:24:45.931789 4, 0xFFFF, sum = 0
1618 00:24:45.935969 5, 0xFFFF, sum = 0
1619 00:24:45.936044 6, 0xFFFF, sum = 0
1620 00:24:45.938409 7, 0xFFFF, sum = 0
1621 00:24:45.938483 8, 0xFFFF, sum = 0
1622 00:24:45.941990 9, 0x0, sum = 1
1623 00:24:45.942088 10, 0x0, sum = 2
1624 00:24:45.945503 11, 0x0, sum = 3
1625 00:24:45.945603 12, 0x0, sum = 4
1626 00:24:45.945716 best_step = 10
1627 00:24:45.945814
1628 00:24:45.948756 ==
1629 00:24:45.952068 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 00:24:45.955062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 00:24:45.955163 ==
1632 00:24:45.955261 RX Vref Scan: 1
1633 00:24:45.955356
1634 00:24:45.958893 Set Vref Range= 32 -> 127
1635 00:24:45.958989
1636 00:24:45.961724 RX Vref 32 -> 127, step: 1
1637 00:24:45.961822
1638 00:24:45.965191 RX Delay -111 -> 252, step: 8
1639 00:24:45.965290
1640 00:24:45.968926 Set Vref, RX VrefLevel [Byte0]: 32
1641 00:24:45.972299 [Byte1]: 32
1642 00:24:45.972404
1643 00:24:45.975629 Set Vref, RX VrefLevel [Byte0]: 33
1644 00:24:45.978595 [Byte1]: 33
1645 00:24:45.978693
1646 00:24:45.982020 Set Vref, RX VrefLevel [Byte0]: 34
1647 00:24:45.985947 [Byte1]: 34
1648 00:24:45.988728
1649 00:24:45.988826 Set Vref, RX VrefLevel [Byte0]: 35
1650 00:24:45.991960 [Byte1]: 35
1651 00:24:45.996546
1652 00:24:45.996659 Set Vref, RX VrefLevel [Byte0]: 36
1653 00:24:46.000094 [Byte1]: 36
1654 00:24:46.004245
1655 00:24:46.004354 Set Vref, RX VrefLevel [Byte0]: 37
1656 00:24:46.007667 [Byte1]: 37
1657 00:24:46.011981
1658 00:24:46.012078 Set Vref, RX VrefLevel [Byte0]: 38
1659 00:24:46.015433 [Byte1]: 38
1660 00:24:46.019343
1661 00:24:46.019442 Set Vref, RX VrefLevel [Byte0]: 39
1662 00:24:46.023144 [Byte1]: 39
1663 00:24:46.027071
1664 00:24:46.027171 Set Vref, RX VrefLevel [Byte0]: 40
1665 00:24:46.030676 [Byte1]: 40
1666 00:24:46.034770
1667 00:24:46.034881 Set Vref, RX VrefLevel [Byte0]: 41
1668 00:24:46.038459 [Byte1]: 41
1669 00:24:46.042458
1670 00:24:46.042538 Set Vref, RX VrefLevel [Byte0]: 42
1671 00:24:46.045741 [Byte1]: 42
1672 00:24:46.050247
1673 00:24:46.050343 Set Vref, RX VrefLevel [Byte0]: 43
1674 00:24:46.053608 [Byte1]: 43
1675 00:24:46.057725
1676 00:24:46.057826 Set Vref, RX VrefLevel [Byte0]: 44
1677 00:24:46.060785 [Byte1]: 44
1678 00:24:46.065248
1679 00:24:46.065418 Set Vref, RX VrefLevel [Byte0]: 45
1680 00:24:46.068476 [Byte1]: 45
1681 00:24:46.072834
1682 00:24:46.072931 Set Vref, RX VrefLevel [Byte0]: 46
1683 00:24:46.076335 [Byte1]: 46
1684 00:24:46.080829
1685 00:24:46.081008 Set Vref, RX VrefLevel [Byte0]: 47
1686 00:24:46.084128 [Byte1]: 47
1687 00:24:46.088626
1688 00:24:46.088761 Set Vref, RX VrefLevel [Byte0]: 48
1689 00:24:46.091639 [Byte1]: 48
1690 00:24:46.095782
1691 00:24:46.095880 Set Vref, RX VrefLevel [Byte0]: 49
1692 00:24:46.099160 [Byte1]: 49
1693 00:24:46.103363
1694 00:24:46.103438 Set Vref, RX VrefLevel [Byte0]: 50
1695 00:24:46.107084 [Byte1]: 50
1696 00:24:46.111330
1697 00:24:46.111429 Set Vref, RX VrefLevel [Byte0]: 51
1698 00:24:46.114623 [Byte1]: 51
1699 00:24:46.119039
1700 00:24:46.119152 Set Vref, RX VrefLevel [Byte0]: 52
1701 00:24:46.122671 [Byte1]: 52
1702 00:24:46.126501
1703 00:24:46.126602 Set Vref, RX VrefLevel [Byte0]: 53
1704 00:24:46.129704 [Byte1]: 53
1705 00:24:46.134278
1706 00:24:46.134390 Set Vref, RX VrefLevel [Byte0]: 54
1707 00:24:46.137331 [Byte1]: 54
1708 00:24:46.141773
1709 00:24:46.141881 Set Vref, RX VrefLevel [Byte0]: 55
1710 00:24:46.145356 [Byte1]: 55
1711 00:24:46.149401
1712 00:24:46.149508 Set Vref, RX VrefLevel [Byte0]: 56
1713 00:24:46.152970 [Byte1]: 56
1714 00:24:46.156979
1715 00:24:46.157083 Set Vref, RX VrefLevel [Byte0]: 57
1716 00:24:46.160464 [Byte1]: 57
1717 00:24:46.165234
1718 00:24:46.165329 Set Vref, RX VrefLevel [Byte0]: 58
1719 00:24:46.168117 [Byte1]: 58
1720 00:24:46.172551
1721 00:24:46.172646 Set Vref, RX VrefLevel [Byte0]: 59
1722 00:24:46.175988 [Byte1]: 59
1723 00:24:46.179877
1724 00:24:46.179979 Set Vref, RX VrefLevel [Byte0]: 60
1725 00:24:46.183451 [Byte1]: 60
1726 00:24:46.187398
1727 00:24:46.187493 Set Vref, RX VrefLevel [Byte0]: 61
1728 00:24:46.191460 [Byte1]: 61
1729 00:24:46.195319
1730 00:24:46.195424 Set Vref, RX VrefLevel [Byte0]: 62
1731 00:24:46.198885 [Byte1]: 62
1732 00:24:46.203365
1733 00:24:46.203438 Set Vref, RX VrefLevel [Byte0]: 63
1734 00:24:46.206727 [Byte1]: 63
1735 00:24:46.210782
1736 00:24:46.210889 Set Vref, RX VrefLevel [Byte0]: 64
1737 00:24:46.214070 [Byte1]: 64
1738 00:24:46.218667
1739 00:24:46.218771 Set Vref, RX VrefLevel [Byte0]: 65
1740 00:24:46.221716 [Byte1]: 65
1741 00:24:46.225998
1742 00:24:46.226136 Set Vref, RX VrefLevel [Byte0]: 66
1743 00:24:46.229297 [Byte1]: 66
1744 00:24:46.233802
1745 00:24:46.233901 Set Vref, RX VrefLevel [Byte0]: 67
1746 00:24:46.236791 [Byte1]: 67
1747 00:24:46.241430
1748 00:24:46.241529 Set Vref, RX VrefLevel [Byte0]: 68
1749 00:24:46.244339 [Byte1]: 68
1750 00:24:46.248818
1751 00:24:46.248894 Set Vref, RX VrefLevel [Byte0]: 69
1752 00:24:46.252189 [Byte1]: 69
1753 00:24:46.256774
1754 00:24:46.256873 Set Vref, RX VrefLevel [Byte0]: 70
1755 00:24:46.259770 [Byte1]: 70
1756 00:24:46.264054
1757 00:24:46.264156 Set Vref, RX VrefLevel [Byte0]: 71
1758 00:24:46.267506 [Byte1]: 71
1759 00:24:46.271705
1760 00:24:46.271806 Set Vref, RX VrefLevel [Byte0]: 72
1761 00:24:46.275140 [Byte1]: 72
1762 00:24:46.279709
1763 00:24:46.279814 Set Vref, RX VrefLevel [Byte0]: 73
1764 00:24:46.283014 [Byte1]: 73
1765 00:24:46.287259
1766 00:24:46.287357 Set Vref, RX VrefLevel [Byte0]: 74
1767 00:24:46.290541 [Byte1]: 74
1768 00:24:46.294555
1769 00:24:46.294646 Final RX Vref Byte 0 = 57 to rank0
1770 00:24:46.297961 Final RX Vref Byte 1 = 57 to rank0
1771 00:24:46.301615 Final RX Vref Byte 0 = 57 to rank1
1772 00:24:46.305103 Final RX Vref Byte 1 = 57 to rank1==
1773 00:24:46.308328 Dram Type= 6, Freq= 0, CH_1, rank 0
1774 00:24:46.311659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1775 00:24:46.315151 ==
1776 00:24:46.315250 DQS Delay:
1777 00:24:46.315352 DQS0 = 0, DQS1 = 0
1778 00:24:46.317986 DQM Delay:
1779 00:24:46.318092 DQM0 = 83, DQM1 = 73
1780 00:24:46.321618 DQ Delay:
1781 00:24:46.321725 DQ0 =84, DQ1 =76, DQ2 =76, DQ3 =84
1782 00:24:46.325032 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =80
1783 00:24:46.328373 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1784 00:24:46.332015 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =76
1785 00:24:46.332116
1786 00:24:46.332207
1787 00:24:46.342080 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d01, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
1788 00:24:46.344988 CH1 RK0: MR19=606, MR18=2D01
1789 00:24:46.351726 CH1_RK0: MR19=0x606, MR18=0x2D01, DQSOSC=398, MR23=63, INC=93, DEC=62
1790 00:24:46.351835
1791 00:24:46.355135 ----->DramcWriteLeveling(PI) begin...
1792 00:24:46.355244 ==
1793 00:24:46.358409 Dram Type= 6, Freq= 0, CH_1, rank 1
1794 00:24:46.361667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1795 00:24:46.361740 ==
1796 00:24:46.365173 Write leveling (Byte 0): 30 => 30
1797 00:24:46.368747 Write leveling (Byte 1): 30 => 30
1798 00:24:46.372093 DramcWriteLeveling(PI) end<-----
1799 00:24:46.372193
1800 00:24:46.372283 ==
1801 00:24:46.375140 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 00:24:46.378829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 00:24:46.378900 ==
1804 00:24:46.382208 [Gating] SW mode calibration
1805 00:24:46.388778 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1806 00:24:46.392224 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1807 00:24:46.398991 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1808 00:24:46.402110 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1809 00:24:46.405360 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1810 00:24:46.412560 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 00:24:46.415700 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 00:24:46.419154 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 00:24:46.425835 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 00:24:46.428967 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 00:24:46.432336 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 00:24:46.439461 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 00:24:46.442562 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 00:24:46.445855 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1819 00:24:46.449318 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 00:24:46.456025 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 00:24:46.459119 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 00:24:46.462577 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 00:24:46.469366 0 8 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 1)
1824 00:24:46.472782 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1825 00:24:46.476085 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1826 00:24:46.482534 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 00:24:46.486086 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 00:24:46.489758 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 00:24:46.496439 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 00:24:46.499512 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 00:24:46.502837 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 00:24:46.506543 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
1833 00:24:46.513343 0 9 8 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 1)
1834 00:24:46.516552 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 00:24:46.519670 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 00:24:46.526571 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 00:24:46.530499 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 00:24:46.533668 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1839 00:24:46.540316 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 00:24:46.543342 0 10 4 | B1->B0 | 3030 2c2c | 1 1 | (1 0) (0 0)
1841 00:24:46.546446 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1842 00:24:46.553584 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 00:24:46.556596 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 00:24:46.560638 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 00:24:46.563780 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 00:24:46.569886 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 00:24:46.573370 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1848 00:24:46.576635 0 11 4 | B1->B0 | 2d2d 3737 | 0 1 | (1 1) (0 0)
1849 00:24:46.583762 0 11 8 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
1850 00:24:46.587066 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 00:24:46.590490 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 00:24:46.597108 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 00:24:46.600272 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 00:24:46.604002 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 00:24:46.610493 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 00:24:46.613991 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1857 00:24:46.617367 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 00:24:46.620307 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 00:24:46.627130 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 00:24:46.630504 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 00:24:46.634001 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 00:24:46.640403 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 00:24:46.643874 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 00:24:46.647498 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 00:24:46.653951 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 00:24:46.657260 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 00:24:46.661021 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 00:24:46.667449 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 00:24:46.670706 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 00:24:46.674371 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 00:24:46.681309 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 00:24:46.684210 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1873 00:24:46.687540 Total UI for P1: 0, mck2ui 16
1874 00:24:46.691212 best dqsien dly found for B0: ( 0, 14, 2)
1875 00:24:46.694474 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1876 00:24:46.697657 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1877 00:24:46.700998 Total UI for P1: 0, mck2ui 16
1878 00:24:46.704547 best dqsien dly found for B1: ( 0, 14, 6)
1879 00:24:46.707878 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1880 00:24:46.711063 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1881 00:24:46.711138
1882 00:24:46.717734 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1883 00:24:46.721179 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1884 00:24:46.721254 [Gating] SW calibration Done
1885 00:24:46.721316 ==
1886 00:24:46.724906 Dram Type= 6, Freq= 0, CH_1, rank 1
1887 00:24:46.731484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1888 00:24:46.731591 ==
1889 00:24:46.731679 RX Vref Scan: 0
1890 00:24:46.731758
1891 00:24:46.734644 RX Vref 0 -> 0, step: 1
1892 00:24:46.734744
1893 00:24:46.738240 RX Delay -130 -> 252, step: 16
1894 00:24:46.741365 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1895 00:24:46.744636 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1896 00:24:46.748144 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1897 00:24:46.754949 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1898 00:24:46.758153 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1899 00:24:46.761547 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1900 00:24:46.764969 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1901 00:24:46.768361 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1902 00:24:46.772122 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1903 00:24:46.778761 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1904 00:24:46.782410 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1905 00:24:46.785372 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1906 00:24:46.788784 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1907 00:24:46.792356 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1908 00:24:46.798939 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1909 00:24:46.802145 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1910 00:24:46.802237 ==
1911 00:24:46.805224 Dram Type= 6, Freq= 0, CH_1, rank 1
1912 00:24:46.808631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1913 00:24:46.808754 ==
1914 00:24:46.808822 DQS Delay:
1915 00:24:46.812246 DQS0 = 0, DQS1 = 0
1916 00:24:46.812347 DQM Delay:
1917 00:24:46.815748 DQM0 = 81, DQM1 = 78
1918 00:24:46.815848 DQ Delay:
1919 00:24:46.819165 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1920 00:24:46.822154 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1921 00:24:46.825336 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1922 00:24:46.828929 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1923 00:24:46.829021
1924 00:24:46.829112
1925 00:24:46.829198 ==
1926 00:24:46.832393 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 00:24:46.835693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 00:24:46.835792 ==
1929 00:24:46.838801
1930 00:24:46.838906
1931 00:24:46.838993 TX Vref Scan disable
1932 00:24:46.842433 == TX Byte 0 ==
1933 00:24:46.845672 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1934 00:24:46.849572 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1935 00:24:46.852393 == TX Byte 1 ==
1936 00:24:46.856141 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1937 00:24:46.859238 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1938 00:24:46.859339 ==
1939 00:24:46.862310 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 00:24:46.869289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 00:24:46.869405 ==
1942 00:24:46.881116 TX Vref=22, minBit 9, minWin=27, winSum=444
1943 00:24:46.884152 TX Vref=24, minBit 0, minWin=27, winSum=446
1944 00:24:46.887357 TX Vref=26, minBit 13, minWin=27, winSum=450
1945 00:24:46.890794 TX Vref=28, minBit 0, minWin=28, winSum=450
1946 00:24:46.894239 TX Vref=30, minBit 3, minWin=28, winSum=454
1947 00:24:46.898231 TX Vref=32, minBit 2, minWin=28, winSum=454
1948 00:24:46.904294 [TxChooseVref] Worse bit 3, Min win 28, Win sum 454, Final Vref 30
1949 00:24:46.904375
1950 00:24:46.907809 Final TX Range 1 Vref 30
1951 00:24:46.907914
1952 00:24:46.908004 ==
1953 00:24:46.911104 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 00:24:46.914567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 00:24:46.914666 ==
1956 00:24:46.914760
1957 00:24:46.914846
1958 00:24:46.918005 TX Vref Scan disable
1959 00:24:46.920982 == TX Byte 0 ==
1960 00:24:46.924649 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1961 00:24:46.927672 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1962 00:24:46.931421 == TX Byte 1 ==
1963 00:24:46.934505 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1964 00:24:46.937788 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1965 00:24:46.937892
1966 00:24:46.941512 [DATLAT]
1967 00:24:46.941615 Freq=800, CH1 RK1
1968 00:24:46.941708
1969 00:24:46.944766 DATLAT Default: 0xa
1970 00:24:46.944851 0, 0xFFFF, sum = 0
1971 00:24:46.948232 1, 0xFFFF, sum = 0
1972 00:24:46.948345 2, 0xFFFF, sum = 0
1973 00:24:46.951111 3, 0xFFFF, sum = 0
1974 00:24:46.951217 4, 0xFFFF, sum = 0
1975 00:24:46.954846 5, 0xFFFF, sum = 0
1976 00:24:46.954952 6, 0xFFFF, sum = 0
1977 00:24:46.958020 7, 0xFFFF, sum = 0
1978 00:24:46.958125 8, 0xFFFF, sum = 0
1979 00:24:46.961233 9, 0x0, sum = 1
1980 00:24:46.961336 10, 0x0, sum = 2
1981 00:24:46.964816 11, 0x0, sum = 3
1982 00:24:46.964917 12, 0x0, sum = 4
1983 00:24:46.968251 best_step = 10
1984 00:24:46.968348
1985 00:24:46.968440 ==
1986 00:24:46.971213 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 00:24:46.974841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 00:24:46.974943 ==
1989 00:24:46.975032 RX Vref Scan: 0
1990 00:24:46.975124
1991 00:24:46.978121 RX Vref 0 -> 0, step: 1
1992 00:24:46.978220
1993 00:24:46.981531 RX Delay -95 -> 252, step: 8
1994 00:24:46.984760 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1995 00:24:46.991348 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
1996 00:24:46.994884 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
1997 00:24:46.998311 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
1998 00:24:47.001355 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1999 00:24:47.004959 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2000 00:24:47.008598 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2001 00:24:47.014997 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2002 00:24:47.018892 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2003 00:24:47.021860 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2004 00:24:47.025219 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2005 00:24:47.028728 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2006 00:24:47.035412 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2007 00:24:47.038684 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2008 00:24:47.042198 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2009 00:24:47.045257 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2010 00:24:47.045355 ==
2011 00:24:47.048835 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 00:24:47.055633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 00:24:47.055730 ==
2014 00:24:47.055825 DQS Delay:
2015 00:24:47.055901 DQS0 = 0, DQS1 = 0
2016 00:24:47.059338 DQM Delay:
2017 00:24:47.059435 DQM0 = 80, DQM1 = 75
2018 00:24:47.062013 DQ Delay:
2019 00:24:47.065310 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2020 00:24:47.065407 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2021 00:24:47.068653 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2022 00:24:47.072059 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =84
2023 00:24:47.075989
2024 00:24:47.076112
2025 00:24:47.082028 [DQSOSCAuto] RK1, (LSB)MR18= 0x212b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2026 00:24:47.085789 CH1 RK1: MR19=606, MR18=212B
2027 00:24:47.092229 CH1_RK1: MR19=0x606, MR18=0x212B, DQSOSC=398, MR23=63, INC=93, DEC=62
2028 00:24:47.092326 [RxdqsGatingPostProcess] freq 800
2029 00:24:47.099168 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2030 00:24:47.102737 Pre-setting of DQS Precalculation
2031 00:24:47.105758 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2032 00:24:47.115892 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2033 00:24:47.122929 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2034 00:24:47.123030
2035 00:24:47.123137
2036 00:24:47.125785 [Calibration Summary] 1600 Mbps
2037 00:24:47.125886 CH 0, Rank 0
2038 00:24:47.129445 SW Impedance : PASS
2039 00:24:47.129535 DUTY Scan : NO K
2040 00:24:47.132670 ZQ Calibration : PASS
2041 00:24:47.136481 Jitter Meter : NO K
2042 00:24:47.136576 CBT Training : PASS
2043 00:24:47.139361 Write leveling : PASS
2044 00:24:47.142589 RX DQS gating : PASS
2045 00:24:47.142700 RX DQ/DQS(RDDQC) : PASS
2046 00:24:47.146214 TX DQ/DQS : PASS
2047 00:24:47.149458 RX DATLAT : PASS
2048 00:24:47.149555 RX DQ/DQS(Engine): PASS
2049 00:24:47.152757 TX OE : NO K
2050 00:24:47.152868 All Pass.
2051 00:24:47.152947
2052 00:24:47.153023 CH 0, Rank 1
2053 00:24:47.156121 SW Impedance : PASS
2054 00:24:47.159750 DUTY Scan : NO K
2055 00:24:47.159890 ZQ Calibration : PASS
2056 00:24:47.163084 Jitter Meter : NO K
2057 00:24:47.166169 CBT Training : PASS
2058 00:24:47.166304 Write leveling : PASS
2059 00:24:47.169428 RX DQS gating : PASS
2060 00:24:47.172998 RX DQ/DQS(RDDQC) : PASS
2061 00:24:47.173099 TX DQ/DQS : PASS
2062 00:24:47.176209 RX DATLAT : PASS
2063 00:24:47.179888 RX DQ/DQS(Engine): PASS
2064 00:24:47.179990 TX OE : NO K
2065 00:24:47.180085 All Pass.
2066 00:24:47.180172
2067 00:24:47.183005 CH 1, Rank 0
2068 00:24:47.183111 SW Impedance : PASS
2069 00:24:47.186500 DUTY Scan : NO K
2070 00:24:47.189733 ZQ Calibration : PASS
2071 00:24:47.189837 Jitter Meter : NO K
2072 00:24:47.193298 CBT Training : PASS
2073 00:24:47.196365 Write leveling : PASS
2074 00:24:47.196464 RX DQS gating : PASS
2075 00:24:47.199780 RX DQ/DQS(RDDQC) : PASS
2076 00:24:47.203106 TX DQ/DQS : PASS
2077 00:24:47.203209 RX DATLAT : PASS
2078 00:24:47.206782 RX DQ/DQS(Engine): PASS
2079 00:24:47.209950 TX OE : NO K
2080 00:24:47.210050 All Pass.
2081 00:24:47.210138
2082 00:24:47.210226 CH 1, Rank 1
2083 00:24:47.213333 SW Impedance : PASS
2084 00:24:47.216954 DUTY Scan : NO K
2085 00:24:47.217040 ZQ Calibration : PASS
2086 00:24:47.220240 Jitter Meter : NO K
2087 00:24:47.220338 CBT Training : PASS
2088 00:24:47.223360 Write leveling : PASS
2089 00:24:47.226775 RX DQS gating : PASS
2090 00:24:47.226877 RX DQ/DQS(RDDQC) : PASS
2091 00:24:47.230018 TX DQ/DQS : PASS
2092 00:24:47.233765 RX DATLAT : PASS
2093 00:24:47.233864 RX DQ/DQS(Engine): PASS
2094 00:24:47.236720 TX OE : NO K
2095 00:24:47.236817 All Pass.
2096 00:24:47.236886
2097 00:24:47.240129 DramC Write-DBI off
2098 00:24:47.243725 PER_BANK_REFRESH: Hybrid Mode
2099 00:24:47.243798 TX_TRACKING: ON
2100 00:24:47.246740 [GetDramInforAfterCalByMRR] Vendor 6.
2101 00:24:47.250609 [GetDramInforAfterCalByMRR] Revision 606.
2102 00:24:47.253777 [GetDramInforAfterCalByMRR] Revision 2 0.
2103 00:24:47.256942 MR0 0x3b3b
2104 00:24:47.257055 MR8 0x5151
2105 00:24:47.260339 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2106 00:24:47.260442
2107 00:24:47.260536 MR0 0x3b3b
2108 00:24:47.264112 MR8 0x5151
2109 00:24:47.267453 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2110 00:24:47.267553
2111 00:24:47.274414 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2112 00:24:47.277023 [FAST_K] Save calibration result to emmc
2113 00:24:47.284004 [FAST_K] Save calibration result to emmc
2114 00:24:47.284111 dram_init: config_dvfs: 1
2115 00:24:47.287212 dramc_set_vcore_voltage set vcore to 662500
2116 00:24:47.290619 Read voltage for 1200, 2
2117 00:24:47.290750 Vio18 = 0
2118 00:24:47.294122 Vcore = 662500
2119 00:24:47.294236 Vdram = 0
2120 00:24:47.294334 Vddq = 0
2121 00:24:47.297682 Vmddr = 0
2122 00:24:47.300823 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2123 00:24:47.307272 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2124 00:24:47.307381 MEM_TYPE=3, freq_sel=15
2125 00:24:47.310692 sv_algorithm_assistance_LP4_1600
2126 00:24:47.317536 ============ PULL DRAM RESETB DOWN ============
2127 00:24:47.321090 ========== PULL DRAM RESETB DOWN end =========
2128 00:24:47.324373 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2129 00:24:47.327687 ===================================
2130 00:24:47.331413 LPDDR4 DRAM CONFIGURATION
2131 00:24:47.334155 ===================================
2132 00:24:47.334259 EX_ROW_EN[0] = 0x0
2133 00:24:47.338081 EX_ROW_EN[1] = 0x0
2134 00:24:47.338185 LP4Y_EN = 0x0
2135 00:24:47.341519 WORK_FSP = 0x0
2136 00:24:47.341605 WL = 0x4
2137 00:24:47.344298 RL = 0x4
2138 00:24:47.344392 BL = 0x2
2139 00:24:47.347836 RPST = 0x0
2140 00:24:47.351107 RD_PRE = 0x0
2141 00:24:47.351210 WR_PRE = 0x1
2142 00:24:47.355079 WR_PST = 0x0
2143 00:24:47.355182 DBI_WR = 0x0
2144 00:24:47.357979 DBI_RD = 0x0
2145 00:24:47.358079 OTF = 0x1
2146 00:24:47.361071 ===================================
2147 00:24:47.364527 ===================================
2148 00:24:47.364626 ANA top config
2149 00:24:47.367918 ===================================
2150 00:24:47.371109 DLL_ASYNC_EN = 0
2151 00:24:47.374720 ALL_SLAVE_EN = 0
2152 00:24:47.378065 NEW_RANK_MODE = 1
2153 00:24:47.378167 DLL_IDLE_MODE = 1
2154 00:24:47.381256 LP45_APHY_COMB_EN = 1
2155 00:24:47.385145 TX_ODT_DIS = 1
2156 00:24:47.388086 NEW_8X_MODE = 1
2157 00:24:47.391468 ===================================
2158 00:24:47.394785 ===================================
2159 00:24:47.398123 data_rate = 2400
2160 00:24:47.398223 CKR = 1
2161 00:24:47.401565 DQ_P2S_RATIO = 8
2162 00:24:47.405132 ===================================
2163 00:24:47.408275 CA_P2S_RATIO = 8
2164 00:24:47.411432 DQ_CA_OPEN = 0
2165 00:24:47.415221 DQ_SEMI_OPEN = 0
2166 00:24:47.418127 CA_SEMI_OPEN = 0
2167 00:24:47.418228 CA_FULL_RATE = 0
2168 00:24:47.421591 DQ_CKDIV4_EN = 0
2169 00:24:47.425362 CA_CKDIV4_EN = 0
2170 00:24:47.428453 CA_PREDIV_EN = 0
2171 00:24:47.431926 PH8_DLY = 17
2172 00:24:47.432027 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2173 00:24:47.435751 DQ_AAMCK_DIV = 4
2174 00:24:47.438784 CA_AAMCK_DIV = 4
2175 00:24:47.442396 CA_ADMCK_DIV = 4
2176 00:24:47.445522 DQ_TRACK_CA_EN = 0
2177 00:24:47.448881 CA_PICK = 1200
2178 00:24:47.448969 CA_MCKIO = 1200
2179 00:24:47.452114 MCKIO_SEMI = 0
2180 00:24:47.455543 PLL_FREQ = 2366
2181 00:24:47.459302 DQ_UI_PI_RATIO = 32
2182 00:24:47.462022 CA_UI_PI_RATIO = 0
2183 00:24:47.465354 ===================================
2184 00:24:47.468919 ===================================
2185 00:24:47.472124 memory_type:LPDDR4
2186 00:24:47.472199 GP_NUM : 10
2187 00:24:47.475883 SRAM_EN : 1
2188 00:24:47.475974 MD32_EN : 0
2189 00:24:47.478950 ===================================
2190 00:24:47.482419 [ANA_INIT] >>>>>>>>>>>>>>
2191 00:24:47.485833 <<<<<< [CONFIGURE PHASE]: ANA_TX
2192 00:24:47.489269 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2193 00:24:47.492957 ===================================
2194 00:24:47.496200 data_rate = 2400,PCW = 0X5b00
2195 00:24:47.499474 ===================================
2196 00:24:47.502414 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2197 00:24:47.505954 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2198 00:24:47.512966 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2199 00:24:47.515826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2200 00:24:47.519392 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2201 00:24:47.522631 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2202 00:24:47.525885 [ANA_INIT] flow start
2203 00:24:47.529161 [ANA_INIT] PLL >>>>>>>>
2204 00:24:47.529234 [ANA_INIT] PLL <<<<<<<<
2205 00:24:47.533139 [ANA_INIT] MIDPI >>>>>>>>
2206 00:24:47.536378 [ANA_INIT] MIDPI <<<<<<<<
2207 00:24:47.536450 [ANA_INIT] DLL >>>>>>>>
2208 00:24:47.539739 [ANA_INIT] DLL <<<<<<<<
2209 00:24:47.543081 [ANA_INIT] flow end
2210 00:24:47.546416 ============ LP4 DIFF to SE enter ============
2211 00:24:47.549810 ============ LP4 DIFF to SE exit ============
2212 00:24:47.552853 [ANA_INIT] <<<<<<<<<<<<<
2213 00:24:47.556164 [Flow] Enable top DCM control >>>>>
2214 00:24:47.559637 [Flow] Enable top DCM control <<<<<
2215 00:24:47.562901 Enable DLL master slave shuffle
2216 00:24:47.565990 ==============================================================
2217 00:24:47.569318 Gating Mode config
2218 00:24:47.576299 ==============================================================
2219 00:24:47.576379 Config description:
2220 00:24:47.586592 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2221 00:24:47.593429 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2222 00:24:47.596652 SELPH_MODE 0: By rank 1: By Phase
2223 00:24:47.603381 ==============================================================
2224 00:24:47.606566 GAT_TRACK_EN = 1
2225 00:24:47.609831 RX_GATING_MODE = 2
2226 00:24:47.613639 RX_GATING_TRACK_MODE = 2
2227 00:24:47.616636 SELPH_MODE = 1
2228 00:24:47.616729 PICG_EARLY_EN = 1
2229 00:24:47.620377 VALID_LAT_VALUE = 1
2230 00:24:47.626618 ==============================================================
2231 00:24:47.630146 Enter into Gating configuration >>>>
2232 00:24:47.633835 Exit from Gating configuration <<<<
2233 00:24:47.636858 Enter into DVFS_PRE_config >>>>>
2234 00:24:47.646886 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2235 00:24:47.650054 Exit from DVFS_PRE_config <<<<<
2236 00:24:47.653717 Enter into PICG configuration >>>>
2237 00:24:47.656837 Exit from PICG configuration <<<<
2238 00:24:47.660083 [RX_INPUT] configuration >>>>>
2239 00:24:47.663455 [RX_INPUT] configuration <<<<<
2240 00:24:47.666874 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2241 00:24:47.673775 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2242 00:24:47.680472 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2243 00:24:47.687331 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2244 00:24:47.690406 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2245 00:24:47.696907 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2246 00:24:47.700243 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2247 00:24:47.707362 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2248 00:24:47.710608 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2249 00:24:47.714208 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2250 00:24:47.717338 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2251 00:24:47.724295 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2252 00:24:47.727352 ===================================
2253 00:24:47.727439 LPDDR4 DRAM CONFIGURATION
2254 00:24:47.731072 ===================================
2255 00:24:47.734556 EX_ROW_EN[0] = 0x0
2256 00:24:47.737697 EX_ROW_EN[1] = 0x0
2257 00:24:47.737797 LP4Y_EN = 0x0
2258 00:24:47.741038 WORK_FSP = 0x0
2259 00:24:47.741106 WL = 0x4
2260 00:24:47.744183 RL = 0x4
2261 00:24:47.744247 BL = 0x2
2262 00:24:47.747794 RPST = 0x0
2263 00:24:47.747865 RD_PRE = 0x0
2264 00:24:47.750729 WR_PRE = 0x1
2265 00:24:47.750804 WR_PST = 0x0
2266 00:24:47.754097 DBI_WR = 0x0
2267 00:24:47.754164 DBI_RD = 0x0
2268 00:24:47.757815 OTF = 0x1
2269 00:24:47.760755 ===================================
2270 00:24:47.764166 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2271 00:24:47.767647 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2272 00:24:47.771015 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2273 00:24:47.774324 ===================================
2274 00:24:47.777448 LPDDR4 DRAM CONFIGURATION
2275 00:24:47.780811 ===================================
2276 00:24:47.784422 EX_ROW_EN[0] = 0x10
2277 00:24:47.784499 EX_ROW_EN[1] = 0x0
2278 00:24:47.788156 LP4Y_EN = 0x0
2279 00:24:47.788224 WORK_FSP = 0x0
2280 00:24:47.791016 WL = 0x4
2281 00:24:47.791090 RL = 0x4
2282 00:24:47.794633 BL = 0x2
2283 00:24:47.794707 RPST = 0x0
2284 00:24:47.798205 RD_PRE = 0x0
2285 00:24:47.798279 WR_PRE = 0x1
2286 00:24:47.801187 WR_PST = 0x0
2287 00:24:47.801258 DBI_WR = 0x0
2288 00:24:47.804750 DBI_RD = 0x0
2289 00:24:47.804829 OTF = 0x1
2290 00:24:47.807974 ===================================
2291 00:24:47.814490 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2292 00:24:47.814567 ==
2293 00:24:47.818000 Dram Type= 6, Freq= 0, CH_0, rank 0
2294 00:24:47.824546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2295 00:24:47.824675 ==
2296 00:24:47.824756 [Duty_Offset_Calibration]
2297 00:24:47.828340 B0:2 B1:-1 CA:1
2298 00:24:47.828442
2299 00:24:47.831162 [DutyScan_Calibration_Flow] k_type=0
2300 00:24:47.839908
2301 00:24:47.839986 ==CLK 0==
2302 00:24:47.842846 Final CLK duty delay cell = -4
2303 00:24:47.846052 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2304 00:24:47.849626 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2305 00:24:47.852762 [-4] AVG Duty = 4953%(X100)
2306 00:24:47.852864
2307 00:24:47.855951 CH0 CLK Duty spec in!! Max-Min= 156%
2308 00:24:47.859436 [DutyScan_Calibration_Flow] ====Done====
2309 00:24:47.859536
2310 00:24:47.862527 [DutyScan_Calibration_Flow] k_type=1
2311 00:24:47.877382
2312 00:24:47.877490 ==DQS 0 ==
2313 00:24:47.880978 Final DQS duty delay cell = -4
2314 00:24:47.884025 [-4] MAX Duty = 5000%(X100), DQS PI = 42
2315 00:24:47.887589 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2316 00:24:47.890822 [-4] AVG Duty = 4938%(X100)
2317 00:24:47.890898
2318 00:24:47.890960 ==DQS 1 ==
2319 00:24:47.894086 Final DQS duty delay cell = -4
2320 00:24:47.897680 [-4] MAX Duty = 5093%(X100), DQS PI = 6
2321 00:24:47.900840 [-4] MIN Duty = 5000%(X100), DQS PI = 58
2322 00:24:47.904974 [-4] AVG Duty = 5046%(X100)
2323 00:24:47.905063
2324 00:24:47.907746 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2325 00:24:47.907842
2326 00:24:47.910957 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2327 00:24:47.914180 [DutyScan_Calibration_Flow] ====Done====
2328 00:24:47.914255
2329 00:24:47.917733 [DutyScan_Calibration_Flow] k_type=3
2330 00:24:47.934448
2331 00:24:47.934525 ==DQM 0 ==
2332 00:24:47.937724 Final DQM duty delay cell = 0
2333 00:24:47.941574 [0] MAX Duty = 5031%(X100), DQS PI = 54
2334 00:24:47.944336 [0] MIN Duty = 4907%(X100), DQS PI = 4
2335 00:24:47.944437 [0] AVG Duty = 4969%(X100)
2336 00:24:47.948062
2337 00:24:47.948136 ==DQM 1 ==
2338 00:24:47.951794 Final DQM duty delay cell = 0
2339 00:24:47.954500 [0] MAX Duty = 5156%(X100), DQS PI = 62
2340 00:24:47.958114 [0] MIN Duty = 4969%(X100), DQS PI = 10
2341 00:24:47.958209 [0] AVG Duty = 5062%(X100)
2342 00:24:47.958292
2343 00:24:47.964918 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2344 00:24:47.964988
2345 00:24:47.967856 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2346 00:24:47.971233 [DutyScan_Calibration_Flow] ====Done====
2347 00:24:47.971316
2348 00:24:47.974911 [DutyScan_Calibration_Flow] k_type=2
2349 00:24:47.990477
2350 00:24:47.990565 ==DQ 0 ==
2351 00:24:47.993525 Final DQ duty delay cell = -4
2352 00:24:47.997165 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2353 00:24:48.000094 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2354 00:24:48.003479 [-4] AVG Duty = 4984%(X100)
2355 00:24:48.003577
2356 00:24:48.003683 ==DQ 1 ==
2357 00:24:48.007533 Final DQ duty delay cell = 0
2358 00:24:48.010419 [0] MAX Duty = 5031%(X100), DQS PI = 18
2359 00:24:48.013738 [0] MIN Duty = 4907%(X100), DQS PI = 46
2360 00:24:48.013817 [0] AVG Duty = 4969%(X100)
2361 00:24:48.017139
2362 00:24:48.020554 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2363 00:24:48.020654
2364 00:24:48.023578 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2365 00:24:48.027096 [DutyScan_Calibration_Flow] ====Done====
2366 00:24:48.027198 ==
2367 00:24:48.030419 Dram Type= 6, Freq= 0, CH_1, rank 0
2368 00:24:48.034348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2369 00:24:48.034423 ==
2370 00:24:48.037691 [Duty_Offset_Calibration]
2371 00:24:48.037767 B0:1 B1:1 CA:2
2372 00:24:48.037827
2373 00:24:48.040799 [DutyScan_Calibration_Flow] k_type=0
2374 00:24:48.050679
2375 00:24:48.050754 ==CLK 0==
2376 00:24:48.053954 Final CLK duty delay cell = 0
2377 00:24:48.057566 [0] MAX Duty = 5156%(X100), DQS PI = 24
2378 00:24:48.060457 [0] MIN Duty = 4969%(X100), DQS PI = 44
2379 00:24:48.060530 [0] AVG Duty = 5062%(X100)
2380 00:24:48.060594
2381 00:24:48.064229 CH1 CLK Duty spec in!! Max-Min= 187%
2382 00:24:48.070608 [DutyScan_Calibration_Flow] ====Done====
2383 00:24:48.070685
2384 00:24:48.073917 [DutyScan_Calibration_Flow] k_type=1
2385 00:24:48.089964
2386 00:24:48.090041 ==DQS 0 ==
2387 00:24:48.093042 Final DQS duty delay cell = 0
2388 00:24:48.096964 [0] MAX Duty = 5031%(X100), DQS PI = 18
2389 00:24:48.099856 [0] MIN Duty = 4844%(X100), DQS PI = 50
2390 00:24:48.099928 [0] AVG Duty = 4937%(X100)
2391 00:24:48.103242
2392 00:24:48.103340 ==DQS 1 ==
2393 00:24:48.106598 Final DQS duty delay cell = 0
2394 00:24:48.109999 [0] MAX Duty = 5062%(X100), DQS PI = 36
2395 00:24:48.113147 [0] MIN Duty = 4938%(X100), DQS PI = 0
2396 00:24:48.113225 [0] AVG Duty = 5000%(X100)
2397 00:24:48.113291
2398 00:24:48.116585 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2399 00:24:48.120081
2400 00:24:48.123937 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2401 00:24:48.127342 [DutyScan_Calibration_Flow] ====Done====
2402 00:24:48.127447
2403 00:24:48.130214 [DutyScan_Calibration_Flow] k_type=3
2404 00:24:48.146547
2405 00:24:48.146622 ==DQM 0 ==
2406 00:24:48.149702 Final DQM duty delay cell = 0
2407 00:24:48.153195 [0] MAX Duty = 5093%(X100), DQS PI = 18
2408 00:24:48.156295 [0] MIN Duty = 4875%(X100), DQS PI = 48
2409 00:24:48.156393 [0] AVG Duty = 4984%(X100)
2410 00:24:48.159993
2411 00:24:48.160087 ==DQM 1 ==
2412 00:24:48.163480 Final DQM duty delay cell = 0
2413 00:24:48.166531 [0] MAX Duty = 5156%(X100), DQS PI = 62
2414 00:24:48.169605 [0] MIN Duty = 4938%(X100), DQS PI = 22
2415 00:24:48.169673 [0] AVG Duty = 5047%(X100)
2416 00:24:48.173228
2417 00:24:48.176488 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2418 00:24:48.176584
2419 00:24:48.180068 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2420 00:24:48.183321 [DutyScan_Calibration_Flow] ====Done====
2421 00:24:48.183390
2422 00:24:48.186443 [DutyScan_Calibration_Flow] k_type=2
2423 00:24:48.202204
2424 00:24:48.202286 ==DQ 0 ==
2425 00:24:48.205573 Final DQ duty delay cell = 0
2426 00:24:48.209164 [0] MAX Duty = 5093%(X100), DQS PI = 16
2427 00:24:48.212010 [0] MIN Duty = 4969%(X100), DQS PI = 14
2428 00:24:48.212098 [0] AVG Duty = 5031%(X100)
2429 00:24:48.212225
2430 00:24:48.215705 ==DQ 1 ==
2431 00:24:48.219197 Final DQ duty delay cell = -4
2432 00:24:48.222199 [-4] MAX Duty = 4969%(X100), DQS PI = 12
2433 00:24:48.225856 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2434 00:24:48.225929 [-4] AVG Duty = 4938%(X100)
2435 00:24:48.225989
2436 00:24:48.229003 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2437 00:24:48.232355
2438 00:24:48.232454 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2439 00:24:48.239110 [DutyScan_Calibration_Flow] ====Done====
2440 00:24:48.242632 nWR fixed to 30
2441 00:24:48.242702 [ModeRegInit_LP4] CH0 RK0
2442 00:24:48.246580 [ModeRegInit_LP4] CH0 RK1
2443 00:24:48.249015 [ModeRegInit_LP4] CH1 RK0
2444 00:24:48.249083 [ModeRegInit_LP4] CH1 RK1
2445 00:24:48.252453 match AC timing 7
2446 00:24:48.255816 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2447 00:24:48.259747 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2448 00:24:48.266495 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2449 00:24:48.269740 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2450 00:24:48.273232 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2451 00:24:48.276189 ==
2452 00:24:48.279677 Dram Type= 6, Freq= 0, CH_0, rank 0
2453 00:24:48.283300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2454 00:24:48.283401 ==
2455 00:24:48.286185 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2456 00:24:48.292906 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2457 00:24:48.302267 [CA 0] Center 40 (10~71) winsize 62
2458 00:24:48.306236 [CA 1] Center 39 (9~70) winsize 62
2459 00:24:48.309462 [CA 2] Center 36 (6~67) winsize 62
2460 00:24:48.312600 [CA 3] Center 35 (5~66) winsize 62
2461 00:24:48.315887 [CA 4] Center 35 (5~65) winsize 61
2462 00:24:48.319260 [CA 5] Center 34 (4~64) winsize 61
2463 00:24:48.319335
2464 00:24:48.322184 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2465 00:24:48.322292
2466 00:24:48.325686 [CATrainingPosCal] consider 1 rank data
2467 00:24:48.329129 u2DelayCellTimex100 = 270/100 ps
2468 00:24:48.332312 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2469 00:24:48.335995 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2470 00:24:48.342392 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2471 00:24:48.345680 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2472 00:24:48.349466 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2473 00:24:48.352479 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2474 00:24:48.352580
2475 00:24:48.355981 CA PerBit enable=1, Macro0, CA PI delay=34
2476 00:24:48.356079
2477 00:24:48.359420 [CBTSetCACLKResult] CA Dly = 34
2478 00:24:48.359516 CS Dly: 7 (0~38)
2479 00:24:48.359603 ==
2480 00:24:48.362628 Dram Type= 6, Freq= 0, CH_0, rank 1
2481 00:24:48.369166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2482 00:24:48.369260 ==
2483 00:24:48.373006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2484 00:24:48.379379 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2485 00:24:48.388531 [CA 0] Center 39 (9~70) winsize 62
2486 00:24:48.391590 [CA 1] Center 39 (9~70) winsize 62
2487 00:24:48.394955 [CA 2] Center 36 (6~67) winsize 62
2488 00:24:48.398438 [CA 3] Center 35 (5~66) winsize 62
2489 00:24:48.402256 [CA 4] Center 34 (4~65) winsize 62
2490 00:24:48.405008 [CA 5] Center 34 (4~64) winsize 61
2491 00:24:48.405091
2492 00:24:48.408529 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2493 00:24:48.408612
2494 00:24:48.412561 [CATrainingPosCal] consider 2 rank data
2495 00:24:48.415177 u2DelayCellTimex100 = 270/100 ps
2496 00:24:48.419045 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2497 00:24:48.422182 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2498 00:24:48.428560 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2499 00:24:48.432078 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2500 00:24:48.435288 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2501 00:24:48.438685 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2502 00:24:48.438762
2503 00:24:48.442141 CA PerBit enable=1, Macro0, CA PI delay=34
2504 00:24:48.442222
2505 00:24:48.445436 [CBTSetCACLKResult] CA Dly = 34
2506 00:24:48.445516 CS Dly: 8 (0~41)
2507 00:24:48.445579
2508 00:24:48.448598 ----->DramcWriteLeveling(PI) begin...
2509 00:24:48.448707 ==
2510 00:24:48.452327 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 00:24:48.458676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 00:24:48.458757 ==
2513 00:24:48.462392 Write leveling (Byte 0): 29 => 29
2514 00:24:48.465610 Write leveling (Byte 1): 29 => 29
2515 00:24:48.465690 DramcWriteLeveling(PI) end<-----
2516 00:24:48.465753
2517 00:24:48.468924 ==
2518 00:24:48.469003 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 00:24:48.475782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 00:24:48.475862 ==
2521 00:24:48.478864 [Gating] SW mode calibration
2522 00:24:48.485630 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2523 00:24:48.489111 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2524 00:24:48.495617 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 00:24:48.499060 0 15 4 | B1->B0 | 2424 3030 | 0 1 | (0 0) (1 1)
2526 00:24:48.502288 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 00:24:48.505725 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 00:24:48.512775 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 00:24:48.516056 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 00:24:48.519493 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 00:24:48.525982 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 00:24:48.529352 1 0 0 | B1->B0 | 3333 3131 | 1 1 | (1 1) (1 0)
2533 00:24:48.532892 1 0 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2534 00:24:48.539528 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 00:24:48.542647 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 00:24:48.546056 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 00:24:48.553002 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 00:24:48.556536 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 00:24:48.559877 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 00:24:48.563164 1 1 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2541 00:24:48.569792 1 1 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2542 00:24:48.573271 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 00:24:48.576521 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 00:24:48.583036 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 00:24:48.586834 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 00:24:48.590136 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 00:24:48.596797 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 00:24:48.599831 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2549 00:24:48.603586 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 00:24:48.610268 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 00:24:48.613227 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 00:24:48.616650 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 00:24:48.619990 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 00:24:48.626672 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 00:24:48.630072 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 00:24:48.633580 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 00:24:48.640522 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 00:24:48.643622 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 00:24:48.646835 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 00:24:48.653703 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 00:24:48.657045 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 00:24:48.660206 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 00:24:48.667233 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 00:24:48.670555 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2565 00:24:48.673907 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 00:24:48.677037 Total UI for P1: 0, mck2ui 16
2567 00:24:48.680818 best dqsien dly found for B0: ( 1, 4, 0)
2568 00:24:48.683887 Total UI for P1: 0, mck2ui 16
2569 00:24:48.687469 best dqsien dly found for B1: ( 1, 4, 0)
2570 00:24:48.690350 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2571 00:24:48.694017 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2572 00:24:48.694122
2573 00:24:48.697196 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2574 00:24:48.700954 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2575 00:24:48.704174 [Gating] SW calibration Done
2576 00:24:48.704255 ==
2577 00:24:48.707151 Dram Type= 6, Freq= 0, CH_0, rank 0
2578 00:24:48.710994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2579 00:24:48.714012 ==
2580 00:24:48.714092 RX Vref Scan: 0
2581 00:24:48.714155
2582 00:24:48.717627 RX Vref 0 -> 0, step: 1
2583 00:24:48.717707
2584 00:24:48.717770 RX Delay -40 -> 252, step: 8
2585 00:24:48.724472 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2586 00:24:48.727558 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2587 00:24:48.730725 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2588 00:24:48.734453 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2589 00:24:48.737551 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2590 00:24:48.744510 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2591 00:24:48.747575 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2592 00:24:48.751137 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2593 00:24:48.754253 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2594 00:24:48.757634 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2595 00:24:48.761067 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2596 00:24:48.767779 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2597 00:24:48.771357 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2598 00:24:48.774378 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2599 00:24:48.777995 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2600 00:24:48.781609 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2601 00:24:48.784982 ==
2602 00:24:48.787786 Dram Type= 6, Freq= 0, CH_0, rank 0
2603 00:24:48.791107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2604 00:24:48.791185 ==
2605 00:24:48.791271 DQS Delay:
2606 00:24:48.794951 DQS0 = 0, DQS1 = 0
2607 00:24:48.795024 DQM Delay:
2608 00:24:48.798187 DQM0 = 115, DQM1 = 107
2609 00:24:48.798261 DQ Delay:
2610 00:24:48.801286 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2611 00:24:48.804822 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2612 00:24:48.808006 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2613 00:24:48.811252 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2614 00:24:48.811327
2615 00:24:48.811425
2616 00:24:48.811529 ==
2617 00:24:48.814806 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 00:24:48.821449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 00:24:48.821526 ==
2620 00:24:48.821614
2621 00:24:48.821691
2622 00:24:48.821764 TX Vref Scan disable
2623 00:24:48.824982 == TX Byte 0 ==
2624 00:24:48.828525 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2625 00:24:48.831669 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2626 00:24:48.835180 == TX Byte 1 ==
2627 00:24:48.838245 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2628 00:24:48.841476 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2629 00:24:48.841560 ==
2630 00:24:48.845153 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 00:24:48.851730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 00:24:48.851841 ==
2633 00:24:48.862707 TX Vref=22, minBit 1, minWin=25, winSum=416
2634 00:24:48.866000 TX Vref=24, minBit 1, minWin=25, winSum=418
2635 00:24:48.869287 TX Vref=26, minBit 5, minWin=25, winSum=426
2636 00:24:48.872576 TX Vref=28, minBit 0, minWin=26, winSum=429
2637 00:24:48.875880 TX Vref=30, minBit 1, minWin=26, winSum=431
2638 00:24:48.879682 TX Vref=32, minBit 1, minWin=26, winSum=435
2639 00:24:48.886017 [TxChooseVref] Worse bit 1, Min win 26, Win sum 435, Final Vref 32
2640 00:24:48.886104
2641 00:24:48.889331 Final TX Range 1 Vref 32
2642 00:24:48.889403
2643 00:24:48.889482 ==
2644 00:24:48.892906 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 00:24:48.896360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 00:24:48.896469 ==
2647 00:24:48.896536
2648 00:24:48.896596
2649 00:24:48.899521 TX Vref Scan disable
2650 00:24:48.902873 == TX Byte 0 ==
2651 00:24:48.906293 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2652 00:24:48.909941 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2653 00:24:48.913058 == TX Byte 1 ==
2654 00:24:48.916556 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2655 00:24:48.919492 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2656 00:24:48.919573
2657 00:24:48.923513 [DATLAT]
2658 00:24:48.923615 Freq=1200, CH0 RK0
2659 00:24:48.923693
2660 00:24:48.926809 DATLAT Default: 0xd
2661 00:24:48.926888 0, 0xFFFF, sum = 0
2662 00:24:48.930091 1, 0xFFFF, sum = 0
2663 00:24:48.930172 2, 0xFFFF, sum = 0
2664 00:24:48.933334 3, 0xFFFF, sum = 0
2665 00:24:48.933416 4, 0xFFFF, sum = 0
2666 00:24:48.936427 5, 0xFFFF, sum = 0
2667 00:24:48.936544 6, 0xFFFF, sum = 0
2668 00:24:48.939702 7, 0xFFFF, sum = 0
2669 00:24:48.939783 8, 0xFFFF, sum = 0
2670 00:24:48.943716 9, 0xFFFF, sum = 0
2671 00:24:48.943797 10, 0xFFFF, sum = 0
2672 00:24:48.946475 11, 0xFFFF, sum = 0
2673 00:24:48.946557 12, 0x0, sum = 1
2674 00:24:48.950095 13, 0x0, sum = 2
2675 00:24:48.950176 14, 0x0, sum = 3
2676 00:24:48.953118 15, 0x0, sum = 4
2677 00:24:48.953198 best_step = 13
2678 00:24:48.953261
2679 00:24:48.953337 ==
2680 00:24:48.956616 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 00:24:48.959922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 00:24:48.963057 ==
2683 00:24:48.963137 RX Vref Scan: 1
2684 00:24:48.963200
2685 00:24:48.967209 Set Vref Range= 32 -> 127
2686 00:24:48.967289
2687 00:24:48.970133 RX Vref 32 -> 127, step: 1
2688 00:24:48.970213
2689 00:24:48.970290 RX Delay -21 -> 252, step: 4
2690 00:24:48.970362
2691 00:24:48.973842 Set Vref, RX VrefLevel [Byte0]: 32
2692 00:24:48.977013 [Byte1]: 32
2693 00:24:48.980823
2694 00:24:48.980903 Set Vref, RX VrefLevel [Byte0]: 33
2695 00:24:48.984200 [Byte1]: 33
2696 00:24:48.988644
2697 00:24:48.988778 Set Vref, RX VrefLevel [Byte0]: 34
2698 00:24:48.992092 [Byte1]: 34
2699 00:24:48.996405
2700 00:24:48.996484 Set Vref, RX VrefLevel [Byte0]: 35
2701 00:24:48.999752 [Byte1]: 35
2702 00:24:49.004525
2703 00:24:49.004605 Set Vref, RX VrefLevel [Byte0]: 36
2704 00:24:49.007686 [Byte1]: 36
2705 00:24:49.012443
2706 00:24:49.012577 Set Vref, RX VrefLevel [Byte0]: 37
2707 00:24:49.015718 [Byte1]: 37
2708 00:24:49.020352
2709 00:24:49.020432 Set Vref, RX VrefLevel [Byte0]: 38
2710 00:24:49.023405 [Byte1]: 38
2711 00:24:49.028601
2712 00:24:49.028705 Set Vref, RX VrefLevel [Byte0]: 39
2713 00:24:49.031739 [Byte1]: 39
2714 00:24:49.036076
2715 00:24:49.036158 Set Vref, RX VrefLevel [Byte0]: 40
2716 00:24:49.039434 [Byte1]: 40
2717 00:24:49.044099
2718 00:24:49.044181 Set Vref, RX VrefLevel [Byte0]: 41
2719 00:24:49.047698 [Byte1]: 41
2720 00:24:49.052451
2721 00:24:49.052530 Set Vref, RX VrefLevel [Byte0]: 42
2722 00:24:49.055480 [Byte1]: 42
2723 00:24:49.060092
2724 00:24:49.060171 Set Vref, RX VrefLevel [Byte0]: 43
2725 00:24:49.063743 [Byte1]: 43
2726 00:24:49.068121
2727 00:24:49.068201 Set Vref, RX VrefLevel [Byte0]: 44
2728 00:24:49.071583 [Byte1]: 44
2729 00:24:49.075935
2730 00:24:49.076038 Set Vref, RX VrefLevel [Byte0]: 45
2731 00:24:49.078893 [Byte1]: 45
2732 00:24:49.083887
2733 00:24:49.083983 Set Vref, RX VrefLevel [Byte0]: 46
2734 00:24:49.087024 [Byte1]: 46
2735 00:24:49.091502
2736 00:24:49.091599 Set Vref, RX VrefLevel [Byte0]: 47
2737 00:24:49.095040 [Byte1]: 47
2738 00:24:49.099559
2739 00:24:49.099656 Set Vref, RX VrefLevel [Byte0]: 48
2740 00:24:49.102759 [Byte1]: 48
2741 00:24:49.107498
2742 00:24:49.107595 Set Vref, RX VrefLevel [Byte0]: 49
2743 00:24:49.110758 [Byte1]: 49
2744 00:24:49.115778
2745 00:24:49.115874 Set Vref, RX VrefLevel [Byte0]: 50
2746 00:24:49.119012 [Byte1]: 50
2747 00:24:49.123109
2748 00:24:49.123206 Set Vref, RX VrefLevel [Byte0]: 51
2749 00:24:49.126943 [Byte1]: 51
2750 00:24:49.131592
2751 00:24:49.131687 Set Vref, RX VrefLevel [Byte0]: 52
2752 00:24:49.134989 [Byte1]: 52
2753 00:24:49.139119
2754 00:24:49.139216 Set Vref, RX VrefLevel [Byte0]: 53
2755 00:24:49.142775 [Byte1]: 53
2756 00:24:49.147345
2757 00:24:49.147441 Set Vref, RX VrefLevel [Byte0]: 54
2758 00:24:49.150531 [Byte1]: 54
2759 00:24:49.155378
2760 00:24:49.155474 Set Vref, RX VrefLevel [Byte0]: 55
2761 00:24:49.158502 [Byte1]: 55
2762 00:24:49.163289
2763 00:24:49.163385 Set Vref, RX VrefLevel [Byte0]: 56
2764 00:24:49.166386 [Byte1]: 56
2765 00:24:49.171180
2766 00:24:49.171276 Set Vref, RX VrefLevel [Byte0]: 57
2767 00:24:49.174116 [Byte1]: 57
2768 00:24:49.178929
2769 00:24:49.179068 Set Vref, RX VrefLevel [Byte0]: 58
2770 00:24:49.182026 [Byte1]: 58
2771 00:24:49.186852
2772 00:24:49.186951 Set Vref, RX VrefLevel [Byte0]: 59
2773 00:24:49.190059 [Byte1]: 59
2774 00:24:49.195077
2775 00:24:49.195156 Set Vref, RX VrefLevel [Byte0]: 60
2776 00:24:49.197775 [Byte1]: 60
2777 00:24:49.202387
2778 00:24:49.202467 Set Vref, RX VrefLevel [Byte0]: 61
2779 00:24:49.205921 [Byte1]: 61
2780 00:24:49.210291
2781 00:24:49.210375 Set Vref, RX VrefLevel [Byte0]: 62
2782 00:24:49.213638 [Byte1]: 62
2783 00:24:49.218663
2784 00:24:49.218743 Set Vref, RX VrefLevel [Byte0]: 63
2785 00:24:49.221907 [Byte1]: 63
2786 00:24:49.226579
2787 00:24:49.226659 Set Vref, RX VrefLevel [Byte0]: 64
2788 00:24:49.229638 [Byte1]: 64
2789 00:24:49.234179
2790 00:24:49.234256 Set Vref, RX VrefLevel [Byte0]: 65
2791 00:24:49.237674 [Byte1]: 65
2792 00:24:49.242534
2793 00:24:49.242608 Set Vref, RX VrefLevel [Byte0]: 66
2794 00:24:49.245345 [Byte1]: 66
2795 00:24:49.250078
2796 00:24:49.253306 Set Vref, RX VrefLevel [Byte0]: 67
2797 00:24:49.253394 [Byte1]: 67
2798 00:24:49.258056
2799 00:24:49.258129 Final RX Vref Byte 0 = 52 to rank0
2800 00:24:49.261369 Final RX Vref Byte 1 = 50 to rank0
2801 00:24:49.264912 Final RX Vref Byte 0 = 52 to rank1
2802 00:24:49.268543 Final RX Vref Byte 1 = 50 to rank1==
2803 00:24:49.271933 Dram Type= 6, Freq= 0, CH_0, rank 0
2804 00:24:49.275594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2805 00:24:49.278536 ==
2806 00:24:49.278611 DQS Delay:
2807 00:24:49.278700 DQS0 = 0, DQS1 = 0
2808 00:24:49.281645 DQM Delay:
2809 00:24:49.281717 DQM0 = 115, DQM1 = 105
2810 00:24:49.284996 DQ Delay:
2811 00:24:49.288762 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2812 00:24:49.292324 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =122
2813 00:24:49.295135 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
2814 00:24:49.298358 DQ12 =114, DQ13 =110, DQ14 =120, DQ15 =114
2815 00:24:49.298435
2816 00:24:49.298516
2817 00:24:49.305299 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 409 ps
2818 00:24:49.308605 CH0 RK0: MR19=403, MR18=2F1
2819 00:24:49.315530 CH0_RK0: MR19=0x403, MR18=0x2F1, DQSOSC=409, MR23=63, INC=39, DEC=26
2820 00:24:49.315643
2821 00:24:49.318713 ----->DramcWriteLeveling(PI) begin...
2822 00:24:49.318798 ==
2823 00:24:49.322115 Dram Type= 6, Freq= 0, CH_0, rank 1
2824 00:24:49.325475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 00:24:49.325567 ==
2826 00:24:49.328694 Write leveling (Byte 0): 33 => 33
2827 00:24:49.331955 Write leveling (Byte 1): 28 => 28
2828 00:24:49.335302 DramcWriteLeveling(PI) end<-----
2829 00:24:49.335383
2830 00:24:49.335445 ==
2831 00:24:49.338969 Dram Type= 6, Freq= 0, CH_0, rank 1
2832 00:24:49.342357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2833 00:24:49.342438 ==
2834 00:24:49.345527 [Gating] SW mode calibration
2835 00:24:49.352537 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2836 00:24:49.358994 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2837 00:24:49.362305 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2838 00:24:49.366149 0 15 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2839 00:24:49.372549 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 00:24:49.375787 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 00:24:49.379210 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 00:24:49.385664 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 00:24:49.389466 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2844 00:24:49.392412 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
2845 00:24:49.399268 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
2846 00:24:49.402480 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 00:24:49.405764 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 00:24:49.409530 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 00:24:49.415897 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 00:24:49.419606 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 00:24:49.422875 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2852 00:24:49.429256 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2853 00:24:49.432556 1 1 0 | B1->B0 | 2e2e 3c3c | 1 0 | (0 0) (0 0)
2854 00:24:49.436116 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 00:24:49.443037 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 00:24:49.446370 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 00:24:49.449762 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 00:24:49.456903 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 00:24:49.460230 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2860 00:24:49.463197 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2861 00:24:49.467095 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2862 00:24:49.473487 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2863 00:24:49.476565 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 00:24:49.480083 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 00:24:49.487083 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 00:24:49.490244 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 00:24:49.493986 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 00:24:49.500101 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 00:24:49.503476 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 00:24:49.507134 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 00:24:49.510473 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 00:24:49.517212 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 00:24:49.520688 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 00:24:49.523567 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 00:24:49.530469 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2876 00:24:49.533722 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2877 00:24:49.537414 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2878 00:24:49.540735 Total UI for P1: 0, mck2ui 16
2879 00:24:49.544169 best dqsien dly found for B0: ( 1, 3, 26)
2880 00:24:49.550790 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 00:24:49.550868 Total UI for P1: 0, mck2ui 16
2882 00:24:49.554070 best dqsien dly found for B1: ( 1, 4, 0)
2883 00:24:49.557964 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2884 00:24:49.564348 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2885 00:24:49.564432
2886 00:24:49.567785 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2887 00:24:49.570844 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2888 00:24:49.574122 [Gating] SW calibration Done
2889 00:24:49.574202 ==
2890 00:24:49.577683 Dram Type= 6, Freq= 0, CH_0, rank 1
2891 00:24:49.581183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 00:24:49.581264 ==
2893 00:24:49.581327 RX Vref Scan: 0
2894 00:24:49.581386
2895 00:24:49.584171 RX Vref 0 -> 0, step: 1
2896 00:24:49.584251
2897 00:24:49.587993 RX Delay -40 -> 252, step: 8
2898 00:24:49.591212 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2899 00:24:49.594286 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2900 00:24:49.601096 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2901 00:24:49.604477 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2902 00:24:49.607978 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2903 00:24:49.611333 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2904 00:24:49.614817 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2905 00:24:49.618335 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2906 00:24:49.624600 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2907 00:24:49.628050 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2908 00:24:49.631471 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2909 00:24:49.634534 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2910 00:24:49.638263 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2911 00:24:49.641969 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2912 00:24:49.648618 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2913 00:24:49.651592 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2914 00:24:49.651701 ==
2915 00:24:49.654739 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 00:24:49.658294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 00:24:49.658391 ==
2918 00:24:49.661590 DQS Delay:
2919 00:24:49.661672 DQS0 = 0, DQS1 = 0
2920 00:24:49.661736 DQM Delay:
2921 00:24:49.665268 DQM0 = 115, DQM1 = 106
2922 00:24:49.665350 DQ Delay:
2923 00:24:49.668443 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2924 00:24:49.671568 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2925 00:24:49.674993 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =95
2926 00:24:49.681981 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =111
2927 00:24:49.682099
2928 00:24:49.682188
2929 00:24:49.682300 ==
2930 00:24:49.685149 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 00:24:49.688650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 00:24:49.688794 ==
2933 00:24:49.688901
2934 00:24:49.688992
2935 00:24:49.691931 TX Vref Scan disable
2936 00:24:49.692029 == TX Byte 0 ==
2937 00:24:49.698555 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2938 00:24:49.701834 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2939 00:24:49.701914 == TX Byte 1 ==
2940 00:24:49.708857 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2941 00:24:49.712045 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2942 00:24:49.712145 ==
2943 00:24:49.715617 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 00:24:49.719193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 00:24:49.719296 ==
2946 00:24:49.731264 TX Vref=22, minBit 0, minWin=25, winSum=422
2947 00:24:49.734703 TX Vref=24, minBit 1, minWin=25, winSum=428
2948 00:24:49.737882 TX Vref=26, minBit 0, minWin=26, winSum=429
2949 00:24:49.741145 TX Vref=28, minBit 3, minWin=26, winSum=439
2950 00:24:49.744388 TX Vref=30, minBit 0, minWin=27, winSum=438
2951 00:24:49.748074 TX Vref=32, minBit 12, minWin=26, winSum=435
2952 00:24:49.754670 [TxChooseVref] Worse bit 0, Min win 27, Win sum 438, Final Vref 30
2953 00:24:49.754773
2954 00:24:49.758607 Final TX Range 1 Vref 30
2955 00:24:49.758707
2956 00:24:49.758797 ==
2957 00:24:49.761418 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 00:24:49.765221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 00:24:49.765302 ==
2960 00:24:49.765367
2961 00:24:49.765425
2962 00:24:49.768084 TX Vref Scan disable
2963 00:24:49.771857 == TX Byte 0 ==
2964 00:24:49.774939 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2965 00:24:49.778630 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2966 00:24:49.781942 == TX Byte 1 ==
2967 00:24:49.785029 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2968 00:24:49.788207 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2969 00:24:49.788283
2970 00:24:49.791604 [DATLAT]
2971 00:24:49.791701 Freq=1200, CH0 RK1
2972 00:24:49.791792
2973 00:24:49.795381 DATLAT Default: 0xd
2974 00:24:49.795484 0, 0xFFFF, sum = 0
2975 00:24:49.798355 1, 0xFFFF, sum = 0
2976 00:24:49.798435 2, 0xFFFF, sum = 0
2977 00:24:49.802381 3, 0xFFFF, sum = 0
2978 00:24:49.802461 4, 0xFFFF, sum = 0
2979 00:24:49.805318 5, 0xFFFF, sum = 0
2980 00:24:49.805428 6, 0xFFFF, sum = 0
2981 00:24:49.808844 7, 0xFFFF, sum = 0
2982 00:24:49.808918 8, 0xFFFF, sum = 0
2983 00:24:49.812291 9, 0xFFFF, sum = 0
2984 00:24:49.812389 10, 0xFFFF, sum = 0
2985 00:24:49.815514 11, 0xFFFF, sum = 0
2986 00:24:49.815616 12, 0x0, sum = 1
2987 00:24:49.818538 13, 0x0, sum = 2
2988 00:24:49.818646 14, 0x0, sum = 3
2989 00:24:49.821915 15, 0x0, sum = 4
2990 00:24:49.822017 best_step = 13
2991 00:24:49.822085
2992 00:24:49.822144 ==
2993 00:24:49.825368 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 00:24:49.831840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 00:24:49.831945 ==
2996 00:24:49.832037 RX Vref Scan: 0
2997 00:24:49.832125
2998 00:24:49.835567 RX Vref 0 -> 0, step: 1
2999 00:24:49.835673
3000 00:24:49.838880 RX Delay -21 -> 252, step: 4
3001 00:24:49.841893 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3002 00:24:49.845347 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3003 00:24:49.849198 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3004 00:24:49.855522 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3005 00:24:49.859087 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3006 00:24:49.862315 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3007 00:24:49.865983 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3008 00:24:49.868898 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3009 00:24:49.875657 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3010 00:24:49.878968 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3011 00:24:49.882366 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3012 00:24:49.885801 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3013 00:24:49.889516 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3014 00:24:49.892647 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3015 00:24:49.899276 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3016 00:24:49.902560 iDelay=195, Bit 15, Center 112 (43 ~ 182) 140
3017 00:24:49.902671 ==
3018 00:24:49.906021 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 00:24:49.909250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 00:24:49.909360 ==
3021 00:24:49.912588 DQS Delay:
3022 00:24:49.912676 DQS0 = 0, DQS1 = 0
3023 00:24:49.912756 DQM Delay:
3024 00:24:49.915878 DQM0 = 114, DQM1 = 104
3025 00:24:49.915973 DQ Delay:
3026 00:24:49.919279 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3027 00:24:49.922778 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3028 00:24:49.925961 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3029 00:24:49.929460 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =112
3030 00:24:49.933220
3031 00:24:49.933299
3032 00:24:49.939298 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3033 00:24:49.942973 CH0 RK1: MR19=403, MR18=1F2
3034 00:24:49.946863 CH0_RK1: MR19=0x403, MR18=0x1F2, DQSOSC=409, MR23=63, INC=39, DEC=26
3035 00:24:49.949939 [RxdqsGatingPostProcess] freq 1200
3036 00:24:49.956516 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3037 00:24:49.959613 best DQS0 dly(2T, 0.5T) = (0, 12)
3038 00:24:49.963409 best DQS1 dly(2T, 0.5T) = (0, 12)
3039 00:24:49.966724 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3040 00:24:49.970094 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3041 00:24:49.973457 best DQS0 dly(2T, 0.5T) = (0, 11)
3042 00:24:49.976597 best DQS1 dly(2T, 0.5T) = (0, 12)
3043 00:24:49.979934 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3044 00:24:49.980013 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3045 00:24:49.983610 Pre-setting of DQS Precalculation
3046 00:24:49.989893 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3047 00:24:49.989998 ==
3048 00:24:49.993363 Dram Type= 6, Freq= 0, CH_1, rank 0
3049 00:24:49.996937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3050 00:24:49.997012 ==
3051 00:24:50.003570 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3052 00:24:50.010173 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3053 00:24:50.017228 [CA 0] Center 38 (8~68) winsize 61
3054 00:24:50.020362 [CA 1] Center 38 (8~68) winsize 61
3055 00:24:50.023589 [CA 2] Center 35 (5~65) winsize 61
3056 00:24:50.026952 [CA 3] Center 34 (4~64) winsize 61
3057 00:24:50.030649 [CA 4] Center 34 (4~65) winsize 62
3058 00:24:50.033915 [CA 5] Center 33 (3~64) winsize 62
3059 00:24:50.033989
3060 00:24:50.037198 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3061 00:24:50.037273
3062 00:24:50.040590 [CATrainingPosCal] consider 1 rank data
3063 00:24:50.043634 u2DelayCellTimex100 = 270/100 ps
3064 00:24:50.047189 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3065 00:24:50.050369 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3066 00:24:50.053666 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3067 00:24:50.060503 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3068 00:24:50.063907 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3069 00:24:50.067389 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3070 00:24:50.067495
3071 00:24:50.070718 CA PerBit enable=1, Macro0, CA PI delay=33
3072 00:24:50.070816
3073 00:24:50.073826 [CBTSetCACLKResult] CA Dly = 33
3074 00:24:50.073900 CS Dly: 6 (0~37)
3075 00:24:50.073967 ==
3076 00:24:50.077304 Dram Type= 6, Freq= 0, CH_1, rank 1
3077 00:24:50.080597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 00:24:50.084236 ==
3079 00:24:50.087515 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3080 00:24:50.094056 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3081 00:24:50.102677 [CA 0] Center 38 (8~68) winsize 61
3082 00:24:50.106031 [CA 1] Center 38 (8~68) winsize 61
3083 00:24:50.108992 [CA 2] Center 35 (5~65) winsize 61
3084 00:24:50.112404 [CA 3] Center 34 (4~65) winsize 62
3085 00:24:50.116466 [CA 4] Center 34 (4~65) winsize 62
3086 00:24:50.119266 [CA 5] Center 33 (3~64) winsize 62
3087 00:24:50.119339
3088 00:24:50.122598 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3089 00:24:50.122681
3090 00:24:50.126111 [CATrainingPosCal] consider 2 rank data
3091 00:24:50.129456 u2DelayCellTimex100 = 270/100 ps
3092 00:24:50.133033 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3093 00:24:50.136282 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3094 00:24:50.139482 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3095 00:24:50.142870 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3096 00:24:50.150015 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3097 00:24:50.153075 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3098 00:24:50.153155
3099 00:24:50.156328 CA PerBit enable=1, Macro0, CA PI delay=33
3100 00:24:50.156411
3101 00:24:50.160334 [CBTSetCACLKResult] CA Dly = 33
3102 00:24:50.160414 CS Dly: 7 (0~40)
3103 00:24:50.160506
3104 00:24:50.163074 ----->DramcWriteLeveling(PI) begin...
3105 00:24:50.163170 ==
3106 00:24:50.166511 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 00:24:50.173050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 00:24:50.173156 ==
3109 00:24:50.176366 Write leveling (Byte 0): 26 => 26
3110 00:24:50.176460 Write leveling (Byte 1): 27 => 27
3111 00:24:50.179687 DramcWriteLeveling(PI) end<-----
3112 00:24:50.179795
3113 00:24:50.179858 ==
3114 00:24:50.183061 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 00:24:50.190229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 00:24:50.190326 ==
3117 00:24:50.193595 [Gating] SW mode calibration
3118 00:24:50.199853 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3119 00:24:50.203386 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3120 00:24:50.206806 0 15 0 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3121 00:24:50.213453 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 00:24:50.216634 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 00:24:50.220030 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 00:24:50.226792 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 00:24:50.230069 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 00:24:50.233752 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 00:24:50.240850 0 15 28 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 0)
3128 00:24:50.243192 1 0 0 | B1->B0 | 2424 2d2d | 0 1 | (0 0) (1 0)
3129 00:24:50.247052 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 00:24:50.253829 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3131 00:24:50.256802 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 00:24:50.260632 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 00:24:50.267160 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 00:24:50.270647 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3135 00:24:50.274122 1 0 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3136 00:24:50.277072 1 1 0 | B1->B0 | 4545 3535 | 0 0 | (0 0) (0 0)
3137 00:24:50.283748 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 00:24:50.287324 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 00:24:50.290688 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 00:24:50.297248 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 00:24:50.300514 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 00:24:50.304084 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 00:24:50.310605 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3144 00:24:50.314083 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3145 00:24:50.317747 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 00:24:50.320931 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 00:24:50.327549 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 00:24:50.331059 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 00:24:50.334803 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 00:24:50.341282 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 00:24:50.344611 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 00:24:50.348036 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 00:24:50.354625 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 00:24:50.357942 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 00:24:50.361773 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 00:24:50.368433 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 00:24:50.371535 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 00:24:50.374878 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 00:24:50.378230 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3160 00:24:50.385085 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3161 00:24:50.388268 Total UI for P1: 0, mck2ui 16
3162 00:24:50.391521 best dqsien dly found for B1: ( 1, 3, 28)
3163 00:24:50.394943 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 00:24:50.398553 Total UI for P1: 0, mck2ui 16
3165 00:24:50.401840 best dqsien dly found for B0: ( 1, 3, 30)
3166 00:24:50.405926 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3167 00:24:50.408675 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3168 00:24:50.408787
3169 00:24:50.412238 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3170 00:24:50.415245 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3171 00:24:50.418538 [Gating] SW calibration Done
3172 00:24:50.418610 ==
3173 00:24:50.422414 Dram Type= 6, Freq= 0, CH_1, rank 0
3174 00:24:50.425348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3175 00:24:50.425421 ==
3176 00:24:50.428730 RX Vref Scan: 0
3177 00:24:50.428807
3178 00:24:50.432342 RX Vref 0 -> 0, step: 1
3179 00:24:50.432444
3180 00:24:50.432535 RX Delay -40 -> 252, step: 8
3181 00:24:50.439388 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3182 00:24:50.442377 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3183 00:24:50.445617 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3184 00:24:50.448876 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3185 00:24:50.452501 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3186 00:24:50.459483 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3187 00:24:50.462261 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3188 00:24:50.466037 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3189 00:24:50.469077 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3190 00:24:50.472749 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3191 00:24:50.475673 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3192 00:24:50.483043 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3193 00:24:50.486163 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3194 00:24:50.489305 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3195 00:24:50.492963 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3196 00:24:50.496238 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3197 00:24:50.499104 ==
3198 00:24:50.499203 Dram Type= 6, Freq= 0, CH_1, rank 0
3199 00:24:50.506077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3200 00:24:50.506187 ==
3201 00:24:50.506278 DQS Delay:
3202 00:24:50.510048 DQS0 = 0, DQS1 = 0
3203 00:24:50.510121 DQM Delay:
3204 00:24:50.512826 DQM0 = 116, DQM1 = 109
3205 00:24:50.512907 DQ Delay:
3206 00:24:50.516177 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3207 00:24:50.519123 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3208 00:24:50.522784 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3209 00:24:50.526073 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =115
3210 00:24:50.526145
3211 00:24:50.526206
3212 00:24:50.526263 ==
3213 00:24:50.529636 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 00:24:50.532720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 00:24:50.536374 ==
3216 00:24:50.536451
3217 00:24:50.536511
3218 00:24:50.536569 TX Vref Scan disable
3219 00:24:50.539698 == TX Byte 0 ==
3220 00:24:50.543005 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3221 00:24:50.546345 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3222 00:24:50.549340 == TX Byte 1 ==
3223 00:24:50.553181 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3224 00:24:50.556528 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3225 00:24:50.556625 ==
3226 00:24:50.559424 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 00:24:50.566125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 00:24:50.566207 ==
3229 00:24:50.576785 TX Vref=22, minBit 11, minWin=24, winSum=405
3230 00:24:50.580398 TX Vref=24, minBit 9, minWin=24, winSum=409
3231 00:24:50.583418 TX Vref=26, minBit 1, minWin=25, winSum=419
3232 00:24:50.587216 TX Vref=28, minBit 0, minWin=26, winSum=425
3233 00:24:50.590278 TX Vref=30, minBit 9, minWin=25, winSum=425
3234 00:24:50.593504 TX Vref=32, minBit 1, minWin=26, winSum=426
3235 00:24:50.600234 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 32
3236 00:24:50.600366
3237 00:24:50.603561 Final TX Range 1 Vref 32
3238 00:24:50.603659
3239 00:24:50.603749 ==
3240 00:24:50.607118 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 00:24:50.610319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 00:24:50.610396 ==
3243 00:24:50.610457
3244 00:24:50.610515
3245 00:24:50.613893 TX Vref Scan disable
3246 00:24:50.617322 == TX Byte 0 ==
3247 00:24:50.620308 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3248 00:24:50.623934 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3249 00:24:50.627268 == TX Byte 1 ==
3250 00:24:50.630576 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3251 00:24:50.633896 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3252 00:24:50.633996
3253 00:24:50.637255 [DATLAT]
3254 00:24:50.637327 Freq=1200, CH1 RK0
3255 00:24:50.637388
3256 00:24:50.640818 DATLAT Default: 0xd
3257 00:24:50.640891 0, 0xFFFF, sum = 0
3258 00:24:50.644266 1, 0xFFFF, sum = 0
3259 00:24:50.644366 2, 0xFFFF, sum = 0
3260 00:24:50.647681 3, 0xFFFF, sum = 0
3261 00:24:50.647787 4, 0xFFFF, sum = 0
3262 00:24:50.650592 5, 0xFFFF, sum = 0
3263 00:24:50.650666 6, 0xFFFF, sum = 0
3264 00:24:50.654087 7, 0xFFFF, sum = 0
3265 00:24:50.654159 8, 0xFFFF, sum = 0
3266 00:24:50.657377 9, 0xFFFF, sum = 0
3267 00:24:50.657456 10, 0xFFFF, sum = 0
3268 00:24:50.660820 11, 0xFFFF, sum = 0
3269 00:24:50.660922 12, 0x0, sum = 1
3270 00:24:50.664215 13, 0x0, sum = 2
3271 00:24:50.664315 14, 0x0, sum = 3
3272 00:24:50.667601 15, 0x0, sum = 4
3273 00:24:50.667687 best_step = 13
3274 00:24:50.667752
3275 00:24:50.667811 ==
3276 00:24:50.671411 Dram Type= 6, Freq= 0, CH_1, rank 0
3277 00:24:50.677505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3278 00:24:50.677584 ==
3279 00:24:50.677647 RX Vref Scan: 1
3280 00:24:50.677706
3281 00:24:50.681281 Set Vref Range= 32 -> 127
3282 00:24:50.681352
3283 00:24:50.684221 RX Vref 32 -> 127, step: 1
3284 00:24:50.684288
3285 00:24:50.684352 RX Delay -21 -> 252, step: 4
3286 00:24:50.684411
3287 00:24:50.687903 Set Vref, RX VrefLevel [Byte0]: 32
3288 00:24:50.691243 [Byte1]: 32
3289 00:24:50.695324
3290 00:24:50.695401 Set Vref, RX VrefLevel [Byte0]: 33
3291 00:24:50.698351 [Byte1]: 33
3292 00:24:50.702916
3293 00:24:50.703036 Set Vref, RX VrefLevel [Byte0]: 34
3294 00:24:50.706180 [Byte1]: 34
3295 00:24:50.711339
3296 00:24:50.711441 Set Vref, RX VrefLevel [Byte0]: 35
3297 00:24:50.714658 [Byte1]: 35
3298 00:24:50.718803
3299 00:24:50.718913 Set Vref, RX VrefLevel [Byte0]: 36
3300 00:24:50.722321 [Byte1]: 36
3301 00:24:50.726962
3302 00:24:50.727059 Set Vref, RX VrefLevel [Byte0]: 37
3303 00:24:50.730210 [Byte1]: 37
3304 00:24:50.735113
3305 00:24:50.735210 Set Vref, RX VrefLevel [Byte0]: 38
3306 00:24:50.737930 [Byte1]: 38
3307 00:24:50.742462
3308 00:24:50.742534 Set Vref, RX VrefLevel [Byte0]: 39
3309 00:24:50.745973 [Byte1]: 39
3310 00:24:50.750824
3311 00:24:50.750917 Set Vref, RX VrefLevel [Byte0]: 40
3312 00:24:50.753740 [Byte1]: 40
3313 00:24:50.758374
3314 00:24:50.758515 Set Vref, RX VrefLevel [Byte0]: 41
3315 00:24:50.761616 [Byte1]: 41
3316 00:24:50.766723
3317 00:24:50.766811 Set Vref, RX VrefLevel [Byte0]: 42
3318 00:24:50.769784 [Byte1]: 42
3319 00:24:50.774648
3320 00:24:50.774719 Set Vref, RX VrefLevel [Byte0]: 43
3321 00:24:50.777557 [Byte1]: 43
3322 00:24:50.782281
3323 00:24:50.782352 Set Vref, RX VrefLevel [Byte0]: 44
3324 00:24:50.785969 [Byte1]: 44
3325 00:24:50.790405
3326 00:24:50.790480 Set Vref, RX VrefLevel [Byte0]: 45
3327 00:24:50.793663 [Byte1]: 45
3328 00:24:50.798128
3329 00:24:50.798207 Set Vref, RX VrefLevel [Byte0]: 46
3330 00:24:50.801315 [Byte1]: 46
3331 00:24:50.805961
3332 00:24:50.806039 Set Vref, RX VrefLevel [Byte0]: 47
3333 00:24:50.809490 [Byte1]: 47
3334 00:24:50.813897
3335 00:24:50.813969 Set Vref, RX VrefLevel [Byte0]: 48
3336 00:24:50.817675 [Byte1]: 48
3337 00:24:50.821972
3338 00:24:50.822050 Set Vref, RX VrefLevel [Byte0]: 49
3339 00:24:50.825146 [Byte1]: 49
3340 00:24:50.829817
3341 00:24:50.829887 Set Vref, RX VrefLevel [Byte0]: 50
3342 00:24:50.833512 [Byte1]: 50
3343 00:24:50.837685
3344 00:24:50.837757 Set Vref, RX VrefLevel [Byte0]: 51
3345 00:24:50.840988 [Byte1]: 51
3346 00:24:50.845904
3347 00:24:50.845980 Set Vref, RX VrefLevel [Byte0]: 52
3348 00:24:50.849438 [Byte1]: 52
3349 00:24:50.853290
3350 00:24:50.853358 Set Vref, RX VrefLevel [Byte0]: 53
3351 00:24:50.856968 [Byte1]: 53
3352 00:24:50.861512
3353 00:24:50.861591 Set Vref, RX VrefLevel [Byte0]: 54
3354 00:24:50.864521 [Byte1]: 54
3355 00:24:50.869646
3356 00:24:50.869735 Set Vref, RX VrefLevel [Byte0]: 55
3357 00:24:50.872996 [Byte1]: 55
3358 00:24:50.877500
3359 00:24:50.877573 Set Vref, RX VrefLevel [Byte0]: 56
3360 00:24:50.880865 [Byte1]: 56
3361 00:24:50.885209
3362 00:24:50.885311 Set Vref, RX VrefLevel [Byte0]: 57
3363 00:24:50.888547 [Byte1]: 57
3364 00:24:50.893060
3365 00:24:50.893191 Set Vref, RX VrefLevel [Byte0]: 58
3366 00:24:50.896821 [Byte1]: 58
3367 00:24:50.901420
3368 00:24:50.901500 Set Vref, RX VrefLevel [Byte0]: 59
3369 00:24:50.904541 [Byte1]: 59
3370 00:24:50.909408
3371 00:24:50.909538 Set Vref, RX VrefLevel [Byte0]: 60
3372 00:24:50.912644 [Byte1]: 60
3373 00:24:50.916940
3374 00:24:50.917017 Set Vref, RX VrefLevel [Byte0]: 61
3375 00:24:50.920245 [Byte1]: 61
3376 00:24:50.925190
3377 00:24:50.925262 Set Vref, RX VrefLevel [Byte0]: 62
3378 00:24:50.927983 [Byte1]: 62
3379 00:24:50.932813
3380 00:24:50.932926 Set Vref, RX VrefLevel [Byte0]: 63
3381 00:24:50.935960 [Byte1]: 63
3382 00:24:50.940729
3383 00:24:50.940833 Set Vref, RX VrefLevel [Byte0]: 64
3384 00:24:50.944002 [Byte1]: 64
3385 00:24:50.948874
3386 00:24:50.948947 Set Vref, RX VrefLevel [Byte0]: 65
3387 00:24:50.951741 [Byte1]: 65
3388 00:24:50.956387
3389 00:24:50.956456 Set Vref, RX VrefLevel [Byte0]: 66
3390 00:24:50.960117 [Byte1]: 66
3391 00:24:50.964229
3392 00:24:50.964303 Set Vref, RX VrefLevel [Byte0]: 67
3393 00:24:50.967539 [Byte1]: 67
3394 00:24:50.972181
3395 00:24:50.972251 Set Vref, RX VrefLevel [Byte0]: 68
3396 00:24:50.975576 [Byte1]: 68
3397 00:24:50.980511
3398 00:24:50.980606 Final RX Vref Byte 0 = 59 to rank0
3399 00:24:50.983894 Final RX Vref Byte 1 = 50 to rank0
3400 00:24:50.987081 Final RX Vref Byte 0 = 59 to rank1
3401 00:24:50.990059 Final RX Vref Byte 1 = 50 to rank1==
3402 00:24:50.993669 Dram Type= 6, Freq= 0, CH_1, rank 0
3403 00:24:50.996923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3404 00:24:51.000491 ==
3405 00:24:51.000565 DQS Delay:
3406 00:24:51.000628 DQS0 = 0, DQS1 = 0
3407 00:24:51.003904 DQM Delay:
3408 00:24:51.003985 DQM0 = 115, DQM1 = 108
3409 00:24:51.007027 DQ Delay:
3410 00:24:51.010352 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3411 00:24:51.013956 DQ4 =114, DQ5 =124, DQ6 =126, DQ7 =114
3412 00:24:51.017561 DQ8 =98, DQ9 =96, DQ10 =110, DQ11 =104
3413 00:24:51.020321 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =114
3414 00:24:51.020390
3415 00:24:51.020456
3416 00:24:51.027160 [DQSOSCAuto] RK0, (LSB)MR18= 0xe4, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
3417 00:24:51.030939 CH1 RK0: MR19=403, MR18=E4
3418 00:24:51.037839 CH1_RK0: MR19=0x403, MR18=0xE4, DQSOSC=410, MR23=63, INC=39, DEC=26
3419 00:24:51.037918
3420 00:24:51.040806 ----->DramcWriteLeveling(PI) begin...
3421 00:24:51.040875 ==
3422 00:24:51.044213 Dram Type= 6, Freq= 0, CH_1, rank 1
3423 00:24:51.047308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3424 00:24:51.047381 ==
3425 00:24:51.051028 Write leveling (Byte 0): 26 => 26
3426 00:24:51.054396 Write leveling (Byte 1): 31 => 31
3427 00:24:51.057569 DramcWriteLeveling(PI) end<-----
3428 00:24:51.057637
3429 00:24:51.057696 ==
3430 00:24:51.061083 Dram Type= 6, Freq= 0, CH_1, rank 1
3431 00:24:51.064599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3432 00:24:51.064733 ==
3433 00:24:51.067671 [Gating] SW mode calibration
3434 00:24:51.075087 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3435 00:24:51.081048 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3436 00:24:51.084733 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3437 00:24:51.088134 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 00:24:51.094715 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 00:24:51.098082 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 00:24:51.101503 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 00:24:51.107913 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 00:24:51.111631 0 15 24 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
3443 00:24:51.115087 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3444 00:24:51.118319 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 00:24:51.125126 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3446 00:24:51.128110 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 00:24:51.131322 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 00:24:51.138040 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 00:24:51.141343 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3450 00:24:51.144802 1 0 24 | B1->B0 | 2727 4141 | 0 0 | (0 0) (1 1)
3451 00:24:51.152228 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3452 00:24:51.155122 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 00:24:51.158414 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 00:24:51.165571 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 00:24:51.168387 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 00:24:51.171770 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 00:24:51.175476 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3458 00:24:51.182128 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3459 00:24:51.185616 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3460 00:24:51.188564 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 00:24:51.195628 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 00:24:51.198837 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 00:24:51.202379 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 00:24:51.208784 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 00:24:51.211981 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 00:24:51.215631 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 00:24:51.222362 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 00:24:51.225725 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 00:24:51.228601 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 00:24:51.235541 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 00:24:51.238914 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 00:24:51.241975 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 00:24:51.248713 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 00:24:51.252481 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3475 00:24:51.255547 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3476 00:24:51.258889 Total UI for P1: 0, mck2ui 16
3477 00:24:51.261989 best dqsien dly found for B0: ( 1, 3, 24)
3478 00:24:51.265753 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 00:24:51.268968 Total UI for P1: 0, mck2ui 16
3480 00:24:51.272834 best dqsien dly found for B1: ( 1, 3, 28)
3481 00:24:51.275777 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3482 00:24:51.278729 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3483 00:24:51.278807
3484 00:24:51.285246 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3485 00:24:51.288949 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3486 00:24:51.292363 [Gating] SW calibration Done
3487 00:24:51.292475 ==
3488 00:24:51.295586 Dram Type= 6, Freq= 0, CH_1, rank 1
3489 00:24:51.298628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3490 00:24:51.298703 ==
3491 00:24:51.298770 RX Vref Scan: 0
3492 00:24:51.298832
3493 00:24:51.302631 RX Vref 0 -> 0, step: 1
3494 00:24:51.302742
3495 00:24:51.305961 RX Delay -40 -> 252, step: 8
3496 00:24:51.309002 iDelay=192, Bit 0, Center 111 (40 ~ 183) 144
3497 00:24:51.312160 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3498 00:24:51.315507 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3499 00:24:51.322210 iDelay=192, Bit 3, Center 111 (40 ~ 183) 144
3500 00:24:51.325504 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3501 00:24:51.328761 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3502 00:24:51.332293 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3503 00:24:51.336111 iDelay=192, Bit 7, Center 107 (40 ~ 175) 136
3504 00:24:51.342221 iDelay=192, Bit 8, Center 95 (24 ~ 167) 144
3505 00:24:51.345938 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3506 00:24:51.349136 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3507 00:24:51.352200 iDelay=192, Bit 11, Center 99 (32 ~ 167) 136
3508 00:24:51.355637 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3509 00:24:51.362326 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3510 00:24:51.365625 iDelay=192, Bit 14, Center 115 (48 ~ 183) 136
3511 00:24:51.369262 iDelay=192, Bit 15, Center 115 (48 ~ 183) 136
3512 00:24:51.369360 ==
3513 00:24:51.372405 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 00:24:51.375542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 00:24:51.375614 ==
3516 00:24:51.379149 DQS Delay:
3517 00:24:51.379225 DQS0 = 0, DQS1 = 0
3518 00:24:51.382663 DQM Delay:
3519 00:24:51.382739 DQM0 = 112, DQM1 = 108
3520 00:24:51.382805 DQ Delay:
3521 00:24:51.385821 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =111
3522 00:24:51.389149 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =107
3523 00:24:51.395548 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3524 00:24:51.399189 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3525 00:24:51.399265
3526 00:24:51.399331
3527 00:24:51.399392 ==
3528 00:24:51.402653 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 00:24:51.405892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 00:24:51.405983 ==
3531 00:24:51.406047
3532 00:24:51.406105
3533 00:24:51.409682 TX Vref Scan disable
3534 00:24:51.409752 == TX Byte 0 ==
3535 00:24:51.415948 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3536 00:24:51.419195 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3537 00:24:51.419297 == TX Byte 1 ==
3538 00:24:51.425891 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3539 00:24:51.428972 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3540 00:24:51.429041 ==
3541 00:24:51.432432 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 00:24:51.435623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 00:24:51.435719 ==
3544 00:24:51.448631 TX Vref=22, minBit 0, minWin=25, winSum=416
3545 00:24:51.452072 TX Vref=24, minBit 3, minWin=25, winSum=424
3546 00:24:51.455444 TX Vref=26, minBit 0, minWin=25, winSum=422
3547 00:24:51.458664 TX Vref=28, minBit 1, minWin=26, winSum=430
3548 00:24:51.461819 TX Vref=30, minBit 5, minWin=26, winSum=434
3549 00:24:51.465771 TX Vref=32, minBit 5, minWin=26, winSum=432
3550 00:24:51.471903 [TxChooseVref] Worse bit 5, Min win 26, Win sum 434, Final Vref 30
3551 00:24:51.472005
3552 00:24:51.475733 Final TX Range 1 Vref 30
3553 00:24:51.475830
3554 00:24:51.475918 ==
3555 00:24:51.479022 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 00:24:51.481964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 00:24:51.482035 ==
3558 00:24:51.482098
3559 00:24:51.485278
3560 00:24:51.485378 TX Vref Scan disable
3561 00:24:51.488545 == TX Byte 0 ==
3562 00:24:51.492090 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3563 00:24:51.495423 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3564 00:24:51.498678 == TX Byte 1 ==
3565 00:24:51.501896 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3566 00:24:51.506136 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3567 00:24:51.506237
3568 00:24:51.508627 [DATLAT]
3569 00:24:51.508743 Freq=1200, CH1 RK1
3570 00:24:51.508806
3571 00:24:51.512372 DATLAT Default: 0xd
3572 00:24:51.512479 0, 0xFFFF, sum = 0
3573 00:24:51.515939 1, 0xFFFF, sum = 0
3574 00:24:51.516069 2, 0xFFFF, sum = 0
3575 00:24:51.518633 3, 0xFFFF, sum = 0
3576 00:24:51.518710 4, 0xFFFF, sum = 0
3577 00:24:51.521869 5, 0xFFFF, sum = 0
3578 00:24:51.521947 6, 0xFFFF, sum = 0
3579 00:24:51.525162 7, 0xFFFF, sum = 0
3580 00:24:51.528604 8, 0xFFFF, sum = 0
3581 00:24:51.528727 9, 0xFFFF, sum = 0
3582 00:24:51.532064 10, 0xFFFF, sum = 0
3583 00:24:51.532165 11, 0xFFFF, sum = 0
3584 00:24:51.535517 12, 0x0, sum = 1
3585 00:24:51.535599 13, 0x0, sum = 2
3586 00:24:51.538845 14, 0x0, sum = 3
3587 00:24:51.538927 15, 0x0, sum = 4
3588 00:24:51.538991 best_step = 13
3589 00:24:51.539049
3590 00:24:51.542033 ==
3591 00:24:51.542113 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 00:24:51.548960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 00:24:51.549067 ==
3594 00:24:51.549160 RX Vref Scan: 0
3595 00:24:51.549258
3596 00:24:51.552199 RX Vref 0 -> 0, step: 1
3597 00:24:51.552277
3598 00:24:51.555870 RX Delay -21 -> 252, step: 4
3599 00:24:51.558958 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3600 00:24:51.562287 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3601 00:24:51.568881 iDelay=191, Bit 2, Center 106 (43 ~ 170) 128
3602 00:24:51.572281 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3603 00:24:51.575913 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3604 00:24:51.578811 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3605 00:24:51.582473 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3606 00:24:51.589003 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3607 00:24:51.592384 iDelay=191, Bit 8, Center 98 (35 ~ 162) 128
3608 00:24:51.595733 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3609 00:24:51.599220 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3610 00:24:51.602333 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3611 00:24:51.605558 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3612 00:24:51.612451 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3613 00:24:51.615900 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3614 00:24:51.619326 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3615 00:24:51.619437 ==
3616 00:24:51.622531 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 00:24:51.625757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 00:24:51.629388 ==
3619 00:24:51.629471 DQS Delay:
3620 00:24:51.629552 DQS0 = 0, DQS1 = 0
3621 00:24:51.632425 DQM Delay:
3622 00:24:51.632538 DQM0 = 113, DQM1 = 109
3623 00:24:51.635609 DQ Delay:
3624 00:24:51.639016 DQ0 =112, DQ1 =108, DQ2 =106, DQ3 =112
3625 00:24:51.642715 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3626 00:24:51.646038 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =100
3627 00:24:51.649147 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =116
3628 00:24:51.649253
3629 00:24:51.649344
3630 00:24:51.656082 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3631 00:24:51.659255 CH1 RK1: MR19=303, MR18=F7FE
3632 00:24:51.666042 CH1_RK1: MR19=0x303, MR18=0xF7FE, DQSOSC=410, MR23=63, INC=39, DEC=26
3633 00:24:51.669105 [RxdqsGatingPostProcess] freq 1200
3634 00:24:51.672789 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3635 00:24:51.676209 best DQS0 dly(2T, 0.5T) = (0, 11)
3636 00:24:51.679526 best DQS1 dly(2T, 0.5T) = (0, 11)
3637 00:24:51.682759 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3638 00:24:51.686200 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3639 00:24:51.689185 best DQS0 dly(2T, 0.5T) = (0, 11)
3640 00:24:51.692556 best DQS1 dly(2T, 0.5T) = (0, 11)
3641 00:24:51.696285 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3642 00:24:51.699216 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3643 00:24:51.702849 Pre-setting of DQS Precalculation
3644 00:24:51.705890 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3645 00:24:51.716078 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3646 00:24:51.722586 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3647 00:24:51.722669
3648 00:24:51.722734
3649 00:24:51.726029 [Calibration Summary] 2400 Mbps
3650 00:24:51.726112 CH 0, Rank 0
3651 00:24:51.729414 SW Impedance : PASS
3652 00:24:51.729496 DUTY Scan : NO K
3653 00:24:51.732583 ZQ Calibration : PASS
3654 00:24:51.735983 Jitter Meter : NO K
3655 00:24:51.736067 CBT Training : PASS
3656 00:24:51.739460 Write leveling : PASS
3657 00:24:51.742876 RX DQS gating : PASS
3658 00:24:51.742959 RX DQ/DQS(RDDQC) : PASS
3659 00:24:51.746297 TX DQ/DQS : PASS
3660 00:24:51.749297 RX DATLAT : PASS
3661 00:24:51.749379 RX DQ/DQS(Engine): PASS
3662 00:24:51.752595 TX OE : NO K
3663 00:24:51.752688 All Pass.
3664 00:24:51.752755
3665 00:24:51.756193 CH 0, Rank 1
3666 00:24:51.756275 SW Impedance : PASS
3667 00:24:51.759283 DUTY Scan : NO K
3668 00:24:51.759366 ZQ Calibration : PASS
3669 00:24:51.763052 Jitter Meter : NO K
3670 00:24:51.766449 CBT Training : PASS
3671 00:24:51.766531 Write leveling : PASS
3672 00:24:51.769494 RX DQS gating : PASS
3673 00:24:51.772817 RX DQ/DQS(RDDQC) : PASS
3674 00:24:51.772899 TX DQ/DQS : PASS
3675 00:24:51.776086 RX DATLAT : PASS
3676 00:24:51.779502 RX DQ/DQS(Engine): PASS
3677 00:24:51.779580 TX OE : NO K
3678 00:24:51.783192 All Pass.
3679 00:24:51.783274
3680 00:24:51.783337 CH 1, Rank 0
3681 00:24:51.785988 SW Impedance : PASS
3682 00:24:51.786069 DUTY Scan : NO K
3683 00:24:51.789310 ZQ Calibration : PASS
3684 00:24:51.792980 Jitter Meter : NO K
3685 00:24:51.793062 CBT Training : PASS
3686 00:24:51.795981 Write leveling : PASS
3687 00:24:51.799302 RX DQS gating : PASS
3688 00:24:51.799385 RX DQ/DQS(RDDQC) : PASS
3689 00:24:51.802730 TX DQ/DQS : PASS
3690 00:24:51.802813 RX DATLAT : PASS
3691 00:24:51.806305 RX DQ/DQS(Engine): PASS
3692 00:24:51.809296 TX OE : NO K
3693 00:24:51.809379 All Pass.
3694 00:24:51.809444
3695 00:24:51.809505 CH 1, Rank 1
3696 00:24:51.813281 SW Impedance : PASS
3697 00:24:51.816485 DUTY Scan : NO K
3698 00:24:51.816568 ZQ Calibration : PASS
3699 00:24:51.819312 Jitter Meter : NO K
3700 00:24:51.823067 CBT Training : PASS
3701 00:24:51.823172 Write leveling : PASS
3702 00:24:51.826022 RX DQS gating : PASS
3703 00:24:51.829820 RX DQ/DQS(RDDQC) : PASS
3704 00:24:51.829896 TX DQ/DQS : PASS
3705 00:24:51.832949 RX DATLAT : PASS
3706 00:24:51.833026 RX DQ/DQS(Engine): PASS
3707 00:24:51.836548 TX OE : NO K
3708 00:24:51.836652 All Pass.
3709 00:24:51.836750
3710 00:24:51.839439 DramC Write-DBI off
3711 00:24:51.842804 PER_BANK_REFRESH: Hybrid Mode
3712 00:24:51.842881 TX_TRACKING: ON
3713 00:24:51.853386 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3714 00:24:51.856094 [FAST_K] Save calibration result to emmc
3715 00:24:51.859732 dramc_set_vcore_voltage set vcore to 650000
3716 00:24:51.863170 Read voltage for 600, 5
3717 00:24:51.863284 Vio18 = 0
3718 00:24:51.866590 Vcore = 650000
3719 00:24:51.866671 Vdram = 0
3720 00:24:51.866770 Vddq = 0
3721 00:24:51.866862 Vmddr = 0
3722 00:24:51.873120 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3723 00:24:51.876362 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3724 00:24:51.879627 MEM_TYPE=3, freq_sel=19
3725 00:24:51.882785 sv_algorithm_assistance_LP4_1600
3726 00:24:51.886721 ============ PULL DRAM RESETB DOWN ============
3727 00:24:51.889768 ========== PULL DRAM RESETB DOWN end =========
3728 00:24:51.896707 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3729 00:24:51.899613 ===================================
3730 00:24:51.903313 LPDDR4 DRAM CONFIGURATION
3731 00:24:51.906945 ===================================
3732 00:24:51.907021 EX_ROW_EN[0] = 0x0
3733 00:24:51.909681 EX_ROW_EN[1] = 0x0
3734 00:24:51.909751 LP4Y_EN = 0x0
3735 00:24:51.913444 WORK_FSP = 0x0
3736 00:24:51.913515 WL = 0x2
3737 00:24:51.916367 RL = 0x2
3738 00:24:51.916439 BL = 0x2
3739 00:24:51.919719 RPST = 0x0
3740 00:24:51.919809 RD_PRE = 0x0
3741 00:24:51.923439 WR_PRE = 0x1
3742 00:24:51.923514 WR_PST = 0x0
3743 00:24:51.926496 DBI_WR = 0x0
3744 00:24:51.926574 DBI_RD = 0x0
3745 00:24:51.929974 OTF = 0x1
3746 00:24:51.933203 ===================================
3747 00:24:51.936738 ===================================
3748 00:24:51.936829 ANA top config
3749 00:24:51.940046 ===================================
3750 00:24:51.943322 DLL_ASYNC_EN = 0
3751 00:24:51.946755 ALL_SLAVE_EN = 1
3752 00:24:51.949824 NEW_RANK_MODE = 1
3753 00:24:51.949921 DLL_IDLE_MODE = 1
3754 00:24:51.953488 LP45_APHY_COMB_EN = 1
3755 00:24:51.956786 TX_ODT_DIS = 1
3756 00:24:51.960163 NEW_8X_MODE = 1
3757 00:24:51.963233 ===================================
3758 00:24:51.966699 ===================================
3759 00:24:51.969977 data_rate = 1200
3760 00:24:51.970056 CKR = 1
3761 00:24:51.973213 DQ_P2S_RATIO = 8
3762 00:24:51.976725 ===================================
3763 00:24:51.980048 CA_P2S_RATIO = 8
3764 00:24:51.983789 DQ_CA_OPEN = 0
3765 00:24:51.986510 DQ_SEMI_OPEN = 0
3766 00:24:51.986597 CA_SEMI_OPEN = 0
3767 00:24:51.990135 CA_FULL_RATE = 0
3768 00:24:51.993397 DQ_CKDIV4_EN = 1
3769 00:24:51.996553 CA_CKDIV4_EN = 1
3770 00:24:52.000281 CA_PREDIV_EN = 0
3771 00:24:52.003672 PH8_DLY = 0
3772 00:24:52.003753 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3773 00:24:52.006810 DQ_AAMCK_DIV = 4
3774 00:24:52.009885 CA_AAMCK_DIV = 4
3775 00:24:52.013696 CA_ADMCK_DIV = 4
3776 00:24:52.016836 DQ_TRACK_CA_EN = 0
3777 00:24:52.020107 CA_PICK = 600
3778 00:24:52.020193 CA_MCKIO = 600
3779 00:24:52.023690 MCKIO_SEMI = 0
3780 00:24:52.027432 PLL_FREQ = 2288
3781 00:24:52.030644 DQ_UI_PI_RATIO = 32
3782 00:24:52.033512 CA_UI_PI_RATIO = 0
3783 00:24:52.037120 ===================================
3784 00:24:52.040389 ===================================
3785 00:24:52.043709 memory_type:LPDDR4
3786 00:24:52.043793 GP_NUM : 10
3787 00:24:52.047433 SRAM_EN : 1
3788 00:24:52.047503 MD32_EN : 0
3789 00:24:52.050871 ===================================
3790 00:24:52.053514 [ANA_INIT] >>>>>>>>>>>>>>
3791 00:24:52.057410 <<<<<< [CONFIGURE PHASE]: ANA_TX
3792 00:24:52.060549 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3793 00:24:52.063633 ===================================
3794 00:24:52.067283 data_rate = 1200,PCW = 0X5800
3795 00:24:52.070598 ===================================
3796 00:24:52.073902 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3797 00:24:52.077018 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3798 00:24:52.083697 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3799 00:24:52.086972 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3800 00:24:52.090286 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3801 00:24:52.093459 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3802 00:24:52.096938 [ANA_INIT] flow start
3803 00:24:52.100243 [ANA_INIT] PLL >>>>>>>>
3804 00:24:52.100335 [ANA_INIT] PLL <<<<<<<<
3805 00:24:52.103831 [ANA_INIT] MIDPI >>>>>>>>
3806 00:24:52.106829 [ANA_INIT] MIDPI <<<<<<<<
3807 00:24:52.110190 [ANA_INIT] DLL >>>>>>>>
3808 00:24:52.110265 [ANA_INIT] flow end
3809 00:24:52.113458 ============ LP4 DIFF to SE enter ============
3810 00:24:52.120049 ============ LP4 DIFF to SE exit ============
3811 00:24:52.120131 [ANA_INIT] <<<<<<<<<<<<<
3812 00:24:52.123803 [Flow] Enable top DCM control >>>>>
3813 00:24:52.126897 [Flow] Enable top DCM control <<<<<
3814 00:24:52.130370 Enable DLL master slave shuffle
3815 00:24:52.137009 ==============================================================
3816 00:24:52.137088 Gating Mode config
3817 00:24:52.143775 ==============================================================
3818 00:24:52.146902 Config description:
3819 00:24:52.154342 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3820 00:24:52.160837 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3821 00:24:52.167401 SELPH_MODE 0: By rank 1: By Phase
3822 00:24:52.174275 ==============================================================
3823 00:24:52.174356 GAT_TRACK_EN = 1
3824 00:24:52.177204 RX_GATING_MODE = 2
3825 00:24:52.180623 RX_GATING_TRACK_MODE = 2
3826 00:24:52.183820 SELPH_MODE = 1
3827 00:24:52.187241 PICG_EARLY_EN = 1
3828 00:24:52.190672 VALID_LAT_VALUE = 1
3829 00:24:52.197385 ==============================================================
3830 00:24:52.200485 Enter into Gating configuration >>>>
3831 00:24:52.204059 Exit from Gating configuration <<<<
3832 00:24:52.204138 Enter into DVFS_PRE_config >>>>>
3833 00:24:52.217926 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3834 00:24:52.220903 Exit from DVFS_PRE_config <<<<<
3835 00:24:52.224155 Enter into PICG configuration >>>>
3836 00:24:52.227194 Exit from PICG configuration <<<<
3837 00:24:52.227282 [RX_INPUT] configuration >>>>>
3838 00:24:52.230407 [RX_INPUT] configuration <<<<<
3839 00:24:52.237447 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3840 00:24:52.240510 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3841 00:24:52.247366 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3842 00:24:52.254012 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3843 00:24:52.260841 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3844 00:24:52.267146 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3845 00:24:52.270809 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3846 00:24:52.273885 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3847 00:24:52.277531 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3848 00:24:52.283997 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3849 00:24:52.287501 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3850 00:24:52.290648 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3851 00:24:52.293837 ===================================
3852 00:24:52.297614 LPDDR4 DRAM CONFIGURATION
3853 00:24:52.300890 ===================================
3854 00:24:52.304068 EX_ROW_EN[0] = 0x0
3855 00:24:52.304146 EX_ROW_EN[1] = 0x0
3856 00:24:52.307333 LP4Y_EN = 0x0
3857 00:24:52.307411 WORK_FSP = 0x0
3858 00:24:52.311014 WL = 0x2
3859 00:24:52.311091 RL = 0x2
3860 00:24:52.314107 BL = 0x2
3861 00:24:52.314190 RPST = 0x0
3862 00:24:52.317413 RD_PRE = 0x0
3863 00:24:52.317491 WR_PRE = 0x1
3864 00:24:52.320749 WR_PST = 0x0
3865 00:24:52.320838 DBI_WR = 0x0
3866 00:24:52.324089 DBI_RD = 0x0
3867 00:24:52.324164 OTF = 0x1
3868 00:24:52.327306 ===================================
3869 00:24:52.330991 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3870 00:24:52.337645 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3871 00:24:52.341092 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3872 00:24:52.344147 ===================================
3873 00:24:52.347794 LPDDR4 DRAM CONFIGURATION
3874 00:24:52.350887 ===================================
3875 00:24:52.350960 EX_ROW_EN[0] = 0x10
3876 00:24:52.354041 EX_ROW_EN[1] = 0x0
3877 00:24:52.357790 LP4Y_EN = 0x0
3878 00:24:52.357907 WORK_FSP = 0x0
3879 00:24:52.360947 WL = 0x2
3880 00:24:52.361020 RL = 0x2
3881 00:24:52.364286 BL = 0x2
3882 00:24:52.364389 RPST = 0x0
3883 00:24:52.367636 RD_PRE = 0x0
3884 00:24:52.367708 WR_PRE = 0x1
3885 00:24:52.371256 WR_PST = 0x0
3886 00:24:52.371327 DBI_WR = 0x0
3887 00:24:52.374541 DBI_RD = 0x0
3888 00:24:52.374617 OTF = 0x1
3889 00:24:52.377908 ===================================
3890 00:24:52.384235 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3891 00:24:52.388383 nWR fixed to 30
3892 00:24:52.391680 [ModeRegInit_LP4] CH0 RK0
3893 00:24:52.391788 [ModeRegInit_LP4] CH0 RK1
3894 00:24:52.395132 [ModeRegInit_LP4] CH1 RK0
3895 00:24:52.399016 [ModeRegInit_LP4] CH1 RK1
3896 00:24:52.399091 match AC timing 17
3897 00:24:52.405160 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3898 00:24:52.408207 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3899 00:24:52.411422 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3900 00:24:52.418288 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3901 00:24:52.422146 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3902 00:24:52.422223 ==
3903 00:24:52.425394 Dram Type= 6, Freq= 0, CH_0, rank 0
3904 00:24:52.428371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3905 00:24:52.428445 ==
3906 00:24:52.435288 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3907 00:24:52.441590 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3908 00:24:52.444900 [CA 0] Center 36 (6~66) winsize 61
3909 00:24:52.448464 [CA 1] Center 36 (6~66) winsize 61
3910 00:24:52.451970 [CA 2] Center 34 (4~65) winsize 62
3911 00:24:52.455128 [CA 3] Center 34 (4~65) winsize 62
3912 00:24:52.458367 [CA 4] Center 34 (4~64) winsize 61
3913 00:24:52.461722 [CA 5] Center 33 (3~64) winsize 62
3914 00:24:52.461795
3915 00:24:52.465476 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3916 00:24:52.465548
3917 00:24:52.468276 [CATrainingPosCal] consider 1 rank data
3918 00:24:52.471813 u2DelayCellTimex100 = 270/100 ps
3919 00:24:52.475053 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3920 00:24:52.478412 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3921 00:24:52.481969 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3922 00:24:52.485648 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3923 00:24:52.488419 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3924 00:24:52.491674 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3925 00:24:52.491753
3926 00:24:52.495369 CA PerBit enable=1, Macro0, CA PI delay=33
3927 00:24:52.495449
3928 00:24:52.498847 [CBTSetCACLKResult] CA Dly = 33
3929 00:24:52.501910 CS Dly: 4 (0~35)
3930 00:24:52.501989 ==
3931 00:24:52.505417 Dram Type= 6, Freq= 0, CH_0, rank 1
3932 00:24:52.508690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3933 00:24:52.508799 ==
3934 00:24:52.515257 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3935 00:24:52.522306 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3936 00:24:52.525246 [CA 0] Center 36 (6~66) winsize 61
3937 00:24:52.528806 [CA 1] Center 36 (6~66) winsize 61
3938 00:24:52.532347 [CA 2] Center 34 (4~65) winsize 62
3939 00:24:52.535360 [CA 3] Center 34 (4~65) winsize 62
3940 00:24:52.538625 [CA 4] Center 33 (3~64) winsize 62
3941 00:24:52.542155 [CA 5] Center 33 (3~64) winsize 62
3942 00:24:52.542235
3943 00:24:52.545573 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3944 00:24:52.545653
3945 00:24:52.549299 [CATrainingPosCal] consider 2 rank data
3946 00:24:52.552446 u2DelayCellTimex100 = 270/100 ps
3947 00:24:52.555750 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3948 00:24:52.558750 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3949 00:24:52.562231 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3950 00:24:52.566040 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3951 00:24:52.568984 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3952 00:24:52.572347 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3953 00:24:52.572427
3954 00:24:52.575543 CA PerBit enable=1, Macro0, CA PI delay=33
3955 00:24:52.575623
3956 00:24:52.579217 [CBTSetCACLKResult] CA Dly = 33
3957 00:24:52.582111 CS Dly: 4 (0~36)
3958 00:24:52.582191
3959 00:24:52.585628 ----->DramcWriteLeveling(PI) begin...
3960 00:24:52.585709 ==
3961 00:24:52.589140 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 00:24:52.592205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3963 00:24:52.592286 ==
3964 00:24:52.595945 Write leveling (Byte 0): 32 => 32
3965 00:24:52.598845 Write leveling (Byte 1): 30 => 30
3966 00:24:52.602039 DramcWriteLeveling(PI) end<-----
3967 00:24:52.602119
3968 00:24:52.602181 ==
3969 00:24:52.605211 Dram Type= 6, Freq= 0, CH_0, rank 0
3970 00:24:52.608844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 00:24:52.608965 ==
3972 00:24:52.612216 [Gating] SW mode calibration
3973 00:24:52.618796 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3974 00:24:52.625863 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3975 00:24:52.628605 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 00:24:52.632106 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 00:24:52.638658 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 00:24:52.642209 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3979 00:24:52.646108 0 9 16 | B1->B0 | 3131 2a2a | 0 0 | (1 0) (1 1)
3980 00:24:52.652102 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 00:24:52.655550 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 00:24:52.659022 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 00:24:52.665832 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 00:24:52.669015 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 00:24:52.672522 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 00:24:52.679500 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3987 00:24:52.682896 0 10 16 | B1->B0 | 2929 3a3a | 0 1 | (0 0) (0 0)
3988 00:24:52.685625 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 00:24:52.688962 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 00:24:52.695830 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 00:24:52.699246 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 00:24:52.702809 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 00:24:52.709173 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 00:24:52.712702 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 00:24:52.715882 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3996 00:24:52.722738 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 00:24:52.726201 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 00:24:52.729023 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 00:24:52.735946 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 00:24:52.739097 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 00:24:52.742545 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 00:24:52.749097 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 00:24:52.752611 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 00:24:52.755953 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 00:24:52.762586 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 00:24:52.765833 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 00:24:52.769179 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 00:24:52.772873 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 00:24:52.779788 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 00:24:52.782826 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 00:24:52.786373 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4012 00:24:52.789603 Total UI for P1: 0, mck2ui 16
4013 00:24:52.792662 best dqsien dly found for B0: ( 0, 13, 14)
4014 00:24:52.799567 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 00:24:52.799649 Total UI for P1: 0, mck2ui 16
4016 00:24:52.805987 best dqsien dly found for B1: ( 0, 13, 16)
4017 00:24:52.809480 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4018 00:24:52.812818 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4019 00:24:52.812900
4020 00:24:52.816483 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4021 00:24:52.819389 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4022 00:24:52.822729 [Gating] SW calibration Done
4023 00:24:52.822815 ==
4024 00:24:52.826083 Dram Type= 6, Freq= 0, CH_0, rank 0
4025 00:24:52.829731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4026 00:24:52.829815 ==
4027 00:24:52.832820 RX Vref Scan: 0
4028 00:24:52.832903
4029 00:24:52.832968 RX Vref 0 -> 0, step: 1
4030 00:24:52.833028
4031 00:24:52.836123 RX Delay -230 -> 252, step: 16
4032 00:24:52.843080 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4033 00:24:52.846416 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4034 00:24:52.849655 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4035 00:24:52.853273 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4036 00:24:52.856168 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4037 00:24:52.863164 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4038 00:24:52.866525 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4039 00:24:52.869839 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4040 00:24:52.873070 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4041 00:24:52.876489 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4042 00:24:52.883149 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4043 00:24:52.886271 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4044 00:24:52.889984 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4045 00:24:52.892857 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4046 00:24:52.900088 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4047 00:24:52.903160 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4048 00:24:52.903241 ==
4049 00:24:52.906660 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 00:24:52.909919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 00:24:52.910018 ==
4052 00:24:52.912897 DQS Delay:
4053 00:24:52.912979 DQS0 = 0, DQS1 = 0
4054 00:24:52.913045 DQM Delay:
4055 00:24:52.916676 DQM0 = 41, DQM1 = 33
4056 00:24:52.916788 DQ Delay:
4057 00:24:52.920083 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4058 00:24:52.924115 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4059 00:24:52.926708 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4060 00:24:52.929854 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =49
4061 00:24:52.929935
4062 00:24:52.929997
4063 00:24:52.930090 ==
4064 00:24:52.932952 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 00:24:52.939984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 00:24:52.940090 ==
4067 00:24:52.940156
4068 00:24:52.940217
4069 00:24:52.940275 TX Vref Scan disable
4070 00:24:52.943090 == TX Byte 0 ==
4071 00:24:52.946580 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4072 00:24:52.952869 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4073 00:24:52.952950 == TX Byte 1 ==
4074 00:24:52.956364 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4075 00:24:52.963171 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4076 00:24:52.963252 ==
4077 00:24:52.966269 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 00:24:52.969652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 00:24:52.969733 ==
4080 00:24:52.969797
4081 00:24:52.969856
4082 00:24:52.973152 TX Vref Scan disable
4083 00:24:52.976659 == TX Byte 0 ==
4084 00:24:52.979620 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4085 00:24:52.982862 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4086 00:24:52.986653 == TX Byte 1 ==
4087 00:24:52.989601 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4088 00:24:52.992852 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4089 00:24:52.992935
4090 00:24:52.993000 [DATLAT]
4091 00:24:52.996523 Freq=600, CH0 RK0
4092 00:24:52.996605
4093 00:24:52.996676 DATLAT Default: 0x9
4094 00:24:52.999527 0, 0xFFFF, sum = 0
4095 00:24:52.999609 1, 0xFFFF, sum = 0
4096 00:24:53.003243 2, 0xFFFF, sum = 0
4097 00:24:53.003325 3, 0xFFFF, sum = 0
4098 00:24:53.006354 4, 0xFFFF, sum = 0
4099 00:24:53.009752 5, 0xFFFF, sum = 0
4100 00:24:53.009834 6, 0xFFFF, sum = 0
4101 00:24:53.013140 7, 0xFFFF, sum = 0
4102 00:24:53.013222 8, 0x0, sum = 1
4103 00:24:53.013286 9, 0x0, sum = 2
4104 00:24:53.016605 10, 0x0, sum = 3
4105 00:24:53.016711 11, 0x0, sum = 4
4106 00:24:53.019974 best_step = 9
4107 00:24:53.020054
4108 00:24:53.020117 ==
4109 00:24:53.023207 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 00:24:53.026634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 00:24:53.026715 ==
4112 00:24:53.029628 RX Vref Scan: 1
4113 00:24:53.029708
4114 00:24:53.029771 RX Vref 0 -> 0, step: 1
4115 00:24:53.029831
4116 00:24:53.033058 RX Delay -195 -> 252, step: 8
4117 00:24:53.033139
4118 00:24:53.036441 Set Vref, RX VrefLevel [Byte0]: 52
4119 00:24:53.039914 [Byte1]: 50
4120 00:24:53.043925
4121 00:24:53.044006 Final RX Vref Byte 0 = 52 to rank0
4122 00:24:53.046815 Final RX Vref Byte 1 = 50 to rank0
4123 00:24:53.050478 Final RX Vref Byte 0 = 52 to rank1
4124 00:24:53.053730 Final RX Vref Byte 1 = 50 to rank1==
4125 00:24:53.057348 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 00:24:53.064072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 00:24:53.064168 ==
4128 00:24:53.064232 DQS Delay:
4129 00:24:53.064291 DQS0 = 0, DQS1 = 0
4130 00:24:53.067127 DQM Delay:
4131 00:24:53.067225 DQM0 = 42, DQM1 = 33
4132 00:24:53.070552 DQ Delay:
4133 00:24:53.073943 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4134 00:24:53.074024 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4135 00:24:53.077487 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4136 00:24:53.080577 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4137 00:24:53.083757
4138 00:24:53.083849
4139 00:24:53.090667 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f1e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps
4140 00:24:53.093953 CH0 RK0: MR19=808, MR18=3F1E
4141 00:24:53.100300 CH0_RK0: MR19=0x808, MR18=0x3F1E, DQSOSC=397, MR23=63, INC=166, DEC=110
4142 00:24:53.100384
4143 00:24:53.104204 ----->DramcWriteLeveling(PI) begin...
4144 00:24:53.104326 ==
4145 00:24:53.107569 Dram Type= 6, Freq= 0, CH_0, rank 1
4146 00:24:53.110369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 00:24:53.110476 ==
4148 00:24:53.113655 Write leveling (Byte 0): 31 => 31
4149 00:24:53.117126 Write leveling (Byte 1): 30 => 30
4150 00:24:53.121046 DramcWriteLeveling(PI) end<-----
4151 00:24:53.121128
4152 00:24:53.121190 ==
4153 00:24:53.123691 Dram Type= 6, Freq= 0, CH_0, rank 1
4154 00:24:53.127473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 00:24:53.127558 ==
4156 00:24:53.130284 [Gating] SW mode calibration
4157 00:24:53.137604 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4158 00:24:53.143889 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4159 00:24:53.147536 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 00:24:53.150654 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 00:24:53.157272 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 00:24:53.160717 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
4163 00:24:53.163739 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4164 00:24:53.170462 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 00:24:53.173929 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 00:24:53.177239 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 00:24:53.183891 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 00:24:53.187809 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 00:24:53.190546 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 00:24:53.194200 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
4171 00:24:53.200672 0 10 16 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
4172 00:24:53.204281 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 00:24:53.207350 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 00:24:53.213962 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 00:24:53.217883 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 00:24:53.220831 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 00:24:53.227560 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 00:24:53.230718 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4179 00:24:53.234104 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4180 00:24:53.240849 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 00:24:53.244484 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 00:24:53.247619 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 00:24:53.251684 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 00:24:53.257699 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 00:24:53.261199 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 00:24:53.264179 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 00:24:53.270665 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 00:24:53.274240 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 00:24:53.277723 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 00:24:53.284128 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 00:24:53.287763 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 00:24:53.291407 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 00:24:53.297585 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4194 00:24:53.301244 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4195 00:24:53.304733 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4196 00:24:53.307812 Total UI for P1: 0, mck2ui 16
4197 00:24:53.311061 best dqsien dly found for B0: ( 0, 13, 10)
4198 00:24:53.318367 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 00:24:53.318455 Total UI for P1: 0, mck2ui 16
4200 00:24:53.321195 best dqsien dly found for B1: ( 0, 13, 14)
4201 00:24:53.328097 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4202 00:24:53.331708 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4203 00:24:53.331797
4204 00:24:53.334595 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4205 00:24:53.338142 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4206 00:24:53.341173 [Gating] SW calibration Done
4207 00:24:53.341255 ==
4208 00:24:53.344648 Dram Type= 6, Freq= 0, CH_0, rank 1
4209 00:24:53.347788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 00:24:53.347887 ==
4211 00:24:53.351538 RX Vref Scan: 0
4212 00:24:53.351698
4213 00:24:53.351780 RX Vref 0 -> 0, step: 1
4214 00:24:53.351865
4215 00:24:53.354569 RX Delay -230 -> 252, step: 16
4216 00:24:53.358072 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4217 00:24:53.364587 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4218 00:24:53.367666 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4219 00:24:53.371413 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4220 00:24:53.374722 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4221 00:24:53.377785 iDelay=218, Bit 5, Center 33 (-118 ~ 185) 304
4222 00:24:53.384915 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4223 00:24:53.388168 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4224 00:24:53.391215 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4225 00:24:53.394714 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4226 00:24:53.401526 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4227 00:24:53.404522 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4228 00:24:53.408353 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4229 00:24:53.411242 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4230 00:24:53.414676 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4231 00:24:53.421265 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4232 00:24:53.421345 ==
4233 00:24:53.424535 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 00:24:53.428242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 00:24:53.428334 ==
4236 00:24:53.428403 DQS Delay:
4237 00:24:53.431845 DQS0 = 0, DQS1 = 0
4238 00:24:53.431921 DQM Delay:
4239 00:24:53.434651 DQM0 = 42, DQM1 = 33
4240 00:24:53.434717 DQ Delay:
4241 00:24:53.437993 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4242 00:24:53.441125 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4243 00:24:53.444995 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4244 00:24:53.448098 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4245 00:24:53.448169
4246 00:24:53.448231
4247 00:24:53.448297 ==
4248 00:24:53.451330 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 00:24:53.454486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 00:24:53.458231 ==
4251 00:24:53.458314
4252 00:24:53.458381
4253 00:24:53.458440 TX Vref Scan disable
4254 00:24:53.461637 == TX Byte 0 ==
4255 00:24:53.464600 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4256 00:24:53.468121 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4257 00:24:53.471471 == TX Byte 1 ==
4258 00:24:53.474656 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4259 00:24:53.478564 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4260 00:24:53.478638 ==
4261 00:24:53.481693 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 00:24:53.488082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 00:24:53.488169 ==
4264 00:24:53.488253
4265 00:24:53.488314
4266 00:24:53.488379 TX Vref Scan disable
4267 00:24:53.492998 == TX Byte 0 ==
4268 00:24:53.496080 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4269 00:24:53.499845 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4270 00:24:53.502941 == TX Byte 1 ==
4271 00:24:53.506725 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4272 00:24:53.509878 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4273 00:24:53.509952
4274 00:24:53.512702 [DATLAT]
4275 00:24:53.512779 Freq=600, CH0 RK1
4276 00:24:53.512840
4277 00:24:53.516068 DATLAT Default: 0x9
4278 00:24:53.516133 0, 0xFFFF, sum = 0
4279 00:24:53.519637 1, 0xFFFF, sum = 0
4280 00:24:53.519706 2, 0xFFFF, sum = 0
4281 00:24:53.522781 3, 0xFFFF, sum = 0
4282 00:24:53.522865 4, 0xFFFF, sum = 0
4283 00:24:53.526490 5, 0xFFFF, sum = 0
4284 00:24:53.526577 6, 0xFFFF, sum = 0
4285 00:24:53.529363 7, 0xFFFF, sum = 0
4286 00:24:53.529441 8, 0x0, sum = 1
4287 00:24:53.533192 9, 0x0, sum = 2
4288 00:24:53.533263 10, 0x0, sum = 3
4289 00:24:53.536359 11, 0x0, sum = 4
4290 00:24:53.536432 best_step = 9
4291 00:24:53.536490
4292 00:24:53.536546 ==
4293 00:24:53.539966 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 00:24:53.546226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 00:24:53.546342 ==
4296 00:24:53.546407 RX Vref Scan: 0
4297 00:24:53.546466
4298 00:24:53.549561 RX Vref 0 -> 0, step: 1
4299 00:24:53.549641
4300 00:24:53.553023 RX Delay -195 -> 252, step: 8
4301 00:24:53.556553 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4302 00:24:53.563114 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4303 00:24:53.566349 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4304 00:24:53.569660 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4305 00:24:53.572819 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4306 00:24:53.576166 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4307 00:24:53.583161 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4308 00:24:53.586544 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4309 00:24:53.589522 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4310 00:24:53.593062 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4311 00:24:53.596498 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4312 00:24:53.602979 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4313 00:24:53.606184 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4314 00:24:53.609500 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4315 00:24:53.613025 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4316 00:24:53.620028 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4317 00:24:53.620108 ==
4318 00:24:53.623249 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 00:24:53.626530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 00:24:53.626611 ==
4321 00:24:53.626698 DQS Delay:
4322 00:24:53.629817 DQS0 = 0, DQS1 = 0
4323 00:24:53.629896 DQM Delay:
4324 00:24:53.633289 DQM0 = 39, DQM1 = 32
4325 00:24:53.633369 DQ Delay:
4326 00:24:53.636502 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4327 00:24:53.639623 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4328 00:24:53.643087 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =20
4329 00:24:53.646644 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4330 00:24:53.646726
4331 00:24:53.646789
4332 00:24:53.653429 [DQSOSCAuto] RK1, (LSB)MR18= 0x5335, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4333 00:24:53.656775 CH0 RK1: MR19=808, MR18=5335
4334 00:24:53.663428 CH0_RK1: MR19=0x808, MR18=0x5335, DQSOSC=394, MR23=63, INC=168, DEC=112
4335 00:24:53.666435 [RxdqsGatingPostProcess] freq 600
4336 00:24:53.672952 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4337 00:24:53.676578 Pre-setting of DQS Precalculation
4338 00:24:53.680102 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4339 00:24:53.680185 ==
4340 00:24:53.683370 Dram Type= 6, Freq= 0, CH_1, rank 0
4341 00:24:53.686631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 00:24:53.686714 ==
4343 00:24:53.693808 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4344 00:24:53.699964 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4345 00:24:53.703921 [CA 0] Center 35 (5~66) winsize 62
4346 00:24:53.706786 [CA 1] Center 35 (5~66) winsize 62
4347 00:24:53.710562 [CA 2] Center 34 (4~65) winsize 62
4348 00:24:53.713393 [CA 3] Center 33 (3~64) winsize 62
4349 00:24:53.716692 [CA 4] Center 34 (3~65) winsize 63
4350 00:24:53.719879 [CA 5] Center 33 (2~64) winsize 63
4351 00:24:53.719961
4352 00:24:53.724148 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4353 00:24:53.724230
4354 00:24:53.726567 [CATrainingPosCal] consider 1 rank data
4355 00:24:53.729997 u2DelayCellTimex100 = 270/100 ps
4356 00:24:53.733442 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4357 00:24:53.737010 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4358 00:24:53.740427 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4359 00:24:53.743486 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4360 00:24:53.746747 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4361 00:24:53.750266 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4362 00:24:53.750345
4363 00:24:53.753593 CA PerBit enable=1, Macro0, CA PI delay=33
4364 00:24:53.753705
4365 00:24:53.757102 [CBTSetCACLKResult] CA Dly = 33
4366 00:24:53.760594 CS Dly: 5 (0~36)
4367 00:24:53.760729 ==
4368 00:24:53.763641 Dram Type= 6, Freq= 0, CH_1, rank 1
4369 00:24:53.767189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 00:24:53.767271 ==
4371 00:24:53.774010 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4372 00:24:53.780599 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4373 00:24:53.783859 [CA 0] Center 35 (5~66) winsize 62
4374 00:24:53.787281 [CA 1] Center 36 (6~66) winsize 61
4375 00:24:53.790473 [CA 2] Center 34 (3~65) winsize 63
4376 00:24:53.793754 [CA 3] Center 33 (3~64) winsize 62
4377 00:24:53.797268 [CA 4] Center 34 (3~65) winsize 63
4378 00:24:53.800826 [CA 5] Center 33 (3~64) winsize 62
4379 00:24:53.800906
4380 00:24:53.803818 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4381 00:24:53.803946
4382 00:24:53.807374 [CATrainingPosCal] consider 2 rank data
4383 00:24:53.810490 u2DelayCellTimex100 = 270/100 ps
4384 00:24:53.814109 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4385 00:24:53.817160 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4386 00:24:53.820908 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4387 00:24:53.824016 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4388 00:24:53.826993 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4389 00:24:53.830350 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4390 00:24:53.830432
4391 00:24:53.833906 CA PerBit enable=1, Macro0, CA PI delay=33
4392 00:24:53.833987
4393 00:24:53.837266 [CBTSetCACLKResult] CA Dly = 33
4394 00:24:53.840357 CS Dly: 5 (0~36)
4395 00:24:53.840460
4396 00:24:53.843511 ----->DramcWriteLeveling(PI) begin...
4397 00:24:53.843595 ==
4398 00:24:53.847157 Dram Type= 6, Freq= 0, CH_1, rank 0
4399 00:24:53.850844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 00:24:53.850931 ==
4401 00:24:53.854387 Write leveling (Byte 0): 28 => 28
4402 00:24:53.857241 Write leveling (Byte 1): 32 => 32
4403 00:24:53.860494 DramcWriteLeveling(PI) end<-----
4404 00:24:53.860577
4405 00:24:53.860640 ==
4406 00:24:53.864230 Dram Type= 6, Freq= 0, CH_1, rank 0
4407 00:24:53.866912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 00:24:53.866995 ==
4409 00:24:53.870859 [Gating] SW mode calibration
4410 00:24:53.877265 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4411 00:24:53.883562 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4412 00:24:53.887185 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4413 00:24:53.894071 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4414 00:24:53.897089 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4415 00:24:53.900308 0 9 12 | B1->B0 | 3333 3333 | 0 1 | (0 0) (1 1)
4416 00:24:53.904111 0 9 16 | B1->B0 | 2929 2424 | 0 0 | (1 1) (0 0)
4417 00:24:53.910603 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 00:24:53.913534 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 00:24:53.916786 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4420 00:24:53.923808 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 00:24:53.926918 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 00:24:53.930523 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 00:24:53.937336 0 10 12 | B1->B0 | 2828 2d2d | 1 0 | (0 0) (0 0)
4424 00:24:53.940266 0 10 16 | B1->B0 | 3a39 3e3e | 1 0 | (0 0) (0 0)
4425 00:24:53.943945 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 00:24:53.950511 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 00:24:53.953659 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 00:24:53.957445 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 00:24:53.963744 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 00:24:53.967402 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 00:24:53.970914 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4432 00:24:53.977221 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4433 00:24:53.980839 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 00:24:53.983765 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 00:24:53.990281 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 00:24:53.993602 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 00:24:53.997222 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 00:24:54.000298 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 00:24:54.007588 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 00:24:54.010743 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 00:24:54.013844 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 00:24:54.020422 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 00:24:54.023749 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 00:24:54.027156 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 00:24:54.033865 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 00:24:54.037946 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 00:24:54.041128 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4448 00:24:54.047371 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 00:24:54.047454 Total UI for P1: 0, mck2ui 16
4450 00:24:54.051194 best dqsien dly found for B0: ( 0, 13, 14)
4451 00:24:54.054303 Total UI for P1: 0, mck2ui 16
4452 00:24:54.057553 best dqsien dly found for B1: ( 0, 13, 12)
4453 00:24:54.064170 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4454 00:24:54.067598 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4455 00:24:54.067670
4456 00:24:54.070970 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4457 00:24:54.074005 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4458 00:24:54.077565 [Gating] SW calibration Done
4459 00:24:54.077635 ==
4460 00:24:54.080782 Dram Type= 6, Freq= 0, CH_1, rank 0
4461 00:24:54.084097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 00:24:54.084167 ==
4463 00:24:54.087359 RX Vref Scan: 0
4464 00:24:54.087426
4465 00:24:54.087488 RX Vref 0 -> 0, step: 1
4466 00:24:54.087549
4467 00:24:54.091154 RX Delay -230 -> 252, step: 16
4468 00:24:54.093940 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4469 00:24:54.101184 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4470 00:24:54.104200 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4471 00:24:54.107623 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4472 00:24:54.111198 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4473 00:24:54.114107 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4474 00:24:54.120830 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4475 00:24:54.124074 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4476 00:24:54.127419 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4477 00:24:54.130639 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4478 00:24:54.137415 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4479 00:24:54.140824 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4480 00:24:54.144445 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4481 00:24:54.147503 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4482 00:24:54.150849 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4483 00:24:54.157458 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4484 00:24:54.157538 ==
4485 00:24:54.160849 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 00:24:54.164307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 00:24:54.164382 ==
4488 00:24:54.164462 DQS Delay:
4489 00:24:54.167359 DQS0 = 0, DQS1 = 0
4490 00:24:54.167434 DQM Delay:
4491 00:24:54.170727 DQM0 = 44, DQM1 = 36
4492 00:24:54.170800 DQ Delay:
4493 00:24:54.173948 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4494 00:24:54.177506 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4495 00:24:54.181073 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4496 00:24:54.184077 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4497 00:24:54.184157
4498 00:24:54.184238
4499 00:24:54.184314 ==
4500 00:24:54.187732 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 00:24:54.190770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 00:24:54.194562 ==
4503 00:24:54.194636
4504 00:24:54.194715
4505 00:24:54.194801 TX Vref Scan disable
4506 00:24:54.197422 == TX Byte 0 ==
4507 00:24:54.200779 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4508 00:24:54.204484 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4509 00:24:54.207691 == TX Byte 1 ==
4510 00:24:54.210763 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4511 00:24:54.214112 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4512 00:24:54.214194 ==
4513 00:24:54.217903 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 00:24:54.224128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 00:24:54.224211 ==
4516 00:24:54.224302
4517 00:24:54.224404
4518 00:24:54.224499 TX Vref Scan disable
4519 00:24:54.229078 == TX Byte 0 ==
4520 00:24:54.232189 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4521 00:24:54.235883 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4522 00:24:54.238887 == TX Byte 1 ==
4523 00:24:54.242221 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4524 00:24:54.245915 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4525 00:24:54.249216
4526 00:24:54.249292 [DATLAT]
4527 00:24:54.249372 Freq=600, CH1 RK0
4528 00:24:54.249449
4529 00:24:54.252572 DATLAT Default: 0x9
4530 00:24:54.252645 0, 0xFFFF, sum = 0
4531 00:24:54.256519 1, 0xFFFF, sum = 0
4532 00:24:54.256600 2, 0xFFFF, sum = 0
4533 00:24:54.259129 3, 0xFFFF, sum = 0
4534 00:24:54.259200 4, 0xFFFF, sum = 0
4535 00:24:54.262196 5, 0xFFFF, sum = 0
4536 00:24:54.262278 6, 0xFFFF, sum = 0
4537 00:24:54.265811 7, 0xFFFF, sum = 0
4538 00:24:54.265884 8, 0x0, sum = 1
4539 00:24:54.269130 9, 0x0, sum = 2
4540 00:24:54.269211 10, 0x0, sum = 3
4541 00:24:54.272559 11, 0x0, sum = 4
4542 00:24:54.272639 best_step = 9
4543 00:24:54.272739
4544 00:24:54.272825 ==
4545 00:24:54.275593 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 00:24:54.282566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 00:24:54.282645 ==
4548 00:24:54.282736 RX Vref Scan: 1
4549 00:24:54.282813
4550 00:24:54.285793 RX Vref 0 -> 0, step: 1
4551 00:24:54.285872
4552 00:24:54.289316 RX Delay -179 -> 252, step: 8
4553 00:24:54.289392
4554 00:24:54.292400 Set Vref, RX VrefLevel [Byte0]: 59
4555 00:24:54.295935 [Byte1]: 50
4556 00:24:54.296016
4557 00:24:54.299016 Final RX Vref Byte 0 = 59 to rank0
4558 00:24:54.302342 Final RX Vref Byte 1 = 50 to rank0
4559 00:24:54.305862 Final RX Vref Byte 0 = 59 to rank1
4560 00:24:54.309584 Final RX Vref Byte 1 = 50 to rank1==
4561 00:24:54.312601 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 00:24:54.315853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 00:24:54.315935 ==
4564 00:24:54.316016 DQS Delay:
4565 00:24:54.319138 DQS0 = 0, DQS1 = 0
4566 00:24:54.319210 DQM Delay:
4567 00:24:54.323047 DQM0 = 40, DQM1 = 33
4568 00:24:54.323128 DQ Delay:
4569 00:24:54.326262 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4570 00:24:54.329315 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4571 00:24:54.332730 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4572 00:24:54.335961 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4573 00:24:54.336041
4574 00:24:54.336125
4575 00:24:54.346209 [DQSOSCAuto] RK0, (LSB)MR18= 0x4309, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4576 00:24:54.346293 CH1 RK0: MR19=808, MR18=4309
4577 00:24:54.353043 CH1_RK0: MR19=0x808, MR18=0x4309, DQSOSC=397, MR23=63, INC=166, DEC=110
4578 00:24:54.353125
4579 00:24:54.355951 ----->DramcWriteLeveling(PI) begin...
4580 00:24:54.356034 ==
4581 00:24:54.359270 Dram Type= 6, Freq= 0, CH_1, rank 1
4582 00:24:54.366026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 00:24:54.366112 ==
4584 00:24:54.369424 Write leveling (Byte 0): 28 => 28
4585 00:24:54.369502 Write leveling (Byte 1): 31 => 31
4586 00:24:54.372612 DramcWriteLeveling(PI) end<-----
4587 00:24:54.372759
4588 00:24:54.372838 ==
4589 00:24:54.376041 Dram Type= 6, Freq= 0, CH_1, rank 1
4590 00:24:54.383233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 00:24:54.383314 ==
4592 00:24:54.386106 [Gating] SW mode calibration
4593 00:24:54.393111 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4594 00:24:54.396226 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4595 00:24:54.399452 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4596 00:24:54.406440 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4597 00:24:54.409488 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4598 00:24:54.413419 0 9 12 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 0)
4599 00:24:54.419988 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4600 00:24:54.422986 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 00:24:54.426431 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4602 00:24:54.433042 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4603 00:24:54.436329 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 00:24:54.439761 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 00:24:54.446291 0 10 8 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
4606 00:24:54.449592 0 10 12 | B1->B0 | 3131 3d3d | 0 0 | (0 0) (0 0)
4607 00:24:54.452814 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4608 00:24:54.459628 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 00:24:54.463167 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 00:24:54.466661 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 00:24:54.472913 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 00:24:54.476951 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 00:24:54.479590 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4614 00:24:54.483412 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4615 00:24:54.490018 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 00:24:54.493082 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 00:24:54.496438 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 00:24:54.503543 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 00:24:54.506378 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 00:24:54.510226 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 00:24:54.516738 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 00:24:54.520461 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 00:24:54.523785 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 00:24:54.530482 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 00:24:54.533785 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 00:24:54.537031 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 00:24:54.540316 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 00:24:54.547053 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 00:24:54.550159 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4630 00:24:54.553390 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4631 00:24:54.557285 Total UI for P1: 0, mck2ui 16
4632 00:24:54.560464 best dqsien dly found for B0: ( 0, 13, 8)
4633 00:24:54.567323 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 00:24:54.567400 Total UI for P1: 0, mck2ui 16
4635 00:24:54.573690 best dqsien dly found for B1: ( 0, 13, 12)
4636 00:24:54.576928 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4637 00:24:54.580278 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4638 00:24:54.580371
4639 00:24:54.583338 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4640 00:24:54.587171 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4641 00:24:54.590657 [Gating] SW calibration Done
4642 00:24:54.590733 ==
4643 00:24:54.593405 Dram Type= 6, Freq= 0, CH_1, rank 1
4644 00:24:54.597504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 00:24:54.597588 ==
4646 00:24:54.600092 RX Vref Scan: 0
4647 00:24:54.600170
4648 00:24:54.600267 RX Vref 0 -> 0, step: 1
4649 00:24:54.600363
4650 00:24:54.603438 RX Delay -230 -> 252, step: 16
4651 00:24:54.610570 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4652 00:24:54.613661 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4653 00:24:54.617097 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4654 00:24:54.620130 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4655 00:24:54.623841 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4656 00:24:54.630347 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4657 00:24:54.633723 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4658 00:24:54.637241 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4659 00:24:54.640371 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4660 00:24:54.643828 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4661 00:24:54.650639 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4662 00:24:54.653480 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4663 00:24:54.657008 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4664 00:24:54.660151 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4665 00:24:54.667172 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4666 00:24:54.670488 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4667 00:24:54.670592 ==
4668 00:24:54.673749 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 00:24:54.677052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 00:24:54.677133 ==
4671 00:24:54.680647 DQS Delay:
4672 00:24:54.680756 DQS0 = 0, DQS1 = 0
4673 00:24:54.680847 DQM Delay:
4674 00:24:54.683666 DQM0 = 40, DQM1 = 36
4675 00:24:54.683784 DQ Delay:
4676 00:24:54.687560 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4677 00:24:54.690611 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4678 00:24:54.693640 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4679 00:24:54.697186 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4680 00:24:54.697265
4681 00:24:54.697346
4682 00:24:54.697424 ==
4683 00:24:54.700623 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 00:24:54.707066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 00:24:54.707170 ==
4686 00:24:54.707273
4687 00:24:54.707362
4688 00:24:54.707449 TX Vref Scan disable
4689 00:24:54.710803 == TX Byte 0 ==
4690 00:24:54.713941 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4691 00:24:54.717191 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4692 00:24:54.720444 == TX Byte 1 ==
4693 00:24:54.723955 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4694 00:24:54.727434 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4695 00:24:54.730592 ==
4696 00:24:54.733910 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 00:24:54.737228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 00:24:54.737309 ==
4699 00:24:54.737377
4700 00:24:54.737436
4701 00:24:54.740487 TX Vref Scan disable
4702 00:24:54.740587 == TX Byte 0 ==
4703 00:24:54.747404 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4704 00:24:54.750526 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4705 00:24:54.750629 == TX Byte 1 ==
4706 00:24:54.757368 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4707 00:24:54.760800 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4708 00:24:54.760877
4709 00:24:54.760937 [DATLAT]
4710 00:24:54.764215 Freq=600, CH1 RK1
4711 00:24:54.764313
4712 00:24:54.764408 DATLAT Default: 0x9
4713 00:24:54.767482 0, 0xFFFF, sum = 0
4714 00:24:54.767582 1, 0xFFFF, sum = 0
4715 00:24:54.770764 2, 0xFFFF, sum = 0
4716 00:24:54.770878 3, 0xFFFF, sum = 0
4717 00:24:54.774409 4, 0xFFFF, sum = 0
4718 00:24:54.774491 5, 0xFFFF, sum = 0
4719 00:24:54.777660 6, 0xFFFF, sum = 0
4720 00:24:54.777743 7, 0xFFFF, sum = 0
4721 00:24:54.780684 8, 0x0, sum = 1
4722 00:24:54.780772 9, 0x0, sum = 2
4723 00:24:54.784486 10, 0x0, sum = 3
4724 00:24:54.784586 11, 0x0, sum = 4
4725 00:24:54.787546 best_step = 9
4726 00:24:54.787645
4727 00:24:54.787733 ==
4728 00:24:54.790579 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 00:24:54.794286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 00:24:54.794391 ==
4731 00:24:54.797704 RX Vref Scan: 0
4732 00:24:54.797778
4733 00:24:54.797839 RX Vref 0 -> 0, step: 1
4734 00:24:54.797915
4735 00:24:54.800862 RX Delay -179 -> 252, step: 8
4736 00:24:54.807800 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4737 00:24:54.810954 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4738 00:24:54.814280 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4739 00:24:54.817901 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4740 00:24:54.824701 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4741 00:24:54.827587 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4742 00:24:54.831081 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4743 00:24:54.834298 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4744 00:24:54.837514 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4745 00:24:54.844626 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4746 00:24:54.847669 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4747 00:24:54.850782 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4748 00:24:54.854274 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4749 00:24:54.861397 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4750 00:24:54.864442 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4751 00:24:54.867550 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4752 00:24:54.867657 ==
4753 00:24:54.870941 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 00:24:54.874372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 00:24:54.874476 ==
4756 00:24:54.877466 DQS Delay:
4757 00:24:54.877565 DQS0 = 0, DQS1 = 0
4758 00:24:54.880957 DQM Delay:
4759 00:24:54.881057 DQM0 = 38, DQM1 = 33
4760 00:24:54.881156 DQ Delay:
4761 00:24:54.884844 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4762 00:24:54.887756 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =36
4763 00:24:54.891298 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4764 00:24:54.894536 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4765 00:24:54.894639
4766 00:24:54.894728
4767 00:24:54.904227 [DQSOSCAuto] RK1, (LSB)MR18= 0x3645, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4768 00:24:54.907533 CH1 RK1: MR19=808, MR18=3645
4769 00:24:54.914398 CH1_RK1: MR19=0x808, MR18=0x3645, DQSOSC=396, MR23=63, INC=167, DEC=111
4770 00:24:54.914485 [RxdqsGatingPostProcess] freq 600
4771 00:24:54.921402 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4772 00:24:54.924780 Pre-setting of DQS Precalculation
4773 00:24:54.928083 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4774 00:24:54.937964 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4775 00:24:54.944343 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4776 00:24:54.944425
4777 00:24:54.944488
4778 00:24:54.948354 [Calibration Summary] 1200 Mbps
4779 00:24:54.948461 CH 0, Rank 0
4780 00:24:54.951044 SW Impedance : PASS
4781 00:24:54.951149 DUTY Scan : NO K
4782 00:24:54.954752 ZQ Calibration : PASS
4783 00:24:54.957725 Jitter Meter : NO K
4784 00:24:54.957798 CBT Training : PASS
4785 00:24:54.961469 Write leveling : PASS
4786 00:24:54.961542 RX DQS gating : PASS
4787 00:24:54.964317 RX DQ/DQS(RDDQC) : PASS
4788 00:24:54.967834 TX DQ/DQS : PASS
4789 00:24:54.967906 RX DATLAT : PASS
4790 00:24:54.971710 RX DQ/DQS(Engine): PASS
4791 00:24:54.974415 TX OE : NO K
4792 00:24:54.974500 All Pass.
4793 00:24:54.974562
4794 00:24:54.974620 CH 0, Rank 1
4795 00:24:54.978361 SW Impedance : PASS
4796 00:24:54.980892 DUTY Scan : NO K
4797 00:24:54.980994 ZQ Calibration : PASS
4798 00:24:54.984341 Jitter Meter : NO K
4799 00:24:54.988031 CBT Training : PASS
4800 00:24:54.988138 Write leveling : PASS
4801 00:24:54.991258 RX DQS gating : PASS
4802 00:24:54.994289 RX DQ/DQS(RDDQC) : PASS
4803 00:24:54.994394 TX DQ/DQS : PASS
4804 00:24:54.998014 RX DATLAT : PASS
4805 00:24:55.001388 RX DQ/DQS(Engine): PASS
4806 00:24:55.001460 TX OE : NO K
4807 00:24:55.001521 All Pass.
4808 00:24:55.004221
4809 00:24:55.004326 CH 1, Rank 0
4810 00:24:55.007494 SW Impedance : PASS
4811 00:24:55.007590 DUTY Scan : NO K
4812 00:24:55.011074 ZQ Calibration : PASS
4813 00:24:55.011179 Jitter Meter : NO K
4814 00:24:55.014696 CBT Training : PASS
4815 00:24:55.017590 Write leveling : PASS
4816 00:24:55.017662 RX DQS gating : PASS
4817 00:24:55.021344 RX DQ/DQS(RDDQC) : PASS
4818 00:24:55.024909 TX DQ/DQS : PASS
4819 00:24:55.024982 RX DATLAT : PASS
4820 00:24:55.027858 RX DQ/DQS(Engine): PASS
4821 00:24:55.031254 TX OE : NO K
4822 00:24:55.031343 All Pass.
4823 00:24:55.031407
4824 00:24:55.031465 CH 1, Rank 1
4825 00:24:55.034262 SW Impedance : PASS
4826 00:24:55.037754 DUTY Scan : NO K
4827 00:24:55.037854 ZQ Calibration : PASS
4828 00:24:55.041073 Jitter Meter : NO K
4829 00:24:55.044650 CBT Training : PASS
4830 00:24:55.044790 Write leveling : PASS
4831 00:24:55.047538 RX DQS gating : PASS
4832 00:24:55.051242 RX DQ/DQS(RDDQC) : PASS
4833 00:24:55.051316 TX DQ/DQS : PASS
4834 00:24:55.054391 RX DATLAT : PASS
4835 00:24:55.054486 RX DQ/DQS(Engine): PASS
4836 00:24:55.057728 TX OE : NO K
4837 00:24:55.057807 All Pass.
4838 00:24:55.057887
4839 00:24:55.061153 DramC Write-DBI off
4840 00:24:55.064872 PER_BANK_REFRESH: Hybrid Mode
4841 00:24:55.064952 TX_TRACKING: ON
4842 00:24:55.074679 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4843 00:24:55.077973 [FAST_K] Save calibration result to emmc
4844 00:24:55.081146 dramc_set_vcore_voltage set vcore to 662500
4845 00:24:55.084573 Read voltage for 933, 3
4846 00:24:55.084655 Vio18 = 0
4847 00:24:55.084758 Vcore = 662500
4848 00:24:55.087972 Vdram = 0
4849 00:24:55.088052 Vddq = 0
4850 00:24:55.088116 Vmddr = 0
4851 00:24:55.094855 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4852 00:24:55.098468 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4853 00:24:55.101794 MEM_TYPE=3, freq_sel=17
4854 00:24:55.104725 sv_algorithm_assistance_LP4_1600
4855 00:24:55.108230 ============ PULL DRAM RESETB DOWN ============
4856 00:24:55.111204 ========== PULL DRAM RESETB DOWN end =========
4857 00:24:55.118382 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4858 00:24:55.121520 ===================================
4859 00:24:55.121601 LPDDR4 DRAM CONFIGURATION
4860 00:24:55.124737 ===================================
4861 00:24:55.128512 EX_ROW_EN[0] = 0x0
4862 00:24:55.132056 EX_ROW_EN[1] = 0x0
4863 00:24:55.132134 LP4Y_EN = 0x0
4864 00:24:55.134983 WORK_FSP = 0x0
4865 00:24:55.135062 WL = 0x3
4866 00:24:55.138138 RL = 0x3
4867 00:24:55.138216 BL = 0x2
4868 00:24:55.141522 RPST = 0x0
4869 00:24:55.141601 RD_PRE = 0x0
4870 00:24:55.145225 WR_PRE = 0x1
4871 00:24:55.145307 WR_PST = 0x0
4872 00:24:55.148378 DBI_WR = 0x0
4873 00:24:55.148457 DBI_RD = 0x0
4874 00:24:55.151713 OTF = 0x1
4875 00:24:55.155052 ===================================
4876 00:24:55.158130 ===================================
4877 00:24:55.158261 ANA top config
4878 00:24:55.161388 ===================================
4879 00:24:55.164776 DLL_ASYNC_EN = 0
4880 00:24:55.168047 ALL_SLAVE_EN = 1
4881 00:24:55.171785 NEW_RANK_MODE = 1
4882 00:24:55.171865 DLL_IDLE_MODE = 1
4883 00:24:55.175107 LP45_APHY_COMB_EN = 1
4884 00:24:55.178033 TX_ODT_DIS = 1
4885 00:24:55.181634 NEW_8X_MODE = 1
4886 00:24:55.184993 ===================================
4887 00:24:55.188131 ===================================
4888 00:24:55.188203 data_rate = 1866
4889 00:24:55.191514 CKR = 1
4890 00:24:55.194740 DQ_P2S_RATIO = 8
4891 00:24:55.198133 ===================================
4892 00:24:55.201620 CA_P2S_RATIO = 8
4893 00:24:55.205290 DQ_CA_OPEN = 0
4894 00:24:55.208599 DQ_SEMI_OPEN = 0
4895 00:24:55.208720 CA_SEMI_OPEN = 0
4896 00:24:55.212581 CA_FULL_RATE = 0
4897 00:24:55.215126 DQ_CKDIV4_EN = 1
4898 00:24:55.218367 CA_CKDIV4_EN = 1
4899 00:24:55.222086 CA_PREDIV_EN = 0
4900 00:24:55.222161 PH8_DLY = 0
4901 00:24:55.224799 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4902 00:24:55.228171 DQ_AAMCK_DIV = 4
4903 00:24:55.232191 CA_AAMCK_DIV = 4
4904 00:24:55.235358 CA_ADMCK_DIV = 4
4905 00:24:55.238813 DQ_TRACK_CA_EN = 0
4906 00:24:55.238929 CA_PICK = 933
4907 00:24:55.241646 CA_MCKIO = 933
4908 00:24:55.245362 MCKIO_SEMI = 0
4909 00:24:55.248237 PLL_FREQ = 3732
4910 00:24:55.251672 DQ_UI_PI_RATIO = 32
4911 00:24:55.255157 CA_UI_PI_RATIO = 0
4912 00:24:55.258543 ===================================
4913 00:24:55.262211 ===================================
4914 00:24:55.262293 memory_type:LPDDR4
4915 00:24:55.265102 GP_NUM : 10
4916 00:24:55.268310 SRAM_EN : 1
4917 00:24:55.268380 MD32_EN : 0
4918 00:24:55.271689 ===================================
4919 00:24:55.275376 [ANA_INIT] >>>>>>>>>>>>>>
4920 00:24:55.278770 <<<<<< [CONFIGURE PHASE]: ANA_TX
4921 00:24:55.281914 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4922 00:24:55.285279 ===================================
4923 00:24:55.288350 data_rate = 1866,PCW = 0X8f00
4924 00:24:55.292294 ===================================
4925 00:24:55.295233 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4926 00:24:55.298927 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4927 00:24:55.305522 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4928 00:24:55.308583 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4929 00:24:55.312195 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4930 00:24:55.315682 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4931 00:24:55.318748 [ANA_INIT] flow start
4932 00:24:55.322030 [ANA_INIT] PLL >>>>>>>>
4933 00:24:55.322101 [ANA_INIT] PLL <<<<<<<<
4934 00:24:55.325216 [ANA_INIT] MIDPI >>>>>>>>
4935 00:24:55.328829 [ANA_INIT] MIDPI <<<<<<<<
4936 00:24:55.328903 [ANA_INIT] DLL >>>>>>>>
4937 00:24:55.332374 [ANA_INIT] flow end
4938 00:24:55.335555 ============ LP4 DIFF to SE enter ============
4939 00:24:55.338799 ============ LP4 DIFF to SE exit ============
4940 00:24:55.342168 [ANA_INIT] <<<<<<<<<<<<<
4941 00:24:55.345619 [Flow] Enable top DCM control >>>>>
4942 00:24:55.348821 [Flow] Enable top DCM control <<<<<
4943 00:24:55.352237 Enable DLL master slave shuffle
4944 00:24:55.359148 ==============================================================
4945 00:24:55.359238 Gating Mode config
4946 00:24:55.365307 ==============================================================
4947 00:24:55.365383 Config description:
4948 00:24:55.375437 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4949 00:24:55.382221 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4950 00:24:55.389063 SELPH_MODE 0: By rank 1: By Phase
4951 00:24:55.392255 ==============================================================
4952 00:24:55.395797 GAT_TRACK_EN = 1
4953 00:24:55.398841 RX_GATING_MODE = 2
4954 00:24:55.402807 RX_GATING_TRACK_MODE = 2
4955 00:24:55.405825 SELPH_MODE = 1
4956 00:24:55.409054 PICG_EARLY_EN = 1
4957 00:24:55.412309 VALID_LAT_VALUE = 1
4958 00:24:55.415915 ==============================================================
4959 00:24:55.419203 Enter into Gating configuration >>>>
4960 00:24:55.422520 Exit from Gating configuration <<<<
4961 00:24:55.426107 Enter into DVFS_PRE_config >>>>>
4962 00:24:55.439218 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4963 00:24:55.442574 Exit from DVFS_PRE_config <<<<<
4964 00:24:55.442655 Enter into PICG configuration >>>>
4965 00:24:55.446245 Exit from PICG configuration <<<<
4966 00:24:55.449306 [RX_INPUT] configuration >>>>>
4967 00:24:55.452968 [RX_INPUT] configuration <<<<<
4968 00:24:55.459223 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4969 00:24:55.462683 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4970 00:24:55.469849 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4971 00:24:55.476154 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4972 00:24:55.482949 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4973 00:24:55.489783 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4974 00:24:55.492989 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4975 00:24:55.496483 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4976 00:24:55.499696 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4977 00:24:55.506612 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4978 00:24:55.509797 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4979 00:24:55.513223 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4980 00:24:55.516756 ===================================
4981 00:24:55.519903 LPDDR4 DRAM CONFIGURATION
4982 00:24:55.522928 ===================================
4983 00:24:55.523065 EX_ROW_EN[0] = 0x0
4984 00:24:55.526541 EX_ROW_EN[1] = 0x0
4985 00:24:55.526638 LP4Y_EN = 0x0
4986 00:24:55.529997 WORK_FSP = 0x0
4987 00:24:55.530093 WL = 0x3
4988 00:24:55.532879 RL = 0x3
4989 00:24:55.532960 BL = 0x2
4990 00:24:55.536426 RPST = 0x0
4991 00:24:55.539615 RD_PRE = 0x0
4992 00:24:55.539711 WR_PRE = 0x1
4993 00:24:55.543552 WR_PST = 0x0
4994 00:24:55.543634 DBI_WR = 0x0
4995 00:24:55.546632 DBI_RD = 0x0
4996 00:24:55.546714 OTF = 0x1
4997 00:24:55.550017 ===================================
4998 00:24:55.553150 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4999 00:24:55.556276 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5000 00:24:55.563008 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5001 00:24:55.566489 ===================================
5002 00:24:55.569674 LPDDR4 DRAM CONFIGURATION
5003 00:24:55.572950 ===================================
5004 00:24:55.573027 EX_ROW_EN[0] = 0x10
5005 00:24:55.576759 EX_ROW_EN[1] = 0x0
5006 00:24:55.576840 LP4Y_EN = 0x0
5007 00:24:55.579820 WORK_FSP = 0x0
5008 00:24:55.579892 WL = 0x3
5009 00:24:55.583243 RL = 0x3
5010 00:24:55.583319 BL = 0x2
5011 00:24:55.586335 RPST = 0x0
5012 00:24:55.586402 RD_PRE = 0x0
5013 00:24:55.589952 WR_PRE = 0x1
5014 00:24:55.590029 WR_PST = 0x0
5015 00:24:55.593729 DBI_WR = 0x0
5016 00:24:55.593804 DBI_RD = 0x0
5017 00:24:55.596921 OTF = 0x1
5018 00:24:55.599812 ===================================
5019 00:24:55.606660 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5020 00:24:55.610282 nWR fixed to 30
5021 00:24:55.613184 [ModeRegInit_LP4] CH0 RK0
5022 00:24:55.613265 [ModeRegInit_LP4] CH0 RK1
5023 00:24:55.616546 [ModeRegInit_LP4] CH1 RK0
5024 00:24:55.619743 [ModeRegInit_LP4] CH1 RK1
5025 00:24:55.619824 match AC timing 9
5026 00:24:55.626748 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5027 00:24:55.630195 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5028 00:24:55.633370 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5029 00:24:55.640010 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5030 00:24:55.643326 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5031 00:24:55.643408 ==
5032 00:24:55.646505 Dram Type= 6, Freq= 0, CH_0, rank 0
5033 00:24:55.649812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5034 00:24:55.649895 ==
5035 00:24:55.656710 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5036 00:24:55.663146 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5037 00:24:55.666287 [CA 0] Center 38 (8~69) winsize 62
5038 00:24:55.670318 [CA 1] Center 38 (7~69) winsize 63
5039 00:24:55.673218 [CA 2] Center 35 (5~66) winsize 62
5040 00:24:55.676517 [CA 3] Center 35 (4~66) winsize 63
5041 00:24:55.679722 [CA 4] Center 34 (4~64) winsize 61
5042 00:24:55.683064 [CA 5] Center 34 (4~64) winsize 61
5043 00:24:55.683145
5044 00:24:55.686299 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5045 00:24:55.686381
5046 00:24:55.690115 [CATrainingPosCal] consider 1 rank data
5047 00:24:55.693122 u2DelayCellTimex100 = 270/100 ps
5048 00:24:55.696417 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5049 00:24:55.700030 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5050 00:24:55.703097 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5051 00:24:55.706273 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5052 00:24:55.709793 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5053 00:24:55.713037 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5054 00:24:55.713118
5055 00:24:55.716587 CA PerBit enable=1, Macro0, CA PI delay=34
5056 00:24:55.716679
5057 00:24:55.719927 [CBTSetCACLKResult] CA Dly = 34
5058 00:24:55.723120 CS Dly: 7 (0~38)
5059 00:24:55.723201 ==
5060 00:24:55.726548 Dram Type= 6, Freq= 0, CH_0, rank 1
5061 00:24:55.729973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5062 00:24:55.730056 ==
5063 00:24:55.736582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5064 00:24:55.743616 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5065 00:24:55.746835 [CA 0] Center 38 (7~69) winsize 63
5066 00:24:55.750338 [CA 1] Center 38 (7~69) winsize 63
5067 00:24:55.753321 [CA 2] Center 35 (5~66) winsize 62
5068 00:24:55.756941 [CA 3] Center 35 (4~66) winsize 63
5069 00:24:55.760111 [CA 4] Center 34 (3~65) winsize 63
5070 00:24:55.760193 [CA 5] Center 33 (3~64) winsize 62
5071 00:24:55.763370
5072 00:24:55.766753 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5073 00:24:55.766847
5074 00:24:55.770226 [CATrainingPosCal] consider 2 rank data
5075 00:24:55.773171 u2DelayCellTimex100 = 270/100 ps
5076 00:24:55.776688 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5077 00:24:55.780377 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5078 00:24:55.783357 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5079 00:24:55.786854 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5080 00:24:55.790067 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5081 00:24:55.793291 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5082 00:24:55.793372
5083 00:24:55.797049 CA PerBit enable=1, Macro0, CA PI delay=34
5084 00:24:55.797131
5085 00:24:55.800353 [CBTSetCACLKResult] CA Dly = 34
5086 00:24:55.803332 CS Dly: 7 (0~39)
5087 00:24:55.803413
5088 00:24:55.806571 ----->DramcWriteLeveling(PI) begin...
5089 00:24:55.806654 ==
5090 00:24:55.810326 Dram Type= 6, Freq= 0, CH_0, rank 0
5091 00:24:55.813236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 00:24:55.813316 ==
5093 00:24:55.816716 Write leveling (Byte 0): 31 => 31
5094 00:24:55.820000 Write leveling (Byte 1): 25 => 25
5095 00:24:55.823194 DramcWriteLeveling(PI) end<-----
5096 00:24:55.823268
5097 00:24:55.823337 ==
5098 00:24:55.826875 Dram Type= 6, Freq= 0, CH_0, rank 0
5099 00:24:55.830209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5100 00:24:55.830292 ==
5101 00:24:55.833220 [Gating] SW mode calibration
5102 00:24:55.840471 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5103 00:24:55.847104 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5104 00:24:55.850133 0 14 0 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5105 00:24:55.853862 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5106 00:24:55.860815 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 00:24:55.863607 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 00:24:55.866616 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 00:24:55.873318 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 00:24:55.876824 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 00:24:55.879976 0 14 28 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
5112 00:24:55.886830 0 15 0 | B1->B0 | 3232 2828 | 1 0 | (1 0) (0 0)
5113 00:24:55.890106 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5114 00:24:55.893607 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 00:24:55.900417 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 00:24:55.903567 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 00:24:55.907473 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 00:24:55.914053 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 00:24:55.917229 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 00:24:55.920322 1 0 0 | B1->B0 | 3030 3b3b | 0 0 | (0 0) (0 0)
5121 00:24:55.923725 1 0 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5122 00:24:55.930077 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 00:24:55.934036 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 00:24:55.937117 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 00:24:55.943720 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 00:24:55.947302 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 00:24:55.950538 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 00:24:55.957190 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 00:24:55.960458 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 00:24:55.963653 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 00:24:55.970817 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 00:24:55.973873 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 00:24:55.976963 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 00:24:55.983849 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 00:24:55.987173 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 00:24:55.990653 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 00:24:55.996872 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 00:24:56.000484 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 00:24:56.003803 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 00:24:56.007442 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 00:24:56.013673 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 00:24:56.017248 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 00:24:56.020881 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 00:24:56.027418 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5145 00:24:56.030457 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 00:24:56.034427 Total UI for P1: 0, mck2ui 16
5147 00:24:56.037035 best dqsien dly found for B0: ( 1, 3, 0)
5148 00:24:56.040536 Total UI for P1: 0, mck2ui 16
5149 00:24:56.044103 best dqsien dly found for B1: ( 1, 3, 0)
5150 00:24:56.047364 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5151 00:24:56.050592 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5152 00:24:56.050673
5153 00:24:56.053957 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5154 00:24:56.057412 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5155 00:24:56.060821 [Gating] SW calibration Done
5156 00:24:56.060934 ==
5157 00:24:56.064003 Dram Type= 6, Freq= 0, CH_0, rank 0
5158 00:24:56.067216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5159 00:24:56.067314 ==
5160 00:24:56.070990 RX Vref Scan: 0
5161 00:24:56.071087
5162 00:24:56.071181 RX Vref 0 -> 0, step: 1
5163 00:24:56.074051
5164 00:24:56.074147 RX Delay -80 -> 252, step: 8
5165 00:24:56.080882 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5166 00:24:56.084190 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5167 00:24:56.087275 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5168 00:24:56.091059 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5169 00:24:56.094485 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5170 00:24:56.097215 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5171 00:24:56.100573 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5172 00:24:56.107647 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5173 00:24:56.110718 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5174 00:24:56.114027 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5175 00:24:56.117439 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5176 00:24:56.121597 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5177 00:24:56.127653 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5178 00:24:56.131243 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5179 00:24:56.134133 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5180 00:24:56.137452 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5181 00:24:56.137548 ==
5182 00:24:56.140775 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 00:24:56.144156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 00:24:56.144240 ==
5185 00:24:56.147670 DQS Delay:
5186 00:24:56.147751 DQS0 = 0, DQS1 = 0
5187 00:24:56.150758 DQM Delay:
5188 00:24:56.150839 DQM0 = 98, DQM1 = 86
5189 00:24:56.150903 DQ Delay:
5190 00:24:56.154111 DQ0 =95, DQ1 =103, DQ2 =95, DQ3 =91
5191 00:24:56.157580 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5192 00:24:56.160905 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5193 00:24:56.164328 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5194 00:24:56.164410
5195 00:24:56.167938
5196 00:24:56.168019 ==
5197 00:24:56.171015 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 00:24:56.174364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 00:24:56.174446 ==
5200 00:24:56.174511
5201 00:24:56.174572
5202 00:24:56.177489 TX Vref Scan disable
5203 00:24:56.177570 == TX Byte 0 ==
5204 00:24:56.184292 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5205 00:24:56.187883 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5206 00:24:56.187966 == TX Byte 1 ==
5207 00:24:56.194526 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5208 00:24:56.197747 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5209 00:24:56.197833 ==
5210 00:24:56.200861 Dram Type= 6, Freq= 0, CH_0, rank 0
5211 00:24:56.204301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5212 00:24:56.204382 ==
5213 00:24:56.204446
5214 00:24:56.204505
5215 00:24:56.207631 TX Vref Scan disable
5216 00:24:56.211112 == TX Byte 0 ==
5217 00:24:56.214841 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5218 00:24:56.217705 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5219 00:24:56.221408 == TX Byte 1 ==
5220 00:24:56.224336 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5221 00:24:56.227970 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5222 00:24:56.228048
5223 00:24:56.231713 [DATLAT]
5224 00:24:56.231795 Freq=933, CH0 RK0
5225 00:24:56.231864
5226 00:24:56.234683 DATLAT Default: 0xd
5227 00:24:56.234756 0, 0xFFFF, sum = 0
5228 00:24:56.237642 1, 0xFFFF, sum = 0
5229 00:24:56.237717 2, 0xFFFF, sum = 0
5230 00:24:56.241368 3, 0xFFFF, sum = 0
5231 00:24:56.241453 4, 0xFFFF, sum = 0
5232 00:24:56.244561 5, 0xFFFF, sum = 0
5233 00:24:56.244679 6, 0xFFFF, sum = 0
5234 00:24:56.248050 7, 0xFFFF, sum = 0
5235 00:24:56.248159 8, 0xFFFF, sum = 0
5236 00:24:56.251445 9, 0xFFFF, sum = 0
5237 00:24:56.251527 10, 0x0, sum = 1
5238 00:24:56.254484 11, 0x0, sum = 2
5239 00:24:56.254565 12, 0x0, sum = 3
5240 00:24:56.258460 13, 0x0, sum = 4
5241 00:24:56.258535 best_step = 11
5242 00:24:56.258597
5243 00:24:56.258655 ==
5244 00:24:56.261503 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 00:24:56.264542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 00:24:56.264656 ==
5247 00:24:56.267942 RX Vref Scan: 1
5248 00:24:56.268010
5249 00:24:56.271414 RX Vref 0 -> 0, step: 1
5250 00:24:56.271501
5251 00:24:56.271599 RX Delay -61 -> 252, step: 4
5252 00:24:56.271704
5253 00:24:56.274367 Set Vref, RX VrefLevel [Byte0]: 52
5254 00:24:56.277874 [Byte1]: 50
5255 00:24:56.282938
5256 00:24:56.283020 Final RX Vref Byte 0 = 52 to rank0
5257 00:24:56.286095 Final RX Vref Byte 1 = 50 to rank0
5258 00:24:56.289371 Final RX Vref Byte 0 = 52 to rank1
5259 00:24:56.293116 Final RX Vref Byte 1 = 50 to rank1==
5260 00:24:56.296176 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 00:24:56.302546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 00:24:56.302629 ==
5263 00:24:56.302693 DQS Delay:
5264 00:24:56.302753 DQS0 = 0, DQS1 = 0
5265 00:24:56.306555 DQM Delay:
5266 00:24:56.306637 DQM0 = 97, DQM1 = 88
5267 00:24:56.309522 DQ Delay:
5268 00:24:56.312607 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5269 00:24:56.315814 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =102
5270 00:24:56.319334 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =82
5271 00:24:56.322750 DQ12 =94, DQ13 =90, DQ14 =102, DQ15 =98
5272 00:24:56.322831
5273 00:24:56.322894
5274 00:24:56.329246 [DQSOSCAuto] RK0, (LSB)MR18= 0x1501, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 415 ps
5275 00:24:56.332516 CH0 RK0: MR19=505, MR18=1501
5276 00:24:56.339303 CH0_RK0: MR19=0x505, MR18=0x1501, DQSOSC=415, MR23=63, INC=62, DEC=41
5277 00:24:56.339385
5278 00:24:56.342733 ----->DramcWriteLeveling(PI) begin...
5279 00:24:56.342816 ==
5280 00:24:56.346039 Dram Type= 6, Freq= 0, CH_0, rank 1
5281 00:24:56.349184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 00:24:56.349267 ==
5283 00:24:56.352984 Write leveling (Byte 0): 33 => 33
5284 00:24:56.356596 Write leveling (Byte 1): 25 => 25
5285 00:24:56.359394 DramcWriteLeveling(PI) end<-----
5286 00:24:56.359476
5287 00:24:56.359540 ==
5288 00:24:56.362970 Dram Type= 6, Freq= 0, CH_0, rank 1
5289 00:24:56.365756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 00:24:56.365838 ==
5291 00:24:56.369184 [Gating] SW mode calibration
5292 00:24:56.375968 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5293 00:24:56.382641 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5294 00:24:56.386552 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5295 00:24:56.389218 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5296 00:24:56.395932 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 00:24:56.399253 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 00:24:56.402620 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 00:24:56.409662 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 00:24:56.412864 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 00:24:56.416109 0 14 28 | B1->B0 | 3333 2f2f | 1 1 | (1 0) (1 1)
5302 00:24:56.422751 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
5303 00:24:56.426074 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5304 00:24:56.429584 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 00:24:56.436098 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 00:24:56.439914 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 00:24:56.442800 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 00:24:56.449178 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 00:24:56.452804 0 15 28 | B1->B0 | 2929 3636 | 0 1 | (0 0) (0 0)
5310 00:24:56.456173 1 0 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5311 00:24:56.462579 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 00:24:56.466306 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 00:24:56.469462 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 00:24:56.472848 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 00:24:56.479336 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 00:24:56.482804 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5317 00:24:56.486184 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5318 00:24:56.492767 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5319 00:24:56.496330 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5320 00:24:56.499396 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 00:24:56.506232 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 00:24:56.509493 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 00:24:56.512696 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 00:24:56.519894 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 00:24:56.522772 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 00:24:56.526323 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 00:24:56.532996 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 00:24:56.536480 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 00:24:56.539810 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 00:24:56.542970 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 00:24:56.549712 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 00:24:56.553350 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5333 00:24:56.556357 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5334 00:24:56.563111 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5335 00:24:56.566442 Total UI for P1: 0, mck2ui 16
5336 00:24:56.569556 best dqsien dly found for B0: ( 1, 2, 26)
5337 00:24:56.573191 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 00:24:56.576414 Total UI for P1: 0, mck2ui 16
5339 00:24:56.579860 best dqsien dly found for B1: ( 1, 3, 0)
5340 00:24:56.583111 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5341 00:24:56.586394 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5342 00:24:56.586468
5343 00:24:56.589816 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5344 00:24:56.593131 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5345 00:24:56.596639 [Gating] SW calibration Done
5346 00:24:56.596723 ==
5347 00:24:56.599711 Dram Type= 6, Freq= 0, CH_0, rank 1
5348 00:24:56.602837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 00:24:56.606500 ==
5350 00:24:56.606573 RX Vref Scan: 0
5351 00:24:56.606634
5352 00:24:56.609733 RX Vref 0 -> 0, step: 1
5353 00:24:56.609806
5354 00:24:56.609870 RX Delay -80 -> 252, step: 8
5355 00:24:56.616627 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5356 00:24:56.620145 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5357 00:24:56.623343 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5358 00:24:56.626818 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5359 00:24:56.630580 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5360 00:24:56.633491 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5361 00:24:56.636425 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5362 00:24:56.643420 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5363 00:24:56.646650 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5364 00:24:56.650466 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5365 00:24:56.653660 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5366 00:24:56.656570 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5367 00:24:56.663659 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5368 00:24:56.666721 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5369 00:24:56.670059 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5370 00:24:56.673674 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5371 00:24:56.673805 ==
5372 00:24:56.677193 Dram Type= 6, Freq= 0, CH_0, rank 1
5373 00:24:56.680226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 00:24:56.680312 ==
5375 00:24:56.683639 DQS Delay:
5376 00:24:56.683716 DQS0 = 0, DQS1 = 0
5377 00:24:56.686958 DQM Delay:
5378 00:24:56.687042 DQM0 = 97, DQM1 = 87
5379 00:24:56.687124 DQ Delay:
5380 00:24:56.690188 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5381 00:24:56.693437 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5382 00:24:56.696735 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5383 00:24:56.700505 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5384 00:24:56.700588
5385 00:24:56.700696
5386 00:24:56.703767 ==
5387 00:24:56.706947 Dram Type= 6, Freq= 0, CH_0, rank 1
5388 00:24:56.709982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5389 00:24:56.710067 ==
5390 00:24:56.710151
5391 00:24:56.710229
5392 00:24:56.713405 TX Vref Scan disable
5393 00:24:56.713478 == TX Byte 0 ==
5394 00:24:56.716917 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5395 00:24:56.723689 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5396 00:24:56.723768 == TX Byte 1 ==
5397 00:24:56.726656 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5398 00:24:56.733394 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5399 00:24:56.733477 ==
5400 00:24:56.736809 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 00:24:56.740359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 00:24:56.740449 ==
5403 00:24:56.740558
5404 00:24:56.740655
5405 00:24:56.743524 TX Vref Scan disable
5406 00:24:56.746907 == TX Byte 0 ==
5407 00:24:56.750050 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5408 00:24:56.753471 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5409 00:24:56.757077 == TX Byte 1 ==
5410 00:24:56.760633 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5411 00:24:56.763720 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5412 00:24:56.763819
5413 00:24:56.763919 [DATLAT]
5414 00:24:56.767076 Freq=933, CH0 RK1
5415 00:24:56.767150
5416 00:24:56.767232 DATLAT Default: 0xb
5417 00:24:56.770493 0, 0xFFFF, sum = 0
5418 00:24:56.773876 1, 0xFFFF, sum = 0
5419 00:24:56.773966 2, 0xFFFF, sum = 0
5420 00:24:56.777168 3, 0xFFFF, sum = 0
5421 00:24:56.777242 4, 0xFFFF, sum = 0
5422 00:24:56.780286 5, 0xFFFF, sum = 0
5423 00:24:56.780363 6, 0xFFFF, sum = 0
5424 00:24:56.784418 7, 0xFFFF, sum = 0
5425 00:24:56.784497 8, 0xFFFF, sum = 0
5426 00:24:56.786940 9, 0xFFFF, sum = 0
5427 00:24:56.787037 10, 0x0, sum = 1
5428 00:24:56.790388 11, 0x0, sum = 2
5429 00:24:56.790465 12, 0x0, sum = 3
5430 00:24:56.793964 13, 0x0, sum = 4
5431 00:24:56.794065 best_step = 11
5432 00:24:56.794129
5433 00:24:56.794187 ==
5434 00:24:56.797352 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 00:24:56.800834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 00:24:56.800909 ==
5437 00:24:56.804022 RX Vref Scan: 0
5438 00:24:56.804096
5439 00:24:56.806802 RX Vref 0 -> 0, step: 1
5440 00:24:56.806921
5441 00:24:56.807051 RX Delay -61 -> 252, step: 4
5442 00:24:56.815134 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5443 00:24:56.818517 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5444 00:24:56.821776 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5445 00:24:56.824719 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5446 00:24:56.828034 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5447 00:24:56.831580 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5448 00:24:56.838065 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5449 00:24:56.841543 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5450 00:24:56.845183 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5451 00:24:56.848585 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5452 00:24:56.851909 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5453 00:24:56.855118 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5454 00:24:56.861980 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5455 00:24:56.864916 iDelay=199, Bit 13, Center 94 (7 ~ 182) 176
5456 00:24:56.868376 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5457 00:24:56.871630 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5458 00:24:56.871708 ==
5459 00:24:56.875299 Dram Type= 6, Freq= 0, CH_0, rank 1
5460 00:24:56.878352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5461 00:24:56.881422 ==
5462 00:24:56.881498 DQS Delay:
5463 00:24:56.881564 DQS0 = 0, DQS1 = 0
5464 00:24:56.885535 DQM Delay:
5465 00:24:56.885605 DQM0 = 95, DQM1 = 88
5466 00:24:56.885664 DQ Delay:
5467 00:24:56.888741 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5468 00:24:56.891547 DQ4 =96, DQ5 =84, DQ6 =106, DQ7 =104
5469 00:24:56.895189 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =80
5470 00:24:56.898167 DQ12 =94, DQ13 =94, DQ14 =96, DQ15 =94
5471 00:24:56.898242
5472 00:24:56.901905
5473 00:24:56.908338 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b08, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5474 00:24:56.912047 CH0 RK1: MR19=505, MR18=1B08
5475 00:24:56.918545 CH0_RK1: MR19=0x505, MR18=0x1B08, DQSOSC=413, MR23=63, INC=63, DEC=42
5476 00:24:56.918625 [RxdqsGatingPostProcess] freq 933
5477 00:24:56.924975 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5478 00:24:56.928461 best DQS0 dly(2T, 0.5T) = (0, 11)
5479 00:24:56.931749 best DQS1 dly(2T, 0.5T) = (0, 11)
5480 00:24:56.935141 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5481 00:24:56.938711 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5482 00:24:56.942021 best DQS0 dly(2T, 0.5T) = (0, 10)
5483 00:24:56.945572 best DQS1 dly(2T, 0.5T) = (0, 11)
5484 00:24:56.948613 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5485 00:24:56.951684 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5486 00:24:56.955461 Pre-setting of DQS Precalculation
5487 00:24:56.958647 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5488 00:24:56.958730 ==
5489 00:24:56.962207 Dram Type= 6, Freq= 0, CH_1, rank 0
5490 00:24:56.965219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 00:24:56.965302 ==
5492 00:24:56.971900 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5493 00:24:56.978618 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5494 00:24:56.982244 [CA 0] Center 36 (6~67) winsize 62
5495 00:24:56.985360 [CA 1] Center 36 (6~67) winsize 62
5496 00:24:56.988803 [CA 2] Center 33 (3~64) winsize 62
5497 00:24:56.992181 [CA 3] Center 33 (3~64) winsize 62
5498 00:24:56.995211 [CA 4] Center 34 (4~64) winsize 61
5499 00:24:56.998766 [CA 5] Center 32 (2~63) winsize 62
5500 00:24:56.998848
5501 00:24:57.002051 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5502 00:24:57.002123
5503 00:24:57.005422 [CATrainingPosCal] consider 1 rank data
5504 00:24:57.008645 u2DelayCellTimex100 = 270/100 ps
5505 00:24:57.012072 CA0 delay=36 (6~67),Diff = 4 PI (24 cell)
5506 00:24:57.015205 CA1 delay=36 (6~67),Diff = 4 PI (24 cell)
5507 00:24:57.018491 CA2 delay=33 (3~64),Diff = 1 PI (6 cell)
5508 00:24:57.021966 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5509 00:24:57.025208 CA4 delay=34 (4~64),Diff = 2 PI (12 cell)
5510 00:24:57.028970 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5511 00:24:57.029052
5512 00:24:57.035594 CA PerBit enable=1, Macro0, CA PI delay=32
5513 00:24:57.035667
5514 00:24:57.035736 [CBTSetCACLKResult] CA Dly = 32
5515 00:24:57.038953 CS Dly: 4 (0~35)
5516 00:24:57.039025 ==
5517 00:24:57.042223 Dram Type= 6, Freq= 0, CH_1, rank 1
5518 00:24:57.046072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5519 00:24:57.046145 ==
5520 00:24:57.052264 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5521 00:24:57.058851 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5522 00:24:57.062418 [CA 0] Center 36 (6~67) winsize 62
5523 00:24:57.065635 [CA 1] Center 36 (6~67) winsize 62
5524 00:24:57.069212 [CA 2] Center 33 (3~64) winsize 62
5525 00:24:57.072268 [CA 3] Center 33 (3~64) winsize 62
5526 00:24:57.075720 [CA 4] Center 33 (3~64) winsize 62
5527 00:24:57.078937 [CA 5] Center 32 (2~63) winsize 62
5528 00:24:57.079020
5529 00:24:57.082472 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5530 00:24:57.082553
5531 00:24:57.085892 [CATrainingPosCal] consider 2 rank data
5532 00:24:57.089441 u2DelayCellTimex100 = 270/100 ps
5533 00:24:57.092324 CA0 delay=36 (6~67),Diff = 4 PI (24 cell)
5534 00:24:57.096109 CA1 delay=36 (6~67),Diff = 4 PI (24 cell)
5535 00:24:57.099299 CA2 delay=33 (3~64),Diff = 1 PI (6 cell)
5536 00:24:57.102230 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5537 00:24:57.106198 CA4 delay=34 (4~64),Diff = 2 PI (12 cell)
5538 00:24:57.109216 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5539 00:24:57.109296
5540 00:24:57.112446 CA PerBit enable=1, Macro0, CA PI delay=32
5541 00:24:57.112542
5542 00:24:57.115976 [CBTSetCACLKResult] CA Dly = 32
5543 00:24:57.119154 CS Dly: 5 (0~37)
5544 00:24:57.119249
5545 00:24:57.122513 ----->DramcWriteLeveling(PI) begin...
5546 00:24:57.122596 ==
5547 00:24:57.125966 Dram Type= 6, Freq= 0, CH_1, rank 0
5548 00:24:57.129052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5549 00:24:57.129134 ==
5550 00:24:57.132827 Write leveling (Byte 0): 24 => 24
5551 00:24:57.135993 Write leveling (Byte 1): 25 => 25
5552 00:24:57.139467 DramcWriteLeveling(PI) end<-----
5553 00:24:57.139547
5554 00:24:57.139611 ==
5555 00:24:57.142434 Dram Type= 6, Freq= 0, CH_1, rank 0
5556 00:24:57.145869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 00:24:57.145951 ==
5558 00:24:57.149274 [Gating] SW mode calibration
5559 00:24:57.156522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5560 00:24:57.162824 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5561 00:24:57.165988 0 14 0 | B1->B0 | 3232 3232 | 0 1 | (0 0) (1 1)
5562 00:24:57.169469 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 00:24:57.176316 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 00:24:57.179684 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 00:24:57.182701 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 00:24:57.189457 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 00:24:57.193483 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 00:24:57.196217 0 14 28 | B1->B0 | 2f2f 2f2f | 0 0 | (1 0) (1 0)
5569 00:24:57.202774 0 15 0 | B1->B0 | 2727 2727 | 1 1 | (1 0) (1 0)
5570 00:24:57.206331 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 00:24:57.209575 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 00:24:57.216122 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 00:24:57.219647 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 00:24:57.222860 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 00:24:57.229824 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 00:24:57.233221 0 15 28 | B1->B0 | 3333 3131 | 0 0 | (0 0) (0 0)
5577 00:24:57.237165 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5578 00:24:57.240141 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 00:24:57.246663 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 00:24:57.250148 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 00:24:57.253057 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 00:24:57.260024 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 00:24:57.263132 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5584 00:24:57.267063 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5585 00:24:57.273489 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5586 00:24:57.276532 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 00:24:57.280363 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 00:24:57.286755 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 00:24:57.290069 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 00:24:57.293811 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 00:24:57.296942 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 00:24:57.303606 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 00:24:57.307204 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 00:24:57.310274 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 00:24:57.317001 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 00:24:57.320468 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 00:24:57.323708 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 00:24:57.330226 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 00:24:57.333772 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 00:24:57.337138 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 00:24:57.340412 Total UI for P1: 0, mck2ui 16
5602 00:24:57.343926 best dqsien dly found for B0: ( 1, 2, 26)
5603 00:24:57.347133 Total UI for P1: 0, mck2ui 16
5604 00:24:57.350395 best dqsien dly found for B1: ( 1, 2, 26)
5605 00:24:57.353857 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5606 00:24:57.356907 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5607 00:24:57.357014
5608 00:24:57.360463 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5609 00:24:57.366867 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5610 00:24:57.366953 [Gating] SW calibration Done
5611 00:24:57.367039 ==
5612 00:24:57.370358 Dram Type= 6, Freq= 0, CH_1, rank 0
5613 00:24:57.376818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5614 00:24:57.376929 ==
5615 00:24:57.377023 RX Vref Scan: 0
5616 00:24:57.377087
5617 00:24:57.380552 RX Vref 0 -> 0, step: 1
5618 00:24:57.380650
5619 00:24:57.383531 RX Delay -80 -> 252, step: 8
5620 00:24:57.386981 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5621 00:24:57.390165 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5622 00:24:57.393855 iDelay=208, Bit 2, Center 83 (-8 ~ 175) 184
5623 00:24:57.397229 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5624 00:24:57.403747 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5625 00:24:57.407047 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5626 00:24:57.410636 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5627 00:24:57.413877 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5628 00:24:57.417074 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5629 00:24:57.420541 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5630 00:24:57.427429 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5631 00:24:57.430320 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5632 00:24:57.433761 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5633 00:24:57.437090 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5634 00:24:57.440493 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5635 00:24:57.443713 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5636 00:24:57.447212 ==
5637 00:24:57.447313 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 00:24:57.453916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 00:24:57.454001 ==
5640 00:24:57.454087 DQS Delay:
5641 00:24:57.457504 DQS0 = 0, DQS1 = 0
5642 00:24:57.457589 DQM Delay:
5643 00:24:57.460580 DQM0 = 96, DQM1 = 89
5644 00:24:57.460672 DQ Delay:
5645 00:24:57.463946 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5646 00:24:57.467664 DQ4 =95, DQ5 =111, DQ6 =107, DQ7 =91
5647 00:24:57.470548 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5648 00:24:57.474234 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5649 00:24:57.474365
5650 00:24:57.474451
5651 00:24:57.474532 ==
5652 00:24:57.477715 Dram Type= 6, Freq= 0, CH_1, rank 0
5653 00:24:57.480509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5654 00:24:57.480595 ==
5655 00:24:57.480716
5656 00:24:57.480799
5657 00:24:57.484165 TX Vref Scan disable
5658 00:24:57.487757 == TX Byte 0 ==
5659 00:24:57.491166 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5660 00:24:57.494286 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5661 00:24:57.497321 == TX Byte 1 ==
5662 00:24:57.500645 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5663 00:24:57.503914 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5664 00:24:57.503998 ==
5665 00:24:57.507590 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 00:24:57.511016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 00:24:57.511099 ==
5668 00:24:57.511185
5669 00:24:57.514335
5670 00:24:57.514418 TX Vref Scan disable
5671 00:24:57.517284 == TX Byte 0 ==
5672 00:24:57.520927 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5673 00:24:57.524627 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5674 00:24:57.527879 == TX Byte 1 ==
5675 00:24:57.531421 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5676 00:24:57.534689 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5677 00:24:57.534773
5678 00:24:57.537486 [DATLAT]
5679 00:24:57.537569 Freq=933, CH1 RK0
5680 00:24:57.537656
5681 00:24:57.540826 DATLAT Default: 0xd
5682 00:24:57.540909 0, 0xFFFF, sum = 0
5683 00:24:57.544131 1, 0xFFFF, sum = 0
5684 00:24:57.544220 2, 0xFFFF, sum = 0
5685 00:24:57.547732 3, 0xFFFF, sum = 0
5686 00:24:57.547833 4, 0xFFFF, sum = 0
5687 00:24:57.550991 5, 0xFFFF, sum = 0
5688 00:24:57.551076 6, 0xFFFF, sum = 0
5689 00:24:57.554674 7, 0xFFFF, sum = 0
5690 00:24:57.554759 8, 0xFFFF, sum = 0
5691 00:24:57.557959 9, 0xFFFF, sum = 0
5692 00:24:57.558044 10, 0x0, sum = 1
5693 00:24:57.561238 11, 0x0, sum = 2
5694 00:24:57.561339 12, 0x0, sum = 3
5695 00:24:57.564473 13, 0x0, sum = 4
5696 00:24:57.564558 best_step = 11
5697 00:24:57.564659
5698 00:24:57.564794 ==
5699 00:24:57.567865 Dram Type= 6, Freq= 0, CH_1, rank 0
5700 00:24:57.574395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5701 00:24:57.574496 ==
5702 00:24:57.574627 RX Vref Scan: 1
5703 00:24:57.574708
5704 00:24:57.577899 RX Vref 0 -> 0, step: 1
5705 00:24:57.577985
5706 00:24:57.581257 RX Delay -61 -> 252, step: 4
5707 00:24:57.581356
5708 00:24:57.584727 Set Vref, RX VrefLevel [Byte0]: 59
5709 00:24:57.588051 [Byte1]: 50
5710 00:24:57.588134
5711 00:24:57.591497 Final RX Vref Byte 0 = 59 to rank0
5712 00:24:57.594647 Final RX Vref Byte 1 = 50 to rank0
5713 00:24:57.597865 Final RX Vref Byte 0 = 59 to rank1
5714 00:24:57.601396 Final RX Vref Byte 1 = 50 to rank1==
5715 00:24:57.604685 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 00:24:57.607958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 00:24:57.608042 ==
5718 00:24:57.611608 DQS Delay:
5719 00:24:57.611691 DQS0 = 0, DQS1 = 0
5720 00:24:57.611775 DQM Delay:
5721 00:24:57.614436 DQM0 = 97, DQM1 = 88
5722 00:24:57.614519 DQ Delay:
5723 00:24:57.618117 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =96
5724 00:24:57.621627 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =94
5725 00:24:57.624580 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =84
5726 00:24:57.628198 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =92
5727 00:24:57.628282
5728 00:24:57.628367
5729 00:24:57.637801 [DQSOSCAuto] RK0, (LSB)MR18= 0x15f1, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps
5730 00:24:57.637889 CH1 RK0: MR19=504, MR18=15F1
5731 00:24:57.644715 CH1_RK0: MR19=0x504, MR18=0x15F1, DQSOSC=415, MR23=63, INC=62, DEC=41
5732 00:24:57.644815
5733 00:24:57.647923 ----->DramcWriteLeveling(PI) begin...
5734 00:24:57.648013 ==
5735 00:24:57.651289 Dram Type= 6, Freq= 0, CH_1, rank 1
5736 00:24:57.658334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 00:24:57.658411 ==
5738 00:24:57.661358 Write leveling (Byte 0): 26 => 26
5739 00:24:57.664861 Write leveling (Byte 1): 29 => 29
5740 00:24:57.664964 DramcWriteLeveling(PI) end<-----
5741 00:24:57.665074
5742 00:24:57.668008 ==
5743 00:24:57.671065 Dram Type= 6, Freq= 0, CH_1, rank 1
5744 00:24:57.674462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 00:24:57.674533 ==
5746 00:24:57.677937 [Gating] SW mode calibration
5747 00:24:57.684502 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5748 00:24:57.687890 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5749 00:24:57.694467 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 00:24:57.698287 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 00:24:57.701423 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 00:24:57.708113 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 00:24:57.711449 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 00:24:57.714445 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5755 00:24:57.721646 0 14 24 | B1->B0 | 3030 2e2e | 1 1 | (1 1) (1 0)
5756 00:24:57.724608 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5757 00:24:57.728246 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 00:24:57.731613 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 00:24:57.737983 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 00:24:57.741627 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 00:24:57.745001 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 00:24:57.751610 0 15 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5763 00:24:57.754803 0 15 24 | B1->B0 | 2727 3333 | 0 1 | (0 0) (0 0)
5764 00:24:57.758133 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5765 00:24:57.765113 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 00:24:57.768103 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 00:24:57.771673 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 00:24:57.778460 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 00:24:57.781927 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 00:24:57.785054 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 00:24:57.791741 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5772 00:24:57.794783 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5773 00:24:57.798478 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 00:24:57.805028 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 00:24:57.808550 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 00:24:57.811941 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 00:24:57.815257 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 00:24:57.821749 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 00:24:57.825508 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 00:24:57.828444 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 00:24:57.835217 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 00:24:57.838541 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 00:24:57.841818 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 00:24:57.848829 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 00:24:57.852061 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 00:24:57.855161 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 00:24:57.861885 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5788 00:24:57.864861 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5789 00:24:57.868704 Total UI for P1: 0, mck2ui 16
5790 00:24:57.872007 best dqsien dly found for B0: ( 1, 2, 24)
5791 00:24:57.875467 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 00:24:57.878365 Total UI for P1: 0, mck2ui 16
5793 00:24:57.881773 best dqsien dly found for B1: ( 1, 2, 26)
5794 00:24:57.885369 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5795 00:24:57.888319 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5796 00:24:57.888426
5797 00:24:57.891605 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5798 00:24:57.898366 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5799 00:24:57.898452 [Gating] SW calibration Done
5800 00:24:57.898514 ==
5801 00:24:57.901642 Dram Type= 6, Freq= 0, CH_1, rank 1
5802 00:24:57.908219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 00:24:57.908299 ==
5804 00:24:57.908360 RX Vref Scan: 0
5805 00:24:57.908417
5806 00:24:57.911594 RX Vref 0 -> 0, step: 1
5807 00:24:57.911691
5808 00:24:57.914949 RX Delay -80 -> 252, step: 8
5809 00:24:57.918718 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5810 00:24:57.922174 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5811 00:24:57.925376 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5812 00:24:57.928518 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5813 00:24:57.931758 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5814 00:24:57.938553 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5815 00:24:57.942001 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5816 00:24:57.945302 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5817 00:24:57.948419 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5818 00:24:57.951754 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5819 00:24:57.958589 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5820 00:24:57.962117 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5821 00:24:57.965291 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5822 00:24:57.968719 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5823 00:24:57.971853 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5824 00:24:57.975557 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5825 00:24:57.975652 ==
5826 00:24:57.979038 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 00:24:57.985798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 00:24:57.985889 ==
5829 00:24:57.985955 DQS Delay:
5830 00:24:57.988653 DQS0 = 0, DQS1 = 0
5831 00:24:57.988759 DQM Delay:
5832 00:24:57.988821 DQM0 = 94, DQM1 = 88
5833 00:24:57.992220 DQ Delay:
5834 00:24:57.995321 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5835 00:24:57.999165 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5836 00:24:58.002089 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5837 00:24:58.005563 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5838 00:24:58.005647
5839 00:24:58.005709
5840 00:24:58.005766 ==
5841 00:24:58.008955 Dram Type= 6, Freq= 0, CH_1, rank 1
5842 00:24:58.012423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5843 00:24:58.012518 ==
5844 00:24:58.012604
5845 00:24:58.012732
5846 00:24:58.015816 TX Vref Scan disable
5847 00:24:58.015899 == TX Byte 0 ==
5848 00:24:58.022364 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5849 00:24:58.025549 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5850 00:24:58.025628 == TX Byte 1 ==
5851 00:24:58.032303 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5852 00:24:58.035453 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5853 00:24:58.035533 ==
5854 00:24:58.039290 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 00:24:58.042680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 00:24:58.042752 ==
5857 00:24:58.042812
5858 00:24:58.042877
5859 00:24:58.045972 TX Vref Scan disable
5860 00:24:58.049380 == TX Byte 0 ==
5861 00:24:58.052326 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5862 00:24:58.056064 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5863 00:24:58.059848 == TX Byte 1 ==
5864 00:24:58.062880 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5865 00:24:58.065879 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5866 00:24:58.065955
5867 00:24:58.069272 [DATLAT]
5868 00:24:58.069342 Freq=933, CH1 RK1
5869 00:24:58.069402
5870 00:24:58.072365 DATLAT Default: 0xb
5871 00:24:58.072446 0, 0xFFFF, sum = 0
5872 00:24:58.075715 1, 0xFFFF, sum = 0
5873 00:24:58.075797 2, 0xFFFF, sum = 0
5874 00:24:58.079001 3, 0xFFFF, sum = 0
5875 00:24:58.079082 4, 0xFFFF, sum = 0
5876 00:24:58.082457 5, 0xFFFF, sum = 0
5877 00:24:58.082556 6, 0xFFFF, sum = 0
5878 00:24:58.085653 7, 0xFFFF, sum = 0
5879 00:24:58.085761 8, 0xFFFF, sum = 0
5880 00:24:58.089277 9, 0xFFFF, sum = 0
5881 00:24:58.089391 10, 0x0, sum = 1
5882 00:24:58.092228 11, 0x0, sum = 2
5883 00:24:58.092302 12, 0x0, sum = 3
5884 00:24:58.095787 13, 0x0, sum = 4
5885 00:24:58.095856 best_step = 11
5886 00:24:58.095914
5887 00:24:58.095980 ==
5888 00:24:58.099203 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 00:24:58.102550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 00:24:58.105744 ==
5891 00:24:58.105849 RX Vref Scan: 0
5892 00:24:58.105935
5893 00:24:58.108984 RX Vref 0 -> 0, step: 1
5894 00:24:58.109081
5895 00:24:58.112263 RX Delay -61 -> 252, step: 4
5896 00:24:58.116018 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5897 00:24:58.119628 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5898 00:24:58.122421 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5899 00:24:58.129233 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5900 00:24:58.132570 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5901 00:24:58.136426 iDelay=199, Bit 5, Center 102 (11 ~ 194) 184
5902 00:24:58.139454 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5903 00:24:58.142691 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5904 00:24:58.146003 iDelay=199, Bit 8, Center 78 (-17 ~ 174) 192
5905 00:24:58.152877 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5906 00:24:58.156493 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5907 00:24:58.159731 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5908 00:24:58.162976 iDelay=199, Bit 12, Center 100 (15 ~ 186) 172
5909 00:24:58.166128 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5910 00:24:58.169222 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5911 00:24:58.175993 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5912 00:24:58.176070 ==
5913 00:24:58.179318 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 00:24:58.183118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 00:24:58.183255 ==
5916 00:24:58.183362 DQS Delay:
5917 00:24:58.186282 DQS0 = 0, DQS1 = 0
5918 00:24:58.186392 DQM Delay:
5919 00:24:58.189921 DQM0 = 95, DQM1 = 90
5920 00:24:58.189999 DQ Delay:
5921 00:24:58.192783 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
5922 00:24:58.196553 DQ4 =96, DQ5 =102, DQ6 =106, DQ7 =92
5923 00:24:58.199673 DQ8 =78, DQ9 =80, DQ10 =90, DQ11 =82
5924 00:24:58.203266 DQ12 =100, DQ13 =98, DQ14 =100, DQ15 =98
5925 00:24:58.203369
5926 00:24:58.203476
5927 00:24:58.213001 [DQSOSCAuto] RK1, (LSB)MR18= 0x121b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
5928 00:24:58.213086 CH1 RK1: MR19=505, MR18=121B
5929 00:24:58.219692 CH1_RK1: MR19=0x505, MR18=0x121B, DQSOSC=413, MR23=63, INC=63, DEC=42
5930 00:24:58.223100 [RxdqsGatingPostProcess] freq 933
5931 00:24:58.229501 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5932 00:24:58.233240 best DQS0 dly(2T, 0.5T) = (0, 10)
5933 00:24:58.233355 best DQS1 dly(2T, 0.5T) = (0, 10)
5934 00:24:58.236354 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5935 00:24:58.239964 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5936 00:24:58.242915 best DQS0 dly(2T, 0.5T) = (0, 10)
5937 00:24:58.246535 best DQS1 dly(2T, 0.5T) = (0, 10)
5938 00:24:58.250030 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5939 00:24:58.252936 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5940 00:24:58.256454 Pre-setting of DQS Precalculation
5941 00:24:58.262892 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5942 00:24:58.269821 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5943 00:24:58.276721 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5944 00:24:58.276814
5945 00:24:58.276899
5946 00:24:58.279605 [Calibration Summary] 1866 Mbps
5947 00:24:58.279680 CH 0, Rank 0
5948 00:24:58.283057 SW Impedance : PASS
5949 00:24:58.286247 DUTY Scan : NO K
5950 00:24:58.286324 ZQ Calibration : PASS
5951 00:24:58.289820 Jitter Meter : NO K
5952 00:24:58.289900 CBT Training : PASS
5953 00:24:58.293402 Write leveling : PASS
5954 00:24:58.297136 RX DQS gating : PASS
5955 00:24:58.297221 RX DQ/DQS(RDDQC) : PASS
5956 00:24:58.300250 TX DQ/DQS : PASS
5957 00:24:58.303603 RX DATLAT : PASS
5958 00:24:58.303686 RX DQ/DQS(Engine): PASS
5959 00:24:58.306637 TX OE : NO K
5960 00:24:58.306714 All Pass.
5961 00:24:58.306807
5962 00:24:58.310099 CH 0, Rank 1
5963 00:24:58.310173 SW Impedance : PASS
5964 00:24:58.313126 DUTY Scan : NO K
5965 00:24:58.316839 ZQ Calibration : PASS
5966 00:24:58.316927 Jitter Meter : NO K
5967 00:24:58.319943 CBT Training : PASS
5968 00:24:58.320019 Write leveling : PASS
5969 00:24:58.323229 RX DQS gating : PASS
5970 00:24:58.326838 RX DQ/DQS(RDDQC) : PASS
5971 00:24:58.326921 TX DQ/DQS : PASS
5972 00:24:58.329689 RX DATLAT : PASS
5973 00:24:58.333410 RX DQ/DQS(Engine): PASS
5974 00:24:58.333496 TX OE : NO K
5975 00:24:58.336635 All Pass.
5976 00:24:58.336729
5977 00:24:58.336813 CH 1, Rank 0
5978 00:24:58.340283 SW Impedance : PASS
5979 00:24:58.340357 DUTY Scan : NO K
5980 00:24:58.343632 ZQ Calibration : PASS
5981 00:24:58.346749 Jitter Meter : NO K
5982 00:24:58.346827 CBT Training : PASS
5983 00:24:58.349925 Write leveling : PASS
5984 00:24:58.353196 RX DQS gating : PASS
5985 00:24:58.353273 RX DQ/DQS(RDDQC) : PASS
5986 00:24:58.356710 TX DQ/DQS : PASS
5987 00:24:58.360107 RX DATLAT : PASS
5988 00:24:58.360181 RX DQ/DQS(Engine): PASS
5989 00:24:58.363233 TX OE : NO K
5990 00:24:58.363318 All Pass.
5991 00:24:58.363400
5992 00:24:58.366790 CH 1, Rank 1
5993 00:24:58.366864 SW Impedance : PASS
5994 00:24:58.369911 DUTY Scan : NO K
5995 00:24:58.369989 ZQ Calibration : PASS
5996 00:24:58.373258 Jitter Meter : NO K
5997 00:24:58.376456 CBT Training : PASS
5998 00:24:58.376539 Write leveling : PASS
5999 00:24:58.379752 RX DQS gating : PASS
6000 00:24:58.383579 RX DQ/DQS(RDDQC) : PASS
6001 00:24:58.383655 TX DQ/DQS : PASS
6002 00:24:58.386881 RX DATLAT : PASS
6003 00:24:58.390157 RX DQ/DQS(Engine): PASS
6004 00:24:58.390240 TX OE : NO K
6005 00:24:58.393827 All Pass.
6006 00:24:58.393909
6007 00:24:58.393974 DramC Write-DBI off
6008 00:24:58.397131 PER_BANK_REFRESH: Hybrid Mode
6009 00:24:58.397213 TX_TRACKING: ON
6010 00:24:58.406833 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6011 00:24:58.410273 [FAST_K] Save calibration result to emmc
6012 00:24:58.413449 dramc_set_vcore_voltage set vcore to 650000
6013 00:24:58.416908 Read voltage for 400, 6
6014 00:24:58.416992 Vio18 = 0
6015 00:24:58.420543 Vcore = 650000
6016 00:24:58.420625 Vdram = 0
6017 00:24:58.420700 Vddq = 0
6018 00:24:58.420763 Vmddr = 0
6019 00:24:58.426500 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6020 00:24:58.433111 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6021 00:24:58.433206 MEM_TYPE=3, freq_sel=20
6022 00:24:58.436448 sv_algorithm_assistance_LP4_800
6023 00:24:58.440249 ============ PULL DRAM RESETB DOWN ============
6024 00:24:58.446804 ========== PULL DRAM RESETB DOWN end =========
6025 00:24:58.449949 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6026 00:24:58.453589 ===================================
6027 00:24:58.456494 LPDDR4 DRAM CONFIGURATION
6028 00:24:58.460111 ===================================
6029 00:24:58.460210 EX_ROW_EN[0] = 0x0
6030 00:24:58.463276 EX_ROW_EN[1] = 0x0
6031 00:24:58.463357 LP4Y_EN = 0x0
6032 00:24:58.466852 WORK_FSP = 0x0
6033 00:24:58.466933 WL = 0x2
6034 00:24:58.470674 RL = 0x2
6035 00:24:58.470754 BL = 0x2
6036 00:24:58.473350 RPST = 0x0
6037 00:24:58.473447 RD_PRE = 0x0
6038 00:24:58.476817 WR_PRE = 0x1
6039 00:24:58.476915 WR_PST = 0x0
6040 00:24:58.480555 DBI_WR = 0x0
6041 00:24:58.483525 DBI_RD = 0x0
6042 00:24:58.483624 OTF = 0x1
6043 00:24:58.486724 ===================================
6044 00:24:58.490225 ===================================
6045 00:24:58.490306 ANA top config
6046 00:24:58.494024 ===================================
6047 00:24:58.497298 DLL_ASYNC_EN = 0
6048 00:24:58.500164 ALL_SLAVE_EN = 1
6049 00:24:58.503619 NEW_RANK_MODE = 1
6050 00:24:58.506928 DLL_IDLE_MODE = 1
6051 00:24:58.507030 LP45_APHY_COMB_EN = 1
6052 00:24:58.510351 TX_ODT_DIS = 1
6053 00:24:58.513419 NEW_8X_MODE = 1
6054 00:24:58.516976 ===================================
6055 00:24:58.520182 ===================================
6056 00:24:58.523408 data_rate = 800
6057 00:24:58.527080 CKR = 1
6058 00:24:58.527180 DQ_P2S_RATIO = 4
6059 00:24:58.530134 ===================================
6060 00:24:58.533676 CA_P2S_RATIO = 4
6061 00:24:58.537281 DQ_CA_OPEN = 0
6062 00:24:58.540264 DQ_SEMI_OPEN = 1
6063 00:24:58.543782 CA_SEMI_OPEN = 1
6064 00:24:58.543883 CA_FULL_RATE = 0
6065 00:24:58.546897 DQ_CKDIV4_EN = 0
6066 00:24:58.550221 CA_CKDIV4_EN = 1
6067 00:24:58.553371 CA_PREDIV_EN = 0
6068 00:24:58.557169 PH8_DLY = 0
6069 00:24:58.560323 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6070 00:24:58.560398 DQ_AAMCK_DIV = 0
6071 00:24:58.564042 CA_AAMCK_DIV = 0
6072 00:24:58.566704 CA_ADMCK_DIV = 4
6073 00:24:58.570496 DQ_TRACK_CA_EN = 0
6074 00:24:58.573836 CA_PICK = 800
6075 00:24:58.576912 CA_MCKIO = 400
6076 00:24:58.580202 MCKIO_SEMI = 400
6077 00:24:58.580277 PLL_FREQ = 3016
6078 00:24:58.583558 DQ_UI_PI_RATIO = 32
6079 00:24:58.586870 CA_UI_PI_RATIO = 32
6080 00:24:58.590530 ===================================
6081 00:24:58.593599 ===================================
6082 00:24:58.596997 memory_type:LPDDR4
6083 00:24:58.597074 GP_NUM : 10
6084 00:24:58.600502 SRAM_EN : 1
6085 00:24:58.603482 MD32_EN : 0
6086 00:24:58.607041 ===================================
6087 00:24:58.607117 [ANA_INIT] >>>>>>>>>>>>>>
6088 00:24:58.610280 <<<<<< [CONFIGURE PHASE]: ANA_TX
6089 00:24:58.613481 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6090 00:24:58.617087 ===================================
6091 00:24:58.620131 data_rate = 800,PCW = 0X7400
6092 00:24:58.623706 ===================================
6093 00:24:58.626660 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6094 00:24:58.633884 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6095 00:24:58.643452 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6096 00:24:58.650194 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6097 00:24:58.653467 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6098 00:24:58.656699 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6099 00:24:58.656801 [ANA_INIT] flow start
6100 00:24:58.660637 [ANA_INIT] PLL >>>>>>>>
6101 00:24:58.663799 [ANA_INIT] PLL <<<<<<<<
6102 00:24:58.663903 [ANA_INIT] MIDPI >>>>>>>>
6103 00:24:58.667200 [ANA_INIT] MIDPI <<<<<<<<
6104 00:24:58.670379 [ANA_INIT] DLL >>>>>>>>
6105 00:24:58.670483 [ANA_INIT] flow end
6106 00:24:58.673623 ============ LP4 DIFF to SE enter ============
6107 00:24:58.680155 ============ LP4 DIFF to SE exit ============
6108 00:24:58.680261 [ANA_INIT] <<<<<<<<<<<<<
6109 00:24:58.683706 [Flow] Enable top DCM control >>>>>
6110 00:24:58.687493 [Flow] Enable top DCM control <<<<<
6111 00:24:58.690371 Enable DLL master slave shuffle
6112 00:24:58.697393 ==============================================================
6113 00:24:58.697470 Gating Mode config
6114 00:24:58.703512 ==============================================================
6115 00:24:58.707078 Config description:
6116 00:24:58.713636 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6117 00:24:58.720383 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6118 00:24:58.727012 SELPH_MODE 0: By rank 1: By Phase
6119 00:24:58.734061 ==============================================================
6120 00:24:58.734140 GAT_TRACK_EN = 0
6121 00:24:58.737712 RX_GATING_MODE = 2
6122 00:24:58.740561 RX_GATING_TRACK_MODE = 2
6123 00:24:58.743919 SELPH_MODE = 1
6124 00:24:58.747565 PICG_EARLY_EN = 1
6125 00:24:58.750781 VALID_LAT_VALUE = 1
6126 00:24:58.757325 ==============================================================
6127 00:24:58.760535 Enter into Gating configuration >>>>
6128 00:24:58.763861 Exit from Gating configuration <<<<
6129 00:24:58.767154 Enter into DVFS_PRE_config >>>>>
6130 00:24:58.777282 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6131 00:24:58.780744 Exit from DVFS_PRE_config <<<<<
6132 00:24:58.783770 Enter into PICG configuration >>>>
6133 00:24:58.787164 Exit from PICG configuration <<<<
6134 00:24:58.790362 [RX_INPUT] configuration >>>>>
6135 00:24:58.790440 [RX_INPUT] configuration <<<<<
6136 00:24:58.797657 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6137 00:24:58.804616 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6138 00:24:58.807421 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6139 00:24:58.814019 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6140 00:24:58.820511 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6141 00:24:58.827304 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6142 00:24:58.831049 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6143 00:24:58.833903 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6144 00:24:58.840656 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6145 00:24:58.844359 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6146 00:24:58.847293 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6147 00:24:58.851096 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6148 00:24:58.853963 ===================================
6149 00:24:58.857546 LPDDR4 DRAM CONFIGURATION
6150 00:24:58.860765 ===================================
6151 00:24:58.864173 EX_ROW_EN[0] = 0x0
6152 00:24:58.864250 EX_ROW_EN[1] = 0x0
6153 00:24:58.867272 LP4Y_EN = 0x0
6154 00:24:58.867349 WORK_FSP = 0x0
6155 00:24:58.870536 WL = 0x2
6156 00:24:58.870618 RL = 0x2
6157 00:24:58.873877 BL = 0x2
6158 00:24:58.873952 RPST = 0x0
6159 00:24:58.877332 RD_PRE = 0x0
6160 00:24:58.877409 WR_PRE = 0x1
6161 00:24:58.880653 WR_PST = 0x0
6162 00:24:58.880737 DBI_WR = 0x0
6163 00:24:58.884176 DBI_RD = 0x0
6164 00:24:58.884257 OTF = 0x1
6165 00:24:58.887341 ===================================
6166 00:24:58.894062 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6167 00:24:58.897611 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6168 00:24:58.900459 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6169 00:24:58.904157 ===================================
6170 00:24:58.907610 LPDDR4 DRAM CONFIGURATION
6171 00:24:58.910647 ===================================
6172 00:24:58.914196 EX_ROW_EN[0] = 0x10
6173 00:24:58.914272 EX_ROW_EN[1] = 0x0
6174 00:24:58.917780 LP4Y_EN = 0x0
6175 00:24:58.917884 WORK_FSP = 0x0
6176 00:24:58.920943 WL = 0x2
6177 00:24:58.921051 RL = 0x2
6178 00:24:58.923969 BL = 0x2
6179 00:24:58.924045 RPST = 0x0
6180 00:24:58.927723 RD_PRE = 0x0
6181 00:24:58.927795 WR_PRE = 0x1
6182 00:24:58.930615 WR_PST = 0x0
6183 00:24:58.930694 DBI_WR = 0x0
6184 00:24:58.934106 DBI_RD = 0x0
6185 00:24:58.934183 OTF = 0x1
6186 00:24:58.937564 ===================================
6187 00:24:58.944522 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6188 00:24:58.948485 nWR fixed to 30
6189 00:24:58.951546 [ModeRegInit_LP4] CH0 RK0
6190 00:24:58.951641 [ModeRegInit_LP4] CH0 RK1
6191 00:24:58.955320 [ModeRegInit_LP4] CH1 RK0
6192 00:24:58.959035 [ModeRegInit_LP4] CH1 RK1
6193 00:24:58.959113 match AC timing 19
6194 00:24:58.965155 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6195 00:24:58.968600 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6196 00:24:58.971623 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6197 00:24:58.978415 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6198 00:24:58.981711 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6199 00:24:58.981798 ==
6200 00:24:58.985540 Dram Type= 6, Freq= 0, CH_0, rank 0
6201 00:24:58.988340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6202 00:24:58.988416 ==
6203 00:24:58.995241 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6204 00:24:59.001791 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6205 00:24:59.005164 [CA 0] Center 36 (8~64) winsize 57
6206 00:24:59.008870 [CA 1] Center 36 (8~64) winsize 57
6207 00:24:59.008949 [CA 2] Center 36 (8~64) winsize 57
6208 00:24:59.011918 [CA 3] Center 36 (8~64) winsize 57
6209 00:24:59.015288 [CA 4] Center 36 (8~64) winsize 57
6210 00:24:59.018653 [CA 5] Center 36 (8~64) winsize 57
6211 00:24:59.018744
6212 00:24:59.021992 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6213 00:24:59.022072
6214 00:24:59.025122 [CATrainingPosCal] consider 1 rank data
6215 00:24:59.028845 u2DelayCellTimex100 = 270/100 ps
6216 00:24:59.031760 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 00:24:59.038904 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 00:24:59.041969 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 00:24:59.045645 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 00:24:59.048771 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 00:24:59.052157 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 00:24:59.052251
6223 00:24:59.055334 CA PerBit enable=1, Macro0, CA PI delay=36
6224 00:24:59.055417
6225 00:24:59.058638 [CBTSetCACLKResult] CA Dly = 36
6226 00:24:59.058760 CS Dly: 1 (0~32)
6227 00:24:59.062177 ==
6228 00:24:59.062258 Dram Type= 6, Freq= 0, CH_0, rank 1
6229 00:24:59.068740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6230 00:24:59.068834 ==
6231 00:24:59.071755 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6232 00:24:59.078607 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6233 00:24:59.082200 [CA 0] Center 36 (8~64) winsize 57
6234 00:24:59.085873 [CA 1] Center 36 (8~64) winsize 57
6235 00:24:59.088319 [CA 2] Center 36 (8~64) winsize 57
6236 00:24:59.092143 [CA 3] Center 36 (8~64) winsize 57
6237 00:24:59.095097 [CA 4] Center 36 (8~64) winsize 57
6238 00:24:59.099033 [CA 5] Center 36 (8~64) winsize 57
6239 00:24:59.099111
6240 00:24:59.102030 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6241 00:24:59.102128
6242 00:24:59.105306 [CATrainingPosCal] consider 2 rank data
6243 00:24:59.108932 u2DelayCellTimex100 = 270/100 ps
6244 00:24:59.111850 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 00:24:59.115235 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 00:24:59.118363 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 00:24:59.121678 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 00:24:59.125191 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 00:24:59.131858 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 00:24:59.131938
6251 00:24:59.135157 CA PerBit enable=1, Macro0, CA PI delay=36
6252 00:24:59.135229
6253 00:24:59.138562 [CBTSetCACLKResult] CA Dly = 36
6254 00:24:59.138632 CS Dly: 1 (0~32)
6255 00:24:59.138701
6256 00:24:59.142053 ----->DramcWriteLeveling(PI) begin...
6257 00:24:59.142125 ==
6258 00:24:59.145461 Dram Type= 6, Freq= 0, CH_0, rank 0
6259 00:24:59.148529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6260 00:24:59.151788 ==
6261 00:24:59.151862 Write leveling (Byte 0): 40 => 8
6262 00:24:59.154903 Write leveling (Byte 1): 32 => 0
6263 00:24:59.158751 DramcWriteLeveling(PI) end<-----
6264 00:24:59.158828
6265 00:24:59.158889 ==
6266 00:24:59.161696 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 00:24:59.168627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 00:24:59.168729 ==
6269 00:24:59.168807 [Gating] SW mode calibration
6270 00:24:59.178280 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6271 00:24:59.181963 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6272 00:24:59.185284 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6273 00:24:59.192012 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6274 00:24:59.195186 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6275 00:24:59.198672 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 00:24:59.205301 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 00:24:59.208337 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 00:24:59.212027 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 00:24:59.218593 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 00:24:59.222151 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 00:24:59.225467 Total UI for P1: 0, mck2ui 16
6282 00:24:59.228417 best dqsien dly found for B0: ( 0, 14, 24)
6283 00:24:59.231665 Total UI for P1: 0, mck2ui 16
6284 00:24:59.235303 best dqsien dly found for B1: ( 0, 14, 24)
6285 00:24:59.238543 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6286 00:24:59.242563 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6287 00:24:59.242639
6288 00:24:59.245599 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6289 00:24:59.248550 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6290 00:24:59.251967 [Gating] SW calibration Done
6291 00:24:59.252041 ==
6292 00:24:59.255454 Dram Type= 6, Freq= 0, CH_0, rank 0
6293 00:24:59.258735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 00:24:59.258811 ==
6295 00:24:59.261941 RX Vref Scan: 0
6296 00:24:59.262009
6297 00:24:59.265591 RX Vref 0 -> 0, step: 1
6298 00:24:59.265667
6299 00:24:59.268520 RX Delay -410 -> 252, step: 16
6300 00:24:59.271844 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6301 00:24:59.275502 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6302 00:24:59.278479 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6303 00:24:59.285455 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6304 00:24:59.288977 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6305 00:24:59.291850 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6306 00:24:59.295413 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6307 00:24:59.301983 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6308 00:24:59.305451 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6309 00:24:59.308474 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6310 00:24:59.312173 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6311 00:24:59.319060 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6312 00:24:59.321870 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6313 00:24:59.325216 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6314 00:24:59.328463 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6315 00:24:59.335431 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6316 00:24:59.335532 ==
6317 00:24:59.338673 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 00:24:59.342316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 00:24:59.342388 ==
6320 00:24:59.342447 DQS Delay:
6321 00:24:59.345299 DQS0 = 35, DQS1 = 51
6322 00:24:59.345372 DQM Delay:
6323 00:24:59.348483 DQM0 = 8, DQM1 = 10
6324 00:24:59.348552 DQ Delay:
6325 00:24:59.352105 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6326 00:24:59.355438 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6327 00:24:59.358796 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6328 00:24:59.362357 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6329 00:24:59.362445
6330 00:24:59.362505
6331 00:24:59.362566 ==
6332 00:24:59.365499 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 00:24:59.368868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 00:24:59.368943 ==
6335 00:24:59.369012
6336 00:24:59.369068
6337 00:24:59.372140 TX Vref Scan disable
6338 00:24:59.372224 == TX Byte 0 ==
6339 00:24:59.378835 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6340 00:24:59.381954 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6341 00:24:59.382055 == TX Byte 1 ==
6342 00:24:59.388694 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6343 00:24:59.392566 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6344 00:24:59.392688 ==
6345 00:24:59.395664 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 00:24:59.398723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 00:24:59.398812 ==
6348 00:24:59.398872
6349 00:24:59.398932
6350 00:24:59.401864 TX Vref Scan disable
6351 00:24:59.401936 == TX Byte 0 ==
6352 00:24:59.408685 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6353 00:24:59.412167 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6354 00:24:59.412265 == TX Byte 1 ==
6355 00:24:59.419022 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6356 00:24:59.422031 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6357 00:24:59.422105
6358 00:24:59.422166 [DATLAT]
6359 00:24:59.425614 Freq=400, CH0 RK0
6360 00:24:59.425680
6361 00:24:59.425739 DATLAT Default: 0xf
6362 00:24:59.428812 0, 0xFFFF, sum = 0
6363 00:24:59.428881 1, 0xFFFF, sum = 0
6364 00:24:59.432159 2, 0xFFFF, sum = 0
6365 00:24:59.432232 3, 0xFFFF, sum = 0
6366 00:24:59.435415 4, 0xFFFF, sum = 0
6367 00:24:59.435490 5, 0xFFFF, sum = 0
6368 00:24:59.439377 6, 0xFFFF, sum = 0
6369 00:24:59.439478 7, 0xFFFF, sum = 0
6370 00:24:59.442414 8, 0xFFFF, sum = 0
6371 00:24:59.442483 9, 0xFFFF, sum = 0
6372 00:24:59.445572 10, 0xFFFF, sum = 0
6373 00:24:59.449033 11, 0xFFFF, sum = 0
6374 00:24:59.449116 12, 0xFFFF, sum = 0
6375 00:24:59.452535 13, 0x0, sum = 1
6376 00:24:59.452642 14, 0x0, sum = 2
6377 00:24:59.452742 15, 0x0, sum = 3
6378 00:24:59.455476 16, 0x0, sum = 4
6379 00:24:59.455542 best_step = 14
6380 00:24:59.455605
6381 00:24:59.458632 ==
6382 00:24:59.458726 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 00:24:59.465311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 00:24:59.465381 ==
6385 00:24:59.465440 RX Vref Scan: 1
6386 00:24:59.465501
6387 00:24:59.469051 RX Vref 0 -> 0, step: 1
6388 00:24:59.469127
6389 00:24:59.472021 RX Delay -343 -> 252, step: 8
6390 00:24:59.472114
6391 00:24:59.475584 Set Vref, RX VrefLevel [Byte0]: 52
6392 00:24:59.478671 [Byte1]: 50
6393 00:24:59.482594
6394 00:24:59.482666 Final RX Vref Byte 0 = 52 to rank0
6395 00:24:59.485874 Final RX Vref Byte 1 = 50 to rank0
6396 00:24:59.489083 Final RX Vref Byte 0 = 52 to rank1
6397 00:24:59.492540 Final RX Vref Byte 1 = 50 to rank1==
6398 00:24:59.495390 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 00:24:59.502569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 00:24:59.502651 ==
6401 00:24:59.502713 DQS Delay:
6402 00:24:59.502771 DQS0 = 44, DQS1 = 60
6403 00:24:59.505426 DQM Delay:
6404 00:24:59.505499 DQM0 = 11, DQM1 = 14
6405 00:24:59.508991 DQ Delay:
6406 00:24:59.512221 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6407 00:24:59.512303 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6408 00:24:59.515652 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =12
6409 00:24:59.519135 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6410 00:24:59.519238
6411 00:24:59.519326
6412 00:24:59.529361 [DQSOSCAuto] RK0, (LSB)MR18= 0x8856, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6413 00:24:59.532514 CH0 RK0: MR19=C0C, MR18=8856
6414 00:24:59.539280 CH0_RK0: MR19=0xC0C, MR18=0x8856, DQSOSC=392, MR23=63, INC=384, DEC=256
6415 00:24:59.539370 ==
6416 00:24:59.542316 Dram Type= 6, Freq= 0, CH_0, rank 1
6417 00:24:59.545856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 00:24:59.545935 ==
6419 00:24:59.548978 [Gating] SW mode calibration
6420 00:24:59.555730 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6421 00:24:59.558935 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6422 00:24:59.565928 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6423 00:24:59.569123 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6424 00:24:59.572455 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6425 00:24:59.579118 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 00:24:59.582273 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 00:24:59.585891 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 00:24:59.592263 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 00:24:59.595529 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 00:24:59.599103 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 00:24:59.602124 Total UI for P1: 0, mck2ui 16
6432 00:24:59.606052 best dqsien dly found for B0: ( 0, 14, 24)
6433 00:24:59.609230 Total UI for P1: 0, mck2ui 16
6434 00:24:59.612563 best dqsien dly found for B1: ( 0, 14, 24)
6435 00:24:59.615794 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6436 00:24:59.618863 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6437 00:24:59.618957
6438 00:24:59.625806 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6439 00:24:59.628977 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6440 00:24:59.629068 [Gating] SW calibration Done
6441 00:24:59.632182 ==
6442 00:24:59.635471 Dram Type= 6, Freq= 0, CH_0, rank 1
6443 00:24:59.639264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 00:24:59.639348 ==
6445 00:24:59.639430 RX Vref Scan: 0
6446 00:24:59.639516
6447 00:24:59.642137 RX Vref 0 -> 0, step: 1
6448 00:24:59.642265
6449 00:24:59.645820 RX Delay -410 -> 252, step: 16
6450 00:24:59.648605 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6451 00:24:59.655247 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6452 00:24:59.658773 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6453 00:24:59.662027 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6454 00:24:59.665748 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6455 00:24:59.672038 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6456 00:24:59.675504 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6457 00:24:59.678657 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6458 00:24:59.681808 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6459 00:24:59.688364 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6460 00:24:59.691749 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6461 00:24:59.695083 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6462 00:24:59.698417 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6463 00:24:59.705490 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6464 00:24:59.708656 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6465 00:24:59.712023 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6466 00:24:59.712106 ==
6467 00:24:59.715067 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 00:24:59.718745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 00:24:59.721965 ==
6470 00:24:59.722045 DQS Delay:
6471 00:24:59.722127 DQS0 = 43, DQS1 = 51
6472 00:24:59.724873 DQM Delay:
6473 00:24:59.724981 DQM0 = 11, DQM1 = 11
6474 00:24:59.728217 DQ Delay:
6475 00:24:59.728314 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6476 00:24:59.731769 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6477 00:24:59.734982 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6478 00:24:59.738104 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6479 00:24:59.738188
6480 00:24:59.738269
6481 00:24:59.738349 ==
6482 00:24:59.741633 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 00:24:59.748491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 00:24:59.748576 ==
6485 00:24:59.748696
6486 00:24:59.748798
6487 00:24:59.748877 TX Vref Scan disable
6488 00:24:59.751635 == TX Byte 0 ==
6489 00:24:59.755237 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6490 00:24:59.758427 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6491 00:24:59.762075 == TX Byte 1 ==
6492 00:24:59.765155 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6493 00:24:59.768494 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6494 00:24:59.768636 ==
6495 00:24:59.771923 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 00:24:59.778575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 00:24:59.778661 ==
6498 00:24:59.778747
6499 00:24:59.778824
6500 00:24:59.778907 TX Vref Scan disable
6501 00:24:59.781795 == TX Byte 0 ==
6502 00:24:59.785041 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6503 00:24:59.788848 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6504 00:24:59.791901 == TX Byte 1 ==
6505 00:24:59.795139 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6506 00:24:59.798301 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6507 00:24:59.798394
6508 00:24:59.802062 [DATLAT]
6509 00:24:59.802148 Freq=400, CH0 RK1
6510 00:24:59.802211
6511 00:24:59.805028 DATLAT Default: 0xe
6512 00:24:59.805121 0, 0xFFFF, sum = 0
6513 00:24:59.808742 1, 0xFFFF, sum = 0
6514 00:24:59.808827 2, 0xFFFF, sum = 0
6515 00:24:59.811778 3, 0xFFFF, sum = 0
6516 00:24:59.811851 4, 0xFFFF, sum = 0
6517 00:24:59.814949 5, 0xFFFF, sum = 0
6518 00:24:59.815021 6, 0xFFFF, sum = 0
6519 00:24:59.818399 7, 0xFFFF, sum = 0
6520 00:24:59.818470 8, 0xFFFF, sum = 0
6521 00:24:59.822264 9, 0xFFFF, sum = 0
6522 00:24:59.822354 10, 0xFFFF, sum = 0
6523 00:24:59.825006 11, 0xFFFF, sum = 0
6524 00:24:59.825108 12, 0xFFFF, sum = 0
6525 00:24:59.828442 13, 0x0, sum = 1
6526 00:24:59.828519 14, 0x0, sum = 2
6527 00:24:59.832081 15, 0x0, sum = 3
6528 00:24:59.832178 16, 0x0, sum = 4
6529 00:24:59.835044 best_step = 14
6530 00:24:59.835118
6531 00:24:59.835224 ==
6532 00:24:59.838866 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 00:24:59.842088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 00:24:59.842166 ==
6535 00:24:59.845367 RX Vref Scan: 0
6536 00:24:59.845443
6537 00:24:59.845527 RX Vref 0 -> 0, step: 1
6538 00:24:59.845609
6539 00:24:59.848800 RX Delay -343 -> 252, step: 8
6540 00:24:59.856327 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6541 00:24:59.860288 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6542 00:24:59.863241 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6543 00:24:59.866418 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6544 00:24:59.873244 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6545 00:24:59.876564 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6546 00:24:59.879847 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6547 00:24:59.883665 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6548 00:24:59.890122 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6549 00:24:59.893200 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6550 00:24:59.896911 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6551 00:24:59.900037 iDelay=217, Bit 11, Center -52 (-287 ~ 184) 472
6552 00:24:59.906501 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6553 00:24:59.910156 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6554 00:24:59.913440 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6555 00:24:59.916574 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6556 00:24:59.920279 ==
6557 00:24:59.920375 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 00:24:59.926991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 00:24:59.927070 ==
6560 00:24:59.927158 DQS Delay:
6561 00:24:59.930463 DQS0 = 48, DQS1 = 60
6562 00:24:59.930546 DQM Delay:
6563 00:24:59.933904 DQM0 = 14, DQM1 = 13
6564 00:24:59.933989 DQ Delay:
6565 00:24:59.936794 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6566 00:24:59.940287 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6567 00:24:59.943452 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6568 00:24:59.947337 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6569 00:24:59.947434
6570 00:24:59.947523
6571 00:24:59.953312 [DQSOSCAuto] RK1, (LSB)MR18= 0x9f72, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 389 ps
6572 00:24:59.956591 CH0 RK1: MR19=C0C, MR18=9F72
6573 00:24:59.963659 CH0_RK1: MR19=0xC0C, MR18=0x9F72, DQSOSC=389, MR23=63, INC=390, DEC=260
6574 00:24:59.967157 [RxdqsGatingPostProcess] freq 400
6575 00:24:59.970241 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6576 00:24:59.973583 best DQS0 dly(2T, 0.5T) = (0, 10)
6577 00:24:59.976728 best DQS1 dly(2T, 0.5T) = (0, 10)
6578 00:24:59.980237 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6579 00:24:59.983777 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6580 00:24:59.986776 best DQS0 dly(2T, 0.5T) = (0, 10)
6581 00:24:59.989832 best DQS1 dly(2T, 0.5T) = (0, 10)
6582 00:24:59.993675 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6583 00:24:59.996836 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6584 00:25:00.000030 Pre-setting of DQS Precalculation
6585 00:25:00.003454 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6586 00:25:00.003534 ==
6587 00:25:00.006670 Dram Type= 6, Freq= 0, CH_1, rank 0
6588 00:25:00.013557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 00:25:00.013655 ==
6590 00:25:00.017947 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6591 00:25:00.023996 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6592 00:25:00.027188 [CA 0] Center 36 (8~64) winsize 57
6593 00:25:00.030178 [CA 1] Center 36 (8~64) winsize 57
6594 00:25:00.033681 [CA 2] Center 36 (8~64) winsize 57
6595 00:25:00.037036 [CA 3] Center 36 (8~64) winsize 57
6596 00:25:00.040554 [CA 4] Center 36 (8~64) winsize 57
6597 00:25:00.043973 [CA 5] Center 36 (8~64) winsize 57
6598 00:25:00.044052
6599 00:25:00.046990 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6600 00:25:00.047061
6601 00:25:00.050294 [CATrainingPosCal] consider 1 rank data
6602 00:25:00.053913 u2DelayCellTimex100 = 270/100 ps
6603 00:25:00.057420 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 00:25:00.060413 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 00:25:00.064081 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 00:25:00.067175 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 00:25:00.070410 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 00:25:00.073747 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 00:25:00.073817
6610 00:25:00.077163 CA PerBit enable=1, Macro0, CA PI delay=36
6611 00:25:00.080518
6612 00:25:00.080607 [CBTSetCACLKResult] CA Dly = 36
6613 00:25:00.084086 CS Dly: 1 (0~32)
6614 00:25:00.084162 ==
6615 00:25:00.087247 Dram Type= 6, Freq= 0, CH_1, rank 1
6616 00:25:00.090458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 00:25:00.090525 ==
6618 00:25:00.097052 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6619 00:25:00.103861 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6620 00:25:00.106980 [CA 0] Center 36 (8~64) winsize 57
6621 00:25:00.110376 [CA 1] Center 36 (8~64) winsize 57
6622 00:25:00.110448 [CA 2] Center 36 (8~64) winsize 57
6623 00:25:00.113821 [CA 3] Center 36 (8~64) winsize 57
6624 00:25:00.117215 [CA 4] Center 36 (8~64) winsize 57
6625 00:25:00.120348 [CA 5] Center 36 (8~64) winsize 57
6626 00:25:00.120419
6627 00:25:00.123842 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6628 00:25:00.123910
6629 00:25:00.130522 [CATrainingPosCal] consider 2 rank data
6630 00:25:00.130622 u2DelayCellTimex100 = 270/100 ps
6631 00:25:00.133688 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 00:25:00.140322 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 00:25:00.143858 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 00:25:00.147782 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 00:25:00.150852 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 00:25:00.154009 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 00:25:00.154115
6638 00:25:00.157359 CA PerBit enable=1, Macro0, CA PI delay=36
6639 00:25:00.157434
6640 00:25:00.160547 [CBTSetCACLKResult] CA Dly = 36
6641 00:25:00.160642 CS Dly: 1 (0~32)
6642 00:25:00.160785
6643 00:25:00.167584 ----->DramcWriteLeveling(PI) begin...
6644 00:25:00.167704 ==
6645 00:25:00.170600 Dram Type= 6, Freq= 0, CH_1, rank 0
6646 00:25:00.174237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 00:25:00.174324 ==
6648 00:25:00.177209 Write leveling (Byte 0): 40 => 8
6649 00:25:00.180587 Write leveling (Byte 1): 40 => 8
6650 00:25:00.183661 DramcWriteLeveling(PI) end<-----
6651 00:25:00.183734
6652 00:25:00.183795 ==
6653 00:25:00.187681 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 00:25:00.191396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 00:25:00.191468 ==
6656 00:25:00.193990 [Gating] SW mode calibration
6657 00:25:00.200474 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6658 00:25:00.203886 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6659 00:25:00.211004 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6660 00:25:00.213895 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6661 00:25:00.217412 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6662 00:25:00.224189 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 00:25:00.227703 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 00:25:00.230710 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 00:25:00.237689 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 00:25:00.240842 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 00:25:00.243921 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 00:25:00.247256 Total UI for P1: 0, mck2ui 16
6669 00:25:00.250563 best dqsien dly found for B0: ( 0, 14, 24)
6670 00:25:00.253952 Total UI for P1: 0, mck2ui 16
6671 00:25:00.257234 best dqsien dly found for B1: ( 0, 14, 24)
6672 00:25:00.260623 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6673 00:25:00.264306 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6674 00:25:00.264392
6675 00:25:00.270695 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6676 00:25:00.274348 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6677 00:25:00.274433 [Gating] SW calibration Done
6678 00:25:00.277356 ==
6679 00:25:00.280754 Dram Type= 6, Freq= 0, CH_1, rank 0
6680 00:25:00.284105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 00:25:00.284179 ==
6682 00:25:00.284266 RX Vref Scan: 0
6683 00:25:00.284344
6684 00:25:00.287576 RX Vref 0 -> 0, step: 1
6685 00:25:00.287663
6686 00:25:00.290674 RX Delay -410 -> 252, step: 16
6687 00:25:00.294443 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6688 00:25:00.297232 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6689 00:25:00.304191 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6690 00:25:00.307723 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6691 00:25:00.310793 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6692 00:25:00.314130 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6693 00:25:00.320943 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6694 00:25:00.324550 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6695 00:25:00.327595 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6696 00:25:00.331456 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6697 00:25:00.337572 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6698 00:25:00.340959 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6699 00:25:00.344684 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6700 00:25:00.347818 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6701 00:25:00.354383 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6702 00:25:00.358289 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6703 00:25:00.358358 ==
6704 00:25:00.361639 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 00:25:00.364496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 00:25:00.364590 ==
6707 00:25:00.367788 DQS Delay:
6708 00:25:00.367877 DQS0 = 51, DQS1 = 59
6709 00:25:00.367956 DQM Delay:
6710 00:25:00.371259 DQM0 = 19, DQM1 = 16
6711 00:25:00.371335 DQ Delay:
6712 00:25:00.374755 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6713 00:25:00.377788 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6714 00:25:00.381315 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6715 00:25:00.384697 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6716 00:25:00.384795
6717 00:25:00.384876
6718 00:25:00.384959 ==
6719 00:25:00.387636 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 00:25:00.391025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 00:25:00.394585 ==
6722 00:25:00.394657
6723 00:25:00.394736
6724 00:25:00.394817 TX Vref Scan disable
6725 00:25:00.397574 == TX Byte 0 ==
6726 00:25:00.401352 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6727 00:25:00.404488 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6728 00:25:00.408134 == TX Byte 1 ==
6729 00:25:00.411043 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 00:25:00.414874 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 00:25:00.414954 ==
6732 00:25:00.418309 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 00:25:00.421279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 00:25:00.424683 ==
6735 00:25:00.424774
6736 00:25:00.424853
6737 00:25:00.424930 TX Vref Scan disable
6738 00:25:00.428676 == TX Byte 0 ==
6739 00:25:00.431179 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6740 00:25:00.434526 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6741 00:25:00.437931 == TX Byte 1 ==
6742 00:25:00.441476 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 00:25:00.444699 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 00:25:00.444797
6745 00:25:00.444860 [DATLAT]
6746 00:25:00.448100 Freq=400, CH1 RK0
6747 00:25:00.448190
6748 00:25:00.451118 DATLAT Default: 0xf
6749 00:25:00.451237 0, 0xFFFF, sum = 0
6750 00:25:00.455193 1, 0xFFFF, sum = 0
6751 00:25:00.455270 2, 0xFFFF, sum = 0
6752 00:25:00.458275 3, 0xFFFF, sum = 0
6753 00:25:00.458361 4, 0xFFFF, sum = 0
6754 00:25:00.461176 5, 0xFFFF, sum = 0
6755 00:25:00.461262 6, 0xFFFF, sum = 0
6756 00:25:00.464744 7, 0xFFFF, sum = 0
6757 00:25:00.464855 8, 0xFFFF, sum = 0
6758 00:25:00.467768 9, 0xFFFF, sum = 0
6759 00:25:00.467885 10, 0xFFFF, sum = 0
6760 00:25:00.471316 11, 0xFFFF, sum = 0
6761 00:25:00.471418 12, 0xFFFF, sum = 0
6762 00:25:00.474425 13, 0x0, sum = 1
6763 00:25:00.474556 14, 0x0, sum = 2
6764 00:25:00.478232 15, 0x0, sum = 3
6765 00:25:00.478335 16, 0x0, sum = 4
6766 00:25:00.481278 best_step = 14
6767 00:25:00.481367
6768 00:25:00.481474 ==
6769 00:25:00.484438 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 00:25:00.488353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 00:25:00.488484 ==
6772 00:25:00.491196 RX Vref Scan: 1
6773 00:25:00.491295
6774 00:25:00.491384 RX Vref 0 -> 0, step: 1
6775 00:25:00.491471
6776 00:25:00.494668 RX Delay -359 -> 252, step: 8
6777 00:25:00.494772
6778 00:25:00.498094 Set Vref, RX VrefLevel [Byte0]: 59
6779 00:25:00.501325 [Byte1]: 50
6780 00:25:00.505595
6781 00:25:00.505670 Final RX Vref Byte 0 = 59 to rank0
6782 00:25:00.509308 Final RX Vref Byte 1 = 50 to rank0
6783 00:25:00.512759 Final RX Vref Byte 0 = 59 to rank1
6784 00:25:00.515487 Final RX Vref Byte 1 = 50 to rank1==
6785 00:25:00.519210 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 00:25:00.526129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 00:25:00.526214 ==
6788 00:25:00.526303 DQS Delay:
6789 00:25:00.526386 DQS0 = 52, DQS1 = 60
6790 00:25:00.528850 DQM Delay:
6791 00:25:00.528926 DQM0 = 16, DQM1 = 12
6792 00:25:00.532314 DQ Delay:
6793 00:25:00.535550 DQ0 =20, DQ1 =12, DQ2 =0, DQ3 =16
6794 00:25:00.535632 DQ4 =12, DQ5 =24, DQ6 =28, DQ7 =16
6795 00:25:00.539304 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6796 00:25:00.542930 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6797 00:25:00.543011
6798 00:25:00.543094
6799 00:25:00.552373 [DQSOSCAuto] RK0, (LSB)MR18= 0x8b32, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6800 00:25:00.556342 CH1 RK0: MR19=C0C, MR18=8B32
6801 00:25:00.562575 CH1_RK0: MR19=0xC0C, MR18=0x8B32, DQSOSC=392, MR23=63, INC=384, DEC=256
6802 00:25:00.562651 ==
6803 00:25:00.566007 Dram Type= 6, Freq= 0, CH_1, rank 1
6804 00:25:00.569147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 00:25:00.569223 ==
6806 00:25:00.572864 [Gating] SW mode calibration
6807 00:25:00.579278 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6808 00:25:00.582449 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6809 00:25:00.589354 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6810 00:25:00.592622 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6811 00:25:00.596011 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6812 00:25:00.602501 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 00:25:00.605880 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 00:25:00.609267 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 00:25:00.615766 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 00:25:00.619796 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 00:25:00.623008 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 00:25:00.625947 Total UI for P1: 0, mck2ui 16
6819 00:25:00.629397 best dqsien dly found for B0: ( 0, 14, 24)
6820 00:25:00.632885 Total UI for P1: 0, mck2ui 16
6821 00:25:00.636315 best dqsien dly found for B1: ( 0, 14, 24)
6822 00:25:00.639744 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6823 00:25:00.642620 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6824 00:25:00.642789
6825 00:25:00.648987 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6826 00:25:00.652543 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6827 00:25:00.652639 [Gating] SW calibration Done
6828 00:25:00.655825 ==
6829 00:25:00.659371 Dram Type= 6, Freq= 0, CH_1, rank 1
6830 00:25:00.662351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 00:25:00.662436 ==
6832 00:25:00.662496 RX Vref Scan: 0
6833 00:25:00.662553
6834 00:25:00.666157 RX Vref 0 -> 0, step: 1
6835 00:25:00.666226
6836 00:25:00.669301 RX Delay -410 -> 252, step: 16
6837 00:25:00.672649 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6838 00:25:00.675718 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6839 00:25:00.682320 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6840 00:25:00.685939 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6841 00:25:00.689170 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6842 00:25:00.692235 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6843 00:25:00.698956 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6844 00:25:00.702628 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6845 00:25:00.706154 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6846 00:25:00.708906 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6847 00:25:00.715810 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6848 00:25:00.719397 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6849 00:25:00.722273 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6850 00:25:00.725645 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6851 00:25:00.732622 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6852 00:25:00.735946 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6853 00:25:00.736018 ==
6854 00:25:00.739042 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 00:25:00.742432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 00:25:00.742500 ==
6857 00:25:00.745920 DQS Delay:
6858 00:25:00.746031 DQS0 = 51, DQS1 = 51
6859 00:25:00.749414 DQM Delay:
6860 00:25:00.749479 DQM0 = 17, DQM1 = 12
6861 00:25:00.749535 DQ Delay:
6862 00:25:00.752807 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6863 00:25:00.755805 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6864 00:25:00.759931 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6865 00:25:00.762777 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6866 00:25:00.762847
6867 00:25:00.762904
6868 00:25:00.762959 ==
6869 00:25:00.766144 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 00:25:00.772459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 00:25:00.772525 ==
6872 00:25:00.772582
6873 00:25:00.772636
6874 00:25:00.772719 TX Vref Scan disable
6875 00:25:00.775839 == TX Byte 0 ==
6876 00:25:00.779608 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6877 00:25:00.782826 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6878 00:25:00.786065 == TX Byte 1 ==
6879 00:25:00.789539 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6880 00:25:00.792935 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6881 00:25:00.793036 ==
6882 00:25:00.795967 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 00:25:00.802931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 00:25:00.803005 ==
6885 00:25:00.803065
6886 00:25:00.803121
6887 00:25:00.803176 TX Vref Scan disable
6888 00:25:00.805986 == TX Byte 0 ==
6889 00:25:00.809506 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6890 00:25:00.812549 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6891 00:25:00.816230 == TX Byte 1 ==
6892 00:25:00.819676 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6893 00:25:00.822692 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6894 00:25:00.822760
6895 00:25:00.825825 [DATLAT]
6896 00:25:00.825890 Freq=400, CH1 RK1
6897 00:25:00.825948
6898 00:25:00.829584 DATLAT Default: 0xe
6899 00:25:00.829650 0, 0xFFFF, sum = 0
6900 00:25:00.833074 1, 0xFFFF, sum = 0
6901 00:25:00.833143 2, 0xFFFF, sum = 0
6902 00:25:00.836360 3, 0xFFFF, sum = 0
6903 00:25:00.836429 4, 0xFFFF, sum = 0
6904 00:25:00.839881 5, 0xFFFF, sum = 0
6905 00:25:00.839949 6, 0xFFFF, sum = 0
6906 00:25:00.843142 7, 0xFFFF, sum = 0
6907 00:25:00.843215 8, 0xFFFF, sum = 0
6908 00:25:00.846143 9, 0xFFFF, sum = 0
6909 00:25:00.846218 10, 0xFFFF, sum = 0
6910 00:25:00.849676 11, 0xFFFF, sum = 0
6911 00:25:00.849748 12, 0xFFFF, sum = 0
6912 00:25:00.853410 13, 0x0, sum = 1
6913 00:25:00.853480 14, 0x0, sum = 2
6914 00:25:00.856062 15, 0x0, sum = 3
6915 00:25:00.856127 16, 0x0, sum = 4
6916 00:25:00.859922 best_step = 14
6917 00:25:00.859986
6918 00:25:00.860043 ==
6919 00:25:00.863232 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 00:25:00.866562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 00:25:00.866626 ==
6922 00:25:00.866683 RX Vref Scan: 0
6923 00:25:00.869784
6924 00:25:00.869846 RX Vref 0 -> 0, step: 1
6925 00:25:00.869902
6926 00:25:00.872787 RX Delay -343 -> 252, step: 8
6927 00:25:00.880626 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6928 00:25:00.883949 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6929 00:25:00.887259 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6930 00:25:00.890678 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6931 00:25:00.897287 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6932 00:25:00.900739 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6933 00:25:00.903941 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6934 00:25:00.907662 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6935 00:25:00.913811 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6936 00:25:00.917057 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6937 00:25:00.920251 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6938 00:25:00.923886 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6939 00:25:00.930392 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6940 00:25:00.934077 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6941 00:25:00.937024 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6942 00:25:00.940312 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6943 00:25:00.943576 ==
6944 00:25:00.947253 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 00:25:00.950244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 00:25:00.950312 ==
6947 00:25:00.950375 DQS Delay:
6948 00:25:00.953981 DQS0 = 52, DQS1 = 60
6949 00:25:00.954045 DQM Delay:
6950 00:25:00.956912 DQM0 = 13, DQM1 = 13
6951 00:25:00.956986 DQ Delay:
6952 00:25:00.960263 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6953 00:25:00.963861 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6954 00:25:00.967221 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6955 00:25:00.970269 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6956 00:25:00.970339
6957 00:25:00.970399
6958 00:25:00.977787 [DQSOSCAuto] RK1, (LSB)MR18= 0x7d94, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 394 ps
6959 00:25:00.980741 CH1 RK1: MR19=C0C, MR18=7D94
6960 00:25:00.987364 CH1_RK1: MR19=0xC0C, MR18=0x7D94, DQSOSC=391, MR23=63, INC=386, DEC=257
6961 00:25:00.990327 [RxdqsGatingPostProcess] freq 400
6962 00:25:00.993850 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6963 00:25:00.997583 best DQS0 dly(2T, 0.5T) = (0, 10)
6964 00:25:01.000946 best DQS1 dly(2T, 0.5T) = (0, 10)
6965 00:25:01.003952 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6966 00:25:01.007528 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6967 00:25:01.010664 best DQS0 dly(2T, 0.5T) = (0, 10)
6968 00:25:01.014442 best DQS1 dly(2T, 0.5T) = (0, 10)
6969 00:25:01.017410 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6970 00:25:01.020829 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6971 00:25:01.024421 Pre-setting of DQS Precalculation
6972 00:25:01.027554 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6973 00:25:01.034316 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6974 00:25:01.044120 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6975 00:25:01.044197
6976 00:25:01.044260
6977 00:25:01.044318 [Calibration Summary] 800 Mbps
6978 00:25:01.047616 CH 0, Rank 0
6979 00:25:01.051013 SW Impedance : PASS
6980 00:25:01.051080 DUTY Scan : NO K
6981 00:25:01.054294 ZQ Calibration : PASS
6982 00:25:01.054358 Jitter Meter : NO K
6983 00:25:01.057813 CBT Training : PASS
6984 00:25:01.060887 Write leveling : PASS
6985 00:25:01.060954 RX DQS gating : PASS
6986 00:25:01.064352 RX DQ/DQS(RDDQC) : PASS
6987 00:25:01.067518 TX DQ/DQS : PASS
6988 00:25:01.067586 RX DATLAT : PASS
6989 00:25:01.071240 RX DQ/DQS(Engine): PASS
6990 00:25:01.075026 TX OE : NO K
6991 00:25:01.075111 All Pass.
6992 00:25:01.075215
6993 00:25:01.075273 CH 0, Rank 1
6994 00:25:01.077530 SW Impedance : PASS
6995 00:25:01.080806 DUTY Scan : NO K
6996 00:25:01.080871 ZQ Calibration : PASS
6997 00:25:01.084554 Jitter Meter : NO K
6998 00:25:01.084651 CBT Training : PASS
6999 00:25:01.087739 Write leveling : NO K
7000 00:25:01.091206 RX DQS gating : PASS
7001 00:25:01.091274 RX DQ/DQS(RDDQC) : PASS
7002 00:25:01.094908 TX DQ/DQS : PASS
7003 00:25:01.098042 RX DATLAT : PASS
7004 00:25:01.098108 RX DQ/DQS(Engine): PASS
7005 00:25:01.101108 TX OE : NO K
7006 00:25:01.101172 All Pass.
7007 00:25:01.101228
7008 00:25:01.104673 CH 1, Rank 0
7009 00:25:01.104771 SW Impedance : PASS
7010 00:25:01.107816 DUTY Scan : NO K
7011 00:25:01.111178 ZQ Calibration : PASS
7012 00:25:01.111246 Jitter Meter : NO K
7013 00:25:01.115020 CBT Training : PASS
7014 00:25:01.117873 Write leveling : PASS
7015 00:25:01.117938 RX DQS gating : PASS
7016 00:25:01.121335 RX DQ/DQS(RDDQC) : PASS
7017 00:25:01.121402 TX DQ/DQS : PASS
7018 00:25:01.124893 RX DATLAT : PASS
7019 00:25:01.127883 RX DQ/DQS(Engine): PASS
7020 00:25:01.127948 TX OE : NO K
7021 00:25:01.131329 All Pass.
7022 00:25:01.131422
7023 00:25:01.131506 CH 1, Rank 1
7024 00:25:01.134548 SW Impedance : PASS
7025 00:25:01.134614 DUTY Scan : NO K
7026 00:25:01.137990 ZQ Calibration : PASS
7027 00:25:01.141116 Jitter Meter : NO K
7028 00:25:01.141186 CBT Training : PASS
7029 00:25:01.144939 Write leveling : NO K
7030 00:25:01.147927 RX DQS gating : PASS
7031 00:25:01.147996 RX DQ/DQS(RDDQC) : PASS
7032 00:25:01.151541 TX DQ/DQS : PASS
7033 00:25:01.154679 RX DATLAT : PASS
7034 00:25:01.154753 RX DQ/DQS(Engine): PASS
7035 00:25:01.158270 TX OE : NO K
7036 00:25:01.158338 All Pass.
7037 00:25:01.158395
7038 00:25:01.161404 DramC Write-DBI off
7039 00:25:01.164821 PER_BANK_REFRESH: Hybrid Mode
7040 00:25:01.164886 TX_TRACKING: ON
7041 00:25:01.175282 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7042 00:25:01.178033 [FAST_K] Save calibration result to emmc
7043 00:25:01.181820 dramc_set_vcore_voltage set vcore to 725000
7044 00:25:01.181886 Read voltage for 1600, 0
7045 00:25:01.185035 Vio18 = 0
7046 00:25:01.185100 Vcore = 725000
7047 00:25:01.185158 Vdram = 0
7048 00:25:01.188145 Vddq = 0
7049 00:25:01.188208 Vmddr = 0
7050 00:25:01.191776 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7051 00:25:01.198495 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7052 00:25:01.201690 MEM_TYPE=3, freq_sel=13
7053 00:25:01.205066 sv_algorithm_assistance_LP4_3733
7054 00:25:01.208251 ============ PULL DRAM RESETB DOWN ============
7055 00:25:01.211977 ========== PULL DRAM RESETB DOWN end =========
7056 00:25:01.218518 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7057 00:25:01.218587 ===================================
7058 00:25:01.221659 LPDDR4 DRAM CONFIGURATION
7059 00:25:01.225277 ===================================
7060 00:25:01.228305 EX_ROW_EN[0] = 0x0
7061 00:25:01.228397 EX_ROW_EN[1] = 0x0
7062 00:25:01.231918 LP4Y_EN = 0x0
7063 00:25:01.231994 WORK_FSP = 0x1
7064 00:25:01.235307 WL = 0x5
7065 00:25:01.235371 RL = 0x5
7066 00:25:01.238939 BL = 0x2
7067 00:25:01.239006 RPST = 0x0
7068 00:25:01.241844 RD_PRE = 0x0
7069 00:25:01.241908 WR_PRE = 0x1
7070 00:25:01.244888 WR_PST = 0x1
7071 00:25:01.248477 DBI_WR = 0x0
7072 00:25:01.248543 DBI_RD = 0x0
7073 00:25:01.252019 OTF = 0x1
7074 00:25:01.255033 ===================================
7075 00:25:01.258728 ===================================
7076 00:25:01.258795 ANA top config
7077 00:25:01.261652 ===================================
7078 00:25:01.265024 DLL_ASYNC_EN = 0
7079 00:25:01.265090 ALL_SLAVE_EN = 0
7080 00:25:01.268546 NEW_RANK_MODE = 1
7081 00:25:01.271805 DLL_IDLE_MODE = 1
7082 00:25:01.275223 LP45_APHY_COMB_EN = 1
7083 00:25:01.278214 TX_ODT_DIS = 0
7084 00:25:01.278281 NEW_8X_MODE = 1
7085 00:25:01.281782 ===================================
7086 00:25:01.285481 ===================================
7087 00:25:01.288413 data_rate = 3200
7088 00:25:01.292040 CKR = 1
7089 00:25:01.295234 DQ_P2S_RATIO = 8
7090 00:25:01.298505 ===================================
7091 00:25:01.302261 CA_P2S_RATIO = 8
7092 00:25:01.302327 DQ_CA_OPEN = 0
7093 00:25:01.305319 DQ_SEMI_OPEN = 0
7094 00:25:01.308448 CA_SEMI_OPEN = 0
7095 00:25:01.311972 CA_FULL_RATE = 0
7096 00:25:01.315476 DQ_CKDIV4_EN = 0
7097 00:25:01.318653 CA_CKDIV4_EN = 0
7098 00:25:01.318719 CA_PREDIV_EN = 0
7099 00:25:01.321885 PH8_DLY = 12
7100 00:25:01.325330 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7101 00:25:01.328821 DQ_AAMCK_DIV = 4
7102 00:25:01.332084 CA_AAMCK_DIV = 4
7103 00:25:01.335506 CA_ADMCK_DIV = 4
7104 00:25:01.335573 DQ_TRACK_CA_EN = 0
7105 00:25:01.339198 CA_PICK = 1600
7106 00:25:01.342022 CA_MCKIO = 1600
7107 00:25:01.345537 MCKIO_SEMI = 0
7108 00:25:01.348992 PLL_FREQ = 3068
7109 00:25:01.352468 DQ_UI_PI_RATIO = 32
7110 00:25:01.355626 CA_UI_PI_RATIO = 0
7111 00:25:01.359038 ===================================
7112 00:25:01.362785 ===================================
7113 00:25:01.362853 memory_type:LPDDR4
7114 00:25:01.365860 GP_NUM : 10
7115 00:25:01.365926 SRAM_EN : 1
7116 00:25:01.368661 MD32_EN : 0
7117 00:25:01.372314 ===================================
7118 00:25:01.375495 [ANA_INIT] >>>>>>>>>>>>>>
7119 00:25:01.379251 <<<<<< [CONFIGURE PHASE]: ANA_TX
7120 00:25:01.382234 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7121 00:25:01.385459 ===================================
7122 00:25:01.385549 data_rate = 3200,PCW = 0X7600
7123 00:25:01.388908 ===================================
7124 00:25:01.392489 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7125 00:25:01.398860 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7126 00:25:01.405660 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7127 00:25:01.408989 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7128 00:25:01.413072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7129 00:25:01.415835 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7130 00:25:01.418827 [ANA_INIT] flow start
7131 00:25:01.418898 [ANA_INIT] PLL >>>>>>>>
7132 00:25:01.422447 [ANA_INIT] PLL <<<<<<<<
7133 00:25:01.425811 [ANA_INIT] MIDPI >>>>>>>>
7134 00:25:01.429100 [ANA_INIT] MIDPI <<<<<<<<
7135 00:25:01.429167 [ANA_INIT] DLL >>>>>>>>
7136 00:25:01.432393 [ANA_INIT] DLL <<<<<<<<
7137 00:25:01.435673 [ANA_INIT] flow end
7138 00:25:01.438918 ============ LP4 DIFF to SE enter ============
7139 00:25:01.442759 ============ LP4 DIFF to SE exit ============
7140 00:25:01.445707 [ANA_INIT] <<<<<<<<<<<<<
7141 00:25:01.448995 [Flow] Enable top DCM control >>>>>
7142 00:25:01.452363 [Flow] Enable top DCM control <<<<<
7143 00:25:01.455680 Enable DLL master slave shuffle
7144 00:25:01.459269 ==============================================================
7145 00:25:01.462730 Gating Mode config
7146 00:25:01.465531 ==============================================================
7147 00:25:01.469108 Config description:
7148 00:25:01.479418 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7149 00:25:01.485833 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7150 00:25:01.489294 SELPH_MODE 0: By rank 1: By Phase
7151 00:25:01.495963 ==============================================================
7152 00:25:01.498940 GAT_TRACK_EN = 1
7153 00:25:01.502525 RX_GATING_MODE = 2
7154 00:25:01.505773 RX_GATING_TRACK_MODE = 2
7155 00:25:01.505845 SELPH_MODE = 1
7156 00:25:01.509417 PICG_EARLY_EN = 1
7157 00:25:01.512837 VALID_LAT_VALUE = 1
7158 00:25:01.519286 ==============================================================
7159 00:25:01.522553 Enter into Gating configuration >>>>
7160 00:25:01.526220 Exit from Gating configuration <<<<
7161 00:25:01.529808 Enter into DVFS_PRE_config >>>>>
7162 00:25:01.539562 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7163 00:25:01.542773 Exit from DVFS_PRE_config <<<<<
7164 00:25:01.546082 Enter into PICG configuration >>>>
7165 00:25:01.549881 Exit from PICG configuration <<<<
7166 00:25:01.552662 [RX_INPUT] configuration >>>>>
7167 00:25:01.556172 [RX_INPUT] configuration <<<<<
7168 00:25:01.559543 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7169 00:25:01.566279 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7170 00:25:01.572619 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7171 00:25:01.579269 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7172 00:25:01.583261 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7173 00:25:01.589442 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7174 00:25:01.592927 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7175 00:25:01.599471 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7176 00:25:01.603150 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7177 00:25:01.606085 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7178 00:25:01.609274 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7179 00:25:01.616210 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7180 00:25:01.619281 ===================================
7181 00:25:01.619350 LPDDR4 DRAM CONFIGURATION
7182 00:25:01.623165 ===================================
7183 00:25:01.626438 EX_ROW_EN[0] = 0x0
7184 00:25:01.629357 EX_ROW_EN[1] = 0x0
7185 00:25:01.629422 LP4Y_EN = 0x0
7186 00:25:01.632632 WORK_FSP = 0x1
7187 00:25:01.632749 WL = 0x5
7188 00:25:01.636209 RL = 0x5
7189 00:25:01.636278 BL = 0x2
7190 00:25:01.639127 RPST = 0x0
7191 00:25:01.639209 RD_PRE = 0x0
7192 00:25:01.642518 WR_PRE = 0x1
7193 00:25:01.642586 WR_PST = 0x1
7194 00:25:01.645713 DBI_WR = 0x0
7195 00:25:01.645826 DBI_RD = 0x0
7196 00:25:01.649926 OTF = 0x1
7197 00:25:01.652871 ===================================
7198 00:25:01.655914 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7199 00:25:01.659471 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7200 00:25:01.666422 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7201 00:25:01.669590 ===================================
7202 00:25:01.669662 LPDDR4 DRAM CONFIGURATION
7203 00:25:01.672516 ===================================
7204 00:25:01.676284 EX_ROW_EN[0] = 0x10
7205 00:25:01.676377 EX_ROW_EN[1] = 0x0
7206 00:25:01.679185 LP4Y_EN = 0x0
7207 00:25:01.682512 WORK_FSP = 0x1
7208 00:25:01.682595 WL = 0x5
7209 00:25:01.685730 RL = 0x5
7210 00:25:01.685799 BL = 0x2
7211 00:25:01.689156 RPST = 0x0
7212 00:25:01.689219 RD_PRE = 0x0
7213 00:25:01.693115 WR_PRE = 0x1
7214 00:25:01.693181 WR_PST = 0x1
7215 00:25:01.696225 DBI_WR = 0x0
7216 00:25:01.696290 DBI_RD = 0x0
7217 00:25:01.699221 OTF = 0x1
7218 00:25:01.702860 ===================================
7219 00:25:01.706387 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7220 00:25:01.709290 ==
7221 00:25:01.712976 Dram Type= 6, Freq= 0, CH_0, rank 0
7222 00:25:01.716278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7223 00:25:01.716345 ==
7224 00:25:01.719345 [Duty_Offset_Calibration]
7225 00:25:01.719414 B0:2 B1:-1 CA:1
7226 00:25:01.719472
7227 00:25:01.722743 [DutyScan_Calibration_Flow] k_type=0
7228 00:25:01.731977
7229 00:25:01.732054 ==CLK 0==
7230 00:25:01.735336 Final CLK duty delay cell = -4
7231 00:25:01.738474 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7232 00:25:01.741902 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7233 00:25:01.745135 [-4] AVG Duty = 4937%(X100)
7234 00:25:01.745201
7235 00:25:01.748582 CH0 CLK Duty spec in!! Max-Min= 187%
7236 00:25:01.752222 [DutyScan_Calibration_Flow] ====Done====
7237 00:25:01.752291
7238 00:25:01.754875 [DutyScan_Calibration_Flow] k_type=1
7239 00:25:01.771560
7240 00:25:01.771636 ==DQS 0 ==
7241 00:25:01.774791 Final DQS duty delay cell = 0
7242 00:25:01.778041 [0] MAX Duty = 5125%(X100), DQS PI = 20
7243 00:25:01.781384 [0] MIN Duty = 5000%(X100), DQS PI = 14
7244 00:25:01.781451 [0] AVG Duty = 5062%(X100)
7245 00:25:01.785178
7246 00:25:01.785244 ==DQS 1 ==
7247 00:25:01.787971 Final DQS duty delay cell = -4
7248 00:25:01.791388 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7249 00:25:01.794685 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7250 00:25:01.798173 [-4] AVG Duty = 5046%(X100)
7251 00:25:01.798237
7252 00:25:01.801375 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7253 00:25:01.801454
7254 00:25:01.804917 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7255 00:25:01.808422 [DutyScan_Calibration_Flow] ====Done====
7256 00:25:01.808516
7257 00:25:01.811288 [DutyScan_Calibration_Flow] k_type=3
7258 00:25:01.828907
7259 00:25:01.828982 ==DQM 0 ==
7260 00:25:01.831854 Final DQM duty delay cell = 0
7261 00:25:01.835230 [0] MAX Duty = 5000%(X100), DQS PI = 18
7262 00:25:01.838445 [0] MIN Duty = 4875%(X100), DQS PI = 6
7263 00:25:01.838517 [0] AVG Duty = 4937%(X100)
7264 00:25:01.842182
7265 00:25:01.842279 ==DQM 1 ==
7266 00:25:01.845217 Final DQM duty delay cell = 0
7267 00:25:01.848814 [0] MAX Duty = 5187%(X100), DQS PI = 58
7268 00:25:01.851871 [0] MIN Duty = 4969%(X100), DQS PI = 18
7269 00:25:01.851937 [0] AVG Duty = 5078%(X100)
7270 00:25:01.855895
7271 00:25:01.858745 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7272 00:25:01.858810
7273 00:25:01.862237 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7274 00:25:01.865811 [DutyScan_Calibration_Flow] ====Done====
7275 00:25:01.865879
7276 00:25:01.868589 [DutyScan_Calibration_Flow] k_type=2
7277 00:25:01.885073
7278 00:25:01.885148 ==DQ 0 ==
7279 00:25:01.888238 Final DQ duty delay cell = -4
7280 00:25:01.891517 [-4] MAX Duty = 5031%(X100), DQS PI = 56
7281 00:25:01.894666 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7282 00:25:01.898411 [-4] AVG Duty = 4937%(X100)
7283 00:25:01.898476
7284 00:25:01.898534 ==DQ 1 ==
7285 00:25:01.901415 Final DQ duty delay cell = 0
7286 00:25:01.905156 [0] MAX Duty = 5000%(X100), DQS PI = 0
7287 00:25:01.908661 [0] MIN Duty = 4938%(X100), DQS PI = 10
7288 00:25:01.908768 [0] AVG Duty = 4969%(X100)
7289 00:25:01.911524
7290 00:25:01.914802 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7291 00:25:01.914870
7292 00:25:01.918369 CH0 DQ 1 Duty spec in!! Max-Min= 62%
7293 00:25:01.921720 [DutyScan_Calibration_Flow] ====Done====
7294 00:25:01.921788 ==
7295 00:25:01.924816 Dram Type= 6, Freq= 0, CH_1, rank 0
7296 00:25:01.928336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7297 00:25:01.928406 ==
7298 00:25:01.931501 [Duty_Offset_Calibration]
7299 00:25:01.931581 B0:1 B1:1 CA:2
7300 00:25:01.931636
7301 00:25:01.934952 [DutyScan_Calibration_Flow] k_type=0
7302 00:25:01.945295
7303 00:25:01.945390 ==CLK 0==
7304 00:25:01.948385 Final CLK duty delay cell = 0
7305 00:25:01.952100 [0] MAX Duty = 5187%(X100), DQS PI = 24
7306 00:25:01.955354 [0] MIN Duty = 4938%(X100), DQS PI = 50
7307 00:25:01.955453 [0] AVG Duty = 5062%(X100)
7308 00:25:01.959017
7309 00:25:01.962179 CH1 CLK Duty spec in!! Max-Min= 249%
7310 00:25:01.965163 [DutyScan_Calibration_Flow] ====Done====
7311 00:25:01.965231
7312 00:25:01.968606 [DutyScan_Calibration_Flow] k_type=1
7313 00:25:01.985270
7314 00:25:01.985346 ==DQS 0 ==
7315 00:25:01.988395 Final DQS duty delay cell = 0
7316 00:25:01.991780 [0] MAX Duty = 5062%(X100), DQS PI = 22
7317 00:25:01.994855 [0] MIN Duty = 4813%(X100), DQS PI = 50
7318 00:25:01.998389 [0] AVG Duty = 4937%(X100)
7319 00:25:01.998455
7320 00:25:01.998513 ==DQS 1 ==
7321 00:25:02.001879 Final DQS duty delay cell = 0
7322 00:25:02.004973 [0] MAX Duty = 5031%(X100), DQS PI = 34
7323 00:25:02.008197 [0] MIN Duty = 4938%(X100), DQS PI = 14
7324 00:25:02.011564 [0] AVG Duty = 4984%(X100)
7325 00:25:02.011628
7326 00:25:02.015280 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7327 00:25:02.015350
7328 00:25:02.018752 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7329 00:25:02.021766 [DutyScan_Calibration_Flow] ====Done====
7330 00:25:02.021832
7331 00:25:02.024877 [DutyScan_Calibration_Flow] k_type=3
7332 00:25:02.041640
7333 00:25:02.041718 ==DQM 0 ==
7334 00:25:02.045394 Final DQM duty delay cell = 0
7335 00:25:02.048439 [0] MAX Duty = 5156%(X100), DQS PI = 20
7336 00:25:02.051934 [0] MIN Duty = 4844%(X100), DQS PI = 50
7337 00:25:02.055084 [0] AVG Duty = 5000%(X100)
7338 00:25:02.055162
7339 00:25:02.055222 ==DQM 1 ==
7340 00:25:02.058610 Final DQM duty delay cell = 0
7341 00:25:02.061746 [0] MAX Duty = 5125%(X100), DQS PI = 10
7342 00:25:02.065371 [0] MIN Duty = 4907%(X100), DQS PI = 20
7343 00:25:02.065445 [0] AVG Duty = 5016%(X100)
7344 00:25:02.068410
7345 00:25:02.072260 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7346 00:25:02.072331
7347 00:25:02.076028 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7348 00:25:02.078469 [DutyScan_Calibration_Flow] ====Done====
7349 00:25:02.078540
7350 00:25:02.081822 [DutyScan_Calibration_Flow] k_type=2
7351 00:25:02.098554
7352 00:25:02.098627 ==DQ 0 ==
7353 00:25:02.101855 Final DQ duty delay cell = 0
7354 00:25:02.105513 [0] MAX Duty = 5187%(X100), DQS PI = 20
7355 00:25:02.108981 [0] MIN Duty = 4938%(X100), DQS PI = 52
7356 00:25:02.109049 [0] AVG Duty = 5062%(X100)
7357 00:25:02.111817
7358 00:25:02.111900 ==DQ 1 ==
7359 00:25:02.115545 Final DQ duty delay cell = 0
7360 00:25:02.118878 [0] MAX Duty = 5093%(X100), DQS PI = 6
7361 00:25:02.121995 [0] MIN Duty = 5031%(X100), DQS PI = 0
7362 00:25:02.122062 [0] AVG Duty = 5062%(X100)
7363 00:25:02.122118
7364 00:25:02.125303 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7365 00:25:02.125379
7366 00:25:02.128857 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7367 00:25:02.135879 [DutyScan_Calibration_Flow] ====Done====
7368 00:25:02.138789 nWR fixed to 30
7369 00:25:02.138858 [ModeRegInit_LP4] CH0 RK0
7370 00:25:02.142096 [ModeRegInit_LP4] CH0 RK1
7371 00:25:02.145474 [ModeRegInit_LP4] CH1 RK0
7372 00:25:02.145541 [ModeRegInit_LP4] CH1 RK1
7373 00:25:02.148438 match AC timing 5
7374 00:25:02.151886 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7375 00:25:02.155542 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7376 00:25:02.161948 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7377 00:25:02.165588 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7378 00:25:02.172039 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7379 00:25:02.172110 [MiockJmeterHQA]
7380 00:25:02.172170
7381 00:25:02.175498 [DramcMiockJmeter] u1RxGatingPI = 0
7382 00:25:02.175569 0 : 4368, 4142
7383 00:25:02.178687 4 : 4252, 4027
7384 00:25:02.178759 8 : 4255, 4029
7385 00:25:02.182302 12 : 4252, 4027
7386 00:25:02.182373 16 : 4252, 4027
7387 00:25:02.185218 20 : 4253, 4027
7388 00:25:02.185293 24 : 4252, 4027
7389 00:25:02.185353 28 : 4257, 4029
7390 00:25:02.188552 32 : 4252, 4027
7391 00:25:02.188644 36 : 4252, 4027
7392 00:25:02.191949 40 : 4255, 4029
7393 00:25:02.192018 44 : 4255, 4029
7394 00:25:02.195979 48 : 4370, 4142
7395 00:25:02.196044 52 : 4365, 4140
7396 00:25:02.198892 56 : 4252, 4027
7397 00:25:02.198957 60 : 4254, 4029
7398 00:25:02.199014 64 : 4257, 4029
7399 00:25:02.202135 68 : 4259, 4034
7400 00:25:02.202199 72 : 4250, 4026
7401 00:25:02.205428 76 : 4360, 4138
7402 00:25:02.205493 80 : 4249, 4027
7403 00:25:02.209067 84 : 4252, 4029
7404 00:25:02.209137 88 : 4254, 4032
7405 00:25:02.209196 92 : 4250, 4027
7406 00:25:02.211927 96 : 4361, 3331
7407 00:25:02.211992 100 : 4252, 0
7408 00:25:02.215577 104 : 4252, 0
7409 00:25:02.215644 108 : 4255, 0
7410 00:25:02.215701 112 : 4250, 0
7411 00:25:02.219001 116 : 4252, 0
7412 00:25:02.219065 120 : 4252, 0
7413 00:25:02.222912 124 : 4365, 0
7414 00:25:02.222977 128 : 4253, 0
7415 00:25:02.223033 132 : 4360, 0
7416 00:25:02.225444 136 : 4252, 0
7417 00:25:02.225507 140 : 4252, 0
7418 00:25:02.228991 144 : 4255, 0
7419 00:25:02.229058 148 : 4250, 0
7420 00:25:02.229115 152 : 4250, 0
7421 00:25:02.232319 156 : 4250, 0
7422 00:25:02.232385 160 : 4363, 0
7423 00:25:02.235130 164 : 4254, 0
7424 00:25:02.235202 168 : 4363, 0
7425 00:25:02.235261 172 : 4250, 0
7426 00:25:02.238790 176 : 4250, 0
7427 00:25:02.238866 180 : 4250, 0
7428 00:25:02.238926 184 : 4250, 0
7429 00:25:02.242461 188 : 4255, 0
7430 00:25:02.242529 192 : 4257, 0
7431 00:25:02.245350 196 : 4363, 0
7432 00:25:02.245415 200 : 4250, 0
7433 00:25:02.245472 204 : 4363, 0
7434 00:25:02.248972 208 : 4360, 0
7435 00:25:02.249037 212 : 4250, 153
7436 00:25:02.252347 216 : 4255, 3497
7437 00:25:02.252440 220 : 4368, 4145
7438 00:25:02.255324 224 : 4252, 4029
7439 00:25:02.255392 228 : 4254, 4030
7440 00:25:02.259223 232 : 4255, 4029
7441 00:25:02.259288 236 : 4249, 4027
7442 00:25:02.259344 240 : 4365, 4139
7443 00:25:02.261901 244 : 4363, 4139
7444 00:25:02.261967 248 : 4363, 4139
7445 00:25:02.265519 252 : 4249, 4027
7446 00:25:02.265593 256 : 4250, 4027
7447 00:25:02.268943 260 : 4252, 4029
7448 00:25:02.269015 264 : 4252, 4029
7449 00:25:02.272047 268 : 4250, 4027
7450 00:25:02.272113 272 : 4361, 4137
7451 00:25:02.275429 276 : 4363, 4140
7452 00:25:02.275495 280 : 4363, 4140
7453 00:25:02.278911 284 : 4252, 4029
7454 00:25:02.278978 288 : 4250, 4027
7455 00:25:02.281962 292 : 4365, 4140
7456 00:25:02.282037 296 : 4255, 4029
7457 00:25:02.282100 300 : 4363, 4140
7458 00:25:02.285521 304 : 4249, 4027
7459 00:25:02.285621 308 : 4255, 4029
7460 00:25:02.288895 312 : 4250, 4027
7461 00:25:02.288964 316 : 4255, 4029
7462 00:25:02.292207 320 : 4252, 4030
7463 00:25:02.292278 324 : 4250, 4027
7464 00:25:02.295502 328 : 4255, 4029
7465 00:25:02.295571 332 : 4253, 2842
7466 00:25:02.298877 336 : 4363, 74
7467 00:25:02.298943
7468 00:25:02.298999 MIOCK jitter meter ch=0
7469 00:25:02.299052
7470 00:25:02.302204 1T = (336-100) = 236 dly cells
7471 00:25:02.308806 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7472 00:25:02.308874 ==
7473 00:25:02.312045 Dram Type= 6, Freq= 0, CH_0, rank 0
7474 00:25:02.315545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7475 00:25:02.315617 ==
7476 00:25:02.322408 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7477 00:25:02.325447 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7478 00:25:02.329400 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7479 00:25:02.335833 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7480 00:25:02.345024 [CA 0] Center 44 (14~75) winsize 62
7481 00:25:02.348588 [CA 1] Center 43 (13~74) winsize 62
7482 00:25:02.351777 [CA 2] Center 39 (10~68) winsize 59
7483 00:25:02.355132 [CA 3] Center 39 (10~68) winsize 59
7484 00:25:02.358358 [CA 4] Center 37 (7~67) winsize 61
7485 00:25:02.361768 [CA 5] Center 37 (7~67) winsize 61
7486 00:25:02.361836
7487 00:25:02.365140 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7488 00:25:02.365213
7489 00:25:02.368130 [CATrainingPosCal] consider 1 rank data
7490 00:25:02.371647 u2DelayCellTimex100 = 275/100 ps
7491 00:25:02.375314 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7492 00:25:02.381745 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7493 00:25:02.385112 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7494 00:25:02.388326 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7495 00:25:02.392054 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7496 00:25:02.395226 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7497 00:25:02.395323
7498 00:25:02.398393 CA PerBit enable=1, Macro0, CA PI delay=37
7499 00:25:02.398461
7500 00:25:02.401862 [CBTSetCACLKResult] CA Dly = 37
7501 00:25:02.405144 CS Dly: 11 (0~42)
7502 00:25:02.408598 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7503 00:25:02.412095 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7504 00:25:02.412162 ==
7505 00:25:02.415023 Dram Type= 6, Freq= 0, CH_0, rank 1
7506 00:25:02.418219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7507 00:25:02.421841 ==
7508 00:25:02.425019 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7509 00:25:02.428332 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7510 00:25:02.435303 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7511 00:25:02.438487 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7512 00:25:02.448653 [CA 0] Center 43 (13~74) winsize 62
7513 00:25:02.452419 [CA 1] Center 43 (13~74) winsize 62
7514 00:25:02.455731 [CA 2] Center 39 (10~69) winsize 60
7515 00:25:02.458684 [CA 3] Center 38 (9~68) winsize 60
7516 00:25:02.462466 [CA 4] Center 37 (7~67) winsize 61
7517 00:25:02.465750 [CA 5] Center 37 (7~67) winsize 61
7518 00:25:02.465824
7519 00:25:02.468979 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7520 00:25:02.469058
7521 00:25:02.472279 [CATrainingPosCal] consider 2 rank data
7522 00:25:02.475838 u2DelayCellTimex100 = 275/100 ps
7523 00:25:02.478886 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7524 00:25:02.486021 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7525 00:25:02.489117 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7526 00:25:02.492387 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7527 00:25:02.495653 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7528 00:25:02.499100 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7529 00:25:02.499180
7530 00:25:02.502398 CA PerBit enable=1, Macro0, CA PI delay=37
7531 00:25:02.502470
7532 00:25:02.505768 [CBTSetCACLKResult] CA Dly = 37
7533 00:25:02.505877 CS Dly: 11 (0~43)
7534 00:25:02.512348 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7535 00:25:02.515625 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7536 00:25:02.515699
7537 00:25:02.519187 ----->DramcWriteLeveling(PI) begin...
7538 00:25:02.519316 ==
7539 00:25:02.522467 Dram Type= 6, Freq= 0, CH_0, rank 0
7540 00:25:02.526387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 00:25:02.526490 ==
7542 00:25:02.529546 Write leveling (Byte 0): 34 => 34
7543 00:25:02.532771 Write leveling (Byte 1): 28 => 28
7544 00:25:02.536312 DramcWriteLeveling(PI) end<-----
7545 00:25:02.536409
7546 00:25:02.536496 ==
7547 00:25:02.539374 Dram Type= 6, Freq= 0, CH_0, rank 0
7548 00:25:02.542388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7549 00:25:02.546033 ==
7550 00:25:02.546128 [Gating] SW mode calibration
7551 00:25:02.552808 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7552 00:25:02.559254 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7553 00:25:02.562927 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7554 00:25:02.569410 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7555 00:25:02.572756 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7556 00:25:02.576218 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7557 00:25:02.582959 1 4 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7558 00:25:02.585987 1 4 20 | B1->B0 | 2323 3131 | 1 1 | (1 1) (1 1)
7559 00:25:02.589632 1 4 24 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
7560 00:25:02.596551 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7561 00:25:02.599530 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7562 00:25:02.602983 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7563 00:25:02.606349 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7564 00:25:02.613058 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7565 00:25:02.615945 1 5 16 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
7566 00:25:02.619229 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7567 00:25:02.626009 1 5 24 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
7568 00:25:02.629733 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 00:25:02.632768 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 00:25:02.639660 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 00:25:02.642520 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7572 00:25:02.646136 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7573 00:25:02.652575 1 6 16 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
7574 00:25:02.656311 1 6 20 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
7575 00:25:02.659907 1 6 24 | B1->B0 | 4040 4646 | 1 0 | (1 1) (0 0)
7576 00:25:02.666346 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 00:25:02.669403 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7578 00:25:02.672640 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7579 00:25:02.679597 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7580 00:25:02.682714 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7581 00:25:02.686094 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 00:25:02.692755 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7583 00:25:02.696059 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7584 00:25:02.699251 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 00:25:02.702847 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 00:25:02.709405 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 00:25:02.712754 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 00:25:02.716043 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 00:25:02.722822 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 00:25:02.726137 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 00:25:02.729835 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 00:25:02.736157 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 00:25:02.740006 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 00:25:02.742567 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 00:25:02.749531 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 00:25:02.752605 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 00:25:02.756205 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7598 00:25:02.763143 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7599 00:25:02.766534 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7600 00:25:02.769576 Total UI for P1: 0, mck2ui 16
7601 00:25:02.773116 best dqsien dly found for B0: ( 1, 9, 18)
7602 00:25:02.776266 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 00:25:02.779789 Total UI for P1: 0, mck2ui 16
7604 00:25:02.783123 best dqsien dly found for B1: ( 1, 9, 24)
7605 00:25:02.786373 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7606 00:25:02.789650 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7607 00:25:02.789725
7608 00:25:02.793171 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7609 00:25:02.796543 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7610 00:25:02.799756 [Gating] SW calibration Done
7611 00:25:02.799832 ==
7612 00:25:02.803016 Dram Type= 6, Freq= 0, CH_0, rank 0
7613 00:25:02.809630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7614 00:25:02.809701 ==
7615 00:25:02.809762 RX Vref Scan: 0
7616 00:25:02.809820
7617 00:25:02.813084 RX Vref 0 -> 0, step: 1
7618 00:25:02.813177
7619 00:25:02.817171 RX Delay 0 -> 252, step: 8
7620 00:25:02.819738 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7621 00:25:02.823236 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7622 00:25:02.826873 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7623 00:25:02.829992 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7624 00:25:02.836455 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7625 00:25:02.839856 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7626 00:25:02.843118 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7627 00:25:02.846424 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7628 00:25:02.850261 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7629 00:25:02.856431 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7630 00:25:02.859682 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7631 00:25:02.863300 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7632 00:25:02.866574 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7633 00:25:02.870131 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7634 00:25:02.876820 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7635 00:25:02.880014 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7636 00:25:02.880083 ==
7637 00:25:02.883219 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 00:25:02.887139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 00:25:02.887232 ==
7640 00:25:02.887320 DQS Delay:
7641 00:25:02.890196 DQS0 = 0, DQS1 = 0
7642 00:25:02.890263 DQM Delay:
7643 00:25:02.893349 DQM0 = 132, DQM1 = 125
7644 00:25:02.893417 DQ Delay:
7645 00:25:02.897058 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7646 00:25:02.900015 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7647 00:25:02.903467 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7648 00:25:02.906653 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7649 00:25:02.906720
7650 00:25:02.910170
7651 00:25:02.910243 ==
7652 00:25:02.913739 Dram Type= 6, Freq= 0, CH_0, rank 0
7653 00:25:02.916883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7654 00:25:02.916949 ==
7655 00:25:02.917005
7656 00:25:02.917060
7657 00:25:02.920020 TX Vref Scan disable
7658 00:25:02.920083 == TX Byte 0 ==
7659 00:25:02.927220 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7660 00:25:02.930247 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7661 00:25:02.930323 == TX Byte 1 ==
7662 00:25:02.936793 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7663 00:25:02.940102 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7664 00:25:02.940173 ==
7665 00:25:02.943523 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 00:25:02.946748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 00:25:02.946824 ==
7668 00:25:02.961605
7669 00:25:02.965040 TX Vref early break, caculate TX vref
7670 00:25:02.968532 TX Vref=16, minBit 4, minWin=21, winSum=357
7671 00:25:02.972130 TX Vref=18, minBit 1, minWin=22, winSum=369
7672 00:25:02.975244 TX Vref=20, minBit 7, minWin=22, winSum=380
7673 00:25:02.978649 TX Vref=22, minBit 1, minWin=23, winSum=390
7674 00:25:02.981992 TX Vref=24, minBit 4, minWin=23, winSum=402
7675 00:25:02.988526 TX Vref=26, minBit 4, minWin=24, winSum=413
7676 00:25:02.991944 TX Vref=28, minBit 4, minWin=24, winSum=417
7677 00:25:02.995147 TX Vref=30, minBit 4, minWin=24, winSum=419
7678 00:25:02.998812 TX Vref=32, minBit 4, minWin=23, winSum=413
7679 00:25:03.001749 TX Vref=34, minBit 4, minWin=24, winSum=404
7680 00:25:03.005173 TX Vref=36, minBit 0, minWin=23, winSum=389
7681 00:25:03.012082 [TxChooseVref] Worse bit 4, Min win 24, Win sum 419, Final Vref 30
7682 00:25:03.012210
7683 00:25:03.015302 Final TX Range 0 Vref 30
7684 00:25:03.015375
7685 00:25:03.015434 ==
7686 00:25:03.019215 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 00:25:03.022109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7688 00:25:03.022177 ==
7689 00:25:03.022240
7690 00:25:03.022332
7691 00:25:03.025764 TX Vref Scan disable
7692 00:25:03.032341 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7693 00:25:03.032444 == TX Byte 0 ==
7694 00:25:03.035487 u2DelayCellOfst[0]=14 cells (4 PI)
7695 00:25:03.038805 u2DelayCellOfst[1]=17 cells (5 PI)
7696 00:25:03.042250 u2DelayCellOfst[2]=10 cells (3 PI)
7697 00:25:03.045582 u2DelayCellOfst[3]=14 cells (4 PI)
7698 00:25:03.048942 u2DelayCellOfst[4]=10 cells (3 PI)
7699 00:25:03.052193 u2DelayCellOfst[5]=0 cells (0 PI)
7700 00:25:03.055660 u2DelayCellOfst[6]=17 cells (5 PI)
7701 00:25:03.055759 u2DelayCellOfst[7]=17 cells (5 PI)
7702 00:25:03.062066 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7703 00:25:03.065493 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7704 00:25:03.065569 == TX Byte 1 ==
7705 00:25:03.069218 u2DelayCellOfst[8]=0 cells (0 PI)
7706 00:25:03.072544 u2DelayCellOfst[9]=0 cells (0 PI)
7707 00:25:03.075983 u2DelayCellOfst[10]=7 cells (2 PI)
7708 00:25:03.079193 u2DelayCellOfst[11]=0 cells (0 PI)
7709 00:25:03.082713 u2DelayCellOfst[12]=14 cells (4 PI)
7710 00:25:03.085643 u2DelayCellOfst[13]=14 cells (4 PI)
7711 00:25:03.089040 u2DelayCellOfst[14]=17 cells (5 PI)
7712 00:25:03.092879 u2DelayCellOfst[15]=14 cells (4 PI)
7713 00:25:03.095505 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7714 00:25:03.098950 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7715 00:25:03.102244 DramC Write-DBI on
7716 00:25:03.102350 ==
7717 00:25:03.106079 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 00:25:03.108797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 00:25:03.108867 ==
7720 00:25:03.108927
7721 00:25:03.112344
7722 00:25:03.112443 TX Vref Scan disable
7723 00:25:03.115809 == TX Byte 0 ==
7724 00:25:03.118988 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7725 00:25:03.122389 == TX Byte 1 ==
7726 00:25:03.125681 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7727 00:25:03.125753 DramC Write-DBI off
7728 00:25:03.125822
7729 00:25:03.129237 [DATLAT]
7730 00:25:03.129339 Freq=1600, CH0 RK0
7731 00:25:03.129427
7732 00:25:03.132440 DATLAT Default: 0xf
7733 00:25:03.132538 0, 0xFFFF, sum = 0
7734 00:25:03.135682 1, 0xFFFF, sum = 0
7735 00:25:03.135772 2, 0xFFFF, sum = 0
7736 00:25:03.139538 3, 0xFFFF, sum = 0
7737 00:25:03.139639 4, 0xFFFF, sum = 0
7738 00:25:03.142239 5, 0xFFFF, sum = 0
7739 00:25:03.142310 6, 0xFFFF, sum = 0
7740 00:25:03.145524 7, 0xFFFF, sum = 0
7741 00:25:03.145593 8, 0xFFFF, sum = 0
7742 00:25:03.149308 9, 0xFFFF, sum = 0
7743 00:25:03.149409 10, 0xFFFF, sum = 0
7744 00:25:03.152511 11, 0xFFFF, sum = 0
7745 00:25:03.156224 12, 0xFFFF, sum = 0
7746 00:25:03.156325 13, 0xFFFF, sum = 0
7747 00:25:03.158841 14, 0x0, sum = 1
7748 00:25:03.158940 15, 0x0, sum = 2
7749 00:25:03.162901 16, 0x0, sum = 3
7750 00:25:03.163002 17, 0x0, sum = 4
7751 00:25:03.163093 best_step = 15
7752 00:25:03.163180
7753 00:25:03.165745 ==
7754 00:25:03.165841 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 00:25:03.172461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 00:25:03.172559 ==
7757 00:25:03.172647 RX Vref Scan: 1
7758 00:25:03.172721
7759 00:25:03.175765 Set Vref Range= 24 -> 127
7760 00:25:03.175861
7761 00:25:03.179131 RX Vref 24 -> 127, step: 1
7762 00:25:03.179226
7763 00:25:03.182346 RX Delay 11 -> 252, step: 4
7764 00:25:03.182440
7765 00:25:03.186152 Set Vref, RX VrefLevel [Byte0]: 24
7766 00:25:03.188926 [Byte1]: 24
7767 00:25:03.189022
7768 00:25:03.192483 Set Vref, RX VrefLevel [Byte0]: 25
7769 00:25:03.195738 [Byte1]: 25
7770 00:25:03.195833
7771 00:25:03.199519 Set Vref, RX VrefLevel [Byte0]: 26
7772 00:25:03.202577 [Byte1]: 26
7773 00:25:03.202680
7774 00:25:03.206068 Set Vref, RX VrefLevel [Byte0]: 27
7775 00:25:03.209128 [Byte1]: 27
7776 00:25:03.213430
7777 00:25:03.213533 Set Vref, RX VrefLevel [Byte0]: 28
7778 00:25:03.216733 [Byte1]: 28
7779 00:25:03.221056
7780 00:25:03.221131 Set Vref, RX VrefLevel [Byte0]: 29
7781 00:25:03.224240 [Byte1]: 29
7782 00:25:03.229055
7783 00:25:03.229127 Set Vref, RX VrefLevel [Byte0]: 30
7784 00:25:03.231982 [Byte1]: 30
7785 00:25:03.236214
7786 00:25:03.236319 Set Vref, RX VrefLevel [Byte0]: 31
7787 00:25:03.239419 [Byte1]: 31
7788 00:25:03.243738
7789 00:25:03.243811 Set Vref, RX VrefLevel [Byte0]: 32
7790 00:25:03.247142 [Byte1]: 32
7791 00:25:03.251568
7792 00:25:03.251679 Set Vref, RX VrefLevel [Byte0]: 33
7793 00:25:03.254576 [Byte1]: 33
7794 00:25:03.259034
7795 00:25:03.259132 Set Vref, RX VrefLevel [Byte0]: 34
7796 00:25:03.262535 [Byte1]: 34
7797 00:25:03.266661
7798 00:25:03.266756 Set Vref, RX VrefLevel [Byte0]: 35
7799 00:25:03.270275 [Byte1]: 35
7800 00:25:03.274190
7801 00:25:03.274263 Set Vref, RX VrefLevel [Byte0]: 36
7802 00:25:03.277823 [Byte1]: 36
7803 00:25:03.282243
7804 00:25:03.282311 Set Vref, RX VrefLevel [Byte0]: 37
7805 00:25:03.285364 [Byte1]: 37
7806 00:25:03.289349
7807 00:25:03.289465 Set Vref, RX VrefLevel [Byte0]: 38
7808 00:25:03.292792 [Byte1]: 38
7809 00:25:03.296830
7810 00:25:03.296897 Set Vref, RX VrefLevel [Byte0]: 39
7811 00:25:03.300168 [Byte1]: 39
7812 00:25:03.304602
7813 00:25:03.304715 Set Vref, RX VrefLevel [Byte0]: 40
7814 00:25:03.308094 [Byte1]: 40
7815 00:25:03.312061
7816 00:25:03.312162 Set Vref, RX VrefLevel [Byte0]: 41
7817 00:25:03.315886 [Byte1]: 41
7818 00:25:03.319552
7819 00:25:03.319655 Set Vref, RX VrefLevel [Byte0]: 42
7820 00:25:03.323132 [Byte1]: 42
7821 00:25:03.327513
7822 00:25:03.327615 Set Vref, RX VrefLevel [Byte0]: 43
7823 00:25:03.330690 [Byte1]: 43
7824 00:25:03.334943
7825 00:25:03.335031 Set Vref, RX VrefLevel [Byte0]: 44
7826 00:25:03.338525 [Byte1]: 44
7827 00:25:03.342794
7828 00:25:03.342894 Set Vref, RX VrefLevel [Byte0]: 45
7829 00:25:03.346084 [Byte1]: 45
7830 00:25:03.350340
7831 00:25:03.350412 Set Vref, RX VrefLevel [Byte0]: 46
7832 00:25:03.353439 [Byte1]: 46
7833 00:25:03.358072
7834 00:25:03.358144 Set Vref, RX VrefLevel [Byte0]: 47
7835 00:25:03.360966 [Byte1]: 47
7836 00:25:03.365230
7837 00:25:03.365299 Set Vref, RX VrefLevel [Byte0]: 48
7838 00:25:03.369141 [Byte1]: 48
7839 00:25:03.373327
7840 00:25:03.373425 Set Vref, RX VrefLevel [Byte0]: 49
7841 00:25:03.376631 [Byte1]: 49
7842 00:25:03.381112
7843 00:25:03.381190 Set Vref, RX VrefLevel [Byte0]: 50
7844 00:25:03.384484 [Byte1]: 50
7845 00:25:03.388766
7846 00:25:03.388863 Set Vref, RX VrefLevel [Byte0]: 51
7847 00:25:03.391430 [Byte1]: 51
7848 00:25:03.395886
7849 00:25:03.395963 Set Vref, RX VrefLevel [Byte0]: 52
7850 00:25:03.399614 [Byte1]: 52
7851 00:25:03.403706
7852 00:25:03.403779 Set Vref, RX VrefLevel [Byte0]: 53
7853 00:25:03.406757 [Byte1]: 53
7854 00:25:03.411194
7855 00:25:03.411264 Set Vref, RX VrefLevel [Byte0]: 54
7856 00:25:03.414257 [Byte1]: 54
7857 00:25:03.419234
7858 00:25:03.419339 Set Vref, RX VrefLevel [Byte0]: 55
7859 00:25:03.422083 [Byte1]: 55
7860 00:25:03.426430
7861 00:25:03.426532 Set Vref, RX VrefLevel [Byte0]: 56
7862 00:25:03.429758 [Byte1]: 56
7863 00:25:03.434215
7864 00:25:03.434314 Set Vref, RX VrefLevel [Byte0]: 57
7865 00:25:03.437603 [Byte1]: 57
7866 00:25:03.441618
7867 00:25:03.441694 Set Vref, RX VrefLevel [Byte0]: 58
7868 00:25:03.444844 [Byte1]: 58
7869 00:25:03.448983
7870 00:25:03.449081 Set Vref, RX VrefLevel [Byte0]: 59
7871 00:25:03.452703 [Byte1]: 59
7872 00:25:03.457180
7873 00:25:03.457259 Set Vref, RX VrefLevel [Byte0]: 60
7874 00:25:03.460103 [Byte1]: 60
7875 00:25:03.464488
7876 00:25:03.464586 Set Vref, RX VrefLevel [Byte0]: 61
7877 00:25:03.467990 [Byte1]: 61
7878 00:25:03.471809
7879 00:25:03.471905 Set Vref, RX VrefLevel [Byte0]: 62
7880 00:25:03.475433 [Byte1]: 62
7881 00:25:03.479716
7882 00:25:03.479804 Set Vref, RX VrefLevel [Byte0]: 63
7883 00:25:03.482733 [Byte1]: 63
7884 00:25:03.487197
7885 00:25:03.487295 Set Vref, RX VrefLevel [Byte0]: 64
7886 00:25:03.490830 [Byte1]: 64
7887 00:25:03.495343
7888 00:25:03.495439 Set Vref, RX VrefLevel [Byte0]: 65
7889 00:25:03.498217 [Byte1]: 65
7890 00:25:03.502590
7891 00:25:03.502659 Set Vref, RX VrefLevel [Byte0]: 66
7892 00:25:03.505627 [Byte1]: 66
7893 00:25:03.510465
7894 00:25:03.510535 Set Vref, RX VrefLevel [Byte0]: 67
7895 00:25:03.513405 [Byte1]: 67
7896 00:25:03.517480
7897 00:25:03.517582 Set Vref, RX VrefLevel [Byte0]: 68
7898 00:25:03.521213 [Byte1]: 68
7899 00:25:03.525178
7900 00:25:03.525252 Set Vref, RX VrefLevel [Byte0]: 69
7901 00:25:03.528699 [Byte1]: 69
7902 00:25:03.532893
7903 00:25:03.532996 Set Vref, RX VrefLevel [Byte0]: 70
7904 00:25:03.536398 [Byte1]: 70
7905 00:25:03.540926
7906 00:25:03.541008 Set Vref, RX VrefLevel [Byte0]: 71
7907 00:25:03.544213 [Byte1]: 71
7908 00:25:03.548342
7909 00:25:03.548446 Set Vref, RX VrefLevel [Byte0]: 72
7910 00:25:03.551608 [Byte1]: 72
7911 00:25:03.555923
7912 00:25:03.556004 Set Vref, RX VrefLevel [Byte0]: 73
7913 00:25:03.558911 [Byte1]: 73
7914 00:25:03.563161
7915 00:25:03.563262 Set Vref, RX VrefLevel [Byte0]: 74
7916 00:25:03.566669 [Byte1]: 74
7917 00:25:03.570894
7918 00:25:03.570991 Set Vref, RX VrefLevel [Byte0]: 75
7919 00:25:03.574146 [Byte1]: 75
7920 00:25:03.578781
7921 00:25:03.578853 Final RX Vref Byte 0 = 56 to rank0
7922 00:25:03.582165 Final RX Vref Byte 1 = 60 to rank0
7923 00:25:03.585280 Final RX Vref Byte 0 = 56 to rank1
7924 00:25:03.588797 Final RX Vref Byte 1 = 60 to rank1==
7925 00:25:03.592138 Dram Type= 6, Freq= 0, CH_0, rank 0
7926 00:25:03.595788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7927 00:25:03.598949 ==
7928 00:25:03.599050 DQS Delay:
7929 00:25:03.599140 DQS0 = 0, DQS1 = 0
7930 00:25:03.601850 DQM Delay:
7931 00:25:03.601918 DQM0 = 129, DQM1 = 122
7932 00:25:03.605843 DQ Delay:
7933 00:25:03.608998 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126
7934 00:25:03.612177 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
7935 00:25:03.615327 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =118
7936 00:25:03.619078 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =134
7937 00:25:03.619149
7938 00:25:03.619210
7939 00:25:03.619271
7940 00:25:03.622240 [DramC_TX_OE_Calibration] TA2
7941 00:25:03.625118 Original DQ_B0 (3 6) =30, OEN = 27
7942 00:25:03.628540 Original DQ_B1 (3 6) =30, OEN = 27
7943 00:25:03.631879 24, 0x0, End_B0=24 End_B1=24
7944 00:25:03.631963 25, 0x0, End_B0=25 End_B1=25
7945 00:25:03.635338 26, 0x0, End_B0=26 End_B1=26
7946 00:25:03.638539 27, 0x0, End_B0=27 End_B1=27
7947 00:25:03.642044 28, 0x0, End_B0=28 End_B1=28
7948 00:25:03.642127 29, 0x0, End_B0=29 End_B1=29
7949 00:25:03.645754 30, 0x0, End_B0=30 End_B1=30
7950 00:25:03.648882 31, 0x4545, End_B0=30 End_B1=30
7951 00:25:03.652484 Byte0 end_step=30 best_step=27
7952 00:25:03.655705 Byte1 end_step=30 best_step=27
7953 00:25:03.658550 Byte0 TX OE(2T, 0.5T) = (3, 3)
7954 00:25:03.658633 Byte1 TX OE(2T, 0.5T) = (3, 3)
7955 00:25:03.658697
7956 00:25:03.661974
7957 00:25:03.668804 [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7958 00:25:03.672143 CH0 RK0: MR19=303, MR18=1509
7959 00:25:03.679176 CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
7960 00:25:03.679260
7961 00:25:03.682316 ----->DramcWriteLeveling(PI) begin...
7962 00:25:03.682391 ==
7963 00:25:03.685370 Dram Type= 6, Freq= 0, CH_0, rank 1
7964 00:25:03.688959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7965 00:25:03.689033 ==
7966 00:25:03.692197 Write leveling (Byte 0): 35 => 35
7967 00:25:03.695791 Write leveling (Byte 1): 28 => 28
7968 00:25:03.699237 DramcWriteLeveling(PI) end<-----
7969 00:25:03.699336
7970 00:25:03.699429 ==
7971 00:25:03.702123 Dram Type= 6, Freq= 0, CH_0, rank 1
7972 00:25:03.705635 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7973 00:25:03.705709 ==
7974 00:25:03.709074 [Gating] SW mode calibration
7975 00:25:03.715521 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7976 00:25:03.722032 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7977 00:25:03.725840 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7978 00:25:03.728841 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7979 00:25:03.735490 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7980 00:25:03.739117 1 4 12 | B1->B0 | 2323 3433 | 0 1 | (0 0) (1 1)
7981 00:25:03.742399 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7982 00:25:03.745636 1 4 20 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
7983 00:25:03.752604 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7984 00:25:03.755913 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7985 00:25:03.758932 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7986 00:25:03.765953 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7987 00:25:03.768854 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7988 00:25:03.772912 1 5 12 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
7989 00:25:03.779082 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7990 00:25:03.782285 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
7991 00:25:03.785936 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7992 00:25:03.792437 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 00:25:03.795797 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 00:25:03.798741 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 00:25:03.805368 1 6 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7996 00:25:03.808715 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (1 1)
7997 00:25:03.812401 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7998 00:25:03.819193 1 6 20 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
7999 00:25:03.822484 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8000 00:25:03.826023 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 00:25:03.832365 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 00:25:03.835899 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 00:25:03.838814 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8004 00:25:03.842321 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8005 00:25:03.848942 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8006 00:25:03.852429 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8007 00:25:03.856372 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8008 00:25:03.862291 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 00:25:03.865790 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 00:25:03.869456 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 00:25:03.875993 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 00:25:03.879263 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 00:25:03.882539 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 00:25:03.888996 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 00:25:03.892663 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 00:25:03.895738 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 00:25:03.902864 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 00:25:03.905793 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 00:25:03.909090 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8020 00:25:03.912548 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8021 00:25:03.919886 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8022 00:25:03.922501 Total UI for P1: 0, mck2ui 16
8023 00:25:03.925955 best dqsien dly found for B0: ( 1, 9, 10)
8024 00:25:03.929259 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8025 00:25:03.932705 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 00:25:03.936062 Total UI for P1: 0, mck2ui 16
8027 00:25:03.939723 best dqsien dly found for B1: ( 1, 9, 18)
8028 00:25:03.942335 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8029 00:25:03.945761 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8030 00:25:03.945858
8031 00:25:03.952498 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8032 00:25:03.956054 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8033 00:25:03.959136 [Gating] SW calibration Done
8034 00:25:03.959290 ==
8035 00:25:03.962495 Dram Type= 6, Freq= 0, CH_0, rank 1
8036 00:25:03.966104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8037 00:25:03.966185 ==
8038 00:25:03.966249 RX Vref Scan: 0
8039 00:25:03.966308
8040 00:25:03.969205 RX Vref 0 -> 0, step: 1
8041 00:25:03.969286
8042 00:25:03.972707 RX Delay 0 -> 252, step: 8
8043 00:25:03.976064 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8044 00:25:03.979566 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8045 00:25:03.982776 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8046 00:25:03.989206 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8047 00:25:03.992501 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8048 00:25:03.996045 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8049 00:25:03.999602 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8050 00:25:04.002890 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8051 00:25:04.009260 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8052 00:25:04.012883 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8053 00:25:04.015878 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8054 00:25:04.019218 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8055 00:25:04.022699 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8056 00:25:04.029495 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8057 00:25:04.032990 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8058 00:25:04.036113 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8059 00:25:04.036194 ==
8060 00:25:04.039726 Dram Type= 6, Freq= 0, CH_0, rank 1
8061 00:25:04.043059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8062 00:25:04.043140 ==
8063 00:25:04.046575 DQS Delay:
8064 00:25:04.046655 DQS0 = 0, DQS1 = 0
8065 00:25:04.049671 DQM Delay:
8066 00:25:04.049751 DQM0 = 131, DQM1 = 124
8067 00:25:04.049847 DQ Delay:
8068 00:25:04.053300 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
8069 00:25:04.059383 DQ4 =131, DQ5 =115, DQ6 =139, DQ7 =139
8070 00:25:04.063041 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8071 00:25:04.066114 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8072 00:25:04.066195
8073 00:25:04.066258
8074 00:25:04.066317 ==
8075 00:25:04.069456 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 00:25:04.072849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 00:25:04.072930 ==
8078 00:25:04.072993
8079 00:25:04.073051
8080 00:25:04.076426 TX Vref Scan disable
8081 00:25:04.079375 == TX Byte 0 ==
8082 00:25:04.083129 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8083 00:25:04.086139 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8084 00:25:04.089510 == TX Byte 1 ==
8085 00:25:04.092878 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8086 00:25:04.096783 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8087 00:25:04.096866 ==
8088 00:25:04.099712 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 00:25:04.103162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 00:25:04.106036 ==
8091 00:25:04.120608
8092 00:25:04.123802 TX Vref early break, caculate TX vref
8093 00:25:04.127077 TX Vref=16, minBit 1, minWin=23, winSum=381
8094 00:25:04.130521 TX Vref=18, minBit 1, minWin=23, winSum=385
8095 00:25:04.133766 TX Vref=20, minBit 1, minWin=23, winSum=394
8096 00:25:04.137208 TX Vref=22, minBit 0, minWin=24, winSum=407
8097 00:25:04.140409 TX Vref=24, minBit 4, minWin=24, winSum=414
8098 00:25:04.143693 TX Vref=26, minBit 4, minWin=24, winSum=417
8099 00:25:04.150525 TX Vref=28, minBit 4, minWin=25, winSum=421
8100 00:25:04.154152 TX Vref=30, minBit 0, minWin=25, winSum=419
8101 00:25:04.157441 TX Vref=32, minBit 4, minWin=25, winSum=414
8102 00:25:04.160535 TX Vref=34, minBit 2, minWin=24, winSum=406
8103 00:25:04.163695 TX Vref=36, minBit 1, minWin=24, winSum=400
8104 00:25:04.167290 TX Vref=38, minBit 0, minWin=23, winSum=386
8105 00:25:04.174098 [TxChooseVref] Worse bit 4, Min win 25, Win sum 421, Final Vref 28
8106 00:25:04.174180
8107 00:25:04.177050 Final TX Range 0 Vref 28
8108 00:25:04.177132
8109 00:25:04.177195 ==
8110 00:25:04.180529 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 00:25:04.183905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 00:25:04.183986 ==
8113 00:25:04.184049
8114 00:25:04.184108
8115 00:25:04.187104 TX Vref Scan disable
8116 00:25:04.194265 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8117 00:25:04.194374 == TX Byte 0 ==
8118 00:25:04.197598 u2DelayCellOfst[0]=14 cells (4 PI)
8119 00:25:04.200934 u2DelayCellOfst[1]=17 cells (5 PI)
8120 00:25:04.204037 u2DelayCellOfst[2]=10 cells (3 PI)
8121 00:25:04.207241 u2DelayCellOfst[3]=10 cells (3 PI)
8122 00:25:04.210714 u2DelayCellOfst[4]=10 cells (3 PI)
8123 00:25:04.214172 u2DelayCellOfst[5]=0 cells (0 PI)
8124 00:25:04.217360 u2DelayCellOfst[6]=17 cells (5 PI)
8125 00:25:04.220568 u2DelayCellOfst[7]=17 cells (5 PI)
8126 00:25:04.224109 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8127 00:25:04.227253 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8128 00:25:04.231064 == TX Byte 1 ==
8129 00:25:04.234160 u2DelayCellOfst[8]=0 cells (0 PI)
8130 00:25:04.234241 u2DelayCellOfst[9]=0 cells (0 PI)
8131 00:25:04.237135 u2DelayCellOfst[10]=7 cells (2 PI)
8132 00:25:04.240761 u2DelayCellOfst[11]=0 cells (0 PI)
8133 00:25:04.244451 u2DelayCellOfst[12]=14 cells (4 PI)
8134 00:25:04.247955 u2DelayCellOfst[13]=10 cells (3 PI)
8135 00:25:04.250916 u2DelayCellOfst[14]=14 cells (4 PI)
8136 00:25:04.254686 u2DelayCellOfst[15]=10 cells (3 PI)
8137 00:25:04.257648 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8138 00:25:04.263923 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8139 00:25:04.264003 DramC Write-DBI on
8140 00:25:04.264066 ==
8141 00:25:04.267651 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 00:25:04.270908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 00:25:04.274284 ==
8144 00:25:04.274365
8145 00:25:04.274427
8146 00:25:04.274486 TX Vref Scan disable
8147 00:25:04.277794 == TX Byte 0 ==
8148 00:25:04.280993 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8149 00:25:04.284722 == TX Byte 1 ==
8150 00:25:04.287972 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8151 00:25:04.288053 DramC Write-DBI off
8152 00:25:04.291532
8153 00:25:04.291612 [DATLAT]
8154 00:25:04.291675 Freq=1600, CH0 RK1
8155 00:25:04.291734
8156 00:25:04.294358 DATLAT Default: 0xf
8157 00:25:04.294438 0, 0xFFFF, sum = 0
8158 00:25:04.298085 1, 0xFFFF, sum = 0
8159 00:25:04.298185 2, 0xFFFF, sum = 0
8160 00:25:04.301638 3, 0xFFFF, sum = 0
8161 00:25:04.301721 4, 0xFFFF, sum = 0
8162 00:25:04.304548 5, 0xFFFF, sum = 0
8163 00:25:04.304632 6, 0xFFFF, sum = 0
8164 00:25:04.307835 7, 0xFFFF, sum = 0
8165 00:25:04.310931 8, 0xFFFF, sum = 0
8166 00:25:04.311014 9, 0xFFFF, sum = 0
8167 00:25:04.314281 10, 0xFFFF, sum = 0
8168 00:25:04.314377 11, 0xFFFF, sum = 0
8169 00:25:04.317995 12, 0xFFFF, sum = 0
8170 00:25:04.318111 13, 0xFFFF, sum = 0
8171 00:25:04.321020 14, 0x0, sum = 1
8172 00:25:04.321131 15, 0x0, sum = 2
8173 00:25:04.324867 16, 0x0, sum = 3
8174 00:25:04.324951 17, 0x0, sum = 4
8175 00:25:04.327695 best_step = 15
8176 00:25:04.327775
8177 00:25:04.327838 ==
8178 00:25:04.331065 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 00:25:04.334538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 00:25:04.334619 ==
8181 00:25:04.334683 RX Vref Scan: 0
8182 00:25:04.334741
8183 00:25:04.337731 RX Vref 0 -> 0, step: 1
8184 00:25:04.337854
8185 00:25:04.341166 RX Delay 11 -> 252, step: 4
8186 00:25:04.344831 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8187 00:25:04.351250 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8188 00:25:04.354573 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8189 00:25:04.357855 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8190 00:25:04.361046 iDelay=191, Bit 4, Center 126 (75 ~ 178) 104
8191 00:25:04.364389 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8192 00:25:04.368201 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8193 00:25:04.374344 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8194 00:25:04.377821 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8195 00:25:04.381487 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8196 00:25:04.384376 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8197 00:25:04.388106 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8198 00:25:04.394158 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8199 00:25:04.397778 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8200 00:25:04.401528 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8201 00:25:04.404591 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8202 00:25:04.404718 ==
8203 00:25:04.407860 Dram Type= 6, Freq= 0, CH_0, rank 1
8204 00:25:04.414819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8205 00:25:04.414900 ==
8206 00:25:04.414964 DQS Delay:
8207 00:25:04.415023 DQS0 = 0, DQS1 = 0
8208 00:25:04.418296 DQM Delay:
8209 00:25:04.418377 DQM0 = 126, DQM1 = 122
8210 00:25:04.421322 DQ Delay:
8211 00:25:04.425032 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8212 00:25:04.427946 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =136
8213 00:25:04.431311 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8214 00:25:04.434694 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8215 00:25:04.434775
8216 00:25:04.434839
8217 00:25:04.434897
8218 00:25:04.438322 [DramC_TX_OE_Calibration] TA2
8219 00:25:04.441405 Original DQ_B0 (3 6) =30, OEN = 27
8220 00:25:04.444478 Original DQ_B1 (3 6) =30, OEN = 27
8221 00:25:04.447871 24, 0x0, End_B0=24 End_B1=24
8222 00:25:04.447953 25, 0x0, End_B0=25 End_B1=25
8223 00:25:04.451347 26, 0x0, End_B0=26 End_B1=26
8224 00:25:04.454714 27, 0x0, End_B0=27 End_B1=27
8225 00:25:04.458009 28, 0x0, End_B0=28 End_B1=28
8226 00:25:04.458092 29, 0x0, End_B0=29 End_B1=29
8227 00:25:04.461581 30, 0x0, End_B0=30 End_B1=30
8228 00:25:04.464603 31, 0x4141, End_B0=30 End_B1=30
8229 00:25:04.468311 Byte0 end_step=30 best_step=27
8230 00:25:04.471920 Byte1 end_step=30 best_step=27
8231 00:25:04.474842 Byte0 TX OE(2T, 0.5T) = (3, 3)
8232 00:25:04.474922 Byte1 TX OE(2T, 0.5T) = (3, 3)
8233 00:25:04.474985
8234 00:25:04.477902
8235 00:25:04.485182 [DQSOSCAuto] RK1, (LSB)MR18= 0x190d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8236 00:25:04.488217 CH0 RK1: MR19=303, MR18=190D
8237 00:25:04.495264 CH0_RK1: MR19=0x303, MR18=0x190D, DQSOSC=397, MR23=63, INC=23, DEC=15
8238 00:25:04.495346 [RxdqsGatingPostProcess] freq 1600
8239 00:25:04.501428 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8240 00:25:04.505139 best DQS0 dly(2T, 0.5T) = (1, 1)
8241 00:25:04.507996 best DQS1 dly(2T, 0.5T) = (1, 1)
8242 00:25:04.511554 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8243 00:25:04.514877 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8244 00:25:04.518148 best DQS0 dly(2T, 0.5T) = (1, 1)
8245 00:25:04.521484 best DQS1 dly(2T, 0.5T) = (1, 1)
8246 00:25:04.524676 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8247 00:25:04.524771 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8248 00:25:04.528142 Pre-setting of DQS Precalculation
8249 00:25:04.535026 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8250 00:25:04.535107 ==
8251 00:25:04.538635 Dram Type= 6, Freq= 0, CH_1, rank 0
8252 00:25:04.541593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8253 00:25:04.541674 ==
8254 00:25:04.548393 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8255 00:25:04.551624 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8256 00:25:04.554981 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8257 00:25:04.561671 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8258 00:25:04.570689 [CA 0] Center 43 (14~72) winsize 59
8259 00:25:04.574033 [CA 1] Center 43 (14~72) winsize 59
8260 00:25:04.577466 [CA 2] Center 38 (10~67) winsize 58
8261 00:25:04.580803 [CA 3] Center 36 (7~66) winsize 60
8262 00:25:04.583831 [CA 4] Center 38 (8~68) winsize 61
8263 00:25:04.587463 [CA 5] Center 37 (8~66) winsize 59
8264 00:25:04.587545
8265 00:25:04.590548 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8266 00:25:04.590629
8267 00:25:04.594058 [CATrainingPosCal] consider 1 rank data
8268 00:25:04.597637 u2DelayCellTimex100 = 275/100 ps
8269 00:25:04.600574 CA0 delay=43 (14~72),Diff = 7 PI (24 cell)
8270 00:25:04.607988 CA1 delay=43 (14~72),Diff = 7 PI (24 cell)
8271 00:25:04.610784 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
8272 00:25:04.614119 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8273 00:25:04.617549 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8274 00:25:04.620612 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8275 00:25:04.620717
8276 00:25:04.624472 CA PerBit enable=1, Macro0, CA PI delay=36
8277 00:25:04.624552
8278 00:25:04.627352 [CBTSetCACLKResult] CA Dly = 36
8279 00:25:04.630645 CS Dly: 9 (0~40)
8280 00:25:04.633925 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8281 00:25:04.637406 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8282 00:25:04.637487 ==
8283 00:25:04.640649 Dram Type= 6, Freq= 0, CH_1, rank 1
8284 00:25:04.644298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8285 00:25:04.644379 ==
8286 00:25:04.650659 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8287 00:25:04.654223 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8288 00:25:04.660613 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8289 00:25:04.664294 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8290 00:25:04.673987 [CA 0] Center 43 (14~72) winsize 59
8291 00:25:04.677244 [CA 1] Center 42 (13~72) winsize 60
8292 00:25:04.680719 [CA 2] Center 38 (10~67) winsize 58
8293 00:25:04.684089 [CA 3] Center 37 (8~67) winsize 60
8294 00:25:04.687123 [CA 4] Center 38 (8~68) winsize 61
8295 00:25:04.690545 [CA 5] Center 36 (7~66) winsize 60
8296 00:25:04.690627
8297 00:25:04.694087 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8298 00:25:04.694170
8299 00:25:04.697300 [CATrainingPosCal] consider 2 rank data
8300 00:25:04.701021 u2DelayCellTimex100 = 275/100 ps
8301 00:25:04.704560 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8302 00:25:04.710935 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8303 00:25:04.714225 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8304 00:25:04.717992 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8305 00:25:04.721059 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8306 00:25:04.724593 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8307 00:25:04.724680
8308 00:25:04.727865 CA PerBit enable=1, Macro0, CA PI delay=37
8309 00:25:04.727945
8310 00:25:04.730734 [CBTSetCACLKResult] CA Dly = 37
8311 00:25:04.730813 CS Dly: 10 (0~43)
8312 00:25:04.737457 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8313 00:25:04.740790 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8314 00:25:04.740871
8315 00:25:04.744679 ----->DramcWriteLeveling(PI) begin...
8316 00:25:04.744776 ==
8317 00:25:04.747589 Dram Type= 6, Freq= 0, CH_1, rank 0
8318 00:25:04.751065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8319 00:25:04.751145 ==
8320 00:25:04.754403 Write leveling (Byte 0): 26 => 26
8321 00:25:04.757810 Write leveling (Byte 1): 30 => 30
8322 00:25:04.761248 DramcWriteLeveling(PI) end<-----
8323 00:25:04.761328
8324 00:25:04.761391 ==
8325 00:25:04.764464 Dram Type= 6, Freq= 0, CH_1, rank 0
8326 00:25:04.767931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8327 00:25:04.771275 ==
8328 00:25:04.771357 [Gating] SW mode calibration
8329 00:25:04.777959 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8330 00:25:04.784516 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8331 00:25:04.788600 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 00:25:04.794690 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 00:25:04.797704 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 00:25:04.801151 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 00:25:04.807967 1 4 16 | B1->B0 | 2828 2323 | 0 1 | (0 0) (1 1)
8336 00:25:04.811279 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 00:25:04.814771 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 00:25:04.821473 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 00:25:04.824552 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8340 00:25:04.828250 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8341 00:25:04.831121 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8342 00:25:04.837814 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8343 00:25:04.841250 1 5 16 | B1->B0 | 2424 2c2c | 0 1 | (1 0) (1 0)
8344 00:25:04.844779 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 00:25:04.851223 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 00:25:04.854739 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 00:25:04.858060 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 00:25:04.864936 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 00:25:04.868021 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 00:25:04.871645 1 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8351 00:25:04.877990 1 6 16 | B1->B0 | 3e3e 2f2f | 0 1 | (0 0) (0 0)
8352 00:25:04.881752 1 6 20 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8353 00:25:04.884912 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 00:25:04.891500 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 00:25:04.894898 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 00:25:04.898020 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 00:25:04.904531 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 00:25:04.908256 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8359 00:25:04.911305 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8360 00:25:04.917725 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 00:25:04.921631 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 00:25:04.925002 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 00:25:04.927897 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 00:25:04.934382 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 00:25:04.937695 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 00:25:04.941153 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 00:25:04.947770 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 00:25:04.951205 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 00:25:04.954411 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 00:25:04.961446 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 00:25:04.964519 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 00:25:04.967836 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 00:25:04.974383 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 00:25:04.978013 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8375 00:25:04.981325 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8376 00:25:04.988026 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 00:25:04.988107 Total UI for P1: 0, mck2ui 16
8378 00:25:04.994725 best dqsien dly found for B0: ( 1, 9, 14)
8379 00:25:04.994806 Total UI for P1: 0, mck2ui 16
8380 00:25:05.001445 best dqsien dly found for B1: ( 1, 9, 14)
8381 00:25:05.004487 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8382 00:25:05.008067 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8383 00:25:05.008199
8384 00:25:05.011475 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8385 00:25:05.014904 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8386 00:25:05.017945 [Gating] SW calibration Done
8387 00:25:05.018028 ==
8388 00:25:05.021337 Dram Type= 6, Freq= 0, CH_1, rank 0
8389 00:25:05.024637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8390 00:25:05.024740 ==
8391 00:25:05.027659 RX Vref Scan: 0
8392 00:25:05.027739
8393 00:25:05.027803 RX Vref 0 -> 0, step: 1
8394 00:25:05.027862
8395 00:25:05.031109 RX Delay 0 -> 252, step: 8
8396 00:25:05.034696 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8397 00:25:05.041300 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8398 00:25:05.044550 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8399 00:25:05.048354 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8400 00:25:05.051293 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8401 00:25:05.055050 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8402 00:25:05.057825 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8403 00:25:05.064712 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8404 00:25:05.067942 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8405 00:25:05.071204 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8406 00:25:05.074715 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8407 00:25:05.077959 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8408 00:25:05.084682 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8409 00:25:05.087839 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8410 00:25:05.091272 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8411 00:25:05.095006 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8412 00:25:05.095087 ==
8413 00:25:05.098278 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 00:25:05.104585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 00:25:05.104691 ==
8416 00:25:05.104773 DQS Delay:
8417 00:25:05.104833 DQS0 = 0, DQS1 = 0
8418 00:25:05.107834 DQM Delay:
8419 00:25:05.107929 DQM0 = 135, DQM1 = 127
8420 00:25:05.111166 DQ Delay:
8421 00:25:05.114415 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8422 00:25:05.117941 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8423 00:25:05.121145 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8424 00:25:05.124583 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8425 00:25:05.124671
8426 00:25:05.124751
8427 00:25:05.124810 ==
8428 00:25:05.128135 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 00:25:05.131354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 00:25:05.134446 ==
8431 00:25:05.134527
8432 00:25:05.134590
8433 00:25:05.134648 TX Vref Scan disable
8434 00:25:05.137932 == TX Byte 0 ==
8435 00:25:05.141261 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8436 00:25:05.144611 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8437 00:25:05.147831 == TX Byte 1 ==
8438 00:25:05.151432 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8439 00:25:05.154409 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8440 00:25:05.154491 ==
8441 00:25:05.157828 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 00:25:05.164702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 00:25:05.164799 ==
8444 00:25:05.176464
8445 00:25:05.180208 TX Vref early break, caculate TX vref
8446 00:25:05.183107 TX Vref=16, minBit 8, minWin=21, winSum=362
8447 00:25:05.186531 TX Vref=18, minBit 5, minWin=22, winSum=368
8448 00:25:05.189679 TX Vref=20, minBit 5, minWin=22, winSum=375
8449 00:25:05.193924 TX Vref=22, minBit 9, minWin=23, winSum=391
8450 00:25:05.196378 TX Vref=24, minBit 8, minWin=23, winSum=402
8451 00:25:05.203088 TX Vref=26, minBit 1, minWin=25, winSum=412
8452 00:25:05.206797 TX Vref=28, minBit 1, minWin=25, winSum=416
8453 00:25:05.210268 TX Vref=30, minBit 9, minWin=25, winSum=414
8454 00:25:05.213684 TX Vref=32, minBit 15, minWin=24, winSum=407
8455 00:25:05.216893 TX Vref=34, minBit 9, minWin=23, winSum=394
8456 00:25:05.223816 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 28
8457 00:25:05.223915
8458 00:25:05.226669 Final TX Range 0 Vref 28
8459 00:25:05.226755
8460 00:25:05.226819 ==
8461 00:25:05.229936 Dram Type= 6, Freq= 0, CH_1, rank 0
8462 00:25:05.233409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8463 00:25:05.233490 ==
8464 00:25:05.233554
8465 00:25:05.233614
8466 00:25:05.236627 TX Vref Scan disable
8467 00:25:05.243605 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8468 00:25:05.243702 == TX Byte 0 ==
8469 00:25:05.246829 u2DelayCellOfst[0]=14 cells (4 PI)
8470 00:25:05.250357 u2DelayCellOfst[1]=10 cells (3 PI)
8471 00:25:05.253535 u2DelayCellOfst[2]=0 cells (0 PI)
8472 00:25:05.256888 u2DelayCellOfst[3]=7 cells (2 PI)
8473 00:25:05.260357 u2DelayCellOfst[4]=10 cells (3 PI)
8474 00:25:05.260438 u2DelayCellOfst[5]=17 cells (5 PI)
8475 00:25:05.263410 u2DelayCellOfst[6]=17 cells (5 PI)
8476 00:25:05.266840 u2DelayCellOfst[7]=7 cells (2 PI)
8477 00:25:05.273738 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8478 00:25:05.276811 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8479 00:25:05.276892 == TX Byte 1 ==
8480 00:25:05.280170 u2DelayCellOfst[8]=0 cells (0 PI)
8481 00:25:05.283621 u2DelayCellOfst[9]=0 cells (0 PI)
8482 00:25:05.286827 u2DelayCellOfst[10]=7 cells (2 PI)
8483 00:25:05.290344 u2DelayCellOfst[11]=3 cells (1 PI)
8484 00:25:05.293706 u2DelayCellOfst[12]=10 cells (3 PI)
8485 00:25:05.296949 u2DelayCellOfst[13]=14 cells (4 PI)
8486 00:25:05.300065 u2DelayCellOfst[14]=14 cells (4 PI)
8487 00:25:05.303430 u2DelayCellOfst[15]=14 cells (4 PI)
8488 00:25:05.306884 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8489 00:25:05.310092 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8490 00:25:05.313758 DramC Write-DBI on
8491 00:25:05.313839 ==
8492 00:25:05.317073 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 00:25:05.320172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 00:25:05.320254 ==
8495 00:25:05.320317
8496 00:25:05.320376
8497 00:25:05.323556 TX Vref Scan disable
8498 00:25:05.327000 == TX Byte 0 ==
8499 00:25:05.330122 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8500 00:25:05.330238 == TX Byte 1 ==
8501 00:25:05.336877 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8502 00:25:05.336976 DramC Write-DBI off
8503 00:25:05.337052
8504 00:25:05.337110 [DATLAT]
8505 00:25:05.340300 Freq=1600, CH1 RK0
8506 00:25:05.340380
8507 00:25:05.343589 DATLAT Default: 0xf
8508 00:25:05.343669 0, 0xFFFF, sum = 0
8509 00:25:05.347027 1, 0xFFFF, sum = 0
8510 00:25:05.347109 2, 0xFFFF, sum = 0
8511 00:25:05.350210 3, 0xFFFF, sum = 0
8512 00:25:05.350308 4, 0xFFFF, sum = 0
8513 00:25:05.353494 5, 0xFFFF, sum = 0
8514 00:25:05.353576 6, 0xFFFF, sum = 0
8515 00:25:05.356902 7, 0xFFFF, sum = 0
8516 00:25:05.356984 8, 0xFFFF, sum = 0
8517 00:25:05.360465 9, 0xFFFF, sum = 0
8518 00:25:05.360561 10, 0xFFFF, sum = 0
8519 00:25:05.363750 11, 0xFFFF, sum = 0
8520 00:25:05.363846 12, 0xFFFF, sum = 0
8521 00:25:05.367081 13, 0xFFFF, sum = 0
8522 00:25:05.367162 14, 0x0, sum = 1
8523 00:25:05.370298 15, 0x0, sum = 2
8524 00:25:05.370387 16, 0x0, sum = 3
8525 00:25:05.373953 17, 0x0, sum = 4
8526 00:25:05.374035 best_step = 15
8527 00:25:05.374113
8528 00:25:05.374200 ==
8529 00:25:05.377260 Dram Type= 6, Freq= 0, CH_1, rank 0
8530 00:25:05.383654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8531 00:25:05.383735 ==
8532 00:25:05.383799 RX Vref Scan: 1
8533 00:25:05.383857
8534 00:25:05.386993 Set Vref Range= 24 -> 127
8535 00:25:05.387093
8536 00:25:05.390293 RX Vref 24 -> 127, step: 1
8537 00:25:05.390416
8538 00:25:05.390507 RX Delay 11 -> 252, step: 4
8539 00:25:05.390594
8540 00:25:05.393674 Set Vref, RX VrefLevel [Byte0]: 24
8541 00:25:05.396848 [Byte1]: 24
8542 00:25:05.401606
8543 00:25:05.401687 Set Vref, RX VrefLevel [Byte0]: 25
8544 00:25:05.404560 [Byte1]: 25
8545 00:25:05.408565
8546 00:25:05.408648 Set Vref, RX VrefLevel [Byte0]: 26
8547 00:25:05.412207 [Byte1]: 26
8548 00:25:05.416437
8549 00:25:05.416517 Set Vref, RX VrefLevel [Byte0]: 27
8550 00:25:05.419466 [Byte1]: 27
8551 00:25:05.424011
8552 00:25:05.424092 Set Vref, RX VrefLevel [Byte0]: 28
8553 00:25:05.427297 [Byte1]: 28
8554 00:25:05.431929
8555 00:25:05.432013 Set Vref, RX VrefLevel [Byte0]: 29
8556 00:25:05.435014 [Byte1]: 29
8557 00:25:05.439156
8558 00:25:05.439238 Set Vref, RX VrefLevel [Byte0]: 30
8559 00:25:05.442705 [Byte1]: 30
8560 00:25:05.446589
8561 00:25:05.446672 Set Vref, RX VrefLevel [Byte0]: 31
8562 00:25:05.450400 [Byte1]: 31
8563 00:25:05.454615
8564 00:25:05.454698 Set Vref, RX VrefLevel [Byte0]: 32
8565 00:25:05.458286 [Byte1]: 32
8566 00:25:05.461841
8567 00:25:05.461923 Set Vref, RX VrefLevel [Byte0]: 33
8568 00:25:05.464983 [Byte1]: 33
8569 00:25:05.469522
8570 00:25:05.469604 Set Vref, RX VrefLevel [Byte0]: 34
8571 00:25:05.472592 [Byte1]: 34
8572 00:25:05.477074
8573 00:25:05.477157 Set Vref, RX VrefLevel [Byte0]: 35
8574 00:25:05.480823 [Byte1]: 35
8575 00:25:05.485177
8576 00:25:05.485259 Set Vref, RX VrefLevel [Byte0]: 36
8577 00:25:05.488445 [Byte1]: 36
8578 00:25:05.492448
8579 00:25:05.492530 Set Vref, RX VrefLevel [Byte0]: 37
8580 00:25:05.496180 [Byte1]: 37
8581 00:25:05.500109
8582 00:25:05.500191 Set Vref, RX VrefLevel [Byte0]: 38
8583 00:25:05.503669 [Byte1]: 38
8584 00:25:05.507510
8585 00:25:05.507592 Set Vref, RX VrefLevel [Byte0]: 39
8586 00:25:05.511271 [Byte1]: 39
8587 00:25:05.515470
8588 00:25:05.515554 Set Vref, RX VrefLevel [Byte0]: 40
8589 00:25:05.518517 [Byte1]: 40
8590 00:25:05.523227
8591 00:25:05.523310 Set Vref, RX VrefLevel [Byte0]: 41
8592 00:25:05.526241 [Byte1]: 41
8593 00:25:05.530623
8594 00:25:05.530706 Set Vref, RX VrefLevel [Byte0]: 42
8595 00:25:05.533907 [Byte1]: 42
8596 00:25:05.538159
8597 00:25:05.538242 Set Vref, RX VrefLevel [Byte0]: 43
8598 00:25:05.541253 [Byte1]: 43
8599 00:25:05.545702
8600 00:25:05.545799 Set Vref, RX VrefLevel [Byte0]: 44
8601 00:25:05.548942 [Byte1]: 44
8602 00:25:05.553457
8603 00:25:05.553538 Set Vref, RX VrefLevel [Byte0]: 45
8604 00:25:05.556400 [Byte1]: 45
8605 00:25:05.561013
8606 00:25:05.561093 Set Vref, RX VrefLevel [Byte0]: 46
8607 00:25:05.564408 [Byte1]: 46
8608 00:25:05.568433
8609 00:25:05.568513 Set Vref, RX VrefLevel [Byte0]: 47
8610 00:25:05.571857 [Byte1]: 47
8611 00:25:05.576111
8612 00:25:05.576192 Set Vref, RX VrefLevel [Byte0]: 48
8613 00:25:05.579378 [Byte1]: 48
8614 00:25:05.583496
8615 00:25:05.583576 Set Vref, RX VrefLevel [Byte0]: 49
8616 00:25:05.587290 [Byte1]: 49
8617 00:25:05.591655
8618 00:25:05.591756 Set Vref, RX VrefLevel [Byte0]: 50
8619 00:25:05.594817 [Byte1]: 50
8620 00:25:05.599135
8621 00:25:05.599216 Set Vref, RX VrefLevel [Byte0]: 51
8622 00:25:05.602056 [Byte1]: 51
8623 00:25:05.606866
8624 00:25:05.606946 Set Vref, RX VrefLevel [Byte0]: 52
8625 00:25:05.610025 [Byte1]: 52
8626 00:25:05.614125
8627 00:25:05.614205 Set Vref, RX VrefLevel [Byte0]: 53
8628 00:25:05.617398 [Byte1]: 53
8629 00:25:05.621674
8630 00:25:05.621755 Set Vref, RX VrefLevel [Byte0]: 54
8631 00:25:05.625132 [Byte1]: 54
8632 00:25:05.629721
8633 00:25:05.629911 Set Vref, RX VrefLevel [Byte0]: 55
8634 00:25:05.632800 [Byte1]: 55
8635 00:25:05.637227
8636 00:25:05.637308 Set Vref, RX VrefLevel [Byte0]: 56
8637 00:25:05.640545 [Byte1]: 56
8638 00:25:05.644903
8639 00:25:05.644991 Set Vref, RX VrefLevel [Byte0]: 57
8640 00:25:05.648181 [Byte1]: 57
8641 00:25:05.651985
8642 00:25:05.652066 Set Vref, RX VrefLevel [Byte0]: 58
8643 00:25:05.655560 [Byte1]: 58
8644 00:25:05.659925
8645 00:25:05.660005 Set Vref, RX VrefLevel [Byte0]: 59
8646 00:25:05.663235 [Byte1]: 59
8647 00:25:05.667582
8648 00:25:05.667663 Set Vref, RX VrefLevel [Byte0]: 60
8649 00:25:05.670823 [Byte1]: 60
8650 00:25:05.675243
8651 00:25:05.675324 Set Vref, RX VrefLevel [Byte0]: 61
8652 00:25:05.678252 [Byte1]: 61
8653 00:25:05.682818
8654 00:25:05.682900 Set Vref, RX VrefLevel [Byte0]: 62
8655 00:25:05.685748 [Byte1]: 62
8656 00:25:05.690000
8657 00:25:05.690080 Set Vref, RX VrefLevel [Byte0]: 63
8658 00:25:05.693461 [Byte1]: 63
8659 00:25:05.697989
8660 00:25:05.698069 Set Vref, RX VrefLevel [Byte0]: 64
8661 00:25:05.700982 [Byte1]: 64
8662 00:25:05.705368
8663 00:25:05.705448 Set Vref, RX VrefLevel [Byte0]: 65
8664 00:25:05.708956 [Byte1]: 65
8665 00:25:05.713055
8666 00:25:05.713136 Set Vref, RX VrefLevel [Byte0]: 66
8667 00:25:05.716465 [Byte1]: 66
8668 00:25:05.720582
8669 00:25:05.720662 Set Vref, RX VrefLevel [Byte0]: 67
8670 00:25:05.724448 [Byte1]: 67
8671 00:25:05.728567
8672 00:25:05.728647 Set Vref, RX VrefLevel [Byte0]: 68
8673 00:25:05.731483 [Byte1]: 68
8674 00:25:05.735817
8675 00:25:05.735897 Set Vref, RX VrefLevel [Byte0]: 69
8676 00:25:05.739114 [Byte1]: 69
8677 00:25:05.743478
8678 00:25:05.743560 Set Vref, RX VrefLevel [Byte0]: 70
8679 00:25:05.746992 [Byte1]: 70
8680 00:25:05.750984
8681 00:25:05.751068 Set Vref, RX VrefLevel [Byte0]: 71
8682 00:25:05.754682 [Byte1]: 71
8683 00:25:05.758852
8684 00:25:05.758933 Set Vref, RX VrefLevel [Byte0]: 72
8685 00:25:05.761965 [Byte1]: 72
8686 00:25:05.766250
8687 00:25:05.766330 Set Vref, RX VrefLevel [Byte0]: 73
8688 00:25:05.769450 [Byte1]: 73
8689 00:25:05.774032
8690 00:25:05.774112 Set Vref, RX VrefLevel [Byte0]: 74
8691 00:25:05.777316 [Byte1]: 74
8692 00:25:05.781799
8693 00:25:05.781879 Final RX Vref Byte 0 = 60 to rank0
8694 00:25:05.784816 Final RX Vref Byte 1 = 57 to rank0
8695 00:25:05.788616 Final RX Vref Byte 0 = 60 to rank1
8696 00:25:05.792149 Final RX Vref Byte 1 = 57 to rank1==
8697 00:25:05.795048 Dram Type= 6, Freq= 0, CH_1, rank 0
8698 00:25:05.798651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8699 00:25:05.801848 ==
8700 00:25:05.801929 DQS Delay:
8701 00:25:05.801992 DQS0 = 0, DQS1 = 0
8702 00:25:05.805048 DQM Delay:
8703 00:25:05.805182 DQM0 = 131, DQM1 = 124
8704 00:25:05.808506 DQ Delay:
8705 00:25:05.811890 DQ0 =134, DQ1 =124, DQ2 =120, DQ3 =130
8706 00:25:05.815230 DQ4 =130, DQ5 =142, DQ6 =144, DQ7 =128
8707 00:25:05.818804 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =118
8708 00:25:05.822077 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =130
8709 00:25:05.822161
8710 00:25:05.822225
8711 00:25:05.822284
8712 00:25:05.825306 [DramC_TX_OE_Calibration] TA2
8713 00:25:05.828540 Original DQ_B0 (3 6) =30, OEN = 27
8714 00:25:05.832047 Original DQ_B1 (3 6) =30, OEN = 27
8715 00:25:05.832129 24, 0x0, End_B0=24 End_B1=24
8716 00:25:05.835376 25, 0x0, End_B0=25 End_B1=25
8717 00:25:05.838934 26, 0x0, End_B0=26 End_B1=26
8718 00:25:05.842188 27, 0x0, End_B0=27 End_B1=27
8719 00:25:05.845329 28, 0x0, End_B0=28 End_B1=28
8720 00:25:05.845416 29, 0x0, End_B0=29 End_B1=29
8721 00:25:05.848308 30, 0x0, End_B0=30 End_B1=30
8722 00:25:05.851966 31, 0x4141, End_B0=30 End_B1=30
8723 00:25:05.855272 Byte0 end_step=30 best_step=27
8724 00:25:05.858670 Byte1 end_step=30 best_step=27
8725 00:25:05.862019 Byte0 TX OE(2T, 0.5T) = (3, 3)
8726 00:25:05.862101 Byte1 TX OE(2T, 0.5T) = (3, 3)
8727 00:25:05.862165
8728 00:25:05.862223
8729 00:25:05.871725 [DQSOSCAuto] RK0, (LSB)MR18= 0x1400, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
8730 00:25:05.875013 CH1 RK0: MR19=303, MR18=1400
8731 00:25:05.881845 CH1_RK0: MR19=0x303, MR18=0x1400, DQSOSC=399, MR23=63, INC=23, DEC=15
8732 00:25:05.881927
8733 00:25:05.885223 ----->DramcWriteLeveling(PI) begin...
8734 00:25:05.885305 ==
8735 00:25:05.888616 Dram Type= 6, Freq= 0, CH_1, rank 1
8736 00:25:05.891923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8737 00:25:05.892007 ==
8738 00:25:05.895088 Write leveling (Byte 0): 25 => 25
8739 00:25:05.898870 Write leveling (Byte 1): 25 => 25
8740 00:25:05.901879 DramcWriteLeveling(PI) end<-----
8741 00:25:05.901960
8742 00:25:05.902023 ==
8743 00:25:05.905205 Dram Type= 6, Freq= 0, CH_1, rank 1
8744 00:25:05.908508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 00:25:05.908590 ==
8746 00:25:05.911769 [Gating] SW mode calibration
8747 00:25:05.918378 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8748 00:25:05.925741 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8749 00:25:05.928867 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8750 00:25:05.931945 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 00:25:05.938398 1 4 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
8752 00:25:05.942138 1 4 12 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
8753 00:25:05.945407 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 00:25:05.948913 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8755 00:25:05.955247 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8756 00:25:05.958631 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 00:25:05.962279 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 00:25:05.968759 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8759 00:25:05.972258 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 0)
8760 00:25:05.975354 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8761 00:25:05.981825 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8762 00:25:05.985627 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 00:25:05.988710 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 00:25:05.995122 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 00:25:05.999046 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 00:25:06.002121 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 00:25:06.008816 1 6 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8768 00:25:06.011842 1 6 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
8769 00:25:06.015449 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 00:25:06.022309 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 00:25:06.025493 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8772 00:25:06.028541 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 00:25:06.032203 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 00:25:06.039105 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 00:25:06.042788 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8776 00:25:06.045531 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8777 00:25:06.052157 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8778 00:25:06.055372 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8779 00:25:06.059139 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 00:25:06.065428 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 00:25:06.069067 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 00:25:06.072071 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 00:25:06.078663 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 00:25:06.082440 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 00:25:06.085394 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 00:25:06.093068 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 00:25:06.095666 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 00:25:06.099351 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 00:25:06.102631 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 00:25:06.109132 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 00:25:06.112586 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8792 00:25:06.115657 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8793 00:25:06.118929 Total UI for P1: 0, mck2ui 16
8794 00:25:06.122416 best dqsien dly found for B0: ( 1, 9, 8)
8795 00:25:06.129169 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 00:25:06.129250 Total UI for P1: 0, mck2ui 16
8797 00:25:06.136014 best dqsien dly found for B1: ( 1, 9, 12)
8798 00:25:06.139276 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8799 00:25:06.142332 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8800 00:25:06.142413
8801 00:25:06.145937 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8802 00:25:06.149182 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8803 00:25:06.152660 [Gating] SW calibration Done
8804 00:25:06.152764 ==
8805 00:25:06.155656 Dram Type= 6, Freq= 0, CH_1, rank 1
8806 00:25:06.159089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8807 00:25:06.159183 ==
8808 00:25:06.162373 RX Vref Scan: 0
8809 00:25:06.162470
8810 00:25:06.162559 RX Vref 0 -> 0, step: 1
8811 00:25:06.162661
8812 00:25:06.165905 RX Delay 0 -> 252, step: 8
8813 00:25:06.169198 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8814 00:25:06.172965 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8815 00:25:06.179572 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8816 00:25:06.183009 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8817 00:25:06.186109 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8818 00:25:06.189575 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8819 00:25:06.192520 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8820 00:25:06.199183 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8821 00:25:06.202472 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8822 00:25:06.206245 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8823 00:25:06.209353 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8824 00:25:06.212712 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8825 00:25:06.219191 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8826 00:25:06.222967 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8827 00:25:06.225990 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8828 00:25:06.229220 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8829 00:25:06.229318 ==
8830 00:25:06.232557 Dram Type= 6, Freq= 0, CH_1, rank 1
8831 00:25:06.239069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8832 00:25:06.239155 ==
8833 00:25:06.239223 DQS Delay:
8834 00:25:06.242683 DQS0 = 0, DQS1 = 0
8835 00:25:06.242773 DQM Delay:
8836 00:25:06.242838 DQM0 = 132, DQM1 = 127
8837 00:25:06.245939 DQ Delay:
8838 00:25:06.249312 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8839 00:25:06.252869 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8840 00:25:06.255995 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8841 00:25:06.259154 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8842 00:25:06.259234
8843 00:25:06.259297
8844 00:25:06.259355 ==
8845 00:25:06.262367 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 00:25:06.265799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 00:25:06.269141 ==
8848 00:25:06.269221
8849 00:25:06.269283
8850 00:25:06.269341 TX Vref Scan disable
8851 00:25:06.272434 == TX Byte 0 ==
8852 00:25:06.275745 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8853 00:25:06.279657 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8854 00:25:06.282777 == TX Byte 1 ==
8855 00:25:06.285869 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8856 00:25:06.289448 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8857 00:25:06.289526 ==
8858 00:25:06.292431 Dram Type= 6, Freq= 0, CH_1, rank 1
8859 00:25:06.299657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8860 00:25:06.299765 ==
8861 00:25:06.312181
8862 00:25:06.315718 TX Vref early break, caculate TX vref
8863 00:25:06.318660 TX Vref=16, minBit 8, minWin=22, winSum=386
8864 00:25:06.321989 TX Vref=18, minBit 0, minWin=23, winSum=397
8865 00:25:06.325277 TX Vref=20, minBit 8, minWin=24, winSum=403
8866 00:25:06.328773 TX Vref=22, minBit 8, minWin=24, winSum=409
8867 00:25:06.331845 TX Vref=24, minBit 6, minWin=25, winSum=422
8868 00:25:06.338706 TX Vref=26, minBit 0, minWin=26, winSum=426
8869 00:25:06.341898 TX Vref=28, minBit 1, minWin=26, winSum=433
8870 00:25:06.345405 TX Vref=30, minBit 0, minWin=26, winSum=429
8871 00:25:06.349337 TX Vref=32, minBit 0, minWin=25, winSum=420
8872 00:25:06.352111 TX Vref=34, minBit 0, minWin=24, winSum=411
8873 00:25:06.355918 TX Vref=36, minBit 0, minWin=23, winSum=403
8874 00:25:06.361905 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 28
8875 00:25:06.361985
8876 00:25:06.365258 Final TX Range 0 Vref 28
8877 00:25:06.365338
8878 00:25:06.365401 ==
8879 00:25:06.369064 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 00:25:06.372218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 00:25:06.372298 ==
8882 00:25:06.372361
8883 00:25:06.372418
8884 00:25:06.375242 TX Vref Scan disable
8885 00:25:06.382179 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8886 00:25:06.382291 == TX Byte 0 ==
8887 00:25:06.385637 u2DelayCellOfst[0]=17 cells (5 PI)
8888 00:25:06.388934 u2DelayCellOfst[1]=10 cells (3 PI)
8889 00:25:06.392125 u2DelayCellOfst[2]=0 cells (0 PI)
8890 00:25:06.395563 u2DelayCellOfst[3]=7 cells (2 PI)
8891 00:25:06.398859 u2DelayCellOfst[4]=10 cells (3 PI)
8892 00:25:06.402222 u2DelayCellOfst[5]=17 cells (5 PI)
8893 00:25:06.405660 u2DelayCellOfst[6]=17 cells (5 PI)
8894 00:25:06.408663 u2DelayCellOfst[7]=7 cells (2 PI)
8895 00:25:06.412043 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8896 00:25:06.415512 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8897 00:25:06.418698 == TX Byte 1 ==
8898 00:25:06.418778 u2DelayCellOfst[8]=0 cells (0 PI)
8899 00:25:06.422350 u2DelayCellOfst[9]=7 cells (2 PI)
8900 00:25:06.425562 u2DelayCellOfst[10]=14 cells (4 PI)
8901 00:25:06.428587 u2DelayCellOfst[11]=7 cells (2 PI)
8902 00:25:06.432243 u2DelayCellOfst[12]=14 cells (4 PI)
8903 00:25:06.435370 u2DelayCellOfst[13]=17 cells (5 PI)
8904 00:25:06.438693 u2DelayCellOfst[14]=17 cells (5 PI)
8905 00:25:06.441725 u2DelayCellOfst[15]=17 cells (5 PI)
8906 00:25:06.445527 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8907 00:25:06.451881 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8908 00:25:06.451994 DramC Write-DBI on
8909 00:25:06.452060 ==
8910 00:25:06.455308 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 00:25:06.459135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 00:25:06.462031 ==
8913 00:25:06.462111
8914 00:25:06.462173
8915 00:25:06.462231 TX Vref Scan disable
8916 00:25:06.465534 == TX Byte 0 ==
8917 00:25:06.468978 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8918 00:25:06.471899 == TX Byte 1 ==
8919 00:25:06.475321 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8920 00:25:06.478398 DramC Write-DBI off
8921 00:25:06.478477
8922 00:25:06.478540 [DATLAT]
8923 00:25:06.478598 Freq=1600, CH1 RK1
8924 00:25:06.478656
8925 00:25:06.481636 DATLAT Default: 0xf
8926 00:25:06.481716 0, 0xFFFF, sum = 0
8927 00:25:06.485257 1, 0xFFFF, sum = 0
8928 00:25:06.485338 2, 0xFFFF, sum = 0
8929 00:25:06.488573 3, 0xFFFF, sum = 0
8930 00:25:06.492501 4, 0xFFFF, sum = 0
8931 00:25:06.492582 5, 0xFFFF, sum = 0
8932 00:25:06.495212 6, 0xFFFF, sum = 0
8933 00:25:06.495293 7, 0xFFFF, sum = 0
8934 00:25:06.498348 8, 0xFFFF, sum = 0
8935 00:25:06.498429 9, 0xFFFF, sum = 0
8936 00:25:06.501991 10, 0xFFFF, sum = 0
8937 00:25:06.502072 11, 0xFFFF, sum = 0
8938 00:25:06.505122 12, 0xFFFF, sum = 0
8939 00:25:06.505203 13, 0xFFFF, sum = 0
8940 00:25:06.508564 14, 0x0, sum = 1
8941 00:25:06.508644 15, 0x0, sum = 2
8942 00:25:06.511889 16, 0x0, sum = 3
8943 00:25:06.511970 17, 0x0, sum = 4
8944 00:25:06.515454 best_step = 15
8945 00:25:06.515533
8946 00:25:06.515595 ==
8947 00:25:06.518662 Dram Type= 6, Freq= 0, CH_1, rank 1
8948 00:25:06.521622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8949 00:25:06.521703 ==
8950 00:25:06.521766 RX Vref Scan: 0
8951 00:25:06.525448
8952 00:25:06.525528 RX Vref 0 -> 0, step: 1
8953 00:25:06.525593
8954 00:25:06.528547 RX Delay 11 -> 252, step: 4
8955 00:25:06.531917 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8956 00:25:06.539029 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8957 00:25:06.541956 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8958 00:25:06.544924 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8959 00:25:06.548390 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8960 00:25:06.551854 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8961 00:25:06.558880 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8962 00:25:06.561934 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8963 00:25:06.565253 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8964 00:25:06.568335 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8965 00:25:06.572109 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8966 00:25:06.578488 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8967 00:25:06.582312 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8968 00:25:06.585706 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8969 00:25:06.588575 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8970 00:25:06.591619 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8971 00:25:06.591698 ==
8972 00:25:06.595104 Dram Type= 6, Freq= 0, CH_1, rank 1
8973 00:25:06.602500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8974 00:25:06.602581 ==
8975 00:25:06.602643 DQS Delay:
8976 00:25:06.605073 DQS0 = 0, DQS1 = 0
8977 00:25:06.605153 DQM Delay:
8978 00:25:06.608611 DQM0 = 130, DQM1 = 126
8979 00:25:06.608697 DQ Delay:
8980 00:25:06.611682 DQ0 =132, DQ1 =126, DQ2 =118, DQ3 =130
8981 00:25:06.615019 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =124
8982 00:25:06.618469 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =120
8983 00:25:06.621937 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
8984 00:25:06.622017
8985 00:25:06.622080
8986 00:25:06.622138
8987 00:25:06.625340 [DramC_TX_OE_Calibration] TA2
8988 00:25:06.629067 Original DQ_B0 (3 6) =30, OEN = 27
8989 00:25:06.631807 Original DQ_B1 (3 6) =30, OEN = 27
8990 00:25:06.635058 24, 0x0, End_B0=24 End_B1=24
8991 00:25:06.635142 25, 0x0, End_B0=25 End_B1=25
8992 00:25:06.638581 26, 0x0, End_B0=26 End_B1=26
8993 00:25:06.642078 27, 0x0, End_B0=27 End_B1=27
8994 00:25:06.645177 28, 0x0, End_B0=28 End_B1=28
8995 00:25:06.648823 29, 0x0, End_B0=29 End_B1=29
8996 00:25:06.648905 30, 0x0, End_B0=30 End_B1=30
8997 00:25:06.652262 31, 0x4141, End_B0=30 End_B1=30
8998 00:25:06.655660 Byte0 end_step=30 best_step=27
8999 00:25:06.658587 Byte1 end_step=30 best_step=27
9000 00:25:06.662304 Byte0 TX OE(2T, 0.5T) = (3, 3)
9001 00:25:06.662384 Byte1 TX OE(2T, 0.5T) = (3, 3)
9002 00:25:06.665250
9003 00:25:06.665329
9004 00:25:06.672099 [DQSOSCAuto] RK1, (LSB)MR18= 0x1319, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
9005 00:25:06.675898 CH1 RK1: MR19=303, MR18=1319
9006 00:25:06.682025 CH1_RK1: MR19=0x303, MR18=0x1319, DQSOSC=397, MR23=63, INC=23, DEC=15
9007 00:25:06.685158 [RxdqsGatingPostProcess] freq 1600
9008 00:25:06.688874 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9009 00:25:06.691889 best DQS0 dly(2T, 0.5T) = (1, 1)
9010 00:25:06.695117 best DQS1 dly(2T, 0.5T) = (1, 1)
9011 00:25:06.698638 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9012 00:25:06.701954 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9013 00:25:06.705634 best DQS0 dly(2T, 0.5T) = (1, 1)
9014 00:25:06.708820 best DQS1 dly(2T, 0.5T) = (1, 1)
9015 00:25:06.712118 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9016 00:25:06.715491 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9017 00:25:06.715571 Pre-setting of DQS Precalculation
9018 00:25:06.722252 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9019 00:25:06.728601 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9020 00:25:06.735728 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9021 00:25:06.735809
9022 00:25:06.735871
9023 00:25:06.739483 [Calibration Summary] 3200 Mbps
9024 00:25:06.742231 CH 0, Rank 0
9025 00:25:06.742324 SW Impedance : PASS
9026 00:25:06.745198 DUTY Scan : NO K
9027 00:25:06.748994 ZQ Calibration : PASS
9028 00:25:06.749074 Jitter Meter : NO K
9029 00:25:06.752058 CBT Training : PASS
9030 00:25:06.755205 Write leveling : PASS
9031 00:25:06.755286 RX DQS gating : PASS
9032 00:25:06.758792 RX DQ/DQS(RDDQC) : PASS
9033 00:25:06.758872 TX DQ/DQS : PASS
9034 00:25:06.762056 RX DATLAT : PASS
9035 00:25:06.765268 RX DQ/DQS(Engine): PASS
9036 00:25:06.765348 TX OE : PASS
9037 00:25:06.768593 All Pass.
9038 00:25:06.768681
9039 00:25:06.768782 CH 0, Rank 1
9040 00:25:06.772315 SW Impedance : PASS
9041 00:25:06.772395 DUTY Scan : NO K
9042 00:25:06.775852 ZQ Calibration : PASS
9043 00:25:06.778706 Jitter Meter : NO K
9044 00:25:06.778787 CBT Training : PASS
9045 00:25:06.782437 Write leveling : PASS
9046 00:25:06.785628 RX DQS gating : PASS
9047 00:25:06.785708 RX DQ/DQS(RDDQC) : PASS
9048 00:25:06.788719 TX DQ/DQS : PASS
9049 00:25:06.792310 RX DATLAT : PASS
9050 00:25:06.792390 RX DQ/DQS(Engine): PASS
9051 00:25:06.795568 TX OE : PASS
9052 00:25:06.795648 All Pass.
9053 00:25:06.795710
9054 00:25:06.795769 CH 1, Rank 0
9055 00:25:06.798751 SW Impedance : PASS
9056 00:25:06.802323 DUTY Scan : NO K
9057 00:25:06.802402 ZQ Calibration : PASS
9058 00:25:06.805626 Jitter Meter : NO K
9059 00:25:06.809020 CBT Training : PASS
9060 00:25:06.809100 Write leveling : PASS
9061 00:25:06.812699 RX DQS gating : PASS
9062 00:25:06.815462 RX DQ/DQS(RDDQC) : PASS
9063 00:25:06.815541 TX DQ/DQS : PASS
9064 00:25:06.818753 RX DATLAT : PASS
9065 00:25:06.822188 RX DQ/DQS(Engine): PASS
9066 00:25:06.822268 TX OE : PASS
9067 00:25:06.825570 All Pass.
9068 00:25:06.825650
9069 00:25:06.825712 CH 1, Rank 1
9070 00:25:06.828979 SW Impedance : PASS
9071 00:25:06.829058 DUTY Scan : NO K
9072 00:25:06.832055 ZQ Calibration : PASS
9073 00:25:06.835770 Jitter Meter : NO K
9074 00:25:06.835850 CBT Training : PASS
9075 00:25:06.839314 Write leveling : PASS
9076 00:25:06.839395 RX DQS gating : PASS
9077 00:25:06.842308 RX DQ/DQS(RDDQC) : PASS
9078 00:25:06.845870 TX DQ/DQS : PASS
9079 00:25:06.845951 RX DATLAT : PASS
9080 00:25:06.849049 RX DQ/DQS(Engine): PASS
9081 00:25:06.852372 TX OE : PASS
9082 00:25:06.852468 All Pass.
9083 00:25:06.852559
9084 00:25:06.852647 DramC Write-DBI on
9085 00:25:06.855554 PER_BANK_REFRESH: Hybrid Mode
9086 00:25:06.859011 TX_TRACKING: ON
9087 00:25:06.865932 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9088 00:25:06.875406 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9089 00:25:06.882573 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9090 00:25:06.885820 [FAST_K] Save calibration result to emmc
9091 00:25:06.889274 sync common calibartion params.
9092 00:25:06.892311 sync cbt_mode0:1, 1:1
9093 00:25:06.892390 dram_init: ddr_geometry: 2
9094 00:25:06.895986 dram_init: ddr_geometry: 2
9095 00:25:06.899075 dram_init: ddr_geometry: 2
9096 00:25:06.899154 0:dram_rank_size:100000000
9097 00:25:06.902440 1:dram_rank_size:100000000
9098 00:25:06.909039 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9099 00:25:06.909120 DFS_SHUFFLE_HW_MODE: ON
9100 00:25:06.915477 dramc_set_vcore_voltage set vcore to 725000
9101 00:25:06.915557 Read voltage for 1600, 0
9102 00:25:06.919092 Vio18 = 0
9103 00:25:06.919172 Vcore = 725000
9104 00:25:06.919235 Vdram = 0
9105 00:25:06.922901 Vddq = 0
9106 00:25:06.922981 Vmddr = 0
9107 00:25:06.926168 switch to 3200 Mbps bootup
9108 00:25:06.926247 [DramcRunTimeConfig]
9109 00:25:06.926310 PHYPLL
9110 00:25:06.929309 DPM_CONTROL_AFTERK: ON
9111 00:25:06.929389 PER_BANK_REFRESH: ON
9112 00:25:06.932547 REFRESH_OVERHEAD_REDUCTION: ON
9113 00:25:06.936267 CMD_PICG_NEW_MODE: OFF
9114 00:25:06.936347 XRTWTW_NEW_MODE: ON
9115 00:25:06.939189 XRTRTR_NEW_MODE: ON
9116 00:25:06.939269 TX_TRACKING: ON
9117 00:25:06.943022 RDSEL_TRACKING: OFF
9118 00:25:06.946470 DQS Precalculation for DVFS: ON
9119 00:25:06.946550 RX_TRACKING: OFF
9120 00:25:06.949302 HW_GATING DBG: ON
9121 00:25:06.949381 ZQCS_ENABLE_LP4: ON
9122 00:25:06.952591 RX_PICG_NEW_MODE: ON
9123 00:25:06.952677 TX_PICG_NEW_MODE: ON
9124 00:25:06.956063 ENABLE_RX_DCM_DPHY: ON
9125 00:25:06.959222 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9126 00:25:06.962686 DUMMY_READ_FOR_TRACKING: OFF
9127 00:25:06.966246 !!! SPM_CONTROL_AFTERK: OFF
9128 00:25:06.966334 !!! SPM could not control APHY
9129 00:25:06.969403 IMPEDANCE_TRACKING: ON
9130 00:25:06.969483 TEMP_SENSOR: ON
9131 00:25:06.972661 HW_SAVE_FOR_SR: OFF
9132 00:25:06.976232 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9133 00:25:06.979772 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9134 00:25:06.982690 Read ODT Tracking: ON
9135 00:25:06.982769 Refresh Rate DeBounce: ON
9136 00:25:06.986245 DFS_NO_QUEUE_FLUSH: ON
9137 00:25:06.989377 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9138 00:25:06.992625 ENABLE_DFS_RUNTIME_MRW: OFF
9139 00:25:06.992750 DDR_RESERVE_NEW_MODE: ON
9140 00:25:06.996359 MR_CBT_SWITCH_FREQ: ON
9141 00:25:06.999602 =========================
9142 00:25:07.017078 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9143 00:25:07.020583 dram_init: ddr_geometry: 2
9144 00:25:07.038587 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9145 00:25:07.041634 dram_init: dram init end (result: 0)
9146 00:25:07.048469 DRAM-K: Full calibration passed in 24493 msecs
9147 00:25:07.051834 MRC: failed to locate region type 0.
9148 00:25:07.051914 DRAM rank0 size:0x100000000,
9149 00:25:07.054941 DRAM rank1 size=0x100000000
9150 00:25:07.064994 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9151 00:25:07.071720 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9152 00:25:07.078510 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9153 00:25:07.085473 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9154 00:25:07.088539 DRAM rank0 size:0x100000000,
9155 00:25:07.091430 DRAM rank1 size=0x100000000
9156 00:25:07.091510 CBMEM:
9157 00:25:07.094846 IMD: root @ 0xfffff000 254 entries.
9158 00:25:07.098527 IMD: root @ 0xffffec00 62 entries.
9159 00:25:07.101336 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9160 00:25:07.104779 WARNING: RO_VPD is uninitialized or empty.
9161 00:25:07.111225 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9162 00:25:07.118388 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9163 00:25:07.130893 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9164 00:25:07.142589 BS: romstage times (exec / console): total (unknown) / 24010 ms
9165 00:25:07.142670
9166 00:25:07.142733
9167 00:25:07.152808 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9168 00:25:07.156899 ARM64: Exception handlers installed.
9169 00:25:07.159077 ARM64: Testing exception
9170 00:25:07.162889 ARM64: Done test exception
9171 00:25:07.162969 Enumerating buses...
9172 00:25:07.166080 Show all devs... Before device enumeration.
9173 00:25:07.169506 Root Device: enabled 1
9174 00:25:07.172725 CPU_CLUSTER: 0: enabled 1
9175 00:25:07.172805 CPU: 00: enabled 1
9176 00:25:07.175976 Compare with tree...
9177 00:25:07.176055 Root Device: enabled 1
9178 00:25:07.179274 CPU_CLUSTER: 0: enabled 1
9179 00:25:07.182681 CPU: 00: enabled 1
9180 00:25:07.182761 Root Device scanning...
9181 00:25:07.186323 scan_static_bus for Root Device
9182 00:25:07.189210 CPU_CLUSTER: 0 enabled
9183 00:25:07.192833 scan_static_bus for Root Device done
9184 00:25:07.196319 scan_bus: bus Root Device finished in 8 msecs
9185 00:25:07.196399 done
9186 00:25:07.202456 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9187 00:25:07.206285 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9188 00:25:07.212744 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9189 00:25:07.216007 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9190 00:25:07.219410 Allocating resources...
9191 00:25:07.219490 Reading resources...
9192 00:25:07.225936 Root Device read_resources bus 0 link: 0
9193 00:25:07.226016 DRAM rank0 size:0x100000000,
9194 00:25:07.229036 DRAM rank1 size=0x100000000
9195 00:25:07.232564 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9196 00:25:07.235730 CPU: 00 missing read_resources
9197 00:25:07.239096 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9198 00:25:07.245840 Root Device read_resources bus 0 link: 0 done
9199 00:25:07.245921 Done reading resources.
9200 00:25:07.252648 Show resources in subtree (Root Device)...After reading.
9201 00:25:07.255886 Root Device child on link 0 CPU_CLUSTER: 0
9202 00:25:07.259006 CPU_CLUSTER: 0 child on link 0 CPU: 00
9203 00:25:07.269468 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9204 00:25:07.269550 CPU: 00
9205 00:25:07.272515 Root Device assign_resources, bus 0 link: 0
9206 00:25:07.275888 CPU_CLUSTER: 0 missing set_resources
9207 00:25:07.279126 Root Device assign_resources, bus 0 link: 0 done
9208 00:25:07.282369 Done setting resources.
9209 00:25:07.289435 Show resources in subtree (Root Device)...After assigning values.
9210 00:25:07.292680 Root Device child on link 0 CPU_CLUSTER: 0
9211 00:25:07.295920 CPU_CLUSTER: 0 child on link 0 CPU: 00
9212 00:25:07.305897 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9213 00:25:07.305978 CPU: 00
9214 00:25:07.309044 Done allocating resources.
9215 00:25:07.312819 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9216 00:25:07.315884 Enabling resources...
9217 00:25:07.315964 done.
9218 00:25:07.319045 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9219 00:25:07.322826 Initializing devices...
9220 00:25:07.322905 Root Device init
9221 00:25:07.326262 init hardware done!
9222 00:25:07.329196 0x00000018: ctrlr->caps
9223 00:25:07.329278 52.000 MHz: ctrlr->f_max
9224 00:25:07.332893 0.400 MHz: ctrlr->f_min
9225 00:25:07.336078 0x40ff8080: ctrlr->voltages
9226 00:25:07.336160 sclk: 390625
9227 00:25:07.336223 Bus Width = 1
9228 00:25:07.339750 sclk: 390625
9229 00:25:07.339830 Bus Width = 1
9230 00:25:07.342835 Early init status = 3
9231 00:25:07.346392 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9232 00:25:07.350064 in-header: 03 fc 00 00 01 00 00 00
9233 00:25:07.353478 in-data: 00
9234 00:25:07.356439 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9235 00:25:07.361578 in-header: 03 fd 00 00 00 00 00 00
9236 00:25:07.364509 in-data:
9237 00:25:07.367929 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9238 00:25:07.371588 in-header: 03 fc 00 00 01 00 00 00
9239 00:25:07.374510 in-data: 00
9240 00:25:07.377838 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9241 00:25:07.382944 in-header: 03 fd 00 00 00 00 00 00
9242 00:25:07.386701 in-data:
9243 00:25:07.389618 [SSUSB] Setting up USB HOST controller...
9244 00:25:07.392970 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9245 00:25:07.396592 [SSUSB] phy power-on done.
9246 00:25:07.399494 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9247 00:25:07.406349 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9248 00:25:07.409564 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9249 00:25:07.416443 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9250 00:25:07.423043 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9251 00:25:07.429589 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9252 00:25:07.436431 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9253 00:25:07.443056 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9254 00:25:07.446581 SPM: binary array size = 0x9dc
9255 00:25:07.449762 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9256 00:25:07.456862 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9257 00:25:07.463179 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9258 00:25:07.466497 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9259 00:25:07.469887 configure_display: Starting display init
9260 00:25:07.506224 anx7625_power_on_init: Init interface.
9261 00:25:07.509570 anx7625_disable_pd_protocol: Disabled PD feature.
9262 00:25:07.512649 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9263 00:25:07.540996 anx7625_start_dp_work: Secure OCM version=00
9264 00:25:07.543850 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9265 00:25:07.558695 sp_tx_get_edid_block: EDID Block = 1
9266 00:25:07.662334 Extracted contents:
9267 00:25:07.664834 header: 00 ff ff ff ff ff ff 00
9268 00:25:07.667802 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9269 00:25:07.671105 version: 01 04
9270 00:25:07.674910 basic params: 95 1f 11 78 0a
9271 00:25:07.677750 chroma info: 76 90 94 55 54 90 27 21 50 54
9272 00:25:07.681528 established: 00 00 00
9273 00:25:07.687780 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9274 00:25:07.691136 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9275 00:25:07.697741 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9276 00:25:07.704834 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9277 00:25:07.711124 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9278 00:25:07.714447 extensions: 00
9279 00:25:07.714528 checksum: fb
9280 00:25:07.714591
9281 00:25:07.718053 Manufacturer: IVO Model 57d Serial Number 0
9282 00:25:07.721383 Made week 0 of 2020
9283 00:25:07.721463 EDID version: 1.4
9284 00:25:07.725093 Digital display
9285 00:25:07.728052 6 bits per primary color channel
9286 00:25:07.728136 DisplayPort interface
9287 00:25:07.731541 Maximum image size: 31 cm x 17 cm
9288 00:25:07.731622 Gamma: 220%
9289 00:25:07.734760 Check DPMS levels
9290 00:25:07.737870 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9291 00:25:07.741501 First detailed timing is preferred timing
9292 00:25:07.744877 Established timings supported:
9293 00:25:07.747789 Standard timings supported:
9294 00:25:07.747870 Detailed timings
9295 00:25:07.754465 Hex of detail: 383680a07038204018303c0035ae10000019
9296 00:25:07.757994 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9297 00:25:07.761513 0780 0798 07c8 0820 hborder 0
9298 00:25:07.768260 0438 043b 0447 0458 vborder 0
9299 00:25:07.768342 -hsync -vsync
9300 00:25:07.771379 Did detailed timing
9301 00:25:07.774625 Hex of detail: 000000000000000000000000000000000000
9302 00:25:07.778161 Manufacturer-specified data, tag 0
9303 00:25:07.785312 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9304 00:25:07.785392 ASCII string: InfoVision
9305 00:25:07.791832 Hex of detail: 000000fe00523134304e574635205248200a
9306 00:25:07.791912 ASCII string: R140NWF5 RH
9307 00:25:07.794846 Checksum
9308 00:25:07.794925 Checksum: 0xfb (valid)
9309 00:25:07.801836 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9310 00:25:07.801916 DSI data_rate: 832800000 bps
9311 00:25:07.809083 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9312 00:25:07.812450 anx7625_parse_edid: pixelclock(138800).
9313 00:25:07.815964 hactive(1920), hsync(48), hfp(24), hbp(88)
9314 00:25:07.819289 vactive(1080), vsync(12), vfp(3), vbp(17)
9315 00:25:07.822463 anx7625_dsi_config: config dsi.
9316 00:25:07.829323 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9317 00:25:07.843337 anx7625_dsi_config: success to config DSI
9318 00:25:07.847270 anx7625_dp_start: MIPI phy setup OK.
9319 00:25:07.849806 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9320 00:25:07.853398 mtk_ddp_mode_set invalid vrefresh 60
9321 00:25:07.856613 main_disp_path_setup
9322 00:25:07.856732 ovl_layer_smi_id_en
9323 00:25:07.860075 ovl_layer_smi_id_en
9324 00:25:07.860155 ccorr_config
9325 00:25:07.860218 aal_config
9326 00:25:07.863128 gamma_config
9327 00:25:07.863207 postmask_config
9328 00:25:07.866379 dither_config
9329 00:25:07.869796 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9330 00:25:07.876783 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9331 00:25:07.879986 Root Device init finished in 551 msecs
9332 00:25:07.880065 CPU_CLUSTER: 0 init
9333 00:25:07.890233 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9334 00:25:07.893179 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9335 00:25:07.896902 APU_MBOX 0x190000b0 = 0x10001
9336 00:25:07.899864 APU_MBOX 0x190001b0 = 0x10001
9337 00:25:07.903587 APU_MBOX 0x190005b0 = 0x10001
9338 00:25:07.906803 APU_MBOX 0x190006b0 = 0x10001
9339 00:25:07.909912 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9340 00:25:07.922218 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9341 00:25:07.934891 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9342 00:25:07.941534 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9343 00:25:07.953053 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9344 00:25:07.962301 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9345 00:25:07.965722 CPU_CLUSTER: 0 init finished in 81 msecs
9346 00:25:07.969101 Devices initialized
9347 00:25:07.972189 Show all devs... After init.
9348 00:25:07.972269 Root Device: enabled 1
9349 00:25:07.975881 CPU_CLUSTER: 0: enabled 1
9350 00:25:07.978783 CPU: 00: enabled 1
9351 00:25:07.982232 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9352 00:25:07.985619 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9353 00:25:07.989349 ELOG: NV offset 0x57f000 size 0x1000
9354 00:25:07.995412 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9355 00:25:08.002285 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9356 00:25:08.005894 ELOG: Event(17) added with size 13 at 2023-08-14 00:25:11 UTC
9357 00:25:08.009051 out: cmd=0x121: 03 db 21 01 00 00 00 00
9358 00:25:08.013364 in-header: 03 2f 00 00 2c 00 00 00
9359 00:25:08.026523 in-data: 30 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9360 00:25:08.033051 ELOG: Event(A1) added with size 10 at 2023-08-14 00:25:11 UTC
9361 00:25:08.040018 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9362 00:25:08.046454 ELOG: Event(A0) added with size 9 at 2023-08-14 00:25:11 UTC
9363 00:25:08.049980 elog_add_boot_reason: Logged dev mode boot
9364 00:25:08.053382 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9365 00:25:08.056838 Finalize devices...
9366 00:25:08.056918 Devices finalized
9367 00:25:08.063149 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9368 00:25:08.066602 Writing coreboot table at 0xffe64000
9369 00:25:08.070315 0. 000000000010a000-0000000000113fff: RAMSTAGE
9370 00:25:08.073265 1. 0000000040000000-00000000400fffff: RAM
9371 00:25:08.076507 2. 0000000040100000-000000004032afff: RAMSTAGE
9372 00:25:08.083200 3. 000000004032b000-00000000545fffff: RAM
9373 00:25:08.086546 4. 0000000054600000-000000005465ffff: BL31
9374 00:25:08.089747 5. 0000000054660000-00000000ffe63fff: RAM
9375 00:25:08.093470 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9376 00:25:08.100535 7. 0000000100000000-000000023fffffff: RAM
9377 00:25:08.100640 Passing 5 GPIOs to payload:
9378 00:25:08.106426 NAME | PORT | POLARITY | VALUE
9379 00:25:08.109874 EC in RW | 0x000000aa | low | undefined
9380 00:25:08.116636 EC interrupt | 0x00000005 | low | undefined
9381 00:25:08.119948 TPM interrupt | 0x000000ab | high | undefined
9382 00:25:08.123698 SD card detect | 0x00000011 | high | undefined
9383 00:25:08.129844 speaker enable | 0x00000093 | high | undefined
9384 00:25:08.133469 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9385 00:25:08.137041 in-header: 03 f9 00 00 02 00 00 00
9386 00:25:08.137121 in-data: 02 00
9387 00:25:08.140354 ADC[4]: Raw value=899483 ID=7
9388 00:25:08.143231 ADC[3]: Raw value=212967 ID=1
9389 00:25:08.143337 RAM Code: 0x71
9390 00:25:08.147069 ADC[6]: Raw value=74557 ID=0
9391 00:25:08.150039 ADC[5]: Raw value=212229 ID=1
9392 00:25:08.150119 SKU Code: 0x1
9393 00:25:08.156586 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ae41
9394 00:25:08.160065 coreboot table: 964 bytes.
9395 00:25:08.163434 IMD ROOT 0. 0xfffff000 0x00001000
9396 00:25:08.166842 IMD SMALL 1. 0xffffe000 0x00001000
9397 00:25:08.170277 RO MCACHE 2. 0xffffc000 0x00001104
9398 00:25:08.173793 CONSOLE 3. 0xfff7c000 0x00080000
9399 00:25:08.176981 FMAP 4. 0xfff7b000 0x00000452
9400 00:25:08.180015 TIME STAMP 5. 0xfff7a000 0x00000910
9401 00:25:08.183472 VBOOT WORK 6. 0xfff66000 0x00014000
9402 00:25:08.187411 RAMOOPS 7. 0xffe66000 0x00100000
9403 00:25:08.187491 COREBOOT 8. 0xffe64000 0x00002000
9404 00:25:08.190443 IMD small region:
9405 00:25:08.193522 IMD ROOT 0. 0xffffec00 0x00000400
9406 00:25:08.197013 VPD 1. 0xffffeba0 0x0000004c
9407 00:25:08.200581 MMC STATUS 2. 0xffffeb80 0x00000004
9408 00:25:08.206754 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9409 00:25:08.206835 Probing TPM: done!
9410 00:25:08.213835 Connected to device vid:did:rid of 1ae0:0028:00
9411 00:25:08.220629 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9412 00:25:08.224027 Initialized TPM device CR50 revision 0
9413 00:25:08.227772 Checking cr50 for pending updates
9414 00:25:08.233709 Reading cr50 TPM mode
9415 00:25:08.241377 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9416 00:25:08.248293 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9417 00:25:08.288206 read SPI 0x3990ec 0x4f1b0: 34857 us, 9295 KB/s, 74.360 Mbps
9418 00:25:08.291376 Checking segment from ROM address 0x40100000
9419 00:25:08.294853 Checking segment from ROM address 0x4010001c
9420 00:25:08.301585 Loading segment from ROM address 0x40100000
9421 00:25:08.301667 code (compression=0)
9422 00:25:08.308266 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9423 00:25:08.318565 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9424 00:25:08.318648 it's not compressed!
9425 00:25:08.325609 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9426 00:25:08.328437 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9427 00:25:08.348879 Loading segment from ROM address 0x4010001c
9428 00:25:08.348963 Entry Point 0x80000000
9429 00:25:08.351978 Loaded segments
9430 00:25:08.355304 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9431 00:25:08.362137 Jumping to boot code at 0x80000000(0xffe64000)
9432 00:25:08.368800 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9433 00:25:08.375133 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9434 00:25:08.382770 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9435 00:25:08.386300 Checking segment from ROM address 0x40100000
9436 00:25:08.389539 Checking segment from ROM address 0x4010001c
9437 00:25:08.396469 Loading segment from ROM address 0x40100000
9438 00:25:08.396551 code (compression=1)
9439 00:25:08.403434 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9440 00:25:08.410223 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9441 00:25:08.413492 using LZMA
9442 00:25:08.421592 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9443 00:25:08.427940 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9444 00:25:08.431249 Loading segment from ROM address 0x4010001c
9445 00:25:08.431330 Entry Point 0x54601000
9446 00:25:08.434830 Loaded segments
9447 00:25:08.438153 NOTICE: MT8192 bl31_setup
9448 00:25:08.444957 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9449 00:25:08.448296 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9450 00:25:08.452036 WARNING: region 0:
9451 00:25:08.455239 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9452 00:25:08.455320 WARNING: region 1:
9453 00:25:08.461657 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9454 00:25:08.465058 WARNING: region 2:
9455 00:25:08.468537 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9456 00:25:08.471810 WARNING: region 3:
9457 00:25:08.475829 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9458 00:25:08.478249 WARNING: region 4:
9459 00:25:08.481794 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9460 00:25:08.485261 WARNING: region 5:
9461 00:25:08.488373 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9462 00:25:08.491953 WARNING: region 6:
9463 00:25:08.495228 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 00:25:08.495310 WARNING: region 7:
9465 00:25:08.502176 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9466 00:25:08.508884 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9467 00:25:08.512097 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9468 00:25:08.515439 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9469 00:25:08.518994 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9470 00:25:08.525994 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9471 00:25:08.529257 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9472 00:25:08.535730 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9473 00:25:08.539318 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9474 00:25:08.542725 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9475 00:25:08.549673 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9476 00:25:08.552584 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9477 00:25:08.556080 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9478 00:25:08.562620 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9479 00:25:08.566310 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9480 00:25:08.569683 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9481 00:25:08.576366 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9482 00:25:08.579802 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9483 00:25:08.583396 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9484 00:25:08.589334 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9485 00:25:08.592725 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9486 00:25:08.599436 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9487 00:25:08.603087 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9488 00:25:08.606323 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9489 00:25:08.613213 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9490 00:25:08.616424 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9491 00:25:08.619868 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9492 00:25:08.626524 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9493 00:25:08.629784 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9494 00:25:08.636295 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9495 00:25:08.640051 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9496 00:25:08.643205 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9497 00:25:08.649728 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9498 00:25:08.653883 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9499 00:25:08.657179 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9500 00:25:08.660309 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9501 00:25:08.666580 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9502 00:25:08.670445 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9503 00:25:08.673671 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9504 00:25:08.676823 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9505 00:25:08.683989 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9506 00:25:08.686672 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9507 00:25:08.690180 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9508 00:25:08.693561 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9509 00:25:08.700193 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9510 00:25:08.703896 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9511 00:25:08.706924 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9512 00:25:08.710671 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9513 00:25:08.717111 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9514 00:25:08.720856 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9515 00:25:08.723712 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9516 00:25:08.730980 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9517 00:25:08.733847 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9518 00:25:08.740691 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9519 00:25:08.744115 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9520 00:25:08.750776 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9521 00:25:08.754338 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9522 00:25:08.757791 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9523 00:25:08.764451 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9524 00:25:08.767874 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9525 00:25:08.774189 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9526 00:25:08.777642 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9527 00:25:08.781241 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9528 00:25:08.787872 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9529 00:25:08.791466 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9530 00:25:08.797770 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9531 00:25:08.801160 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9532 00:25:08.808070 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9533 00:25:08.811124 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9534 00:25:08.814465 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9535 00:25:08.821264 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9536 00:25:08.825017 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9537 00:25:08.831516 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9538 00:25:08.834693 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9539 00:25:08.838702 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9540 00:25:08.845417 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9541 00:25:08.848610 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9542 00:25:08.854922 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9543 00:25:08.858238 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9544 00:25:08.864896 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9545 00:25:08.868446 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9546 00:25:08.871756 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9547 00:25:08.878781 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9548 00:25:08.881967 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9549 00:25:08.888641 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9550 00:25:08.891807 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9551 00:25:08.898694 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9552 00:25:08.902418 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9553 00:25:08.905274 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9554 00:25:08.912382 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9555 00:25:08.915648 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9556 00:25:08.922159 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9557 00:25:08.925392 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9558 00:25:08.928799 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9559 00:25:08.936033 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9560 00:25:08.939116 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9561 00:25:08.946198 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9562 00:25:08.948954 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9563 00:25:08.952967 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9564 00:25:08.956017 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9565 00:25:08.962653 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9566 00:25:08.966144 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9567 00:25:08.969570 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9568 00:25:08.976326 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9569 00:25:08.979382 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9570 00:25:08.986431 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9571 00:25:08.989376 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9572 00:25:08.992941 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9573 00:25:08.999552 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9574 00:25:09.003051 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9575 00:25:09.006344 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9576 00:25:09.013107 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9577 00:25:09.016273 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9578 00:25:09.023082 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9579 00:25:09.026446 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9580 00:25:09.029531 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9581 00:25:09.036162 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9582 00:25:09.039839 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9583 00:25:09.042833 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9584 00:25:09.049994 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9585 00:25:09.052947 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9586 00:25:09.056379 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9587 00:25:09.059988 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9588 00:25:09.063102 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9589 00:25:09.069801 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9590 00:25:09.073330 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9591 00:25:09.079966 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9592 00:25:09.083318 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9593 00:25:09.086500 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9594 00:25:09.093394 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9595 00:25:09.096947 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9596 00:25:09.100047 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9597 00:25:09.106757 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9598 00:25:09.110176 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9599 00:25:09.116683 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9600 00:25:09.120373 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9601 00:25:09.123501 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9602 00:25:09.130817 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9603 00:25:09.133857 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9604 00:25:09.137366 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9605 00:25:09.143626 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9606 00:25:09.147311 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9607 00:25:09.154113 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9608 00:25:09.157510 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9609 00:25:09.160763 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9610 00:25:09.167573 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9611 00:25:09.170862 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9612 00:25:09.174027 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9613 00:25:09.180980 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9614 00:25:09.184509 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9615 00:25:09.191678 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9616 00:25:09.194615 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9617 00:25:09.197508 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9618 00:25:09.204197 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9619 00:25:09.207687 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9620 00:25:09.210913 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9621 00:25:09.217838 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9622 00:25:09.221123 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9623 00:25:09.227800 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9624 00:25:09.231144 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9625 00:25:09.234699 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9626 00:25:09.241707 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9627 00:25:09.244569 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9628 00:25:09.248292 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9629 00:25:09.254991 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9630 00:25:09.258250 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9631 00:25:09.261275 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9632 00:25:09.268163 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9633 00:25:09.271798 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9634 00:25:09.277818 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9635 00:25:09.281343 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9636 00:25:09.284958 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9637 00:25:09.291660 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9638 00:25:09.294848 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9639 00:25:09.298225 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9640 00:25:09.305008 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9641 00:25:09.308170 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9642 00:25:09.314766 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9643 00:25:09.318833 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9644 00:25:09.321694 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9645 00:25:09.328381 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9646 00:25:09.331746 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9647 00:25:09.338454 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9648 00:25:09.341757 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9649 00:25:09.344937 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9650 00:25:09.351788 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9651 00:25:09.355058 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9652 00:25:09.361599 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9653 00:25:09.365239 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9654 00:25:09.368110 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9655 00:25:09.374853 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9656 00:25:09.378590 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9657 00:25:09.384997 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9658 00:25:09.388372 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9659 00:25:09.391281 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9660 00:25:09.398406 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9661 00:25:09.401428 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9662 00:25:09.408213 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9663 00:25:09.411417 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9664 00:25:09.415039 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9665 00:25:09.422123 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9666 00:25:09.425314 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9667 00:25:09.432008 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9668 00:25:09.434955 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9669 00:25:09.438797 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9670 00:25:09.445285 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9671 00:25:09.448768 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9672 00:25:09.455264 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9673 00:25:09.458425 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9674 00:25:09.461899 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9675 00:25:09.468932 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9676 00:25:09.472333 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9677 00:25:09.478986 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9678 00:25:09.482116 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9679 00:25:09.485600 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9680 00:25:09.491879 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9681 00:25:09.495463 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9682 00:25:09.501967 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9683 00:25:09.505913 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9684 00:25:09.508925 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9685 00:25:09.515211 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9686 00:25:09.518948 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9687 00:25:09.525907 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9688 00:25:09.528749 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9689 00:25:09.535396 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9690 00:25:09.538967 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9691 00:25:09.542082 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9692 00:25:09.548988 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9693 00:25:09.552451 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9694 00:25:09.559094 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9695 00:25:09.562462 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9696 00:25:09.565734 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9697 00:25:09.569207 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9698 00:25:09.572457 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9699 00:25:09.579008 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9700 00:25:09.582189 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9701 00:25:09.585699 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9702 00:25:09.592354 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9703 00:25:09.596227 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9704 00:25:09.598869 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9705 00:25:09.605662 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9706 00:25:09.609130 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9707 00:25:09.615821 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9708 00:25:09.618987 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9709 00:25:09.622596 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9710 00:25:09.629696 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9711 00:25:09.632893 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9712 00:25:09.635813 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9713 00:25:09.642410 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9714 00:25:09.645820 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9715 00:25:09.649061 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9716 00:25:09.655974 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9717 00:25:09.659640 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9718 00:25:09.662938 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9719 00:25:09.669258 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9720 00:25:09.673043 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9721 00:25:09.676169 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9722 00:25:09.682943 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9723 00:25:09.686526 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9724 00:25:09.689623 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9725 00:25:09.695971 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9726 00:25:09.699295 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9727 00:25:09.706003 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9728 00:25:09.709479 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9729 00:25:09.712775 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9730 00:25:09.719713 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9731 00:25:09.722926 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9732 00:25:09.725990 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9733 00:25:09.732959 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9734 00:25:09.736204 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9735 00:25:09.740161 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9736 00:25:09.743090 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9737 00:25:09.749279 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9738 00:25:09.752913 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9739 00:25:09.756496 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9740 00:25:09.759438 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9741 00:25:09.766028 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9742 00:25:09.769754 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9743 00:25:09.772802 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9744 00:25:09.776228 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9745 00:25:09.783171 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9746 00:25:09.785988 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9747 00:25:09.789893 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9748 00:25:09.796157 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9749 00:25:09.799807 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9750 00:25:09.803179 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9751 00:25:09.809387 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9752 00:25:09.813345 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9753 00:25:09.819512 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9754 00:25:09.822875 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9755 00:25:09.826728 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9756 00:25:09.833080 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9757 00:25:09.836439 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9758 00:25:09.843239 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9759 00:25:09.846806 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9760 00:25:09.850158 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9761 00:25:09.856589 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9762 00:25:09.860255 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9763 00:25:09.866561 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9764 00:25:09.870061 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9765 00:25:09.873704 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9766 00:25:09.880124 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9767 00:25:09.883309 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9768 00:25:09.890122 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9769 00:25:09.893601 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9770 00:25:09.896519 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9771 00:25:09.903411 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9772 00:25:09.906919 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9773 00:25:09.913384 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9774 00:25:09.916512 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9775 00:25:09.920306 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9776 00:25:09.927112 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9777 00:25:09.930109 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9778 00:25:09.936647 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9779 00:25:09.939911 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9780 00:25:09.943356 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9781 00:25:09.950010 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9782 00:25:09.953254 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9783 00:25:09.959829 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9784 00:25:09.963228 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9785 00:25:09.966539 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9786 00:25:09.973387 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9787 00:25:09.976787 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9788 00:25:09.983313 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9789 00:25:09.986775 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9790 00:25:09.990017 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9791 00:25:09.996784 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9792 00:25:10.000394 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9793 00:25:10.006682 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9794 00:25:10.010061 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9795 00:25:10.013950 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9796 00:25:10.020296 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9797 00:25:10.023900 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9798 00:25:10.030542 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9799 00:25:10.033712 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9800 00:25:10.037331 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9801 00:25:10.043942 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9802 00:25:10.047413 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9803 00:25:10.053917 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9804 00:25:10.057160 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9805 00:25:10.060595 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9806 00:25:10.067657 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9807 00:25:10.070961 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9808 00:25:10.078051 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9809 00:25:10.080992 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9810 00:25:10.083863 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9811 00:25:10.090842 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9812 00:25:10.094373 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9813 00:25:10.098183 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9814 00:25:10.103963 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9815 00:25:10.107755 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9816 00:25:10.114118 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9817 00:25:10.117402 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9818 00:25:10.123918 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9819 00:25:10.127344 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9820 00:25:10.130811 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9821 00:25:10.137429 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9822 00:25:10.140374 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9823 00:25:10.147446 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9824 00:25:10.150320 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9825 00:25:10.157263 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9826 00:25:10.160605 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9827 00:25:10.163817 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9828 00:25:10.170614 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9829 00:25:10.174178 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9830 00:25:10.180550 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9831 00:25:10.183507 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9832 00:25:10.190275 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9833 00:25:10.193607 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9834 00:25:10.200492 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9835 00:25:10.203623 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9836 00:25:10.206712 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9837 00:25:10.213927 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9838 00:25:10.217136 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9839 00:25:10.223338 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9840 00:25:10.226759 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9841 00:25:10.233525 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9842 00:25:10.236626 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9843 00:25:10.240070 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9844 00:25:10.246683 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9845 00:25:10.250435 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9846 00:25:10.256936 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9847 00:25:10.260653 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9848 00:25:10.263510 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9849 00:25:10.270389 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9850 00:25:10.273648 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9851 00:25:10.280101 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9852 00:25:10.283659 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9853 00:25:10.290075 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9854 00:25:10.293586 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9855 00:25:10.297137 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9856 00:25:10.303492 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9857 00:25:10.306710 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9858 00:25:10.313904 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9859 00:25:10.317021 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9860 00:25:10.324082 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9861 00:25:10.327210 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9862 00:25:10.330266 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9863 00:25:10.337231 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9864 00:25:10.340373 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9865 00:25:10.347165 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9866 00:25:10.350726 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9867 00:25:10.353638 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9868 00:25:10.360221 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9869 00:25:10.363538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9870 00:25:10.370165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9871 00:25:10.373716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9872 00:25:10.380379 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9873 00:25:10.383597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9874 00:25:10.390531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9875 00:25:10.393648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9876 00:25:10.400675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9877 00:25:10.403662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9878 00:25:10.410076 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9879 00:25:10.413645 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9880 00:25:10.417522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9881 00:25:10.424104 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9882 00:25:10.426963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9883 00:25:10.433682 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9884 00:25:10.437384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9885 00:25:10.444050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9886 00:25:10.447072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9887 00:25:10.453705 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9888 00:25:10.457041 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9889 00:25:10.464276 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9890 00:25:10.467059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9891 00:25:10.474356 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9892 00:25:10.477297 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9893 00:25:10.483980 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9894 00:25:10.487213 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9895 00:25:10.493744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9896 00:25:10.497538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9897 00:25:10.503703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9898 00:25:10.507181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9899 00:25:10.513915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9900 00:25:10.517532 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9901 00:25:10.517612 INFO: [APUAPC] vio 0
9902 00:25:10.524887 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9903 00:25:10.528051 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9904 00:25:10.531849 INFO: [APUAPC] D0_APC_0: 0x400510
9905 00:25:10.535207 INFO: [APUAPC] D0_APC_1: 0x0
9906 00:25:10.538192 INFO: [APUAPC] D0_APC_2: 0x1540
9907 00:25:10.541481 INFO: [APUAPC] D0_APC_3: 0x0
9908 00:25:10.545012 INFO: [APUAPC] D1_APC_0: 0xffffffff
9909 00:25:10.549163 INFO: [APUAPC] D1_APC_1: 0xffffffff
9910 00:25:10.551730 INFO: [APUAPC] D1_APC_2: 0x3fffff
9911 00:25:10.554888 INFO: [APUAPC] D1_APC_3: 0x0
9912 00:25:10.558436 INFO: [APUAPC] D2_APC_0: 0xffffffff
9913 00:25:10.561722 INFO: [APUAPC] D2_APC_1: 0xffffffff
9914 00:25:10.564997 INFO: [APUAPC] D2_APC_2: 0x3fffff
9915 00:25:10.568219 INFO: [APUAPC] D2_APC_3: 0x0
9916 00:25:10.571545 INFO: [APUAPC] D3_APC_0: 0xffffffff
9917 00:25:10.574705 INFO: [APUAPC] D3_APC_1: 0xffffffff
9918 00:25:10.578043 INFO: [APUAPC] D3_APC_2: 0x3fffff
9919 00:25:10.578121 INFO: [APUAPC] D3_APC_3: 0x0
9920 00:25:10.581878 INFO: [APUAPC] D4_APC_0: 0xffffffff
9921 00:25:10.588558 INFO: [APUAPC] D4_APC_1: 0xffffffff
9922 00:25:10.588637 INFO: [APUAPC] D4_APC_2: 0x3fffff
9923 00:25:10.591829 INFO: [APUAPC] D4_APC_3: 0x0
9924 00:25:10.595200 INFO: [APUAPC] D5_APC_0: 0xffffffff
9925 00:25:10.598289 INFO: [APUAPC] D5_APC_1: 0xffffffff
9926 00:25:10.601921 INFO: [APUAPC] D5_APC_2: 0x3fffff
9927 00:25:10.604907 INFO: [APUAPC] D5_APC_3: 0x0
9928 00:25:10.608144 INFO: [APUAPC] D6_APC_0: 0xffffffff
9929 00:25:10.612207 INFO: [APUAPC] D6_APC_1: 0xffffffff
9930 00:25:10.614827 INFO: [APUAPC] D6_APC_2: 0x3fffff
9931 00:25:10.618366 INFO: [APUAPC] D6_APC_3: 0x0
9932 00:25:10.621709 INFO: [APUAPC] D7_APC_0: 0xffffffff
9933 00:25:10.624605 INFO: [APUAPC] D7_APC_1: 0xffffffff
9934 00:25:10.628249 INFO: [APUAPC] D7_APC_2: 0x3fffff
9935 00:25:10.631515 INFO: [APUAPC] D7_APC_3: 0x0
9936 00:25:10.634813 INFO: [APUAPC] D8_APC_0: 0xffffffff
9937 00:25:10.638336 INFO: [APUAPC] D8_APC_1: 0xffffffff
9938 00:25:10.641510 INFO: [APUAPC] D8_APC_2: 0x3fffff
9939 00:25:10.645525 INFO: [APUAPC] D8_APC_3: 0x0
9940 00:25:10.648528 INFO: [APUAPC] D9_APC_0: 0xffffffff
9941 00:25:10.651607 INFO: [APUAPC] D9_APC_1: 0xffffffff
9942 00:25:10.654783 INFO: [APUAPC] D9_APC_2: 0x3fffff
9943 00:25:10.658215 INFO: [APUAPC] D9_APC_3: 0x0
9944 00:25:10.661611 INFO: [APUAPC] D10_APC_0: 0xffffffff
9945 00:25:10.665303 INFO: [APUAPC] D10_APC_1: 0xffffffff
9946 00:25:10.668219 INFO: [APUAPC] D10_APC_2: 0x3fffff
9947 00:25:10.671561 INFO: [APUAPC] D10_APC_3: 0x0
9948 00:25:10.675089 INFO: [APUAPC] D11_APC_0: 0xffffffff
9949 00:25:10.678322 INFO: [APUAPC] D11_APC_1: 0xffffffff
9950 00:25:10.681730 INFO: [APUAPC] D11_APC_2: 0x3fffff
9951 00:25:10.684808 INFO: [APUAPC] D11_APC_3: 0x0
9952 00:25:10.688489 INFO: [APUAPC] D12_APC_0: 0xffffffff
9953 00:25:10.691985 INFO: [APUAPC] D12_APC_1: 0xffffffff
9954 00:25:10.695217 INFO: [APUAPC] D12_APC_2: 0x3fffff
9955 00:25:10.698308 INFO: [APUAPC] D12_APC_3: 0x0
9956 00:25:10.702196 INFO: [APUAPC] D13_APC_0: 0xffffffff
9957 00:25:10.705136 INFO: [APUAPC] D13_APC_1: 0xffffffff
9958 00:25:10.708540 INFO: [APUAPC] D13_APC_2: 0x3fffff
9959 00:25:10.712280 INFO: [APUAPC] D13_APC_3: 0x0
9960 00:25:10.715001 INFO: [APUAPC] D14_APC_0: 0xffffffff
9961 00:25:10.718487 INFO: [APUAPC] D14_APC_1: 0xffffffff
9962 00:25:10.721851 INFO: [APUAPC] D14_APC_2: 0x3fffff
9963 00:25:10.725066 INFO: [APUAPC] D14_APC_3: 0x0
9964 00:25:10.728398 INFO: [APUAPC] D15_APC_0: 0xffffffff
9965 00:25:10.731580 INFO: [APUAPC] D15_APC_1: 0xffffffff
9966 00:25:10.735310 INFO: [APUAPC] D15_APC_2: 0x3fffff
9967 00:25:10.738866 INFO: [APUAPC] D15_APC_3: 0x0
9968 00:25:10.741674 INFO: [APUAPC] APC_CON: 0x4
9969 00:25:10.745404 INFO: [NOCDAPC] D0_APC_0: 0x0
9970 00:25:10.745483 INFO: [NOCDAPC] D0_APC_1: 0x0
9971 00:25:10.748515 INFO: [NOCDAPC] D1_APC_0: 0x0
9972 00:25:10.751912 INFO: [NOCDAPC] D1_APC_1: 0xfff
9973 00:25:10.755211 INFO: [NOCDAPC] D2_APC_0: 0x0
9974 00:25:10.758299 INFO: [NOCDAPC] D2_APC_1: 0xfff
9975 00:25:10.761708 INFO: [NOCDAPC] D3_APC_0: 0x0
9976 00:25:10.765125 INFO: [NOCDAPC] D3_APC_1: 0xfff
9977 00:25:10.768483 INFO: [NOCDAPC] D4_APC_0: 0x0
9978 00:25:10.772378 INFO: [NOCDAPC] D4_APC_1: 0xfff
9979 00:25:10.772457 INFO: [NOCDAPC] D5_APC_0: 0x0
9980 00:25:10.775399 INFO: [NOCDAPC] D5_APC_1: 0xfff
9981 00:25:10.778557 INFO: [NOCDAPC] D6_APC_0: 0x0
9982 00:25:10.782376 INFO: [NOCDAPC] D6_APC_1: 0xfff
9983 00:25:10.785349 INFO: [NOCDAPC] D7_APC_0: 0x0
9984 00:25:10.788828 INFO: [NOCDAPC] D7_APC_1: 0xfff
9985 00:25:10.792003 INFO: [NOCDAPC] D8_APC_0: 0x0
9986 00:25:10.795322 INFO: [NOCDAPC] D8_APC_1: 0xfff
9987 00:25:10.798569 INFO: [NOCDAPC] D9_APC_0: 0x0
9988 00:25:10.801714 INFO: [NOCDAPC] D9_APC_1: 0xfff
9989 00:25:10.805316 INFO: [NOCDAPC] D10_APC_0: 0x0
9990 00:25:10.808432 INFO: [NOCDAPC] D10_APC_1: 0xfff
9991 00:25:10.808511 INFO: [NOCDAPC] D11_APC_0: 0x0
9992 00:25:10.811947 INFO: [NOCDAPC] D11_APC_1: 0xfff
9993 00:25:10.815102 INFO: [NOCDAPC] D12_APC_0: 0x0
9994 00:25:10.818771 INFO: [NOCDAPC] D12_APC_1: 0xfff
9995 00:25:10.821839 INFO: [NOCDAPC] D13_APC_0: 0x0
9996 00:25:10.825609 INFO: [NOCDAPC] D13_APC_1: 0xfff
9997 00:25:10.828930 INFO: [NOCDAPC] D14_APC_0: 0x0
9998 00:25:10.832380 INFO: [NOCDAPC] D14_APC_1: 0xfff
9999 00:25:10.835470 INFO: [NOCDAPC] D15_APC_0: 0x0
10000 00:25:10.838886 INFO: [NOCDAPC] D15_APC_1: 0xfff
10001 00:25:10.842239 INFO: [NOCDAPC] APC_CON: 0x4
10002 00:25:10.845836 INFO: [APUAPC] set_apusys_apc done
10003 00:25:10.848879 INFO: [DEVAPC] devapc_init done
10004 00:25:10.852202 INFO: GICv3 without legacy support detected.
10005 00:25:10.855531 INFO: ARM GICv3 driver initialized in EL3
10006 00:25:10.859054 INFO: Maximum SPI INTID supported: 639
10007 00:25:10.862382 INFO: BL31: Initializing runtime services
10008 00:25:10.868789 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10009 00:25:10.872382 INFO: SPM: enable CPC mode
10010 00:25:10.875667 INFO: mcdi ready for mcusys-off-idle and system suspend
10011 00:25:10.882230 INFO: BL31: Preparing for EL3 exit to normal world
10012 00:25:10.885292 INFO: Entry point address = 0x80000000
10013 00:25:10.888619 INFO: SPSR = 0x8
10014 00:25:10.892998
10015 00:25:10.893071
10016 00:25:10.893132
10017 00:25:10.896133 Starting depthcharge on Spherion...
10018 00:25:10.896211
10019 00:25:10.896271 Wipe memory regions:
10020 00:25:10.896328
10021 00:25:10.896989 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10022 00:25:10.897081 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10023 00:25:10.897157 Setting prompt string to ['asurada:']
10024 00:25:10.897227 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10025 00:25:10.900043 [0x00000040000000, 0x00000054600000)
10026 00:25:11.021812
10027 00:25:11.021923 [0x00000054660000, 0x00000080000000)
10028 00:25:11.282540
10029 00:25:11.283000 [0x000000821a7280, 0x000000ffe64000)
10030 00:25:12.027964
10031 00:25:12.028428 [0x00000100000000, 0x00000240000000)
10032 00:25:13.917016
10033 00:25:13.920756 Initializing XHCI USB controller at 0x11200000.
10034 00:25:14.958649
10035 00:25:14.961806 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10036 00:25:14.962226
10037 00:25:14.962553
10038 00:25:14.963016
10039 00:25:14.963761 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10041 00:25:15.064801 asurada: tftpboot 192.168.201.1 11280945/tftp-deploy-adx72mtx/kernel/image.itb 11280945/tftp-deploy-adx72mtx/kernel/cmdline
10042 00:25:15.065310 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10043 00:25:15.065715 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10044 00:25:15.069897 tftpboot 192.168.201.1 11280945/tftp-deploy-adx72mtx/kernel/image.ittp-deploy-adx72mtx/kernel/cmdline
10045 00:25:15.070314
10046 00:25:15.070637 Waiting for link
10047 00:25:15.230500
10048 00:25:15.230953 R8152: Initializing
10049 00:25:15.231355
10050 00:25:15.234241 Version 6 (ocp_data = 5c30)
10051 00:25:15.234646
10052 00:25:15.237019 R8152: Done initializing
10053 00:25:15.237424
10054 00:25:15.237744 Adding net device
10055 00:25:17.388803
10056 00:25:17.389262 done.
10057 00:25:17.389589
10058 00:25:17.390050 MAC: 00:24:32:30:78:52
10059 00:25:17.390461
10060 00:25:17.391966 Sending DHCP discover... done.
10061 00:25:17.392370
10062 00:25:17.395649 Waiting for reply... done.
10063 00:25:17.396051
10064 00:25:17.398967 Sending DHCP request... done.
10065 00:25:17.399373
10066 00:25:17.403692 Waiting for reply... done.
10067 00:25:17.404095
10068 00:25:17.404411 My ip is 192.168.201.14
10069 00:25:17.404759
10070 00:25:17.407257 The DHCP server ip is 192.168.201.1
10071 00:25:17.407662
10072 00:25:17.414292 TFTP server IP predefined by user: 192.168.201.1
10073 00:25:17.414702
10074 00:25:17.420483 Bootfile predefined by user: 11280945/tftp-deploy-adx72mtx/kernel/image.itb
10075 00:25:17.420948
10076 00:25:17.421277 Sending tftp read request... done.
10077 00:25:17.421579
10078 00:25:17.430024 Waiting for the transfer...
10079 00:25:17.430431
10080 00:25:18.043854 00000000 ################################################################
10081 00:25:18.043997
10082 00:25:18.615960 00080000 ################################################################
10083 00:25:18.616105
10084 00:25:19.177931 00100000 ################################################################
10085 00:25:19.178072
10086 00:25:19.752227 00180000 ################################################################
10087 00:25:19.752382
10088 00:25:20.327275 00200000 ################################################################
10089 00:25:20.327431
10090 00:25:20.901355 00280000 ################################################################
10091 00:25:20.901495
10092 00:25:21.471531 00300000 ################################################################
10093 00:25:21.471669
10094 00:25:22.038156 00380000 ################################################################
10095 00:25:22.038295
10096 00:25:22.608702 00400000 ################################################################
10097 00:25:22.608855
10098 00:25:23.163875 00480000 ################################################################
10099 00:25:23.164003
10100 00:25:23.726131 00500000 ################################################################
10101 00:25:23.726287
10102 00:25:24.283863 00580000 ################################################################
10103 00:25:24.284002
10104 00:25:24.845091 00600000 ################################################################
10105 00:25:24.845221
10106 00:25:25.400925 00680000 ################################################################
10107 00:25:25.401057
10108 00:25:25.979717 00700000 ################################################################
10109 00:25:25.979848
10110 00:25:26.557368 00780000 ################################################################
10111 00:25:26.557495
10112 00:25:27.129573 00800000 ################################################################
10113 00:25:27.129737
10114 00:25:27.709121 00880000 ################################################################
10115 00:25:27.709243
10116 00:25:28.274373 00900000 ################################################################
10117 00:25:28.274500
10118 00:25:28.876204 00980000 ################################################################
10119 00:25:28.876337
10120 00:25:29.441033 00a00000 ################################################################
10121 00:25:29.441166
10122 00:25:30.074834 00a80000 ################################################################
10123 00:25:30.074959
10124 00:25:30.648538 00b00000 ################################################################
10125 00:25:30.648706
10126 00:25:31.219472 00b80000 ################################################################
10127 00:25:31.219627
10128 00:25:31.790441 00c00000 ################################################################
10129 00:25:31.790587
10130 00:25:32.365905 00c80000 ################################################################
10131 00:25:32.366035
10132 00:25:32.931654 00d00000 ################################################################
10133 00:25:32.931797
10134 00:25:33.498913 00d80000 ################################################################
10135 00:25:33.499042
10136 00:25:34.065947 00e00000 ################################################################
10137 00:25:34.066096
10138 00:25:34.627710 00e80000 ################################################################
10139 00:25:34.627892
10140 00:25:35.185999 00f00000 ################################################################
10141 00:25:35.186132
10142 00:25:35.754535 00f80000 ################################################################
10143 00:25:35.755039
10144 00:25:36.319324 01000000 ################################################################
10145 00:25:36.319449
10146 00:25:36.877402 01080000 ################################################################
10147 00:25:36.877568
10148 00:25:37.440852 01100000 ################################################################
10149 00:25:37.440984
10150 00:25:38.011014 01180000 ################################################################
10151 00:25:38.011189
10152 00:25:38.580953 01200000 ################################################################
10153 00:25:38.581090
10154 00:25:39.184352 01280000 ################################################################
10155 00:25:39.184538
10156 00:25:39.868580 01300000 ################################################################
10157 00:25:39.869200
10158 00:25:40.551871 01380000 ################################################################
10159 00:25:40.552014
10160 00:25:41.191933 01400000 ################################################################
10161 00:25:41.192513
10162 00:25:41.875908 01480000 ################################################################
10163 00:25:41.876445
10164 00:25:42.562324 01500000 ################################################################
10165 00:25:42.562825
10166 00:25:43.259421 01580000 ################################################################
10167 00:25:43.259937
10168 00:25:43.952330 01600000 ################################################################
10169 00:25:43.952903
10170 00:25:44.582689 01680000 ################################################################
10171 00:25:44.582833
10172 00:25:45.142356 01700000 ################################################################
10173 00:25:45.142497
10174 00:25:45.757656 01780000 ################################################################
10175 00:25:45.758244
10176 00:25:46.442428 01800000 ################################################################
10177 00:25:46.442942
10178 00:25:47.178898 01880000 ################################################################
10179 00:25:47.179390
10180 00:25:47.825195 01900000 ################################################################
10181 00:25:47.825339
10182 00:25:48.391569 01980000 ################################################################
10183 00:25:48.391700
10184 00:25:48.999598 01a00000 ################################################################
10185 00:25:49.000130
10186 00:25:49.686428 01a80000 ################################################################
10187 00:25:49.686923
10188 00:25:50.357509 01b00000 ################################################################
10189 00:25:50.357648
10190 00:25:50.995297 01b80000 ################################################################
10191 00:25:50.995830
10192 00:25:51.560168 01c00000 ################################################################
10193 00:25:51.560323
10194 00:25:52.138183 01c80000 ################################################################
10195 00:25:52.138334
10196 00:25:52.750844 01d00000 ################################################################
10197 00:25:52.751347
10198 00:25:53.356519 01d80000 ################################################################
10199 00:25:53.357111
10200 00:25:53.959863 01e00000 ################################################################
10201 00:25:53.960359
10202 00:25:54.617100 01e80000 ################################################################
10203 00:25:54.617256
10204 00:25:55.275233 01f00000 ################################################################
10205 00:25:55.275733
10206 00:25:55.939878 01f80000 ################################################################
10207 00:25:55.940370
10208 00:25:56.634249 02000000 ################################################################
10209 00:25:56.634781
10210 00:25:57.344065 02080000 ################################################################
10211 00:25:57.344584
10212 00:25:58.038912 02100000 ################################################################
10213 00:25:58.039410
10214 00:25:58.719392 02180000 ################################################################
10215 00:25:58.719900
10216 00:25:59.399308 02200000 ################################################################
10217 00:25:59.399812
10218 00:26:00.097172 02280000 ################################################################
10219 00:26:00.097674
10220 00:26:00.779759 02300000 ################################################################
10221 00:26:00.780274
10222 00:26:01.470526 02380000 ################################################################
10223 00:26:01.471078
10224 00:26:02.170011 02400000 ################################################################
10225 00:26:02.170541
10226 00:26:02.872237 02480000 ################################################################
10227 00:26:02.872804
10228 00:26:03.535598 02500000 ################################################################
10229 00:26:03.535741
10230 00:26:04.236463 02580000 ################################################################
10231 00:26:04.237090
10232 00:26:04.935195 02600000 ################################################################
10233 00:26:04.935755
10234 00:26:05.625980 02680000 ################################################################
10235 00:26:05.626498
10236 00:26:06.281484 02700000 ################################################################
10237 00:26:06.281628
10238 00:26:06.957169 02780000 ################################################################
10239 00:26:06.957669
10240 00:26:07.638037 02800000 ################################################################
10241 00:26:07.638563
10242 00:26:08.335108 02880000 ################################################################
10243 00:26:08.335706
10244 00:26:09.010229 02900000 ################################################################
10245 00:26:09.010743
10246 00:26:09.682272 02980000 ################################################################
10247 00:26:09.682776
10248 00:26:10.381896 02a00000 ################################################################
10249 00:26:10.382384
10250 00:26:10.987012 02a80000 ################################################################
10251 00:26:10.987556
10252 00:26:11.656949 02b00000 ################################################################
10253 00:26:11.657474
10254 00:26:12.231682 02b80000 ################################################################
10255 00:26:12.231814
10256 00:26:12.813677 02c00000 ################################################################
10257 00:26:12.813811
10258 00:26:13.454176 02c80000 ################################################################
10259 00:26:13.454682
10260 00:26:14.046007 02d00000 ################################################################
10261 00:26:14.046153
10262 00:26:14.570592 02d80000 ################################################################
10263 00:26:14.570741
10264 00:26:15.100652 02e00000 ################################################################
10265 00:26:15.100835
10266 00:26:15.667206 02e80000 ################################################################
10267 00:26:15.667359
10268 00:26:16.231270 02f00000 ################################################################
10269 00:26:16.231419
10270 00:26:16.797932 02f80000 ################################################################
10271 00:26:16.798081
10272 00:26:17.348419 03000000 ################################################################
10273 00:26:17.348565
10274 00:26:17.906488 03080000 ################################################################
10275 00:26:17.906631
10276 00:26:18.458650 03100000 ################################################################
10277 00:26:18.458817
10278 00:26:19.014083 03180000 ################################################################
10279 00:26:19.014223
10280 00:26:19.557084 03200000 ################################################################
10281 00:26:19.557230
10282 00:26:20.089775 03280000 ################################################################
10283 00:26:20.089921
10284 00:26:20.635747 03300000 ################################################################
10285 00:26:20.635894
10286 00:26:21.169602 03380000 ################################################################
10287 00:26:21.169747
10288 00:26:21.716645 03400000 ################################################################
10289 00:26:21.716793
10290 00:26:22.263554 03480000 ################################################################
10291 00:26:22.263723
10292 00:26:22.796097 03500000 ################################################################
10293 00:26:22.796239
10294 00:26:23.321000 03580000 ################################################################
10295 00:26:23.321143
10296 00:26:23.844598 03600000 ################################################################
10297 00:26:23.844795
10298 00:26:24.368622 03680000 ################################################################
10299 00:26:24.368789
10300 00:26:24.897920 03700000 ################################################################
10301 00:26:24.898077
10302 00:26:25.425813 03780000 ################################################################
10303 00:26:25.425956
10304 00:26:25.954408 03800000 ################################################################
10305 00:26:25.954556
10306 00:26:26.482660 03880000 ################################################################
10307 00:26:26.482801
10308 00:26:27.010494 03900000 ################################################################
10309 00:26:27.010638
10310 00:26:27.538560 03980000 ################################################################
10311 00:26:27.538699
10312 00:26:28.068507 03a00000 ################################################################
10313 00:26:28.068683
10314 00:26:28.632962 03a80000 ################################################################
10315 00:26:28.633110
10316 00:26:29.200009 03b00000 ################################################################
10317 00:26:29.200155
10318 00:26:29.765241 03b80000 ################################################################
10319 00:26:29.765392
10320 00:26:30.325810 03c00000 ################################################################
10321 00:26:30.325961
10322 00:26:30.889052 03c80000 ################################################################
10323 00:26:30.889202
10324 00:26:31.464615 03d00000 ################################################################
10325 00:26:31.464809
10326 00:26:32.031965 03d80000 ################################################################
10327 00:26:32.032115
10328 00:26:32.593195 03e00000 ################################################################
10329 00:26:32.593345
10330 00:26:33.173198 03e80000 ################################################################
10331 00:26:33.173348
10332 00:26:33.749220 03f00000 ################################################################
10333 00:26:33.749371
10334 00:26:34.324839 03f80000 ################################################################
10335 00:26:34.324994
10336 00:26:34.895356 04000000 ################################################################
10337 00:26:34.895498
10338 00:26:35.460576 04080000 ################################################################
10339 00:26:35.460776
10340 00:26:36.023874 04100000 ################################################################
10341 00:26:36.024024
10342 00:26:36.584060 04180000 ################################################################
10343 00:26:36.584203
10344 00:26:37.145033 04200000 ################################################################
10345 00:26:37.145184
10346 00:26:37.713084 04280000 ################################################################
10347 00:26:37.713231
10348 00:26:38.283856 04300000 ################################################################
10349 00:26:38.284000
10350 00:26:38.851409 04380000 ################################################################
10351 00:26:38.851558
10352 00:26:39.422917 04400000 ################################################################
10353 00:26:39.423058
10354 00:26:39.988023 04480000 ################################################################
10355 00:26:39.988170
10356 00:26:40.568084 04500000 ################################################################
10357 00:26:40.568236
10358 00:26:41.134634 04580000 ################################################################
10359 00:26:41.134782
10360 00:26:41.705822 04600000 ################################################################
10361 00:26:41.705994
10362 00:26:42.354699 04680000 ################################################################
10363 00:26:42.355159
10364 00:26:43.050173 04700000 ################################################################
10365 00:26:43.050677
10366 00:26:43.736642 04780000 ################################################################
10367 00:26:43.737176
10368 00:26:44.427771 04800000 ################################################################
10369 00:26:44.428449
10370 00:26:45.119212 04880000 ################################################################
10371 00:26:45.119719
10372 00:26:45.815460 04900000 ################################################################
10373 00:26:45.815967
10374 00:26:46.502612 04980000 ################################################################
10375 00:26:46.503145
10376 00:26:47.092346 04a00000 ################################################################
10377 00:26:47.092491
10378 00:26:47.772986 04a80000 ################################################################
10379 00:26:47.773481
10380 00:26:48.464638 04b00000 ################################################################
10381 00:26:48.465172
10382 00:26:49.084203 04b80000 ################################################################
10383 00:26:49.084336
10384 00:26:49.726426 04c00000 ################################################################
10385 00:26:49.726906
10386 00:26:50.321023 04c80000 ################################################################
10387 00:26:50.321161
10388 00:26:50.887950 04d00000 ################################################################
10389 00:26:50.888080
10390 00:26:51.463241 04d80000 ################################################################
10391 00:26:51.463382
10392 00:26:51.986537 04e00000 ################################################################
10393 00:26:51.986675
10394 00:26:52.518285 04e80000 ################################################################
10395 00:26:52.518449
10396 00:26:53.040127 04f00000 ################################################################
10397 00:26:53.040289
10398 00:26:53.566085 04f80000 ################################################################
10399 00:26:53.566219
10400 00:26:54.089625 05000000 ################################################################
10401 00:26:54.089757
10402 00:26:54.611326 05080000 ################################################################
10403 00:26:54.611494
10404 00:26:55.134332 05100000 ################################################################
10405 00:26:55.134492
10406 00:26:55.658589 05180000 ################################################################
10407 00:26:55.658755
10408 00:26:56.190189 05200000 ################################################################
10409 00:26:56.190347
10410 00:26:56.713745 05280000 ################################################################
10411 00:26:56.713876
10412 00:26:57.237434 05300000 ################################################################
10413 00:26:57.237564
10414 00:26:57.758864 05380000 ################################################################
10415 00:26:57.759018
10416 00:26:58.279644 05400000 ################################################################
10417 00:26:58.279799
10418 00:26:58.807892 05480000 ################################################################
10419 00:26:58.808026
10420 00:26:59.334119 05500000 ################################################################
10421 00:26:59.334302
10422 00:26:59.868660 05580000 ################################################################
10423 00:26:59.868828
10424 00:27:00.391976 05600000 ################################################################
10425 00:27:00.392133
10426 00:27:00.917243 05680000 ################################################################
10427 00:27:00.917397
10428 00:27:01.439022 05700000 ################################################################
10429 00:27:01.439177
10430 00:27:01.961968 05780000 ################################################################
10431 00:27:01.962094
10432 00:27:02.483342 05800000 ################################################################
10433 00:27:02.483471
10434 00:27:03.004606 05880000 ################################################################
10435 00:27:03.004738
10436 00:27:03.530044 05900000 ################################################################
10437 00:27:03.530178
10438 00:27:04.051095 05980000 ################################################################
10439 00:27:04.051229
10440 00:27:04.572670 05a00000 ################################################################
10441 00:27:04.572819
10442 00:27:05.095327 05a80000 ################################################################
10443 00:27:05.095468
10444 00:27:05.619115 05b00000 ################################################################
10445 00:27:05.619263
10446 00:27:06.142067 05b80000 ################################################################
10447 00:27:06.142227
10448 00:27:06.662212 05c00000 ################################################################
10449 00:27:06.662361
10450 00:27:07.183278 05c80000 ################################################################
10451 00:27:07.183420
10452 00:27:07.705103 05d00000 ################################################################
10453 00:27:07.705249
10454 00:27:08.226964 05d80000 ################################################################
10455 00:27:08.227117
10456 00:27:08.747208 05e00000 ################################################################
10457 00:27:08.747349
10458 00:27:09.271673 05e80000 ################################################################
10459 00:27:09.271816
10460 00:27:09.794008 05f00000 ################################################################
10461 00:27:09.794149
10462 00:27:10.316824 05f80000 ################################################################
10463 00:27:10.316980
10464 00:27:10.845619 06000000 ################################################################
10465 00:27:10.845777
10466 00:27:11.368024 06080000 ################################################################
10467 00:27:11.368170
10468 00:27:11.902891 06100000 ################################################################
10469 00:27:11.903029
10470 00:27:12.431125 06180000 ################################################################
10471 00:27:12.431274
10472 00:27:12.952663 06200000 ################################################################
10473 00:27:12.952841
10474 00:27:13.481843 06280000 ################################################################
10475 00:27:13.481981
10476 00:27:14.002788 06300000 ################################################################
10477 00:27:14.002933
10478 00:27:14.523909 06380000 ################################################################
10479 00:27:14.524051
10480 00:27:15.045136 06400000 ################################################################
10481 00:27:15.045281
10482 00:27:15.566398 06480000 ################################################################
10483 00:27:15.566543
10484 00:27:16.087112 06500000 ################################################################
10485 00:27:16.087262
10486 00:27:16.607984 06580000 ################################################################
10487 00:27:16.608126
10488 00:27:17.128644 06600000 ################################################################
10489 00:27:17.128797
10490 00:27:17.650876 06680000 ################################################################
10491 00:27:17.651024
10492 00:27:18.175439 06700000 ################################################################
10493 00:27:18.175583
10494 00:27:18.696191 06780000 ################################################################
10495 00:27:18.696359
10496 00:27:18.937578 06800000 ############################## done.
10497 00:27:18.937720
10498 00:27:18.940689 The bootfile was 109295066 bytes long.
10499 00:27:18.940786
10500 00:27:18.944263 Sending tftp read request... done.
10501 00:27:18.944343
10502 00:27:18.944406 Waiting for the transfer...
10503 00:27:18.944466
10504 00:27:18.947619 00000000 # done.
10505 00:27:18.947701
10506 00:27:18.954069 Command line loaded dynamically from TFTP file: 11280945/tftp-deploy-adx72mtx/kernel/cmdline
10507 00:27:18.954165
10508 00:27:18.967533 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10509 00:27:18.967615
10510 00:27:18.971059 Loading FIT.
10511 00:27:18.971131
10512 00:27:18.974515 Image ramdisk-1 has 98208438 bytes.
10513 00:27:18.974593
10514 00:27:18.974655 Image fdt-1 has 47278 bytes.
10515 00:27:18.974713
10516 00:27:18.977343 Image kernel-1 has 11037315 bytes.
10517 00:27:18.977421
10518 00:27:18.987493 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10519 00:27:18.987572
10520 00:27:19.004726 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10521 00:27:19.004813
10522 00:27:19.010895 Choosing best match conf-1 for compat google,spherion-rev2.
10523 00:27:19.015115
10524 00:27:19.019578 Connected to device vid:did:rid of 1ae0:0028:00
10525 00:27:19.027451
10526 00:27:19.031122 tpm_get_response: command 0x17b, return code 0x0
10527 00:27:19.031201
10528 00:27:19.034344 ec_init: CrosEC protocol v3 supported (256, 248)
10529 00:27:19.038039
10530 00:27:19.041859 tpm_cleanup: add release locality here.
10531 00:27:19.041939
10532 00:27:19.042001 Shutting down all USB controllers.
10533 00:27:19.045128
10534 00:27:19.045206 Removing current net device
10535 00:27:19.045267
10536 00:27:19.051807 Exiting depthcharge with code 4 at timestamp: 157472258
10537 00:27:19.051886
10538 00:27:19.055029 LZMA decompressing kernel-1 to 0x821a6718
10539 00:27:19.055108
10540 00:27:19.058262 LZMA decompressing kernel-1 to 0x40000000
10541 00:27:20.446611
10542 00:27:20.446751 jumping to kernel
10543 00:27:20.447223 end: 2.2.4 bootloader-commands (duration 00:02:10) [common]
10544 00:27:20.447319 start: 2.2.5 auto-login-action (timeout 00:02:16) [common]
10545 00:27:20.447393 Setting prompt string to ['Linux version [0-9]']
10546 00:27:20.447460 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10547 00:27:20.447526 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10548 00:27:20.528383
10549 00:27:20.531620 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10550 00:27:20.534994 start: 2.2.5.1 login-action (timeout 00:02:16) [common]
10551 00:27:20.535084 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10552 00:27:20.535171 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10553 00:27:20.535249 Using line separator: #'\n'#
10554 00:27:20.535308 No login prompt set.
10555 00:27:20.535370 Parsing kernel messages
10556 00:27:20.535424 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10557 00:27:20.535523 [login-action] Waiting for messages, (timeout 00:02:16)
10558 00:27:20.554847 [ 0.000000] Linux version 6.1.45-cip3 (KernelCI@build-j12530-arm64-gcc-10-defconfig-arm64-chromebook-5rwxg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Aug 14 00:09:07 UTC 2023
10559 00:27:20.557835 [ 0.000000] random: crng init done
10560 00:27:20.561404 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10561 00:27:20.564867 [ 0.000000] efi: UEFI not found.
10562 00:27:20.574626 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10563 00:27:20.581610 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10564 00:27:20.591853 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10565 00:27:20.601534 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10566 00:27:20.608325 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10567 00:27:20.611365 [ 0.000000] printk: bootconsole [mtk8250] enabled
10568 00:27:20.619744 [ 0.000000] NUMA: No NUMA configuration found
10569 00:27:20.626336 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10570 00:27:20.632975 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10571 00:27:20.633055 [ 0.000000] Zone ranges:
10572 00:27:20.640029 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10573 00:27:20.643376 [ 0.000000] DMA32 empty
10574 00:27:20.650641 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10575 00:27:20.653867 [ 0.000000] Movable zone start for each node
10576 00:27:20.656599 [ 0.000000] Early memory node ranges
10577 00:27:20.663256 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10578 00:27:20.670354 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10579 00:27:20.676847 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10580 00:27:20.683512 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10581 00:27:20.686867 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10582 00:27:20.697110 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10583 00:27:20.752254 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10584 00:27:20.759034 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10585 00:27:20.765221 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10586 00:27:20.768824 [ 0.000000] psci: probing for conduit method from DT.
10587 00:27:20.775665 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10588 00:27:20.778812 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10589 00:27:20.785440 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10590 00:27:20.789034 [ 0.000000] psci: SMC Calling Convention v1.2
10591 00:27:20.795250 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10592 00:27:20.798939 [ 0.000000] Detected VIPT I-cache on CPU0
10593 00:27:20.805329 [ 0.000000] CPU features: detected: GIC system register CPU interface
10594 00:27:20.812223 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10595 00:27:20.818981 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10596 00:27:20.825654 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10597 00:27:20.832476 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10598 00:27:20.839340 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10599 00:27:20.845451 [ 0.000000] alternatives: applying boot alternatives
10600 00:27:20.848895 [ 0.000000] Fallback order for Node 0: 0
10601 00:27:20.855507 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10602 00:27:20.858801 [ 0.000000] Policy zone: Normal
10603 00:27:20.875749 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10604 00:27:20.885290 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10605 00:27:20.895684 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10606 00:27:20.905651 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10607 00:27:20.912236 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10608 00:27:20.915583 <6>[ 0.000000] software IO TLB: area num 8.
10609 00:27:20.972056 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10610 00:27:21.121560 <6>[ 0.000000] Memory: 7873648K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 479120K reserved, 32768K cma-reserved)
10611 00:27:21.127985 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10612 00:27:21.134616 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10613 00:27:21.137983 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10614 00:27:21.144242 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10615 00:27:21.150968 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10616 00:27:21.154435 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10617 00:27:21.164209 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10618 00:27:21.170608 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10619 00:27:21.177891 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10620 00:27:21.184104 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10621 00:27:21.187433 <6>[ 0.000000] GICv3: 608 SPIs implemented
10622 00:27:21.190783 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10623 00:27:21.197354 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10624 00:27:21.201083 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10625 00:27:21.207602 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10626 00:27:21.220479 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10627 00:27:21.230715 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10628 00:27:21.237379 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10629 00:27:21.247835 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10630 00:27:21.260604 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10631 00:27:21.267375 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10632 00:27:21.273993 <6>[ 0.009186] Console: colour dummy device 80x25
10633 00:27:21.284312 <6>[ 0.013915] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10634 00:27:21.287555 <6>[ 0.024358] pid_max: default: 32768 minimum: 301
10635 00:27:21.294256 <6>[ 0.029229] LSM: Security Framework initializing
10636 00:27:21.301435 <6>[ 0.034167] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10637 00:27:21.310825 <6>[ 0.041979] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10638 00:27:21.317671 <6>[ 0.051414] cblist_init_generic: Setting adjustable number of callback queues.
10639 00:27:21.324506 <6>[ 0.058859] cblist_init_generic: Setting shift to 3 and lim to 1.
10640 00:27:21.330767 <6>[ 0.065199] cblist_init_generic: Setting adjustable number of callback queues.
10641 00:27:21.337614 <6>[ 0.072670] cblist_init_generic: Setting shift to 3 and lim to 1.
10642 00:27:21.344131 <6>[ 0.079068] rcu: Hierarchical SRCU implementation.
10643 00:27:21.351027 <6>[ 0.084081] rcu: Max phase no-delay instances is 1000.
10644 00:27:21.354884 <6>[ 0.091111] EFI services will not be available.
10645 00:27:21.361679 <6>[ 0.096082] smp: Bringing up secondary CPUs ...
10646 00:27:21.368503 <6>[ 0.101134] Detected VIPT I-cache on CPU1
10647 00:27:21.375054 <6>[ 0.101205] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10648 00:27:21.381752 <6>[ 0.101235] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10649 00:27:21.385127 <6>[ 0.101567] Detected VIPT I-cache on CPU2
10650 00:27:21.391631 <6>[ 0.101617] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10651 00:27:21.398285 <6>[ 0.101633] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10652 00:27:21.405119 <6>[ 0.101890] Detected VIPT I-cache on CPU3
10653 00:27:21.411459 <6>[ 0.101937] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10654 00:27:21.418047 <6>[ 0.101950] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10655 00:27:21.421664 <6>[ 0.102255] CPU features: detected: Spectre-v4
10656 00:27:21.428208 <6>[ 0.102260] CPU features: detected: Spectre-BHB
10657 00:27:21.431508 <6>[ 0.102265] Detected PIPT I-cache on CPU4
10658 00:27:21.438384 <6>[ 0.102323] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10659 00:27:21.444841 <6>[ 0.102341] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10660 00:27:21.451922 <6>[ 0.102633] Detected PIPT I-cache on CPU5
10661 00:27:21.458275 <6>[ 0.102697] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10662 00:27:21.464844 <6>[ 0.102714] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10663 00:27:21.468211 <6>[ 0.102999] Detected PIPT I-cache on CPU6
10664 00:27:21.474728 <6>[ 0.103067] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10665 00:27:21.481478 <6>[ 0.103084] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10666 00:27:21.485028 <6>[ 0.103383] Detected PIPT I-cache on CPU7
10667 00:27:21.495471 <6>[ 0.103449] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10668 00:27:21.502163 <6>[ 0.103466] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10669 00:27:21.505246 <6>[ 0.103513] smp: Brought up 1 node, 8 CPUs
10670 00:27:21.508177 <6>[ 0.244908] SMP: Total of 8 processors activated.
10671 00:27:21.515331 <6>[ 0.249860] CPU features: detected: 32-bit EL0 Support
10672 00:27:21.525271 <6>[ 0.255256] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10673 00:27:21.531832 <6>[ 0.264111] CPU features: detected: Common not Private translations
10674 00:27:21.534889 <6>[ 0.270627] CPU features: detected: CRC32 instructions
10675 00:27:21.541470 <6>[ 0.276012] CPU features: detected: RCpc load-acquire (LDAPR)
10676 00:27:21.548102 <6>[ 0.281971] CPU features: detected: LSE atomic instructions
10677 00:27:21.554909 <6>[ 0.287789] CPU features: detected: Privileged Access Never
10678 00:27:21.558270 <6>[ 0.293569] CPU features: detected: RAS Extension Support
10679 00:27:21.564884 <6>[ 0.299212] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10680 00:27:21.571632 <6>[ 0.306433] CPU: All CPU(s) started at EL2
10681 00:27:21.574663 <6>[ 0.310750] alternatives: applying system-wide alternatives
10682 00:27:21.586318 <6>[ 0.321468] devtmpfs: initialized
10683 00:27:21.598299 <6>[ 0.330317] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10684 00:27:21.608824 <6>[ 0.340280] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10685 00:27:21.615393 <6>[ 0.348290] pinctrl core: initialized pinctrl subsystem
10686 00:27:21.619157 <6>[ 0.355092] DMI not present or invalid.
10687 00:27:21.625552 <6>[ 0.359497] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10688 00:27:21.631737 <6>[ 0.366355] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10689 00:27:21.642589 <6>[ 0.373935] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10690 00:27:21.648760 <6>[ 0.382144] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10691 00:27:21.655970 <6>[ 0.390390] audit: initializing netlink subsys (disabled)
10692 00:27:21.662067 <5>[ 0.396085] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10693 00:27:21.669249 <6>[ 0.396807] thermal_sys: Registered thermal governor 'step_wise'
10694 00:27:21.675814 <6>[ 0.404054] thermal_sys: Registered thermal governor 'power_allocator'
10695 00:27:21.682368 <6>[ 0.410311] cpuidle: using governor menu
10696 00:27:21.686110 <6>[ 0.421270] NET: Registered PF_QIPCRTR protocol family
10697 00:27:21.692326 <6>[ 0.426754] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10698 00:27:21.698929 <6>[ 0.433860] ASID allocator initialised with 32768 entries
10699 00:27:21.705349 <6>[ 0.440473] Serial: AMBA PL011 UART driver
10700 00:27:21.714499 <4>[ 0.449629] Trying to register duplicate clock ID: 134
10701 00:27:21.770988 <6>[ 0.509557] KASLR enabled
10702 00:27:21.785395 <6>[ 0.517306] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10703 00:27:21.792358 <6>[ 0.524321] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10704 00:27:21.798809 <6>[ 0.530809] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10705 00:27:21.805587 <6>[ 0.537812] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10706 00:27:21.812410 <6>[ 0.544300] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10707 00:27:21.818804 <6>[ 0.551304] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10708 00:27:21.825063 <6>[ 0.557793] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10709 00:27:21.832146 <6>[ 0.564799] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10710 00:27:21.835131 <6>[ 0.572320] ACPI: Interpreter disabled.
10711 00:27:21.843653 <6>[ 0.578825] iommu: Default domain type: Translated
10712 00:27:21.850303 <6>[ 0.583937] iommu: DMA domain TLB invalidation policy: strict mode
10713 00:27:21.854081 <5>[ 0.590589] SCSI subsystem initialized
10714 00:27:21.860377 <6>[ 0.594752] usbcore: registered new interface driver usbfs
10715 00:27:21.867127 <6>[ 0.600488] usbcore: registered new interface driver hub
10716 00:27:21.870266 <6>[ 0.606041] usbcore: registered new device driver usb
10717 00:27:21.877212 <6>[ 0.612186] pps_core: LinuxPPS API ver. 1 registered
10718 00:27:21.886887 <6>[ 0.617380] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10719 00:27:21.890305 <6>[ 0.626728] PTP clock support registered
10720 00:27:21.893806 <6>[ 0.630975] EDAC MC: Ver: 3.0.0
10721 00:27:21.901028 <6>[ 0.636178] FPGA manager framework
10722 00:27:21.904777 <6>[ 0.639858] Advanced Linux Sound Architecture Driver Initialized.
10723 00:27:21.908207 <6>[ 0.646633] vgaarb: loaded
10724 00:27:21.914864 <6>[ 0.649813] clocksource: Switched to clocksource arch_sys_counter
10725 00:27:21.921779 <5>[ 0.656250] VFS: Disk quotas dquot_6.6.0
10726 00:27:21.928450 <6>[ 0.660432] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10727 00:27:21.931482 <6>[ 0.667623] pnp: PnP ACPI: disabled
10728 00:27:21.939634 <6>[ 0.674305] NET: Registered PF_INET protocol family
10729 00:27:21.948848 <6>[ 0.679892] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10730 00:27:21.960878 <6>[ 0.692197] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10731 00:27:21.970114 <6>[ 0.701012] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10732 00:27:21.977073 <6>[ 0.708983] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10733 00:27:21.983510 <6>[ 0.717682] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10734 00:27:21.995377 <6>[ 0.727431] TCP: Hash tables configured (established 65536 bind 65536)
10735 00:27:22.002355 <6>[ 0.734291] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10736 00:27:22.009566 <6>[ 0.741491] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10737 00:27:22.015797 <6>[ 0.749195] NET: Registered PF_UNIX/PF_LOCAL protocol family
10738 00:27:22.022055 <6>[ 0.755375] RPC: Registered named UNIX socket transport module.
10739 00:27:22.025513 <6>[ 0.761529] RPC: Registered udp transport module.
10740 00:27:22.031935 <6>[ 0.766464] RPC: Registered tcp transport module.
10741 00:27:22.038885 <6>[ 0.771396] RPC: Registered tcp NFSv4.1 backchannel transport module.
10742 00:27:22.042417 <6>[ 0.778063] PCI: CLS 0 bytes, default 64
10743 00:27:22.046007 <6>[ 0.782343] Unpacking initramfs...
10744 00:27:22.070466 <6>[ 0.801970] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10745 00:27:22.080079 <6>[ 0.810648] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10746 00:27:22.083558 <6>[ 0.819527] kvm [1]: IPA Size Limit: 40 bits
10747 00:27:22.090671 <6>[ 0.824053] kvm [1]: GICv3: no GICV resource entry
10748 00:27:22.093788 <6>[ 0.829074] kvm [1]: disabling GICv2 emulation
10749 00:27:22.099928 <6>[ 0.833765] kvm [1]: GIC system register CPU interface enabled
10750 00:27:22.103752 <6>[ 0.839953] kvm [1]: vgic interrupt IRQ18
10751 00:27:22.110308 <6>[ 0.844318] kvm [1]: VHE mode initialized successfully
10752 00:27:22.116629 <5>[ 0.850826] Initialise system trusted keyrings
10753 00:27:22.123940 <6>[ 0.855632] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10754 00:27:22.130686 <6>[ 0.865671] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10755 00:27:22.137041 <5>[ 0.872063] NFS: Registering the id_resolver key type
10756 00:27:22.140468 <5>[ 0.877364] Key type id_resolver registered
10757 00:27:22.147018 <5>[ 0.881781] Key type id_legacy registered
10758 00:27:22.153908 <6>[ 0.886061] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10759 00:27:22.160954 <6>[ 0.892985] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10760 00:27:22.166959 <6>[ 0.900705] 9p: Installing v9fs 9p2000 file system support
10761 00:27:22.203525 <5>[ 0.938533] Key type asymmetric registered
10762 00:27:22.206656 <5>[ 0.942865] Asymmetric key parser 'x509' registered
10763 00:27:22.217072 <6>[ 0.948010] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10764 00:27:22.220271 <6>[ 0.955628] io scheduler mq-deadline registered
10765 00:27:22.223369 <6>[ 0.960406] io scheduler kyber registered
10766 00:27:22.242949 <6>[ 0.978008] EINJ: ACPI disabled.
10767 00:27:22.276301 <4>[ 1.004587] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10768 00:27:22.286156 <4>[ 1.015215] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10769 00:27:22.301313 <6>[ 1.036342] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10770 00:27:22.309004 <6>[ 1.044351] printk: console [ttyS0] disabled
10771 00:27:22.337379 <6>[ 1.069002] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10772 00:27:22.344223 <6>[ 1.078479] printk: console [ttyS0] enabled
10773 00:27:22.347435 <6>[ 1.078479] printk: console [ttyS0] enabled
10774 00:27:22.353882 <6>[ 1.087375] printk: bootconsole [mtk8250] disabled
10775 00:27:22.357319 <6>[ 1.087375] printk: bootconsole [mtk8250] disabled
10776 00:27:22.363941 <6>[ 1.098666] SuperH (H)SCI(F) driver initialized
10777 00:27:22.366924 <6>[ 1.103965] msm_serial: driver initialized
10778 00:27:22.381227 <6>[ 1.113104] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10779 00:27:22.391576 <6>[ 1.121654] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10780 00:27:22.397642 <6>[ 1.130196] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10781 00:27:22.408146 <6>[ 1.138824] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10782 00:27:22.414763 <6>[ 1.147531] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10783 00:27:22.424141 <6>[ 1.156252] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10784 00:27:22.434302 <6>[ 1.164793] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10785 00:27:22.441138 <6>[ 1.173624] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10786 00:27:22.451077 <6>[ 1.182167] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10787 00:27:22.462671 <6>[ 1.197936] loop: module loaded
10788 00:27:22.469142 <6>[ 1.203905] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10789 00:27:22.492321 <4>[ 1.227230] mtk-pmic-keys: Failed to locate of_node [id: -1]
10790 00:27:22.499006 <6>[ 1.234054] megasas: 07.719.03.00-rc1
10791 00:27:22.509280 <6>[ 1.243687] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10792 00:27:22.518578 <6>[ 1.253199] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10793 00:27:22.534963 <6>[ 1.269964] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10794 00:27:22.591773 <6>[ 1.320342] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10795 00:27:26.065006 <6>[ 4.800877] Freeing initrd memory: 95904K
10796 00:27:26.075883 <6>[ 4.811330] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10797 00:27:26.086351 <6>[ 4.822121] tun: Universal TUN/TAP device driver, 1.6
10798 00:27:26.089977 <6>[ 4.828219] thunder_xcv, ver 1.0
10799 00:27:26.093138 <6>[ 4.831724] thunder_bgx, ver 1.0
10800 00:27:26.096627 <6>[ 4.835219] nicpf, ver 1.0
10801 00:27:26.107145 <6>[ 4.839281] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10802 00:27:26.110293 <6>[ 4.846758] hns3: Copyright (c) 2017 Huawei Corporation.
10803 00:27:26.113518 <6>[ 4.852344] hclge is initializing
10804 00:27:26.120415 <6>[ 4.855924] e1000: Intel(R) PRO/1000 Network Driver
10805 00:27:26.126767 <6>[ 4.861054] e1000: Copyright (c) 1999-2006 Intel Corporation.
10806 00:27:26.130467 <6>[ 4.867069] e1000e: Intel(R) PRO/1000 Network Driver
10807 00:27:26.136883 <6>[ 4.872285] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10808 00:27:26.143236 <6>[ 4.878472] igb: Intel(R) Gigabit Ethernet Network Driver
10809 00:27:26.150089 <6>[ 4.884122] igb: Copyright (c) 2007-2014 Intel Corporation.
10810 00:27:26.156594 <6>[ 4.889958] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10811 00:27:26.163873 <6>[ 4.896476] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10812 00:27:26.166611 <6>[ 4.902949] sky2: driver version 1.30
10813 00:27:26.172983 <6>[ 4.907998] VFIO - User Level meta-driver version: 0.3
10814 00:27:26.181042 <6>[ 4.916377] usbcore: registered new interface driver usb-storage
10815 00:27:26.187509 <6>[ 4.922825] usbcore: registered new device driver onboard-usb-hub
10816 00:27:26.196495 <6>[ 4.932035] mt6397-rtc mt6359-rtc: registered as rtc0
10817 00:27:26.206447 <6>[ 4.937519] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-14T00:27:29 UTC (1691972849)
10818 00:27:26.209701 <6>[ 4.947167] i2c_dev: i2c /dev entries driver
10819 00:27:26.227342 <6>[ 4.959176] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10820 00:27:26.247591 <6>[ 4.983190] cpu cpu0: EM: created perf domain
10821 00:27:26.250958 <6>[ 4.988231] cpu cpu4: EM: created perf domain
10822 00:27:26.258092 <6>[ 4.993834] sdhci: Secure Digital Host Controller Interface driver
10823 00:27:26.264825 <6>[ 5.000262] sdhci: Copyright(c) Pierre Ossman
10824 00:27:26.271739 <6>[ 5.005229] Synopsys Designware Multimedia Card Interface Driver
10825 00:27:26.278112 <6>[ 5.011877] sdhci-pltfm: SDHCI platform and OF driver helper
10826 00:27:26.281400 <6>[ 5.011910] mmc0: CQHCI version 5.10
10827 00:27:26.288675 <6>[ 5.021881] ledtrig-cpu: registered to indicate activity on CPUs
10828 00:27:26.294717 <6>[ 5.028845] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10829 00:27:26.301429 <6>[ 5.035917] usbcore: registered new interface driver usbhid
10830 00:27:26.304791 <6>[ 5.041739] usbhid: USB HID core driver
10831 00:27:26.311487 <6>[ 5.045947] spi_master spi0: will run message pump with realtime priority
10832 00:27:26.358775 <6>[ 5.087875] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10833 00:27:26.378311 <6>[ 5.103554] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10834 00:27:26.381987 <6>[ 5.117859] mmc0: Command Queue Engine enabled
10835 00:27:26.388560 <6>[ 5.118342] cros-ec-spi spi0.0: Chrome EC device registered
10836 00:27:26.395363 <6>[ 5.122586] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10837 00:27:26.398278 <6>[ 5.135626] mmcblk0: mmc0:0001 DA4128 116 GiB
10838 00:27:26.410022 <6>[ 5.142340] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10839 00:27:26.416578 <6>[ 5.146832] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10840 00:27:26.423107 <6>[ 5.152708] NET: Registered PF_PACKET protocol family
10841 00:27:26.426671 <6>[ 5.159019] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10842 00:27:26.433186 <6>[ 5.162956] 9pnet: Installing 9P2000 support
10843 00:27:26.436373 <6>[ 5.168764] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10844 00:27:26.443051 <5>[ 5.172652] Key type dns_resolver registered
10845 00:27:26.449708 <6>[ 5.178536] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10846 00:27:26.453129 <6>[ 5.182889] registered taskstats version 1
10847 00:27:26.456342 <5>[ 5.193258] Loading compiled-in X.509 certificates
10848 00:27:26.486034 <4>[ 5.215031] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10849 00:27:26.496173 <4>[ 5.225712] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10850 00:27:26.503022 <3>[ 5.236242] debugfs: File 'uA_load' in directory '/' already present!
10851 00:27:26.509380 <3>[ 5.242942] debugfs: File 'min_uV' in directory '/' already present!
10852 00:27:26.515679 <3>[ 5.249549] debugfs: File 'max_uV' in directory '/' already present!
10853 00:27:26.522099 <3>[ 5.256215] debugfs: File 'constraint_flags' in directory '/' already present!
10854 00:27:26.533321 <3>[ 5.265759] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10855 00:27:26.542425 <6>[ 5.278205] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10856 00:27:26.549524 <6>[ 5.285047] xhci-mtk 11200000.usb: xHCI Host Controller
10857 00:27:26.556064 <6>[ 5.290532] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10858 00:27:26.565967 <6>[ 5.298391] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10859 00:27:26.572849 <6>[ 5.307829] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10860 00:27:26.579505 <6>[ 5.313954] xhci-mtk 11200000.usb: xHCI Host Controller
10861 00:27:26.586840 <6>[ 5.319438] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10862 00:27:26.593119 <6>[ 5.327086] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10863 00:27:26.600049 <6>[ 5.334779] hub 1-0:1.0: USB hub found
10864 00:27:26.602972 <6>[ 5.338793] hub 1-0:1.0: 1 port detected
10865 00:27:26.609313 <6>[ 5.343072] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10866 00:27:26.616574 <6>[ 5.351642] hub 2-0:1.0: USB hub found
10867 00:27:26.619926 <6>[ 5.355650] hub 2-0:1.0: 1 port detected
10868 00:27:26.628481 <6>[ 5.364097] mtk-msdc 11f70000.mmc: Got CD GPIO
10869 00:27:26.640353 <6>[ 5.372612] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10870 00:27:26.646846 <6>[ 5.380629] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10871 00:27:26.656859 <4>[ 5.388537] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10872 00:27:26.666959 <6>[ 5.398073] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10873 00:27:26.673440 <6>[ 5.406149] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10874 00:27:26.680500 <6>[ 5.414299] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10875 00:27:26.690083 <6>[ 5.422235] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10876 00:27:26.696905 <6>[ 5.430054] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10877 00:27:26.706743 <6>[ 5.437875] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10878 00:27:26.716631 <6>[ 5.448343] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10879 00:27:26.723440 <6>[ 5.456729] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10880 00:27:26.733482 <6>[ 5.465068] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10881 00:27:26.740420 <6>[ 5.473409] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10882 00:27:26.750492 <6>[ 5.481749] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10883 00:27:26.756770 <6>[ 5.490088] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10884 00:27:26.766516 <6>[ 5.498427] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10885 00:27:26.773335 <6>[ 5.506765] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10886 00:27:26.783796 <6>[ 5.515105] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10887 00:27:26.790261 <6>[ 5.523443] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10888 00:27:26.799898 <6>[ 5.531780] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10889 00:27:26.806530 <6>[ 5.540118] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10890 00:27:26.816996 <6>[ 5.548456] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10891 00:27:26.823087 <6>[ 5.556793] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10892 00:27:26.833748 <6>[ 5.565131] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10893 00:27:26.840163 <6>[ 5.573917] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10894 00:27:26.846673 <6>[ 5.581083] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10895 00:27:26.853228 <6>[ 5.587850] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10896 00:27:26.859511 <6>[ 5.594617] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10897 00:27:26.866634 <6>[ 5.601567] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10898 00:27:26.876326 <6>[ 5.608416] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10899 00:27:26.886447 <6>[ 5.617548] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10900 00:27:26.896357 <6>[ 5.626666] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10901 00:27:26.906609 <6>[ 5.635960] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10902 00:27:26.912971 <6>[ 5.645428] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10903 00:27:26.923070 <6>[ 5.654895] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10904 00:27:26.932872 <6>[ 5.664016] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10905 00:27:26.942461 <6>[ 5.673485] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10906 00:27:26.952451 <6>[ 5.682603] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10907 00:27:26.962773 <6>[ 5.691899] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10908 00:27:26.972531 <6>[ 5.702059] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10909 00:27:26.982323 <6>[ 5.714112] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10910 00:27:27.009817 <6>[ 5.742167] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10911 00:27:27.038040 <6>[ 5.773372] hub 2-1:1.0: USB hub found
10912 00:27:27.040916 <6>[ 5.777841] hub 2-1:1.0: 3 ports detected
10913 00:27:27.161453 <6>[ 5.894073] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10914 00:27:27.316082 <6>[ 6.051960] hub 1-1:1.0: USB hub found
10915 00:27:27.319941 <6>[ 6.056412] hub 1-1:1.0: 4 ports detected
10916 00:27:27.394030 <6>[ 6.126396] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10917 00:27:27.641686 <6>[ 6.374160] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10918 00:27:27.773757 <6>[ 6.509371] hub 1-1.4:1.0: USB hub found
10919 00:27:27.776908 <6>[ 6.513989] hub 1-1.4:1.0: 2 ports detected
10920 00:27:28.073344 <6>[ 6.806124] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10921 00:27:28.265674 <6>[ 6.998160] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10922 00:27:39.258492 <6>[ 17.999099] ALSA device list:
10923 00:27:39.265076 <6>[ 18.002394] No soundcards found.
10924 00:27:39.273109 <6>[ 18.010349] Freeing unused kernel memory: 8384K
10925 00:27:39.276605 <6>[ 18.015354] Run /init as init process
10926 00:27:39.325638 <6>[ 18.062754] NET: Registered PF_INET6 protocol family
10927 00:27:39.332298 <6>[ 18.069429] Segment Routing with IPv6
10928 00:27:39.335464 <6>[ 18.073394] In-situ OAM (IOAM) with IPv6
10929 00:27:39.367413 <30>[ 18.087824] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10930 00:27:39.374635 <30>[ 18.111588] systemd[1]: Detected architecture arm64.
10931 00:27:39.374715
10932 00:27:39.380888 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10933 00:27:39.380967
10934 00:27:39.392736 <30>[ 18.130112] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10935 00:27:39.542690 <30>[ 18.276557] systemd[1]: Queued start job for default target Graphical Interface.
10936 00:27:39.569604 <30>[ 18.307040] systemd[1]: Created slice system-getty.slice.
10937 00:27:39.576709 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10938 00:27:39.594077 <30>[ 18.331067] systemd[1]: Created slice system-modprobe.slice.
10939 00:27:39.600712 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10940 00:27:39.617616 <30>[ 18.354408] systemd[1]: Created slice system-serial\x2dgetty.slice.
10941 00:27:39.626974 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10942 00:27:39.642215 <30>[ 18.379126] systemd[1]: Created slice User and Session Slice.
10943 00:27:39.648823 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10944 00:27:39.668683 <30>[ 18.402680] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10945 00:27:39.675505 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10946 00:27:39.696563 <30>[ 18.430302] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10947 00:27:39.703228 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10948 00:27:39.723586 <30>[ 18.454130] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10949 00:27:39.730229 <30>[ 18.466270] systemd[1]: Reached target Local Encrypted Volumes.
10950 00:27:39.736807 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10951 00:27:39.754386 <30>[ 18.490605] systemd[1]: Reached target Paths.
10952 00:27:39.756815 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10953 00:27:39.772898 <30>[ 18.510103] systemd[1]: Reached target Remote File Systems.
10954 00:27:39.779552 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10955 00:27:39.797099 <30>[ 18.534474] systemd[1]: Reached target Slices.
10956 00:27:39.803642 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10957 00:27:39.816673 <30>[ 18.554123] systemd[1]: Reached target Swap.
10958 00:27:39.819863 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10959 00:27:39.840567 <30>[ 18.574564] systemd[1]: Listening on initctl Compatibility Named Pipe.
10960 00:27:39.847602 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10961 00:27:39.854041 <30>[ 18.589715] systemd[1]: Listening on Journal Audit Socket.
10962 00:27:39.860501 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10963 00:27:39.873348 <30>[ 18.610567] systemd[1]: Listening on Journal Socket (/dev/log).
10964 00:27:39.880257 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10965 00:27:39.898144 <30>[ 18.635331] systemd[1]: Listening on Journal Socket.
10966 00:27:39.904569 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10967 00:27:39.917799 <30>[ 18.654682] systemd[1]: Listening on udev Control Socket.
10968 00:27:39.924209 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10969 00:27:39.941864 <30>[ 18.679125] systemd[1]: Listening on udev Kernel Socket.
10970 00:27:39.948529 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10971 00:27:40.004956 <30>[ 18.742287] systemd[1]: Mounting Huge Pages File System...
10972 00:27:40.011667 Mounting [0;1;39mHuge Pages File System[0m...
10973 00:27:40.029019 <30>[ 18.766066] systemd[1]: Mounting POSIX Message Queue File System...
10974 00:27:40.035296 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10975 00:27:40.073176 <30>[ 18.810163] systemd[1]: Mounting Kernel Debug File System...
10976 00:27:40.079625 Mounting [0;1;39mKernel Debug File System[0m...
10977 00:27:40.096602 <30>[ 18.830323] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10978 00:27:40.109292 <30>[ 18.843277] systemd[1]: Starting Create list of static device nodes for the current kernel...
10979 00:27:40.115945 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10980 00:27:40.137024 <30>[ 18.874394] systemd[1]: Starting Load Kernel Module configfs...
10981 00:27:40.143876 Starting [0;1;39mLoad Kernel Module configfs[0m...
10982 00:27:40.161055 <30>[ 18.898218] systemd[1]: Starting Load Kernel Module drm...
10983 00:27:40.167444 Starting [0;1;39mLoad Kernel Module drm[0m...
10984 00:27:40.184309 <30>[ 18.918172] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10985 00:27:40.199091 <30>[ 18.935663] systemd[1]: Starting Journal Service...
10986 00:27:40.201990 Starting [0;1;39mJournal Service[0m...
10987 00:27:40.233491 <30>[ 18.970400] systemd[1]: Starting Load Kernel Modules...
10988 00:27:40.239881 Starting [0;1;39mLoad Kernel Modules[0m...
10989 00:27:40.259104 <30>[ 18.992793] systemd[1]: Starting Remount Root and Kernel File Systems...
10990 00:27:40.265298 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10991 00:27:40.279237 <30>[ 19.016588] systemd[1]: Starting Coldplug All udev Devices...
10992 00:27:40.285996 Starting [0;1;39mColdplug All udev Devices[0m...
10993 00:27:40.303749 <30>[ 19.041091] systemd[1]: Started Journal Service.
10994 00:27:40.310393 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10995 00:27:40.326909 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10996 00:27:40.333616 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10997 00:27:40.350109 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10998 00:27:40.370891 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10999 00:27:40.388053 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11000 00:27:40.406598 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11001 00:27:40.422978 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11002 00:27:40.442937 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11003 00:27:40.456688 See 'systemctl status systemd-remount-fs.service' for details.
11004 00:27:40.508338 Mounting [0;1;39mKernel Configuration File System[0m...
11005 00:27:40.527731 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11006 00:27:40.542290 <46>[ 19.275687] systemd-journald[174]: Received client request to flush runtime journal.
11007 00:27:40.550456 Starting [0;1;39mLoad/Save Random Seed[0m...
11008 00:27:40.568948 Starting [0;1;39mApply Kernel Variables[0m...
11009 00:27:40.590082 Starting [0;1;39mCreate System Users[0m...
11010 00:27:40.609247 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11011 00:27:40.627362 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11012 00:27:40.650092 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11013 00:27:40.667226 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11014 00:27:40.686276 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11015 00:27:40.702214 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11016 00:27:40.741989 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11017 00:27:40.760838 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11018 00:27:40.777148 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11019 00:27:40.796998 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11020 00:27:40.842064 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11021 00:27:40.864908 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11022 00:27:40.894405 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11023 00:27:40.914440 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11024 00:27:40.968257 Starting [0;1;39mNetwork Time Synchronization[0m...
11025 00:27:40.992020 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11026 00:27:41.029128 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11027 00:27:41.073777 <6>[ 19.807715] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11028 00:27:41.094315 <6>[ 19.828270] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11029 00:27:41.101059 <6>[ 19.836311] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11030 00:27:41.111424 <6>[ 19.845100] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11031 00:27:41.117706 Startin<6>[ 19.854442] remoteproc remoteproc0: scp is available
11032 00:27:41.124417 g [0;1;39mLoad/<6>[ 19.861009] remoteproc remoteproc0: powering up scp
11033 00:27:41.134316 Save Screen …o<6>[ 19.867355] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11034 00:27:41.144136 f leds:white:kbd<4>[ 19.868995] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11035 00:27:41.151306 _backlight[0m..<6>[ 19.877166] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11036 00:27:41.151380 .
11037 00:27:41.157518 <4>[ 19.886391] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11038 00:27:41.171262 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11039 00:27:41.191862 <3>[ 19.925000] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11040 00:27:41.194199 <6>[ 19.931632] mc: Linux media interface: v0.10
11041 00:27:41.204415 <3>[ 19.933225] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11042 00:27:41.207534 <6>[ 19.940713] usbcore: registered new interface driver r8152
11043 00:27:41.217404 <3>[ 19.945776] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11044 00:27:41.223909 <3>[ 19.959881] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11045 00:27:41.234916 <3>[ 19.968057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11046 00:27:41.243876 [[0;32m OK [<3>[ 19.976206] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11047 00:27:41.253961 0m] Finished [0<3>[ 19.985866] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11048 00:27:41.260518 ;1;39mLoad/Save <3>[ 19.995327] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11049 00:27:41.270645 Screen …s of l<6>[ 19.999643] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11050 00:27:41.280563 eds:white:kbd_ba<3>[ 20.005405] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11051 00:27:41.280645 cklight[0m.
11052 00:27:41.287792 <6>[ 20.007474] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11053 00:27:41.297375 <6>[ 20.010523] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11054 00:27:41.304063 <6>[ 20.013174] pci_bus 0000:00: root bus resource [bus 00-ff]
11055 00:27:41.311896 <6>[ 20.013710] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11056 00:27:41.318477 <6>[ 20.013717] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11057 00:27:41.324942 <6>[ 20.013719] remoteproc remoteproc0: remote processor scp is now up
11058 00:27:41.334815 <6>[ 20.034375] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11059 00:27:41.345805 <4>[ 20.038247] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11060 00:27:41.348653 <4>[ 20.038247] Fallback method does not support PEC.
11061 00:27:41.358155 <6>[ 20.040559] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11062 00:27:41.365031 <3>[ 20.044394] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11063 00:27:41.374655 <3>[ 20.044415] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11064 00:27:41.381245 <3>[ 20.044422] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11065 00:27:41.388544 <3>[ 20.045877] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11066 00:27:41.399097 <3>[ 20.045889] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11067 00:27:41.405831 <3>[ 20.045893] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11068 00:27:41.412562 <3>[ 20.045900] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11069 00:27:41.422283 <3>[ 20.045905] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11070 00:27:41.432580 <6>[ 20.057059] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11071 00:27:41.439940 <3>[ 20.061970] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11072 00:27:41.449389 <6>[ 20.062069] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11073 00:27:41.456458 <6>[ 20.062126] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11074 00:27:41.463502 <6>[ 20.062155] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11075 00:27:41.469780 <6>[ 20.062262] pci 0000:00:00.0: supports D1 D2
11076 00:27:41.476763 <6>[ 20.062266] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11077 00:27:41.482942 <3>[ 20.070343] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11078 00:27:41.490150 <6>[ 20.081284] videodev: Linux video capture interface: v2.00
11079 00:27:41.496563 <6>[ 20.094294] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11080 00:27:41.503127 <6>[ 20.127680] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11081 00:27:41.509484 <6>[ 20.129482] Bluetooth: Core ver 2.22
11082 00:27:41.512940 <6>[ 20.129595] NET: Registered PF_BLUETOOTH protocol family
11083 00:27:41.519399 <6>[ 20.129599] Bluetooth: HCI device and connection manager initialized
11084 00:27:41.526073 <6>[ 20.129632] Bluetooth: HCI socket layer initialized
11085 00:27:41.529352 <6>[ 20.129641] Bluetooth: L2CAP socket layer initialized
11086 00:27:41.536031 <6>[ 20.129656] Bluetooth: SCO socket layer initialized
11087 00:27:41.546522 <3>[ 20.135862] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11088 00:27:41.552836 <6>[ 20.138371] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11089 00:27:41.559769 <6>[ 20.138400] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11090 00:27:41.566226 <6>[ 20.138428] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11091 00:27:41.572587 <6>[ 20.138444] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11092 00:27:41.579644 <6>[ 20.138555] pci 0000:01:00.0: supports D1 D2
11093 00:27:41.586397 <6>[ 20.138557] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11094 00:27:41.590353 <6>[ 20.148421] usbcore: registered new interface driver cdc_ether
11095 00:27:41.596539 <6>[ 20.153906] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11096 00:27:41.606724 <6>[ 20.153947] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11097 00:27:41.613649 <6>[ 20.153954] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11098 00:27:41.620774 <6>[ 20.153967] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11099 00:27:41.630692 <6>[ 20.153983] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11100 00:27:41.638037 <6>[ 20.153999] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11101 00:27:41.645067 <6>[ 20.154016] pci 0000:00:00.0: PCI bridge to [bus 01]
11102 00:27:41.651984 <6>[ 20.154024] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11103 00:27:41.658388 <6>[ 20.154190] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11104 00:27:41.664786 <6>[ 20.156468] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11105 00:27:41.671697 <3>[ 20.156807] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
11106 00:27:41.681262 <4>[ 20.169481] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11107 00:27:41.688145 <6>[ 20.174057] usbcore: registered new interface driver r8153_ecm
11108 00:27:41.694745 <6>[ 20.174862] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11109 00:27:41.701070 <4>[ 20.182578] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11110 00:27:41.711228 <3>[ 20.194316] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11111 00:27:41.721129 <4>[ 20.212411] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11112 00:27:41.724643 <6>[ 20.224663] usbcore: registered new interface driver btusb
11113 00:27:41.731176 <3>[ 20.225847] Bluetooth: hci0: Failed to load firmware file (-2)
11114 00:27:41.738030 <6>[ 20.251228] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11115 00:27:41.744808 <3>[ 20.256442] Bluetooth: hci0: Failed to set up firmware (-2)
11116 00:27:41.754779 <6>[ 20.294043] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11117 00:27:41.764402 <6>[ 20.295169] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11118 00:27:41.771267 <6>[ 20.295312] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11119 00:27:41.777787 <6>[ 20.296951] usbcore: registered new interface driver uvcvideo
11120 00:27:41.788104 <4>[ 20.301263] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11121 00:27:41.798259 <5>[ 20.310770] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11122 00:27:41.804618 <6>[ 20.318881] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11123 00:27:41.811343 <5>[ 20.331793] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11124 00:27:41.817528 <6>[ 20.334157] r8152 2-1.3:1.0 eth0: v1.12.13
11125 00:27:41.824282 <3>[ 20.336197] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11126 00:27:41.834413 <3>[ 20.338060] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11127 00:27:41.841271 <4>[ 20.340905] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11128 00:27:41.851203 <3>[ 20.360651] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11129 00:27:41.858172 <6>[ 20.364891] cfg80211: failed to load regulatory.db
11130 00:27:41.861499 <6>[ 20.365509] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
11131 00:27:41.871163 <3>[ 20.388267] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11132 00:27:41.877604 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11133 00:27:41.906424 <3>[ 20.640428] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11134 00:27:41.912810 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11135 00:27:41.923572 <6>[ 20.657653] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11136 00:27:41.927361 <6>[ 20.665149] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11137 00:27:41.938062 <3>[ 20.670344] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11138 00:27:41.954796 <6>[ 20.691814] mt7921e 0000:01:00.0: ASIC revision: 79610010
11139 00:27:42.031587 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11140 00:27:42.049391 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11141 00:27:42.063040 <4>[ 20.794079] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11142 00:27:42.073186 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11143 00:27:42.079545 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11144 00:27:42.092762 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11145 00:27:42.112652 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11146 00:27:42.124689 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11147 00:27:42.148206 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11148 00:27:42.160655 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11149 00:27:42.181530 <4>[ 20.912288] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11150 00:27:42.189835 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11151 00:27:42.208577 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11152 00:27:42.265643 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11153 00:27:42.301999 <4>[ 21.032730] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11154 00:27:42.314145 Starting [0;1;39mUser Login Management[0m...
11155 00:27:42.335519 Starting [0;1;39mPermit User Sessions[0m...
11156 00:27:42.350857 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11157 00:27:42.422195 <4>[ 21.152730] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11158 00:27:42.442505 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11159 00:27:42.461885 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11160 00:27:42.468242 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11161 00:27:42.488645 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11162 00:27:42.506655 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11163 00:27:42.526031 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11164 00:27:42.541491 [[0;32m OK [<4>[ 21.272796] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11165 00:27:42.548884 0m] Reached target [0;1;39mMulti-User System[0m.
11166 00:27:42.562636 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11167 00:27:42.613243 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11168 00:27:42.643267 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11169 00:27:42.661753 <4>[ 21.392729] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11170 00:27:42.677767
11171 00:27:42.677846
11172 00:27:42.681062 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11173 00:27:42.681134
11174 00:27:42.684551 debian-bullseye-arm64 login: root (automatic login)
11175 00:27:42.684618
11176 00:27:42.684703
11177 00:27:42.706005 Linux debian-bullseye-arm64 6.1.45-cip3 #1 SMP PREEMPT Mon Aug 14 00:09:07 UTC 2023 aarch64
11178 00:27:42.706093
11179 00:27:42.712597 The programs included with the Debian GNU/Linux system are free software;
11180 00:27:42.719725 the exact distribution terms for each program are described in the
11181 00:27:42.722597 individual files in /usr/share/doc/*/copyright.
11182 00:27:42.722677
11183 00:27:42.729205 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11184 00:27:42.732288 permitted by applicable law.
11185 00:27:42.732778 Matched prompt #10: / #
11187 00:27:42.732980 Setting prompt string to ['/ #']
11188 00:27:42.733076 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11190 00:27:42.733264 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11191 00:27:42.733356 start: 2.2.6 expect-shell-connection (timeout 00:01:53) [common]
11192 00:27:42.733424 Setting prompt string to ['/ #']
11193 00:27:42.733483 Forcing a shell prompt, looking for ['/ #']
11195 00:27:42.783666 / #
11196 00:27:42.783766 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11197 00:27:42.783840 Waiting using forced prompt support (timeout 00:02:30)
11198 00:27:42.786054 <4>[ 21.516816] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11199 00:27:42.828847
11200 00:27:42.829128 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11201 00:27:42.829222 start: 2.2.7 export-device-env (timeout 00:01:53) [common]
11202 00:27:42.829323 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11203 00:27:42.829408 end: 2.2 depthcharge-retry (duration 00:03:07) [common]
11204 00:27:42.829491 end: 2 depthcharge-action (duration 00:03:07) [common]
11205 00:27:42.829580 start: 3 lava-test-retry (timeout 00:05:00) [common]
11206 00:27:42.829662 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11207 00:27:42.829727 Using namespace: common
11209 00:27:42.929990 / # #
11210 00:27:42.930108 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11211 00:27:42.930223 #<4>[ 21.636393] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11212 00:27:42.935257
11213 00:27:42.935506 Using /lava-11280945
11215 00:27:43.035784 / # export SHELL=/bin/sh
11216 00:27:43.035936 export SHELL=/bin/sh<4>[ 21.756094] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11217 00:27:43.041076
11219 00:27:43.141532 / # . /lava-11280945/environment
11220 00:27:43.188796 . /lava-11280945/environment<4>[ 21.876680] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11221 00:27:43.188904
11223 00:27:43.289356 / # /lava-11280945/bin/lava-test-runner /lava-11280945/0
11224 00:27:43.289484 Test shell timeout: 10s (minimum of the action and connection timeout)
11225 00:27:43.289832 /lava-11280945/bin/lava-test-runner /lava-11280945/0<3>[ 21.994655] mt7921e 0000:01:00.0: hardware init failed
11226 00:27:43.294964
11227 00:27:43.336792 + export TESTRUN_ID=0_sleep
11228 00:27:43.336875 + cd /lava-11280945/0/tests/0_sleep
11229 00:27:43.336940 + cat uuid
11230 00:27:43.336999 + UUID=11280945_1.5.2.3.1
11231 00:27:43.337063 + set +x
11232 00:27:43.337120 <LAVA_SIGNAL_STARTRUN 0_sleep 11280945_1.5.2.3.1>
11233 00:27:43.337176 + ./config/lava/sleep/sleep.sh mem freeze
11234 00:27:43.337230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11235 00:27:43.337462 Received signal: <STARTRUN> 0_sleep 11280945_1.5.2.3.1
11236 00:27:43.337523 Starting test lava.0_sleep (11280945_1.5.2.3.1)
11237 00:27:43.337602 Skipping test definition patterns.
11238 00:27:43.337685 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11240 00:27:43.342364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11241 00:27:43.342608 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11243 00:27:43.345223 rtcwake: assuming RTC uses UTC ...
11244 00:27:43.354742 rtcwake: wakeup from "mem" using rtc0 at Mon<6>[ 22.091823] PM: suspend entry (deep)
11245 00:27:43.358018 Aug 14 00:27:52<6>[ 22.096129] Filesystems sync: 0.000 seconds
11246 00:27:43.358089 2023
11247 00:27:43.366029 <6>[ 22.103615] Freezing user space processes
11248 00:27:43.372532 <6>[ 22.109685] Freezing user space processes completed (elapsed 0.001 seconds)
11249 00:27:43.379357 <6>[ 22.116992] OOM killer disabled.
11250 00:27:43.382914 <6>[ 22.120484] Freezing remaining freezable tasks
11251 00:27:43.393064 <6>[ 22.126508] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11252 00:27:43.399441 <6>[ 22.134176] printk: Suspending console(s) (use no_console_suspend to debug)
11253 00:27:46.653798 <3>[ 25.166250] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11254 00:27:46.664314 <3>[ 25.166291] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11255 00:27:46.673928 <3>[ 25.166324] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11256 00:27:46.680734 <3>[ 25.166355] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11257 00:27:46.687107 <3>[ 25.166686] PM: Some devices failed to suspend, or early wake event detected
11258 00:27:46.696995 <4>[ 25.182072] typec port0-partner: PM: parent port0 should not be sleeping
11259 00:27:46.700790 <6>[ 25.438727] OOM killer enabled.
11260 00:27:46.707772 <6>[ 25.442143] Restarting tasks ... done.
11261 00:27:46.714597 <5>[ 25.450936] random: crng reseeded on system resumption
11262 00:27:46.717851 <6>[ 25.457449] PM: suspend exit
11263 00:27:46.721256 rtcwake: write error
11264 00:27:46.727863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11265 00:27:46.728141 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11267 00:27:46.731113 rtcwake: assuming RTC uses UTC ...
11268 00:27:46.734232 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 14 00:27:56 2023
11269 00:27:46.748742 <6>[ 25.486762] PM: suspend entry (deep)
11270 00:27:46.752402 <6>[ 25.490659] Filesystems sync: 0.000 seconds
11271 00:27:46.755413 <6>[ 25.495680] Freezing user space processes
11272 00:27:46.767144 <6>[ 25.501683] Freezing user space processes completed (elapsed 0.001 seconds)
11273 00:27:46.771120 <6>[ 25.508920] OOM killer disabled.
11274 00:27:46.774161 <6>[ 25.512402] Freezing remaining freezable tasks
11275 00:27:46.784029 <6>[ 25.517850] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11276 00:27:46.790461 <6>[ 25.525502] printk: Suspending console(s) (use no_console_suspend to debug)
11277 00:27:50.237531 <3>[ 28.750164] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11278 00:27:50.248028 <3>[ 28.750196] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11279 00:27:50.257818 <3>[ 28.750251] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11280 00:27:50.264256 <3>[ 28.750297] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11281 00:27:50.271060 <3>[ 28.750611] PM: Some devices failed to suspend, or early wake event detected
11282 00:27:50.274289 <6>[ 29.016007] OOM killer enabled.
11283 00:27:50.283069 <6>[ 29.019419] Restarting tasks ... done.
11284 00:27:50.286478 <5>[ 29.025548] random: crng reseeded on system resumption
11285 00:27:50.290266 <6>[ 29.032198] PM: suspend exit
11286 00:27:50.293880 rtcwake: write error
11287 00:27:50.300758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11288 00:27:50.301009 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11290 00:27:50.303678 rtcwake: assuming RTC uses UTC ...
11291 00:27:50.310857 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 14 00:27:59 2023
11292 00:27:50.322723 <6>[ 29.061333] PM: suspend entry (deep)
11293 00:27:50.326085 <6>[ 29.065243] Filesystems sync: 0.000 seconds
11294 00:27:50.329425 <6>[ 29.070327] Freezing user space processes
11295 00:27:50.341181 <6>[ 29.076224] Freezing user space processes completed (elapsed 0.001 seconds)
11296 00:27:50.344896 <6>[ 29.083446] OOM killer disabled.
11297 00:27:50.347898 <6>[ 29.086927] Freezing remaining freezable tasks
11298 00:27:50.358547 <6>[ 29.092803] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11299 00:27:50.364422 <6>[ 29.100452] printk: Suspending console(s) (use no_console_suspend to debug)
11300 00:27:53.829585 <3>[ 32.334164] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11301 00:27:53.840363 <3>[ 32.334194] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11302 00:27:53.850111 <3>[ 32.334237] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11303 00:27:53.856369 <3>[ 32.334278] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11304 00:27:53.863475 <3>[ 32.334578] PM: Some devices failed to suspend, or early wake event detected
11305 00:27:53.866398 <6>[ 32.608128] OOM killer enabled.
11306 00:27:53.875541 <6>[ 32.611546] Restarting tasks ... done.
11307 00:27:53.878817 <5>[ 32.617853] random: crng reseeded on system resumption
11308 00:27:53.882671 <6>[ 32.624550] PM: suspend exit
11309 00:27:53.885767 rtcwake: write error
11310 00:27:53.893458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11311 00:27:53.894139 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11313 00:27:53.896656 rtcwake: assuming RTC uses UTC ...
11314 00:27:53.903497 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 14 00:28:03 2023
11315 00:27:53.916365 <6>[ 32.654029] PM: suspend entry (deep)
11316 00:27:53.918975 <6>[ 32.657952] Filesystems sync: 0.000 seconds
11317 00:27:53.922426 <6>[ 32.662945] Freezing user space processes
11318 00:27:53.933855 <6>[ 32.668862] Freezing user space processes completed (elapsed 0.001 seconds)
11319 00:27:53.937042 <6>[ 32.676102] OOM killer disabled.
11320 00:27:53.940355 <6>[ 32.679584] Freezing remaining freezable tasks
11321 00:27:53.950783 <6>[ 32.685612] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11322 00:27:53.957031 <6>[ 32.693300] printk: Suspending console(s) (use no_console_suspend to debug)
11323 00:27:57.404962 <3>[ 35.918119] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11324 00:27:57.415070 <3>[ 35.918148] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11325 00:27:57.425835 <3>[ 35.918191] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11326 00:27:57.431883 <3>[ 35.918232] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11327 00:27:57.438231 <3>[ 35.918517] PM: Some devices failed to suspend, or early wake event detected
11328 00:27:57.441998 <6>[ 36.184144] OOM killer enabled.
11329 00:27:57.450393 <6>[ 36.187554] Restarting tasks ... done.
11330 00:27:57.457271 <5>[ 36.196365] random: crng reseeded on system resumption
11331 00:27:57.460484 <6>[ 36.203282] PM: suspend exit
11332 00:27:57.463643 rtcwake: write error
11333 00:27:57.471220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11334 00:27:57.471479 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11336 00:27:57.474762 rtcwake: assuming RTC uses UTC ...
11337 00:27:57.481100 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 14 00:28:07 2023
11338 00:27:57.493866 <6>[ 36.232823] PM: suspend entry (deep)
11339 00:27:57.497130 <6>[ 36.236720] Filesystems sync: 0.000 seconds
11340 00:27:57.500630 <6>[ 36.241713] Freezing user space processes
11341 00:27:57.511823 <6>[ 36.247820] Freezing user space processes completed (elapsed 0.001 seconds)
11342 00:27:57.515131 <6>[ 36.255067] OOM killer disabled.
11343 00:27:57.518527 <6>[ 36.258551] Freezing remaining freezable tasks
11344 00:27:57.528514 <6>[ 36.264598] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11345 00:27:57.535037 <6>[ 36.272271] printk: Suspending console(s) (use no_console_suspend to debug)
11346 00:28:00.997052 <3>[ 39.502163] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11347 00:28:01.007297 <3>[ 39.502193] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11348 00:28:01.016794 <3>[ 39.502235] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11349 00:28:01.023122 <3>[ 39.502276] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11350 00:28:01.030226 <3>[ 39.502572] PM: Some devices failed to suspend, or early wake event detected
11351 00:28:01.033267 <6>[ 39.776231] OOM killer enabled.
11352 00:28:01.042813 <6>[ 39.779641] Restarting tasks ... done.
11353 00:28:01.046026 <5>[ 39.786701] random: crng reseeded on system resumption
11354 00:28:01.050696 <6>[ 39.793917] PM: suspend exit
11355 00:28:01.054046 rtcwake: write error
11356 00:28:01.061057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11357 00:28:01.061313 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11359 00:28:01.064378 rtcwake: assuming RTC uses UTC ...
11360 00:28:01.071030 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 14 00:28:10 2023
11361 00:28:01.083775 <6>[ 39.823342] PM: suspend entry (deep)
11362 00:28:01.087095 <6>[ 39.827237] Filesystems sync: 0.000 seconds
11363 00:28:01.090130 <6>[ 39.832254] Freezing user space processes
11364 00:28:01.101685 <6>[ 39.837895] Freezing user space processes completed (elapsed 0.001 seconds)
11365 00:28:01.104623 <6>[ 39.845115] OOM killer disabled.
11366 00:28:01.108069 <6>[ 39.848595] Freezing remaining freezable tasks
11367 00:28:01.117978 <6>[ 39.854464] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11368 00:28:01.124785 <6>[ 39.862115] printk: Suspending console(s) (use no_console_suspend to debug)
11369 00:28:04.576785 <3>[ 43.086131] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11370 00:28:04.587259 <3>[ 43.086161] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11371 00:28:04.596998 <3>[ 43.086204] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11372 00:28:04.603984 <3>[ 43.086248] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11373 00:28:04.610032 <3>[ 43.086440] PM: Some devices failed to suspend, or early wake event detected
11374 00:28:04.613501 <6>[ 43.356238] OOM killer enabled.
11375 00:28:04.621822 <6>[ 43.359651] Restarting tasks ... done.
11376 00:28:04.625410 <5>[ 43.365728] random: crng reseeded on system resumption
11377 00:28:04.629511 <6>[ 43.372399] PM: suspend exit
11378 00:28:04.632363 rtcwake: write error
11379 00:28:04.639339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11380 00:28:04.640021 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11382 00:28:04.642961 rtcwake: assuming RTC uses UTC ...
11383 00:28:04.649435 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 14 00:28:14 2023
11384 00:28:04.661895 <6>[ 43.401858] PM: suspend entry (deep)
11385 00:28:04.665482 <6>[ 43.405730] Filesystems sync: 0.000 seconds
11386 00:28:04.668557 <6>[ 43.410744] Freezing user space processes
11387 00:28:04.679945 <6>[ 43.416636] Freezing user space processes completed (elapsed 0.001 seconds)
11388 00:28:04.683720 <6>[ 43.423872] OOM killer disabled.
11389 00:28:04.687251 <6>[ 43.427353] Freezing remaining freezable tasks
11390 00:28:04.697143 <6>[ 43.433395] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11391 00:28:04.704419 <6>[ 43.441085] printk: Suspending console(s) (use no_console_suspend to debug)
11392 00:28:08.160022 <3>[ 46.670148] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11393 00:28:08.170056 <3>[ 46.670183] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11394 00:28:08.180480 <3>[ 46.670230] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11395 00:28:08.187452 <3>[ 46.670271] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11396 00:28:08.193800 <3>[ 46.670463] PM: Some devices failed to suspend, or early wake event detected
11397 00:28:08.200352 <6>[ 46.940251] OOM killer enabled.
11398 00:28:08.203108 <6>[ 46.943661] Restarting tasks ... done.
11399 00:28:08.210244 <5>[ 46.949737] random: crng reseeded on system resumption
11400 00:28:08.213512 <6>[ 46.956349] PM: suspend exit
11401 00:28:08.216589 rtcwake: write error
11402 00:28:08.224248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11403 00:28:08.224929 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11405 00:28:08.227156 rtcwake: assuming RTC uses UTC ...
11406 00:28:08.233517 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 14 00:28:17 2023
11407 00:28:08.245340 <6>[ 46.985744] PM: suspend entry (deep)
11408 00:28:08.248246 <6>[ 46.989663] Filesystems sync: 0.000 seconds
11409 00:28:08.251816 <6>[ 46.994685] Freezing user space processes
11410 00:28:08.263792 <6>[ 47.000612] Freezing user space processes completed (elapsed 0.001 seconds)
11411 00:28:08.266865 <6>[ 47.007840] OOM killer disabled.
11412 00:28:08.269990 <6>[ 47.011322] Freezing remaining freezable tasks
11413 00:28:08.280072 <6>[ 47.017435] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11414 00:28:08.286765 <6>[ 47.025112] printk: Suspending console(s) (use no_console_suspend to debug)
11415 00:28:11.744103 <6>[ 48.206223] vpu: disabling
11416 00:28:11.747455 <6>[ 48.206367] vproc2: disabling
11417 00:28:11.750722 <6>[ 48.206428] vproc1: disabling
11418 00:28:11.753891 <6>[ 48.206482] vaud18: disabling
11419 00:28:11.757727 <6>[ 48.206730] vsram_others: disabling
11420 00:28:11.760878 <6>[ 48.206929] va09: disabling
11421 00:28:11.764422 <6>[ 48.207007] vsram_md: disabling
11422 00:28:11.767538 <6>[ 48.207135] Vgpu: disabling
11423 00:28:11.774212 <3>[ 50.254133] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11424 00:28:11.784245 <3>[ 50.254164] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11425 00:28:11.793996 <3>[ 50.254207] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11426 00:28:11.800872 <3>[ 50.254247] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11427 00:28:11.807663 <3>[ 50.254568] PM: Some devices failed to suspend, or early wake event detected
11428 00:28:11.810963 <6>[ 50.554095] OOM killer enabled.
11429 00:28:11.818830 <6>[ 50.557494] Restarting tasks ... done.
11430 00:28:11.821895 <5>[ 50.564058] random: crng reseeded on system resumption
11431 00:28:11.826626 <6>[ 50.570927] PM: suspend exit
11432 00:28:11.829655 rtcwake: write error
11433 00:28:11.836588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11434 00:28:11.836867 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11436 00:28:11.839988 rtcwake: assuming RTC uses UTC ...
11437 00:28:11.846420 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 14 00:28:21 2023
11438 00:28:11.859047 <6>[ 50.599920] PM: suspend entry (deep)
11439 00:28:11.862374 <6>[ 50.603812] Filesystems sync: 0.000 seconds
11440 00:28:11.865627 <6>[ 50.608857] Freezing user space processes
11441 00:28:11.877064 <6>[ 50.614626] Freezing user space processes completed (elapsed 0.001 seconds)
11442 00:28:11.880922 <6>[ 50.621845] OOM killer disabled.
11443 00:28:11.883784 <6>[ 50.625322] Freezing remaining freezable tasks
11444 00:28:11.893611 <6>[ 50.631356] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11445 00:28:11.900652 <6>[ 50.639028] printk: Suspending console(s) (use no_console_suspend to debug)
11446 00:28:15.330814 <3>[ 53.838114] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11447 00:28:15.340826 <3>[ 53.838145] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11448 00:28:15.350997 <3>[ 53.838187] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11449 00:28:15.357776 <3>[ 53.838227] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11450 00:28:15.367240 <3>[ 53.838505] PM: Some devices failed to suspend, or early wake event detected
11451 00:28:15.370565 <6>[ 54.112278] OOM killer enabled.
11452 00:28:15.374048 <6>[ 54.115690] Restarting tasks ... done.
11453 00:28:15.381926 <5>[ 54.123285] random: crng reseeded on system resumption
11454 00:28:15.385486 <6>[ 54.129997] PM: suspend exit
11455 00:28:15.388622 rtcwake: write error
11456 00:28:15.395742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11457 00:28:15.395994 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11459 00:28:15.398972 rtcwake: assuming RTC uses UTC ...
11460 00:28:15.405789 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 14 00:28:25 2023
11461 00:28:15.418333 <6>[ 54.159446] PM: suspend entry (deep)
11462 00:28:15.421731 <6>[ 54.163340] Filesystems sync: 0.000 seconds
11463 00:28:15.424851 <6>[ 54.168371] Freezing user space processes
11464 00:28:15.435774 <6>[ 54.173948] Freezing user space processes completed (elapsed 0.001 seconds)
11465 00:28:15.438929 <6>[ 54.181169] OOM killer disabled.
11466 00:28:15.442322 <6>[ 54.184648] Freezing remaining freezable tasks
11467 00:28:15.452235 <6>[ 54.190535] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11468 00:28:15.459036 <6>[ 54.198186] printk: Suspending console(s) (use no_console_suspend to debug)
11469 00:28:18.910960 <3>[ 57.422115] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11470 00:28:18.920513 <3>[ 57.422145] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11471 00:28:18.930646 <3>[ 57.422188] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11472 00:28:18.937474 <3>[ 57.422228] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11473 00:28:18.944596 <3>[ 57.422516] PM: Some devices failed to suspend, or early wake event detected
11474 00:28:18.947371 <6>[ 57.692107] OOM killer enabled.
11475 00:28:18.955948 <6>[ 57.695518] Restarting tasks ... done.
11476 00:28:18.959498 <5>[ 57.701224] random: crng reseeded on system resumption
11477 00:28:18.963019 <6>[ 57.707797] PM: suspend exit
11478 00:28:18.966621 rtcwake: write error
11479 00:28:18.974282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11480 00:28:18.975060 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11482 00:28:18.977092 rtcwake: assuming RTC uses UTC ...
11483 00:28:18.983434 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 14 00:28:28 2023
11484 00:28:18.996909 <6>[ 57.738446] PM: suspend entry (s2idle)
11485 00:28:19.000295 <6>[ 57.742506] Filesystems sync: 0.000 seconds
11486 00:28:19.003557 <6>[ 57.747547] Freezing user space processes
11487 00:28:19.015444 <6>[ 57.753427] Freezing user space processes completed (elapsed 0.001 seconds)
11488 00:28:19.018808 <6>[ 57.760646] OOM killer disabled.
11489 00:28:19.022135 <6>[ 57.764125] Freezing remaining freezable tasks
11490 00:28:19.031789 <6>[ 57.769865] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11491 00:28:19.038392 <6>[ 57.777515] printk: Suspending console(s) (use no_console_suspend to debug)
11492 00:28:22.498308 <3>[ 61.006116] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11493 00:28:22.508616 <3>[ 61.006147] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11494 00:28:22.518345 <3>[ 61.006189] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11495 00:28:22.525036 <3>[ 61.006234] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11496 00:28:22.531786 <3>[ 61.006492] PM: Some devices failed to suspend, or early wake event detected
11497 00:28:22.535089 <6>[ 61.280140] OOM killer enabled.
11498 00:28:22.543548 <6>[ 61.283552] Restarting tasks ... done.
11499 00:28:22.546507 <5>[ 61.289077] random: crng reseeded on system resumption
11500 00:28:22.551017 <6>[ 61.296189] PM: suspend exit
11501 00:28:22.554263 rtcwake: write error
11502 00:28:22.562043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11503 00:28:22.562824 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11505 00:28:22.564907 rtcwake: assuming RTC uses UTC ...
11506 00:28:22.571723 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 14 00:28:32 2023
11507 00:28:22.583696 <6>[ 61.325763] PM: suspend entry (s2idle)
11508 00:28:22.587147 <6>[ 61.329844] Filesystems sync: 0.000 seconds
11509 00:28:22.590521 <6>[ 61.334776] Freezing user space processes
11510 00:28:22.602308 <6>[ 61.340722] Freezing user space processes completed (elapsed 0.001 seconds)
11511 00:28:22.605496 <6>[ 61.347953] OOM killer disabled.
11512 00:28:22.608765 <6>[ 61.351436] Freezing remaining freezable tasks
11513 00:28:22.619019 <6>[ 61.357463] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11514 00:28:22.626027 <6>[ 61.365136] printk: Suspending console(s) (use no_console_suspend to debug)
11515 00:28:26.082130 <3>[ 64.590154] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11516 00:28:26.092765 <3>[ 64.590187] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11517 00:28:26.101840 <3>[ 64.590234] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11518 00:28:26.108758 <3>[ 64.590274] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11519 00:28:26.115368 <3>[ 64.590498] PM: Some devices failed to suspend, or early wake event detected
11520 00:28:26.118843 <6>[ 64.864147] OOM killer enabled.
11521 00:28:26.127355 <6>[ 64.867559] Restarting tasks ... done.
11522 00:28:26.130241 <5>[ 64.873321] random: crng reseeded on system resumption
11523 00:28:26.134760 <6>[ 64.880000] PM: suspend exit
11524 00:28:26.137633 rtcwake: write error
11525 00:28:26.144755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11526 00:28:26.145475 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11528 00:28:26.148301 rtcwake: assuming RTC uses UTC ...
11529 00:28:26.154828 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 14 00:28:35 2023
11530 00:28:26.167118 <6>[ 64.909365] PM: suspend entry (s2idle)
11531 00:28:26.171031 <6>[ 64.913449] Filesystems sync: 0.000 seconds
11532 00:28:26.174041 <6>[ 64.918527] Freezing user space processes
11533 00:28:26.185584 <6>[ 64.924541] Freezing user space processes completed (elapsed 0.001 seconds)
11534 00:28:26.188727 <6>[ 64.931773] OOM killer disabled.
11535 00:28:26.192219 <6>[ 64.935255] Freezing remaining freezable tasks
11536 00:28:26.202162 <6>[ 64.941309] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11537 00:28:26.209742 <6>[ 64.948981] printk: Suspending console(s) (use no_console_suspend to debug)
11538 00:28:29.665670 <3>[ 68.174121] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11539 00:28:29.675441 <3>[ 68.174151] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11540 00:28:29.685565 <3>[ 68.174194] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11541 00:28:29.692295 <3>[ 68.174235] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11542 00:28:29.698665 <3>[ 68.174538] PM: Some devices failed to suspend, or early wake event detected
11543 00:28:29.702049 <6>[ 68.448134] OOM killer enabled.
11544 00:28:29.710600 <6>[ 68.451547] Restarting tasks ... done.
11545 00:28:29.713812 <5>[ 68.457315] random: crng reseeded on system resumption
11546 00:28:29.717672 <6>[ 68.463836] PM: suspend exit
11547 00:28:29.720740 rtcwake: write error
11548 00:28:29.728121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11549 00:28:29.728833 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11551 00:28:29.731397 rtcwake: assuming RTC uses UTC ...
11552 00:28:29.737871 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 14 00:28:39 2023
11553 00:28:29.750597 <6>[ 68.493454] PM: suspend entry (s2idle)
11554 00:28:29.754165 <6>[ 68.497523] Filesystems sync: 0.000 seconds
11555 00:28:29.757356 <6>[ 68.502507] Freezing user space processes
11556 00:28:29.769360 <6>[ 68.508475] Freezing user space processes completed (elapsed 0.001 seconds)
11557 00:28:29.772414 <6>[ 68.515710] OOM killer disabled.
11558 00:28:29.775919 <6>[ 68.519190] Freezing remaining freezable tasks
11559 00:28:29.785864 <6>[ 68.525270] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11560 00:28:29.792540 <6>[ 68.532944] printk: Suspending console(s) (use no_console_suspend to debug)
11561 00:28:33.248656 <3>[ 71.758453] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11562 00:28:33.258949 <3>[ 71.758483] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11563 00:28:33.269035 <3>[ 71.758526] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11564 00:28:33.275785 <3>[ 71.758570] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11565 00:28:33.282138 <3>[ 71.758753] PM: Some devices failed to suspend, or early wake event detected
11566 00:28:33.285658 <6>[ 72.032111] OOM killer enabled.
11567 00:28:33.295363 <6>[ 72.035524] Restarting tasks ... done.
11568 00:28:33.298724 <5>[ 72.042684] random: crng reseeded on system resumption
11569 00:28:33.302655 <6>[ 72.049406] PM: suspend exit
11570 00:28:33.306151 rtcwake: write error
11571 00:28:33.313501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11572 00:28:33.313748 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11574 00:28:33.316520 rtcwake: assuming RTC uses UTC ...
11575 00:28:33.322889 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 14 00:28:42 2023
11576 00:28:33.335631 <6>[ 72.078834] PM: suspend entry (s2idle)
11577 00:28:33.339074 <6>[ 72.082904] Filesystems sync: 0.000 seconds
11578 00:28:33.342038 <6>[ 72.087907] Freezing user space processes
11579 00:28:33.353449 <6>[ 72.093876] Freezing user space processes completed (elapsed 0.001 seconds)
11580 00:28:33.356652 <6>[ 72.101106] OOM killer disabled.
11581 00:28:33.360549 <6>[ 72.104586] Freezing remaining freezable tasks
11582 00:28:33.370569 <6>[ 72.110492] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11583 00:28:33.376880 <6>[ 72.118144] printk: Suspending console(s) (use no_console_suspend to debug)
11584 00:28:36.833020 <3>[ 75.342201] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11585 00:28:36.843084 <3>[ 75.342239] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11586 00:28:36.852660 <3>[ 75.342288] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11587 00:28:36.859510 <3>[ 75.342328] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11588 00:28:36.866042 <3>[ 75.342584] PM: Some devices failed to suspend, or early wake event detected
11589 00:28:36.869447 <6>[ 75.616176] OOM killer enabled.
11590 00:28:36.877516 <6>[ 75.619587] Restarting tasks ... done.
11591 00:28:36.881282 <5>[ 75.625382] random: crng reseeded on system resumption
11592 00:28:36.885815 <6>[ 75.632167] PM: suspend exit
11593 00:28:36.888494 rtcwake: write error
11594 00:28:36.895853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11595 00:28:36.896707 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11597 00:28:36.899262 rtcwake: assuming RTC uses UTC ...
11598 00:28:36.905617 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 14 00:28:46 2023
11599 00:28:36.918249 <6>[ 75.662020] PM: suspend entry (s2idle)
11600 00:28:36.922419 <6>[ 75.666076] Filesystems sync: 0.000 seconds
11601 00:28:36.925239 <6>[ 75.671081] Freezing user space processes
11602 00:28:36.936601 <6>[ 75.676992] Freezing user space processes completed (elapsed 0.001 seconds)
11603 00:28:36.939843 <6>[ 75.684224] OOM killer disabled.
11604 00:28:36.943095 <6>[ 75.687711] Freezing remaining freezable tasks
11605 00:28:36.953801 <6>[ 75.693718] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11606 00:28:36.960067 <6>[ 75.701392] printk: Suspending console(s) (use no_console_suspend to debug)
11607 00:28:40.416129 <3>[ 78.926120] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11608 00:28:40.426107 <3>[ 78.926150] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11609 00:28:40.436434 <3>[ 78.926193] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11610 00:28:40.442891 <3>[ 78.926233] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11611 00:28:40.449397 <3>[ 78.926519] PM: Some devices failed to suspend, or early wake event detected
11612 00:28:40.456538 <6>[ 79.200142] OOM killer enabled.
11613 00:28:40.459657 <6>[ 79.203555] Restarting tasks ... done.
11614 00:28:40.465942 <5>[ 79.210159] random: crng reseeded on system resumption
11615 00:28:40.469341 <6>[ 79.216715] PM: suspend exit
11616 00:28:40.472497 rtcwake: write error
11617 00:28:40.479782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11618 00:28:40.480478 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11620 00:28:40.483798 rtcwake: assuming RTC uses UTC ...
11621 00:28:40.489709 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 14 00:28:50 2023
11622 00:28:40.502046 <6>[ 79.246132] PM: suspend entry (s2idle)
11623 00:28:40.505736 <6>[ 79.250194] Filesystems sync: 0.000 seconds
11624 00:28:40.508848 <6>[ 79.255205] Freezing user space processes
11625 00:28:40.520564 <6>[ 79.261111] Freezing user space processes completed (elapsed 0.001 seconds)
11626 00:28:40.523842 <6>[ 79.268345] OOM killer disabled.
11627 00:28:40.526973 <6>[ 79.271825] Freezing remaining freezable tasks
11628 00:28:40.537614 <6>[ 79.277885] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11629 00:28:40.543812 <6>[ 79.285564] printk: Suspending console(s) (use no_console_suspend to debug)
11630 00:28:43.999593 <3>[ 82.510147] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11631 00:28:44.010103 <3>[ 82.510177] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11632 00:28:44.019743 <3>[ 82.510220] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11633 00:28:44.026671 <3>[ 82.510260] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11634 00:28:44.033667 <3>[ 82.510712] PM: Some devices failed to suspend, or early wake event detected
11635 00:28:44.036653 <6>[ 82.784120] OOM killer enabled.
11636 00:28:44.045018 <6>[ 82.787530] Restarting tasks ... done.
11637 00:28:44.048215 <5>[ 82.793525] random: crng reseeded on system resumption
11638 00:28:44.052516 <6>[ 82.800493] PM: suspend exit
11639 00:28:44.055965 rtcwake: write error
11640 00:28:44.063443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11641 00:28:44.064113 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11643 00:28:44.066224 rtcwake: assuming RTC uses UTC ...
11644 00:28:44.073200 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 14 00:28:53 2023
11645 00:28:44.085747 <6>[ 82.830140] PM: suspend entry (s2idle)
11646 00:28:44.089757 <6>[ 82.834215] Filesystems sync: 0.000 seconds
11647 00:28:44.092750 <6>[ 82.839228] Freezing user space processes
11648 00:28:44.104326 <6>[ 82.845146] Freezing user space processes completed (elapsed 0.001 seconds)
11649 00:28:44.107502 <6>[ 82.852378] OOM killer disabled.
11650 00:28:44.110473 <6>[ 82.855860] Freezing remaining freezable tasks
11651 00:28:44.121151 <6>[ 82.861940] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11652 00:28:44.127405 <6>[ 82.869606] printk: Suspending console(s) (use no_console_suspend to debug)
11653 00:28:47.583392 <3>[ 86.094116] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11654 00:28:47.593223 <3>[ 86.094146] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11655 00:28:47.603455 <3>[ 86.094189] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11656 00:28:47.610222 <3>[ 86.094229] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11657 00:28:47.616575 <3>[ 86.094529] PM: Some devices failed to suspend, or early wake event detected
11658 00:28:47.620051 <6>[ 86.367986] OOM killer enabled.
11659 00:28:47.630975 <6>[ 86.371404] Restarting tasks ... done.
11660 00:28:47.634487 <5>[ 86.379876] random: crng reseeded on system resumption
11661 00:28:47.638373 <6>[ 86.386756] PM: suspend exit
11662 00:28:47.641662 rtcwake: write error
11663 00:28:47.649277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11664 00:28:47.650000 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11666 00:28:47.652008 rtcwake: assuming RTC uses UTC ...
11667 00:28:47.658954 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 14 00:28:57 2023
11668 00:28:47.671150 <6>[ 86.415847] PM: suspend entry (s2idle)
11669 00:28:47.674871 <6>[ 86.419905] Filesystems sync: 0.000 seconds
11670 00:28:47.678216 <6>[ 86.424897] Freezing user space processes
11671 00:28:47.689427 <6>[ 86.430707] Freezing user space processes completed (elapsed 0.001 seconds)
11672 00:28:47.692600 <6>[ 86.437925] OOM killer disabled.
11673 00:28:47.695655 <6>[ 86.441403] Freezing remaining freezable tasks
11674 00:28:47.705649 <6>[ 86.447444] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11675 00:28:47.712239 <6>[ 86.455116] printk: Suspending console(s) (use no_console_suspend to debug)
11676 00:28:51.166968 <3>[ 89.678117] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11677 00:28:51.176865 <3>[ 89.678146] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11678 00:28:51.187060 <3>[ 89.678189] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11679 00:28:51.193879 <3>[ 89.678233] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11680 00:28:51.200347 <3>[ 89.678422] PM: Some devices failed to suspend, or early wake event detected
11681 00:28:51.204142 <6>[ 89.952148] OOM killer enabled.
11682 00:28:51.214458 <6>[ 89.955560] Restarting tasks ... done.
11683 00:28:51.217892 <5>[ 89.963723] random: crng reseeded on system resumption
11684 00:28:51.221345 <6>[ 89.970124] PM: suspend exit
11685 00:28:51.224854 rtcwake: write error
11686 00:28:51.232172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11687 00:28:51.232846 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11689 00:28:51.235177 rtcwake: assuming RTC uses UTC ...
11690 00:28:51.242191 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 14 00:29:00 2023
11691 00:28:51.254627 <6>[ 89.999488] PM: suspend entry (s2idle)
11692 00:28:51.257685 <6>[ 90.003550] Filesystems sync: 0.000 seconds
11693 00:28:51.261024 <6>[ 90.008569] Freezing user space processes
11694 00:28:51.271774 <6>[ 90.013912] Freezing user space processes completed (elapsed 0.001 seconds)
11695 00:28:51.275419 <6>[ 90.021133] OOM killer disabled.
11696 00:28:51.278377 <6>[ 90.024613] Freezing remaining freezable tasks
11697 00:28:51.288958 <6>[ 90.030496] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11698 00:28:51.295663 <6>[ 90.038145] printk: Suspending console(s) (use no_console_suspend to debug)
11699 00:28:54.750768 <3>[ 93.262216] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11700 00:28:54.760540 <3>[ 93.262261] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11701 00:28:54.770443 <3>[ 93.262313] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11702 00:28:54.777485 <3>[ 93.262361] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11703 00:28:54.784012 <3>[ 93.262621] PM: Some devices failed to suspend, or early wake event detected
11704 00:28:54.790601 <6>[ 93.536267] OOM killer enabled.
11705 00:28:54.798098 <6>[ 93.539678] Restarting tasks ... done.
11706 00:28:54.801708 <5>[ 93.547815] random: crng reseeded on system resumption
11707 00:28:54.805982 <6>[ 93.554525] PM: suspend exit
11708 00:28:54.808560 rtcwake: write error
11709 00:28:54.815922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11710 00:28:54.816327 + set +x
11711 00:28:54.816916 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11713 00:28:54.822500 <LAVA_SIGNAL_ENDRUN 0_sleep 11280945_1.5.2.3.1>
11714 00:28:54.822947 <LAVA_TEST_RUNNER EXIT>
11715 00:28:54.823601 Received signal: <ENDRUN> 0_sleep 11280945_1.5.2.3.1
11716 00:28:54.823972 Ending use of test pattern.
11717 00:28:54.824304 Ending test lava.0_sleep (11280945_1.5.2.3.1), duration 71.49
11719 00:28:54.826093 ok: lava_test_shell seems to have completed
11720 00:28:54.827049 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
11721 00:28:54.827515 end: 3.1 lava-test-shell (duration 00:01:12) [common]
11722 00:28:54.827935 end: 3 lava-test-retry (duration 00:01:12) [common]
11723 00:28:54.828349 start: 4 finalize (timeout 00:05:11) [common]
11724 00:28:54.828872 start: 4.1 power-off (timeout 00:00:30) [common]
11725 00:28:54.829608 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11726 00:28:54.913750 >> Command sent successfully.
11727 00:28:54.918370 Returned 0 in 0 seconds
11728 00:28:55.019452 end: 4.1 power-off (duration 00:00:00) [common]
11730 00:28:55.020988 start: 4.2 read-feedback (timeout 00:05:11) [common]
11731 00:28:55.022529 Listened to connection for namespace 'common' for up to 1s
11732 00:28:55.023411 Listened to connection for namespace 'common' for up to 1s
11733 00:28:56.022723 Finalising connection for namespace 'common'
11734 00:28:56.022906 Disconnecting from shell: Finalise
11735 00:28:56.022998 / #
11736 00:28:56.123696 end: 4.2 read-feedback (duration 00:00:01) [common]
11737 00:28:56.124536 end: 4 finalize (duration 00:00:01) [common]
11738 00:28:56.125298 Cleaning after the job
11739 00:28:56.125819 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11280945/tftp-deploy-adx72mtx/ramdisk
11740 00:28:56.170623 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11280945/tftp-deploy-adx72mtx/kernel
11741 00:28:56.198962 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11280945/tftp-deploy-adx72mtx/dtb
11742 00:28:56.199188 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11280945/tftp-deploy-adx72mtx/modules
11743 00:28:56.206271 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11280945
11744 00:28:56.374723 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11280945
11745 00:28:56.374898 Job finished correctly