Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 73
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 38
- Errors: 1
1 00:23:40.827175 lava-dispatcher, installed at version: 2023.05.1
2 00:23:40.827379 start: 0 validate
3 00:23:40.827511 Start time: 2023-08-14 00:23:40.827503+00:00 (UTC)
4 00:23:40.827631 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:23:40.827794 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 00:23:41.098380 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:23:41.099239 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:23:58.388800 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:23:58.389535 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:23:58.660138 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:23:58.660861 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:24:01.428348 validate duration: 20.60
14 00:24:01.428596 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:24:01.428691 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:24:01.428778 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:24:01.428897 Not decompressing ramdisk as can be used compressed.
18 00:24:01.428981 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 00:24:01.429041 saving as /var/lib/lava/dispatcher/tmp/11280966/tftp-deploy-20drlgbp/ramdisk/rootfs.cpio.gz
20 00:24:01.429098 total size: 26246609 (25MB)
21 00:24:01.694839 progress 0% (0MB)
22 00:24:01.701924 progress 5% (1MB)
23 00:24:01.708693 progress 10% (2MB)
24 00:24:01.715509 progress 15% (3MB)
25 00:24:01.722383 progress 20% (5MB)
26 00:24:01.729205 progress 25% (6MB)
27 00:24:01.736022 progress 30% (7MB)
28 00:24:01.742851 progress 35% (8MB)
29 00:24:01.749604 progress 40% (10MB)
30 00:24:01.756393 progress 45% (11MB)
31 00:24:01.763245 progress 50% (12MB)
32 00:24:01.770028 progress 55% (13MB)
33 00:24:01.776803 progress 60% (15MB)
34 00:24:01.783540 progress 65% (16MB)
35 00:24:01.790307 progress 70% (17MB)
36 00:24:01.797243 progress 75% (18MB)
37 00:24:01.804488 progress 80% (20MB)
38 00:24:01.811280 progress 85% (21MB)
39 00:24:01.817876 progress 90% (22MB)
40 00:24:01.824763 progress 95% (23MB)
41 00:24:01.831488 progress 100% (25MB)
42 00:24:01.831751 25MB downloaded in 0.40s (62.17MB/s)
43 00:24:01.831901 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:24:01.832132 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:24:01.832215 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:24:01.832295 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:24:01.832430 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:24:01.832500 saving as /var/lib/lava/dispatcher/tmp/11280966/tftp-deploy-20drlgbp/kernel/Image
50 00:24:01.832560 total size: 49220096 (46MB)
51 00:24:01.832618 No compression specified
52 00:24:01.833686 progress 0% (0MB)
53 00:24:01.846433 progress 5% (2MB)
54 00:24:01.859113 progress 10% (4MB)
55 00:24:01.871848 progress 15% (7MB)
56 00:24:01.884500 progress 20% (9MB)
57 00:24:01.897151 progress 25% (11MB)
58 00:24:01.909927 progress 30% (14MB)
59 00:24:01.922583 progress 35% (16MB)
60 00:24:01.935348 progress 40% (18MB)
61 00:24:01.948146 progress 45% (21MB)
62 00:24:01.961041 progress 50% (23MB)
63 00:24:01.973620 progress 55% (25MB)
64 00:24:01.986314 progress 60% (28MB)
65 00:24:01.999221 progress 65% (30MB)
66 00:24:02.011919 progress 70% (32MB)
67 00:24:02.024751 progress 75% (35MB)
68 00:24:02.037419 progress 80% (37MB)
69 00:24:02.050182 progress 85% (39MB)
70 00:24:02.062739 progress 90% (42MB)
71 00:24:02.075270 progress 95% (44MB)
72 00:24:02.087815 progress 100% (46MB)
73 00:24:02.087956 46MB downloaded in 0.26s (183.80MB/s)
74 00:24:02.088099 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:24:02.088322 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:24:02.088405 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:24:02.088485 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:24:02.088623 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:24:02.088709 saving as /var/lib/lava/dispatcher/tmp/11280966/tftp-deploy-20drlgbp/dtb/mt8192-asurada-spherion-r0.dtb
81 00:24:02.088769 total size: 47278 (0MB)
82 00:24:02.088826 No compression specified
83 00:24:02.089957 progress 69% (0MB)
84 00:24:02.090227 progress 100% (0MB)
85 00:24:02.090379 0MB downloaded in 0.00s (28.04MB/s)
86 00:24:02.090495 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:24:02.090810 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:24:02.090893 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:24:02.090972 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:24:02.091081 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:24:02.091146 saving as /var/lib/lava/dispatcher/tmp/11280966/tftp-deploy-20drlgbp/modules/modules.tar
93 00:24:02.091203 total size: 8562896 (8MB)
94 00:24:02.091260 Using unxz to decompress xz
95 00:24:02.095352 progress 0% (0MB)
96 00:24:02.117109 progress 5% (0MB)
97 00:24:02.139362 progress 10% (0MB)
98 00:24:02.165403 progress 15% (1MB)
99 00:24:02.190810 progress 20% (1MB)
100 00:24:02.216634 progress 25% (2MB)
101 00:24:02.242778 progress 30% (2MB)
102 00:24:02.267388 progress 35% (2MB)
103 00:24:02.292146 progress 40% (3MB)
104 00:24:02.316563 progress 45% (3MB)
105 00:24:02.343267 progress 50% (4MB)
106 00:24:02.368038 progress 55% (4MB)
107 00:24:02.392358 progress 60% (4MB)
108 00:24:02.414764 progress 65% (5MB)
109 00:24:02.440089 progress 70% (5MB)
110 00:24:02.464048 progress 75% (6MB)
111 00:24:02.491628 progress 80% (6MB)
112 00:24:02.521757 progress 85% (6MB)
113 00:24:02.547360 progress 90% (7MB)
114 00:24:02.571342 progress 95% (7MB)
115 00:24:02.594099 progress 100% (8MB)
116 00:24:02.599137 8MB downloaded in 0.51s (16.08MB/s)
117 00:24:02.599415 end: 1.4.1 http-download (duration 00:00:01) [common]
119 00:24:02.599672 end: 1.4 download-retry (duration 00:00:01) [common]
120 00:24:02.599832 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:24:02.599929 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:24:02.600008 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:24:02.600091 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:24:02.600319 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh
125 00:24:02.600450 makedir: /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin
126 00:24:02.600552 makedir: /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/tests
127 00:24:02.600648 makedir: /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/results
128 00:24:02.600758 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-add-keys
129 00:24:02.600904 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-add-sources
130 00:24:02.601037 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-background-process-start
131 00:24:02.601163 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-background-process-stop
132 00:24:02.601286 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-common-functions
133 00:24:02.601406 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-echo-ipv4
134 00:24:02.601576 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-install-packages
135 00:24:02.601716 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-installed-packages
136 00:24:02.601837 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-os-build
137 00:24:02.601960 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-probe-channel
138 00:24:02.602082 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-probe-ip
139 00:24:02.602205 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-target-ip
140 00:24:02.602325 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-target-mac
141 00:24:02.602445 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-target-storage
142 00:24:02.602571 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-test-case
143 00:24:02.602734 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-test-event
144 00:24:02.602854 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-test-feedback
145 00:24:02.602974 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-test-raise
146 00:24:02.603105 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-test-reference
147 00:24:02.603227 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-test-runner
148 00:24:02.603348 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-test-set
149 00:24:02.603472 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-test-shell
150 00:24:02.603596 Updating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-install-packages (oe)
151 00:24:02.603745 Updating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/bin/lava-installed-packages (oe)
152 00:24:02.603864 Creating /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/environment
153 00:24:02.603961 LAVA metadata
154 00:24:02.604035 - LAVA_JOB_ID=11280966
155 00:24:02.604098 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:24:02.604200 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:24:02.604265 skipped lava-vland-overlay
158 00:24:02.604336 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:24:02.604415 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:24:02.604474 skipped lava-multinode-overlay
161 00:24:02.604545 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:24:02.604626 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:24:02.604695 Loading test definitions
164 00:24:02.604783 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:24:02.604851 Using /lava-11280966 at stage 0
166 00:24:02.605209 uuid=11280966_1.5.2.3.1 testdef=None
167 00:24:02.605294 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:24:02.605375 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:24:02.605890 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:24:02.606103 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:24:02.606744 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:24:02.606970 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:24:02.607594 runner path: /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 11280966_1.5.2.3.1
176 00:24:02.607746 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:24:02.607948 Creating lava-test-runner.conf files
179 00:24:02.608009 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11280966/lava-overlay-o8981exh/lava-11280966/0 for stage 0
180 00:24:02.608095 - 0_v4l2-compliance-mtk-vcodec-enc
181 00:24:02.608191 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:24:02.608272 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:24:02.614879 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:24:02.614978 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:24:02.615103 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:24:02.615338 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:24:02.615438 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:24:03.332602 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 00:24:03.332984 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 00:24:03.333104 extracting modules file /var/lib/lava/dispatcher/tmp/11280966/tftp-deploy-20drlgbp/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11280966/extract-overlay-ramdisk-6iz1dy0l/ramdisk
191 00:24:03.562523 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:24:03.562823 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 00:24:03.562920 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11280966/compress-overlay-6v127tgc/overlay-1.5.2.4.tar.gz to ramdisk
194 00:24:03.562990 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11280966/compress-overlay-6v127tgc/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11280966/extract-overlay-ramdisk-6iz1dy0l/ramdisk
195 00:24:03.569548 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:24:03.569661 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 00:24:03.569747 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:24:03.569833 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 00:24:03.569912 Building ramdisk /var/lib/lava/dispatcher/tmp/11280966/extract-overlay-ramdisk-6iz1dy0l/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11280966/extract-overlay-ramdisk-6iz1dy0l/ramdisk
200 00:24:04.183053 >> 227033 blocks
201 00:24:08.054411 rename /var/lib/lava/dispatcher/tmp/11280966/extract-overlay-ramdisk-6iz1dy0l/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11280966/tftp-deploy-20drlgbp/ramdisk/ramdisk.cpio.gz
202 00:24:08.054901 end: 1.5.7 compress-ramdisk (duration 00:00:04) [common]
203 00:24:08.055018 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 00:24:08.055118 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 00:24:08.055225 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11280966/tftp-deploy-20drlgbp/kernel/Image'
206 00:24:20.529606 Returned 0 in 12 seconds
207 00:24:20.630247 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11280966/tftp-deploy-20drlgbp/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11280966/tftp-deploy-20drlgbp/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11280966/tftp-deploy-20drlgbp/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11280966/tftp-deploy-20drlgbp/kernel/image.itb
208 00:24:21.246832 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:24:21.247209 output: Created: Mon Aug 14 01:24:21 2023
210 00:24:21.247282 output: Image 0 (kernel-1)
211 00:24:21.247345 output: Description:
212 00:24:21.247407 output: Created: Mon Aug 14 01:24:21 2023
213 00:24:21.247465 output: Type: Kernel Image
214 00:24:21.247521 output: Compression: lzma compressed
215 00:24:21.247579 output: Data Size: 11037315 Bytes = 10778.63 KiB = 10.53 MiB
216 00:24:21.247632 output: Architecture: AArch64
217 00:24:21.247692 output: OS: Linux
218 00:24:21.247748 output: Load Address: 0x00000000
219 00:24:21.247803 output: Entry Point: 0x00000000
220 00:24:21.247860 output: Hash algo: crc32
221 00:24:21.247914 output: Hash value: e7f77b4c
222 00:24:21.247965 output: Image 1 (fdt-1)
223 00:24:21.248016 output: Description: mt8192-asurada-spherion-r0
224 00:24:21.248066 output: Created: Mon Aug 14 01:24:21 2023
225 00:24:21.248117 output: Type: Flat Device Tree
226 00:24:21.248167 output: Compression: uncompressed
227 00:24:21.248218 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 00:24:21.248268 output: Architecture: AArch64
229 00:24:21.248318 output: Hash algo: crc32
230 00:24:21.248369 output: Hash value: cc4352de
231 00:24:21.248420 output: Image 2 (ramdisk-1)
232 00:24:21.248470 output: Description: unavailable
233 00:24:21.248521 output: Created: Mon Aug 14 01:24:21 2023
234 00:24:21.248571 output: Type: RAMDisk Image
235 00:24:21.248621 output: Compression: Unknown Compression
236 00:24:21.248671 output: Data Size: 39244568 Bytes = 38324.77 KiB = 37.43 MiB
237 00:24:21.248721 output: Architecture: AArch64
238 00:24:21.248771 output: OS: Linux
239 00:24:21.248821 output: Load Address: unavailable
240 00:24:21.248871 output: Entry Point: unavailable
241 00:24:21.248921 output: Hash algo: crc32
242 00:24:21.248970 output: Hash value: 9f8f1145
243 00:24:21.249020 output: Default Configuration: 'conf-1'
244 00:24:21.249070 output: Configuration 0 (conf-1)
245 00:24:21.249120 output: Description: mt8192-asurada-spherion-r0
246 00:24:21.249171 output: Kernel: kernel-1
247 00:24:21.249221 output: Init Ramdisk: ramdisk-1
248 00:24:21.249271 output: FDT: fdt-1
249 00:24:21.249321 output: Loadables: kernel-1
250 00:24:21.249371 output:
251 00:24:21.249571 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 00:24:21.249665 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 00:24:21.249775 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 00:24:21.249868 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 00:24:21.249945 No LXC device requested
256 00:24:21.250020 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:24:21.250103 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 00:24:21.250183 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:24:21.250251 Checking files for TFTP limit of 4294967296 bytes.
260 00:24:21.250757 end: 1 tftp-deploy (duration 00:00:20) [common]
261 00:24:21.250857 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:24:21.250945 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:24:21.251065 substitutions:
264 00:24:21.251129 - {DTB}: 11280966/tftp-deploy-20drlgbp/dtb/mt8192-asurada-spherion-r0.dtb
265 00:24:21.251191 - {INITRD}: 11280966/tftp-deploy-20drlgbp/ramdisk/ramdisk.cpio.gz
266 00:24:21.251250 - {KERNEL}: 11280966/tftp-deploy-20drlgbp/kernel/Image
267 00:24:21.251305 - {LAVA_MAC}: None
268 00:24:21.251360 - {PRESEED_CONFIG}: None
269 00:24:21.251413 - {PRESEED_LOCAL}: None
270 00:24:21.251465 - {RAMDISK}: 11280966/tftp-deploy-20drlgbp/ramdisk/ramdisk.cpio.gz
271 00:24:21.251517 - {ROOT_PART}: None
272 00:24:21.251570 - {ROOT}: None
273 00:24:21.251622 - {SERVER_IP}: 192.168.201.1
274 00:24:21.251674 - {TEE}: None
275 00:24:21.251725 Parsed boot commands:
276 00:24:21.251776 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:24:21.251953 Parsed boot commands: tftpboot 192.168.201.1 11280966/tftp-deploy-20drlgbp/kernel/image.itb 11280966/tftp-deploy-20drlgbp/kernel/cmdline
278 00:24:21.252039 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:24:21.252124 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:24:21.252213 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:24:21.252294 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:24:21.252364 Not connected, no need to disconnect.
283 00:24:21.252434 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:24:21.252510 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:24:21.252575 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 00:24:21.256534 Setting prompt string to ['lava-test: # ']
287 00:24:21.256887 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:24:21.256993 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:24:21.257090 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:24:21.257181 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:24:21.257412 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
292 00:24:26.405935 >> Command sent successfully.
293 00:24:26.416297 Returned 0 in 5 seconds
294 00:24:26.517559 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 00:24:26.520134 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 00:24:26.520762 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 00:24:26.521236 Setting prompt string to 'Starting depthcharge on Spherion...'
299 00:24:26.521572 Changing prompt to 'Starting depthcharge on Spherion...'
300 00:24:26.521904 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 00:24:26.523143 [Enter `^Ec?' for help]
302 00:24:26.681308
303 00:24:26.681848
304 00:24:26.682185 F0: 102B 0000
305 00:24:26.682490
306 00:24:26.682844 F3: 1001 0000 [0200]
307 00:24:26.683194
308 00:24:26.685020 F3: 1001 0000
309 00:24:26.685453
310 00:24:26.685777 F7: 102D 0000
311 00:24:26.686080
312 00:24:26.687987 F1: 0000 0000
313 00:24:26.688402
314 00:24:26.688722 V0: 0000 0000 [0001]
315 00:24:26.689073
316 00:24:26.691245 00: 0007 8000
317 00:24:26.691666
318 00:24:26.691991 01: 0000 0000
319 00:24:26.692302
320 00:24:26.694129 BP: 0C00 0209 [0000]
321 00:24:26.694540
322 00:24:26.694926 G0: 1182 0000
323 00:24:26.695233
324 00:24:26.698685 EC: 0000 0021 [4000]
325 00:24:26.699199
326 00:24:26.699527 S7: 0000 0000 [0000]
327 00:24:26.699832
328 00:24:26.701882 CC: 0000 0000 [0001]
329 00:24:26.702412
330 00:24:26.702810 T0: 0000 0040 [010F]
331 00:24:26.703124
332 00:24:26.703419 Jump to BL
333 00:24:26.704569
334 00:24:26.728368
335 00:24:26.728877
336 00:24:26.729239
337 00:24:26.735525 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 00:24:26.739099 ARM64: Exception handlers installed.
339 00:24:26.742855 ARM64: Testing exception
340 00:24:26.746547 ARM64: Done test exception
341 00:24:26.753583 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 00:24:26.763823 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 00:24:26.770180 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 00:24:26.780620 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 00:24:26.787301 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 00:24:26.793671 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 00:24:26.804747 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 00:24:26.811636 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 00:24:26.831190 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 00:24:26.834288 WDT: Last reset was cold boot
351 00:24:26.837848 SPI1(PAD0) initialized at 2873684 Hz
352 00:24:26.840950 SPI5(PAD0) initialized at 992727 Hz
353 00:24:26.844432 VBOOT: Loading verstage.
354 00:24:26.851059 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 00:24:26.854176 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 00:24:26.857622 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 00:24:26.861151 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 00:24:26.869104 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 00:24:26.875328 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 00:24:26.886467 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 00:24:26.887104
362 00:24:26.887475
363 00:24:26.896695 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 00:24:26.899211 ARM64: Exception handlers installed.
365 00:24:26.902646 ARM64: Testing exception
366 00:24:26.903218 ARM64: Done test exception
367 00:24:26.909257 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 00:24:26.912554 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 00:24:26.927545 Probing TPM: . done!
370 00:24:26.928102 TPM ready after 0 ms
371 00:24:26.933924 Connected to device vid:did:rid of 1ae0:0028:00
372 00:24:26.943739 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 00:24:27.009009 Initialized TPM device CR50 revision 0
374 00:24:27.021651 tlcl_send_startup: Startup return code is 0
375 00:24:27.022210 TPM: setup succeeded
376 00:24:27.032850 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 00:24:27.040966 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 00:24:27.048918 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 00:24:27.060365 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 00:24:27.064126 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 00:24:27.067531 in-header: 03 07 00 00 08 00 00 00
382 00:24:27.070365 in-data: aa e4 47 04 13 02 00 00
383 00:24:27.074168 Chrome EC: UHEPI supported
384 00:24:27.080229 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 00:24:27.083269 in-header: 03 ad 00 00 08 00 00 00
386 00:24:27.086908 in-data: 00 20 20 08 00 00 00 00
387 00:24:27.087470 Phase 1
388 00:24:27.090260 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 00:24:27.097678 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 00:24:27.103460 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 00:24:27.107004 Recovery requested (1009000e)
392 00:24:27.110753 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 00:24:27.119508 tlcl_extend: response is 0
394 00:24:27.127573 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 00:24:27.132563 tlcl_extend: response is 0
396 00:24:27.139188 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 00:24:27.159589 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 00:24:27.166569 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 00:24:27.167206
400 00:24:27.167571
401 00:24:27.177505 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 00:24:27.181045 ARM64: Exception handlers installed.
403 00:24:27.181617 ARM64: Testing exception
404 00:24:27.184047 ARM64: Done test exception
405 00:24:27.205072 pmic_efuse_setting: Set efuses in 11 msecs
406 00:24:27.208068 pmwrap_interface_init: Select PMIF_VLD_RDY
407 00:24:27.215669 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 00:24:27.218437 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 00:24:27.225527 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 00:24:27.228391 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 00:24:27.235304 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 00:24:27.238376 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 00:24:27.242294 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 00:24:27.248573 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 00:24:27.251894 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 00:24:27.258408 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 00:24:27.261580 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 00:24:27.265561 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 00:24:27.271542 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 00:24:27.278221 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 00:24:27.282527 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 00:24:27.288152 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 00:24:27.295246 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 00:24:27.298787 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 00:24:27.306526 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 00:24:27.312793 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 00:24:27.316443 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 00:24:27.323203 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 00:24:27.326620 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 00:24:27.333800 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 00:24:27.337884 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 00:24:27.344594 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 00:24:27.348956 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 00:24:27.355495 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 00:24:27.358302 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 00:24:27.365115 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 00:24:27.368285 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 00:24:27.375543 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 00:24:27.378468 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 00:24:27.385963 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 00:24:27.389763 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 00:24:27.393482 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 00:24:27.399535 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 00:24:27.402752 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 00:24:27.410162 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 00:24:27.412654 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 00:24:27.415781 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 00:24:27.423199 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 00:24:27.426083 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 00:24:27.429605 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 00:24:27.435894 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 00:24:27.439347 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 00:24:27.443641 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 00:24:27.445912 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 00:24:27.452367 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 00:24:27.456068 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 00:24:27.459261 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 00:24:27.469224 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 00:24:27.475893 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 00:24:27.482548 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 00:24:27.489022 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 00:24:27.499808 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 00:24:27.503064 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 00:24:27.506073 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:24:27.512503 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 00:24:27.519235 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x11
467 00:24:27.522172 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 00:24:27.529954 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
469 00:24:27.533096 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 00:24:27.542051 [RTC]rtc_get_frequency_meter,154: input=15, output=835
471 00:24:27.551975 [RTC]rtc_get_frequency_meter,154: input=7, output=708
472 00:24:27.561269 [RTC]rtc_get_frequency_meter,154: input=11, output=773
473 00:24:27.570979 [RTC]rtc_get_frequency_meter,154: input=13, output=803
474 00:24:27.580563 [RTC]rtc_get_frequency_meter,154: input=12, output=788
475 00:24:27.589786 [RTC]rtc_get_frequency_meter,154: input=12, output=788
476 00:24:27.599441 [RTC]rtc_get_frequency_meter,154: input=13, output=804
477 00:24:27.602507 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
478 00:24:27.610080 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
479 00:24:27.613076 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 00:24:27.616864 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 00:24:27.623003 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 00:24:27.626472 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 00:24:27.630203 ADC[4]: Raw value=904879 ID=7
484 00:24:27.630807 ADC[3]: Raw value=212912 ID=1
485 00:24:27.633152 RAM Code: 0x71
486 00:24:27.636542 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 00:24:27.642786 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 00:24:27.650185 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 00:24:27.656608 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 00:24:27.659551 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 00:24:27.663092 in-header: 03 07 00 00 08 00 00 00
492 00:24:27.666331 in-data: aa e4 47 04 13 02 00 00
493 00:24:27.669780 Chrome EC: UHEPI supported
494 00:24:27.675940 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 00:24:27.679925 in-header: 03 dd 00 00 08 00 00 00
496 00:24:27.682559 in-data: 90 20 60 08 00 00 00 00
497 00:24:27.685747 MRC: failed to locate region type 0.
498 00:24:27.692773 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 00:24:27.696920 DRAM-K: Running full calibration
500 00:24:27.702560 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 00:24:27.703240 header.status = 0x0
502 00:24:27.706371 header.version = 0x6 (expected: 0x6)
503 00:24:27.709213 header.size = 0xd00 (expected: 0xd00)
504 00:24:27.713260 header.flags = 0x0
505 00:24:27.719046 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 00:24:27.736437 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 00:24:27.743005 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 00:24:27.745731 dram_init: ddr_geometry: 2
509 00:24:27.749514 [EMI] MDL number = 2
510 00:24:27.750070 [EMI] Get MDL freq = 0
511 00:24:27.752837 dram_init: ddr_type: 0
512 00:24:27.753291 is_discrete_lpddr4: 1
513 00:24:27.755884 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 00:24:27.756296
515 00:24:27.756622
516 00:24:27.759522 [Bian_co] ETT version 0.0.0.1
517 00:24:27.765981 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 00:24:27.766538
519 00:24:27.769665 dramc_set_vcore_voltage set vcore to 650000
520 00:24:27.770181 Read voltage for 800, 4
521 00:24:27.772963 Vio18 = 0
522 00:24:27.773531 Vcore = 650000
523 00:24:27.776273 Vdram = 0
524 00:24:27.776830 Vddq = 0
525 00:24:27.777192 Vmddr = 0
526 00:24:27.779232 dram_init: config_dvfs: 1
527 00:24:27.782756 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 00:24:27.789364 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 00:24:27.792692 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
530 00:24:27.795438 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
531 00:24:27.799140 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
532 00:24:27.802873 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
533 00:24:27.806070 MEM_TYPE=3, freq_sel=18
534 00:24:27.809308 sv_algorithm_assistance_LP4_1600
535 00:24:27.812062 ============ PULL DRAM RESETB DOWN ============
536 00:24:27.818690 ========== PULL DRAM RESETB DOWN end =========
537 00:24:27.822327 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 00:24:27.825631 ===================================
539 00:24:27.828768 LPDDR4 DRAM CONFIGURATION
540 00:24:27.832268 ===================================
541 00:24:27.832783 EX_ROW_EN[0] = 0x0
542 00:24:27.835209 EX_ROW_EN[1] = 0x0
543 00:24:27.835621 LP4Y_EN = 0x0
544 00:24:27.838548 WORK_FSP = 0x0
545 00:24:27.841669 WL = 0x2
546 00:24:27.842148 RL = 0x2
547 00:24:27.845615 BL = 0x2
548 00:24:27.846128 RPST = 0x0
549 00:24:27.848626 RD_PRE = 0x0
550 00:24:27.849136 WR_PRE = 0x1
551 00:24:27.852289 WR_PST = 0x0
552 00:24:27.852816 DBI_WR = 0x0
553 00:24:27.855460 DBI_RD = 0x0
554 00:24:27.855973 OTF = 0x1
555 00:24:27.858722 ===================================
556 00:24:27.861727 ===================================
557 00:24:27.865166 ANA top config
558 00:24:27.869050 ===================================
559 00:24:27.869565 DLL_ASYNC_EN = 0
560 00:24:27.871279 ALL_SLAVE_EN = 1
561 00:24:27.874720 NEW_RANK_MODE = 1
562 00:24:27.878164 DLL_IDLE_MODE = 1
563 00:24:27.881543 LP45_APHY_COMB_EN = 1
564 00:24:27.882097 TX_ODT_DIS = 1
565 00:24:27.884860 NEW_8X_MODE = 1
566 00:24:27.888288 ===================================
567 00:24:27.891580 ===================================
568 00:24:27.894685 data_rate = 1600
569 00:24:27.898257 CKR = 1
570 00:24:27.901229 DQ_P2S_RATIO = 8
571 00:24:27.904938 ===================================
572 00:24:27.905496 CA_P2S_RATIO = 8
573 00:24:27.907894 DQ_CA_OPEN = 0
574 00:24:27.911303 DQ_SEMI_OPEN = 0
575 00:24:27.914528 CA_SEMI_OPEN = 0
576 00:24:27.918264 CA_FULL_RATE = 0
577 00:24:27.921851 DQ_CKDIV4_EN = 1
578 00:24:27.922408 CA_CKDIV4_EN = 1
579 00:24:27.924506 CA_PREDIV_EN = 0
580 00:24:27.928036 PH8_DLY = 0
581 00:24:27.930925 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 00:24:27.934441 DQ_AAMCK_DIV = 4
583 00:24:27.938002 CA_AAMCK_DIV = 4
584 00:24:27.938577 CA_ADMCK_DIV = 4
585 00:24:27.940991 DQ_TRACK_CA_EN = 0
586 00:24:27.944911 CA_PICK = 800
587 00:24:27.948082 CA_MCKIO = 800
588 00:24:27.950813 MCKIO_SEMI = 0
589 00:24:27.954066 PLL_FREQ = 3068
590 00:24:27.957843 DQ_UI_PI_RATIO = 32
591 00:24:27.961284 CA_UI_PI_RATIO = 0
592 00:24:27.961846 ===================================
593 00:24:27.964084 ===================================
594 00:24:27.967698 memory_type:LPDDR4
595 00:24:27.971256 GP_NUM : 10
596 00:24:27.971809 SRAM_EN : 1
597 00:24:27.973979 MD32_EN : 0
598 00:24:27.977395 ===================================
599 00:24:27.980664 [ANA_INIT] >>>>>>>>>>>>>>
600 00:24:27.984066 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 00:24:27.987199 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 00:24:27.991195 ===================================
603 00:24:27.991652 data_rate = 1600,PCW = 0X7600
604 00:24:27.995013 ===================================
605 00:24:27.998125 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 00:24:28.003668 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 00:24:28.010441 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 00:24:28.014158 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 00:24:28.017196 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 00:24:28.020855 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 00:24:28.023524 [ANA_INIT] flow start
612 00:24:28.027295 [ANA_INIT] PLL >>>>>>>>
613 00:24:28.027850 [ANA_INIT] PLL <<<<<<<<
614 00:24:28.030345 [ANA_INIT] MIDPI >>>>>>>>
615 00:24:28.033759 [ANA_INIT] MIDPI <<<<<<<<
616 00:24:28.034313 [ANA_INIT] DLL >>>>>>>>
617 00:24:28.037380 [ANA_INIT] flow end
618 00:24:28.040150 ============ LP4 DIFF to SE enter ============
619 00:24:28.043597 ============ LP4 DIFF to SE exit ============
620 00:24:28.047305 [ANA_INIT] <<<<<<<<<<<<<
621 00:24:28.050059 [Flow] Enable top DCM control >>>>>
622 00:24:28.054029 [Flow] Enable top DCM control <<<<<
623 00:24:28.057405 Enable DLL master slave shuffle
624 00:24:28.064038 ==============================================================
625 00:24:28.064552 Gating Mode config
626 00:24:28.069819 ==============================================================
627 00:24:28.073519 Config description:
628 00:24:28.080372 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 00:24:28.087031 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 00:24:28.093291 SELPH_MODE 0: By rank 1: By Phase
631 00:24:28.099761 ==============================================================
632 00:24:28.100305 GAT_TRACK_EN = 1
633 00:24:28.103431 RX_GATING_MODE = 2
634 00:24:28.106699 RX_GATING_TRACK_MODE = 2
635 00:24:28.109849 SELPH_MODE = 1
636 00:24:28.113094 PICG_EARLY_EN = 1
637 00:24:28.116335 VALID_LAT_VALUE = 1
638 00:24:28.123239 ==============================================================
639 00:24:28.126166 Enter into Gating configuration >>>>
640 00:24:28.129701 Exit from Gating configuration <<<<
641 00:24:28.133012 Enter into DVFS_PRE_config >>>>>
642 00:24:28.143273 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 00:24:28.147225 Exit from DVFS_PRE_config <<<<<
644 00:24:28.150488 Enter into PICG configuration >>>>
645 00:24:28.150989 Exit from PICG configuration <<<<
646 00:24:28.154293 [RX_INPUT] configuration >>>>>
647 00:24:28.158436 [RX_INPUT] configuration <<<<<
648 00:24:28.161592 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 00:24:28.169639 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 00:24:28.176744 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 00:24:28.180041 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 00:24:28.186144 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 00:24:28.193090 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 00:24:28.197299 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 00:24:28.200296 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 00:24:28.204235 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 00:24:28.211059 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 00:24:28.215571 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 00:24:28.218378 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 00:24:28.222303 ===================================
661 00:24:28.223119 LPDDR4 DRAM CONFIGURATION
662 00:24:28.226190 ===================================
663 00:24:28.229995 EX_ROW_EN[0] = 0x0
664 00:24:28.230816 EX_ROW_EN[1] = 0x0
665 00:24:28.233720 LP4Y_EN = 0x0
666 00:24:28.234378 WORK_FSP = 0x0
667 00:24:28.236742 WL = 0x2
668 00:24:28.237199 RL = 0x2
669 00:24:28.240428 BL = 0x2
670 00:24:28.240978 RPST = 0x0
671 00:24:28.243843 RD_PRE = 0x0
672 00:24:28.244373 WR_PRE = 0x1
673 00:24:28.248002 WR_PST = 0x0
674 00:24:28.248462 DBI_WR = 0x0
675 00:24:28.250677 DBI_RD = 0x0
676 00:24:28.251117 OTF = 0x1
677 00:24:28.254759 ===================================
678 00:24:28.258796 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 00:24:28.262300 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 00:24:28.269451 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 00:24:28.269984 ===================================
682 00:24:28.273448 LPDDR4 DRAM CONFIGURATION
683 00:24:28.277215 ===================================
684 00:24:28.280684 EX_ROW_EN[0] = 0x10
685 00:24:28.281185 EX_ROW_EN[1] = 0x0
686 00:24:28.283882 LP4Y_EN = 0x0
687 00:24:28.284407 WORK_FSP = 0x0
688 00:24:28.287160 WL = 0x2
689 00:24:28.287573 RL = 0x2
690 00:24:28.288087 BL = 0x2
691 00:24:28.290817 RPST = 0x0
692 00:24:28.291231 RD_PRE = 0x0
693 00:24:28.294717 WR_PRE = 0x1
694 00:24:28.295131 WR_PST = 0x0
695 00:24:28.298473 DBI_WR = 0x0
696 00:24:28.298983 DBI_RD = 0x0
697 00:24:28.302213 OTF = 0x1
698 00:24:28.305837 ===================================
699 00:24:28.308775 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 00:24:28.314694 nWR fixed to 40
701 00:24:28.318358 [ModeRegInit_LP4] CH0 RK0
702 00:24:28.318978 [ModeRegInit_LP4] CH0 RK1
703 00:24:28.321594 [ModeRegInit_LP4] CH1 RK0
704 00:24:28.324424 [ModeRegInit_LP4] CH1 RK1
705 00:24:28.324835 match AC timing 13
706 00:24:28.331239 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 00:24:28.334904 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 00:24:28.337895 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 00:24:28.344280 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 00:24:28.348030 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 00:24:28.348554 [EMI DOE] emi_dcm 0
712 00:24:28.354633 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 00:24:28.355159 ==
714 00:24:28.358049 Dram Type= 6, Freq= 0, CH_0, rank 0
715 00:24:28.361280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 00:24:28.361703 ==
717 00:24:28.368147 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 00:24:28.371220 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 00:24:28.382506 [CA 0] Center 37 (6~68) winsize 63
720 00:24:28.385182 [CA 1] Center 36 (6~67) winsize 62
721 00:24:28.388245 [CA 2] Center 34 (4~65) winsize 62
722 00:24:28.391747 [CA 3] Center 34 (4~65) winsize 62
723 00:24:28.395274 [CA 4] Center 34 (4~64) winsize 61
724 00:24:28.398340 [CA 5] Center 33 (3~64) winsize 62
725 00:24:28.398794
726 00:24:28.402505 [CmdBusTrainingLP45] Vref(ca) range 1: 30
727 00:24:28.403094
728 00:24:28.404669 [CATrainingPosCal] consider 1 rank data
729 00:24:28.408226 u2DelayCellTimex100 = 270/100 ps
730 00:24:28.411314 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
731 00:24:28.418068 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
732 00:24:28.421458 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 00:24:28.424986 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 00:24:28.428121 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
735 00:24:28.431740 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 00:24:28.432298
737 00:24:28.434998 CA PerBit enable=1, Macro0, CA PI delay=33
738 00:24:28.435719
739 00:24:28.438127 [CBTSetCACLKResult] CA Dly = 33
740 00:24:28.441528 CS Dly: 6 (0~37)
741 00:24:28.442108 ==
742 00:24:28.445233 Dram Type= 6, Freq= 0, CH_0, rank 1
743 00:24:28.448501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 00:24:28.449089 ==
745 00:24:28.451325 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 00:24:28.458034 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 00:24:28.468040 [CA 0] Center 37 (6~68) winsize 63
748 00:24:28.471414 [CA 1] Center 37 (7~67) winsize 61
749 00:24:28.474525 [CA 2] Center 34 (4~65) winsize 62
750 00:24:28.478206 [CA 3] Center 34 (4~65) winsize 62
751 00:24:28.481925 [CA 4] Center 33 (3~64) winsize 62
752 00:24:28.485824 [CA 5] Center 33 (2~64) winsize 63
753 00:24:28.486577
754 00:24:28.488705 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 00:24:28.489348
756 00:24:28.492566 [CATrainingPosCal] consider 2 rank data
757 00:24:28.496504 u2DelayCellTimex100 = 270/100 ps
758 00:24:28.500468 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
759 00:24:28.503858 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
760 00:24:28.507069 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 00:24:28.510827 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 00:24:28.514359 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
763 00:24:28.518058 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 00:24:28.518573
765 00:24:28.521017 CA PerBit enable=1, Macro0, CA PI delay=33
766 00:24:28.521525
767 00:24:28.524921 [CBTSetCACLKResult] CA Dly = 33
768 00:24:28.527337 CS Dly: 6 (0~38)
769 00:24:28.527756
770 00:24:28.531054 ----->DramcWriteLeveling(PI) begin...
771 00:24:28.531492 ==
772 00:24:28.534688 Dram Type= 6, Freq= 0, CH_0, rank 0
773 00:24:28.538103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 00:24:28.538671 ==
775 00:24:28.541232 Write leveling (Byte 0): 32 => 32
776 00:24:28.544123 Write leveling (Byte 1): 31 => 31
777 00:24:28.547696 DramcWriteLeveling(PI) end<-----
778 00:24:28.548213
779 00:24:28.548546 ==
780 00:24:28.550658 Dram Type= 6, Freq= 0, CH_0, rank 0
781 00:24:28.553865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 00:24:28.554461 ==
783 00:24:28.557235 [Gating] SW mode calibration
784 00:24:28.563770 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 00:24:28.570569 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 00:24:28.573649 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 00:24:28.577263 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 00:24:28.583509 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 00:24:28.587247 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:24:28.590353 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:24:28.597463 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:24:28.600286 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:24:28.603718 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:24:28.610408 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 00:24:28.613734 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 00:24:28.616740 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 00:24:28.623764 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 00:24:28.626716 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 00:24:28.630468 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:24:28.636574 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:24:28.640660 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:24:28.643484 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 00:24:28.650507 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 00:24:28.653545 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 00:24:28.656806 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 00:24:28.663521 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 00:24:28.667528 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 00:24:28.669855 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 00:24:28.673897 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 00:24:28.679982 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 00:24:28.683549 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 00:24:28.687246 0 9 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
813 00:24:28.693837 0 9 12 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
814 00:24:28.696449 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 00:24:28.699986 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 00:24:28.706674 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 00:24:28.710417 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 00:24:28.713594 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 00:24:28.720148 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
820 00:24:28.723548 0 10 8 | B1->B0 | 3333 2929 | 1 0 | (1 1) (1 0)
821 00:24:28.726735 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
822 00:24:28.733427 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 00:24:28.736334 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 00:24:28.739403 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 00:24:28.746332 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:24:28.749708 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 00:24:28.753979 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
828 00:24:28.757914 0 11 8 | B1->B0 | 2525 3a3a | 0 0 | (0 0) (0 0)
829 00:24:28.764565 0 11 12 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
830 00:24:28.768149 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 00:24:28.771972 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 00:24:28.775217 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 00:24:28.778812 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 00:24:28.786068 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 00:24:28.789407 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 00:24:28.793562 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 00:24:28.797077 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 00:24:28.804998 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 00:24:28.808297 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 00:24:28.812208 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 00:24:28.815088 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:24:28.818749 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:24:28.825570 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:24:28.828375 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 00:24:28.831935 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 00:24:28.838724 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 00:24:28.841707 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 00:24:28.844988 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 00:24:28.851764 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 00:24:28.855409 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 00:24:28.858629 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 00:24:28.865528 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 00:24:28.866050 Total UI for P1: 0, mck2ui 16
854 00:24:28.868690 best dqsien dly found for B0: ( 0, 14, 6)
855 00:24:28.875942 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 00:24:28.876361 Total UI for P1: 0, mck2ui 16
857 00:24:28.879504 best dqsien dly found for B1: ( 0, 14, 8)
858 00:24:28.883920 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 00:24:28.887162 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 00:24:28.887719
861 00:24:28.890311 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 00:24:28.897679 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 00:24:28.898254 [Gating] SW calibration Done
864 00:24:28.898658 ==
865 00:24:28.901005 Dram Type= 6, Freq= 0, CH_0, rank 0
866 00:24:28.907579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 00:24:28.908043 ==
868 00:24:28.908408 RX Vref Scan: 0
869 00:24:28.908745
870 00:24:28.910916 RX Vref 0 -> 0, step: 1
871 00:24:28.911375
872 00:24:28.914275 RX Delay -130 -> 252, step: 16
873 00:24:28.917512 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 00:24:28.921052 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 00:24:28.925011 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 00:24:28.927650 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 00:24:28.934974 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 00:24:28.937168 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 00:24:28.940720 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 00:24:28.944420 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
881 00:24:28.947864 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 00:24:28.954682 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
883 00:24:28.957704 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 00:24:28.960737 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 00:24:28.964187 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 00:24:28.970404 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 00:24:28.973685 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 00:24:28.977672 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
889 00:24:28.978233 ==
890 00:24:28.980664 Dram Type= 6, Freq= 0, CH_0, rank 0
891 00:24:28.984161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 00:24:28.984729 ==
893 00:24:28.987257 DQS Delay:
894 00:24:28.987719 DQS0 = 0, DQS1 = 0
895 00:24:28.990422 DQM Delay:
896 00:24:28.991018 DQM0 = 87, DQM1 = 75
897 00:24:28.991421 DQ Delay:
898 00:24:28.994077 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 00:24:28.997300 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
900 00:24:29.001175 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
901 00:24:29.003972 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =77
902 00:24:29.004437
903 00:24:29.004796
904 00:24:29.007328 ==
905 00:24:29.010304 Dram Type= 6, Freq= 0, CH_0, rank 0
906 00:24:29.013739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 00:24:29.014301 ==
908 00:24:29.014731
909 00:24:29.015093
910 00:24:29.017193 TX Vref Scan disable
911 00:24:29.017755 == TX Byte 0 ==
912 00:24:29.020288 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
913 00:24:29.027742 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
914 00:24:29.028321 == TX Byte 1 ==
915 00:24:29.030530 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
916 00:24:29.036517 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
917 00:24:29.037248 ==
918 00:24:29.040119 Dram Type= 6, Freq= 0, CH_0, rank 0
919 00:24:29.043460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 00:24:29.044014 ==
921 00:24:29.056923 TX Vref=22, minBit 13, minWin=26, winSum=442
922 00:24:29.060237 TX Vref=24, minBit 8, minWin=27, winSum=449
923 00:24:29.063264 TX Vref=26, minBit 5, minWin=27, winSum=446
924 00:24:29.066832 TX Vref=28, minBit 8, minWin=27, winSum=445
925 00:24:29.070052 TX Vref=30, minBit 8, minWin=27, winSum=447
926 00:24:29.076503 TX Vref=32, minBit 4, minWin=27, winSum=446
927 00:24:29.079723 [TxChooseVref] Worse bit 8, Min win 27, Win sum 449, Final Vref 24
928 00:24:29.080269
929 00:24:29.082901 Final TX Range 1 Vref 24
930 00:24:29.083365
931 00:24:29.083728 ==
932 00:24:29.087130 Dram Type= 6, Freq= 0, CH_0, rank 0
933 00:24:29.089972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 00:24:29.093103 ==
935 00:24:29.093618
936 00:24:29.094190
937 00:24:29.094552 TX Vref Scan disable
938 00:24:29.096741 == TX Byte 0 ==
939 00:24:29.100261 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
940 00:24:29.106293 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
941 00:24:29.106818 == TX Byte 1 ==
942 00:24:29.110055 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
943 00:24:29.116676 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
944 00:24:29.117139
945 00:24:29.117475 [DATLAT]
946 00:24:29.117786 Freq=800, CH0 RK0
947 00:24:29.118085
948 00:24:29.120139 DATLAT Default: 0xa
949 00:24:29.120557 0, 0xFFFF, sum = 0
950 00:24:29.122904 1, 0xFFFF, sum = 0
951 00:24:29.123325 2, 0xFFFF, sum = 0
952 00:24:29.126393 3, 0xFFFF, sum = 0
953 00:24:29.129874 4, 0xFFFF, sum = 0
954 00:24:29.130295 5, 0xFFFF, sum = 0
955 00:24:29.133121 6, 0xFFFF, sum = 0
956 00:24:29.133651 7, 0xFFFF, sum = 0
957 00:24:29.136699 8, 0xFFFF, sum = 0
958 00:24:29.137369 9, 0x0, sum = 1
959 00:24:29.139896 10, 0x0, sum = 2
960 00:24:29.140419 11, 0x0, sum = 3
961 00:24:29.140751 12, 0x0, sum = 4
962 00:24:29.142953 best_step = 10
963 00:24:29.143366
964 00:24:29.143691 ==
965 00:24:29.146707 Dram Type= 6, Freq= 0, CH_0, rank 0
966 00:24:29.150344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 00:24:29.150918 ==
968 00:24:29.153297 RX Vref Scan: 1
969 00:24:29.153812
970 00:24:29.156813 Set Vref Range= 32 -> 127
971 00:24:29.157346
972 00:24:29.157683 RX Vref 32 -> 127, step: 1
973 00:24:29.157989
974 00:24:29.159852 RX Delay -111 -> 252, step: 8
975 00:24:29.160268
976 00:24:29.162929 Set Vref, RX VrefLevel [Byte0]: 32
977 00:24:29.166411 [Byte1]: 32
978 00:24:29.169492
979 00:24:29.170010 Set Vref, RX VrefLevel [Byte0]: 33
980 00:24:29.173292 [Byte1]: 33
981 00:24:29.177579
982 00:24:29.178097 Set Vref, RX VrefLevel [Byte0]: 34
983 00:24:29.180525 [Byte1]: 34
984 00:24:29.185179
985 00:24:29.185696 Set Vref, RX VrefLevel [Byte0]: 35
986 00:24:29.188301 [Byte1]: 35
987 00:24:29.193093
988 00:24:29.193632 Set Vref, RX VrefLevel [Byte0]: 36
989 00:24:29.195477 [Byte1]: 36
990 00:24:29.200027
991 00:24:29.200540 Set Vref, RX VrefLevel [Byte0]: 37
992 00:24:29.203548 [Byte1]: 37
993 00:24:29.208076
994 00:24:29.208597 Set Vref, RX VrefLevel [Byte0]: 38
995 00:24:29.211001 [Byte1]: 38
996 00:24:29.215452
997 00:24:29.215862 Set Vref, RX VrefLevel [Byte0]: 39
998 00:24:29.219074 [Byte1]: 39
999 00:24:29.223042
1000 00:24:29.223559 Set Vref, RX VrefLevel [Byte0]: 40
1001 00:24:29.226337 [Byte1]: 40
1002 00:24:29.230384
1003 00:24:29.230939 Set Vref, RX VrefLevel [Byte0]: 41
1004 00:24:29.233909 [Byte1]: 41
1005 00:24:29.238690
1006 00:24:29.239104 Set Vref, RX VrefLevel [Byte0]: 42
1007 00:24:29.241789 [Byte1]: 42
1008 00:24:29.246047
1009 00:24:29.246462 Set Vref, RX VrefLevel [Byte0]: 43
1010 00:24:29.248919 [Byte1]: 43
1011 00:24:29.253757
1012 00:24:29.254274 Set Vref, RX VrefLevel [Byte0]: 44
1013 00:24:29.257051 [Byte1]: 44
1014 00:24:29.261408
1015 00:24:29.261931 Set Vref, RX VrefLevel [Byte0]: 45
1016 00:24:29.264502 [Byte1]: 45
1017 00:24:29.269255
1018 00:24:29.269799 Set Vref, RX VrefLevel [Byte0]: 46
1019 00:24:29.272721 [Byte1]: 46
1020 00:24:29.276785
1021 00:24:29.277300 Set Vref, RX VrefLevel [Byte0]: 47
1022 00:24:29.279699 [Byte1]: 47
1023 00:24:29.284093
1024 00:24:29.284612 Set Vref, RX VrefLevel [Byte0]: 48
1025 00:24:29.287514 [Byte1]: 48
1026 00:24:29.291645
1027 00:24:29.292192 Set Vref, RX VrefLevel [Byte0]: 49
1028 00:24:29.295102 [Byte1]: 49
1029 00:24:29.299724
1030 00:24:29.300276 Set Vref, RX VrefLevel [Byte0]: 50
1031 00:24:29.303249 [Byte1]: 50
1032 00:24:29.307342
1033 00:24:29.307793 Set Vref, RX VrefLevel [Byte0]: 51
1034 00:24:29.310669 [Byte1]: 51
1035 00:24:29.315206
1036 00:24:29.315751 Set Vref, RX VrefLevel [Byte0]: 52
1037 00:24:29.318946 [Byte1]: 52
1038 00:24:29.322815
1039 00:24:29.323359 Set Vref, RX VrefLevel [Byte0]: 53
1040 00:24:29.326057 [Byte1]: 53
1041 00:24:29.330115
1042 00:24:29.330569 Set Vref, RX VrefLevel [Byte0]: 54
1043 00:24:29.333976 [Byte1]: 54
1044 00:24:29.337705
1045 00:24:29.340760 Set Vref, RX VrefLevel [Byte0]: 55
1046 00:24:29.341219 [Byte1]: 55
1047 00:24:29.345901
1048 00:24:29.346323 Set Vref, RX VrefLevel [Byte0]: 56
1049 00:24:29.348798 [Byte1]: 56
1050 00:24:29.353391
1051 00:24:29.353906 Set Vref, RX VrefLevel [Byte0]: 57
1052 00:24:29.356629 [Byte1]: 57
1053 00:24:29.361074
1054 00:24:29.361688 Set Vref, RX VrefLevel [Byte0]: 58
1055 00:24:29.364386 [Byte1]: 58
1056 00:24:29.368716
1057 00:24:29.369278 Set Vref, RX VrefLevel [Byte0]: 59
1058 00:24:29.371892 [Byte1]: 59
1059 00:24:29.376228
1060 00:24:29.376735 Set Vref, RX VrefLevel [Byte0]: 60
1061 00:24:29.379346 [Byte1]: 60
1062 00:24:29.383484
1063 00:24:29.383889 Set Vref, RX VrefLevel [Byte0]: 61
1064 00:24:29.386955 [Byte1]: 61
1065 00:24:29.391356
1066 00:24:29.394680 Set Vref, RX VrefLevel [Byte0]: 62
1067 00:24:29.395096 [Byte1]: 62
1068 00:24:29.398869
1069 00:24:29.399278 Set Vref, RX VrefLevel [Byte0]: 63
1070 00:24:29.402550 [Byte1]: 63
1071 00:24:29.406947
1072 00:24:29.407446 Set Vref, RX VrefLevel [Byte0]: 64
1073 00:24:29.410357 [Byte1]: 64
1074 00:24:29.414227
1075 00:24:29.414683 Set Vref, RX VrefLevel [Byte0]: 65
1076 00:24:29.417753 [Byte1]: 65
1077 00:24:29.422000
1078 00:24:29.422412 Set Vref, RX VrefLevel [Byte0]: 66
1079 00:24:29.425387 [Byte1]: 66
1080 00:24:29.429922
1081 00:24:29.430334 Set Vref, RX VrefLevel [Byte0]: 67
1082 00:24:29.433004 [Byte1]: 67
1083 00:24:29.437506
1084 00:24:29.438058 Set Vref, RX VrefLevel [Byte0]: 68
1085 00:24:29.440933 [Byte1]: 68
1086 00:24:29.444549
1087 00:24:29.444959 Set Vref, RX VrefLevel [Byte0]: 69
1088 00:24:29.447785 [Byte1]: 69
1089 00:24:29.452569
1090 00:24:29.452979 Set Vref, RX VrefLevel [Byte0]: 70
1091 00:24:29.456101 [Byte1]: 70
1092 00:24:29.460543
1093 00:24:29.461045 Set Vref, RX VrefLevel [Byte0]: 71
1094 00:24:29.463828 [Byte1]: 71
1095 00:24:29.467709
1096 00:24:29.468118 Set Vref, RX VrefLevel [Byte0]: 72
1097 00:24:29.470965 [Byte1]: 72
1098 00:24:29.475910
1099 00:24:29.476416 Set Vref, RX VrefLevel [Byte0]: 73
1100 00:24:29.479099 [Byte1]: 73
1101 00:24:29.482986
1102 00:24:29.483526 Set Vref, RX VrefLevel [Byte0]: 74
1103 00:24:29.486847 [Byte1]: 74
1104 00:24:29.490877
1105 00:24:29.491381 Set Vref, RX VrefLevel [Byte0]: 75
1106 00:24:29.494376 [Byte1]: 75
1107 00:24:29.498368
1108 00:24:29.498857 Set Vref, RX VrefLevel [Byte0]: 76
1109 00:24:29.501950 [Byte1]: 76
1110 00:24:29.506162
1111 00:24:29.506718 Set Vref, RX VrefLevel [Byte0]: 77
1112 00:24:29.509259 [Byte1]: 77
1113 00:24:29.513420
1114 00:24:29.517188 Set Vref, RX VrefLevel [Byte0]: 78
1115 00:24:29.517718 [Byte1]: 78
1116 00:24:29.521357
1117 00:24:29.524421 Set Vref, RX VrefLevel [Byte0]: 79
1118 00:24:29.524949 [Byte1]: 79
1119 00:24:29.528632
1120 00:24:29.529168 Set Vref, RX VrefLevel [Byte0]: 80
1121 00:24:29.532215 [Byte1]: 80
1122 00:24:29.536403
1123 00:24:29.536823 Set Vref, RX VrefLevel [Byte0]: 81
1124 00:24:29.539650 [Byte1]: 81
1125 00:24:29.544897
1126 00:24:29.545422 Final RX Vref Byte 0 = 60 to rank0
1127 00:24:29.548218 Final RX Vref Byte 1 = 49 to rank0
1128 00:24:29.552181 Final RX Vref Byte 0 = 60 to rank1
1129 00:24:29.555254 Final RX Vref Byte 1 = 49 to rank1==
1130 00:24:29.558811 Dram Type= 6, Freq= 0, CH_0, rank 0
1131 00:24:29.562648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1132 00:24:29.563122 ==
1133 00:24:29.563528 DQS Delay:
1134 00:24:29.566237 DQS0 = 0, DQS1 = 0
1135 00:24:29.566803 DQM Delay:
1136 00:24:29.570414 DQM0 = 86, DQM1 = 76
1137 00:24:29.571135 DQ Delay:
1138 00:24:29.573036 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1139 00:24:29.576907 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1140 00:24:29.580620 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1141 00:24:29.584410 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1142 00:24:29.584911
1143 00:24:29.585235
1144 00:24:29.591835 [DQSOSCAuto] RK0, (LSB)MR18= 0x4425, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
1145 00:24:29.595556 CH0 RK0: MR19=606, MR18=4425
1146 00:24:29.598976 CH0_RK0: MR19=0x606, MR18=0x4425, DQSOSC=392, MR23=63, INC=96, DEC=64
1147 00:24:29.599389
1148 00:24:29.602716 ----->DramcWriteLeveling(PI) begin...
1149 00:24:29.603215 ==
1150 00:24:29.646834 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 00:24:29.647696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 00:24:29.648082 ==
1153 00:24:29.648422 Write leveling (Byte 0): 36 => 36
1154 00:24:29.648812 Write leveling (Byte 1): 31 => 31
1155 00:24:29.649144 DramcWriteLeveling(PI) end<-----
1156 00:24:29.649559
1157 00:24:29.649875 ==
1158 00:24:29.650177 Dram Type= 6, Freq= 0, CH_0, rank 1
1159 00:24:29.650481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1160 00:24:29.650821 ==
1161 00:24:29.651122 [Gating] SW mode calibration
1162 00:24:29.651513 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1163 00:24:29.651839 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1164 00:24:29.652143 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1165 00:24:29.690563 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1166 00:24:29.691499 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1167 00:24:29.691897 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 00:24:29.692243 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 00:24:29.692565 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 00:24:29.692877 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 00:24:29.693247 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 00:24:29.693747 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 00:24:29.694149 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 00:24:29.694464 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:24:29.734753 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:24:29.735316 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 00:24:29.736010 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 00:24:29.736384 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 00:24:29.736719 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 00:24:29.737035 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 00:24:29.737415 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1182 00:24:29.737741 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1183 00:24:29.738046 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 00:24:29.738387 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 00:24:29.778776 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 00:24:29.779311 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 00:24:29.779996 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 00:24:29.780367 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 00:24:29.780698 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1190 00:24:29.781012 0 9 8 | B1->B0 | 2525 2e2e | 0 1 | (0 0) (1 1)
1191 00:24:29.781387 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1192 00:24:29.781714 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 00:24:29.782022 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 00:24:29.782387 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 00:24:29.812143 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 00:24:29.812852 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 00:24:29.813747 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 00:24:29.814135 0 10 8 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (0 0)
1199 00:24:29.814475 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
1200 00:24:29.814862 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 00:24:29.815185 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 00:24:29.817044 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 00:24:29.820246 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 00:24:29.823213 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 00:24:29.826699 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1206 00:24:29.833347 0 11 8 | B1->B0 | 2f2f 3b3a | 0 1 | (0 0) (0 0)
1207 00:24:29.836505 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1208 00:24:29.839255 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 00:24:29.846797 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 00:24:29.850706 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 00:24:29.853229 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 00:24:29.859525 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 00:24:29.863232 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 00:24:29.866450 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1215 00:24:29.873368 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 00:24:29.876473 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 00:24:29.879979 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 00:24:29.886468 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 00:24:29.889891 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 00:24:29.893253 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 00:24:29.899467 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 00:24:29.902887 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 00:24:29.906537 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 00:24:29.912528 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 00:24:29.916504 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 00:24:29.920342 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 00:24:29.922947 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 00:24:29.930035 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 00:24:29.932893 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1230 00:24:29.935941 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1231 00:24:29.942384 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1232 00:24:29.946000 Total UI for P1: 0, mck2ui 16
1233 00:24:29.949836 best dqsien dly found for B0: ( 0, 14, 6)
1234 00:24:29.952997 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 00:24:29.956091 Total UI for P1: 0, mck2ui 16
1236 00:24:29.960010 best dqsien dly found for B1: ( 0, 14, 10)
1237 00:24:29.963109 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1238 00:24:29.966284 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1239 00:24:29.966887
1240 00:24:29.970020 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1241 00:24:29.972839 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1242 00:24:29.976414 [Gating] SW calibration Done
1243 00:24:29.976958 ==
1244 00:24:29.979884 Dram Type= 6, Freq= 0, CH_0, rank 1
1245 00:24:29.982996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1246 00:24:29.985983 ==
1247 00:24:29.986518 RX Vref Scan: 0
1248 00:24:29.986940
1249 00:24:29.989734 RX Vref 0 -> 0, step: 1
1250 00:24:29.990273
1251 00:24:29.992715 RX Delay -130 -> 252, step: 16
1252 00:24:29.995732 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1253 00:24:29.999293 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1254 00:24:30.002586 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1255 00:24:30.005833 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1256 00:24:30.012859 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1257 00:24:30.015682 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1258 00:24:30.019214 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1259 00:24:30.022457 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1260 00:24:30.025938 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1261 00:24:30.032414 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1262 00:24:30.036097 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1263 00:24:30.038510 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1264 00:24:30.042315 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1265 00:24:30.048746 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1266 00:24:30.051934 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1267 00:24:30.055267 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1268 00:24:30.055725 ==
1269 00:24:30.058932 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 00:24:30.061914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 00:24:30.062395 ==
1272 00:24:30.065195 DQS Delay:
1273 00:24:30.065746 DQS0 = 0, DQS1 = 0
1274 00:24:30.068736 DQM Delay:
1275 00:24:30.069295 DQM0 = 85, DQM1 = 77
1276 00:24:30.069664 DQ Delay:
1277 00:24:30.072140 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1278 00:24:30.075518 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1279 00:24:30.078641 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1280 00:24:30.082128 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1281 00:24:30.082726
1282 00:24:30.083092
1283 00:24:30.085437 ==
1284 00:24:30.085989 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 00:24:30.091801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 00:24:30.092359 ==
1287 00:24:30.092718
1288 00:24:30.093049
1289 00:24:30.094995 TX Vref Scan disable
1290 00:24:30.095609 == TX Byte 0 ==
1291 00:24:30.098211 Update DQ dly =587 (2 ,2, 11) DQ OEN =(1 ,7)
1292 00:24:30.104779 Update DQM dly =587 (2 ,2, 11) DQM OEN =(1 ,7)
1293 00:24:30.105232 == TX Byte 1 ==
1294 00:24:30.112178 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1295 00:24:30.114924 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1296 00:24:30.115337 ==
1297 00:24:30.118347 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 00:24:30.121249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 00:24:30.121662 ==
1300 00:24:30.135521 TX Vref=22, minBit 2, minWin=27, winSum=437
1301 00:24:30.139021 TX Vref=24, minBit 3, minWin=27, winSum=440
1302 00:24:30.142125 TX Vref=26, minBit 3, minWin=27, winSum=439
1303 00:24:30.145480 TX Vref=28, minBit 1, minWin=27, winSum=442
1304 00:24:30.148421 TX Vref=30, minBit 0, minWin=27, winSum=442
1305 00:24:30.155528 TX Vref=32, minBit 0, minWin=27, winSum=438
1306 00:24:30.159207 [TxChooseVref] Worse bit 1, Min win 27, Win sum 442, Final Vref 28
1307 00:24:30.159754
1308 00:24:30.162448 Final TX Range 1 Vref 28
1309 00:24:30.163033
1310 00:24:30.163386 ==
1311 00:24:30.165073 Dram Type= 6, Freq= 0, CH_0, rank 1
1312 00:24:30.168686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1313 00:24:30.169204 ==
1314 00:24:30.171788
1315 00:24:30.172294
1316 00:24:30.172658 TX Vref Scan disable
1317 00:24:30.175308 == TX Byte 0 ==
1318 00:24:30.178978 Update DQ dly =587 (2 ,2, 11) DQ OEN =(1 ,7)
1319 00:24:30.185554 Update DQM dly =587 (2 ,2, 11) DQM OEN =(1 ,7)
1320 00:24:30.186073 == TX Byte 1 ==
1321 00:24:30.188539 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1322 00:24:30.195392 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1323 00:24:30.195907
1324 00:24:30.196278 [DATLAT]
1325 00:24:30.196612 Freq=800, CH0 RK1
1326 00:24:30.196932
1327 00:24:30.198767 DATLAT Default: 0xa
1328 00:24:30.199329 0, 0xFFFF, sum = 0
1329 00:24:30.201710 1, 0xFFFF, sum = 0
1330 00:24:30.205365 2, 0xFFFF, sum = 0
1331 00:24:30.205920 3, 0xFFFF, sum = 0
1332 00:24:30.208643 4, 0xFFFF, sum = 0
1333 00:24:30.209205 5, 0xFFFF, sum = 0
1334 00:24:30.211730 6, 0xFFFF, sum = 0
1335 00:24:30.212197 7, 0xFFFF, sum = 0
1336 00:24:30.215445 8, 0xFFFF, sum = 0
1337 00:24:30.216006 9, 0x0, sum = 1
1338 00:24:30.218816 10, 0x0, sum = 2
1339 00:24:30.219370 11, 0x0, sum = 3
1340 00:24:30.219741 12, 0x0, sum = 4
1341 00:24:30.222071 best_step = 10
1342 00:24:30.222676
1343 00:24:30.223052 ==
1344 00:24:30.225038 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 00:24:30.228555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 00:24:30.229035 ==
1347 00:24:30.231527 RX Vref Scan: 0
1348 00:24:30.232030
1349 00:24:30.235540 RX Vref 0 -> 0, step: 1
1350 00:24:30.236070
1351 00:24:30.236392 RX Delay -111 -> 252, step: 8
1352 00:24:30.242317 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1353 00:24:30.245572 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1354 00:24:30.248626 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1355 00:24:30.252464 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1356 00:24:30.255494 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1357 00:24:30.262351 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1358 00:24:30.265875 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1359 00:24:30.268738 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1360 00:24:30.272322 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1361 00:24:30.275241 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1362 00:24:30.282119 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1363 00:24:30.285521 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1364 00:24:30.288353 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1365 00:24:30.291949 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1366 00:24:30.298755 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1367 00:24:30.301945 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1368 00:24:30.302418 ==
1369 00:24:30.305791 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 00:24:30.308927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 00:24:30.309528 ==
1372 00:24:30.310012 DQS Delay:
1373 00:24:30.311842 DQS0 = 0, DQS1 = 0
1374 00:24:30.312306 DQM Delay:
1375 00:24:30.315325 DQM0 = 86, DQM1 = 76
1376 00:24:30.315749 DQ Delay:
1377 00:24:30.318688 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =84
1378 00:24:30.322286 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1379 00:24:30.325466 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
1380 00:24:30.328841 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1381 00:24:30.329447
1382 00:24:30.329885
1383 00:24:30.338541 [DQSOSCAuto] RK1, (LSB)MR18= 0x460d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
1384 00:24:30.339098 CH0 RK1: MR19=606, MR18=460D
1385 00:24:30.345710 CH0_RK1: MR19=0x606, MR18=0x460D, DQSOSC=392, MR23=63, INC=96, DEC=64
1386 00:24:30.348502 [RxdqsGatingPostProcess] freq 800
1387 00:24:30.355545 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1388 00:24:30.358991 Pre-setting of DQS Precalculation
1389 00:24:30.362148 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1390 00:24:30.362707 ==
1391 00:24:30.366045 Dram Type= 6, Freq= 0, CH_1, rank 0
1392 00:24:30.368285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1393 00:24:30.372191 ==
1394 00:24:30.375066 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1395 00:24:30.381809 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1396 00:24:30.390705 [CA 0] Center 36 (6~67) winsize 62
1397 00:24:30.394026 [CA 1] Center 36 (6~67) winsize 62
1398 00:24:30.397406 [CA 2] Center 34 (4~65) winsize 62
1399 00:24:30.400546 [CA 3] Center 34 (3~65) winsize 63
1400 00:24:30.404071 [CA 4] Center 34 (4~65) winsize 62
1401 00:24:30.407190 [CA 5] Center 34 (3~65) winsize 63
1402 00:24:30.407596
1403 00:24:30.410443 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1404 00:24:30.410997
1405 00:24:30.413628 [CATrainingPosCal] consider 1 rank data
1406 00:24:30.416958 u2DelayCellTimex100 = 270/100 ps
1407 00:24:30.420594 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1408 00:24:30.427278 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1409 00:24:30.430555 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1410 00:24:30.433160 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1411 00:24:30.436523 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1412 00:24:30.440104 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1413 00:24:30.440605
1414 00:24:30.443597 CA PerBit enable=1, Macro0, CA PI delay=34
1415 00:24:30.444009
1416 00:24:30.446645 [CBTSetCACLKResult] CA Dly = 34
1417 00:24:30.450288 CS Dly: 5 (0~36)
1418 00:24:30.450859 ==
1419 00:24:30.452927 Dram Type= 6, Freq= 0, CH_1, rank 1
1420 00:24:30.457299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1421 00:24:30.457814 ==
1422 00:24:30.463280 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1423 00:24:30.466563 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1424 00:24:30.476701 [CA 0] Center 36 (6~67) winsize 62
1425 00:24:30.480421 [CA 1] Center 36 (6~67) winsize 62
1426 00:24:30.483863 [CA 2] Center 34 (4~65) winsize 62
1427 00:24:30.486848 [CA 3] Center 34 (3~65) winsize 63
1428 00:24:30.490075 [CA 4] Center 34 (4~65) winsize 62
1429 00:24:30.494008 [CA 5] Center 34 (3~65) winsize 63
1430 00:24:30.494559
1431 00:24:30.496665 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1432 00:24:30.497420
1433 00:24:30.499783 [CATrainingPosCal] consider 2 rank data
1434 00:24:30.503246 u2DelayCellTimex100 = 270/100 ps
1435 00:24:30.506342 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1436 00:24:30.513164 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1437 00:24:30.516570 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1438 00:24:30.520841 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1439 00:24:30.523066 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1440 00:24:30.526797 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1441 00:24:30.527307
1442 00:24:30.529966 CA PerBit enable=1, Macro0, CA PI delay=34
1443 00:24:30.530478
1444 00:24:30.533379 [CBTSetCACLKResult] CA Dly = 34
1445 00:24:30.533896 CS Dly: 5 (0~37)
1446 00:24:30.536302
1447 00:24:30.539321 ----->DramcWriteLeveling(PI) begin...
1448 00:24:30.539737 ==
1449 00:24:30.542833 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 00:24:30.546261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 00:24:30.546811 ==
1452 00:24:30.549135 Write leveling (Byte 0): 26 => 26
1453 00:24:30.552652 Write leveling (Byte 1): 26 => 26
1454 00:24:30.556641 DramcWriteLeveling(PI) end<-----
1455 00:24:30.557155
1456 00:24:30.557481 ==
1457 00:24:30.559439 Dram Type= 6, Freq= 0, CH_1, rank 0
1458 00:24:30.562823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1459 00:24:30.563358 ==
1460 00:24:30.565987 [Gating] SW mode calibration
1461 00:24:30.572422 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1462 00:24:30.578963 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1463 00:24:30.582582 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1464 00:24:30.585988 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1465 00:24:30.592805 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1466 00:24:30.595539 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 00:24:30.599015 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 00:24:30.605442 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 00:24:30.609117 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 00:24:30.612931 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 00:24:30.618499 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 00:24:30.622480 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 00:24:30.625071 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 00:24:30.631689 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 00:24:30.635228 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 00:24:30.638351 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 00:24:30.645332 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 00:24:30.648438 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 00:24:30.651982 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1480 00:24:30.658672 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1481 00:24:30.661440 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1482 00:24:30.665158 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 00:24:30.671363 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 00:24:30.674702 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 00:24:30.678132 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 00:24:30.685012 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 00:24:30.687877 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 00:24:30.691221 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1489 00:24:30.697977 0 9 8 | B1->B0 | 2d2d 302f | 0 1 | (0 0) (0 0)
1490 00:24:30.701125 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 00:24:30.704901 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 00:24:30.711865 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 00:24:30.714994 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 00:24:30.718165 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 00:24:30.724742 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 00:24:30.727849 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (0 0) (1 0)
1497 00:24:30.731652 0 10 8 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
1498 00:24:30.737870 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 00:24:30.740878 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 00:24:30.744200 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 00:24:30.747561 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 00:24:30.754145 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 00:24:30.757243 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 00:24:30.760376 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1505 00:24:30.767498 0 11 8 | B1->B0 | 3e3e 3d3d | 0 0 | (0 0) (0 0)
1506 00:24:30.770831 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 00:24:30.773862 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 00:24:30.780659 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 00:24:30.783858 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 00:24:30.787236 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 00:24:30.794229 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 00:24:30.797727 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1513 00:24:30.801209 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1514 00:24:30.807696 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 00:24:30.811200 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 00:24:30.814116 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 00:24:30.820528 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 00:24:30.823798 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 00:24:30.827262 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 00:24:30.834127 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 00:24:30.837542 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 00:24:30.840445 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 00:24:30.847537 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 00:24:30.850719 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 00:24:30.854475 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 00:24:30.860687 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 00:24:30.863956 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 00:24:30.867165 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1529 00:24:30.874419 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1530 00:24:30.874986 Total UI for P1: 0, mck2ui 16
1531 00:24:30.877817 best dqsien dly found for B0: ( 0, 14, 4)
1532 00:24:30.884860 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 00:24:30.887681 Total UI for P1: 0, mck2ui 16
1534 00:24:30.890478 best dqsien dly found for B1: ( 0, 14, 8)
1535 00:24:30.894475 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1536 00:24:30.897550 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1537 00:24:30.898062
1538 00:24:30.900739 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1539 00:24:30.904143 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1540 00:24:30.907208 [Gating] SW calibration Done
1541 00:24:30.907721 ==
1542 00:24:30.910320 Dram Type= 6, Freq= 0, CH_1, rank 0
1543 00:24:30.913503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1544 00:24:30.913977 ==
1545 00:24:30.916293 RX Vref Scan: 0
1546 00:24:30.916380
1547 00:24:30.919860 RX Vref 0 -> 0, step: 1
1548 00:24:30.919940
1549 00:24:30.920002 RX Delay -130 -> 252, step: 16
1550 00:24:30.926104 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1551 00:24:30.930103 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1552 00:24:30.932962 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1553 00:24:30.936489 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1554 00:24:30.939502 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1555 00:24:30.946117 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1556 00:24:30.949253 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1557 00:24:30.952865 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1558 00:24:30.956515 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1559 00:24:30.960121 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1560 00:24:30.966364 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1561 00:24:30.969539 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1562 00:24:30.972769 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1563 00:24:30.976369 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1564 00:24:30.982762 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1565 00:24:30.986668 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1566 00:24:30.986749 ==
1567 00:24:30.989261 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 00:24:30.992828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 00:24:30.992915 ==
1570 00:24:30.995779 DQS Delay:
1571 00:24:30.995891 DQS0 = 0, DQS1 = 0
1572 00:24:30.996008 DQM Delay:
1573 00:24:30.999054 DQM0 = 89, DQM1 = 78
1574 00:24:30.999174 DQ Delay:
1575 00:24:31.002950 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1576 00:24:31.006333 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1577 00:24:31.009466 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1578 00:24:31.013581 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1579 00:24:31.013776
1580 00:24:31.013876
1581 00:24:31.013965 ==
1582 00:24:31.016074 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 00:24:31.023131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 00:24:31.023357 ==
1585 00:24:31.023487
1586 00:24:31.023600
1587 00:24:31.023706 TX Vref Scan disable
1588 00:24:31.026140 == TX Byte 0 ==
1589 00:24:31.029576 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1590 00:24:31.036384 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1591 00:24:31.036705 == TX Byte 1 ==
1592 00:24:31.039835 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1593 00:24:31.046299 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1594 00:24:31.046813 ==
1595 00:24:31.050003 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 00:24:31.053406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 00:24:31.053811 ==
1598 00:24:31.065462 TX Vref=22, minBit 8, minWin=27, winSum=445
1599 00:24:31.069026 TX Vref=24, minBit 0, minWin=27, winSum=449
1600 00:24:31.072027 TX Vref=26, minBit 13, minWin=27, winSum=448
1601 00:24:31.075235 TX Vref=28, minBit 13, minWin=27, winSum=450
1602 00:24:31.079352 TX Vref=30, minBit 13, minWin=27, winSum=452
1603 00:24:31.085264 TX Vref=32, minBit 8, minWin=27, winSum=447
1604 00:24:31.089001 [TxChooseVref] Worse bit 13, Min win 27, Win sum 452, Final Vref 30
1605 00:24:31.089505
1606 00:24:31.092476 Final TX Range 1 Vref 30
1607 00:24:31.092987
1608 00:24:31.093308 ==
1609 00:24:31.095722 Dram Type= 6, Freq= 0, CH_1, rank 0
1610 00:24:31.098559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1611 00:24:31.102717 ==
1612 00:24:31.103387
1613 00:24:31.103716
1614 00:24:31.104010 TX Vref Scan disable
1615 00:24:31.105505 == TX Byte 0 ==
1616 00:24:31.108962 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1617 00:24:31.115833 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1618 00:24:31.116355 == TX Byte 1 ==
1619 00:24:31.118915 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1620 00:24:31.126003 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1621 00:24:31.126505
1622 00:24:31.126894 [DATLAT]
1623 00:24:31.127198 Freq=800, CH1 RK0
1624 00:24:31.127487
1625 00:24:31.129381 DATLAT Default: 0xa
1626 00:24:31.129884 0, 0xFFFF, sum = 0
1627 00:24:31.132145 1, 0xFFFF, sum = 0
1628 00:24:31.132601 2, 0xFFFF, sum = 0
1629 00:24:31.135738 3, 0xFFFF, sum = 0
1630 00:24:31.139051 4, 0xFFFF, sum = 0
1631 00:24:31.139465 5, 0xFFFF, sum = 0
1632 00:24:31.142405 6, 0xFFFF, sum = 0
1633 00:24:31.142908 7, 0xFFFF, sum = 0
1634 00:24:31.145657 8, 0xFFFF, sum = 0
1635 00:24:31.146190 9, 0x0, sum = 1
1636 00:24:31.146524 10, 0x0, sum = 2
1637 00:24:31.148868 11, 0x0, sum = 3
1638 00:24:31.149281 12, 0x0, sum = 4
1639 00:24:31.151891 best_step = 10
1640 00:24:31.152388
1641 00:24:31.152713 ==
1642 00:24:31.155353 Dram Type= 6, Freq= 0, CH_1, rank 0
1643 00:24:31.158983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1644 00:24:31.159393 ==
1645 00:24:31.162144 RX Vref Scan: 1
1646 00:24:31.162699
1647 00:24:31.163090 Set Vref Range= 32 -> 127
1648 00:24:31.165541
1649 00:24:31.165972 RX Vref 32 -> 127, step: 1
1650 00:24:31.166431
1651 00:24:31.168901 RX Delay -95 -> 252, step: 8
1652 00:24:31.169420
1653 00:24:31.172323 Set Vref, RX VrefLevel [Byte0]: 32
1654 00:24:31.175274 [Byte1]: 32
1655 00:24:31.175784
1656 00:24:31.178429 Set Vref, RX VrefLevel [Byte0]: 33
1657 00:24:31.181742 [Byte1]: 33
1658 00:24:31.186222
1659 00:24:31.186780 Set Vref, RX VrefLevel [Byte0]: 34
1660 00:24:31.189247 [Byte1]: 34
1661 00:24:31.193319
1662 00:24:31.193802 Set Vref, RX VrefLevel [Byte0]: 35
1663 00:24:31.196922 [Byte1]: 35
1664 00:24:31.201075
1665 00:24:31.201479 Set Vref, RX VrefLevel [Byte0]: 36
1666 00:24:31.204291 [Byte1]: 36
1667 00:24:31.208811
1668 00:24:31.209239 Set Vref, RX VrefLevel [Byte0]: 37
1669 00:24:31.212165 [Byte1]: 37
1670 00:24:31.216359
1671 00:24:31.216762 Set Vref, RX VrefLevel [Byte0]: 38
1672 00:24:31.220126 [Byte1]: 38
1673 00:24:31.223911
1674 00:24:31.224316 Set Vref, RX VrefLevel [Byte0]: 39
1675 00:24:31.227316 [Byte1]: 39
1676 00:24:31.232223
1677 00:24:31.232656 Set Vref, RX VrefLevel [Byte0]: 40
1678 00:24:31.234956 [Byte1]: 40
1679 00:24:31.238784
1680 00:24:31.239231 Set Vref, RX VrefLevel [Byte0]: 41
1681 00:24:31.242118 [Byte1]: 41
1682 00:24:31.246714
1683 00:24:31.247119 Set Vref, RX VrefLevel [Byte0]: 42
1684 00:24:31.250344 [Byte1]: 42
1685 00:24:31.254561
1686 00:24:31.255000 Set Vref, RX VrefLevel [Byte0]: 43
1687 00:24:31.257607 [Byte1]: 43
1688 00:24:31.262278
1689 00:24:31.262713 Set Vref, RX VrefLevel [Byte0]: 44
1690 00:24:31.265084 [Byte1]: 44
1691 00:24:31.269732
1692 00:24:31.270140 Set Vref, RX VrefLevel [Byte0]: 45
1693 00:24:31.272829 [Byte1]: 45
1694 00:24:31.276665
1695 00:24:31.276744 Set Vref, RX VrefLevel [Byte0]: 46
1696 00:24:31.280027 [Byte1]: 46
1697 00:24:31.284242
1698 00:24:31.284320 Set Vref, RX VrefLevel [Byte0]: 47
1699 00:24:31.287837 [Byte1]: 47
1700 00:24:31.291700
1701 00:24:31.291778 Set Vref, RX VrefLevel [Byte0]: 48
1702 00:24:31.295089 [Byte1]: 48
1703 00:24:31.299560
1704 00:24:31.299638 Set Vref, RX VrefLevel [Byte0]: 49
1705 00:24:31.303226 [Byte1]: 49
1706 00:24:31.306945
1707 00:24:31.307023 Set Vref, RX VrefLevel [Byte0]: 50
1708 00:24:31.310425 [Byte1]: 50
1709 00:24:31.314694
1710 00:24:31.314773 Set Vref, RX VrefLevel [Byte0]: 51
1711 00:24:31.317838 [Byte1]: 51
1712 00:24:31.322187
1713 00:24:31.322266 Set Vref, RX VrefLevel [Byte0]: 52
1714 00:24:31.325451 [Byte1]: 52
1715 00:24:31.329997
1716 00:24:31.330077 Set Vref, RX VrefLevel [Byte0]: 53
1717 00:24:31.333561 [Byte1]: 53
1718 00:24:31.337702
1719 00:24:31.337787 Set Vref, RX VrefLevel [Byte0]: 54
1720 00:24:31.341048 [Byte1]: 54
1721 00:24:31.345129
1722 00:24:31.345219 Set Vref, RX VrefLevel [Byte0]: 55
1723 00:24:31.349404 [Byte1]: 55
1724 00:24:31.352975
1725 00:24:31.353378 Set Vref, RX VrefLevel [Byte0]: 56
1726 00:24:31.356567 [Byte1]: 56
1727 00:24:31.360770
1728 00:24:31.361172 Set Vref, RX VrefLevel [Byte0]: 57
1729 00:24:31.363994 [Byte1]: 57
1730 00:24:31.368134
1731 00:24:31.368592 Set Vref, RX VrefLevel [Byte0]: 58
1732 00:24:31.371466 [Byte1]: 58
1733 00:24:31.376301
1734 00:24:31.376743 Set Vref, RX VrefLevel [Byte0]: 59
1735 00:24:31.379247 [Byte1]: 59
1736 00:24:31.383247
1737 00:24:31.383326 Set Vref, RX VrefLevel [Byte0]: 60
1738 00:24:31.386176 [Byte1]: 60
1739 00:24:31.391050
1740 00:24:31.391129 Set Vref, RX VrefLevel [Byte0]: 61
1741 00:24:31.394385 [Byte1]: 61
1742 00:24:31.398294
1743 00:24:31.398378 Set Vref, RX VrefLevel [Byte0]: 62
1744 00:24:31.401529 [Byte1]: 62
1745 00:24:31.405677
1746 00:24:31.405783 Set Vref, RX VrefLevel [Byte0]: 63
1747 00:24:31.409213 [Byte1]: 63
1748 00:24:31.413376
1749 00:24:31.413474 Set Vref, RX VrefLevel [Byte0]: 64
1750 00:24:31.417106 [Byte1]: 64
1751 00:24:31.421849
1752 00:24:31.421928 Set Vref, RX VrefLevel [Byte0]: 65
1753 00:24:31.424476 [Byte1]: 65
1754 00:24:31.428454
1755 00:24:31.428533 Set Vref, RX VrefLevel [Byte0]: 66
1756 00:24:31.431913 [Byte1]: 66
1757 00:24:31.436264
1758 00:24:31.436342 Set Vref, RX VrefLevel [Byte0]: 67
1759 00:24:31.439490 [Byte1]: 67
1760 00:24:31.444149
1761 00:24:31.444228 Set Vref, RX VrefLevel [Byte0]: 68
1762 00:24:31.446920 [Byte1]: 68
1763 00:24:31.451432
1764 00:24:31.451511 Set Vref, RX VrefLevel [Byte0]: 69
1765 00:24:31.455341 [Byte1]: 69
1766 00:24:31.460167
1767 00:24:31.460245 Set Vref, RX VrefLevel [Byte0]: 70
1768 00:24:31.462461 [Byte1]: 70
1769 00:24:31.466543
1770 00:24:31.466656 Set Vref, RX VrefLevel [Byte0]: 71
1771 00:24:31.469964 [Byte1]: 71
1772 00:24:31.474200
1773 00:24:31.474278 Set Vref, RX VrefLevel [Byte0]: 72
1774 00:24:31.477263 [Byte1]: 72
1775 00:24:31.482079
1776 00:24:31.482157 Final RX Vref Byte 0 = 56 to rank0
1777 00:24:31.485182 Final RX Vref Byte 1 = 63 to rank0
1778 00:24:31.488442 Final RX Vref Byte 0 = 56 to rank1
1779 00:24:31.491896 Final RX Vref Byte 1 = 63 to rank1==
1780 00:24:31.494800 Dram Type= 6, Freq= 0, CH_1, rank 0
1781 00:24:31.501811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1782 00:24:31.501890 ==
1783 00:24:31.501952 DQS Delay:
1784 00:24:31.505079 DQS0 = 0, DQS1 = 0
1785 00:24:31.505160 DQM Delay:
1786 00:24:31.505223 DQM0 = 87, DQM1 = 79
1787 00:24:31.508186 DQ Delay:
1788 00:24:31.511692 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1789 00:24:31.515267 DQ4 =84, DQ5 =100, DQ6 =100, DQ7 =80
1790 00:24:31.518222 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1791 00:24:31.521447 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1792 00:24:31.521527
1793 00:24:31.521589
1794 00:24:31.528715 [DQSOSCAuto] RK0, (LSB)MR18= 0x331f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1795 00:24:31.531944 CH1 RK0: MR19=606, MR18=331F
1796 00:24:31.538260 CH1_RK0: MR19=0x606, MR18=0x331F, DQSOSC=396, MR23=63, INC=94, DEC=62
1797 00:24:31.538349
1798 00:24:31.541301 ----->DramcWriteLeveling(PI) begin...
1799 00:24:31.541380 ==
1800 00:24:31.545065 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 00:24:31.548694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 00:24:31.548795 ==
1803 00:24:31.551516 Write leveling (Byte 0): 26 => 26
1804 00:24:31.554771 Write leveling (Byte 1): 29 => 29
1805 00:24:31.558090 DramcWriteLeveling(PI) end<-----
1806 00:24:31.558174
1807 00:24:31.558239 ==
1808 00:24:31.561877 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 00:24:31.565343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 00:24:31.565512 ==
1811 00:24:31.568032 [Gating] SW mode calibration
1812 00:24:31.574970 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1813 00:24:31.581751 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1814 00:24:31.584890 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1815 00:24:31.592278 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1816 00:24:31.594869 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1817 00:24:31.598449 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 00:24:31.604675 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 00:24:31.608877 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 00:24:31.611770 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 00:24:31.615221 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 00:24:31.621987 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 00:24:31.624873 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 00:24:31.628437 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 00:24:31.634538 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 00:24:31.638681 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 00:24:31.641765 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 00:24:31.648544 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 00:24:31.651501 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 00:24:31.654729 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1831 00:24:31.661687 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1832 00:24:31.665071 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 00:24:31.667831 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 00:24:31.674535 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 00:24:31.678306 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 00:24:31.682472 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 00:24:31.688210 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 00:24:31.691517 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 00:24:31.694395 0 9 4 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
1840 00:24:31.700994 0 9 8 | B1->B0 | 3434 2525 | 0 1 | (0 0) (1 1)
1841 00:24:31.704541 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1842 00:24:31.707587 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 00:24:31.714835 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 00:24:31.718003 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 00:24:31.722019 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 00:24:31.727512 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 00:24:31.730887 0 10 4 | B1->B0 | 3232 3333 | 1 1 | (1 0) (0 1)
1848 00:24:31.734357 0 10 8 | B1->B0 | 2626 2e2e | 0 1 | (0 0) (1 0)
1849 00:24:31.741626 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 00:24:31.744441 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 00:24:31.747538 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 00:24:31.754432 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 00:24:31.757754 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 00:24:31.761111 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 00:24:31.767358 0 11 4 | B1->B0 | 2424 2727 | 1 0 | (0 0) (0 0)
1856 00:24:31.770736 0 11 8 | B1->B0 | 4040 3535 | 0 0 | (1 1) (0 0)
1857 00:24:31.773984 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 00:24:31.780668 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 00:24:31.784408 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 00:24:31.787129 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 00:24:31.793751 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 00:24:31.797496 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 00:24:31.800349 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 00:24:31.807194 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1865 00:24:31.810490 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 00:24:31.814302 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 00:24:31.817269 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 00:24:31.823708 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 00:24:31.826951 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 00:24:31.830748 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 00:24:31.837415 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 00:24:31.840217 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 00:24:31.843661 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 00:24:31.850967 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 00:24:31.853644 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 00:24:31.857218 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 00:24:31.864032 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 00:24:31.867548 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 00:24:31.869882 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1880 00:24:31.876527 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1881 00:24:31.880842 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 00:24:31.883064 Total UI for P1: 0, mck2ui 16
1883 00:24:31.886496 best dqsien dly found for B0: ( 0, 14, 6)
1884 00:24:31.889857 Total UI for P1: 0, mck2ui 16
1885 00:24:31.893571 best dqsien dly found for B1: ( 0, 14, 6)
1886 00:24:31.896404 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1887 00:24:31.899757 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1888 00:24:31.900249
1889 00:24:31.903030 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1890 00:24:31.907029 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1891 00:24:31.909798 [Gating] SW calibration Done
1892 00:24:31.910203 ==
1893 00:24:31.913359 Dram Type= 6, Freq= 0, CH_1, rank 1
1894 00:24:31.919567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1895 00:24:31.919974 ==
1896 00:24:31.920294 RX Vref Scan: 0
1897 00:24:31.920607
1898 00:24:31.922823 RX Vref 0 -> 0, step: 1
1899 00:24:31.923227
1900 00:24:31.926048 RX Delay -130 -> 252, step: 16
1901 00:24:31.929374 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1902 00:24:31.932590 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1903 00:24:31.935995 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1904 00:24:31.939399 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1905 00:24:31.945803 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1906 00:24:31.949586 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1907 00:24:31.952619 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1908 00:24:31.956000 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1909 00:24:31.962729 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1910 00:24:31.966055 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1911 00:24:31.969271 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1912 00:24:31.972410 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1913 00:24:31.976023 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1914 00:24:31.982573 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1915 00:24:31.985995 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1916 00:24:31.988857 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1917 00:24:31.989344 ==
1918 00:24:31.992532 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 00:24:31.995510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 00:24:31.996014 ==
1921 00:24:31.998937 DQS Delay:
1922 00:24:31.999425 DQS0 = 0, DQS1 = 0
1923 00:24:32.002086 DQM Delay:
1924 00:24:32.002497 DQM0 = 86, DQM1 = 78
1925 00:24:32.002899 DQ Delay:
1926 00:24:32.005526 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1927 00:24:32.008800 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1928 00:24:32.012370 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1929 00:24:32.015535 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1930 00:24:32.016084
1931 00:24:32.018823
1932 00:24:32.019304 ==
1933 00:24:32.021826 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 00:24:32.025539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 00:24:32.025960 ==
1936 00:24:32.026385
1937 00:24:32.026895
1938 00:24:32.028852 TX Vref Scan disable
1939 00:24:32.029263 == TX Byte 0 ==
1940 00:24:32.035640 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1941 00:24:32.039241 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1942 00:24:32.039655 == TX Byte 1 ==
1943 00:24:32.045386 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1944 00:24:32.048647 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1945 00:24:32.049174 ==
1946 00:24:32.052086 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 00:24:32.056039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 00:24:32.056628 ==
1949 00:24:32.068766 TX Vref=22, minBit 9, minWin=26, winSum=441
1950 00:24:32.072146 TX Vref=24, minBit 1, minWin=27, winSum=444
1951 00:24:32.075323 TX Vref=26, minBit 1, minWin=27, winSum=448
1952 00:24:32.079228 TX Vref=28, minBit 13, minWin=27, winSum=451
1953 00:24:32.082334 TX Vref=30, minBit 8, minWin=27, winSum=451
1954 00:24:32.088850 TX Vref=32, minBit 8, minWin=27, winSum=446
1955 00:24:32.091613 [TxChooseVref] Worse bit 13, Min win 27, Win sum 451, Final Vref 28
1956 00:24:32.094909
1957 00:24:32.095455 Final TX Range 1 Vref 28
1958 00:24:32.096002
1959 00:24:32.096503 ==
1960 00:24:32.098306 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 00:24:32.104868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 00:24:32.105199 ==
1963 00:24:32.105467
1964 00:24:32.105708
1965 00:24:32.105940 TX Vref Scan disable
1966 00:24:32.108747 == TX Byte 0 ==
1967 00:24:32.112561 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1968 00:24:32.119393 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1969 00:24:32.119771 == TX Byte 1 ==
1970 00:24:32.122521 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1971 00:24:32.128495 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1972 00:24:32.128600
1973 00:24:32.128689 [DATLAT]
1974 00:24:32.128774 Freq=800, CH1 RK1
1975 00:24:32.128863
1976 00:24:32.131781 DATLAT Default: 0xa
1977 00:24:32.131888 0, 0xFFFF, sum = 0
1978 00:24:32.135508 1, 0xFFFF, sum = 0
1979 00:24:32.135588 2, 0xFFFF, sum = 0
1980 00:24:32.138873 3, 0xFFFF, sum = 0
1981 00:24:32.141764 4, 0xFFFF, sum = 0
1982 00:24:32.141839 5, 0xFFFF, sum = 0
1983 00:24:32.145316 6, 0xFFFF, sum = 0
1984 00:24:32.145420 7, 0xFFFF, sum = 0
1985 00:24:32.148301 8, 0xFFFF, sum = 0
1986 00:24:32.148406 9, 0x0, sum = 1
1987 00:24:32.152178 10, 0x0, sum = 2
1988 00:24:32.152272 11, 0x0, sum = 3
1989 00:24:32.152368 12, 0x0, sum = 4
1990 00:24:32.155217 best_step = 10
1991 00:24:32.155318
1992 00:24:32.155389 ==
1993 00:24:32.158611 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 00:24:32.161436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 00:24:32.161542 ==
1996 00:24:32.165097 RX Vref Scan: 0
1997 00:24:32.165205
1998 00:24:32.165301 RX Vref 0 -> 0, step: 1
1999 00:24:32.168958
2000 00:24:32.169061 RX Delay -95 -> 252, step: 8
2001 00:24:32.175208 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2002 00:24:32.178716 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2003 00:24:32.182297 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2004 00:24:32.185300 iDelay=217, Bit 3, Center 88 (-23 ~ 200) 224
2005 00:24:32.188673 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2006 00:24:32.195188 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2007 00:24:32.198679 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2008 00:24:32.201796 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2009 00:24:32.205236 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2010 00:24:32.208729 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2011 00:24:32.215289 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2012 00:24:32.218896 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2013 00:24:32.221745 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2014 00:24:32.225971 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2015 00:24:32.231932 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2016 00:24:32.235358 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2017 00:24:32.235465 ==
2018 00:24:32.238495 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 00:24:32.242200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 00:24:32.242651 ==
2021 00:24:32.243126 DQS Delay:
2022 00:24:32.245518 DQS0 = 0, DQS1 = 0
2023 00:24:32.245918 DQM Delay:
2024 00:24:32.248925 DQM0 = 88, DQM1 = 78
2025 00:24:32.249329 DQ Delay:
2026 00:24:32.252450 DQ0 =92, DQ1 =80, DQ2 =80, DQ3 =88
2027 00:24:32.255606 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2028 00:24:32.259121 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =68
2029 00:24:32.262225 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2030 00:24:32.262783
2031 00:24:32.263117
2032 00:24:32.272585 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2033 00:24:32.273176 CH1 RK1: MR19=606, MR18=1B13
2034 00:24:32.278903 CH1_RK1: MR19=0x606, MR18=0x1B13, DQSOSC=403, MR23=63, INC=90, DEC=60
2035 00:24:32.282428 [RxdqsGatingPostProcess] freq 800
2036 00:24:32.288626 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2037 00:24:32.292129 Pre-setting of DQS Precalculation
2038 00:24:32.295412 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2039 00:24:32.302046 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2040 00:24:32.311656 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2041 00:24:32.312244
2042 00:24:32.312701
2043 00:24:32.315577 [Calibration Summary] 1600 Mbps
2044 00:24:32.316067 CH 0, Rank 0
2045 00:24:32.318485 SW Impedance : PASS
2046 00:24:32.319087 DUTY Scan : NO K
2047 00:24:32.322013 ZQ Calibration : PASS
2048 00:24:32.325254 Jitter Meter : NO K
2049 00:24:32.325667 CBT Training : PASS
2050 00:24:32.328848 Write leveling : PASS
2051 00:24:32.329356 RX DQS gating : PASS
2052 00:24:32.331668 RX DQ/DQS(RDDQC) : PASS
2053 00:24:32.335589 TX DQ/DQS : PASS
2054 00:24:32.336000 RX DATLAT : PASS
2055 00:24:32.338346 RX DQ/DQS(Engine): PASS
2056 00:24:32.342096 TX OE : NO K
2057 00:24:32.342636 All Pass.
2058 00:24:32.343162
2059 00:24:32.343483 CH 0, Rank 1
2060 00:24:32.345086 SW Impedance : PASS
2061 00:24:32.348424 DUTY Scan : NO K
2062 00:24:32.348833 ZQ Calibration : PASS
2063 00:24:32.352005 Jitter Meter : NO K
2064 00:24:32.354916 CBT Training : PASS
2065 00:24:32.355324 Write leveling : PASS
2066 00:24:32.358093 RX DQS gating : PASS
2067 00:24:32.361699 RX DQ/DQS(RDDQC) : PASS
2068 00:24:32.362136 TX DQ/DQS : PASS
2069 00:24:32.364766 RX DATLAT : PASS
2070 00:24:32.368419 RX DQ/DQS(Engine): PASS
2071 00:24:32.368829 TX OE : NO K
2072 00:24:32.371409 All Pass.
2073 00:24:32.371841
2074 00:24:32.372161 CH 1, Rank 0
2075 00:24:32.375084 SW Impedance : PASS
2076 00:24:32.375645 DUTY Scan : NO K
2077 00:24:32.378219 ZQ Calibration : PASS
2078 00:24:32.381670 Jitter Meter : NO K
2079 00:24:32.382216 CBT Training : PASS
2080 00:24:32.384767 Write leveling : PASS
2081 00:24:32.385189 RX DQS gating : PASS
2082 00:24:32.388380 RX DQ/DQS(RDDQC) : PASS
2083 00:24:32.391686 TX DQ/DQS : PASS
2084 00:24:32.392096 RX DATLAT : PASS
2085 00:24:32.394689 RX DQ/DQS(Engine): PASS
2086 00:24:32.398654 TX OE : NO K
2087 00:24:32.399189 All Pass.
2088 00:24:32.399584
2089 00:24:32.399891 CH 1, Rank 1
2090 00:24:32.401280 SW Impedance : PASS
2091 00:24:32.404407 DUTY Scan : NO K
2092 00:24:32.405048 ZQ Calibration : PASS
2093 00:24:32.407785 Jitter Meter : NO K
2094 00:24:32.411230 CBT Training : PASS
2095 00:24:32.411674 Write leveling : PASS
2096 00:24:32.414711 RX DQS gating : PASS
2097 00:24:32.417589 RX DQ/DQS(RDDQC) : PASS
2098 00:24:32.418010 TX DQ/DQS : PASS
2099 00:24:32.421683 RX DATLAT : PASS
2100 00:24:32.424756 RX DQ/DQS(Engine): PASS
2101 00:24:32.425434 TX OE : NO K
2102 00:24:32.427809 All Pass.
2103 00:24:32.428222
2104 00:24:32.428734 DramC Write-DBI off
2105 00:24:32.431030 PER_BANK_REFRESH: Hybrid Mode
2106 00:24:32.431505 TX_TRACKING: ON
2107 00:24:32.434634 [GetDramInforAfterCalByMRR] Vendor 6.
2108 00:24:32.441047 [GetDramInforAfterCalByMRR] Revision 606.
2109 00:24:32.444531 [GetDramInforAfterCalByMRR] Revision 2 0.
2110 00:24:32.445074 MR0 0x3b3b
2111 00:24:32.445406 MR8 0x5151
2112 00:24:32.447653 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2113 00:24:32.448064
2114 00:24:32.451015 MR0 0x3b3b
2115 00:24:32.451422 MR8 0x5151
2116 00:24:32.454798 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2117 00:24:32.455205
2118 00:24:32.464421 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2119 00:24:32.468139 [FAST_K] Save calibration result to emmc
2120 00:24:32.471236 [FAST_K] Save calibration result to emmc
2121 00:24:32.474411 dram_init: config_dvfs: 1
2122 00:24:32.477815 dramc_set_vcore_voltage set vcore to 662500
2123 00:24:32.481427 Read voltage for 1200, 2
2124 00:24:32.481936 Vio18 = 0
2125 00:24:32.482258 Vcore = 662500
2126 00:24:32.484433 Vdram = 0
2127 00:24:32.484838 Vddq = 0
2128 00:24:32.485158 Vmddr = 0
2129 00:24:32.491371 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2130 00:24:32.494755 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2131 00:24:32.497724 MEM_TYPE=3, freq_sel=15
2132 00:24:32.501447 sv_algorithm_assistance_LP4_1600
2133 00:24:32.504495 ============ PULL DRAM RESETB DOWN ============
2134 00:24:32.508014 ========== PULL DRAM RESETB DOWN end =========
2135 00:24:32.514472 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2136 00:24:32.517931 ===================================
2137 00:24:32.518669 LPDDR4 DRAM CONFIGURATION
2138 00:24:32.520922 ===================================
2139 00:24:32.524781 EX_ROW_EN[0] = 0x0
2140 00:24:32.528269 EX_ROW_EN[1] = 0x0
2141 00:24:32.528820 LP4Y_EN = 0x0
2142 00:24:32.530993 WORK_FSP = 0x0
2143 00:24:32.531443 WL = 0x4
2144 00:24:32.534814 RL = 0x4
2145 00:24:32.535372 BL = 0x2
2146 00:24:32.537662 RPST = 0x0
2147 00:24:32.538209 RD_PRE = 0x0
2148 00:24:32.540631 WR_PRE = 0x1
2149 00:24:32.541164 WR_PST = 0x0
2150 00:24:32.544237 DBI_WR = 0x0
2151 00:24:32.544707 DBI_RD = 0x0
2152 00:24:32.547882 OTF = 0x1
2153 00:24:32.551206 ===================================
2154 00:24:32.554073 ===================================
2155 00:24:32.554488 ANA top config
2156 00:24:32.557412 ===================================
2157 00:24:32.561035 DLL_ASYNC_EN = 0
2158 00:24:32.564196 ALL_SLAVE_EN = 0
2159 00:24:32.567287 NEW_RANK_MODE = 1
2160 00:24:32.567706 DLL_IDLE_MODE = 1
2161 00:24:32.570755 LP45_APHY_COMB_EN = 1
2162 00:24:32.574096 TX_ODT_DIS = 1
2163 00:24:32.577742 NEW_8X_MODE = 1
2164 00:24:32.580738 ===================================
2165 00:24:32.583899 ===================================
2166 00:24:32.587562 data_rate = 2400
2167 00:24:32.588125 CKR = 1
2168 00:24:32.590554 DQ_P2S_RATIO = 8
2169 00:24:32.594166 ===================================
2170 00:24:32.597511 CA_P2S_RATIO = 8
2171 00:24:32.601121 DQ_CA_OPEN = 0
2172 00:24:32.603891 DQ_SEMI_OPEN = 0
2173 00:24:32.608060 CA_SEMI_OPEN = 0
2174 00:24:32.608611 CA_FULL_RATE = 0
2175 00:24:32.610912 DQ_CKDIV4_EN = 0
2176 00:24:32.614041 CA_CKDIV4_EN = 0
2177 00:24:32.617300 CA_PREDIV_EN = 0
2178 00:24:32.620170 PH8_DLY = 17
2179 00:24:32.623713 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2180 00:24:32.624165 DQ_AAMCK_DIV = 4
2181 00:24:32.626772 CA_AAMCK_DIV = 4
2182 00:24:32.630196 CA_ADMCK_DIV = 4
2183 00:24:32.634217 DQ_TRACK_CA_EN = 0
2184 00:24:32.637020 CA_PICK = 1200
2185 00:24:32.640604 CA_MCKIO = 1200
2186 00:24:32.643312 MCKIO_SEMI = 0
2187 00:24:32.643976 PLL_FREQ = 2366
2188 00:24:32.647072 DQ_UI_PI_RATIO = 32
2189 00:24:32.650951 CA_UI_PI_RATIO = 0
2190 00:24:32.653388 ===================================
2191 00:24:32.657044 ===================================
2192 00:24:32.660089 memory_type:LPDDR4
2193 00:24:32.663549 GP_NUM : 10
2194 00:24:32.664094 SRAM_EN : 1
2195 00:24:32.666974 MD32_EN : 0
2196 00:24:32.670687 ===================================
2197 00:24:32.671314 [ANA_INIT] >>>>>>>>>>>>>>
2198 00:24:32.673598 <<<<<< [CONFIGURE PHASE]: ANA_TX
2199 00:24:32.676542 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2200 00:24:32.680616 ===================================
2201 00:24:32.684055 data_rate = 2400,PCW = 0X5b00
2202 00:24:32.686987 ===================================
2203 00:24:32.691046 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2204 00:24:32.696708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 00:24:32.700206 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2206 00:24:32.706915 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2207 00:24:32.709944 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2208 00:24:32.713267 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2209 00:24:32.716599 [ANA_INIT] flow start
2210 00:24:32.717133 [ANA_INIT] PLL >>>>>>>>
2211 00:24:32.720157 [ANA_INIT] PLL <<<<<<<<
2212 00:24:32.723096 [ANA_INIT] MIDPI >>>>>>>>
2213 00:24:32.723610 [ANA_INIT] MIDPI <<<<<<<<
2214 00:24:32.726578 [ANA_INIT] DLL >>>>>>>>
2215 00:24:32.730132 [ANA_INIT] DLL <<<<<<<<
2216 00:24:32.730579 [ANA_INIT] flow end
2217 00:24:32.736837 ============ LP4 DIFF to SE enter ============
2218 00:24:32.740381 ============ LP4 DIFF to SE exit ============
2219 00:24:32.740935 [ANA_INIT] <<<<<<<<<<<<<
2220 00:24:32.743392 [Flow] Enable top DCM control >>>>>
2221 00:24:32.746701 [Flow] Enable top DCM control <<<<<
2222 00:24:32.750300 Enable DLL master slave shuffle
2223 00:24:32.756369 ==============================================================
2224 00:24:32.759478 Gating Mode config
2225 00:24:32.763323 ==============================================================
2226 00:24:32.766166 Config description:
2227 00:24:32.776400 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2228 00:24:32.783111 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2229 00:24:32.786111 SELPH_MODE 0: By rank 1: By Phase
2230 00:24:32.793198 ==============================================================
2231 00:24:32.796547 GAT_TRACK_EN = 1
2232 00:24:32.799896 RX_GATING_MODE = 2
2233 00:24:32.802535 RX_GATING_TRACK_MODE = 2
2234 00:24:32.803024 SELPH_MODE = 1
2235 00:24:32.806033 PICG_EARLY_EN = 1
2236 00:24:32.808988 VALID_LAT_VALUE = 1
2237 00:24:32.815811 ==============================================================
2238 00:24:32.819287 Enter into Gating configuration >>>>
2239 00:24:32.822493 Exit from Gating configuration <<<<
2240 00:24:32.825906 Enter into DVFS_PRE_config >>>>>
2241 00:24:32.835918 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2242 00:24:32.839737 Exit from DVFS_PRE_config <<<<<
2243 00:24:32.842700 Enter into PICG configuration >>>>
2244 00:24:32.846030 Exit from PICG configuration <<<<
2245 00:24:32.849081 [RX_INPUT] configuration >>>>>
2246 00:24:32.852361 [RX_INPUT] configuration <<<<<
2247 00:24:32.856301 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2248 00:24:32.862812 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2249 00:24:32.869386 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 00:24:32.875825 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 00:24:32.883005 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2252 00:24:32.885795 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2253 00:24:32.892334 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2254 00:24:32.895751 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2255 00:24:32.899209 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2256 00:24:32.902073 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2257 00:24:32.905577 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2258 00:24:32.912109 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2259 00:24:32.915670 ===================================
2260 00:24:32.918778 LPDDR4 DRAM CONFIGURATION
2261 00:24:32.922012 ===================================
2262 00:24:32.922468 EX_ROW_EN[0] = 0x0
2263 00:24:32.925272 EX_ROW_EN[1] = 0x0
2264 00:24:32.925722 LP4Y_EN = 0x0
2265 00:24:32.929023 WORK_FSP = 0x0
2266 00:24:32.929592 WL = 0x4
2267 00:24:32.932184 RL = 0x4
2268 00:24:32.932734 BL = 0x2
2269 00:24:32.935403 RPST = 0x0
2270 00:24:32.935856 RD_PRE = 0x0
2271 00:24:32.938639 WR_PRE = 0x1
2272 00:24:32.939095 WR_PST = 0x0
2273 00:24:32.941988 DBI_WR = 0x0
2274 00:24:32.942439 DBI_RD = 0x0
2275 00:24:32.945393 OTF = 0x1
2276 00:24:32.949266 ===================================
2277 00:24:32.952011 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2278 00:24:32.955114 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2279 00:24:32.961556 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2280 00:24:32.965415 ===================================
2281 00:24:32.965827 LPDDR4 DRAM CONFIGURATION
2282 00:24:32.968830 ===================================
2283 00:24:32.972285 EX_ROW_EN[0] = 0x10
2284 00:24:32.975235 EX_ROW_EN[1] = 0x0
2285 00:24:32.975747 LP4Y_EN = 0x0
2286 00:24:32.979041 WORK_FSP = 0x0
2287 00:24:32.979548 WL = 0x4
2288 00:24:32.982064 RL = 0x4
2289 00:24:32.982575 BL = 0x2
2290 00:24:32.985173 RPST = 0x0
2291 00:24:32.985686 RD_PRE = 0x0
2292 00:24:32.988129 WR_PRE = 0x1
2293 00:24:32.988535 WR_PST = 0x0
2294 00:24:32.991487 DBI_WR = 0x0
2295 00:24:32.991892 DBI_RD = 0x0
2296 00:24:32.995217 OTF = 0x1
2297 00:24:32.998546 ===================================
2298 00:24:33.004983 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2299 00:24:33.005392 ==
2300 00:24:33.008279 Dram Type= 6, Freq= 0, CH_0, rank 0
2301 00:24:33.011525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2302 00:24:33.011936 ==
2303 00:24:33.014895 [Duty_Offset_Calibration]
2304 00:24:33.015359 B0:1 B1:-1 CA:0
2305 00:24:33.015680
2306 00:24:33.018126 [DutyScan_Calibration_Flow] k_type=0
2307 00:24:33.029034
2308 00:24:33.029536 ==CLK 0==
2309 00:24:33.032108 Final CLK duty delay cell = 0
2310 00:24:33.035687 [0] MAX Duty = 5125%(X100), DQS PI = 24
2311 00:24:33.039104 [0] MIN Duty = 4907%(X100), DQS PI = 8
2312 00:24:33.039611 [0] AVG Duty = 5016%(X100)
2313 00:24:33.042697
2314 00:24:33.045183 CH0 CLK Duty spec in!! Max-Min= 218%
2315 00:24:33.049300 [DutyScan_Calibration_Flow] ====Done====
2316 00:24:33.049707
2317 00:24:33.051998 [DutyScan_Calibration_Flow] k_type=1
2318 00:24:33.066207
2319 00:24:33.066742 ==DQS 0 ==
2320 00:24:33.069631 Final DQS duty delay cell = -4
2321 00:24:33.073070 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2322 00:24:33.076463 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2323 00:24:33.079987 [-4] AVG Duty = 4968%(X100)
2324 00:24:33.080493
2325 00:24:33.080809 ==DQS 1 ==
2326 00:24:33.083276 Final DQS duty delay cell = -4
2327 00:24:33.086544 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2328 00:24:33.089876 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2329 00:24:33.093339 [-4] AVG Duty = 4938%(X100)
2330 00:24:33.093848
2331 00:24:33.097368 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2332 00:24:33.097896
2333 00:24:33.099941 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2334 00:24:33.103484 [DutyScan_Calibration_Flow] ====Done====
2335 00:24:33.104040
2336 00:24:33.106548 [DutyScan_Calibration_Flow] k_type=3
2337 00:24:33.124822
2338 00:24:33.125367 ==DQM 0 ==
2339 00:24:33.127853 Final DQM duty delay cell = 0
2340 00:24:33.131897 [0] MAX Duty = 5062%(X100), DQS PI = 20
2341 00:24:33.134582 [0] MIN Duty = 4875%(X100), DQS PI = 8
2342 00:24:33.138102 [0] AVG Duty = 4968%(X100)
2343 00:24:33.138698
2344 00:24:33.139059 ==DQM 1 ==
2345 00:24:33.141012 Final DQM duty delay cell = 4
2346 00:24:33.144140 [4] MAX Duty = 5187%(X100), DQS PI = 56
2347 00:24:33.147712 [4] MIN Duty = 5000%(X100), DQS PI = 24
2348 00:24:33.151032 [4] AVG Duty = 5093%(X100)
2349 00:24:33.151577
2350 00:24:33.154084 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2351 00:24:33.154663
2352 00:24:33.157785 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2353 00:24:33.161325 [DutyScan_Calibration_Flow] ====Done====
2354 00:24:33.161869
2355 00:24:33.164511 [DutyScan_Calibration_Flow] k_type=2
2356 00:24:33.179702
2357 00:24:33.180243 ==DQ 0 ==
2358 00:24:33.183351 Final DQ duty delay cell = -4
2359 00:24:33.186464 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2360 00:24:33.189452 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2361 00:24:33.192922 [-4] AVG Duty = 4969%(X100)
2362 00:24:33.193459
2363 00:24:33.193809 ==DQ 1 ==
2364 00:24:33.196142 Final DQ duty delay cell = -4
2365 00:24:33.199373 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2366 00:24:33.202825 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2367 00:24:33.206268 [-4] AVG Duty = 4938%(X100)
2368 00:24:33.206851
2369 00:24:33.209580 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2370 00:24:33.210118
2371 00:24:33.212532 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2372 00:24:33.215698 [DutyScan_Calibration_Flow] ====Done====
2373 00:24:33.216141 ==
2374 00:24:33.220306 Dram Type= 6, Freq= 0, CH_1, rank 0
2375 00:24:33.222299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2376 00:24:33.222831 ==
2377 00:24:33.226124 [Duty_Offset_Calibration]
2378 00:24:33.226565 B0:-1 B1:1 CA:1
2379 00:24:33.229346
2380 00:24:33.232648 [DutyScan_Calibration_Flow] k_type=0
2381 00:24:33.240761
2382 00:24:33.241293 ==CLK 0==
2383 00:24:33.243529 Final CLK duty delay cell = 0
2384 00:24:33.247197 [0] MAX Duty = 5156%(X100), DQS PI = 22
2385 00:24:33.251163 [0] MIN Duty = 4969%(X100), DQS PI = 62
2386 00:24:33.251607 [0] AVG Duty = 5062%(X100)
2387 00:24:33.253768
2388 00:24:33.254301 CH1 CLK Duty spec in!! Max-Min= 187%
2389 00:24:33.260405 [DutyScan_Calibration_Flow] ====Done====
2390 00:24:33.260940
2391 00:24:33.263180 [DutyScan_Calibration_Flow] k_type=1
2392 00:24:33.279560
2393 00:24:33.280100 ==DQS 0 ==
2394 00:24:33.283036 Final DQS duty delay cell = 0
2395 00:24:33.286200 [0] MAX Duty = 5156%(X100), DQS PI = 48
2396 00:24:33.289417 [0] MIN Duty = 4875%(X100), DQS PI = 8
2397 00:24:33.292949 [0] AVG Duty = 5015%(X100)
2398 00:24:33.293494
2399 00:24:33.293847 ==DQS 1 ==
2400 00:24:33.296030 Final DQS duty delay cell = 0
2401 00:24:33.299624 [0] MAX Duty = 5094%(X100), DQS PI = 10
2402 00:24:33.303192 [0] MIN Duty = 4969%(X100), DQS PI = 56
2403 00:24:33.306410 [0] AVG Duty = 5031%(X100)
2404 00:24:33.306990
2405 00:24:33.309240 CH1 DQS 0 Duty spec in!! Max-Min= 281%
2406 00:24:33.309782
2407 00:24:33.312558 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2408 00:24:33.315654 [DutyScan_Calibration_Flow] ====Done====
2409 00:24:33.316107
2410 00:24:33.319232 [DutyScan_Calibration_Flow] k_type=3
2411 00:24:33.335587
2412 00:24:33.336128 ==DQM 0 ==
2413 00:24:33.338828 Final DQM duty delay cell = -4
2414 00:24:33.342026 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2415 00:24:33.345444 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2416 00:24:33.348598 [-4] AVG Duty = 4969%(X100)
2417 00:24:33.349141
2418 00:24:33.349491 ==DQM 1 ==
2419 00:24:33.352016 Final DQM duty delay cell = 0
2420 00:24:33.355246 [0] MAX Duty = 5187%(X100), DQS PI = 4
2421 00:24:33.358158 [0] MIN Duty = 5000%(X100), DQS PI = 30
2422 00:24:33.361687 [0] AVG Duty = 5093%(X100)
2423 00:24:33.362235
2424 00:24:33.365180 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2425 00:24:33.365727
2426 00:24:33.368400 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2427 00:24:33.372274 [DutyScan_Calibration_Flow] ====Done====
2428 00:24:33.372819
2429 00:24:33.375275 [DutyScan_Calibration_Flow] k_type=2
2430 00:24:33.392133
2431 00:24:33.392681 ==DQ 0 ==
2432 00:24:33.395755 Final DQ duty delay cell = 0
2433 00:24:33.398904 [0] MAX Duty = 5187%(X100), DQS PI = 30
2434 00:24:33.402095 [0] MIN Duty = 4907%(X100), DQS PI = 6
2435 00:24:33.402545 [0] AVG Duty = 5047%(X100)
2436 00:24:33.402944
2437 00:24:33.405279 ==DQ 1 ==
2438 00:24:33.408391 Final DQ duty delay cell = 0
2439 00:24:33.412260 [0] MAX Duty = 5124%(X100), DQS PI = 10
2440 00:24:33.415185 [0] MIN Duty = 4969%(X100), DQS PI = 58
2441 00:24:33.415668 [0] AVG Duty = 5046%(X100)
2442 00:24:33.416026
2443 00:24:33.418716 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2444 00:24:33.421724
2445 00:24:33.425517 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2446 00:24:33.428066 [DutyScan_Calibration_Flow] ====Done====
2447 00:24:33.431793 nWR fixed to 30
2448 00:24:33.432301 [ModeRegInit_LP4] CH0 RK0
2449 00:24:33.434966 [ModeRegInit_LP4] CH0 RK1
2450 00:24:33.439174 [ModeRegInit_LP4] CH1 RK0
2451 00:24:33.441941 [ModeRegInit_LP4] CH1 RK1
2452 00:24:33.442394 match AC timing 7
2453 00:24:33.445126 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2454 00:24:33.448359 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2455 00:24:33.455400 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2456 00:24:33.458994 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2457 00:24:33.466132 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2458 00:24:33.466754 ==
2459 00:24:33.468654 Dram Type= 6, Freq= 0, CH_0, rank 0
2460 00:24:33.471985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2461 00:24:33.472535 ==
2462 00:24:33.478656 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2463 00:24:33.485247 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2464 00:24:33.491881 [CA 0] Center 39 (9~70) winsize 62
2465 00:24:33.495426 [CA 1] Center 39 (9~69) winsize 61
2466 00:24:33.499027 [CA 2] Center 35 (5~66) winsize 62
2467 00:24:33.502198 [CA 3] Center 35 (4~66) winsize 63
2468 00:24:33.504952 [CA 4] Center 33 (4~63) winsize 60
2469 00:24:33.508536 [CA 5] Center 33 (3~63) winsize 61
2470 00:24:33.509078
2471 00:24:33.511678 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2472 00:24:33.512221
2473 00:24:33.514790 [CATrainingPosCal] consider 1 rank data
2474 00:24:33.518647 u2DelayCellTimex100 = 270/100 ps
2475 00:24:33.522008 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2476 00:24:33.528437 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2477 00:24:33.531755 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2478 00:24:33.534947 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2479 00:24:33.538067 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2480 00:24:33.541518 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2481 00:24:33.542067
2482 00:24:33.544901 CA PerBit enable=1, Macro0, CA PI delay=33
2483 00:24:33.545364
2484 00:24:33.548512 [CBTSetCACLKResult] CA Dly = 33
2485 00:24:33.549052 CS Dly: 8 (0~39)
2486 00:24:33.551600 ==
2487 00:24:33.554712 Dram Type= 6, Freq= 0, CH_0, rank 1
2488 00:24:33.558288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2489 00:24:33.558903 ==
2490 00:24:33.561475 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2491 00:24:33.567963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2492 00:24:33.578211 [CA 0] Center 39 (9~70) winsize 62
2493 00:24:33.580991 [CA 1] Center 39 (9~70) winsize 62
2494 00:24:33.584529 [CA 2] Center 35 (5~66) winsize 62
2495 00:24:33.587552 [CA 3] Center 34 (4~65) winsize 62
2496 00:24:33.591414 [CA 4] Center 33 (3~64) winsize 62
2497 00:24:33.594154 [CA 5] Center 33 (3~63) winsize 61
2498 00:24:33.594750
2499 00:24:33.597555 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2500 00:24:33.598105
2501 00:24:33.600963 [CATrainingPosCal] consider 2 rank data
2502 00:24:33.603935 u2DelayCellTimex100 = 270/100 ps
2503 00:24:33.607643 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2504 00:24:33.614140 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2505 00:24:33.617167 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2506 00:24:33.620867 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2507 00:24:33.623925 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2508 00:24:33.627114 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2509 00:24:33.627559
2510 00:24:33.630776 CA PerBit enable=1, Macro0, CA PI delay=33
2511 00:24:33.631223
2512 00:24:33.634113 [CBTSetCACLKResult] CA Dly = 33
2513 00:24:33.634712 CS Dly: 9 (0~41)
2514 00:24:33.635074
2515 00:24:33.637484 ----->DramcWriteLeveling(PI) begin...
2516 00:24:33.640952 ==
2517 00:24:33.644185 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 00:24:33.647547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 00:24:33.648025 ==
2520 00:24:33.650465 Write leveling (Byte 0): 33 => 33
2521 00:24:33.653903 Write leveling (Byte 1): 27 => 27
2522 00:24:33.657160 DramcWriteLeveling(PI) end<-----
2523 00:24:33.657609
2524 00:24:33.657956 ==
2525 00:24:33.660599 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 00:24:33.663542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 00:24:33.664041 ==
2528 00:24:33.667495 [Gating] SW mode calibration
2529 00:24:33.674062 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2530 00:24:33.681070 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2531 00:24:33.683738 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2532 00:24:33.687222 0 15 4 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
2533 00:24:33.693836 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 00:24:33.696875 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 00:24:33.700453 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 00:24:33.707094 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 00:24:33.710504 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2538 00:24:33.713519 0 15 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
2539 00:24:33.720604 1 0 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
2540 00:24:33.724607 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2541 00:24:33.727068 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 00:24:33.733355 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 00:24:33.737105 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 00:24:33.740411 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 00:24:33.743227 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
2546 00:24:33.750077 1 0 28 | B1->B0 | 2323 3534 | 0 1 | (0 0) (0 0)
2547 00:24:33.753545 1 1 0 | B1->B0 | 2323 4646 | 1 0 | (0 0) (0 0)
2548 00:24:33.756511 1 1 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2549 00:24:33.762960 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 00:24:33.766725 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 00:24:33.769824 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 00:24:33.776602 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 00:24:33.779645 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 00:24:33.783148 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2555 00:24:33.790342 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2556 00:24:33.792852 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2557 00:24:33.796479 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 00:24:33.802831 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 00:24:33.806789 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 00:24:33.809955 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 00:24:33.815948 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 00:24:33.819217 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 00:24:33.822818 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 00:24:33.829508 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 00:24:33.832546 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 00:24:33.836566 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 00:24:33.843050 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 00:24:33.846272 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 00:24:33.849648 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2570 00:24:33.855611 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2571 00:24:33.859074 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2572 00:24:33.862718 Total UI for P1: 0, mck2ui 16
2573 00:24:33.866277 best dqsien dly found for B0: ( 1, 3, 26)
2574 00:24:33.869975 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2575 00:24:33.876561 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 00:24:33.877111 Total UI for P1: 0, mck2ui 16
2577 00:24:33.882825 best dqsien dly found for B1: ( 1, 4, 2)
2578 00:24:33.886152 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2579 00:24:33.889230 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2580 00:24:33.889808
2581 00:24:33.892708 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2582 00:24:33.895918 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2583 00:24:33.899738 [Gating] SW calibration Done
2584 00:24:33.900287 ==
2585 00:24:33.903042 Dram Type= 6, Freq= 0, CH_0, rank 0
2586 00:24:33.906021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2587 00:24:33.906577 ==
2588 00:24:33.909265 RX Vref Scan: 0
2589 00:24:33.909812
2590 00:24:33.910166 RX Vref 0 -> 0, step: 1
2591 00:24:33.910494
2592 00:24:33.912123 RX Delay -40 -> 252, step: 8
2593 00:24:33.916862 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2594 00:24:33.922701 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2595 00:24:33.925813 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2596 00:24:33.928854 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2597 00:24:33.932271 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2598 00:24:33.935905 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2599 00:24:33.942487 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2600 00:24:33.946225 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2601 00:24:33.949174 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2602 00:24:33.952423 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2603 00:24:33.955510 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2604 00:24:33.958894 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2605 00:24:33.965527 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2606 00:24:33.969196 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2607 00:24:33.971932 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2608 00:24:33.976048 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2609 00:24:33.976594 ==
2610 00:24:33.978526 Dram Type= 6, Freq= 0, CH_0, rank 0
2611 00:24:33.985584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2612 00:24:33.986133 ==
2613 00:24:33.986491 DQS Delay:
2614 00:24:33.989090 DQS0 = 0, DQS1 = 0
2615 00:24:33.989541 DQM Delay:
2616 00:24:33.992459 DQM0 = 119, DQM1 = 106
2617 00:24:33.993005 DQ Delay:
2618 00:24:33.995256 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2619 00:24:33.998814 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2620 00:24:34.002363 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2621 00:24:34.005476 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2622 00:24:34.006027
2623 00:24:34.006470
2624 00:24:34.006860 ==
2625 00:24:34.008753 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 00:24:34.011889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 00:24:34.015615 ==
2628 00:24:34.016068
2629 00:24:34.016418
2630 00:24:34.016743 TX Vref Scan disable
2631 00:24:34.018299 == TX Byte 0 ==
2632 00:24:34.021946 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2633 00:24:34.025437 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2634 00:24:34.028747 == TX Byte 1 ==
2635 00:24:34.031833 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2636 00:24:34.035113 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2637 00:24:34.039137 ==
2638 00:24:34.042179 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 00:24:34.045468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 00:24:34.046016 ==
2641 00:24:34.056554 TX Vref=22, minBit 13, minWin=24, winSum=410
2642 00:24:34.060259 TX Vref=24, minBit 13, minWin=25, winSum=418
2643 00:24:34.063899 TX Vref=26, minBit 7, minWin=26, winSum=428
2644 00:24:34.066981 TX Vref=28, minBit 8, minWin=26, winSum=431
2645 00:24:34.070288 TX Vref=30, minBit 4, minWin=26, winSum=434
2646 00:24:34.076620 TX Vref=32, minBit 4, minWin=26, winSum=429
2647 00:24:34.080150 [TxChooseVref] Worse bit 4, Min win 26, Win sum 434, Final Vref 30
2648 00:24:34.080700
2649 00:24:34.083178 Final TX Range 1 Vref 30
2650 00:24:34.083637
2651 00:24:34.083992 ==
2652 00:24:34.086897 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 00:24:34.089644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 00:24:34.093422 ==
2655 00:24:34.094017
2656 00:24:34.094377
2657 00:24:34.094759 TX Vref Scan disable
2658 00:24:34.096870 == TX Byte 0 ==
2659 00:24:34.100092 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2660 00:24:34.106793 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2661 00:24:34.107335 == TX Byte 1 ==
2662 00:24:34.109727 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2663 00:24:34.116540 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2664 00:24:34.117107
2665 00:24:34.117472 [DATLAT]
2666 00:24:34.117804 Freq=1200, CH0 RK0
2667 00:24:34.118124
2668 00:24:34.119757 DATLAT Default: 0xd
2669 00:24:34.123012 0, 0xFFFF, sum = 0
2670 00:24:34.123612 1, 0xFFFF, sum = 0
2671 00:24:34.126860 2, 0xFFFF, sum = 0
2672 00:24:34.127505 3, 0xFFFF, sum = 0
2673 00:24:34.129987 4, 0xFFFF, sum = 0
2674 00:24:34.130657 5, 0xFFFF, sum = 0
2675 00:24:34.133170 6, 0xFFFF, sum = 0
2676 00:24:34.133633 7, 0xFFFF, sum = 0
2677 00:24:34.136387 8, 0xFFFF, sum = 0
2678 00:24:34.136943 9, 0xFFFF, sum = 0
2679 00:24:34.139760 10, 0xFFFF, sum = 0
2680 00:24:34.140221 11, 0xFFFF, sum = 0
2681 00:24:34.143867 12, 0x0, sum = 1
2682 00:24:34.144426 13, 0x0, sum = 2
2683 00:24:34.146760 14, 0x0, sum = 3
2684 00:24:34.147231 15, 0x0, sum = 4
2685 00:24:34.147598 best_step = 13
2686 00:24:34.149993
2687 00:24:34.150540 ==
2688 00:24:34.153333 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 00:24:34.156605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 00:24:34.157063 ==
2691 00:24:34.157620 RX Vref Scan: 1
2692 00:24:34.157982
2693 00:24:34.159733 Set Vref Range= 32 -> 127
2694 00:24:34.160188
2695 00:24:34.163680 RX Vref 32 -> 127, step: 1
2696 00:24:34.164238
2697 00:24:34.166688 RX Delay -21 -> 252, step: 4
2698 00:24:34.167235
2699 00:24:34.169445 Set Vref, RX VrefLevel [Byte0]: 32
2700 00:24:34.173071 [Byte1]: 32
2701 00:24:34.173607
2702 00:24:34.176870 Set Vref, RX VrefLevel [Byte0]: 33
2703 00:24:34.179904 [Byte1]: 33
2704 00:24:34.183049
2705 00:24:34.183587 Set Vref, RX VrefLevel [Byte0]: 34
2706 00:24:34.186642 [Byte1]: 34
2707 00:24:34.191444
2708 00:24:34.191990 Set Vref, RX VrefLevel [Byte0]: 35
2709 00:24:34.194585 [Byte1]: 35
2710 00:24:34.199124
2711 00:24:34.199709 Set Vref, RX VrefLevel [Byte0]: 36
2712 00:24:34.202218 [Byte1]: 36
2713 00:24:34.206757
2714 00:24:34.207293 Set Vref, RX VrefLevel [Byte0]: 37
2715 00:24:34.210144 [Byte1]: 37
2716 00:24:34.215563
2717 00:24:34.216095 Set Vref, RX VrefLevel [Byte0]: 38
2718 00:24:34.218278 [Byte1]: 38
2719 00:24:34.222794
2720 00:24:34.223337 Set Vref, RX VrefLevel [Byte0]: 39
2721 00:24:34.226354 [Byte1]: 39
2722 00:24:34.230543
2723 00:24:34.231142 Set Vref, RX VrefLevel [Byte0]: 40
2724 00:24:34.234309 [Byte1]: 40
2725 00:24:34.238716
2726 00:24:34.239257 Set Vref, RX VrefLevel [Byte0]: 41
2727 00:24:34.241699 [Byte1]: 41
2728 00:24:34.246506
2729 00:24:34.247128 Set Vref, RX VrefLevel [Byte0]: 42
2730 00:24:34.249796 [Byte1]: 42
2731 00:24:34.254717
2732 00:24:34.255263 Set Vref, RX VrefLevel [Byte0]: 43
2733 00:24:34.258161 [Byte1]: 43
2734 00:24:34.263076
2735 00:24:34.263621 Set Vref, RX VrefLevel [Byte0]: 44
2736 00:24:34.265928 [Byte1]: 44
2737 00:24:34.270540
2738 00:24:34.271132 Set Vref, RX VrefLevel [Byte0]: 45
2739 00:24:34.274096 [Byte1]: 45
2740 00:24:34.278351
2741 00:24:34.278938 Set Vref, RX VrefLevel [Byte0]: 46
2742 00:24:34.281484 [Byte1]: 46
2743 00:24:34.286501
2744 00:24:34.287085 Set Vref, RX VrefLevel [Byte0]: 47
2745 00:24:34.289483 [Byte1]: 47
2746 00:24:34.295203
2747 00:24:34.295744 Set Vref, RX VrefLevel [Byte0]: 48
2748 00:24:34.297310 [Byte1]: 48
2749 00:24:34.302030
2750 00:24:34.302570 Set Vref, RX VrefLevel [Byte0]: 49
2751 00:24:34.306019 [Byte1]: 49
2752 00:24:34.310087
2753 00:24:34.310676 Set Vref, RX VrefLevel [Byte0]: 50
2754 00:24:34.313652 [Byte1]: 50
2755 00:24:34.317801
2756 00:24:34.318417 Set Vref, RX VrefLevel [Byte0]: 51
2757 00:24:34.321065 [Byte1]: 51
2758 00:24:34.325341
2759 00:24:34.325937 Set Vref, RX VrefLevel [Byte0]: 52
2760 00:24:34.329115 [Byte1]: 52
2761 00:24:34.333937
2762 00:24:34.334491 Set Vref, RX VrefLevel [Byte0]: 53
2763 00:24:34.337257 [Byte1]: 53
2764 00:24:34.341451
2765 00:24:34.341896 Set Vref, RX VrefLevel [Byte0]: 54
2766 00:24:34.344841 [Byte1]: 54
2767 00:24:34.349483
2768 00:24:34.349922 Set Vref, RX VrefLevel [Byte0]: 55
2769 00:24:34.352642 [Byte1]: 55
2770 00:24:34.357256
2771 00:24:34.357984 Set Vref, RX VrefLevel [Byte0]: 56
2772 00:24:34.360694 [Byte1]: 56
2773 00:24:34.365656
2774 00:24:34.366060 Set Vref, RX VrefLevel [Byte0]: 57
2775 00:24:34.368494 [Byte1]: 57
2776 00:24:34.373075
2777 00:24:34.373481 Set Vref, RX VrefLevel [Byte0]: 58
2778 00:24:34.376153 [Byte1]: 58
2779 00:24:34.381148
2780 00:24:34.381556 Set Vref, RX VrefLevel [Byte0]: 59
2781 00:24:34.384429 [Byte1]: 59
2782 00:24:34.388797
2783 00:24:34.389201 Set Vref, RX VrefLevel [Byte0]: 60
2784 00:24:34.392287 [Byte1]: 60
2785 00:24:34.396719
2786 00:24:34.397126 Set Vref, RX VrefLevel [Byte0]: 61
2787 00:24:34.400750 [Byte1]: 61
2788 00:24:34.405214
2789 00:24:34.405746 Set Vref, RX VrefLevel [Byte0]: 62
2790 00:24:34.408181 [Byte1]: 62
2791 00:24:34.412926
2792 00:24:34.413331 Set Vref, RX VrefLevel [Byte0]: 63
2793 00:24:34.415981 [Byte1]: 63
2794 00:24:34.420617
2795 00:24:34.421173 Set Vref, RX VrefLevel [Byte0]: 64
2796 00:24:34.424211 [Byte1]: 64
2797 00:24:34.428940
2798 00:24:34.429344 Set Vref, RX VrefLevel [Byte0]: 65
2799 00:24:34.431915 [Byte1]: 65
2800 00:24:34.437334
2801 00:24:34.437793 Set Vref, RX VrefLevel [Byte0]: 66
2802 00:24:34.439831 [Byte1]: 66
2803 00:24:34.444611
2804 00:24:34.445019 Set Vref, RX VrefLevel [Byte0]: 67
2805 00:24:34.448055 [Byte1]: 67
2806 00:24:34.452493
2807 00:24:34.452903 Set Vref, RX VrefLevel [Byte0]: 68
2808 00:24:34.455954 [Byte1]: 68
2809 00:24:34.460308
2810 00:24:34.460719 Set Vref, RX VrefLevel [Byte0]: 69
2811 00:24:34.463858 [Byte1]: 69
2812 00:24:34.468143
2813 00:24:34.468555 Set Vref, RX VrefLevel [Byte0]: 70
2814 00:24:34.474745 [Byte1]: 70
2815 00:24:34.475162
2816 00:24:34.478139 Set Vref, RX VrefLevel [Byte0]: 71
2817 00:24:34.481559 [Byte1]: 71
2818 00:24:34.481968
2819 00:24:34.484740 Set Vref, RX VrefLevel [Byte0]: 72
2820 00:24:34.487981 [Byte1]: 72
2821 00:24:34.492732
2822 00:24:34.493145 Set Vref, RX VrefLevel [Byte0]: 73
2823 00:24:34.495543 [Byte1]: 73
2824 00:24:34.501127
2825 00:24:34.501534 Set Vref, RX VrefLevel [Byte0]: 74
2826 00:24:34.503515 [Byte1]: 74
2827 00:24:34.507835
2828 00:24:34.508243 Set Vref, RX VrefLevel [Byte0]: 75
2829 00:24:34.511520 [Byte1]: 75
2830 00:24:34.516133
2831 00:24:34.516540 Set Vref, RX VrefLevel [Byte0]: 76
2832 00:24:34.519064 [Byte1]: 76
2833 00:24:34.523642
2834 00:24:34.524052 Set Vref, RX VrefLevel [Byte0]: 77
2835 00:24:34.527446 [Byte1]: 77
2836 00:24:34.531657
2837 00:24:34.532069 Final RX Vref Byte 0 = 60 to rank0
2838 00:24:34.535680 Final RX Vref Byte 1 = 57 to rank0
2839 00:24:34.538311 Final RX Vref Byte 0 = 60 to rank1
2840 00:24:34.542543 Final RX Vref Byte 1 = 57 to rank1==
2841 00:24:34.545253 Dram Type= 6, Freq= 0, CH_0, rank 0
2842 00:24:34.551784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 00:24:34.552212 ==
2844 00:24:34.552537 DQS Delay:
2845 00:24:34.552834 DQS0 = 0, DQS1 = 0
2846 00:24:34.555650 DQM Delay:
2847 00:24:34.556056 DQM0 = 119, DQM1 = 108
2848 00:24:34.558085 DQ Delay:
2849 00:24:34.561645 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2850 00:24:34.565593 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
2851 00:24:34.568717 DQ8 =96, DQ9 =94, DQ10 =112, DQ11 =102
2852 00:24:34.572260 DQ12 =112, DQ13 =112, DQ14 =122, DQ15 =114
2853 00:24:34.572673
2854 00:24:34.572994
2855 00:24:34.578261 [DQSOSCAuto] RK0, (LSB)MR18= 0x1500, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 401 ps
2856 00:24:34.581701 CH0 RK0: MR19=404, MR18=1500
2857 00:24:34.588080 CH0_RK0: MR19=0x404, MR18=0x1500, DQSOSC=401, MR23=63, INC=40, DEC=27
2858 00:24:34.588568
2859 00:24:34.591933 ----->DramcWriteLeveling(PI) begin...
2860 00:24:34.592352 ==
2861 00:24:34.594895 Dram Type= 6, Freq= 0, CH_0, rank 1
2862 00:24:34.598137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2863 00:24:34.602406 ==
2864 00:24:34.602932 Write leveling (Byte 0): 33 => 33
2865 00:24:34.605620 Write leveling (Byte 1): 31 => 31
2866 00:24:34.607771 DramcWriteLeveling(PI) end<-----
2867 00:24:34.608180
2868 00:24:34.608612 ==
2869 00:24:34.610830 Dram Type= 6, Freq= 0, CH_0, rank 1
2870 00:24:34.617631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2871 00:24:34.617711 ==
2872 00:24:34.617774 [Gating] SW mode calibration
2873 00:24:34.627664 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2874 00:24:34.631478 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2875 00:24:34.634267 0 15 0 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
2876 00:24:34.641097 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2877 00:24:34.644589 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2878 00:24:34.647600 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2879 00:24:34.654469 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2880 00:24:34.657624 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2881 00:24:34.661148 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2882 00:24:34.667466 0 15 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2883 00:24:34.670814 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
2884 00:24:34.674748 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2885 00:24:34.681760 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2886 00:24:34.684588 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2887 00:24:34.687699 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2888 00:24:34.694283 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2889 00:24:34.697545 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 00:24:34.701182 1 0 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2891 00:24:34.707591 1 1 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2892 00:24:34.711176 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 00:24:34.714354 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2894 00:24:34.720657 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2895 00:24:34.724554 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 00:24:34.727517 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 00:24:34.734740 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2898 00:24:34.737317 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2899 00:24:34.740721 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2900 00:24:34.747131 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 00:24:34.751255 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 00:24:34.753989 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 00:24:34.760880 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 00:24:34.764076 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 00:24:34.767282 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 00:24:34.774124 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 00:24:34.777033 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 00:24:34.780549 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 00:24:34.786860 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 00:24:34.790194 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 00:24:34.793524 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 00:24:34.800225 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 00:24:34.803995 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2914 00:24:34.806851 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2915 00:24:34.813699 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2916 00:24:34.813779 Total UI for P1: 0, mck2ui 16
2917 00:24:34.816706 best dqsien dly found for B0: ( 1, 3, 26)
2918 00:24:34.823320 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 00:24:34.826749 Total UI for P1: 0, mck2ui 16
2920 00:24:34.830121 best dqsien dly found for B1: ( 1, 3, 30)
2921 00:24:34.833333 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2922 00:24:34.837141 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2923 00:24:34.837219
2924 00:24:34.839970 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2925 00:24:34.843162 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2926 00:24:34.846656 [Gating] SW calibration Done
2927 00:24:34.846751 ==
2928 00:24:34.849924 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 00:24:34.853117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 00:24:34.853197 ==
2931 00:24:34.856600 RX Vref Scan: 0
2932 00:24:34.856679
2933 00:24:34.859925 RX Vref 0 -> 0, step: 1
2934 00:24:34.860004
2935 00:24:34.860066 RX Delay -40 -> 252, step: 8
2936 00:24:34.866504 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2937 00:24:34.869548 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2938 00:24:34.873037 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2939 00:24:34.876691 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2940 00:24:34.879515 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2941 00:24:34.886337 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2942 00:24:34.889468 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2943 00:24:34.892644 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2944 00:24:34.896097 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
2945 00:24:34.899890 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2946 00:24:34.906147 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2947 00:24:34.909891 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2948 00:24:34.913052 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2949 00:24:34.916255 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2950 00:24:34.922719 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2951 00:24:34.925799 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2952 00:24:34.925879 ==
2953 00:24:34.929346 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 00:24:34.932668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 00:24:34.932749 ==
2956 00:24:34.932812 DQS Delay:
2957 00:24:34.936031 DQS0 = 0, DQS1 = 0
2958 00:24:34.936111 DQM Delay:
2959 00:24:34.938891 DQM0 = 116, DQM1 = 108
2960 00:24:34.938971 DQ Delay:
2961 00:24:34.942845 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2962 00:24:34.946108 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2963 00:24:34.949006 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
2964 00:24:34.955316 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2965 00:24:34.955397
2966 00:24:34.955459
2967 00:24:34.955517 ==
2968 00:24:34.959600 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 00:24:34.962440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 00:24:34.962520 ==
2971 00:24:34.962583
2972 00:24:34.962649
2973 00:24:34.965328 TX Vref Scan disable
2974 00:24:34.965407 == TX Byte 0 ==
2975 00:24:34.972082 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2976 00:24:34.975790 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2977 00:24:34.975869 == TX Byte 1 ==
2978 00:24:34.982179 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2979 00:24:34.985315 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2980 00:24:34.985395 ==
2981 00:24:34.989038 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 00:24:34.992294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 00:24:34.992374 ==
2984 00:24:35.004890 TX Vref=22, minBit 5, minWin=25, winSum=420
2985 00:24:35.008069 TX Vref=24, minBit 1, minWin=26, winSum=422
2986 00:24:35.011442 TX Vref=26, minBit 1, minWin=26, winSum=427
2987 00:24:35.014994 TX Vref=28, minBit 10, minWin=26, winSum=434
2988 00:24:35.018181 TX Vref=30, minBit 1, minWin=26, winSum=432
2989 00:24:35.024752 TX Vref=32, minBit 10, minWin=25, winSum=431
2990 00:24:35.027807 [TxChooseVref] Worse bit 10, Min win 26, Win sum 434, Final Vref 28
2991 00:24:35.027888
2992 00:24:35.032081 Final TX Range 1 Vref 28
2993 00:24:35.032161
2994 00:24:35.032223 ==
2995 00:24:35.035110 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 00:24:35.037754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 00:24:35.041496 ==
2998 00:24:35.041576
2999 00:24:35.041637
3000 00:24:35.041696 TX Vref Scan disable
3001 00:24:35.045060 == TX Byte 0 ==
3002 00:24:35.047978 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3003 00:24:35.054857 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3004 00:24:35.054937 == TX Byte 1 ==
3005 00:24:35.058448 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3006 00:24:35.065044 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3007 00:24:35.065123
3008 00:24:35.065186 [DATLAT]
3009 00:24:35.065244 Freq=1200, CH0 RK1
3010 00:24:35.065300
3011 00:24:35.068154 DATLAT Default: 0xd
3012 00:24:35.068234 0, 0xFFFF, sum = 0
3013 00:24:35.071746 1, 0xFFFF, sum = 0
3014 00:24:35.074559 2, 0xFFFF, sum = 0
3015 00:24:35.074646 3, 0xFFFF, sum = 0
3016 00:24:35.077961 4, 0xFFFF, sum = 0
3017 00:24:35.078041 5, 0xFFFF, sum = 0
3018 00:24:35.081233 6, 0xFFFF, sum = 0
3019 00:24:35.081314 7, 0xFFFF, sum = 0
3020 00:24:35.085057 8, 0xFFFF, sum = 0
3021 00:24:35.085138 9, 0xFFFF, sum = 0
3022 00:24:35.087825 10, 0xFFFF, sum = 0
3023 00:24:35.087906 11, 0xFFFF, sum = 0
3024 00:24:35.090982 12, 0x0, sum = 1
3025 00:24:35.091063 13, 0x0, sum = 2
3026 00:24:35.094708 14, 0x0, sum = 3
3027 00:24:35.094789 15, 0x0, sum = 4
3028 00:24:35.098261 best_step = 13
3029 00:24:35.098340
3030 00:24:35.098403 ==
3031 00:24:35.101197 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 00:24:35.104346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 00:24:35.104427 ==
3034 00:24:35.104489 RX Vref Scan: 0
3035 00:24:35.104547
3036 00:24:35.108190 RX Vref 0 -> 0, step: 1
3037 00:24:35.108269
3038 00:24:35.111357 RX Delay -21 -> 252, step: 4
3039 00:24:35.117734 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3040 00:24:35.121323 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3041 00:24:35.124602 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3042 00:24:35.128100 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3043 00:24:35.131059 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3044 00:24:35.134162 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3045 00:24:35.141137 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3046 00:24:35.144438 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3047 00:24:35.147810 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3048 00:24:35.150892 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3049 00:24:35.154460 iDelay=199, Bit 10, Center 112 (43 ~ 182) 140
3050 00:24:35.160763 iDelay=199, Bit 11, Center 104 (39 ~ 170) 132
3051 00:24:35.164286 iDelay=199, Bit 12, Center 116 (51 ~ 182) 132
3052 00:24:35.167519 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
3053 00:24:35.170790 iDelay=199, Bit 14, Center 122 (59 ~ 186) 128
3054 00:24:35.177341 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3055 00:24:35.177421 ==
3056 00:24:35.181056 Dram Type= 6, Freq= 0, CH_0, rank 1
3057 00:24:35.184313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3058 00:24:35.184394 ==
3059 00:24:35.184457 DQS Delay:
3060 00:24:35.187933 DQS0 = 0, DQS1 = 0
3061 00:24:35.188013 DQM Delay:
3062 00:24:35.190684 DQM0 = 116, DQM1 = 109
3063 00:24:35.190764 DQ Delay:
3064 00:24:35.193968 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3065 00:24:35.197115 DQ4 =116, DQ5 =110, DQ6 =128, DQ7 =124
3066 00:24:35.200862 DQ8 =98, DQ9 =94, DQ10 =112, DQ11 =104
3067 00:24:35.204171 DQ12 =116, DQ13 =114, DQ14 =122, DQ15 =116
3068 00:24:35.204251
3069 00:24:35.204313
3070 00:24:35.213989 [DQSOSCAuto] RK1, (LSB)MR18= 0xfe8, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 404 ps
3071 00:24:35.217126 CH0 RK1: MR19=403, MR18=FE8
3072 00:24:35.220537 CH0_RK1: MR19=0x403, MR18=0xFE8, DQSOSC=404, MR23=63, INC=40, DEC=26
3073 00:24:35.223781 [RxdqsGatingPostProcess] freq 1200
3074 00:24:35.230859 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3075 00:24:35.233983 best DQS0 dly(2T, 0.5T) = (0, 11)
3076 00:24:35.236911 best DQS1 dly(2T, 0.5T) = (0, 12)
3077 00:24:35.241262 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3078 00:24:35.243734 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3079 00:24:35.246838 best DQS0 dly(2T, 0.5T) = (0, 11)
3080 00:24:35.250255 best DQS1 dly(2T, 0.5T) = (0, 11)
3081 00:24:35.253583 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3082 00:24:35.257102 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3083 00:24:35.257185 Pre-setting of DQS Precalculation
3084 00:24:35.263847 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3085 00:24:35.263928 ==
3086 00:24:35.267256 Dram Type= 6, Freq= 0, CH_1, rank 0
3087 00:24:35.270411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3088 00:24:35.270492 ==
3089 00:24:35.276714 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3090 00:24:35.283320 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3091 00:24:35.291040 [CA 0] Center 37 (7~68) winsize 62
3092 00:24:35.294371 [CA 1] Center 37 (7~68) winsize 62
3093 00:24:35.297439 [CA 2] Center 34 (4~64) winsize 61
3094 00:24:35.301464 [CA 3] Center 33 (3~64) winsize 62
3095 00:24:35.304445 [CA 4] Center 34 (4~64) winsize 61
3096 00:24:35.307660 [CA 5] Center 33 (3~64) winsize 62
3097 00:24:35.307740
3098 00:24:35.310983 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3099 00:24:35.311063
3100 00:24:35.314535 [CATrainingPosCal] consider 1 rank data
3101 00:24:35.317694 u2DelayCellTimex100 = 270/100 ps
3102 00:24:35.320773 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3103 00:24:35.327709 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3104 00:24:35.330853 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3105 00:24:35.334000 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3106 00:24:35.337841 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3107 00:24:35.340776 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3108 00:24:35.340855
3109 00:24:35.344553 CA PerBit enable=1, Macro0, CA PI delay=33
3110 00:24:35.344633
3111 00:24:35.347170 [CBTSetCACLKResult] CA Dly = 33
3112 00:24:35.347250 CS Dly: 6 (0~37)
3113 00:24:35.350484 ==
3114 00:24:35.353958 Dram Type= 6, Freq= 0, CH_1, rank 1
3115 00:24:35.357240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 00:24:35.357321 ==
3117 00:24:35.361233 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3118 00:24:35.367181 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3119 00:24:35.376764 [CA 0] Center 37 (7~67) winsize 61
3120 00:24:35.379893 [CA 1] Center 37 (7~68) winsize 62
3121 00:24:35.383498 [CA 2] Center 34 (4~65) winsize 62
3122 00:24:35.386789 [CA 3] Center 33 (3~64) winsize 62
3123 00:24:35.389913 [CA 4] Center 34 (3~65) winsize 63
3124 00:24:35.393432 [CA 5] Center 33 (3~64) winsize 62
3125 00:24:35.393512
3126 00:24:35.396749 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3127 00:24:35.396829
3128 00:24:35.399978 [CATrainingPosCal] consider 2 rank data
3129 00:24:35.403126 u2DelayCellTimex100 = 270/100 ps
3130 00:24:35.406407 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3131 00:24:35.413134 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3132 00:24:35.416816 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3133 00:24:35.420715 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3134 00:24:35.422998 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3135 00:24:35.426384 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3136 00:24:35.426464
3137 00:24:35.429525 CA PerBit enable=1, Macro0, CA PI delay=33
3138 00:24:35.429604
3139 00:24:35.433060 [CBTSetCACLKResult] CA Dly = 33
3140 00:24:35.433140 CS Dly: 7 (0~40)
3141 00:24:35.436273
3142 00:24:35.440031 ----->DramcWriteLeveling(PI) begin...
3143 00:24:35.440112 ==
3144 00:24:35.443094 Dram Type= 6, Freq= 0, CH_1, rank 0
3145 00:24:35.446201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3146 00:24:35.446281 ==
3147 00:24:35.450292 Write leveling (Byte 0): 24 => 24
3148 00:24:35.452741 Write leveling (Byte 1): 29 => 29
3149 00:24:35.456131 DramcWriteLeveling(PI) end<-----
3150 00:24:35.456212
3151 00:24:35.456295 ==
3152 00:24:35.459676 Dram Type= 6, Freq= 0, CH_1, rank 0
3153 00:24:35.462682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3154 00:24:35.462763 ==
3155 00:24:35.466120 [Gating] SW mode calibration
3156 00:24:35.472761 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3157 00:24:35.479307 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3158 00:24:35.482954 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3159 00:24:35.486134 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3160 00:24:35.492863 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3161 00:24:35.496099 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3162 00:24:35.499038 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3163 00:24:35.506163 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3164 00:24:35.509239 0 15 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
3165 00:24:35.512907 0 15 28 | B1->B0 | 2626 2323 | 1 0 | (1 0) (1 0)
3166 00:24:35.518985 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3167 00:24:35.522774 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3168 00:24:35.525730 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3169 00:24:35.532185 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3170 00:24:35.536031 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3171 00:24:35.538916 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 00:24:35.545495 1 0 24 | B1->B0 | 2a2a 3b3b | 0 1 | (0 0) (1 1)
3173 00:24:35.548990 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 00:24:35.552621 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 00:24:35.556344 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 00:24:35.562453 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 00:24:35.565375 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 00:24:35.568724 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 00:24:35.575878 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 00:24:35.579465 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3181 00:24:35.582156 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3182 00:24:35.588794 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 00:24:35.592265 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 00:24:35.596141 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 00:24:35.602973 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 00:24:35.605373 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 00:24:35.609200 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 00:24:35.615366 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 00:24:35.618803 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 00:24:35.622126 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 00:24:35.628865 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 00:24:35.631794 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 00:24:35.635434 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 00:24:35.641848 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 00:24:35.645541 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 00:24:35.648331 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3197 00:24:35.655505 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3198 00:24:35.655585 Total UI for P1: 0, mck2ui 16
3199 00:24:35.661977 best dqsien dly found for B0: ( 1, 3, 24)
3200 00:24:35.665006 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 00:24:35.668463 Total UI for P1: 0, mck2ui 16
3202 00:24:35.671378 best dqsien dly found for B1: ( 1, 3, 26)
3203 00:24:35.675729 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3204 00:24:35.678240 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3205 00:24:35.678320
3206 00:24:35.682042 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3207 00:24:35.684976 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3208 00:24:35.688268 [Gating] SW calibration Done
3209 00:24:35.688348 ==
3210 00:24:35.691666 Dram Type= 6, Freq= 0, CH_1, rank 0
3211 00:24:35.694744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3212 00:24:35.698230 ==
3213 00:24:35.698309 RX Vref Scan: 0
3214 00:24:35.698372
3215 00:24:35.701561 RX Vref 0 -> 0, step: 1
3216 00:24:35.701641
3217 00:24:35.701703 RX Delay -40 -> 252, step: 8
3218 00:24:35.708587 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3219 00:24:35.712343 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3220 00:24:35.715112 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3221 00:24:35.718490 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3222 00:24:35.721915 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3223 00:24:35.728355 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3224 00:24:35.731865 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3225 00:24:35.735212 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3226 00:24:35.738315 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3227 00:24:35.741704 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3228 00:24:35.748096 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3229 00:24:35.752116 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3230 00:24:35.754747 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3231 00:24:35.758271 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3232 00:24:35.761994 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3233 00:24:35.768328 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3234 00:24:35.768409 ==
3235 00:24:35.771694 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 00:24:35.775153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 00:24:35.775234 ==
3238 00:24:35.775297 DQS Delay:
3239 00:24:35.778453 DQS0 = 0, DQS1 = 0
3240 00:24:35.778559 DQM Delay:
3241 00:24:35.781593 DQM0 = 118, DQM1 = 108
3242 00:24:35.781673 DQ Delay:
3243 00:24:35.784808 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3244 00:24:35.788112 DQ4 =115, DQ5 =131, DQ6 =123, DQ7 =115
3245 00:24:35.791314 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3246 00:24:35.794557 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =119
3247 00:24:35.794683
3248 00:24:35.794760
3249 00:24:35.797890 ==
3250 00:24:35.801275 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 00:24:35.804745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 00:24:35.804825 ==
3253 00:24:35.804888
3254 00:24:35.804945
3255 00:24:35.807893 TX Vref Scan disable
3256 00:24:35.807972 == TX Byte 0 ==
3257 00:24:35.811507 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3258 00:24:35.817906 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3259 00:24:35.817985 == TX Byte 1 ==
3260 00:24:35.821102 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3261 00:24:35.828440 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3262 00:24:35.828520 ==
3263 00:24:35.831148 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 00:24:35.834312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 00:24:35.834391 ==
3266 00:24:35.846871 TX Vref=22, minBit 10, minWin=24, winSum=417
3267 00:24:35.850144 TX Vref=24, minBit 11, minWin=25, winSum=424
3268 00:24:35.853485 TX Vref=26, minBit 9, minWin=25, winSum=429
3269 00:24:35.857199 TX Vref=28, minBit 11, minWin=25, winSum=433
3270 00:24:35.860493 TX Vref=30, minBit 11, minWin=25, winSum=432
3271 00:24:35.866581 TX Vref=32, minBit 9, minWin=25, winSum=427
3272 00:24:35.869976 [TxChooseVref] Worse bit 11, Min win 25, Win sum 433, Final Vref 28
3273 00:24:35.870057
3274 00:24:35.873910 Final TX Range 1 Vref 28
3275 00:24:35.873990
3276 00:24:35.874052 ==
3277 00:24:35.876769 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 00:24:35.883687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 00:24:35.883766 ==
3280 00:24:35.883828
3281 00:24:35.883885
3282 00:24:35.883941 TX Vref Scan disable
3283 00:24:35.887215 == TX Byte 0 ==
3284 00:24:35.890378 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3285 00:24:35.896796 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3286 00:24:35.896876 == TX Byte 1 ==
3287 00:24:35.900455 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3288 00:24:35.906622 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3289 00:24:35.906716
3290 00:24:35.906778 [DATLAT]
3291 00:24:35.906843 Freq=1200, CH1 RK0
3292 00:24:35.906941
3293 00:24:35.910528 DATLAT Default: 0xd
3294 00:24:35.910655 0, 0xFFFF, sum = 0
3295 00:24:35.913690 1, 0xFFFF, sum = 0
3296 00:24:35.913771 2, 0xFFFF, sum = 0
3297 00:24:35.916942 3, 0xFFFF, sum = 0
3298 00:24:35.919915 4, 0xFFFF, sum = 0
3299 00:24:35.919996 5, 0xFFFF, sum = 0
3300 00:24:35.923271 6, 0xFFFF, sum = 0
3301 00:24:35.923351 7, 0xFFFF, sum = 0
3302 00:24:35.926779 8, 0xFFFF, sum = 0
3303 00:24:35.926860 9, 0xFFFF, sum = 0
3304 00:24:35.930625 10, 0xFFFF, sum = 0
3305 00:24:35.930705 11, 0xFFFF, sum = 0
3306 00:24:35.933537 12, 0x0, sum = 1
3307 00:24:35.933617 13, 0x0, sum = 2
3308 00:24:35.937309 14, 0x0, sum = 3
3309 00:24:35.937388 15, 0x0, sum = 4
3310 00:24:35.937451 best_step = 13
3311 00:24:35.937509
3312 00:24:35.940328 ==
3313 00:24:35.943443 Dram Type= 6, Freq= 0, CH_1, rank 0
3314 00:24:35.947268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3315 00:24:35.947348 ==
3316 00:24:35.947409 RX Vref Scan: 1
3317 00:24:35.947467
3318 00:24:35.950170 Set Vref Range= 32 -> 127
3319 00:24:35.950248
3320 00:24:35.953588 RX Vref 32 -> 127, step: 1
3321 00:24:35.953667
3322 00:24:35.957167 RX Delay -21 -> 252, step: 4
3323 00:24:35.957247
3324 00:24:35.960037 Set Vref, RX VrefLevel [Byte0]: 32
3325 00:24:35.963584 [Byte1]: 32
3326 00:24:35.963663
3327 00:24:35.966965 Set Vref, RX VrefLevel [Byte0]: 33
3328 00:24:35.970330 [Byte1]: 33
3329 00:24:35.970408
3330 00:24:35.973911 Set Vref, RX VrefLevel [Byte0]: 34
3331 00:24:35.977030 [Byte1]: 34
3332 00:24:35.981215
3333 00:24:35.981293 Set Vref, RX VrefLevel [Byte0]: 35
3334 00:24:35.984631 [Byte1]: 35
3335 00:24:35.989331
3336 00:24:35.989409 Set Vref, RX VrefLevel [Byte0]: 36
3337 00:24:35.992571 [Byte1]: 36
3338 00:24:35.997007
3339 00:24:35.997088 Set Vref, RX VrefLevel [Byte0]: 37
3340 00:24:36.000614 [Byte1]: 37
3341 00:24:36.004928
3342 00:24:36.005006 Set Vref, RX VrefLevel [Byte0]: 38
3343 00:24:36.008655 [Byte1]: 38
3344 00:24:36.012708
3345 00:24:36.012787 Set Vref, RX VrefLevel [Byte0]: 39
3346 00:24:36.016436 [Byte1]: 39
3347 00:24:36.020795
3348 00:24:36.020874 Set Vref, RX VrefLevel [Byte0]: 40
3349 00:24:36.027215 [Byte1]: 40
3350 00:24:36.027294
3351 00:24:36.031071 Set Vref, RX VrefLevel [Byte0]: 41
3352 00:24:36.033973 [Byte1]: 41
3353 00:24:36.034052
3354 00:24:36.037655 Set Vref, RX VrefLevel [Byte0]: 42
3355 00:24:36.040407 [Byte1]: 42
3356 00:24:36.044376
3357 00:24:36.044454 Set Vref, RX VrefLevel [Byte0]: 43
3358 00:24:36.048136 [Byte1]: 43
3359 00:24:36.052858
3360 00:24:36.052937 Set Vref, RX VrefLevel [Byte0]: 44
3361 00:24:36.056078 [Byte1]: 44
3362 00:24:36.061151
3363 00:24:36.061230 Set Vref, RX VrefLevel [Byte0]: 45
3364 00:24:36.064113 [Byte1]: 45
3365 00:24:36.068375
3366 00:24:36.068453 Set Vref, RX VrefLevel [Byte0]: 46
3367 00:24:36.071513 [Byte1]: 46
3368 00:24:36.076674
3369 00:24:36.076753 Set Vref, RX VrefLevel [Byte0]: 47
3370 00:24:36.079465 [Byte1]: 47
3371 00:24:36.084133
3372 00:24:36.084211 Set Vref, RX VrefLevel [Byte0]: 48
3373 00:24:36.087333 [Byte1]: 48
3374 00:24:36.092461
3375 00:24:36.092540 Set Vref, RX VrefLevel [Byte0]: 49
3376 00:24:36.095227 [Byte1]: 49
3377 00:24:36.099911
3378 00:24:36.099989 Set Vref, RX VrefLevel [Byte0]: 50
3379 00:24:36.103729 [Byte1]: 50
3380 00:24:36.108048
3381 00:24:36.108126 Set Vref, RX VrefLevel [Byte0]: 51
3382 00:24:36.111249 [Byte1]: 51
3383 00:24:36.115883
3384 00:24:36.115961 Set Vref, RX VrefLevel [Byte0]: 52
3385 00:24:36.119188 [Byte1]: 52
3386 00:24:36.123863
3387 00:24:36.123980 Set Vref, RX VrefLevel [Byte0]: 53
3388 00:24:36.126846 [Byte1]: 53
3389 00:24:36.132098
3390 00:24:36.132176 Set Vref, RX VrefLevel [Byte0]: 54
3391 00:24:36.135013 [Byte1]: 54
3392 00:24:36.139632
3393 00:24:36.139710 Set Vref, RX VrefLevel [Byte0]: 55
3394 00:24:36.142933 [Byte1]: 55
3395 00:24:36.147420
3396 00:24:36.147515 Set Vref, RX VrefLevel [Byte0]: 56
3397 00:24:36.150847 [Byte1]: 56
3398 00:24:36.155269
3399 00:24:36.155347 Set Vref, RX VrefLevel [Byte0]: 57
3400 00:24:36.158862 [Byte1]: 57
3401 00:24:36.164161
3402 00:24:36.164240 Set Vref, RX VrefLevel [Byte0]: 58
3403 00:24:36.167412 [Byte1]: 58
3404 00:24:36.171363
3405 00:24:36.171441 Set Vref, RX VrefLevel [Byte0]: 59
3406 00:24:36.174447 [Byte1]: 59
3407 00:24:36.179001
3408 00:24:36.179080 Set Vref, RX VrefLevel [Byte0]: 60
3409 00:24:36.182321 [Byte1]: 60
3410 00:24:36.186927
3411 00:24:36.187007 Set Vref, RX VrefLevel [Byte0]: 61
3412 00:24:36.190840 [Byte1]: 61
3413 00:24:36.195128
3414 00:24:36.195210 Set Vref, RX VrefLevel [Byte0]: 62
3415 00:24:36.199377 [Byte1]: 62
3416 00:24:36.203201
3417 00:24:36.203280 Set Vref, RX VrefLevel [Byte0]: 63
3418 00:24:36.206208 [Byte1]: 63
3419 00:24:36.210655
3420 00:24:36.210735 Set Vref, RX VrefLevel [Byte0]: 64
3421 00:24:36.214476 [Byte1]: 64
3422 00:24:36.218941
3423 00:24:36.219020 Set Vref, RX VrefLevel [Byte0]: 65
3424 00:24:36.222626 [Byte1]: 65
3425 00:24:36.226712
3426 00:24:36.226791 Set Vref, RX VrefLevel [Byte0]: 66
3427 00:24:36.230063 [Byte1]: 66
3428 00:24:36.234758
3429 00:24:36.234837 Set Vref, RX VrefLevel [Byte0]: 67
3430 00:24:36.237808 [Byte1]: 67
3431 00:24:36.242641
3432 00:24:36.242720 Final RX Vref Byte 0 = 48 to rank0
3433 00:24:36.245839 Final RX Vref Byte 1 = 54 to rank0
3434 00:24:36.248921 Final RX Vref Byte 0 = 48 to rank1
3435 00:24:36.252639 Final RX Vref Byte 1 = 54 to rank1==
3436 00:24:36.256352 Dram Type= 6, Freq= 0, CH_1, rank 0
3437 00:24:36.262476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3438 00:24:36.262557 ==
3439 00:24:36.262625 DQS Delay:
3440 00:24:36.262685 DQS0 = 0, DQS1 = 0
3441 00:24:36.266385 DQM Delay:
3442 00:24:36.266464 DQM0 = 116, DQM1 = 110
3443 00:24:36.268880 DQ Delay:
3444 00:24:36.272513 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3445 00:24:36.275855 DQ4 =114, DQ5 =126, DQ6 =124, DQ7 =114
3446 00:24:36.279314 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =100
3447 00:24:36.282538 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3448 00:24:36.282623
3449 00:24:36.282685
3450 00:24:36.292424 [DQSOSCAuto] RK0, (LSB)MR18= 0x5f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 408 ps
3451 00:24:36.292504 CH1 RK0: MR19=403, MR18=5F9
3452 00:24:36.299310 CH1_RK0: MR19=0x403, MR18=0x5F9, DQSOSC=408, MR23=63, INC=39, DEC=26
3453 00:24:36.299390
3454 00:24:36.302091 ----->DramcWriteLeveling(PI) begin...
3455 00:24:36.302172 ==
3456 00:24:36.305788 Dram Type= 6, Freq= 0, CH_1, rank 1
3457 00:24:36.308681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3458 00:24:36.312028 ==
3459 00:24:36.315750 Write leveling (Byte 0): 25 => 25
3460 00:24:36.315830 Write leveling (Byte 1): 26 => 26
3461 00:24:36.318918 DramcWriteLeveling(PI) end<-----
3462 00:24:36.318997
3463 00:24:36.319058 ==
3464 00:24:36.321997 Dram Type= 6, Freq= 0, CH_1, rank 1
3465 00:24:36.329068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3466 00:24:36.329148 ==
3467 00:24:36.331682 [Gating] SW mode calibration
3468 00:24:36.338210 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3469 00:24:36.341798 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3470 00:24:36.348410 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 00:24:36.352010 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3472 00:24:36.355436 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3473 00:24:36.361579 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3474 00:24:36.364668 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3475 00:24:36.368350 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3476 00:24:36.374468 0 15 24 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (0 0)
3477 00:24:36.378526 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3478 00:24:36.381906 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 00:24:36.387894 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3480 00:24:36.390946 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3481 00:24:36.394368 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3482 00:24:36.400716 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 00:24:36.404021 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 00:24:36.407408 1 0 24 | B1->B0 | 3434 2424 | 0 0 | (0 0) (0 0)
3485 00:24:36.414032 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3486 00:24:36.417305 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 00:24:36.421004 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 00:24:36.427511 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 00:24:36.430771 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 00:24:36.434318 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 00:24:36.440738 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 00:24:36.443984 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3493 00:24:36.447323 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3494 00:24:36.454452 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 00:24:36.456951 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 00:24:36.460372 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 00:24:36.467363 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 00:24:36.470542 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 00:24:36.473797 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 00:24:36.480173 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 00:24:36.483326 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 00:24:36.486680 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 00:24:36.493180 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 00:24:36.497110 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 00:24:36.500505 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 00:24:36.506500 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 00:24:36.509738 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 00:24:36.513518 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3509 00:24:36.519596 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3510 00:24:36.519676 Total UI for P1: 0, mck2ui 16
3511 00:24:36.526374 best dqsien dly found for B1: ( 1, 3, 24)
3512 00:24:36.529781 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 00:24:36.532827 Total UI for P1: 0, mck2ui 16
3514 00:24:36.536203 best dqsien dly found for B0: ( 1, 3, 28)
3515 00:24:36.539551 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3516 00:24:36.542862 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3517 00:24:36.542941
3518 00:24:36.546737 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3519 00:24:36.549569 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3520 00:24:36.553076 [Gating] SW calibration Done
3521 00:24:36.553155 ==
3522 00:24:36.556690 Dram Type= 6, Freq= 0, CH_1, rank 1
3523 00:24:36.559490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3524 00:24:36.562644 ==
3525 00:24:36.562723 RX Vref Scan: 0
3526 00:24:36.562786
3527 00:24:36.566139 RX Vref 0 -> 0, step: 1
3528 00:24:36.566219
3529 00:24:36.569486 RX Delay -40 -> 252, step: 8
3530 00:24:36.573006 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3531 00:24:36.575834 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3532 00:24:36.579207 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3533 00:24:36.582740 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3534 00:24:36.588709 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3535 00:24:36.592553 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3536 00:24:36.595680 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3537 00:24:36.599218 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3538 00:24:36.602243 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3539 00:24:36.608667 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3540 00:24:36.612192 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3541 00:24:36.615642 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3542 00:24:36.618800 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3543 00:24:36.625407 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3544 00:24:36.628613 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3545 00:24:36.631577 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3546 00:24:36.631656 ==
3547 00:24:36.635143 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 00:24:36.638520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 00:24:36.638680 ==
3550 00:24:36.641984 DQS Delay:
3551 00:24:36.642063 DQS0 = 0, DQS1 = 0
3552 00:24:36.645070 DQM Delay:
3553 00:24:36.645150 DQM0 = 116, DQM1 = 110
3554 00:24:36.645213 DQ Delay:
3555 00:24:36.651513 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =111
3556 00:24:36.654962 DQ4 =115, DQ5 =123, DQ6 =127, DQ7 =115
3557 00:24:36.658401 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3558 00:24:36.661845 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3559 00:24:36.661925
3560 00:24:36.661987
3561 00:24:36.662045 ==
3562 00:24:36.665647 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 00:24:36.668100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 00:24:36.668180 ==
3565 00:24:36.668243
3566 00:24:36.668301
3567 00:24:36.671356 TX Vref Scan disable
3568 00:24:36.675113 == TX Byte 0 ==
3569 00:24:36.677934 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3570 00:24:36.681581 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3571 00:24:36.684240 == TX Byte 1 ==
3572 00:24:36.687897 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3573 00:24:36.691096 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3574 00:24:36.691176 ==
3575 00:24:36.694408 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 00:24:36.700797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 00:24:36.700877 ==
3578 00:24:36.711352 TX Vref=22, minBit 0, minWin=26, winSum=425
3579 00:24:36.715139 TX Vref=24, minBit 1, minWin=26, winSum=430
3580 00:24:36.718203 TX Vref=26, minBit 9, minWin=26, winSum=433
3581 00:24:36.720922 TX Vref=28, minBit 9, minWin=26, winSum=435
3582 00:24:36.724699 TX Vref=30, minBit 9, minWin=26, winSum=436
3583 00:24:36.731172 TX Vref=32, minBit 4, minWin=26, winSum=431
3584 00:24:36.734351 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 30
3585 00:24:36.734431
3586 00:24:36.737929 Final TX Range 1 Vref 30
3587 00:24:36.738008
3588 00:24:36.738070 ==
3589 00:24:36.740810 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 00:24:36.744051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 00:24:36.748279 ==
3592 00:24:36.748359
3593 00:24:36.748421
3594 00:24:36.748479 TX Vref Scan disable
3595 00:24:36.751202 == TX Byte 0 ==
3596 00:24:36.754245 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3597 00:24:36.760851 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3598 00:24:36.760959 == TX Byte 1 ==
3599 00:24:36.764390 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3600 00:24:36.770756 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3601 00:24:36.770836
3602 00:24:36.770898 [DATLAT]
3603 00:24:36.770956 Freq=1200, CH1 RK1
3604 00:24:36.771012
3605 00:24:36.773994 DATLAT Default: 0xd
3606 00:24:36.777275 0, 0xFFFF, sum = 0
3607 00:24:36.777356 1, 0xFFFF, sum = 0
3608 00:24:36.781017 2, 0xFFFF, sum = 0
3609 00:24:36.781098 3, 0xFFFF, sum = 0
3610 00:24:36.783930 4, 0xFFFF, sum = 0
3611 00:24:36.784011 5, 0xFFFF, sum = 0
3612 00:24:36.787603 6, 0xFFFF, sum = 0
3613 00:24:36.787684 7, 0xFFFF, sum = 0
3614 00:24:36.790397 8, 0xFFFF, sum = 0
3615 00:24:36.790478 9, 0xFFFF, sum = 0
3616 00:24:36.794164 10, 0xFFFF, sum = 0
3617 00:24:36.794245 11, 0xFFFF, sum = 0
3618 00:24:36.797096 12, 0x0, sum = 1
3619 00:24:36.797177 13, 0x0, sum = 2
3620 00:24:36.800491 14, 0x0, sum = 3
3621 00:24:36.800572 15, 0x0, sum = 4
3622 00:24:36.803798 best_step = 13
3623 00:24:36.803878
3624 00:24:36.803940 ==
3625 00:24:36.806954 Dram Type= 6, Freq= 0, CH_1, rank 1
3626 00:24:36.810311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3627 00:24:36.810392 ==
3628 00:24:36.814279 RX Vref Scan: 0
3629 00:24:36.814359
3630 00:24:36.814422 RX Vref 0 -> 0, step: 1
3631 00:24:36.814480
3632 00:24:36.817074 RX Delay -21 -> 252, step: 4
3633 00:24:36.823429 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3634 00:24:36.827041 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3635 00:24:36.830326 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3636 00:24:36.833280 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3637 00:24:36.836827 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3638 00:24:36.843268 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3639 00:24:36.847038 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3640 00:24:36.849911 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3641 00:24:36.853138 iDelay=199, Bit 8, Center 100 (35 ~ 166) 132
3642 00:24:36.857503 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3643 00:24:36.863151 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3644 00:24:36.866305 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3645 00:24:36.869613 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3646 00:24:36.873129 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3647 00:24:36.880110 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3648 00:24:36.882770 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3649 00:24:36.882850 ==
3650 00:24:36.886489 Dram Type= 6, Freq= 0, CH_1, rank 1
3651 00:24:36.889935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3652 00:24:36.890016 ==
3653 00:24:36.892937 DQS Delay:
3654 00:24:36.893016 DQS0 = 0, DQS1 = 0
3655 00:24:36.893079 DQM Delay:
3656 00:24:36.896428 DQM0 = 117, DQM1 = 110
3657 00:24:36.896508 DQ Delay:
3658 00:24:36.899457 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3659 00:24:36.902503 DQ4 =114, DQ5 =128, DQ6 =130, DQ7 =116
3660 00:24:36.906037 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =100
3661 00:24:36.912726 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3662 00:24:36.912806
3663 00:24:36.912868
3664 00:24:36.919034 [DQSOSCAuto] RK1, (LSB)MR18= 0xf4f0, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
3665 00:24:36.922525 CH1 RK1: MR19=303, MR18=F4F0
3666 00:24:36.929229 CH1_RK1: MR19=0x303, MR18=0xF4F0, DQSOSC=415, MR23=63, INC=38, DEC=25
3667 00:24:36.932192 [RxdqsGatingPostProcess] freq 1200
3668 00:24:36.935722 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3669 00:24:36.938883 best DQS0 dly(2T, 0.5T) = (0, 11)
3670 00:24:36.942437 best DQS1 dly(2T, 0.5T) = (0, 11)
3671 00:24:36.945929 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3672 00:24:36.948497 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3673 00:24:36.951896 best DQS0 dly(2T, 0.5T) = (0, 11)
3674 00:24:36.955366 best DQS1 dly(2T, 0.5T) = (0, 11)
3675 00:24:36.959466 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3676 00:24:36.962020 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3677 00:24:36.965346 Pre-setting of DQS Precalculation
3678 00:24:36.971761 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3679 00:24:36.978473 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3680 00:24:36.985540 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3681 00:24:36.985621
3682 00:24:36.985683
3683 00:24:36.988029 [Calibration Summary] 2400 Mbps
3684 00:24:36.988108 CH 0, Rank 0
3685 00:24:36.991317 SW Impedance : PASS
3686 00:24:36.994829 DUTY Scan : NO K
3687 00:24:36.994908 ZQ Calibration : PASS
3688 00:24:36.998099 Jitter Meter : NO K
3689 00:24:37.001249 CBT Training : PASS
3690 00:24:37.001329 Write leveling : PASS
3691 00:24:37.005046 RX DQS gating : PASS
3692 00:24:37.008203 RX DQ/DQS(RDDQC) : PASS
3693 00:24:37.008283 TX DQ/DQS : PASS
3694 00:24:37.012073 RX DATLAT : PASS
3695 00:24:37.012153 RX DQ/DQS(Engine): PASS
3696 00:24:37.014540 TX OE : NO K
3697 00:24:37.014626 All Pass.
3698 00:24:37.014689
3699 00:24:37.018181 CH 0, Rank 1
3700 00:24:37.021373 SW Impedance : PASS
3701 00:24:37.021453 DUTY Scan : NO K
3702 00:24:37.024370 ZQ Calibration : PASS
3703 00:24:37.024450 Jitter Meter : NO K
3704 00:24:37.027949 CBT Training : PASS
3705 00:24:37.031455 Write leveling : PASS
3706 00:24:37.031535 RX DQS gating : PASS
3707 00:24:37.034469 RX DQ/DQS(RDDQC) : PASS
3708 00:24:37.037897 TX DQ/DQS : PASS
3709 00:24:37.037977 RX DATLAT : PASS
3710 00:24:37.041145 RX DQ/DQS(Engine): PASS
3711 00:24:37.044339 TX OE : NO K
3712 00:24:37.044418 All Pass.
3713 00:24:37.044480
3714 00:24:37.044538 CH 1, Rank 0
3715 00:24:37.047580 SW Impedance : PASS
3716 00:24:37.051310 DUTY Scan : NO K
3717 00:24:37.051390 ZQ Calibration : PASS
3718 00:24:37.054155 Jitter Meter : NO K
3719 00:24:37.057707 CBT Training : PASS
3720 00:24:37.057786 Write leveling : PASS
3721 00:24:37.060682 RX DQS gating : PASS
3722 00:24:37.064251 RX DQ/DQS(RDDQC) : PASS
3723 00:24:37.064331 TX DQ/DQS : PASS
3724 00:24:37.067543 RX DATLAT : PASS
3725 00:24:37.071119 RX DQ/DQS(Engine): PASS
3726 00:24:37.071199 TX OE : NO K
3727 00:24:37.074229 All Pass.
3728 00:24:37.074308
3729 00:24:37.074370 CH 1, Rank 1
3730 00:24:37.077158 SW Impedance : PASS
3731 00:24:37.077238 DUTY Scan : NO K
3732 00:24:37.080772 ZQ Calibration : PASS
3733 00:24:37.083691 Jitter Meter : NO K
3734 00:24:37.083771 CBT Training : PASS
3735 00:24:37.087229 Write leveling : PASS
3736 00:24:37.090495 RX DQS gating : PASS
3737 00:24:37.090574 RX DQ/DQS(RDDQC) : PASS
3738 00:24:37.093744 TX DQ/DQS : PASS
3739 00:24:37.097094 RX DATLAT : PASS
3740 00:24:37.097205 RX DQ/DQS(Engine): PASS
3741 00:24:37.100370 TX OE : NO K
3742 00:24:37.100450 All Pass.
3743 00:24:37.100513
3744 00:24:37.103518 DramC Write-DBI off
3745 00:24:37.107411 PER_BANK_REFRESH: Hybrid Mode
3746 00:24:37.107491 TX_TRACKING: ON
3747 00:24:37.116929 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3748 00:24:37.119727 [FAST_K] Save calibration result to emmc
3749 00:24:37.123542 dramc_set_vcore_voltage set vcore to 650000
3750 00:24:37.126355 Read voltage for 600, 5
3751 00:24:37.126434 Vio18 = 0
3752 00:24:37.126497 Vcore = 650000
3753 00:24:37.130070 Vdram = 0
3754 00:24:37.130149 Vddq = 0
3755 00:24:37.130211 Vmddr = 0
3756 00:24:37.136472 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3757 00:24:37.140457 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3758 00:24:37.143511 MEM_TYPE=3, freq_sel=19
3759 00:24:37.146413 sv_algorithm_assistance_LP4_1600
3760 00:24:37.149336 ============ PULL DRAM RESETB DOWN ============
3761 00:24:37.152696 ========== PULL DRAM RESETB DOWN end =========
3762 00:24:37.159550 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3763 00:24:37.162524 ===================================
3764 00:24:37.165781 LPDDR4 DRAM CONFIGURATION
3765 00:24:37.169140 ===================================
3766 00:24:37.169220 EX_ROW_EN[0] = 0x0
3767 00:24:37.172868 EX_ROW_EN[1] = 0x0
3768 00:24:37.172948 LP4Y_EN = 0x0
3769 00:24:37.176017 WORK_FSP = 0x0
3770 00:24:37.176096 WL = 0x2
3771 00:24:37.179088 RL = 0x2
3772 00:24:37.179167 BL = 0x2
3773 00:24:37.182623 RPST = 0x0
3774 00:24:37.182715 RD_PRE = 0x0
3775 00:24:37.185532 WR_PRE = 0x1
3776 00:24:37.185611 WR_PST = 0x0
3777 00:24:37.189064 DBI_WR = 0x0
3778 00:24:37.192359 DBI_RD = 0x0
3779 00:24:37.192438 OTF = 0x1
3780 00:24:37.195403 ===================================
3781 00:24:37.199207 ===================================
3782 00:24:37.199286 ANA top config
3783 00:24:37.202298 ===================================
3784 00:24:37.205412 DLL_ASYNC_EN = 0
3785 00:24:37.209441 ALL_SLAVE_EN = 1
3786 00:24:37.212019 NEW_RANK_MODE = 1
3787 00:24:37.215271 DLL_IDLE_MODE = 1
3788 00:24:37.215351 LP45_APHY_COMB_EN = 1
3789 00:24:37.218548 TX_ODT_DIS = 1
3790 00:24:37.221930 NEW_8X_MODE = 1
3791 00:24:37.225382 ===================================
3792 00:24:37.228965 ===================================
3793 00:24:37.231764 data_rate = 1200
3794 00:24:37.235187 CKR = 1
3795 00:24:37.238518 DQ_P2S_RATIO = 8
3796 00:24:37.242053 ===================================
3797 00:24:37.242132 CA_P2S_RATIO = 8
3798 00:24:37.244834 DQ_CA_OPEN = 0
3799 00:24:37.248170 DQ_SEMI_OPEN = 0
3800 00:24:37.251599 CA_SEMI_OPEN = 0
3801 00:24:37.254917 CA_FULL_RATE = 0
3802 00:24:37.258087 DQ_CKDIV4_EN = 1
3803 00:24:37.258166 CA_CKDIV4_EN = 1
3804 00:24:37.261552 CA_PREDIV_EN = 0
3805 00:24:37.265514 PH8_DLY = 0
3806 00:24:37.268138 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3807 00:24:37.271239 DQ_AAMCK_DIV = 4
3808 00:24:37.274629 CA_AAMCK_DIV = 4
3809 00:24:37.274708 CA_ADMCK_DIV = 4
3810 00:24:37.278429 DQ_TRACK_CA_EN = 0
3811 00:24:37.281673 CA_PICK = 600
3812 00:24:37.284383 CA_MCKIO = 600
3813 00:24:37.288152 MCKIO_SEMI = 0
3814 00:24:37.291361 PLL_FREQ = 2288
3815 00:24:37.295023 DQ_UI_PI_RATIO = 32
3816 00:24:37.295102 CA_UI_PI_RATIO = 0
3817 00:24:37.297826 ===================================
3818 00:24:37.301460 ===================================
3819 00:24:37.304524 memory_type:LPDDR4
3820 00:24:37.307610 GP_NUM : 10
3821 00:24:37.307688 SRAM_EN : 1
3822 00:24:37.311532 MD32_EN : 0
3823 00:24:37.314300 ===================================
3824 00:24:37.317991 [ANA_INIT] >>>>>>>>>>>>>>
3825 00:24:37.320680 <<<<<< [CONFIGURE PHASE]: ANA_TX
3826 00:24:37.324211 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3827 00:24:37.327722 ===================================
3828 00:24:37.327802 data_rate = 1200,PCW = 0X5800
3829 00:24:37.331452 ===================================
3830 00:24:37.334303 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3831 00:24:37.340921 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3832 00:24:37.347235 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3833 00:24:37.351009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3834 00:24:37.353946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3835 00:24:37.357927 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3836 00:24:37.360583 [ANA_INIT] flow start
3837 00:24:37.364224 [ANA_INIT] PLL >>>>>>>>
3838 00:24:37.364303 [ANA_INIT] PLL <<<<<<<<
3839 00:24:37.367277 [ANA_INIT] MIDPI >>>>>>>>
3840 00:24:37.370909 [ANA_INIT] MIDPI <<<<<<<<
3841 00:24:37.370988 [ANA_INIT] DLL >>>>>>>>
3842 00:24:37.374016 [ANA_INIT] flow end
3843 00:24:37.377290 ============ LP4 DIFF to SE enter ============
3844 00:24:37.380791 ============ LP4 DIFF to SE exit ============
3845 00:24:37.383978 [ANA_INIT] <<<<<<<<<<<<<
3846 00:24:37.387431 [Flow] Enable top DCM control >>>>>
3847 00:24:37.390219 [Flow] Enable top DCM control <<<<<
3848 00:24:37.393743 Enable DLL master slave shuffle
3849 00:24:37.400535 ==============================================================
3850 00:24:37.400615 Gating Mode config
3851 00:24:37.407099 ==============================================================
3852 00:24:37.410556 Config description:
3853 00:24:37.416688 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3854 00:24:37.423326 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3855 00:24:37.430239 SELPH_MODE 0: By rank 1: By Phase
3856 00:24:37.436535 ==============================================================
3857 00:24:37.436686 GAT_TRACK_EN = 1
3858 00:24:37.440217 RX_GATING_MODE = 2
3859 00:24:37.443173 RX_GATING_TRACK_MODE = 2
3860 00:24:37.446185 SELPH_MODE = 1
3861 00:24:37.449883 PICG_EARLY_EN = 1
3862 00:24:37.453144 VALID_LAT_VALUE = 1
3863 00:24:37.459782 ==============================================================
3864 00:24:37.463182 Enter into Gating configuration >>>>
3865 00:24:37.466226 Exit from Gating configuration <<<<
3866 00:24:37.469639 Enter into DVFS_PRE_config >>>>>
3867 00:24:37.479891 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3868 00:24:37.482529 Exit from DVFS_PRE_config <<<<<
3869 00:24:37.486319 Enter into PICG configuration >>>>
3870 00:24:37.489923 Exit from PICG configuration <<<<
3871 00:24:37.492652 [RX_INPUT] configuration >>>>>
3872 00:24:37.496041 [RX_INPUT] configuration <<<<<
3873 00:24:37.499152 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3874 00:24:37.505978 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3875 00:24:37.512818 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3876 00:24:37.519012 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3877 00:24:37.522629 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3878 00:24:37.528994 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3879 00:24:37.532134 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3880 00:24:37.538660 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3881 00:24:37.541951 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3882 00:24:37.545285 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3883 00:24:37.548394 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3884 00:24:37.555053 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3885 00:24:37.558855 ===================================
3886 00:24:37.561750 LPDDR4 DRAM CONFIGURATION
3887 00:24:37.565762 ===================================
3888 00:24:37.565842 EX_ROW_EN[0] = 0x0
3889 00:24:37.568487 EX_ROW_EN[1] = 0x0
3890 00:24:37.568566 LP4Y_EN = 0x0
3891 00:24:37.571584 WORK_FSP = 0x0
3892 00:24:37.571663 WL = 0x2
3893 00:24:37.575005 RL = 0x2
3894 00:24:37.575083 BL = 0x2
3895 00:24:37.578334 RPST = 0x0
3896 00:24:37.578413 RD_PRE = 0x0
3897 00:24:37.581291 WR_PRE = 0x1
3898 00:24:37.581371 WR_PST = 0x0
3899 00:24:37.585028 DBI_WR = 0x0
3900 00:24:37.588199 DBI_RD = 0x0
3901 00:24:37.588277 OTF = 0x1
3902 00:24:37.591306 ===================================
3903 00:24:37.595149 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3904 00:24:37.598067 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3905 00:24:37.604551 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3906 00:24:37.607973 ===================================
3907 00:24:37.610943 LPDDR4 DRAM CONFIGURATION
3908 00:24:37.614657 ===================================
3909 00:24:37.614750 EX_ROW_EN[0] = 0x10
3910 00:24:37.618115 EX_ROW_EN[1] = 0x0
3911 00:24:37.618194 LP4Y_EN = 0x0
3912 00:24:37.621146 WORK_FSP = 0x0
3913 00:24:37.621225 WL = 0x2
3914 00:24:37.624428 RL = 0x2
3915 00:24:37.624507 BL = 0x2
3916 00:24:37.627857 RPST = 0x0
3917 00:24:37.627936 RD_PRE = 0x0
3918 00:24:37.630833 WR_PRE = 0x1
3919 00:24:37.634226 WR_PST = 0x0
3920 00:24:37.634305 DBI_WR = 0x0
3921 00:24:37.637536 DBI_RD = 0x0
3922 00:24:37.637615 OTF = 0x1
3923 00:24:37.640697 ===================================
3924 00:24:37.647690 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3925 00:24:37.651621 nWR fixed to 30
3926 00:24:37.654483 [ModeRegInit_LP4] CH0 RK0
3927 00:24:37.654588 [ModeRegInit_LP4] CH0 RK1
3928 00:24:37.658015 [ModeRegInit_LP4] CH1 RK0
3929 00:24:37.661031 [ModeRegInit_LP4] CH1 RK1
3930 00:24:37.661109 match AC timing 17
3931 00:24:37.667661 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3932 00:24:37.670864 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3933 00:24:37.674107 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3934 00:24:37.680739 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3935 00:24:37.683956 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3936 00:24:37.684035 ==
3937 00:24:37.687897 Dram Type= 6, Freq= 0, CH_0, rank 0
3938 00:24:37.690904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3939 00:24:37.690983 ==
3940 00:24:37.697142 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3941 00:24:37.704105 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3942 00:24:37.707035 [CA 0] Center 36 (6~66) winsize 61
3943 00:24:37.710868 [CA 1] Center 36 (6~66) winsize 61
3944 00:24:37.713875 [CA 2] Center 34 (3~65) winsize 63
3945 00:24:37.716952 [CA 3] Center 34 (3~65) winsize 63
3946 00:24:37.720767 [CA 4] Center 33 (3~64) winsize 62
3947 00:24:37.723698 [CA 5] Center 33 (3~64) winsize 62
3948 00:24:37.723776
3949 00:24:37.727060 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3950 00:24:37.727163
3951 00:24:37.730254 [CATrainingPosCal] consider 1 rank data
3952 00:24:37.733742 u2DelayCellTimex100 = 270/100 ps
3953 00:24:37.737054 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3954 00:24:37.740554 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3955 00:24:37.743773 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
3956 00:24:37.746956 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3957 00:24:37.753415 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3958 00:24:37.756796 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3959 00:24:37.756876
3960 00:24:37.760525 CA PerBit enable=1, Macro0, CA PI delay=33
3961 00:24:37.760605
3962 00:24:37.763139 [CBTSetCACLKResult] CA Dly = 33
3963 00:24:37.763219 CS Dly: 5 (0~36)
3964 00:24:37.763281 ==
3965 00:24:37.766653 Dram Type= 6, Freq= 0, CH_0, rank 1
3966 00:24:37.773651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3967 00:24:37.773731 ==
3968 00:24:37.776862 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3969 00:24:37.782998 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3970 00:24:37.786494 [CA 0] Center 36 (6~66) winsize 61
3971 00:24:37.789690 [CA 1] Center 36 (6~66) winsize 61
3972 00:24:37.792866 [CA 2] Center 34 (4~64) winsize 61
3973 00:24:37.797196 [CA 3] Center 34 (4~64) winsize 61
3974 00:24:37.799814 [CA 4] Center 33 (2~64) winsize 63
3975 00:24:37.803190 [CA 5] Center 33 (2~64) winsize 63
3976 00:24:37.803270
3977 00:24:37.806236 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3978 00:24:37.806316
3979 00:24:37.809630 [CATrainingPosCal] consider 2 rank data
3980 00:24:37.813130 u2DelayCellTimex100 = 270/100 ps
3981 00:24:37.816519 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3982 00:24:37.823297 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3983 00:24:37.826228 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3984 00:24:37.829450 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3985 00:24:37.832684 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3986 00:24:37.836147 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3987 00:24:37.836226
3988 00:24:37.839174 CA PerBit enable=1, Macro0, CA PI delay=33
3989 00:24:37.839254
3990 00:24:37.842824 [CBTSetCACLKResult] CA Dly = 33
3991 00:24:37.845849 CS Dly: 6 (0~39)
3992 00:24:37.845928
3993 00:24:37.849173 ----->DramcWriteLeveling(PI) begin...
3994 00:24:37.849254 ==
3995 00:24:37.852738 Dram Type= 6, Freq= 0, CH_0, rank 0
3996 00:24:37.855778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3997 00:24:37.855859 ==
3998 00:24:37.859111 Write leveling (Byte 0): 36 => 36
3999 00:24:37.862534 Write leveling (Byte 1): 30 => 30
4000 00:24:37.865886 DramcWriteLeveling(PI) end<-----
4001 00:24:37.865966
4002 00:24:37.866027 ==
4003 00:24:37.869234 Dram Type= 6, Freq= 0, CH_0, rank 0
4004 00:24:37.872851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4005 00:24:37.872931 ==
4006 00:24:37.875401 [Gating] SW mode calibration
4007 00:24:37.882275 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4008 00:24:37.888453 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4009 00:24:37.892180 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4010 00:24:37.895516 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4011 00:24:37.902219 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4012 00:24:37.905243 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4013 00:24:37.909611 0 9 16 | B1->B0 | 2e2e 2828 | 0 0 | (1 1) (0 0)
4014 00:24:37.915005 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 00:24:37.918572 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 00:24:37.921601 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 00:24:37.928109 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 00:24:37.931941 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 00:24:37.934804 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 00:24:37.941397 0 10 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
4021 00:24:37.944818 0 10 16 | B1->B0 | 3636 4444 | 0 0 | (0 0) (0 0)
4022 00:24:37.948076 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 00:24:37.954471 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 00:24:37.958273 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 00:24:37.961644 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 00:24:37.967718 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 00:24:37.971303 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 00:24:37.975095 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4029 00:24:37.981081 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4030 00:24:37.984163 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 00:24:37.987990 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 00:24:37.994585 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 00:24:37.997603 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 00:24:38.000850 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 00:24:38.007963 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 00:24:38.011128 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 00:24:38.014446 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 00:24:38.020744 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 00:24:38.024146 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 00:24:38.027557 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 00:24:38.034107 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 00:24:38.036976 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 00:24:38.040960 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 00:24:38.047379 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 00:24:38.050047 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 00:24:38.053696 Total UI for P1: 0, mck2ui 16
4047 00:24:38.056784 best dqsien dly found for B0: ( 0, 13, 14)
4048 00:24:38.060256 Total UI for P1: 0, mck2ui 16
4049 00:24:38.063339 best dqsien dly found for B1: ( 0, 13, 14)
4050 00:24:38.066926 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4051 00:24:38.070193 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4052 00:24:38.070273
4053 00:24:38.073609 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4054 00:24:38.079754 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4055 00:24:38.079834 [Gating] SW calibration Done
4056 00:24:38.079896 ==
4057 00:24:38.083789 Dram Type= 6, Freq= 0, CH_0, rank 0
4058 00:24:38.089905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4059 00:24:38.089985 ==
4060 00:24:38.090053 RX Vref Scan: 0
4061 00:24:38.090110
4062 00:24:38.093039 RX Vref 0 -> 0, step: 1
4063 00:24:38.093119
4064 00:24:38.096461 RX Delay -230 -> 252, step: 16
4065 00:24:38.100092 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4066 00:24:38.103300 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4067 00:24:38.109566 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4068 00:24:38.112687 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4069 00:24:38.116035 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4070 00:24:38.119525 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4071 00:24:38.122955 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4072 00:24:38.129315 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4073 00:24:38.132373 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4074 00:24:38.136236 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4075 00:24:38.139082 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4076 00:24:38.145629 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4077 00:24:38.148928 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4078 00:24:38.152776 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4079 00:24:38.156395 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4080 00:24:38.162091 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4081 00:24:38.162171 ==
4082 00:24:38.166317 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 00:24:38.168877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 00:24:38.168957 ==
4085 00:24:38.169018 DQS Delay:
4086 00:24:38.172285 DQS0 = 0, DQS1 = 0
4087 00:24:38.172363 DQM Delay:
4088 00:24:38.175289 DQM0 = 42, DQM1 = 30
4089 00:24:38.175367 DQ Delay:
4090 00:24:38.178650 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4091 00:24:38.182630 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4092 00:24:38.185638 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4093 00:24:38.188434 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4094 00:24:38.188513
4095 00:24:38.188573
4096 00:24:38.188630 ==
4097 00:24:38.192195 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 00:24:38.195408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 00:24:38.198684 ==
4100 00:24:38.198763
4101 00:24:38.198824
4102 00:24:38.198882 TX Vref Scan disable
4103 00:24:38.202061 == TX Byte 0 ==
4104 00:24:38.205176 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4105 00:24:38.212214 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4106 00:24:38.212294 == TX Byte 1 ==
4107 00:24:38.214887 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4108 00:24:38.222105 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4109 00:24:38.222187 ==
4110 00:24:38.225072 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 00:24:38.228458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 00:24:38.228563 ==
4113 00:24:38.228653
4114 00:24:38.228738
4115 00:24:38.231720 TX Vref Scan disable
4116 00:24:38.234890 == TX Byte 0 ==
4117 00:24:38.237956 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4118 00:24:38.241263 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4119 00:24:38.244898 == TX Byte 1 ==
4120 00:24:38.247971 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4121 00:24:38.251364 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4122 00:24:38.251460
4123 00:24:38.254411 [DATLAT]
4124 00:24:38.254490 Freq=600, CH0 RK0
4125 00:24:38.254552
4126 00:24:38.257884 DATLAT Default: 0x9
4127 00:24:38.257963 0, 0xFFFF, sum = 0
4128 00:24:38.261275 1, 0xFFFF, sum = 0
4129 00:24:38.261364 2, 0xFFFF, sum = 0
4130 00:24:38.264533 3, 0xFFFF, sum = 0
4131 00:24:38.264613 4, 0xFFFF, sum = 0
4132 00:24:38.268223 5, 0xFFFF, sum = 0
4133 00:24:38.268303 6, 0xFFFF, sum = 0
4134 00:24:38.271420 7, 0xFFFF, sum = 0
4135 00:24:38.271500 8, 0x0, sum = 1
4136 00:24:38.274436 9, 0x0, sum = 2
4137 00:24:38.274516 10, 0x0, sum = 3
4138 00:24:38.277516 11, 0x0, sum = 4
4139 00:24:38.277597 best_step = 9
4140 00:24:38.277658
4141 00:24:38.277715 ==
4142 00:24:38.281006 Dram Type= 6, Freq= 0, CH_0, rank 0
4143 00:24:38.284392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 00:24:38.284471 ==
4145 00:24:38.287703 RX Vref Scan: 1
4146 00:24:38.287782
4147 00:24:38.290991 RX Vref 0 -> 0, step: 1
4148 00:24:38.291070
4149 00:24:38.291131 RX Delay -195 -> 252, step: 8
4150 00:24:38.293960
4151 00:24:38.294038 Set Vref, RX VrefLevel [Byte0]: 60
4152 00:24:38.297539 [Byte1]: 57
4153 00:24:38.302555
4154 00:24:38.305718 Final RX Vref Byte 0 = 60 to rank0
4155 00:24:38.305797 Final RX Vref Byte 1 = 57 to rank0
4156 00:24:38.309606 Final RX Vref Byte 0 = 60 to rank1
4157 00:24:38.312085 Final RX Vref Byte 1 = 57 to rank1==
4158 00:24:38.316214 Dram Type= 6, Freq= 0, CH_0, rank 0
4159 00:24:38.322095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 00:24:38.322174 ==
4161 00:24:38.322236 DQS Delay:
4162 00:24:38.325662 DQS0 = 0, DQS1 = 0
4163 00:24:38.325741 DQM Delay:
4164 00:24:38.325803 DQM0 = 43, DQM1 = 32
4165 00:24:38.328848 DQ Delay:
4166 00:24:38.332217 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4167 00:24:38.335177 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4168 00:24:38.338495 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4169 00:24:38.341924 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4170 00:24:38.342003
4171 00:24:38.342063
4172 00:24:38.348436 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a42, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 389 ps
4173 00:24:38.351667 CH0 RK0: MR19=808, MR18=6A42
4174 00:24:38.358201 CH0_RK0: MR19=0x808, MR18=0x6A42, DQSOSC=389, MR23=63, INC=173, DEC=115
4175 00:24:38.358281
4176 00:24:38.362327 ----->DramcWriteLeveling(PI) begin...
4177 00:24:38.362408 ==
4178 00:24:38.364757 Dram Type= 6, Freq= 0, CH_0, rank 1
4179 00:24:38.367964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 00:24:38.368044 ==
4181 00:24:38.372086 Write leveling (Byte 0): 34 => 34
4182 00:24:38.374633 Write leveling (Byte 1): 33 => 33
4183 00:24:38.377868 DramcWriteLeveling(PI) end<-----
4184 00:24:38.377947
4185 00:24:38.378008 ==
4186 00:24:38.381224 Dram Type= 6, Freq= 0, CH_0, rank 1
4187 00:24:38.387941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 00:24:38.388020 ==
4189 00:24:38.388082 [Gating] SW mode calibration
4190 00:24:38.398397 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4191 00:24:38.401348 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4192 00:24:38.404921 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4193 00:24:38.411139 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4194 00:24:38.414515 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4195 00:24:38.417860 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4196 00:24:38.424169 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4197 00:24:38.427871 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 00:24:38.431247 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 00:24:38.437488 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 00:24:38.441014 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 00:24:38.443913 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 00:24:38.450776 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 00:24:38.454000 0 10 12 | B1->B0 | 2828 2d2d | 0 1 | (0 0) (0 0)
4204 00:24:38.457337 0 10 16 | B1->B0 | 3a3a 4444 | 1 0 | (0 0) (0 0)
4205 00:24:38.463958 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 00:24:38.467718 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 00:24:38.470197 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 00:24:38.476986 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 00:24:38.480490 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 00:24:38.484066 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 00:24:38.490126 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4212 00:24:38.493769 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 00:24:38.497282 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 00:24:38.503541 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 00:24:38.507076 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 00:24:38.510084 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 00:24:38.516462 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 00:24:38.519658 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 00:24:38.523392 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 00:24:38.529905 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 00:24:38.533061 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 00:24:38.536230 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 00:24:38.542747 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 00:24:38.546205 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 00:24:38.549228 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 00:24:38.556066 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 00:24:38.559284 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 00:24:38.562764 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 00:24:38.565974 Total UI for P1: 0, mck2ui 16
4230 00:24:38.569120 best dqsien dly found for B0: ( 0, 13, 14)
4231 00:24:38.573009 Total UI for P1: 0, mck2ui 16
4232 00:24:38.576396 best dqsien dly found for B1: ( 0, 13, 14)
4233 00:24:38.579410 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4234 00:24:38.585820 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4235 00:24:38.585899
4236 00:24:38.588686 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4237 00:24:38.592130 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4238 00:24:38.595541 [Gating] SW calibration Done
4239 00:24:38.595620 ==
4240 00:24:38.599115 Dram Type= 6, Freq= 0, CH_0, rank 1
4241 00:24:38.602413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4242 00:24:38.602518 ==
4243 00:24:38.605443 RX Vref Scan: 0
4244 00:24:38.605520
4245 00:24:38.605582 RX Vref 0 -> 0, step: 1
4246 00:24:38.605639
4247 00:24:38.609291 RX Delay -230 -> 252, step: 16
4248 00:24:38.612119 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4249 00:24:38.618560 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4250 00:24:38.622444 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4251 00:24:38.625794 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4252 00:24:38.628561 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4253 00:24:38.634858 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4254 00:24:38.638806 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4255 00:24:38.642035 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4256 00:24:38.645384 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4257 00:24:38.651734 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4258 00:24:38.655158 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4259 00:24:38.658308 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4260 00:24:38.661718 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4261 00:24:38.668398 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4262 00:24:38.671453 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4263 00:24:38.675308 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4264 00:24:38.675390 ==
4265 00:24:38.678184 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 00:24:38.681839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 00:24:38.681919 ==
4268 00:24:38.684654 DQS Delay:
4269 00:24:38.684733 DQS0 = 0, DQS1 = 0
4270 00:24:38.688177 DQM Delay:
4271 00:24:38.688257 DQM0 = 43, DQM1 = 36
4272 00:24:38.688320 DQ Delay:
4273 00:24:38.691205 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4274 00:24:38.694491 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4275 00:24:38.698105 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4276 00:24:38.701130 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4277 00:24:38.701209
4278 00:24:38.701272
4279 00:24:38.704521 ==
4280 00:24:38.707829 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 00:24:38.711028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 00:24:38.711109 ==
4283 00:24:38.711171
4284 00:24:38.711228
4285 00:24:38.714132 TX Vref Scan disable
4286 00:24:38.714212 == TX Byte 0 ==
4287 00:24:38.720833 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4288 00:24:38.724047 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4289 00:24:38.724127 == TX Byte 1 ==
4290 00:24:38.731232 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4291 00:24:38.734125 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4292 00:24:38.734205 ==
4293 00:24:38.737485 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 00:24:38.740560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 00:24:38.740640 ==
4296 00:24:38.740702
4297 00:24:38.740758
4298 00:24:38.743856 TX Vref Scan disable
4299 00:24:38.747458 == TX Byte 0 ==
4300 00:24:38.750474 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4301 00:24:38.754017 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4302 00:24:38.757245 == TX Byte 1 ==
4303 00:24:38.760444 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4304 00:24:38.763721 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4305 00:24:38.767405
4306 00:24:38.767484 [DATLAT]
4307 00:24:38.767546 Freq=600, CH0 RK1
4308 00:24:38.767604
4309 00:24:38.770913 DATLAT Default: 0x9
4310 00:24:38.770992 0, 0xFFFF, sum = 0
4311 00:24:38.774042 1, 0xFFFF, sum = 0
4312 00:24:38.774122 2, 0xFFFF, sum = 0
4313 00:24:38.777400 3, 0xFFFF, sum = 0
4314 00:24:38.780229 4, 0xFFFF, sum = 0
4315 00:24:38.780309 5, 0xFFFF, sum = 0
4316 00:24:38.783476 6, 0xFFFF, sum = 0
4317 00:24:38.783556 7, 0xFFFF, sum = 0
4318 00:24:38.787125 8, 0x0, sum = 1
4319 00:24:38.787205 9, 0x0, sum = 2
4320 00:24:38.787272 10, 0x0, sum = 3
4321 00:24:38.790232 11, 0x0, sum = 4
4322 00:24:38.790338 best_step = 9
4323 00:24:38.790427
4324 00:24:38.790512 ==
4325 00:24:38.793683 Dram Type= 6, Freq= 0, CH_0, rank 1
4326 00:24:38.799923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 00:24:38.800003 ==
4328 00:24:38.800065 RX Vref Scan: 0
4329 00:24:38.800123
4330 00:24:38.803831 RX Vref 0 -> 0, step: 1
4331 00:24:38.803911
4332 00:24:38.807461 RX Delay -179 -> 252, step: 8
4333 00:24:38.809897 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4334 00:24:38.816252 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4335 00:24:38.819759 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4336 00:24:38.822931 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4337 00:24:38.826309 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4338 00:24:38.832946 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4339 00:24:38.836602 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4340 00:24:38.839739 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4341 00:24:38.843162 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4342 00:24:38.849322 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4343 00:24:38.852655 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4344 00:24:38.856106 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4345 00:24:38.860110 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4346 00:24:38.866253 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4347 00:24:38.869127 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4348 00:24:38.873451 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4349 00:24:38.873530 ==
4350 00:24:38.875739 Dram Type= 6, Freq= 0, CH_0, rank 1
4351 00:24:38.879123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4352 00:24:38.879203 ==
4353 00:24:38.882538 DQS Delay:
4354 00:24:38.882660 DQS0 = 0, DQS1 = 0
4355 00:24:38.885643 DQM Delay:
4356 00:24:38.885721 DQM0 = 41, DQM1 = 35
4357 00:24:38.885782 DQ Delay:
4358 00:24:38.889231 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4359 00:24:38.892474 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4360 00:24:38.896182 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4361 00:24:38.899261 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4362 00:24:38.899339
4363 00:24:38.899421
4364 00:24:38.909231 [DQSOSCAuto] RK1, (LSB)MR18= 0x6417, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
4365 00:24:38.912147 CH0 RK1: MR19=808, MR18=6417
4366 00:24:38.919014 CH0_RK1: MR19=0x808, MR18=0x6417, DQSOSC=391, MR23=63, INC=171, DEC=114
4367 00:24:38.922418 [RxdqsGatingPostProcess] freq 600
4368 00:24:38.925852 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4369 00:24:38.929294 Pre-setting of DQS Precalculation
4370 00:24:38.935680 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4371 00:24:38.935760 ==
4372 00:24:38.938714 Dram Type= 6, Freq= 0, CH_1, rank 0
4373 00:24:38.942729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 00:24:38.942811 ==
4375 00:24:38.948960 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4376 00:24:38.951993 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4377 00:24:38.955855 [CA 0] Center 35 (5~66) winsize 62
4378 00:24:38.959224 [CA 1] Center 35 (5~66) winsize 62
4379 00:24:38.962586 [CA 2] Center 34 (4~65) winsize 62
4380 00:24:38.966112 [CA 3] Center 33 (3~64) winsize 62
4381 00:24:38.969046 [CA 4] Center 34 (4~64) winsize 61
4382 00:24:38.972635 [CA 5] Center 33 (3~64) winsize 62
4383 00:24:38.972715
4384 00:24:38.975813 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4385 00:24:38.975892
4386 00:24:38.979227 [CATrainingPosCal] consider 1 rank data
4387 00:24:38.982292 u2DelayCellTimex100 = 270/100 ps
4388 00:24:38.985800 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4389 00:24:38.992508 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4390 00:24:38.995880 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4391 00:24:38.999276 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4392 00:24:39.002390 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4393 00:24:39.005413 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4394 00:24:39.005493
4395 00:24:39.009012 CA PerBit enable=1, Macro0, CA PI delay=33
4396 00:24:39.009091
4397 00:24:39.012187 [CBTSetCACLKResult] CA Dly = 33
4398 00:24:39.015445 CS Dly: 4 (0~35)
4399 00:24:39.015546 ==
4400 00:24:39.018903 Dram Type= 6, Freq= 0, CH_1, rank 1
4401 00:24:39.022733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 00:24:39.022813 ==
4403 00:24:39.029038 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4404 00:24:39.031897 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4405 00:24:39.035984 [CA 0] Center 35 (5~66) winsize 62
4406 00:24:39.039883 [CA 1] Center 36 (6~66) winsize 61
4407 00:24:39.043093 [CA 2] Center 34 (4~65) winsize 62
4408 00:24:39.045978 [CA 3] Center 34 (3~65) winsize 63
4409 00:24:39.049074 [CA 4] Center 34 (3~65) winsize 63
4410 00:24:39.052426 [CA 5] Center 33 (3~64) winsize 62
4411 00:24:39.052505
4412 00:24:39.056203 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4413 00:24:39.056282
4414 00:24:39.059327 [CATrainingPosCal] consider 2 rank data
4415 00:24:39.062530 u2DelayCellTimex100 = 270/100 ps
4416 00:24:39.065833 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4417 00:24:39.072806 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4418 00:24:39.075722 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4419 00:24:39.079028 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4420 00:24:39.082400 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4421 00:24:39.085677 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4422 00:24:39.085756
4423 00:24:39.089089 CA PerBit enable=1, Macro0, CA PI delay=33
4424 00:24:39.089168
4425 00:24:39.092374 [CBTSetCACLKResult] CA Dly = 33
4426 00:24:39.095213 CS Dly: 5 (0~37)
4427 00:24:39.095309
4428 00:24:39.098611 ----->DramcWriteLeveling(PI) begin...
4429 00:24:39.098692 ==
4430 00:24:39.102479 Dram Type= 6, Freq= 0, CH_1, rank 0
4431 00:24:39.105465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4432 00:24:39.105545 ==
4433 00:24:39.108870 Write leveling (Byte 0): 29 => 29
4434 00:24:39.112008 Write leveling (Byte 1): 30 => 30
4435 00:24:39.115417 DramcWriteLeveling(PI) end<-----
4436 00:24:39.115496
4437 00:24:39.115557 ==
4438 00:24:39.118526 Dram Type= 6, Freq= 0, CH_1, rank 0
4439 00:24:39.121707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4440 00:24:39.121786 ==
4441 00:24:39.125538 [Gating] SW mode calibration
4442 00:24:39.131490 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4443 00:24:39.138317 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4444 00:24:39.141826 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4445 00:24:39.144790 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4446 00:24:39.152007 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4447 00:24:39.155088 0 9 12 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (1 0)
4448 00:24:39.158554 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4449 00:24:39.164976 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 00:24:39.168195 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 00:24:39.171636 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 00:24:39.177967 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 00:24:39.181693 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 00:24:39.184657 0 10 8 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
4455 00:24:39.191466 0 10 12 | B1->B0 | 2d2d 3737 | 0 0 | (0 0) (1 1)
4456 00:24:39.194578 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4457 00:24:39.197710 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 00:24:39.204580 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 00:24:39.207628 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 00:24:39.211443 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 00:24:39.217693 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 00:24:39.221127 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4463 00:24:39.224767 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4464 00:24:39.231223 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 00:24:39.234228 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 00:24:39.237534 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 00:24:39.244227 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 00:24:39.247857 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 00:24:39.250825 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 00:24:39.257659 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 00:24:39.260622 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 00:24:39.264792 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 00:24:39.270568 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 00:24:39.274280 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 00:24:39.277027 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 00:24:39.284074 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 00:24:39.287103 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 00:24:39.290275 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 00:24:39.297434 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4480 00:24:39.297514 Total UI for P1: 0, mck2ui 16
4481 00:24:39.303836 best dqsien dly found for B0: ( 0, 13, 10)
4482 00:24:39.306885 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 00:24:39.310881 Total UI for P1: 0, mck2ui 16
4484 00:24:39.313865 best dqsien dly found for B1: ( 0, 13, 12)
4485 00:24:39.317132 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4486 00:24:39.320042 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4487 00:24:39.320121
4488 00:24:39.323977 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4489 00:24:39.327515 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4490 00:24:39.330062 [Gating] SW calibration Done
4491 00:24:39.330141 ==
4492 00:24:39.333523 Dram Type= 6, Freq= 0, CH_1, rank 0
4493 00:24:39.337013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4494 00:24:39.339936 ==
4495 00:24:39.340018 RX Vref Scan: 0
4496 00:24:39.340085
4497 00:24:39.343209 RX Vref 0 -> 0, step: 1
4498 00:24:39.343288
4499 00:24:39.346529 RX Delay -230 -> 252, step: 16
4500 00:24:39.350193 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4501 00:24:39.353481 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4502 00:24:39.356403 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4503 00:24:39.363656 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4504 00:24:39.366582 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4505 00:24:39.369604 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4506 00:24:39.373130 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4507 00:24:39.376390 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4508 00:24:39.383109 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4509 00:24:39.386187 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4510 00:24:39.389483 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4511 00:24:39.392760 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4512 00:24:39.399480 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4513 00:24:39.402605 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4514 00:24:39.406045 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4515 00:24:39.409304 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4516 00:24:39.412581 ==
4517 00:24:39.415876 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 00:24:39.419278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 00:24:39.419357 ==
4520 00:24:39.419419 DQS Delay:
4521 00:24:39.422307 DQS0 = 0, DQS1 = 0
4522 00:24:39.422385 DQM Delay:
4523 00:24:39.425783 DQM0 = 46, DQM1 = 36
4524 00:24:39.425861 DQ Delay:
4525 00:24:39.429255 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4526 00:24:39.432379 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4527 00:24:39.435468 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4528 00:24:39.438760 DQ12 =49, DQ13 =41, DQ14 =49, DQ15 =49
4529 00:24:39.438839
4530 00:24:39.438901
4531 00:24:39.438959 ==
4532 00:24:39.442445 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 00:24:39.445786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 00:24:39.445865 ==
4535 00:24:39.445927
4536 00:24:39.445985
4537 00:24:39.448883 TX Vref Scan disable
4538 00:24:39.452077 == TX Byte 0 ==
4539 00:24:39.455396 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4540 00:24:39.458827 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4541 00:24:39.462135 == TX Byte 1 ==
4542 00:24:39.465220 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4543 00:24:39.468629 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4544 00:24:39.468708 ==
4545 00:24:39.472613 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 00:24:39.478845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 00:24:39.478925 ==
4548 00:24:39.478986
4549 00:24:39.479044
4550 00:24:39.479098 TX Vref Scan disable
4551 00:24:39.482905 == TX Byte 0 ==
4552 00:24:39.486421 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4553 00:24:39.492788 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4554 00:24:39.492867 == TX Byte 1 ==
4555 00:24:39.496997 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4556 00:24:39.502729 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4557 00:24:39.502808
4558 00:24:39.502870 [DATLAT]
4559 00:24:39.502927 Freq=600, CH1 RK0
4560 00:24:39.502982
4561 00:24:39.506839 DATLAT Default: 0x9
4562 00:24:39.506917 0, 0xFFFF, sum = 0
4563 00:24:39.509521 1, 0xFFFF, sum = 0
4564 00:24:39.512937 2, 0xFFFF, sum = 0
4565 00:24:39.513017 3, 0xFFFF, sum = 0
4566 00:24:39.516148 4, 0xFFFF, sum = 0
4567 00:24:39.516228 5, 0xFFFF, sum = 0
4568 00:24:39.519539 6, 0xFFFF, sum = 0
4569 00:24:39.519619 7, 0xFFFF, sum = 0
4570 00:24:39.522514 8, 0x0, sum = 1
4571 00:24:39.522654 9, 0x0, sum = 2
4572 00:24:39.522719 10, 0x0, sum = 3
4573 00:24:39.526309 11, 0x0, sum = 4
4574 00:24:39.526389 best_step = 9
4575 00:24:39.526451
4576 00:24:39.526508 ==
4577 00:24:39.529646 Dram Type= 6, Freq= 0, CH_1, rank 0
4578 00:24:39.535767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 00:24:39.535846 ==
4580 00:24:39.535908 RX Vref Scan: 1
4581 00:24:39.535965
4582 00:24:39.539001 RX Vref 0 -> 0, step: 1
4583 00:24:39.539079
4584 00:24:39.542498 RX Delay -195 -> 252, step: 8
4585 00:24:39.542576
4586 00:24:39.545827 Set Vref, RX VrefLevel [Byte0]: 48
4587 00:24:39.549407 [Byte1]: 54
4588 00:24:39.549486
4589 00:24:39.552697 Final RX Vref Byte 0 = 48 to rank0
4590 00:24:39.555364 Final RX Vref Byte 1 = 54 to rank0
4591 00:24:39.558782 Final RX Vref Byte 0 = 48 to rank1
4592 00:24:39.562034 Final RX Vref Byte 1 = 54 to rank1==
4593 00:24:39.565218 Dram Type= 6, Freq= 0, CH_1, rank 0
4594 00:24:39.568680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 00:24:39.572092 ==
4596 00:24:39.572171 DQS Delay:
4597 00:24:39.572232 DQS0 = 0, DQS1 = 0
4598 00:24:39.575632 DQM Delay:
4599 00:24:39.575711 DQM0 = 48, DQM1 = 37
4600 00:24:39.578785 DQ Delay:
4601 00:24:39.581973 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =44
4602 00:24:39.582055 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4603 00:24:39.585351 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4604 00:24:39.588641 DQ12 =48, DQ13 =40, DQ14 =48, DQ15 =48
4605 00:24:39.591980
4606 00:24:39.592058
4607 00:24:39.598611 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f33, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4608 00:24:39.602000 CH1 RK0: MR19=808, MR18=4F33
4609 00:24:39.608723 CH1_RK0: MR19=0x808, MR18=0x4F33, DQSOSC=394, MR23=63, INC=168, DEC=112
4610 00:24:39.608803
4611 00:24:39.612239 ----->DramcWriteLeveling(PI) begin...
4612 00:24:39.612320 ==
4613 00:24:39.614919 Dram Type= 6, Freq= 0, CH_1, rank 1
4614 00:24:39.618048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 00:24:39.618128 ==
4616 00:24:39.621678 Write leveling (Byte 0): 29 => 29
4617 00:24:39.624759 Write leveling (Byte 1): 30 => 30
4618 00:24:39.628090 DramcWriteLeveling(PI) end<-----
4619 00:24:39.628172
4620 00:24:39.628235 ==
4621 00:24:39.631763 Dram Type= 6, Freq= 0, CH_1, rank 1
4622 00:24:39.635044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 00:24:39.635117 ==
4624 00:24:39.638704 [Gating] SW mode calibration
4625 00:24:39.645144 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4626 00:24:39.651680 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4627 00:24:39.654721 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4628 00:24:39.661130 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4629 00:24:39.664393 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4630 00:24:39.667932 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 0) (1 1)
4631 00:24:39.674480 0 9 16 | B1->B0 | 2525 2929 | 0 0 | (1 1) (0 0)
4632 00:24:39.677774 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 00:24:39.681025 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 00:24:39.687731 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4635 00:24:39.690880 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 00:24:39.694305 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4637 00:24:39.700694 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4638 00:24:39.704127 0 10 12 | B1->B0 | 3535 2626 | 0 0 | (0 0) (1 1)
4639 00:24:39.707253 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4640 00:24:39.714094 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 00:24:39.716937 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 00:24:39.720394 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 00:24:39.727137 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 00:24:39.730226 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 00:24:39.733712 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4646 00:24:39.740705 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4647 00:24:39.743763 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 00:24:39.747116 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 00:24:39.753764 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 00:24:39.756719 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 00:24:39.760755 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 00:24:39.767017 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 00:24:39.770052 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 00:24:39.773771 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 00:24:39.776869 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 00:24:39.783528 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 00:24:39.787294 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 00:24:39.790201 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 00:24:39.796818 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 00:24:39.800019 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 00:24:39.803262 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 00:24:39.809878 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4663 00:24:39.813259 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 00:24:39.817184 Total UI for P1: 0, mck2ui 16
4665 00:24:39.820318 best dqsien dly found for B0: ( 0, 13, 14)
4666 00:24:39.823525 Total UI for P1: 0, mck2ui 16
4667 00:24:39.826388 best dqsien dly found for B1: ( 0, 13, 12)
4668 00:24:39.830036 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4669 00:24:39.833112 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4670 00:24:39.833192
4671 00:24:39.836876 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4672 00:24:39.840069 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4673 00:24:39.842961 [Gating] SW calibration Done
4674 00:24:39.843040 ==
4675 00:24:39.846487 Dram Type= 6, Freq= 0, CH_1, rank 1
4676 00:24:39.853031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4677 00:24:39.853136 ==
4678 00:24:39.853249 RX Vref Scan: 0
4679 00:24:39.853355
4680 00:24:39.856550 RX Vref 0 -> 0, step: 1
4681 00:24:39.856628
4682 00:24:39.859562 RX Delay -230 -> 252, step: 16
4683 00:24:39.863181 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4684 00:24:39.866492 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4685 00:24:39.869440 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4686 00:24:39.876209 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4687 00:24:39.879286 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4688 00:24:39.882755 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4689 00:24:39.886036 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4690 00:24:39.892382 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4691 00:24:39.895724 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4692 00:24:39.899406 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4693 00:24:39.902668 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4694 00:24:39.909046 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4695 00:24:39.912310 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4696 00:24:39.915944 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4697 00:24:39.919222 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4698 00:24:39.925936 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4699 00:24:39.926016 ==
4700 00:24:39.928798 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 00:24:39.932331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 00:24:39.932412 ==
4703 00:24:39.932475 DQS Delay:
4704 00:24:39.935987 DQS0 = 0, DQS1 = 0
4705 00:24:39.936067 DQM Delay:
4706 00:24:39.938978 DQM0 = 42, DQM1 = 39
4707 00:24:39.939058 DQ Delay:
4708 00:24:39.941867 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4709 00:24:39.945433 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4710 00:24:39.948823 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =33
4711 00:24:39.951990 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4712 00:24:39.952070
4713 00:24:39.952132
4714 00:24:39.952190 ==
4715 00:24:39.955854 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 00:24:39.958704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 00:24:39.958784 ==
4718 00:24:39.962383
4719 00:24:39.962462
4720 00:24:39.962523 TX Vref Scan disable
4721 00:24:39.965338 == TX Byte 0 ==
4722 00:24:39.969088 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4723 00:24:39.971930 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4724 00:24:39.975167 == TX Byte 1 ==
4725 00:24:39.978741 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4726 00:24:39.982019 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4727 00:24:39.982099 ==
4728 00:24:39.985329 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 00:24:39.991509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 00:24:39.991590 ==
4731 00:24:39.991652
4732 00:24:39.991710
4733 00:24:39.994738 TX Vref Scan disable
4734 00:24:39.994817 == TX Byte 0 ==
4735 00:24:40.001461 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4736 00:24:40.005456 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4737 00:24:40.005536 == TX Byte 1 ==
4738 00:24:40.011588 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4739 00:24:40.014522 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4740 00:24:40.014660
4741 00:24:40.014725 [DATLAT]
4742 00:24:40.018437 Freq=600, CH1 RK1
4743 00:24:40.018516
4744 00:24:40.018578 DATLAT Default: 0x9
4745 00:24:40.021356 0, 0xFFFF, sum = 0
4746 00:24:40.021437 1, 0xFFFF, sum = 0
4747 00:24:40.024825 2, 0xFFFF, sum = 0
4748 00:24:40.024906 3, 0xFFFF, sum = 0
4749 00:24:40.027752 4, 0xFFFF, sum = 0
4750 00:24:40.031290 5, 0xFFFF, sum = 0
4751 00:24:40.031371 6, 0xFFFF, sum = 0
4752 00:24:40.034659 7, 0xFFFF, sum = 0
4753 00:24:40.034740 8, 0x0, sum = 1
4754 00:24:40.034804 9, 0x0, sum = 2
4755 00:24:40.037962 10, 0x0, sum = 3
4756 00:24:40.038043 11, 0x0, sum = 4
4757 00:24:40.041345 best_step = 9
4758 00:24:40.041424
4759 00:24:40.041486 ==
4760 00:24:40.044673 Dram Type= 6, Freq= 0, CH_1, rank 1
4761 00:24:40.047759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4762 00:24:40.047839 ==
4763 00:24:40.051341 RX Vref Scan: 0
4764 00:24:40.051421
4765 00:24:40.051483 RX Vref 0 -> 0, step: 1
4766 00:24:40.051541
4767 00:24:40.054784 RX Delay -195 -> 252, step: 8
4768 00:24:40.061840 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4769 00:24:40.064963 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4770 00:24:40.068520 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4771 00:24:40.071711 iDelay=213, Bit 3, Center 44 (-99 ~ 188) 288
4772 00:24:40.078735 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4773 00:24:40.082159 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4774 00:24:40.085048 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4775 00:24:40.088262 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4776 00:24:40.091549 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4777 00:24:40.098627 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4778 00:24:40.101481 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4779 00:24:40.104772 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4780 00:24:40.108343 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4781 00:24:40.114582 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4782 00:24:40.117729 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4783 00:24:40.121126 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4784 00:24:40.121209 ==
4785 00:24:40.124492 Dram Type= 6, Freq= 0, CH_1, rank 1
4786 00:24:40.130884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4787 00:24:40.130965 ==
4788 00:24:40.131028 DQS Delay:
4789 00:24:40.131086 DQS0 = 0, DQS1 = 0
4790 00:24:40.134276 DQM Delay:
4791 00:24:40.134355 DQM0 = 46, DQM1 = 36
4792 00:24:40.137482 DQ Delay:
4793 00:24:40.140533 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4794 00:24:40.143909 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4795 00:24:40.147389 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4796 00:24:40.150467 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4797 00:24:40.150546
4798 00:24:40.150673
4799 00:24:40.157159 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4800 00:24:40.160788 CH1 RK1: MR19=808, MR18=2D22
4801 00:24:40.167013 CH1_RK1: MR19=0x808, MR18=0x2D22, DQSOSC=401, MR23=63, INC=163, DEC=108
4802 00:24:40.170948 [RxdqsGatingPostProcess] freq 600
4803 00:24:40.173777 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4804 00:24:40.176891 Pre-setting of DQS Precalculation
4805 00:24:40.183609 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4806 00:24:40.189891 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4807 00:24:40.196829 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4808 00:24:40.196909
4809 00:24:40.196971
4810 00:24:40.200169 [Calibration Summary] 1200 Mbps
4811 00:24:40.200249 CH 0, Rank 0
4812 00:24:40.204099 SW Impedance : PASS
4813 00:24:40.206558 DUTY Scan : NO K
4814 00:24:40.206671 ZQ Calibration : PASS
4815 00:24:40.210148 Jitter Meter : NO K
4816 00:24:40.213337 CBT Training : PASS
4817 00:24:40.213416 Write leveling : PASS
4818 00:24:40.216641 RX DQS gating : PASS
4819 00:24:40.219681 RX DQ/DQS(RDDQC) : PASS
4820 00:24:40.219761 TX DQ/DQS : PASS
4821 00:24:40.223303 RX DATLAT : PASS
4822 00:24:40.226151 RX DQ/DQS(Engine): PASS
4823 00:24:40.226230 TX OE : NO K
4824 00:24:40.229623 All Pass.
4825 00:24:40.229703
4826 00:24:40.229765 CH 0, Rank 1
4827 00:24:40.232660 SW Impedance : PASS
4828 00:24:40.232740 DUTY Scan : NO K
4829 00:24:40.236248 ZQ Calibration : PASS
4830 00:24:40.239224 Jitter Meter : NO K
4831 00:24:40.239304 CBT Training : PASS
4832 00:24:40.242835 Write leveling : PASS
4833 00:24:40.246379 RX DQS gating : PASS
4834 00:24:40.246459 RX DQ/DQS(RDDQC) : PASS
4835 00:24:40.249902 TX DQ/DQS : PASS
4836 00:24:40.252620 RX DATLAT : PASS
4837 00:24:40.252699 RX DQ/DQS(Engine): PASS
4838 00:24:40.255811 TX OE : NO K
4839 00:24:40.255891 All Pass.
4840 00:24:40.255953
4841 00:24:40.259364 CH 1, Rank 0
4842 00:24:40.259444 SW Impedance : PASS
4843 00:24:40.262888 DUTY Scan : NO K
4844 00:24:40.265616 ZQ Calibration : PASS
4845 00:24:40.265696 Jitter Meter : NO K
4846 00:24:40.269170 CBT Training : PASS
4847 00:24:40.272161 Write leveling : PASS
4848 00:24:40.272241 RX DQS gating : PASS
4849 00:24:40.275496 RX DQ/DQS(RDDQC) : PASS
4850 00:24:40.279156 TX DQ/DQS : PASS
4851 00:24:40.279236 RX DATLAT : PASS
4852 00:24:40.282791 RX DQ/DQS(Engine): PASS
4853 00:24:40.285202 TX OE : NO K
4854 00:24:40.285282 All Pass.
4855 00:24:40.285344
4856 00:24:40.285402 CH 1, Rank 1
4857 00:24:40.288647 SW Impedance : PASS
4858 00:24:40.291992 DUTY Scan : NO K
4859 00:24:40.292071 ZQ Calibration : PASS
4860 00:24:40.295432 Jitter Meter : NO K
4861 00:24:40.298882 CBT Training : PASS
4862 00:24:40.298961 Write leveling : PASS
4863 00:24:40.302027 RX DQS gating : PASS
4864 00:24:40.302107 RX DQ/DQS(RDDQC) : PASS
4865 00:24:40.305293 TX DQ/DQS : PASS
4866 00:24:40.308892 RX DATLAT : PASS
4867 00:24:40.308971 RX DQ/DQS(Engine): PASS
4868 00:24:40.312624 TX OE : NO K
4869 00:24:40.312703 All Pass.
4870 00:24:40.312766
4871 00:24:40.315057 DramC Write-DBI off
4872 00:24:40.318607 PER_BANK_REFRESH: Hybrid Mode
4873 00:24:40.318687 TX_TRACKING: ON
4874 00:24:40.328249 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4875 00:24:40.331706 [FAST_K] Save calibration result to emmc
4876 00:24:40.334814 dramc_set_vcore_voltage set vcore to 662500
4877 00:24:40.338328 Read voltage for 933, 3
4878 00:24:40.338408 Vio18 = 0
4879 00:24:40.341308 Vcore = 662500
4880 00:24:40.341411 Vdram = 0
4881 00:24:40.341474 Vddq = 0
4882 00:24:40.341532 Vmddr = 0
4883 00:24:40.348627 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4884 00:24:40.354656 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4885 00:24:40.354736 MEM_TYPE=3, freq_sel=17
4886 00:24:40.357733 sv_algorithm_assistance_LP4_1600
4887 00:24:40.361486 ============ PULL DRAM RESETB DOWN ============
4888 00:24:40.367600 ========== PULL DRAM RESETB DOWN end =========
4889 00:24:40.371031 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4890 00:24:40.374712 ===================================
4891 00:24:40.378049 LPDDR4 DRAM CONFIGURATION
4892 00:24:40.381082 ===================================
4893 00:24:40.381162 EX_ROW_EN[0] = 0x0
4894 00:24:40.385528 EX_ROW_EN[1] = 0x0
4895 00:24:40.385608 LP4Y_EN = 0x0
4896 00:24:40.387741 WORK_FSP = 0x0
4897 00:24:40.390966 WL = 0x3
4898 00:24:40.391045 RL = 0x3
4899 00:24:40.393906 BL = 0x2
4900 00:24:40.393985 RPST = 0x0
4901 00:24:40.397468 RD_PRE = 0x0
4902 00:24:40.397547 WR_PRE = 0x1
4903 00:24:40.400791 WR_PST = 0x0
4904 00:24:40.400871 DBI_WR = 0x0
4905 00:24:40.404273 DBI_RD = 0x0
4906 00:24:40.404352 OTF = 0x1
4907 00:24:40.407490 ===================================
4908 00:24:40.410657 ===================================
4909 00:24:40.414427 ANA top config
4910 00:24:40.417132 ===================================
4911 00:24:40.417212 DLL_ASYNC_EN = 0
4912 00:24:40.420574 ALL_SLAVE_EN = 1
4913 00:24:40.424487 NEW_RANK_MODE = 1
4914 00:24:40.427284 DLL_IDLE_MODE = 1
4915 00:24:40.430909 LP45_APHY_COMB_EN = 1
4916 00:24:40.431023 TX_ODT_DIS = 1
4917 00:24:40.434109 NEW_8X_MODE = 1
4918 00:24:40.437611 ===================================
4919 00:24:40.440637 ===================================
4920 00:24:40.443487 data_rate = 1866
4921 00:24:40.447234 CKR = 1
4922 00:24:40.450232 DQ_P2S_RATIO = 8
4923 00:24:40.453482 ===================================
4924 00:24:40.456816 CA_P2S_RATIO = 8
4925 00:24:40.456896 DQ_CA_OPEN = 0
4926 00:24:40.460142 DQ_SEMI_OPEN = 0
4927 00:24:40.463405 CA_SEMI_OPEN = 0
4928 00:24:40.467142 CA_FULL_RATE = 0
4929 00:24:40.470156 DQ_CKDIV4_EN = 1
4930 00:24:40.473798 CA_CKDIV4_EN = 1
4931 00:24:40.473878 CA_PREDIV_EN = 0
4932 00:24:40.476520 PH8_DLY = 0
4933 00:24:40.479765 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4934 00:24:40.483711 DQ_AAMCK_DIV = 4
4935 00:24:40.486474 CA_AAMCK_DIV = 4
4936 00:24:40.489826 CA_ADMCK_DIV = 4
4937 00:24:40.489906 DQ_TRACK_CA_EN = 0
4938 00:24:40.493619 CA_PICK = 933
4939 00:24:40.496104 CA_MCKIO = 933
4940 00:24:40.499924 MCKIO_SEMI = 0
4941 00:24:40.503507 PLL_FREQ = 3732
4942 00:24:40.506190 DQ_UI_PI_RATIO = 32
4943 00:24:40.509568 CA_UI_PI_RATIO = 0
4944 00:24:40.512683 ===================================
4945 00:24:40.516155 ===================================
4946 00:24:40.516235 memory_type:LPDDR4
4947 00:24:40.519489 GP_NUM : 10
4948 00:24:40.522845 SRAM_EN : 1
4949 00:24:40.522925 MD32_EN : 0
4950 00:24:40.526562 ===================================
4951 00:24:40.530179 [ANA_INIT] >>>>>>>>>>>>>>
4952 00:24:40.533019 <<<<<< [CONFIGURE PHASE]: ANA_TX
4953 00:24:40.535708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4954 00:24:40.539353 ===================================
4955 00:24:40.542582 data_rate = 1866,PCW = 0X8f00
4956 00:24:40.546045 ===================================
4957 00:24:40.549284 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4958 00:24:40.552441 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4959 00:24:40.559901 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4960 00:24:40.562837 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4961 00:24:40.565751 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4962 00:24:40.569031 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4963 00:24:40.572407 [ANA_INIT] flow start
4964 00:24:40.575675 [ANA_INIT] PLL >>>>>>>>
4965 00:24:40.575755 [ANA_INIT] PLL <<<<<<<<
4966 00:24:40.579187 [ANA_INIT] MIDPI >>>>>>>>
4967 00:24:40.582568 [ANA_INIT] MIDPI <<<<<<<<
4968 00:24:40.585306 [ANA_INIT] DLL >>>>>>>>
4969 00:24:40.585384 [ANA_INIT] flow end
4970 00:24:40.589044 ============ LP4 DIFF to SE enter ============
4971 00:24:40.595709 ============ LP4 DIFF to SE exit ============
4972 00:24:40.595789 [ANA_INIT] <<<<<<<<<<<<<
4973 00:24:40.598737 [Flow] Enable top DCM control >>>>>
4974 00:24:40.601821 [Flow] Enable top DCM control <<<<<
4975 00:24:40.605370 Enable DLL master slave shuffle
4976 00:24:40.611958 ==============================================================
4977 00:24:40.612038 Gating Mode config
4978 00:24:40.618687 ==============================================================
4979 00:24:40.621967 Config description:
4980 00:24:40.631632 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4981 00:24:40.638469 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4982 00:24:40.642412 SELPH_MODE 0: By rank 1: By Phase
4983 00:24:40.648438 ==============================================================
4984 00:24:40.651588 GAT_TRACK_EN = 1
4985 00:24:40.655035 RX_GATING_MODE = 2
4986 00:24:40.658242 RX_GATING_TRACK_MODE = 2
4987 00:24:40.658321 SELPH_MODE = 1
4988 00:24:40.661493 PICG_EARLY_EN = 1
4989 00:24:40.664800 VALID_LAT_VALUE = 1
4990 00:24:40.671790 ==============================================================
4991 00:24:40.675189 Enter into Gating configuration >>>>
4992 00:24:40.677779 Exit from Gating configuration <<<<
4993 00:24:40.681366 Enter into DVFS_PRE_config >>>>>
4994 00:24:40.691553 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4995 00:24:40.694501 Exit from DVFS_PRE_config <<<<<
4996 00:24:40.697709 Enter into PICG configuration >>>>
4997 00:24:40.701172 Exit from PICG configuration <<<<
4998 00:24:40.704211 [RX_INPUT] configuration >>>>>
4999 00:24:40.707664 [RX_INPUT] configuration <<<<<
5000 00:24:40.710841 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5001 00:24:40.717452 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5002 00:24:40.724687 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5003 00:24:40.730999 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5004 00:24:40.737502 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5005 00:24:40.740640 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5006 00:24:40.747707 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5007 00:24:40.750941 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5008 00:24:40.753592 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5009 00:24:40.757590 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5010 00:24:40.763986 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5011 00:24:40.767561 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5012 00:24:40.770328 ===================================
5013 00:24:40.773856 LPDDR4 DRAM CONFIGURATION
5014 00:24:40.777203 ===================================
5015 00:24:40.777283 EX_ROW_EN[0] = 0x0
5016 00:24:40.780621 EX_ROW_EN[1] = 0x0
5017 00:24:40.780699 LP4Y_EN = 0x0
5018 00:24:40.784067 WORK_FSP = 0x0
5019 00:24:40.784146 WL = 0x3
5020 00:24:40.786927 RL = 0x3
5021 00:24:40.787006 BL = 0x2
5022 00:24:40.790503 RPST = 0x0
5023 00:24:40.793846 RD_PRE = 0x0
5024 00:24:40.793925 WR_PRE = 0x1
5025 00:24:40.797003 WR_PST = 0x0
5026 00:24:40.797082 DBI_WR = 0x0
5027 00:24:40.800400 DBI_RD = 0x0
5028 00:24:40.800479 OTF = 0x1
5029 00:24:40.803930 ===================================
5030 00:24:40.806706 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5031 00:24:40.813923 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5032 00:24:40.816952 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5033 00:24:40.820196 ===================================
5034 00:24:40.823828 LPDDR4 DRAM CONFIGURATION
5035 00:24:40.826862 ===================================
5036 00:24:40.826942 EX_ROW_EN[0] = 0x10
5037 00:24:40.830646 EX_ROW_EN[1] = 0x0
5038 00:24:40.830725 LP4Y_EN = 0x0
5039 00:24:40.833618 WORK_FSP = 0x0
5040 00:24:40.833697 WL = 0x3
5041 00:24:40.836416 RL = 0x3
5042 00:24:40.839908 BL = 0x2
5043 00:24:40.839987 RPST = 0x0
5044 00:24:40.843320 RD_PRE = 0x0
5045 00:24:40.843399 WR_PRE = 0x1
5046 00:24:40.846562 WR_PST = 0x0
5047 00:24:40.846680 DBI_WR = 0x0
5048 00:24:40.849605 DBI_RD = 0x0
5049 00:24:40.849683 OTF = 0x1
5050 00:24:40.853142 ===================================
5051 00:24:40.859679 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5052 00:24:40.863577 nWR fixed to 30
5053 00:24:40.866865 [ModeRegInit_LP4] CH0 RK0
5054 00:24:40.866948 [ModeRegInit_LP4] CH0 RK1
5055 00:24:40.869971 [ModeRegInit_LP4] CH1 RK0
5056 00:24:40.873436 [ModeRegInit_LP4] CH1 RK1
5057 00:24:40.873515 match AC timing 9
5058 00:24:40.879856 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5059 00:24:40.883166 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5060 00:24:40.886613 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5061 00:24:40.893511 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5062 00:24:40.896516 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5063 00:24:40.896595 ==
5064 00:24:40.899805 Dram Type= 6, Freq= 0, CH_0, rank 0
5065 00:24:40.903030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5066 00:24:40.903109 ==
5067 00:24:40.909747 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5068 00:24:40.916817 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5069 00:24:40.919827 [CA 0] Center 37 (7~68) winsize 62
5070 00:24:40.922770 [CA 1] Center 37 (7~68) winsize 62
5071 00:24:40.926192 [CA 2] Center 34 (4~65) winsize 62
5072 00:24:40.929209 [CA 3] Center 34 (4~65) winsize 62
5073 00:24:40.932691 [CA 4] Center 33 (3~64) winsize 62
5074 00:24:40.935852 [CA 5] Center 33 (3~63) winsize 61
5075 00:24:40.935931
5076 00:24:40.939505 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5077 00:24:40.939584
5078 00:24:40.942697 [CATrainingPosCal] consider 1 rank data
5079 00:24:40.945943 u2DelayCellTimex100 = 270/100 ps
5080 00:24:40.949955 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5081 00:24:40.952984 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5082 00:24:40.956071 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5083 00:24:40.959992 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5084 00:24:40.965915 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5085 00:24:40.969044 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5086 00:24:40.969123
5087 00:24:40.973079 CA PerBit enable=1, Macro0, CA PI delay=33
5088 00:24:40.973158
5089 00:24:40.976038 [CBTSetCACLKResult] CA Dly = 33
5090 00:24:40.976117 CS Dly: 7 (0~38)
5091 00:24:40.976179 ==
5092 00:24:40.978992 Dram Type= 6, Freq= 0, CH_0, rank 1
5093 00:24:40.985340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 00:24:40.985420 ==
5095 00:24:40.988666 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5096 00:24:40.995409 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5097 00:24:40.998730 [CA 0] Center 37 (7~68) winsize 62
5098 00:24:41.001876 [CA 1] Center 37 (7~68) winsize 62
5099 00:24:41.005361 [CA 2] Center 34 (4~65) winsize 62
5100 00:24:41.008762 [CA 3] Center 34 (4~65) winsize 62
5101 00:24:41.012389 [CA 4] Center 33 (3~64) winsize 62
5102 00:24:41.014893 [CA 5] Center 33 (3~63) winsize 61
5103 00:24:41.014972
5104 00:24:41.018506 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5105 00:24:41.018625
5106 00:24:41.021731 [CATrainingPosCal] consider 2 rank data
5107 00:24:41.024815 u2DelayCellTimex100 = 270/100 ps
5108 00:24:41.028141 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5109 00:24:41.035037 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5110 00:24:41.038185 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5111 00:24:41.041521 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5112 00:24:41.045040 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5113 00:24:41.048710 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5114 00:24:41.048789
5115 00:24:41.051370 CA PerBit enable=1, Macro0, CA PI delay=33
5116 00:24:41.051450
5117 00:24:41.054448 [CBTSetCACLKResult] CA Dly = 33
5118 00:24:41.057857 CS Dly: 7 (0~39)
5119 00:24:41.057935
5120 00:24:41.061373 ----->DramcWriteLeveling(PI) begin...
5121 00:24:41.061454 ==
5122 00:24:41.065156 Dram Type= 6, Freq= 0, CH_0, rank 0
5123 00:24:41.068045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5124 00:24:41.068156 ==
5125 00:24:41.071158 Write leveling (Byte 0): 33 => 33
5126 00:24:41.074518 Write leveling (Byte 1): 27 => 27
5127 00:24:41.077936 DramcWriteLeveling(PI) end<-----
5128 00:24:41.078014
5129 00:24:41.078075 ==
5130 00:24:41.081322 Dram Type= 6, Freq= 0, CH_0, rank 0
5131 00:24:41.084253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5132 00:24:41.084332 ==
5133 00:24:41.088091 [Gating] SW mode calibration
5134 00:24:41.094392 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5135 00:24:41.101287 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5136 00:24:41.104407 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
5137 00:24:41.107477 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (1 1) (1 1)
5138 00:24:41.113971 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 00:24:41.117691 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 00:24:41.121033 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5141 00:24:41.127575 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 00:24:41.130730 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 00:24:41.133846 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5144 00:24:41.140364 0 15 0 | B1->B0 | 3030 2424 | 0 0 | (0 1) (0 0)
5145 00:24:41.143860 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5146 00:24:41.147308 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 00:24:41.153472 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 00:24:41.157176 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 00:24:41.160491 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 00:24:41.166811 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 00:24:41.170250 0 15 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
5152 00:24:41.173877 1 0 0 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
5153 00:24:41.179890 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 00:24:41.183782 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 00:24:41.186958 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 00:24:41.193139 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 00:24:41.196634 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 00:24:41.200225 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 00:24:41.206445 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5160 00:24:41.210402 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5161 00:24:41.213544 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 00:24:41.220362 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 00:24:41.223526 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 00:24:41.226779 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 00:24:41.232988 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 00:24:41.236379 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 00:24:41.239741 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 00:24:41.246050 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 00:24:41.249791 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 00:24:41.252701 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 00:24:41.259539 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 00:24:41.263204 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 00:24:41.265941 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 00:24:41.272822 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 00:24:41.275906 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5176 00:24:41.279251 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 00:24:41.283010 Total UI for P1: 0, mck2ui 16
5178 00:24:41.285721 best dqsien dly found for B0: ( 1, 2, 28)
5179 00:24:41.289170 Total UI for P1: 0, mck2ui 16
5180 00:24:41.292706 best dqsien dly found for B1: ( 1, 2, 30)
5181 00:24:41.295724 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5182 00:24:41.299080 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5183 00:24:41.299158
5184 00:24:41.305604 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5185 00:24:41.309231 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5186 00:24:41.309310 [Gating] SW calibration Done
5187 00:24:41.312351 ==
5188 00:24:41.315661 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 00:24:41.319165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 00:24:41.319245 ==
5191 00:24:41.319307 RX Vref Scan: 0
5192 00:24:41.319364
5193 00:24:41.322490 RX Vref 0 -> 0, step: 1
5194 00:24:41.322586
5195 00:24:41.325534 RX Delay -80 -> 252, step: 8
5196 00:24:41.328914 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5197 00:24:41.332339 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5198 00:24:41.335582 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5199 00:24:41.341843 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5200 00:24:41.345601 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5201 00:24:41.348521 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5202 00:24:41.351893 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5203 00:24:41.355039 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5204 00:24:41.358847 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5205 00:24:41.365102 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5206 00:24:41.368375 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5207 00:24:41.371933 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5208 00:24:41.375059 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5209 00:24:41.378283 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5210 00:24:41.385034 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5211 00:24:41.388559 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5212 00:24:41.388639 ==
5213 00:24:41.392199 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 00:24:41.395027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 00:24:41.395108 ==
5216 00:24:41.398072 DQS Delay:
5217 00:24:41.398151 DQS0 = 0, DQS1 = 0
5218 00:24:41.398214 DQM Delay:
5219 00:24:41.401424 DQM0 = 97, DQM1 = 85
5220 00:24:41.401528 DQ Delay:
5221 00:24:41.404726 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5222 00:24:41.408139 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5223 00:24:41.412239 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5224 00:24:41.414684 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5225 00:24:41.414772
5226 00:24:41.414835
5227 00:24:41.414893 ==
5228 00:24:41.418102 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 00:24:41.424523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 00:24:41.424604 ==
5231 00:24:41.424666
5232 00:24:41.424723
5233 00:24:41.424777 TX Vref Scan disable
5234 00:24:41.428552 == TX Byte 0 ==
5235 00:24:41.432131 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5236 00:24:41.438771 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5237 00:24:41.438851 == TX Byte 1 ==
5238 00:24:41.441720 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5239 00:24:41.448582 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5240 00:24:41.448662 ==
5241 00:24:41.451488 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 00:24:41.454933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 00:24:41.455055 ==
5244 00:24:41.455146
5245 00:24:41.455232
5246 00:24:41.458509 TX Vref Scan disable
5247 00:24:41.461547 == TX Byte 0 ==
5248 00:24:41.464750 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5249 00:24:41.468007 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5250 00:24:41.471165 == TX Byte 1 ==
5251 00:24:41.474518 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5252 00:24:41.478156 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5253 00:24:41.478236
5254 00:24:41.478297 [DATLAT]
5255 00:24:41.481193 Freq=933, CH0 RK0
5256 00:24:41.481273
5257 00:24:41.484593 DATLAT Default: 0xd
5258 00:24:41.484672 0, 0xFFFF, sum = 0
5259 00:24:41.487575 1, 0xFFFF, sum = 0
5260 00:24:41.487655 2, 0xFFFF, sum = 0
5261 00:24:41.491043 3, 0xFFFF, sum = 0
5262 00:24:41.491123 4, 0xFFFF, sum = 0
5263 00:24:41.494617 5, 0xFFFF, sum = 0
5264 00:24:41.494698 6, 0xFFFF, sum = 0
5265 00:24:41.497710 7, 0xFFFF, sum = 0
5266 00:24:41.497791 8, 0xFFFF, sum = 0
5267 00:24:41.500901 9, 0xFFFF, sum = 0
5268 00:24:41.500983 10, 0x0, sum = 1
5269 00:24:41.504173 11, 0x0, sum = 2
5270 00:24:41.504263 12, 0x0, sum = 3
5271 00:24:41.507268 13, 0x0, sum = 4
5272 00:24:41.507349 best_step = 11
5273 00:24:41.507412
5274 00:24:41.507470 ==
5275 00:24:41.511053 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 00:24:41.514849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 00:24:41.517168 ==
5278 00:24:41.517247 RX Vref Scan: 1
5279 00:24:41.517310
5280 00:24:41.520880 RX Vref 0 -> 0, step: 1
5281 00:24:41.520960
5282 00:24:41.524389 RX Delay -69 -> 252, step: 4
5283 00:24:41.524469
5284 00:24:41.527514 Set Vref, RX VrefLevel [Byte0]: 60
5285 00:24:41.530401 [Byte1]: 57
5286 00:24:41.530481
5287 00:24:41.533684 Final RX Vref Byte 0 = 60 to rank0
5288 00:24:41.536971 Final RX Vref Byte 1 = 57 to rank0
5289 00:24:41.540583 Final RX Vref Byte 0 = 60 to rank1
5290 00:24:41.543874 Final RX Vref Byte 1 = 57 to rank1==
5291 00:24:41.546808 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 00:24:41.550011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 00:24:41.550091 ==
5294 00:24:41.553216 DQS Delay:
5295 00:24:41.553295 DQS0 = 0, DQS1 = 0
5296 00:24:41.553357 DQM Delay:
5297 00:24:41.556887 DQM0 = 97, DQM1 = 86
5298 00:24:41.556966 DQ Delay:
5299 00:24:41.560000 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5300 00:24:41.563474 DQ4 =98, DQ5 =88, DQ6 =108, DQ7 =106
5301 00:24:41.566768 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =82
5302 00:24:41.569972 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =92
5303 00:24:41.570052
5304 00:24:41.570113
5305 00:24:41.580003 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d13, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5306 00:24:41.583664 CH0 RK0: MR19=505, MR18=2D13
5307 00:24:41.589986 CH0_RK0: MR19=0x505, MR18=0x2D13, DQSOSC=407, MR23=63, INC=65, DEC=43
5308 00:24:41.590065
5309 00:24:41.592988 ----->DramcWriteLeveling(PI) begin...
5310 00:24:41.593069 ==
5311 00:24:41.596513 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 00:24:41.599515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 00:24:41.599595 ==
5314 00:24:41.603038 Write leveling (Byte 0): 35 => 35
5315 00:24:41.606207 Write leveling (Byte 1): 34 => 34
5316 00:24:41.609487 DramcWriteLeveling(PI) end<-----
5317 00:24:41.609566
5318 00:24:41.609627 ==
5319 00:24:41.612793 Dram Type= 6, Freq= 0, CH_0, rank 1
5320 00:24:41.616396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 00:24:41.616474 ==
5322 00:24:41.620171 [Gating] SW mode calibration
5323 00:24:41.626077 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5324 00:24:41.633109 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5325 00:24:41.636319 0 14 0 | B1->B0 | 2c2b 3232 | 1 1 | (1 1) (1 1)
5326 00:24:41.639595 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 00:24:41.646012 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 00:24:41.649631 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 00:24:41.652563 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 00:24:41.659492 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 00:24:41.662392 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 00:24:41.665465 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
5333 00:24:41.672148 0 15 0 | B1->B0 | 2c2c 2525 | 0 0 | (0 0) (1 0)
5334 00:24:41.675817 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 00:24:41.679012 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 00:24:41.686288 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 00:24:41.688959 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 00:24:41.692391 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 00:24:41.698892 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 00:24:41.702269 0 15 28 | B1->B0 | 2929 3838 | 0 0 | (0 0) (0 0)
5341 00:24:41.705312 1 0 0 | B1->B0 | 3f3f 4444 | 0 0 | (0 0) (0 0)
5342 00:24:41.712285 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 00:24:41.715794 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 00:24:41.719014 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 00:24:41.725858 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 00:24:41.728979 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 00:24:41.732068 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 00:24:41.738178 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 00:24:41.742339 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5350 00:24:41.745123 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 00:24:41.751716 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 00:24:41.754795 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 00:24:41.758464 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 00:24:41.764756 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 00:24:41.767881 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 00:24:41.771292 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 00:24:41.778005 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 00:24:41.781635 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 00:24:41.784939 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 00:24:41.790985 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 00:24:41.794344 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 00:24:41.797614 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 00:24:41.804813 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 00:24:41.807437 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5365 00:24:41.810988 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5366 00:24:41.814370 Total UI for P1: 0, mck2ui 16
5367 00:24:41.817739 best dqsien dly found for B0: ( 1, 2, 28)
5368 00:24:41.824351 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 00:24:41.824430 Total UI for P1: 0, mck2ui 16
5370 00:24:41.830714 best dqsien dly found for B1: ( 1, 2, 30)
5371 00:24:41.834369 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5372 00:24:41.837409 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5373 00:24:41.837488
5374 00:24:41.840722 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5375 00:24:41.844324 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5376 00:24:41.847243 [Gating] SW calibration Done
5377 00:24:41.847322 ==
5378 00:24:41.850492 Dram Type= 6, Freq= 0, CH_0, rank 1
5379 00:24:41.853782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5380 00:24:41.853862 ==
5381 00:24:41.857059 RX Vref Scan: 0
5382 00:24:41.857138
5383 00:24:41.857200 RX Vref 0 -> 0, step: 1
5384 00:24:41.857258
5385 00:24:41.860564 RX Delay -80 -> 252, step: 8
5386 00:24:41.863770 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5387 00:24:41.870315 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5388 00:24:41.874479 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5389 00:24:41.876933 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5390 00:24:41.880117 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5391 00:24:41.884063 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5392 00:24:41.886574 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5393 00:24:41.893935 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5394 00:24:41.896634 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5395 00:24:41.900063 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5396 00:24:41.903514 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5397 00:24:41.906851 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5398 00:24:41.913679 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5399 00:24:41.917065 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5400 00:24:41.919726 iDelay=208, Bit 14, Center 95 (-8 ~ 199) 208
5401 00:24:41.923158 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5402 00:24:41.923237 ==
5403 00:24:41.926775 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 00:24:41.933224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 00:24:41.933304 ==
5406 00:24:41.933366 DQS Delay:
5407 00:24:41.936489 DQS0 = 0, DQS1 = 0
5408 00:24:41.936568 DQM Delay:
5409 00:24:41.936630 DQM0 = 96, DQM1 = 87
5410 00:24:41.939664 DQ Delay:
5411 00:24:41.942761 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5412 00:24:41.946218 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5413 00:24:41.949532 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5414 00:24:41.952658 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5415 00:24:41.952737
5416 00:24:41.952799
5417 00:24:41.952856 ==
5418 00:24:41.956188 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 00:24:41.959206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 00:24:41.959286 ==
5421 00:24:41.959348
5422 00:24:41.959406
5423 00:24:41.962958 TX Vref Scan disable
5424 00:24:41.965997 == TX Byte 0 ==
5425 00:24:41.969149 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5426 00:24:41.972483 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5427 00:24:41.976184 == TX Byte 1 ==
5428 00:24:41.979162 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5429 00:24:41.982460 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5430 00:24:41.982565 ==
5431 00:24:41.986213 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 00:24:41.989062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 00:24:41.992269 ==
5434 00:24:41.992347
5435 00:24:41.992409
5436 00:24:41.992465 TX Vref Scan disable
5437 00:24:41.995953 == TX Byte 0 ==
5438 00:24:41.999586 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5439 00:24:42.005742 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5440 00:24:42.005822 == TX Byte 1 ==
5441 00:24:42.009507 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5442 00:24:42.015719 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5443 00:24:42.015798
5444 00:24:42.015859 [DATLAT]
5445 00:24:42.015917 Freq=933, CH0 RK1
5446 00:24:42.015973
5447 00:24:42.019489 DATLAT Default: 0xb
5448 00:24:42.019568 0, 0xFFFF, sum = 0
5449 00:24:42.022747 1, 0xFFFF, sum = 0
5450 00:24:42.025429 2, 0xFFFF, sum = 0
5451 00:24:42.025509 3, 0xFFFF, sum = 0
5452 00:24:42.029342 4, 0xFFFF, sum = 0
5453 00:24:42.029422 5, 0xFFFF, sum = 0
5454 00:24:42.032536 6, 0xFFFF, sum = 0
5455 00:24:42.032616 7, 0xFFFF, sum = 0
5456 00:24:42.035710 8, 0xFFFF, sum = 0
5457 00:24:42.035790 9, 0xFFFF, sum = 0
5458 00:24:42.039409 10, 0x0, sum = 1
5459 00:24:42.039488 11, 0x0, sum = 2
5460 00:24:42.042433 12, 0x0, sum = 3
5461 00:24:42.042540 13, 0x0, sum = 4
5462 00:24:42.046353 best_step = 11
5463 00:24:42.046457
5464 00:24:42.046546 ==
5465 00:24:42.049445 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 00:24:42.051954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 00:24:42.052033 ==
5468 00:24:42.052095 RX Vref Scan: 0
5469 00:24:42.052153
5470 00:24:42.055573 RX Vref 0 -> 0, step: 1
5471 00:24:42.055680
5472 00:24:42.058447 RX Delay -61 -> 252, step: 4
5473 00:24:42.065285 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5474 00:24:42.068603 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5475 00:24:42.072106 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5476 00:24:42.075361 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5477 00:24:42.078253 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5478 00:24:42.081766 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5479 00:24:42.088410 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5480 00:24:42.091863 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5481 00:24:42.095377 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5482 00:24:42.098146 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5483 00:24:42.101766 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5484 00:24:42.108378 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5485 00:24:42.111505 iDelay=203, Bit 12, Center 90 (-5 ~ 186) 192
5486 00:24:42.114965 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5487 00:24:42.118507 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5488 00:24:42.121481 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5489 00:24:42.125362 ==
5490 00:24:42.127713 Dram Type= 6, Freq= 0, CH_0, rank 1
5491 00:24:42.131597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 00:24:42.131676 ==
5493 00:24:42.131738 DQS Delay:
5494 00:24:42.134576 DQS0 = 0, DQS1 = 0
5495 00:24:42.134699 DQM Delay:
5496 00:24:42.137829 DQM0 = 94, DQM1 = 87
5497 00:24:42.137908 DQ Delay:
5498 00:24:42.141510 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
5499 00:24:42.144440 DQ4 =94, DQ5 =86, DQ6 =106, DQ7 =104
5500 00:24:42.147684 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =82
5501 00:24:42.151061 DQ12 =90, DQ13 =92, DQ14 =96, DQ15 =92
5502 00:24:42.151141
5503 00:24:42.151203
5504 00:24:42.158027 [DQSOSCAuto] RK1, (LSB)MR18= 0x2efe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 407 ps
5505 00:24:42.160970 CH0 RK1: MR19=504, MR18=2EFE
5506 00:24:42.167396 CH0_RK1: MR19=0x504, MR18=0x2EFE, DQSOSC=407, MR23=63, INC=65, DEC=43
5507 00:24:42.171063 [RxdqsGatingPostProcess] freq 933
5508 00:24:42.177323 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5509 00:24:42.180733 best DQS0 dly(2T, 0.5T) = (0, 10)
5510 00:24:42.180812 best DQS1 dly(2T, 0.5T) = (0, 10)
5511 00:24:42.184408 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5512 00:24:42.187530 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5513 00:24:42.190758 best DQS0 dly(2T, 0.5T) = (0, 10)
5514 00:24:42.193934 best DQS1 dly(2T, 0.5T) = (0, 10)
5515 00:24:42.197744 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5516 00:24:42.201037 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5517 00:24:42.203862 Pre-setting of DQS Precalculation
5518 00:24:42.210885 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5519 00:24:42.210965 ==
5520 00:24:42.213714 Dram Type= 6, Freq= 0, CH_1, rank 0
5521 00:24:42.217280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 00:24:42.217359 ==
5523 00:24:42.223600 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5524 00:24:42.230583 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5525 00:24:42.233436 [CA 0] Center 36 (6~67) winsize 62
5526 00:24:42.237195 [CA 1] Center 36 (6~67) winsize 62
5527 00:24:42.240041 [CA 2] Center 34 (4~65) winsize 62
5528 00:24:42.243293 [CA 3] Center 33 (3~64) winsize 62
5529 00:24:42.246566 [CA 4] Center 34 (4~64) winsize 61
5530 00:24:42.246687 [CA 5] Center 33 (3~64) winsize 62
5531 00:24:42.250088
5532 00:24:42.253515 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5533 00:24:42.253594
5534 00:24:42.256618 [CATrainingPosCal] consider 1 rank data
5535 00:24:42.259953 u2DelayCellTimex100 = 270/100 ps
5536 00:24:42.263586 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5537 00:24:42.267133 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5538 00:24:42.269758 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5539 00:24:42.273194 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5540 00:24:42.276622 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5541 00:24:42.279838 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5542 00:24:42.279917
5543 00:24:42.282923 CA PerBit enable=1, Macro0, CA PI delay=33
5544 00:24:42.286182
5545 00:24:42.286260 [CBTSetCACLKResult] CA Dly = 33
5546 00:24:42.290035 CS Dly: 6 (0~37)
5547 00:24:42.290113 ==
5548 00:24:42.292876 Dram Type= 6, Freq= 0, CH_1, rank 1
5549 00:24:42.296404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 00:24:42.296484 ==
5551 00:24:42.303462 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5552 00:24:42.309648 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5553 00:24:42.312641 [CA 0] Center 36 (6~67) winsize 62
5554 00:24:42.316496 [CA 1] Center 36 (6~67) winsize 62
5555 00:24:42.319784 [CA 2] Center 34 (4~65) winsize 62
5556 00:24:42.323168 [CA 3] Center 33 (3~64) winsize 62
5557 00:24:42.326067 [CA 4] Center 34 (3~65) winsize 63
5558 00:24:42.329795 [CA 5] Center 33 (3~64) winsize 62
5559 00:24:42.329873
5560 00:24:42.332658 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5561 00:24:42.332737
5562 00:24:42.335863 [CATrainingPosCal] consider 2 rank data
5563 00:24:42.339084 u2DelayCellTimex100 = 270/100 ps
5564 00:24:42.343184 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5565 00:24:42.345629 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5566 00:24:42.348796 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5567 00:24:42.352769 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5568 00:24:42.355385 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5569 00:24:42.362160 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5570 00:24:42.362239
5571 00:24:42.365449 CA PerBit enable=1, Macro0, CA PI delay=33
5572 00:24:42.365529
5573 00:24:42.368974 [CBTSetCACLKResult] CA Dly = 33
5574 00:24:42.369078 CS Dly: 7 (0~39)
5575 00:24:42.369178
5576 00:24:42.372206 ----->DramcWriteLeveling(PI) begin...
5577 00:24:42.372286 ==
5578 00:24:42.375979 Dram Type= 6, Freq= 0, CH_1, rank 0
5579 00:24:42.381991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 00:24:42.382071 ==
5581 00:24:42.385711 Write leveling (Byte 0): 28 => 28
5582 00:24:42.385790 Write leveling (Byte 1): 30 => 30
5583 00:24:42.388556 DramcWriteLeveling(PI) end<-----
5584 00:24:42.388634
5585 00:24:42.388696 ==
5586 00:24:42.392268 Dram Type= 6, Freq= 0, CH_1, rank 0
5587 00:24:42.398610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5588 00:24:42.398690 ==
5589 00:24:42.402512 [Gating] SW mode calibration
5590 00:24:42.408811 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5591 00:24:42.411923 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5592 00:24:42.418806 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 00:24:42.421845 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 00:24:42.424840 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 00:24:42.432024 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 00:24:42.435078 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 00:24:42.438424 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 00:24:42.444780 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
5599 00:24:42.447973 0 14 28 | B1->B0 | 2d2d 2525 | 1 0 | (1 0) (0 0)
5600 00:24:42.451538 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 00:24:42.458435 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 00:24:42.461414 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 00:24:42.464786 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 00:24:42.471232 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 00:24:42.474710 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 00:24:42.477939 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5607 00:24:42.484508 0 15 28 | B1->B0 | 3535 3f3f | 1 0 | (0 0) (0 0)
5608 00:24:42.487705 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 00:24:42.491632 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 00:24:42.497577 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 00:24:42.501358 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 00:24:42.504362 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 00:24:42.510817 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 00:24:42.514385 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 00:24:42.518073 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5616 00:24:42.524362 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 00:24:42.527458 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 00:24:42.530839 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 00:24:42.538041 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 00:24:42.541125 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 00:24:42.544102 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 00:24:42.550780 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 00:24:42.553752 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 00:24:42.557433 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 00:24:42.563821 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 00:24:42.567478 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 00:24:42.570052 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 00:24:42.577473 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 00:24:42.580525 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5630 00:24:42.583681 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5631 00:24:42.589926 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 00:24:42.590006 Total UI for P1: 0, mck2ui 16
5633 00:24:42.596670 best dqsien dly found for B0: ( 1, 2, 22)
5634 00:24:42.596750 Total UI for P1: 0, mck2ui 16
5635 00:24:42.599760 best dqsien dly found for B1: ( 1, 2, 24)
5636 00:24:42.606550 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5637 00:24:42.609702 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5638 00:24:42.609782
5639 00:24:42.612949 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5640 00:24:42.616525 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5641 00:24:42.619868 [Gating] SW calibration Done
5642 00:24:42.619947 ==
5643 00:24:42.623239 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 00:24:42.626277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 00:24:42.626362 ==
5646 00:24:42.629673 RX Vref Scan: 0
5647 00:24:42.629753
5648 00:24:42.629816 RX Vref 0 -> 0, step: 1
5649 00:24:42.629874
5650 00:24:42.632843 RX Delay -80 -> 252, step: 8
5651 00:24:42.636334 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5652 00:24:42.643246 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5653 00:24:42.646077 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5654 00:24:42.649257 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5655 00:24:42.652927 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5656 00:24:42.656041 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5657 00:24:42.659245 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5658 00:24:42.666015 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5659 00:24:42.669237 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5660 00:24:42.672464 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5661 00:24:42.676151 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5662 00:24:42.679677 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5663 00:24:42.685604 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5664 00:24:42.689340 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5665 00:24:42.692806 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5666 00:24:42.696083 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5667 00:24:42.696162 ==
5668 00:24:42.699376 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 00:24:42.705316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 00:24:42.705396 ==
5671 00:24:42.705458 DQS Delay:
5672 00:24:42.705516 DQS0 = 0, DQS1 = 0
5673 00:24:42.708621 DQM Delay:
5674 00:24:42.708699 DQM0 = 102, DQM1 = 91
5675 00:24:42.712913 DQ Delay:
5676 00:24:42.715249 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =103
5677 00:24:42.718769 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5678 00:24:42.722542 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5679 00:24:42.725892 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5680 00:24:42.725970
5681 00:24:42.726032
5682 00:24:42.726088 ==
5683 00:24:42.728785 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 00:24:42.731705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 00:24:42.731785 ==
5686 00:24:42.731847
5687 00:24:42.731904
5688 00:24:42.735129 TX Vref Scan disable
5689 00:24:42.738580 == TX Byte 0 ==
5690 00:24:42.741730 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5691 00:24:42.745000 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5692 00:24:42.748368 == TX Byte 1 ==
5693 00:24:42.751639 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5694 00:24:42.754798 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5695 00:24:42.754877 ==
5696 00:24:42.758141 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 00:24:42.761383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 00:24:42.764897 ==
5699 00:24:42.764975
5700 00:24:42.765038
5701 00:24:42.765095 TX Vref Scan disable
5702 00:24:42.768912 == TX Byte 0 ==
5703 00:24:42.771765 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5704 00:24:42.778197 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5705 00:24:42.778302 == TX Byte 1 ==
5706 00:24:42.781966 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5707 00:24:42.788729 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5708 00:24:42.788813
5709 00:24:42.788874 [DATLAT]
5710 00:24:42.788931 Freq=933, CH1 RK0
5711 00:24:42.788986
5712 00:24:42.791611 DATLAT Default: 0xd
5713 00:24:42.791690 0, 0xFFFF, sum = 0
5714 00:24:42.794830 1, 0xFFFF, sum = 0
5715 00:24:42.798516 2, 0xFFFF, sum = 0
5716 00:24:42.798602 3, 0xFFFF, sum = 0
5717 00:24:42.801949 4, 0xFFFF, sum = 0
5718 00:24:42.802029 5, 0xFFFF, sum = 0
5719 00:24:42.804702 6, 0xFFFF, sum = 0
5720 00:24:42.804782 7, 0xFFFF, sum = 0
5721 00:24:42.808205 8, 0xFFFF, sum = 0
5722 00:24:42.808286 9, 0xFFFF, sum = 0
5723 00:24:42.811458 10, 0x0, sum = 1
5724 00:24:42.811538 11, 0x0, sum = 2
5725 00:24:42.814761 12, 0x0, sum = 3
5726 00:24:42.814841 13, 0x0, sum = 4
5727 00:24:42.814904 best_step = 11
5728 00:24:42.817780
5729 00:24:42.817858 ==
5730 00:24:42.821550 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 00:24:42.824847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 00:24:42.824927 ==
5733 00:24:42.824988 RX Vref Scan: 1
5734 00:24:42.825045
5735 00:24:42.827918 RX Vref 0 -> 0, step: 1
5736 00:24:42.827997
5737 00:24:42.831176 RX Delay -69 -> 252, step: 4
5738 00:24:42.831257
5739 00:24:42.834489 Set Vref, RX VrefLevel [Byte0]: 48
5740 00:24:42.837463 [Byte1]: 54
5741 00:24:42.841184
5742 00:24:42.841263 Final RX Vref Byte 0 = 48 to rank0
5743 00:24:42.844741 Final RX Vref Byte 1 = 54 to rank0
5744 00:24:42.847980 Final RX Vref Byte 0 = 48 to rank1
5745 00:24:42.850868 Final RX Vref Byte 1 = 54 to rank1==
5746 00:24:42.854168 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 00:24:42.860701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 00:24:42.860780 ==
5749 00:24:42.860842 DQS Delay:
5750 00:24:42.864384 DQS0 = 0, DQS1 = 0
5751 00:24:42.864463 DQM Delay:
5752 00:24:42.864524 DQM0 = 101, DQM1 = 93
5753 00:24:42.867584 DQ Delay:
5754 00:24:42.871192 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =98
5755 00:24:42.874068 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =98
5756 00:24:42.877305 DQ8 =84, DQ9 =86, DQ10 =92, DQ11 =86
5757 00:24:42.880771 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5758 00:24:42.880850
5759 00:24:42.880912
5760 00:24:42.887335 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5761 00:24:42.890712 CH1 RK0: MR19=505, MR18=1F0F
5762 00:24:42.897129 CH1_RK0: MR19=0x505, MR18=0x1F0F, DQSOSC=412, MR23=63, INC=63, DEC=42
5763 00:24:42.897209
5764 00:24:42.900193 ----->DramcWriteLeveling(PI) begin...
5765 00:24:42.900273 ==
5766 00:24:42.903949 Dram Type= 6, Freq= 0, CH_1, rank 1
5767 00:24:42.907138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 00:24:42.910888 ==
5769 00:24:42.910966 Write leveling (Byte 0): 24 => 24
5770 00:24:42.913923 Write leveling (Byte 1): 32 => 32
5771 00:24:42.916932 DramcWriteLeveling(PI) end<-----
5772 00:24:42.917012
5773 00:24:42.917073 ==
5774 00:24:42.920532 Dram Type= 6, Freq= 0, CH_1, rank 1
5775 00:24:42.926719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 00:24:42.926802 ==
5777 00:24:42.930013 [Gating] SW mode calibration
5778 00:24:42.936876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5779 00:24:42.939789 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5780 00:24:42.946393 0 14 0 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
5781 00:24:42.950117 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 00:24:42.953008 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 00:24:42.960186 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 00:24:42.962978 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 00:24:42.966674 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 00:24:42.973249 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
5787 00:24:42.976588 0 14 28 | B1->B0 | 2828 2d2d | 0 0 | (0 0) (0 0)
5788 00:24:42.979549 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 00:24:42.986396 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 00:24:42.989827 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 00:24:42.992936 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 00:24:42.999432 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 00:24:43.002740 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 00:24:43.005756 0 15 24 | B1->B0 | 2f2e 2a2a | 1 0 | (0 0) (0 0)
5795 00:24:43.009232 0 15 28 | B1->B0 | 4343 3535 | 0 0 | (0 0) (0 0)
5796 00:24:43.016321 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5797 00:24:43.019611 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 00:24:43.022657 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 00:24:43.029886 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 00:24:43.032303 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 00:24:43.035808 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 00:24:43.042468 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5803 00:24:43.046081 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5804 00:24:43.049975 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 00:24:43.055372 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 00:24:43.058948 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 00:24:43.062144 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 00:24:43.068570 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 00:24:43.072188 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 00:24:43.075629 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 00:24:43.082082 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 00:24:43.085067 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 00:24:43.088975 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 00:24:43.095095 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 00:24:43.098320 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 00:24:43.101516 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 00:24:43.108414 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 00:24:43.112018 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5819 00:24:43.114845 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5820 00:24:43.121326 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 00:24:43.124945 Total UI for P1: 0, mck2ui 16
5822 00:24:43.127994 best dqsien dly found for B0: ( 1, 2, 26)
5823 00:24:43.131227 Total UI for P1: 0, mck2ui 16
5824 00:24:43.134611 best dqsien dly found for B1: ( 1, 2, 26)
5825 00:24:43.137894 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5826 00:24:43.141658 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5827 00:24:43.141737
5828 00:24:43.145305 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5829 00:24:43.147759 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5830 00:24:43.151560 [Gating] SW calibration Done
5831 00:24:43.151639 ==
5832 00:24:43.154524 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 00:24:43.157669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 00:24:43.157749 ==
5835 00:24:43.160956 RX Vref Scan: 0
5836 00:24:43.161034
5837 00:24:43.164324 RX Vref 0 -> 0, step: 1
5838 00:24:43.164403
5839 00:24:43.164464 RX Delay -80 -> 252, step: 8
5840 00:24:43.171088 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5841 00:24:43.174724 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5842 00:24:43.178145 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5843 00:24:43.181079 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5844 00:24:43.184245 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5845 00:24:43.187550 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5846 00:24:43.193930 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5847 00:24:43.197940 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5848 00:24:43.200512 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5849 00:24:43.204171 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5850 00:24:43.207309 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5851 00:24:43.214093 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5852 00:24:43.217251 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5853 00:24:43.220564 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5854 00:24:43.223683 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5855 00:24:43.227163 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5856 00:24:43.230282 ==
5857 00:24:43.230362 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 00:24:43.237127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 00:24:43.237207 ==
5860 00:24:43.237270 DQS Delay:
5861 00:24:43.239948 DQS0 = 0, DQS1 = 0
5862 00:24:43.240027 DQM Delay:
5863 00:24:43.243317 DQM0 = 99, DQM1 = 91
5864 00:24:43.243396 DQ Delay:
5865 00:24:43.246720 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5866 00:24:43.250152 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =91
5867 00:24:43.253549 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =83
5868 00:24:43.256559 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5869 00:24:43.256639
5870 00:24:43.256702
5871 00:24:43.256759 ==
5872 00:24:43.260100 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 00:24:43.263143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 00:24:43.263224 ==
5875 00:24:43.263286
5876 00:24:43.263344
5877 00:24:43.266557 TX Vref Scan disable
5878 00:24:43.269881 == TX Byte 0 ==
5879 00:24:43.273216 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5880 00:24:43.276254 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5881 00:24:43.279548 == TX Byte 1 ==
5882 00:24:43.283061 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5883 00:24:43.286426 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5884 00:24:43.286507 ==
5885 00:24:43.290359 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 00:24:43.296224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 00:24:43.296305 ==
5888 00:24:43.296367
5889 00:24:43.296425
5890 00:24:43.296480 TX Vref Scan disable
5891 00:24:43.300501 == TX Byte 0 ==
5892 00:24:43.303764 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5893 00:24:43.310291 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5894 00:24:43.310372 == TX Byte 1 ==
5895 00:24:43.313790 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5896 00:24:43.320410 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5897 00:24:43.320490
5898 00:24:43.320553 [DATLAT]
5899 00:24:43.320611 Freq=933, CH1 RK1
5900 00:24:43.320668
5901 00:24:43.323410 DATLAT Default: 0xb
5902 00:24:43.323490 0, 0xFFFF, sum = 0
5903 00:24:43.326862 1, 0xFFFF, sum = 0
5904 00:24:43.330044 2, 0xFFFF, sum = 0
5905 00:24:43.330125 3, 0xFFFF, sum = 0
5906 00:24:43.333360 4, 0xFFFF, sum = 0
5907 00:24:43.333441 5, 0xFFFF, sum = 0
5908 00:24:43.336717 6, 0xFFFF, sum = 0
5909 00:24:43.336798 7, 0xFFFF, sum = 0
5910 00:24:43.340144 8, 0xFFFF, sum = 0
5911 00:24:43.340225 9, 0xFFFF, sum = 0
5912 00:24:43.343391 10, 0x0, sum = 1
5913 00:24:43.343473 11, 0x0, sum = 2
5914 00:24:43.346666 12, 0x0, sum = 3
5915 00:24:43.346747 13, 0x0, sum = 4
5916 00:24:43.349912 best_step = 11
5917 00:24:43.349990
5918 00:24:43.350052 ==
5919 00:24:43.353597 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 00:24:43.356407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 00:24:43.356487 ==
5922 00:24:43.356549 RX Vref Scan: 0
5923 00:24:43.356607
5924 00:24:43.360205 RX Vref 0 -> 0, step: 1
5925 00:24:43.360285
5926 00:24:43.363181 RX Delay -61 -> 252, step: 4
5927 00:24:43.370161 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5928 00:24:43.372820 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5929 00:24:43.376380 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5930 00:24:43.379420 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5931 00:24:43.382830 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
5932 00:24:43.389224 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5933 00:24:43.392613 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5934 00:24:43.396292 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5935 00:24:43.399194 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
5936 00:24:43.402555 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5937 00:24:43.405665 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5938 00:24:43.412424 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5939 00:24:43.415582 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
5940 00:24:43.418834 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
5941 00:24:43.422246 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
5942 00:24:43.429123 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5943 00:24:43.429220 ==
5944 00:24:43.432314 Dram Type= 6, Freq= 0, CH_1, rank 1
5945 00:24:43.435963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5946 00:24:43.436061 ==
5947 00:24:43.436148 DQS Delay:
5948 00:24:43.438416 DQS0 = 0, DQS1 = 0
5949 00:24:43.438511 DQM Delay:
5950 00:24:43.442240 DQM0 = 101, DQM1 = 94
5951 00:24:43.442334 DQ Delay:
5952 00:24:43.445347 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =98
5953 00:24:43.449102 DQ4 =100, DQ5 =110, DQ6 =114, DQ7 =98
5954 00:24:43.452436 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =84
5955 00:24:43.455426 DQ12 =104, DQ13 =102, DQ14 =100, DQ15 =102
5956 00:24:43.455507
5957 00:24:43.455568
5958 00:24:43.465194 [DQSOSCAuto] RK1, (LSB)MR18= 0x902, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
5959 00:24:43.465274 CH1 RK1: MR19=505, MR18=902
5960 00:24:43.471740 CH1_RK1: MR19=0x505, MR18=0x902, DQSOSC=419, MR23=63, INC=61, DEC=41
5961 00:24:43.475053 [RxdqsGatingPostProcess] freq 933
5962 00:24:43.481840 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5963 00:24:43.484947 best DQS0 dly(2T, 0.5T) = (0, 10)
5964 00:24:43.488640 best DQS1 dly(2T, 0.5T) = (0, 10)
5965 00:24:43.492065 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5966 00:24:43.494775 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5967 00:24:43.498408 best DQS0 dly(2T, 0.5T) = (0, 10)
5968 00:24:43.501824 best DQS1 dly(2T, 0.5T) = (0, 10)
5969 00:24:43.504536 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5970 00:24:43.508301 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5971 00:24:43.508380 Pre-setting of DQS Precalculation
5972 00:24:43.514520 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5973 00:24:43.521162 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5974 00:24:43.527732 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5975 00:24:43.527812
5976 00:24:43.527874
5977 00:24:43.531311 [Calibration Summary] 1866 Mbps
5978 00:24:43.535230 CH 0, Rank 0
5979 00:24:43.535308 SW Impedance : PASS
5980 00:24:43.537629 DUTY Scan : NO K
5981 00:24:43.541357 ZQ Calibration : PASS
5982 00:24:43.541437 Jitter Meter : NO K
5983 00:24:43.544977 CBT Training : PASS
5984 00:24:43.547923 Write leveling : PASS
5985 00:24:43.548002 RX DQS gating : PASS
5986 00:24:43.551360 RX DQ/DQS(RDDQC) : PASS
5987 00:24:43.554135 TX DQ/DQS : PASS
5988 00:24:43.554214 RX DATLAT : PASS
5989 00:24:43.557670 RX DQ/DQS(Engine): PASS
5990 00:24:43.560641 TX OE : NO K
5991 00:24:43.560720 All Pass.
5992 00:24:43.560781
5993 00:24:43.560838 CH 0, Rank 1
5994 00:24:43.564259 SW Impedance : PASS
5995 00:24:43.567385 DUTY Scan : NO K
5996 00:24:43.567464 ZQ Calibration : PASS
5997 00:24:43.571007 Jitter Meter : NO K
5998 00:24:43.571110 CBT Training : PASS
5999 00:24:43.574025 Write leveling : PASS
6000 00:24:43.577275 RX DQS gating : PASS
6001 00:24:43.577354 RX DQ/DQS(RDDQC) : PASS
6002 00:24:43.580825 TX DQ/DQS : PASS
6003 00:24:43.583969 RX DATLAT : PASS
6004 00:24:43.584047 RX DQ/DQS(Engine): PASS
6005 00:24:43.587864 TX OE : NO K
6006 00:24:43.587944 All Pass.
6007 00:24:43.588006
6008 00:24:43.590378 CH 1, Rank 0
6009 00:24:43.590466 SW Impedance : PASS
6010 00:24:43.593953 DUTY Scan : NO K
6011 00:24:43.597109 ZQ Calibration : PASS
6012 00:24:43.597188 Jitter Meter : NO K
6013 00:24:43.600319 CBT Training : PASS
6014 00:24:43.603428 Write leveling : PASS
6015 00:24:43.603507 RX DQS gating : PASS
6016 00:24:43.606998 RX DQ/DQS(RDDQC) : PASS
6017 00:24:43.610124 TX DQ/DQS : PASS
6018 00:24:43.610204 RX DATLAT : PASS
6019 00:24:43.613474 RX DQ/DQS(Engine): PASS
6020 00:24:43.616899 TX OE : NO K
6021 00:24:43.616978 All Pass.
6022 00:24:43.617039
6023 00:24:43.617096 CH 1, Rank 1
6024 00:24:43.620129 SW Impedance : PASS
6025 00:24:43.623375 DUTY Scan : NO K
6026 00:24:43.623453 ZQ Calibration : PASS
6027 00:24:43.626879 Jitter Meter : NO K
6028 00:24:43.630190 CBT Training : PASS
6029 00:24:43.630268 Write leveling : PASS
6030 00:24:43.633162 RX DQS gating : PASS
6031 00:24:43.633241 RX DQ/DQS(RDDQC) : PASS
6032 00:24:43.636773 TX DQ/DQS : PASS
6033 00:24:43.639989 RX DATLAT : PASS
6034 00:24:43.640069 RX DQ/DQS(Engine): PASS
6035 00:24:43.643225 TX OE : NO K
6036 00:24:43.643342 All Pass.
6037 00:24:43.643403
6038 00:24:43.646733 DramC Write-DBI off
6039 00:24:43.650022 PER_BANK_REFRESH: Hybrid Mode
6040 00:24:43.650101 TX_TRACKING: ON
6041 00:24:43.660479 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6042 00:24:43.662908 [FAST_K] Save calibration result to emmc
6043 00:24:43.666320 dramc_set_vcore_voltage set vcore to 650000
6044 00:24:43.670119 Read voltage for 400, 6
6045 00:24:43.670195 Vio18 = 0
6046 00:24:43.672887 Vcore = 650000
6047 00:24:43.672995 Vdram = 0
6048 00:24:43.673094 Vddq = 0
6049 00:24:43.673189 Vmddr = 0
6050 00:24:43.680028 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6051 00:24:43.686198 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6052 00:24:43.686298 MEM_TYPE=3, freq_sel=20
6053 00:24:43.689491 sv_algorithm_assistance_LP4_800
6054 00:24:43.693374 ============ PULL DRAM RESETB DOWN ============
6055 00:24:43.699556 ========== PULL DRAM RESETB DOWN end =========
6056 00:24:43.702348 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6057 00:24:43.705676 ===================================
6058 00:24:43.708944 LPDDR4 DRAM CONFIGURATION
6059 00:24:43.713037 ===================================
6060 00:24:43.713139 EX_ROW_EN[0] = 0x0
6061 00:24:43.715499 EX_ROW_EN[1] = 0x0
6062 00:24:43.715599 LP4Y_EN = 0x0
6063 00:24:43.718914 WORK_FSP = 0x0
6064 00:24:43.722302 WL = 0x2
6065 00:24:43.722395 RL = 0x2
6066 00:24:43.725574 BL = 0x2
6067 00:24:43.725675 RPST = 0x0
6068 00:24:43.729459 RD_PRE = 0x0
6069 00:24:43.729551 WR_PRE = 0x1
6070 00:24:43.732496 WR_PST = 0x0
6071 00:24:43.732596 DBI_WR = 0x0
6072 00:24:43.735535 DBI_RD = 0x0
6073 00:24:43.735631 OTF = 0x1
6074 00:24:43.738752 ===================================
6075 00:24:43.742072 ===================================
6076 00:24:43.745202 ANA top config
6077 00:24:43.748843 ===================================
6078 00:24:43.748938 DLL_ASYNC_EN = 0
6079 00:24:43.752293 ALL_SLAVE_EN = 1
6080 00:24:43.755585 NEW_RANK_MODE = 1
6081 00:24:43.758906 DLL_IDLE_MODE = 1
6082 00:24:43.761787 LP45_APHY_COMB_EN = 1
6083 00:24:43.761881 TX_ODT_DIS = 1
6084 00:24:43.765152 NEW_8X_MODE = 1
6085 00:24:43.768446 ===================================
6086 00:24:43.771677 ===================================
6087 00:24:43.775056 data_rate = 800
6088 00:24:43.778858 CKR = 1
6089 00:24:43.781680 DQ_P2S_RATIO = 4
6090 00:24:43.785500 ===================================
6091 00:24:43.785595 CA_P2S_RATIO = 4
6092 00:24:43.788309 DQ_CA_OPEN = 0
6093 00:24:43.791604 DQ_SEMI_OPEN = 1
6094 00:24:43.795264 CA_SEMI_OPEN = 1
6095 00:24:43.798493 CA_FULL_RATE = 0
6096 00:24:43.801896 DQ_CKDIV4_EN = 0
6097 00:24:43.801975 CA_CKDIV4_EN = 1
6098 00:24:43.805435 CA_PREDIV_EN = 0
6099 00:24:43.808398 PH8_DLY = 0
6100 00:24:43.811468 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6101 00:24:43.815198 DQ_AAMCK_DIV = 0
6102 00:24:43.818130 CA_AAMCK_DIV = 0
6103 00:24:43.821164 CA_ADMCK_DIV = 4
6104 00:24:43.821243 DQ_TRACK_CA_EN = 0
6105 00:24:43.824992 CA_PICK = 800
6106 00:24:43.828607 CA_MCKIO = 400
6107 00:24:43.831461 MCKIO_SEMI = 400
6108 00:24:43.834707 PLL_FREQ = 3016
6109 00:24:43.837686 DQ_UI_PI_RATIO = 32
6110 00:24:43.841303 CA_UI_PI_RATIO = 32
6111 00:24:43.844724 ===================================
6112 00:24:43.847633 ===================================
6113 00:24:43.847712 memory_type:LPDDR4
6114 00:24:43.851139 GP_NUM : 10
6115 00:24:43.854755 SRAM_EN : 1
6116 00:24:43.854833 MD32_EN : 0
6117 00:24:43.857879 ===================================
6118 00:24:43.860835 [ANA_INIT] >>>>>>>>>>>>>>
6119 00:24:43.864368 <<<<<< [CONFIGURE PHASE]: ANA_TX
6120 00:24:43.867841 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6121 00:24:43.871273 ===================================
6122 00:24:43.874369 data_rate = 800,PCW = 0X7400
6123 00:24:43.877454 ===================================
6124 00:24:43.880896 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6125 00:24:43.884424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6126 00:24:43.897504 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6127 00:24:43.900880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6128 00:24:43.903739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6129 00:24:43.907650 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6130 00:24:43.911205 [ANA_INIT] flow start
6131 00:24:43.913969 [ANA_INIT] PLL >>>>>>>>
6132 00:24:43.914047 [ANA_INIT] PLL <<<<<<<<
6133 00:24:43.917931 [ANA_INIT] MIDPI >>>>>>>>
6134 00:24:43.920656 [ANA_INIT] MIDPI <<<<<<<<
6135 00:24:43.920734 [ANA_INIT] DLL >>>>>>>>
6136 00:24:43.923846 [ANA_INIT] flow end
6137 00:24:43.927089 ============ LP4 DIFF to SE enter ============
6138 00:24:43.930858 ============ LP4 DIFF to SE exit ============
6139 00:24:43.933961 [ANA_INIT] <<<<<<<<<<<<<
6140 00:24:43.937250 [Flow] Enable top DCM control >>>>>
6141 00:24:43.940216 [Flow] Enable top DCM control <<<<<
6142 00:24:43.943847 Enable DLL master slave shuffle
6143 00:24:43.950231 ==============================================================
6144 00:24:43.950310 Gating Mode config
6145 00:24:43.957358 ==============================================================
6146 00:24:43.957437 Config description:
6147 00:24:43.966988 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6148 00:24:43.973578 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6149 00:24:43.979834 SELPH_MODE 0: By rank 1: By Phase
6150 00:24:43.986547 ==============================================================
6151 00:24:43.989978 GAT_TRACK_EN = 0
6152 00:24:43.990056 RX_GATING_MODE = 2
6153 00:24:43.993486 RX_GATING_TRACK_MODE = 2
6154 00:24:43.996404 SELPH_MODE = 1
6155 00:24:43.999898 PICG_EARLY_EN = 1
6156 00:24:44.002848 VALID_LAT_VALUE = 1
6157 00:24:44.010302 ==============================================================
6158 00:24:44.012727 Enter into Gating configuration >>>>
6159 00:24:44.016053 Exit from Gating configuration <<<<
6160 00:24:44.019326 Enter into DVFS_PRE_config >>>>>
6161 00:24:44.029195 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6162 00:24:44.032839 Exit from DVFS_PRE_config <<<<<
6163 00:24:44.035710 Enter into PICG configuration >>>>
6164 00:24:44.039418 Exit from PICG configuration <<<<
6165 00:24:44.043653 [RX_INPUT] configuration >>>>>
6166 00:24:44.046044 [RX_INPUT] configuration <<<<<
6167 00:24:44.048925 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6168 00:24:44.056204 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6169 00:24:44.062574 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6170 00:24:44.068822 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6171 00:24:44.072157 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6172 00:24:44.078650 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6173 00:24:44.085299 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6174 00:24:44.088387 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6175 00:24:44.092159 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6176 00:24:44.095451 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6177 00:24:44.099154 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6178 00:24:44.105208 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6179 00:24:44.108543 ===================================
6180 00:24:44.111844 LPDDR4 DRAM CONFIGURATION
6181 00:24:44.114968 ===================================
6182 00:24:44.115047 EX_ROW_EN[0] = 0x0
6183 00:24:44.118500 EX_ROW_EN[1] = 0x0
6184 00:24:44.118578 LP4Y_EN = 0x0
6185 00:24:44.121626 WORK_FSP = 0x0
6186 00:24:44.121705 WL = 0x2
6187 00:24:44.124792 RL = 0x2
6188 00:24:44.124870 BL = 0x2
6189 00:24:44.128354 RPST = 0x0
6190 00:24:44.128431 RD_PRE = 0x0
6191 00:24:44.131624 WR_PRE = 0x1
6192 00:24:44.131730 WR_PST = 0x0
6193 00:24:44.134736 DBI_WR = 0x0
6194 00:24:44.138207 DBI_RD = 0x0
6195 00:24:44.138306 OTF = 0x1
6196 00:24:44.141438 ===================================
6197 00:24:44.144940 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6198 00:24:44.147892 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6199 00:24:44.154633 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6200 00:24:44.157975 ===================================
6201 00:24:44.162104 LPDDR4 DRAM CONFIGURATION
6202 00:24:44.162183 ===================================
6203 00:24:44.164693 EX_ROW_EN[0] = 0x10
6204 00:24:44.168142 EX_ROW_EN[1] = 0x0
6205 00:24:44.168220 LP4Y_EN = 0x0
6206 00:24:44.171435 WORK_FSP = 0x0
6207 00:24:44.171512 WL = 0x2
6208 00:24:44.174817 RL = 0x2
6209 00:24:44.174895 BL = 0x2
6210 00:24:44.177760 RPST = 0x0
6211 00:24:44.177838 RD_PRE = 0x0
6212 00:24:44.181114 WR_PRE = 0x1
6213 00:24:44.181192 WR_PST = 0x0
6214 00:24:44.184361 DBI_WR = 0x0
6215 00:24:44.184438 DBI_RD = 0x0
6216 00:24:44.187603 OTF = 0x1
6217 00:24:44.191052 ===================================
6218 00:24:44.197744 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6219 00:24:44.201046 nWR fixed to 30
6220 00:24:44.204642 [ModeRegInit_LP4] CH0 RK0
6221 00:24:44.204721 [ModeRegInit_LP4] CH0 RK1
6222 00:24:44.207712 [ModeRegInit_LP4] CH1 RK0
6223 00:24:44.211055 [ModeRegInit_LP4] CH1 RK1
6224 00:24:44.211133 match AC timing 19
6225 00:24:44.217940 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6226 00:24:44.220890 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6227 00:24:44.223955 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6228 00:24:44.230890 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6229 00:24:44.233813 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6230 00:24:44.233892 ==
6231 00:24:44.237182 Dram Type= 6, Freq= 0, CH_0, rank 0
6232 00:24:44.240376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6233 00:24:44.240456 ==
6234 00:24:44.247093 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6235 00:24:44.253621 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6236 00:24:44.257064 [CA 0] Center 36 (8~64) winsize 57
6237 00:24:44.260477 [CA 1] Center 36 (8~64) winsize 57
6238 00:24:44.263879 [CA 2] Center 36 (8~64) winsize 57
6239 00:24:44.267450 [CA 3] Center 36 (8~64) winsize 57
6240 00:24:44.270681 [CA 4] Center 36 (8~64) winsize 57
6241 00:24:44.270761 [CA 5] Center 36 (8~64) winsize 57
6242 00:24:44.273575
6243 00:24:44.276900 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6244 00:24:44.276979
6245 00:24:44.280251 [CATrainingPosCal] consider 1 rank data
6246 00:24:44.283691 u2DelayCellTimex100 = 270/100 ps
6247 00:24:44.286834 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 00:24:44.290233 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 00:24:44.293392 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 00:24:44.297265 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 00:24:44.300140 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 00:24:44.303441 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 00:24:44.303520
6254 00:24:44.307138 CA PerBit enable=1, Macro0, CA PI delay=36
6255 00:24:44.307217
6256 00:24:44.310005 [CBTSetCACLKResult] CA Dly = 36
6257 00:24:44.313738 CS Dly: 1 (0~32)
6258 00:24:44.313816 ==
6259 00:24:44.317164 Dram Type= 6, Freq= 0, CH_0, rank 1
6260 00:24:44.320322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 00:24:44.320400 ==
6262 00:24:44.327201 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6263 00:24:44.333485 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6264 00:24:44.336837 [CA 0] Center 36 (8~64) winsize 57
6265 00:24:44.339984 [CA 1] Center 36 (8~64) winsize 57
6266 00:24:44.340063 [CA 2] Center 36 (8~64) winsize 57
6267 00:24:44.343228 [CA 3] Center 36 (8~64) winsize 57
6268 00:24:44.346313 [CA 4] Center 36 (8~64) winsize 57
6269 00:24:44.350393 [CA 5] Center 36 (8~64) winsize 57
6270 00:24:44.350472
6271 00:24:44.353096 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6272 00:24:44.356532
6273 00:24:44.360046 [CATrainingPosCal] consider 2 rank data
6274 00:24:44.360125 u2DelayCellTimex100 = 270/100 ps
6275 00:24:44.366585 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 00:24:44.369733 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 00:24:44.373151 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 00:24:44.376406 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 00:24:44.380260 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 00:24:44.383052 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 00:24:44.383130
6282 00:24:44.386506 CA PerBit enable=1, Macro0, CA PI delay=36
6283 00:24:44.386584
6284 00:24:44.389739 [CBTSetCACLKResult] CA Dly = 36
6285 00:24:44.392712 CS Dly: 1 (0~32)
6286 00:24:44.392790
6287 00:24:44.396587 ----->DramcWriteLeveling(PI) begin...
6288 00:24:44.396667 ==
6289 00:24:44.399702 Dram Type= 6, Freq= 0, CH_0, rank 0
6290 00:24:44.402939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 00:24:44.403018 ==
6292 00:24:44.406424 Write leveling (Byte 0): 40 => 8
6293 00:24:44.409770 Write leveling (Byte 1): 32 => 0
6294 00:24:44.412616 DramcWriteLeveling(PI) end<-----
6295 00:24:44.412687
6296 00:24:44.412749 ==
6297 00:24:44.416431 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 00:24:44.419935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 00:24:44.420007 ==
6300 00:24:44.423154 [Gating] SW mode calibration
6301 00:24:44.429264 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6302 00:24:44.435939 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6303 00:24:44.439328 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6304 00:24:44.442617 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6305 00:24:44.449053 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6306 00:24:44.452941 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6307 00:24:44.455744 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6308 00:24:44.462318 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 00:24:44.465856 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 00:24:44.469379 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 00:24:44.475678 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6312 00:24:44.479577 Total UI for P1: 0, mck2ui 16
6313 00:24:44.482283 best dqsien dly found for B0: ( 0, 14, 24)
6314 00:24:44.482378 Total UI for P1: 0, mck2ui 16
6315 00:24:44.489237 best dqsien dly found for B1: ( 0, 14, 24)
6316 00:24:44.492076 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6317 00:24:44.495413 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6318 00:24:44.495483
6319 00:24:44.499263 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6320 00:24:44.501789 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6321 00:24:44.505364 [Gating] SW calibration Done
6322 00:24:44.505433 ==
6323 00:24:44.508704 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 00:24:44.512206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 00:24:44.512302 ==
6326 00:24:44.515237 RX Vref Scan: 0
6327 00:24:44.515308
6328 00:24:44.518333 RX Vref 0 -> 0, step: 1
6329 00:24:44.518401
6330 00:24:44.518473 RX Delay -410 -> 252, step: 16
6331 00:24:44.525002 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6332 00:24:44.528438 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6333 00:24:44.531421 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6334 00:24:44.538831 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6335 00:24:44.541751 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6336 00:24:44.544878 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6337 00:24:44.548090 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6338 00:24:44.554927 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6339 00:24:44.557768 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6340 00:24:44.561332 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6341 00:24:44.564731 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6342 00:24:44.571440 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6343 00:24:44.574574 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6344 00:24:44.577948 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6345 00:24:44.581081 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6346 00:24:44.587866 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6347 00:24:44.587945 ==
6348 00:24:44.591281 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 00:24:44.594303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 00:24:44.594382 ==
6351 00:24:44.594443 DQS Delay:
6352 00:24:44.597575 DQS0 = 43, DQS1 = 59
6353 00:24:44.597653 DQM Delay:
6354 00:24:44.600657 DQM0 = 10, DQM1 = 12
6355 00:24:44.600760 DQ Delay:
6356 00:24:44.603991 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6357 00:24:44.607227 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6358 00:24:44.611222 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6359 00:24:44.613964 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6360 00:24:44.614057
6361 00:24:44.614145
6362 00:24:44.614230 ==
6363 00:24:44.617396 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 00:24:44.620738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 00:24:44.620814 ==
6366 00:24:44.624062
6367 00:24:44.624157
6368 00:24:44.624242 TX Vref Scan disable
6369 00:24:44.627175 == TX Byte 0 ==
6370 00:24:44.630500 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6371 00:24:44.633813 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6372 00:24:44.637379 == TX Byte 1 ==
6373 00:24:44.640785 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6374 00:24:44.643565 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6375 00:24:44.643662 ==
6376 00:24:44.647730 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 00:24:44.653840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 00:24:44.653940 ==
6379 00:24:44.654028
6380 00:24:44.654114
6381 00:24:44.654198 TX Vref Scan disable
6382 00:24:44.657393 == TX Byte 0 ==
6383 00:24:44.660543 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6384 00:24:44.663332 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6385 00:24:44.667614 == TX Byte 1 ==
6386 00:24:44.670172 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6387 00:24:44.673364 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6388 00:24:44.673443
6389 00:24:44.676844 [DATLAT]
6390 00:24:44.676922 Freq=400, CH0 RK0
6391 00:24:44.676983
6392 00:24:44.680177 DATLAT Default: 0xf
6393 00:24:44.680256 0, 0xFFFF, sum = 0
6394 00:24:44.683297 1, 0xFFFF, sum = 0
6395 00:24:44.683377 2, 0xFFFF, sum = 0
6396 00:24:44.687068 3, 0xFFFF, sum = 0
6397 00:24:44.687148 4, 0xFFFF, sum = 0
6398 00:24:44.689905 5, 0xFFFF, sum = 0
6399 00:24:44.689984 6, 0xFFFF, sum = 0
6400 00:24:44.693383 7, 0xFFFF, sum = 0
6401 00:24:44.693463 8, 0xFFFF, sum = 0
6402 00:24:44.696725 9, 0xFFFF, sum = 0
6403 00:24:44.699634 10, 0xFFFF, sum = 0
6404 00:24:44.699713 11, 0xFFFF, sum = 0
6405 00:24:44.703368 12, 0xFFFF, sum = 0
6406 00:24:44.703448 13, 0x0, sum = 1
6407 00:24:44.706420 14, 0x0, sum = 2
6408 00:24:44.706500 15, 0x0, sum = 3
6409 00:24:44.709667 16, 0x0, sum = 4
6410 00:24:44.709748 best_step = 14
6411 00:24:44.709809
6412 00:24:44.709866 ==
6413 00:24:44.712983 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 00:24:44.716661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 00:24:44.716740 ==
6416 00:24:44.720018 RX Vref Scan: 1
6417 00:24:44.720097
6418 00:24:44.723014 RX Vref 0 -> 0, step: 1
6419 00:24:44.723093
6420 00:24:44.723155 RX Delay -359 -> 252, step: 8
6421 00:24:44.723212
6422 00:24:44.727101 Set Vref, RX VrefLevel [Byte0]: 60
6423 00:24:44.729823 [Byte1]: 57
6424 00:24:44.735164
6425 00:24:44.735242 Final RX Vref Byte 0 = 60 to rank0
6426 00:24:44.738556 Final RX Vref Byte 1 = 57 to rank0
6427 00:24:44.741688 Final RX Vref Byte 0 = 60 to rank1
6428 00:24:44.745518 Final RX Vref Byte 1 = 57 to rank1==
6429 00:24:44.748703 Dram Type= 6, Freq= 0, CH_0, rank 0
6430 00:24:44.755099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 00:24:44.755178 ==
6432 00:24:44.755240 DQS Delay:
6433 00:24:44.758155 DQS0 = 48, DQS1 = 60
6434 00:24:44.758234 DQM Delay:
6435 00:24:44.758295 DQM0 = 12, DQM1 = 11
6436 00:24:44.761801 DQ Delay:
6437 00:24:44.764763 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6438 00:24:44.768231 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =24
6439 00:24:44.768310 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6440 00:24:44.771494 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6441 00:24:44.774948
6442 00:24:44.775029
6443 00:24:44.781675 [DQSOSCAuto] RK0, (LSB)MR18= 0xc486, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 385 ps
6444 00:24:44.784808 CH0 RK0: MR19=C0C, MR18=C486
6445 00:24:44.791708 CH0_RK0: MR19=0xC0C, MR18=0xC486, DQSOSC=385, MR23=63, INC=398, DEC=265
6446 00:24:44.791791 ==
6447 00:24:44.794861 Dram Type= 6, Freq= 0, CH_0, rank 1
6448 00:24:44.798215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 00:24:44.798319 ==
6450 00:24:44.801483 [Gating] SW mode calibration
6451 00:24:44.807929 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6452 00:24:44.814574 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6453 00:24:44.818396 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6454 00:24:44.821266 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6455 00:24:44.828246 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6456 00:24:44.831418 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 00:24:44.834093 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 00:24:44.840813 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 00:24:44.844358 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 00:24:44.847354 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 00:24:44.853957 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6462 00:24:44.854037 Total UI for P1: 0, mck2ui 16
6463 00:24:44.860531 best dqsien dly found for B0: ( 0, 14, 24)
6464 00:24:44.860638 Total UI for P1: 0, mck2ui 16
6465 00:24:44.867218 best dqsien dly found for B1: ( 0, 14, 24)
6466 00:24:44.870943 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6467 00:24:44.873677 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6468 00:24:44.873781
6469 00:24:44.877177 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6470 00:24:44.880254 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6471 00:24:44.884404 [Gating] SW calibration Done
6472 00:24:44.884482 ==
6473 00:24:44.887420 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 00:24:44.890457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 00:24:44.890537 ==
6476 00:24:44.893821 RX Vref Scan: 0
6477 00:24:44.893899
6478 00:24:44.893960 RX Vref 0 -> 0, step: 1
6479 00:24:44.897144
6480 00:24:44.897222 RX Delay -410 -> 252, step: 16
6481 00:24:44.904120 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6482 00:24:44.906794 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6483 00:24:44.910278 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6484 00:24:44.913698 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6485 00:24:44.920559 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6486 00:24:44.923260 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6487 00:24:44.926501 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6488 00:24:44.930070 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6489 00:24:44.936478 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6490 00:24:44.939814 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6491 00:24:44.943422 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6492 00:24:44.949732 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6493 00:24:44.953101 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6494 00:24:44.956282 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6495 00:24:44.959532 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6496 00:24:44.966159 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6497 00:24:44.966237 ==
6498 00:24:44.969664 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 00:24:44.973051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 00:24:44.973132 ==
6501 00:24:44.973194 DQS Delay:
6502 00:24:44.976035 DQS0 = 43, DQS1 = 59
6503 00:24:44.976114 DQM Delay:
6504 00:24:44.979722 DQM0 = 10, DQM1 = 14
6505 00:24:44.979801 DQ Delay:
6506 00:24:44.982574 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6507 00:24:44.985894 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6508 00:24:44.989151 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6509 00:24:44.992799 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6510 00:24:44.992878
6511 00:24:44.992939
6512 00:24:44.992996 ==
6513 00:24:44.995719 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 00:24:44.999372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 00:24:44.999451 ==
6516 00:24:44.999513
6517 00:24:45.002565
6518 00:24:45.002653 TX Vref Scan disable
6519 00:24:45.006029 == TX Byte 0 ==
6520 00:24:45.009124 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6521 00:24:45.012055 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6522 00:24:45.015310 == TX Byte 1 ==
6523 00:24:45.018917 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6524 00:24:45.022152 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6525 00:24:45.022230 ==
6526 00:24:45.025362 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 00:24:45.028979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 00:24:45.032370 ==
6529 00:24:45.032448
6530 00:24:45.032509
6531 00:24:45.032565 TX Vref Scan disable
6532 00:24:45.035284 == TX Byte 0 ==
6533 00:24:45.038567 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6534 00:24:45.041667 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6535 00:24:45.045282 == TX Byte 1 ==
6536 00:24:45.048389 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6537 00:24:45.052124 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6538 00:24:45.052203
6539 00:24:45.054996 [DATLAT]
6540 00:24:45.055074 Freq=400, CH0 RK1
6541 00:24:45.055136
6542 00:24:45.058791 DATLAT Default: 0xe
6543 00:24:45.058900 0, 0xFFFF, sum = 0
6544 00:24:45.061633 1, 0xFFFF, sum = 0
6545 00:24:45.061731 2, 0xFFFF, sum = 0
6546 00:24:45.064846 3, 0xFFFF, sum = 0
6547 00:24:45.064922 4, 0xFFFF, sum = 0
6548 00:24:45.068229 5, 0xFFFF, sum = 0
6549 00:24:45.068326 6, 0xFFFF, sum = 0
6550 00:24:45.071245 7, 0xFFFF, sum = 0
6551 00:24:45.071348 8, 0xFFFF, sum = 0
6552 00:24:45.074699 9, 0xFFFF, sum = 0
6553 00:24:45.074775 10, 0xFFFF, sum = 0
6554 00:24:45.078472 11, 0xFFFF, sum = 0
6555 00:24:45.081240 12, 0xFFFF, sum = 0
6556 00:24:45.081312 13, 0x0, sum = 1
6557 00:24:45.081386 14, 0x0, sum = 2
6558 00:24:45.085320 15, 0x0, sum = 3
6559 00:24:45.085385 16, 0x0, sum = 4
6560 00:24:45.087904 best_step = 14
6561 00:24:45.087969
6562 00:24:45.088028 ==
6563 00:24:45.091064 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 00:24:45.094870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 00:24:45.094936 ==
6566 00:24:45.098276 RX Vref Scan: 0
6567 00:24:45.098341
6568 00:24:45.098396 RX Vref 0 -> 0, step: 1
6569 00:24:45.101184
6570 00:24:45.101279 RX Delay -359 -> 252, step: 8
6571 00:24:45.109161 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6572 00:24:45.112809 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6573 00:24:45.115977 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6574 00:24:45.123016 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6575 00:24:45.126205 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6576 00:24:45.129039 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6577 00:24:45.132820 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6578 00:24:45.139170 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6579 00:24:45.142694 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6580 00:24:45.145543 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6581 00:24:45.148900 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6582 00:24:45.155398 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6583 00:24:45.158991 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6584 00:24:45.162319 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6585 00:24:45.168854 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6586 00:24:45.171920 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6587 00:24:45.172029 ==
6588 00:24:45.175208 Dram Type= 6, Freq= 0, CH_0, rank 1
6589 00:24:45.178688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 00:24:45.178762 ==
6591 00:24:45.182241 DQS Delay:
6592 00:24:45.182340 DQS0 = 44, DQS1 = 56
6593 00:24:45.182434 DQM Delay:
6594 00:24:45.185089 DQM0 = 8, DQM1 = 11
6595 00:24:45.185180 DQ Delay:
6596 00:24:45.188370 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6597 00:24:45.191980 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6598 00:24:45.195350 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6599 00:24:45.198937 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6600 00:24:45.199005
6601 00:24:45.199078
6602 00:24:45.204878 [DQSOSCAuto] RK1, (LSB)MR18= 0xb944, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6603 00:24:45.208796 CH0 RK1: MR19=C0C, MR18=B944
6604 00:24:45.214755 CH0_RK1: MR19=0xC0C, MR18=0xB944, DQSOSC=386, MR23=63, INC=396, DEC=264
6605 00:24:45.218488 [RxdqsGatingPostProcess] freq 400
6606 00:24:45.224671 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6607 00:24:45.228328 best DQS0 dly(2T, 0.5T) = (0, 10)
6608 00:24:45.231402 best DQS1 dly(2T, 0.5T) = (0, 10)
6609 00:24:45.234898 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6610 00:24:45.238748 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6611 00:24:45.238820 best DQS0 dly(2T, 0.5T) = (0, 10)
6612 00:24:45.241576 best DQS1 dly(2T, 0.5T) = (0, 10)
6613 00:24:45.244583 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6614 00:24:45.248149 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6615 00:24:45.251548 Pre-setting of DQS Precalculation
6616 00:24:45.257850 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6617 00:24:45.257924 ==
6618 00:24:45.261008 Dram Type= 6, Freq= 0, CH_1, rank 0
6619 00:24:45.264737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 00:24:45.264833 ==
6621 00:24:45.271062 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6622 00:24:45.277926 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6623 00:24:45.281457 [CA 0] Center 36 (8~64) winsize 57
6624 00:24:45.281559 [CA 1] Center 36 (8~64) winsize 57
6625 00:24:45.284609 [CA 2] Center 36 (8~64) winsize 57
6626 00:24:45.287494 [CA 3] Center 36 (8~64) winsize 57
6627 00:24:45.290822 [CA 4] Center 36 (8~64) winsize 57
6628 00:24:45.294646 [CA 5] Center 36 (8~64) winsize 57
6629 00:24:45.294730
6630 00:24:45.298006 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6631 00:24:45.300832
6632 00:24:45.303988 [CATrainingPosCal] consider 1 rank data
6633 00:24:45.304070 u2DelayCellTimex100 = 270/100 ps
6634 00:24:45.310945 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 00:24:45.314184 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 00:24:45.317179 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 00:24:45.320552 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 00:24:45.323878 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 00:24:45.327108 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 00:24:45.327190
6641 00:24:45.330633 CA PerBit enable=1, Macro0, CA PI delay=36
6642 00:24:45.330715
6643 00:24:45.333527 [CBTSetCACLKResult] CA Dly = 36
6644 00:24:45.337015 CS Dly: 1 (0~32)
6645 00:24:45.337095 ==
6646 00:24:45.340376 Dram Type= 6, Freq= 0, CH_1, rank 1
6647 00:24:45.343763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 00:24:45.343845 ==
6649 00:24:45.350264 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6650 00:24:45.356801 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6651 00:24:45.356883 [CA 0] Center 36 (8~64) winsize 57
6652 00:24:45.359895 [CA 1] Center 36 (8~64) winsize 57
6653 00:24:45.363154 [CA 2] Center 36 (8~64) winsize 57
6654 00:24:45.366708 [CA 3] Center 36 (8~64) winsize 57
6655 00:24:45.370074 [CA 4] Center 36 (8~64) winsize 57
6656 00:24:45.373185 [CA 5] Center 36 (8~64) winsize 57
6657 00:24:45.373260
6658 00:24:45.376414 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6659 00:24:45.376509
6660 00:24:45.379637 [CATrainingPosCal] consider 2 rank data
6661 00:24:45.383090 u2DelayCellTimex100 = 270/100 ps
6662 00:24:45.386707 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 00:24:45.392978 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 00:24:45.397316 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 00:24:45.400028 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 00:24:45.402869 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 00:24:45.406440 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 00:24:45.406521
6669 00:24:45.409848 CA PerBit enable=1, Macro0, CA PI delay=36
6670 00:24:45.409929
6671 00:24:45.413150 [CBTSetCACLKResult] CA Dly = 36
6672 00:24:45.416483 CS Dly: 1 (0~32)
6673 00:24:45.416564
6674 00:24:45.419491 ----->DramcWriteLeveling(PI) begin...
6675 00:24:45.419574 ==
6676 00:24:45.422803 Dram Type= 6, Freq= 0, CH_1, rank 0
6677 00:24:45.426439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 00:24:45.426522 ==
6679 00:24:45.429331 Write leveling (Byte 0): 40 => 8
6680 00:24:45.432784 Write leveling (Byte 1): 40 => 8
6681 00:24:45.435895 DramcWriteLeveling(PI) end<-----
6682 00:24:45.435976
6683 00:24:45.436058 ==
6684 00:24:45.439220 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 00:24:45.442768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 00:24:45.442851 ==
6687 00:24:45.445754 [Gating] SW mode calibration
6688 00:24:45.452651 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6689 00:24:45.459096 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6690 00:24:45.462327 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6691 00:24:45.466017 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6692 00:24:45.472307 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6693 00:24:45.475816 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6694 00:24:45.478928 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6695 00:24:45.485848 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 00:24:45.488773 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 00:24:45.492413 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 00:24:45.499080 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6699 00:24:45.499162 Total UI for P1: 0, mck2ui 16
6700 00:24:45.505650 best dqsien dly found for B0: ( 0, 14, 24)
6701 00:24:45.505733 Total UI for P1: 0, mck2ui 16
6702 00:24:45.512215 best dqsien dly found for B1: ( 0, 14, 24)
6703 00:24:45.516163 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6704 00:24:45.518676 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6705 00:24:45.518756
6706 00:24:45.521790 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6707 00:24:45.525714 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6708 00:24:45.528222 [Gating] SW calibration Done
6709 00:24:45.528302 ==
6710 00:24:45.531671 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 00:24:45.534907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 00:24:45.534988 ==
6713 00:24:45.538392 RX Vref Scan: 0
6714 00:24:45.538472
6715 00:24:45.538534 RX Vref 0 -> 0, step: 1
6716 00:24:45.541541
6717 00:24:45.541620 RX Delay -410 -> 252, step: 16
6718 00:24:45.548244 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6719 00:24:45.551562 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6720 00:24:45.554884 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6721 00:24:45.558306 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6722 00:24:45.564711 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6723 00:24:45.567769 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6724 00:24:45.571488 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6725 00:24:45.574543 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6726 00:24:45.581351 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6727 00:24:45.584541 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6728 00:24:45.587894 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6729 00:24:45.593983 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6730 00:24:45.597344 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6731 00:24:45.600836 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6732 00:24:45.604165 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6733 00:24:45.610781 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6734 00:24:45.610861 ==
6735 00:24:45.613848 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 00:24:45.617467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 00:24:45.617548 ==
6738 00:24:45.617611 DQS Delay:
6739 00:24:45.621070 DQS0 = 43, DQS1 = 51
6740 00:24:45.621149 DQM Delay:
6741 00:24:45.623837 DQM0 = 12, DQM1 = 14
6742 00:24:45.623916 DQ Delay:
6743 00:24:45.627298 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6744 00:24:45.630637 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6745 00:24:45.634115 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6746 00:24:45.637425 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6747 00:24:45.637505
6748 00:24:45.637567
6749 00:24:45.637625 ==
6750 00:24:45.640630 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 00:24:45.643813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 00:24:45.643894 ==
6753 00:24:45.643957
6754 00:24:45.644015
6755 00:24:45.647127 TX Vref Scan disable
6756 00:24:45.650711 == TX Byte 0 ==
6757 00:24:45.654102 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6758 00:24:45.657449 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6759 00:24:45.660240 == TX Byte 1 ==
6760 00:24:45.663648 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6761 00:24:45.666899 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6762 00:24:45.666978 ==
6763 00:24:45.670153 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 00:24:45.673546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 00:24:45.676687 ==
6766 00:24:45.676767
6767 00:24:45.676829
6768 00:24:45.676886 TX Vref Scan disable
6769 00:24:45.680262 == TX Byte 0 ==
6770 00:24:45.683329 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6771 00:24:45.686823 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6772 00:24:45.690522 == TX Byte 1 ==
6773 00:24:45.693564 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6774 00:24:45.696768 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6775 00:24:45.696848
6776 00:24:45.696910 [DATLAT]
6777 00:24:45.700159 Freq=400, CH1 RK0
6778 00:24:45.700239
6779 00:24:45.703210 DATLAT Default: 0xf
6780 00:24:45.703289 0, 0xFFFF, sum = 0
6781 00:24:45.706836 1, 0xFFFF, sum = 0
6782 00:24:45.706917 2, 0xFFFF, sum = 0
6783 00:24:45.709736 3, 0xFFFF, sum = 0
6784 00:24:45.709817 4, 0xFFFF, sum = 0
6785 00:24:45.713220 5, 0xFFFF, sum = 0
6786 00:24:45.713301 6, 0xFFFF, sum = 0
6787 00:24:45.716512 7, 0xFFFF, sum = 0
6788 00:24:45.716593 8, 0xFFFF, sum = 0
6789 00:24:45.720008 9, 0xFFFF, sum = 0
6790 00:24:45.720088 10, 0xFFFF, sum = 0
6791 00:24:45.723110 11, 0xFFFF, sum = 0
6792 00:24:45.723191 12, 0xFFFF, sum = 0
6793 00:24:45.726277 13, 0x0, sum = 1
6794 00:24:45.726358 14, 0x0, sum = 2
6795 00:24:45.729891 15, 0x0, sum = 3
6796 00:24:45.729972 16, 0x0, sum = 4
6797 00:24:45.733037 best_step = 14
6798 00:24:45.733116
6799 00:24:45.733179 ==
6800 00:24:45.736192 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 00:24:45.740003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 00:24:45.740086 ==
6803 00:24:45.742865 RX Vref Scan: 1
6804 00:24:45.742945
6805 00:24:45.743007 RX Vref 0 -> 0, step: 1
6806 00:24:45.743065
6807 00:24:45.746203 RX Delay -343 -> 252, step: 8
6808 00:24:45.746283
6809 00:24:45.749332 Set Vref, RX VrefLevel [Byte0]: 48
6810 00:24:45.752518 [Byte1]: 54
6811 00:24:45.757738
6812 00:24:45.757817 Final RX Vref Byte 0 = 48 to rank0
6813 00:24:45.761392 Final RX Vref Byte 1 = 54 to rank0
6814 00:24:45.764443 Final RX Vref Byte 0 = 48 to rank1
6815 00:24:45.767439 Final RX Vref Byte 1 = 54 to rank1==
6816 00:24:45.771041 Dram Type= 6, Freq= 0, CH_1, rank 0
6817 00:24:45.777844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 00:24:45.777925 ==
6819 00:24:45.777986 DQS Delay:
6820 00:24:45.781067 DQS0 = 44, DQS1 = 56
6821 00:24:45.781147 DQM Delay:
6822 00:24:45.781209 DQM0 = 7, DQM1 = 11
6823 00:24:45.784126 DQ Delay:
6824 00:24:45.787660 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6825 00:24:45.787739 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6826 00:24:45.791123 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6827 00:24:45.794203 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6828 00:24:45.794283
6829 00:24:45.794345
6830 00:24:45.803701 [DQSOSCAuto] RK0, (LSB)MR18= 0xa278, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 389 ps
6831 00:24:45.807651 CH1 RK0: MR19=C0C, MR18=A278
6832 00:24:45.813520 CH1_RK0: MR19=0xC0C, MR18=0xA278, DQSOSC=389, MR23=63, INC=390, DEC=260
6833 00:24:45.813600 ==
6834 00:24:45.817150 Dram Type= 6, Freq= 0, CH_1, rank 1
6835 00:24:45.820331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 00:24:45.820412 ==
6837 00:24:45.823922 [Gating] SW mode calibration
6838 00:24:45.830235 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6839 00:24:45.837329 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6840 00:24:45.840136 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6841 00:24:45.843472 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6842 00:24:45.850214 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6843 00:24:45.853325 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6844 00:24:45.856560 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6845 00:24:45.863227 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 00:24:45.866353 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 00:24:45.869659 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 00:24:45.876768 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6849 00:24:45.876849 Total UI for P1: 0, mck2ui 16
6850 00:24:45.882838 best dqsien dly found for B0: ( 0, 14, 24)
6851 00:24:45.882918 Total UI for P1: 0, mck2ui 16
6852 00:24:45.889410 best dqsien dly found for B1: ( 0, 14, 24)
6853 00:24:45.892914 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6854 00:24:45.896940 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6855 00:24:45.897020
6856 00:24:45.899599 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6857 00:24:45.902939 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6858 00:24:45.906181 [Gating] SW calibration Done
6859 00:24:45.906260 ==
6860 00:24:45.909602 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 00:24:45.913206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 00:24:45.913287 ==
6863 00:24:45.916068 RX Vref Scan: 0
6864 00:24:45.916148
6865 00:24:45.916209 RX Vref 0 -> 0, step: 1
6866 00:24:45.919318
6867 00:24:45.919397 RX Delay -410 -> 252, step: 16
6868 00:24:45.925655 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6869 00:24:45.929086 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6870 00:24:45.932486 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6871 00:24:45.935712 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6872 00:24:45.942153 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6873 00:24:45.945652 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6874 00:24:45.948887 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6875 00:24:45.955072 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6876 00:24:45.959286 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6877 00:24:45.961727 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6878 00:24:45.964916 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6879 00:24:45.971806 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6880 00:24:45.975252 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6881 00:24:45.978109 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6882 00:24:45.981964 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6883 00:24:45.988289 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6884 00:24:45.988366 ==
6885 00:24:45.991988 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 00:24:45.994935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 00:24:45.995015 ==
6888 00:24:45.995096 DQS Delay:
6889 00:24:45.998521 DQS0 = 51, DQS1 = 51
6890 00:24:45.998602 DQM Delay:
6891 00:24:46.001225 DQM0 = 20, DQM1 = 15
6892 00:24:46.001303 DQ Delay:
6893 00:24:46.004939 DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16
6894 00:24:46.008813 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6895 00:24:46.011727 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6896 00:24:46.014936 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6897 00:24:46.015014
6898 00:24:46.015091
6899 00:24:46.015166 ==
6900 00:24:46.017972 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 00:24:46.020981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 00:24:46.025002 ==
6903 00:24:46.025101
6904 00:24:46.025183
6905 00:24:46.025267 TX Vref Scan disable
6906 00:24:46.027691 == TX Byte 0 ==
6907 00:24:46.031322 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6908 00:24:46.034885 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6909 00:24:46.037640 == TX Byte 1 ==
6910 00:24:46.041897 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6911 00:24:46.044588 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6912 00:24:46.044663 ==
6913 00:24:46.047432 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 00:24:46.054334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 00:24:46.054412 ==
6916 00:24:46.054516
6917 00:24:46.054648
6918 00:24:46.054724 TX Vref Scan disable
6919 00:24:46.057599 == TX Byte 0 ==
6920 00:24:46.060849 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6921 00:24:46.064021 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6922 00:24:46.067462 == TX Byte 1 ==
6923 00:24:46.070824 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6924 00:24:46.073657 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6925 00:24:46.073761
6926 00:24:46.077121 [DATLAT]
6927 00:24:46.077191 Freq=400, CH1 RK1
6928 00:24:46.077251
6929 00:24:46.080119 DATLAT Default: 0xe
6930 00:24:46.080190 0, 0xFFFF, sum = 0
6931 00:24:46.084196 1, 0xFFFF, sum = 0
6932 00:24:46.084265 2, 0xFFFF, sum = 0
6933 00:24:46.086753 3, 0xFFFF, sum = 0
6934 00:24:46.086853 4, 0xFFFF, sum = 0
6935 00:24:46.090534 5, 0xFFFF, sum = 0
6936 00:24:46.090637 6, 0xFFFF, sum = 0
6937 00:24:46.093567 7, 0xFFFF, sum = 0
6938 00:24:46.093639 8, 0xFFFF, sum = 0
6939 00:24:46.096780 9, 0xFFFF, sum = 0
6940 00:24:46.100043 10, 0xFFFF, sum = 0
6941 00:24:46.100114 11, 0xFFFF, sum = 0
6942 00:24:46.103552 12, 0xFFFF, sum = 0
6943 00:24:46.103621 13, 0x0, sum = 1
6944 00:24:46.106959 14, 0x0, sum = 2
6945 00:24:46.107026 15, 0x0, sum = 3
6946 00:24:46.107082 16, 0x0, sum = 4
6947 00:24:46.109969 best_step = 14
6948 00:24:46.110034
6949 00:24:46.110094 ==
6950 00:24:46.113497 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 00:24:46.116704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 00:24:46.116806 ==
6953 00:24:46.119852 RX Vref Scan: 0
6954 00:24:46.119927
6955 00:24:46.123167 RX Vref 0 -> 0, step: 1
6956 00:24:46.123235
6957 00:24:46.123293 RX Delay -343 -> 252, step: 8
6958 00:24:46.132272 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
6959 00:24:46.135162 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6960 00:24:46.138709 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
6961 00:24:46.145369 iDelay=225, Bit 3, Center -36 (-271 ~ 200) 472
6962 00:24:46.148279 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
6963 00:24:46.152040 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
6964 00:24:46.154908 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6965 00:24:46.161767 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6966 00:24:46.165226 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6967 00:24:46.168297 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6968 00:24:46.171484 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
6969 00:24:46.178459 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
6970 00:24:46.181392 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6971 00:24:46.184999 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6972 00:24:46.188313 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6973 00:24:46.194451 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
6974 00:24:46.194524 ==
6975 00:24:46.197876 Dram Type= 6, Freq= 0, CH_1, rank 1
6976 00:24:46.201945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6977 00:24:46.202012 ==
6978 00:24:46.202070 DQS Delay:
6979 00:24:46.204731 DQS0 = 48, DQS1 = 56
6980 00:24:46.204800 DQM Delay:
6981 00:24:46.208000 DQM0 = 12, DQM1 = 11
6982 00:24:46.208064 DQ Delay:
6983 00:24:46.210806 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6984 00:24:46.214395 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6985 00:24:46.217636 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6986 00:24:46.221239 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6987 00:24:46.221306
6988 00:24:46.221363
6989 00:24:46.230829 [DQSOSCAuto] RK1, (LSB)MR18= 0x7564, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
6990 00:24:46.230904 CH1 RK1: MR19=C0C, MR18=7564
6991 00:24:46.237274 CH1_RK1: MR19=0xC0C, MR18=0x7564, DQSOSC=395, MR23=63, INC=378, DEC=252
6992 00:24:46.240660 [RxdqsGatingPostProcess] freq 400
6993 00:24:46.247798 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6994 00:24:46.251069 best DQS0 dly(2T, 0.5T) = (0, 10)
6995 00:24:46.254023 best DQS1 dly(2T, 0.5T) = (0, 10)
6996 00:24:46.257215 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6997 00:24:46.260591 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6998 00:24:46.264038 best DQS0 dly(2T, 0.5T) = (0, 10)
6999 00:24:46.264108 best DQS1 dly(2T, 0.5T) = (0, 10)
7000 00:24:46.267964 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7001 00:24:46.270514 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7002 00:24:46.273795 Pre-setting of DQS Precalculation
7003 00:24:46.280207 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7004 00:24:46.287271 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7005 00:24:46.293643 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7006 00:24:46.293716
7007 00:24:46.293779
7008 00:24:46.296689 [Calibration Summary] 800 Mbps
7009 00:24:46.300206 CH 0, Rank 0
7010 00:24:46.300272 SW Impedance : PASS
7011 00:24:46.303379 DUTY Scan : NO K
7012 00:24:46.306826 ZQ Calibration : PASS
7013 00:24:46.306893 Jitter Meter : NO K
7014 00:24:46.310012 CBT Training : PASS
7015 00:24:46.313268 Write leveling : PASS
7016 00:24:46.313337 RX DQS gating : PASS
7017 00:24:46.316811 RX DQ/DQS(RDDQC) : PASS
7018 00:24:46.316876 TX DQ/DQS : PASS
7019 00:24:46.319792 RX DATLAT : PASS
7020 00:24:46.323213 RX DQ/DQS(Engine): PASS
7021 00:24:46.323278 TX OE : NO K
7022 00:24:46.326156 All Pass.
7023 00:24:46.326221
7024 00:24:46.326280 CH 0, Rank 1
7025 00:24:46.329692 SW Impedance : PASS
7026 00:24:46.329763 DUTY Scan : NO K
7027 00:24:46.333051 ZQ Calibration : PASS
7028 00:24:46.336261 Jitter Meter : NO K
7029 00:24:46.336332 CBT Training : PASS
7030 00:24:46.339629 Write leveling : NO K
7031 00:24:46.342896 RX DQS gating : PASS
7032 00:24:46.342967 RX DQ/DQS(RDDQC) : PASS
7033 00:24:46.346535 TX DQ/DQS : PASS
7034 00:24:46.349557 RX DATLAT : PASS
7035 00:24:46.349633 RX DQ/DQS(Engine): PASS
7036 00:24:46.352861 TX OE : NO K
7037 00:24:46.352929 All Pass.
7038 00:24:46.352986
7039 00:24:46.356017 CH 1, Rank 0
7040 00:24:46.356083 SW Impedance : PASS
7041 00:24:46.359578 DUTY Scan : NO K
7042 00:24:46.362890 ZQ Calibration : PASS
7043 00:24:46.362960 Jitter Meter : NO K
7044 00:24:46.365985 CBT Training : PASS
7045 00:24:46.369721 Write leveling : PASS
7046 00:24:46.369788 RX DQS gating : PASS
7047 00:24:46.372647 RX DQ/DQS(RDDQC) : PASS
7048 00:24:46.375812 TX DQ/DQS : PASS
7049 00:24:46.375890 RX DATLAT : PASS
7050 00:24:46.379343 RX DQ/DQS(Engine): PASS
7051 00:24:46.382419 TX OE : NO K
7052 00:24:46.382487 All Pass.
7053 00:24:46.382544
7054 00:24:46.382611 CH 1, Rank 1
7055 00:24:46.386499 SW Impedance : PASS
7056 00:24:46.389347 DUTY Scan : NO K
7057 00:24:46.389446 ZQ Calibration : PASS
7058 00:24:46.392640 Jitter Meter : NO K
7059 00:24:46.395981 CBT Training : PASS
7060 00:24:46.396047 Write leveling : NO K
7061 00:24:46.398890 RX DQS gating : PASS
7062 00:24:46.398957 RX DQ/DQS(RDDQC) : PASS
7063 00:24:46.402218 TX DQ/DQS : PASS
7064 00:24:46.405360 RX DATLAT : PASS
7065 00:24:46.405453 RX DQ/DQS(Engine): PASS
7066 00:24:46.408761 TX OE : NO K
7067 00:24:46.408829 All Pass.
7068 00:24:46.408886
7069 00:24:46.412037 DramC Write-DBI off
7070 00:24:46.415588 PER_BANK_REFRESH: Hybrid Mode
7071 00:24:46.415657 TX_TRACKING: ON
7072 00:24:46.425476 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7073 00:24:46.428567 [FAST_K] Save calibration result to emmc
7074 00:24:46.431754 dramc_set_vcore_voltage set vcore to 725000
7075 00:24:46.435879 Read voltage for 1600, 0
7076 00:24:46.435951 Vio18 = 0
7077 00:24:46.438703 Vcore = 725000
7078 00:24:46.438791 Vdram = 0
7079 00:24:46.438892 Vddq = 0
7080 00:24:46.438990 Vmddr = 0
7081 00:24:46.445399 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7082 00:24:46.451457 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7083 00:24:46.451536 MEM_TYPE=3, freq_sel=13
7084 00:24:46.455310 sv_algorithm_assistance_LP4_3733
7085 00:24:46.458776 ============ PULL DRAM RESETB DOWN ============
7086 00:24:46.465517 ========== PULL DRAM RESETB DOWN end =========
7087 00:24:46.468517 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7088 00:24:46.472278 ===================================
7089 00:24:46.474997 LPDDR4 DRAM CONFIGURATION
7090 00:24:46.478219 ===================================
7091 00:24:46.478300 EX_ROW_EN[0] = 0x0
7092 00:24:46.481524 EX_ROW_EN[1] = 0x0
7093 00:24:46.481601 LP4Y_EN = 0x0
7094 00:24:46.485263 WORK_FSP = 0x1
7095 00:24:46.488287 WL = 0x5
7096 00:24:46.488371 RL = 0x5
7097 00:24:46.491562 BL = 0x2
7098 00:24:46.491641 RPST = 0x0
7099 00:24:46.494853 RD_PRE = 0x0
7100 00:24:46.494929 WR_PRE = 0x1
7101 00:24:46.498137 WR_PST = 0x1
7102 00:24:46.498229 DBI_WR = 0x0
7103 00:24:46.501190 DBI_RD = 0x0
7104 00:24:46.501267 OTF = 0x1
7105 00:24:46.504679 ===================================
7106 00:24:46.507778 ===================================
7107 00:24:46.511295 ANA top config
7108 00:24:46.514805 ===================================
7109 00:24:46.514882 DLL_ASYNC_EN = 0
7110 00:24:46.517815 ALL_SLAVE_EN = 0
7111 00:24:46.521115 NEW_RANK_MODE = 1
7112 00:24:46.524253 DLL_IDLE_MODE = 1
7113 00:24:46.527968 LP45_APHY_COMB_EN = 1
7114 00:24:46.528049 TX_ODT_DIS = 0
7115 00:24:46.530925 NEW_8X_MODE = 1
7116 00:24:46.534346 ===================================
7117 00:24:46.537932 ===================================
7118 00:24:46.541164 data_rate = 3200
7119 00:24:46.544018 CKR = 1
7120 00:24:46.547804 DQ_P2S_RATIO = 8
7121 00:24:46.551433 ===================================
7122 00:24:46.551502 CA_P2S_RATIO = 8
7123 00:24:46.554728 DQ_CA_OPEN = 0
7124 00:24:46.557333 DQ_SEMI_OPEN = 0
7125 00:24:46.560940 CA_SEMI_OPEN = 0
7126 00:24:46.563679 CA_FULL_RATE = 0
7127 00:24:46.567195 DQ_CKDIV4_EN = 0
7128 00:24:46.570518 CA_CKDIV4_EN = 0
7129 00:24:46.570659 CA_PREDIV_EN = 0
7130 00:24:46.574093 PH8_DLY = 12
7131 00:24:46.577000 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7132 00:24:46.580479 DQ_AAMCK_DIV = 4
7133 00:24:46.583698 CA_AAMCK_DIV = 4
7134 00:24:46.587510 CA_ADMCK_DIV = 4
7135 00:24:46.587584 DQ_TRACK_CA_EN = 0
7136 00:24:46.590411 CA_PICK = 1600
7137 00:24:46.593444 CA_MCKIO = 1600
7138 00:24:46.596812 MCKIO_SEMI = 0
7139 00:24:46.600271 PLL_FREQ = 3068
7140 00:24:46.603497 DQ_UI_PI_RATIO = 32
7141 00:24:46.606610 CA_UI_PI_RATIO = 0
7142 00:24:46.610445 ===================================
7143 00:24:46.613225 ===================================
7144 00:24:46.613297 memory_type:LPDDR4
7145 00:24:46.616690 GP_NUM : 10
7146 00:24:46.619736 SRAM_EN : 1
7147 00:24:46.619812 MD32_EN : 0
7148 00:24:46.623053 ===================================
7149 00:24:46.626334 [ANA_INIT] >>>>>>>>>>>>>>
7150 00:24:46.630007 <<<<<< [CONFIGURE PHASE]: ANA_TX
7151 00:24:46.633343 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7152 00:24:46.636434 ===================================
7153 00:24:46.639498 data_rate = 3200,PCW = 0X7600
7154 00:24:46.642839 ===================================
7155 00:24:46.646734 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7156 00:24:46.649968 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7157 00:24:46.656663 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7158 00:24:46.659421 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7159 00:24:46.662812 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7160 00:24:46.669727 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7161 00:24:46.669807 [ANA_INIT] flow start
7162 00:24:46.672941 [ANA_INIT] PLL >>>>>>>>
7163 00:24:46.673011 [ANA_INIT] PLL <<<<<<<<
7164 00:24:46.676897 [ANA_INIT] MIDPI >>>>>>>>
7165 00:24:46.679639 [ANA_INIT] MIDPI <<<<<<<<
7166 00:24:46.682937 [ANA_INIT] DLL >>>>>>>>
7167 00:24:46.683006 [ANA_INIT] DLL <<<<<<<<
7168 00:24:46.686387 [ANA_INIT] flow end
7169 00:24:46.689336 ============ LP4 DIFF to SE enter ============
7170 00:24:46.692506 ============ LP4 DIFF to SE exit ============
7171 00:24:46.695896 [ANA_INIT] <<<<<<<<<<<<<
7172 00:24:46.698950 [Flow] Enable top DCM control >>>>>
7173 00:24:46.703267 [Flow] Enable top DCM control <<<<<
7174 00:24:46.706119 Enable DLL master slave shuffle
7175 00:24:46.712706 ==============================================================
7176 00:24:46.712777 Gating Mode config
7177 00:24:46.719222 ==============================================================
7178 00:24:46.719308 Config description:
7179 00:24:46.728751 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7180 00:24:46.735683 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7181 00:24:46.742394 SELPH_MODE 0: By rank 1: By Phase
7182 00:24:46.748740 ==============================================================
7183 00:24:46.748814 GAT_TRACK_EN = 1
7184 00:24:46.752019 RX_GATING_MODE = 2
7185 00:24:46.755050 RX_GATING_TRACK_MODE = 2
7186 00:24:46.758938 SELPH_MODE = 1
7187 00:24:46.761739 PICG_EARLY_EN = 1
7188 00:24:46.764964 VALID_LAT_VALUE = 1
7189 00:24:46.771736 ==============================================================
7190 00:24:46.774833 Enter into Gating configuration >>>>
7191 00:24:46.778664 Exit from Gating configuration <<<<
7192 00:24:46.782191 Enter into DVFS_PRE_config >>>>>
7193 00:24:46.791600 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7194 00:24:46.794973 Exit from DVFS_PRE_config <<<<<
7195 00:24:46.798205 Enter into PICG configuration >>>>
7196 00:24:46.801597 Exit from PICG configuration <<<<
7197 00:24:46.805074 [RX_INPUT] configuration >>>>>
7198 00:24:46.808825 [RX_INPUT] configuration <<<<<
7199 00:24:46.811423 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7200 00:24:46.818263 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7201 00:24:46.824775 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7202 00:24:46.827755 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7203 00:24:46.834327 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7204 00:24:46.841505 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7205 00:24:46.844288 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7206 00:24:46.851621 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7207 00:24:46.853969 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7208 00:24:46.857468 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7209 00:24:46.860653 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7210 00:24:46.867297 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7211 00:24:46.870495 ===================================
7212 00:24:46.874342 LPDDR4 DRAM CONFIGURATION
7213 00:24:46.877413 ===================================
7214 00:24:46.877493 EX_ROW_EN[0] = 0x0
7215 00:24:46.880510 EX_ROW_EN[1] = 0x0
7216 00:24:46.880579 LP4Y_EN = 0x0
7217 00:24:46.884161 WORK_FSP = 0x1
7218 00:24:46.884232 WL = 0x5
7219 00:24:46.887896 RL = 0x5
7220 00:24:46.887963 BL = 0x2
7221 00:24:46.890647 RPST = 0x0
7222 00:24:46.890742 RD_PRE = 0x0
7223 00:24:46.893560 WR_PRE = 0x1
7224 00:24:46.893626 WR_PST = 0x1
7225 00:24:46.896859 DBI_WR = 0x0
7226 00:24:46.896929 DBI_RD = 0x0
7227 00:24:46.900750 OTF = 0x1
7228 00:24:46.903897 ===================================
7229 00:24:46.907525 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7230 00:24:46.910199 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7231 00:24:46.916765 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7232 00:24:46.920405 ===================================
7233 00:24:46.920483 LPDDR4 DRAM CONFIGURATION
7234 00:24:46.923690 ===================================
7235 00:24:46.926686 EX_ROW_EN[0] = 0x10
7236 00:24:46.930034 EX_ROW_EN[1] = 0x0
7237 00:24:46.930128 LP4Y_EN = 0x0
7238 00:24:46.933550 WORK_FSP = 0x1
7239 00:24:46.933616 WL = 0x5
7240 00:24:46.936933 RL = 0x5
7241 00:24:46.937009 BL = 0x2
7242 00:24:46.939840 RPST = 0x0
7243 00:24:46.939932 RD_PRE = 0x0
7244 00:24:46.943507 WR_PRE = 0x1
7245 00:24:46.943577 WR_PST = 0x1
7246 00:24:46.946807 DBI_WR = 0x0
7247 00:24:46.946871 DBI_RD = 0x0
7248 00:24:46.950160 OTF = 0x1
7249 00:24:46.953185 ===================================
7250 00:24:46.959635 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7251 00:24:46.959704 ==
7252 00:24:46.963158 Dram Type= 6, Freq= 0, CH_0, rank 0
7253 00:24:46.966106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7254 00:24:46.966208 ==
7255 00:24:46.969790 [Duty_Offset_Calibration]
7256 00:24:46.969886 B0:1 B1:-1 CA:0
7257 00:24:46.973018
7258 00:24:46.976051 [DutyScan_Calibration_Flow] k_type=0
7259 00:24:46.984240
7260 00:24:46.984312 ==CLK 0==
7261 00:24:46.987543 Final CLK duty delay cell = 0
7262 00:24:46.990850 [0] MAX Duty = 5125%(X100), DQS PI = 22
7263 00:24:46.994877 [0] MIN Duty = 4875%(X100), DQS PI = 10
7264 00:24:46.997550 [0] AVG Duty = 5000%(X100)
7265 00:24:46.997617
7266 00:24:47.000870 CH0 CLK Duty spec in!! Max-Min= 250%
7267 00:24:47.004293 [DutyScan_Calibration_Flow] ====Done====
7268 00:24:47.004360
7269 00:24:47.007439 [DutyScan_Calibration_Flow] k_type=1
7270 00:24:47.023537
7271 00:24:47.023608 ==DQS 0 ==
7272 00:24:47.026597 Final DQS duty delay cell = -4
7273 00:24:47.030376 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7274 00:24:47.033827 [-4] MIN Duty = 4844%(X100), DQS PI = 58
7275 00:24:47.036470 [-4] AVG Duty = 4906%(X100)
7276 00:24:47.036544
7277 00:24:47.036608 ==DQS 1 ==
7278 00:24:47.040358 Final DQS duty delay cell = 0
7279 00:24:47.043547 [0] MAX Duty = 5156%(X100), DQS PI = 0
7280 00:24:47.046465 [0] MIN Duty = 5031%(X100), DQS PI = 20
7281 00:24:47.049881 [0] AVG Duty = 5093%(X100)
7282 00:24:47.049949
7283 00:24:47.053260 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7284 00:24:47.053326
7285 00:24:47.056600 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7286 00:24:47.059906 [DutyScan_Calibration_Flow] ====Done====
7287 00:24:47.059972
7288 00:24:47.062777 [DutyScan_Calibration_Flow] k_type=3
7289 00:24:47.080798
7290 00:24:47.080877 ==DQM 0 ==
7291 00:24:47.084120 Final DQM duty delay cell = 0
7292 00:24:47.087536 [0] MAX Duty = 5124%(X100), DQS PI = 22
7293 00:24:47.091422 [0] MIN Duty = 4907%(X100), DQS PI = 10
7294 00:24:47.094178 [0] AVG Duty = 5015%(X100)
7295 00:24:47.094250
7296 00:24:47.094309 ==DQM 1 ==
7297 00:24:47.097278 Final DQM duty delay cell = 0
7298 00:24:47.100844 [0] MAX Duty = 5031%(X100), DQS PI = 4
7299 00:24:47.104387 [0] MIN Duty = 4813%(X100), DQS PI = 20
7300 00:24:47.107452 [0] AVG Duty = 4922%(X100)
7301 00:24:47.107521
7302 00:24:47.110894 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7303 00:24:47.110968
7304 00:24:47.113710 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7305 00:24:47.117542 [DutyScan_Calibration_Flow] ====Done====
7306 00:24:47.117609
7307 00:24:47.120448 [DutyScan_Calibration_Flow] k_type=2
7308 00:24:47.138005
7309 00:24:47.138077 ==DQ 0 ==
7310 00:24:47.140945 Final DQ duty delay cell = -4
7311 00:24:47.144188 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7312 00:24:47.147536 [-4] MIN Duty = 4876%(X100), DQS PI = 56
7313 00:24:47.150764 [-4] AVG Duty = 4953%(X100)
7314 00:24:47.150836
7315 00:24:47.150896 ==DQ 1 ==
7316 00:24:47.153646 Final DQ duty delay cell = 0
7317 00:24:47.156923 [0] MAX Duty = 5125%(X100), DQS PI = 0
7318 00:24:47.160191 [0] MIN Duty = 5000%(X100), DQS PI = 38
7319 00:24:47.163426 [0] AVG Duty = 5062%(X100)
7320 00:24:47.163502
7321 00:24:47.166868 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7322 00:24:47.166945
7323 00:24:47.170492 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7324 00:24:47.173061 [DutyScan_Calibration_Flow] ====Done====
7325 00:24:47.173131 ==
7326 00:24:47.176784 Dram Type= 6, Freq= 0, CH_1, rank 0
7327 00:24:47.180323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7328 00:24:47.180431 ==
7329 00:24:47.183314 [Duty_Offset_Calibration]
7330 00:24:47.183381 B0:-1 B1:1 CA:2
7331 00:24:47.187104
7332 00:24:47.187173 [DutyScan_Calibration_Flow] k_type=0
7333 00:24:47.197639
7334 00:24:47.197707 ==CLK 0==
7335 00:24:47.201289 Final CLK duty delay cell = 0
7336 00:24:47.204275 [0] MAX Duty = 5187%(X100), DQS PI = 22
7337 00:24:47.208121 [0] MIN Duty = 4969%(X100), DQS PI = 0
7338 00:24:47.211432 [0] AVG Duty = 5078%(X100)
7339 00:24:47.211502
7340 00:24:47.214325 CH1 CLK Duty spec in!! Max-Min= 218%
7341 00:24:47.217505 [DutyScan_Calibration_Flow] ====Done====
7342 00:24:47.217596
7343 00:24:47.220574 [DutyScan_Calibration_Flow] k_type=1
7344 00:24:47.237463
7345 00:24:47.237539 ==DQS 0 ==
7346 00:24:47.240875 Final DQS duty delay cell = 0
7347 00:24:47.244694 [0] MAX Duty = 5156%(X100), DQS PI = 18
7348 00:24:47.247366 [0] MIN Duty = 4907%(X100), DQS PI = 10
7349 00:24:47.250651 [0] AVG Duty = 5031%(X100)
7350 00:24:47.250722
7351 00:24:47.250780 ==DQS 1 ==
7352 00:24:47.253861 Final DQS duty delay cell = 0
7353 00:24:47.256988 [0] MAX Duty = 5093%(X100), DQS PI = 24
7354 00:24:47.260471 [0] MIN Duty = 4969%(X100), DQS PI = 54
7355 00:24:47.263819 [0] AVG Duty = 5031%(X100)
7356 00:24:47.263895
7357 00:24:47.266998 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7358 00:24:47.267112
7359 00:24:47.270941 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7360 00:24:47.273451 [DutyScan_Calibration_Flow] ====Done====
7361 00:24:47.273520
7362 00:24:47.276894 [DutyScan_Calibration_Flow] k_type=3
7363 00:24:47.293628
7364 00:24:47.293709 ==DQM 0 ==
7365 00:24:47.296586 Final DQM duty delay cell = -4
7366 00:24:47.300032 [-4] MAX Duty = 5062%(X100), DQS PI = 18
7367 00:24:47.303429 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7368 00:24:47.306757 [-4] AVG Duty = 4937%(X100)
7369 00:24:47.306832
7370 00:24:47.306920 ==DQM 1 ==
7371 00:24:47.309805 Final DQM duty delay cell = 0
7372 00:24:47.313406 [0] MAX Duty = 5156%(X100), DQS PI = 2
7373 00:24:47.316384 [0] MIN Duty = 4969%(X100), DQS PI = 32
7374 00:24:47.319893 [0] AVG Duty = 5062%(X100)
7375 00:24:47.319967
7376 00:24:47.323415 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7377 00:24:47.323495
7378 00:24:47.326754 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7379 00:24:47.329645 [DutyScan_Calibration_Flow] ====Done====
7380 00:24:47.329748
7381 00:24:47.332844 [DutyScan_Calibration_Flow] k_type=2
7382 00:24:47.350979
7383 00:24:47.351062 ==DQ 0 ==
7384 00:24:47.353754 Final DQ duty delay cell = 0
7385 00:24:47.357702 [0] MAX Duty = 5187%(X100), DQS PI = 32
7386 00:24:47.360695 [0] MIN Duty = 4906%(X100), DQS PI = 10
7387 00:24:47.360777 [0] AVG Duty = 5046%(X100)
7388 00:24:47.363690
7389 00:24:47.363765 ==DQ 1 ==
7390 00:24:47.367519 Final DQ duty delay cell = 0
7391 00:24:47.371140 [0] MAX Duty = 5156%(X100), DQS PI = 8
7392 00:24:47.373945 [0] MIN Duty = 4969%(X100), DQS PI = 56
7393 00:24:47.374022 [0] AVG Duty = 5062%(X100)
7394 00:24:47.374107
7395 00:24:47.380615 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7396 00:24:47.380692
7397 00:24:47.383770 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7398 00:24:47.387227 [DutyScan_Calibration_Flow] ====Done====
7399 00:24:47.390341 nWR fixed to 30
7400 00:24:47.390416 [ModeRegInit_LP4] CH0 RK0
7401 00:24:47.394675 [ModeRegInit_LP4] CH0 RK1
7402 00:24:47.397588 [ModeRegInit_LP4] CH1 RK0
7403 00:24:47.400577 [ModeRegInit_LP4] CH1 RK1
7404 00:24:47.400650 match AC timing 5
7405 00:24:47.403681 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7406 00:24:47.410423 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7407 00:24:47.413363 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7408 00:24:47.420376 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7409 00:24:47.423859 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7410 00:24:47.423938 [MiockJmeterHQA]
7411 00:24:47.423999
7412 00:24:47.426717 [DramcMiockJmeter] u1RxGatingPI = 0
7413 00:24:47.430488 0 : 4364, 4137
7414 00:24:47.430568 4 : 4253, 4027
7415 00:24:47.433283 8 : 4252, 4026
7416 00:24:47.433363 12 : 4365, 4140
7417 00:24:47.433426 16 : 4253, 4027
7418 00:24:47.436572 20 : 4253, 4027
7419 00:24:47.436651 24 : 4253, 4027
7420 00:24:47.440150 28 : 4252, 4027
7421 00:24:47.440229 32 : 4365, 4140
7422 00:24:47.443468 36 : 4363, 4138
7423 00:24:47.443549 40 : 4255, 4029
7424 00:24:47.447154 44 : 4254, 4029
7425 00:24:47.447234 48 : 4363, 4137
7426 00:24:47.447296 52 : 4253, 4027
7427 00:24:47.450155 56 : 4363, 4140
7428 00:24:47.450234 60 : 4255, 4029
7429 00:24:47.453233 64 : 4250, 4026
7430 00:24:47.453313 68 : 4250, 4026
7431 00:24:47.456780 72 : 4250, 4026
7432 00:24:47.456860 76 : 4361, 4138
7433 00:24:47.460216 80 : 4250, 4027
7434 00:24:47.460295 84 : 4361, 4137
7435 00:24:47.460358 88 : 4363, 4139
7436 00:24:47.463295 92 : 4252, 595
7437 00:24:47.463375 96 : 4363, 0
7438 00:24:47.466400 100 : 4250, 0
7439 00:24:47.466479 104 : 4252, 0
7440 00:24:47.466542 108 : 4250, 0
7441 00:24:47.469805 112 : 4250, 0
7442 00:24:47.469895 116 : 4253, 0
7443 00:24:47.473022 120 : 4360, 0
7444 00:24:47.473097 124 : 4360, 0
7445 00:24:47.473185 128 : 4250, 0
7446 00:24:47.476139 132 : 4255, 0
7447 00:24:47.476214 136 : 4361, 0
7448 00:24:47.479787 140 : 4250, 0
7449 00:24:47.479862 144 : 4253, 0
7450 00:24:47.479943 148 : 4250, 0
7451 00:24:47.483242 152 : 4250, 0
7452 00:24:47.483317 156 : 4252, 0
7453 00:24:47.483397 160 : 4250, 0
7454 00:24:47.486074 164 : 4250, 0
7455 00:24:47.486147 168 : 4253, 0
7456 00:24:47.489684 172 : 4360, 0
7457 00:24:47.489768 176 : 4360, 0
7458 00:24:47.489850 180 : 4250, 0
7459 00:24:47.493473 184 : 4255, 0
7460 00:24:47.493558 188 : 4361, 0
7461 00:24:47.496142 192 : 4249, 0
7462 00:24:47.496216 196 : 4255, 0
7463 00:24:47.496296 200 : 4250, 0
7464 00:24:47.499512 204 : 4250, 0
7465 00:24:47.499594 208 : 4253, 0
7466 00:24:47.503109 212 : 4250, 0
7467 00:24:47.503185 216 : 4250, 0
7468 00:24:47.503265 220 : 4252, 0
7469 00:24:47.506293 224 : 4360, 322
7470 00:24:47.506370 228 : 4250, 3357
7471 00:24:47.509774 232 : 4361, 4137
7472 00:24:47.509848 236 : 4250, 4027
7473 00:24:47.512797 240 : 4250, 4026
7474 00:24:47.512869 244 : 4250, 4027
7475 00:24:47.516031 248 : 4250, 4027
7476 00:24:47.516106 252 : 4250, 4026
7477 00:24:47.516186 256 : 4360, 4137
7478 00:24:47.519338 260 : 4250, 4027
7479 00:24:47.519414 264 : 4361, 4137
7480 00:24:47.523132 268 : 4361, 4138
7481 00:24:47.523207 272 : 4361, 4138
7482 00:24:47.526093 276 : 4250, 4027
7483 00:24:47.526166 280 : 4363, 4140
7484 00:24:47.529366 284 : 4250, 4026
7485 00:24:47.529442 288 : 4250, 4026
7486 00:24:47.532959 292 : 4252, 4029
7487 00:24:47.533043 296 : 4252, 4030
7488 00:24:47.535868 300 : 4253, 4029
7489 00:24:47.535949 304 : 4361, 4137
7490 00:24:47.539414 308 : 4255, 4029
7491 00:24:47.539492 312 : 4250, 4027
7492 00:24:47.542876 316 : 4254, 4030
7493 00:24:47.542953 320 : 4363, 4140
7494 00:24:47.543042 324 : 4363, 4137
7495 00:24:47.545853 328 : 4250, 4027
7496 00:24:47.545926 332 : 4363, 4140
7497 00:24:47.549000 336 : 4250, 3816
7498 00:24:47.549076 340 : 4250, 1705
7499 00:24:47.549162
7500 00:24:47.552479 MIOCK jitter meter ch=0
7501 00:24:47.552552
7502 00:24:47.556291 1T = (340-92) = 248 dly cells
7503 00:24:47.562134 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7504 00:24:47.562236 ==
7505 00:24:47.566407 Dram Type= 6, Freq= 0, CH_0, rank 0
7506 00:24:47.568689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7507 00:24:47.568768 ==
7508 00:24:47.575298 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7509 00:24:47.578733 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7510 00:24:47.581996 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7511 00:24:47.588524 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7512 00:24:47.598510 [CA 0] Center 43 (13~74) winsize 62
7513 00:24:47.601377 [CA 1] Center 43 (13~74) winsize 62
7514 00:24:47.604723 [CA 2] Center 39 (10~68) winsize 59
7515 00:24:47.608215 [CA 3] Center 38 (8~68) winsize 61
7516 00:24:47.610931 [CA 4] Center 37 (8~66) winsize 59
7517 00:24:47.614176 [CA 5] Center 36 (7~66) winsize 60
7518 00:24:47.614251
7519 00:24:47.617805 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7520 00:24:47.617881
7521 00:24:47.621176 [CATrainingPosCal] consider 1 rank data
7522 00:24:47.624428 u2DelayCellTimex100 = 262/100 ps
7523 00:24:47.631063 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7524 00:24:47.634688 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7525 00:24:47.637324 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7526 00:24:47.640882 CA3 delay=38 (8~68),Diff = 2 PI (7 cell)
7527 00:24:47.644193 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7528 00:24:47.647235 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7529 00:24:47.647311
7530 00:24:47.650535 CA PerBit enable=1, Macro0, CA PI delay=36
7531 00:24:47.650673
7532 00:24:47.653925 [CBTSetCACLKResult] CA Dly = 36
7533 00:24:47.657606 CS Dly: 12 (0~43)
7534 00:24:47.660363 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7535 00:24:47.664497 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7536 00:24:47.664579 ==
7537 00:24:47.667512 Dram Type= 6, Freq= 0, CH_0, rank 1
7538 00:24:47.673678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 00:24:47.673753 ==
7540 00:24:47.677141 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7541 00:24:47.683738 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7542 00:24:47.686671 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7543 00:24:47.693358 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7544 00:24:47.701325 [CA 0] Center 42 (12~73) winsize 62
7545 00:24:47.704505 [CA 1] Center 43 (13~73) winsize 61
7546 00:24:47.707911 [CA 2] Center 37 (8~67) winsize 60
7547 00:24:47.711083 [CA 3] Center 37 (7~67) winsize 61
7548 00:24:47.714491 [CA 4] Center 35 (6~65) winsize 60
7549 00:24:47.717688 [CA 5] Center 35 (5~65) winsize 61
7550 00:24:47.717763
7551 00:24:47.720679 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7552 00:24:47.720752
7553 00:24:47.727535 [CATrainingPosCal] consider 2 rank data
7554 00:24:47.727619 u2DelayCellTimex100 = 262/100 ps
7555 00:24:47.734091 CA0 delay=43 (13~73),Diff = 7 PI (26 cell)
7556 00:24:47.738052 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7557 00:24:47.740727 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7558 00:24:47.744079 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
7559 00:24:47.747421 CA4 delay=36 (8~65),Diff = 0 PI (0 cell)
7560 00:24:47.750740 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7561 00:24:47.750816
7562 00:24:47.753716 CA PerBit enable=1, Macro0, CA PI delay=36
7563 00:24:47.753794
7564 00:24:47.757314 [CBTSetCACLKResult] CA Dly = 36
7565 00:24:47.760173 CS Dly: 12 (0~43)
7566 00:24:47.763751 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7567 00:24:47.767286 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7568 00:24:47.767367
7569 00:24:47.770576 ----->DramcWriteLeveling(PI) begin...
7570 00:24:47.773862 ==
7571 00:24:47.777106 Dram Type= 6, Freq= 0, CH_0, rank 0
7572 00:24:47.780188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 00:24:47.780269 ==
7574 00:24:47.783644 Write leveling (Byte 0): 36 => 36
7575 00:24:47.787367 Write leveling (Byte 1): 26 => 26
7576 00:24:47.789803 DramcWriteLeveling(PI) end<-----
7577 00:24:47.789881
7578 00:24:47.789957 ==
7579 00:24:47.793678 Dram Type= 6, Freq= 0, CH_0, rank 0
7580 00:24:47.796492 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7581 00:24:47.796574 ==
7582 00:24:47.800098 [Gating] SW mode calibration
7583 00:24:47.806448 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7584 00:24:47.813025 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7585 00:24:47.816816 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 00:24:47.819712 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 00:24:47.826408 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 00:24:47.829987 1 4 12 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7589 00:24:47.832807 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7590 00:24:47.839534 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (1 1) (1 1)
7591 00:24:47.843124 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7592 00:24:47.846148 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 00:24:47.852739 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 00:24:47.855995 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 00:24:47.859348 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 00:24:47.866236 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
7597 00:24:47.869384 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7598 00:24:47.872583 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
7599 00:24:47.879059 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7600 00:24:47.882840 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 00:24:47.885601 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 00:24:47.892547 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 00:24:47.895790 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7604 00:24:47.899033 1 6 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
7605 00:24:47.902256 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7606 00:24:47.909013 1 6 20 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7607 00:24:47.912372 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 00:24:47.915906 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 00:24:47.922522 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 00:24:47.925644 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 00:24:47.928935 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 00:24:47.935337 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7613 00:24:47.938695 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7614 00:24:47.941786 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7615 00:24:47.948665 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 00:24:47.951754 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 00:24:47.954957 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 00:24:47.962062 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 00:24:47.965091 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 00:24:47.971662 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 00:24:47.975350 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 00:24:47.978225 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 00:24:47.981543 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 00:24:47.988805 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 00:24:47.991737 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 00:24:47.994852 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 00:24:48.001346 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7628 00:24:48.004749 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7629 00:24:48.007730 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7630 00:24:48.014289 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7631 00:24:48.017655 Total UI for P1: 0, mck2ui 16
7632 00:24:48.021146 best dqsien dly found for B0: ( 1, 9, 12)
7633 00:24:48.024336 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7634 00:24:48.027585 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 00:24:48.031128 Total UI for P1: 0, mck2ui 16
7636 00:24:48.033955 best dqsien dly found for B1: ( 1, 9, 22)
7637 00:24:48.041511 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7638 00:24:48.044387 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7639 00:24:48.044467
7640 00:24:48.047443 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7641 00:24:48.050447 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7642 00:24:48.053837 [Gating] SW calibration Done
7643 00:24:48.053916 ==
7644 00:24:48.057158 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 00:24:48.060696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 00:24:48.060776 ==
7647 00:24:48.063789 RX Vref Scan: 0
7648 00:24:48.063867
7649 00:24:48.063929 RX Vref 0 -> 0, step: 1
7650 00:24:48.063986
7651 00:24:48.067449 RX Delay 0 -> 252, step: 8
7652 00:24:48.070511 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7653 00:24:48.076895 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7654 00:24:48.080175 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7655 00:24:48.083693 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7656 00:24:48.087452 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7657 00:24:48.090186 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7658 00:24:48.096627 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7659 00:24:48.099970 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7660 00:24:48.103369 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7661 00:24:48.106692 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7662 00:24:48.109891 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7663 00:24:48.116548 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7664 00:24:48.119788 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7665 00:24:48.123495 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7666 00:24:48.126195 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7667 00:24:48.132987 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7668 00:24:48.133063 ==
7669 00:24:48.136474 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 00:24:48.140075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 00:24:48.140158 ==
7672 00:24:48.140220 DQS Delay:
7673 00:24:48.142837 DQS0 = 0, DQS1 = 0
7674 00:24:48.142933 DQM Delay:
7675 00:24:48.146863 DQM0 = 136, DQM1 = 127
7676 00:24:48.146935 DQ Delay:
7677 00:24:48.149894 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7678 00:24:48.153411 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =147
7679 00:24:48.156268 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7680 00:24:48.159480 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7681 00:24:48.159553
7682 00:24:48.159613
7683 00:24:48.162532 ==
7684 00:24:48.165883 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 00:24:48.169152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 00:24:48.169227 ==
7687 00:24:48.169295
7688 00:24:48.169352
7689 00:24:48.172729 TX Vref Scan disable
7690 00:24:48.172809 == TX Byte 0 ==
7691 00:24:48.179255 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7692 00:24:48.182468 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7693 00:24:48.182542 == TX Byte 1 ==
7694 00:24:48.189317 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7695 00:24:48.192378 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7696 00:24:48.192462 ==
7697 00:24:48.195539 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 00:24:48.198724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 00:24:48.198821 ==
7700 00:24:48.213288
7701 00:24:48.216460 TX Vref early break, caculate TX vref
7702 00:24:48.220257 TX Vref=16, minBit 4, minWin=22, winSum=368
7703 00:24:48.223119 TX Vref=18, minBit 1, minWin=23, winSum=378
7704 00:24:48.226275 TX Vref=20, minBit 6, minWin=23, winSum=385
7705 00:24:48.230220 TX Vref=22, minBit 2, minWin=24, winSum=398
7706 00:24:48.232949 TX Vref=24, minBit 1, minWin=24, winSum=409
7707 00:24:48.239927 TX Vref=26, minBit 0, minWin=25, winSum=412
7708 00:24:48.243021 TX Vref=28, minBit 4, minWin=25, winSum=416
7709 00:24:48.246406 TX Vref=30, minBit 0, minWin=24, winSum=403
7710 00:24:48.249619 TX Vref=32, minBit 0, minWin=24, winSum=396
7711 00:24:48.252942 TX Vref=34, minBit 4, minWin=23, winSum=386
7712 00:24:48.259813 [TxChooseVref] Worse bit 4, Min win 25, Win sum 416, Final Vref 28
7713 00:24:48.259918
7714 00:24:48.263053 Final TX Range 0 Vref 28
7715 00:24:48.263152
7716 00:24:48.263242 ==
7717 00:24:48.266037 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 00:24:48.269844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 00:24:48.269915 ==
7720 00:24:48.269983
7721 00:24:48.270039
7722 00:24:48.272907 TX Vref Scan disable
7723 00:24:48.279967 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7724 00:24:48.280048 == TX Byte 0 ==
7725 00:24:48.282789 u2DelayCellOfst[0]=14 cells (4 PI)
7726 00:24:48.286410 u2DelayCellOfst[1]=18 cells (5 PI)
7727 00:24:48.289241 u2DelayCellOfst[2]=14 cells (4 PI)
7728 00:24:48.292405 u2DelayCellOfst[3]=14 cells (4 PI)
7729 00:24:48.295564 u2DelayCellOfst[4]=11 cells (3 PI)
7730 00:24:48.298909 u2DelayCellOfst[5]=0 cells (0 PI)
7731 00:24:48.302260 u2DelayCellOfst[6]=18 cells (5 PI)
7732 00:24:48.305582 u2DelayCellOfst[7]=22 cells (6 PI)
7733 00:24:48.309020 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7734 00:24:48.312810 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7735 00:24:48.316106 == TX Byte 1 ==
7736 00:24:48.318776 u2DelayCellOfst[8]=0 cells (0 PI)
7737 00:24:48.322100 u2DelayCellOfst[9]=3 cells (1 PI)
7738 00:24:48.325561 u2DelayCellOfst[10]=7 cells (2 PI)
7739 00:24:48.325633 u2DelayCellOfst[11]=3 cells (1 PI)
7740 00:24:48.328880 u2DelayCellOfst[12]=14 cells (4 PI)
7741 00:24:48.331897 u2DelayCellOfst[13]=14 cells (4 PI)
7742 00:24:48.335105 u2DelayCellOfst[14]=14 cells (4 PI)
7743 00:24:48.338773 u2DelayCellOfst[15]=11 cells (3 PI)
7744 00:24:48.344871 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7745 00:24:48.348383 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7746 00:24:48.351591 DramC Write-DBI on
7747 00:24:48.351669 ==
7748 00:24:48.355006 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 00:24:48.358154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 00:24:48.358234 ==
7751 00:24:48.358295
7752 00:24:48.358352
7753 00:24:48.361773 TX Vref Scan disable
7754 00:24:48.361851 == TX Byte 0 ==
7755 00:24:48.368275 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7756 00:24:48.368357 == TX Byte 1 ==
7757 00:24:48.371648 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7758 00:24:48.374721 DramC Write-DBI off
7759 00:24:48.374800
7760 00:24:48.374861 [DATLAT]
7761 00:24:48.377952 Freq=1600, CH0 RK0
7762 00:24:48.378031
7763 00:24:48.378093 DATLAT Default: 0xf
7764 00:24:48.381173 0, 0xFFFF, sum = 0
7765 00:24:48.381254 1, 0xFFFF, sum = 0
7766 00:24:48.384545 2, 0xFFFF, sum = 0
7767 00:24:48.387948 3, 0xFFFF, sum = 0
7768 00:24:48.388029 4, 0xFFFF, sum = 0
7769 00:24:48.391034 5, 0xFFFF, sum = 0
7770 00:24:48.391145 6, 0xFFFF, sum = 0
7771 00:24:48.394440 7, 0xFFFF, sum = 0
7772 00:24:48.394520 8, 0xFFFF, sum = 0
7773 00:24:48.398056 9, 0xFFFF, sum = 0
7774 00:24:48.398139 10, 0xFFFF, sum = 0
7775 00:24:48.401140 11, 0xFFFF, sum = 0
7776 00:24:48.401221 12, 0xFFFF, sum = 0
7777 00:24:48.404415 13, 0xFFFF, sum = 0
7778 00:24:48.404495 14, 0x0, sum = 1
7779 00:24:48.407412 15, 0x0, sum = 2
7780 00:24:48.407493 16, 0x0, sum = 3
7781 00:24:48.410957 17, 0x0, sum = 4
7782 00:24:48.411038 best_step = 15
7783 00:24:48.411100
7784 00:24:48.411157 ==
7785 00:24:48.414373 Dram Type= 6, Freq= 0, CH_0, rank 0
7786 00:24:48.420712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7787 00:24:48.420791 ==
7788 00:24:48.420853 RX Vref Scan: 1
7789 00:24:48.420911
7790 00:24:48.424243 Set Vref Range= 24 -> 127
7791 00:24:48.424322
7792 00:24:48.427303 RX Vref 24 -> 127, step: 1
7793 00:24:48.427382
7794 00:24:48.427444 RX Delay 19 -> 252, step: 4
7795 00:24:48.430488
7796 00:24:48.430567 Set Vref, RX VrefLevel [Byte0]: 24
7797 00:24:48.433901 [Byte1]: 24
7798 00:24:48.438099
7799 00:24:48.438178 Set Vref, RX VrefLevel [Byte0]: 25
7800 00:24:48.441475 [Byte1]: 25
7801 00:24:48.446088
7802 00:24:48.446167 Set Vref, RX VrefLevel [Byte0]: 26
7803 00:24:48.448923 [Byte1]: 26
7804 00:24:48.453256
7805 00:24:48.453335 Set Vref, RX VrefLevel [Byte0]: 27
7806 00:24:48.456556 [Byte1]: 27
7807 00:24:48.460829
7808 00:24:48.460908 Set Vref, RX VrefLevel [Byte0]: 28
7809 00:24:48.464070 [Byte1]: 28
7810 00:24:48.469166
7811 00:24:48.469262 Set Vref, RX VrefLevel [Byte0]: 29
7812 00:24:48.471781 [Byte1]: 29
7813 00:24:48.476546
7814 00:24:48.476624 Set Vref, RX VrefLevel [Byte0]: 30
7815 00:24:48.479298 [Byte1]: 30
7816 00:24:48.483687
7817 00:24:48.483765 Set Vref, RX VrefLevel [Byte0]: 31
7818 00:24:48.486750 [Byte1]: 31
7819 00:24:48.491273
7820 00:24:48.491351 Set Vref, RX VrefLevel [Byte0]: 32
7821 00:24:48.494387 [Byte1]: 32
7822 00:24:48.498602
7823 00:24:48.498680 Set Vref, RX VrefLevel [Byte0]: 33
7824 00:24:48.501790 [Byte1]: 33
7825 00:24:48.506201
7826 00:24:48.506279 Set Vref, RX VrefLevel [Byte0]: 34
7827 00:24:48.509286 [Byte1]: 34
7828 00:24:48.513685
7829 00:24:48.513763 Set Vref, RX VrefLevel [Byte0]: 35
7830 00:24:48.517484 [Byte1]: 35
7831 00:24:48.521650
7832 00:24:48.521732 Set Vref, RX VrefLevel [Byte0]: 36
7833 00:24:48.524510 [Byte1]: 36
7834 00:24:48.528999
7835 00:24:48.529078 Set Vref, RX VrefLevel [Byte0]: 37
7836 00:24:48.532288 [Byte1]: 37
7837 00:24:48.537003
7838 00:24:48.537082 Set Vref, RX VrefLevel [Byte0]: 38
7839 00:24:48.539835 [Byte1]: 38
7840 00:24:48.544004
7841 00:24:48.544106 Set Vref, RX VrefLevel [Byte0]: 39
7842 00:24:48.547633 [Byte1]: 39
7843 00:24:48.551753
7844 00:24:48.551832 Set Vref, RX VrefLevel [Byte0]: 40
7845 00:24:48.555150 [Byte1]: 40
7846 00:24:48.559690
7847 00:24:48.559769 Set Vref, RX VrefLevel [Byte0]: 41
7848 00:24:48.562379 [Byte1]: 41
7849 00:24:48.566719
7850 00:24:48.566814 Set Vref, RX VrefLevel [Byte0]: 42
7851 00:24:48.570657 [Byte1]: 42
7852 00:24:48.574347
7853 00:24:48.574426 Set Vref, RX VrefLevel [Byte0]: 43
7854 00:24:48.578064 [Byte1]: 43
7855 00:24:48.582044
7856 00:24:48.582123 Set Vref, RX VrefLevel [Byte0]: 44
7857 00:24:48.585358 [Byte1]: 44
7858 00:24:48.590040
7859 00:24:48.590119 Set Vref, RX VrefLevel [Byte0]: 45
7860 00:24:48.592790 [Byte1]: 45
7861 00:24:48.597077
7862 00:24:48.597156 Set Vref, RX VrefLevel [Byte0]: 46
7863 00:24:48.600219 [Byte1]: 46
7864 00:24:48.605156
7865 00:24:48.605235 Set Vref, RX VrefLevel [Byte0]: 47
7866 00:24:48.608300 [Byte1]: 47
7867 00:24:48.612474
7868 00:24:48.612570 Set Vref, RX VrefLevel [Byte0]: 48
7869 00:24:48.615626 [Byte1]: 48
7870 00:24:48.619846
7871 00:24:48.619925 Set Vref, RX VrefLevel [Byte0]: 49
7872 00:24:48.623072 [Byte1]: 49
7873 00:24:48.627330
7874 00:24:48.627409 Set Vref, RX VrefLevel [Byte0]: 50
7875 00:24:48.631139 [Byte1]: 50
7876 00:24:48.634911
7877 00:24:48.638255 Set Vref, RX VrefLevel [Byte0]: 51
7878 00:24:48.641883 [Byte1]: 51
7879 00:24:48.641983
7880 00:24:48.644647 Set Vref, RX VrefLevel [Byte0]: 52
7881 00:24:48.647928 [Byte1]: 52
7882 00:24:48.648008
7883 00:24:48.651448 Set Vref, RX VrefLevel [Byte0]: 53
7884 00:24:48.654573 [Byte1]: 53
7885 00:24:48.654692
7886 00:24:48.657693 Set Vref, RX VrefLevel [Byte0]: 54
7887 00:24:48.661050 [Byte1]: 54
7888 00:24:48.665158
7889 00:24:48.665236 Set Vref, RX VrefLevel [Byte0]: 55
7890 00:24:48.671769 [Byte1]: 55
7891 00:24:48.671848
7892 00:24:48.675100 Set Vref, RX VrefLevel [Byte0]: 56
7893 00:24:48.678025 [Byte1]: 56
7894 00:24:48.678105
7895 00:24:48.681575 Set Vref, RX VrefLevel [Byte0]: 57
7896 00:24:48.684828 [Byte1]: 57
7897 00:24:48.688253
7898 00:24:48.688332 Set Vref, RX VrefLevel [Byte0]: 58
7899 00:24:48.691539 [Byte1]: 58
7900 00:24:48.695847
7901 00:24:48.695930 Set Vref, RX VrefLevel [Byte0]: 59
7902 00:24:48.698617 [Byte1]: 59
7903 00:24:48.703676
7904 00:24:48.703756 Set Vref, RX VrefLevel [Byte0]: 60
7905 00:24:48.706495 [Byte1]: 60
7906 00:24:48.711003
7907 00:24:48.711083 Set Vref, RX VrefLevel [Byte0]: 61
7908 00:24:48.713883 [Byte1]: 61
7909 00:24:48.718384
7910 00:24:48.718463 Set Vref, RX VrefLevel [Byte0]: 62
7911 00:24:48.721809 [Byte1]: 62
7912 00:24:48.725750
7913 00:24:48.725829 Set Vref, RX VrefLevel [Byte0]: 63
7914 00:24:48.728954 [Byte1]: 63
7915 00:24:48.734100
7916 00:24:48.734179 Set Vref, RX VrefLevel [Byte0]: 64
7917 00:24:48.736741 [Byte1]: 64
7918 00:24:48.741267
7919 00:24:48.741347 Set Vref, RX VrefLevel [Byte0]: 65
7920 00:24:48.744153 [Byte1]: 65
7921 00:24:48.748812
7922 00:24:48.748891 Set Vref, RX VrefLevel [Byte0]: 66
7923 00:24:48.751771 [Byte1]: 66
7924 00:24:48.756210
7925 00:24:48.756289 Set Vref, RX VrefLevel [Byte0]: 67
7926 00:24:48.759222 [Byte1]: 67
7927 00:24:48.763509
7928 00:24:48.763589 Set Vref, RX VrefLevel [Byte0]: 68
7929 00:24:48.766865 [Byte1]: 68
7930 00:24:48.771157
7931 00:24:48.771236 Set Vref, RX VrefLevel [Byte0]: 69
7932 00:24:48.774557 [Byte1]: 69
7933 00:24:48.778907
7934 00:24:48.778986 Set Vref, RX VrefLevel [Byte0]: 70
7935 00:24:48.782307 [Byte1]: 70
7936 00:24:48.786629
7937 00:24:48.786708 Set Vref, RX VrefLevel [Byte0]: 71
7938 00:24:48.789439 [Byte1]: 71
7939 00:24:48.794439
7940 00:24:48.794518 Set Vref, RX VrefLevel [Byte0]: 72
7941 00:24:48.797279 [Byte1]: 72
7942 00:24:48.801971
7943 00:24:48.802051 Set Vref, RX VrefLevel [Byte0]: 73
7944 00:24:48.804878 [Byte1]: 73
7945 00:24:48.809067
7946 00:24:48.809146 Set Vref, RX VrefLevel [Byte0]: 74
7947 00:24:48.812734 [Byte1]: 74
7948 00:24:48.816956
7949 00:24:48.817036 Set Vref, RX VrefLevel [Byte0]: 75
7950 00:24:48.820734 [Byte1]: 75
7951 00:24:48.824577
7952 00:24:48.824656 Set Vref, RX VrefLevel [Byte0]: 76
7953 00:24:48.827476 [Byte1]: 76
7954 00:24:48.832144
7955 00:24:48.832223 Set Vref, RX VrefLevel [Byte0]: 77
7956 00:24:48.835253 [Byte1]: 77
7957 00:24:48.839584
7958 00:24:48.839662 Set Vref, RX VrefLevel [Byte0]: 78
7959 00:24:48.842539 [Byte1]: 78
7960 00:24:48.847388
7961 00:24:48.847467 Set Vref, RX VrefLevel [Byte0]: 79
7962 00:24:48.850638 [Byte1]: 79
7963 00:24:48.854912
7964 00:24:48.854993 Set Vref, RX VrefLevel [Byte0]: 80
7965 00:24:48.857665 [Byte1]: 80
7966 00:24:48.862267
7967 00:24:48.862346 Final RX Vref Byte 0 = 66 to rank0
7968 00:24:48.865489 Final RX Vref Byte 1 = 57 to rank0
7969 00:24:48.869207 Final RX Vref Byte 0 = 66 to rank1
7970 00:24:48.872231 Final RX Vref Byte 1 = 57 to rank1==
7971 00:24:48.875113 Dram Type= 6, Freq= 0, CH_0, rank 0
7972 00:24:48.881733 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7973 00:24:48.881813 ==
7974 00:24:48.881876 DQS Delay:
7975 00:24:48.885067 DQS0 = 0, DQS1 = 0
7976 00:24:48.885146 DQM Delay:
7977 00:24:48.885208 DQM0 = 133, DQM1 = 124
7978 00:24:48.888765 DQ Delay:
7979 00:24:48.892024 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
7980 00:24:48.895179 DQ4 =136, DQ5 =122, DQ6 =140, DQ7 =142
7981 00:24:48.899091 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =118
7982 00:24:48.901646 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =130
7983 00:24:48.901736
7984 00:24:48.901798
7985 00:24:48.901856
7986 00:24:48.905362 [DramC_TX_OE_Calibration] TA2
7987 00:24:48.908610 Original DQ_B0 (3 6) =30, OEN = 27
7988 00:24:48.911659 Original DQ_B1 (3 6) =30, OEN = 27
7989 00:24:48.914945 24, 0x0, End_B0=24 End_B1=24
7990 00:24:48.915025 25, 0x0, End_B0=25 End_B1=25
7991 00:24:48.918761 26, 0x0, End_B0=26 End_B1=26
7992 00:24:48.921433 27, 0x0, End_B0=27 End_B1=27
7993 00:24:48.925411 28, 0x0, End_B0=28 End_B1=28
7994 00:24:48.927990 29, 0x0, End_B0=29 End_B1=29
7995 00:24:48.928070 30, 0x0, End_B0=30 End_B1=30
7996 00:24:48.931476 31, 0x5151, End_B0=30 End_B1=30
7997 00:24:48.934864 Byte0 end_step=30 best_step=27
7998 00:24:48.938314 Byte1 end_step=30 best_step=27
7999 00:24:48.941091 Byte0 TX OE(2T, 0.5T) = (3, 3)
8000 00:24:48.944523 Byte1 TX OE(2T, 0.5T) = (3, 3)
8001 00:24:48.944602
8002 00:24:48.944663
8003 00:24:48.951273 [DQSOSCAuto] RK0, (LSB)MR18= 0x2516, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
8004 00:24:48.954202 CH0 RK0: MR19=303, MR18=2516
8005 00:24:48.961009 CH0_RK0: MR19=0x303, MR18=0x2516, DQSOSC=391, MR23=63, INC=24, DEC=16
8006 00:24:48.961097
8007 00:24:48.964497 ----->DramcWriteLeveling(PI) begin...
8008 00:24:48.964577 ==
8009 00:24:48.967993 Dram Type= 6, Freq= 0, CH_0, rank 1
8010 00:24:48.970580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8011 00:24:48.970698 ==
8012 00:24:48.974092 Write leveling (Byte 0): 36 => 36
8013 00:24:48.977189 Write leveling (Byte 1): 28 => 28
8014 00:24:48.980681 DramcWriteLeveling(PI) end<-----
8015 00:24:48.980761
8016 00:24:48.980822 ==
8017 00:24:48.983863 Dram Type= 6, Freq= 0, CH_0, rank 1
8018 00:24:48.990796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8019 00:24:48.990879 ==
8020 00:24:48.990940 [Gating] SW mode calibration
8021 00:24:49.000924 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8022 00:24:49.003717 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8023 00:24:49.007063 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 00:24:49.013739 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 00:24:49.016998 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 00:24:49.020228 1 4 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8027 00:24:49.027329 1 4 16 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
8028 00:24:49.029994 1 4 20 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
8029 00:24:49.036585 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8030 00:24:49.040617 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8031 00:24:49.043480 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8032 00:24:49.049749 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8033 00:24:49.053206 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8034 00:24:49.056431 1 5 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
8035 00:24:49.060081 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
8036 00:24:49.066330 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
8037 00:24:49.069326 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 00:24:49.072745 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 00:24:49.079570 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 00:24:49.082932 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 00:24:49.086213 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 00:24:49.092852 1 6 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8043 00:24:49.095924 1 6 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
8044 00:24:49.099649 1 6 20 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
8045 00:24:49.105811 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 00:24:49.109123 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 00:24:49.112310 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 00:24:49.119829 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8049 00:24:49.122838 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8050 00:24:49.125769 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8051 00:24:49.133026 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8052 00:24:49.135472 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8053 00:24:49.139047 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 00:24:49.145696 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 00:24:49.149319 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 00:24:49.152311 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 00:24:49.158791 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 00:24:49.162006 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 00:24:49.166181 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 00:24:49.172534 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 00:24:49.175450 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 00:24:49.178887 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 00:24:49.185500 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 00:24:49.188648 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 00:24:49.192225 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8066 00:24:49.198633 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8067 00:24:49.198713 Total UI for P1: 0, mck2ui 16
8068 00:24:49.205775 best dqsien dly found for B0: ( 1, 9, 8)
8069 00:24:49.209039 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8070 00:24:49.212145 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 00:24:49.215520 Total UI for P1: 0, mck2ui 16
8072 00:24:49.218832 best dqsien dly found for B1: ( 1, 9, 14)
8073 00:24:49.222226 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8074 00:24:49.225031 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8075 00:24:49.225112
8076 00:24:49.231663 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8077 00:24:49.235042 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8078 00:24:49.238825 [Gating] SW calibration Done
8079 00:24:49.238905 ==
8080 00:24:49.241969 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 00:24:49.244797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 00:24:49.244878 ==
8083 00:24:49.244940 RX Vref Scan: 0
8084 00:24:49.244999
8085 00:24:49.247822 RX Vref 0 -> 0, step: 1
8086 00:24:49.247902
8087 00:24:49.251193 RX Delay 0 -> 252, step: 8
8088 00:24:49.254634 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8089 00:24:49.257878 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8090 00:24:49.264943 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8091 00:24:49.267862 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8092 00:24:49.270967 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8093 00:24:49.274494 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8094 00:24:49.278157 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8095 00:24:49.284414 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8096 00:24:49.287713 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8097 00:24:49.291009 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8098 00:24:49.295190 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8099 00:24:49.297534 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8100 00:24:49.304143 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8101 00:24:49.307416 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8102 00:24:49.311138 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8103 00:24:49.314111 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8104 00:24:49.314190 ==
8105 00:24:49.317469 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 00:24:49.324239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 00:24:49.324326 ==
8108 00:24:49.324389 DQS Delay:
8109 00:24:49.327304 DQS0 = 0, DQS1 = 0
8110 00:24:49.327384 DQM Delay:
8111 00:24:49.327447 DQM0 = 133, DQM1 = 128
8112 00:24:49.331093 DQ Delay:
8113 00:24:49.334028 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8114 00:24:49.337135 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8115 00:24:49.340955 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =127
8116 00:24:49.343934 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8117 00:24:49.344052
8118 00:24:49.344118
8119 00:24:49.344176 ==
8120 00:24:49.347189 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 00:24:49.354259 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 00:24:49.354339 ==
8123 00:24:49.354401
8124 00:24:49.354458
8125 00:24:49.354514 TX Vref Scan disable
8126 00:24:49.357279 == TX Byte 0 ==
8127 00:24:49.360850 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8128 00:24:49.367674 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8129 00:24:49.367754 == TX Byte 1 ==
8130 00:24:49.370333 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8131 00:24:49.377003 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8132 00:24:49.377083 ==
8133 00:24:49.379850 Dram Type= 6, Freq= 0, CH_0, rank 1
8134 00:24:49.383647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8135 00:24:49.383745 ==
8136 00:24:49.396734
8137 00:24:49.400255 TX Vref early break, caculate TX vref
8138 00:24:49.403486 TX Vref=16, minBit 0, minWin=23, winSum=383
8139 00:24:49.406744 TX Vref=18, minBit 0, minWin=23, winSum=389
8140 00:24:49.410208 TX Vref=20, minBit 0, minWin=24, winSum=395
8141 00:24:49.413395 TX Vref=22, minBit 1, minWin=24, winSum=403
8142 00:24:49.416406 TX Vref=24, minBit 3, minWin=24, winSum=415
8143 00:24:49.423470 TX Vref=26, minBit 1, minWin=24, winSum=413
8144 00:24:49.426803 TX Vref=28, minBit 0, minWin=24, winSum=413
8145 00:24:49.429694 TX Vref=30, minBit 0, minWin=24, winSum=403
8146 00:24:49.433450 TX Vref=32, minBit 1, minWin=23, winSum=394
8147 00:24:49.436483 TX Vref=34, minBit 1, minWin=22, winSum=387
8148 00:24:49.442971 [TxChooseVref] Worse bit 3, Min win 24, Win sum 415, Final Vref 24
8149 00:24:49.443050
8150 00:24:49.446842 Final TX Range 0 Vref 24
8151 00:24:49.446921
8152 00:24:49.446983 ==
8153 00:24:49.450001 Dram Type= 6, Freq= 0, CH_0, rank 1
8154 00:24:49.452882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8155 00:24:49.452962 ==
8156 00:24:49.453024
8157 00:24:49.453082
8158 00:24:49.456590 TX Vref Scan disable
8159 00:24:49.463021 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8160 00:24:49.463100 == TX Byte 0 ==
8161 00:24:49.466588 u2DelayCellOfst[0]=11 cells (3 PI)
8162 00:24:49.469479 u2DelayCellOfst[1]=14 cells (4 PI)
8163 00:24:49.472980 u2DelayCellOfst[2]=11 cells (3 PI)
8164 00:24:49.476360 u2DelayCellOfst[3]=11 cells (3 PI)
8165 00:24:49.479727 u2DelayCellOfst[4]=7 cells (2 PI)
8166 00:24:49.482921 u2DelayCellOfst[5]=0 cells (0 PI)
8167 00:24:49.486344 u2DelayCellOfst[6]=14 cells (4 PI)
8168 00:24:49.489704 u2DelayCellOfst[7]=14 cells (4 PI)
8169 00:24:49.492612 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8170 00:24:49.497060 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8171 00:24:49.499010 == TX Byte 1 ==
8172 00:24:49.502633 u2DelayCellOfst[8]=0 cells (0 PI)
8173 00:24:49.502712 u2DelayCellOfst[9]=0 cells (0 PI)
8174 00:24:49.505912 u2DelayCellOfst[10]=7 cells (2 PI)
8175 00:24:49.509487 u2DelayCellOfst[11]=3 cells (1 PI)
8176 00:24:49.512492 u2DelayCellOfst[12]=11 cells (3 PI)
8177 00:24:49.515930 u2DelayCellOfst[13]=11 cells (3 PI)
8178 00:24:49.519276 u2DelayCellOfst[14]=14 cells (4 PI)
8179 00:24:49.522118 u2DelayCellOfst[15]=11 cells (3 PI)
8180 00:24:49.528638 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8181 00:24:49.531863 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8182 00:24:49.531942 DramC Write-DBI on
8183 00:24:49.532003 ==
8184 00:24:49.535395 Dram Type= 6, Freq= 0, CH_0, rank 1
8185 00:24:49.542104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8186 00:24:49.542183 ==
8187 00:24:49.542246
8188 00:24:49.542304
8189 00:24:49.542359 TX Vref Scan disable
8190 00:24:49.546273 == TX Byte 0 ==
8191 00:24:49.549826 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8192 00:24:49.552856 == TX Byte 1 ==
8193 00:24:49.556062 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8194 00:24:49.559384 DramC Write-DBI off
8195 00:24:49.559463
8196 00:24:49.559524 [DATLAT]
8197 00:24:49.559581 Freq=1600, CH0 RK1
8198 00:24:49.559637
8199 00:24:49.562792 DATLAT Default: 0xf
8200 00:24:49.565723 0, 0xFFFF, sum = 0
8201 00:24:49.565803 1, 0xFFFF, sum = 0
8202 00:24:49.569513 2, 0xFFFF, sum = 0
8203 00:24:49.569593 3, 0xFFFF, sum = 0
8204 00:24:49.573041 4, 0xFFFF, sum = 0
8205 00:24:49.573121 5, 0xFFFF, sum = 0
8206 00:24:49.575969 6, 0xFFFF, sum = 0
8207 00:24:49.576049 7, 0xFFFF, sum = 0
8208 00:24:49.579511 8, 0xFFFF, sum = 0
8209 00:24:49.579591 9, 0xFFFF, sum = 0
8210 00:24:49.583046 10, 0xFFFF, sum = 0
8211 00:24:49.583126 11, 0xFFFF, sum = 0
8212 00:24:49.585714 12, 0xFFFF, sum = 0
8213 00:24:49.585794 13, 0xFFFF, sum = 0
8214 00:24:49.588863 14, 0x0, sum = 1
8215 00:24:49.588943 15, 0x0, sum = 2
8216 00:24:49.592085 16, 0x0, sum = 3
8217 00:24:49.592173 17, 0x0, sum = 4
8218 00:24:49.595765 best_step = 15
8219 00:24:49.595844
8220 00:24:49.595906 ==
8221 00:24:49.599040 Dram Type= 6, Freq= 0, CH_0, rank 1
8222 00:24:49.602157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8223 00:24:49.602237 ==
8224 00:24:49.605400 RX Vref Scan: 0
8225 00:24:49.605479
8226 00:24:49.605569 RX Vref 0 -> 0, step: 1
8227 00:24:49.605630
8228 00:24:49.608720 RX Delay 11 -> 252, step: 4
8229 00:24:49.615280 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8230 00:24:49.618994 iDelay=195, Bit 1, Center 136 (83 ~ 190) 108
8231 00:24:49.621860 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8232 00:24:49.625145 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8233 00:24:49.628116 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8234 00:24:49.635221 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8235 00:24:49.638235 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8236 00:24:49.641369 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8237 00:24:49.645271 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8238 00:24:49.648050 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8239 00:24:49.654809 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8240 00:24:49.658091 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8241 00:24:49.661077 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8242 00:24:49.664828 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8243 00:24:49.671166 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8244 00:24:49.674238 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8245 00:24:49.674319 ==
8246 00:24:49.678305 Dram Type= 6, Freq= 0, CH_0, rank 1
8247 00:24:49.681732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8248 00:24:49.681813 ==
8249 00:24:49.684591 DQS Delay:
8250 00:24:49.684674 DQS0 = 0, DQS1 = 0
8251 00:24:49.684736 DQM Delay:
8252 00:24:49.687916 DQM0 = 130, DQM1 = 125
8253 00:24:49.687995 DQ Delay:
8254 00:24:49.690817 DQ0 =128, DQ1 =136, DQ2 =126, DQ3 =126
8255 00:24:49.697452 DQ4 =130, DQ5 =120, DQ6 =140, DQ7 =140
8256 00:24:49.700697 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8257 00:24:49.703890 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8258 00:24:49.703969
8259 00:24:49.704031
8260 00:24:49.704089
8261 00:24:49.707343 [DramC_TX_OE_Calibration] TA2
8262 00:24:49.710822 Original DQ_B0 (3 6) =30, OEN = 27
8263 00:24:49.714039 Original DQ_B1 (3 6) =30, OEN = 27
8264 00:24:49.714119 24, 0x0, End_B0=24 End_B1=24
8265 00:24:49.717404 25, 0x0, End_B0=25 End_B1=25
8266 00:24:49.720516 26, 0x0, End_B0=26 End_B1=26
8267 00:24:49.723713 27, 0x0, End_B0=27 End_B1=27
8268 00:24:49.727176 28, 0x0, End_B0=28 End_B1=28
8269 00:24:49.727257 29, 0x0, End_B0=29 End_B1=29
8270 00:24:49.730690 30, 0x0, End_B0=30 End_B1=30
8271 00:24:49.733500 31, 0x4545, End_B0=30 End_B1=30
8272 00:24:49.736873 Byte0 end_step=30 best_step=27
8273 00:24:49.740537 Byte1 end_step=30 best_step=27
8274 00:24:49.743395 Byte0 TX OE(2T, 0.5T) = (3, 3)
8275 00:24:49.743475 Byte1 TX OE(2T, 0.5T) = (3, 3)
8276 00:24:49.743538
8277 00:24:49.743595
8278 00:24:49.753236 [DQSOSCAuto] RK1, (LSB)MR18= 0x2306, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
8279 00:24:49.756647 CH0 RK1: MR19=303, MR18=2306
8280 00:24:49.763525 CH0_RK1: MR19=0x303, MR18=0x2306, DQSOSC=392, MR23=63, INC=24, DEC=16
8281 00:24:49.766415 [RxdqsGatingPostProcess] freq 1600
8282 00:24:49.770272 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8283 00:24:49.773094 best DQS0 dly(2T, 0.5T) = (1, 1)
8284 00:24:49.776439 best DQS1 dly(2T, 0.5T) = (1, 1)
8285 00:24:49.779688 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8286 00:24:49.783643 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8287 00:24:49.786439 best DQS0 dly(2T, 0.5T) = (1, 1)
8288 00:24:49.789381 best DQS1 dly(2T, 0.5T) = (1, 1)
8289 00:24:49.793278 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8290 00:24:49.796272 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8291 00:24:49.799647 Pre-setting of DQS Precalculation
8292 00:24:49.802851 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8293 00:24:49.802930 ==
8294 00:24:49.806514 Dram Type= 6, Freq= 0, CH_1, rank 0
8295 00:24:49.809591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8296 00:24:49.809671 ==
8297 00:24:49.816159 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8298 00:24:49.819689 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8299 00:24:49.825678 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8300 00:24:49.829125 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8301 00:24:49.839708 [CA 0] Center 42 (13~72) winsize 60
8302 00:24:49.842809 [CA 1] Center 42 (13~72) winsize 60
8303 00:24:49.846008 [CA 2] Center 38 (9~67) winsize 59
8304 00:24:49.849679 [CA 3] Center 36 (7~66) winsize 60
8305 00:24:49.852548 [CA 4] Center 37 (8~67) winsize 60
8306 00:24:49.855898 [CA 5] Center 37 (8~67) winsize 60
8307 00:24:49.855974
8308 00:24:49.859347 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8309 00:24:49.859419
8310 00:24:49.865674 [CATrainingPosCal] consider 1 rank data
8311 00:24:49.865754 u2DelayCellTimex100 = 262/100 ps
8312 00:24:49.872237 CA0 delay=42 (13~72),Diff = 6 PI (22 cell)
8313 00:24:49.875601 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8314 00:24:49.878927 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8315 00:24:49.882029 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8316 00:24:49.885527 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8317 00:24:49.888843 CA5 delay=37 (8~67),Diff = 1 PI (3 cell)
8318 00:24:49.888922
8319 00:24:49.892261 CA PerBit enable=1, Macro0, CA PI delay=36
8320 00:24:49.892340
8321 00:24:49.895686 [CBTSetCACLKResult] CA Dly = 36
8322 00:24:49.898843 CS Dly: 9 (0~40)
8323 00:24:49.902261 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8324 00:24:49.905600 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8325 00:24:49.905680 ==
8326 00:24:49.908515 Dram Type= 6, Freq= 0, CH_1, rank 1
8327 00:24:49.915010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8328 00:24:49.915090 ==
8329 00:24:49.918524 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8330 00:24:49.925202 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8331 00:24:49.928462 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8332 00:24:49.935021 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8333 00:24:49.942472 [CA 0] Center 43 (14~72) winsize 59
8334 00:24:49.945753 [CA 1] Center 42 (13~72) winsize 60
8335 00:24:49.949497 [CA 2] Center 38 (9~67) winsize 59
8336 00:24:49.952397 [CA 3] Center 37 (8~67) winsize 60
8337 00:24:49.956064 [CA 4] Center 38 (9~67) winsize 59
8338 00:24:49.959325 [CA 5] Center 37 (8~66) winsize 59
8339 00:24:49.959400
8340 00:24:49.962421 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8341 00:24:49.962535
8342 00:24:49.969184 [CATrainingPosCal] consider 2 rank data
8343 00:24:49.969263 u2DelayCellTimex100 = 262/100 ps
8344 00:24:49.975407 CA0 delay=43 (14~72),Diff = 6 PI (22 cell)
8345 00:24:49.978913 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8346 00:24:49.982499 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8347 00:24:49.985294 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8348 00:24:49.988859 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8349 00:24:49.991723 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8350 00:24:49.991803
8351 00:24:49.995241 CA PerBit enable=1, Macro0, CA PI delay=37
8352 00:24:49.995320
8353 00:24:49.999089 [CBTSetCACLKResult] CA Dly = 37
8354 00:24:50.002485 CS Dly: 10 (0~43)
8355 00:24:50.004943 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8356 00:24:50.008399 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8357 00:24:50.008479
8358 00:24:50.011899 ----->DramcWriteLeveling(PI) begin...
8359 00:24:50.011980 ==
8360 00:24:50.014777 Dram Type= 6, Freq= 0, CH_1, rank 0
8361 00:24:50.021236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8362 00:24:50.021316 ==
8363 00:24:50.024410 Write leveling (Byte 0): 24 => 24
8364 00:24:50.027865 Write leveling (Byte 1): 26 => 26
8365 00:24:50.031214 DramcWriteLeveling(PI) end<-----
8366 00:24:50.031294
8367 00:24:50.031356 ==
8368 00:24:50.034396 Dram Type= 6, Freq= 0, CH_1, rank 0
8369 00:24:50.037605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 00:24:50.037686 ==
8371 00:24:50.041206 [Gating] SW mode calibration
8372 00:24:50.047970 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8373 00:24:50.054182 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8374 00:24:50.057858 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 00:24:50.060793 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 00:24:50.067851 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 00:24:50.071062 1 4 12 | B1->B0 | 3433 3434 | 1 1 | (0 0) (1 1)
8378 00:24:50.074181 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 00:24:50.080918 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 00:24:50.083988 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 00:24:50.087323 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 00:24:50.093782 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 00:24:50.097310 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 00:24:50.100442 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8385 00:24:50.107252 1 5 12 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
8386 00:24:50.110598 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8387 00:24:50.113882 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 00:24:50.120315 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 00:24:50.123439 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 00:24:50.127557 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 00:24:50.130375 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 00:24:50.137237 1 6 8 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8393 00:24:50.140871 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8394 00:24:50.146739 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 00:24:50.149844 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 00:24:50.153286 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 00:24:50.160472 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 00:24:50.163854 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 00:24:50.166536 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 00:24:50.172786 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8401 00:24:50.176219 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8402 00:24:50.179879 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8403 00:24:50.186274 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 00:24:50.189718 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 00:24:50.192954 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 00:24:50.199161 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 00:24:50.202398 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 00:24:50.206167 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 00:24:50.212510 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 00:24:50.215531 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 00:24:50.219908 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 00:24:50.225615 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 00:24:50.229115 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 00:24:50.231962 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 00:24:50.238715 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 00:24:50.242215 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8417 00:24:50.245623 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8418 00:24:50.252090 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 00:24:50.252171 Total UI for P1: 0, mck2ui 16
8420 00:24:50.258567 best dqsien dly found for B0: ( 1, 9, 10)
8421 00:24:50.258687 Total UI for P1: 0, mck2ui 16
8422 00:24:50.262019 best dqsien dly found for B1: ( 1, 9, 12)
8423 00:24:50.268953 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8424 00:24:50.271645 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8425 00:24:50.271727
8426 00:24:50.275180 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8427 00:24:50.278585 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8428 00:24:50.281794 [Gating] SW calibration Done
8429 00:24:50.281875 ==
8430 00:24:50.285221 Dram Type= 6, Freq= 0, CH_1, rank 0
8431 00:24:50.288238 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8432 00:24:50.288331 ==
8433 00:24:50.291813 RX Vref Scan: 0
8434 00:24:50.291892
8435 00:24:50.291954 RX Vref 0 -> 0, step: 1
8436 00:24:50.292013
8437 00:24:50.295155 RX Delay 0 -> 252, step: 8
8438 00:24:50.298858 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8439 00:24:50.305280 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8440 00:24:50.308637 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8441 00:24:50.311543 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8442 00:24:50.314707 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8443 00:24:50.319070 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8444 00:24:50.324780 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8445 00:24:50.328299 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8446 00:24:50.331993 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8447 00:24:50.334963 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8448 00:24:50.337828 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8449 00:24:50.344834 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8450 00:24:50.348471 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8451 00:24:50.351786 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8452 00:24:50.354289 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8453 00:24:50.361178 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8454 00:24:50.361258 ==
8455 00:24:50.364531 Dram Type= 6, Freq= 0, CH_1, rank 0
8456 00:24:50.367840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8457 00:24:50.367920 ==
8458 00:24:50.367983 DQS Delay:
8459 00:24:50.370938 DQS0 = 0, DQS1 = 0
8460 00:24:50.371018 DQM Delay:
8461 00:24:50.374804 DQM0 = 138, DQM1 = 130
8462 00:24:50.374885 DQ Delay:
8463 00:24:50.377918 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8464 00:24:50.380954 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8465 00:24:50.384144 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8466 00:24:50.387828 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8467 00:24:50.387907
8468 00:24:50.387969
8469 00:24:50.391160 ==
8470 00:24:50.391240 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 00:24:50.397582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 00:24:50.397669 ==
8473 00:24:50.397734
8474 00:24:50.397793
8475 00:24:50.401076 TX Vref Scan disable
8476 00:24:50.401144 == TX Byte 0 ==
8477 00:24:50.404170 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8478 00:24:50.411306 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8479 00:24:50.411381 == TX Byte 1 ==
8480 00:24:50.414317 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8481 00:24:50.420568 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8482 00:24:50.420645 ==
8483 00:24:50.424004 Dram Type= 6, Freq= 0, CH_1, rank 0
8484 00:24:50.427245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8485 00:24:50.427313 ==
8486 00:24:50.440131
8487 00:24:50.443309 TX Vref early break, caculate TX vref
8488 00:24:50.447010 TX Vref=16, minBit 0, minWin=22, winSum=376
8489 00:24:50.450260 TX Vref=18, minBit 0, minWin=22, winSum=385
8490 00:24:50.453251 TX Vref=20, minBit 0, minWin=23, winSum=393
8491 00:24:50.456576 TX Vref=22, minBit 5, minWin=23, winSum=402
8492 00:24:50.459884 TX Vref=24, minBit 0, minWin=24, winSum=416
8493 00:24:50.467221 TX Vref=26, minBit 0, minWin=25, winSum=419
8494 00:24:50.469945 TX Vref=28, minBit 0, minWin=25, winSum=421
8495 00:24:50.473035 TX Vref=30, minBit 1, minWin=24, winSum=410
8496 00:24:50.476438 TX Vref=32, minBit 1, minWin=24, winSum=405
8497 00:24:50.479563 TX Vref=34, minBit 5, minWin=23, winSum=394
8498 00:24:50.486470 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 28
8499 00:24:50.486540
8500 00:24:50.489980 Final TX Range 0 Vref 28
8501 00:24:50.490052
8502 00:24:50.490119 ==
8503 00:24:50.493210 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 00:24:50.496156 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 00:24:50.496225 ==
8506 00:24:50.496283
8507 00:24:50.496345
8508 00:24:50.499559 TX Vref Scan disable
8509 00:24:50.506465 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8510 00:24:50.506536 == TX Byte 0 ==
8511 00:24:50.509484 u2DelayCellOfst[0]=18 cells (5 PI)
8512 00:24:50.512880 u2DelayCellOfst[1]=11 cells (3 PI)
8513 00:24:50.516465 u2DelayCellOfst[2]=0 cells (0 PI)
8514 00:24:50.519591 u2DelayCellOfst[3]=3 cells (1 PI)
8515 00:24:50.523195 u2DelayCellOfst[4]=7 cells (2 PI)
8516 00:24:50.526076 u2DelayCellOfst[5]=18 cells (5 PI)
8517 00:24:50.529861 u2DelayCellOfst[6]=18 cells (5 PI)
8518 00:24:50.532682 u2DelayCellOfst[7]=7 cells (2 PI)
8519 00:24:50.535857 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8520 00:24:50.539518 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8521 00:24:50.542269 == TX Byte 1 ==
8522 00:24:50.545726 u2DelayCellOfst[8]=0 cells (0 PI)
8523 00:24:50.545835 u2DelayCellOfst[9]=3 cells (1 PI)
8524 00:24:50.549230 u2DelayCellOfst[10]=11 cells (3 PI)
8525 00:24:50.552310 u2DelayCellOfst[11]=7 cells (2 PI)
8526 00:24:50.556118 u2DelayCellOfst[12]=14 cells (4 PI)
8527 00:24:50.559147 u2DelayCellOfst[13]=18 cells (5 PI)
8528 00:24:50.562038 u2DelayCellOfst[14]=18 cells (5 PI)
8529 00:24:50.565759 u2DelayCellOfst[15]=18 cells (5 PI)
8530 00:24:50.571970 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8531 00:24:50.575485 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8532 00:24:50.575565 DramC Write-DBI on
8533 00:24:50.575627 ==
8534 00:24:50.578932 Dram Type= 6, Freq= 0, CH_1, rank 0
8535 00:24:50.585393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8536 00:24:50.585474 ==
8537 00:24:50.585536
8538 00:24:50.585594
8539 00:24:50.585649 TX Vref Scan disable
8540 00:24:50.590038 == TX Byte 0 ==
8541 00:24:50.592721 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8542 00:24:50.595940 == TX Byte 1 ==
8543 00:24:50.599203 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8544 00:24:50.602572 DramC Write-DBI off
8545 00:24:50.602674
8546 00:24:50.602736 [DATLAT]
8547 00:24:50.602795 Freq=1600, CH1 RK0
8548 00:24:50.602851
8549 00:24:50.606083 DATLAT Default: 0xf
8550 00:24:50.606162 0, 0xFFFF, sum = 0
8551 00:24:50.609039 1, 0xFFFF, sum = 0
8552 00:24:50.612479 2, 0xFFFF, sum = 0
8553 00:24:50.612559 3, 0xFFFF, sum = 0
8554 00:24:50.615533 4, 0xFFFF, sum = 0
8555 00:24:50.615614 5, 0xFFFF, sum = 0
8556 00:24:50.618821 6, 0xFFFF, sum = 0
8557 00:24:50.618902 7, 0xFFFF, sum = 0
8558 00:24:50.622096 8, 0xFFFF, sum = 0
8559 00:24:50.622176 9, 0xFFFF, sum = 0
8560 00:24:50.625406 10, 0xFFFF, sum = 0
8561 00:24:50.625487 11, 0xFFFF, sum = 0
8562 00:24:50.628992 12, 0xFFFF, sum = 0
8563 00:24:50.629074 13, 0xFFFF, sum = 0
8564 00:24:50.631817 14, 0x0, sum = 1
8565 00:24:50.631898 15, 0x0, sum = 2
8566 00:24:50.635250 16, 0x0, sum = 3
8567 00:24:50.635330 17, 0x0, sum = 4
8568 00:24:50.638448 best_step = 15
8569 00:24:50.638527
8570 00:24:50.638589 ==
8571 00:24:50.642018 Dram Type= 6, Freq= 0, CH_1, rank 0
8572 00:24:50.645131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8573 00:24:50.645211 ==
8574 00:24:50.648275 RX Vref Scan: 1
8575 00:24:50.648356
8576 00:24:50.648418 Set Vref Range= 24 -> 127
8577 00:24:50.652342
8578 00:24:50.652422 RX Vref 24 -> 127, step: 1
8579 00:24:50.652484
8580 00:24:50.655078 RX Delay 19 -> 252, step: 4
8581 00:24:50.655158
8582 00:24:50.658469 Set Vref, RX VrefLevel [Byte0]: 24
8583 00:24:50.661505 [Byte1]: 24
8584 00:24:50.661585
8585 00:24:50.665011 Set Vref, RX VrefLevel [Byte0]: 25
8586 00:24:50.668277 [Byte1]: 25
8587 00:24:50.671800
8588 00:24:50.671879 Set Vref, RX VrefLevel [Byte0]: 26
8589 00:24:50.675544 [Byte1]: 26
8590 00:24:50.679777
8591 00:24:50.679856 Set Vref, RX VrefLevel [Byte0]: 27
8592 00:24:50.683152 [Byte1]: 27
8593 00:24:50.688103
8594 00:24:50.688183 Set Vref, RX VrefLevel [Byte0]: 28
8595 00:24:50.690429 [Byte1]: 28
8596 00:24:50.695198
8597 00:24:50.695277 Set Vref, RX VrefLevel [Byte0]: 29
8598 00:24:50.697846 [Byte1]: 29
8599 00:24:50.702497
8600 00:24:50.702577 Set Vref, RX VrefLevel [Byte0]: 30
8601 00:24:50.705665 [Byte1]: 30
8602 00:24:50.710097
8603 00:24:50.710176 Set Vref, RX VrefLevel [Byte0]: 31
8604 00:24:50.713039 [Byte1]: 31
8605 00:24:50.717682
8606 00:24:50.717765 Set Vref, RX VrefLevel [Byte0]: 32
8607 00:24:50.720626 [Byte1]: 32
8608 00:24:50.725451
8609 00:24:50.725531 Set Vref, RX VrefLevel [Byte0]: 33
8610 00:24:50.728303 [Byte1]: 33
8611 00:24:50.732849
8612 00:24:50.732928 Set Vref, RX VrefLevel [Byte0]: 34
8613 00:24:50.737169 [Byte1]: 34
8614 00:24:50.740152
8615 00:24:50.740231 Set Vref, RX VrefLevel [Byte0]: 35
8616 00:24:50.743849 [Byte1]: 35
8617 00:24:50.747950
8618 00:24:50.750804 Set Vref, RX VrefLevel [Byte0]: 36
8619 00:24:50.754390 [Byte1]: 36
8620 00:24:50.754460
8621 00:24:50.757502 Set Vref, RX VrefLevel [Byte0]: 37
8622 00:24:50.760610 [Byte1]: 37
8623 00:24:50.760682
8624 00:24:50.764060 Set Vref, RX VrefLevel [Byte0]: 38
8625 00:24:50.767721 [Byte1]: 38
8626 00:24:50.767799
8627 00:24:50.770612 Set Vref, RX VrefLevel [Byte0]: 39
8628 00:24:50.774194 [Byte1]: 39
8629 00:24:50.778425
8630 00:24:50.778493 Set Vref, RX VrefLevel [Byte0]: 40
8631 00:24:50.781239 [Byte1]: 40
8632 00:24:50.785815
8633 00:24:50.785889 Set Vref, RX VrefLevel [Byte0]: 41
8634 00:24:50.789060 [Byte1]: 41
8635 00:24:50.793153
8636 00:24:50.793223 Set Vref, RX VrefLevel [Byte0]: 42
8637 00:24:50.797053 [Byte1]: 42
8638 00:24:50.800677
8639 00:24:50.800747 Set Vref, RX VrefLevel [Byte0]: 43
8640 00:24:50.804198 [Byte1]: 43
8641 00:24:50.808562
8642 00:24:50.808639 Set Vref, RX VrefLevel [Byte0]: 44
8643 00:24:50.811800 [Byte1]: 44
8644 00:24:50.815908
8645 00:24:50.815989 Set Vref, RX VrefLevel [Byte0]: 45
8646 00:24:50.819394 [Byte1]: 45
8647 00:24:50.823399
8648 00:24:50.823478 Set Vref, RX VrefLevel [Byte0]: 46
8649 00:24:50.826844 [Byte1]: 46
8650 00:24:50.831372
8651 00:24:50.831451 Set Vref, RX VrefLevel [Byte0]: 47
8652 00:24:50.834403 [Byte1]: 47
8653 00:24:50.838435
8654 00:24:50.838514 Set Vref, RX VrefLevel [Byte0]: 48
8655 00:24:50.841843 [Byte1]: 48
8656 00:24:50.845994
8657 00:24:50.846069 Set Vref, RX VrefLevel [Byte0]: 49
8658 00:24:50.850023 [Byte1]: 49
8659 00:24:50.853895
8660 00:24:50.853970 Set Vref, RX VrefLevel [Byte0]: 50
8661 00:24:50.856817 [Byte1]: 50
8662 00:24:50.861372
8663 00:24:50.861439 Set Vref, RX VrefLevel [Byte0]: 51
8664 00:24:50.864864 [Byte1]: 51
8665 00:24:50.868737
8666 00:24:50.868809 Set Vref, RX VrefLevel [Byte0]: 52
8667 00:24:50.871980 [Byte1]: 52
8668 00:24:50.876273
8669 00:24:50.876341 Set Vref, RX VrefLevel [Byte0]: 53
8670 00:24:50.880205 [Byte1]: 53
8671 00:24:50.883926
8672 00:24:50.883998 Set Vref, RX VrefLevel [Byte0]: 54
8673 00:24:50.887114 [Byte1]: 54
8674 00:24:50.891518
8675 00:24:50.891593 Set Vref, RX VrefLevel [Byte0]: 55
8676 00:24:50.894996 [Byte1]: 55
8677 00:24:50.899080
8678 00:24:50.899149 Set Vref, RX VrefLevel [Byte0]: 56
8679 00:24:50.902655 [Byte1]: 56
8680 00:24:50.906507
8681 00:24:50.906608 Set Vref, RX VrefLevel [Byte0]: 57
8682 00:24:50.910242 [Byte1]: 57
8683 00:24:50.914216
8684 00:24:50.914293 Set Vref, RX VrefLevel [Byte0]: 58
8685 00:24:50.917484 [Byte1]: 58
8686 00:24:50.922057
8687 00:24:50.922137 Set Vref, RX VrefLevel [Byte0]: 59
8688 00:24:50.925483 [Byte1]: 59
8689 00:24:50.929203
8690 00:24:50.929280 Set Vref, RX VrefLevel [Byte0]: 60
8691 00:24:50.932769 [Byte1]: 60
8692 00:24:50.936976
8693 00:24:50.937046 Set Vref, RX VrefLevel [Byte0]: 61
8694 00:24:50.940172 [Byte1]: 61
8695 00:24:50.944721
8696 00:24:50.944792 Set Vref, RX VrefLevel [Byte0]: 62
8697 00:24:50.947857 [Byte1]: 62
8698 00:24:50.952220
8699 00:24:50.952293 Set Vref, RX VrefLevel [Byte0]: 63
8700 00:24:50.956317 [Byte1]: 63
8701 00:24:50.959908
8702 00:24:50.959981 Set Vref, RX VrefLevel [Byte0]: 64
8703 00:24:50.962898 [Byte1]: 64
8704 00:24:50.967598
8705 00:24:50.967679 Set Vref, RX VrefLevel [Byte0]: 65
8706 00:24:50.970501 [Byte1]: 65
8707 00:24:50.974765
8708 00:24:50.974845 Set Vref, RX VrefLevel [Byte0]: 66
8709 00:24:50.978222 [Byte1]: 66
8710 00:24:50.982690
8711 00:24:50.982770 Set Vref, RX VrefLevel [Byte0]: 67
8712 00:24:50.985940 [Byte1]: 67
8713 00:24:50.990202
8714 00:24:50.990281 Set Vref, RX VrefLevel [Byte0]: 68
8715 00:24:50.993545 [Byte1]: 68
8716 00:24:50.997722
8717 00:24:50.997801 Set Vref, RX VrefLevel [Byte0]: 69
8718 00:24:51.000797 [Byte1]: 69
8719 00:24:51.005969
8720 00:24:51.006048 Set Vref, RX VrefLevel [Byte0]: 70
8721 00:24:51.009177 [Byte1]: 70
8722 00:24:51.013210
8723 00:24:51.013289 Set Vref, RX VrefLevel [Byte0]: 71
8724 00:24:51.017049 [Byte1]: 71
8725 00:24:51.020356
8726 00:24:51.020436 Set Vref, RX VrefLevel [Byte0]: 72
8727 00:24:51.023845 [Byte1]: 72
8728 00:24:51.028161
8729 00:24:51.028240 Final RX Vref Byte 0 = 63 to rank0
8730 00:24:51.031497 Final RX Vref Byte 1 = 62 to rank0
8731 00:24:51.034725 Final RX Vref Byte 0 = 63 to rank1
8732 00:24:51.037930 Final RX Vref Byte 1 = 62 to rank1==
8733 00:24:51.041243 Dram Type= 6, Freq= 0, CH_1, rank 0
8734 00:24:51.048579 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8735 00:24:51.048660 ==
8736 00:24:51.048724 DQS Delay:
8737 00:24:51.051661 DQS0 = 0, DQS1 = 0
8738 00:24:51.051740 DQM Delay:
8739 00:24:51.051803 DQM0 = 135, DQM1 = 129
8740 00:24:51.054222 DQ Delay:
8741 00:24:51.057576 DQ0 =142, DQ1 =130, DQ2 =122, DQ3 =132
8742 00:24:51.060720 DQ4 =130, DQ5 =150, DQ6 =146, DQ7 =130
8743 00:24:51.064215 DQ8 =116, DQ9 =116, DQ10 =132, DQ11 =120
8744 00:24:51.067633 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =138
8745 00:24:51.067710
8746 00:24:51.067771
8747 00:24:51.067836
8748 00:24:51.070716 [DramC_TX_OE_Calibration] TA2
8749 00:24:51.074053 Original DQ_B0 (3 6) =30, OEN = 27
8750 00:24:51.077325 Original DQ_B1 (3 6) =30, OEN = 27
8751 00:24:51.080600 24, 0x0, End_B0=24 End_B1=24
8752 00:24:51.080674 25, 0x0, End_B0=25 End_B1=25
8753 00:24:51.083784 26, 0x0, End_B0=26 End_B1=26
8754 00:24:51.087413 27, 0x0, End_B0=27 End_B1=27
8755 00:24:51.090420 28, 0x0, End_B0=28 End_B1=28
8756 00:24:51.093702 29, 0x0, End_B0=29 End_B1=29
8757 00:24:51.093773 30, 0x0, End_B0=30 End_B1=30
8758 00:24:51.097050 31, 0x4545, End_B0=30 End_B1=30
8759 00:24:51.100763 Byte0 end_step=30 best_step=27
8760 00:24:51.103745 Byte1 end_step=30 best_step=27
8761 00:24:51.107499 Byte0 TX OE(2T, 0.5T) = (3, 3)
8762 00:24:51.110135 Byte1 TX OE(2T, 0.5T) = (3, 3)
8763 00:24:51.110205
8764 00:24:51.110271
8765 00:24:51.116803 [DQSOSCAuto] RK0, (LSB)MR18= 0x190e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8766 00:24:51.120085 CH1 RK0: MR19=303, MR18=190E
8767 00:24:51.126824 CH1_RK0: MR19=0x303, MR18=0x190E, DQSOSC=397, MR23=63, INC=23, DEC=15
8768 00:24:51.126907
8769 00:24:51.130402 ----->DramcWriteLeveling(PI) begin...
8770 00:24:51.130483 ==
8771 00:24:51.133482 Dram Type= 6, Freq= 0, CH_1, rank 1
8772 00:24:51.136849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8773 00:24:51.136929 ==
8774 00:24:51.140058 Write leveling (Byte 0): 26 => 26
8775 00:24:51.143209 Write leveling (Byte 1): 27 => 27
8776 00:24:51.146735 DramcWriteLeveling(PI) end<-----
8777 00:24:51.146833
8778 00:24:51.146928 ==
8779 00:24:51.150370 Dram Type= 6, Freq= 0, CH_1, rank 1
8780 00:24:51.153207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8781 00:24:51.156984 ==
8782 00:24:51.157063 [Gating] SW mode calibration
8783 00:24:51.166747 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8784 00:24:51.170068 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8785 00:24:51.173502 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 00:24:51.180117 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 00:24:51.182814 1 4 8 | B1->B0 | 2625 2323 | 1 0 | (0 0) (0 0)
8788 00:24:51.186936 1 4 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
8789 00:24:51.193117 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 00:24:51.196631 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 00:24:51.199632 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 00:24:51.205831 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 00:24:51.209396 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 00:24:51.212862 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 00:24:51.219485 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8796 00:24:51.222398 1 5 12 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 0)
8797 00:24:51.225907 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8798 00:24:51.232692 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 00:24:51.235498 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 00:24:51.239488 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 00:24:51.246055 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 00:24:51.249383 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 00:24:51.252149 1 6 8 | B1->B0 | 2e2d 2323 | 1 0 | (0 0) (0 0)
8804 00:24:51.258888 1 6 12 | B1->B0 | 4646 2424 | 0 0 | (0 0) (0 0)
8805 00:24:51.262248 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 00:24:51.265642 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 00:24:51.272353 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 00:24:51.275210 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 00:24:51.278933 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 00:24:51.285190 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 00:24:51.288330 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8812 00:24:51.291906 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8813 00:24:51.298623 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8814 00:24:51.301860 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 00:24:51.304989 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 00:24:51.311612 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 00:24:51.315408 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 00:24:51.318603 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 00:24:51.324981 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 00:24:51.328857 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 00:24:51.331289 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 00:24:51.338227 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 00:24:51.341217 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 00:24:51.344664 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 00:24:51.351548 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 00:24:51.354367 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 00:24:51.358485 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8828 00:24:51.364201 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8829 00:24:51.368256 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 00:24:51.371145 Total UI for P1: 0, mck2ui 16
8831 00:24:51.374540 best dqsien dly found for B0: ( 1, 9, 10)
8832 00:24:51.377526 Total UI for P1: 0, mck2ui 16
8833 00:24:51.381138 best dqsien dly found for B1: ( 1, 9, 10)
8834 00:24:51.384096 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8835 00:24:51.387899 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8836 00:24:51.387979
8837 00:24:51.390817 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8838 00:24:51.394719 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8839 00:24:51.398017 [Gating] SW calibration Done
8840 00:24:51.398095 ==
8841 00:24:51.400756 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 00:24:51.407411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 00:24:51.407487 ==
8844 00:24:51.407549 RX Vref Scan: 0
8845 00:24:51.407615
8846 00:24:51.410672 RX Vref 0 -> 0, step: 1
8847 00:24:51.410741
8848 00:24:51.413934 RX Delay 0 -> 252, step: 8
8849 00:24:51.417868 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8850 00:24:51.420432 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8851 00:24:51.423721 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8852 00:24:51.427507 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8853 00:24:51.433924 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8854 00:24:51.437058 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8855 00:24:51.440274 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8856 00:24:51.443466 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8857 00:24:51.446879 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8858 00:24:51.453553 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8859 00:24:51.457050 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8860 00:24:51.460050 iDelay=208, Bit 11, Center 119 (56 ~ 183) 128
8861 00:24:51.463179 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8862 00:24:51.470030 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8863 00:24:51.473166 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8864 00:24:51.476403 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8865 00:24:51.476473 ==
8866 00:24:51.479743 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 00:24:51.482753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 00:24:51.486269 ==
8869 00:24:51.486337 DQS Delay:
8870 00:24:51.486396 DQS0 = 0, DQS1 = 0
8871 00:24:51.489917 DQM Delay:
8872 00:24:51.489990 DQM0 = 136, DQM1 = 129
8873 00:24:51.492760 DQ Delay:
8874 00:24:51.496341 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8875 00:24:51.499840 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8876 00:24:51.502610 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8877 00:24:51.506255 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8878 00:24:51.506330
8879 00:24:51.506389
8880 00:24:51.506445 ==
8881 00:24:51.509655 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 00:24:51.513053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 00:24:51.513123 ==
8884 00:24:51.513181
8885 00:24:51.516116
8886 00:24:51.516182 TX Vref Scan disable
8887 00:24:51.519092 == TX Byte 0 ==
8888 00:24:51.522564 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8889 00:24:51.525947 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8890 00:24:51.529351 == TX Byte 1 ==
8891 00:24:51.532406 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8892 00:24:51.535767 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8893 00:24:51.535846 ==
8894 00:24:51.539833 Dram Type= 6, Freq= 0, CH_1, rank 1
8895 00:24:51.545730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8896 00:24:51.545810 ==
8897 00:24:51.557599
8898 00:24:51.560763 TX Vref early break, caculate TX vref
8899 00:24:51.564910 TX Vref=16, minBit 0, minWin=23, winSum=384
8900 00:24:51.567475 TX Vref=18, minBit 1, minWin=23, winSum=393
8901 00:24:51.570906 TX Vref=20, minBit 0, minWin=25, winSum=409
8902 00:24:51.573995 TX Vref=22, minBit 1, minWin=25, winSum=416
8903 00:24:51.577284 TX Vref=24, minBit 5, minWin=25, winSum=423
8904 00:24:51.584173 TX Vref=26, minBit 0, minWin=25, winSum=424
8905 00:24:51.587122 TX Vref=28, minBit 0, minWin=26, winSum=426
8906 00:24:51.590553 TX Vref=30, minBit 0, minWin=25, winSum=421
8907 00:24:51.593955 TX Vref=32, minBit 0, minWin=25, winSum=413
8908 00:24:51.596901 TX Vref=34, minBit 9, minWin=23, winSum=398
8909 00:24:51.603544 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8910 00:24:51.603619
8911 00:24:51.606958 Final TX Range 0 Vref 28
8912 00:24:51.607033
8913 00:24:51.607093 ==
8914 00:24:51.610455 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 00:24:51.614164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 00:24:51.614237 ==
8917 00:24:51.614298
8918 00:24:51.614363
8919 00:24:51.616835 TX Vref Scan disable
8920 00:24:51.623309 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8921 00:24:51.623392 == TX Byte 0 ==
8922 00:24:51.627129 u2DelayCellOfst[0]=22 cells (6 PI)
8923 00:24:51.629966 u2DelayCellOfst[1]=14 cells (4 PI)
8924 00:24:51.633485 u2DelayCellOfst[2]=0 cells (0 PI)
8925 00:24:51.636637 u2DelayCellOfst[3]=7 cells (2 PI)
8926 00:24:51.640557 u2DelayCellOfst[4]=11 cells (3 PI)
8927 00:24:51.643706 u2DelayCellOfst[5]=22 cells (6 PI)
8928 00:24:51.646874 u2DelayCellOfst[6]=22 cells (6 PI)
8929 00:24:51.649732 u2DelayCellOfst[7]=7 cells (2 PI)
8930 00:24:51.653465 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8931 00:24:51.656178 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8932 00:24:51.659663 == TX Byte 1 ==
8933 00:24:51.663069 u2DelayCellOfst[8]=0 cells (0 PI)
8934 00:24:51.666338 u2DelayCellOfst[9]=3 cells (1 PI)
8935 00:24:51.669418 u2DelayCellOfst[10]=11 cells (3 PI)
8936 00:24:51.669491 u2DelayCellOfst[11]=3 cells (1 PI)
8937 00:24:51.672799 u2DelayCellOfst[12]=18 cells (5 PI)
8938 00:24:51.676390 u2DelayCellOfst[13]=18 cells (5 PI)
8939 00:24:51.679603 u2DelayCellOfst[14]=18 cells (5 PI)
8940 00:24:51.683062 u2DelayCellOfst[15]=18 cells (5 PI)
8941 00:24:51.689710 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8942 00:24:51.692939 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8943 00:24:51.693013 DramC Write-DBI on
8944 00:24:51.695920 ==
8945 00:24:51.696000 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 00:24:51.702909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 00:24:51.702989 ==
8948 00:24:51.703050
8949 00:24:51.703107
8950 00:24:51.705942 TX Vref Scan disable
8951 00:24:51.706013 == TX Byte 0 ==
8952 00:24:51.712407 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8953 00:24:51.712488 == TX Byte 1 ==
8954 00:24:51.715888 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8955 00:24:51.719190 DramC Write-DBI off
8956 00:24:51.719258
8957 00:24:51.719316 [DATLAT]
8958 00:24:51.722439 Freq=1600, CH1 RK1
8959 00:24:51.722517
8960 00:24:51.722578 DATLAT Default: 0xf
8961 00:24:51.726080 0, 0xFFFF, sum = 0
8962 00:24:51.726160 1, 0xFFFF, sum = 0
8963 00:24:51.728954 2, 0xFFFF, sum = 0
8964 00:24:51.729034 3, 0xFFFF, sum = 0
8965 00:24:51.732750 4, 0xFFFF, sum = 0
8966 00:24:51.732830 5, 0xFFFF, sum = 0
8967 00:24:51.735591 6, 0xFFFF, sum = 0
8968 00:24:51.735671 7, 0xFFFF, sum = 0
8969 00:24:51.739047 8, 0xFFFF, sum = 0
8970 00:24:51.742202 9, 0xFFFF, sum = 0
8971 00:24:51.742282 10, 0xFFFF, sum = 0
8972 00:24:51.745574 11, 0xFFFF, sum = 0
8973 00:24:51.745655 12, 0xFFFF, sum = 0
8974 00:24:51.748635 13, 0xFFFF, sum = 0
8975 00:24:51.748718 14, 0x0, sum = 1
8976 00:24:51.752298 15, 0x0, sum = 2
8977 00:24:51.752377 16, 0x0, sum = 3
8978 00:24:51.755283 17, 0x0, sum = 4
8979 00:24:51.755363 best_step = 15
8980 00:24:51.755426
8981 00:24:51.755483 ==
8982 00:24:51.758770 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 00:24:51.761839 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 00:24:51.761918 ==
8985 00:24:51.765386 RX Vref Scan: 0
8986 00:24:51.765465
8987 00:24:51.768879 RX Vref 0 -> 0, step: 1
8988 00:24:51.768958
8989 00:24:51.769019 RX Delay 11 -> 252, step: 4
8990 00:24:51.776008 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
8991 00:24:51.779252 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
8992 00:24:51.782324 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
8993 00:24:51.785665 iDelay=203, Bit 3, Center 132 (79 ~ 186) 108
8994 00:24:51.789071 iDelay=203, Bit 4, Center 132 (79 ~ 186) 108
8995 00:24:51.795722 iDelay=203, Bit 5, Center 146 (91 ~ 202) 112
8996 00:24:51.799288 iDelay=203, Bit 6, Center 146 (95 ~ 198) 104
8997 00:24:51.802453 iDelay=203, Bit 7, Center 132 (83 ~ 182) 100
8998 00:24:51.805712 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
8999 00:24:51.809112 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9000 00:24:51.815361 iDelay=203, Bit 10, Center 130 (75 ~ 186) 112
9001 00:24:51.818711 iDelay=203, Bit 11, Center 118 (63 ~ 174) 112
9002 00:24:51.821846 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9003 00:24:51.826030 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9004 00:24:51.832036 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9005 00:24:51.835322 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9006 00:24:51.835393 ==
9007 00:24:51.838650 Dram Type= 6, Freq= 0, CH_1, rank 1
9008 00:24:51.841828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9009 00:24:51.841899 ==
9010 00:24:51.845502 DQS Delay:
9011 00:24:51.845572 DQS0 = 0, DQS1 = 0
9012 00:24:51.845631 DQM Delay:
9013 00:24:51.848845 DQM0 = 134, DQM1 = 127
9014 00:24:51.848922 DQ Delay:
9015 00:24:51.851727 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =132
9016 00:24:51.855138 DQ4 =132, DQ5 =146, DQ6 =146, DQ7 =132
9017 00:24:51.861615 DQ8 =112, DQ9 =116, DQ10 =130, DQ11 =118
9018 00:24:51.865371 DQ12 =136, DQ13 =134, DQ14 =134, DQ15 =138
9019 00:24:51.865450
9020 00:24:51.865512
9021 00:24:51.865570
9022 00:24:51.868619 [DramC_TX_OE_Calibration] TA2
9023 00:24:51.871674 Original DQ_B0 (3 6) =30, OEN = 27
9024 00:24:51.871754 Original DQ_B1 (3 6) =30, OEN = 27
9025 00:24:51.875016 24, 0x0, End_B0=24 End_B1=24
9026 00:24:51.878060 25, 0x0, End_B0=25 End_B1=25
9027 00:24:51.881831 26, 0x0, End_B0=26 End_B1=26
9028 00:24:51.884917 27, 0x0, End_B0=27 End_B1=27
9029 00:24:51.884998 28, 0x0, End_B0=28 End_B1=28
9030 00:24:51.888266 29, 0x0, End_B0=29 End_B1=29
9031 00:24:51.891596 30, 0x0, End_B0=30 End_B1=30
9032 00:24:51.894852 31, 0x4141, End_B0=30 End_B1=30
9033 00:24:51.897814 Byte0 end_step=30 best_step=27
9034 00:24:51.901245 Byte1 end_step=30 best_step=27
9035 00:24:51.901324 Byte0 TX OE(2T, 0.5T) = (3, 3)
9036 00:24:51.904630 Byte1 TX OE(2T, 0.5T) = (3, 3)
9037 00:24:51.904709
9038 00:24:51.904771
9039 00:24:51.914617 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
9040 00:24:51.914697 CH1 RK1: MR19=303, MR18=E0A
9041 00:24:51.921640 CH1_RK1: MR19=0x303, MR18=0xE0A, DQSOSC=402, MR23=63, INC=22, DEC=15
9042 00:24:51.924886 [RxdqsGatingPostProcess] freq 1600
9043 00:24:51.931207 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9044 00:24:51.935006 best DQS0 dly(2T, 0.5T) = (1, 1)
9045 00:24:51.937603 best DQS1 dly(2T, 0.5T) = (1, 1)
9046 00:24:51.941374 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9047 00:24:51.944744 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9048 00:24:51.947929 best DQS0 dly(2T, 0.5T) = (1, 1)
9049 00:24:51.948007 best DQS1 dly(2T, 0.5T) = (1, 1)
9050 00:24:51.950697 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9051 00:24:51.954150 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9052 00:24:51.957639 Pre-setting of DQS Precalculation
9053 00:24:51.963965 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9054 00:24:51.970630 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9055 00:24:51.977327 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9056 00:24:51.977412
9057 00:24:51.977476
9058 00:24:51.980331 [Calibration Summary] 3200 Mbps
9059 00:24:51.984161 CH 0, Rank 0
9060 00:24:51.984242 SW Impedance : PASS
9061 00:24:51.987300 DUTY Scan : NO K
9062 00:24:51.987368 ZQ Calibration : PASS
9063 00:24:51.990710 Jitter Meter : NO K
9064 00:24:51.993801 CBT Training : PASS
9065 00:24:51.993872 Write leveling : PASS
9066 00:24:51.997074 RX DQS gating : PASS
9067 00:24:52.000625 RX DQ/DQS(RDDQC) : PASS
9068 00:24:52.000697 TX DQ/DQS : PASS
9069 00:24:52.004208 RX DATLAT : PASS
9070 00:24:52.007174 RX DQ/DQS(Engine): PASS
9071 00:24:52.007244 TX OE : PASS
9072 00:24:52.010334 All Pass.
9073 00:24:52.010398
9074 00:24:52.010461 CH 0, Rank 1
9075 00:24:52.013558 SW Impedance : PASS
9076 00:24:52.013627 DUTY Scan : NO K
9077 00:24:52.016796 ZQ Calibration : PASS
9078 00:24:52.020393 Jitter Meter : NO K
9079 00:24:52.020473 CBT Training : PASS
9080 00:24:52.024253 Write leveling : PASS
9081 00:24:52.027131 RX DQS gating : PASS
9082 00:24:52.027209 RX DQ/DQS(RDDQC) : PASS
9083 00:24:52.030162 TX DQ/DQS : PASS
9084 00:24:52.033546 RX DATLAT : PASS
9085 00:24:52.033625 RX DQ/DQS(Engine): PASS
9086 00:24:52.036746 TX OE : PASS
9087 00:24:52.036825 All Pass.
9088 00:24:52.036886
9089 00:24:52.039962 CH 1, Rank 0
9090 00:24:52.040040 SW Impedance : PASS
9091 00:24:52.043201 DUTY Scan : NO K
9092 00:24:52.047152 ZQ Calibration : PASS
9093 00:24:52.047230 Jitter Meter : NO K
9094 00:24:52.049998 CBT Training : PASS
9095 00:24:52.053442 Write leveling : PASS
9096 00:24:52.053517 RX DQS gating : PASS
9097 00:24:52.056674 RX DQ/DQS(RDDQC) : PASS
9098 00:24:52.056746 TX DQ/DQS : PASS
9099 00:24:52.059711 RX DATLAT : PASS
9100 00:24:52.062753 RX DQ/DQS(Engine): PASS
9101 00:24:52.062822 TX OE : PASS
9102 00:24:52.066459 All Pass.
9103 00:24:52.066538
9104 00:24:52.066626 CH 1, Rank 1
9105 00:24:52.069618 SW Impedance : PASS
9106 00:24:52.069689 DUTY Scan : NO K
9107 00:24:52.072741 ZQ Calibration : PASS
9108 00:24:52.076214 Jitter Meter : NO K
9109 00:24:52.076294 CBT Training : PASS
9110 00:24:52.079711 Write leveling : PASS
9111 00:24:52.082649 RX DQS gating : PASS
9112 00:24:52.082732 RX DQ/DQS(RDDQC) : PASS
9113 00:24:52.086061 TX DQ/DQS : PASS
9114 00:24:52.089884 RX DATLAT : PASS
9115 00:24:52.089963 RX DQ/DQS(Engine): PASS
9116 00:24:52.092703 TX OE : PASS
9117 00:24:52.092782 All Pass.
9118 00:24:52.092844
9119 00:24:52.096327 DramC Write-DBI on
9120 00:24:52.099164 PER_BANK_REFRESH: Hybrid Mode
9121 00:24:52.099243 TX_TRACKING: ON
9122 00:24:52.109084 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9123 00:24:52.115733 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9124 00:24:52.122670 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9125 00:24:52.128935 [FAST_K] Save calibration result to emmc
9126 00:24:52.129014 sync common calibartion params.
9127 00:24:52.132242 sync cbt_mode0:1, 1:1
9128 00:24:52.135551 dram_init: ddr_geometry: 2
9129 00:24:52.135622 dram_init: ddr_geometry: 2
9130 00:24:52.139347 dram_init: ddr_geometry: 2
9131 00:24:52.142319 0:dram_rank_size:100000000
9132 00:24:52.145434 1:dram_rank_size:100000000
9133 00:24:52.148906 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9134 00:24:52.152522 DFS_SHUFFLE_HW_MODE: ON
9135 00:24:52.155109 dramc_set_vcore_voltage set vcore to 725000
9136 00:24:52.158585 Read voltage for 1600, 0
9137 00:24:52.158696 Vio18 = 0
9138 00:24:52.162229 Vcore = 725000
9139 00:24:52.162299 Vdram = 0
9140 00:24:52.162365 Vddq = 0
9141 00:24:52.162422 Vmddr = 0
9142 00:24:52.164964 switch to 3200 Mbps bootup
9143 00:24:52.169114 [DramcRunTimeConfig]
9144 00:24:52.169184 PHYPLL
9145 00:24:52.172417 DPM_CONTROL_AFTERK: ON
9146 00:24:52.172497 PER_BANK_REFRESH: ON
9147 00:24:52.175157 REFRESH_OVERHEAD_REDUCTION: ON
9148 00:24:52.179136 CMD_PICG_NEW_MODE: OFF
9149 00:24:52.179206 XRTWTW_NEW_MODE: ON
9150 00:24:52.181562 XRTRTR_NEW_MODE: ON
9151 00:24:52.181637 TX_TRACKING: ON
9152 00:24:52.184763 RDSEL_TRACKING: OFF
9153 00:24:52.188556 DQS Precalculation for DVFS: ON
9154 00:24:52.188628 RX_TRACKING: OFF
9155 00:24:52.191388 HW_GATING DBG: ON
9156 00:24:52.191463 ZQCS_ENABLE_LP4: ON
9157 00:24:52.195043 RX_PICG_NEW_MODE: ON
9158 00:24:52.195113 TX_PICG_NEW_MODE: ON
9159 00:24:52.198563 ENABLE_RX_DCM_DPHY: ON
9160 00:24:52.201838 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9161 00:24:52.204711 DUMMY_READ_FOR_TRACKING: OFF
9162 00:24:52.204789 !!! SPM_CONTROL_AFTERK: OFF
9163 00:24:52.208179 !!! SPM could not control APHY
9164 00:24:52.211506 IMPEDANCE_TRACKING: ON
9165 00:24:52.211573 TEMP_SENSOR: ON
9166 00:24:52.214582 HW_SAVE_FOR_SR: OFF
9167 00:24:52.218129 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9168 00:24:52.221445 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9169 00:24:52.221525 Read ODT Tracking: ON
9170 00:24:52.224429 Refresh Rate DeBounce: ON
9171 00:24:52.228208 DFS_NO_QUEUE_FLUSH: ON
9172 00:24:52.231397 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9173 00:24:52.231476 ENABLE_DFS_RUNTIME_MRW: OFF
9174 00:24:52.234488 DDR_RESERVE_NEW_MODE: ON
9175 00:24:52.238087 MR_CBT_SWITCH_FREQ: ON
9176 00:24:52.238167 =========================
9177 00:24:52.258107 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9178 00:24:52.261797 dram_init: ddr_geometry: 2
9179 00:24:52.279999 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9180 00:24:52.283227 dram_init: dram init end (result: 0)
9181 00:24:52.289587 DRAM-K: Full calibration passed in 24582 msecs
9182 00:24:52.292882 MRC: failed to locate region type 0.
9183 00:24:52.292955 DRAM rank0 size:0x100000000,
9184 00:24:52.296248 DRAM rank1 size=0x100000000
9185 00:24:52.306363 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9186 00:24:52.312906 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9187 00:24:52.319000 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9188 00:24:52.329700 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9189 00:24:52.329781 DRAM rank0 size:0x100000000,
9190 00:24:52.332263 DRAM rank1 size=0x100000000
9191 00:24:52.332332 CBMEM:
9192 00:24:52.335533 IMD: root @ 0xfffff000 254 entries.
9193 00:24:52.338970 IMD: root @ 0xffffec00 62 entries.
9194 00:24:52.342236 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9195 00:24:52.349086 WARNING: RO_VPD is uninitialized or empty.
9196 00:24:52.352374 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9197 00:24:52.359752 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9198 00:24:52.372457 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9199 00:24:52.383945 BS: romstage times (exec / console): total (unknown) / 24084 ms
9200 00:24:52.384025
9201 00:24:52.384087
9202 00:24:52.393751 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9203 00:24:52.397038 ARM64: Exception handlers installed.
9204 00:24:52.400678 ARM64: Testing exception
9205 00:24:52.403669 ARM64: Done test exception
9206 00:24:52.403749 Enumerating buses...
9207 00:24:52.407114 Show all devs... Before device enumeration.
9208 00:24:52.410834 Root Device: enabled 1
9209 00:24:52.413669 CPU_CLUSTER: 0: enabled 1
9210 00:24:52.413748 CPU: 00: enabled 1
9211 00:24:52.417106 Compare with tree...
9212 00:24:52.417185 Root Device: enabled 1
9213 00:24:52.420499 CPU_CLUSTER: 0: enabled 1
9214 00:24:52.423403 CPU: 00: enabled 1
9215 00:24:52.423481 Root Device scanning...
9216 00:24:52.426945 scan_static_bus for Root Device
9217 00:24:52.430049 CPU_CLUSTER: 0 enabled
9218 00:24:52.433604 scan_static_bus for Root Device done
9219 00:24:52.436452 scan_bus: bus Root Device finished in 8 msecs
9220 00:24:52.436525 done
9221 00:24:52.443686 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9222 00:24:52.447114 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9223 00:24:52.453171 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9224 00:24:52.456729 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9225 00:24:52.459871 Allocating resources...
9226 00:24:52.463477 Reading resources...
9227 00:24:52.466510 Root Device read_resources bus 0 link: 0
9228 00:24:52.469818 DRAM rank0 size:0x100000000,
9229 00:24:52.469898 DRAM rank1 size=0x100000000
9230 00:24:52.476948 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9231 00:24:52.477023 CPU: 00 missing read_resources
9232 00:24:52.482868 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9233 00:24:52.486646 Root Device read_resources bus 0 link: 0 done
9234 00:24:52.489469 Done reading resources.
9235 00:24:52.493199 Show resources in subtree (Root Device)...After reading.
9236 00:24:52.496449 Root Device child on link 0 CPU_CLUSTER: 0
9237 00:24:52.499299 CPU_CLUSTER: 0 child on link 0 CPU: 00
9238 00:24:52.509509 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9239 00:24:52.509589 CPU: 00
9240 00:24:52.513163 Root Device assign_resources, bus 0 link: 0
9241 00:24:52.516468 CPU_CLUSTER: 0 missing set_resources
9242 00:24:52.522423 Root Device assign_resources, bus 0 link: 0 done
9243 00:24:52.522503 Done setting resources.
9244 00:24:52.529146 Show resources in subtree (Root Device)...After assigning values.
9245 00:24:52.532770 Root Device child on link 0 CPU_CLUSTER: 0
9246 00:24:52.535838 CPU_CLUSTER: 0 child on link 0 CPU: 00
9247 00:24:52.546389 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9248 00:24:52.546469 CPU: 00
9249 00:24:52.549031 Done allocating resources.
9250 00:24:52.555810 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9251 00:24:52.555890 Enabling resources...
9252 00:24:52.555953 done.
9253 00:24:52.562385 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9254 00:24:52.565814 Initializing devices...
9255 00:24:52.565893 Root Device init
9256 00:24:52.569110 init hardware done!
9257 00:24:52.569190 0x00000018: ctrlr->caps
9258 00:24:52.572089 52.000 MHz: ctrlr->f_max
9259 00:24:52.575461 0.400 MHz: ctrlr->f_min
9260 00:24:52.575542 0x40ff8080: ctrlr->voltages
9261 00:24:52.578899 sclk: 390625
9262 00:24:52.578978 Bus Width = 1
9263 00:24:52.579040 sclk: 390625
9264 00:24:52.582578 Bus Width = 1
9265 00:24:52.582698 Early init status = 3
9266 00:24:52.588906 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9267 00:24:52.592216 in-header: 03 fc 00 00 01 00 00 00
9268 00:24:52.595419 in-data: 00
9269 00:24:52.598574 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9270 00:24:52.603538 in-header: 03 fd 00 00 00 00 00 00
9271 00:24:52.606805 in-data:
9272 00:24:52.610092 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9273 00:24:52.614794 in-header: 03 fc 00 00 01 00 00 00
9274 00:24:52.617776 in-data: 00
9275 00:24:52.621105 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9276 00:24:52.626265 in-header: 03 fd 00 00 00 00 00 00
9277 00:24:52.629727 in-data:
9278 00:24:52.633392 [SSUSB] Setting up USB HOST controller...
9279 00:24:52.636472 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9280 00:24:52.639908 [SSUSB] phy power-on done.
9281 00:24:52.642976 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9282 00:24:52.649730 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9283 00:24:52.652730 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9284 00:24:52.659433 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9285 00:24:52.666340 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9286 00:24:52.672641 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9287 00:24:52.679019 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9288 00:24:52.685689 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9289 00:24:52.688994 SPM: binary array size = 0x9dc
9290 00:24:52.692226 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9291 00:24:52.698692 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9292 00:24:52.705631 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9293 00:24:52.712083 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9294 00:24:52.715268 configure_display: Starting display init
9295 00:24:52.749771 anx7625_power_on_init: Init interface.
9296 00:24:52.752962 anx7625_disable_pd_protocol: Disabled PD feature.
9297 00:24:52.756356 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9298 00:24:52.783945 anx7625_start_dp_work: Secure OCM version=00
9299 00:24:52.787682 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9300 00:24:52.802866 sp_tx_get_edid_block: EDID Block = 1
9301 00:24:52.905008 Extracted contents:
9302 00:24:52.908038 header: 00 ff ff ff ff ff ff 00
9303 00:24:52.911793 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9304 00:24:52.914562 version: 01 04
9305 00:24:52.917675 basic params: 95 1f 11 78 0a
9306 00:24:52.921500 chroma info: 76 90 94 55 54 90 27 21 50 54
9307 00:24:52.924344 established: 00 00 00
9308 00:24:52.931561 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9309 00:24:52.934370 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9310 00:24:52.940856 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9311 00:24:52.947672 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9312 00:24:52.954068 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9313 00:24:52.957328 extensions: 00
9314 00:24:52.957419 checksum: fb
9315 00:24:52.957483
9316 00:24:52.964087 Manufacturer: IVO Model 57d Serial Number 0
9317 00:24:52.964171 Made week 0 of 2020
9318 00:24:52.967614 EDID version: 1.4
9319 00:24:52.967696 Digital display
9320 00:24:52.970839 6 bits per primary color channel
9321 00:24:52.970919 DisplayPort interface
9322 00:24:52.974171 Maximum image size: 31 cm x 17 cm
9323 00:24:52.977142 Gamma: 220%
9324 00:24:52.977221 Check DPMS levels
9325 00:24:52.983801 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9326 00:24:52.987538 First detailed timing is preferred timing
9327 00:24:52.987618 Established timings supported:
9328 00:24:52.990714 Standard timings supported:
9329 00:24:52.993516 Detailed timings
9330 00:24:52.997157 Hex of detail: 383680a07038204018303c0035ae10000019
9331 00:24:53.003432 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9332 00:24:53.007122 0780 0798 07c8 0820 hborder 0
9333 00:24:53.010158 0438 043b 0447 0458 vborder 0
9334 00:24:53.013327 -hsync -vsync
9335 00:24:53.013406 Did detailed timing
9336 00:24:53.020001 Hex of detail: 000000000000000000000000000000000000
9337 00:24:53.023837 Manufacturer-specified data, tag 0
9338 00:24:53.026512 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9339 00:24:53.030110 ASCII string: InfoVision
9340 00:24:53.033423 Hex of detail: 000000fe00523134304e574635205248200a
9341 00:24:53.036967 ASCII string: R140NWF5 RH
9342 00:24:53.037046 Checksum
9343 00:24:53.039823 Checksum: 0xfb (valid)
9344 00:24:53.042924 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9345 00:24:53.046891 DSI data_rate: 832800000 bps
9346 00:24:53.052974 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9347 00:24:53.056608 anx7625_parse_edid: pixelclock(138800).
9348 00:24:53.059939 hactive(1920), hsync(48), hfp(24), hbp(88)
9349 00:24:53.063058 vactive(1080), vsync(12), vfp(3), vbp(17)
9350 00:24:53.066202 anx7625_dsi_config: config dsi.
9351 00:24:53.072957 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9352 00:24:53.086745 anx7625_dsi_config: success to config DSI
9353 00:24:53.089995 anx7625_dp_start: MIPI phy setup OK.
9354 00:24:53.093404 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9355 00:24:53.097278 mtk_ddp_mode_set invalid vrefresh 60
9356 00:24:53.100077 main_disp_path_setup
9357 00:24:53.100155 ovl_layer_smi_id_en
9358 00:24:53.103142 ovl_layer_smi_id_en
9359 00:24:53.103222 ccorr_config
9360 00:24:53.103284 aal_config
9361 00:24:53.106884 gamma_config
9362 00:24:53.106964 postmask_config
9363 00:24:53.109969 dither_config
9364 00:24:53.113021 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9365 00:24:53.119594 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9366 00:24:53.123491 Root Device init finished in 554 msecs
9367 00:24:53.126439 CPU_CLUSTER: 0 init
9368 00:24:53.132986 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9369 00:24:53.139455 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9370 00:24:53.139534 APU_MBOX 0x190000b0 = 0x10001
9371 00:24:53.143185 APU_MBOX 0x190001b0 = 0x10001
9372 00:24:53.146540 APU_MBOX 0x190005b0 = 0x10001
9373 00:24:53.149775 APU_MBOX 0x190006b0 = 0x10001
9374 00:24:53.156047 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9375 00:24:53.165996 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9376 00:24:53.178087 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9377 00:24:53.185312 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9378 00:24:53.196484 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9379 00:24:53.205868 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9380 00:24:53.209066 CPU_CLUSTER: 0 init finished in 81 msecs
9381 00:24:53.212468 Devices initialized
9382 00:24:53.215375 Show all devs... After init.
9383 00:24:53.215454 Root Device: enabled 1
9384 00:24:53.218920 CPU_CLUSTER: 0: enabled 1
9385 00:24:53.221973 CPU: 00: enabled 1
9386 00:24:53.225207 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9387 00:24:53.229117 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9388 00:24:53.232453 ELOG: NV offset 0x57f000 size 0x1000
9389 00:24:53.238965 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9390 00:24:53.245215 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9391 00:24:53.248481 ELOG: Event(17) added with size 13 at 2023-08-14 00:24:53 UTC
9392 00:24:53.255735 out: cmd=0x121: 03 db 21 01 00 00 00 00
9393 00:24:53.258430 in-header: 03 d8 00 00 2c 00 00 00
9394 00:24:53.268744 in-data: 87 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9395 00:24:53.274629 ELOG: Event(A1) added with size 10 at 2023-08-14 00:24:53 UTC
9396 00:24:53.281392 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9397 00:24:53.288042 ELOG: Event(A0) added with size 9 at 2023-08-14 00:24:54 UTC
9398 00:24:53.291267 elog_add_boot_reason: Logged dev mode boot
9399 00:24:53.297677 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9400 00:24:53.297756 Finalize devices...
9401 00:24:53.302266 Devices finalized
9402 00:24:53.304399 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9403 00:24:53.307549 Writing coreboot table at 0xffe64000
9404 00:24:53.311289 0. 000000000010a000-0000000000113fff: RAMSTAGE
9405 00:24:53.317761 1. 0000000040000000-00000000400fffff: RAM
9406 00:24:53.320931 2. 0000000040100000-000000004032afff: RAMSTAGE
9407 00:24:53.324651 3. 000000004032b000-00000000545fffff: RAM
9408 00:24:53.327748 4. 0000000054600000-000000005465ffff: BL31
9409 00:24:53.330865 5. 0000000054660000-00000000ffe63fff: RAM
9410 00:24:53.338035 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9411 00:24:53.340581 7. 0000000100000000-000000023fffffff: RAM
9412 00:24:53.344115 Passing 5 GPIOs to payload:
9413 00:24:53.347463 NAME | PORT | POLARITY | VALUE
9414 00:24:53.353767 EC in RW | 0x000000aa | low | undefined
9415 00:24:53.357180 EC interrupt | 0x00000005 | low | undefined
9416 00:24:53.363667 TPM interrupt | 0x000000ab | high | undefined
9417 00:24:53.367086 SD card detect | 0x00000011 | high | undefined
9418 00:24:53.370193 speaker enable | 0x00000093 | high | undefined
9419 00:24:53.373595 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9420 00:24:53.376772 in-header: 03 f9 00 00 02 00 00 00
9421 00:24:53.380058 in-data: 02 00
9422 00:24:53.383747 ADC[4]: Raw value=900443 ID=7
9423 00:24:53.386710 ADC[3]: Raw value=213282 ID=1
9424 00:24:53.386814 RAM Code: 0x71
9425 00:24:53.390305 ADC[6]: Raw value=75036 ID=0
9426 00:24:53.394022 ADC[5]: Raw value=213652 ID=1
9427 00:24:53.394101 SKU Code: 0x1
9428 00:24:53.400360 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a129
9429 00:24:53.400440 coreboot table: 964 bytes.
9430 00:24:53.403684 IMD ROOT 0. 0xfffff000 0x00001000
9431 00:24:53.407224 IMD SMALL 1. 0xffffe000 0x00001000
9432 00:24:53.410003 RO MCACHE 2. 0xffffc000 0x00001104
9433 00:24:53.413162 CONSOLE 3. 0xfff7c000 0x00080000
9434 00:24:53.417103 FMAP 4. 0xfff7b000 0x00000452
9435 00:24:53.420547 TIME STAMP 5. 0xfff7a000 0x00000910
9436 00:24:53.423051 VBOOT WORK 6. 0xfff66000 0x00014000
9437 00:24:53.426497 RAMOOPS 7. 0xffe66000 0x00100000
9438 00:24:53.429873 COREBOOT 8. 0xffe64000 0x00002000
9439 00:24:53.433037 IMD small region:
9440 00:24:53.436543 IMD ROOT 0. 0xffffec00 0x00000400
9441 00:24:53.440070 VPD 1. 0xffffeba0 0x0000004c
9442 00:24:53.442860 MMC STATUS 2. 0xffffeb80 0x00000004
9443 00:24:53.449830 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9444 00:24:53.449909 Probing TPM: done!
9445 00:24:53.456929 Connected to device vid:did:rid of 1ae0:0028:00
9446 00:24:53.462746 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9447 00:24:53.466030 Initialized TPM device CR50 revision 0
9448 00:24:53.469824 Checking cr50 for pending updates
9449 00:24:53.475254 Reading cr50 TPM mode
9450 00:24:53.484069 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9451 00:24:53.490330 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9452 00:24:53.530785 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9453 00:24:53.533749 Checking segment from ROM address 0x40100000
9454 00:24:53.537407 Checking segment from ROM address 0x4010001c
9455 00:24:53.543850 Loading segment from ROM address 0x40100000
9456 00:24:53.543921 code (compression=0)
9457 00:24:53.553736 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9458 00:24:53.560581 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9459 00:24:53.560662 it's not compressed!
9460 00:24:53.567462 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9461 00:24:53.573786 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9462 00:24:53.590551 Loading segment from ROM address 0x4010001c
9463 00:24:53.590640 Entry Point 0x80000000
9464 00:24:53.594368 Loaded segments
9465 00:24:53.597327 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9466 00:24:53.604649 Jumping to boot code at 0x80000000(0xffe64000)
9467 00:24:53.611152 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9468 00:24:53.617275 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9469 00:24:53.625780 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9470 00:24:53.629237 Checking segment from ROM address 0x40100000
9471 00:24:53.631734 Checking segment from ROM address 0x4010001c
9472 00:24:53.638451 Loading segment from ROM address 0x40100000
9473 00:24:53.638531 code (compression=1)
9474 00:24:53.645138 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9475 00:24:53.655126 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9476 00:24:53.655209 using LZMA
9477 00:24:53.663600 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9478 00:24:53.670418 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9479 00:24:53.673851 Loading segment from ROM address 0x4010001c
9480 00:24:53.673924 Entry Point 0x54601000
9481 00:24:53.677293 Loaded segments
9482 00:24:53.680502 NOTICE: MT8192 bl31_setup
9483 00:24:53.687311 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9484 00:24:53.690354 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9485 00:24:53.693805 WARNING: region 0:
9486 00:24:53.697385 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 00:24:53.697465 WARNING: region 1:
9488 00:24:53.703856 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9489 00:24:53.707211 WARNING: region 2:
9490 00:24:53.710411 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9491 00:24:53.713623 WARNING: region 3:
9492 00:24:53.716824 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9493 00:24:53.720519 WARNING: region 4:
9494 00:24:53.727036 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9495 00:24:53.727116 WARNING: region 5:
9496 00:24:53.730113 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 00:24:53.733512 WARNING: region 6:
9498 00:24:53.737020 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 00:24:53.740210 WARNING: region 7:
9500 00:24:53.743270 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9501 00:24:53.749779 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9502 00:24:53.753735 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9503 00:24:53.760485 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9504 00:24:53.763575 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9505 00:24:53.766546 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9506 00:24:53.773419 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9507 00:24:53.776491 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9508 00:24:53.779815 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9509 00:24:53.786294 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9510 00:24:53.789909 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9511 00:24:53.796371 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9512 00:24:53.799937 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9513 00:24:53.802906 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9514 00:24:53.809655 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9515 00:24:53.813190 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9516 00:24:53.816431 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9517 00:24:53.823166 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9518 00:24:53.826183 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9519 00:24:53.832926 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9520 00:24:53.835985 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9521 00:24:53.839662 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9522 00:24:53.846224 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9523 00:24:53.849638 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9524 00:24:53.853238 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9525 00:24:53.859484 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9526 00:24:53.862974 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9527 00:24:53.869739 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9528 00:24:53.872902 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9529 00:24:53.877078 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9530 00:24:53.882973 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9531 00:24:53.886346 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9532 00:24:53.893022 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9533 00:24:53.895924 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9534 00:24:53.899313 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9535 00:24:53.902711 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9536 00:24:53.909039 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9537 00:24:53.912675 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9538 00:24:53.915847 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9539 00:24:53.918934 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9540 00:24:53.925538 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9541 00:24:53.929364 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9542 00:24:53.932124 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9543 00:24:53.935481 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9544 00:24:53.942364 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9545 00:24:53.945786 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9546 00:24:53.949029 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9547 00:24:53.955491 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9548 00:24:53.958963 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9549 00:24:53.962161 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9550 00:24:53.968674 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9551 00:24:53.972146 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9552 00:24:53.978717 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9553 00:24:53.982069 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9554 00:24:53.985581 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9555 00:24:53.991841 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9556 00:24:53.995195 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9557 00:24:54.001815 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9558 00:24:54.004908 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9559 00:24:54.011741 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9560 00:24:54.014986 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9561 00:24:54.021682 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9562 00:24:54.025057 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9563 00:24:54.028192 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9564 00:24:54.034939 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9565 00:24:54.038698 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9566 00:24:54.044882 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9567 00:24:54.048237 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9568 00:24:54.054985 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9569 00:24:54.058103 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9570 00:24:54.061964 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9571 00:24:54.068345 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9572 00:24:54.071419 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9573 00:24:54.078208 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9574 00:24:54.081507 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9575 00:24:54.088083 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9576 00:24:54.091580 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9577 00:24:54.097924 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9578 00:24:54.101338 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9579 00:24:54.104619 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9580 00:24:54.111462 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9581 00:24:54.114732 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9582 00:24:54.121265 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9583 00:24:54.124606 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9584 00:24:54.131302 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9585 00:24:54.134589 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9586 00:24:54.137803 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9587 00:24:54.144288 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9588 00:24:54.148237 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9589 00:24:54.154574 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9590 00:24:54.157533 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9591 00:24:54.164420 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9592 00:24:54.167588 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9593 00:24:54.174496 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9594 00:24:54.177511 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9595 00:24:54.181213 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9596 00:24:54.187553 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9597 00:24:54.190939 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9598 00:24:54.194069 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9599 00:24:54.200725 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9600 00:24:54.204034 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9601 00:24:54.207708 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9602 00:24:54.214693 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9603 00:24:54.217826 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9604 00:24:54.220774 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9605 00:24:54.227083 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9606 00:24:54.230442 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9607 00:24:54.237340 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9608 00:24:54.240805 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9609 00:24:54.244000 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9610 00:24:54.250924 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9611 00:24:54.254084 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9612 00:24:54.260826 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9613 00:24:54.263733 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9614 00:24:54.267605 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9615 00:24:54.273981 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9616 00:24:54.276995 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9617 00:24:54.280498 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9618 00:24:54.287231 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9619 00:24:54.290381 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9620 00:24:54.293793 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9621 00:24:54.300337 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9622 00:24:54.303585 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9623 00:24:54.306921 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9624 00:24:54.310305 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9625 00:24:54.317137 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9626 00:24:54.320130 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9627 00:24:54.326689 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9628 00:24:54.330601 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9629 00:24:54.333974 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9630 00:24:54.340177 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9631 00:24:54.343500 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9632 00:24:54.350381 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9633 00:24:54.353577 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9634 00:24:54.356659 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9635 00:24:54.363554 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9636 00:24:54.366782 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9637 00:24:54.369971 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9638 00:24:54.376729 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9639 00:24:54.379635 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9640 00:24:54.386115 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9641 00:24:54.391140 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9642 00:24:54.396396 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9643 00:24:54.399489 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9644 00:24:54.402938 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9645 00:24:54.409388 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9646 00:24:54.412699 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9647 00:24:54.416010 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9648 00:24:54.423013 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9649 00:24:54.426235 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9650 00:24:54.432593 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9651 00:24:54.436194 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9652 00:24:54.439255 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9653 00:24:54.445779 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9654 00:24:54.449166 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9655 00:24:54.456095 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9656 00:24:54.459309 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9657 00:24:54.462718 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9658 00:24:54.469576 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9659 00:24:54.472557 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9660 00:24:54.478918 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9661 00:24:54.482959 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9662 00:24:54.485828 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9663 00:24:54.492233 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9664 00:24:54.495670 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9665 00:24:54.502704 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9666 00:24:54.505627 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9667 00:24:54.509234 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9668 00:24:54.515318 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9669 00:24:54.519077 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9670 00:24:54.526067 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9671 00:24:54.528416 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9672 00:24:54.532309 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9673 00:24:54.538260 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9674 00:24:54.541957 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9675 00:24:54.548699 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9676 00:24:54.551641 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9677 00:24:54.554918 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9678 00:24:54.561703 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9679 00:24:54.565002 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9680 00:24:54.571728 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9681 00:24:54.575150 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9682 00:24:54.578014 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9683 00:24:54.584612 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9684 00:24:54.588083 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9685 00:24:54.594824 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9686 00:24:54.597687 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9687 00:24:54.601132 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9688 00:24:54.608265 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9689 00:24:54.611133 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9690 00:24:54.617661 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9691 00:24:54.621270 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9692 00:24:54.627397 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9693 00:24:54.630948 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9694 00:24:54.634157 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9695 00:24:54.641029 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9696 00:24:54.644396 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9697 00:24:54.650888 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9698 00:24:54.653889 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9699 00:24:54.657438 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9700 00:24:54.664005 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9701 00:24:54.667331 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9702 00:24:54.674278 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9703 00:24:54.677174 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9704 00:24:54.680765 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9705 00:24:54.687281 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9706 00:24:54.690357 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9707 00:24:54.697422 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9708 00:24:54.700413 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9709 00:24:54.707341 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9710 00:24:54.710301 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9711 00:24:54.713764 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9712 00:24:54.720546 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9713 00:24:54.723293 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9714 00:24:54.730103 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9715 00:24:54.733650 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9716 00:24:54.740394 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9717 00:24:54.743147 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9718 00:24:54.746395 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9719 00:24:54.753409 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9720 00:24:54.756431 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9721 00:24:54.762921 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9722 00:24:54.766264 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9723 00:24:54.773160 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9724 00:24:54.776243 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9725 00:24:54.779806 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9726 00:24:54.786494 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9727 00:24:54.789471 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9728 00:24:54.795918 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9729 00:24:54.799585 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9730 00:24:54.803223 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9731 00:24:54.809450 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9732 00:24:54.812622 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9733 00:24:54.816450 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9734 00:24:54.820056 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9735 00:24:54.825823 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9736 00:24:54.829444 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9737 00:24:54.832497 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9738 00:24:54.839448 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9739 00:24:54.842912 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9740 00:24:54.845653 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9741 00:24:54.852656 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9742 00:24:54.855400 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9743 00:24:54.862224 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9744 00:24:54.865737 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9745 00:24:54.869320 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9746 00:24:54.875944 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9747 00:24:54.878886 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9748 00:24:54.885158 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9749 00:24:54.888324 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9750 00:24:54.891841 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9751 00:24:54.898624 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9752 00:24:54.902736 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9753 00:24:54.905080 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9754 00:24:54.912043 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9755 00:24:54.915670 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9756 00:24:54.921533 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9757 00:24:54.924899 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9758 00:24:54.928166 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9759 00:24:54.934900 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9760 00:24:54.938123 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9761 00:24:54.941440 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9762 00:24:54.948370 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9763 00:24:54.951506 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9764 00:24:54.954902 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9765 00:24:54.961195 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9766 00:24:54.965071 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9767 00:24:54.971036 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9768 00:24:54.974416 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9769 00:24:54.977995 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9770 00:24:54.981399 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9771 00:24:54.987684 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9772 00:24:54.990788 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9773 00:24:54.994310 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9774 00:24:54.997432 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9775 00:24:55.004431 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9776 00:24:55.007658 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9777 00:24:55.010773 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9778 00:24:55.014014 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9779 00:24:55.020760 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9780 00:24:55.023965 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9781 00:24:55.027488 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9782 00:24:55.034171 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9783 00:24:55.037394 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9784 00:24:55.040986 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9785 00:24:55.046923 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9786 00:24:55.050477 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9787 00:24:55.057128 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9788 00:24:55.060990 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9789 00:24:55.067099 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9790 00:24:55.070285 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9791 00:24:55.073936 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9792 00:24:55.080330 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9793 00:24:55.083622 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9794 00:24:55.090271 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9795 00:24:55.093281 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9796 00:24:55.100138 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9797 00:24:55.103141 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9798 00:24:55.106653 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9799 00:24:55.113131 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9800 00:24:55.116736 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9801 00:24:55.123788 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9802 00:24:55.126279 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9803 00:24:55.129504 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9804 00:24:55.136763 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9805 00:24:55.139289 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9806 00:24:55.146085 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9807 00:24:55.149186 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9808 00:24:55.152909 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9809 00:24:55.159242 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9810 00:24:55.163280 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9811 00:24:55.169324 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9812 00:24:55.172867 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9813 00:24:55.179063 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9814 00:24:55.182411 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9815 00:24:55.185608 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9816 00:24:55.193230 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9817 00:24:55.195843 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9818 00:24:55.202493 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9819 00:24:55.206005 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9820 00:24:55.209284 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9821 00:24:55.215440 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9822 00:24:55.219254 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9823 00:24:55.225212 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9824 00:24:55.228474 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9825 00:24:55.235408 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9826 00:24:55.239104 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9827 00:24:55.241976 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9828 00:24:55.249007 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9829 00:24:55.252045 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9830 00:24:55.258766 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9831 00:24:55.261827 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9832 00:24:55.265241 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9833 00:24:55.271621 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9834 00:24:55.275299 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9835 00:24:55.281672 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9836 00:24:55.285087 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9837 00:24:55.291783 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9838 00:24:55.295158 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9839 00:24:55.298846 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9840 00:24:55.304651 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9841 00:24:55.308678 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9842 00:24:55.314555 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9843 00:24:55.317514 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9844 00:24:55.320859 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9845 00:24:55.327343 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9846 00:24:55.331227 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9847 00:24:55.337988 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9848 00:24:55.340959 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9849 00:24:55.347720 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9850 00:24:55.350730 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9851 00:24:55.354017 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9852 00:24:55.360675 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9853 00:24:55.363885 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9854 00:24:55.371145 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9855 00:24:55.373982 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9856 00:24:55.377113 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9857 00:24:55.383729 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9858 00:24:55.386937 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9859 00:24:55.393792 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9860 00:24:55.396931 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9861 00:24:55.403667 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9862 00:24:55.406586 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9863 00:24:55.413523 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9864 00:24:55.416873 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9865 00:24:55.420407 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9866 00:24:55.426518 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9867 00:24:55.430192 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9868 00:24:55.436630 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9869 00:24:55.439891 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9870 00:24:55.446569 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9871 00:24:55.449844 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9872 00:24:55.456694 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9873 00:24:55.459680 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9874 00:24:55.463401 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9875 00:24:55.469813 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9876 00:24:55.473396 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9877 00:24:55.479455 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9878 00:24:55.482601 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9879 00:24:55.489226 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9880 00:24:55.492836 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9881 00:24:55.499284 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9882 00:24:55.502599 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9883 00:24:55.505597 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9884 00:24:55.512383 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9885 00:24:55.515792 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9886 00:24:55.522427 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9887 00:24:55.526281 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9888 00:24:55.532348 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9889 00:24:55.536383 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9890 00:24:55.541933 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9891 00:24:55.545542 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9892 00:24:55.548944 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9893 00:24:55.555431 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9894 00:24:55.558782 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9895 00:24:55.565075 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9896 00:24:55.568321 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9897 00:24:55.575580 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9898 00:24:55.578322 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9899 00:24:55.585036 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9900 00:24:55.588671 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9901 00:24:55.591558 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9902 00:24:55.598117 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9903 00:24:55.601841 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9904 00:24:55.608309 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9905 00:24:55.611735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9906 00:24:55.618358 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9907 00:24:55.621375 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9908 00:24:55.628084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9909 00:24:55.631577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9910 00:24:55.637916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9911 00:24:55.641374 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9912 00:24:55.644902 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9913 00:24:55.650667 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9914 00:24:55.654589 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9915 00:24:55.660795 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9916 00:24:55.664372 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9917 00:24:55.670551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9918 00:24:55.674233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9919 00:24:55.681114 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9920 00:24:55.684093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9921 00:24:55.690523 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9922 00:24:55.693870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9923 00:24:55.700788 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9924 00:24:55.703818 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9925 00:24:55.710427 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9926 00:24:55.713695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9927 00:24:55.720291 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9928 00:24:55.723426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9929 00:24:55.730630 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9930 00:24:55.736809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9931 00:24:55.740005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9932 00:24:55.746616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9933 00:24:55.750363 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9934 00:24:55.756574 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9935 00:24:55.760438 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9936 00:24:55.760517 INFO: [APUAPC] vio 0
9937 00:24:55.767539 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9938 00:24:55.770363 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9939 00:24:55.773703 INFO: [APUAPC] D0_APC_0: 0x400510
9940 00:24:55.776987 INFO: [APUAPC] D0_APC_1: 0x0
9941 00:24:55.780594 INFO: [APUAPC] D0_APC_2: 0x1540
9942 00:24:55.783685 INFO: [APUAPC] D0_APC_3: 0x0
9943 00:24:55.787275 INFO: [APUAPC] D1_APC_0: 0xffffffff
9944 00:24:55.790658 INFO: [APUAPC] D1_APC_1: 0xffffffff
9945 00:24:55.793531 INFO: [APUAPC] D1_APC_2: 0x3fffff
9946 00:24:55.796935 INFO: [APUAPC] D1_APC_3: 0x0
9947 00:24:55.799780 INFO: [APUAPC] D2_APC_0: 0xffffffff
9948 00:24:55.803624 INFO: [APUAPC] D2_APC_1: 0xffffffff
9949 00:24:55.806857 INFO: [APUAPC] D2_APC_2: 0x3fffff
9950 00:24:55.810483 INFO: [APUAPC] D2_APC_3: 0x0
9951 00:24:55.813069 INFO: [APUAPC] D3_APC_0: 0xffffffff
9952 00:24:55.816460 INFO: [APUAPC] D3_APC_1: 0xffffffff
9953 00:24:55.820232 INFO: [APUAPC] D3_APC_2: 0x3fffff
9954 00:24:55.823272 INFO: [APUAPC] D3_APC_3: 0x0
9955 00:24:55.826450 INFO: [APUAPC] D4_APC_0: 0xffffffff
9956 00:24:55.829401 INFO: [APUAPC] D4_APC_1: 0xffffffff
9957 00:24:55.832870 INFO: [APUAPC] D4_APC_2: 0x3fffff
9958 00:24:55.836205 INFO: [APUAPC] D4_APC_3: 0x0
9959 00:24:55.839608 INFO: [APUAPC] D5_APC_0: 0xffffffff
9960 00:24:55.843097 INFO: [APUAPC] D5_APC_1: 0xffffffff
9961 00:24:55.846032 INFO: [APUAPC] D5_APC_2: 0x3fffff
9962 00:24:55.849478 INFO: [APUAPC] D5_APC_3: 0x0
9963 00:24:55.852899 INFO: [APUAPC] D6_APC_0: 0xffffffff
9964 00:24:55.856540 INFO: [APUAPC] D6_APC_1: 0xffffffff
9965 00:24:55.859109 INFO: [APUAPC] D6_APC_2: 0x3fffff
9966 00:24:55.862821 INFO: [APUAPC] D6_APC_3: 0x0
9967 00:24:55.866125 INFO: [APUAPC] D7_APC_0: 0xffffffff
9968 00:24:55.868973 INFO: [APUAPC] D7_APC_1: 0xffffffff
9969 00:24:55.872566 INFO: [APUAPC] D7_APC_2: 0x3fffff
9970 00:24:55.875559 INFO: [APUAPC] D7_APC_3: 0x0
9971 00:24:55.878816 INFO: [APUAPC] D8_APC_0: 0xffffffff
9972 00:24:55.882488 INFO: [APUAPC] D8_APC_1: 0xffffffff
9973 00:24:55.885629 INFO: [APUAPC] D8_APC_2: 0x3fffff
9974 00:24:55.885708 INFO: [APUAPC] D8_APC_3: 0x0
9975 00:24:55.888885 INFO: [APUAPC] D9_APC_0: 0xffffffff
9976 00:24:55.895960 INFO: [APUAPC] D9_APC_1: 0xffffffff
9977 00:24:55.896039 INFO: [APUAPC] D9_APC_2: 0x3fffff
9978 00:24:55.899153 INFO: [APUAPC] D9_APC_3: 0x0
9979 00:24:55.902624 INFO: [APUAPC] D10_APC_0: 0xffffffff
9980 00:24:55.908814 INFO: [APUAPC] D10_APC_1: 0xffffffff
9981 00:24:55.912229 INFO: [APUAPC] D10_APC_2: 0x3fffff
9982 00:24:55.912309 INFO: [APUAPC] D10_APC_3: 0x0
9983 00:24:55.918610 INFO: [APUAPC] D11_APC_0: 0xffffffff
9984 00:24:55.922351 INFO: [APUAPC] D11_APC_1: 0xffffffff
9985 00:24:55.925218 INFO: [APUAPC] D11_APC_2: 0x3fffff
9986 00:24:55.925298 INFO: [APUAPC] D11_APC_3: 0x0
9987 00:24:55.932022 INFO: [APUAPC] D12_APC_0: 0xffffffff
9988 00:24:55.935180 INFO: [APUAPC] D12_APC_1: 0xffffffff
9989 00:24:55.938902 INFO: [APUAPC] D12_APC_2: 0x3fffff
9990 00:24:55.941380 INFO: [APUAPC] D12_APC_3: 0x0
9991 00:24:55.945007 INFO: [APUAPC] D13_APC_0: 0xffffffff
9992 00:24:55.948541 INFO: [APUAPC] D13_APC_1: 0xffffffff
9993 00:24:55.951633 INFO: [APUAPC] D13_APC_2: 0x3fffff
9994 00:24:55.954653 INFO: [APUAPC] D13_APC_3: 0x0
9995 00:24:55.958400 INFO: [APUAPC] D14_APC_0: 0xffffffff
9996 00:24:55.961592 INFO: [APUAPC] D14_APC_1: 0xffffffff
9997 00:24:55.964664 INFO: [APUAPC] D14_APC_2: 0x3fffff
9998 00:24:55.968091 INFO: [APUAPC] D14_APC_3: 0x0
9999 00:24:55.971506 INFO: [APUAPC] D15_APC_0: 0xffffffff
10000 00:24:55.974955 INFO: [APUAPC] D15_APC_1: 0xffffffff
10001 00:24:55.977796 INFO: [APUAPC] D15_APC_2: 0x3fffff
10002 00:24:55.981491 INFO: [APUAPC] D15_APC_3: 0x0
10003 00:24:55.981571 INFO: [APUAPC] APC_CON: 0x4
10004 00:24:55.984999 INFO: [NOCDAPC] D0_APC_0: 0x0
10005 00:24:55.987750 INFO: [NOCDAPC] D0_APC_1: 0x0
10006 00:24:55.991366 INFO: [NOCDAPC] D1_APC_0: 0x0
10007 00:24:55.994754 INFO: [NOCDAPC] D1_APC_1: 0xfff
10008 00:24:55.998225 INFO: [NOCDAPC] D2_APC_0: 0x0
10009 00:24:56.001159 INFO: [NOCDAPC] D2_APC_1: 0xfff
10010 00:24:56.004713 INFO: [NOCDAPC] D3_APC_0: 0x0
10011 00:24:56.007555 INFO: [NOCDAPC] D3_APC_1: 0xfff
10012 00:24:56.011171 INFO: [NOCDAPC] D4_APC_0: 0x0
10013 00:24:56.014390 INFO: [NOCDAPC] D4_APC_1: 0xfff
10014 00:24:56.014471 INFO: [NOCDAPC] D5_APC_0: 0x0
10015 00:24:56.017611 INFO: [NOCDAPC] D5_APC_1: 0xfff
10016 00:24:56.020895 INFO: [NOCDAPC] D6_APC_0: 0x0
10017 00:24:56.024214 INFO: [NOCDAPC] D6_APC_1: 0xfff
10018 00:24:56.027759 INFO: [NOCDAPC] D7_APC_0: 0x0
10019 00:24:56.031031 INFO: [NOCDAPC] D7_APC_1: 0xfff
10020 00:24:56.034099 INFO: [NOCDAPC] D8_APC_0: 0x0
10021 00:24:56.037771 INFO: [NOCDAPC] D8_APC_1: 0xfff
10022 00:24:56.040449 INFO: [NOCDAPC] D9_APC_0: 0x0
10023 00:24:56.044160 INFO: [NOCDAPC] D9_APC_1: 0xfff
10024 00:24:56.047245 INFO: [NOCDAPC] D10_APC_0: 0x0
10025 00:24:56.050381 INFO: [NOCDAPC] D10_APC_1: 0xfff
10026 00:24:56.053636 INFO: [NOCDAPC] D11_APC_0: 0x0
10027 00:24:56.057001 INFO: [NOCDAPC] D11_APC_1: 0xfff
10028 00:24:56.057081 INFO: [NOCDAPC] D12_APC_0: 0x0
10029 00:24:56.060752 INFO: [NOCDAPC] D12_APC_1: 0xfff
10030 00:24:56.064012 INFO: [NOCDAPC] D13_APC_0: 0x0
10031 00:24:56.067230 INFO: [NOCDAPC] D13_APC_1: 0xfff
10032 00:24:56.070161 INFO: [NOCDAPC] D14_APC_0: 0x0
10033 00:24:56.073401 INFO: [NOCDAPC] D14_APC_1: 0xfff
10034 00:24:56.076665 INFO: [NOCDAPC] D15_APC_0: 0x0
10035 00:24:56.080222 INFO: [NOCDAPC] D15_APC_1: 0xfff
10036 00:24:56.084063 INFO: [NOCDAPC] APC_CON: 0x4
10037 00:24:56.086632 INFO: [APUAPC] set_apusys_apc done
10038 00:24:56.089893 INFO: [DEVAPC] devapc_init done
10039 00:24:56.093428 INFO: GICv3 without legacy support detected.
10040 00:24:56.096737 INFO: ARM GICv3 driver initialized in EL3
10041 00:24:56.103058 INFO: Maximum SPI INTID supported: 639
10042 00:24:56.106369 INFO: BL31: Initializing runtime services
10043 00:24:56.113148 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10044 00:24:56.113229 INFO: SPM: enable CPC mode
10045 00:24:56.119874 INFO: mcdi ready for mcusys-off-idle and system suspend
10046 00:24:56.122723 INFO: BL31: Preparing for EL3 exit to normal world
10047 00:24:56.126027 INFO: Entry point address = 0x80000000
10048 00:24:56.129160 INFO: SPSR = 0x8
10049 00:24:56.135298
10050 00:24:56.135377
10051 00:24:56.135439
10052 00:24:56.138462 Starting depthcharge on Spherion...
10053 00:24:56.138542
10054 00:24:56.138610 Wipe memory regions:
10055 00:24:56.138669
10056 00:24:56.139337 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10057 00:24:56.139433 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10058 00:24:56.139514 Setting prompt string to ['asurada:']
10059 00:24:56.139592 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10060 00:24:56.141667 [0x00000040000000, 0x00000054600000)
10061 00:24:56.264274
10062 00:24:56.264391 [0x00000054660000, 0x00000080000000)
10063 00:24:56.524115
10064 00:24:56.524255 [0x000000821a7280, 0x000000ffe64000)
10065 00:24:57.267841
10066 00:24:57.267978 [0x00000100000000, 0x00000240000000)
10067 00:24:59.154342
10068 00:24:59.157342 Initializing XHCI USB controller at 0x11200000.
10069 00:25:00.138929
10070 00:25:00.139070 R8152: Initializing
10071 00:25:00.139137
10072 00:25:00.142292 Version 9 (ocp_data = 6010)
10073 00:25:00.142373
10074 00:25:00.145478 R8152: Done initializing
10075 00:25:00.145558
10076 00:25:00.145621 Adding net device
10077 00:25:00.667422
10078 00:25:00.670762 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10079 00:25:00.670852
10080 00:25:00.670916
10081 00:25:00.670975
10082 00:25:00.671294 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10084 00:25:00.771651 asurada: tftpboot 192.168.201.1 11280966/tftp-deploy-20drlgbp/kernel/image.itb 11280966/tftp-deploy-20drlgbp/kernel/cmdline
10085 00:25:00.771777 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10086 00:25:00.771887 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10087 00:25:00.776259 tftpboot 192.168.201.1 11280966/tftp-deploy-20drlgbp/kernel/image.itp-deploy-20drlgbp/kernel/cmdline
10088 00:25:00.776342
10089 00:25:00.776405 Waiting for link
10090 00:25:00.978498
10091 00:25:00.978661 done.
10092 00:25:00.978730
10093 00:25:00.978789 MAC: f4:f5:e8:50:de:0a
10094 00:25:00.978847
10095 00:25:00.982000 Sending DHCP discover... done.
10096 00:25:00.982081
10097 00:25:00.984856 Waiting for reply... done.
10098 00:25:00.984937
10099 00:25:00.989224 Sending DHCP request... done.
10100 00:25:00.989304
10101 00:25:00.992528 Waiting for reply... done.
10102 00:25:00.992608
10103 00:25:00.992672 My ip is 192.168.201.14
10104 00:25:00.992731
10105 00:25:00.995483 The DHCP server ip is 192.168.201.1
10106 00:25:00.995564
10107 00:25:01.002396 TFTP server IP predefined by user: 192.168.201.1
10108 00:25:01.002477
10109 00:25:01.008747 Bootfile predefined by user: 11280966/tftp-deploy-20drlgbp/kernel/image.itb
10110 00:25:01.008828
10111 00:25:01.012118 Sending tftp read request... done.
10112 00:25:01.012199
10113 00:25:01.015644 Waiting for the transfer...
10114 00:25:01.015724
10115 00:25:01.253750 00000000 ################################################################
10116 00:25:01.253907
10117 00:25:01.487423 00080000 ################################################################
10118 00:25:01.487561
10119 00:25:01.722989 00100000 ################################################################
10120 00:25:01.723124
10121 00:25:01.947740 00180000 ################################################################
10122 00:25:01.947885
10123 00:25:02.185120 00200000 ################################################################
10124 00:25:02.185265
10125 00:25:02.413490 00280000 ################################################################
10126 00:25:02.413636
10127 00:25:02.636507 00300000 ################################################################
10128 00:25:02.636641
10129 00:25:02.869985 00380000 ################################################################
10130 00:25:02.870146
10131 00:25:03.098365 00400000 ################################################################
10132 00:25:03.098513
10133 00:25:03.322925 00480000 ################################################################
10134 00:25:03.323060
10135 00:25:03.552530 00500000 ################################################################
10136 00:25:03.552704
10137 00:25:03.776832 00580000 ################################################################
10138 00:25:03.776976
10139 00:25:04.013914 00600000 ################################################################
10140 00:25:04.014059
10141 00:25:04.236273 00680000 ################################################################
10142 00:25:04.236414
10143 00:25:04.463938 00700000 ################################################################
10144 00:25:04.464085
10145 00:25:04.690850 00780000 ################################################################
10146 00:25:04.690998
10147 00:25:04.922842 00800000 ################################################################
10148 00:25:04.922987
10149 00:25:05.177026 00880000 ################################################################
10150 00:25:05.177162
10151 00:25:05.407492 00900000 ################################################################
10152 00:25:05.407626
10153 00:25:05.634625 00980000 ################################################################
10154 00:25:05.634771
10155 00:25:05.856896 00a00000 ################################################################
10156 00:25:05.857045
10157 00:25:06.080321 00a80000 ################################################################
10158 00:25:06.080462
10159 00:25:06.302427 00b00000 ################################################################
10160 00:25:06.302568
10161 00:25:06.525018 00b80000 ################################################################
10162 00:25:06.525153
10163 00:25:06.749351 00c00000 ################################################################
10164 00:25:06.749488
10165 00:25:06.981007 00c80000 ################################################################
10166 00:25:06.981141
10167 00:25:07.202738 00d00000 ################################################################
10168 00:25:07.202870
10169 00:25:07.425118 00d80000 ################################################################
10170 00:25:07.425246
10171 00:25:07.650522 00e00000 ################################################################
10172 00:25:07.650676
10173 00:25:07.892201 00e80000 ################################################################
10174 00:25:07.892344
10175 00:25:08.117157 00f00000 ################################################################
10176 00:25:08.117301
10177 00:25:08.370745 00f80000 ################################################################
10178 00:25:08.370885
10179 00:25:08.614893 01000000 ################################################################
10180 00:25:08.615029
10181 00:25:08.847392 01080000 ################################################################
10182 00:25:08.847527
10183 00:25:09.081283 01100000 ################################################################
10184 00:25:09.081414
10185 00:25:09.305519 01180000 ################################################################
10186 00:25:09.305651
10187 00:25:09.541923 01200000 ################################################################
10188 00:25:09.542064
10189 00:25:09.792996 01280000 ################################################################
10190 00:25:09.793137
10191 00:25:10.047083 01300000 ################################################################
10192 00:25:10.047223
10193 00:25:10.302587 01380000 ################################################################
10194 00:25:10.302759
10195 00:25:10.531865 01400000 ################################################################
10196 00:25:10.532001
10197 00:25:10.761991 01480000 ################################################################
10198 00:25:10.762124
10199 00:25:11.014969 01500000 ################################################################
10200 00:25:11.015111
10201 00:25:11.250364 01580000 ################################################################
10202 00:25:11.250497
10203 00:25:11.494143 01600000 ################################################################
10204 00:25:11.494298
10205 00:25:11.721606 01680000 ################################################################
10206 00:25:11.721753
10207 00:25:11.956343 01700000 ################################################################
10208 00:25:11.956475
10209 00:25:12.186443 01780000 ################################################################
10210 00:25:12.186604
10211 00:25:12.418504 01800000 ################################################################
10212 00:25:12.418677
10213 00:25:12.655578 01880000 ################################################################
10214 00:25:12.655706
10215 00:25:12.899101 01900000 ################################################################
10216 00:25:12.899238
10217 00:25:13.132468 01980000 ################################################################
10218 00:25:13.132627
10219 00:25:13.382938 01a00000 ################################################################
10220 00:25:13.383070
10221 00:25:13.622065 01a80000 ################################################################
10222 00:25:13.622224
10223 00:25:13.875851 01b00000 ################################################################
10224 00:25:13.875983
10225 00:25:14.115777 01b80000 ################################################################
10226 00:25:14.115921
10227 00:25:14.354719 01c00000 ################################################################
10228 00:25:14.354843
10229 00:25:14.583690 01c80000 ################################################################
10230 00:25:14.583822
10231 00:25:14.842343 01d00000 ################################################################
10232 00:25:14.842495
10233 00:25:15.069065 01d80000 ################################################################
10234 00:25:15.069197
10235 00:25:15.330291 01e00000 ################################################################
10236 00:25:15.330418
10237 00:25:15.595400 01e80000 ################################################################
10238 00:25:15.595549
10239 00:25:15.849798 01f00000 ################################################################
10240 00:25:15.849924
10241 00:25:16.117517 01f80000 ################################################################
10242 00:25:16.117671
10243 00:25:16.375364 02000000 ################################################################
10244 00:25:16.375507
10245 00:25:16.605524 02080000 ################################################################
10246 00:25:16.605661
10247 00:25:16.834722 02100000 ################################################################
10248 00:25:16.834854
10249 00:25:17.083172 02180000 ################################################################
10250 00:25:17.083313
10251 00:25:17.330536 02200000 ################################################################
10252 00:25:17.330686
10253 00:25:17.600332 02280000 ################################################################
10254 00:25:17.600475
10255 00:25:17.872047 02300000 ################################################################
10256 00:25:17.872182
10257 00:25:18.142236 02380000 ################################################################
10258 00:25:18.142378
10259 00:25:18.408324 02400000 ################################################################
10260 00:25:18.408467
10261 00:25:18.680333 02480000 ################################################################
10262 00:25:18.680473
10263 00:25:18.950468 02500000 ################################################################
10264 00:25:18.950610
10265 00:25:19.212056 02580000 ################################################################
10266 00:25:19.212207
10267 00:25:19.480022 02600000 ################################################################
10268 00:25:19.480160
10269 00:25:19.742612 02680000 ################################################################
10270 00:25:19.742757
10271 00:25:19.996967 02700000 ################################################################
10272 00:25:19.997105
10273 00:25:20.264723 02780000 ################################################################
10274 00:25:20.264854
10275 00:25:20.534773 02800000 ################################################################
10276 00:25:20.534993
10277 00:25:20.779251 02880000 ################################################################
10278 00:25:20.779386
10279 00:25:21.049072 02900000 ################################################################
10280 00:25:21.049208
10281 00:25:21.319126 02980000 ################################################################
10282 00:25:21.319270
10283 00:25:21.591845 02a00000 ################################################################
10284 00:25:21.591986
10285 00:25:21.821611 02a80000 ################################################################
10286 00:25:21.821741
10287 00:25:22.062567 02b00000 ################################################################
10288 00:25:22.062702
10289 00:25:22.293033 02b80000 ################################################################
10290 00:25:22.293170
10291 00:25:22.532818 02c00000 ################################################################
10292 00:25:22.532958
10293 00:25:22.760195 02c80000 ################################################################
10294 00:25:22.760331
10295 00:25:22.997559 02d00000 ################################################################
10296 00:25:22.997690
10297 00:25:23.240716 02d80000 ################################################################
10298 00:25:23.240853
10299 00:25:23.510120 02e00000 ################################################################
10300 00:25:23.510255
10301 00:25:23.783597 02e80000 ################################################################
10302 00:25:23.783731
10303 00:25:24.040035 02f00000 ################################################################
10304 00:25:24.040170
10305 00:25:24.274975 02f80000 ################################################################ done.
10306 00:25:24.275101
10307 00:25:24.278432 The bootfile was 50331194 bytes long.
10308 00:25:24.278610
10309 00:25:24.281739 Sending tftp read request... done.
10310 00:25:24.281845
10311 00:25:24.281917 Waiting for the transfer...
10312 00:25:24.281985
10313 00:25:24.285358 00000000 # done.
10314 00:25:24.285524
10315 00:25:24.291321 Command line loaded dynamically from TFTP file: 11280966/tftp-deploy-20drlgbp/kernel/cmdline
10316 00:25:24.291499
10317 00:25:24.304633 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10318 00:25:24.307788
10319 00:25:24.307934 Loading FIT.
10320 00:25:24.308049
10321 00:25:24.311296 Image ramdisk-1 has 39244568 bytes.
10322 00:25:24.311550
10323 00:25:24.315197 Image fdt-1 has 47278 bytes.
10324 00:25:24.315448
10325 00:25:24.318058 Image kernel-1 has 11037315 bytes.
10326 00:25:24.318340
10327 00:25:24.324549 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10328 00:25:24.324894
10329 00:25:24.344497 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10330 00:25:24.345109
10331 00:25:24.348565 Choosing best match conf-1 for compat google,spherion-rev2.
10332 00:25:24.352944
10333 00:25:24.357369 Connected to device vid:did:rid of 1ae0:0028:00
10334 00:25:24.364212
10335 00:25:24.368149 tpm_get_response: command 0x17b, return code 0x0
10336 00:25:24.368713
10337 00:25:24.370570 ec_init: CrosEC protocol v3 supported (256, 248)
10338 00:25:24.375288
10339 00:25:24.378015 tpm_cleanup: add release locality here.
10340 00:25:24.378472
10341 00:25:24.378878 Shutting down all USB controllers.
10342 00:25:24.381946
10343 00:25:24.382496 Removing current net device
10344 00:25:24.382900
10345 00:25:24.387845 Exiting depthcharge with code 4 at timestamp: 57656256
10346 00:25:24.388301
10347 00:25:24.391563 LZMA decompressing kernel-1 to 0x821a6718
10348 00:25:24.392126
10349 00:25:24.395221 LZMA decompressing kernel-1 to 0x40000000
10350 00:25:25.783724
10351 00:25:25.784272 jumping to kernel
10352 00:25:25.785792 end: 2.2.4 bootloader-commands (duration 00:00:30) [common]
10353 00:25:25.786301 start: 2.2.5 auto-login-action (timeout 00:03:55) [common]
10354 00:25:25.786738 Setting prompt string to ['Linux version [0-9]']
10355 00:25:25.787107 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10356 00:25:25.787469 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10357 00:25:25.865370
10358 00:25:25.868527 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10359 00:25:25.872114 start: 2.2.5.1 login-action (timeout 00:03:55) [common]
10360 00:25:25.872717 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10361 00:25:25.873183 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10362 00:25:25.873593 Using line separator: #'\n'#
10363 00:25:25.873930 No login prompt set.
10364 00:25:25.874273 Parsing kernel messages
10365 00:25:25.874581 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10366 00:25:25.875255 [login-action] Waiting for messages, (timeout 00:03:55)
10367 00:25:25.891519 [ 0.000000] Linux version 6.1.45-cip3 (KernelCI@build-j12530-arm64-gcc-10-defconfig-arm64-chromebook-5rwxg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Aug 14 00:09:07 UTC 2023
10368 00:25:25.894678 [ 0.000000] random: crng init done
10369 00:25:25.901121 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10370 00:25:25.904910 [ 0.000000] efi: UEFI not found.
10371 00:25:25.910986 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10372 00:25:25.917906 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10373 00:25:25.927770 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10374 00:25:25.938114 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10375 00:25:25.943926 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10376 00:25:25.950823 [ 0.000000] printk: bootconsole [mtk8250] enabled
10377 00:25:25.957602 [ 0.000000] NUMA: No NUMA configuration found
10378 00:25:25.964094 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10379 00:25:25.967628 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10380 00:25:25.970862 [ 0.000000] Zone ranges:
10381 00:25:25.977768 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10382 00:25:25.980887 [ 0.000000] DMA32 empty
10383 00:25:25.987887 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10384 00:25:25.990356 [ 0.000000] Movable zone start for each node
10385 00:25:25.993914 [ 0.000000] Early memory node ranges
10386 00:25:26.000552 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10387 00:25:26.007193 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10388 00:25:26.013941 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10389 00:25:26.020236 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10390 00:25:26.026749 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10391 00:25:26.033069 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10392 00:25:26.089828 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10393 00:25:26.096520 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10394 00:25:26.102820 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10395 00:25:26.106206 [ 0.000000] psci: probing for conduit method from DT.
10396 00:25:26.112177 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10397 00:25:26.115586 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10398 00:25:26.122231 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10399 00:25:26.125466 [ 0.000000] psci: SMC Calling Convention v1.2
10400 00:25:26.131880 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10401 00:25:26.135596 [ 0.000000] Detected VIPT I-cache on CPU0
10402 00:25:26.142023 [ 0.000000] CPU features: detected: GIC system register CPU interface
10403 00:25:26.148933 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10404 00:25:26.154987 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10405 00:25:26.162054 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10406 00:25:26.172359 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10407 00:25:26.178978 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10408 00:25:26.182009 [ 0.000000] alternatives: applying boot alternatives
10409 00:25:26.188711 [ 0.000000] Fallback order for Node 0: 0
10410 00:25:26.195823 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10411 00:25:26.198887 [ 0.000000] Policy zone: Normal
10412 00:25:26.211309 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10413 00:25:26.221394 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10414 00:25:26.233751 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10415 00:25:26.243158 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10416 00:25:26.249978 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10417 00:25:26.253358 <6>[ 0.000000] software IO TLB: area num 8.
10418 00:25:26.309985 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10419 00:25:26.459217 <6>[ 0.000000] Memory: 7931232K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 421536K reserved, 32768K cma-reserved)
10420 00:25:26.465730 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10421 00:25:26.472746 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10422 00:25:26.475202 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10423 00:25:26.482174 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10424 00:25:26.488592 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10425 00:25:26.491901 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10426 00:25:26.501695 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10427 00:25:26.508654 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10428 00:25:26.514863 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10429 00:25:26.521960 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10430 00:25:26.524578 <6>[ 0.000000] GICv3: 608 SPIs implemented
10431 00:25:26.527733 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10432 00:25:26.535194 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10433 00:25:26.538013 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10434 00:25:26.544799 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10435 00:25:26.558459 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10436 00:25:26.570952 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10437 00:25:26.577845 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10438 00:25:26.586169 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10439 00:25:26.598851 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10440 00:25:26.605308 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10441 00:25:26.612235 <6>[ 0.009184] Console: colour dummy device 80x25
10442 00:25:26.621983 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10443 00:25:26.629217 <6>[ 0.024344] pid_max: default: 32768 minimum: 301
10444 00:25:26.632005 <6>[ 0.029215] LSM: Security Framework initializing
10445 00:25:26.639312 <6>[ 0.034153] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10446 00:25:26.648714 <6>[ 0.041967] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10447 00:25:26.658307 <6>[ 0.051397] cblist_init_generic: Setting adjustable number of callback queues.
10448 00:25:26.662386 <6>[ 0.058843] cblist_init_generic: Setting shift to 3 and lim to 1.
10449 00:25:26.671310 <6>[ 0.065219] cblist_init_generic: Setting adjustable number of callback queues.
10450 00:25:26.678431 <6>[ 0.072691] cblist_init_generic: Setting shift to 3 and lim to 1.
10451 00:25:26.681098 <6>[ 0.079090] rcu: Hierarchical SRCU implementation.
10452 00:25:26.687990 <6>[ 0.084103] rcu: Max phase no-delay instances is 1000.
10453 00:25:26.694772 <6>[ 0.091168] EFI services will not be available.
10454 00:25:26.697921 <6>[ 0.096164] smp: Bringing up secondary CPUs ...
10455 00:25:26.706448 <6>[ 0.101216] Detected VIPT I-cache on CPU1
10456 00:25:26.713205 <6>[ 0.101286] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10457 00:25:26.719699 <6>[ 0.101315] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10458 00:25:26.723357 <6>[ 0.101652] Detected VIPT I-cache on CPU2
10459 00:25:26.732732 <6>[ 0.101702] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10460 00:25:26.739455 <6>[ 0.101718] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10461 00:25:26.742960 <6>[ 0.101978] Detected VIPT I-cache on CPU3
10462 00:25:26.749527 <6>[ 0.102025] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10463 00:25:26.756196 <6>[ 0.102039] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10464 00:25:26.762384 <6>[ 0.102344] CPU features: detected: Spectre-v4
10465 00:25:26.765865 <6>[ 0.102350] CPU features: detected: Spectre-BHB
10466 00:25:26.769169 <6>[ 0.102355] Detected PIPT I-cache on CPU4
10467 00:25:26.776114 <6>[ 0.102411] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10468 00:25:26.782361 <6>[ 0.102428] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10469 00:25:26.789036 <6>[ 0.102720] Detected PIPT I-cache on CPU5
10470 00:25:26.795561 <6>[ 0.102781] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10471 00:25:26.802281 <6>[ 0.102798] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10472 00:25:26.805708 <6>[ 0.103082] Detected PIPT I-cache on CPU6
10473 00:25:26.811770 <6>[ 0.103147] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10474 00:25:26.822404 <6>[ 0.103164] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10475 00:25:26.825099 <6>[ 0.103466] Detected PIPT I-cache on CPU7
10476 00:25:26.832028 <6>[ 0.103530] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10477 00:25:26.838900 <6>[ 0.103547] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10478 00:25:26.842126 <6>[ 0.103595] smp: Brought up 1 node, 8 CPUs
10479 00:25:26.848453 <6>[ 0.244841] SMP: Total of 8 processors activated.
10480 00:25:26.851870 <6>[ 0.249763] CPU features: detected: 32-bit EL0 Support
10481 00:25:26.861606 <6>[ 0.255159] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10482 00:25:26.867998 <6>[ 0.264014] CPU features: detected: Common not Private translations
10483 00:25:26.874946 <6>[ 0.270490] CPU features: detected: CRC32 instructions
10484 00:25:26.881499 <6>[ 0.275842] CPU features: detected: RCpc load-acquire (LDAPR)
10485 00:25:26.884811 <6>[ 0.281802] CPU features: detected: LSE atomic instructions
10486 00:25:26.891754 <6>[ 0.287619] CPU features: detected: Privileged Access Never
10487 00:25:26.897644 <6>[ 0.293399] CPU features: detected: RAS Extension Support
10488 00:25:26.904364 <6>[ 0.299043] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10489 00:25:26.907504 <6>[ 0.306262] CPU: All CPU(s) started at EL2
10490 00:25:26.914281 <6>[ 0.310579] alternatives: applying system-wide alternatives
10491 00:25:26.924231 <6>[ 0.321293] devtmpfs: initialized
10492 00:25:26.940099 <6>[ 0.330285] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10493 00:25:26.946291 <6>[ 0.340245] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10494 00:25:26.953358 <6>[ 0.348251] pinctrl core: initialized pinctrl subsystem
10495 00:25:26.956678 <6>[ 0.354926] DMI not present or invalid.
10496 00:25:26.963357 <6>[ 0.359337] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10497 00:25:26.973018 <6>[ 0.366119] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10498 00:25:26.979448 <6>[ 0.373699] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10499 00:25:26.989472 <6>[ 0.381911] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10500 00:25:26.992855 <6>[ 0.390154] audit: initializing netlink subsys (disabled)
10501 00:25:27.002712 <5>[ 0.395849] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10502 00:25:27.008696 <6>[ 0.396569] thermal_sys: Registered thermal governor 'step_wise'
10503 00:25:27.015310 <6>[ 0.403818] thermal_sys: Registered thermal governor 'power_allocator'
10504 00:25:27.018855 <6>[ 0.410074] cpuidle: using governor menu
10505 00:25:27.025808 <6>[ 0.421036] NET: Registered PF_QIPCRTR protocol family
10506 00:25:27.031761 <6>[ 0.426517] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10507 00:25:27.038503 <6>[ 0.433625] ASID allocator initialised with 32768 entries
10508 00:25:27.041655 <6>[ 0.440211] Serial: AMBA PL011 UART driver
10509 00:25:27.051891 <4>[ 0.449028] Trying to register duplicate clock ID: 134
10510 00:25:27.106515 <6>[ 0.506556] KASLR enabled
10511 00:25:27.120635 <6>[ 0.514360] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10512 00:25:27.128011 <6>[ 0.521373] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10513 00:25:27.134399 <6>[ 0.527861] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10514 00:25:27.140638 <6>[ 0.534868] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10515 00:25:27.147255 <6>[ 0.541356] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10516 00:25:27.153915 <6>[ 0.548360] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10517 00:25:27.160562 <6>[ 0.554847] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10518 00:25:27.166741 <6>[ 0.561849] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10519 00:25:27.170180 <6>[ 0.569354] ACPI: Interpreter disabled.
10520 00:25:27.178515 <6>[ 0.575756] iommu: Default domain type: Translated
10521 00:25:27.185596 <6>[ 0.580867] iommu: DMA domain TLB invalidation policy: strict mode
10522 00:25:27.188636 <5>[ 0.587523] SCSI subsystem initialized
10523 00:25:27.195106 <6>[ 0.591690] usbcore: registered new interface driver usbfs
10524 00:25:27.201770 <6>[ 0.597419] usbcore: registered new interface driver hub
10525 00:25:27.205074 <6>[ 0.602972] usbcore: registered new device driver usb
10526 00:25:27.211537 <6>[ 0.609069] pps_core: LinuxPPS API ver. 1 registered
10527 00:25:27.221919 <6>[ 0.614262] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10528 00:25:27.225038 <6>[ 0.623611] PTP clock support registered
10529 00:25:27.228314 <6>[ 0.627854] EDAC MC: Ver: 3.0.0
10530 00:25:27.235839 <6>[ 0.633009] FPGA manager framework
10531 00:25:27.242959 <6>[ 0.636688] Advanced Linux Sound Architecture Driver Initialized.
10532 00:25:27.246124 <6>[ 0.643465] vgaarb: loaded
10533 00:25:27.252731 <6>[ 0.646646] clocksource: Switched to clocksource arch_sys_counter
10534 00:25:27.255735 <5>[ 0.653085] VFS: Disk quotas dquot_6.6.0
10535 00:25:27.262345 <6>[ 0.657272] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10536 00:25:27.265924 <6>[ 0.664464] pnp: PnP ACPI: disabled
10537 00:25:27.274285 <6>[ 0.671143] NET: Registered PF_INET protocol family
10538 00:25:27.284261 <6>[ 0.676730] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10539 00:25:27.295207 <6>[ 0.689018] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10540 00:25:27.305778 <6>[ 0.697832] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10541 00:25:27.311739 <6>[ 0.705803] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10542 00:25:27.318525 <6>[ 0.714499] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10543 00:25:27.331005 <6>[ 0.724244] TCP: Hash tables configured (established 65536 bind 65536)
10544 00:25:27.337229 <6>[ 0.731104] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10545 00:25:27.343797 <6>[ 0.738303] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10546 00:25:27.350047 <6>[ 0.746007] NET: Registered PF_UNIX/PF_LOCAL protocol family
10547 00:25:27.356982 <6>[ 0.752176] RPC: Registered named UNIX socket transport module.
10548 00:25:27.360110 <6>[ 0.758328] RPC: Registered udp transport module.
10549 00:25:27.367313 <6>[ 0.763262] RPC: Registered tcp transport module.
10550 00:25:27.373306 <6>[ 0.768192] RPC: Registered tcp NFSv4.1 backchannel transport module.
10551 00:25:27.377328 <6>[ 0.774862] PCI: CLS 0 bytes, default 64
10552 00:25:27.380157 <6>[ 0.779256] Unpacking initramfs...
10553 00:25:27.397453 <6>[ 0.791264] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10554 00:25:27.407664 <6>[ 0.799936] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10555 00:25:27.410262 <6>[ 0.808798] kvm [1]: IPA Size Limit: 40 bits
10556 00:25:27.417174 <6>[ 0.813330] kvm [1]: GICv3: no GICV resource entry
10557 00:25:27.420050 <6>[ 0.818353] kvm [1]: disabling GICv2 emulation
10558 00:25:27.427171 <6>[ 0.823041] kvm [1]: GIC system register CPU interface enabled
10559 00:25:27.433615 <6>[ 0.830721] kvm [1]: vgic interrupt IRQ18
10560 00:25:27.437150 <6>[ 0.835089] kvm [1]: VHE mode initialized successfully
10561 00:25:27.444812 <5>[ 0.841473] Initialise system trusted keyrings
10562 00:25:27.450942 <6>[ 0.846278] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10563 00:25:27.459557 <6>[ 0.856293] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10564 00:25:27.466103 <5>[ 0.862699] NFS: Registering the id_resolver key type
10565 00:25:27.469189 <5>[ 0.868003] Key type id_resolver registered
10566 00:25:27.475898 <5>[ 0.872417] Key type id_legacy registered
10567 00:25:27.482586 <6>[ 0.876696] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10568 00:25:27.489546 <6>[ 0.883622] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10569 00:25:27.495592 <6>[ 0.891326] 9p: Installing v9fs 9p2000 file system support
10570 00:25:27.531685 <5>[ 0.928494] Key type asymmetric registered
10571 00:25:27.534636 <5>[ 0.932823] Asymmetric key parser 'x509' registered
10572 00:25:27.545171 <6>[ 0.937963] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10573 00:25:27.548067 <6>[ 0.945584] io scheduler mq-deadline registered
10574 00:25:27.551210 <6>[ 0.950358] io scheduler kyber registered
10575 00:25:27.570781 <6>[ 0.967352] EINJ: ACPI disabled.
10576 00:25:27.602420 <4>[ 0.992741] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10577 00:25:27.612171 <4>[ 1.003362] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10578 00:25:27.627131 <6>[ 1.023893] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10579 00:25:27.635604 <6>[ 1.032007] printk: console [ttyS0] disabled
10580 00:25:27.662908 <6>[ 1.056653] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10581 00:25:27.669626 <6>[ 1.066138] printk: console [ttyS0] enabled
10582 00:25:27.673566 <6>[ 1.066138] printk: console [ttyS0] enabled
10583 00:25:27.679257 <6>[ 1.075037] printk: bootconsole [mtk8250] disabled
10584 00:25:27.682675 <6>[ 1.075037] printk: bootconsole [mtk8250] disabled
10585 00:25:27.689370 <6>[ 1.086298] SuperH (H)SCI(F) driver initialized
10586 00:25:27.692565 <6>[ 1.091575] msm_serial: driver initialized
10587 00:25:27.707004 <6>[ 1.100612] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10588 00:25:27.716324 <6>[ 1.109160] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10589 00:25:27.722919 <6>[ 1.117701] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10590 00:25:27.733403 <6>[ 1.126330] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10591 00:25:27.742994 <6>[ 1.135037] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10592 00:25:27.749535 <6>[ 1.143749] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10593 00:25:27.759096 <6>[ 1.152289] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10594 00:25:27.769057 <6>[ 1.161102] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10595 00:25:27.775816 <6>[ 1.169647] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10596 00:25:27.788703 <6>[ 1.185405] loop: module loaded
10597 00:25:27.794769 <6>[ 1.191526] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10598 00:25:27.817772 <4>[ 1.214904] mtk-pmic-keys: Failed to locate of_node [id: -1]
10599 00:25:27.824323 <6>[ 1.221753] megasas: 07.719.03.00-rc1
10600 00:25:27.834367 <6>[ 1.231408] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10601 00:25:27.844985 <6>[ 1.242026] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10602 00:25:27.861892 <6>[ 1.258573] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10603 00:25:27.922077 <6>[ 1.312704] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10604 00:25:28.958455 <6>[ 2.355953] Freeing initrd memory: 38320K
10605 00:25:28.968792 <6>[ 2.366214] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10606 00:25:28.979918 <6>[ 2.377034] tun: Universal TUN/TAP device driver, 1.6
10607 00:25:28.983188 <6>[ 2.383098] thunder_xcv, ver 1.0
10608 00:25:28.986379 <6>[ 2.386593] thunder_bgx, ver 1.0
10609 00:25:28.989978 <6>[ 2.390094] nicpf, ver 1.0
10610 00:25:29.000286 <6>[ 2.394109] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10611 00:25:29.003078 <6>[ 2.401584] hns3: Copyright (c) 2017 Huawei Corporation.
10612 00:25:29.010438 <6>[ 2.407177] hclge is initializing
10613 00:25:29.013486 <6>[ 2.410752] e1000: Intel(R) PRO/1000 Network Driver
10614 00:25:29.020018 <6>[ 2.415881] e1000: Copyright (c) 1999-2006 Intel Corporation.
10615 00:25:29.023652 <6>[ 2.421893] e1000e: Intel(R) PRO/1000 Network Driver
10616 00:25:29.030154 <6>[ 2.427108] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10617 00:25:29.036700 <6>[ 2.433292] igb: Intel(R) Gigabit Ethernet Network Driver
10618 00:25:29.043082 <6>[ 2.438942] igb: Copyright (c) 2007-2014 Intel Corporation.
10619 00:25:29.050182 <6>[ 2.444778] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10620 00:25:29.056815 <6>[ 2.451296] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10621 00:25:29.059953 <6>[ 2.457763] sky2: driver version 1.30
10622 00:25:29.066051 <6>[ 2.462763] VFIO - User Level meta-driver version: 0.3
10623 00:25:29.074173 <6>[ 2.471047] usbcore: registered new interface driver usb-storage
10624 00:25:29.080128 <6>[ 2.477485] usbcore: registered new device driver onboard-usb-hub
10625 00:25:29.089481 <6>[ 2.486583] mt6397-rtc mt6359-rtc: registered as rtc0
10626 00:25:29.098885 <6>[ 2.492051] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-14T00:25:29 UTC (1691972729)
10627 00:25:29.103048 <6>[ 2.501619] i2c_dev: i2c /dev entries driver
10628 00:25:29.119212 <6>[ 2.513414] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10629 00:25:29.139032 <6>[ 2.536409] cpu cpu0: EM: created perf domain
10630 00:25:29.142742 <6>[ 2.541454] cpu cpu4: EM: created perf domain
10631 00:25:29.149955 <6>[ 2.547093] sdhci: Secure Digital Host Controller Interface driver
10632 00:25:29.156723 <6>[ 2.553525] sdhci: Copyright(c) Pierre Ossman
10633 00:25:29.163464 <6>[ 2.558483] Synopsys Designware Multimedia Card Interface Driver
10634 00:25:29.170272 <6>[ 2.565140] sdhci-pltfm: SDHCI platform and OF driver helper
10635 00:25:29.173039 <6>[ 2.565197] mmc0: CQHCI version 5.10
10636 00:25:29.180360 <6>[ 2.575416] ledtrig-cpu: registered to indicate activity on CPUs
10637 00:25:29.186271 <6>[ 2.582474] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10638 00:25:29.193064 <6>[ 2.589552] usbcore: registered new interface driver usbhid
10639 00:25:29.196493 <6>[ 2.595375] usbhid: USB HID core driver
10640 00:25:29.203359 <6>[ 2.599564] spi_master spi0: will run message pump with realtime priority
10641 00:25:29.249938 <6>[ 2.640905] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10642 00:25:29.269467 <6>[ 2.656429] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10643 00:25:29.273392 <6>[ 2.670432] mmc0: Command Queue Engine enabled
10644 00:25:29.279562 <6>[ 2.675174] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10645 00:25:29.286326 <6>[ 2.681929] cros-ec-spi spi0.0: Chrome EC device registered
10646 00:25:29.289752 <6>[ 2.682385] mmcblk0: mmc0:0001 DA4128 116 GiB
10647 00:25:29.300693 <6>[ 2.697764] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10648 00:25:29.307830 <6>[ 2.705074] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10649 00:25:29.314842 <6>[ 2.711167] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10650 00:25:29.324120 <6>[ 2.715799] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10651 00:25:29.330583 <6>[ 2.717093] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10652 00:25:29.334124 <6>[ 2.727010] NET: Registered PF_PACKET protocol family
10653 00:25:29.340915 <6>[ 2.737613] 9pnet: Installing 9P2000 support
10654 00:25:29.344038 <5>[ 2.742183] Key type dns_resolver registered
10655 00:25:29.350657 <6>[ 2.747154] registered taskstats version 1
10656 00:25:29.353611 <5>[ 2.751547] Loading compiled-in X.509 certificates
10657 00:25:29.384592 <4>[ 2.775129] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10658 00:25:29.394205 <4>[ 2.785877] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10659 00:25:29.401751 <3>[ 2.796458] debugfs: File 'uA_load' in directory '/' already present!
10660 00:25:29.407490 <3>[ 2.803172] debugfs: File 'min_uV' in directory '/' already present!
10661 00:25:29.414453 <3>[ 2.809784] debugfs: File 'max_uV' in directory '/' already present!
10662 00:25:29.420553 <3>[ 2.816396] debugfs: File 'constraint_flags' in directory '/' already present!
10663 00:25:29.432145 <3>[ 2.826038] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10664 00:25:29.442070 <6>[ 2.839441] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10665 00:25:29.449117 <6>[ 2.846161] xhci-mtk 11200000.usb: xHCI Host Controller
10666 00:25:29.455278 <6>[ 2.851665] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10667 00:25:29.465298 <6>[ 2.859504] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10668 00:25:29.472441 <6>[ 2.868927] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10669 00:25:29.478939 <6>[ 2.874994] xhci-mtk 11200000.usb: xHCI Host Controller
10670 00:25:29.485225 <6>[ 2.880468] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10671 00:25:29.491940 <6>[ 2.888113] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10672 00:25:29.498399 <6>[ 2.895797] hub 1-0:1.0: USB hub found
10673 00:25:29.502234 <6>[ 2.899813] hub 1-0:1.0: 1 port detected
10674 00:25:29.511540 <6>[ 2.904073] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10675 00:25:29.514737 <6>[ 2.912623] hub 2-0:1.0: USB hub found
10676 00:25:29.517923 <6>[ 2.916626] hub 2-0:1.0: 1 port detected
10677 00:25:29.527777 <6>[ 2.924960] mtk-msdc 11f70000.mmc: Got CD GPIO
10678 00:25:29.537414 <6>[ 2.931394] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10679 00:25:29.544128 <6>[ 2.939416] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10680 00:25:29.554038 <4>[ 2.947312] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10681 00:25:29.564474 <6>[ 2.956836] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10682 00:25:29.571451 <6>[ 2.964913] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10683 00:25:29.577063 <6>[ 2.972913] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10684 00:25:29.587177 <6>[ 2.980835] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10685 00:25:29.594221 <6>[ 2.988651] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10686 00:25:29.603274 <6>[ 2.996468] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10687 00:25:29.613839 <6>[ 3.007025] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10688 00:25:29.620080 <6>[ 3.015383] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10689 00:25:29.630484 <6>[ 3.023721] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10690 00:25:29.636450 <6>[ 3.032059] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10691 00:25:29.646757 <6>[ 3.040397] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10692 00:25:29.653439 <6>[ 3.048735] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10693 00:25:29.662773 <6>[ 3.057073] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10694 00:25:29.673386 <6>[ 3.065411] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10695 00:25:29.679532 <6>[ 3.073749] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10696 00:25:29.689431 <6>[ 3.082087] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10697 00:25:29.695905 <6>[ 3.090424] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10698 00:25:29.706130 <6>[ 3.098766] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10699 00:25:29.712504 <6>[ 3.107105] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10700 00:25:29.722431 <6>[ 3.115442] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10701 00:25:29.728743 <6>[ 3.123780] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10702 00:25:29.735361 <6>[ 3.132587] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10703 00:25:29.742298 <6>[ 3.139795] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10704 00:25:29.749353 <6>[ 3.146574] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10705 00:25:29.759538 <6>[ 3.153342] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10706 00:25:29.766357 <6>[ 3.160279] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10707 00:25:29.772746 <6>[ 3.167139] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10708 00:25:29.782320 <6>[ 3.176272] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10709 00:25:29.792385 <6>[ 3.185392] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10710 00:25:29.802631 <6>[ 3.194688] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10711 00:25:29.811932 <6>[ 3.204157] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10712 00:25:29.822162 <6>[ 3.213626] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10713 00:25:29.828594 <6>[ 3.222746] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10714 00:25:29.838281 <6>[ 3.232213] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10715 00:25:29.848569 <6>[ 3.241333] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10716 00:25:29.858269 <6>[ 3.250637] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10717 00:25:29.868402 <6>[ 3.260797] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10718 00:25:29.878840 <6>[ 3.272786] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10719 00:25:29.909408 <6>[ 3.303231] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10720 00:25:29.936923 <6>[ 3.334506] hub 2-1:1.0: USB hub found
10721 00:25:29.940820 <6>[ 3.338980] hub 2-1:1.0: 3 ports detected
10722 00:25:30.060855 <6>[ 3.454853] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10723 00:25:30.215556 <6>[ 3.613004] hub 1-1:1.0: USB hub found
10724 00:25:30.218566 <6>[ 3.617463] hub 1-1:1.0: 4 ports detected
10725 00:25:30.540584 <6>[ 3.935056] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10726 00:25:30.671823 <6>[ 4.069256] hub 1-1.1:1.0: USB hub found
10727 00:25:30.675488 <6>[ 4.073611] hub 1-1.1:1.0: 4 ports detected
10728 00:25:30.789126 <6>[ 4.183013] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10729 00:25:30.920986 <6>[ 4.318486] hub 1-1.4:1.0: USB hub found
10730 00:25:30.924576 <6>[ 4.323144] hub 1-1.4:1.0: 2 ports detected
10731 00:25:31.001295 <6>[ 4.394958] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10732 00:25:31.184598 <6>[ 4.578958] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10733 00:25:31.270079 <3>[ 4.666999] usb 1-1.1.4: device descriptor read/64, error -32
10734 00:25:31.461449 <3>[ 4.858999] usb 1-1.1.4: device descriptor read/64, error -32
10735 00:25:31.656538 <6>[ 5.050920] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10736 00:25:31.840821 <6>[ 5.234956] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10737 00:25:31.925757 <3>[ 5.322995] usb 1-1.1.4: device descriptor read/64, error -32
10738 00:25:32.117294 <3>[ 5.515019] usb 1-1.1.4: device descriptor read/64, error -32
10739 00:25:32.229618 <6>[ 5.627430] usb 1-1.1-port4: attempt power cycle
10740 00:25:32.317222 <6>[ 5.711096] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10741 00:25:32.840927 <6>[ 6.234975] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10742 00:25:32.847151 <4>[ 6.242403] usb 1-1.1.4: Device not responding to setup address.
10743 00:25:33.057095 <4>[ 6.455000] usb 1-1.1.4: Device not responding to setup address.
10744 00:25:33.269439 <3>[ 6.666965] usb 1-1.1.4: device not accepting address 10, error -71
10745 00:25:33.356718 <6>[ 6.750950] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10746 00:25:33.362902 <4>[ 6.758398] usb 1-1.1.4: Device not responding to setup address.
10747 00:25:33.574496 <4>[ 6.971156] usb 1-1.1.4: Device not responding to setup address.
10748 00:25:33.788770 <3>[ 7.183002] usb 1-1.1.4: device not accepting address 11, error -71
10749 00:25:33.791677 <3>[ 7.189861] usb 1-1.1-port4: unable to enumerate USB device
10750 00:25:42.166346 <6>[ 15.568013] ALSA device list:
10751 00:25:42.172442 <6>[ 15.571314] No soundcards found.
10752 00:25:42.181125 <6>[ 15.579415] Freeing unused kernel memory: 8384K
10753 00:25:42.183968 <6>[ 15.584438] Run /init as init process
10754 00:25:42.238571 <6>[ 15.637087] NET: Registered PF_INET6 protocol family
10755 00:25:42.245305 <6>[ 15.643887] Segment Routing with IPv6
10756 00:25:42.248582 <6>[ 15.647871] In-situ OAM (IOAM) with IPv6
10757 00:25:42.285243 <30>[ 15.664079] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10758 00:25:42.288349 <30>[ 15.688034] systemd[1]: Detected architecture arm64.
10759 00:25:42.291921
10760 00:25:42.295172 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10761 00:25:42.295625
10762 00:25:42.308086 <30>[ 15.706867] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10763 00:25:42.481589 <30>[ 15.876902] systemd[1]: Queued start job for default target Graphical Interface.
10764 00:25:42.509252 <30>[ 15.907649] systemd[1]: Created slice system-getty.slice.
10765 00:25:42.515433 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10766 00:25:42.532501 <30>[ 15.931168] systemd[1]: Created slice system-modprobe.slice.
10767 00:25:42.539247 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10768 00:25:42.556604 <30>[ 15.955453] systemd[1]: Created slice system-serial\x2dgetty.slice.
10769 00:25:42.566812 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10770 00:25:42.581336 <30>[ 15.979949] systemd[1]: Created slice User and Session Slice.
10771 00:25:42.588069 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10772 00:25:42.608059 <30>[ 16.003529] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10773 00:25:42.617862 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10774 00:25:42.635673 <30>[ 16.031458] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10775 00:25:42.642688 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10776 00:25:42.662660 <30>[ 16.054912] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10777 00:25:42.669676 <30>[ 16.067039] systemd[1]: Reached target Local Encrypted Volumes.
10778 00:25:42.676193 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10779 00:25:42.692753 <30>[ 16.091448] systemd[1]: Reached target Paths.
10780 00:25:42.695880 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10781 00:25:42.712059 <30>[ 16.110947] systemd[1]: Reached target Remote File Systems.
10782 00:25:42.718690 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10783 00:25:42.736422 <30>[ 16.135309] systemd[1]: Reached target Slices.
10784 00:25:42.743117 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10785 00:25:42.756236 <30>[ 16.154981] systemd[1]: Reached target Swap.
10786 00:25:42.759507 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10787 00:25:42.780085 <30>[ 16.175477] systemd[1]: Listening on initctl Compatibility Named Pipe.
10788 00:25:42.786990 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10789 00:25:42.793471 <30>[ 16.190903] systemd[1]: Listening on Journal Audit Socket.
10790 00:25:42.800474 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10791 00:25:42.812643 <30>[ 16.211472] systemd[1]: Listening on Journal Socket (/dev/log).
10792 00:25:42.819565 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10793 00:25:42.837956 <30>[ 16.236272] systemd[1]: Listening on Journal Socket.
10794 00:25:42.844046 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10795 00:25:42.860177 <30>[ 16.255740] systemd[1]: Listening on Network Service Netlink Socket.
10796 00:25:42.866896 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10797 00:25:42.881821 <30>[ 16.280251] systemd[1]: Listening on udev Control Socket.
10798 00:25:42.888362 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10799 00:25:42.905552 <30>[ 16.304104] systemd[1]: Listening on udev Kernel Socket.
10800 00:25:42.911768 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10801 00:25:42.964908 <30>[ 16.363231] systemd[1]: Mounting Huge Pages File System...
10802 00:25:42.970900 Mounting [0;1;39mHuge Pages File System[0m...
10803 00:25:42.986427 <30>[ 16.385033] systemd[1]: Mounting POSIX Message Queue File System...
10804 00:25:42.992989 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10805 00:25:43.010028 <30>[ 16.408775] systemd[1]: Mounting Kernel Debug File System...
10806 00:25:43.017232 Mounting [0;1;39mKernel Debug File System[0m...
10807 00:25:43.035174 <30>[ 16.431060] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10808 00:25:43.046800 <30>[ 16.441960] systemd[1]: Starting Create list of static device nodes for the current kernel...
10809 00:25:43.053389 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10810 00:25:43.075217 <30>[ 16.474339] systemd[1]: Starting Load Kernel Module configfs...
10811 00:25:43.081839 Starting [0;1;39mLoad Kernel Module configfs[0m...
10812 00:25:43.104745 <30>[ 16.503606] systemd[1]: Starting Load Kernel Module drm...
10813 00:25:43.111201 Starting [0;1;39mLoad Kernel Module drm[0m...
10814 00:25:43.127854 <30>[ 16.523314] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10815 00:25:43.142454 <30>[ 16.541303] systemd[1]: Starting Journal Service...
10816 00:25:43.146074 Starting [0;1;39mJournal Service[0m...
10817 00:25:43.170481 <30>[ 16.569258] systemd[1]: Starting Load Kernel Modules...
10818 00:25:43.177108 Starting [0;1;39mLoad Kernel Modules[0m...
10819 00:25:43.200297 <30>[ 16.596087] systemd[1]: Starting Remount Root and Kernel File Systems...
10820 00:25:43.207099 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10821 00:25:43.230701 <30>[ 16.628614] systemd[1]: Starting Coldplug All udev Devices...
10822 00:25:43.237264 Starting [0;1;39mColdplug All udev Devices[0m...
10823 00:25:43.259263 <30>[ 16.658211] systemd[1]: Started Journal Service.
10824 00:25:43.265886 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10825 00:25:43.287245 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10826 00:25:43.309160 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10827 00:25:43.328737 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10828 00:25:43.353031 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10829 00:25:43.376142 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10830 00:25:43.395550 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10831 00:25:43.414134 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10832 00:25:43.434421 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10833 00:25:43.448486 See 'systemctl status systemd-remount-fs.service' for details.
10834 00:25:43.497009 Mounting [0;1;39mKernel Configuration File System[0m...
10835 00:25:43.517391 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10836 00:25:43.540057 Startin<46>[ 16.936098] systemd-journald[182]: Received client request to flush runtime journal.
10837 00:25:43.542749 g [0;1;39mLoad/Save Random Seed[0m...
10838 00:25:43.563132 Starting [0;1;39mApply Kernel Variables[0m...
10839 00:25:43.581792 Starting [0;1;39mCreate System Users[0m...
10840 00:25:43.599592 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10841 00:25:43.617780 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10842 00:25:43.637299 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10843 00:25:43.649995 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10844 00:25:43.665807 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10845 00:25:43.682361 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10846 00:25:43.720857 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10847 00:25:43.747708 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10848 00:25:43.764450 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10849 00:25:43.780696 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10850 00:25:43.832947 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10851 00:25:43.857005 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10852 00:25:43.877300 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10853 00:25:43.897396 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10854 00:25:43.948887 Starting [0;1;39mNetwork Service[0m...
10855 00:25:43.971547 Starting [0;1;39mNetwork Time Synchronization[0m...
10856 00:25:43.991100 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10857 00:25:44.037426 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10858 00:25:44.057078 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10859 00:25:44.079519 [[0;32m OK [0m] Started [0;<6>[ 17.474419] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10860 00:25:44.083121 1;39mNetwork Time Synchronization[0m.
10861 00:25:44.108568 <6>[ 17.504156] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10862 00:25:44.111762 <6>[ 17.509897] remoteproc remoteproc0: scp is available
10863 00:25:44.122129 <6>[ 17.511885] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10864 00:25:44.128440 <6>[ 17.517202] remoteproc remoteproc0: powering up scp
10865 00:25:44.134703 <6>[ 17.525679] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10866 00:25:44.141483 <6>[ 17.532034] mc: Linux media interface: v0.10
10867 00:25:44.148541 <6>[ 17.539545] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10868 00:25:44.154719 <6>[ 17.552607] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10869 00:25:44.158021 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10870 00:25:44.174872 <4>[ 17.570061] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10871 00:25:44.188568 <4>[ 17.584255] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10872 00:25:44.199028 <3>[ 17.593813] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10873 00:25:44.209228 [[0;32m OK [<3>[ 17.603736] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10874 00:25:44.218285 0m] Created slic<3>[ 17.612148] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10875 00:25:44.224867 e [0;1;39msyste<6>[ 17.622444] usbcore: registered new interface driver r8152
10876 00:25:44.234945 m-systemd\x2dbac<3>[ 17.623239] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10877 00:25:44.244713 klight.slice[0m<3>[ 17.638362] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10878 00:25:44.245256 .
10879 00:25:44.251168 <3>[ 17.648383] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10880 00:25:44.261474 <3>[ 17.656642] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10881 00:25:44.267787 <6>[ 17.663102] videodev: Linux video capture interface: v2.00
10882 00:25:44.274355 <3>[ 17.664946] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10883 00:25:44.284147 <6>[ 17.667245] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10884 00:25:44.291152 <6>[ 17.667813] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10885 00:25:44.301209 <6>[ 17.667821] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10886 00:25:44.307568 <6>[ 17.667837] pci_bus 0000:00: root bus resource [bus 00-ff]
10887 00:25:44.313910 <6>[ 17.667857] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10888 00:25:44.324620 <6>[ 17.667865] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10889 00:25:44.330549 <6>[ 17.668069] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10890 00:25:44.337261 <6>[ 17.668119] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10891 00:25:44.343902 <6>[ 17.668306] pci 0000:00:00.0: supports D1 D2
10892 00:25:44.350159 <6>[ 17.668317] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10893 00:25:44.357446 <6>[ 17.670999] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10894 00:25:44.363604 <6>[ 17.681159] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10895 00:25:44.373488 <3>[ 17.682412] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10896 00:25:44.380208 <3>[ 17.682887] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10897 00:25:44.390409 <3>[ 17.682898] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10898 00:25:44.396419 <3>[ 17.682905] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10899 00:25:44.407111 <3>[ 17.683004] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10900 00:25:44.412715 <3>[ 17.683009] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10901 00:25:44.423152 <3>[ 17.683015] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10902 00:25:44.430120 <3>[ 17.683022] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10903 00:25:44.437386 <3>[ 17.683026] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10904 00:25:44.447350 <3>[ 17.683058] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10905 00:25:44.454083 <6>[ 17.688974] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10906 00:25:44.461429 <6>[ 17.689049] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10907 00:25:44.467234 <6>[ 17.689079] remoteproc remoteproc0: remote processor scp is now up
10908 00:25:44.473637 <6>[ 17.696358] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10909 00:25:44.483843 <6>[ 17.713405] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10910 00:25:44.490737 <6>[ 17.717870] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10911 00:25:44.497718 <6>[ 17.717908] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10912 00:25:44.507516 <6>[ 17.717931] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10913 00:25:44.510805 <6>[ 17.718126] pci 0000:01:00.0: supports D1 D2
10914 00:25:44.517654 <6>[ 17.718590] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10915 00:25:44.527749 <4>[ 17.753137] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10916 00:25:44.531612 <4>[ 17.753137] Fallback method does not support PEC.
10917 00:25:44.538210 <6>[ 17.753473] usbcore: registered new interface driver cdc_ether
10918 00:25:44.545060 <6>[ 17.754619] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10919 00:25:44.554987 <6>[ 17.758383] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10920 00:25:44.562049 <6>[ 17.761152] usbcore: registered new interface driver r8153_ecm
10921 00:25:44.567929 <6>[ 17.769536] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10922 00:25:44.571528 <6>[ 17.786185] Bluetooth: Core ver 2.22
10923 00:25:44.578415 <6>[ 17.810555] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10924 00:25:44.584851 <6>[ 17.810757] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10925 00:25:44.591857 <6>[ 17.810824] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10926 00:25:44.601533 <6>[ 17.810828] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10927 00:25:44.608218 <6>[ 17.810837] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10928 00:25:44.618108 <6>[ 17.810851] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10929 00:25:44.625716 <6>[ 17.810865] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10930 00:25:44.628764 <6>[ 17.810879] pci 0000:00:00.0: PCI bridge to [bus 01]
10931 00:25:44.638679 <6>[ 17.810886] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10932 00:25:44.645504 <6>[ 17.811237] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10933 00:25:44.652099 <6>[ 17.811324] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10934 00:25:44.658743 <6>[ 17.812064] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10935 00:25:44.661623 <6>[ 17.812496] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10936 00:25:44.674912 <6>[ 17.813094] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10937 00:25:44.681649 <6>[ 17.813569] usbcore: registered new interface driver uvcvideo
10938 00:25:44.688846 <6>[ 17.818218] NET: Registered PF_BLUETOOTH protocol family
10939 00:25:44.695174 <5>[ 17.830481] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10940 00:25:44.701877 <6>[ 17.834330] Bluetooth: HCI device and connection manager initialized
10941 00:25:44.711044 <4>[ 17.841697] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10942 00:25:44.717855 <4>[ 17.841707] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10943 00:25:44.728056 <3>[ 17.845556] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10944 00:25:44.738133 <3>[ 17.846509] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 00:25:44.744260 <3>[ 17.847705] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 00:25:44.750905 <6>[ 17.850691] Bluetooth: HCI socket layer initialized
10947 00:25:44.757626 <5>[ 17.853220] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10948 00:25:44.767822 <4>[ 17.853282] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10949 00:25:44.770825 <6>[ 17.853288] cfg80211: failed to load regulatory.db
10950 00:25:44.777314 <6>[ 17.894769] r8152 1-1.1.1:1.0 eth0: v1.12.13
10951 00:25:44.780789 <6>[ 17.895487] Bluetooth: L2CAP socket layer initialized
10952 00:25:44.791323 <3>[ 17.907284] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 00:25:44.797813 <3>[ 17.908328] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10954 00:25:44.804566 <6>[ 17.909724] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10955 00:25:44.808324 <6>[ 17.910436] Bluetooth: SCO socket layer initialized
10956 00:25:44.818312 <3>[ 17.939716] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10957 00:25:44.824663 <6>[ 17.949249] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10958 00:25:44.835498 <3>[ 17.974270] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 00:25:44.842020 <6>[ 17.975369] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10960 00:25:44.845378 <6>[ 18.005193] usbcore: registered new interface driver btusb
10961 00:25:44.855298 <4>[ 18.006044] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10962 00:25:44.862232 <3>[ 18.006056] Bluetooth: hci0: Failed to load firmware file (-2)
10963 00:25:44.868833 <3>[ 18.006060] Bluetooth: hci0: Failed to set up firmware (-2)
10964 00:25:44.878961 <4>[ 18.006064] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10965 00:25:44.888676 <3>[ 18.009120] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 00:25:44.895038 <3>[ 18.030330] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 00:25:44.901697 <6>[ 18.034169] mt7921e 0000:01:00.0: ASIC revision: 79610010
10968 00:25:44.911188 <3>[ 18.062632] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 00:25:44.921433 <4>[ 18.161921] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10970 00:25:44.927734 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10971 00:25:44.944074 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10972 00:25:45.013181 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10973 00:25:45.040530 <4>[ 18.433182] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10974 00:25:45.054177 Starting [0;1;39mNetwork Name Resolution[0m...
10975 00:25:45.074487 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10976 00:25:45.132731 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10977 00:25:45.164880 <4>[ 18.557280] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10978 00:25:45.283929 <4>[ 18.676500] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10979 00:25:45.297525 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10980 00:25:45.312147 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10981 00:25:45.331467 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10982 00:25:45.348063 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10983 00:25:45.367972 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10984 00:25:45.383863 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10985 00:25:45.400353 <4>[ 18.792836] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10986 00:25:45.406866 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10987 00:25:45.423899 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10988 00:25:45.436035 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10989 00:25:45.451897 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10990 00:25:45.471624 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10991 00:25:45.520320 <4>[ 18.912883] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10992 00:25:45.527297 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10993 00:25:45.555397 Starting [0;1;39mUser Login Management[0m...
10994 00:25:45.572424 Starting [0;1;39mPermit User Sessions[0m...
10995 00:25:45.592405 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10996 00:25:45.613170 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10997 00:25:45.645136 <4>[ 19.037661] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10998 00:25:45.651956 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10999 00:25:45.658682 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11000 00:25:45.676849 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11001 00:25:45.693789 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11002 00:25:45.709124 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11003 00:25:45.726675 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11004 00:25:45.744880 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11005 00:25:45.768149 <4>[ 19.161034] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11006 00:25:45.800192 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11007 00:25:45.828619 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11008 00:25:45.879028
11009 00:25:45.879572
11010 00:25:45.891395 Debian GNU/Linux 11 debian-bu<4>[ 19.283364] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11011 00:25:45.891957 llseye-arm64 ttyS0
11012 00:25:45.892317
11013 00:25:45.897895 debian-bullseye-arm64 login: root (automatic login)
11014 00:25:45.898452
11015 00:25:45.898854
11016 00:25:45.920092 Linux debian-bullseye-arm64 6.1.45-cip3 #1 SMP PREEMPT Mon Aug 14 00:09:07 UTC 2023 aarch64
11017 00:25:45.920654
11018 00:25:45.926683 The programs included with the Debian GNU/Linux system are free software;
11019 00:25:45.933397 the exact distribution terms for each program are described in the
11020 00:25:45.936585 individual files in /usr/share/doc/*/copyright.
11021 00:25:45.937139
11022 00:25:45.943054 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11023 00:25:45.946741 permitted by applicable law.
11024 00:25:45.948033 Matched prompt #10: / #
11026 00:25:45.949144 Setting prompt string to ['/ #']
11027 00:25:45.949614 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11029 00:25:45.950942 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11030 00:25:45.951429 start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
11031 00:25:45.951820 Setting prompt string to ['/ #']
11032 00:25:45.952179 Forcing a shell prompt, looking for ['/ #']
11034 00:25:46.002986 / #
11035 00:25:46.003638 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11036 00:25:46.004072 Waiting using forced prompt support (timeout 00:02:30)
11037 00:25:46.047305 <4>[ 19.405580] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11038 00:25:46.047874
11039 00:25:46.048627 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11040 00:25:46.049136 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
11041 00:25:46.049639 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11042 00:25:46.050112 end: 2.2 depthcharge-retry (duration 00:01:25) [common]
11043 00:25:46.050691 end: 2 depthcharge-action (duration 00:01:25) [common]
11044 00:25:46.051222 start: 3 lava-test-retry (timeout 00:08:15) [common]
11045 00:25:46.051680 start: 3.1 lava-test-shell (timeout 00:08:15) [common]
11046 00:25:46.052089 Using namespace: common
11048 00:25:46.153309 / # #
11049 00:25:46.153969 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11050 00:25:46.154556 #<3>[ 19.523277] mt7921e 0000:01:00.0: hardware init failed
11051 00:25:46.159796
11052 00:25:46.160665 Using /lava-11280966
11054 00:25:46.261836 / # export SHELL=/bin/sh
11055 00:25:46.268069 export SHELL=/bin/sh
11057 00:25:46.369654 / # . /lava-11280966/environment
11058 00:25:46.370416 . /lava-11280966/environment<6>[ 19.750369] IPv6: ADDRCONF(NETDEV_CHANGE): enxf4f5e850de0a: link becomes ready
11059 00:25:46.370906 <6>[ 19.758511] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
11060 00:25:46.375896
11062 00:25:46.477564 / # /lava-11280966/bin/lava-test-runner /lava-11280966/0
11063 00:25:46.478250 Test shell timeout: 10s (minimum of the action and connection timeout)
11064 00:25:46.483713 /lava-11280966/bin/lava-test-runner /lava-11280966/0
11065 00:25:46.506455 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11066 00:25:46.512921 + cd /lava-11280966/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11067 00:25:46.513484 + cat uuid
11068 00:25:46.516323 + UUID=11280966_1.5.2.3.1
11069 00:25:46.516874 + set +x
11070 00:25:46.522958 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 11280966_1.5.2.3.1>
11071 00:25:46.523785 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 11280966_1.5.2.3.1
11072 00:25:46.524184 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (11280966_1.5.2.3.1)
11073 00:25:46.524615 Skipping test definition patterns.
11074 00:25:46.525886 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11075 00:25:46.532453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11076 00:25:46.533254 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11078 00:25:46.543282 device: /dev/vide<4>[ 19.936942] use of bytesused == 0 is deprecated and will be removed in the future,
11079 00:25:46.543842 o2
11080 00:25:46.545784 <4>[ 19.945587] use the actual size instead.
11081 00:25:46.552744 <4>[ 19.952188] ------------[ cut here ]------------
11082 00:25:46.559761 <4>[ 19.957077] get_vaddr_frames() cannot follow VM_IO mapping
11083 00:25:46.572802 <4>[ 19.957262] WARNING: CPU: 0 PID: 307 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11084 00:25:46.618862 <4>[ 19.975380] Modules linked in: btusb btintel btmtk btrtl btbcm mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 cfg80211 mtk_vcodec_enc mtk_vcodec_common uvcvideo mtk_vpu v4l2_mem2mem videobuf2_vmalloc videobuf2_dma_contig bluetooth r8153_ecm videobuf2_memops cros_ec_rpmsg cdc_ether videobuf2_v4l2 ecdh_generic hid_google_hammer videobuf2_common ecc usbnet videodev rfkill r8152 sbs_battery cros_ec_typec hid_vivaldi_common cros_ec_chardev crct10dif_ce elants_i2c mc pcie_mediatek_gen3 elan_i2c mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11085 00:25:46.629109 <4>[ 20.024763] CPU: 0 PID: 307 Comm: v4l2-compliance Not tainted 6.1.45-cip3 #1
11086 00:25:46.631907 <4>[ 20.032062] Hardware name: Google Spherion (rev0 - 3) (DT)
11087 00:25:46.641960 <4>[ 20.037796] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11088 00:25:46.645645 <4>[ 20.045008] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11089 00:25:46.652619 <4>[ 20.051099] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11090 00:25:46.655084 <4>[ 20.057190] sp : ffff8000091a3850
11091 00:25:46.664891 <4>[ 20.060753] x29: ffff8000091a3850 x28: ffffdc72a29bf000 x27: ffffdc72a29bb238
11092 00:25:46.671932 <4>[ 20.068141] x26: 0000000000000000 x25: ffffdc72d5e2bfe0 x24: ffff0f4e4e921298
11093 00:25:46.678309 <4>[ 20.075529] x23: ffff0f4e4a187400 x22: ffff0f4e40d48410 x21: 0000000000000000
11094 00:25:46.685279 <4>[ 20.082915] x20: 00000000fffffff2 x19: ffff0f4e4977a400 x18: fffffffffffe9c48
11095 00:25:46.695067 <4>[ 20.090302] x17: 0000000000000000 x16: ffffdc72d3c8bb90 x15: 0000000000000038
11096 00:25:46.701688 <4>[ 20.097689] x14: 000000000000001b x13: 0000000000000000 x12: 0000000000000000
11097 00:25:46.708296 <4>[ 20.105075] x11: 0000000000000000 x10: 0000000000000a60 x9 : ffff8000091a3700
11098 00:25:46.714969 <4>[ 20.112462] x8 : ffff0f4e4a297200 x7 : ffff0f4f7ef1ce40 x6 : 0000000000000012
11099 00:25:46.721061 <4>[ 20.119848] x5 : 00000000410fd050 x4 : 0000000000c0000e x3 : 0000000000200000
11100 00:25:46.731350 <4>[ 20.127234] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff0f4e4a296740
11101 00:25:46.734852 <4>[ 20.134621] Call trace:
11102 00:25:46.738134 <4>[ 20.137318] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11103 00:25:46.744484 <4>[ 20.143061] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11104 00:25:46.751337 <4>[ 20.149063] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11105 00:25:46.757941 <4>[ 20.155414] __prepare_userptr+0x280/0x410 [videobuf2_common]
11106 00:25:46.764568 <4>[ 20.161418] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11107 00:25:46.767715 <4>[ 20.167074] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11108 00:25:46.774383 <4>[ 20.173250] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11109 00:25:46.780813 <4>[ 20.178749] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11110 00:25:46.787385 <4>[ 20.184519] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11111 00:25:46.790824 <4>[ 20.190784] v4l_prepare_buf+0x48/0x60 [videodev]
11112 00:25:46.797519 <4>[ 20.195815] __video_do_ioctl+0x184/0x3d0 [videodev]
11113 00:25:46.800677 <4>[ 20.201058] video_usercopy+0x358/0x680 [videodev]
11114 00:25:46.807697 <4>[ 20.206128] video_ioctl2+0x18/0x30 [videodev]
11115 00:25:46.810433 <4>[ 20.210851] v4l2_ioctl+0x40/0x60 [videodev]
11116 00:25:46.814218 <4>[ 20.215400] __arm64_sys_ioctl+0xa8/0xf0
11117 00:25:46.821000 <4>[ 20.219580] invoke_syscall+0x48/0x114
11118 00:25:46.824071 <4>[ 20.223586] el0_svc_common.constprop.0+0x44/0xec
11119 00:25:46.826980 <4>[ 20.228541] do_el0_svc+0x2c/0xd0
11120 00:25:46.830188 <4>[ 20.232107] el0_svc+0x2c/0x84
11121 00:25:46.837097 <4>[ 20.235413] el0t_64_sync_handler+0xb8/0xc0
11122 00:25:46.840270 <4>[ 20.239847] el0t_64_sync+0x18c/0x190
11123 00:25:46.843429 <4>[ 20.243762] ---[ end trace 0000000000000000 ]---
11124 00:25:46.856536 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11125 00:25:46.864971 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11126 00:25:46.871521
11127 00:25:46.885089 Compliance test for mtk-vcodec-enc device /dev/video2:
11128 00:25:46.898549
11129 00:25:46.908445 Driver Info:
11130 00:25:46.918827 Driver name : mtk-vcodec-enc
11131 00:25:46.933579 Card type : MT8192 video encoder
11132 00:25:46.945870 Bus info : platform:17020000.vcodec
11133 00:25:46.953732 Driver version : 6.1.45
11134 00:25:46.967246 Capabilities : 0x84204000
11135 00:25:46.982472 Video Memory-to-Memory Multiplanar
11136 00:25:46.995555 Streaming
11137 00:25:47.005801 Extended Pix Format
11138 00:25:47.017209 Device Capabilities
11139 00:25:47.032642 Device Caps : 0x04204000
11140 00:25:47.042208 Video Memory-to-Memory Multiplanar
11141 00:25:47.059143 Streaming
11142 00:25:47.070825 Extended Pix Format
11143 00:25:47.085762 Detected Stateful Encoder
11144 00:25:47.095760
11145 00:25:47.108644 Required ioctls:
11146 00:25:47.127455 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11147 00:25:47.128019 test VIDIOC_QUERYCAP: OK
11148 00:25:47.128710 Received signal: <TESTSET> START Required-ioctls
11149 00:25:47.129099 Starting test_set Required-ioctls
11150 00:25:47.158124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11151 00:25:47.158999 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11153 00:25:47.161216 test invalid ioctls: OK
11154 00:25:47.182457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11155 00:25:47.183146
11156 00:25:47.183785 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11158 00:25:47.193316 Allow for multiple opens:
11159 00:25:47.202633 <LAVA_SIGNAL_TESTSET STOP>
11160 00:25:47.203474 Received signal: <TESTSET> STOP
11161 00:25:47.203865 Closing test_set Required-ioctls
11162 00:25:47.212242 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11163 00:25:47.213076 Received signal: <TESTSET> START Allow-for-multiple-opens
11164 00:25:47.213482 Starting test_set Allow-for-multiple-opens
11165 00:25:47.215203 test second /dev/video2 open: OK
11166 00:25:47.242306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11167 00:25:47.243385 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11169 00:25:47.245341 test VIDIOC_QUERYCAP: OK
11170 00:25:47.267575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11171 00:25:47.268413 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11173 00:25:47.270575 test VIDIOC_G/S_PRIORITY: OK
11174 00:25:47.293329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11175 00:25:47.294162 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11177 00:25:47.295881 test for unlimited opens: OK
11178 00:25:47.324918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11179 00:25:47.325480
11180 00:25:47.326115 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11182 00:25:47.335594 Debug ioctls:
11183 00:25:47.342998 <LAVA_SIGNAL_TESTSET STOP>
11184 00:25:47.343825 Received signal: <TESTSET> STOP
11185 00:25:47.344207 Closing test_set Allow-for-multiple-opens
11186 00:25:47.351961 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11187 00:25:47.352798 Received signal: <TESTSET> START Debug-ioctls
11188 00:25:47.353183 Starting test_set Debug-ioctls
11189 00:25:47.355206 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11190 00:25:47.376961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11191 00:25:47.377800 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11193 00:25:47.383116 test VIDIOC_LOG_STATUS: OK (Not Supported)
11194 00:25:47.401640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11195 00:25:47.402184
11196 00:25:47.402810 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11198 00:25:47.416568 Input ioctls:
11199 00:25:47.423730 <LAVA_SIGNAL_TESTSET STOP>
11200 00:25:47.424578 Received signal: <TESTSET> STOP
11201 00:25:47.424957 Closing test_set Debug-ioctls
11202 00:25:47.433663 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11203 00:25:47.434501 Received signal: <TESTSET> START Input-ioctls
11204 00:25:47.434915 Starting test_set Input-ioctls
11205 00:25:47.436687 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11206 00:25:47.461846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11207 00:25:47.462717 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11209 00:25:47.465243 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11210 00:25:47.483592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11211 00:25:47.484430 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11213 00:25:47.490360 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11214 00:25:47.507512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11215 00:25:47.508353 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11217 00:25:47.513566 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11218 00:25:47.533255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11219 00:25:47.534071 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11221 00:25:47.539293 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11222 00:25:47.561855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11223 00:25:47.562768 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11225 00:25:47.565154 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11226 00:25:47.588567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11227 00:25:47.589422 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11229 00:25:47.591432 Inputs: 0 Audio Inputs: 0 Tuners: 0
11230 00:25:47.599557
11231 00:25:47.624151 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11232 00:25:47.646228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11233 00:25:47.647173 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11235 00:25:47.653010 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11236 00:25:47.672694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11237 00:25:47.673525 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11239 00:25:47.678432 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11240 00:25:47.697463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11241 00:25:47.698293 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11243 00:25:47.704159 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11244 00:25:47.721487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11245 00:25:47.722336 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11247 00:25:47.727953 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11248 00:25:47.745227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11249 00:25:47.745778
11250 00:25:47.746413 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11252 00:25:47.764863 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11253 00:25:47.788315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11254 00:25:47.789125 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11256 00:25:47.794652 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11257 00:25:47.816281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11258 00:25:47.817124 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11260 00:25:47.819289 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11261 00:25:47.837842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11262 00:25:47.838711 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11264 00:25:47.844035 test VIDIOC_G/S_EDID: OK (Not Supported)
11265 00:25:47.862909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11266 00:25:47.863551
11267 00:25:47.864202 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11269 00:25:47.878904 Control ioctls:
11270 00:25:47.888596 <LAVA_SIGNAL_TESTSET STOP>
11271 00:25:47.889431 Received signal: <TESTSET> STOP
11272 00:25:47.889812 Closing test_set Input-ioctls
11273 00:25:47.898736 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11274 00:25:47.899575 Received signal: <TESTSET> START Control-ioctls
11275 00:25:47.899983 Starting test_set Control-ioctls
11276 00:25:47.902262 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11277 00:25:47.925525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11278 00:25:47.926086 test VIDIOC_QUERYCTRL: OK
11279 00:25:47.926735 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11281 00:25:47.944416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11282 00:25:47.945273 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11284 00:25:47.948519 test VIDIOC_G/S_CTRL: OK
11285 00:25:47.966793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11286 00:25:47.967617 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11288 00:25:47.970398 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11289 00:25:47.992840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11290 00:25:47.993647 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11292 00:25:48.003032 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11293 00:25:48.006095 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11294 00:25:48.031060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11295 00:25:48.031886 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11297 00:25:48.034183 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11298 00:25:48.050713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11299 00:25:48.051533 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11301 00:25:48.053869 Standard Controls: 16 Private Controls: 0
11302 00:25:48.059812
11303 00:25:48.072470 Format ioctls:
11304 00:25:48.078923 <LAVA_SIGNAL_TESTSET STOP>
11305 00:25:48.079735 Received signal: <TESTSET> STOP
11306 00:25:48.080114 Closing test_set Control-ioctls
11307 00:25:48.088322 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11308 00:25:48.089042 Received signal: <TESTSET> START Format-ioctls
11309 00:25:48.089630 Starting test_set Format-ioctls
11310 00:25:48.091368 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11311 00:25:48.115507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11312 00:25:48.116673 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11314 00:25:48.119338 test VIDIOC_G/S_PARM: OK
11315 00:25:48.136890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11316 00:25:48.137713 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11318 00:25:48.140470 test VIDIOC_G_FBUF: OK (Not Supported)
11319 00:25:48.176695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11320 00:25:48.177632 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11322 00:25:48.180040 test VIDIOC_G_FMT: OK
11323 00:25:48.203544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11324 00:25:48.204370 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11326 00:25:48.206936 test VIDIOC_TRY_FMT: OK
11327 00:25:48.226162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11328 00:25:48.227031 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11330 00:25:48.235919 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11331 00:25:48.245530 test VIDIOC_S_FMT: FAIL
11332 00:25:48.273997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11333 00:25:48.274826 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11335 00:25:48.276717 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11336 00:25:48.297435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11337 00:25:48.298262 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11339 00:25:48.300993 test Cropping: OK
11340 00:25:48.327060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11341 00:25:48.327884 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11343 00:25:48.329223 test Composing: OK (Not Supported)
11344 00:25:48.356325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11345 00:25:48.357145 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11347 00:25:48.359327 test Scaling: OK (Not Supported)
11348 00:25:48.380308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11349 00:25:48.380860
11350 00:25:48.381486 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11352 00:25:48.391438 Codec ioctls:
11353 00:25:48.404304 <LAVA_SIGNAL_TESTSET STOP>
11354 00:25:48.405140 Received signal: <TESTSET> STOP
11355 00:25:48.405716 Closing test_set Format-ioctls
11356 00:25:48.414727 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11357 00:25:48.415562 Received signal: <TESTSET> START Codec-ioctls
11358 00:25:48.415944 Starting test_set Codec-ioctls
11359 00:25:48.417924 test VIDIOC_(TRY_)ENCODER_CMD: OK
11360 00:25:48.438902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11361 00:25:48.439708 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11363 00:25:48.444988 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11364 00:25:48.463567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11365 00:25:48.464390 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11367 00:25:48.469955 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11368 00:25:48.488413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11369 00:25:48.489077
11370 00:25:48.489844 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11372 00:25:48.500285 Buffer ioctls:
11373 00:25:48.509616 <LAVA_SIGNAL_TESTSET STOP>
11374 00:25:48.510501 Received signal: <TESTSET> STOP
11375 00:25:48.510965 Closing test_set Codec-ioctls
11376 00:25:48.519228 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11377 00:25:48.520079 Received signal: <TESTSET> START Buffer-ioctls
11378 00:25:48.520491 Starting test_set Buffer-ioctls
11379 00:25:48.522163 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11380 00:25:48.545733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11381 00:25:48.546289 test VIDIOC_EXPBUF: OK
11382 00:25:48.547112 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11384 00:25:48.567511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11385 00:25:48.568364 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11387 00:25:48.570417 test Requests: OK (Not Supported)
11388 00:25:48.592199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11389 00:25:48.592763
11390 00:25:48.593517 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11392 00:25:48.603504 Test input 0:
11393 00:25:48.614028
11394 00:25:48.626299 Streaming ioctls:
11395 00:25:48.635932 <LAVA_SIGNAL_TESTSET STOP>
11396 00:25:48.636757 Received signal: <TESTSET> STOP
11397 00:25:48.637145 Closing test_set Buffer-ioctls
11398 00:25:48.647453 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11399 00:25:48.648275 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11400 00:25:48.648658 Starting test_set Streaming-ioctls_Test-input-0
11401 00:25:48.650717 test read/write: OK (Not Supported)
11402 00:25:48.673420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11403 00:25:48.674247 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11405 00:25:48.680180 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11406 00:25:48.690133 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11407 00:25:48.693761 test blocking wait: FAIL
11408 00:25:48.718500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11409 00:25:48.719402 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11411 00:25:48.727951 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11412 00:25:48.731543 test MMAP (select): FAIL
11413 00:25:48.759364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11414 00:25:48.760213 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11416 00:25:48.765508 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11417 00:25:48.769817 test MMAP (epoll): FAIL
11418 00:25:48.794838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11419 00:25:48.795680 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11421 00:25:48.804932 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11422 00:25:48.811500 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11423 00:25:48.815689 test USERPTR (select): FAIL
11424 00:25:48.844391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11425 00:25:48.845261 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11427 00:25:48.850418 test DMABUF: Cannot test, specify --expbuf-device
11428 00:25:48.854704
11429 00:25:48.872541 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11430 00:25:48.881320 <LAVA_TEST_RUNNER EXIT>
11431 00:25:48.882180 ok: lava_test_shell seems to have completed
11432 00:25:48.882627 Marking unfinished test run as failed
11434 00:25:48.887661 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11435 00:25:48.888323 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11436 00:25:48.888790 end: 3 lava-test-retry (duration 00:00:03) [common]
11437 00:25:48.889273 start: 4 finalize (timeout 00:08:13) [common]
11438 00:25:48.889757 start: 4.1 power-off (timeout 00:00:30) [common]
11439 00:25:48.890836 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11440 00:25:49.013133 >> Command sent successfully.
11441 00:25:49.017468 Returned 0 in 0 seconds
11442 00:25:49.118390 end: 4.1 power-off (duration 00:00:00) [common]
11444 00:25:49.120538 start: 4.2 read-feedback (timeout 00:08:12) [common]
11445 00:25:49.121938 Listened to connection for namespace 'common' for up to 1s
11446 00:25:50.122716 Finalising connection for namespace 'common'
11447 00:25:50.123423 Disconnecting from shell: Finalise
11448 00:25:50.123895 / #
11449 00:25:50.225125 end: 4.2 read-feedback (duration 00:00:01) [common]
11450 00:25:50.225855 end: 4 finalize (duration 00:00:01) [common]
11451 00:25:50.226451 Cleaning after the job
11452 00:25:50.227025 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11280966/tftp-deploy-20drlgbp/ramdisk
11453 00:25:50.254291 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11280966/tftp-deploy-20drlgbp/kernel
11454 00:25:50.275041 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11280966/tftp-deploy-20drlgbp/dtb
11455 00:25:50.275358 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11280966/tftp-deploy-20drlgbp/modules
11456 00:25:50.285696 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11280966
11457 00:25:50.354466 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11280966
11458 00:25:50.354686 Job finished correctly