Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 39
- Boot result: PASS
- Warnings: 1
- Errors: 1
- Kernel Warnings: 26
1 13:20:23.386153 lava-dispatcher, installed at version: 2023.06
2 13:20:23.386377 start: 0 validate
3 13:20:23.386514 Start time: 2023-09-06 13:20:23.386507+00:00 (UTC)
4 13:20:23.386659 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:20:23.386809 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 13:20:23.641047 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:20:23.641836 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4-14-g09ffd7fb38ff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:20:23.912278 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:20:23.913060 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4-14-g09ffd7fb38ff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:20:58.937492 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:20:58.938163 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:20:59.450837 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:20:59.451026 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4-14-g09ffd7fb38ff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 13:20:59.725491 validate duration: 36.34
16 13:20:59.726769 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:20:59.727340 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:20:59.727830 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:20:59.728462 Not decompressing ramdisk as can be used compressed.
20 13:20:59.728969 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 13:20:59.729324 saving as /var/lib/lava/dispatcher/tmp/11445602/tftp-deploy-75s0rxey/ramdisk/initrd.cpio.gz
22 13:20:59.729684 total size: 4665412 (4 MB)
23 13:21:02.853928 progress 0 % (0 MB)
24 13:21:02.862342 progress 5 % (0 MB)
25 13:21:02.869882 progress 10 % (0 MB)
26 13:21:02.877128 progress 15 % (0 MB)
27 13:21:02.884072 progress 20 % (0 MB)
28 13:21:02.889823 progress 25 % (1 MB)
29 13:21:02.895028 progress 30 % (1 MB)
30 13:21:02.899345 progress 35 % (1 MB)
31 13:21:02.903200 progress 40 % (1 MB)
32 13:21:02.906843 progress 45 % (2 MB)
33 13:21:02.909818 progress 50 % (2 MB)
34 13:21:02.912618 progress 55 % (2 MB)
35 13:21:02.915258 progress 60 % (2 MB)
36 13:21:02.917848 progress 65 % (2 MB)
37 13:21:02.920224 progress 70 % (3 MB)
38 13:21:02.922460 progress 75 % (3 MB)
39 13:21:02.924599 progress 80 % (3 MB)
40 13:21:02.926873 progress 85 % (3 MB)
41 13:21:02.928859 progress 90 % (4 MB)
42 13:21:02.930858 progress 95 % (4 MB)
43 13:21:02.932944 progress 100 % (4 MB)
44 13:21:02.933253 4 MB downloaded in 3.20 s (1.39 MB/s)
45 13:21:02.933491 end: 1.1.1 http-download (duration 00:00:03) [common]
47 13:21:02.933764 end: 1.1 download-retry (duration 00:00:03) [common]
48 13:21:02.933849 start: 1.2 download-retry (timeout 00:09:57) [common]
49 13:21:02.933930 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 13:21:02.934094 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4-14-g09ffd7fb38ff/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 13:21:02.934180 saving as /var/lib/lava/dispatcher/tmp/11445602/tftp-deploy-75s0rxey/kernel/Image
52 13:21:02.934260 total size: 49220096 (46 MB)
53 13:21:02.934352 No compression specified
54 13:21:02.949245 progress 0 % (0 MB)
55 13:21:02.963130 progress 5 % (2 MB)
56 13:21:02.977156 progress 10 % (4 MB)
57 13:21:02.990676 progress 15 % (7 MB)
58 13:21:03.004478 progress 20 % (9 MB)
59 13:21:03.018221 progress 25 % (11 MB)
60 13:21:03.032125 progress 30 % (14 MB)
61 13:21:03.045822 progress 35 % (16 MB)
62 13:21:03.059308 progress 40 % (18 MB)
63 13:21:03.072205 progress 45 % (21 MB)
64 13:21:03.085180 progress 50 % (23 MB)
65 13:21:03.098912 progress 55 % (25 MB)
66 13:21:03.112165 progress 60 % (28 MB)
67 13:21:03.125371 progress 65 % (30 MB)
68 13:21:03.138484 progress 70 % (32 MB)
69 13:21:03.151646 progress 75 % (35 MB)
70 13:21:03.164696 progress 80 % (37 MB)
71 13:21:03.177627 progress 85 % (39 MB)
72 13:21:03.190457 progress 90 % (42 MB)
73 13:21:03.203094 progress 95 % (44 MB)
74 13:21:03.215922 progress 100 % (46 MB)
75 13:21:03.216069 46 MB downloaded in 0.28 s (166.57 MB/s)
76 13:21:03.216227 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:21:03.216460 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:21:03.216545 start: 1.3 download-retry (timeout 00:09:57) [common]
80 13:21:03.216630 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 13:21:03.216813 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4-14-g09ffd7fb38ff/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:21:03.216883 saving as /var/lib/lava/dispatcher/tmp/11445602/tftp-deploy-75s0rxey/dtb/mt8192-asurada-spherion-r0.dtb
83 13:21:03.216942 total size: 47278 (0 MB)
84 13:21:03.217009 No compression specified
85 13:21:03.218167 progress 69 % (0 MB)
86 13:21:03.218445 progress 100 % (0 MB)
87 13:21:03.218598 0 MB downloaded in 0.00 s (27.27 MB/s)
88 13:21:03.218716 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:21:03.218931 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:21:03.219012 start: 1.4 download-retry (timeout 00:09:57) [common]
92 13:21:03.219090 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 13:21:03.219199 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 13:21:03.219263 saving as /var/lib/lava/dispatcher/tmp/11445602/tftp-deploy-75s0rxey/nfsrootfs/full.rootfs.tar
95 13:21:03.219320 total size: 125290964 (119 MB)
96 13:21:03.219379 Using unxz to decompress xz
97 13:21:03.227350 progress 0 % (0 MB)
98 13:21:03.548744 progress 5 % (6 MB)
99 13:21:03.877479 progress 10 % (11 MB)
100 13:21:04.203643 progress 15 % (17 MB)
101 13:21:04.386099 progress 20 % (23 MB)
102 13:21:04.558252 progress 25 % (29 MB)
103 13:21:04.906374 progress 30 % (35 MB)
104 13:21:05.257908 progress 35 % (41 MB)
105 13:21:05.640612 progress 40 % (47 MB)
106 13:21:06.012492 progress 45 % (53 MB)
107 13:21:06.393524 progress 50 % (59 MB)
108 13:21:06.738592 progress 55 % (65 MB)
109 13:21:07.095915 progress 60 % (71 MB)
110 13:21:07.425953 progress 65 % (77 MB)
111 13:21:07.782859 progress 70 % (83 MB)
112 13:21:08.157159 progress 75 % (89 MB)
113 13:21:08.569620 progress 80 % (95 MB)
114 13:21:08.980233 progress 85 % (101 MB)
115 13:21:09.221362 progress 90 % (107 MB)
116 13:21:09.553111 progress 95 % (113 MB)
117 13:21:09.918576 progress 100 % (119 MB)
118 13:21:09.924179 119 MB downloaded in 6.70 s (17.82 MB/s)
119 13:21:09.924493 end: 1.4.1 http-download (duration 00:00:07) [common]
121 13:21:09.924800 end: 1.4 download-retry (duration 00:00:07) [common]
122 13:21:09.924891 start: 1.5 download-retry (timeout 00:09:50) [common]
123 13:21:09.924980 start: 1.5.1 http-download (timeout 00:09:50) [common]
124 13:21:09.925129 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4-14-g09ffd7fb38ff/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 13:21:09.925200 saving as /var/lib/lava/dispatcher/tmp/11445602/tftp-deploy-75s0rxey/modules/modules.tar
126 13:21:09.925261 total size: 8610736 (8 MB)
127 13:21:09.925322 Using unxz to decompress xz
128 13:21:09.929658 progress 0 % (0 MB)
129 13:21:09.950686 progress 5 % (0 MB)
130 13:21:09.974288 progress 10 % (0 MB)
131 13:21:10.003578 progress 15 % (1 MB)
132 13:21:10.031666 progress 20 % (1 MB)
133 13:21:10.055295 progress 25 % (2 MB)
134 13:21:10.079123 progress 30 % (2 MB)
135 13:21:10.103630 progress 35 % (2 MB)
136 13:21:10.130147 progress 40 % (3 MB)
137 13:21:10.156259 progress 45 % (3 MB)
138 13:21:10.181891 progress 50 % (4 MB)
139 13:21:10.207155 progress 55 % (4 MB)
140 13:21:10.232171 progress 60 % (4 MB)
141 13:21:10.256581 progress 65 % (5 MB)
142 13:21:10.280275 progress 70 % (5 MB)
143 13:21:10.307394 progress 75 % (6 MB)
144 13:21:10.331483 progress 80 % (6 MB)
145 13:21:10.357059 progress 85 % (7 MB)
146 13:21:10.381602 progress 90 % (7 MB)
147 13:21:10.405251 progress 95 % (7 MB)
148 13:21:10.431165 progress 100 % (8 MB)
149 13:21:10.437018 8 MB downloaded in 0.51 s (16.05 MB/s)
150 13:21:10.437270 end: 1.5.1 http-download (duration 00:00:01) [common]
152 13:21:10.437532 end: 1.5 download-retry (duration 00:00:01) [common]
153 13:21:10.437623 start: 1.6 prepare-tftp-overlay (timeout 00:09:49) [common]
154 13:21:10.437720 start: 1.6.1 extract-nfsrootfs (timeout 00:09:49) [common]
155 13:21:12.594232 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11445602/extract-nfsrootfs-n61gzwea
156 13:21:12.594442 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 13:21:12.594547 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 13:21:12.594726 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk
159 13:21:12.594860 makedir: /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin
160 13:21:12.594964 makedir: /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/tests
161 13:21:12.595065 makedir: /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/results
162 13:21:12.595169 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-add-keys
163 13:21:12.595316 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-add-sources
164 13:21:12.595446 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-background-process-start
165 13:21:12.595576 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-background-process-stop
166 13:21:12.595704 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-common-functions
167 13:21:12.595830 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-echo-ipv4
168 13:21:12.595956 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-install-packages
169 13:21:12.596081 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-installed-packages
170 13:21:12.596206 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-os-build
171 13:21:12.596331 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-probe-channel
172 13:21:12.596457 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-probe-ip
173 13:21:12.596582 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-target-ip
174 13:21:12.596788 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-target-mac
175 13:21:12.596916 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-target-storage
176 13:21:12.597045 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-test-case
177 13:21:12.597173 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-test-event
178 13:21:12.597298 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-test-feedback
179 13:21:12.597424 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-test-raise
180 13:21:12.597548 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-test-reference
181 13:21:12.597677 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-test-runner
182 13:21:12.597802 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-test-set
183 13:21:12.597927 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-test-shell
184 13:21:12.598056 Updating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-install-packages (oe)
185 13:21:12.598212 Updating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/bin/lava-installed-packages (oe)
186 13:21:12.598337 Creating /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/environment
187 13:21:12.598435 LAVA metadata
188 13:21:12.598507 - LAVA_JOB_ID=11445602
189 13:21:12.598570 - LAVA_DISPATCHER_IP=192.168.201.1
190 13:21:12.598672 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
191 13:21:12.598741 skipped lava-vland-overlay
192 13:21:12.598816 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 13:21:12.598894 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
194 13:21:12.598955 skipped lava-multinode-overlay
195 13:21:12.599026 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 13:21:12.599104 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
197 13:21:12.599176 Loading test definitions
198 13:21:12.599266 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
199 13:21:12.599336 Using /lava-11445602 at stage 0
200 13:21:12.599650 uuid=11445602_1.6.2.3.1 testdef=None
201 13:21:12.599739 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 13:21:12.599822 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
203 13:21:12.600328 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 13:21:12.600549 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
206 13:21:12.601194 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 13:21:12.601422 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
209 13:21:12.602040 runner path: /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/0/tests/0_dmesg test_uuid 11445602_1.6.2.3.1
210 13:21:12.602198 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 13:21:12.602421 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:47) [common]
213 13:21:12.602492 Using /lava-11445602 at stage 1
214 13:21:12.602796 uuid=11445602_1.6.2.3.5 testdef=None
215 13:21:12.602884 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 13:21:12.602968 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
217 13:21:12.603435 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 13:21:12.603650 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
220 13:21:12.604282 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 13:21:12.604507 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
223 13:21:12.605278 runner path: /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/1/tests/1_bootrr test_uuid 11445602_1.6.2.3.5
224 13:21:12.605433 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 13:21:12.605636 Creating lava-test-runner.conf files
227 13:21:12.605698 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/0 for stage 0
228 13:21:12.605788 - 0_dmesg
229 13:21:12.605867 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11445602/lava-overlay-5ujctzzk/lava-11445602/1 for stage 1
230 13:21:12.605957 - 1_bootrr
231 13:21:12.606051 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 13:21:12.606135 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
233 13:21:12.613483 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 13:21:12.613612 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:47) [common]
235 13:21:12.613701 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 13:21:12.613788 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 13:21:12.613873 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:47) [common]
238 13:21:12.734534 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 13:21:12.734926 start: 1.6.4 extract-modules (timeout 00:09:47) [common]
240 13:21:12.735050 extracting modules file /var/lib/lava/dispatcher/tmp/11445602/tftp-deploy-75s0rxey/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11445602/extract-nfsrootfs-n61gzwea
241 13:21:12.959279 extracting modules file /var/lib/lava/dispatcher/tmp/11445602/tftp-deploy-75s0rxey/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11445602/extract-overlay-ramdisk-4hr0wogx/ramdisk
242 13:21:13.199340 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 13:21:13.199518 start: 1.6.5 apply-overlay-tftp (timeout 00:09:47) [common]
244 13:21:13.199612 [common] Applying overlay to NFS
245 13:21:13.199684 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11445602/compress-overlay-pqcpmc55/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11445602/extract-nfsrootfs-n61gzwea
246 13:21:13.207935 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 13:21:13.208082 start: 1.6.6 configure-preseed-file (timeout 00:09:47) [common]
248 13:21:13.208181 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 13:21:13.208267 start: 1.6.7 compress-ramdisk (timeout 00:09:47) [common]
250 13:21:13.208349 Building ramdisk /var/lib/lava/dispatcher/tmp/11445602/extract-overlay-ramdisk-4hr0wogx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11445602/extract-overlay-ramdisk-4hr0wogx/ramdisk
251 13:21:13.536432 >> 119255 blocks
252 13:21:15.441644 rename /var/lib/lava/dispatcher/tmp/11445602/extract-overlay-ramdisk-4hr0wogx/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11445602/tftp-deploy-75s0rxey/ramdisk/ramdisk.cpio.gz
253 13:21:15.442100 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 13:21:15.442224 start: 1.6.8 prepare-kernel (timeout 00:09:44) [common]
255 13:21:15.442330 start: 1.6.8.1 prepare-fit (timeout 00:09:44) [common]
256 13:21:15.442440 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11445602/tftp-deploy-75s0rxey/kernel/Image'
257 13:21:27.824385 Returned 0 in 12 seconds
258 13:21:27.925346 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11445602/tftp-deploy-75s0rxey/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11445602/tftp-deploy-75s0rxey/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11445602/tftp-deploy-75s0rxey/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11445602/tftp-deploy-75s0rxey/kernel/image.itb
259 13:21:28.292810 output: FIT description: Kernel Image image with one or more FDT blobs
260 13:21:28.293184 output: Created: Wed Sep 6 14:21:28 2023
261 13:21:28.293259 output: Image 0 (kernel-1)
262 13:21:28.293326 output: Description:
263 13:21:28.293389 output: Created: Wed Sep 6 14:21:28 2023
264 13:21:28.293449 output: Type: Kernel Image
265 13:21:28.293510 output: Compression: lzma compressed
266 13:21:28.293565 output: Data Size: 11038222 Bytes = 10779.51 KiB = 10.53 MiB
267 13:21:28.293623 output: Architecture: AArch64
268 13:21:28.293681 output: OS: Linux
269 13:21:28.293738 output: Load Address: 0x00000000
270 13:21:28.293790 output: Entry Point: 0x00000000
271 13:21:28.293841 output: Hash algo: crc32
272 13:21:28.293892 output: Hash value: eae831c7
273 13:21:28.293943 output: Image 1 (fdt-1)
274 13:21:28.293994 output: Description: mt8192-asurada-spherion-r0
275 13:21:28.294045 output: Created: Wed Sep 6 14:21:28 2023
276 13:21:28.294096 output: Type: Flat Device Tree
277 13:21:28.294147 output: Compression: uncompressed
278 13:21:28.294198 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 13:21:28.294250 output: Architecture: AArch64
280 13:21:28.294301 output: Hash algo: crc32
281 13:21:28.294351 output: Hash value: cc4352de
282 13:21:28.294401 output: Image 2 (ramdisk-1)
283 13:21:28.294452 output: Description: unavailable
284 13:21:28.294503 output: Created: Wed Sep 6 14:21:28 2023
285 13:21:28.294554 output: Type: RAMDisk Image
286 13:21:28.294605 output: Compression: Unknown Compression
287 13:21:28.294656 output: Data Size: 17774713 Bytes = 17358.12 KiB = 16.95 MiB
288 13:21:28.294708 output: Architecture: AArch64
289 13:21:28.294759 output: OS: Linux
290 13:21:28.294809 output: Load Address: unavailable
291 13:21:28.294860 output: Entry Point: unavailable
292 13:21:28.294911 output: Hash algo: crc32
293 13:21:28.294961 output: Hash value: 6e0de315
294 13:21:28.295012 output: Default Configuration: 'conf-1'
295 13:21:28.295063 output: Configuration 0 (conf-1)
296 13:21:28.295114 output: Description: mt8192-asurada-spherion-r0
297 13:21:28.295165 output: Kernel: kernel-1
298 13:21:28.295215 output: Init Ramdisk: ramdisk-1
299 13:21:28.295266 output: FDT: fdt-1
300 13:21:28.295316 output: Loadables: kernel-1
301 13:21:28.295367 output:
302 13:21:28.295573 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 13:21:28.295671 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 13:21:28.295773 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
305 13:21:28.295866 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:31) [common]
306 13:21:28.295947 No LXC device requested
307 13:21:28.296023 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 13:21:28.296110 start: 1.8 deploy-device-env (timeout 00:09:31) [common]
309 13:21:28.296187 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 13:21:28.296252 Checking files for TFTP limit of 4294967296 bytes.
311 13:21:28.296765 end: 1 tftp-deploy (duration 00:00:29) [common]
312 13:21:28.296872 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 13:21:28.296964 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 13:21:28.297087 substitutions:
315 13:21:28.297153 - {DTB}: 11445602/tftp-deploy-75s0rxey/dtb/mt8192-asurada-spherion-r0.dtb
316 13:21:28.297215 - {INITRD}: 11445602/tftp-deploy-75s0rxey/ramdisk/ramdisk.cpio.gz
317 13:21:28.297272 - {KERNEL}: 11445602/tftp-deploy-75s0rxey/kernel/Image
318 13:21:28.297327 - {LAVA_MAC}: None
319 13:21:28.297384 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11445602/extract-nfsrootfs-n61gzwea
320 13:21:28.297438 - {NFS_SERVER_IP}: 192.168.201.1
321 13:21:28.297492 - {PRESEED_CONFIG}: None
322 13:21:28.297544 - {PRESEED_LOCAL}: None
323 13:21:28.297597 - {RAMDISK}: 11445602/tftp-deploy-75s0rxey/ramdisk/ramdisk.cpio.gz
324 13:21:28.297650 - {ROOT_PART}: None
325 13:21:28.297703 - {ROOT}: None
326 13:21:28.297755 - {SERVER_IP}: 192.168.201.1
327 13:21:28.297806 - {TEE}: None
328 13:21:28.297858 Parsed boot commands:
329 13:21:28.297909 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 13:21:28.298093 Parsed boot commands: tftpboot 192.168.201.1 11445602/tftp-deploy-75s0rxey/kernel/image.itb 11445602/tftp-deploy-75s0rxey/kernel/cmdline
331 13:21:28.298178 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 13:21:28.298260 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 13:21:28.298349 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 13:21:28.298431 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 13:21:28.298500 Not connected, no need to disconnect.
336 13:21:28.298572 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 13:21:28.298653 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 13:21:28.298717 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
339 13:21:28.302810 Setting prompt string to ['lava-test: # ']
340 13:21:28.303168 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 13:21:28.303270 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 13:21:28.303361 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 13:21:28.303448 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 13:21:28.303651 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
345 13:21:33.453301 >> Command sent successfully.
346 13:21:33.463885 Returned 0 in 5 seconds
347 13:21:33.565150 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 13:21:33.566548 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 13:21:33.567161 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 13:21:33.567695 Setting prompt string to 'Starting depthcharge on Spherion...'
352 13:21:33.568043 Changing prompt to 'Starting depthcharge on Spherion...'
353 13:21:33.568411 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 13:21:33.569688 [Enter `^Ec?' for help]
355 13:21:33.732998
356 13:21:33.733501
357 13:21:33.733842 F0: 102B 0000
358 13:21:33.734282
359 13:21:33.734745 F3: 1001 0000 [0200]
360 13:21:33.736639
361 13:21:33.737087 F3: 1001 0000
362 13:21:33.737426
363 13:21:33.737740 F7: 102D 0000
364 13:21:33.738044
365 13:21:33.739277 F1: 0000 0000
366 13:21:33.739700
367 13:21:33.740033 V0: 0000 0000 [0001]
368 13:21:33.740361
369 13:21:33.742775 00: 0007 8000
370 13:21:33.743216
371 13:21:33.743552 01: 0000 0000
372 13:21:33.743872
373 13:21:33.746567 BP: 0C00 0209 [0000]
374 13:21:33.746988
375 13:21:33.747322 G0: 1182 0000
376 13:21:33.747633
377 13:21:33.750251 EC: 0000 0021 [4000]
378 13:21:33.750672
379 13:21:33.751008 S7: 0000 0000 [0000]
380 13:21:33.751320
381 13:21:33.753475 CC: 0000 0000 [0001]
382 13:21:33.753895
383 13:21:33.754233 T0: 0000 0040 [010F]
384 13:21:33.754549
385 13:21:33.754863 Jump to BL
386 13:21:33.755366
387 13:21:33.779961
388 13:21:33.780384
389 13:21:33.780769
390 13:21:33.787243 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 13:21:33.790793 ARM64: Exception handlers installed.
392 13:21:33.794117 ARM64: Testing exception
393 13:21:33.797553 ARM64: Done test exception
394 13:21:33.804316 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 13:21:33.814587 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 13:21:33.821559 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 13:21:33.831399 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 13:21:33.838033 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 13:21:33.844975 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 13:21:33.856640 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 13:21:33.863824 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 13:21:33.882876 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 13:21:33.886536 WDT: Last reset was cold boot
404 13:21:33.889297 SPI1(PAD0) initialized at 2873684 Hz
405 13:21:33.892494 SPI5(PAD0) initialized at 992727 Hz
406 13:21:33.896028 VBOOT: Loading verstage.
407 13:21:33.902384 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 13:21:33.906185 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 13:21:33.909176 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 13:21:33.912637 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 13:21:33.920127 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 13:21:33.926690 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 13:21:33.937450 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
414 13:21:33.937868
415 13:21:33.938200
416 13:21:33.948006 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 13:21:33.950869 ARM64: Exception handlers installed.
418 13:21:33.954481 ARM64: Testing exception
419 13:21:33.954904 ARM64: Done test exception
420 13:21:33.961147 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 13:21:33.964439 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 13:21:33.979521 Probing TPM: . done!
423 13:21:33.980035 TPM ready after 0 ms
424 13:21:33.987112 Connected to device vid:did:rid of 1ae0:0028:00
425 13:21:33.993363 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
426 13:21:34.051229 Initialized TPM device CR50 revision 0
427 13:21:34.063104 tlcl_send_startup: Startup return code is 0
428 13:21:34.063576 TPM: setup succeeded
429 13:21:34.074781 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 13:21:34.083518 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 13:21:34.095951 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 13:21:34.106034 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 13:21:34.109160 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 13:21:34.112839 in-header: 03 07 00 00 08 00 00 00
435 13:21:34.116957 in-data: aa e4 47 04 13 02 00 00
436 13:21:34.120123 Chrome EC: UHEPI supported
437 13:21:34.127548 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 13:21:34.131390 in-header: 03 ad 00 00 08 00 00 00
439 13:21:34.134863 in-data: 00 20 20 08 00 00 00 00
440 13:21:34.135462 Phase 1
441 13:21:34.139140 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 13:21:34.143090 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 13:21:34.150713 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 13:21:34.153933 Recovery requested (1009000e)
445 13:21:34.161483 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 13:21:34.167007 tlcl_extend: response is 0
447 13:21:34.176487 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 13:21:34.181901 tlcl_extend: response is 0
449 13:21:34.188613 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 13:21:34.208908 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
451 13:21:34.215716 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 13:21:34.216218
453 13:21:34.216572
454 13:21:34.225985 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 13:21:34.229995 ARM64: Exception handlers installed.
456 13:21:34.230433 ARM64: Testing exception
457 13:21:34.233494 ARM64: Done test exception
458 13:21:34.254177 pmic_efuse_setting: Set efuses in 11 msecs
459 13:21:34.258014 pmwrap_interface_init: Select PMIF_VLD_RDY
460 13:21:34.264758 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 13:21:34.267975 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 13:21:34.274608 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 13:21:34.278282 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 13:21:34.282032 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 13:21:34.289002 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 13:21:34.292387 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 13:21:34.296407 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 13:21:34.303387 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 13:21:34.307147 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 13:21:34.310088 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 13:21:34.314316 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 13:21:34.321896 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 13:21:34.325330 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 13:21:34.333178 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 13:21:34.336912 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 13:21:34.344501 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 13:21:34.351198 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 13:21:34.355428 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 13:21:34.362268 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 13:21:34.366094 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 13:21:34.373010 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 13:21:34.376577 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 13:21:34.384349 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 13:21:34.388093 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 13:21:34.395581 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 13:21:34.399022 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 13:21:34.402927 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 13:21:34.410545 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 13:21:34.413843 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 13:21:34.417542 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 13:21:34.424791 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 13:21:34.429144 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 13:21:34.432312 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 13:21:34.439923 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 13:21:34.443327 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 13:21:34.450856 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 13:21:34.454239 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 13:21:34.458423 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 13:21:34.462032 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 13:21:34.465422 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 13:21:34.469260 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 13:21:34.476863 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 13:21:34.480545 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 13:21:34.484710 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 13:21:34.487982 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 13:21:34.491851 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 13:21:34.496039 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 13:21:34.502608 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 13:21:34.506070 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 13:21:34.510267 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 13:21:34.517488 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 13:21:34.525158 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 13:21:34.528923 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 13:21:34.540539 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 13:21:34.547197 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 13:21:34.551534 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 13:21:34.554793 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 13:21:34.562340 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 13:21:34.566075 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x12
520 13:21:34.573408 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 13:21:34.577095 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
522 13:21:34.580757 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 13:21:34.592610 [RTC]rtc_get_frequency_meter,154: input=15, output=790
524 13:21:34.601573 [RTC]rtc_get_frequency_meter,154: input=23, output=979
525 13:21:34.611067 [RTC]rtc_get_frequency_meter,154: input=19, output=883
526 13:21:34.620447 [RTC]rtc_get_frequency_meter,154: input=17, output=838
527 13:21:34.629808 [RTC]rtc_get_frequency_meter,154: input=16, output=813
528 13:21:34.639811 [RTC]rtc_get_frequency_meter,154: input=15, output=789
529 13:21:34.649777 [RTC]rtc_get_frequency_meter,154: input=16, output=815
530 13:21:34.653487 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
531 13:21:34.656903 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
532 13:21:34.660755 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 13:21:34.668501 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 13:21:34.672379 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 13:21:34.675914 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 13:21:34.679331 ADC[4]: Raw value=902066 ID=7
537 13:21:34.679751 ADC[3]: Raw value=212967 ID=1
538 13:21:34.683356 RAM Code: 0x71
539 13:21:34.687009 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 13:21:34.691075 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 13:21:34.698562 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 13:21:34.705958 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 13:21:34.709693 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 13:21:34.713487 in-header: 03 07 00 00 08 00 00 00
545 13:21:34.717607 in-data: aa e4 47 04 13 02 00 00
546 13:21:34.721049 Chrome EC: UHEPI supported
547 13:21:34.724412 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 13:21:34.728182 in-header: 03 ed 00 00 08 00 00 00
549 13:21:34.732069 in-data: 80 20 60 08 00 00 00 00
550 13:21:34.735905 MRC: failed to locate region type 0.
551 13:21:34.742897 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 13:21:34.746937 DRAM-K: Running full calibration
553 13:21:34.750840 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 13:21:34.754384 header.status = 0x0
555 13:21:34.758436 header.version = 0x6 (expected: 0x6)
556 13:21:34.762197 header.size = 0xd00 (expected: 0xd00)
557 13:21:34.762618 header.flags = 0x0
558 13:21:34.769081 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 13:21:34.786493 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
560 13:21:34.793542 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 13:21:34.797400 dram_init: ddr_geometry: 2
562 13:21:34.797904 [EMI] MDL number = 2
563 13:21:34.801282 [EMI] Get MDL freq = 0
564 13:21:34.801789 dram_init: ddr_type: 0
565 13:21:34.804997 is_discrete_lpddr4: 1
566 13:21:34.808744 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 13:21:34.809143
568 13:21:34.809478
569 13:21:34.809799 [Bian_co] ETT version 0.0.0.1
570 13:21:34.815903 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 13:21:34.816335
572 13:21:34.819863 dramc_set_vcore_voltage set vcore to 650000
573 13:21:34.820376 Read voltage for 800, 4
574 13:21:34.820779 Vio18 = 0
575 13:21:34.823482 Vcore = 650000
576 13:21:34.823920 Vdram = 0
577 13:21:34.824256 Vddq = 0
578 13:21:34.827198 Vmddr = 0
579 13:21:34.827645 dram_init: config_dvfs: 1
580 13:21:34.834780 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 13:21:34.838402 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 13:21:34.842550 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
583 13:21:34.845744 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
584 13:21:34.849183 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
585 13:21:34.852519 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
586 13:21:34.855815 MEM_TYPE=3, freq_sel=18
587 13:21:34.859319 sv_algorithm_assistance_LP4_1600
588 13:21:34.862464 ============ PULL DRAM RESETB DOWN ============
589 13:21:34.866053 ========== PULL DRAM RESETB DOWN end =========
590 13:21:34.872425 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 13:21:34.876032 ===================================
592 13:21:34.876615 LPDDR4 DRAM CONFIGURATION
593 13:21:34.879259 ===================================
594 13:21:34.882425 EX_ROW_EN[0] = 0x0
595 13:21:34.885930 EX_ROW_EN[1] = 0x0
596 13:21:34.886496 LP4Y_EN = 0x0
597 13:21:34.889151 WORK_FSP = 0x0
598 13:21:34.889742 WL = 0x2
599 13:21:34.892494 RL = 0x2
600 13:21:34.892994 BL = 0x2
601 13:21:34.896382 RPST = 0x0
602 13:21:34.896952 RD_PRE = 0x0
603 13:21:34.899375 WR_PRE = 0x1
604 13:21:34.899931 WR_PST = 0x0
605 13:21:34.902835 DBI_WR = 0x0
606 13:21:34.903406 DBI_RD = 0x0
607 13:21:34.906533 OTF = 0x1
608 13:21:34.909392 ===================================
609 13:21:34.912974 ===================================
610 13:21:34.913396 ANA top config
611 13:21:34.916560 ===================================
612 13:21:34.919915 DLL_ASYNC_EN = 0
613 13:21:34.922890 ALL_SLAVE_EN = 1
614 13:21:34.923366 NEW_RANK_MODE = 1
615 13:21:34.926559 DLL_IDLE_MODE = 1
616 13:21:34.929841 LP45_APHY_COMB_EN = 1
617 13:21:34.933032 TX_ODT_DIS = 1
618 13:21:34.933456 NEW_8X_MODE = 1
619 13:21:34.936828 ===================================
620 13:21:34.939514 ===================================
621 13:21:34.943098 data_rate = 1600
622 13:21:34.947015 CKR = 1
623 13:21:34.949734 DQ_P2S_RATIO = 8
624 13:21:34.953351 ===================================
625 13:21:34.956863 CA_P2S_RATIO = 8
626 13:21:34.959747 DQ_CA_OPEN = 0
627 13:21:34.960193 DQ_SEMI_OPEN = 0
628 13:21:34.963402 CA_SEMI_OPEN = 0
629 13:21:34.966634 CA_FULL_RATE = 0
630 13:21:34.970207 DQ_CKDIV4_EN = 1
631 13:21:34.973462 CA_CKDIV4_EN = 1
632 13:21:34.976643 CA_PREDIV_EN = 0
633 13:21:34.977249 PH8_DLY = 0
634 13:21:34.980203 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 13:21:34.984057 DQ_AAMCK_DIV = 4
636 13:21:34.986936 CA_AAMCK_DIV = 4
637 13:21:34.989827 CA_ADMCK_DIV = 4
638 13:21:34.990434 DQ_TRACK_CA_EN = 0
639 13:21:34.993574 CA_PICK = 800
640 13:21:34.996924 CA_MCKIO = 800
641 13:21:35.000099 MCKIO_SEMI = 0
642 13:21:35.003838 PLL_FREQ = 3068
643 13:21:35.007319 DQ_UI_PI_RATIO = 32
644 13:21:35.007875 CA_UI_PI_RATIO = 0
645 13:21:35.011285 ===================================
646 13:21:35.015233 ===================================
647 13:21:35.018562 memory_type:LPDDR4
648 13:21:35.019059 GP_NUM : 10
649 13:21:35.022043 SRAM_EN : 1
650 13:21:35.022466 MD32_EN : 0
651 13:21:35.025762 ===================================
652 13:21:35.029583 [ANA_INIT] >>>>>>>>>>>>>>
653 13:21:35.033323 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 13:21:35.036591 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 13:21:35.040521 ===================================
656 13:21:35.041028 data_rate = 1600,PCW = 0X7600
657 13:21:35.043634 ===================================
658 13:21:35.047458 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 13:21:35.054121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 13:21:35.060417 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 13:21:35.064414 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 13:21:35.067320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 13:21:35.070719 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 13:21:35.074302 [ANA_INIT] flow start
665 13:21:35.074798 [ANA_INIT] PLL >>>>>>>>
666 13:21:35.077429 [ANA_INIT] PLL <<<<<<<<
667 13:21:35.081474 [ANA_INIT] MIDPI >>>>>>>>
668 13:21:35.081941 [ANA_INIT] MIDPI <<<<<<<<
669 13:21:35.084587 [ANA_INIT] DLL >>>>>>>>
670 13:21:35.087860 [ANA_INIT] flow end
671 13:21:35.090926 ============ LP4 DIFF to SE enter ============
672 13:21:35.094270 ============ LP4 DIFF to SE exit ============
673 13:21:35.097908 [ANA_INIT] <<<<<<<<<<<<<
674 13:21:35.101368 [Flow] Enable top DCM control >>>>>
675 13:21:35.104490 [Flow] Enable top DCM control <<<<<
676 13:21:35.108001 Enable DLL master slave shuffle
677 13:21:35.111373 ==============================================================
678 13:21:35.114539 Gating Mode config
679 13:21:35.121206 ==============================================================
680 13:21:35.121627 Config description:
681 13:21:35.131194 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 13:21:35.138091 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 13:21:35.141476 SELPH_MODE 0: By rank 1: By Phase
684 13:21:35.147973 ==============================================================
685 13:21:35.151539 GAT_TRACK_EN = 1
686 13:21:35.154836 RX_GATING_MODE = 2
687 13:21:35.158142 RX_GATING_TRACK_MODE = 2
688 13:21:35.161553 SELPH_MODE = 1
689 13:21:35.162036 PICG_EARLY_EN = 1
690 13:21:35.165114 VALID_LAT_VALUE = 1
691 13:21:35.171730 ==============================================================
692 13:21:35.174479 Enter into Gating configuration >>>>
693 13:21:35.178021 Exit from Gating configuration <<<<
694 13:21:35.181858 Enter into DVFS_PRE_config >>>>>
695 13:21:35.191768 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 13:21:35.194595 Exit from DVFS_PRE_config <<<<<
697 13:21:35.198587 Enter into PICG configuration >>>>
698 13:21:35.201605 Exit from PICG configuration <<<<
699 13:21:35.204959 [RX_INPUT] configuration >>>>>
700 13:21:35.208364 [RX_INPUT] configuration <<<<<
701 13:21:35.211648 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 13:21:35.218144 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 13:21:35.225618 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 13:21:35.228998 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 13:21:35.236323 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 13:21:35.242420 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 13:21:35.245766 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 13:21:35.249032 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 13:21:35.256105 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 13:21:35.259116 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 13:21:35.262701 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 13:21:35.266263 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 13:21:35.269350 ===================================
714 13:21:35.272764 LPDDR4 DRAM CONFIGURATION
715 13:21:35.276204 ===================================
716 13:21:35.279827 EX_ROW_EN[0] = 0x0
717 13:21:35.279902 EX_ROW_EN[1] = 0x0
718 13:21:35.282987 LP4Y_EN = 0x0
719 13:21:35.283073 WORK_FSP = 0x0
720 13:21:35.285986 WL = 0x2
721 13:21:35.286057 RL = 0x2
722 13:21:35.289582 BL = 0x2
723 13:21:35.289679 RPST = 0x0
724 13:21:35.293158 RD_PRE = 0x0
725 13:21:35.293233 WR_PRE = 0x1
726 13:21:35.296104 WR_PST = 0x0
727 13:21:35.296199 DBI_WR = 0x0
728 13:21:35.299436 DBI_RD = 0x0
729 13:21:35.299505 OTF = 0x1
730 13:21:35.303054 ===================================
731 13:21:35.306065 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 13:21:35.312950 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 13:21:35.316410 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 13:21:35.319622 ===================================
735 13:21:35.323012 LPDDR4 DRAM CONFIGURATION
736 13:21:35.326637 ===================================
737 13:21:35.326709 EX_ROW_EN[0] = 0x10
738 13:21:35.329786 EX_ROW_EN[1] = 0x0
739 13:21:35.332996 LP4Y_EN = 0x0
740 13:21:35.333097 WORK_FSP = 0x0
741 13:21:35.336524 WL = 0x2
742 13:21:35.336630 RL = 0x2
743 13:21:35.340220 BL = 0x2
744 13:21:35.340326 RPST = 0x0
745 13:21:35.343666 RD_PRE = 0x0
746 13:21:35.343740 WR_PRE = 0x1
747 13:21:35.347056 WR_PST = 0x0
748 13:21:35.347127 DBI_WR = 0x0
749 13:21:35.349778 DBI_RD = 0x0
750 13:21:35.349878 OTF = 0x1
751 13:21:35.353062 ===================================
752 13:21:35.360179 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 13:21:35.363972 nWR fixed to 40
754 13:21:35.367242 [ModeRegInit_LP4] CH0 RK0
755 13:21:35.367340 [ModeRegInit_LP4] CH0 RK1
756 13:21:35.370687 [ModeRegInit_LP4] CH1 RK0
757 13:21:35.373848 [ModeRegInit_LP4] CH1 RK1
758 13:21:35.373923 match AC timing 13
759 13:21:35.380486 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 13:21:35.383805 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 13:21:35.387677 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 13:21:35.394033 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 13:21:35.397506 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 13:21:35.397606 [EMI DOE] emi_dcm 0
765 13:21:35.404171 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 13:21:35.404269 ==
767 13:21:35.407465 Dram Type= 6, Freq= 0, CH_0, rank 0
768 13:21:35.410888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 13:21:35.410985 ==
770 13:21:35.417381 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 13:21:35.420793 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 13:21:35.431418 [CA 0] Center 37 (7~68) winsize 62
773 13:21:35.434398 [CA 1] Center 37 (6~68) winsize 63
774 13:21:35.437845 [CA 2] Center 35 (5~66) winsize 62
775 13:21:35.441531 [CA 3] Center 34 (4~65) winsize 62
776 13:21:35.444487 [CA 4] Center 34 (4~65) winsize 62
777 13:21:35.447991 [CA 5] Center 34 (4~64) winsize 61
778 13:21:35.448063
779 13:21:35.451764 [CmdBusTrainingLP45] Vref(ca) range 1: 34
780 13:21:35.451860
781 13:21:35.454581 [CATrainingPosCal] consider 1 rank data
782 13:21:35.458240 u2DelayCellTimex100 = 270/100 ps
783 13:21:35.461583 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
784 13:21:35.464809 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
785 13:21:35.468063 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
786 13:21:35.471576 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
787 13:21:35.478426 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
788 13:21:35.481446 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
789 13:21:35.481518
790 13:21:35.484829 CA PerBit enable=1, Macro0, CA PI delay=34
791 13:21:35.484903
792 13:21:35.488595 [CBTSetCACLKResult] CA Dly = 34
793 13:21:35.488732 CS Dly: 5 (0~36)
794 13:21:35.488821 ==
795 13:21:35.492067 Dram Type= 6, Freq= 0, CH_0, rank 1
796 13:21:35.495350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 13:21:35.498309 ==
798 13:21:35.502041 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 13:21:35.508606 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 13:21:35.517608 [CA 0] Center 37 (6~68) winsize 63
801 13:21:35.520856 [CA 1] Center 37 (6~68) winsize 63
802 13:21:35.524077 [CA 2] Center 35 (5~66) winsize 62
803 13:21:35.527641 [CA 3] Center 35 (4~66) winsize 63
804 13:21:35.530933 [CA 4] Center 34 (3~65) winsize 63
805 13:21:35.534082 [CA 5] Center 33 (3~64) winsize 62
806 13:21:35.534156
807 13:21:35.537647 [CmdBusTrainingLP45] Vref(ca) range 1: 34
808 13:21:35.537719
809 13:21:35.540935 [CATrainingPosCal] consider 2 rank data
810 13:21:35.544487 u2DelayCellTimex100 = 270/100 ps
811 13:21:35.547857 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
812 13:21:35.550788 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
813 13:21:35.554609 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
814 13:21:35.561350 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
815 13:21:35.564603 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
816 13:21:35.567422 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
817 13:21:35.567518
818 13:21:35.571009 CA PerBit enable=1, Macro0, CA PI delay=34
819 13:21:35.571101
820 13:21:35.574885 [CBTSetCACLKResult] CA Dly = 34
821 13:21:35.574967 CS Dly: 6 (0~38)
822 13:21:35.575030
823 13:21:35.577519 ----->DramcWriteLeveling(PI) begin...
824 13:21:35.577623 ==
825 13:21:35.581155 Dram Type= 6, Freq= 0, CH_0, rank 0
826 13:21:35.588699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 13:21:35.588795 ==
828 13:21:35.588857 Write leveling (Byte 0): 29 => 29
829 13:21:35.591781 Write leveling (Byte 1): 29 => 29
830 13:21:35.595964 DramcWriteLeveling(PI) end<-----
831 13:21:35.596043
832 13:21:35.596106 ==
833 13:21:35.599530 Dram Type= 6, Freq= 0, CH_0, rank 0
834 13:21:35.603008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 13:21:35.603083 ==
836 13:21:35.606636 [Gating] SW mode calibration
837 13:21:35.613136 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 13:21:35.617004 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 13:21:35.624317 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 13:21:35.627874 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
841 13:21:35.630894 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
842 13:21:35.637776 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 13:21:35.640858 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 13:21:35.644153 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 13:21:35.651021 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 13:21:35.654724 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 13:21:35.657819 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 13:21:35.661202 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 13:21:35.667626 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 13:21:35.671567 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 13:21:35.674222 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 13:21:35.681725 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 13:21:35.684353 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 13:21:35.687879 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 13:21:35.694628 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 13:21:35.698000 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 13:21:35.701272 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
858 13:21:35.707909 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 13:21:35.711359 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 13:21:35.714867 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 13:21:35.718075 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 13:21:35.725265 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 13:21:35.728233 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 13:21:35.731946 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 13:21:35.739171 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 13:21:35.741530 0 9 12 | B1->B0 | 2d2d 3333 | 0 0 | (0 0) (0 0)
867 13:21:35.745032 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 13:21:35.751913 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 13:21:35.755064 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 13:21:35.758542 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 13:21:35.765021 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 13:21:35.768622 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
873 13:21:35.771876 0 10 8 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 1)
874 13:21:35.775307 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
875 13:21:35.781721 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 13:21:35.785571 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 13:21:35.788378 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 13:21:35.795187 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 13:21:35.798622 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 13:21:35.802001 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
881 13:21:35.808644 0 11 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
882 13:21:35.812395 0 11 12 | B1->B0 | 3939 4343 | 0 0 | (0 0) (0 0)
883 13:21:35.815523 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 13:21:35.822562 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 13:21:35.825682 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 13:21:35.829267 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 13:21:35.832426 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 13:21:35.839261 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
889 13:21:35.842564 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
890 13:21:35.846290 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
891 13:21:35.852553 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 13:21:35.855925 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 13:21:35.859010 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 13:21:35.866164 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 13:21:35.869167 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 13:21:35.872781 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 13:21:35.879777 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 13:21:35.882593 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 13:21:35.886396 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 13:21:35.889661 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 13:21:35.896298 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 13:21:35.899721 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 13:21:35.903241 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 13:21:35.909398 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 13:21:35.913013 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
906 13:21:35.916258 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
907 13:21:35.919768 Total UI for P1: 0, mck2ui 16
908 13:21:35.922952 best dqsien dly found for B0: ( 0, 14, 8)
909 13:21:35.929573 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
910 13:21:35.929673 Total UI for P1: 0, mck2ui 16
911 13:21:35.936395 best dqsien dly found for B1: ( 0, 14, 10)
912 13:21:35.939725 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
913 13:21:35.943105 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
914 13:21:35.943186
915 13:21:35.947158 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
916 13:21:35.949765 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
917 13:21:35.953447 [Gating] SW calibration Done
918 13:21:35.953528 ==
919 13:21:35.957120 Dram Type= 6, Freq= 0, CH_0, rank 0
920 13:21:35.959880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 13:21:35.959962 ==
922 13:21:35.963299 RX Vref Scan: 0
923 13:21:35.963380
924 13:21:35.963443 RX Vref 0 -> 0, step: 1
925 13:21:35.963503
926 13:21:35.967126 RX Delay -130 -> 252, step: 16
927 13:21:35.970270 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
928 13:21:35.973713 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
929 13:21:35.980066 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
930 13:21:35.983506 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
931 13:21:35.987298 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
932 13:21:35.990758 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
933 13:21:35.993785 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
934 13:21:36.000076 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
935 13:21:36.003595 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
936 13:21:36.007061 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
937 13:21:36.010784 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
938 13:21:36.014313 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
939 13:21:36.020300 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
940 13:21:36.024002 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
941 13:21:36.027101 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
942 13:21:36.030518 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
943 13:21:36.030594 ==
944 13:21:36.033910 Dram Type= 6, Freq= 0, CH_0, rank 0
945 13:21:36.037378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
946 13:21:36.040465 ==
947 13:21:36.040573 DQS Delay:
948 13:21:36.040691 DQS0 = 0, DQS1 = 0
949 13:21:36.044024 DQM Delay:
950 13:21:36.044110 DQM0 = 86, DQM1 = 76
951 13:21:36.044175 DQ Delay:
952 13:21:36.047501 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
953 13:21:36.050556 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
954 13:21:36.054179 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
955 13:21:36.057408 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
956 13:21:36.057487
957 13:21:36.057549
958 13:21:36.060941 ==
959 13:21:36.064294 Dram Type= 6, Freq= 0, CH_0, rank 0
960 13:21:36.067576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 13:21:36.067691 ==
962 13:21:36.067782
963 13:21:36.067868
964 13:21:36.071045 TX Vref Scan disable
965 13:21:36.071143 == TX Byte 0 ==
966 13:21:36.074214 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
967 13:21:36.080553 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
968 13:21:36.080674 == TX Byte 1 ==
969 13:21:36.084308 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
970 13:21:36.090796 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
971 13:21:36.090870 ==
972 13:21:36.094330 Dram Type= 6, Freq= 0, CH_0, rank 0
973 13:21:36.097370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 13:21:36.097445 ==
975 13:21:36.110472 TX Vref=22, minBit 5, minWin=27, winSum=441
976 13:21:36.113886 TX Vref=24, minBit 5, minWin=27, winSum=444
977 13:21:36.117256 TX Vref=26, minBit 0, minWin=27, winSum=444
978 13:21:36.120641 TX Vref=28, minBit 0, minWin=28, winSum=452
979 13:21:36.124342 TX Vref=30, minBit 3, minWin=27, winSum=450
980 13:21:36.127320 TX Vref=32, minBit 2, minWin=28, winSum=451
981 13:21:36.133906 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 28
982 13:21:36.134009
983 13:21:36.137526 Final TX Range 1 Vref 28
984 13:21:36.137607
985 13:21:36.137670 ==
986 13:21:36.141173 Dram Type= 6, Freq= 0, CH_0, rank 0
987 13:21:36.144232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 13:21:36.144313 ==
989 13:21:36.144377
990 13:21:36.147528
991 13:21:36.147608 TX Vref Scan disable
992 13:21:36.150854 == TX Byte 0 ==
993 13:21:36.154676 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
994 13:21:36.158133 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
995 13:21:36.161158 == TX Byte 1 ==
996 13:21:36.164214 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
997 13:21:36.167703 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
998 13:21:36.167784
999 13:21:36.170814 [DATLAT]
1000 13:21:36.170894 Freq=800, CH0 RK0
1001 13:21:36.170959
1002 13:21:36.174433 DATLAT Default: 0xa
1003 13:21:36.174514 0, 0xFFFF, sum = 0
1004 13:21:36.177716 1, 0xFFFF, sum = 0
1005 13:21:36.177801 2, 0xFFFF, sum = 0
1006 13:21:36.180977 3, 0xFFFF, sum = 0
1007 13:21:36.181059 4, 0xFFFF, sum = 0
1008 13:21:36.185016 5, 0xFFFF, sum = 0
1009 13:21:36.185097 6, 0xFFFF, sum = 0
1010 13:21:36.187695 7, 0xFFFF, sum = 0
1011 13:21:36.187777 8, 0xFFFF, sum = 0
1012 13:21:36.191214 9, 0x0, sum = 1
1013 13:21:36.191295 10, 0x0, sum = 2
1014 13:21:36.194675 11, 0x0, sum = 3
1015 13:21:36.194790 12, 0x0, sum = 4
1016 13:21:36.198091 best_step = 10
1017 13:21:36.198170
1018 13:21:36.198234 ==
1019 13:21:36.201764 Dram Type= 6, Freq= 0, CH_0, rank 0
1020 13:21:36.204784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1021 13:21:36.204868 ==
1022 13:21:36.204933 RX Vref Scan: 1
1023 13:21:36.208303
1024 13:21:36.208384 Set Vref Range= 32 -> 127
1025 13:21:36.208453
1026 13:21:36.211258 RX Vref 32 -> 127, step: 1
1027 13:21:36.211337
1028 13:21:36.214666 RX Delay -111 -> 252, step: 8
1029 13:21:36.214746
1030 13:21:36.218036 Set Vref, RX VrefLevel [Byte0]: 32
1031 13:21:36.221713 [Byte1]: 32
1032 13:21:36.221792
1033 13:21:36.224709 Set Vref, RX VrefLevel [Byte0]: 33
1034 13:21:36.228803 [Byte1]: 33
1035 13:21:36.228882
1036 13:21:36.232143 Set Vref, RX VrefLevel [Byte0]: 34
1037 13:21:36.235208 [Byte1]: 34
1038 13:21:36.238474
1039 13:21:36.238579 Set Vref, RX VrefLevel [Byte0]: 35
1040 13:21:36.241905 [Byte1]: 35
1041 13:21:36.246215
1042 13:21:36.246290 Set Vref, RX VrefLevel [Byte0]: 36
1043 13:21:36.249869 [Byte1]: 36
1044 13:21:36.254631
1045 13:21:36.254710 Set Vref, RX VrefLevel [Byte0]: 37
1046 13:21:36.257977 [Byte1]: 37
1047 13:21:36.261799
1048 13:21:36.261878 Set Vref, RX VrefLevel [Byte0]: 38
1049 13:21:36.265658 [Byte1]: 38
1050 13:21:36.270321
1051 13:21:36.270403 Set Vref, RX VrefLevel [Byte0]: 39
1052 13:21:36.273105 [Byte1]: 39
1053 13:21:36.277414
1054 13:21:36.277497 Set Vref, RX VrefLevel [Byte0]: 40
1055 13:21:36.280927 [Byte1]: 40
1056 13:21:36.284782
1057 13:21:36.284861 Set Vref, RX VrefLevel [Byte0]: 41
1058 13:21:36.288460 [Byte1]: 41
1059 13:21:36.292337
1060 13:21:36.292416 Set Vref, RX VrefLevel [Byte0]: 42
1061 13:21:36.295410 [Byte1]: 42
1062 13:21:36.300125
1063 13:21:36.300203 Set Vref, RX VrefLevel [Byte0]: 43
1064 13:21:36.303310 [Byte1]: 43
1065 13:21:36.307446
1066 13:21:36.307525 Set Vref, RX VrefLevel [Byte0]: 44
1067 13:21:36.310724 [Byte1]: 44
1068 13:21:36.315421
1069 13:21:36.315502 Set Vref, RX VrefLevel [Byte0]: 45
1070 13:21:36.318705 [Byte1]: 45
1071 13:21:36.323075
1072 13:21:36.323155 Set Vref, RX VrefLevel [Byte0]: 46
1073 13:21:36.325939 [Byte1]: 46
1074 13:21:36.330181
1075 13:21:36.330260 Set Vref, RX VrefLevel [Byte0]: 47
1076 13:21:36.333568 [Byte1]: 47
1077 13:21:36.338075
1078 13:21:36.338155 Set Vref, RX VrefLevel [Byte0]: 48
1079 13:21:36.341372 [Byte1]: 48
1080 13:21:36.346026
1081 13:21:36.346105 Set Vref, RX VrefLevel [Byte0]: 49
1082 13:21:36.349253 [Byte1]: 49
1083 13:21:36.353189
1084 13:21:36.353269 Set Vref, RX VrefLevel [Byte0]: 50
1085 13:21:36.356531 [Byte1]: 50
1086 13:21:36.360844
1087 13:21:36.360941 Set Vref, RX VrefLevel [Byte0]: 51
1088 13:21:36.364307 [Byte1]: 51
1089 13:21:36.368541
1090 13:21:36.368620 Set Vref, RX VrefLevel [Byte0]: 52
1091 13:21:36.372027 [Byte1]: 52
1092 13:21:36.376404
1093 13:21:36.376483 Set Vref, RX VrefLevel [Byte0]: 53
1094 13:21:36.379402 [Byte1]: 53
1095 13:21:36.384239
1096 13:21:36.384319 Set Vref, RX VrefLevel [Byte0]: 54
1097 13:21:36.387257 [Byte1]: 54
1098 13:21:36.391592
1099 13:21:36.391671 Set Vref, RX VrefLevel [Byte0]: 55
1100 13:21:36.394842 [Byte1]: 55
1101 13:21:36.399302
1102 13:21:36.399382 Set Vref, RX VrefLevel [Byte0]: 56
1103 13:21:36.402936 [Byte1]: 56
1104 13:21:36.407000
1105 13:21:36.407080 Set Vref, RX VrefLevel [Byte0]: 57
1106 13:21:36.410215 [Byte1]: 57
1107 13:21:36.414503
1108 13:21:36.414582 Set Vref, RX VrefLevel [Byte0]: 58
1109 13:21:36.418485 [Byte1]: 58
1110 13:21:36.422555
1111 13:21:36.422634 Set Vref, RX VrefLevel [Byte0]: 59
1112 13:21:36.425460 [Byte1]: 59
1113 13:21:36.429668
1114 13:21:36.429747 Set Vref, RX VrefLevel [Byte0]: 60
1115 13:21:36.433131 [Byte1]: 60
1116 13:21:36.437550
1117 13:21:36.437629 Set Vref, RX VrefLevel [Byte0]: 61
1118 13:21:36.440976 [Byte1]: 61
1119 13:21:36.445577
1120 13:21:36.445657 Set Vref, RX VrefLevel [Byte0]: 62
1121 13:21:36.448296 [Byte1]: 62
1122 13:21:36.453013
1123 13:21:36.453092 Set Vref, RX VrefLevel [Byte0]: 63
1124 13:21:36.456868 [Byte1]: 63
1125 13:21:36.460612
1126 13:21:36.460744 Set Vref, RX VrefLevel [Byte0]: 64
1127 13:21:36.463806 [Byte1]: 64
1128 13:21:36.467919
1129 13:21:36.467999 Set Vref, RX VrefLevel [Byte0]: 65
1130 13:21:36.471450 [Byte1]: 65
1131 13:21:36.475915
1132 13:21:36.475994 Set Vref, RX VrefLevel [Byte0]: 66
1133 13:21:36.478710 [Byte1]: 66
1134 13:21:36.483084
1135 13:21:36.483172 Set Vref, RX VrefLevel [Byte0]: 67
1136 13:21:36.486728 [Byte1]: 67
1137 13:21:36.491105
1138 13:21:36.491174 Set Vref, RX VrefLevel [Byte0]: 68
1139 13:21:36.494250 [Byte1]: 68
1140 13:21:36.498811
1141 13:21:36.498891 Set Vref, RX VrefLevel [Byte0]: 69
1142 13:21:36.502017 [Byte1]: 69
1143 13:21:36.506626
1144 13:21:36.506716 Set Vref, RX VrefLevel [Byte0]: 70
1145 13:21:36.510007 [Byte1]: 70
1146 13:21:36.513654
1147 13:21:36.513735 Set Vref, RX VrefLevel [Byte0]: 71
1148 13:21:36.517386 [Byte1]: 71
1149 13:21:36.521595
1150 13:21:36.521674 Set Vref, RX VrefLevel [Byte0]: 72
1151 13:21:36.525019 [Byte1]: 72
1152 13:21:36.529053
1153 13:21:36.529131 Set Vref, RX VrefLevel [Byte0]: 73
1154 13:21:36.532386 [Byte1]: 73
1155 13:21:36.537030
1156 13:21:36.537109 Set Vref, RX VrefLevel [Byte0]: 74
1157 13:21:36.540498 [Byte1]: 74
1158 13:21:36.544721
1159 13:21:36.544800 Set Vref, RX VrefLevel [Byte0]: 75
1160 13:21:36.547659 [Byte1]: 75
1161 13:21:36.552091
1162 13:21:36.552170 Final RX Vref Byte 0 = 59 to rank0
1163 13:21:36.555318 Final RX Vref Byte 1 = 55 to rank0
1164 13:21:36.559327 Final RX Vref Byte 0 = 59 to rank1
1165 13:21:36.562658 Final RX Vref Byte 1 = 55 to rank1==
1166 13:21:36.566060 Dram Type= 6, Freq= 0, CH_0, rank 0
1167 13:21:36.569082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1168 13:21:36.572348 ==
1169 13:21:36.572427 DQS Delay:
1170 13:21:36.572492 DQS0 = 0, DQS1 = 0
1171 13:21:36.575929 DQM Delay:
1172 13:21:36.576008 DQM0 = 87, DQM1 = 79
1173 13:21:36.576071 DQ Delay:
1174 13:21:36.579340 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1175 13:21:36.582729 DQ4 =92, DQ5 =76, DQ6 =92, DQ7 =92
1176 13:21:36.585882 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1177 13:21:36.588984 DQ12 =88, DQ13 =80, DQ14 =92, DQ15 =88
1178 13:21:36.589063
1179 13:21:36.589125
1180 13:21:36.599680 [DQSOSCAuto] RK0, (LSB)MR18= 0x250c, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1181 13:21:36.603460 CH0 RK0: MR19=606, MR18=250C
1182 13:21:36.605899 CH0_RK0: MR19=0x606, MR18=0x250C, DQSOSC=400, MR23=63, INC=92, DEC=61
1183 13:21:36.609178
1184 13:21:36.612702 ----->DramcWriteLeveling(PI) begin...
1185 13:21:36.612774 ==
1186 13:21:36.616208 Dram Type= 6, Freq= 0, CH_0, rank 1
1187 13:21:36.619529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1188 13:21:36.619626 ==
1189 13:21:36.622669 Write leveling (Byte 0): 30 => 30
1190 13:21:36.626056 Write leveling (Byte 1): 30 => 30
1191 13:21:36.629913 DramcWriteLeveling(PI) end<-----
1192 13:21:36.630008
1193 13:21:36.630094 ==
1194 13:21:36.632917 Dram Type= 6, Freq= 0, CH_0, rank 1
1195 13:21:36.636025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1196 13:21:36.636124 ==
1197 13:21:36.639690 [Gating] SW mode calibration
1198 13:21:36.646104 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1199 13:21:36.649861 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1200 13:21:36.656290 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1201 13:21:36.659843 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1202 13:21:36.662924 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 13:21:36.710229 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 13:21:36.710349 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 13:21:36.710626 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 13:21:36.710719 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 13:21:36.711001 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 13:21:36.711448 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 13:21:36.711542 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 13:21:36.711810 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 13:21:36.712143 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 13:21:36.712512 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 13:21:36.751855 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 13:21:36.751964 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 13:21:36.752340 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 13:21:36.752660 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 13:21:36.753057 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1218 13:21:36.753573 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1219 13:21:36.753642 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 13:21:36.754109 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 13:21:36.754510 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 13:21:36.757331 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 13:21:36.760519 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 13:21:36.760614 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 13:21:36.763759 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1226 13:21:36.770478 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
1227 13:21:36.773945 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1228 13:21:36.777296 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1229 13:21:36.783865 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1230 13:21:36.787605 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1231 13:21:36.790544 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1232 13:21:36.797256 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1233 13:21:36.800543 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1234 13:21:36.804328 0 10 8 | B1->B0 | 3232 2424 | 1 1 | (1 0) (1 0)
1235 13:21:36.810570 0 10 12 | B1->B0 | 2323 2323 | 1 0 | (1 0) (0 0)
1236 13:21:36.814185 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 13:21:36.817521 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 13:21:36.820788 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 13:21:36.827388 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 13:21:36.830810 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 13:21:36.834172 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1242 13:21:36.841511 0 11 8 | B1->B0 | 2525 3b3b | 0 0 | (0 0) (0 0)
1243 13:21:36.845601 0 11 12 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
1244 13:21:36.849004 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1245 13:21:36.852582 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1246 13:21:36.859089 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1247 13:21:36.862267 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1248 13:21:36.866589 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1249 13:21:36.869680 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 13:21:36.876056 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1251 13:21:36.879757 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 13:21:36.883612 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 13:21:36.890378 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 13:21:36.893306 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 13:21:36.896359 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 13:21:36.899875 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 13:21:36.906377 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 13:21:36.909982 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 13:21:36.913314 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 13:21:36.919779 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 13:21:36.923232 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 13:21:36.926807 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 13:21:36.933527 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 13:21:36.936924 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 13:21:36.940126 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1266 13:21:36.943344 Total UI for P1: 0, mck2ui 16
1267 13:21:36.946720 best dqsien dly found for B0: ( 0, 14, 2)
1268 13:21:36.953518 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1269 13:21:36.956654 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 13:21:36.960338 Total UI for P1: 0, mck2ui 16
1271 13:21:36.963402 best dqsien dly found for B1: ( 0, 14, 8)
1272 13:21:36.967285 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1273 13:21:36.970269 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1274 13:21:36.970350
1275 13:21:36.973474 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1276 13:21:36.976894 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1277 13:21:36.980193 [Gating] SW calibration Done
1278 13:21:36.980272 ==
1279 13:21:36.983770 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 13:21:36.987323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1281 13:21:36.987402 ==
1282 13:21:36.990703 RX Vref Scan: 0
1283 13:21:36.990782
1284 13:21:36.990844 RX Vref 0 -> 0, step: 1
1285 13:21:36.990902
1286 13:21:36.994143 RX Delay -130 -> 252, step: 16
1287 13:21:36.997257 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1288 13:21:37.004231 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1289 13:21:37.007407 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1290 13:21:37.010480 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1291 13:21:37.014184 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1292 13:21:37.017422 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1293 13:21:37.024290 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1294 13:21:37.028241 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1295 13:21:37.031146 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1296 13:21:37.034182 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1297 13:21:37.037905 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1298 13:21:37.044787 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1299 13:21:37.047924 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1300 13:21:37.051080 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1301 13:21:37.054675 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1302 13:21:37.058043 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1303 13:21:37.058122 ==
1304 13:21:37.060986 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 13:21:37.068145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 13:21:37.068226 ==
1307 13:21:37.068289 DQS Delay:
1308 13:21:37.071129 DQS0 = 0, DQS1 = 0
1309 13:21:37.071211 DQM Delay:
1310 13:21:37.071273 DQM0 = 87, DQM1 = 73
1311 13:21:37.074560 DQ Delay:
1312 13:21:37.077867 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1313 13:21:37.081657 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =101
1314 13:21:37.084442 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1315 13:21:37.087756 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
1316 13:21:37.087834
1317 13:21:37.087896
1318 13:21:37.087954 ==
1319 13:21:37.091379 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 13:21:37.094851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 13:21:37.094930 ==
1322 13:21:37.094992
1323 13:21:37.095049
1324 13:21:37.098386 TX Vref Scan disable
1325 13:21:37.098464 == TX Byte 0 ==
1326 13:21:37.104543 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1327 13:21:37.108580 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1328 13:21:37.108683 == TX Byte 1 ==
1329 13:21:37.115030 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1330 13:21:37.118134 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1331 13:21:37.118214 ==
1332 13:21:37.121437 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 13:21:37.125205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 13:21:37.125285 ==
1335 13:21:37.138781 TX Vref=22, minBit 3, minWin=27, winSum=446
1336 13:21:37.141750 TX Vref=24, minBit 3, minWin=27, winSum=448
1337 13:21:37.145694 TX Vref=26, minBit 3, minWin=27, winSum=447
1338 13:21:37.148658 TX Vref=28, minBit 9, minWin=27, winSum=453
1339 13:21:37.152314 TX Vref=30, minBit 0, minWin=28, winSum=455
1340 13:21:37.155513 TX Vref=32, minBit 2, minWin=27, winSum=452
1341 13:21:37.162298 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
1342 13:21:37.162378
1343 13:21:37.165454 Final TX Range 1 Vref 30
1344 13:21:37.165534
1345 13:21:37.165595 ==
1346 13:21:37.169390 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 13:21:37.173147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 13:21:37.173226 ==
1349 13:21:37.173288
1350 13:21:37.173346
1351 13:21:37.175970 TX Vref Scan disable
1352 13:21:37.179281 == TX Byte 0 ==
1353 13:21:37.182230 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1354 13:21:37.185519 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1355 13:21:37.189150 == TX Byte 1 ==
1356 13:21:37.192442 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1357 13:21:37.195840 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1358 13:21:37.195921
1359 13:21:37.199041 [DATLAT]
1360 13:21:37.199119 Freq=800, CH0 RK1
1361 13:21:37.199181
1362 13:21:37.202700 DATLAT Default: 0xa
1363 13:21:37.202778 0, 0xFFFF, sum = 0
1364 13:21:37.205866 1, 0xFFFF, sum = 0
1365 13:21:37.205965 2, 0xFFFF, sum = 0
1366 13:21:37.209402 3, 0xFFFF, sum = 0
1367 13:21:37.209480 4, 0xFFFF, sum = 0
1368 13:21:37.212639 5, 0xFFFF, sum = 0
1369 13:21:37.212724 6, 0xFFFF, sum = 0
1370 13:21:37.216560 7, 0xFFFF, sum = 0
1371 13:21:37.216640 8, 0x0, sum = 1
1372 13:21:37.219585 9, 0x0, sum = 2
1373 13:21:37.219664 10, 0x0, sum = 3
1374 13:21:37.222482 11, 0x0, sum = 4
1375 13:21:37.222561 best_step = 9
1376 13:21:37.222623
1377 13:21:37.222680 ==
1378 13:21:37.225885 Dram Type= 6, Freq= 0, CH_0, rank 1
1379 13:21:37.229702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 13:21:37.229781 ==
1381 13:21:37.233146 RX Vref Scan: 0
1382 13:21:37.233223
1383 13:21:37.236108 RX Vref 0 -> 0, step: 1
1384 13:21:37.236186
1385 13:21:37.236248 RX Delay -95 -> 252, step: 8
1386 13:21:37.243285 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1387 13:21:37.246385 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1388 13:21:37.249576 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1389 13:21:37.252847 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1390 13:21:37.256308 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1391 13:21:37.263560 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1392 13:21:37.266800 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1393 13:21:37.270315 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1394 13:21:37.273352 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1395 13:21:37.276811 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1396 13:21:37.283355 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1397 13:21:37.287049 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1398 13:21:37.290221 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1399 13:21:37.293689 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1400 13:21:37.296678 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1401 13:21:37.303623 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1402 13:21:37.303701 ==
1403 13:21:37.306629 Dram Type= 6, Freq= 0, CH_0, rank 1
1404 13:21:37.310635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 13:21:37.310714 ==
1406 13:21:37.310776 DQS Delay:
1407 13:21:37.313307 DQS0 = 0, DQS1 = 0
1408 13:21:37.313384 DQM Delay:
1409 13:21:37.317348 DQM0 = 87, DQM1 = 78
1410 13:21:37.317426 DQ Delay:
1411 13:21:37.320194 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1412 13:21:37.323722 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1413 13:21:37.326875 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1414 13:21:37.330207 DQ12 =80, DQ13 =80, DQ14 =92, DQ15 =88
1415 13:21:37.330285
1416 13:21:37.330346
1417 13:21:37.337604 [DQSOSCAuto] RK1, (LSB)MR18= 0x311a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1418 13:21:37.340272 CH0 RK1: MR19=606, MR18=311A
1419 13:21:37.347018 CH0_RK1: MR19=0x606, MR18=0x311A, DQSOSC=397, MR23=63, INC=93, DEC=62
1420 13:21:37.351128 [RxdqsGatingPostProcess] freq 800
1421 13:21:37.354181 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1422 13:21:37.357399 Pre-setting of DQS Precalculation
1423 13:21:37.363660 [DualRankRxdatlatCal] RK0: 10, RK1: 9, Final_Datlat 10
1424 13:21:37.363739 ==
1425 13:21:37.367726 Dram Type= 6, Freq= 0, CH_1, rank 0
1426 13:21:37.371214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 13:21:37.371293 ==
1428 13:21:37.377466 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1429 13:21:37.383663 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1430 13:21:37.391953 [CA 0] Center 36 (6~67) winsize 62
1431 13:21:37.395682 [CA 1] Center 36 (6~67) winsize 62
1432 13:21:37.397987 [CA 2] Center 34 (4~64) winsize 61
1433 13:21:37.401338 [CA 3] Center 33 (3~64) winsize 62
1434 13:21:37.404506 [CA 4] Center 34 (3~65) winsize 63
1435 13:21:37.408418 [CA 5] Center 33 (3~64) winsize 62
1436 13:21:37.408497
1437 13:21:37.411370 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1438 13:21:37.411449
1439 13:21:37.415035 [CATrainingPosCal] consider 1 rank data
1440 13:21:37.417966 u2DelayCellTimex100 = 270/100 ps
1441 13:21:37.421580 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1442 13:21:37.424935 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1443 13:21:37.428015 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1444 13:21:37.434713 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1445 13:21:37.438310 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1446 13:21:37.441497 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1447 13:21:37.441569
1448 13:21:37.445183 CA PerBit enable=1, Macro0, CA PI delay=33
1449 13:21:37.445256
1450 13:21:37.448222 [CBTSetCACLKResult] CA Dly = 33
1451 13:21:37.448322 CS Dly: 5 (0~36)
1452 13:21:37.448408 ==
1453 13:21:37.451566 Dram Type= 6, Freq= 0, CH_1, rank 1
1454 13:21:37.458554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1455 13:21:37.458658 ==
1456 13:21:37.461431 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1457 13:21:37.468258 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1458 13:21:37.477181 [CA 0] Center 36 (6~67) winsize 62
1459 13:21:37.480478 [CA 1] Center 36 (6~67) winsize 62
1460 13:21:37.484292 [CA 2] Center 33 (3~64) winsize 62
1461 13:21:37.487804 [CA 3] Center 33 (3~64) winsize 62
1462 13:21:37.490683 [CA 4] Center 34 (4~65) winsize 62
1463 13:21:37.493935 [CA 5] Center 33 (3~64) winsize 62
1464 13:21:37.494004
1465 13:21:37.497636 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1466 13:21:37.497711
1467 13:21:37.500603 [CATrainingPosCal] consider 2 rank data
1468 13:21:37.504768 u2DelayCellTimex100 = 270/100 ps
1469 13:21:37.508156 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1470 13:21:37.511612 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1471 13:21:37.515206 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1472 13:21:37.519782 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1473 13:21:37.523416 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1474 13:21:37.526853 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1475 13:21:37.526932
1476 13:21:37.530330 CA PerBit enable=1, Macro0, CA PI delay=33
1477 13:21:37.530413
1478 13:21:37.533891 [CBTSetCACLKResult] CA Dly = 33
1479 13:21:37.533967 CS Dly: 5 (0~36)
1480 13:21:37.534046
1481 13:21:37.537787 ----->DramcWriteLeveling(PI) begin...
1482 13:21:37.537893 ==
1483 13:21:37.541319 Dram Type= 6, Freq= 0, CH_1, rank 0
1484 13:21:37.547719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1485 13:21:37.547794 ==
1486 13:21:37.551177 Write leveling (Byte 0): 27 => 27
1487 13:21:37.551279 Write leveling (Byte 1): 28 => 28
1488 13:21:37.554486 DramcWriteLeveling(PI) end<-----
1489 13:21:37.554580
1490 13:21:37.558252 ==
1491 13:21:37.558322 Dram Type= 6, Freq= 0, CH_1, rank 0
1492 13:21:37.564611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1493 13:21:37.564748 ==
1494 13:21:37.568045 [Gating] SW mode calibration
1495 13:21:37.574768 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1496 13:21:37.578462 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1497 13:21:37.584558 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1498 13:21:37.587955 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1499 13:21:37.591438 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1500 13:21:37.598030 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 13:21:37.601633 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 13:21:37.604722 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 13:21:37.608006 0 6 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1504 13:21:37.614575 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 13:21:37.618237 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 13:21:37.621310 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 13:21:37.628550 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 13:21:37.631685 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1509 13:21:37.634631 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 13:21:37.641668 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 13:21:37.644621 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 13:21:37.647941 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 13:21:37.654940 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 13:21:37.658511 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 13:21:37.661717 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 13:21:37.665015 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 13:21:37.671536 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 13:21:37.675170 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 13:21:37.678288 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 13:21:37.685319 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 13:21:37.688321 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 13:21:37.692011 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 13:21:37.698836 0 9 8 | B1->B0 | 2525 2525 | 1 1 | (1 1) (1 1)
1524 13:21:37.702178 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1525 13:21:37.705118 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1526 13:21:37.712110 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1527 13:21:37.715593 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1528 13:21:37.718629 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1529 13:21:37.725143 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1530 13:21:37.728639 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1531 13:21:37.732252 0 10 8 | B1->B0 | 2d2d 2d2d | 0 0 | (1 1) (0 0)
1532 13:21:37.735578 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 13:21:37.742020 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 13:21:37.745933 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1535 13:21:37.749002 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 13:21:37.755401 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1537 13:21:37.758755 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 13:21:37.762075 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1539 13:21:37.769253 0 11 8 | B1->B0 | 3333 3635 | 0 1 | (0 0) (0 0)
1540 13:21:37.772403 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1541 13:21:37.776539 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1542 13:21:37.782663 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1543 13:21:37.785825 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1544 13:21:37.789171 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1545 13:21:37.792490 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1546 13:21:37.798879 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 13:21:37.802583 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 13:21:37.806004 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 13:21:37.812702 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 13:21:37.816204 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 13:21:37.819520 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 13:21:37.826037 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 13:21:37.829433 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 13:21:37.832619 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 13:21:37.839640 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 13:21:37.843165 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 13:21:37.846365 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 13:21:37.849639 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 13:21:37.856627 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 13:21:37.859790 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 13:21:37.863587 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 13:21:37.869870 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1563 13:21:37.873481 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1564 13:21:37.876557 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 13:21:37.880102 Total UI for P1: 0, mck2ui 16
1566 13:21:37.883398 best dqsien dly found for B0: ( 0, 14, 6)
1567 13:21:37.886686 Total UI for P1: 0, mck2ui 16
1568 13:21:37.890084 best dqsien dly found for B1: ( 0, 14, 6)
1569 13:21:37.893626 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1570 13:21:37.896650 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1571 13:21:37.896785
1572 13:21:37.899971 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1573 13:21:37.903998 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1574 13:21:37.906695 [Gating] SW calibration Done
1575 13:21:37.906788 ==
1576 13:21:37.910255 Dram Type= 6, Freq= 0, CH_1, rank 0
1577 13:21:37.917426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1578 13:21:37.917534 ==
1579 13:21:37.917623 RX Vref Scan: 0
1580 13:21:37.917715
1581 13:21:37.920593 RX Vref 0 -> 0, step: 1
1582 13:21:37.920730
1583 13:21:37.923683 RX Delay -130 -> 252, step: 16
1584 13:21:37.926865 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1585 13:21:37.930748 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1586 13:21:37.933773 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1587 13:21:37.936992 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1588 13:21:37.943819 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1589 13:21:37.947386 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1590 13:21:37.950773 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1591 13:21:37.953817 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1592 13:21:37.957135 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1593 13:21:37.960671 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1594 13:21:37.967523 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1595 13:21:37.970609 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1596 13:21:37.974345 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1597 13:21:37.977300 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1598 13:21:37.980924 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1599 13:21:37.987797 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1600 13:21:37.987868 ==
1601 13:21:37.991132 Dram Type= 6, Freq= 0, CH_1, rank 0
1602 13:21:37.994248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1603 13:21:37.994315 ==
1604 13:21:37.994374 DQS Delay:
1605 13:21:37.997550 DQS0 = 0, DQS1 = 0
1606 13:21:37.997645 DQM Delay:
1607 13:21:38.001591 DQM0 = 83, DQM1 = 78
1608 13:21:38.001662 DQ Delay:
1609 13:21:38.004127 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1610 13:21:38.007874 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =77
1611 13:21:38.011034 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1612 13:21:38.014334 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1613 13:21:38.014405
1614 13:21:38.014480
1615 13:21:38.014567 ==
1616 13:21:38.018120 Dram Type= 6, Freq= 0, CH_1, rank 0
1617 13:21:38.021330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1618 13:21:38.021399 ==
1619 13:21:38.021458
1620 13:21:38.021513
1621 13:21:38.024407 TX Vref Scan disable
1622 13:21:38.028268 == TX Byte 0 ==
1623 13:21:38.031203 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1624 13:21:38.034501 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1625 13:21:38.038591 == TX Byte 1 ==
1626 13:21:38.041199 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1627 13:21:38.044542 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1628 13:21:38.044623 ==
1629 13:21:38.047777 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 13:21:38.051805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 13:21:38.054746 ==
1632 13:21:38.065919 TX Vref=22, minBit 10, minWin=26, winSum=432
1633 13:21:38.069165 TX Vref=24, minBit 0, minWin=27, winSum=439
1634 13:21:38.072598 TX Vref=26, minBit 15, minWin=26, winSum=443
1635 13:21:38.075941 TX Vref=28, minBit 11, minWin=27, winSum=446
1636 13:21:38.079479 TX Vref=30, minBit 12, minWin=27, winSum=453
1637 13:21:38.086315 TX Vref=32, minBit 9, minWin=27, winSum=452
1638 13:21:38.090163 [TxChooseVref] Worse bit 12, Min win 27, Win sum 453, Final Vref 30
1639 13:21:38.090234
1640 13:21:38.093588 Final TX Range 1 Vref 30
1641 13:21:38.093659
1642 13:21:38.093720 ==
1643 13:21:38.097419 Dram Type= 6, Freq= 0, CH_1, rank 0
1644 13:21:38.100053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1645 13:21:38.100170 ==
1646 13:21:38.100263
1647 13:21:38.100349
1648 13:21:38.103259 TX Vref Scan disable
1649 13:21:38.106857 == TX Byte 0 ==
1650 13:21:38.110110 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1651 13:21:38.113830 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1652 13:21:38.116871 == TX Byte 1 ==
1653 13:21:38.120258 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1654 13:21:38.123653 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1655 13:21:38.123758
1656 13:21:38.126980 [DATLAT]
1657 13:21:38.127076 Freq=800, CH1 RK0
1658 13:21:38.127163
1659 13:21:38.130505 DATLAT Default: 0xa
1660 13:21:38.130598 0, 0xFFFF, sum = 0
1661 13:21:38.134127 1, 0xFFFF, sum = 0
1662 13:21:38.134198 2, 0xFFFF, sum = 0
1663 13:21:38.137069 3, 0xFFFF, sum = 0
1664 13:21:38.137144 4, 0xFFFF, sum = 0
1665 13:21:38.140416 5, 0xFFFF, sum = 0
1666 13:21:38.140518 6, 0xFFFF, sum = 0
1667 13:21:38.144020 7, 0xFFFF, sum = 0
1668 13:21:38.144101 8, 0xFFFF, sum = 0
1669 13:21:38.147461 9, 0x0, sum = 1
1670 13:21:38.147566 10, 0x0, sum = 2
1671 13:21:38.150789 11, 0x0, sum = 3
1672 13:21:38.150886 12, 0x0, sum = 4
1673 13:21:38.150974 best_step = 10
1674 13:21:38.153950
1675 13:21:38.154030 ==
1676 13:21:38.157223 Dram Type= 6, Freq= 0, CH_1, rank 0
1677 13:21:38.160590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1678 13:21:38.160722 ==
1679 13:21:38.160786 RX Vref Scan: 1
1680 13:21:38.160843
1681 13:21:38.163985 Set Vref Range= 32 -> 127
1682 13:21:38.164051
1683 13:21:38.168197 RX Vref 32 -> 127, step: 1
1684 13:21:38.168289
1685 13:21:38.170695 RX Delay -95 -> 252, step: 8
1686 13:21:38.170790
1687 13:21:38.174046 Set Vref, RX VrefLevel [Byte0]: 32
1688 13:21:38.177502 [Byte1]: 32
1689 13:21:38.177581
1690 13:21:38.180745 Set Vref, RX VrefLevel [Byte0]: 33
1691 13:21:38.184095 [Byte1]: 33
1692 13:21:38.184188
1693 13:21:38.187468 Set Vref, RX VrefLevel [Byte0]: 34
1694 13:21:38.190737 [Byte1]: 34
1695 13:21:38.194224
1696 13:21:38.194296 Set Vref, RX VrefLevel [Byte0]: 35
1697 13:21:38.197814 [Byte1]: 35
1698 13:21:38.201541
1699 13:21:38.201620 Set Vref, RX VrefLevel [Byte0]: 36
1700 13:21:38.204959 [Byte1]: 36
1701 13:21:38.209218
1702 13:21:38.209296 Set Vref, RX VrefLevel [Byte0]: 37
1703 13:21:38.212504 [Byte1]: 37
1704 13:21:38.216985
1705 13:21:38.217063 Set Vref, RX VrefLevel [Byte0]: 38
1706 13:21:38.219908 [Byte1]: 38
1707 13:21:38.224520
1708 13:21:38.224602 Set Vref, RX VrefLevel [Byte0]: 39
1709 13:21:38.227802 [Byte1]: 39
1710 13:21:38.231917
1711 13:21:38.231996 Set Vref, RX VrefLevel [Byte0]: 40
1712 13:21:38.235808 [Byte1]: 40
1713 13:21:38.239592
1714 13:21:38.239671 Set Vref, RX VrefLevel [Byte0]: 41
1715 13:21:38.242922 [Byte1]: 41
1716 13:21:38.247874
1717 13:21:38.247953 Set Vref, RX VrefLevel [Byte0]: 42
1718 13:21:38.251034 [Byte1]: 42
1719 13:21:38.254884
1720 13:21:38.254962 Set Vref, RX VrefLevel [Byte0]: 43
1721 13:21:38.258105 [Byte1]: 43
1722 13:21:38.262935
1723 13:21:38.263013 Set Vref, RX VrefLevel [Byte0]: 44
1724 13:21:38.266154 [Byte1]: 44
1725 13:21:38.269863
1726 13:21:38.269948 Set Vref, RX VrefLevel [Byte0]: 45
1727 13:21:38.273274 [Byte1]: 45
1728 13:21:38.277515
1729 13:21:38.277601 Set Vref, RX VrefLevel [Byte0]: 46
1730 13:21:38.280750 [Byte1]: 46
1731 13:21:38.285071
1732 13:21:38.285144 Set Vref, RX VrefLevel [Byte0]: 47
1733 13:21:38.289216 [Byte1]: 47
1734 13:21:38.292875
1735 13:21:38.292980 Set Vref, RX VrefLevel [Byte0]: 48
1736 13:21:38.296638 [Byte1]: 48
1737 13:21:38.300647
1738 13:21:38.300762 Set Vref, RX VrefLevel [Byte0]: 49
1739 13:21:38.303717 [Byte1]: 49
1740 13:21:38.308021
1741 13:21:38.308116 Set Vref, RX VrefLevel [Byte0]: 50
1742 13:21:38.311336 [Byte1]: 50
1743 13:21:38.316229
1744 13:21:38.316334 Set Vref, RX VrefLevel [Byte0]: 51
1745 13:21:38.318986 [Byte1]: 51
1746 13:21:38.323776
1747 13:21:38.323872 Set Vref, RX VrefLevel [Byte0]: 52
1748 13:21:38.326686 [Byte1]: 52
1749 13:21:38.331049
1750 13:21:38.331150 Set Vref, RX VrefLevel [Byte0]: 53
1751 13:21:38.334121 [Byte1]: 53
1752 13:21:38.338676
1753 13:21:38.338780 Set Vref, RX VrefLevel [Byte0]: 54
1754 13:21:38.342119 [Byte1]: 54
1755 13:21:38.346059
1756 13:21:38.346161 Set Vref, RX VrefLevel [Byte0]: 55
1757 13:21:38.349564 [Byte1]: 55
1758 13:21:38.354135
1759 13:21:38.354214 Set Vref, RX VrefLevel [Byte0]: 56
1760 13:21:38.356971 [Byte1]: 56
1761 13:21:38.361266
1762 13:21:38.361350 Set Vref, RX VrefLevel [Byte0]: 57
1763 13:21:38.364973 [Byte1]: 57
1764 13:21:38.368835
1765 13:21:38.368926 Set Vref, RX VrefLevel [Byte0]: 58
1766 13:21:38.372051 [Byte1]: 58
1767 13:21:38.376807
1768 13:21:38.376886 Set Vref, RX VrefLevel [Byte0]: 59
1769 13:21:38.380097 [Byte1]: 59
1770 13:21:38.384455
1771 13:21:38.384533 Set Vref, RX VrefLevel [Byte0]: 60
1772 13:21:38.387148 [Byte1]: 60
1773 13:21:38.391503
1774 13:21:38.391582 Set Vref, RX VrefLevel [Byte0]: 61
1775 13:21:38.394991 [Byte1]: 61
1776 13:21:38.399405
1777 13:21:38.399484 Set Vref, RX VrefLevel [Byte0]: 62
1778 13:21:38.402438 [Byte1]: 62
1779 13:21:38.406680
1780 13:21:38.406759 Set Vref, RX VrefLevel [Byte0]: 63
1781 13:21:38.409898 [Byte1]: 63
1782 13:21:38.414496
1783 13:21:38.414574 Set Vref, RX VrefLevel [Byte0]: 64
1784 13:21:38.417624 [Byte1]: 64
1785 13:21:38.422045
1786 13:21:38.422124 Set Vref, RX VrefLevel [Byte0]: 65
1787 13:21:38.425286 [Byte1]: 65
1788 13:21:38.429476
1789 13:21:38.429555 Set Vref, RX VrefLevel [Byte0]: 66
1790 13:21:38.432960 [Byte1]: 66
1791 13:21:38.437827
1792 13:21:38.437935 Set Vref, RX VrefLevel [Byte0]: 67
1793 13:21:38.440574 [Byte1]: 67
1794 13:21:38.444793
1795 13:21:38.444871 Set Vref, RX VrefLevel [Byte0]: 68
1796 13:21:38.448367 [Byte1]: 68
1797 13:21:38.454409
1798 13:21:38.454488 Set Vref, RX VrefLevel [Byte0]: 69
1799 13:21:38.455876 [Byte1]: 69
1800 13:21:38.459805
1801 13:21:38.459912 Set Vref, RX VrefLevel [Byte0]: 70
1802 13:21:38.463206 [Byte1]: 70
1803 13:21:38.467631
1804 13:21:38.467710 Set Vref, RX VrefLevel [Byte0]: 71
1805 13:21:38.470829 [Byte1]: 71
1806 13:21:38.475655
1807 13:21:38.475734 Set Vref, RX VrefLevel [Byte0]: 72
1808 13:21:38.478428 [Byte1]: 72
1809 13:21:38.483209
1810 13:21:38.483287 Set Vref, RX VrefLevel [Byte0]: 73
1811 13:21:38.486532 [Byte1]: 73
1812 13:21:38.490210
1813 13:21:38.490288 Set Vref, RX VrefLevel [Byte0]: 74
1814 13:21:38.493922 [Byte1]: 74
1815 13:21:38.498113
1816 13:21:38.498192 Set Vref, RX VrefLevel [Byte0]: 75
1817 13:21:38.501372 [Byte1]: 75
1818 13:21:38.506065
1819 13:21:38.506144 Set Vref, RX VrefLevel [Byte0]: 76
1820 13:21:38.509101 [Byte1]: 76
1821 13:21:38.513736
1822 13:21:38.513814 Final RX Vref Byte 0 = 65 to rank0
1823 13:21:38.516564 Final RX Vref Byte 1 = 56 to rank0
1824 13:21:38.519797 Final RX Vref Byte 0 = 65 to rank1
1825 13:21:38.523161 Final RX Vref Byte 1 = 56 to rank1==
1826 13:21:38.527122 Dram Type= 6, Freq= 0, CH_1, rank 0
1827 13:21:38.530038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1828 13:21:38.533989 ==
1829 13:21:38.534069 DQS Delay:
1830 13:21:38.534133 DQS0 = 0, DQS1 = 0
1831 13:21:38.536719 DQM Delay:
1832 13:21:38.536815 DQM0 = 83, DQM1 = 73
1833 13:21:38.540568 DQ Delay:
1834 13:21:38.540677 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1835 13:21:38.543398 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =76
1836 13:21:38.547029 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1837 13:21:38.549879 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =76
1838 13:21:38.549954
1839 13:21:38.553732
1840 13:21:38.560301 [DQSOSCAuto] RK0, (LSB)MR18= 0x26fb, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1841 13:21:38.563623 CH1 RK0: MR19=605, MR18=26FB
1842 13:21:38.570594 CH1_RK0: MR19=0x605, MR18=0x26FB, DQSOSC=400, MR23=63, INC=92, DEC=61
1843 13:21:38.570666
1844 13:21:38.573572 ----->DramcWriteLeveling(PI) begin...
1845 13:21:38.573637 ==
1846 13:21:38.576850 Dram Type= 6, Freq= 0, CH_1, rank 1
1847 13:21:38.580153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 13:21:38.580216 ==
1849 13:21:38.583535 Write leveling (Byte 0): 26 => 26
1850 13:21:38.586848 Write leveling (Byte 1): 27 => 27
1851 13:21:38.590515 DramcWriteLeveling(PI) end<-----
1852 13:21:38.590580
1853 13:21:38.590640 ==
1854 13:21:38.593924 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 13:21:38.596994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1856 13:21:38.597066 ==
1857 13:21:38.600782 [Gating] SW mode calibration
1858 13:21:38.607089 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1859 13:21:38.610634 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1860 13:21:38.617624 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1861 13:21:38.620603 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1862 13:21:38.624388 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1863 13:21:38.630542 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 13:21:38.634541 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 13:21:38.637404 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 13:21:38.644144 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 13:21:38.648077 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 13:21:38.651176 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 13:21:38.657524 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 13:21:38.660978 0 7 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1871 13:21:38.664207 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 13:21:38.667872 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 13:21:38.674299 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 13:21:38.677634 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1875 13:21:38.681042 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1876 13:21:38.687651 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1877 13:21:38.691014 0 8 4 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 0)
1878 13:21:38.694334 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 13:21:38.701408 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1880 13:21:38.704744 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 13:21:38.708121 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 13:21:38.715082 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 13:21:38.718523 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 13:21:38.722132 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 13:21:38.728795 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1886 13:21:38.731735 0 9 8 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
1887 13:21:38.735062 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 13:21:38.738825 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 13:21:38.745174 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 13:21:38.748807 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 13:21:38.752137 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 13:21:38.758952 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1893 13:21:38.762181 0 10 4 | B1->B0 | 3131 2626 | 1 0 | (1 0) (1 0)
1894 13:21:38.765794 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1895 13:21:38.772172 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 13:21:38.775785 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 13:21:38.779154 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 13:21:38.782352 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1899 13:21:38.789014 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 13:21:38.792256 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1901 13:21:38.796007 0 11 4 | B1->B0 | 2525 3535 | 0 0 | (0 0) (1 1)
1902 13:21:38.802540 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1903 13:21:38.806432 0 11 12 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
1904 13:21:38.809028 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 13:21:38.816100 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 13:21:38.819417 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 13:21:38.822663 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 13:21:38.829605 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 13:21:38.832540 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1910 13:21:38.835880 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1911 13:21:38.842699 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 13:21:38.846350 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 13:21:38.849599 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 13:21:38.852568 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 13:21:38.859125 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 13:21:38.862820 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 13:21:38.865885 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 13:21:38.872967 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 13:21:38.876213 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 13:21:38.879670 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 13:21:38.886732 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 13:21:38.890079 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 13:21:38.893099 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 13:21:38.896513 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 13:21:38.903226 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1926 13:21:38.906325 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 13:21:38.909675 Total UI for P1: 0, mck2ui 16
1928 13:21:38.913006 best dqsien dly found for B0: ( 0, 14, 4)
1929 13:21:38.916531 Total UI for P1: 0, mck2ui 16
1930 13:21:38.919581 best dqsien dly found for B1: ( 0, 14, 6)
1931 13:21:38.923022 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1932 13:21:38.926916 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1933 13:21:38.927283
1934 13:21:38.930174 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1935 13:21:38.933648 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1936 13:21:38.936459 [Gating] SW calibration Done
1937 13:21:38.936984 ==
1938 13:21:38.940135 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 13:21:38.943350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 13:21:38.946346 ==
1941 13:21:38.946840 RX Vref Scan: 0
1942 13:21:38.947228
1943 13:21:38.949849 RX Vref 0 -> 0, step: 1
1944 13:21:38.950312
1945 13:21:38.953242 RX Delay -130 -> 252, step: 16
1946 13:21:38.956559 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1947 13:21:38.960390 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1948 13:21:38.963530 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1949 13:21:38.966924 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1950 13:21:38.973162 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1951 13:21:38.977169 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1952 13:21:38.979952 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1953 13:21:38.983850 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1954 13:21:38.986991 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1955 13:21:38.990423 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1956 13:21:38.997006 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1957 13:21:39.000019 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1958 13:21:39.003546 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1959 13:21:39.006976 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1960 13:21:39.010089 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1961 13:21:39.016859 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1962 13:21:39.017288 ==
1963 13:21:39.020088 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 13:21:39.024153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 13:21:39.024562 ==
1966 13:21:39.024935 DQS Delay:
1967 13:21:39.027009 DQS0 = 0, DQS1 = 0
1968 13:21:39.027460 DQM Delay:
1969 13:21:39.030258 DQM0 = 78, DQM1 = 75
1970 13:21:39.030680 DQ Delay:
1971 13:21:39.034314 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1972 13:21:39.037071 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =69
1973 13:21:39.040335 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1974 13:21:39.043827 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1975 13:21:39.044290
1976 13:21:39.044836
1977 13:21:39.045160 ==
1978 13:21:39.047266 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 13:21:39.050570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 13:21:39.050980 ==
1981 13:21:39.051302
1982 13:21:39.051598
1983 13:21:39.053721 TX Vref Scan disable
1984 13:21:39.057197 == TX Byte 0 ==
1985 13:21:39.060596 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1986 13:21:39.063754 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1987 13:21:39.067632 == TX Byte 1 ==
1988 13:21:39.070538 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1989 13:21:39.073912 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1990 13:21:39.074370 ==
1991 13:21:39.077472 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 13:21:39.081013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 13:21:39.084172 ==
1994 13:21:39.095313 TX Vref=22, minBit 5, minWin=27, winSum=440
1995 13:21:39.098593 TX Vref=24, minBit 0, minWin=27, winSum=438
1996 13:21:39.101842 TX Vref=26, minBit 0, minWin=27, winSum=444
1997 13:21:39.105531 TX Vref=28, minBit 10, minWin=27, winSum=449
1998 13:21:39.108506 TX Vref=30, minBit 13, minWin=27, winSum=452
1999 13:21:39.115306 TX Vref=32, minBit 13, minWin=27, winSum=452
2000 13:21:39.118900 [TxChooseVref] Worse bit 13, Min win 27, Win sum 452, Final Vref 30
2001 13:21:39.119310
2002 13:21:39.122337 Final TX Range 1 Vref 30
2003 13:21:39.122742
2004 13:21:39.123063 ==
2005 13:21:39.125613 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 13:21:39.129068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 13:21:39.129477 ==
2008 13:21:39.132519
2009 13:21:39.133089
2010 13:21:39.133461 TX Vref Scan disable
2011 13:21:39.135541 == TX Byte 0 ==
2012 13:21:39.138834 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2013 13:21:39.142971 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2014 13:21:39.145434 == TX Byte 1 ==
2015 13:21:39.149061 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2016 13:21:39.152424 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2017 13:21:39.155449
2018 13:21:39.155856 [DATLAT]
2019 13:21:39.156257 Freq=800, CH1 RK1
2020 13:21:39.156588
2021 13:21:39.158859 DATLAT Default: 0xa
2022 13:21:39.159267 0, 0xFFFF, sum = 0
2023 13:21:39.162468 1, 0xFFFF, sum = 0
2024 13:21:39.162887 2, 0xFFFF, sum = 0
2025 13:21:39.165936 3, 0xFFFF, sum = 0
2026 13:21:39.166353 4, 0xFFFF, sum = 0
2027 13:21:39.169290 5, 0xFFFF, sum = 0
2028 13:21:39.169706 6, 0xFFFF, sum = 0
2029 13:21:39.172708 7, 0xFFFF, sum = 0
2030 13:21:39.173124 8, 0xFFFF, sum = 0
2031 13:21:39.175783 9, 0x0, sum = 1
2032 13:21:39.176201 10, 0x0, sum = 2
2033 13:21:39.179775 11, 0x0, sum = 3
2034 13:21:39.180195 12, 0x0, sum = 4
2035 13:21:39.182529 best_step = 10
2036 13:21:39.182937
2037 13:21:39.183263 ==
2038 13:21:39.186371 Dram Type= 6, Freq= 0, CH_1, rank 1
2039 13:21:39.189344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2040 13:21:39.189759 ==
2041 13:21:39.192724 RX Vref Scan: 0
2042 13:21:39.193137
2043 13:21:39.193462 RX Vref 0 -> 0, step: 1
2044 13:21:39.193774
2045 13:21:39.196418 RX Delay -111 -> 252, step: 8
2046 13:21:39.202853 iDelay=201, Bit 0, Center 84 (-31 ~ 200) 232
2047 13:21:39.206128 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2048 13:21:39.209462 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2049 13:21:39.212784 iDelay=201, Bit 3, Center 76 (-39 ~ 192) 232
2050 13:21:39.216396 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2051 13:21:39.219898 iDelay=201, Bit 5, Center 92 (-15 ~ 200) 216
2052 13:21:39.226480 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2053 13:21:39.229524 iDelay=201, Bit 7, Center 76 (-31 ~ 184) 216
2054 13:21:39.232955 iDelay=201, Bit 8, Center 64 (-55 ~ 184) 240
2055 13:21:39.236528 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2056 13:21:39.239630 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2057 13:21:39.246424 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2058 13:21:39.249593 iDelay=201, Bit 12, Center 80 (-31 ~ 192) 224
2059 13:21:39.253104 iDelay=201, Bit 13, Center 80 (-39 ~ 200) 240
2060 13:21:39.256512 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2061 13:21:39.259711 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2062 13:21:39.263069 ==
2063 13:21:39.263514 Dram Type= 6, Freq= 0, CH_1, rank 1
2064 13:21:39.270845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2065 13:21:39.271294 ==
2066 13:21:39.271664 DQS Delay:
2067 13:21:39.273051 DQS0 = 0, DQS1 = 0
2068 13:21:39.273476 DQM Delay:
2069 13:21:39.273801 DQM0 = 80, DQM1 = 75
2070 13:21:39.276448 DQ Delay:
2071 13:21:39.279980 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2072 13:21:39.283166 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
2073 13:21:39.286487 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2074 13:21:39.289985 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
2075 13:21:39.290395
2076 13:21:39.290715
2077 13:21:39.297126 [DQSOSCAuto] RK1, (LSB)MR18= 0x232e, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2078 13:21:39.300093 CH1 RK1: MR19=606, MR18=232E
2079 13:21:39.306934 CH1_RK1: MR19=0x606, MR18=0x232E, DQSOSC=398, MR23=63, INC=93, DEC=62
2080 13:21:39.310424 [RxdqsGatingPostProcess] freq 800
2081 13:21:39.313727 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2082 13:21:39.317000 Pre-setting of DQS Precalculation
2083 13:21:39.323412 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2084 13:21:39.330446 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2085 13:21:39.337201 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2086 13:21:39.337617
2087 13:21:39.337945
2088 13:21:39.340232 [Calibration Summary] 1600 Mbps
2089 13:21:39.340644 CH 0, Rank 0
2090 13:21:39.344064 SW Impedance : PASS
2091 13:21:39.344472 DUTY Scan : NO K
2092 13:21:39.346914 ZQ Calibration : PASS
2093 13:21:39.350411 Jitter Meter : NO K
2094 13:21:39.350825 CBT Training : PASS
2095 13:21:39.354377 Write leveling : PASS
2096 13:21:39.357106 RX DQS gating : PASS
2097 13:21:39.357520 RX DQ/DQS(RDDQC) : PASS
2098 13:21:39.360540 TX DQ/DQS : PASS
2099 13:21:39.364119 RX DATLAT : PASS
2100 13:21:39.364529 RX DQ/DQS(Engine): PASS
2101 13:21:39.367838 TX OE : NO K
2102 13:21:39.368252 All Pass.
2103 13:21:39.368578
2104 13:21:39.370456 CH 0, Rank 1
2105 13:21:39.370866 SW Impedance : PASS
2106 13:21:39.374382 DUTY Scan : NO K
2107 13:21:39.377161 ZQ Calibration : PASS
2108 13:21:39.377572 Jitter Meter : NO K
2109 13:21:39.380745 CBT Training : PASS
2110 13:21:39.381303 Write leveling : PASS
2111 13:21:39.384170 RX DQS gating : PASS
2112 13:21:39.387513 RX DQ/DQS(RDDQC) : PASS
2113 13:21:39.387922 TX DQ/DQS : PASS
2114 13:21:39.390625 RX DATLAT : PASS
2115 13:21:39.393839 RX DQ/DQS(Engine): PASS
2116 13:21:39.394250 TX OE : NO K
2117 13:21:39.397961 All Pass.
2118 13:21:39.398381
2119 13:21:39.398708 CH 1, Rank 0
2120 13:21:39.400848 SW Impedance : PASS
2121 13:21:39.401293 DUTY Scan : NO K
2122 13:21:39.404062 ZQ Calibration : PASS
2123 13:21:39.407306 Jitter Meter : NO K
2124 13:21:39.407720 CBT Training : PASS
2125 13:21:39.410509 Write leveling : PASS
2126 13:21:39.414390 RX DQS gating : PASS
2127 13:21:39.414803 RX DQ/DQS(RDDQC) : PASS
2128 13:21:39.417268 TX DQ/DQS : PASS
2129 13:21:39.417683 RX DATLAT : PASS
2130 13:21:39.420742 RX DQ/DQS(Engine): PASS
2131 13:21:39.424572 TX OE : NO K
2132 13:21:39.425028 All Pass.
2133 13:21:39.425354
2134 13:21:39.425660 CH 1, Rank 1
2135 13:21:39.427886 SW Impedance : PASS
2136 13:21:39.430950 DUTY Scan : NO K
2137 13:21:39.431362 ZQ Calibration : PASS
2138 13:21:39.434375 Jitter Meter : NO K
2139 13:21:39.437445 CBT Training : PASS
2140 13:21:39.437857 Write leveling : PASS
2141 13:21:39.441463 RX DQS gating : PASS
2142 13:21:39.444302 RX DQ/DQS(RDDQC) : PASS
2143 13:21:39.444757 TX DQ/DQS : PASS
2144 13:21:39.447806 RX DATLAT : PASS
2145 13:21:39.448383 RX DQ/DQS(Engine): PASS
2146 13:21:39.450909 TX OE : NO K
2147 13:21:39.451322 All Pass.
2148 13:21:39.451652
2149 13:21:39.454248 DramC Write-DBI off
2150 13:21:39.457765 PER_BANK_REFRESH: Hybrid Mode
2151 13:21:39.458176 TX_TRACKING: ON
2152 13:21:39.460964 [GetDramInforAfterCalByMRR] Vendor 6.
2153 13:21:39.464585 [GetDramInforAfterCalByMRR] Revision 606.
2154 13:21:39.467720 [GetDramInforAfterCalByMRR] Revision 2 0.
2155 13:21:39.471263 MR0 0x3b3b
2156 13:21:39.471673 MR8 0x5151
2157 13:21:39.474552 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2158 13:21:39.474966
2159 13:21:39.478334 MR0 0x3b3b
2160 13:21:39.478745 MR8 0x5151
2161 13:21:39.481272 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2162 13:21:39.481685
2163 13:21:39.491113 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2164 13:21:39.495020 [FAST_K] Save calibration result to emmc
2165 13:21:39.498667 [FAST_K] Save calibration result to emmc
2166 13:21:39.501614 dram_init: config_dvfs: 1
2167 13:21:39.504783 dramc_set_vcore_voltage set vcore to 662500
2168 13:21:39.505226 Read voltage for 1200, 2
2169 13:21:39.508295 Vio18 = 0
2170 13:21:39.508799 Vcore = 662500
2171 13:21:39.509268 Vdram = 0
2172 13:21:39.511327 Vddq = 0
2173 13:21:39.511774 Vmddr = 0
2174 13:21:39.514472 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2175 13:21:39.521418 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2176 13:21:39.524595 MEM_TYPE=3, freq_sel=15
2177 13:21:39.525132 sv_algorithm_assistance_LP4_1600
2178 13:21:39.531511 ============ PULL DRAM RESETB DOWN ============
2179 13:21:39.534979 ========== PULL DRAM RESETB DOWN end =========
2180 13:21:39.538278 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2181 13:21:39.542039 ===================================
2182 13:21:39.544923 LPDDR4 DRAM CONFIGURATION
2183 13:21:39.548765 ===================================
2184 13:21:39.551778 EX_ROW_EN[0] = 0x0
2185 13:21:39.552221 EX_ROW_EN[1] = 0x0
2186 13:21:39.555382 LP4Y_EN = 0x0
2187 13:21:39.555822 WORK_FSP = 0x0
2188 13:21:39.558544 WL = 0x4
2189 13:21:39.559003 RL = 0x4
2190 13:21:39.562071 BL = 0x2
2191 13:21:39.562521 RPST = 0x0
2192 13:21:39.564849 RD_PRE = 0x0
2193 13:21:39.565298 WR_PRE = 0x1
2194 13:21:39.568313 WR_PST = 0x0
2195 13:21:39.568864 DBI_WR = 0x0
2196 13:21:39.572009 DBI_RD = 0x0
2197 13:21:39.572457 OTF = 0x1
2198 13:21:39.575634 ===================================
2199 13:21:39.578438 ===================================
2200 13:21:39.581952 ANA top config
2201 13:21:39.585386 ===================================
2202 13:21:39.585834 DLL_ASYNC_EN = 0
2203 13:21:39.588749 ALL_SLAVE_EN = 0
2204 13:21:39.592095 NEW_RANK_MODE = 1
2205 13:21:39.595689 DLL_IDLE_MODE = 1
2206 13:21:39.599142 LP45_APHY_COMB_EN = 1
2207 13:21:39.599587 TX_ODT_DIS = 1
2208 13:21:39.602311 NEW_8X_MODE = 1
2209 13:21:39.605508 ===================================
2210 13:21:39.609040 ===================================
2211 13:21:39.612461 data_rate = 2400
2212 13:21:39.616256 CKR = 1
2213 13:21:39.619145 DQ_P2S_RATIO = 8
2214 13:21:39.619553 ===================================
2215 13:21:39.622603 CA_P2S_RATIO = 8
2216 13:21:39.625807 DQ_CA_OPEN = 0
2217 13:21:39.629153 DQ_SEMI_OPEN = 0
2218 13:21:39.632640 CA_SEMI_OPEN = 0
2219 13:21:39.636208 CA_FULL_RATE = 0
2220 13:21:39.636614 DQ_CKDIV4_EN = 0
2221 13:21:39.639327 CA_CKDIV4_EN = 0
2222 13:21:39.642228 CA_PREDIV_EN = 0
2223 13:21:39.646066 PH8_DLY = 17
2224 13:21:39.649343 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2225 13:21:39.652579 DQ_AAMCK_DIV = 4
2226 13:21:39.653038 CA_AAMCK_DIV = 4
2227 13:21:39.655769 CA_ADMCK_DIV = 4
2228 13:21:39.659663 DQ_TRACK_CA_EN = 0
2229 13:21:39.662670 CA_PICK = 1200
2230 13:21:39.666189 CA_MCKIO = 1200
2231 13:21:39.670160 MCKIO_SEMI = 0
2232 13:21:39.672751 PLL_FREQ = 2366
2233 13:21:39.673158 DQ_UI_PI_RATIO = 32
2234 13:21:39.676082 CA_UI_PI_RATIO = 0
2235 13:21:39.679520 ===================================
2236 13:21:39.682689 ===================================
2237 13:21:39.686000 memory_type:LPDDR4
2238 13:21:39.689348 GP_NUM : 10
2239 13:21:39.689745 SRAM_EN : 1
2240 13:21:39.693212 MD32_EN : 0
2241 13:21:39.696169 ===================================
2242 13:21:39.696571 [ANA_INIT] >>>>>>>>>>>>>>
2243 13:21:39.699826 <<<<<< [CONFIGURE PHASE]: ANA_TX
2244 13:21:39.702755 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2245 13:21:39.706278 ===================================
2246 13:21:39.709918 data_rate = 2400,PCW = 0X5b00
2247 13:21:39.712732 ===================================
2248 13:21:39.716481 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2249 13:21:39.723129 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2250 13:21:39.726651 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2251 13:21:39.733062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2252 13:21:39.736539 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2253 13:21:39.739843 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2254 13:21:39.740291 [ANA_INIT] flow start
2255 13:21:39.743512 [ANA_INIT] PLL >>>>>>>>
2256 13:21:39.746812 [ANA_INIT] PLL <<<<<<<<
2257 13:21:39.747260 [ANA_INIT] MIDPI >>>>>>>>
2258 13:21:39.750164 [ANA_INIT] MIDPI <<<<<<<<
2259 13:21:39.753407 [ANA_INIT] DLL >>>>>>>>
2260 13:21:39.753858 [ANA_INIT] DLL <<<<<<<<
2261 13:21:39.756505 [ANA_INIT] flow end
2262 13:21:39.760035 ============ LP4 DIFF to SE enter ============
2263 13:21:39.763275 ============ LP4 DIFF to SE exit ============
2264 13:21:39.766614 [ANA_INIT] <<<<<<<<<<<<<
2265 13:21:39.770064 [Flow] Enable top DCM control >>>>>
2266 13:21:39.774036 [Flow] Enable top DCM control <<<<<
2267 13:21:39.776579 Enable DLL master slave shuffle
2268 13:21:39.783679 ==============================================================
2269 13:21:39.784134 Gating Mode config
2270 13:21:39.790303 ==============================================================
2271 13:21:39.790783 Config description:
2272 13:21:39.800242 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2273 13:21:39.807194 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2274 13:21:39.813824 SELPH_MODE 0: By rank 1: By Phase
2275 13:21:39.817362 ==============================================================
2276 13:21:39.820327 GAT_TRACK_EN = 1
2277 13:21:39.823750 RX_GATING_MODE = 2
2278 13:21:39.827508 RX_GATING_TRACK_MODE = 2
2279 13:21:39.830501 SELPH_MODE = 1
2280 13:21:39.834206 PICG_EARLY_EN = 1
2281 13:21:39.837233 VALID_LAT_VALUE = 1
2282 13:21:39.840864 ==============================================================
2283 13:21:39.844632 Enter into Gating configuration >>>>
2284 13:21:39.847492 Exit from Gating configuration <<<<
2285 13:21:39.851011 Enter into DVFS_PRE_config >>>>>
2286 13:21:39.861196 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2287 13:21:39.864575 Exit from DVFS_PRE_config <<<<<
2288 13:21:39.867988 Enter into PICG configuration >>>>
2289 13:21:39.870980 Exit from PICG configuration <<<<
2290 13:21:39.874405 [RX_INPUT] configuration >>>>>
2291 13:21:39.877897 [RX_INPUT] configuration <<<<<
2292 13:21:39.884851 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2293 13:21:39.887890 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2294 13:21:39.895026 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2295 13:21:39.901586 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2296 13:21:39.908481 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2297 13:21:39.911492 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2298 13:21:39.918767 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2299 13:21:39.921472 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2300 13:21:39.925090 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2301 13:21:39.928382 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2302 13:21:39.931774 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2303 13:21:39.938262 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2304 13:21:39.941800 ===================================
2305 13:21:39.945477 LPDDR4 DRAM CONFIGURATION
2306 13:21:39.948759 ===================================
2307 13:21:39.949224 EX_ROW_EN[0] = 0x0
2308 13:21:39.951986 EX_ROW_EN[1] = 0x0
2309 13:21:39.952440 LP4Y_EN = 0x0
2310 13:21:39.954963 WORK_FSP = 0x0
2311 13:21:39.955414 WL = 0x4
2312 13:21:39.958534 RL = 0x4
2313 13:21:39.958970 BL = 0x2
2314 13:21:39.961703 RPST = 0x0
2315 13:21:39.962174 RD_PRE = 0x0
2316 13:21:39.965106 WR_PRE = 0x1
2317 13:21:39.965578 WR_PST = 0x0
2318 13:21:39.968445 DBI_WR = 0x0
2319 13:21:39.968999 DBI_RD = 0x0
2320 13:21:39.971849 OTF = 0x1
2321 13:21:39.975182 ===================================
2322 13:21:39.978766 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2323 13:21:39.982255 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2324 13:21:39.988638 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2325 13:21:39.992303 ===================================
2326 13:21:39.992801 LPDDR4 DRAM CONFIGURATION
2327 13:21:39.995199 ===================================
2328 13:21:39.999014 EX_ROW_EN[0] = 0x10
2329 13:21:39.999457 EX_ROW_EN[1] = 0x0
2330 13:21:40.001817 LP4Y_EN = 0x0
2331 13:21:40.002258 WORK_FSP = 0x0
2332 13:21:40.006164 WL = 0x4
2333 13:21:40.009110 RL = 0x4
2334 13:21:40.009551 BL = 0x2
2335 13:21:40.012130 RPST = 0x0
2336 13:21:40.012569 RD_PRE = 0x0
2337 13:21:40.015260 WR_PRE = 0x1
2338 13:21:40.015702 WR_PST = 0x0
2339 13:21:40.018680 DBI_WR = 0x0
2340 13:21:40.019133 DBI_RD = 0x0
2341 13:21:40.022417 OTF = 0x1
2342 13:21:40.025546 ===================================
2343 13:21:40.029131 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2344 13:21:40.032225 ==
2345 13:21:40.032702 Dram Type= 6, Freq= 0, CH_0, rank 0
2346 13:21:40.039150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2347 13:21:40.039608 ==
2348 13:21:40.039968 [Duty_Offset_Calibration]
2349 13:21:40.042559 B0:2 B1:-1 CA:1
2350 13:21:40.043019
2351 13:21:40.045753 [DutyScan_Calibration_Flow] k_type=0
2352 13:21:40.054202
2353 13:21:40.054646 ==CLK 0==
2354 13:21:40.057553 Final CLK duty delay cell = -4
2355 13:21:40.060961 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2356 13:21:40.064058 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2357 13:21:40.067383 [-4] AVG Duty = 4969%(X100)
2358 13:21:40.067666
2359 13:21:40.070990 CH0 CLK Duty spec in!! Max-Min= 124%
2360 13:21:40.074379 [DutyScan_Calibration_Flow] ====Done====
2361 13:21:40.074700
2362 13:21:40.077336 [DutyScan_Calibration_Flow] k_type=1
2363 13:21:40.092373
2364 13:21:40.092722 ==DQS 0 ==
2365 13:21:40.095381 Final DQS duty delay cell = -4
2366 13:21:40.098909 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2367 13:21:40.102144 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2368 13:21:40.105718 [-4] AVG Duty = 4938%(X100)
2369 13:21:40.106036
2370 13:21:40.106268 ==DQS 1 ==
2371 13:21:40.108931 Final DQS duty delay cell = -4
2372 13:21:40.112876 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2373 13:21:40.115581 [-4] MIN Duty = 5000%(X100), DQS PI = 48
2374 13:21:40.119466 [-4] AVG Duty = 5062%(X100)
2375 13:21:40.119780
2376 13:21:40.122876 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2377 13:21:40.123197
2378 13:21:40.125906 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2379 13:21:40.129030 [DutyScan_Calibration_Flow] ====Done====
2380 13:21:40.129352
2381 13:21:40.132407 [DutyScan_Calibration_Flow] k_type=3
2382 13:21:40.149454
2383 13:21:40.149851 ==DQM 0 ==
2384 13:21:40.152554 Final DQM duty delay cell = 0
2385 13:21:40.156450 [0] MAX Duty = 5000%(X100), DQS PI = 56
2386 13:21:40.159458 [0] MIN Duty = 4907%(X100), DQS PI = 4
2387 13:21:40.159864 [0] AVG Duty = 4953%(X100)
2388 13:21:40.160187
2389 13:21:40.162788 ==DQM 1 ==
2390 13:21:40.166277 Final DQM duty delay cell = 0
2391 13:21:40.169556 [0] MAX Duty = 5156%(X100), DQS PI = 62
2392 13:21:40.172852 [0] MIN Duty = 4969%(X100), DQS PI = 8
2393 13:21:40.173253 [0] AVG Duty = 5062%(X100)
2394 13:21:40.173574
2395 13:21:40.176183 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2396 13:21:40.179518
2397 13:21:40.183000 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2398 13:21:40.186380 [DutyScan_Calibration_Flow] ====Done====
2399 13:21:40.186779
2400 13:21:40.189692 [DutyScan_Calibration_Flow] k_type=2
2401 13:21:40.204961
2402 13:21:40.205362 ==DQ 0 ==
2403 13:21:40.208857 Final DQ duty delay cell = -4
2404 13:21:40.211646 [-4] MAX Duty = 5031%(X100), DQS PI = 0
2405 13:21:40.215008 [-4] MIN Duty = 4844%(X100), DQS PI = 18
2406 13:21:40.218203 [-4] AVG Duty = 4937%(X100)
2407 13:21:40.218634
2408 13:21:40.219041 ==DQ 1 ==
2409 13:21:40.221866 Final DQ duty delay cell = 0
2410 13:21:40.225221 [0] MAX Duty = 5031%(X100), DQS PI = 18
2411 13:21:40.228371 [0] MIN Duty = 4907%(X100), DQS PI = 46
2412 13:21:40.228888 [0] AVG Duty = 4969%(X100)
2413 13:21:40.229254
2414 13:21:40.234923 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2415 13:21:40.235371
2416 13:21:40.238204 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2417 13:21:40.241840 [DutyScan_Calibration_Flow] ====Done====
2418 13:21:40.242319 ==
2419 13:21:40.244940 Dram Type= 6, Freq= 0, CH_1, rank 0
2420 13:21:40.248271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2421 13:21:40.248768 ==
2422 13:21:40.252221 [Duty_Offset_Calibration]
2423 13:21:40.252717 B0:1 B1:1 CA:2
2424 13:21:40.253214
2425 13:21:40.255036 [DutyScan_Calibration_Flow] k_type=0
2426 13:21:40.264970
2427 13:21:40.265418 ==CLK 0==
2428 13:21:40.268127 Final CLK duty delay cell = 0
2429 13:21:40.272253 [0] MAX Duty = 5125%(X100), DQS PI = 24
2430 13:21:40.275055 [0] MIN Duty = 4969%(X100), DQS PI = 40
2431 13:21:40.275458 [0] AVG Duty = 5047%(X100)
2432 13:21:40.275777
2433 13:21:40.278738 CH1 CLK Duty spec in!! Max-Min= 156%
2434 13:21:40.285398 [DutyScan_Calibration_Flow] ====Done====
2435 13:21:40.285844
2436 13:21:40.288404 [DutyScan_Calibration_Flow] k_type=1
2437 13:21:40.304609
2438 13:21:40.305110 ==DQS 0 ==
2439 13:21:40.307579 Final DQS duty delay cell = 0
2440 13:21:40.311327 [0] MAX Duty = 5031%(X100), DQS PI = 18
2441 13:21:40.314564 [0] MIN Duty = 4875%(X100), DQS PI = 30
2442 13:21:40.314970 [0] AVG Duty = 4953%(X100)
2443 13:21:40.318164
2444 13:21:40.318566 ==DQS 1 ==
2445 13:21:40.321281 Final DQS duty delay cell = 0
2446 13:21:40.324561 [0] MAX Duty = 5062%(X100), DQS PI = 36
2447 13:21:40.328216 [0] MIN Duty = 4907%(X100), DQS PI = 14
2448 13:21:40.328620 [0] AVG Duty = 4984%(X100)
2449 13:21:40.328997
2450 13:21:40.334576 CH1 DQS 0 Duty spec in!! Max-Min= 156%
2451 13:21:40.334980
2452 13:21:40.338208 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2453 13:21:40.341421 [DutyScan_Calibration_Flow] ====Done====
2454 13:21:40.341829
2455 13:21:40.344656 [DutyScan_Calibration_Flow] k_type=3
2456 13:21:40.360983
2457 13:21:40.361437 ==DQM 0 ==
2458 13:21:40.363972 Final DQM duty delay cell = 0
2459 13:21:40.367684 [0] MAX Duty = 5093%(X100), DQS PI = 18
2460 13:21:40.371496 [0] MIN Duty = 4876%(X100), DQS PI = 50
2461 13:21:40.374204 [0] AVG Duty = 4984%(X100)
2462 13:21:40.374695
2463 13:21:40.375064 ==DQM 1 ==
2464 13:21:40.377719 Final DQM duty delay cell = 0
2465 13:21:40.381250 [0] MAX Duty = 5156%(X100), DQS PI = 62
2466 13:21:40.384517 [0] MIN Duty = 4938%(X100), DQS PI = 22
2467 13:21:40.385030 [0] AVG Duty = 5047%(X100)
2468 13:21:40.387647
2469 13:21:40.391009 CH1 DQM 0 Duty spec in!! Max-Min= 217%
2470 13:21:40.391464
2471 13:21:40.394269 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2472 13:21:40.398239 [DutyScan_Calibration_Flow] ====Done====
2473 13:21:40.398676
2474 13:21:40.401062 [DutyScan_Calibration_Flow] k_type=2
2475 13:21:40.417271
2476 13:21:40.417716 ==DQ 0 ==
2477 13:21:40.420920 Final DQ duty delay cell = 0
2478 13:21:40.424076 [0] MAX Duty = 5125%(X100), DQS PI = 18
2479 13:21:40.427529 [0] MIN Duty = 4938%(X100), DQS PI = 50
2480 13:21:40.427964 [0] AVG Duty = 5031%(X100)
2481 13:21:40.431100
2482 13:21:40.431516 ==DQ 1 ==
2483 13:21:40.434442 Final DQ duty delay cell = 0
2484 13:21:40.437797 [0] MAX Duty = 5093%(X100), DQS PI = 8
2485 13:21:40.441305 [0] MIN Duty = 5000%(X100), DQS PI = 50
2486 13:21:40.441707 [0] AVG Duty = 5046%(X100)
2487 13:21:40.442064
2488 13:21:40.444522 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2489 13:21:40.444972
2490 13:21:40.448303 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2491 13:21:40.451090 [DutyScan_Calibration_Flow] ====Done====
2492 13:21:40.456606 nWR fixed to 30
2493 13:21:40.460025 [ModeRegInit_LP4] CH0 RK0
2494 13:21:40.460465 [ModeRegInit_LP4] CH0 RK1
2495 13:21:40.463424 [ModeRegInit_LP4] CH1 RK0
2496 13:21:40.466662 [ModeRegInit_LP4] CH1 RK1
2497 13:21:40.467113 match AC timing 7
2498 13:21:40.473290 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2499 13:21:40.477207 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2500 13:21:40.480022 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2501 13:21:40.486916 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2502 13:21:40.489919 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2503 13:21:40.490372 ==
2504 13:21:40.493288 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 13:21:40.497286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 13:21:40.497742 ==
2507 13:21:40.503260 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2508 13:21:40.510183 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2509 13:21:40.517515 [CA 0] Center 40 (10~71) winsize 62
2510 13:21:40.520715 [CA 1] Center 39 (9~70) winsize 62
2511 13:21:40.523994 [CA 2] Center 36 (6~67) winsize 62
2512 13:21:40.527913 [CA 3] Center 35 (5~66) winsize 62
2513 13:21:40.531325 [CA 4] Center 34 (4~65) winsize 62
2514 13:21:40.534455 [CA 5] Center 34 (4~64) winsize 61
2515 13:21:40.534859
2516 13:21:40.538024 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2517 13:21:40.538431
2518 13:21:40.541448 [CATrainingPosCal] consider 1 rank data
2519 13:21:40.544644 u2DelayCellTimex100 = 270/100 ps
2520 13:21:40.547702 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2521 13:21:40.551171 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2522 13:21:40.554431 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2523 13:21:40.561244 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2524 13:21:40.564806 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2525 13:21:40.567920 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2526 13:21:40.568323
2527 13:21:40.571783 CA PerBit enable=1, Macro0, CA PI delay=34
2528 13:21:40.572267
2529 13:21:40.574906 [CBTSetCACLKResult] CA Dly = 34
2530 13:21:40.575309 CS Dly: 7 (0~38)
2531 13:21:40.575628 ==
2532 13:21:40.578021 Dram Type= 6, Freq= 0, CH_0, rank 1
2533 13:21:40.584936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 13:21:40.585384 ==
2535 13:21:40.588083 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2536 13:21:40.594788 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2537 13:21:40.603476 [CA 0] Center 39 (9~70) winsize 62
2538 13:21:40.606873 [CA 1] Center 40 (10~70) winsize 61
2539 13:21:40.610199 [CA 2] Center 36 (6~67) winsize 62
2540 13:21:40.613323 [CA 3] Center 36 (5~67) winsize 63
2541 13:21:40.617181 [CA 4] Center 34 (4~65) winsize 62
2542 13:21:40.620356 [CA 5] Center 34 (4~64) winsize 61
2543 13:21:40.620807
2544 13:21:40.623232 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2545 13:21:40.623634
2546 13:21:40.626773 [CATrainingPosCal] consider 2 rank data
2547 13:21:40.630171 u2DelayCellTimex100 = 270/100 ps
2548 13:21:40.633463 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2549 13:21:40.640114 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2550 13:21:40.643706 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2551 13:21:40.646763 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2552 13:21:40.650045 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2553 13:21:40.653440 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2554 13:21:40.653846
2555 13:21:40.657304 CA PerBit enable=1, Macro0, CA PI delay=34
2556 13:21:40.657721
2557 13:21:40.660458 [CBTSetCACLKResult] CA Dly = 34
2558 13:21:40.660979 CS Dly: 8 (0~41)
2559 13:21:40.661346
2560 13:21:40.664094 ----->DramcWriteLeveling(PI) begin...
2561 13:21:40.667048 ==
2562 13:21:40.667448 Dram Type= 6, Freq= 0, CH_0, rank 0
2563 13:21:40.673522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2564 13:21:40.673977 ==
2565 13:21:40.677198 Write leveling (Byte 0): 29 => 29
2566 13:21:40.680574 Write leveling (Byte 1): 30 => 30
2567 13:21:40.681026 DramcWriteLeveling(PI) end<-----
2568 13:21:40.683661
2569 13:21:40.684061 ==
2570 13:21:40.687268 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 13:21:40.690424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 13:21:40.690829 ==
2573 13:21:40.693911 [Gating] SW mode calibration
2574 13:21:40.700637 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2575 13:21:40.703872 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2576 13:21:40.710875 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2577 13:21:40.713797 0 15 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2578 13:21:40.717773 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2579 13:21:40.723788 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 13:21:40.727759 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 13:21:40.730964 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 13:21:40.737454 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 13:21:40.741379 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 13:21:40.744219 1 0 0 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 1)
2585 13:21:40.747358 1 0 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
2586 13:21:40.754099 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 13:21:40.757643 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 13:21:40.760782 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 13:21:40.767832 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 13:21:40.771355 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 13:21:40.774586 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 13:21:40.781132 1 1 0 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
2593 13:21:40.784393 1 1 4 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
2594 13:21:40.787945 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 13:21:40.794619 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 13:21:40.797736 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 13:21:40.801323 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 13:21:40.804422 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 13:21:40.812142 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 13:21:40.814631 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2601 13:21:40.818348 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 13:21:40.824719 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 13:21:40.827799 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 13:21:40.831183 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 13:21:40.837866 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 13:21:40.841491 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 13:21:40.844450 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 13:21:40.851443 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 13:21:40.854681 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 13:21:40.858178 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 13:21:40.864651 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 13:21:40.867877 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 13:21:40.871568 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 13:21:40.874861 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 13:21:40.882037 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 13:21:40.884724 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2617 13:21:40.888297 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 13:21:40.891927 Total UI for P1: 0, mck2ui 16
2619 13:21:40.894888 best dqsien dly found for B0: ( 1, 4, 0)
2620 13:21:40.898201 Total UI for P1: 0, mck2ui 16
2621 13:21:40.901660 best dqsien dly found for B1: ( 1, 4, 0)
2622 13:21:40.905249 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2623 13:21:40.908396 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2624 13:21:40.908926
2625 13:21:40.915133 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2626 13:21:40.918383 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2627 13:21:40.918916 [Gating] SW calibration Done
2628 13:21:40.919253 ==
2629 13:21:40.921618 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 13:21:40.928506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 13:21:40.928963 ==
2632 13:21:40.929292 RX Vref Scan: 0
2633 13:21:40.929592
2634 13:21:40.932159 RX Vref 0 -> 0, step: 1
2635 13:21:40.932565
2636 13:21:40.935210 RX Delay -40 -> 252, step: 8
2637 13:21:40.938825 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2638 13:21:40.941922 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2639 13:21:40.945161 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2640 13:21:40.948724 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2641 13:21:40.955378 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2642 13:21:40.959146 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2643 13:21:40.962153 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2644 13:21:40.965530 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2645 13:21:40.969034 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2646 13:21:40.975385 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2647 13:21:40.978790 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2648 13:21:40.982262 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2649 13:21:40.985434 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2650 13:21:40.989098 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2651 13:21:40.995176 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2652 13:21:40.998498 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2653 13:21:40.998577 ==
2654 13:21:41.001810 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 13:21:41.005311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 13:21:41.005391 ==
2657 13:21:41.005454 DQS Delay:
2658 13:21:41.008816 DQS0 = 0, DQS1 = 0
2659 13:21:41.008895 DQM Delay:
2660 13:21:41.012181 DQM0 = 116, DQM1 = 107
2661 13:21:41.012259 DQ Delay:
2662 13:21:41.015406 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2663 13:21:41.018560 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2664 13:21:41.022530 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2665 13:21:41.025784 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2666 13:21:41.025862
2667 13:21:41.025924
2668 13:21:41.028717 ==
2669 13:21:41.028796 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 13:21:41.035447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 13:21:41.035527 ==
2672 13:21:41.035589
2673 13:21:41.035646
2674 13:21:41.035701 TX Vref Scan disable
2675 13:21:41.039469 == TX Byte 0 ==
2676 13:21:41.042656 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2677 13:21:41.046141 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2678 13:21:41.049409 == TX Byte 1 ==
2679 13:21:41.052861 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2680 13:21:41.056073 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2681 13:21:41.059123 ==
2682 13:21:41.062864 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 13:21:41.065975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 13:21:41.066116 ==
2685 13:21:41.077197 TX Vref=22, minBit 1, minWin=25, winSum=414
2686 13:21:41.081012 TX Vref=24, minBit 5, minWin=25, winSum=421
2687 13:21:41.083893 TX Vref=26, minBit 4, minWin=25, winSum=422
2688 13:21:41.087072 TX Vref=28, minBit 1, minWin=26, winSum=429
2689 13:21:41.090619 TX Vref=30, minBit 0, minWin=26, winSum=429
2690 13:21:41.093747 TX Vref=32, minBit 1, minWin=26, winSum=432
2691 13:21:41.100544 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 32
2692 13:21:41.100649
2693 13:21:41.103709 Final TX Range 1 Vref 32
2694 13:21:41.103814
2695 13:21:41.103878 ==
2696 13:21:41.107279 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 13:21:41.110932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2698 13:21:41.111012 ==
2699 13:21:41.111075
2700 13:21:41.111132
2701 13:21:41.113867 TX Vref Scan disable
2702 13:21:41.117310 == TX Byte 0 ==
2703 13:21:41.120500 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2704 13:21:41.124294 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2705 13:21:41.127200 == TX Byte 1 ==
2706 13:21:41.130770 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2707 13:21:41.134032 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2708 13:21:41.134111
2709 13:21:41.137758 [DATLAT]
2710 13:21:41.137837 Freq=1200, CH0 RK0
2711 13:21:41.137900
2712 13:21:41.140941 DATLAT Default: 0xd
2713 13:21:41.141019 0, 0xFFFF, sum = 0
2714 13:21:41.144433 1, 0xFFFF, sum = 0
2715 13:21:41.144539 2, 0xFFFF, sum = 0
2716 13:21:41.147799 3, 0xFFFF, sum = 0
2717 13:21:41.147880 4, 0xFFFF, sum = 0
2718 13:21:41.151407 5, 0xFFFF, sum = 0
2719 13:21:41.151488 6, 0xFFFF, sum = 0
2720 13:21:41.154611 7, 0xFFFF, sum = 0
2721 13:21:41.154690 8, 0xFFFF, sum = 0
2722 13:21:41.157886 9, 0xFFFF, sum = 0
2723 13:21:41.157993 10, 0xFFFF, sum = 0
2724 13:21:41.161132 11, 0xFFFF, sum = 0
2725 13:21:41.161259 12, 0x0, sum = 1
2726 13:21:41.164055 13, 0x0, sum = 2
2727 13:21:41.164175 14, 0x0, sum = 3
2728 13:21:41.167450 15, 0x0, sum = 4
2729 13:21:41.167553 best_step = 13
2730 13:21:41.167650
2731 13:21:41.167744 ==
2732 13:21:41.171032 Dram Type= 6, Freq= 0, CH_0, rank 0
2733 13:21:41.174493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2734 13:21:41.178215 ==
2735 13:21:41.178314 RX Vref Scan: 1
2736 13:21:41.178407
2737 13:21:41.181167 Set Vref Range= 32 -> 127
2738 13:21:41.181289
2739 13:21:41.184581 RX Vref 32 -> 127, step: 1
2740 13:21:41.184719
2741 13:21:41.184829 RX Delay -21 -> 252, step: 4
2742 13:21:41.184938
2743 13:21:41.188293 Set Vref, RX VrefLevel [Byte0]: 32
2744 13:21:41.191278 [Byte1]: 32
2745 13:21:41.195427
2746 13:21:41.195527 Set Vref, RX VrefLevel [Byte0]: 33
2747 13:21:41.198523 [Byte1]: 33
2748 13:21:41.203115
2749 13:21:41.203218 Set Vref, RX VrefLevel [Byte0]: 34
2750 13:21:41.206590 [Byte1]: 34
2751 13:21:41.211225
2752 13:21:41.211358 Set Vref, RX VrefLevel [Byte0]: 35
2753 13:21:41.214786 [Byte1]: 35
2754 13:21:41.219503
2755 13:21:41.219584 Set Vref, RX VrefLevel [Byte0]: 36
2756 13:21:41.222509 [Byte1]: 36
2757 13:21:41.227388
2758 13:21:41.227470 Set Vref, RX VrefLevel [Byte0]: 37
2759 13:21:41.230363 [Byte1]: 37
2760 13:21:41.235123
2761 13:21:41.235204 Set Vref, RX VrefLevel [Byte0]: 38
2762 13:21:41.238347 [Byte1]: 38
2763 13:21:41.243272
2764 13:21:41.243357 Set Vref, RX VrefLevel [Byte0]: 39
2765 13:21:41.246463 [Byte1]: 39
2766 13:21:41.251102
2767 13:21:41.251184 Set Vref, RX VrefLevel [Byte0]: 40
2768 13:21:41.254616 [Byte1]: 40
2769 13:21:41.259102
2770 13:21:41.259184 Set Vref, RX VrefLevel [Byte0]: 41
2771 13:21:41.262659 [Byte1]: 41
2772 13:21:41.266831
2773 13:21:41.266912 Set Vref, RX VrefLevel [Byte0]: 42
2774 13:21:41.270141 [Byte1]: 42
2775 13:21:41.274866
2776 13:21:41.274948 Set Vref, RX VrefLevel [Byte0]: 43
2777 13:21:41.277973 [Byte1]: 43
2778 13:21:41.282549
2779 13:21:41.282631 Set Vref, RX VrefLevel [Byte0]: 44
2780 13:21:41.285837 [Byte1]: 44
2781 13:21:41.290803
2782 13:21:41.290885 Set Vref, RX VrefLevel [Byte0]: 45
2783 13:21:41.293657 [Byte1]: 45
2784 13:21:41.298213
2785 13:21:41.298294 Set Vref, RX VrefLevel [Byte0]: 46
2786 13:21:41.301721 [Byte1]: 46
2787 13:21:41.306082
2788 13:21:41.306164 Set Vref, RX VrefLevel [Byte0]: 47
2789 13:21:41.309586 [Byte1]: 47
2790 13:21:41.314670
2791 13:21:41.314751 Set Vref, RX VrefLevel [Byte0]: 48
2792 13:21:41.317628 [Byte1]: 48
2793 13:21:41.322584
2794 13:21:41.322669 Set Vref, RX VrefLevel [Byte0]: 49
2795 13:21:41.325711 [Byte1]: 49
2796 13:21:41.330197
2797 13:21:41.330279 Set Vref, RX VrefLevel [Byte0]: 50
2798 13:21:41.333665 [Byte1]: 50
2799 13:21:41.338038
2800 13:21:41.338119 Set Vref, RX VrefLevel [Byte0]: 51
2801 13:21:41.341739 [Byte1]: 51
2802 13:21:41.346073
2803 13:21:41.346154 Set Vref, RX VrefLevel [Byte0]: 52
2804 13:21:41.349507 [Byte1]: 52
2805 13:21:41.353727
2806 13:21:41.353808 Set Vref, RX VrefLevel [Byte0]: 53
2807 13:21:41.357606 [Byte1]: 53
2808 13:21:41.362037
2809 13:21:41.362118 Set Vref, RX VrefLevel [Byte0]: 54
2810 13:21:41.364902 [Byte1]: 54
2811 13:21:41.369890
2812 13:21:41.369971 Set Vref, RX VrefLevel [Byte0]: 55
2813 13:21:41.373154 [Byte1]: 55
2814 13:21:41.377539
2815 13:21:41.377620 Set Vref, RX VrefLevel [Byte0]: 56
2816 13:21:41.381087 [Byte1]: 56
2817 13:21:41.385530
2818 13:21:41.385611 Set Vref, RX VrefLevel [Byte0]: 57
2819 13:21:41.388637 [Byte1]: 57
2820 13:21:41.393395
2821 13:21:41.393476 Set Vref, RX VrefLevel [Byte0]: 58
2822 13:21:41.396835 [Byte1]: 58
2823 13:21:41.401517
2824 13:21:41.401598 Set Vref, RX VrefLevel [Byte0]: 59
2825 13:21:41.404836 [Byte1]: 59
2826 13:21:41.409849
2827 13:21:41.409934 Set Vref, RX VrefLevel [Byte0]: 60
2828 13:21:41.412520 [Byte1]: 60
2829 13:21:41.417379
2830 13:21:41.417460 Set Vref, RX VrefLevel [Byte0]: 61
2831 13:21:41.420495 [Byte1]: 61
2832 13:21:41.425501
2833 13:21:41.425582 Set Vref, RX VrefLevel [Byte0]: 62
2834 13:21:41.428554 [Byte1]: 62
2835 13:21:41.433033
2836 13:21:41.433115 Set Vref, RX VrefLevel [Byte0]: 63
2837 13:21:41.436372 [Byte1]: 63
2838 13:21:41.441258
2839 13:21:41.441339 Set Vref, RX VrefLevel [Byte0]: 64
2840 13:21:41.444251 [Byte1]: 64
2841 13:21:41.449102
2842 13:21:41.449180 Set Vref, RX VrefLevel [Byte0]: 65
2843 13:21:41.452323 [Byte1]: 65
2844 13:21:41.457155
2845 13:21:41.457233 Set Vref, RX VrefLevel [Byte0]: 66
2846 13:21:41.460295 [Byte1]: 66
2847 13:21:41.464900
2848 13:21:41.464978 Set Vref, RX VrefLevel [Byte0]: 67
2849 13:21:41.468077 [Byte1]: 67
2850 13:21:41.472833
2851 13:21:41.472911 Set Vref, RX VrefLevel [Byte0]: 68
2852 13:21:41.475959 [Byte1]: 68
2853 13:21:41.480919
2854 13:21:41.480997 Set Vref, RX VrefLevel [Byte0]: 69
2855 13:21:41.484159 [Byte1]: 69
2856 13:21:41.488651
2857 13:21:41.488739 Set Vref, RX VrefLevel [Byte0]: 70
2858 13:21:41.491948 [Byte1]: 70
2859 13:21:41.496633
2860 13:21:41.496757 Final RX Vref Byte 0 = 53 to rank0
2861 13:21:41.499938 Final RX Vref Byte 1 = 53 to rank0
2862 13:21:41.503275 Final RX Vref Byte 0 = 53 to rank1
2863 13:21:41.506607 Final RX Vref Byte 1 = 53 to rank1==
2864 13:21:41.510169 Dram Type= 6, Freq= 0, CH_0, rank 0
2865 13:21:41.513139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2866 13:21:41.516646 ==
2867 13:21:41.516764 DQS Delay:
2868 13:21:41.516825 DQS0 = 0, DQS1 = 0
2869 13:21:41.519920 DQM Delay:
2870 13:21:41.519998 DQM0 = 115, DQM1 = 105
2871 13:21:41.523535 DQ Delay:
2872 13:21:41.527040 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2873 13:21:41.529796 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =122
2874 13:21:41.533251 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =96
2875 13:21:41.536638 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2876 13:21:41.536761
2877 13:21:41.536823
2878 13:21:41.543628 [DQSOSCAuto] RK0, (LSB)MR18= 0xfeed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2879 13:21:41.546893 CH0 RK0: MR19=303, MR18=FEED
2880 13:21:41.553553 CH0_RK0: MR19=0x303, MR18=0xFEED, DQSOSC=410, MR23=63, INC=39, DEC=26
2881 13:21:41.553632
2882 13:21:41.557028 ----->DramcWriteLeveling(PI) begin...
2883 13:21:41.557108 ==
2884 13:21:41.560380 Dram Type= 6, Freq= 0, CH_0, rank 1
2885 13:21:41.564140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2886 13:21:41.564220 ==
2887 13:21:41.567121 Write leveling (Byte 0): 31 => 31
2888 13:21:41.570311 Write leveling (Byte 1): 29 => 29
2889 13:21:41.573509 DramcWriteLeveling(PI) end<-----
2890 13:21:41.573587
2891 13:21:41.573648 ==
2892 13:21:41.576659 Dram Type= 6, Freq= 0, CH_0, rank 1
2893 13:21:41.580318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2894 13:21:41.583502 ==
2895 13:21:41.583580 [Gating] SW mode calibration
2896 13:21:41.590576 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2897 13:21:41.597134 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2898 13:21:41.600643 0 15 0 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
2899 13:21:41.607172 0 15 4 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
2900 13:21:41.610599 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 13:21:41.614014 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2902 13:21:41.617318 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2903 13:21:41.624330 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2904 13:21:41.627466 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2905 13:21:41.630484 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
2906 13:21:41.637554 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2907 13:21:41.640682 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 13:21:41.644496 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 13:21:41.651123 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 13:21:41.654394 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 13:21:41.657413 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 13:21:41.664431 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2913 13:21:41.667932 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2914 13:21:41.671014 1 1 0 | B1->B0 | 3535 4343 | 0 0 | (0 0) (0 0)
2915 13:21:41.674816 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 13:21:41.681263 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 13:21:41.684513 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 13:21:41.687492 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 13:21:41.694173 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 13:21:41.697930 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2921 13:21:41.701126 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2922 13:21:41.708175 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2923 13:21:41.711230 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 13:21:41.714675 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 13:21:41.721094 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 13:21:41.724472 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 13:21:41.728019 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 13:21:41.734845 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 13:21:41.738106 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 13:21:41.741019 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 13:21:41.748339 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 13:21:41.751481 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 13:21:41.754730 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 13:21:41.758194 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 13:21:41.765080 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 13:21:41.768228 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2937 13:21:41.771435 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2938 13:21:41.778620 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2939 13:21:41.778699 Total UI for P1: 0, mck2ui 16
2940 13:21:41.784776 best dqsien dly found for B0: ( 1, 3, 26)
2941 13:21:41.788340 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2942 13:21:41.791587 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 13:21:41.795181 Total UI for P1: 0, mck2ui 16
2944 13:21:41.798410 best dqsien dly found for B1: ( 1, 4, 2)
2945 13:21:41.802079 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2946 13:21:41.805321 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2947 13:21:41.805401
2948 13:21:41.808434 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2949 13:21:41.812309 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2950 13:21:41.815365 [Gating] SW calibration Done
2951 13:21:41.815444 ==
2952 13:21:41.818468 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 13:21:41.825184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 13:21:41.825264 ==
2955 13:21:41.825325 RX Vref Scan: 0
2956 13:21:41.825383
2957 13:21:41.828702 RX Vref 0 -> 0, step: 1
2958 13:21:41.828797
2959 13:21:41.832270 RX Delay -40 -> 252, step: 8
2960 13:21:41.835148 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2961 13:21:41.838330 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2962 13:21:41.841896 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2963 13:21:41.845564 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2964 13:21:41.851886 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2965 13:21:41.854994 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2966 13:21:41.858522 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2967 13:21:41.861937 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2968 13:21:41.865148 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2969 13:21:41.868702 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2970 13:21:41.875605 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2971 13:21:41.879026 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2972 13:21:41.882068 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2973 13:21:41.885299 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2974 13:21:41.889134 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2975 13:21:41.895623 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2976 13:21:41.895702 ==
2977 13:21:41.898754 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 13:21:41.902365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 13:21:41.902445 ==
2980 13:21:41.902507 DQS Delay:
2981 13:21:41.905866 DQS0 = 0, DQS1 = 0
2982 13:21:41.905944 DQM Delay:
2983 13:21:41.908893 DQM0 = 115, DQM1 = 105
2984 13:21:41.908972 DQ Delay:
2985 13:21:41.912235 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2986 13:21:41.915735 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2987 13:21:41.919051 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2988 13:21:41.922349 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2989 13:21:41.922428
2990 13:21:41.922490
2991 13:21:41.922547 ==
2992 13:21:41.926117 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 13:21:41.932455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 13:21:41.932538 ==
2995 13:21:41.932600
2996 13:21:41.932657
2997 13:21:41.932754 TX Vref Scan disable
2998 13:21:41.936062 == TX Byte 0 ==
2999 13:21:41.939237 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3000 13:21:41.942945 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3001 13:21:41.945919 == TX Byte 1 ==
3002 13:21:41.949286 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3003 13:21:41.952911 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3004 13:21:41.956470 ==
3005 13:21:41.956552 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 13:21:41.963091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 13:21:41.963174 ==
3008 13:21:41.974226 TX Vref=22, minBit 5, minWin=25, winSum=426
3009 13:21:41.977207 TX Vref=24, minBit 1, minWin=26, winSum=432
3010 13:21:41.980926 TX Vref=26, minBit 1, minWin=26, winSum=433
3011 13:21:41.984258 TX Vref=28, minBit 5, minWin=26, winSum=436
3012 13:21:41.987595 TX Vref=30, minBit 12, minWin=26, winSum=440
3013 13:21:41.990972 TX Vref=32, minBit 5, minWin=26, winSum=434
3014 13:21:41.997666 [TxChooseVref] Worse bit 12, Min win 26, Win sum 440, Final Vref 30
3015 13:21:41.997748
3016 13:21:42.000858 Final TX Range 1 Vref 30
3017 13:21:42.000941
3018 13:21:42.001024 ==
3019 13:21:42.004331 Dram Type= 6, Freq= 0, CH_0, rank 1
3020 13:21:42.007571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3021 13:21:42.007650 ==
3022 13:21:42.007712
3023 13:21:42.010586
3024 13:21:42.010664 TX Vref Scan disable
3025 13:21:42.014160 == TX Byte 0 ==
3026 13:21:42.017636 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3027 13:21:42.021270 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3028 13:21:42.024263 == TX Byte 1 ==
3029 13:21:42.027893 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3030 13:21:42.031222 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3031 13:21:42.031301
3032 13:21:42.034169 [DATLAT]
3033 13:21:42.034248 Freq=1200, CH0 RK1
3034 13:21:42.034310
3035 13:21:42.037789 DATLAT Default: 0xd
3036 13:21:42.037893 0, 0xFFFF, sum = 0
3037 13:21:42.040795 1, 0xFFFF, sum = 0
3038 13:21:42.040891 2, 0xFFFF, sum = 0
3039 13:21:42.044306 3, 0xFFFF, sum = 0
3040 13:21:42.044386 4, 0xFFFF, sum = 0
3041 13:21:42.047696 5, 0xFFFF, sum = 0
3042 13:21:42.047802 6, 0xFFFF, sum = 0
3043 13:21:42.050814 7, 0xFFFF, sum = 0
3044 13:21:42.050919 8, 0xFFFF, sum = 0
3045 13:21:42.054427 9, 0xFFFF, sum = 0
3046 13:21:42.054507 10, 0xFFFF, sum = 0
3047 13:21:42.057563 11, 0xFFFF, sum = 0
3048 13:21:42.061137 12, 0x0, sum = 1
3049 13:21:42.061217 13, 0x0, sum = 2
3050 13:21:42.061281 14, 0x0, sum = 3
3051 13:21:42.064462 15, 0x0, sum = 4
3052 13:21:42.064568 best_step = 13
3053 13:21:42.064657
3054 13:21:42.064731 ==
3055 13:21:42.067512 Dram Type= 6, Freq= 0, CH_0, rank 1
3056 13:21:42.074300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3057 13:21:42.074379 ==
3058 13:21:42.074441 RX Vref Scan: 0
3059 13:21:42.074499
3060 13:21:42.077516 RX Vref 0 -> 0, step: 1
3061 13:21:42.077594
3062 13:21:42.081431 RX Delay -21 -> 252, step: 4
3063 13:21:42.084845 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3064 13:21:42.087729 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3065 13:21:42.094785 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3066 13:21:42.097582 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3067 13:21:42.101111 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3068 13:21:42.104421 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3069 13:21:42.107822 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3070 13:21:42.114392 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3071 13:21:42.118189 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3072 13:21:42.121134 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3073 13:21:42.124479 iDelay=195, Bit 10, Center 108 (39 ~ 178) 140
3074 13:21:42.127984 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3075 13:21:42.131529 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3076 13:21:42.137914 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3077 13:21:42.141500 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3078 13:21:42.144793 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3079 13:21:42.144872 ==
3080 13:21:42.148338 Dram Type= 6, Freq= 0, CH_0, rank 1
3081 13:21:42.151761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3082 13:21:42.151840 ==
3083 13:21:42.155385 DQS Delay:
3084 13:21:42.155489 DQS0 = 0, DQS1 = 0
3085 13:21:42.158013 DQM Delay:
3086 13:21:42.158091 DQM0 = 114, DQM1 = 105
3087 13:21:42.158154 DQ Delay:
3088 13:21:42.161480 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3089 13:21:42.168184 DQ4 =114, DQ5 =104, DQ6 =122, DQ7 =122
3090 13:21:42.172037 DQ8 =94, DQ9 =92, DQ10 =108, DQ11 =96
3091 13:21:42.174823 DQ12 =110, DQ13 =112, DQ14 =116, DQ15 =114
3092 13:21:42.174905
3093 13:21:42.174967
3094 13:21:42.181692 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3095 13:21:42.185214 CH0 RK1: MR19=403, MR18=3F5
3096 13:21:42.192146 CH0_RK1: MR19=0x403, MR18=0x3F5, DQSOSC=408, MR23=63, INC=39, DEC=26
3097 13:21:42.195055 [RxdqsGatingPostProcess] freq 1200
3098 13:21:42.198691 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3099 13:21:42.202066 best DQS0 dly(2T, 0.5T) = (0, 12)
3100 13:21:42.205250 best DQS1 dly(2T, 0.5T) = (0, 12)
3101 13:21:42.208440 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3102 13:21:42.212451 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3103 13:21:42.215489 best DQS0 dly(2T, 0.5T) = (0, 11)
3104 13:21:42.219081 best DQS1 dly(2T, 0.5T) = (0, 12)
3105 13:21:42.222209 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3106 13:21:42.225774 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3107 13:21:42.225853 Pre-setting of DQS Precalculation
3108 13:21:42.232593 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3109 13:21:42.232705 ==
3110 13:21:42.235393 Dram Type= 6, Freq= 0, CH_1, rank 0
3111 13:21:42.238780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 13:21:42.238860 ==
3113 13:21:42.245760 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3114 13:21:42.252464 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3115 13:21:42.259520 [CA 0] Center 38 (8~68) winsize 61
3116 13:21:42.262825 [CA 1] Center 38 (8~68) winsize 61
3117 13:21:42.266403 [CA 2] Center 35 (5~65) winsize 61
3118 13:21:42.270001 [CA 3] Center 34 (4~65) winsize 62
3119 13:21:42.273367 [CA 4] Center 34 (4~65) winsize 62
3120 13:21:42.276290 [CA 5] Center 34 (4~64) winsize 61
3121 13:21:42.276369
3122 13:21:42.279632 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3123 13:21:42.279710
3124 13:21:42.283286 [CATrainingPosCal] consider 1 rank data
3125 13:21:42.286870 u2DelayCellTimex100 = 270/100 ps
3126 13:21:42.289946 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3127 13:21:42.293198 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3128 13:21:42.296911 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3129 13:21:42.303803 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3130 13:21:42.306680 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3131 13:21:42.310036 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3132 13:21:42.310116
3133 13:21:42.313224 CA PerBit enable=1, Macro0, CA PI delay=34
3134 13:21:42.313336
3135 13:21:42.316705 [CBTSetCACLKResult] CA Dly = 34
3136 13:21:42.316783 CS Dly: 6 (0~37)
3137 13:21:42.316847 ==
3138 13:21:42.320019 Dram Type= 6, Freq= 0, CH_1, rank 1
3139 13:21:42.326642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3140 13:21:42.326722 ==
3141 13:21:42.330148 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3142 13:21:42.336622 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3143 13:21:42.345073 [CA 0] Center 38 (8~68) winsize 61
3144 13:21:42.348636 [CA 1] Center 38 (9~68) winsize 60
3145 13:21:42.352359 [CA 2] Center 34 (4~65) winsize 62
3146 13:21:42.355319 [CA 3] Center 34 (4~65) winsize 62
3147 13:21:42.359067 [CA 4] Center 34 (4~65) winsize 62
3148 13:21:42.361844 [CA 5] Center 33 (3~64) winsize 62
3149 13:21:42.361923
3150 13:21:42.365536 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3151 13:21:42.365614
3152 13:21:42.369243 [CATrainingPosCal] consider 2 rank data
3153 13:21:42.371901 u2DelayCellTimex100 = 270/100 ps
3154 13:21:42.375834 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3155 13:21:42.378952 CA1 delay=38 (9~68),Diff = 4 PI (19 cell)
3156 13:21:42.385362 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3157 13:21:42.388701 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3158 13:21:42.392309 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3159 13:21:42.395404 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3160 13:21:42.395484
3161 13:21:42.398734 CA PerBit enable=1, Macro0, CA PI delay=34
3162 13:21:42.398813
3163 13:21:42.402046 [CBTSetCACLKResult] CA Dly = 34
3164 13:21:42.402125 CS Dly: 7 (0~40)
3165 13:21:42.402187
3166 13:21:42.405464 ----->DramcWriteLeveling(PI) begin...
3167 13:21:42.405545 ==
3168 13:21:42.409094 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 13:21:42.415444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 13:21:42.415524 ==
3171 13:21:42.418827 Write leveling (Byte 0): 26 => 26
3172 13:21:42.422748 Write leveling (Byte 1): 28 => 28
3173 13:21:42.422827 DramcWriteLeveling(PI) end<-----
3174 13:21:42.422890
3175 13:21:42.425416 ==
3176 13:21:42.428834 Dram Type= 6, Freq= 0, CH_1, rank 0
3177 13:21:42.432038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3178 13:21:42.432121 ==
3179 13:21:42.435979 [Gating] SW mode calibration
3180 13:21:42.442385 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3181 13:21:42.445845 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3182 13:21:42.452539 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3183 13:21:42.455818 0 15 4 | B1->B0 | 3433 3434 | 1 1 | (1 1) (1 1)
3184 13:21:42.459072 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 13:21:42.465974 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3186 13:21:42.469004 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 13:21:42.472767 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 13:21:42.479452 0 15 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3189 13:21:42.482531 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3190 13:21:42.485858 1 0 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3191 13:21:42.489073 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 13:21:42.496236 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 13:21:42.499309 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 13:21:42.502483 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 13:21:42.509672 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 13:21:42.512983 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 13:21:42.516082 1 0 28 | B1->B0 | 2626 2424 | 1 0 | (0 0) (0 0)
3198 13:21:42.522731 1 1 0 | B1->B0 | 4141 3535 | 0 0 | (0 0) (0 0)
3199 13:21:42.525901 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 13:21:42.529606 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 13:21:42.536264 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 13:21:42.540163 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 13:21:42.543279 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 13:21:42.546239 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 13:21:42.552979 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 13:21:42.556243 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3207 13:21:42.559778 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 13:21:42.566786 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 13:21:42.569931 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 13:21:42.573219 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 13:21:42.580181 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 13:21:42.583323 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 13:21:42.586981 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 13:21:42.590074 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 13:21:42.596905 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 13:21:42.600175 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 13:21:42.603829 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 13:21:42.610713 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 13:21:42.614216 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 13:21:42.617254 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 13:21:42.623902 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3222 13:21:42.627479 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 13:21:42.630870 Total UI for P1: 0, mck2ui 16
3224 13:21:42.634170 best dqsien dly found for B0: ( 1, 3, 28)
3225 13:21:42.637417 Total UI for P1: 0, mck2ui 16
3226 13:21:42.640911 best dqsien dly found for B1: ( 1, 3, 28)
3227 13:21:42.644192 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3228 13:21:42.647882 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3229 13:21:42.648293
3230 13:21:42.651622 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3231 13:21:42.654620 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3232 13:21:42.658066 [Gating] SW calibration Done
3233 13:21:42.658471 ==
3234 13:21:42.661236 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 13:21:42.664436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 13:21:42.664890 ==
3237 13:21:42.667937 RX Vref Scan: 0
3238 13:21:42.668339
3239 13:21:42.668657 RX Vref 0 -> 0, step: 1
3240 13:21:42.671610
3241 13:21:42.672076 RX Delay -40 -> 252, step: 8
3242 13:21:42.678117 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3243 13:21:42.681548 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3244 13:21:42.685336 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3245 13:21:42.688519 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3246 13:21:42.692010 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3247 13:21:42.694779 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3248 13:21:42.701492 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3249 13:21:42.704745 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3250 13:21:42.707999 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3251 13:21:42.711496 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3252 13:21:42.714838 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3253 13:21:42.721860 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3254 13:21:42.725180 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3255 13:21:42.728093 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3256 13:21:42.731842 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3257 13:21:42.735278 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3258 13:21:42.735683 ==
3259 13:21:42.738714 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 13:21:42.744836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 13:21:42.745249 ==
3262 13:21:42.745572 DQS Delay:
3263 13:21:42.748616 DQS0 = 0, DQS1 = 0
3264 13:21:42.749057 DQM Delay:
3265 13:21:42.751573 DQM0 = 116, DQM1 = 109
3266 13:21:42.751980 DQ Delay:
3267 13:21:42.755170 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =119
3268 13:21:42.758405 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3269 13:21:42.762114 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3270 13:21:42.765135 DQ12 =123, DQ13 =115, DQ14 =111, DQ15 =111
3271 13:21:42.765543
3272 13:21:42.765867
3273 13:21:42.766164 ==
3274 13:21:42.768422 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 13:21:42.771608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 13:21:42.772048 ==
3277 13:21:42.775016
3278 13:21:42.775420
3279 13:21:42.775741 TX Vref Scan disable
3280 13:21:42.778383 == TX Byte 0 ==
3281 13:21:42.782013 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3282 13:21:42.785284 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3283 13:21:42.788569 == TX Byte 1 ==
3284 13:21:42.792095 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3285 13:21:42.795623 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3286 13:21:42.796032 ==
3287 13:21:42.798991 Dram Type= 6, Freq= 0, CH_1, rank 0
3288 13:21:42.805883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3289 13:21:42.806307 ==
3290 13:21:42.816010 TX Vref=22, minBit 2, minWin=24, winSum=413
3291 13:21:42.818940 TX Vref=24, minBit 1, minWin=25, winSum=416
3292 13:21:42.822448 TX Vref=26, minBit 0, minWin=26, winSum=423
3293 13:21:42.826114 TX Vref=28, minBit 1, minWin=25, winSum=424
3294 13:21:42.829108 TX Vref=30, minBit 0, minWin=26, winSum=431
3295 13:21:42.832593 TX Vref=32, minBit 11, minWin=25, winSum=430
3296 13:21:42.839307 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 30
3297 13:21:42.839731
3298 13:21:42.842773 Final TX Range 1 Vref 30
3299 13:21:42.843194
3300 13:21:42.843626 ==
3301 13:21:42.845958 Dram Type= 6, Freq= 0, CH_1, rank 0
3302 13:21:42.849692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3303 13:21:42.850114 ==
3304 13:21:42.850546
3305 13:21:42.850948
3306 13:21:42.853125 TX Vref Scan disable
3307 13:21:42.855948 == TX Byte 0 ==
3308 13:21:42.860343 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3309 13:21:42.863161 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3310 13:21:42.866300 == TX Byte 1 ==
3311 13:21:42.870005 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3312 13:21:42.873145 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3313 13:21:42.873581
3314 13:21:42.876387 [DATLAT]
3315 13:21:42.876874 Freq=1200, CH1 RK0
3316 13:21:42.877308
3317 13:21:42.880064 DATLAT Default: 0xd
3318 13:21:42.880481 0, 0xFFFF, sum = 0
3319 13:21:42.883002 1, 0xFFFF, sum = 0
3320 13:21:42.883430 2, 0xFFFF, sum = 0
3321 13:21:42.886362 3, 0xFFFF, sum = 0
3322 13:21:42.886830 4, 0xFFFF, sum = 0
3323 13:21:42.889560 5, 0xFFFF, sum = 0
3324 13:21:42.889986 6, 0xFFFF, sum = 0
3325 13:21:42.893314 7, 0xFFFF, sum = 0
3326 13:21:42.893740 8, 0xFFFF, sum = 0
3327 13:21:42.896356 9, 0xFFFF, sum = 0
3328 13:21:42.896820 10, 0xFFFF, sum = 0
3329 13:21:42.900021 11, 0xFFFF, sum = 0
3330 13:21:42.900447 12, 0x0, sum = 1
3331 13:21:42.903536 13, 0x0, sum = 2
3332 13:21:42.903964 14, 0x0, sum = 3
3333 13:21:42.906667 15, 0x0, sum = 4
3334 13:21:42.907094 best_step = 13
3335 13:21:42.907521
3336 13:21:42.907926 ==
3337 13:21:42.909683 Dram Type= 6, Freq= 0, CH_1, rank 0
3338 13:21:42.913439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3339 13:21:42.916631 ==
3340 13:21:42.917082 RX Vref Scan: 1
3341 13:21:42.917516
3342 13:21:42.919900 Set Vref Range= 32 -> 127
3343 13:21:42.920321
3344 13:21:42.920875 RX Vref 32 -> 127, step: 1
3345 13:21:42.923263
3346 13:21:42.923797 RX Delay -21 -> 252, step: 4
3347 13:21:42.924279
3348 13:21:42.926725 Set Vref, RX VrefLevel [Byte0]: 32
3349 13:21:42.930199 [Byte1]: 32
3350 13:21:42.934178
3351 13:21:42.934652 Set Vref, RX VrefLevel [Byte0]: 33
3352 13:21:42.937303 [Byte1]: 33
3353 13:21:42.941659
3354 13:21:42.941918 Set Vref, RX VrefLevel [Byte0]: 34
3355 13:21:42.945092 [Byte1]: 34
3356 13:21:42.949462
3357 13:21:42.949634 Set Vref, RX VrefLevel [Byte0]: 35
3358 13:21:42.953137 [Byte1]: 35
3359 13:21:42.958016
3360 13:21:42.958188 Set Vref, RX VrefLevel [Byte0]: 36
3361 13:21:42.960954 [Byte1]: 36
3362 13:21:42.965622
3363 13:21:42.965794 Set Vref, RX VrefLevel [Byte0]: 37
3364 13:21:42.968831 [Byte1]: 37
3365 13:21:42.973576
3366 13:21:42.973748 Set Vref, RX VrefLevel [Byte0]: 38
3367 13:21:42.977198 [Byte1]: 38
3368 13:21:42.981242
3369 13:21:42.981445 Set Vref, RX VrefLevel [Byte0]: 39
3370 13:21:42.984394 [Byte1]: 39
3371 13:21:42.989778
3372 13:21:42.990087 Set Vref, RX VrefLevel [Byte0]: 40
3373 13:21:42.992912 [Byte1]: 40
3374 13:21:42.997556
3375 13:21:42.997956 Set Vref, RX VrefLevel [Byte0]: 41
3376 13:21:43.000427 [Byte1]: 41
3377 13:21:43.005480
3378 13:21:43.005881 Set Vref, RX VrefLevel [Byte0]: 42
3379 13:21:43.008779 [Byte1]: 42
3380 13:21:43.012939
3381 13:21:43.013337 Set Vref, RX VrefLevel [Byte0]: 43
3382 13:21:43.016747 [Byte1]: 43
3383 13:21:43.020825
3384 13:21:43.021230 Set Vref, RX VrefLevel [Byte0]: 44
3385 13:21:43.024620 [Byte1]: 44
3386 13:21:43.028971
3387 13:21:43.029373 Set Vref, RX VrefLevel [Byte0]: 45
3388 13:21:43.032774 [Byte1]: 45
3389 13:21:43.037106
3390 13:21:43.037510 Set Vref, RX VrefLevel [Byte0]: 46
3391 13:21:43.040412 [Byte1]: 46
3392 13:21:43.044743
3393 13:21:43.045144 Set Vref, RX VrefLevel [Byte0]: 47
3394 13:21:43.048041 [Byte1]: 47
3395 13:21:43.052824
3396 13:21:43.053225 Set Vref, RX VrefLevel [Byte0]: 48
3397 13:21:43.056143 [Byte1]: 48
3398 13:21:43.060777
3399 13:21:43.061180 Set Vref, RX VrefLevel [Byte0]: 49
3400 13:21:43.064226 [Byte1]: 49
3401 13:21:43.068645
3402 13:21:43.069103 Set Vref, RX VrefLevel [Byte0]: 50
3403 13:21:43.072165 [Byte1]: 50
3404 13:21:43.076940
3405 13:21:43.077339 Set Vref, RX VrefLevel [Byte0]: 51
3406 13:21:43.080092 [Byte1]: 51
3407 13:21:43.084780
3408 13:21:43.085184 Set Vref, RX VrefLevel [Byte0]: 52
3409 13:21:43.087640 [Byte1]: 52
3410 13:21:43.092352
3411 13:21:43.092778 Set Vref, RX VrefLevel [Byte0]: 53
3412 13:21:43.095702 [Byte1]: 53
3413 13:21:43.100090
3414 13:21:43.100494 Set Vref, RX VrefLevel [Byte0]: 54
3415 13:21:43.103760 [Byte1]: 54
3416 13:21:43.108003
3417 13:21:43.108423 Set Vref, RX VrefLevel [Byte0]: 55
3418 13:21:43.111637 [Byte1]: 55
3419 13:21:43.116099
3420 13:21:43.116521 Set Vref, RX VrefLevel [Byte0]: 56
3421 13:21:43.119335 [Byte1]: 56
3422 13:21:43.123905
3423 13:21:43.124438 Set Vref, RX VrefLevel [Byte0]: 57
3424 13:21:43.127814 [Byte1]: 57
3425 13:21:43.132057
3426 13:21:43.132462 Set Vref, RX VrefLevel [Byte0]: 58
3427 13:21:43.135323 [Byte1]: 58
3428 13:21:43.140373
3429 13:21:43.140840 Set Vref, RX VrefLevel [Byte0]: 59
3430 13:21:43.143932 [Byte1]: 59
3431 13:21:43.147871
3432 13:21:43.148277 Set Vref, RX VrefLevel [Byte0]: 60
3433 13:21:43.151204 [Byte1]: 60
3434 13:21:43.155815
3435 13:21:43.156220 Set Vref, RX VrefLevel [Byte0]: 61
3436 13:21:43.159386 [Byte1]: 61
3437 13:21:43.163576
3438 13:21:43.163978 Set Vref, RX VrefLevel [Byte0]: 62
3439 13:21:43.167261 [Byte1]: 62
3440 13:21:43.171524
3441 13:21:43.171926 Set Vref, RX VrefLevel [Byte0]: 63
3442 13:21:43.174719 [Byte1]: 63
3443 13:21:43.179829
3444 13:21:43.180235 Set Vref, RX VrefLevel [Byte0]: 64
3445 13:21:43.182910 [Byte1]: 64
3446 13:21:43.187533
3447 13:21:43.187940 Set Vref, RX VrefLevel [Byte0]: 65
3448 13:21:43.190809 [Byte1]: 65
3449 13:21:43.195598
3450 13:21:43.196006 Set Vref, RX VrefLevel [Byte0]: 66
3451 13:21:43.199102 [Byte1]: 66
3452 13:21:43.203232
3453 13:21:43.203646 Set Vref, RX VrefLevel [Byte0]: 67
3454 13:21:43.206447 [Byte1]: 67
3455 13:21:43.211529
3456 13:21:43.211933 Set Vref, RX VrefLevel [Byte0]: 68
3457 13:21:43.214350 [Byte1]: 68
3458 13:21:43.219203
3459 13:21:43.219608 Set Vref, RX VrefLevel [Byte0]: 69
3460 13:21:43.222215 [Byte1]: 69
3461 13:21:43.227347
3462 13:21:43.227749 Final RX Vref Byte 0 = 60 to rank0
3463 13:21:43.230374 Final RX Vref Byte 1 = 51 to rank0
3464 13:21:43.233919 Final RX Vref Byte 0 = 60 to rank1
3465 13:21:43.236981 Final RX Vref Byte 1 = 51 to rank1==
3466 13:21:43.240579 Dram Type= 6, Freq= 0, CH_1, rank 0
3467 13:21:43.243795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3468 13:21:43.247266 ==
3469 13:21:43.247668 DQS Delay:
3470 13:21:43.247986 DQS0 = 0, DQS1 = 0
3471 13:21:43.250474 DQM Delay:
3472 13:21:43.251099 DQM0 = 116, DQM1 = 109
3473 13:21:43.253898 DQ Delay:
3474 13:21:43.257449 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =116
3475 13:21:43.260842 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3476 13:21:43.264039 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3477 13:21:43.267728 DQ12 =116, DQ13 =118, DQ14 =116, DQ15 =114
3478 13:21:43.268139
3479 13:21:43.268459
3480 13:21:43.273991 [DQSOSCAuto] RK0, (LSB)MR18= 0xfce0, (MSB)MR19= 0x303, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
3481 13:21:43.277797 CH1 RK0: MR19=303, MR18=FCE0
3482 13:21:43.284612 CH1_RK0: MR19=0x303, MR18=0xFCE0, DQSOSC=411, MR23=63, INC=38, DEC=25
3483 13:21:43.285053
3484 13:21:43.287399 ----->DramcWriteLeveling(PI) begin...
3485 13:21:43.287812 ==
3486 13:21:43.291012 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 13:21:43.294198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 13:21:43.294608 ==
3489 13:21:43.298111 Write leveling (Byte 0): 28 => 28
3490 13:21:43.301118 Write leveling (Byte 1): 28 => 28
3491 13:21:43.304345 DramcWriteLeveling(PI) end<-----
3492 13:21:43.304795
3493 13:21:43.305148 ==
3494 13:21:43.307648 Dram Type= 6, Freq= 0, CH_1, rank 1
3495 13:21:43.310855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3496 13:21:43.311264 ==
3497 13:21:43.314403 [Gating] SW mode calibration
3498 13:21:43.321598 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3499 13:21:43.327859 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3500 13:21:43.330993 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3501 13:21:43.334667 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 13:21:43.340990 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 13:21:43.344815 0 15 12 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
3504 13:21:43.347965 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3505 13:21:43.354416 0 15 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3506 13:21:43.358037 0 15 24 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (0 1)
3507 13:21:43.360930 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3508 13:21:43.367661 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 13:21:43.371231 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 13:21:43.374908 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 13:21:43.381229 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 13:21:43.384482 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 13:21:43.388291 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 13:21:43.394555 1 0 24 | B1->B0 | 2727 3c3c | 0 0 | (0 0) (1 1)
3515 13:21:43.397804 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3516 13:21:43.401323 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 13:21:43.407669 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 13:21:43.411782 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 13:21:43.414420 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 13:21:43.417912 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 13:21:43.424601 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3522 13:21:43.428039 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3523 13:21:43.431081 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3524 13:21:43.438217 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 13:21:43.441558 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 13:21:43.444913 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 13:21:43.451289 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 13:21:43.454979 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 13:21:43.457968 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 13:21:43.464772 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 13:21:43.468032 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 13:21:43.471215 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 13:21:43.477809 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 13:21:43.481228 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 13:21:43.484515 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 13:21:43.487886 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 13:21:43.494660 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3538 13:21:43.498025 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3539 13:21:43.501223 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3540 13:21:43.504488 Total UI for P1: 0, mck2ui 16
3541 13:21:43.507795 best dqsien dly found for B0: ( 1, 3, 22)
3542 13:21:43.514443 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 13:21:43.517790 Total UI for P1: 0, mck2ui 16
3544 13:21:43.521561 best dqsien dly found for B1: ( 1, 3, 28)
3545 13:21:43.524428 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3546 13:21:43.527904 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3547 13:21:43.527987
3548 13:21:43.531378 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3549 13:21:43.534656 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3550 13:21:43.538095 [Gating] SW calibration Done
3551 13:21:43.538174 ==
3552 13:21:43.541870 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 13:21:43.544743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 13:21:43.544823 ==
3555 13:21:43.547911 RX Vref Scan: 0
3556 13:21:43.547989
3557 13:21:43.548052 RX Vref 0 -> 0, step: 1
3558 13:21:43.548110
3559 13:21:43.551466 RX Delay -40 -> 252, step: 8
3560 13:21:43.554975 iDelay=192, Bit 0, Center 111 (40 ~ 183) 144
3561 13:21:43.561159 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3562 13:21:43.564769 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3563 13:21:43.568247 iDelay=192, Bit 3, Center 115 (48 ~ 183) 136
3564 13:21:43.571446 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3565 13:21:43.574845 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3566 13:21:43.581784 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3567 13:21:43.584803 iDelay=192, Bit 7, Center 111 (48 ~ 175) 128
3568 13:21:43.588227 iDelay=192, Bit 8, Center 99 (24 ~ 175) 152
3569 13:21:43.591361 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3570 13:21:43.594711 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3571 13:21:43.601399 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3572 13:21:43.604939 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3573 13:21:43.608071 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3574 13:21:43.611704 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3575 13:21:43.615003 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3576 13:21:43.615082 ==
3577 13:21:43.618199 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 13:21:43.624804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 13:21:43.624884 ==
3580 13:21:43.624947 DQS Delay:
3581 13:21:43.628220 DQS0 = 0, DQS1 = 0
3582 13:21:43.628298 DQM Delay:
3583 13:21:43.631293 DQM0 = 113, DQM1 = 110
3584 13:21:43.631374 DQ Delay:
3585 13:21:43.634951 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =115
3586 13:21:43.638160 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =111
3587 13:21:43.641536 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3588 13:21:43.644902 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3589 13:21:43.644982
3590 13:21:43.645044
3591 13:21:43.645102 ==
3592 13:21:43.648114 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 13:21:43.651717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 13:21:43.654798 ==
3595 13:21:43.654878
3596 13:21:43.654940
3597 13:21:43.654998 TX Vref Scan disable
3598 13:21:43.657991 == TX Byte 0 ==
3599 13:21:43.661532 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3600 13:21:43.665118 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3601 13:21:43.668145 == TX Byte 1 ==
3602 13:21:43.671554 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3603 13:21:43.674954 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3604 13:21:43.675034 ==
3605 13:21:43.678045 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 13:21:43.684633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 13:21:43.684760 ==
3608 13:21:43.695266 TX Vref=22, minBit 3, minWin=25, winSum=417
3609 13:21:43.698873 TX Vref=24, minBit 0, minWin=26, winSum=425
3610 13:21:43.702221 TX Vref=26, minBit 2, minWin=26, winSum=430
3611 13:21:43.705607 TX Vref=28, minBit 2, minWin=26, winSum=431
3612 13:21:43.708595 TX Vref=30, minBit 2, minWin=26, winSum=434
3613 13:21:43.712051 TX Vref=32, minBit 2, minWin=26, winSum=431
3614 13:21:43.718696 [TxChooseVref] Worse bit 2, Min win 26, Win sum 434, Final Vref 30
3615 13:21:43.718776
3616 13:21:43.722139 Final TX Range 1 Vref 30
3617 13:21:43.722220
3618 13:21:43.722281 ==
3619 13:21:43.725401 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 13:21:43.728568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 13:21:43.728648 ==
3622 13:21:43.728747
3623 13:21:43.732220
3624 13:21:43.732298 TX Vref Scan disable
3625 13:21:43.735384 == TX Byte 0 ==
3626 13:21:43.738682 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3627 13:21:43.742129 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3628 13:21:43.745553 == TX Byte 1 ==
3629 13:21:43.748690 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3630 13:21:43.752154 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3631 13:21:43.752233
3632 13:21:43.755391 [DATLAT]
3633 13:21:43.755470 Freq=1200, CH1 RK1
3634 13:21:43.755534
3635 13:21:43.758714 DATLAT Default: 0xd
3636 13:21:43.758792 0, 0xFFFF, sum = 0
3637 13:21:43.762130 1, 0xFFFF, sum = 0
3638 13:21:43.762210 2, 0xFFFF, sum = 0
3639 13:21:43.765254 3, 0xFFFF, sum = 0
3640 13:21:43.765334 4, 0xFFFF, sum = 0
3641 13:21:43.768582 5, 0xFFFF, sum = 0
3642 13:21:43.768662 6, 0xFFFF, sum = 0
3643 13:21:43.772037 7, 0xFFFF, sum = 0
3644 13:21:43.772121 8, 0xFFFF, sum = 0
3645 13:21:43.775635 9, 0xFFFF, sum = 0
3646 13:21:43.778942 10, 0xFFFF, sum = 0
3647 13:21:43.779022 11, 0xFFFF, sum = 0
3648 13:21:43.782301 12, 0x0, sum = 1
3649 13:21:43.782381 13, 0x0, sum = 2
3650 13:21:43.782444 14, 0x0, sum = 3
3651 13:21:43.785479 15, 0x0, sum = 4
3652 13:21:43.785559 best_step = 13
3653 13:21:43.785622
3654 13:21:43.788494 ==
3655 13:21:43.788573 Dram Type= 6, Freq= 0, CH_1, rank 1
3656 13:21:43.795266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3657 13:21:43.795346 ==
3658 13:21:43.795409 RX Vref Scan: 0
3659 13:21:43.795467
3660 13:21:43.798648 RX Vref 0 -> 0, step: 1
3661 13:21:43.798727
3662 13:21:43.802095 RX Delay -21 -> 252, step: 4
3663 13:21:43.805596 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3664 13:21:43.808615 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3665 13:21:43.815869 iDelay=191, Bit 2, Center 106 (43 ~ 170) 128
3666 13:21:43.819028 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3667 13:21:43.822277 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3668 13:21:43.825604 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3669 13:21:43.828940 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3670 13:21:43.835507 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3671 13:21:43.838860 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3672 13:21:43.841972 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3673 13:21:43.845244 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3674 13:21:43.848580 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3675 13:21:43.855194 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3676 13:21:43.859290 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3677 13:21:43.861980 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3678 13:21:43.865724 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3679 13:21:43.865804 ==
3680 13:21:43.868721 Dram Type= 6, Freq= 0, CH_1, rank 1
3681 13:21:43.875963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3682 13:21:43.876043 ==
3683 13:21:43.876106 DQS Delay:
3684 13:21:43.876165 DQS0 = 0, DQS1 = 0
3685 13:21:43.878869 DQM Delay:
3686 13:21:43.878947 DQM0 = 113, DQM1 = 109
3687 13:21:43.881770 DQ Delay:
3688 13:21:43.885579 DQ0 =112, DQ1 =108, DQ2 =106, DQ3 =112
3689 13:21:43.888825 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3690 13:21:43.891816 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =100
3691 13:21:43.895419 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =116
3692 13:21:43.895498
3693 13:21:43.895560
3694 13:21:43.902036 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3695 13:21:43.905528 CH1 RK1: MR19=303, MR18=F7FE
3696 13:21:43.912565 CH1_RK1: MR19=0x303, MR18=0xF7FE, DQSOSC=410, MR23=63, INC=39, DEC=26
3697 13:21:43.915189 [RxdqsGatingPostProcess] freq 1200
3698 13:21:43.922030 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3699 13:21:43.925474 best DQS0 dly(2T, 0.5T) = (0, 11)
3700 13:21:43.925553 best DQS1 dly(2T, 0.5T) = (0, 11)
3701 13:21:43.928950 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3702 13:21:43.932138 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3703 13:21:43.935429 best DQS0 dly(2T, 0.5T) = (0, 11)
3704 13:21:43.938845 best DQS1 dly(2T, 0.5T) = (0, 11)
3705 13:21:43.942435 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3706 13:21:43.946404 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3707 13:21:43.948696 Pre-setting of DQS Precalculation
3708 13:21:43.955353 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3709 13:21:43.962148 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3710 13:21:43.968997 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3711 13:21:43.969076
3712 13:21:43.969139
3713 13:21:43.972491 [Calibration Summary] 2400 Mbps
3714 13:21:43.972570 CH 0, Rank 0
3715 13:21:43.975655 SW Impedance : PASS
3716 13:21:43.978804 DUTY Scan : NO K
3717 13:21:43.978884 ZQ Calibration : PASS
3718 13:21:43.982217 Jitter Meter : NO K
3719 13:21:43.982297 CBT Training : PASS
3720 13:21:43.985445 Write leveling : PASS
3721 13:21:43.988845 RX DQS gating : PASS
3722 13:21:43.988924 RX DQ/DQS(RDDQC) : PASS
3723 13:21:43.992434 TX DQ/DQS : PASS
3724 13:21:43.995719 RX DATLAT : PASS
3725 13:21:43.995797 RX DQ/DQS(Engine): PASS
3726 13:21:43.999054 TX OE : NO K
3727 13:21:43.999134 All Pass.
3728 13:21:43.999196
3729 13:21:44.002426 CH 0, Rank 1
3730 13:21:44.002505 SW Impedance : PASS
3731 13:21:44.005941 DUTY Scan : NO K
3732 13:21:44.009090 ZQ Calibration : PASS
3733 13:21:44.009169 Jitter Meter : NO K
3734 13:21:44.012826 CBT Training : PASS
3735 13:21:44.012905 Write leveling : PASS
3736 13:21:44.015735 RX DQS gating : PASS
3737 13:21:44.019352 RX DQ/DQS(RDDQC) : PASS
3738 13:21:44.019431 TX DQ/DQS : PASS
3739 13:21:44.022581 RX DATLAT : PASS
3740 13:21:44.026143 RX DQ/DQS(Engine): PASS
3741 13:21:44.026222 TX OE : NO K
3742 13:21:44.029485 All Pass.
3743 13:21:44.029563
3744 13:21:44.029625 CH 1, Rank 0
3745 13:21:44.032942 SW Impedance : PASS
3746 13:21:44.033021 DUTY Scan : NO K
3747 13:21:44.035775 ZQ Calibration : PASS
3748 13:21:44.039420 Jitter Meter : NO K
3749 13:21:44.039499 CBT Training : PASS
3750 13:21:44.042655 Write leveling : PASS
3751 13:21:44.045853 RX DQS gating : PASS
3752 13:21:44.045933 RX DQ/DQS(RDDQC) : PASS
3753 13:21:44.049295 TX DQ/DQS : PASS
3754 13:21:44.049374 RX DATLAT : PASS
3755 13:21:44.052620 RX DQ/DQS(Engine): PASS
3756 13:21:44.055847 TX OE : NO K
3757 13:21:44.055927 All Pass.
3758 13:21:44.055989
3759 13:21:44.056047 CH 1, Rank 1
3760 13:21:44.059372 SW Impedance : PASS
3761 13:21:44.063050 DUTY Scan : NO K
3762 13:21:44.063129 ZQ Calibration : PASS
3763 13:21:44.065798 Jitter Meter : NO K
3764 13:21:44.069331 CBT Training : PASS
3765 13:21:44.069410 Write leveling : PASS
3766 13:21:44.072611 RX DQS gating : PASS
3767 13:21:44.076422 RX DQ/DQS(RDDQC) : PASS
3768 13:21:44.076526 TX DQ/DQS : PASS
3769 13:21:44.079343 RX DATLAT : PASS
3770 13:21:44.082551 RX DQ/DQS(Engine): PASS
3771 13:21:44.082630 TX OE : NO K
3772 13:21:44.082694 All Pass.
3773 13:21:44.086179
3774 13:21:44.086258 DramC Write-DBI off
3775 13:21:44.089367 PER_BANK_REFRESH: Hybrid Mode
3776 13:21:44.089446 TX_TRACKING: ON
3777 13:21:44.099803 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3778 13:21:44.102952 [FAST_K] Save calibration result to emmc
3779 13:21:44.106215 dramc_set_vcore_voltage set vcore to 650000
3780 13:21:44.109344 Read voltage for 600, 5
3781 13:21:44.109428 Vio18 = 0
3782 13:21:44.112826 Vcore = 650000
3783 13:21:44.112916 Vdram = 0
3784 13:21:44.112988 Vddq = 0
3785 13:21:44.113055 Vmddr = 0
3786 13:21:44.119333 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3787 13:21:44.125964 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3788 13:21:44.126083 MEM_TYPE=3, freq_sel=19
3789 13:21:44.129305 sv_algorithm_assistance_LP4_1600
3790 13:21:44.132965 ============ PULL DRAM RESETB DOWN ============
3791 13:21:44.139365 ========== PULL DRAM RESETB DOWN end =========
3792 13:21:44.142821 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3793 13:21:44.146861 ===================================
3794 13:21:44.149516 LPDDR4 DRAM CONFIGURATION
3795 13:21:44.152715 ===================================
3796 13:21:44.152794 EX_ROW_EN[0] = 0x0
3797 13:21:44.156209 EX_ROW_EN[1] = 0x0
3798 13:21:44.156287 LP4Y_EN = 0x0
3799 13:21:44.159727 WORK_FSP = 0x0
3800 13:21:44.159806 WL = 0x2
3801 13:21:44.162742 RL = 0x2
3802 13:21:44.162821 BL = 0x2
3803 13:21:44.166334 RPST = 0x0
3804 13:21:44.166428 RD_PRE = 0x0
3805 13:21:44.169746 WR_PRE = 0x1
3806 13:21:44.169825 WR_PST = 0x0
3807 13:21:44.172791 DBI_WR = 0x0
3808 13:21:44.172870 DBI_RD = 0x0
3809 13:21:44.176101 OTF = 0x1
3810 13:21:44.179507 ===================================
3811 13:21:44.182775 ===================================
3812 13:21:44.182854 ANA top config
3813 13:21:44.186333 ===================================
3814 13:21:44.189308 DLL_ASYNC_EN = 0
3815 13:21:44.193141 ALL_SLAVE_EN = 1
3816 13:21:44.196144 NEW_RANK_MODE = 1
3817 13:21:44.196224 DLL_IDLE_MODE = 1
3818 13:21:44.199527 LP45_APHY_COMB_EN = 1
3819 13:21:44.203079 TX_ODT_DIS = 1
3820 13:21:44.206345 NEW_8X_MODE = 1
3821 13:21:44.210007 ===================================
3822 13:21:44.213548 ===================================
3823 13:21:44.216549 data_rate = 1200
3824 13:21:44.216675 CKR = 1
3825 13:21:44.220059 DQ_P2S_RATIO = 8
3826 13:21:44.223170 ===================================
3827 13:21:44.226901 CA_P2S_RATIO = 8
3828 13:21:44.229771 DQ_CA_OPEN = 0
3829 13:21:44.233040 DQ_SEMI_OPEN = 0
3830 13:21:44.233119 CA_SEMI_OPEN = 0
3831 13:21:44.236644 CA_FULL_RATE = 0
3832 13:21:44.240138 DQ_CKDIV4_EN = 1
3833 13:21:44.243196 CA_CKDIV4_EN = 1
3834 13:21:44.246987 CA_PREDIV_EN = 0
3835 13:21:44.249713 PH8_DLY = 0
3836 13:21:44.249792 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3837 13:21:44.253471 DQ_AAMCK_DIV = 4
3838 13:21:44.256786 CA_AAMCK_DIV = 4
3839 13:21:44.260133 CA_ADMCK_DIV = 4
3840 13:21:44.263358 DQ_TRACK_CA_EN = 0
3841 13:21:44.266655 CA_PICK = 600
3842 13:21:44.269672 CA_MCKIO = 600
3843 13:21:44.269751 MCKIO_SEMI = 0
3844 13:21:44.273691 PLL_FREQ = 2288
3845 13:21:44.276320 DQ_UI_PI_RATIO = 32
3846 13:21:44.279791 CA_UI_PI_RATIO = 0
3847 13:21:44.283091 ===================================
3848 13:21:44.286440 ===================================
3849 13:21:44.289899 memory_type:LPDDR4
3850 13:21:44.289978 GP_NUM : 10
3851 13:21:44.293160 SRAM_EN : 1
3852 13:21:44.293240 MD32_EN : 0
3853 13:21:44.296424 ===================================
3854 13:21:44.299911 [ANA_INIT] >>>>>>>>>>>>>>
3855 13:21:44.303355 <<<<<< [CONFIGURE PHASE]: ANA_TX
3856 13:21:44.306519 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3857 13:21:44.309827 ===================================
3858 13:21:44.313415 data_rate = 1200,PCW = 0X5800
3859 13:21:44.316787 ===================================
3860 13:21:44.320054 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3861 13:21:44.323371 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3862 13:21:44.330130 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3863 13:21:44.333514 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3864 13:21:44.336782 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3865 13:21:44.343396 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3866 13:21:44.343476 [ANA_INIT] flow start
3867 13:21:44.346807 [ANA_INIT] PLL >>>>>>>>
3868 13:21:44.346886 [ANA_INIT] PLL <<<<<<<<
3869 13:21:44.350472 [ANA_INIT] MIDPI >>>>>>>>
3870 13:21:44.354084 [ANA_INIT] MIDPI <<<<<<<<
3871 13:21:44.356796 [ANA_INIT] DLL >>>>>>>>
3872 13:21:44.356874 [ANA_INIT] flow end
3873 13:21:44.360127 ============ LP4 DIFF to SE enter ============
3874 13:21:44.367012 ============ LP4 DIFF to SE exit ============
3875 13:21:44.367092 [ANA_INIT] <<<<<<<<<<<<<
3876 13:21:44.370219 [Flow] Enable top DCM control >>>>>
3877 13:21:44.373504 [Flow] Enable top DCM control <<<<<
3878 13:21:44.377021 Enable DLL master slave shuffle
3879 13:21:44.383963 ==============================================================
3880 13:21:44.384043 Gating Mode config
3881 13:21:44.390791 ==============================================================
3882 13:21:44.393644 Config description:
3883 13:21:44.400093 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3884 13:21:44.407224 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3885 13:21:44.413789 SELPH_MODE 0: By rank 1: By Phase
3886 13:21:44.420297 ==============================================================
3887 13:21:44.420403 GAT_TRACK_EN = 1
3888 13:21:44.423543 RX_GATING_MODE = 2
3889 13:21:44.427013 RX_GATING_TRACK_MODE = 2
3890 13:21:44.430578 SELPH_MODE = 1
3891 13:21:44.433730 PICG_EARLY_EN = 1
3892 13:21:44.436854 VALID_LAT_VALUE = 1
3893 13:21:44.443761 ==============================================================
3894 13:21:44.447075 Enter into Gating configuration >>>>
3895 13:21:44.450306 Exit from Gating configuration <<<<
3896 13:21:44.454021 Enter into DVFS_PRE_config >>>>>
3897 13:21:44.463874 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3898 13:21:44.467366 Exit from DVFS_PRE_config <<<<<
3899 13:21:44.470492 Enter into PICG configuration >>>>
3900 13:21:44.473612 Exit from PICG configuration <<<<
3901 13:21:44.476935 [RX_INPUT] configuration >>>>>
3902 13:21:44.477019 [RX_INPUT] configuration <<<<<
3903 13:21:44.483807 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3904 13:21:44.487193 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3905 13:21:44.494132 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3906 13:21:44.500473 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3907 13:21:44.507351 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3908 13:21:44.514098 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3909 13:21:44.517040 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3910 13:21:44.520874 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3911 13:21:44.523861 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3912 13:21:44.530815 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3913 13:21:44.534158 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3914 13:21:44.537883 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3915 13:21:44.541180 ===================================
3916 13:21:44.544157 LPDDR4 DRAM CONFIGURATION
3917 13:21:44.547689 ===================================
3918 13:21:44.550852 EX_ROW_EN[0] = 0x0
3919 13:21:44.550931 EX_ROW_EN[1] = 0x0
3920 13:21:44.554310 LP4Y_EN = 0x0
3921 13:21:44.554388 WORK_FSP = 0x0
3922 13:21:44.557456 WL = 0x2
3923 13:21:44.557534 RL = 0x2
3924 13:21:44.561189 BL = 0x2
3925 13:21:44.561297 RPST = 0x0
3926 13:21:44.564317 RD_PRE = 0x0
3927 13:21:44.564422 WR_PRE = 0x1
3928 13:21:44.567929 WR_PST = 0x0
3929 13:21:44.568008 DBI_WR = 0x0
3930 13:21:44.570937 DBI_RD = 0x0
3931 13:21:44.571016 OTF = 0x1
3932 13:21:44.573946 ===================================
3933 13:21:44.577960 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3934 13:21:44.584180 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3935 13:21:44.587310 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3936 13:21:44.590967 ===================================
3937 13:21:44.593966 LPDDR4 DRAM CONFIGURATION
3938 13:21:44.597574 ===================================
3939 13:21:44.597665 EX_ROW_EN[0] = 0x10
3940 13:21:44.600655 EX_ROW_EN[1] = 0x0
3941 13:21:44.604384 LP4Y_EN = 0x0
3942 13:21:44.604483 WORK_FSP = 0x0
3943 13:21:44.607726 WL = 0x2
3944 13:21:44.607834 RL = 0x2
3945 13:21:44.611097 BL = 0x2
3946 13:21:44.611214 RPST = 0x0
3947 13:21:44.613985 RD_PRE = 0x0
3948 13:21:44.614103 WR_PRE = 0x1
3949 13:21:44.617437 WR_PST = 0x0
3950 13:21:44.617568 DBI_WR = 0x0
3951 13:21:44.620654 DBI_RD = 0x0
3952 13:21:44.620823 OTF = 0x1
3953 13:21:44.624288 ===================================
3954 13:21:44.630758 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3955 13:21:44.635018 nWR fixed to 30
3956 13:21:44.638337 [ModeRegInit_LP4] CH0 RK0
3957 13:21:44.638416 [ModeRegInit_LP4] CH0 RK1
3958 13:21:44.641433 [ModeRegInit_LP4] CH1 RK0
3959 13:21:44.644908 [ModeRegInit_LP4] CH1 RK1
3960 13:21:44.644987 match AC timing 17
3961 13:21:44.651686 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3962 13:21:44.655054 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3963 13:21:44.658433 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3964 13:21:44.664741 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3965 13:21:44.668216 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3966 13:21:44.668295 ==
3967 13:21:44.671739 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 13:21:44.675291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 13:21:44.675370 ==
3970 13:21:44.681796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3971 13:21:44.688077 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3972 13:21:44.691768 [CA 0] Center 36 (6~67) winsize 62
3973 13:21:44.694763 [CA 1] Center 36 (6~66) winsize 61
3974 13:21:44.698224 [CA 2] Center 34 (4~65) winsize 62
3975 13:21:44.701626 [CA 3] Center 34 (4~65) winsize 62
3976 13:21:44.704736 [CA 4] Center 33 (3~64) winsize 62
3977 13:21:44.708232 [CA 5] Center 33 (3~64) winsize 62
3978 13:21:44.708311
3979 13:21:44.711676 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3980 13:21:44.711755
3981 13:21:44.714824 [CATrainingPosCal] consider 1 rank data
3982 13:21:44.718757 u2DelayCellTimex100 = 270/100 ps
3983 13:21:44.721691 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3984 13:21:44.724943 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3985 13:21:44.728511 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3986 13:21:44.731655 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3987 13:21:44.734673 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3988 13:21:44.737968 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3989 13:21:44.738047
3990 13:21:44.744871 CA PerBit enable=1, Macro0, CA PI delay=33
3991 13:21:44.744950
3992 13:21:44.745012 [CBTSetCACLKResult] CA Dly = 33
3993 13:21:44.748168 CS Dly: 4 (0~35)
3994 13:21:44.748247 ==
3995 13:21:44.751591 Dram Type= 6, Freq= 0, CH_0, rank 1
3996 13:21:44.754962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3997 13:21:44.755067 ==
3998 13:21:44.761761 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3999 13:21:44.768238 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4000 13:21:44.771541 [CA 0] Center 36 (6~66) winsize 61
4001 13:21:44.774820 [CA 1] Center 36 (6~66) winsize 61
4002 13:21:44.778153 [CA 2] Center 34 (4~65) winsize 62
4003 13:21:44.781528 [CA 3] Center 34 (4~65) winsize 62
4004 13:21:44.784954 [CA 4] Center 33 (3~64) winsize 62
4005 13:21:44.788402 [CA 5] Center 33 (3~64) winsize 62
4006 13:21:44.788480
4007 13:21:44.791343 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4008 13:21:44.791422
4009 13:21:44.794967 [CATrainingPosCal] consider 2 rank data
4010 13:21:44.798227 u2DelayCellTimex100 = 270/100 ps
4011 13:21:44.801356 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4012 13:21:44.804617 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4013 13:21:44.807980 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4014 13:21:44.811629 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4015 13:21:44.814770 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4016 13:21:44.818431 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4017 13:21:44.818510
4018 13:21:44.824802 CA PerBit enable=1, Macro0, CA PI delay=33
4019 13:21:44.824881
4020 13:21:44.824942 [CBTSetCACLKResult] CA Dly = 33
4021 13:21:44.828217 CS Dly: 4 (0~36)
4022 13:21:44.828295
4023 13:21:44.831652 ----->DramcWriteLeveling(PI) begin...
4024 13:21:44.831732 ==
4025 13:21:44.834930 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 13:21:44.838298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 13:21:44.838378 ==
4028 13:21:44.841950 Write leveling (Byte 0): 33 => 33
4029 13:21:44.844630 Write leveling (Byte 1): 31 => 31
4030 13:21:44.848111 DramcWriteLeveling(PI) end<-----
4031 13:21:44.848188
4032 13:21:44.848249 ==
4033 13:21:44.851433 Dram Type= 6, Freq= 0, CH_0, rank 0
4034 13:21:44.855179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 13:21:44.858282 ==
4036 13:21:44.858361 [Gating] SW mode calibration
4037 13:21:44.865097 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4038 13:21:44.871723 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4039 13:21:44.875036 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4040 13:21:44.881722 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4041 13:21:44.884847 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4042 13:21:44.888424 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4043 13:21:44.895162 0 9 16 | B1->B0 | 2f2f 2d2d | 1 0 | (1 0) (0 0)
4044 13:21:44.898536 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4045 13:21:44.901801 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 13:21:44.908812 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 13:21:44.912074 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 13:21:44.914871 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 13:21:44.918313 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 13:21:44.925691 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4051 13:21:44.928281 0 10 16 | B1->B0 | 2f2f 3a3a | 0 0 | (0 0) (0 0)
4052 13:21:44.932089 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 13:21:44.938555 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 13:21:44.942303 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 13:21:44.945528 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 13:21:44.951849 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 13:21:44.955105 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 13:21:44.958480 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 13:21:44.965180 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 13:21:44.968343 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 13:21:44.971752 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 13:21:44.978491 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 13:21:44.982554 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 13:21:44.985144 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 13:21:44.988561 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 13:21:44.995371 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 13:21:44.998740 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 13:21:45.001824 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 13:21:45.008526 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 13:21:45.011772 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 13:21:45.015301 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 13:21:45.021993 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 13:21:45.025464 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 13:21:45.028857 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4075 13:21:45.035282 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4076 13:21:45.035361 Total UI for P1: 0, mck2ui 16
4077 13:21:45.041854 best dqsien dly found for B0: ( 0, 13, 12)
4078 13:21:45.045163 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 13:21:45.048592 Total UI for P1: 0, mck2ui 16
4080 13:21:45.052000 best dqsien dly found for B1: ( 0, 13, 16)
4081 13:21:45.055285 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4082 13:21:45.058538 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4083 13:21:45.058616
4084 13:21:45.062340 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4085 13:21:45.065749 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4086 13:21:45.068860 [Gating] SW calibration Done
4087 13:21:45.068939 ==
4088 13:21:45.072038 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 13:21:45.075594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 13:21:45.078748 ==
4091 13:21:45.078826 RX Vref Scan: 0
4092 13:21:45.078888
4093 13:21:45.082097 RX Vref 0 -> 0, step: 1
4094 13:21:45.082176
4095 13:21:45.085885 RX Delay -230 -> 252, step: 16
4096 13:21:45.088658 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4097 13:21:45.092268 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4098 13:21:45.095342 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4099 13:21:45.098817 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4100 13:21:45.105277 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4101 13:21:45.108683 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4102 13:21:45.112100 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4103 13:21:45.115450 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4104 13:21:45.118860 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4105 13:21:45.126144 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4106 13:21:45.129089 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4107 13:21:45.132215 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4108 13:21:45.135594 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4109 13:21:45.142318 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4110 13:21:45.145710 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4111 13:21:45.148899 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4112 13:21:45.148978 ==
4113 13:21:45.152268 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 13:21:45.155622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 13:21:45.155702 ==
4116 13:21:45.159140 DQS Delay:
4117 13:21:45.159219 DQS0 = 0, DQS1 = 0
4118 13:21:45.162585 DQM Delay:
4119 13:21:45.162663 DQM0 = 40, DQM1 = 32
4120 13:21:45.162725 DQ Delay:
4121 13:21:45.166434 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4122 13:21:45.168806 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4123 13:21:45.172844 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4124 13:21:45.175866 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4125 13:21:45.175969
4126 13:21:45.176060
4127 13:21:45.178866 ==
4128 13:21:45.182446 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 13:21:45.185978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 13:21:45.186061 ==
4131 13:21:45.186123
4132 13:21:45.186180
4133 13:21:45.189230 TX Vref Scan disable
4134 13:21:45.189308 == TX Byte 0 ==
4135 13:21:45.195715 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4136 13:21:45.198971 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4137 13:21:45.199062 == TX Byte 1 ==
4138 13:21:45.202744 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4139 13:21:45.208870 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4140 13:21:45.208982 ==
4141 13:21:45.212333 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 13:21:45.215781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 13:21:45.215911 ==
4144 13:21:45.216014
4145 13:21:45.216108
4146 13:21:45.219644 TX Vref Scan disable
4147 13:21:45.222591 == TX Byte 0 ==
4148 13:21:45.226056 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4149 13:21:45.229438 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4150 13:21:45.232486 == TX Byte 1 ==
4151 13:21:45.235826 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4152 13:21:45.239531 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4153 13:21:45.239831
4154 13:21:45.242673 [DATLAT]
4155 13:21:45.242956 Freq=600, CH0 RK0
4156 13:21:45.243182
4157 13:21:45.246098 DATLAT Default: 0x9
4158 13:21:45.246466 0, 0xFFFF, sum = 0
4159 13:21:45.249238 1, 0xFFFF, sum = 0
4160 13:21:45.249666 2, 0xFFFF, sum = 0
4161 13:21:45.253254 3, 0xFFFF, sum = 0
4162 13:21:45.253872 4, 0xFFFF, sum = 0
4163 13:21:45.256109 5, 0xFFFF, sum = 0
4164 13:21:45.256521 6, 0xFFFF, sum = 0
4165 13:21:45.259374 7, 0xFFFF, sum = 0
4166 13:21:45.259783 8, 0x0, sum = 1
4167 13:21:45.263197 9, 0x0, sum = 2
4168 13:21:45.263605 10, 0x0, sum = 3
4169 13:21:45.265829 11, 0x0, sum = 4
4170 13:21:45.266237 best_step = 9
4171 13:21:45.266552
4172 13:21:45.266846 ==
4173 13:21:45.269366 Dram Type= 6, Freq= 0, CH_0, rank 0
4174 13:21:45.272757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 13:21:45.273166 ==
4176 13:21:45.276619 RX Vref Scan: 1
4177 13:21:45.277088
4178 13:21:45.279511 RX Vref 0 -> 0, step: 1
4179 13:21:45.279911
4180 13:21:45.280227 RX Delay -195 -> 252, step: 8
4181 13:21:45.280519
4182 13:21:45.283184 Set Vref, RX VrefLevel [Byte0]: 53
4183 13:21:45.286211 [Byte1]: 53
4184 13:21:45.290833
4185 13:21:45.291234 Final RX Vref Byte 0 = 53 to rank0
4186 13:21:45.294117 Final RX Vref Byte 1 = 53 to rank0
4187 13:21:45.297488 Final RX Vref Byte 0 = 53 to rank1
4188 13:21:45.300426 Final RX Vref Byte 1 = 53 to rank1==
4189 13:21:45.303979 Dram Type= 6, Freq= 0, CH_0, rank 0
4190 13:21:45.310959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 13:21:45.311364 ==
4192 13:21:45.311686 DQS Delay:
4193 13:21:45.314122 DQS0 = 0, DQS1 = 0
4194 13:21:45.314528 DQM Delay:
4195 13:21:45.314847 DQM0 = 42, DQM1 = 33
4196 13:21:45.317369 DQ Delay:
4197 13:21:45.320442 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4198 13:21:45.324097 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4199 13:21:45.327123 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4200 13:21:45.330509 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4201 13:21:45.330932
4202 13:21:45.331258
4203 13:21:45.337393 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d1b, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
4204 13:21:45.340937 CH0 RK0: MR19=808, MR18=3D1B
4205 13:21:45.347503 CH0_RK0: MR19=0x808, MR18=0x3D1B, DQSOSC=398, MR23=63, INC=165, DEC=110
4206 13:21:45.347910
4207 13:21:45.351057 ----->DramcWriteLeveling(PI) begin...
4208 13:21:45.351465 ==
4209 13:21:45.353904 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 13:21:45.357466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 13:21:45.357895 ==
4212 13:21:45.360724 Write leveling (Byte 0): 32 => 32
4213 13:21:45.363891 Write leveling (Byte 1): 31 => 31
4214 13:21:45.367901 DramcWriteLeveling(PI) end<-----
4215 13:21:45.368319
4216 13:21:45.368635 ==
4217 13:21:45.370933 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 13:21:45.374201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 13:21:45.374610 ==
4220 13:21:45.377349 [Gating] SW mode calibration
4221 13:21:45.384494 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4222 13:21:45.390805 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4223 13:21:45.394270 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4224 13:21:45.398139 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4225 13:21:45.403935 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4226 13:21:45.407773 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (0 1)
4227 13:21:45.410875 0 9 16 | B1->B0 | 3030 2424 | 0 0 | (0 0) (0 0)
4228 13:21:45.417551 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 13:21:45.420661 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 13:21:45.424288 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 13:21:45.430709 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 13:21:45.433553 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 13:21:45.437253 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 13:21:45.443668 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
4235 13:21:45.446966 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4236 13:21:45.450491 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 13:21:45.457129 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 13:21:45.460467 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 13:21:45.463556 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 13:21:45.467132 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 13:21:45.473547 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4242 13:21:45.476806 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4243 13:21:45.480475 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4244 13:21:45.486752 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 13:21:45.490197 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 13:21:45.493880 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 13:21:45.500071 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 13:21:45.504023 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 13:21:45.506929 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 13:21:45.513744 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 13:21:45.517031 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 13:21:45.520240 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 13:21:45.526888 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 13:21:45.530328 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 13:21:45.533831 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 13:21:45.540470 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 13:21:45.543664 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 13:21:45.547049 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4259 13:21:45.550264 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4260 13:21:45.553716 Total UI for P1: 0, mck2ui 16
4261 13:21:45.557307 best dqsien dly found for B0: ( 0, 13, 12)
4262 13:21:45.563844 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 13:21:45.567464 Total UI for P1: 0, mck2ui 16
4264 13:21:45.570549 best dqsien dly found for B1: ( 0, 13, 16)
4265 13:21:45.573891 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4266 13:21:45.577024 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4267 13:21:45.577103
4268 13:21:45.580244 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4269 13:21:45.583629 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4270 13:21:45.587043 [Gating] SW calibration Done
4271 13:21:45.587121 ==
4272 13:21:45.590736 Dram Type= 6, Freq= 0, CH_0, rank 1
4273 13:21:45.593901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4274 13:21:45.594006 ==
4275 13:21:45.596943 RX Vref Scan: 0
4276 13:21:45.597021
4277 13:21:45.600098 RX Vref 0 -> 0, step: 1
4278 13:21:45.600175
4279 13:21:45.600237 RX Delay -230 -> 252, step: 16
4280 13:21:45.607248 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4281 13:21:45.610227 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4282 13:21:45.614180 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4283 13:21:45.616838 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4284 13:21:45.623490 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4285 13:21:45.627253 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4286 13:21:45.631085 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4287 13:21:45.633770 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4288 13:21:45.637368 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4289 13:21:45.643708 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4290 13:21:45.647487 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4291 13:21:45.650336 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4292 13:21:45.653895 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4293 13:21:45.660452 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4294 13:21:45.663963 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4295 13:21:45.667367 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4296 13:21:45.667446 ==
4297 13:21:45.670513 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 13:21:45.674492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 13:21:45.674571 ==
4300 13:21:45.677283 DQS Delay:
4301 13:21:45.677360 DQS0 = 0, DQS1 = 0
4302 13:21:45.677422 DQM Delay:
4303 13:21:45.680514 DQM0 = 41, DQM1 = 32
4304 13:21:45.680617 DQ Delay:
4305 13:21:45.684151 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4306 13:21:45.687130 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4307 13:21:45.690603 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4308 13:21:45.694181 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4309 13:21:45.694284
4310 13:21:45.694373
4311 13:21:45.694459 ==
4312 13:21:45.697388 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 13:21:45.704446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 13:21:45.704525 ==
4315 13:21:45.704588
4316 13:21:45.704645
4317 13:21:45.704742 TX Vref Scan disable
4318 13:21:45.707573 == TX Byte 0 ==
4319 13:21:45.711164 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4320 13:21:45.714288 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4321 13:21:45.717836 == TX Byte 1 ==
4322 13:21:45.721194 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4323 13:21:45.724621 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4324 13:21:45.727754 ==
4325 13:21:45.731691 Dram Type= 6, Freq= 0, CH_0, rank 1
4326 13:21:45.734678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 13:21:45.734758 ==
4328 13:21:45.734820
4329 13:21:45.734877
4330 13:21:45.738060 TX Vref Scan disable
4331 13:21:45.738139 == TX Byte 0 ==
4332 13:21:45.744491 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4333 13:21:45.747940 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4334 13:21:45.748019 == TX Byte 1 ==
4335 13:21:45.754644 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4336 13:21:45.757687 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4337 13:21:45.757791
4338 13:21:45.757880 [DATLAT]
4339 13:21:45.761214 Freq=600, CH0 RK1
4340 13:21:45.761296
4341 13:21:45.761358 DATLAT Default: 0x9
4342 13:21:45.764820 0, 0xFFFF, sum = 0
4343 13:21:45.764899 1, 0xFFFF, sum = 0
4344 13:21:45.767874 2, 0xFFFF, sum = 0
4345 13:21:45.767974 3, 0xFFFF, sum = 0
4346 13:21:45.771231 4, 0xFFFF, sum = 0
4347 13:21:45.771311 5, 0xFFFF, sum = 0
4348 13:21:45.775002 6, 0xFFFF, sum = 0
4349 13:21:45.775082 7, 0xFFFF, sum = 0
4350 13:21:45.777952 8, 0x0, sum = 1
4351 13:21:45.778034 9, 0x0, sum = 2
4352 13:21:45.781172 10, 0x0, sum = 3
4353 13:21:45.781251 11, 0x0, sum = 4
4354 13:21:45.784640 best_step = 9
4355 13:21:45.784758
4356 13:21:45.784819 ==
4357 13:21:45.787997 Dram Type= 6, Freq= 0, CH_0, rank 1
4358 13:21:45.791424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4359 13:21:45.791502 ==
4360 13:21:45.794611 RX Vref Scan: 0
4361 13:21:45.794688
4362 13:21:45.794749 RX Vref 0 -> 0, step: 1
4363 13:21:45.794806
4364 13:21:45.797893 RX Delay -195 -> 252, step: 8
4365 13:21:45.805042 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4366 13:21:45.808463 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4367 13:21:45.811555 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4368 13:21:45.814796 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4369 13:21:45.821828 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4370 13:21:45.824919 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4371 13:21:45.828525 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4372 13:21:45.831511 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4373 13:21:45.835391 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4374 13:21:45.842205 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4375 13:21:45.845185 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4376 13:21:45.848484 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4377 13:21:45.851690 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4378 13:21:45.858318 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4379 13:21:45.861630 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4380 13:21:45.865077 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4381 13:21:45.865155 ==
4382 13:21:45.868593 Dram Type= 6, Freq= 0, CH_0, rank 1
4383 13:21:45.871847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4384 13:21:45.871925 ==
4385 13:21:45.874993 DQS Delay:
4386 13:21:45.875071 DQS0 = 0, DQS1 = 0
4387 13:21:45.878351 DQM Delay:
4388 13:21:45.878428 DQM0 = 39, DQM1 = 33
4389 13:21:45.878489 DQ Delay:
4390 13:21:45.882412 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4391 13:21:45.885218 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4392 13:21:45.888207 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4393 13:21:45.891599 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4394 13:21:45.891676
4395 13:21:45.891737
4396 13:21:45.901843 [DQSOSCAuto] RK1, (LSB)MR18= 0x5133, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4397 13:21:45.904815 CH0 RK1: MR19=808, MR18=5133
4398 13:21:45.908477 CH0_RK1: MR19=0x808, MR18=0x5133, DQSOSC=394, MR23=63, INC=168, DEC=112
4399 13:21:45.911597 [RxdqsGatingPostProcess] freq 600
4400 13:21:45.918325 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4401 13:21:45.921832 Pre-setting of DQS Precalculation
4402 13:21:45.925417 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4403 13:21:45.925496 ==
4404 13:21:45.928815 Dram Type= 6, Freq= 0, CH_1, rank 0
4405 13:21:45.935253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 13:21:45.935333 ==
4407 13:21:45.938555 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4408 13:21:45.945000 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4409 13:21:45.948540 [CA 0] Center 35 (5~65) winsize 61
4410 13:21:45.951740 [CA 1] Center 35 (5~66) winsize 62
4411 13:21:45.955480 [CA 2] Center 33 (3~64) winsize 62
4412 13:21:45.958639 [CA 3] Center 33 (3~64) winsize 62
4413 13:21:45.962032 [CA 4] Center 34 (3~65) winsize 63
4414 13:21:45.965876 [CA 5] Center 33 (3~64) winsize 62
4415 13:21:45.965954
4416 13:21:45.968875 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4417 13:21:45.968955
4418 13:21:45.972371 [CATrainingPosCal] consider 1 rank data
4419 13:21:45.975556 u2DelayCellTimex100 = 270/100 ps
4420 13:21:45.978831 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4421 13:21:45.982144 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4422 13:21:45.985905 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4423 13:21:45.992221 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4424 13:21:45.995234 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4425 13:21:45.998685 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4426 13:21:45.998763
4427 13:21:46.002198 CA PerBit enable=1, Macro0, CA PI delay=33
4428 13:21:46.002276
4429 13:21:46.005567 [CBTSetCACLKResult] CA Dly = 33
4430 13:21:46.005645 CS Dly: 4 (0~35)
4431 13:21:46.005712 ==
4432 13:21:46.009037 Dram Type= 6, Freq= 0, CH_1, rank 1
4433 13:21:46.015564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4434 13:21:46.015643 ==
4435 13:21:46.018887 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4436 13:21:46.025479 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4437 13:21:46.028955 [CA 0] Center 35 (5~66) winsize 62
4438 13:21:46.032601 [CA 1] Center 36 (6~66) winsize 61
4439 13:21:46.036034 [CA 2] Center 34 (4~65) winsize 62
4440 13:21:46.039699 [CA 3] Center 34 (3~65) winsize 63
4441 13:21:46.042142 [CA 4] Center 34 (4~65) winsize 62
4442 13:21:46.045389 [CA 5] Center 33 (3~64) winsize 62
4443 13:21:46.045467
4444 13:21:46.048590 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4445 13:21:46.048728
4446 13:21:46.052289 [CATrainingPosCal] consider 2 rank data
4447 13:21:46.056014 u2DelayCellTimex100 = 270/100 ps
4448 13:21:46.059237 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4449 13:21:46.062309 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4450 13:21:46.065477 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4451 13:21:46.072229 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4452 13:21:46.075315 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4453 13:21:46.078778 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4454 13:21:46.078882
4455 13:21:46.082282 CA PerBit enable=1, Macro0, CA PI delay=33
4456 13:21:46.082361
4457 13:21:46.085352 [CBTSetCACLKResult] CA Dly = 33
4458 13:21:46.085431 CS Dly: 4 (0~36)
4459 13:21:46.085494
4460 13:21:46.088884 ----->DramcWriteLeveling(PI) begin...
4461 13:21:46.088992 ==
4462 13:21:46.092190 Dram Type= 6, Freq= 0, CH_1, rank 0
4463 13:21:46.098831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4464 13:21:46.098912 ==
4465 13:21:46.102177 Write leveling (Byte 0): 28 => 28
4466 13:21:46.105641 Write leveling (Byte 1): 31 => 31
4467 13:21:46.105721 DramcWriteLeveling(PI) end<-----
4468 13:21:46.105783
4469 13:21:46.108955 ==
4470 13:21:46.112673 Dram Type= 6, Freq= 0, CH_1, rank 0
4471 13:21:46.115642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 13:21:46.115721 ==
4473 13:21:46.118899 [Gating] SW mode calibration
4474 13:21:46.125949 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4475 13:21:46.129289 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4476 13:21:46.135577 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4477 13:21:46.138958 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4478 13:21:46.142742 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4479 13:21:46.149004 0 9 12 | B1->B0 | 3535 3232 | 0 1 | (0 0) (1 1)
4480 13:21:46.152311 0 9 16 | B1->B0 | 2b2b 2a2a | 0 0 | (0 0) (0 0)
4481 13:21:46.155942 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 13:21:46.162528 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 13:21:46.166034 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 13:21:46.169754 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4485 13:21:46.172439 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 13:21:46.178954 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4487 13:21:46.182462 0 10 12 | B1->B0 | 2929 2c2c | 0 0 | (1 1) (0 0)
4488 13:21:46.185688 0 10 16 | B1->B0 | 4242 4444 | 0 0 | (0 0) (0 0)
4489 13:21:46.193023 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 13:21:46.196009 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 13:21:46.199160 0 10 28 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
4492 13:21:46.205781 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 13:21:46.209085 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 13:21:46.213308 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 13:21:46.219212 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4496 13:21:46.222525 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 13:21:46.226086 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 13:21:46.232556 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 13:21:46.235851 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 13:21:46.239324 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 13:21:46.242786 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 13:21:46.249517 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 13:21:46.252515 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 13:21:46.255878 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 13:21:46.262428 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 13:21:46.265759 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 13:21:46.269662 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 13:21:46.276031 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 13:21:46.279555 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 13:21:46.282596 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 13:21:46.289417 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 13:21:46.292841 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4513 13:21:46.295874 Total UI for P1: 0, mck2ui 16
4514 13:21:46.299370 best dqsien dly found for B1: ( 0, 13, 14)
4515 13:21:46.302535 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4516 13:21:46.305698 Total UI for P1: 0, mck2ui 16
4517 13:21:46.309369 best dqsien dly found for B0: ( 0, 13, 16)
4518 13:21:46.313137 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4519 13:21:46.315902 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4520 13:21:46.315992
4521 13:21:46.319351 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4522 13:21:46.326225 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4523 13:21:46.326362 [Gating] SW calibration Done
4524 13:21:46.326463 ==
4525 13:21:46.329495 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 13:21:46.336282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 13:21:46.336365 ==
4528 13:21:46.336428 RX Vref Scan: 0
4529 13:21:46.336487
4530 13:21:46.339698 RX Vref 0 -> 0, step: 1
4531 13:21:46.339778
4532 13:21:46.343215 RX Delay -230 -> 252, step: 16
4533 13:21:46.346205 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4534 13:21:46.349468 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4535 13:21:46.352967 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4536 13:21:46.359578 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4537 13:21:46.362921 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4538 13:21:46.366069 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4539 13:21:46.369582 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4540 13:21:46.376283 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4541 13:21:46.379493 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4542 13:21:46.383221 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4543 13:21:46.386115 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4544 13:21:46.389943 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4545 13:21:46.396526 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4546 13:21:46.399496 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4547 13:21:46.402852 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4548 13:21:46.406472 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4549 13:21:46.409536 ==
4550 13:21:46.409639 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 13:21:46.416384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 13:21:46.416464 ==
4553 13:21:46.416545 DQS Delay:
4554 13:21:46.419525 DQS0 = 0, DQS1 = 0
4555 13:21:46.419644 DQM Delay:
4556 13:21:46.423177 DQM0 = 45, DQM1 = 35
4557 13:21:46.423257 DQ Delay:
4558 13:21:46.426182 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4559 13:21:46.429533 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4560 13:21:46.433108 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4561 13:21:46.436430 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4562 13:21:46.436525
4563 13:21:46.436589
4564 13:21:46.436648 ==
4565 13:21:46.439913 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 13:21:46.443196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 13:21:46.443277 ==
4568 13:21:46.443358
4569 13:21:46.443461
4570 13:21:46.446664 TX Vref Scan disable
4571 13:21:46.449966 == TX Byte 0 ==
4572 13:21:46.452759 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4573 13:21:46.456298 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4574 13:21:46.456379 == TX Byte 1 ==
4575 13:21:46.463281 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4576 13:21:46.466590 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4577 13:21:46.466698 ==
4578 13:21:46.470186 Dram Type= 6, Freq= 0, CH_1, rank 0
4579 13:21:46.473338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 13:21:46.473489 ==
4581 13:21:46.473584
4582 13:21:46.476228
4583 13:21:46.476308 TX Vref Scan disable
4584 13:21:46.479680 == TX Byte 0 ==
4585 13:21:46.484000 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4586 13:21:46.486746 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4587 13:21:46.489858 == TX Byte 1 ==
4588 13:21:46.493575 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4589 13:21:46.496709 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4590 13:21:46.500268
4591 13:21:46.500352 [DATLAT]
4592 13:21:46.500418 Freq=600, CH1 RK0
4593 13:21:46.500479
4594 13:21:46.503520 DATLAT Default: 0x9
4595 13:21:46.503602 0, 0xFFFF, sum = 0
4596 13:21:46.507048 1, 0xFFFF, sum = 0
4597 13:21:46.507132 2, 0xFFFF, sum = 0
4598 13:21:46.509907 3, 0xFFFF, sum = 0
4599 13:21:46.509991 4, 0xFFFF, sum = 0
4600 13:21:46.513567 5, 0xFFFF, sum = 0
4601 13:21:46.513648 6, 0xFFFF, sum = 0
4602 13:21:46.516993 7, 0xFFFF, sum = 0
4603 13:21:46.517092 8, 0x0, sum = 1
4604 13:21:46.520245 9, 0x0, sum = 2
4605 13:21:46.520326 10, 0x0, sum = 3
4606 13:21:46.523472 11, 0x0, sum = 4
4607 13:21:46.523598 best_step = 9
4608 13:21:46.523663
4609 13:21:46.523721 ==
4610 13:21:46.527099 Dram Type= 6, Freq= 0, CH_1, rank 0
4611 13:21:46.533472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 13:21:46.533554 ==
4613 13:21:46.533618 RX Vref Scan: 1
4614 13:21:46.533678
4615 13:21:46.537272 RX Vref 0 -> 0, step: 1
4616 13:21:46.537352
4617 13:21:46.540677 RX Delay -195 -> 252, step: 8
4618 13:21:46.540773
4619 13:21:46.543719 Set Vref, RX VrefLevel [Byte0]: 60
4620 13:21:46.546766 [Byte1]: 51
4621 13:21:46.546846
4622 13:21:46.550246 Final RX Vref Byte 0 = 60 to rank0
4623 13:21:46.553637 Final RX Vref Byte 1 = 51 to rank0
4624 13:21:46.556824 Final RX Vref Byte 0 = 60 to rank1
4625 13:21:46.559925 Final RX Vref Byte 1 = 51 to rank1==
4626 13:21:46.563785 Dram Type= 6, Freq= 0, CH_1, rank 0
4627 13:21:46.567157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 13:21:46.567238 ==
4629 13:21:46.567302 DQS Delay:
4630 13:21:46.570248 DQS0 = 0, DQS1 = 0
4631 13:21:46.570328 DQM Delay:
4632 13:21:46.573721 DQM0 = 40, DQM1 = 32
4633 13:21:46.573801 DQ Delay:
4634 13:21:46.576914 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4635 13:21:46.580538 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4636 13:21:46.583456 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4637 13:21:46.587000 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4638 13:21:46.587078
4639 13:21:46.587140
4640 13:21:46.596742 [DQSOSCAuto] RK0, (LSB)MR18= 0x490f, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4641 13:21:46.596844 CH1 RK0: MR19=808, MR18=490F
4642 13:21:46.603609 CH1_RK0: MR19=0x808, MR18=0x490F, DQSOSC=396, MR23=63, INC=167, DEC=111
4643 13:21:46.603692
4644 13:21:46.606943 ----->DramcWriteLeveling(PI) begin...
4645 13:21:46.607024 ==
4646 13:21:46.610008 Dram Type= 6, Freq= 0, CH_1, rank 1
4647 13:21:46.617018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 13:21:46.617099 ==
4649 13:21:46.620095 Write leveling (Byte 0): 31 => 31
4650 13:21:46.623305 Write leveling (Byte 1): 32 => 32
4651 13:21:46.623387 DramcWriteLeveling(PI) end<-----
4652 13:21:46.623449
4653 13:21:46.626652 ==
4654 13:21:46.630193 Dram Type= 6, Freq= 0, CH_1, rank 1
4655 13:21:46.633261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4656 13:21:46.633341 ==
4657 13:21:46.637263 [Gating] SW mode calibration
4658 13:21:46.644197 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4659 13:21:46.646880 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4660 13:21:46.653398 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4661 13:21:46.656769 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4662 13:21:46.660324 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4663 13:21:46.666776 0 9 12 | B1->B0 | 3131 2929 | 0 0 | (0 0) (1 0)
4664 13:21:46.670088 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4665 13:21:46.673614 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 13:21:46.680860 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 13:21:46.684017 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4668 13:21:46.686777 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 13:21:46.690518 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 13:21:46.696836 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4671 13:21:46.699965 0 10 12 | B1->B0 | 3434 4242 | 0 0 | (0 0) (1 1)
4672 13:21:46.703272 0 10 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
4673 13:21:46.710240 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 13:21:46.713470 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 13:21:46.716937 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 13:21:46.723470 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 13:21:46.726931 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 13:21:46.730082 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4679 13:21:46.736986 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4680 13:21:46.740477 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 13:21:46.743536 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 13:21:46.750641 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 13:21:46.753795 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 13:21:46.756992 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 13:21:46.763819 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 13:21:46.766959 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 13:21:46.770357 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 13:21:46.773849 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 13:21:46.780574 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 13:21:46.783747 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 13:21:46.787096 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 13:21:46.793863 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 13:21:46.796853 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 13:21:46.800670 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 13:21:46.807313 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4696 13:21:46.810512 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 13:21:46.813754 Total UI for P1: 0, mck2ui 16
4698 13:21:46.817662 best dqsien dly found for B0: ( 0, 13, 12)
4699 13:21:46.820620 Total UI for P1: 0, mck2ui 16
4700 13:21:46.823802 best dqsien dly found for B1: ( 0, 13, 14)
4701 13:21:46.827017 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4702 13:21:46.830420 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4703 13:21:46.830518
4704 13:21:46.833800 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4705 13:21:46.837037 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4706 13:21:46.841020 [Gating] SW calibration Done
4707 13:21:46.841086 ==
4708 13:21:46.844128 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 13:21:46.847389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 13:21:46.850496 ==
4711 13:21:46.850568 RX Vref Scan: 0
4712 13:21:46.850628
4713 13:21:46.853838 RX Vref 0 -> 0, step: 1
4714 13:21:46.853903
4715 13:21:46.857489 RX Delay -230 -> 252, step: 16
4716 13:21:46.860846 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4717 13:21:46.863973 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4718 13:21:46.867455 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4719 13:21:46.870946 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4720 13:21:46.877227 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4721 13:21:46.880867 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4722 13:21:46.884320 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4723 13:21:46.887606 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4724 13:21:46.890660 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4725 13:21:46.897536 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4726 13:21:46.901012 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4727 13:21:46.904127 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4728 13:21:46.907573 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4729 13:21:46.914023 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4730 13:21:46.918060 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4731 13:21:46.920800 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4732 13:21:46.920873 ==
4733 13:21:46.924528 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 13:21:46.927370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 13:21:46.927466 ==
4736 13:21:46.930730 DQS Delay:
4737 13:21:46.930829 DQS0 = 0, DQS1 = 0
4738 13:21:46.934249 DQM Delay:
4739 13:21:46.934348 DQM0 = 41, DQM1 = 35
4740 13:21:46.934436 DQ Delay:
4741 13:21:46.937410 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4742 13:21:46.941053 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4743 13:21:46.944111 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4744 13:21:46.947956 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4745 13:21:46.948036
4746 13:21:46.948097
4747 13:21:46.950768 ==
4748 13:21:46.954312 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 13:21:46.957663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 13:21:46.957744 ==
4751 13:21:46.957806
4752 13:21:46.957864
4753 13:21:46.960998 TX Vref Scan disable
4754 13:21:46.961077 == TX Byte 0 ==
4755 13:21:46.964053 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4756 13:21:46.971437 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4757 13:21:46.971517 == TX Byte 1 ==
4758 13:21:46.974563 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4759 13:21:46.981010 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4760 13:21:46.981089 ==
4761 13:21:46.984234 Dram Type= 6, Freq= 0, CH_1, rank 1
4762 13:21:46.987559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4763 13:21:46.987666 ==
4764 13:21:46.987758
4765 13:21:46.987819
4766 13:21:46.990995 TX Vref Scan disable
4767 13:21:46.994395 == TX Byte 0 ==
4768 13:21:46.997789 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4769 13:21:47.000855 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4770 13:21:47.004677 == TX Byte 1 ==
4771 13:21:47.007602 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4772 13:21:47.011024 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4773 13:21:47.011104
4774 13:21:47.011166 [DATLAT]
4775 13:21:47.014563 Freq=600, CH1 RK1
4776 13:21:47.014642
4777 13:21:47.017699 DATLAT Default: 0x9
4778 13:21:47.017778 0, 0xFFFF, sum = 0
4779 13:21:47.021552 1, 0xFFFF, sum = 0
4780 13:21:47.021658 2, 0xFFFF, sum = 0
4781 13:21:47.024859 3, 0xFFFF, sum = 0
4782 13:21:47.024939 4, 0xFFFF, sum = 0
4783 13:21:47.027819 5, 0xFFFF, sum = 0
4784 13:21:47.027899 6, 0xFFFF, sum = 0
4785 13:21:47.031130 7, 0xFFFF, sum = 0
4786 13:21:47.031210 8, 0x0, sum = 1
4787 13:21:47.034568 9, 0x0, sum = 2
4788 13:21:47.034648 10, 0x0, sum = 3
4789 13:21:47.034713 11, 0x0, sum = 4
4790 13:21:47.037689 best_step = 9
4791 13:21:47.037768
4792 13:21:47.037830 ==
4793 13:21:47.041003 Dram Type= 6, Freq= 0, CH_1, rank 1
4794 13:21:47.044509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4795 13:21:47.044588 ==
4796 13:21:47.047763 RX Vref Scan: 0
4797 13:21:47.047843
4798 13:21:47.047909 RX Vref 0 -> 0, step: 1
4799 13:21:47.051101
4800 13:21:47.051182 RX Delay -195 -> 252, step: 8
4801 13:21:47.058837 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4802 13:21:47.061984 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4803 13:21:47.065302 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4804 13:21:47.068704 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4805 13:21:47.075559 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4806 13:21:47.078668 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4807 13:21:47.082008 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4808 13:21:47.085736 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4809 13:21:47.089328 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4810 13:21:47.095925 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4811 13:21:47.099061 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4812 13:21:47.102750 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4813 13:21:47.105473 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4814 13:21:47.112320 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4815 13:21:47.116236 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4816 13:21:47.119196 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4817 13:21:47.119294 ==
4818 13:21:47.122257 Dram Type= 6, Freq= 0, CH_1, rank 1
4819 13:21:47.125527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4820 13:21:47.125598 ==
4821 13:21:47.128949 DQS Delay:
4822 13:21:47.129018 DQS0 = 0, DQS1 = 0
4823 13:21:47.132856 DQM Delay:
4824 13:21:47.132931 DQM0 = 39, DQM1 = 33
4825 13:21:47.132992 DQ Delay:
4826 13:21:47.135409 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4827 13:21:47.138957 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4828 13:21:47.142670 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4829 13:21:47.145678 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4830 13:21:47.145751
4831 13:21:47.145813
4832 13:21:47.156323 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c4b, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
4833 13:21:47.159189 CH1 RK1: MR19=808, MR18=3C4B
4834 13:21:47.162168 CH1_RK1: MR19=0x808, MR18=0x3C4B, DQSOSC=395, MR23=63, INC=168, DEC=112
4835 13:21:47.165685 [RxdqsGatingPostProcess] freq 600
4836 13:21:47.172503 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4837 13:21:47.175595 Pre-setting of DQS Precalculation
4838 13:21:47.179173 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4839 13:21:47.185802 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4840 13:21:47.195660 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4841 13:21:47.195738
4842 13:21:47.195806
4843 13:21:47.198977 [Calibration Summary] 1200 Mbps
4844 13:21:47.199079 CH 0, Rank 0
4845 13:21:47.202789 SW Impedance : PASS
4846 13:21:47.202885 DUTY Scan : NO K
4847 13:21:47.205628 ZQ Calibration : PASS
4848 13:21:47.209385 Jitter Meter : NO K
4849 13:21:47.209460 CBT Training : PASS
4850 13:21:47.212956 Write leveling : PASS
4851 13:21:47.213026 RX DQS gating : PASS
4852 13:21:47.216183 RX DQ/DQS(RDDQC) : PASS
4853 13:21:47.219354 TX DQ/DQS : PASS
4854 13:21:47.219452 RX DATLAT : PASS
4855 13:21:47.222810 RX DQ/DQS(Engine): PASS
4856 13:21:47.226049 TX OE : NO K
4857 13:21:47.226118 All Pass.
4858 13:21:47.226177
4859 13:21:47.226234 CH 0, Rank 1
4860 13:21:47.229058 SW Impedance : PASS
4861 13:21:47.232428 DUTY Scan : NO K
4862 13:21:47.232531 ZQ Calibration : PASS
4863 13:21:47.235853 Jitter Meter : NO K
4864 13:21:47.239443 CBT Training : PASS
4865 13:21:47.239512 Write leveling : PASS
4866 13:21:47.242333 RX DQS gating : PASS
4867 13:21:47.246082 RX DQ/DQS(RDDQC) : PASS
4868 13:21:47.246151 TX DQ/DQS : PASS
4869 13:21:47.249475 RX DATLAT : PASS
4870 13:21:47.252445 RX DQ/DQS(Engine): PASS
4871 13:21:47.252547 TX OE : NO K
4872 13:21:47.252634 All Pass.
4873 13:21:47.252739
4874 13:21:47.256000 CH 1, Rank 0
4875 13:21:47.256091 SW Impedance : PASS
4876 13:21:47.259300 DUTY Scan : NO K
4877 13:21:47.262503 ZQ Calibration : PASS
4878 13:21:47.262595 Jitter Meter : NO K
4879 13:21:47.265882 CBT Training : PASS
4880 13:21:47.268940 Write leveling : PASS
4881 13:21:47.269011 RX DQS gating : PASS
4882 13:21:47.272444 RX DQ/DQS(RDDQC) : PASS
4883 13:21:47.275852 TX DQ/DQS : PASS
4884 13:21:47.275928 RX DATLAT : PASS
4885 13:21:47.279259 RX DQ/DQS(Engine): PASS
4886 13:21:47.282629 TX OE : NO K
4887 13:21:47.282726 All Pass.
4888 13:21:47.282813
4889 13:21:47.282901 CH 1, Rank 1
4890 13:21:47.285957 SW Impedance : PASS
4891 13:21:47.288908 DUTY Scan : NO K
4892 13:21:47.288981 ZQ Calibration : PASS
4893 13:21:47.292399 Jitter Meter : NO K
4894 13:21:47.295827 CBT Training : PASS
4895 13:21:47.295897 Write leveling : PASS
4896 13:21:47.299379 RX DQS gating : PASS
4897 13:21:47.299453 RX DQ/DQS(RDDQC) : PASS
4898 13:21:47.302243 TX DQ/DQS : PASS
4899 13:21:47.305729 RX DATLAT : PASS
4900 13:21:47.305798 RX DQ/DQS(Engine): PASS
4901 13:21:47.309073 TX OE : NO K
4902 13:21:47.309146 All Pass.
4903 13:21:47.309206
4904 13:21:47.312849 DramC Write-DBI off
4905 13:21:47.315882 PER_BANK_REFRESH: Hybrid Mode
4906 13:21:47.315977 TX_TRACKING: ON
4907 13:21:47.326137 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4908 13:21:47.328926 [FAST_K] Save calibration result to emmc
4909 13:21:47.332570 dramc_set_vcore_voltage set vcore to 662500
4910 13:21:47.335887 Read voltage for 933, 3
4911 13:21:47.335958 Vio18 = 0
4912 13:21:47.336018 Vcore = 662500
4913 13:21:47.339121 Vdram = 0
4914 13:21:47.339190 Vddq = 0
4915 13:21:47.339248 Vmddr = 0
4916 13:21:47.345797 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4917 13:21:47.348829 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4918 13:21:47.352560 MEM_TYPE=3, freq_sel=17
4919 13:21:47.356314 sv_algorithm_assistance_LP4_1600
4920 13:21:47.359107 ============ PULL DRAM RESETB DOWN ============
4921 13:21:47.362265 ========== PULL DRAM RESETB DOWN end =========
4922 13:21:47.369099 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4923 13:21:47.372599 ===================================
4924 13:21:47.372733 LPDDR4 DRAM CONFIGURATION
4925 13:21:47.375975 ===================================
4926 13:21:47.378989 EX_ROW_EN[0] = 0x0
4927 13:21:47.382579 EX_ROW_EN[1] = 0x0
4928 13:21:47.382676 LP4Y_EN = 0x0
4929 13:21:47.385954 WORK_FSP = 0x0
4930 13:21:47.386050 WL = 0x3
4931 13:21:47.389431 RL = 0x3
4932 13:21:47.389504 BL = 0x2
4933 13:21:47.392569 RPST = 0x0
4934 13:21:47.392663 RD_PRE = 0x0
4935 13:21:47.396097 WR_PRE = 0x1
4936 13:21:47.396164 WR_PST = 0x0
4937 13:21:47.399603 DBI_WR = 0x0
4938 13:21:47.399673 DBI_RD = 0x0
4939 13:21:47.402797 OTF = 0x1
4940 13:21:47.406180 ===================================
4941 13:21:47.409579 ===================================
4942 13:21:47.409726 ANA top config
4943 13:21:47.412941 ===================================
4944 13:21:47.416013 DLL_ASYNC_EN = 0
4945 13:21:47.419453 ALL_SLAVE_EN = 1
4946 13:21:47.422960 NEW_RANK_MODE = 1
4947 13:21:47.423063 DLL_IDLE_MODE = 1
4948 13:21:47.425749 LP45_APHY_COMB_EN = 1
4949 13:21:47.429321 TX_ODT_DIS = 1
4950 13:21:47.432507 NEW_8X_MODE = 1
4951 13:21:47.436291 ===================================
4952 13:21:47.439306 ===================================
4953 13:21:47.439404 data_rate = 1866
4954 13:21:47.442487 CKR = 1
4955 13:21:47.445781 DQ_P2S_RATIO = 8
4956 13:21:47.449438 ===================================
4957 13:21:47.452702 CA_P2S_RATIO = 8
4958 13:21:47.455851 DQ_CA_OPEN = 0
4959 13:21:47.459379 DQ_SEMI_OPEN = 0
4960 13:21:47.459476 CA_SEMI_OPEN = 0
4961 13:21:47.462651 CA_FULL_RATE = 0
4962 13:21:47.465741 DQ_CKDIV4_EN = 1
4963 13:21:47.469213 CA_CKDIV4_EN = 1
4964 13:21:47.472652 CA_PREDIV_EN = 0
4965 13:21:47.475952 PH8_DLY = 0
4966 13:21:47.476028 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4967 13:21:47.479137 DQ_AAMCK_DIV = 4
4968 13:21:47.482338 CA_AAMCK_DIV = 4
4969 13:21:47.485878 CA_ADMCK_DIV = 4
4970 13:21:47.489212 DQ_TRACK_CA_EN = 0
4971 13:21:47.492505 CA_PICK = 933
4972 13:21:47.492603 CA_MCKIO = 933
4973 13:21:47.495668 MCKIO_SEMI = 0
4974 13:21:47.499088 PLL_FREQ = 3732
4975 13:21:47.502642 DQ_UI_PI_RATIO = 32
4976 13:21:47.505987 CA_UI_PI_RATIO = 0
4977 13:21:47.509347 ===================================
4978 13:21:47.512533 ===================================
4979 13:21:47.516141 memory_type:LPDDR4
4980 13:21:47.516240 GP_NUM : 10
4981 13:21:47.519376 SRAM_EN : 1
4982 13:21:47.519477 MD32_EN : 0
4983 13:21:47.522655 ===================================
4984 13:21:47.525826 [ANA_INIT] >>>>>>>>>>>>>>
4985 13:21:47.529268 <<<<<< [CONFIGURE PHASE]: ANA_TX
4986 13:21:47.532558 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4987 13:21:47.535880 ===================================
4988 13:21:47.539340 data_rate = 1866,PCW = 0X8f00
4989 13:21:47.542339 ===================================
4990 13:21:47.545803 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4991 13:21:47.552851 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4992 13:21:47.555826 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4993 13:21:47.562571 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4994 13:21:47.566208 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4995 13:21:47.569642 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4996 13:21:47.569743 [ANA_INIT] flow start
4997 13:21:47.572591 [ANA_INIT] PLL >>>>>>>>
4998 13:21:47.575943 [ANA_INIT] PLL <<<<<<<<
4999 13:21:47.576015 [ANA_INIT] MIDPI >>>>>>>>
5000 13:21:47.579245 [ANA_INIT] MIDPI <<<<<<<<
5001 13:21:47.582478 [ANA_INIT] DLL >>>>>>>>
5002 13:21:47.582575 [ANA_INIT] flow end
5003 13:21:47.586140 ============ LP4 DIFF to SE enter ============
5004 13:21:47.592648 ============ LP4 DIFF to SE exit ============
5005 13:21:47.592763 [ANA_INIT] <<<<<<<<<<<<<
5006 13:21:47.595734 [Flow] Enable top DCM control >>>>>
5007 13:21:47.599634 [Flow] Enable top DCM control <<<<<
5008 13:21:47.602674 Enable DLL master slave shuffle
5009 13:21:47.609128 ==============================================================
5010 13:21:47.609203 Gating Mode config
5011 13:21:47.616387 ==============================================================
5012 13:21:47.619085 Config description:
5013 13:21:47.629341 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5014 13:21:47.636123 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5015 13:21:47.639832 SELPH_MODE 0: By rank 1: By Phase
5016 13:21:47.646247 ==============================================================
5017 13:21:47.649344 GAT_TRACK_EN = 1
5018 13:21:47.649422 RX_GATING_MODE = 2
5019 13:21:47.652612 RX_GATING_TRACK_MODE = 2
5020 13:21:47.656306 SELPH_MODE = 1
5021 13:21:47.659598 PICG_EARLY_EN = 1
5022 13:21:47.662827 VALID_LAT_VALUE = 1
5023 13:21:47.669109 ==============================================================
5024 13:21:47.672475 Enter into Gating configuration >>>>
5025 13:21:47.676132 Exit from Gating configuration <<<<
5026 13:21:47.679194 Enter into DVFS_PRE_config >>>>>
5027 13:21:47.689218 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5028 13:21:47.692799 Exit from DVFS_PRE_config <<<<<
5029 13:21:47.695726 Enter into PICG configuration >>>>
5030 13:21:47.699436 Exit from PICG configuration <<<<
5031 13:21:47.702963 [RX_INPUT] configuration >>>>>
5032 13:21:47.703068 [RX_INPUT] configuration <<<<<
5033 13:21:47.709042 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5034 13:21:47.716234 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5035 13:21:47.719583 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5036 13:21:47.726175 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5037 13:21:47.732868 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5038 13:21:47.739391 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5039 13:21:47.742723 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5040 13:21:47.746386 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5041 13:21:47.753024 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5042 13:21:47.756009 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5043 13:21:47.759893 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5044 13:21:47.762663 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5045 13:21:47.766200 ===================================
5046 13:21:47.769743 LPDDR4 DRAM CONFIGURATION
5047 13:21:47.772930 ===================================
5048 13:21:47.776075 EX_ROW_EN[0] = 0x0
5049 13:21:47.776146 EX_ROW_EN[1] = 0x0
5050 13:21:47.779342 LP4Y_EN = 0x0
5051 13:21:47.779442 WORK_FSP = 0x0
5052 13:21:47.782810 WL = 0x3
5053 13:21:47.782906 RL = 0x3
5054 13:21:47.786345 BL = 0x2
5055 13:21:47.786440 RPST = 0x0
5056 13:21:47.789910 RD_PRE = 0x0
5057 13:21:47.789984 WR_PRE = 0x1
5058 13:21:47.792841 WR_PST = 0x0
5059 13:21:47.792909 DBI_WR = 0x0
5060 13:21:47.796193 DBI_RD = 0x0
5061 13:21:47.799389 OTF = 0x1
5062 13:21:47.799465 ===================================
5063 13:21:47.806059 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5064 13:21:47.809844 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5065 13:21:47.813022 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5066 13:21:47.816567 ===================================
5067 13:21:47.819491 LPDDR4 DRAM CONFIGURATION
5068 13:21:47.823418 ===================================
5069 13:21:47.826755 EX_ROW_EN[0] = 0x10
5070 13:21:47.826829 EX_ROW_EN[1] = 0x0
5071 13:21:47.830050 LP4Y_EN = 0x0
5072 13:21:47.830120 WORK_FSP = 0x0
5073 13:21:47.833026 WL = 0x3
5074 13:21:47.833101 RL = 0x3
5075 13:21:47.836495 BL = 0x2
5076 13:21:47.836589 RPST = 0x0
5077 13:21:47.840128 RD_PRE = 0x0
5078 13:21:47.840199 WR_PRE = 0x1
5079 13:21:47.843108 WR_PST = 0x0
5080 13:21:47.843202 DBI_WR = 0x0
5081 13:21:47.846325 DBI_RD = 0x0
5082 13:21:47.846413 OTF = 0x1
5083 13:21:47.849932 ===================================
5084 13:21:47.856397 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5085 13:21:47.860803 nWR fixed to 30
5086 13:21:47.864218 [ModeRegInit_LP4] CH0 RK0
5087 13:21:47.864320 [ModeRegInit_LP4] CH0 RK1
5088 13:21:47.867525 [ModeRegInit_LP4] CH1 RK0
5089 13:21:47.870811 [ModeRegInit_LP4] CH1 RK1
5090 13:21:47.870908 match AC timing 9
5091 13:21:47.877567 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5092 13:21:47.880684 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5093 13:21:47.884164 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5094 13:21:47.890504 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5095 13:21:47.894005 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5096 13:21:47.894077 ==
5097 13:21:47.897429 Dram Type= 6, Freq= 0, CH_0, rank 0
5098 13:21:47.900575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5099 13:21:47.900708 ==
5100 13:21:47.907229 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5101 13:21:47.914183 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5102 13:21:47.917625 [CA 0] Center 38 (8~69) winsize 62
5103 13:21:47.920866 [CA 1] Center 38 (7~69) winsize 63
5104 13:21:47.923913 [CA 2] Center 35 (5~66) winsize 62
5105 13:21:47.927467 [CA 3] Center 35 (5~65) winsize 61
5106 13:21:47.931211 [CA 4] Center 34 (4~64) winsize 61
5107 13:21:47.934162 [CA 5] Center 34 (4~64) winsize 61
5108 13:21:47.934233
5109 13:21:47.937714 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5110 13:21:47.937787
5111 13:21:47.940776 [CATrainingPosCal] consider 1 rank data
5112 13:21:47.943993 u2DelayCellTimex100 = 270/100 ps
5113 13:21:47.947627 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5114 13:21:47.950815 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5115 13:21:47.954633 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5116 13:21:47.957599 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5117 13:21:47.961268 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5118 13:21:47.964195 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5119 13:21:47.964276
5120 13:21:47.970777 CA PerBit enable=1, Macro0, CA PI delay=34
5121 13:21:47.970927
5122 13:21:47.971061 [CBTSetCACLKResult] CA Dly = 34
5123 13:21:47.974156 CS Dly: 6 (0~37)
5124 13:21:47.974288 ==
5125 13:21:47.977407 Dram Type= 6, Freq= 0, CH_0, rank 1
5126 13:21:47.980803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5127 13:21:47.980927 ==
5128 13:21:47.987313 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5129 13:21:47.994243 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5130 13:21:47.997500 [CA 0] Center 38 (7~69) winsize 63
5131 13:21:48.000993 [CA 1] Center 38 (7~69) winsize 63
5132 13:21:48.004396 [CA 2] Center 35 (5~66) winsize 62
5133 13:21:48.007432 [CA 3] Center 35 (5~66) winsize 62
5134 13:21:48.011184 [CA 4] Center 34 (4~65) winsize 62
5135 13:21:48.014361 [CA 5] Center 33 (3~64) winsize 62
5136 13:21:48.014882
5137 13:21:48.017893 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5138 13:21:48.018286
5139 13:21:48.021014 [CATrainingPosCal] consider 2 rank data
5140 13:21:48.024488 u2DelayCellTimex100 = 270/100 ps
5141 13:21:48.027910 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5142 13:21:48.031018 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5143 13:21:48.034619 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5144 13:21:48.038057 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5145 13:21:48.040966 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5146 13:21:48.044797 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5147 13:21:48.045358
5148 13:21:48.047967 CA PerBit enable=1, Macro0, CA PI delay=34
5149 13:21:48.051447
5150 13:21:48.051863 [CBTSetCACLKResult] CA Dly = 34
5151 13:21:48.055712 CS Dly: 7 (0~39)
5152 13:21:48.056130
5153 13:21:48.057756 ----->DramcWriteLeveling(PI) begin...
5154 13:21:48.058184 ==
5155 13:21:48.061647 Dram Type= 6, Freq= 0, CH_0, rank 0
5156 13:21:48.064587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5157 13:21:48.065058 ==
5158 13:21:48.067888 Write leveling (Byte 0): 32 => 32
5159 13:21:48.071875 Write leveling (Byte 1): 29 => 29
5160 13:21:48.075333 DramcWriteLeveling(PI) end<-----
5161 13:21:48.075766
5162 13:21:48.076195 ==
5163 13:21:48.078117 Dram Type= 6, Freq= 0, CH_0, rank 0
5164 13:21:48.081363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5165 13:21:48.081789 ==
5166 13:21:48.084859 [Gating] SW mode calibration
5167 13:21:48.091254 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5168 13:21:48.098018 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5169 13:21:48.101207 0 14 0 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
5170 13:21:48.104965 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5171 13:21:48.111778 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 13:21:48.114701 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 13:21:48.117902 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 13:21:48.125229 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 13:21:48.128534 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 13:21:48.131427 0 14 28 | B1->B0 | 3434 3333 | 0 0 | (0 1) (0 1)
5177 13:21:48.137968 0 15 0 | B1->B0 | 3131 2d2d | 1 0 | (1 1) (0 0)
5178 13:21:48.141347 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (1 0)
5179 13:21:48.144738 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 13:21:48.151371 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 13:21:48.154754 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 13:21:48.158179 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 13:21:48.165252 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 13:21:48.168026 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5185 13:21:48.171427 1 0 0 | B1->B0 | 2d2d 3939 | 1 0 | (0 0) (0 0)
5186 13:21:48.178279 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 13:21:48.181695 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 13:21:48.184985 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 13:21:48.188071 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 13:21:48.195208 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 13:21:48.198381 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 13:21:48.201505 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 13:21:48.208362 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5194 13:21:48.211428 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5195 13:21:48.215118 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 13:21:48.221864 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 13:21:48.225002 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 13:21:48.228718 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 13:21:48.235147 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 13:21:48.238724 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 13:21:48.241814 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 13:21:48.248206 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 13:21:48.251618 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 13:21:48.254922 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 13:21:48.261561 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 13:21:48.264959 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 13:21:48.268282 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 13:21:48.275025 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 13:21:48.278542 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5210 13:21:48.281933 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5211 13:21:48.284743 Total UI for P1: 0, mck2ui 16
5212 13:21:48.288281 best dqsien dly found for B0: ( 1, 3, 0)
5213 13:21:48.291536 Total UI for P1: 0, mck2ui 16
5214 13:21:48.294959 best dqsien dly found for B1: ( 1, 3, 0)
5215 13:21:48.298953 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5216 13:21:48.301765 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5217 13:21:48.302190
5218 13:21:48.305017 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5219 13:21:48.308856 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5220 13:21:48.311926 [Gating] SW calibration Done
5221 13:21:48.312345 ==
5222 13:21:48.315016 Dram Type= 6, Freq= 0, CH_0, rank 0
5223 13:21:48.318130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5224 13:21:48.321558 ==
5225 13:21:48.321979 RX Vref Scan: 0
5226 13:21:48.322407
5227 13:21:48.324654 RX Vref 0 -> 0, step: 1
5228 13:21:48.325127
5229 13:21:48.328236 RX Delay -80 -> 252, step: 8
5230 13:21:48.331617 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5231 13:21:48.334893 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5232 13:21:48.337893 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5233 13:21:48.341517 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5234 13:21:48.344545 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5235 13:21:48.350969 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5236 13:21:48.354264 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5237 13:21:48.357816 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5238 13:21:48.361023 iDelay=200, Bit 8, Center 79 (-8 ~ 167) 176
5239 13:21:48.364539 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5240 13:21:48.367574 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5241 13:21:48.374489 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5242 13:21:48.378323 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5243 13:21:48.380997 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5244 13:21:48.384294 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5245 13:21:48.387734 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5246 13:21:48.387816 ==
5247 13:21:48.391005 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 13:21:48.397865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 13:21:48.397947 ==
5250 13:21:48.398031 DQS Delay:
5251 13:21:48.401017 DQS0 = 0, DQS1 = 0
5252 13:21:48.401099 DQM Delay:
5253 13:21:48.401182 DQM0 = 98, DQM1 = 87
5254 13:21:48.404563 DQ Delay:
5255 13:21:48.407894 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5256 13:21:48.411222 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5257 13:21:48.414863 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5258 13:21:48.418082 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5259 13:21:48.418164
5260 13:21:48.418247
5261 13:21:48.418325 ==
5262 13:21:48.421218 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 13:21:48.424624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 13:21:48.424733 ==
5265 13:21:48.424823
5266 13:21:48.424906
5267 13:21:48.428005 TX Vref Scan disable
5268 13:21:48.428092 == TX Byte 0 ==
5269 13:21:48.434969 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5270 13:21:48.438020 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5271 13:21:48.438119 == TX Byte 1 ==
5272 13:21:48.444826 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5273 13:21:48.447971 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5274 13:21:48.448089 ==
5275 13:21:48.451244 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 13:21:48.454779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 13:21:48.454927 ==
5278 13:21:48.455043
5279 13:21:48.455152
5280 13:21:48.458098 TX Vref Scan disable
5281 13:21:48.462201 == TX Byte 0 ==
5282 13:21:48.464661 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5283 13:21:48.467888 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5284 13:21:48.471962 == TX Byte 1 ==
5285 13:21:48.474950 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5286 13:21:48.479485 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5287 13:21:48.479926
5288 13:21:48.481649 [DATLAT]
5289 13:21:48.482022 Freq=933, CH0 RK0
5290 13:21:48.482321
5291 13:21:48.485268 DATLAT Default: 0xd
5292 13:21:48.485674 0, 0xFFFF, sum = 0
5293 13:21:48.488460 1, 0xFFFF, sum = 0
5294 13:21:48.489105 2, 0xFFFF, sum = 0
5295 13:21:48.491748 3, 0xFFFF, sum = 0
5296 13:21:48.492157 4, 0xFFFF, sum = 0
5297 13:21:48.495013 5, 0xFFFF, sum = 0
5298 13:21:48.495585 6, 0xFFFF, sum = 0
5299 13:21:48.498552 7, 0xFFFF, sum = 0
5300 13:21:48.498963 8, 0xFFFF, sum = 0
5301 13:21:48.501896 9, 0xFFFF, sum = 0
5302 13:21:48.502441 10, 0x0, sum = 1
5303 13:21:48.504980 11, 0x0, sum = 2
5304 13:21:48.505395 12, 0x0, sum = 3
5305 13:21:48.508313 13, 0x0, sum = 4
5306 13:21:48.508785 best_step = 11
5307 13:21:48.509221
5308 13:21:48.509630 ==
5309 13:21:48.512005 Dram Type= 6, Freq= 0, CH_0, rank 0
5310 13:21:48.518437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 13:21:48.518859 ==
5312 13:21:48.519293 RX Vref Scan: 1
5313 13:21:48.519700
5314 13:21:48.521660 RX Vref 0 -> 0, step: 1
5315 13:21:48.522080
5316 13:21:48.525236 RX Delay -61 -> 252, step: 4
5317 13:21:48.525664
5318 13:21:48.528528 Set Vref, RX VrefLevel [Byte0]: 53
5319 13:21:48.531869 [Byte1]: 53
5320 13:21:48.532327
5321 13:21:48.534977 Final RX Vref Byte 0 = 53 to rank0
5322 13:21:48.538645 Final RX Vref Byte 1 = 53 to rank0
5323 13:21:48.541738 Final RX Vref Byte 0 = 53 to rank1
5324 13:21:48.545226 Final RX Vref Byte 1 = 53 to rank1==
5325 13:21:48.548393 Dram Type= 6, Freq= 0, CH_0, rank 0
5326 13:21:48.551613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 13:21:48.552041 ==
5328 13:21:48.555056 DQS Delay:
5329 13:21:48.555476 DQS0 = 0, DQS1 = 0
5330 13:21:48.555907 DQM Delay:
5331 13:21:48.558407 DQM0 = 96, DQM1 = 88
5332 13:21:48.558828 DQ Delay:
5333 13:21:48.561764 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5334 13:21:48.565208 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =102
5335 13:21:48.568749 DQ8 =80, DQ9 =76, DQ10 =86, DQ11 =80
5336 13:21:48.571834 DQ12 =96, DQ13 =92, DQ14 =100, DQ15 =96
5337 13:21:48.572260
5338 13:21:48.572718
5339 13:21:48.581703 [DQSOSCAuto] RK0, (LSB)MR18= 0x13fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5340 13:21:48.582154 CH0 RK0: MR19=504, MR18=13FE
5341 13:21:48.588598 CH0_RK0: MR19=0x504, MR18=0x13FE, DQSOSC=415, MR23=63, INC=62, DEC=41
5342 13:21:48.589058
5343 13:21:48.592012 ----->DramcWriteLeveling(PI) begin...
5344 13:21:48.592438 ==
5345 13:21:48.595465 Dram Type= 6, Freq= 0, CH_0, rank 1
5346 13:21:48.601721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 13:21:48.602245 ==
5348 13:21:48.605151 Write leveling (Byte 0): 27 => 27
5349 13:21:48.608721 Write leveling (Byte 1): 27 => 27
5350 13:21:48.609218 DramcWriteLeveling(PI) end<-----
5351 13:21:48.611904
5352 13:21:48.612396 ==
5353 13:21:48.615266 Dram Type= 6, Freq= 0, CH_0, rank 1
5354 13:21:48.618890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5355 13:21:48.619177 ==
5356 13:21:48.621551 [Gating] SW mode calibration
5357 13:21:48.628391 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5358 13:21:48.631563 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5359 13:21:48.638146 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5360 13:21:48.641835 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5361 13:21:48.644648 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 13:21:48.651784 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 13:21:48.655200 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 13:21:48.658040 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 13:21:48.664642 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 13:21:48.667932 0 14 28 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 0)
5367 13:21:48.672041 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
5368 13:21:48.678141 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5369 13:21:48.681711 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 13:21:48.684853 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 13:21:48.691678 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 13:21:48.694634 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 13:21:48.698179 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 13:21:48.701484 0 15 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5375 13:21:48.708775 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5376 13:21:48.711751 1 0 4 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
5377 13:21:48.714766 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 13:21:48.721791 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 13:21:48.725545 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 13:21:48.728976 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 13:21:48.734858 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 13:21:48.738155 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5383 13:21:48.741835 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5384 13:21:48.748298 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5385 13:21:48.751490 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 13:21:48.754734 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 13:21:48.761642 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 13:21:48.764824 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 13:21:48.768279 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 13:21:48.775054 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 13:21:48.778530 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 13:21:48.781738 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 13:21:48.784679 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 13:21:48.791587 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 13:21:48.795201 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 13:21:48.798496 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 13:21:48.804997 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5398 13:21:48.808301 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5399 13:21:48.811586 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5400 13:21:48.814828 Total UI for P1: 0, mck2ui 16
5401 13:21:48.818264 best dqsien dly found for B0: ( 1, 2, 26)
5402 13:21:48.825000 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 13:21:48.825106 Total UI for P1: 0, mck2ui 16
5404 13:21:48.831724 best dqsien dly found for B1: ( 1, 3, 0)
5405 13:21:48.835030 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5406 13:21:48.838263 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5407 13:21:48.838343
5408 13:21:48.842408 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5409 13:21:48.845230 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5410 13:21:48.848605 [Gating] SW calibration Done
5411 13:21:48.848712 ==
5412 13:21:48.852199 Dram Type= 6, Freq= 0, CH_0, rank 1
5413 13:21:48.855577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5414 13:21:48.855657 ==
5415 13:21:48.858429 RX Vref Scan: 0
5416 13:21:48.858518
5417 13:21:48.858581 RX Vref 0 -> 0, step: 1
5418 13:21:48.858640
5419 13:21:48.862073 RX Delay -80 -> 252, step: 8
5420 13:21:48.865610 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5421 13:21:48.868982 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5422 13:21:48.875350 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5423 13:21:48.878638 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5424 13:21:48.882053 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5425 13:21:48.885354 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5426 13:21:48.888487 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5427 13:21:48.892118 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5428 13:21:48.895423 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5429 13:21:48.902413 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5430 13:21:48.905374 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5431 13:21:48.908580 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5432 13:21:48.912624 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5433 13:21:48.915371 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5434 13:21:48.922266 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5435 13:21:48.925544 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5436 13:21:48.925624 ==
5437 13:21:48.928602 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 13:21:48.932283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 13:21:48.932363 ==
5440 13:21:48.932427 DQS Delay:
5441 13:21:48.935622 DQS0 = 0, DQS1 = 0
5442 13:21:48.935702 DQM Delay:
5443 13:21:48.938709 DQM0 = 97, DQM1 = 87
5444 13:21:48.938789 DQ Delay:
5445 13:21:48.942138 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5446 13:21:48.945416 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5447 13:21:48.948687 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5448 13:21:48.952216 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5449 13:21:48.952295
5450 13:21:48.952357
5451 13:21:48.952415 ==
5452 13:21:48.955800 Dram Type= 6, Freq= 0, CH_0, rank 1
5453 13:21:48.959076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5454 13:21:48.962117 ==
5455 13:21:48.962196
5456 13:21:48.962258
5457 13:21:48.962318 TX Vref Scan disable
5458 13:21:48.965596 == TX Byte 0 ==
5459 13:21:48.968936 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5460 13:21:48.972177 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5461 13:21:48.975801 == TX Byte 1 ==
5462 13:21:48.979183 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5463 13:21:48.982291 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5464 13:21:48.982372 ==
5465 13:21:48.986121 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 13:21:48.992612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 13:21:48.992747 ==
5468 13:21:48.992812
5469 13:21:48.992870
5470 13:21:48.992927 TX Vref Scan disable
5471 13:21:48.996612 == TX Byte 0 ==
5472 13:21:48.999823 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5473 13:21:49.003290 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5474 13:21:49.006570 == TX Byte 1 ==
5475 13:21:49.009867 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5476 13:21:49.013784 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5477 13:21:49.016496
5478 13:21:49.016577 [DATLAT]
5479 13:21:49.016683 Freq=933, CH0 RK1
5480 13:21:49.016764
5481 13:21:49.019993 DATLAT Default: 0xb
5482 13:21:49.020074 0, 0xFFFF, sum = 0
5483 13:21:49.024089 1, 0xFFFF, sum = 0
5484 13:21:49.024172 2, 0xFFFF, sum = 0
5485 13:21:49.026677 3, 0xFFFF, sum = 0
5486 13:21:49.026760 4, 0xFFFF, sum = 0
5487 13:21:49.030174 5, 0xFFFF, sum = 0
5488 13:21:49.030257 6, 0xFFFF, sum = 0
5489 13:21:49.033306 7, 0xFFFF, sum = 0
5490 13:21:49.036433 8, 0xFFFF, sum = 0
5491 13:21:49.036547 9, 0xFFFF, sum = 0
5492 13:21:49.039744 10, 0x0, sum = 1
5493 13:21:49.039825 11, 0x0, sum = 2
5494 13:21:49.039889 12, 0x0, sum = 3
5495 13:21:49.042958 13, 0x0, sum = 4
5496 13:21:49.043038 best_step = 11
5497 13:21:49.043102
5498 13:21:49.046589 ==
5499 13:21:49.046670 Dram Type= 6, Freq= 0, CH_0, rank 1
5500 13:21:49.053092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5501 13:21:49.053173 ==
5502 13:21:49.053237 RX Vref Scan: 0
5503 13:21:49.053296
5504 13:21:49.056453 RX Vref 0 -> 0, step: 1
5505 13:21:49.056558
5506 13:21:49.059813 RX Delay -69 -> 252, step: 4
5507 13:21:49.063189 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5508 13:21:49.066453 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5509 13:21:49.073113 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5510 13:21:49.076480 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5511 13:21:49.079621 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5512 13:21:49.083050 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5513 13:21:49.086495 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5514 13:21:49.089710 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5515 13:21:49.096303 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5516 13:21:49.099760 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5517 13:21:49.103262 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5518 13:21:49.106597 iDelay=199, Bit 11, Center 82 (-5 ~ 170) 176
5519 13:21:49.109950 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5520 13:21:49.116502 iDelay=199, Bit 13, Center 94 (7 ~ 182) 176
5521 13:21:49.120016 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5522 13:21:49.122936 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5523 13:21:49.123021 ==
5524 13:21:49.126350 Dram Type= 6, Freq= 0, CH_0, rank 1
5525 13:21:49.129664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5526 13:21:49.129764 ==
5527 13:21:49.132813 DQS Delay:
5528 13:21:49.132912 DQS0 = 0, DQS1 = 0
5529 13:21:49.132991 DQM Delay:
5530 13:21:49.136817 DQM0 = 96, DQM1 = 88
5531 13:21:49.136925 DQ Delay:
5532 13:21:49.139659 DQ0 =98, DQ1 =96, DQ2 =92, DQ3 =94
5533 13:21:49.143286 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =102
5534 13:21:49.146397 DQ8 =82, DQ9 =78, DQ10 =88, DQ11 =82
5535 13:21:49.150186 DQ12 =94, DQ13 =94, DQ14 =96, DQ15 =96
5536 13:21:49.150334
5537 13:21:49.150453
5538 13:21:49.159951 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c09, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 412 ps
5539 13:21:49.160151 CH0 RK1: MR19=505, MR18=1C09
5540 13:21:49.166593 CH0_RK1: MR19=0x505, MR18=0x1C09, DQSOSC=412, MR23=63, INC=63, DEC=42
5541 13:21:49.170211 [RxdqsGatingPostProcess] freq 933
5542 13:21:49.176949 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5543 13:21:49.180273 best DQS0 dly(2T, 0.5T) = (0, 11)
5544 13:21:49.183989 best DQS1 dly(2T, 0.5T) = (0, 11)
5545 13:21:49.187103 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5546 13:21:49.190684 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5547 13:21:49.193604 best DQS0 dly(2T, 0.5T) = (0, 10)
5548 13:21:49.194014 best DQS1 dly(2T, 0.5T) = (0, 11)
5549 13:21:49.196876 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5550 13:21:49.200726 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5551 13:21:49.203376 Pre-setting of DQS Precalculation
5552 13:21:49.210329 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5553 13:21:49.210750 ==
5554 13:21:49.213504 Dram Type= 6, Freq= 0, CH_1, rank 0
5555 13:21:49.216708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5556 13:21:49.217139 ==
5557 13:21:49.223984 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5558 13:21:49.230491 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5559 13:21:49.233679 [CA 0] Center 36 (6~67) winsize 62
5560 13:21:49.236835 [CA 1] Center 36 (6~67) winsize 62
5561 13:21:49.239908 [CA 2] Center 34 (4~64) winsize 61
5562 13:21:49.243876 [CA 3] Center 33 (3~64) winsize 62
5563 13:21:49.247115 [CA 4] Center 33 (3~64) winsize 62
5564 13:21:49.250488 [CA 5] Center 33 (3~63) winsize 61
5565 13:21:49.250898
5566 13:21:49.253680 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5567 13:21:49.254096
5568 13:21:49.257080 [CATrainingPosCal] consider 1 rank data
5569 13:21:49.260422 u2DelayCellTimex100 = 270/100 ps
5570 13:21:49.263760 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5571 13:21:49.266954 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5572 13:21:49.270323 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5573 13:21:49.273856 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5574 13:21:49.277060 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5575 13:21:49.280126 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5576 13:21:49.280538
5577 13:21:49.284177 CA PerBit enable=1, Macro0, CA PI delay=33
5578 13:21:49.284648
5579 13:21:49.287382 [CBTSetCACLKResult] CA Dly = 33
5580 13:21:49.290158 CS Dly: 4 (0~35)
5581 13:21:49.290566 ==
5582 13:21:49.293896 Dram Type= 6, Freq= 0, CH_1, rank 1
5583 13:21:49.297015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5584 13:21:49.297432 ==
5585 13:21:49.303606 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5586 13:21:49.310136 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5587 13:21:49.313405 [CA 0] Center 36 (6~67) winsize 62
5588 13:21:49.316973 [CA 1] Center 36 (6~67) winsize 62
5589 13:21:49.319963 [CA 2] Center 33 (3~64) winsize 62
5590 13:21:49.323359 [CA 3] Center 33 (3~64) winsize 62
5591 13:21:49.326818 [CA 4] Center 34 (4~65) winsize 62
5592 13:21:49.327248 [CA 5] Center 33 (3~63) winsize 61
5593 13:21:49.330429
5594 13:21:49.333680 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5595 13:21:49.334122
5596 13:21:49.336695 [CATrainingPosCal] consider 2 rank data
5597 13:21:49.340388 u2DelayCellTimex100 = 270/100 ps
5598 13:21:49.343393 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5599 13:21:49.347327 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5600 13:21:49.350142 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5601 13:21:49.353593 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5602 13:21:49.357895 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5603 13:21:49.360378 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5604 13:21:49.360831
5605 13:21:49.363518 CA PerBit enable=1, Macro0, CA PI delay=33
5606 13:21:49.363985
5607 13:21:49.367033 [CBTSetCACLKResult] CA Dly = 33
5608 13:21:49.370201 CS Dly: 5 (0~37)
5609 13:21:49.370622
5610 13:21:49.373363 ----->DramcWriteLeveling(PI) begin...
5611 13:21:49.373788 ==
5612 13:21:49.377468 Dram Type= 6, Freq= 0, CH_1, rank 0
5613 13:21:49.380432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5614 13:21:49.380919 ==
5615 13:21:49.383502 Write leveling (Byte 0): 28 => 28
5616 13:21:49.386806 Write leveling (Byte 1): 29 => 29
5617 13:21:49.390823 DramcWriteLeveling(PI) end<-----
5618 13:21:49.391243
5619 13:21:49.391676 ==
5620 13:21:49.393595 Dram Type= 6, Freq= 0, CH_1, rank 0
5621 13:21:49.397432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5622 13:21:49.397872 ==
5623 13:21:49.400075 [Gating] SW mode calibration
5624 13:21:49.406832 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5625 13:21:49.413930 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5626 13:21:49.417064 0 14 0 | B1->B0 | 3030 3333 | 1 0 | (0 0) (0 0)
5627 13:21:49.420435 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 13:21:49.426773 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 13:21:49.430314 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 13:21:49.433976 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5631 13:21:49.440261 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5632 13:21:49.443819 0 14 24 | B1->B0 | 3534 3434 | 1 1 | (1 1) (1 1)
5633 13:21:49.446925 0 14 28 | B1->B0 | 2e2e 3030 | 1 1 | (1 1) (1 0)
5634 13:21:49.453754 0 15 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 0)
5635 13:21:49.457044 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 13:21:49.460413 0 15 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5637 13:21:49.466965 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 13:21:49.470143 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 13:21:49.473100 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 13:21:49.480128 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 13:21:49.483633 0 15 28 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 0)
5642 13:21:49.486829 1 0 0 | B1->B0 | 4444 4242 | 0 0 | (0 0) (1 1)
5643 13:21:49.489925 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 13:21:49.496545 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 13:21:49.500522 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 13:21:49.503427 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 13:21:49.510071 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 13:21:49.513513 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 13:21:49.517163 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5650 13:21:49.523659 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5651 13:21:49.526688 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 13:21:49.530161 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 13:21:49.537112 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 13:21:49.540261 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 13:21:49.543298 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 13:21:49.550143 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 13:21:49.553447 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 13:21:49.556783 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 13:21:49.563472 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 13:21:49.567117 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 13:21:49.570264 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 13:21:49.576786 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 13:21:49.580203 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 13:21:49.583230 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 13:21:49.590034 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 13:21:49.590113 Total UI for P1: 0, mck2ui 16
5667 13:21:49.593357 best dqsien dly found for B0: ( 1, 2, 26)
5668 13:21:49.597049 Total UI for P1: 0, mck2ui 16
5669 13:21:49.599755 best dqsien dly found for B1: ( 1, 2, 26)
5670 13:21:49.603296 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5671 13:21:49.609764 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5672 13:21:49.609843
5673 13:21:49.613464 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5674 13:21:49.616445 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5675 13:21:49.619906 [Gating] SW calibration Done
5676 13:21:49.619985 ==
5677 13:21:49.623116 Dram Type= 6, Freq= 0, CH_1, rank 0
5678 13:21:49.626457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5679 13:21:49.626536 ==
5680 13:21:49.626598 RX Vref Scan: 0
5681 13:21:49.630238
5682 13:21:49.630316 RX Vref 0 -> 0, step: 1
5683 13:21:49.630378
5684 13:21:49.633057 RX Delay -80 -> 252, step: 8
5685 13:21:49.637020 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5686 13:21:49.639579 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5687 13:21:49.646352 iDelay=208, Bit 2, Center 83 (-8 ~ 175) 184
5688 13:21:49.650056 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5689 13:21:49.653376 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5690 13:21:49.656685 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5691 13:21:49.659823 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5692 13:21:49.663458 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5693 13:21:49.670182 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5694 13:21:49.673607 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5695 13:21:49.676928 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5696 13:21:49.680052 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5697 13:21:49.683084 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5698 13:21:49.686626 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5699 13:21:49.693189 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5700 13:21:49.696674 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5701 13:21:49.696769 ==
5702 13:21:49.700101 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 13:21:49.703686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 13:21:49.703767 ==
5705 13:21:49.703830 DQS Delay:
5706 13:21:49.706928 DQS0 = 0, DQS1 = 0
5707 13:21:49.707008 DQM Delay:
5708 13:21:49.710029 DQM0 = 96, DQM1 = 89
5709 13:21:49.710108 DQ Delay:
5710 13:21:49.713689 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5711 13:21:49.716617 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5712 13:21:49.719735 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5713 13:21:49.723939 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5714 13:21:49.724020
5715 13:21:49.724083
5716 13:21:49.724142 ==
5717 13:21:49.726498 Dram Type= 6, Freq= 0, CH_1, rank 0
5718 13:21:49.733278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5719 13:21:49.733359 ==
5720 13:21:49.733422
5721 13:21:49.733480
5722 13:21:49.733536 TX Vref Scan disable
5723 13:21:49.736947 == TX Byte 0 ==
5724 13:21:49.739799 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5725 13:21:49.743418 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5726 13:21:49.746812 == TX Byte 1 ==
5727 13:21:49.749814 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5728 13:21:49.753166 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5729 13:21:49.757054 ==
5730 13:21:49.757134 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 13:21:49.763579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 13:21:49.763659 ==
5733 13:21:49.763722
5734 13:21:49.763780
5735 13:21:49.766367 TX Vref Scan disable
5736 13:21:49.766446 == TX Byte 0 ==
5737 13:21:49.773099 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5738 13:21:49.776736 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5739 13:21:49.776816 == TX Byte 1 ==
5740 13:21:49.783328 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5741 13:21:49.786486 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5742 13:21:49.786565
5743 13:21:49.786628 [DATLAT]
5744 13:21:49.789782 Freq=933, CH1 RK0
5745 13:21:49.789862
5746 13:21:49.789924 DATLAT Default: 0xd
5747 13:21:49.793348 0, 0xFFFF, sum = 0
5748 13:21:49.793429 1, 0xFFFF, sum = 0
5749 13:21:49.796813 2, 0xFFFF, sum = 0
5750 13:21:49.796894 3, 0xFFFF, sum = 0
5751 13:21:49.799911 4, 0xFFFF, sum = 0
5752 13:21:49.799993 5, 0xFFFF, sum = 0
5753 13:21:49.803145 6, 0xFFFF, sum = 0
5754 13:21:49.803228 7, 0xFFFF, sum = 0
5755 13:21:49.806454 8, 0xFFFF, sum = 0
5756 13:21:49.806535 9, 0xFFFF, sum = 0
5757 13:21:49.809907 10, 0x0, sum = 1
5758 13:21:49.809988 11, 0x0, sum = 2
5759 13:21:49.813408 12, 0x0, sum = 3
5760 13:21:49.813516 13, 0x0, sum = 4
5761 13:21:49.816823 best_step = 11
5762 13:21:49.816904
5763 13:21:49.816966 ==
5764 13:21:49.819828 Dram Type= 6, Freq= 0, CH_1, rank 0
5765 13:21:49.823439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5766 13:21:49.823519 ==
5767 13:21:49.826828 RX Vref Scan: 1
5768 13:21:49.826907
5769 13:21:49.826969 RX Vref 0 -> 0, step: 1
5770 13:21:49.827028
5771 13:21:49.830753 RX Delay -61 -> 252, step: 4
5772 13:21:49.830833
5773 13:21:49.833480 Set Vref, RX VrefLevel [Byte0]: 60
5774 13:21:49.836624 [Byte1]: 51
5775 13:21:49.840644
5776 13:21:49.840747 Final RX Vref Byte 0 = 60 to rank0
5777 13:21:49.844207 Final RX Vref Byte 1 = 51 to rank0
5778 13:21:49.847266 Final RX Vref Byte 0 = 60 to rank1
5779 13:21:49.850501 Final RX Vref Byte 1 = 51 to rank1==
5780 13:21:49.853924 Dram Type= 6, Freq= 0, CH_1, rank 0
5781 13:21:49.857655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 13:21:49.860610 ==
5783 13:21:49.860739 DQS Delay:
5784 13:21:49.860803 DQS0 = 0, DQS1 = 0
5785 13:21:49.863888 DQM Delay:
5786 13:21:49.863967 DQM0 = 98, DQM1 = 90
5787 13:21:49.867463 DQ Delay:
5788 13:21:49.867543 DQ0 =100, DQ1 =92, DQ2 =88, DQ3 =96
5789 13:21:49.870501 DQ4 =96, DQ5 =108, DQ6 =110, DQ7 =94
5790 13:21:49.873727 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =86
5791 13:21:49.880644 DQ12 =100, DQ13 =98, DQ14 =96, DQ15 =96
5792 13:21:49.880750
5793 13:21:49.880813
5794 13:21:49.887236 [DQSOSCAuto] RK0, (LSB)MR18= 0x19f6, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 413 ps
5795 13:21:49.890508 CH1 RK0: MR19=504, MR18=19F6
5796 13:21:49.897296 CH1_RK0: MR19=0x504, MR18=0x19F6, DQSOSC=413, MR23=63, INC=63, DEC=42
5797 13:21:49.897380
5798 13:21:49.900277 ----->DramcWriteLeveling(PI) begin...
5799 13:21:49.900359 ==
5800 13:21:49.903854 Dram Type= 6, Freq= 0, CH_1, rank 1
5801 13:21:49.907255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 13:21:49.907335 ==
5803 13:21:49.910526 Write leveling (Byte 0): 28 => 28
5804 13:21:49.914079 Write leveling (Byte 1): 26 => 26
5805 13:21:49.917291 DramcWriteLeveling(PI) end<-----
5806 13:21:49.917370
5807 13:21:49.917433 ==
5808 13:21:49.920633 Dram Type= 6, Freq= 0, CH_1, rank 1
5809 13:21:49.923690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5810 13:21:49.923770 ==
5811 13:21:49.927405 [Gating] SW mode calibration
5812 13:21:49.934133 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5813 13:21:49.940615 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5814 13:21:49.943967 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 13:21:49.947491 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5816 13:21:49.953862 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 13:21:49.957346 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 13:21:49.961160 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5819 13:21:49.967410 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5820 13:21:49.970600 0 14 24 | B1->B0 | 3131 2e2e | 0 0 | (0 0) (0 0)
5821 13:21:49.974210 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5822 13:21:49.980525 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 13:21:49.984173 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 13:21:49.987155 0 15 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5825 13:21:49.994399 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 13:21:49.997245 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 13:21:50.000534 0 15 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5828 13:21:50.007275 0 15 24 | B1->B0 | 2929 3636 | 1 1 | (0 0) (0 0)
5829 13:21:50.010619 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5830 13:21:50.013943 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 13:21:50.016997 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 13:21:50.023878 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 13:21:50.026932 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 13:21:50.030889 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 13:21:50.036846 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5836 13:21:50.040515 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5837 13:21:50.043655 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5838 13:21:50.050719 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 13:21:50.053565 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 13:21:50.057151 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 13:21:50.063697 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 13:21:50.066872 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 13:21:50.070344 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 13:21:50.076894 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 13:21:50.080497 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 13:21:50.084125 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 13:21:50.090278 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 13:21:50.094055 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 13:21:50.097324 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 13:21:50.104024 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 13:21:50.107041 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 13:21:50.110558 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5853 13:21:50.114185 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5854 13:21:50.117025 Total UI for P1: 0, mck2ui 16
5855 13:21:50.120798 best dqsien dly found for B0: ( 1, 2, 24)
5856 13:21:50.127030 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5857 13:21:50.130596 Total UI for P1: 0, mck2ui 16
5858 13:21:50.134167 best dqsien dly found for B1: ( 1, 2, 28)
5859 13:21:50.137750 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5860 13:21:50.141070 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5861 13:21:50.141149
5862 13:21:50.144253 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5863 13:21:50.147441 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5864 13:21:50.150666 [Gating] SW calibration Done
5865 13:21:50.150746 ==
5866 13:21:50.154252 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 13:21:50.157380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 13:21:50.157460 ==
5869 13:21:50.160482 RX Vref Scan: 0
5870 13:21:50.160562
5871 13:21:50.160624 RX Vref 0 -> 0, step: 1
5872 13:21:50.160694
5873 13:21:50.164162 RX Delay -80 -> 252, step: 8
5874 13:21:50.167605 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5875 13:21:50.173991 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5876 13:21:50.177609 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5877 13:21:50.180678 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5878 13:21:50.184003 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5879 13:21:50.187485 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5880 13:21:50.191095 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5881 13:21:50.197176 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5882 13:21:50.200582 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5883 13:21:50.203998 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5884 13:21:50.207535 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5885 13:21:50.210992 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5886 13:21:50.214202 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5887 13:21:50.220821 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5888 13:21:50.224453 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5889 13:21:50.227416 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5890 13:21:50.227495 ==
5891 13:21:50.231097 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 13:21:50.234161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 13:21:50.234242 ==
5894 13:21:50.237662 DQS Delay:
5895 13:21:50.237741 DQS0 = 0, DQS1 = 0
5896 13:21:50.237804 DQM Delay:
5897 13:21:50.241081 DQM0 = 95, DQM1 = 89
5898 13:21:50.241161 DQ Delay:
5899 13:21:50.244270 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =95
5900 13:21:50.247261 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5901 13:21:50.251025 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5902 13:21:50.254162 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5903 13:21:50.254241
5904 13:21:50.254304
5905 13:21:50.254362 ==
5906 13:21:50.257484 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 13:21:50.263928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 13:21:50.264008 ==
5909 13:21:50.264072
5910 13:21:50.264131
5911 13:21:50.264186 TX Vref Scan disable
5912 13:21:50.267600 == TX Byte 0 ==
5913 13:21:50.270642 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5914 13:21:50.277635 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5915 13:21:50.277715 == TX Byte 1 ==
5916 13:21:50.280599 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5917 13:21:50.284401 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5918 13:21:50.287665 ==
5919 13:21:50.290914 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 13:21:50.294445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 13:21:50.294525 ==
5922 13:21:50.294589
5923 13:21:50.294646
5924 13:21:50.297518 TX Vref Scan disable
5925 13:21:50.297597 == TX Byte 0 ==
5926 13:21:50.304087 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5927 13:21:50.307572 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5928 13:21:50.307652 == TX Byte 1 ==
5929 13:21:50.314060 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5930 13:21:50.317365 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5931 13:21:50.317445
5932 13:21:50.317508 [DATLAT]
5933 13:21:50.320851 Freq=933, CH1 RK1
5934 13:21:50.320931
5935 13:21:50.320993 DATLAT Default: 0xb
5936 13:21:50.324284 0, 0xFFFF, sum = 0
5937 13:21:50.324366 1, 0xFFFF, sum = 0
5938 13:21:50.327770 2, 0xFFFF, sum = 0
5939 13:21:50.327851 3, 0xFFFF, sum = 0
5940 13:21:50.331092 4, 0xFFFF, sum = 0
5941 13:21:50.331173 5, 0xFFFF, sum = 0
5942 13:21:50.334193 6, 0xFFFF, sum = 0
5943 13:21:50.334274 7, 0xFFFF, sum = 0
5944 13:21:50.337366 8, 0xFFFF, sum = 0
5945 13:21:50.337447 9, 0xFFFF, sum = 0
5946 13:21:50.341112 10, 0x0, sum = 1
5947 13:21:50.341193 11, 0x0, sum = 2
5948 13:21:50.344276 12, 0x0, sum = 3
5949 13:21:50.344357 13, 0x0, sum = 4
5950 13:21:50.347698 best_step = 11
5951 13:21:50.347776
5952 13:21:50.347838 ==
5953 13:21:50.350862 Dram Type= 6, Freq= 0, CH_1, rank 1
5954 13:21:50.354093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5955 13:21:50.354174 ==
5956 13:21:50.357571 RX Vref Scan: 0
5957 13:21:50.357651
5958 13:21:50.357712 RX Vref 0 -> 0, step: 1
5959 13:21:50.357771
5960 13:21:50.360592 RX Delay -61 -> 252, step: 4
5961 13:21:50.368114 iDelay=195, Bit 0, Center 98 (7 ~ 190) 184
5962 13:21:50.371597 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5963 13:21:50.374728 iDelay=195, Bit 2, Center 86 (-5 ~ 178) 184
5964 13:21:50.378003 iDelay=195, Bit 3, Center 92 (-1 ~ 186) 188
5965 13:21:50.381320 iDelay=195, Bit 4, Center 96 (7 ~ 186) 180
5966 13:21:50.384624 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5967 13:21:50.391119 iDelay=195, Bit 6, Center 102 (11 ~ 194) 184
5968 13:21:50.394674 iDelay=195, Bit 7, Center 90 (3 ~ 178) 176
5969 13:21:50.397839 iDelay=195, Bit 8, Center 80 (-13 ~ 174) 188
5970 13:21:50.401007 iDelay=195, Bit 9, Center 78 (-13 ~ 170) 184
5971 13:21:50.404409 iDelay=195, Bit 10, Center 92 (3 ~ 182) 180
5972 13:21:50.408169 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5973 13:21:50.414577 iDelay=195, Bit 12, Center 98 (11 ~ 186) 176
5974 13:21:50.417898 iDelay=195, Bit 13, Center 98 (7 ~ 190) 184
5975 13:21:50.421582 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5976 13:21:50.424670 iDelay=195, Bit 15, Center 98 (7 ~ 190) 184
5977 13:21:50.424753 ==
5978 13:21:50.427968 Dram Type= 6, Freq= 0, CH_1, rank 1
5979 13:21:50.431206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5980 13:21:50.434655 ==
5981 13:21:50.434735 DQS Delay:
5982 13:21:50.434797 DQS0 = 0, DQS1 = 0
5983 13:21:50.438371 DQM Delay:
5984 13:21:50.438451 DQM0 = 94, DQM1 = 90
5985 13:21:50.441171 DQ Delay:
5986 13:21:50.441250 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =92
5987 13:21:50.444361 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =90
5988 13:21:50.447989 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =84
5989 13:21:50.451433 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =98
5990 13:21:50.455018
5991 13:21:50.455096
5992 13:21:50.461575 [DQSOSCAuto] RK1, (LSB)MR18= 0xc14, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
5993 13:21:50.465069 CH1 RK1: MR19=505, MR18=C14
5994 13:21:50.471488 CH1_RK1: MR19=0x505, MR18=0xC14, DQSOSC=415, MR23=63, INC=62, DEC=41
5995 13:21:50.471569 [RxdqsGatingPostProcess] freq 933
5996 13:21:50.478128 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5997 13:21:50.481455 best DQS0 dly(2T, 0.5T) = (0, 10)
5998 13:21:50.484388 best DQS1 dly(2T, 0.5T) = (0, 10)
5999 13:21:50.487863 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6000 13:21:50.491475 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6001 13:21:50.494652 best DQS0 dly(2T, 0.5T) = (0, 10)
6002 13:21:50.498123 best DQS1 dly(2T, 0.5T) = (0, 10)
6003 13:21:50.501170 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6004 13:21:50.504511 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6005 13:21:50.508189 Pre-setting of DQS Precalculation
6006 13:21:50.511294 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6007 13:21:50.517990 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6008 13:21:50.524888 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6009 13:21:50.524968
6010 13:21:50.525031
6011 13:21:50.528359 [Calibration Summary] 1866 Mbps
6012 13:21:50.531294 CH 0, Rank 0
6013 13:21:50.531373 SW Impedance : PASS
6014 13:21:50.535358 DUTY Scan : NO K
6015 13:21:50.538056 ZQ Calibration : PASS
6016 13:21:50.538136 Jitter Meter : NO K
6017 13:21:50.541351 CBT Training : PASS
6018 13:21:50.544852 Write leveling : PASS
6019 13:21:50.544932 RX DQS gating : PASS
6020 13:21:50.548005 RX DQ/DQS(RDDQC) : PASS
6021 13:21:50.548084 TX DQ/DQS : PASS
6022 13:21:50.551283 RX DATLAT : PASS
6023 13:21:50.555144 RX DQ/DQS(Engine): PASS
6024 13:21:50.555225 TX OE : NO K
6025 13:21:50.558657 All Pass.
6026 13:21:50.558737
6027 13:21:50.558799 CH 0, Rank 1
6028 13:21:50.561571 SW Impedance : PASS
6029 13:21:50.561651 DUTY Scan : NO K
6030 13:21:50.564905 ZQ Calibration : PASS
6031 13:21:50.568076 Jitter Meter : NO K
6032 13:21:50.568156 CBT Training : PASS
6033 13:21:50.571444 Write leveling : PASS
6034 13:21:50.574797 RX DQS gating : PASS
6035 13:21:50.574876 RX DQ/DQS(RDDQC) : PASS
6036 13:21:50.578224 TX DQ/DQS : PASS
6037 13:21:50.581907 RX DATLAT : PASS
6038 13:21:50.581987 RX DQ/DQS(Engine): PASS
6039 13:21:50.585012 TX OE : NO K
6040 13:21:50.585092 All Pass.
6041 13:21:50.585154
6042 13:21:50.587933 CH 1, Rank 0
6043 13:21:50.588013 SW Impedance : PASS
6044 13:21:50.591543 DUTY Scan : NO K
6045 13:21:50.591622 ZQ Calibration : PASS
6046 13:21:50.594982 Jitter Meter : NO K
6047 13:21:50.598369 CBT Training : PASS
6048 13:21:50.598449 Write leveling : PASS
6049 13:21:50.601454 RX DQS gating : PASS
6050 13:21:50.604917 RX DQ/DQS(RDDQC) : PASS
6051 13:21:50.604997 TX DQ/DQS : PASS
6052 13:21:50.608385 RX DATLAT : PASS
6053 13:21:50.611800 RX DQ/DQS(Engine): PASS
6054 13:21:50.611879 TX OE : NO K
6055 13:21:50.614692 All Pass.
6056 13:21:50.614775
6057 13:21:50.614840 CH 1, Rank 1
6058 13:21:50.618401 SW Impedance : PASS
6059 13:21:50.618481 DUTY Scan : NO K
6060 13:21:50.621460 ZQ Calibration : PASS
6061 13:21:50.624827 Jitter Meter : NO K
6062 13:21:50.624907 CBT Training : PASS
6063 13:21:50.628467 Write leveling : PASS
6064 13:21:50.631291 RX DQS gating : PASS
6065 13:21:50.631372 RX DQ/DQS(RDDQC) : PASS
6066 13:21:50.635206 TX DQ/DQS : PASS
6067 13:21:50.635286 RX DATLAT : PASS
6068 13:21:50.638544 RX DQ/DQS(Engine): PASS
6069 13:21:50.641782 TX OE : NO K
6070 13:21:50.641862 All Pass.
6071 13:21:50.641925
6072 13:21:50.644642 DramC Write-DBI off
6073 13:21:50.644761 PER_BANK_REFRESH: Hybrid Mode
6074 13:21:50.648264 TX_TRACKING: ON
6075 13:21:50.658608 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6076 13:21:50.661376 [FAST_K] Save calibration result to emmc
6077 13:21:50.665266 dramc_set_vcore_voltage set vcore to 650000
6078 13:21:50.665345 Read voltage for 400, 6
6079 13:21:50.668722 Vio18 = 0
6080 13:21:50.668801 Vcore = 650000
6081 13:21:50.668864 Vdram = 0
6082 13:21:50.671631 Vddq = 0
6083 13:21:50.671710 Vmddr = 0
6084 13:21:50.675198 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6085 13:21:50.681961 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6086 13:21:50.685066 MEM_TYPE=3, freq_sel=20
6087 13:21:50.688559 sv_algorithm_assistance_LP4_800
6088 13:21:50.691694 ============ PULL DRAM RESETB DOWN ============
6089 13:21:50.695053 ========== PULL DRAM RESETB DOWN end =========
6090 13:21:50.698321 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6091 13:21:50.701715 ===================================
6092 13:21:50.705313 LPDDR4 DRAM CONFIGURATION
6093 13:21:50.708239 ===================================
6094 13:21:50.711755 EX_ROW_EN[0] = 0x0
6095 13:21:50.711834 EX_ROW_EN[1] = 0x0
6096 13:21:50.715559 LP4Y_EN = 0x0
6097 13:21:50.715640 WORK_FSP = 0x0
6098 13:21:50.718237 WL = 0x2
6099 13:21:50.718317 RL = 0x2
6100 13:21:50.721977 BL = 0x2
6101 13:21:50.722056 RPST = 0x0
6102 13:21:50.725322 RD_PRE = 0x0
6103 13:21:50.725402 WR_PRE = 0x1
6104 13:21:50.728922 WR_PST = 0x0
6105 13:21:50.729002 DBI_WR = 0x0
6106 13:21:50.731621 DBI_RD = 0x0
6107 13:21:50.731700 OTF = 0x1
6108 13:21:50.735241 ===================================
6109 13:21:50.738424 ===================================
6110 13:21:50.741665 ANA top config
6111 13:21:50.745474 ===================================
6112 13:21:50.748652 DLL_ASYNC_EN = 0
6113 13:21:50.748740 ALL_SLAVE_EN = 1
6114 13:21:50.751725 NEW_RANK_MODE = 1
6115 13:21:50.755718 DLL_IDLE_MODE = 1
6116 13:21:50.758614 LP45_APHY_COMB_EN = 1
6117 13:21:50.758694 TX_ODT_DIS = 1
6118 13:21:50.762345 NEW_8X_MODE = 1
6119 13:21:50.765138 ===================================
6120 13:21:50.768626 ===================================
6121 13:21:50.772072 data_rate = 800
6122 13:21:50.775125 CKR = 1
6123 13:21:50.778425 DQ_P2S_RATIO = 4
6124 13:21:50.781879 ===================================
6125 13:21:50.785345 CA_P2S_RATIO = 4
6126 13:21:50.785424 DQ_CA_OPEN = 0
6127 13:21:50.788396 DQ_SEMI_OPEN = 1
6128 13:21:50.791959 CA_SEMI_OPEN = 1
6129 13:21:50.795272 CA_FULL_RATE = 0
6130 13:21:50.798772 DQ_CKDIV4_EN = 0
6131 13:21:50.802022 CA_CKDIV4_EN = 1
6132 13:21:50.802128 CA_PREDIV_EN = 0
6133 13:21:50.805351 PH8_DLY = 0
6134 13:21:50.809040 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6135 13:21:50.811769 DQ_AAMCK_DIV = 0
6136 13:21:50.815512 CA_AAMCK_DIV = 0
6137 13:21:50.815592 CA_ADMCK_DIV = 4
6138 13:21:50.818504 DQ_TRACK_CA_EN = 0
6139 13:21:50.821884 CA_PICK = 800
6140 13:21:50.825360 CA_MCKIO = 400
6141 13:21:50.828534 MCKIO_SEMI = 400
6142 13:21:50.832338 PLL_FREQ = 3016
6143 13:21:50.835927 DQ_UI_PI_RATIO = 32
6144 13:21:50.838736 CA_UI_PI_RATIO = 32
6145 13:21:50.842023 ===================================
6146 13:21:50.842104 ===================================
6147 13:21:50.845580 memory_type:LPDDR4
6148 13:21:50.848975 GP_NUM : 10
6149 13:21:50.849055 SRAM_EN : 1
6150 13:21:50.852022 MD32_EN : 0
6151 13:21:50.855643 ===================================
6152 13:21:50.859010 [ANA_INIT] >>>>>>>>>>>>>>
6153 13:21:50.862059 <<<<<< [CONFIGURE PHASE]: ANA_TX
6154 13:21:50.865633 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6155 13:21:50.868935 ===================================
6156 13:21:50.869015 data_rate = 800,PCW = 0X7400
6157 13:21:50.872228 ===================================
6158 13:21:50.875681 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6159 13:21:50.882029 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6160 13:21:50.892262 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6161 13:21:50.898863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6162 13:21:50.902349 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6163 13:21:50.905343 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6164 13:21:50.908550 [ANA_INIT] flow start
6165 13:21:50.908678 [ANA_INIT] PLL >>>>>>>>
6166 13:21:50.912253 [ANA_INIT] PLL <<<<<<<<
6167 13:21:50.915698 [ANA_INIT] MIDPI >>>>>>>>
6168 13:21:50.915778 [ANA_INIT] MIDPI <<<<<<<<
6169 13:21:50.918774 [ANA_INIT] DLL >>>>>>>>
6170 13:21:50.922366 [ANA_INIT] flow end
6171 13:21:50.925384 ============ LP4 DIFF to SE enter ============
6172 13:21:50.929081 ============ LP4 DIFF to SE exit ============
6173 13:21:50.932367 [ANA_INIT] <<<<<<<<<<<<<
6174 13:21:50.936134 [Flow] Enable top DCM control >>>>>
6175 13:21:50.939322 [Flow] Enable top DCM control <<<<<
6176 13:21:50.942166 Enable DLL master slave shuffle
6177 13:21:50.945983 ==============================================================
6178 13:21:50.949516 Gating Mode config
6179 13:21:50.952222 ==============================================================
6180 13:21:50.956076 Config description:
6181 13:21:50.965780 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6182 13:21:50.972921 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6183 13:21:50.975956 SELPH_MODE 0: By rank 1: By Phase
6184 13:21:50.982124 ==============================================================
6185 13:21:50.985639 GAT_TRACK_EN = 0
6186 13:21:50.989272 RX_GATING_MODE = 2
6187 13:21:50.992466 RX_GATING_TRACK_MODE = 2
6188 13:21:50.996094 SELPH_MODE = 1
6189 13:21:50.996176 PICG_EARLY_EN = 1
6190 13:21:50.999131 VALID_LAT_VALUE = 1
6191 13:21:51.005796 ==============================================================
6192 13:21:51.009103 Enter into Gating configuration >>>>
6193 13:21:51.012819 Exit from Gating configuration <<<<
6194 13:21:51.015950 Enter into DVFS_PRE_config >>>>>
6195 13:21:51.025923 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6196 13:21:51.029089 Exit from DVFS_PRE_config <<<<<
6197 13:21:51.032557 Enter into PICG configuration >>>>
6198 13:21:51.035816 Exit from PICG configuration <<<<
6199 13:21:51.039147 [RX_INPUT] configuration >>>>>
6200 13:21:51.042372 [RX_INPUT] configuration <<<<<
6201 13:21:51.046100 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6202 13:21:51.052597 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6203 13:21:51.059198 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6204 13:21:51.066014 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6205 13:21:51.069353 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6206 13:21:51.075925 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6207 13:21:51.079144 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6208 13:21:51.085890 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6209 13:21:51.089305 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6210 13:21:51.092686 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6211 13:21:51.096429 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6212 13:21:51.102746 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6213 13:21:51.106131 ===================================
6214 13:21:51.106214 LPDDR4 DRAM CONFIGURATION
6215 13:21:51.109393 ===================================
6216 13:21:51.113312 EX_ROW_EN[0] = 0x0
6217 13:21:51.116022 EX_ROW_EN[1] = 0x0
6218 13:21:51.116103 LP4Y_EN = 0x0
6219 13:21:51.119547 WORK_FSP = 0x0
6220 13:21:51.119628 WL = 0x2
6221 13:21:51.122863 RL = 0x2
6222 13:21:51.122945 BL = 0x2
6223 13:21:51.125960 RPST = 0x0
6224 13:21:51.126048 RD_PRE = 0x0
6225 13:21:51.129684 WR_PRE = 0x1
6226 13:21:51.129765 WR_PST = 0x0
6227 13:21:51.132973 DBI_WR = 0x0
6228 13:21:51.133054 DBI_RD = 0x0
6229 13:21:51.136253 OTF = 0x1
6230 13:21:51.139572 ===================================
6231 13:21:51.143040 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6232 13:21:51.146241 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6233 13:21:51.153065 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6234 13:21:51.156655 ===================================
6235 13:21:51.156760 LPDDR4 DRAM CONFIGURATION
6236 13:21:51.159570 ===================================
6237 13:21:51.162630 EX_ROW_EN[0] = 0x10
6238 13:21:51.162712 EX_ROW_EN[1] = 0x0
6239 13:21:51.166284 LP4Y_EN = 0x0
6240 13:21:51.166366 WORK_FSP = 0x0
6241 13:21:51.169294 WL = 0x2
6242 13:21:51.172619 RL = 0x2
6243 13:21:51.172726 BL = 0x2
6244 13:21:51.176025 RPST = 0x0
6245 13:21:51.176106 RD_PRE = 0x0
6246 13:21:51.179510 WR_PRE = 0x1
6247 13:21:51.179592 WR_PST = 0x0
6248 13:21:51.183197 DBI_WR = 0x0
6249 13:21:51.183279 DBI_RD = 0x0
6250 13:21:51.186266 OTF = 0x1
6251 13:21:51.189345 ===================================
6252 13:21:51.192838 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6253 13:21:51.198284 nWR fixed to 30
6254 13:21:51.201932 [ModeRegInit_LP4] CH0 RK0
6255 13:21:51.202014 [ModeRegInit_LP4] CH0 RK1
6256 13:21:51.204783 [ModeRegInit_LP4] CH1 RK0
6257 13:21:51.208168 [ModeRegInit_LP4] CH1 RK1
6258 13:21:51.208250 match AC timing 19
6259 13:21:51.214862 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6260 13:21:51.218210 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6261 13:21:51.221664 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6262 13:21:51.228475 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6263 13:21:51.231663 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6264 13:21:51.231744 ==
6265 13:21:51.235142 Dram Type= 6, Freq= 0, CH_0, rank 0
6266 13:21:51.238544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6267 13:21:51.238626 ==
6268 13:21:51.245501 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6269 13:21:51.251758 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6270 13:21:51.255156 [CA 0] Center 36 (8~64) winsize 57
6271 13:21:51.255262 [CA 1] Center 36 (8~64) winsize 57
6272 13:21:51.258465 [CA 2] Center 36 (8~64) winsize 57
6273 13:21:51.262214 [CA 3] Center 36 (8~64) winsize 57
6274 13:21:51.265481 [CA 4] Center 36 (8~64) winsize 57
6275 13:21:51.268529 [CA 5] Center 36 (8~64) winsize 57
6276 13:21:51.268635
6277 13:21:51.271964 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6278 13:21:51.272045
6279 13:21:51.275368 [CATrainingPosCal] consider 1 rank data
6280 13:21:51.278877 u2DelayCellTimex100 = 270/100 ps
6281 13:21:51.282005 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 13:21:51.285327 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 13:21:51.291824 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 13:21:51.295025 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 13:21:51.298331 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 13:21:51.302087 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 13:21:51.302172
6288 13:21:51.305315 CA PerBit enable=1, Macro0, CA PI delay=36
6289 13:21:51.305396
6290 13:21:51.308562 [CBTSetCACLKResult] CA Dly = 36
6291 13:21:51.308644 CS Dly: 1 (0~32)
6292 13:21:51.311909 ==
6293 13:21:51.315088 Dram Type= 6, Freq= 0, CH_0, rank 1
6294 13:21:51.318268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 13:21:51.318348 ==
6296 13:21:51.322010 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6297 13:21:51.328316 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6298 13:21:51.331876 [CA 0] Center 36 (8~64) winsize 57
6299 13:21:51.334912 [CA 1] Center 36 (8~64) winsize 57
6300 13:21:51.338437 [CA 2] Center 36 (8~64) winsize 57
6301 13:21:51.342267 [CA 3] Center 36 (8~64) winsize 57
6302 13:21:51.345289 [CA 4] Center 36 (8~64) winsize 57
6303 13:21:51.348618 [CA 5] Center 36 (8~64) winsize 57
6304 13:21:51.348707
6305 13:21:51.352043 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6306 13:21:51.352122
6307 13:21:51.354995 [CATrainingPosCal] consider 2 rank data
6308 13:21:51.358391 u2DelayCellTimex100 = 270/100 ps
6309 13:21:51.361969 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 13:21:51.365051 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 13:21:51.368356 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 13:21:51.371706 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 13:21:51.374977 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 13:21:51.378552 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 13:21:51.382047
6316 13:21:51.385633 CA PerBit enable=1, Macro0, CA PI delay=36
6317 13:21:51.385713
6318 13:21:51.388939 [CBTSetCACLKResult] CA Dly = 36
6319 13:21:51.389019 CS Dly: 1 (0~32)
6320 13:21:51.389082
6321 13:21:51.391909 ----->DramcWriteLeveling(PI) begin...
6322 13:21:51.391990 ==
6323 13:21:51.395240 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 13:21:51.398850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 13:21:51.398930 ==
6326 13:21:51.401641 Write leveling (Byte 0): 40 => 8
6327 13:21:51.405254 Write leveling (Byte 1): 32 => 0
6328 13:21:51.408762 DramcWriteLeveling(PI) end<-----
6329 13:21:51.408842
6330 13:21:51.408906 ==
6331 13:21:51.411940 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 13:21:51.415245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 13:21:51.418495 ==
6334 13:21:51.418575 [Gating] SW mode calibration
6335 13:21:51.425218 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6336 13:21:51.431896 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6337 13:21:51.435274 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6338 13:21:51.442160 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6339 13:21:51.445194 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6340 13:21:51.448747 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6341 13:21:51.455791 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 13:21:51.459136 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 13:21:51.462065 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6344 13:21:51.465535 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6345 13:21:51.472375 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6346 13:21:51.475562 Total UI for P1: 0, mck2ui 16
6347 13:21:51.478888 best dqsien dly found for B0: ( 0, 14, 24)
6348 13:21:51.482075 Total UI for P1: 0, mck2ui 16
6349 13:21:51.486736 best dqsien dly found for B1: ( 0, 14, 24)
6350 13:21:51.489381 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6351 13:21:51.492555 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6352 13:21:51.492634
6353 13:21:51.495634 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6354 13:21:51.498811 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6355 13:21:51.503106 [Gating] SW calibration Done
6356 13:21:51.503184 ==
6357 13:21:51.505853 Dram Type= 6, Freq= 0, CH_0, rank 0
6358 13:21:51.508895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6359 13:21:51.508975 ==
6360 13:21:51.512430 RX Vref Scan: 0
6361 13:21:51.512509
6362 13:21:51.512571 RX Vref 0 -> 0, step: 1
6363 13:21:51.512629
6364 13:21:51.515712 RX Delay -410 -> 252, step: 16
6365 13:21:51.522483 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6366 13:21:51.525709 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6367 13:21:51.529540 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6368 13:21:51.532575 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6369 13:21:51.539432 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6370 13:21:51.542243 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6371 13:21:51.545861 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6372 13:21:51.549162 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6373 13:21:51.555928 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6374 13:21:51.559361 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6375 13:21:51.562504 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6376 13:21:51.565977 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6377 13:21:51.572575 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6378 13:21:51.576023 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6379 13:21:51.579147 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6380 13:21:51.582712 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6381 13:21:51.582791 ==
6382 13:21:51.585903 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 13:21:51.592774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 13:21:51.592855 ==
6385 13:21:51.592919 DQS Delay:
6386 13:21:51.595912 DQS0 = 35, DQS1 = 51
6387 13:21:51.595992 DQM Delay:
6388 13:21:51.596055 DQM0 = 7, DQM1 = 10
6389 13:21:51.599351 DQ Delay:
6390 13:21:51.602564 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6391 13:21:51.602644 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6392 13:21:51.606153 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6393 13:21:51.609602 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6394 13:21:51.609682
6395 13:21:51.612646
6396 13:21:51.612763 ==
6397 13:21:51.616621 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 13:21:51.619396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 13:21:51.619477 ==
6400 13:21:51.619540
6401 13:21:51.619598
6402 13:21:51.622996 TX Vref Scan disable
6403 13:21:51.623076 == TX Byte 0 ==
6404 13:21:51.626153 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6405 13:21:51.632774 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6406 13:21:51.632854 == TX Byte 1 ==
6407 13:21:51.636226 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6408 13:21:51.643223 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6409 13:21:51.643305 ==
6410 13:21:51.646223 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 13:21:51.649658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 13:21:51.649741 ==
6413 13:21:51.649825
6414 13:21:51.649904
6415 13:21:51.653036 TX Vref Scan disable
6416 13:21:51.653117 == TX Byte 0 ==
6417 13:21:51.656840 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6418 13:21:51.662579 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6419 13:21:51.662661 == TX Byte 1 ==
6420 13:21:51.665821 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6421 13:21:51.672966 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6422 13:21:51.673054
6423 13:21:51.673137 [DATLAT]
6424 13:21:51.673216 Freq=400, CH0 RK0
6425 13:21:51.676502
6426 13:21:51.676608 DATLAT Default: 0xf
6427 13:21:51.679227 0, 0xFFFF, sum = 0
6428 13:21:51.679310 1, 0xFFFF, sum = 0
6429 13:21:51.682699 2, 0xFFFF, sum = 0
6430 13:21:51.682780 3, 0xFFFF, sum = 0
6431 13:21:51.685857 4, 0xFFFF, sum = 0
6432 13:21:51.685955 5, 0xFFFF, sum = 0
6433 13:21:51.689869 6, 0xFFFF, sum = 0
6434 13:21:51.689951 7, 0xFFFF, sum = 0
6435 13:21:51.692694 8, 0xFFFF, sum = 0
6436 13:21:51.692789 9, 0xFFFF, sum = 0
6437 13:21:51.696236 10, 0xFFFF, sum = 0
6438 13:21:51.696344 11, 0xFFFF, sum = 0
6439 13:21:51.699298 12, 0xFFFF, sum = 0
6440 13:21:51.699379 13, 0x0, sum = 1
6441 13:21:51.702639 14, 0x0, sum = 2
6442 13:21:51.702720 15, 0x0, sum = 3
6443 13:21:51.705957 16, 0x0, sum = 4
6444 13:21:51.706038 best_step = 14
6445 13:21:51.706101
6446 13:21:51.706159 ==
6447 13:21:51.709512 Dram Type= 6, Freq= 0, CH_0, rank 0
6448 13:21:51.713041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 13:21:51.716273 ==
6450 13:21:51.716356 RX Vref Scan: 1
6451 13:21:51.716420
6452 13:21:51.719530 RX Vref 0 -> 0, step: 1
6453 13:21:51.719609
6454 13:21:51.722878 RX Delay -343 -> 252, step: 8
6455 13:21:51.722958
6456 13:21:51.726322 Set Vref, RX VrefLevel [Byte0]: 53
6457 13:21:51.729556 [Byte1]: 53
6458 13:21:51.729636
6459 13:21:51.732679 Final RX Vref Byte 0 = 53 to rank0
6460 13:21:51.736003 Final RX Vref Byte 1 = 53 to rank0
6461 13:21:51.739623 Final RX Vref Byte 0 = 53 to rank1
6462 13:21:51.742846 Final RX Vref Byte 1 = 53 to rank1==
6463 13:21:51.746483 Dram Type= 6, Freq= 0, CH_0, rank 0
6464 13:21:51.749599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 13:21:51.749678 ==
6466 13:21:51.753419 DQS Delay:
6467 13:21:51.753499 DQS0 = 44, DQS1 = 60
6468 13:21:51.756201 DQM Delay:
6469 13:21:51.756281 DQM0 = 11, DQM1 = 14
6470 13:21:51.756343 DQ Delay:
6471 13:21:51.759526 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6472 13:21:51.762779 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6473 13:21:51.766186 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =12
6474 13:21:51.769556 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6475 13:21:51.769636
6476 13:21:51.769698
6477 13:21:51.779462 [DQSOSCAuto] RK0, (LSB)MR18= 0x8654, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6478 13:21:51.779544 CH0 RK0: MR19=C0C, MR18=8654
6479 13:21:51.786239 CH0_RK0: MR19=0xC0C, MR18=0x8654, DQSOSC=393, MR23=63, INC=382, DEC=254
6480 13:21:51.786319 ==
6481 13:21:51.789524 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 13:21:51.796643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 13:21:51.796766 ==
6484 13:21:51.799871 [Gating] SW mode calibration
6485 13:21:51.806078 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6486 13:21:51.809636 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6487 13:21:51.816387 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6488 13:21:51.819901 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6489 13:21:51.822700 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6490 13:21:51.829863 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6491 13:21:51.832716 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 13:21:51.836350 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 13:21:51.839943 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6494 13:21:51.845985 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6495 13:21:51.849523 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6496 13:21:51.853062 Total UI for P1: 0, mck2ui 16
6497 13:21:51.856224 best dqsien dly found for B0: ( 0, 14, 24)
6498 13:21:51.859515 Total UI for P1: 0, mck2ui 16
6499 13:21:51.863229 best dqsien dly found for B1: ( 0, 14, 24)
6500 13:21:51.866031 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6501 13:21:51.869481 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6502 13:21:51.869562
6503 13:21:51.872922 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6504 13:21:51.876230 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6505 13:21:51.879373 [Gating] SW calibration Done
6506 13:21:51.879449 ==
6507 13:21:51.882995 Dram Type= 6, Freq= 0, CH_0, rank 1
6508 13:21:51.889373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 13:21:51.889455 ==
6510 13:21:51.889539 RX Vref Scan: 0
6511 13:21:51.889618
6512 13:21:51.892942 RX Vref 0 -> 0, step: 1
6513 13:21:51.893023
6514 13:21:51.895959 RX Delay -410 -> 252, step: 16
6515 13:21:51.899669 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6516 13:21:51.902643 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6517 13:21:51.906288 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6518 13:21:51.912603 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6519 13:21:51.915939 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6520 13:21:51.919293 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6521 13:21:51.922938 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6522 13:21:51.929518 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6523 13:21:51.932616 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6524 13:21:51.935980 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6525 13:21:51.939269 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6526 13:21:51.946407 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6527 13:21:51.949340 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6528 13:21:51.952624 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6529 13:21:51.956316 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6530 13:21:51.962791 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6531 13:21:51.962872 ==
6532 13:21:51.966748 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 13:21:51.969934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 13:21:51.970017 ==
6535 13:21:51.970101 DQS Delay:
6536 13:21:51.973087 DQS0 = 51, DQS1 = 51
6537 13:21:51.973169 DQM Delay:
6538 13:21:51.976207 DQM0 = 21, DQM1 = 10
6539 13:21:51.976288 DQ Delay:
6540 13:21:51.979724 DQ0 =24, DQ1 =16, DQ2 =24, DQ3 =16
6541 13:21:51.983136 DQ4 =24, DQ5 =0, DQ6 =32, DQ7 =32
6542 13:21:51.986235 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6543 13:21:51.989806 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6544 13:21:51.989888
6545 13:21:51.989970
6546 13:21:51.990049 ==
6547 13:21:51.993234 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 13:21:51.996300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 13:21:51.996383 ==
6550 13:21:51.996466
6551 13:21:51.999766
6552 13:21:51.999848 TX Vref Scan disable
6553 13:21:52.003091 == TX Byte 0 ==
6554 13:21:52.006419 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6555 13:21:52.010150 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6556 13:21:52.012937 == TX Byte 1 ==
6557 13:21:52.016586 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6558 13:21:52.019693 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6559 13:21:52.019775 ==
6560 13:21:52.023366 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 13:21:52.026550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 13:21:52.026632 ==
6563 13:21:52.026716
6564 13:21:52.029877
6565 13:21:52.029959 TX Vref Scan disable
6566 13:21:52.033295 == TX Byte 0 ==
6567 13:21:52.036233 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6568 13:21:52.039634 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6569 13:21:52.043245 == TX Byte 1 ==
6570 13:21:52.046599 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6571 13:21:52.049634 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6572 13:21:52.049715
6573 13:21:52.049799 [DATLAT]
6574 13:21:52.053295 Freq=400, CH0 RK1
6575 13:21:52.053377
6576 13:21:52.053460 DATLAT Default: 0xe
6577 13:21:52.056262 0, 0xFFFF, sum = 0
6578 13:21:52.056346 1, 0xFFFF, sum = 0
6579 13:21:52.060131 2, 0xFFFF, sum = 0
6580 13:21:52.060214 3, 0xFFFF, sum = 0
6581 13:21:52.063167 4, 0xFFFF, sum = 0
6582 13:21:52.063250 5, 0xFFFF, sum = 0
6583 13:21:52.066617 6, 0xFFFF, sum = 0
6584 13:21:52.069616 7, 0xFFFF, sum = 0
6585 13:21:52.069698 8, 0xFFFF, sum = 0
6586 13:21:52.072937 9, 0xFFFF, sum = 0
6587 13:21:52.073021 10, 0xFFFF, sum = 0
6588 13:21:52.076325 11, 0xFFFF, sum = 0
6589 13:21:52.076407 12, 0xFFFF, sum = 0
6590 13:21:52.079536 13, 0x0, sum = 1
6591 13:21:52.079618 14, 0x0, sum = 2
6592 13:21:52.083002 15, 0x0, sum = 3
6593 13:21:52.083085 16, 0x0, sum = 4
6594 13:21:52.083169 best_step = 14
6595 13:21:52.086703
6596 13:21:52.086784 ==
6597 13:21:52.089727 Dram Type= 6, Freq= 0, CH_0, rank 1
6598 13:21:52.093268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6599 13:21:52.093350 ==
6600 13:21:52.093433 RX Vref Scan: 0
6601 13:21:52.093512
6602 13:21:52.096459 RX Vref 0 -> 0, step: 1
6603 13:21:52.096541
6604 13:21:52.099592 RX Delay -343 -> 252, step: 8
6605 13:21:52.106672 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6606 13:21:52.110168 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6607 13:21:52.113800 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6608 13:21:52.116919 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6609 13:21:52.123987 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6610 13:21:52.126829 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6611 13:21:52.130600 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6612 13:21:52.133701 iDelay=217, Bit 7, Center -24 (-263 ~ 216) 480
6613 13:21:52.140225 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6614 13:21:52.143607 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6615 13:21:52.146985 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6616 13:21:52.150035 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6617 13:21:52.156841 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6618 13:21:52.160442 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6619 13:21:52.163418 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6620 13:21:52.170265 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6621 13:21:52.170346 ==
6622 13:21:52.173736 Dram Type= 6, Freq= 0, CH_0, rank 1
6623 13:21:52.176572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 13:21:52.176655 ==
6625 13:21:52.176776 DQS Delay:
6626 13:21:52.180228 DQS0 = 48, DQS1 = 60
6627 13:21:52.180310 DQM Delay:
6628 13:21:52.183662 DQM0 = 13, DQM1 = 13
6629 13:21:52.183744 DQ Delay:
6630 13:21:52.186944 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6631 13:21:52.190290 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =24
6632 13:21:52.193828 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6633 13:21:52.197260 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6634 13:21:52.197342
6635 13:21:52.197425
6636 13:21:52.203791 [DQSOSCAuto] RK1, (LSB)MR18= 0x976a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6637 13:21:52.207135 CH0 RK1: MR19=C0C, MR18=976A
6638 13:21:52.213609 CH0_RK1: MR19=0xC0C, MR18=0x976A, DQSOSC=390, MR23=63, INC=388, DEC=258
6639 13:21:52.217056 [RxdqsGatingPostProcess] freq 400
6640 13:21:52.220596 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6641 13:21:52.223643 best DQS0 dly(2T, 0.5T) = (0, 10)
6642 13:21:52.226776 best DQS1 dly(2T, 0.5T) = (0, 10)
6643 13:21:52.230024 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6644 13:21:52.233681 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6645 13:21:52.236660 best DQS0 dly(2T, 0.5T) = (0, 10)
6646 13:21:52.240470 best DQS1 dly(2T, 0.5T) = (0, 10)
6647 13:21:52.243667 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6648 13:21:52.247076 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6649 13:21:52.250095 Pre-setting of DQS Precalculation
6650 13:21:52.253614 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6651 13:21:52.253693 ==
6652 13:21:52.257016 Dram Type= 6, Freq= 0, CH_1, rank 0
6653 13:21:52.263857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 13:21:52.263938 ==
6655 13:21:52.267111 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6656 13:21:52.273791 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6657 13:21:52.276599 [CA 0] Center 36 (8~64) winsize 57
6658 13:21:52.280101 [CA 1] Center 36 (8~64) winsize 57
6659 13:21:52.283475 [CA 2] Center 36 (8~64) winsize 57
6660 13:21:52.287087 [CA 3] Center 36 (8~64) winsize 57
6661 13:21:52.290146 [CA 4] Center 36 (8~64) winsize 57
6662 13:21:52.293876 [CA 5] Center 36 (8~64) winsize 57
6663 13:21:52.293956
6664 13:21:52.297194 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6665 13:21:52.297275
6666 13:21:52.300104 [CATrainingPosCal] consider 1 rank data
6667 13:21:52.303798 u2DelayCellTimex100 = 270/100 ps
6668 13:21:52.306755 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 13:21:52.310153 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 13:21:52.313651 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 13:21:52.317004 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 13:21:52.320581 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 13:21:52.323829 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 13:21:52.323909
6675 13:21:52.330444 CA PerBit enable=1, Macro0, CA PI delay=36
6676 13:21:52.330524
6677 13:21:52.330588 [CBTSetCACLKResult] CA Dly = 36
6678 13:21:52.333671 CS Dly: 1 (0~32)
6679 13:21:52.333750 ==
6680 13:21:52.337193 Dram Type= 6, Freq= 0, CH_1, rank 1
6681 13:21:52.340622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 13:21:52.340712 ==
6683 13:21:52.347136 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6684 13:21:52.353587 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6685 13:21:52.357134 [CA 0] Center 36 (8~64) winsize 57
6686 13:21:52.360356 [CA 1] Center 36 (8~64) winsize 57
6687 13:21:52.363937 [CA 2] Center 36 (8~64) winsize 57
6688 13:21:52.364017 [CA 3] Center 36 (8~64) winsize 57
6689 13:21:52.367067 [CA 4] Center 36 (8~64) winsize 57
6690 13:21:52.370409 [CA 5] Center 36 (8~64) winsize 57
6691 13:21:52.370488
6692 13:21:52.373749 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6693 13:21:52.377357
6694 13:21:52.380258 [CATrainingPosCal] consider 2 rank data
6695 13:21:52.380341 u2DelayCellTimex100 = 270/100 ps
6696 13:21:52.386925 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 13:21:52.390904 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 13:21:52.393817 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 13:21:52.397324 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 13:21:52.400638 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 13:21:52.403889 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 13:21:52.403995
6703 13:21:52.407345 CA PerBit enable=1, Macro0, CA PI delay=36
6704 13:21:52.407424
6705 13:21:52.410398 [CBTSetCACLKResult] CA Dly = 36
6706 13:21:52.410477 CS Dly: 1 (0~32)
6707 13:21:52.413803
6708 13:21:52.417884 ----->DramcWriteLeveling(PI) begin...
6709 13:21:52.417965 ==
6710 13:21:52.420817 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 13:21:52.424549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 13:21:52.424645 ==
6713 13:21:52.427324 Write leveling (Byte 0): 40 => 8
6714 13:21:52.430615 Write leveling (Byte 1): 40 => 8
6715 13:21:52.433954 DramcWriteLeveling(PI) end<-----
6716 13:21:52.434036
6717 13:21:52.434120 ==
6718 13:21:52.437750 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 13:21:52.440707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 13:21:52.440789 ==
6721 13:21:52.444396 [Gating] SW mode calibration
6722 13:21:52.450881 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6723 13:21:52.457192 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6724 13:21:52.460575 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6725 13:21:52.464319 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6726 13:21:52.467142 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6727 13:21:52.473980 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6728 13:21:52.477583 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 13:21:52.480584 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 13:21:52.487304 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6731 13:21:52.491222 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6732 13:21:52.493981 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6733 13:21:52.497600 Total UI for P1: 0, mck2ui 16
6734 13:21:52.500626 best dqsien dly found for B0: ( 0, 14, 24)
6735 13:21:52.503984 Total UI for P1: 0, mck2ui 16
6736 13:21:52.507562 best dqsien dly found for B1: ( 0, 14, 24)
6737 13:21:52.510833 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6738 13:21:52.514660 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6739 13:21:52.514766
6740 13:21:52.520711 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6741 13:21:52.524034 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6742 13:21:52.524141 [Gating] SW calibration Done
6743 13:21:52.527641 ==
6744 13:21:52.530950 Dram Type= 6, Freq= 0, CH_1, rank 0
6745 13:21:52.534247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6746 13:21:52.534327 ==
6747 13:21:52.534390 RX Vref Scan: 0
6748 13:21:52.534449
6749 13:21:52.537202 RX Vref 0 -> 0, step: 1
6750 13:21:52.537281
6751 13:21:52.540697 RX Delay -410 -> 252, step: 16
6752 13:21:52.544697 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6753 13:21:52.547350 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6754 13:21:52.554045 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6755 13:21:52.557260 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6756 13:21:52.560676 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6757 13:21:52.564285 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6758 13:21:52.570979 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6759 13:21:52.574078 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6760 13:21:52.577840 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6761 13:21:52.580803 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6762 13:21:52.587552 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6763 13:21:52.590582 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6764 13:21:52.594060 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6765 13:21:52.600802 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6766 13:21:52.603887 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6767 13:21:52.607310 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6768 13:21:52.607392 ==
6769 13:21:52.610638 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 13:21:52.613914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 13:21:52.613997 ==
6772 13:21:52.617137 DQS Delay:
6773 13:21:52.617219 DQS0 = 51, DQS1 = 59
6774 13:21:52.620618 DQM Delay:
6775 13:21:52.620745 DQM0 = 19, DQM1 = 17
6776 13:21:52.623874 DQ Delay:
6777 13:21:52.623956 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6778 13:21:52.627594 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6779 13:21:52.630681 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6780 13:21:52.633880 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6781 13:21:52.633961
6782 13:21:52.634045
6783 13:21:52.634124 ==
6784 13:21:52.637514 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 13:21:52.644187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 13:21:52.644269 ==
6787 13:21:52.644353
6788 13:21:52.644431
6789 13:21:52.644508 TX Vref Scan disable
6790 13:21:52.647755 == TX Byte 0 ==
6791 13:21:52.650779 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6792 13:21:52.654042 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6793 13:21:52.657344 == TX Byte 1 ==
6794 13:21:52.660638 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6795 13:21:52.665062 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6796 13:21:52.665143 ==
6797 13:21:52.667824 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 13:21:52.674423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 13:21:52.674505 ==
6800 13:21:52.674589
6801 13:21:52.674666
6802 13:21:52.674743 TX Vref Scan disable
6803 13:21:52.677933 == TX Byte 0 ==
6804 13:21:52.680634 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6805 13:21:52.684093 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6806 13:21:52.687668 == TX Byte 1 ==
6807 13:21:52.690746 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6808 13:21:52.694515 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6809 13:21:52.694597
6810 13:21:52.697317 [DATLAT]
6811 13:21:52.697399 Freq=400, CH1 RK0
6812 13:21:52.697483
6813 13:21:52.700572 DATLAT Default: 0xf
6814 13:21:52.700717 0, 0xFFFF, sum = 0
6815 13:21:52.704176 1, 0xFFFF, sum = 0
6816 13:21:52.704259 2, 0xFFFF, sum = 0
6817 13:21:52.707550 3, 0xFFFF, sum = 0
6818 13:21:52.707633 4, 0xFFFF, sum = 0
6819 13:21:52.711460 5, 0xFFFF, sum = 0
6820 13:21:52.711547 6, 0xFFFF, sum = 0
6821 13:21:52.714468 7, 0xFFFF, sum = 0
6822 13:21:52.714551 8, 0xFFFF, sum = 0
6823 13:21:52.717569 9, 0xFFFF, sum = 0
6824 13:21:52.717653 10, 0xFFFF, sum = 0
6825 13:21:52.721528 11, 0xFFFF, sum = 0
6826 13:21:52.721610 12, 0xFFFF, sum = 0
6827 13:21:52.724597 13, 0x0, sum = 1
6828 13:21:52.724739 14, 0x0, sum = 2
6829 13:21:52.727976 15, 0x0, sum = 3
6830 13:21:52.728059 16, 0x0, sum = 4
6831 13:21:52.730818 best_step = 14
6832 13:21:52.730900
6833 13:21:52.730983 ==
6834 13:21:52.734292 Dram Type= 6, Freq= 0, CH_1, rank 0
6835 13:21:52.737906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 13:21:52.737988 ==
6837 13:21:52.741054 RX Vref Scan: 1
6838 13:21:52.741141
6839 13:21:52.741230 RX Vref 0 -> 0, step: 1
6840 13:21:52.741313
6841 13:21:52.744404 RX Delay -359 -> 252, step: 8
6842 13:21:52.744506
6843 13:21:52.747660 Set Vref, RX VrefLevel [Byte0]: 60
6844 13:21:52.750894 [Byte1]: 51
6845 13:21:52.756140
6846 13:21:52.756249 Final RX Vref Byte 0 = 60 to rank0
6847 13:21:52.759946 Final RX Vref Byte 1 = 51 to rank0
6848 13:21:52.762647 Final RX Vref Byte 0 = 60 to rank1
6849 13:21:52.766330 Final RX Vref Byte 1 = 51 to rank1==
6850 13:21:52.769382 Dram Type= 6, Freq= 0, CH_1, rank 0
6851 13:21:52.772699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 13:21:52.775854 ==
6853 13:21:52.776023 DQS Delay:
6854 13:21:52.776158 DQS0 = 52, DQS1 = 60
6855 13:21:52.779646 DQM Delay:
6856 13:21:52.779842 DQM0 = 15, DQM1 = 13
6857 13:21:52.782863 DQ Delay:
6858 13:21:52.786135 DQ0 =20, DQ1 =12, DQ2 =0, DQ3 =16
6859 13:21:52.789792 DQ4 =12, DQ5 =24, DQ6 =28, DQ7 =12
6860 13:21:52.790086 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6861 13:21:52.793061 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6862 13:21:52.793356
6863 13:21:52.795904
6864 13:21:52.802786 [DQSOSCAuto] RK0, (LSB)MR18= 0x852c, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6865 13:21:52.805974 CH1 RK0: MR19=C0C, MR18=852C
6866 13:21:52.812657 CH1_RK0: MR19=0xC0C, MR18=0x852C, DQSOSC=393, MR23=63, INC=382, DEC=254
6867 13:21:52.813131 ==
6868 13:21:52.816220 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 13:21:52.819940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 13:21:52.820541 ==
6871 13:21:52.822732 [Gating] SW mode calibration
6872 13:21:52.829173 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6873 13:21:52.836006 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6874 13:21:52.839488 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6875 13:21:52.842886 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6876 13:21:52.845998 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6877 13:21:52.852542 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6878 13:21:52.856412 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 13:21:52.859232 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 13:21:52.866202 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6881 13:21:52.869289 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6882 13:21:52.872615 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6883 13:21:52.876313 Total UI for P1: 0, mck2ui 16
6884 13:21:52.879505 best dqsien dly found for B0: ( 0, 14, 24)
6885 13:21:52.882580 Total UI for P1: 0, mck2ui 16
6886 13:21:52.886046 best dqsien dly found for B1: ( 0, 14, 24)
6887 13:21:52.888929 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6888 13:21:52.892460 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6889 13:21:52.895844
6890 13:21:52.899539 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6891 13:21:52.903016 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6892 13:21:52.906030 [Gating] SW calibration Done
6893 13:21:52.906536 ==
6894 13:21:52.909662 Dram Type= 6, Freq= 0, CH_1, rank 1
6895 13:21:52.912636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 13:21:52.913235 ==
6897 13:21:52.913736 RX Vref Scan: 0
6898 13:21:52.914200
6899 13:21:52.915846 RX Vref 0 -> 0, step: 1
6900 13:21:52.916419
6901 13:21:52.919450 RX Delay -410 -> 252, step: 16
6902 13:21:52.922864 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6903 13:21:52.929378 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6904 13:21:52.932509 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6905 13:21:52.936141 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6906 13:21:52.939188 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6907 13:21:52.946003 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6908 13:21:52.949256 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6909 13:21:52.953097 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6910 13:21:52.955774 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6911 13:21:52.959559 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6912 13:21:52.966207 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6913 13:21:52.969295 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6914 13:21:52.972613 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6915 13:21:52.979555 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6916 13:21:52.983015 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6917 13:21:52.986265 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6918 13:21:52.986716 ==
6919 13:21:52.989199 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 13:21:52.992769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 13:21:52.993187 ==
6922 13:21:52.996124 DQS Delay:
6923 13:21:52.996543 DQS0 = 43, DQS1 = 59
6924 13:21:52.999596 DQM Delay:
6925 13:21:53.000003 DQM0 = 10, DQM1 = 19
6926 13:21:53.000328 DQ Delay:
6927 13:21:53.002909 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6928 13:21:53.005996 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6929 13:21:53.009315 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6930 13:21:53.012501 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6931 13:21:53.012988
6932 13:21:53.013408
6933 13:21:53.013873 ==
6934 13:21:53.016489 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 13:21:53.022624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 13:21:53.023275 ==
6937 13:21:53.023768
6938 13:21:53.024122
6939 13:21:53.024460 TX Vref Scan disable
6940 13:21:53.026175 == TX Byte 0 ==
6941 13:21:53.029646 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6942 13:21:53.033150 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6943 13:21:53.036045 == TX Byte 1 ==
6944 13:21:53.039425 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6945 13:21:53.042935 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6946 13:21:53.043386 ==
6947 13:21:53.046340 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 13:21:53.052842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 13:21:53.053317 ==
6950 13:21:53.053686
6951 13:21:53.054033
6952 13:21:53.054366 TX Vref Scan disable
6953 13:21:53.056386 == TX Byte 0 ==
6954 13:21:53.059643 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6955 13:21:53.062886 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6956 13:21:53.066587 == TX Byte 1 ==
6957 13:21:53.069996 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6958 13:21:53.072903 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6959 13:21:53.073412
6960 13:21:53.076237 [DATLAT]
6961 13:21:53.076827 Freq=400, CH1 RK1
6962 13:21:53.077195
6963 13:21:53.080310 DATLAT Default: 0xe
6964 13:21:53.080919 0, 0xFFFF, sum = 0
6965 13:21:53.083111 1, 0xFFFF, sum = 0
6966 13:21:53.083650 2, 0xFFFF, sum = 0
6967 13:21:53.086229 3, 0xFFFF, sum = 0
6968 13:21:53.086665 4, 0xFFFF, sum = 0
6969 13:21:53.089580 5, 0xFFFF, sum = 0
6970 13:21:53.090039 6, 0xFFFF, sum = 0
6971 13:21:53.093123 7, 0xFFFF, sum = 0
6972 13:21:53.093539 8, 0xFFFF, sum = 0
6973 13:21:53.096416 9, 0xFFFF, sum = 0
6974 13:21:53.096860 10, 0xFFFF, sum = 0
6975 13:21:53.099690 11, 0xFFFF, sum = 0
6976 13:21:53.100105 12, 0xFFFF, sum = 0
6977 13:21:53.103043 13, 0x0, sum = 1
6978 13:21:53.103460 14, 0x0, sum = 2
6979 13:21:53.106147 15, 0x0, sum = 3
6980 13:21:53.106563 16, 0x0, sum = 4
6981 13:21:53.109541 best_step = 14
6982 13:21:53.109950
6983 13:21:53.110272 ==
6984 13:21:53.113056 Dram Type= 6, Freq= 0, CH_1, rank 1
6985 13:21:53.116061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6986 13:21:53.116474 ==
6987 13:21:53.119682 RX Vref Scan: 0
6988 13:21:53.120093
6989 13:21:53.120418 RX Vref 0 -> 0, step: 1
6990 13:21:53.120752
6991 13:21:53.123075 RX Delay -359 -> 252, step: 8
6992 13:21:53.130598 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6993 13:21:53.134010 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6994 13:21:53.137653 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6995 13:21:53.140783 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6996 13:21:53.147482 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6997 13:21:53.150941 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6998 13:21:53.154436 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6999 13:21:53.157377 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7000 13:21:53.163927 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7001 13:21:53.167422 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7002 13:21:53.171193 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7003 13:21:53.173993 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7004 13:21:53.180819 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
7005 13:21:53.184025 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7006 13:21:53.187310 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7007 13:21:53.193854 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7008 13:21:53.194266 ==
7009 13:21:53.197092 Dram Type= 6, Freq= 0, CH_1, rank 1
7010 13:21:53.200781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7011 13:21:53.201195 ==
7012 13:21:53.201524 DQS Delay:
7013 13:21:53.204222 DQS0 = 52, DQS1 = 56
7014 13:21:53.204635 DQM Delay:
7015 13:21:53.207679 DQM0 = 13, DQM1 = 9
7016 13:21:53.208087 DQ Delay:
7017 13:21:53.210707 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7018 13:21:53.214040 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7019 13:21:53.216947 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7020 13:21:53.220558 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
7021 13:21:53.220992
7022 13:21:53.221315
7023 13:21:53.227341 [DQSOSCAuto] RK1, (LSB)MR18= 0x7289, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
7024 13:21:53.230734 CH1 RK1: MR19=C0C, MR18=7289
7025 13:21:53.236997 CH1_RK1: MR19=0xC0C, MR18=0x7289, DQSOSC=392, MR23=63, INC=384, DEC=256
7026 13:21:53.240505 [RxdqsGatingPostProcess] freq 400
7027 13:21:53.244002 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7028 13:21:53.247293 best DQS0 dly(2T, 0.5T) = (0, 10)
7029 13:21:53.250085 best DQS1 dly(2T, 0.5T) = (0, 10)
7030 13:21:53.253759 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7031 13:21:53.257004 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7032 13:21:53.260576 best DQS0 dly(2T, 0.5T) = (0, 10)
7033 13:21:53.263923 best DQS1 dly(2T, 0.5T) = (0, 10)
7034 13:21:53.267193 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7035 13:21:53.270737 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7036 13:21:53.273880 Pre-setting of DQS Precalculation
7037 13:21:53.277087 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7038 13:21:53.287377 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7039 13:21:53.293754 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7040 13:21:53.294167
7041 13:21:53.294487
7042 13:21:53.297011 [Calibration Summary] 800 Mbps
7043 13:21:53.297422 CH 0, Rank 0
7044 13:21:53.300313 SW Impedance : PASS
7045 13:21:53.300747 DUTY Scan : NO K
7046 13:21:53.303949 ZQ Calibration : PASS
7047 13:21:53.307041 Jitter Meter : NO K
7048 13:21:53.307452 CBT Training : PASS
7049 13:21:53.310582 Write leveling : PASS
7050 13:21:53.313685 RX DQS gating : PASS
7051 13:21:53.314094 RX DQ/DQS(RDDQC) : PASS
7052 13:21:53.317247 TX DQ/DQS : PASS
7053 13:21:53.320451 RX DATLAT : PASS
7054 13:21:53.320897 RX DQ/DQS(Engine): PASS
7055 13:21:53.323858 TX OE : NO K
7056 13:21:53.324267 All Pass.
7057 13:21:53.324592
7058 13:21:53.324928 CH 0, Rank 1
7059 13:21:53.326959 SW Impedance : PASS
7060 13:21:53.330614 DUTY Scan : NO K
7061 13:21:53.331027 ZQ Calibration : PASS
7062 13:21:53.334013 Jitter Meter : NO K
7063 13:21:53.337111 CBT Training : PASS
7064 13:21:53.337522 Write leveling : NO K
7065 13:21:53.341050 RX DQS gating : PASS
7066 13:21:53.343800 RX DQ/DQS(RDDQC) : PASS
7067 13:21:53.344212 TX DQ/DQS : PASS
7068 13:21:53.347066 RX DATLAT : PASS
7069 13:21:53.350410 RX DQ/DQS(Engine): PASS
7070 13:21:53.350820 TX OE : NO K
7071 13:21:53.351146 All Pass.
7072 13:21:53.353799
7073 13:21:53.354206 CH 1, Rank 0
7074 13:21:53.357822 SW Impedance : PASS
7075 13:21:53.358234 DUTY Scan : NO K
7076 13:21:53.360653 ZQ Calibration : PASS
7077 13:21:53.363961 Jitter Meter : NO K
7078 13:21:53.364490 CBT Training : PASS
7079 13:21:53.367240 Write leveling : PASS
7080 13:21:53.367630 RX DQS gating : PASS
7081 13:21:53.370685 RX DQ/DQS(RDDQC) : PASS
7082 13:21:53.374057 TX DQ/DQS : PASS
7083 13:21:53.374441 RX DATLAT : PASS
7084 13:21:53.377195 RX DQ/DQS(Engine): PASS
7085 13:21:53.380719 TX OE : NO K
7086 13:21:53.381169 All Pass.
7087 13:21:53.381655
7088 13:21:53.382094 CH 1, Rank 1
7089 13:21:53.384445 SW Impedance : PASS
7090 13:21:53.387688 DUTY Scan : NO K
7091 13:21:53.388128 ZQ Calibration : PASS
7092 13:21:53.390837 Jitter Meter : NO K
7093 13:21:53.394295 CBT Training : PASS
7094 13:21:53.394738 Write leveling : NO K
7095 13:21:53.397256 RX DQS gating : PASS
7096 13:21:53.401003 RX DQ/DQS(RDDQC) : PASS
7097 13:21:53.401436 TX DQ/DQS : PASS
7098 13:21:53.404009 RX DATLAT : PASS
7099 13:21:53.404437 RX DQ/DQS(Engine): PASS
7100 13:21:53.407535 TX OE : NO K
7101 13:21:53.407966 All Pass.
7102 13:21:53.408318
7103 13:21:53.410980 DramC Write-DBI off
7104 13:21:53.414324 PER_BANK_REFRESH: Hybrid Mode
7105 13:21:53.414758 TX_TRACKING: ON
7106 13:21:53.424079 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7107 13:21:53.427548 [FAST_K] Save calibration result to emmc
7108 13:21:53.430803 dramc_set_vcore_voltage set vcore to 725000
7109 13:21:53.434219 Read voltage for 1600, 0
7110 13:21:53.434649 Vio18 = 0
7111 13:21:53.435000 Vcore = 725000
7112 13:21:53.437198 Vdram = 0
7113 13:21:53.437627 Vddq = 0
7114 13:21:53.437980 Vmddr = 0
7115 13:21:53.444549 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7116 13:21:53.447866 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7117 13:21:53.450622 MEM_TYPE=3, freq_sel=13
7118 13:21:53.454156 sv_algorithm_assistance_LP4_3733
7119 13:21:53.457405 ============ PULL DRAM RESETB DOWN ============
7120 13:21:53.461158 ========== PULL DRAM RESETB DOWN end =========
7121 13:21:53.467505 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7122 13:21:53.471034 ===================================
7123 13:21:53.474323 LPDDR4 DRAM CONFIGURATION
7124 13:21:53.477444 ===================================
7125 13:21:53.477970 EX_ROW_EN[0] = 0x0
7126 13:21:53.480949 EX_ROW_EN[1] = 0x0
7127 13:21:53.481509 LP4Y_EN = 0x0
7128 13:21:53.484535 WORK_FSP = 0x1
7129 13:21:53.485091 WL = 0x5
7130 13:21:53.487768 RL = 0x5
7131 13:21:53.488197 BL = 0x2
7132 13:21:53.490944 RPST = 0x0
7133 13:21:53.491486 RD_PRE = 0x0
7134 13:21:53.494319 WR_PRE = 0x1
7135 13:21:53.494758 WR_PST = 0x1
7136 13:21:53.498130 DBI_WR = 0x0
7137 13:21:53.498562 DBI_RD = 0x0
7138 13:21:53.500832 OTF = 0x1
7139 13:21:53.504260 ===================================
7140 13:21:53.508249 ===================================
7141 13:21:53.508793 ANA top config
7142 13:21:53.511038 ===================================
7143 13:21:53.514441 DLL_ASYNC_EN = 0
7144 13:21:53.517899 ALL_SLAVE_EN = 0
7145 13:21:53.520975 NEW_RANK_MODE = 1
7146 13:21:53.521418 DLL_IDLE_MODE = 1
7147 13:21:53.524809 LP45_APHY_COMB_EN = 1
7148 13:21:53.527987 TX_ODT_DIS = 0
7149 13:21:53.530914 NEW_8X_MODE = 1
7150 13:21:53.534509 ===================================
7151 13:21:53.538300 ===================================
7152 13:21:53.541086 data_rate = 3200
7153 13:21:53.541541 CKR = 1
7154 13:21:53.544427 DQ_P2S_RATIO = 8
7155 13:21:53.547879 ===================================
7156 13:21:53.551361 CA_P2S_RATIO = 8
7157 13:21:53.554375 DQ_CA_OPEN = 0
7158 13:21:53.558036 DQ_SEMI_OPEN = 0
7159 13:21:53.558468 CA_SEMI_OPEN = 0
7160 13:21:53.561299 CA_FULL_RATE = 0
7161 13:21:53.564778 DQ_CKDIV4_EN = 0
7162 13:21:53.567986 CA_CKDIV4_EN = 0
7163 13:21:53.571281 CA_PREDIV_EN = 0
7164 13:21:53.574239 PH8_DLY = 12
7165 13:21:53.574834 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7166 13:21:53.577668 DQ_AAMCK_DIV = 4
7167 13:21:53.580954 CA_AAMCK_DIV = 4
7168 13:21:53.584457 CA_ADMCK_DIV = 4
7169 13:21:53.587690 DQ_TRACK_CA_EN = 0
7170 13:21:53.591079 CA_PICK = 1600
7171 13:21:53.594332 CA_MCKIO = 1600
7172 13:21:53.594929 MCKIO_SEMI = 0
7173 13:21:53.598227 PLL_FREQ = 3068
7174 13:21:53.601597 DQ_UI_PI_RATIO = 32
7175 13:21:53.604636 CA_UI_PI_RATIO = 0
7176 13:21:53.607665 ===================================
7177 13:21:53.611144 ===================================
7178 13:21:53.614900 memory_type:LPDDR4
7179 13:21:53.615334 GP_NUM : 10
7180 13:21:53.618221 SRAM_EN : 1
7181 13:21:53.618651 MD32_EN : 0
7182 13:21:53.621680 ===================================
7183 13:21:53.624705 [ANA_INIT] >>>>>>>>>>>>>>
7184 13:21:53.627991 <<<<<< [CONFIGURE PHASE]: ANA_TX
7185 13:21:53.631302 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7186 13:21:53.634562 ===================================
7187 13:21:53.637864 data_rate = 3200,PCW = 0X7600
7188 13:21:53.641534 ===================================
7189 13:21:53.644415 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7190 13:21:53.647845 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7191 13:21:53.654603 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7192 13:21:53.658071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7193 13:21:53.664565 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7194 13:21:53.668046 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7195 13:21:53.668530 [ANA_INIT] flow start
7196 13:21:53.671308 [ANA_INIT] PLL >>>>>>>>
7197 13:21:53.671741 [ANA_INIT] PLL <<<<<<<<
7198 13:21:53.674509 [ANA_INIT] MIDPI >>>>>>>>
7199 13:21:53.678273 [ANA_INIT] MIDPI <<<<<<<<
7200 13:21:53.681698 [ANA_INIT] DLL >>>>>>>>
7201 13:21:53.682282 [ANA_INIT] DLL <<<<<<<<
7202 13:21:53.684703 [ANA_INIT] flow end
7203 13:21:53.688463 ============ LP4 DIFF to SE enter ============
7204 13:21:53.691343 ============ LP4 DIFF to SE exit ============
7205 13:21:53.694761 [ANA_INIT] <<<<<<<<<<<<<
7206 13:21:53.698052 [Flow] Enable top DCM control >>>>>
7207 13:21:53.701650 [Flow] Enable top DCM control <<<<<
7208 13:21:53.704850 Enable DLL master slave shuffle
7209 13:21:53.711562 ==============================================================
7210 13:21:53.712069 Gating Mode config
7211 13:21:53.718208 ==============================================================
7212 13:21:53.718622 Config description:
7213 13:21:53.728265 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7214 13:21:53.735082 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7215 13:21:53.741429 SELPH_MODE 0: By rank 1: By Phase
7216 13:21:53.744833 ==============================================================
7217 13:21:53.748487 GAT_TRACK_EN = 1
7218 13:21:53.751805 RX_GATING_MODE = 2
7219 13:21:53.754734 RX_GATING_TRACK_MODE = 2
7220 13:21:53.758131 SELPH_MODE = 1
7221 13:21:53.762251 PICG_EARLY_EN = 1
7222 13:21:53.765285 VALID_LAT_VALUE = 1
7223 13:21:53.768352 ==============================================================
7224 13:21:53.771676 Enter into Gating configuration >>>>
7225 13:21:53.775084 Exit from Gating configuration <<<<
7226 13:21:53.778548 Enter into DVFS_PRE_config >>>>>
7227 13:21:53.792028 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7228 13:21:53.792446 Exit from DVFS_PRE_config <<<<<
7229 13:21:53.794895 Enter into PICG configuration >>>>
7230 13:21:53.798481 Exit from PICG configuration <<<<
7231 13:21:53.801760 [RX_INPUT] configuration >>>>>
7232 13:21:53.805026 [RX_INPUT] configuration <<<<<
7233 13:21:53.811728 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7234 13:21:53.814999 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7235 13:21:53.821576 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7236 13:21:53.828922 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7237 13:21:53.835227 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7238 13:21:53.841730 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7239 13:21:53.845111 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7240 13:21:53.848603 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7241 13:21:53.851925 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7242 13:21:53.858212 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7243 13:21:53.861614 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7244 13:21:53.865365 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7245 13:21:53.868488 ===================================
7246 13:21:53.871650 LPDDR4 DRAM CONFIGURATION
7247 13:21:53.875561 ===================================
7248 13:21:53.876047 EX_ROW_EN[0] = 0x0
7249 13:21:53.878430 EX_ROW_EN[1] = 0x0
7250 13:21:53.878844 LP4Y_EN = 0x0
7251 13:21:53.881808 WORK_FSP = 0x1
7252 13:21:53.882216 WL = 0x5
7253 13:21:53.885299 RL = 0x5
7254 13:21:53.888344 BL = 0x2
7255 13:21:53.888790 RPST = 0x0
7256 13:21:53.891822 RD_PRE = 0x0
7257 13:21:53.892233 WR_PRE = 0x1
7258 13:21:53.895478 WR_PST = 0x1
7259 13:21:53.896065 DBI_WR = 0x0
7260 13:21:53.898247 DBI_RD = 0x0
7261 13:21:53.898638 OTF = 0x1
7262 13:21:53.901880 ===================================
7263 13:21:53.905448 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7264 13:21:53.911839 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7265 13:21:53.915145 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7266 13:21:53.918454 ===================================
7267 13:21:53.921974 LPDDR4 DRAM CONFIGURATION
7268 13:21:53.925428 ===================================
7269 13:21:53.925842 EX_ROW_EN[0] = 0x10
7270 13:21:53.928447 EX_ROW_EN[1] = 0x0
7271 13:21:53.928884 LP4Y_EN = 0x0
7272 13:21:53.932281 WORK_FSP = 0x1
7273 13:21:53.932730 WL = 0x5
7274 13:21:53.935199 RL = 0x5
7275 13:21:53.935608 BL = 0x2
7276 13:21:53.938676 RPST = 0x0
7277 13:21:53.939091 RD_PRE = 0x0
7278 13:21:53.941875 WR_PRE = 0x1
7279 13:21:53.942284 WR_PST = 0x1
7280 13:21:53.945654 DBI_WR = 0x0
7281 13:21:53.946062 DBI_RD = 0x0
7282 13:21:53.948372 OTF = 0x1
7283 13:21:53.951893 ===================================
7284 13:21:53.958574 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7285 13:21:53.958984 ==
7286 13:21:53.961974 Dram Type= 6, Freq= 0, CH_0, rank 0
7287 13:21:53.965372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7288 13:21:53.965789 ==
7289 13:21:53.968783 [Duty_Offset_Calibration]
7290 13:21:53.969193 B0:2 B1:-1 CA:1
7291 13:21:53.969517
7292 13:21:53.971942 [DutyScan_Calibration_Flow] k_type=0
7293 13:21:53.982119
7294 13:21:53.982532 ==CLK 0==
7295 13:21:53.985391 Final CLK duty delay cell = -4
7296 13:21:53.988924 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7297 13:21:53.992208 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7298 13:21:53.995259 [-4] AVG Duty = 4937%(X100)
7299 13:21:53.995672
7300 13:21:53.998705 CH0 CLK Duty spec in!! Max-Min= 187%
7301 13:21:54.002456 [DutyScan_Calibration_Flow] ====Done====
7302 13:21:54.002867
7303 13:21:54.005735 [DutyScan_Calibration_Flow] k_type=1
7304 13:21:54.021568
7305 13:21:54.021974 ==DQS 0 ==
7306 13:21:54.024711 Final DQS duty delay cell = 0
7307 13:21:54.028134 [0] MAX Duty = 5125%(X100), DQS PI = 20
7308 13:21:54.031691 [0] MIN Duty = 5000%(X100), DQS PI = 14
7309 13:21:54.032104 [0] AVG Duty = 5062%(X100)
7310 13:21:54.034843
7311 13:21:54.035427 ==DQS 1 ==
7312 13:21:54.038146 Final DQS duty delay cell = -4
7313 13:21:54.041520 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7314 13:21:54.045054 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7315 13:21:54.048375 [-4] AVG Duty = 5046%(X100)
7316 13:21:54.048937
7317 13:21:54.051915 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7318 13:21:54.052354
7319 13:21:54.054799 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7320 13:21:54.058412 [DutyScan_Calibration_Flow] ====Done====
7321 13:21:54.058841
7322 13:21:54.061403 [DutyScan_Calibration_Flow] k_type=3
7323 13:21:54.078926
7324 13:21:54.079358 ==DQM 0 ==
7325 13:21:54.082363 Final DQM duty delay cell = 0
7326 13:21:54.085843 [0] MAX Duty = 5000%(X100), DQS PI = 20
7327 13:21:54.089273 [0] MIN Duty = 4875%(X100), DQS PI = 4
7328 13:21:54.089703 [0] AVG Duty = 4937%(X100)
7329 13:21:54.092190
7330 13:21:54.092818 ==DQM 1 ==
7331 13:21:54.095682 Final DQM duty delay cell = 0
7332 13:21:54.099298 [0] MAX Duty = 5218%(X100), DQS PI = 58
7333 13:21:54.102556 [0] MIN Duty = 4938%(X100), DQS PI = 20
7334 13:21:54.102993 [0] AVG Duty = 5078%(X100)
7335 13:21:54.105931
7336 13:21:54.109165 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7337 13:21:54.109617
7338 13:21:54.112517 CH0 DQM 1 Duty spec in!! Max-Min= 280%
7339 13:21:54.116360 [DutyScan_Calibration_Flow] ====Done====
7340 13:21:54.116958
7341 13:21:54.119088 [DutyScan_Calibration_Flow] k_type=2
7342 13:21:54.136100
7343 13:21:54.136739 ==DQ 0 ==
7344 13:21:54.139398 Final DQ duty delay cell = 0
7345 13:21:54.142840 [0] MAX Duty = 5156%(X100), DQS PI = 0
7346 13:21:54.146613 [0] MIN Duty = 5031%(X100), DQS PI = 12
7347 13:21:54.147226 [0] AVG Duty = 5093%(X100)
7348 13:21:54.147724
7349 13:21:54.149441 ==DQ 1 ==
7350 13:21:54.152620 Final DQ duty delay cell = 0
7351 13:21:54.155952 [0] MAX Duty = 5031%(X100), DQS PI = 30
7352 13:21:54.159362 [0] MIN Duty = 4907%(X100), DQS PI = 44
7353 13:21:54.159797 [0] AVG Duty = 4969%(X100)
7354 13:21:54.160051
7355 13:21:54.162800 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7356 13:21:54.166907
7357 13:21:54.169375 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7358 13:21:54.172394 [DutyScan_Calibration_Flow] ====Done====
7359 13:21:54.172473 ==
7360 13:21:54.175668 Dram Type= 6, Freq= 0, CH_1, rank 0
7361 13:21:54.179323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7362 13:21:54.179438 ==
7363 13:21:54.182317 [Duty_Offset_Calibration]
7364 13:21:54.182389 B0:1 B1:1 CA:2
7365 13:21:54.182449
7366 13:21:54.186064 [DutyScan_Calibration_Flow] k_type=0
7367 13:21:54.195938
7368 13:21:54.196024 ==CLK 0==
7369 13:21:54.199025 Final CLK duty delay cell = 0
7370 13:21:54.202628 [0] MAX Duty = 5187%(X100), DQS PI = 24
7371 13:21:54.206026 [0] MIN Duty = 4938%(X100), DQS PI = 50
7372 13:21:54.206124 [0] AVG Duty = 5062%(X100)
7373 13:21:54.209508
7374 13:21:54.209578 CH1 CLK Duty spec in!! Max-Min= 249%
7375 13:21:54.216506 [DutyScan_Calibration_Flow] ====Done====
7376 13:21:54.216602
7377 13:21:54.219173 [DutyScan_Calibration_Flow] k_type=1
7378 13:21:54.235644
7379 13:21:54.235747 ==DQS 0 ==
7380 13:21:54.238887 Final DQS duty delay cell = 0
7381 13:21:54.242529 [0] MAX Duty = 5062%(X100), DQS PI = 22
7382 13:21:54.245809 [0] MIN Duty = 4813%(X100), DQS PI = 52
7383 13:21:54.248789 [0] AVG Duty = 4937%(X100)
7384 13:21:54.248864
7385 13:21:54.248924 ==DQS 1 ==
7386 13:21:54.252157 Final DQS duty delay cell = 0
7387 13:21:54.255707 [0] MAX Duty = 5062%(X100), DQS PI = 34
7388 13:21:54.258878 [0] MIN Duty = 4938%(X100), DQS PI = 12
7389 13:21:54.262601 [0] AVG Duty = 5000%(X100)
7390 13:21:54.262672
7391 13:21:54.265561 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7392 13:21:54.265631
7393 13:21:54.268933 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7394 13:21:54.272134 [DutyScan_Calibration_Flow] ====Done====
7395 13:21:54.272202
7396 13:21:54.275726 [DutyScan_Calibration_Flow] k_type=3
7397 13:21:54.292685
7398 13:21:54.292764 ==DQM 0 ==
7399 13:21:54.295959 Final DQM duty delay cell = 0
7400 13:21:54.299351 [0] MAX Duty = 5124%(X100), DQS PI = 18
7401 13:21:54.302687 [0] MIN Duty = 4844%(X100), DQS PI = 48
7402 13:21:54.302783 [0] AVG Duty = 4984%(X100)
7403 13:21:54.305835
7404 13:21:54.305912 ==DQM 1 ==
7405 13:21:54.309329 Final DQM duty delay cell = 0
7406 13:21:54.312977 [0] MAX Duty = 5156%(X100), DQS PI = 60
7407 13:21:54.315858 [0] MIN Duty = 4907%(X100), DQS PI = 18
7408 13:21:54.315927 [0] AVG Duty = 5031%(X100)
7409 13:21:54.319178
7410 13:21:54.322734 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7411 13:21:54.322806
7412 13:21:54.326258 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7413 13:21:54.329665 [DutyScan_Calibration_Flow] ====Done====
7414 13:21:54.329734
7415 13:21:54.332717 [DutyScan_Calibration_Flow] k_type=2
7416 13:21:54.349723
7417 13:21:54.349801 ==DQ 0 ==
7418 13:21:54.353019 Final DQ duty delay cell = 0
7419 13:21:54.356076 [0] MAX Duty = 5156%(X100), DQS PI = 20
7420 13:21:54.359550 [0] MIN Duty = 4907%(X100), DQS PI = 52
7421 13:21:54.359621 [0] AVG Duty = 5031%(X100)
7422 13:21:54.359681
7423 13:21:54.363014 ==DQ 1 ==
7424 13:21:54.366191 Final DQ duty delay cell = 0
7425 13:21:54.369813 [0] MAX Duty = 5093%(X100), DQS PI = 6
7426 13:21:54.372980 [0] MIN Duty = 5031%(X100), DQS PI = 0
7427 13:21:54.373051 [0] AVG Duty = 5062%(X100)
7428 13:21:54.373111
7429 13:21:54.376242 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7430 13:21:54.376339
7431 13:21:54.379838 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7432 13:21:54.383032 [DutyScan_Calibration_Flow] ====Done====
7433 13:21:54.388658 nWR fixed to 30
7434 13:21:54.392060 [ModeRegInit_LP4] CH0 RK0
7435 13:21:54.392131 [ModeRegInit_LP4] CH0 RK1
7436 13:21:54.395519 [ModeRegInit_LP4] CH1 RK0
7437 13:21:54.398393 [ModeRegInit_LP4] CH1 RK1
7438 13:21:54.398463 match AC timing 5
7439 13:21:54.405357 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7440 13:21:54.408302 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7441 13:21:54.411959 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7442 13:21:54.418373 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7443 13:21:54.421855 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7444 13:21:54.421928 [MiockJmeterHQA]
7445 13:21:54.421988
7446 13:21:54.425221 [DramcMiockJmeter] u1RxGatingPI = 0
7447 13:21:54.428430 0 : 4252, 4026
7448 13:21:54.428527 4 : 4252, 4027
7449 13:21:54.431915 8 : 4252, 4027
7450 13:21:54.432017 12 : 4255, 4027
7451 13:21:54.435050 16 : 4368, 4139
7452 13:21:54.435146 20 : 4252, 4027
7453 13:21:54.435240 24 : 4252, 4027
7454 13:21:54.438393 28 : 4253, 4027
7455 13:21:54.438492 32 : 4255, 4030
7456 13:21:54.441681 36 : 4252, 4027
7457 13:21:54.441759 40 : 4252, 4027
7458 13:21:54.444863 44 : 4365, 4140
7459 13:21:54.444936 48 : 4255, 4029
7460 13:21:54.445004 52 : 4254, 4029
7461 13:21:54.448445 56 : 4253, 4026
7462 13:21:54.448540 60 : 4361, 4137
7463 13:21:54.451895 64 : 4250, 4026
7464 13:21:54.451973 68 : 4361, 4137
7465 13:21:54.455351 72 : 4250, 4027
7466 13:21:54.455447 76 : 4250, 4026
7467 13:21:54.459076 80 : 4250, 4027
7468 13:21:54.459172 84 : 4252, 4029
7469 13:21:54.459260 88 : 4361, 4137
7470 13:21:54.461935 92 : 4252, 4027
7471 13:21:54.462003 96 : 4360, 3517
7472 13:21:54.465273 100 : 4250, 0
7473 13:21:54.465344 104 : 4250, 0
7474 13:21:54.468191 108 : 4250, 0
7475 13:21:54.468262 112 : 4250, 0
7476 13:21:54.468322 116 : 4250, 0
7477 13:21:54.471694 120 : 4252, 0
7478 13:21:54.471764 124 : 4250, 0
7479 13:21:54.471827 128 : 4250, 0
7480 13:21:54.475569 132 : 4252, 0
7481 13:21:54.475638 136 : 4360, 0
7482 13:21:54.478325 140 : 4361, 0
7483 13:21:54.478403 144 : 4363, 0
7484 13:21:54.478464 148 : 4250, 0
7485 13:21:54.481791 152 : 4361, 0
7486 13:21:54.481889 156 : 4250, 0
7487 13:21:54.485144 160 : 4249, 0
7488 13:21:54.485243 164 : 4253, 0
7489 13:21:54.485334 168 : 4250, 0
7490 13:21:54.488800 172 : 4252, 0
7491 13:21:54.488873 176 : 4250, 0
7492 13:21:54.488938 180 : 4250, 0
7493 13:21:54.491701 184 : 4252, 0
7494 13:21:54.491770 188 : 4360, 0
7495 13:21:54.495397 192 : 4361, 0
7496 13:21:54.495493 196 : 4363, 0
7497 13:21:54.495581 200 : 4250, 0
7498 13:21:54.498830 204 : 4360, 0
7499 13:21:54.498929 208 : 4250, 0
7500 13:21:54.502015 212 : 4249, 63
7501 13:21:54.502113 216 : 4361, 3671
7502 13:21:54.502201 220 : 4361, 4137
7503 13:21:54.505175 224 : 4249, 4027
7504 13:21:54.505244 228 : 4363, 4140
7505 13:21:54.508608 232 : 4361, 4137
7506 13:21:54.508708 236 : 4250, 4027
7507 13:21:54.511932 240 : 4250, 4027
7508 13:21:54.512000 244 : 4252, 4029
7509 13:21:54.515451 248 : 4253, 4029
7510 13:21:54.515519 252 : 4250, 4027
7511 13:21:54.518651 256 : 4250, 4027
7512 13:21:54.518747 260 : 4253, 4029
7513 13:21:54.522059 264 : 4250, 4027
7514 13:21:54.522130 268 : 4361, 4137
7515 13:21:54.525236 272 : 4361, 4137
7516 13:21:54.525311 276 : 4250, 4026
7517 13:21:54.525374 280 : 4363, 4140
7518 13:21:54.528730 284 : 4361, 4137
7519 13:21:54.528798 288 : 4250, 4026
7520 13:21:54.531906 292 : 4250, 4027
7521 13:21:54.531975 296 : 4252, 4029
7522 13:21:54.535390 300 : 4250, 4027
7523 13:21:54.535490 304 : 4250, 4026
7524 13:21:54.538884 308 : 4250, 4027
7525 13:21:54.538956 312 : 4250, 4027
7526 13:21:54.542133 316 : 4250, 4027
7527 13:21:54.542236 320 : 4361, 4137
7528 13:21:54.545295 324 : 4361, 4137
7529 13:21:54.545384 328 : 4250, 4026
7530 13:21:54.545449 332 : 4363, 3081
7531 13:21:54.548571 336 : 4361, 59
7532 13:21:54.548653
7533 13:21:54.552405 MIOCK jitter meter ch=0
7534 13:21:54.552485
7535 13:21:54.555580 1T = (336-100) = 236 dly cells
7536 13:21:54.558620 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7537 13:21:54.558700 ==
7538 13:21:54.562068 Dram Type= 6, Freq= 0, CH_0, rank 0
7539 13:21:54.568810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7540 13:21:54.568891 ==
7541 13:21:54.572136 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7542 13:21:54.575278 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7543 13:21:54.582042 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7544 13:21:54.588491 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7545 13:21:54.595935 [CA 0] Center 44 (14~75) winsize 62
7546 13:21:54.599426 [CA 1] Center 44 (14~74) winsize 61
7547 13:21:54.602614 [CA 2] Center 39 (10~68) winsize 59
7548 13:21:54.606018 [CA 3] Center 39 (10~68) winsize 59
7549 13:21:54.609497 [CA 4] Center 37 (7~67) winsize 61
7550 13:21:54.612417 [CA 5] Center 37 (7~67) winsize 61
7551 13:21:54.612497
7552 13:21:54.615925 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7553 13:21:54.616004
7554 13:21:54.619289 [CATrainingPosCal] consider 1 rank data
7555 13:21:54.622711 u2DelayCellTimex100 = 275/100 ps
7556 13:21:54.625914 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7557 13:21:54.632426 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7558 13:21:54.636139 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7559 13:21:54.639071 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7560 13:21:54.642835 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7561 13:21:54.646196 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7562 13:21:54.646277
7563 13:21:54.649335 CA PerBit enable=1, Macro0, CA PI delay=37
7564 13:21:54.649416
7565 13:21:54.652610 [CBTSetCACLKResult] CA Dly = 37
7566 13:21:54.655794 CS Dly: 10 (0~41)
7567 13:21:54.659373 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7568 13:21:54.662986 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7569 13:21:54.663085 ==
7570 13:21:54.666046 Dram Type= 6, Freq= 0, CH_0, rank 1
7571 13:21:54.669213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7572 13:21:54.672743 ==
7573 13:21:54.675893 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7574 13:21:54.679259 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7575 13:21:54.686163 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7576 13:21:54.689474 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7577 13:21:54.699837 [CA 0] Center 44 (14~75) winsize 62
7578 13:21:54.703177 [CA 1] Center 44 (14~75) winsize 62
7579 13:21:54.706203 [CA 2] Center 40 (11~69) winsize 59
7580 13:21:54.709637 [CA 3] Center 39 (10~69) winsize 60
7581 13:21:54.712991 [CA 4] Center 38 (8~68) winsize 61
7582 13:21:54.716697 [CA 5] Center 37 (7~67) winsize 61
7583 13:21:54.716777
7584 13:21:54.719371 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7585 13:21:54.719450
7586 13:21:54.722728 [CATrainingPosCal] consider 2 rank data
7587 13:21:54.726302 u2DelayCellTimex100 = 275/100 ps
7588 13:21:54.732702 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7589 13:21:54.736560 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7590 13:21:54.739511 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7591 13:21:54.742999 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7592 13:21:54.746545 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7593 13:21:54.749694 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7594 13:21:54.749786
7595 13:21:54.753074 CA PerBit enable=1, Macro0, CA PI delay=37
7596 13:21:54.753166
7597 13:21:54.756314 [CBTSetCACLKResult] CA Dly = 37
7598 13:21:54.759434 CS Dly: 11 (0~44)
7599 13:21:54.763604 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7600 13:21:54.766358 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7601 13:21:54.766476
7602 13:21:54.769867 ----->DramcWriteLeveling(PI) begin...
7603 13:21:54.770000 ==
7604 13:21:54.773080 Dram Type= 6, Freq= 0, CH_0, rank 0
7605 13:21:54.780148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7606 13:21:54.780318 ==
7607 13:21:54.782964 Write leveling (Byte 0): 32 => 32
7608 13:21:54.783203 Write leveling (Byte 1): 28 => 28
7609 13:21:54.786769 DramcWriteLeveling(PI) end<-----
7610 13:21:54.786966
7611 13:21:54.789310 ==
7612 13:21:54.789556 Dram Type= 6, Freq= 0, CH_0, rank 0
7613 13:21:54.796483 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7614 13:21:54.796810 ==
7615 13:21:54.799629 [Gating] SW mode calibration
7616 13:21:54.806174 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7617 13:21:54.809480 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7618 13:21:54.815864 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 13:21:54.819134 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 13:21:54.822721 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 13:21:54.829596 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7622 13:21:54.832830 1 4 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7623 13:21:54.836000 1 4 20 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7624 13:21:54.842599 1 4 24 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
7625 13:21:54.846066 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7626 13:21:54.849285 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7627 13:21:54.853074 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7628 13:21:54.859965 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7629 13:21:54.862974 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7630 13:21:54.866087 1 5 16 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (0 1)
7631 13:21:54.872659 1 5 20 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
7632 13:21:54.876310 1 5 24 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
7633 13:21:54.879506 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 13:21:54.886458 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7635 13:21:54.889621 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 13:21:54.892944 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 13:21:54.899731 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 13:21:54.903471 1 6 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7639 13:21:54.906720 1 6 20 | B1->B0 | 2525 4444 | 0 0 | (0 0) (0 0)
7640 13:21:54.913112 1 6 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7641 13:21:54.916406 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 13:21:54.919733 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 13:21:54.926875 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 13:21:54.929819 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7645 13:21:54.933659 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 13:21:54.936809 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7647 13:21:54.943876 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7648 13:21:54.946813 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7649 13:21:54.949740 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 13:21:54.956548 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 13:21:54.960314 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 13:21:54.963113 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 13:21:54.970147 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 13:21:54.973327 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 13:21:54.976764 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 13:21:54.983322 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 13:21:54.986584 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 13:21:54.989839 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 13:21:54.996785 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 13:21:54.999922 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 13:21:55.003098 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 13:21:55.009924 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7663 13:21:55.013060 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7664 13:21:55.016803 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7665 13:21:55.019872 Total UI for P1: 0, mck2ui 16
7666 13:21:55.023198 best dqsien dly found for B0: ( 1, 9, 18)
7667 13:21:55.026347 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7668 13:21:55.029844 Total UI for P1: 0, mck2ui 16
7669 13:21:55.033489 best dqsien dly found for B1: ( 1, 9, 22)
7670 13:21:55.036559 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7671 13:21:55.040080 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7672 13:21:55.043552
7673 13:21:55.046665 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7674 13:21:55.050242 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7675 13:21:55.053582 [Gating] SW calibration Done
7676 13:21:55.053995 ==
7677 13:21:55.056824 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 13:21:55.059889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 13:21:55.060299 ==
7680 13:21:55.060626 RX Vref Scan: 0
7681 13:21:55.063579
7682 13:21:55.063987 RX Vref 0 -> 0, step: 1
7683 13:21:55.064312
7684 13:21:55.066390 RX Delay 0 -> 252, step: 8
7685 13:21:55.070214 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7686 13:21:55.073519 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7687 13:21:55.080341 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7688 13:21:55.083290 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7689 13:21:55.086867 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7690 13:21:55.090334 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7691 13:21:55.093616 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7692 13:21:55.096710 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7693 13:21:55.103683 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7694 13:21:55.106927 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7695 13:21:55.110263 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7696 13:21:55.113457 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7697 13:21:55.116482 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7698 13:21:55.123211 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7699 13:21:55.126172 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7700 13:21:55.129691 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7701 13:21:55.129771 ==
7702 13:21:55.133283 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 13:21:55.136556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 13:21:55.139686 ==
7705 13:21:55.139766 DQS Delay:
7706 13:21:55.139828 DQS0 = 0, DQS1 = 0
7707 13:21:55.143188 DQM Delay:
7708 13:21:55.143267 DQM0 = 132, DQM1 = 125
7709 13:21:55.146369 DQ Delay:
7710 13:21:55.149588 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7711 13:21:55.152973 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7712 13:21:55.156282 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7713 13:21:55.160006 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7714 13:21:55.160086
7715 13:21:55.160148
7716 13:21:55.160206 ==
7717 13:21:55.163229 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 13:21:55.166502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 13:21:55.166583 ==
7720 13:21:55.166646
7721 13:21:55.166736
7722 13:21:55.169653 TX Vref Scan disable
7723 13:21:55.172886 == TX Byte 0 ==
7724 13:21:55.176527 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7725 13:21:55.179778 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7726 13:21:55.182955 == TX Byte 1 ==
7727 13:21:55.186491 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7728 13:21:55.189621 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7729 13:21:55.189702 ==
7730 13:21:55.193216 Dram Type= 6, Freq= 0, CH_0, rank 0
7731 13:21:55.199604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7732 13:21:55.199684 ==
7733 13:21:55.212687
7734 13:21:55.215811 TX Vref early break, caculate TX vref
7735 13:21:55.219566 TX Vref=16, minBit 7, minWin=21, winSum=363
7736 13:21:55.222737 TX Vref=18, minBit 0, minWin=22, winSum=371
7737 13:21:55.226252 TX Vref=20, minBit 3, minWin=22, winSum=382
7738 13:21:55.229647 TX Vref=22, minBit 6, minWin=23, winSum=390
7739 13:21:55.232952 TX Vref=24, minBit 0, minWin=24, winSum=404
7740 13:21:55.235962 TX Vref=26, minBit 1, minWin=25, winSum=415
7741 13:21:55.242912 TX Vref=28, minBit 3, minWin=25, winSum=419
7742 13:21:55.246561 TX Vref=30, minBit 1, minWin=25, winSum=420
7743 13:21:55.249466 TX Vref=32, minBit 3, minWin=24, winSum=413
7744 13:21:55.253492 TX Vref=34, minBit 3, minWin=23, winSum=400
7745 13:21:55.256373 TX Vref=36, minBit 0, minWin=23, winSum=398
7746 13:21:55.263253 [TxChooseVref] Worse bit 1, Min win 25, Win sum 420, Final Vref 30
7747 13:21:55.263334
7748 13:21:55.266572 Final TX Range 0 Vref 30
7749 13:21:55.266652
7750 13:21:55.266713 ==
7751 13:21:55.269659 Dram Type= 6, Freq= 0, CH_0, rank 0
7752 13:21:55.272881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7753 13:21:55.272962 ==
7754 13:21:55.273025
7755 13:21:55.273083
7756 13:21:55.276141 TX Vref Scan disable
7757 13:21:55.282641 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7758 13:21:55.282720 == TX Byte 0 ==
7759 13:21:55.286401 u2DelayCellOfst[0]=17 cells (5 PI)
7760 13:21:55.289542 u2DelayCellOfst[1]=21 cells (6 PI)
7761 13:21:55.293223 u2DelayCellOfst[2]=14 cells (4 PI)
7762 13:21:55.296225 u2DelayCellOfst[3]=14 cells (4 PI)
7763 13:21:55.299601 u2DelayCellOfst[4]=10 cells (3 PI)
7764 13:21:55.302739 u2DelayCellOfst[5]=0 cells (0 PI)
7765 13:21:55.306108 u2DelayCellOfst[6]=21 cells (6 PI)
7766 13:21:55.309503 u2DelayCellOfst[7]=21 cells (6 PI)
7767 13:21:55.313123 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7768 13:21:55.316295 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7769 13:21:55.319459 == TX Byte 1 ==
7770 13:21:55.319538 u2DelayCellOfst[8]=0 cells (0 PI)
7771 13:21:55.323361 u2DelayCellOfst[9]=0 cells (0 PI)
7772 13:21:55.326113 u2DelayCellOfst[10]=7 cells (2 PI)
7773 13:21:55.329419 u2DelayCellOfst[11]=3 cells (1 PI)
7774 13:21:55.332998 u2DelayCellOfst[12]=14 cells (4 PI)
7775 13:21:55.336109 u2DelayCellOfst[13]=14 cells (4 PI)
7776 13:21:55.339472 u2DelayCellOfst[14]=17 cells (5 PI)
7777 13:21:55.342780 u2DelayCellOfst[15]=14 cells (4 PI)
7778 13:21:55.346261 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7779 13:21:55.352855 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7780 13:21:55.352935 DramC Write-DBI on
7781 13:21:55.352998 ==
7782 13:21:55.356229 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 13:21:55.359394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 13:21:55.362810 ==
7785 13:21:55.362889
7786 13:21:55.362951
7787 13:21:55.363009 TX Vref Scan disable
7788 13:21:55.366177 == TX Byte 0 ==
7789 13:21:55.369607 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7790 13:21:55.372823 == TX Byte 1 ==
7791 13:21:55.376232 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7792 13:21:55.379543 DramC Write-DBI off
7793 13:21:55.379632
7794 13:21:55.379697 [DATLAT]
7795 13:21:55.379755 Freq=1600, CH0 RK0
7796 13:21:55.379812
7797 13:21:55.382779 DATLAT Default: 0xf
7798 13:21:55.382858 0, 0xFFFF, sum = 0
7799 13:21:55.386610 1, 0xFFFF, sum = 0
7800 13:21:55.386691 2, 0xFFFF, sum = 0
7801 13:21:55.389309 3, 0xFFFF, sum = 0
7802 13:21:55.392937 4, 0xFFFF, sum = 0
7803 13:21:55.393018 5, 0xFFFF, sum = 0
7804 13:21:55.396640 6, 0xFFFF, sum = 0
7805 13:21:55.396742 7, 0xFFFF, sum = 0
7806 13:21:55.399570 8, 0xFFFF, sum = 0
7807 13:21:55.399661 9, 0xFFFF, sum = 0
7808 13:21:55.402811 10, 0xFFFF, sum = 0
7809 13:21:55.402898 11, 0xFFFF, sum = 0
7810 13:21:55.406926 12, 0xFFFF, sum = 0
7811 13:21:55.407019 13, 0xFFFF, sum = 0
7812 13:21:55.409555 14, 0x0, sum = 1
7813 13:21:55.409656 15, 0x0, sum = 2
7814 13:21:55.413041 16, 0x0, sum = 3
7815 13:21:55.413142 17, 0x0, sum = 4
7816 13:21:55.416080 best_step = 15
7817 13:21:55.416188
7818 13:21:55.416272 ==
7819 13:21:55.419949 Dram Type= 6, Freq= 0, CH_0, rank 0
7820 13:21:55.423293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7821 13:21:55.423412 ==
7822 13:21:55.423506 RX Vref Scan: 1
7823 13:21:55.423593
7824 13:21:55.426240 Set Vref Range= 24 -> 127
7825 13:21:55.426371
7826 13:21:55.429561 RX Vref 24 -> 127, step: 1
7827 13:21:55.429711
7828 13:21:55.433275 RX Delay 11 -> 252, step: 4
7829 13:21:55.433423
7830 13:21:55.436693 Set Vref, RX VrefLevel [Byte0]: 24
7831 13:21:55.440317 [Byte1]: 24
7832 13:21:55.440515
7833 13:21:55.443510 Set Vref, RX VrefLevel [Byte0]: 25
7834 13:21:55.446184 [Byte1]: 25
7835 13:21:55.446417
7836 13:21:55.449714 Set Vref, RX VrefLevel [Byte0]: 26
7837 13:21:55.453141 [Byte1]: 26
7838 13:21:55.456701
7839 13:21:55.456794 Set Vref, RX VrefLevel [Byte0]: 27
7840 13:21:55.460341 [Byte1]: 27
7841 13:21:55.464084
7842 13:21:55.464164 Set Vref, RX VrefLevel [Byte0]: 28
7843 13:21:55.467266 [Byte1]: 28
7844 13:21:55.471896
7845 13:21:55.471975 Set Vref, RX VrefLevel [Byte0]: 29
7846 13:21:55.475404 [Byte1]: 29
7847 13:21:55.479286
7848 13:21:55.479364 Set Vref, RX VrefLevel [Byte0]: 30
7849 13:21:55.482486 [Byte1]: 30
7850 13:21:55.487137
7851 13:21:55.487216 Set Vref, RX VrefLevel [Byte0]: 31
7852 13:21:55.490458 [Byte1]: 31
7853 13:21:55.494393
7854 13:21:55.494473 Set Vref, RX VrefLevel [Byte0]: 32
7855 13:21:55.497832 [Byte1]: 32
7856 13:21:55.502280
7857 13:21:55.502359 Set Vref, RX VrefLevel [Byte0]: 33
7858 13:21:55.505404 [Byte1]: 33
7859 13:21:55.509613
7860 13:21:55.509692 Set Vref, RX VrefLevel [Byte0]: 34
7861 13:21:55.513114 [Byte1]: 34
7862 13:21:55.517217
7863 13:21:55.517296 Set Vref, RX VrefLevel [Byte0]: 35
7864 13:21:55.521246 [Byte1]: 35
7865 13:21:55.525062
7866 13:21:55.525141 Set Vref, RX VrefLevel [Byte0]: 36
7867 13:21:55.528551 [Byte1]: 36
7868 13:21:55.532559
7869 13:21:55.532693 Set Vref, RX VrefLevel [Byte0]: 37
7870 13:21:55.535949 [Byte1]: 37
7871 13:21:55.540290
7872 13:21:55.540369 Set Vref, RX VrefLevel [Byte0]: 38
7873 13:21:55.543622 [Byte1]: 38
7874 13:21:55.548067
7875 13:21:55.548145 Set Vref, RX VrefLevel [Byte0]: 39
7876 13:21:55.551159 [Byte1]: 39
7877 13:21:55.555784
7878 13:21:55.555863 Set Vref, RX VrefLevel [Byte0]: 40
7879 13:21:55.558803 [Byte1]: 40
7880 13:21:55.563110
7881 13:21:55.563204 Set Vref, RX VrefLevel [Byte0]: 41
7882 13:21:55.566554 [Byte1]: 41
7883 13:21:55.570654
7884 13:21:55.570733 Set Vref, RX VrefLevel [Byte0]: 42
7885 13:21:55.574132 [Byte1]: 42
7886 13:21:55.578639
7887 13:21:55.578724 Set Vref, RX VrefLevel [Byte0]: 43
7888 13:21:55.581699 [Byte1]: 43
7889 13:21:55.586117
7890 13:21:55.586196 Set Vref, RX VrefLevel [Byte0]: 44
7891 13:21:55.589257 [Byte1]: 44
7892 13:21:55.593389
7893 13:21:55.593468 Set Vref, RX VrefLevel [Byte0]: 45
7894 13:21:55.596966 [Byte1]: 45
7895 13:21:55.601492
7896 13:21:55.601572 Set Vref, RX VrefLevel [Byte0]: 46
7897 13:21:55.604493 [Byte1]: 46
7898 13:21:55.608906
7899 13:21:55.608985 Set Vref, RX VrefLevel [Byte0]: 47
7900 13:21:55.611866 [Byte1]: 47
7901 13:21:55.616372
7902 13:21:55.616471 Set Vref, RX VrefLevel [Byte0]: 48
7903 13:21:55.619467 [Byte1]: 48
7904 13:21:55.624178
7905 13:21:55.624258 Set Vref, RX VrefLevel [Byte0]: 49
7906 13:21:55.627313 [Byte1]: 49
7907 13:21:55.631758
7908 13:21:55.631829 Set Vref, RX VrefLevel [Byte0]: 50
7909 13:21:55.635260 [Byte1]: 50
7910 13:21:55.639917
7911 13:21:55.640025 Set Vref, RX VrefLevel [Byte0]: 51
7912 13:21:55.643084 [Byte1]: 51
7913 13:21:55.646788
7914 13:21:55.646885 Set Vref, RX VrefLevel [Byte0]: 52
7915 13:21:55.650109 [Byte1]: 52
7916 13:21:55.654427
7917 13:21:55.654529 Set Vref, RX VrefLevel [Byte0]: 53
7918 13:21:55.658293 [Byte1]: 53
7919 13:21:55.661916
7920 13:21:55.662016 Set Vref, RX VrefLevel [Byte0]: 54
7921 13:21:55.665640 [Byte1]: 54
7922 13:21:55.669818
7923 13:21:55.669918 Set Vref, RX VrefLevel [Byte0]: 55
7924 13:21:55.672891 [Byte1]: 55
7925 13:21:55.677587
7926 13:21:55.677655 Set Vref, RX VrefLevel [Byte0]: 56
7927 13:21:55.680839 [Byte1]: 56
7928 13:21:55.685105
7929 13:21:55.685202 Set Vref, RX VrefLevel [Byte0]: 57
7930 13:21:55.688753 [Byte1]: 57
7931 13:21:55.692218
7932 13:21:55.692328 Set Vref, RX VrefLevel [Byte0]: 58
7933 13:21:55.696098 [Byte1]: 58
7934 13:21:55.700134
7935 13:21:55.703294 Set Vref, RX VrefLevel [Byte0]: 59
7936 13:21:55.703373 [Byte1]: 59
7937 13:21:55.707873
7938 13:21:55.707958 Set Vref, RX VrefLevel [Byte0]: 60
7939 13:21:55.711340 [Byte1]: 60
7940 13:21:55.715543
7941 13:21:55.715641 Set Vref, RX VrefLevel [Byte0]: 61
7942 13:21:55.718542 [Byte1]: 61
7943 13:21:55.723009
7944 13:21:55.723159 Set Vref, RX VrefLevel [Byte0]: 62
7945 13:21:55.726162 [Byte1]: 62
7946 13:21:55.730789
7947 13:21:55.730921 Set Vref, RX VrefLevel [Byte0]: 63
7948 13:21:55.733984 [Byte1]: 63
7949 13:21:55.738256
7950 13:21:55.738402 Set Vref, RX VrefLevel [Byte0]: 64
7951 13:21:55.741716 [Byte1]: 64
7952 13:21:55.745887
7953 13:21:55.746082 Set Vref, RX VrefLevel [Byte0]: 65
7954 13:21:55.749050 [Byte1]: 65
7955 13:21:55.753614
7956 13:21:55.753847 Set Vref, RX VrefLevel [Byte0]: 66
7957 13:21:55.756920 [Byte1]: 66
7958 13:21:55.761739
7959 13:21:55.762263 Set Vref, RX VrefLevel [Byte0]: 67
7960 13:21:55.764829 [Byte1]: 67
7961 13:21:55.769040
7962 13:21:55.769504 Set Vref, RX VrefLevel [Byte0]: 68
7963 13:21:55.772735 [Byte1]: 68
7964 13:21:55.776483
7965 13:21:55.776945 Set Vref, RX VrefLevel [Byte0]: 69
7966 13:21:55.780043 [Byte1]: 69
7967 13:21:55.784162
7968 13:21:55.784570 Set Vref, RX VrefLevel [Byte0]: 70
7969 13:21:55.787611 [Byte1]: 70
7970 13:21:55.791608
7971 13:21:55.792129 Set Vref, RX VrefLevel [Byte0]: 71
7972 13:21:55.795408 [Byte1]: 71
7973 13:21:55.799455
7974 13:21:55.799865 Set Vref, RX VrefLevel [Byte0]: 72
7975 13:21:55.802837 [Byte1]: 72
7976 13:21:55.806986
7977 13:21:55.807511 Set Vref, RX VrefLevel [Byte0]: 73
7978 13:21:55.810609 [Byte1]: 73
7979 13:21:55.814609
7980 13:21:55.815017 Set Vref, RX VrefLevel [Byte0]: 74
7981 13:21:55.818147 [Byte1]: 74
7982 13:21:55.822371
7983 13:21:55.822938 Set Vref, RX VrefLevel [Byte0]: 75
7984 13:21:55.825504 [Byte1]: 75
7985 13:21:55.830370
7986 13:21:55.830783 Set Vref, RX VrefLevel [Byte0]: 76
7987 13:21:55.833249 [Byte1]: 76
7988 13:21:55.837310
7989 13:21:55.837718 Final RX Vref Byte 0 = 56 to rank0
7990 13:21:55.840859 Final RX Vref Byte 1 = 61 to rank0
7991 13:21:55.844393 Final RX Vref Byte 0 = 56 to rank1
7992 13:21:55.847145 Final RX Vref Byte 1 = 61 to rank1==
7993 13:21:55.850595 Dram Type= 6, Freq= 0, CH_0, rank 0
7994 13:21:55.857251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7995 13:21:55.857332 ==
7996 13:21:55.857395 DQS Delay:
7997 13:21:55.857455 DQS0 = 0, DQS1 = 0
7998 13:21:55.860474 DQM Delay:
7999 13:21:55.860553 DQM0 = 129, DQM1 = 122
8000 13:21:55.863877 DQ Delay:
8001 13:21:55.867302 DQ0 =130, DQ1 =132, DQ2 =122, DQ3 =126
8002 13:21:55.870826 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
8003 13:21:55.874289 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =118
8004 13:21:55.877464 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
8005 13:21:55.877544
8006 13:21:55.877610
8007 13:21:55.877704
8008 13:21:55.880883 [DramC_TX_OE_Calibration] TA2
8009 13:21:55.884157 Original DQ_B0 (3 6) =30, OEN = 27
8010 13:21:55.887491 Original DQ_B1 (3 6) =30, OEN = 27
8011 13:21:55.887571 24, 0x0, End_B0=24 End_B1=24
8012 13:21:55.890674 25, 0x0, End_B0=25 End_B1=25
8013 13:21:55.894214 26, 0x0, End_B0=26 End_B1=26
8014 13:21:55.897587 27, 0x0, End_B0=27 End_B1=27
8015 13:21:55.901077 28, 0x0, End_B0=28 End_B1=28
8016 13:21:55.901173 29, 0x0, End_B0=29 End_B1=29
8017 13:21:55.903980 30, 0x0, End_B0=30 End_B1=30
8018 13:21:55.907465 31, 0x4141, End_B0=30 End_B1=30
8019 13:21:55.910929 Byte0 end_step=30 best_step=27
8020 13:21:55.914365 Byte1 end_step=30 best_step=27
8021 13:21:55.914473 Byte0 TX OE(2T, 0.5T) = (3, 3)
8022 13:21:55.917624 Byte1 TX OE(2T, 0.5T) = (3, 3)
8023 13:21:55.917723
8024 13:21:55.917801
8025 13:21:55.927790 [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
8026 13:21:55.931012 CH0 RK0: MR19=303, MR18=1509
8027 13:21:55.934217 CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
8028 13:21:55.934297
8029 13:21:55.937518 ----->DramcWriteLeveling(PI) begin...
8030 13:21:55.940798 ==
8031 13:21:55.944378 Dram Type= 6, Freq= 0, CH_0, rank 1
8032 13:21:55.948225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8033 13:21:55.948332 ==
8034 13:21:55.951424 Write leveling (Byte 0): 32 => 32
8035 13:21:55.954309 Write leveling (Byte 1): 27 => 27
8036 13:21:55.957676 DramcWriteLeveling(PI) end<-----
8037 13:21:55.957756
8038 13:21:55.957818 ==
8039 13:21:55.960634 Dram Type= 6, Freq= 0, CH_0, rank 1
8040 13:21:55.964356 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8041 13:21:55.964436 ==
8042 13:21:55.967631 [Gating] SW mode calibration
8043 13:21:55.974551 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8044 13:21:55.977526 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8045 13:21:55.984216 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 13:21:55.987978 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 13:21:55.990871 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8048 13:21:55.998141 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8049 13:21:56.001610 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8050 13:21:56.004877 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8051 13:21:56.011311 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8052 13:21:56.014613 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8053 13:21:56.018018 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8054 13:21:56.024640 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8055 13:21:56.027840 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8056 13:21:56.031331 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
8057 13:21:56.038129 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8058 13:21:56.041575 1 5 20 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
8059 13:21:56.044760 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8060 13:21:56.051735 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 13:21:56.054666 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 13:21:56.058194 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 13:21:56.061313 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8064 13:21:56.067951 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8065 13:21:56.071168 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8066 13:21:56.074923 1 6 20 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8067 13:21:56.081352 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 13:21:56.084579 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 13:21:56.087864 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8070 13:21:56.094706 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 13:21:56.098325 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8072 13:21:56.101483 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8073 13:21:56.108271 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8074 13:21:56.111747 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8075 13:21:56.114960 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 13:21:56.121463 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 13:21:56.124689 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 13:21:56.128291 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 13:21:56.131430 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 13:21:56.138440 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 13:21:56.141361 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 13:21:56.144982 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 13:21:56.151470 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 13:21:56.155009 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 13:21:56.158219 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 13:21:56.164994 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8087 13:21:56.168141 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8088 13:21:56.171425 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8089 13:21:56.174699 Total UI for P1: 0, mck2ui 16
8090 13:21:56.178114 best dqsien dly found for B0: ( 1, 9, 6)
8091 13:21:56.184600 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8092 13:21:56.188373 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8093 13:21:56.191725 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8094 13:21:56.195062 Total UI for P1: 0, mck2ui 16
8095 13:21:56.198310 best dqsien dly found for B1: ( 1, 9, 18)
8096 13:21:56.201967 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8097 13:21:56.205192 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8098 13:21:56.205263
8099 13:21:56.208495 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8100 13:21:56.215218 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8101 13:21:56.215292 [Gating] SW calibration Done
8102 13:21:56.215355 ==
8103 13:21:56.218608 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 13:21:56.225299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 13:21:56.225374 ==
8106 13:21:56.225436 RX Vref Scan: 0
8107 13:21:56.225495
8108 13:21:56.228533 RX Vref 0 -> 0, step: 1
8109 13:21:56.228631
8110 13:21:56.231767 RX Delay 0 -> 252, step: 8
8111 13:21:56.235474 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8112 13:21:56.238583 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8113 13:21:56.241911 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8114 13:21:56.245159 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8115 13:21:56.252236 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8116 13:21:56.255337 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8117 13:21:56.258739 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8118 13:21:56.262123 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8119 13:21:56.266030 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8120 13:21:56.269172 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8121 13:21:56.275562 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8122 13:21:56.279354 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8123 13:21:56.282442 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8124 13:21:56.286269 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8125 13:21:56.292309 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8126 13:21:56.296119 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8127 13:21:56.296535 ==
8128 13:21:56.299220 Dram Type= 6, Freq= 0, CH_0, rank 1
8129 13:21:56.302303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8130 13:21:56.302713 ==
8131 13:21:56.303038 DQS Delay:
8132 13:21:56.305697 DQS0 = 0, DQS1 = 0
8133 13:21:56.306105 DQM Delay:
8134 13:21:56.308919 DQM0 = 130, DQM1 = 125
8135 13:21:56.309329 DQ Delay:
8136 13:21:56.312515 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8137 13:21:56.316178 DQ4 =131, DQ5 =115, DQ6 =139, DQ7 =139
8138 13:21:56.319091 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8139 13:21:56.322231 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
8140 13:21:56.325644
8141 13:21:56.326217
8142 13:21:56.326672 ==
8143 13:21:56.329165 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 13:21:56.332518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 13:21:56.332955 ==
8146 13:21:56.333279
8147 13:21:56.333582
8148 13:21:56.335658 TX Vref Scan disable
8149 13:21:56.336066 == TX Byte 0 ==
8150 13:21:56.342450 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8151 13:21:56.345761 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8152 13:21:56.346173 == TX Byte 1 ==
8153 13:21:56.353322 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8154 13:21:56.355963 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8155 13:21:56.356435 ==
8156 13:21:56.359658 Dram Type= 6, Freq= 0, CH_0, rank 1
8157 13:21:56.362355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8158 13:21:56.362898 ==
8159 13:21:56.376207
8160 13:21:56.379600 TX Vref early break, caculate TX vref
8161 13:21:56.383506 TX Vref=16, minBit 3, minWin=22, winSum=372
8162 13:21:56.386628 TX Vref=18, minBit 3, minWin=23, winSum=383
8163 13:21:56.389900 TX Vref=20, minBit 9, minWin=23, winSum=393
8164 13:21:56.393193 TX Vref=22, minBit 0, minWin=24, winSum=402
8165 13:21:56.396070 TX Vref=24, minBit 1, minWin=25, winSum=413
8166 13:21:56.403280 TX Vref=26, minBit 3, minWin=25, winSum=416
8167 13:21:56.406479 TX Vref=28, minBit 4, minWin=25, winSum=426
8168 13:21:56.409863 TX Vref=30, minBit 4, minWin=25, winSum=418
8169 13:21:56.412803 TX Vref=32, minBit 0, minWin=25, winSum=412
8170 13:21:56.416343 TX Vref=34, minBit 2, minWin=24, winSum=401
8171 13:21:56.423224 [TxChooseVref] Worse bit 4, Min win 25, Win sum 426, Final Vref 28
8172 13:21:56.423781
8173 13:21:56.426740 Final TX Range 0 Vref 28
8174 13:21:56.427154
8175 13:21:56.427477 ==
8176 13:21:56.429497 Dram Type= 6, Freq= 0, CH_0, rank 1
8177 13:21:56.432847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8178 13:21:56.432921 ==
8179 13:21:56.432988
8180 13:21:56.433047
8181 13:21:56.436080 TX Vref Scan disable
8182 13:21:56.442947 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8183 13:21:56.443023 == TX Byte 0 ==
8184 13:21:56.446312 u2DelayCellOfst[0]=14 cells (4 PI)
8185 13:21:56.449404 u2DelayCellOfst[1]=17 cells (5 PI)
8186 13:21:56.452787 u2DelayCellOfst[2]=7 cells (2 PI)
8187 13:21:56.456393 u2DelayCellOfst[3]=10 cells (3 PI)
8188 13:21:56.459501 u2DelayCellOfst[4]=7 cells (2 PI)
8189 13:21:56.459601 u2DelayCellOfst[5]=0 cells (0 PI)
8190 13:21:56.462638 u2DelayCellOfst[6]=17 cells (5 PI)
8191 13:21:56.466367 u2DelayCellOfst[7]=17 cells (5 PI)
8192 13:21:56.472813 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8193 13:21:56.475923 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8194 13:21:56.475994 == TX Byte 1 ==
8195 13:21:56.479348 u2DelayCellOfst[8]=0 cells (0 PI)
8196 13:21:56.482669 u2DelayCellOfst[9]=0 cells (0 PI)
8197 13:21:56.486194 u2DelayCellOfst[10]=3 cells (1 PI)
8198 13:21:56.489454 u2DelayCellOfst[11]=0 cells (0 PI)
8199 13:21:56.493260 u2DelayCellOfst[12]=14 cells (4 PI)
8200 13:21:56.496457 u2DelayCellOfst[13]=10 cells (3 PI)
8201 13:21:56.499289 u2DelayCellOfst[14]=14 cells (4 PI)
8202 13:21:56.502889 u2DelayCellOfst[15]=10 cells (3 PI)
8203 13:21:56.506634 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8204 13:21:56.509932 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8205 13:21:56.513265 DramC Write-DBI on
8206 13:21:56.513334 ==
8207 13:21:56.516075 Dram Type= 6, Freq= 0, CH_0, rank 1
8208 13:21:56.519657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8209 13:21:56.519726 ==
8210 13:21:56.519784
8211 13:21:56.519846
8212 13:21:56.522851 TX Vref Scan disable
8213 13:21:56.526396 == TX Byte 0 ==
8214 13:21:56.529537 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8215 13:21:56.529636 == TX Byte 1 ==
8216 13:21:56.536541 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8217 13:21:56.536617 DramC Write-DBI off
8218 13:21:56.536704
8219 13:21:56.539828 [DATLAT]
8220 13:21:56.539924 Freq=1600, CH0 RK1
8221 13:21:56.540014
8222 13:21:56.542876 DATLAT Default: 0xf
8223 13:21:56.542971 0, 0xFFFF, sum = 0
8224 13:21:56.546796 1, 0xFFFF, sum = 0
8225 13:21:56.546900 2, 0xFFFF, sum = 0
8226 13:21:56.549643 3, 0xFFFF, sum = 0
8227 13:21:56.549746 4, 0xFFFF, sum = 0
8228 13:21:56.553039 5, 0xFFFF, sum = 0
8229 13:21:56.553116 6, 0xFFFF, sum = 0
8230 13:21:56.556407 7, 0xFFFF, sum = 0
8231 13:21:56.556508 8, 0xFFFF, sum = 0
8232 13:21:56.559895 9, 0xFFFF, sum = 0
8233 13:21:56.559994 10, 0xFFFF, sum = 0
8234 13:21:56.563127 11, 0xFFFF, sum = 0
8235 13:21:56.563226 12, 0xFFFF, sum = 0
8236 13:21:56.566199 13, 0xFFFF, sum = 0
8237 13:21:56.566277 14, 0x0, sum = 1
8238 13:21:56.570109 15, 0x0, sum = 2
8239 13:21:56.570184 16, 0x0, sum = 3
8240 13:21:56.572983 17, 0x0, sum = 4
8241 13:21:56.573058 best_step = 15
8242 13:21:56.573118
8243 13:21:56.573174 ==
8244 13:21:56.576524 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 13:21:56.583043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 13:21:56.583124 ==
8247 13:21:56.583188 RX Vref Scan: 0
8248 13:21:56.583246
8249 13:21:56.586907 RX Vref 0 -> 0, step: 1
8250 13:21:56.586986
8251 13:21:56.590046 RX Delay 11 -> 252, step: 4
8252 13:21:56.593216 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8253 13:21:56.596287 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8254 13:21:56.599751 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8255 13:21:56.606560 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8256 13:21:56.610176 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8257 13:21:56.613318 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8258 13:21:56.616702 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8259 13:21:56.619769 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8260 13:21:56.626657 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8261 13:21:56.629922 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8262 13:21:56.633383 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8263 13:21:56.636602 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8264 13:21:56.640000 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8265 13:21:56.646476 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8266 13:21:56.649835 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8267 13:21:56.653103 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8268 13:21:56.653183 ==
8269 13:21:56.656787 Dram Type= 6, Freq= 0, CH_0, rank 1
8270 13:21:56.659786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8271 13:21:56.659866 ==
8272 13:21:56.663169 DQS Delay:
8273 13:21:56.663248 DQS0 = 0, DQS1 = 0
8274 13:21:56.666308 DQM Delay:
8275 13:21:56.666387 DQM0 = 126, DQM1 = 122
8276 13:21:56.666450 DQ Delay:
8277 13:21:56.670101 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8278 13:21:56.676563 DQ4 =124, DQ5 =114, DQ6 =134, DQ7 =134
8279 13:21:56.679913 DQ8 =114, DQ9 =110, DQ10 =122, DQ11 =116
8280 13:21:56.683215 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8281 13:21:56.683295
8282 13:21:56.683358
8283 13:21:56.683416
8284 13:21:56.686248 [DramC_TX_OE_Calibration] TA2
8285 13:21:56.689707 Original DQ_B0 (3 6) =30, OEN = 27
8286 13:21:56.693227 Original DQ_B1 (3 6) =30, OEN = 27
8287 13:21:56.693308 24, 0x0, End_B0=24 End_B1=24
8288 13:21:56.696512 25, 0x0, End_B0=25 End_B1=25
8289 13:21:56.700163 26, 0x0, End_B0=26 End_B1=26
8290 13:21:56.703073 27, 0x0, End_B0=27 End_B1=27
8291 13:21:56.703155 28, 0x0, End_B0=28 End_B1=28
8292 13:21:56.706437 29, 0x0, End_B0=29 End_B1=29
8293 13:21:56.709650 30, 0x0, End_B0=30 End_B1=30
8294 13:21:56.713231 31, 0x4141, End_B0=30 End_B1=30
8295 13:21:56.716299 Byte0 end_step=30 best_step=27
8296 13:21:56.719899 Byte1 end_step=30 best_step=27
8297 13:21:56.719980 Byte0 TX OE(2T, 0.5T) = (3, 3)
8298 13:21:56.723414 Byte1 TX OE(2T, 0.5T) = (3, 3)
8299 13:21:56.723494
8300 13:21:56.723556
8301 13:21:56.733131 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
8302 13:21:56.733213 CH0 RK1: MR19=303, MR18=1A0F
8303 13:21:56.740205 CH0_RK1: MR19=0x303, MR18=0x1A0F, DQSOSC=396, MR23=63, INC=23, DEC=15
8304 13:21:56.743040 [RxdqsGatingPostProcess] freq 1600
8305 13:21:56.750240 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8306 13:21:56.753142 best DQS0 dly(2T, 0.5T) = (1, 1)
8307 13:21:56.756383 best DQS1 dly(2T, 0.5T) = (1, 1)
8308 13:21:56.760016 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8309 13:21:56.763089 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8310 13:21:56.766190 best DQS0 dly(2T, 0.5T) = (1, 1)
8311 13:21:56.766270 best DQS1 dly(2T, 0.5T) = (1, 1)
8312 13:21:56.769813 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8313 13:21:56.772891 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8314 13:21:56.776455 Pre-setting of DQS Precalculation
8315 13:21:56.783020 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8316 13:21:56.783100 ==
8317 13:21:56.786370 Dram Type= 6, Freq= 0, CH_1, rank 0
8318 13:21:56.789922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8319 13:21:56.790002 ==
8320 13:21:56.796416 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8321 13:21:56.799679 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8322 13:21:56.803054 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8323 13:21:56.809916 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8324 13:21:56.818526 [CA 0] Center 42 (13~71) winsize 59
8325 13:21:56.821535 [CA 1] Center 42 (14~71) winsize 58
8326 13:21:56.824829 [CA 2] Center 37 (9~66) winsize 58
8327 13:21:56.828438 [CA 3] Center 36 (7~66) winsize 60
8328 13:21:56.831822 [CA 4] Center 37 (8~66) winsize 59
8329 13:21:56.835486 [CA 5] Center 36 (7~66) winsize 60
8330 13:21:56.835566
8331 13:21:56.838311 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8332 13:21:56.838391
8333 13:21:56.842171 [CATrainingPosCal] consider 1 rank data
8334 13:21:56.845136 u2DelayCellTimex100 = 275/100 ps
8335 13:21:56.848888 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8336 13:21:56.856000 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8337 13:21:56.858713 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8338 13:21:56.861662 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8339 13:21:56.864969 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8340 13:21:56.868294 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8341 13:21:56.868374
8342 13:21:56.871583 CA PerBit enable=1, Macro0, CA PI delay=36
8343 13:21:56.871663
8344 13:21:56.875267 [CBTSetCACLKResult] CA Dly = 36
8345 13:21:56.875347 CS Dly: 9 (0~40)
8346 13:21:56.882257 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8347 13:21:56.884987 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8348 13:21:56.885067 ==
8349 13:21:56.888609 Dram Type= 6, Freq= 0, CH_1, rank 1
8350 13:21:56.892184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8351 13:21:56.892263 ==
8352 13:21:56.898554 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8353 13:21:56.901621 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8354 13:21:56.905547 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8355 13:21:56.911853 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8356 13:21:56.921464 [CA 0] Center 43 (14~72) winsize 59
8357 13:21:56.925007 [CA 1] Center 43 (14~72) winsize 59
8358 13:21:56.928470 [CA 2] Center 38 (9~67) winsize 59
8359 13:21:56.931520 [CA 3] Center 37 (8~67) winsize 60
8360 13:21:56.934827 [CA 4] Center 38 (9~68) winsize 60
8361 13:21:56.938228 [CA 5] Center 37 (8~66) winsize 59
8362 13:21:56.938307
8363 13:21:56.941302 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8364 13:21:56.941381
8365 13:21:56.945327 [CATrainingPosCal] consider 2 rank data
8366 13:21:56.948181 u2DelayCellTimex100 = 275/100 ps
8367 13:21:56.951616 CA0 delay=42 (14~71),Diff = 5 PI (17 cell)
8368 13:21:56.958339 CA1 delay=42 (14~71),Diff = 5 PI (17 cell)
8369 13:21:56.961444 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8370 13:21:56.964853 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8371 13:21:56.968513 CA4 delay=37 (9~66),Diff = 0 PI (0 cell)
8372 13:21:56.971764 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8373 13:21:56.971862
8374 13:21:56.974899 CA PerBit enable=1, Macro0, CA PI delay=37
8375 13:21:56.974992
8376 13:21:56.978577 [CBTSetCACLKResult] CA Dly = 37
8377 13:21:56.978647 CS Dly: 11 (0~44)
8378 13:21:56.984700 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8379 13:21:56.988633 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8380 13:21:56.988739
8381 13:21:56.991624 ----->DramcWriteLeveling(PI) begin...
8382 13:21:56.991722 ==
8383 13:21:56.994996 Dram Type= 6, Freq= 0, CH_1, rank 0
8384 13:21:56.998198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 13:21:56.998273 ==
8386 13:21:57.001362 Write leveling (Byte 0): 23 => 23
8387 13:21:57.005053 Write leveling (Byte 1): 27 => 27
8388 13:21:57.008268 DramcWriteLeveling(PI) end<-----
8389 13:21:57.008362
8390 13:21:57.008447 ==
8391 13:21:57.011559 Dram Type= 6, Freq= 0, CH_1, rank 0
8392 13:21:57.014750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8393 13:21:57.018282 ==
8394 13:21:57.018380 [Gating] SW mode calibration
8395 13:21:57.028096 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8396 13:21:57.031365 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8397 13:21:57.034784 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 13:21:57.041606 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 13:21:57.044819 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 13:21:57.048035 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 13:21:57.055097 1 4 16 | B1->B0 | 2f2f 2a2a | 1 1 | (1 1) (1 1)
8402 13:21:57.058120 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8403 13:21:57.061342 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8404 13:21:57.068229 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8405 13:21:57.071440 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8406 13:21:57.075606 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8407 13:21:57.081697 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8408 13:21:57.084616 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8409 13:21:57.088524 1 5 16 | B1->B0 | 2828 3131 | 1 1 | (1 0) (1 0)
8410 13:21:57.094865 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 13:21:57.098316 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 13:21:57.101388 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 13:21:57.105132 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 13:21:57.111701 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 13:21:57.115203 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 13:21:57.118267 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 13:21:57.124977 1 6 16 | B1->B0 | 3838 2c2c | 0 0 | (0 0) (0 0)
8418 13:21:57.128449 1 6 20 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8419 13:21:57.131751 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 13:21:57.138759 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 13:21:57.141497 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8422 13:21:57.144863 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 13:21:57.151720 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 13:21:57.154980 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8425 13:21:57.158720 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8426 13:21:57.165093 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 13:21:57.168780 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 13:21:57.171534 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 13:21:57.178521 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 13:21:57.182058 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 13:21:57.185041 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 13:21:57.191633 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 13:21:57.194918 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 13:21:57.198227 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 13:21:57.202063 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 13:21:57.208218 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 13:21:57.211691 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 13:21:57.215033 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 13:21:57.221884 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 13:21:57.225282 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8441 13:21:57.228951 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8442 13:21:57.235018 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 13:21:57.235116 Total UI for P1: 0, mck2ui 16
8444 13:21:57.241579 best dqsien dly found for B0: ( 1, 9, 14)
8445 13:21:57.241684 Total UI for P1: 0, mck2ui 16
8446 13:21:57.248502 best dqsien dly found for B1: ( 1, 9, 14)
8447 13:21:57.251743 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8448 13:21:57.255197 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8449 13:21:57.255297
8450 13:21:57.258601 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8451 13:21:57.261971 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8452 13:21:57.265465 [Gating] SW calibration Done
8453 13:21:57.265537 ==
8454 13:21:57.268540 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 13:21:57.271890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 13:21:57.271987 ==
8457 13:21:57.275295 RX Vref Scan: 0
8458 13:21:57.275391
8459 13:21:57.275477 RX Vref 0 -> 0, step: 1
8460 13:21:57.275560
8461 13:21:57.278661 RX Delay 0 -> 252, step: 8
8462 13:21:57.281751 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8463 13:21:57.285444 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8464 13:21:57.291834 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8465 13:21:57.295214 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8466 13:21:57.299110 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8467 13:21:57.301663 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8468 13:21:57.305140 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8469 13:21:57.311959 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8470 13:21:57.315954 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8471 13:21:57.318378 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8472 13:21:57.322209 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8473 13:21:57.325341 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8474 13:21:57.331939 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8475 13:21:57.335333 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8476 13:21:57.339030 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8477 13:21:57.342008 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8478 13:21:57.342105 ==
8479 13:21:57.345894 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 13:21:57.352704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 13:21:57.352815 ==
8482 13:21:57.352879 DQS Delay:
8483 13:21:57.352937 DQS0 = 0, DQS1 = 0
8484 13:21:57.355659 DQM Delay:
8485 13:21:57.355754 DQM0 = 134, DQM1 = 126
8486 13:21:57.358816 DQ Delay:
8487 13:21:57.362048 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8488 13:21:57.365975 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8489 13:21:57.368862 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8490 13:21:57.372352 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8491 13:21:57.372422
8492 13:21:57.372481
8493 13:21:57.372564 ==
8494 13:21:57.375217 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 13:21:57.378835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 13:21:57.378930 ==
8497 13:21:57.379020
8498 13:21:57.382320
8499 13:21:57.382389 TX Vref Scan disable
8500 13:21:57.385333 == TX Byte 0 ==
8501 13:21:57.388727 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8502 13:21:57.392058 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8503 13:21:57.395552 == TX Byte 1 ==
8504 13:21:57.398862 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8505 13:21:57.402145 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8506 13:21:57.402246 ==
8507 13:21:57.405571 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 13:21:57.409021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 13:21:57.412225 ==
8510 13:21:57.425008
8511 13:21:57.428228 TX Vref early break, caculate TX vref
8512 13:21:57.431901 TX Vref=16, minBit 8, minWin=21, winSum=362
8513 13:21:57.435431 TX Vref=18, minBit 8, minWin=21, winSum=376
8514 13:21:57.438470 TX Vref=20, minBit 9, minWin=22, winSum=388
8515 13:21:57.441767 TX Vref=22, minBit 8, minWin=23, winSum=397
8516 13:21:57.445031 TX Vref=24, minBit 5, minWin=24, winSum=408
8517 13:21:57.448135 TX Vref=26, minBit 5, minWin=25, winSum=417
8518 13:21:57.455417 TX Vref=28, minBit 8, minWin=25, winSum=421
8519 13:21:57.458514 TX Vref=30, minBit 9, minWin=25, winSum=420
8520 13:21:57.462120 TX Vref=32, minBit 0, minWin=24, winSum=412
8521 13:21:57.465039 TX Vref=34, minBit 0, minWin=24, winSum=400
8522 13:21:57.468372 TX Vref=36, minBit 9, minWin=22, winSum=387
8523 13:21:57.475121 [TxChooseVref] Worse bit 8, Min win 25, Win sum 421, Final Vref 28
8524 13:21:57.475223
8525 13:21:57.478396 Final TX Range 0 Vref 28
8526 13:21:57.478470
8527 13:21:57.478531 ==
8528 13:21:57.481908 Dram Type= 6, Freq= 0, CH_1, rank 0
8529 13:21:57.485060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8530 13:21:57.485163 ==
8531 13:21:57.485256
8532 13:21:57.485342
8533 13:21:57.488548 TX Vref Scan disable
8534 13:21:57.495200 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8535 13:21:57.495300 == TX Byte 0 ==
8536 13:21:57.498480 u2DelayCellOfst[0]=17 cells (5 PI)
8537 13:21:57.502152 u2DelayCellOfst[1]=14 cells (4 PI)
8538 13:21:57.505432 u2DelayCellOfst[2]=0 cells (0 PI)
8539 13:21:57.508330 u2DelayCellOfst[3]=7 cells (2 PI)
8540 13:21:57.511913 u2DelayCellOfst[4]=7 cells (2 PI)
8541 13:21:57.514925 u2DelayCellOfst[5]=17 cells (5 PI)
8542 13:21:57.518237 u2DelayCellOfst[6]=17 cells (5 PI)
8543 13:21:57.518309 u2DelayCellOfst[7]=7 cells (2 PI)
8544 13:21:57.525002 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8545 13:21:57.528261 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8546 13:21:57.528358 == TX Byte 1 ==
8547 13:21:57.531995 u2DelayCellOfst[8]=0 cells (0 PI)
8548 13:21:57.535064 u2DelayCellOfst[9]=3 cells (1 PI)
8549 13:21:57.538770 u2DelayCellOfst[10]=10 cells (3 PI)
8550 13:21:57.541855 u2DelayCellOfst[11]=7 cells (2 PI)
8551 13:21:57.545363 u2DelayCellOfst[12]=14 cells (4 PI)
8552 13:21:57.548470 u2DelayCellOfst[13]=17 cells (5 PI)
8553 13:21:57.552294 u2DelayCellOfst[14]=17 cells (5 PI)
8554 13:21:57.555087 u2DelayCellOfst[15]=17 cells (5 PI)
8555 13:21:57.558397 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8556 13:21:57.561902 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8557 13:21:57.565109 DramC Write-DBI on
8558 13:21:57.565184 ==
8559 13:21:57.568427 Dram Type= 6, Freq= 0, CH_1, rank 0
8560 13:21:57.571783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8561 13:21:57.571880 ==
8562 13:21:57.571967
8563 13:21:57.572056
8564 13:21:57.575021 TX Vref Scan disable
8565 13:21:57.578691 == TX Byte 0 ==
8566 13:21:57.581992 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8567 13:21:57.585358 == TX Byte 1 ==
8568 13:21:57.588598 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8569 13:21:57.588734 DramC Write-DBI off
8570 13:21:57.588830
8571 13:21:57.592260 [DATLAT]
8572 13:21:57.592349 Freq=1600, CH1 RK0
8573 13:21:57.592440
8574 13:21:57.595543 DATLAT Default: 0xf
8575 13:21:57.595640 0, 0xFFFF, sum = 0
8576 13:21:57.598764 1, 0xFFFF, sum = 0
8577 13:21:57.598866 2, 0xFFFF, sum = 0
8578 13:21:57.601861 3, 0xFFFF, sum = 0
8579 13:21:57.601933 4, 0xFFFF, sum = 0
8580 13:21:57.605124 5, 0xFFFF, sum = 0
8581 13:21:57.605221 6, 0xFFFF, sum = 0
8582 13:21:57.608575 7, 0xFFFF, sum = 0
8583 13:21:57.608709 8, 0xFFFF, sum = 0
8584 13:21:57.611760 9, 0xFFFF, sum = 0
8585 13:21:57.611863 10, 0xFFFF, sum = 0
8586 13:21:57.615197 11, 0xFFFF, sum = 0
8587 13:21:57.618464 12, 0xFFFF, sum = 0
8588 13:21:57.618540 13, 0xFFFF, sum = 0
8589 13:21:57.621704 14, 0x0, sum = 1
8590 13:21:57.621781 15, 0x0, sum = 2
8591 13:21:57.625454 16, 0x0, sum = 3
8592 13:21:57.625556 17, 0x0, sum = 4
8593 13:21:57.625645 best_step = 15
8594 13:21:57.625735
8595 13:21:57.628576 ==
8596 13:21:57.631878 Dram Type= 6, Freq= 0, CH_1, rank 0
8597 13:21:57.635025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8598 13:21:57.635125 ==
8599 13:21:57.635211 RX Vref Scan: 1
8600 13:21:57.635282
8601 13:21:57.638269 Set Vref Range= 24 -> 127
8602 13:21:57.638340
8603 13:21:57.641848 RX Vref 24 -> 127, step: 1
8604 13:21:57.641947
8605 13:21:57.645118 RX Delay 11 -> 252, step: 4
8606 13:21:57.645196
8607 13:21:57.648861 Set Vref, RX VrefLevel [Byte0]: 24
8608 13:21:57.651678 [Byte1]: 24
8609 13:21:57.651778
8610 13:21:57.655242 Set Vref, RX VrefLevel [Byte0]: 25
8611 13:21:57.658397 [Byte1]: 25
8612 13:21:57.658495
8613 13:21:57.662102 Set Vref, RX VrefLevel [Byte0]: 26
8614 13:21:57.665510 [Byte1]: 26
8615 13:21:57.665582
8616 13:21:57.668489 Set Vref, RX VrefLevel [Byte0]: 27
8617 13:21:57.672211 [Byte1]: 27
8618 13:21:57.675898
8619 13:21:57.676003 Set Vref, RX VrefLevel [Byte0]: 28
8620 13:21:57.679831 [Byte1]: 28
8621 13:21:57.683932
8622 13:21:57.684030 Set Vref, RX VrefLevel [Byte0]: 29
8623 13:21:57.686959 [Byte1]: 29
8624 13:21:57.691419
8625 13:21:57.691499 Set Vref, RX VrefLevel [Byte0]: 30
8626 13:21:57.694459 [Byte1]: 30
8627 13:21:57.699031
8628 13:21:57.699110 Set Vref, RX VrefLevel [Byte0]: 31
8629 13:21:57.702310 [Byte1]: 31
8630 13:21:57.706652
8631 13:21:57.706731 Set Vref, RX VrefLevel [Byte0]: 32
8632 13:21:57.709927 [Byte1]: 32
8633 13:21:57.713977
8634 13:21:57.714056 Set Vref, RX VrefLevel [Byte0]: 33
8635 13:21:57.717285 [Byte1]: 33
8636 13:21:57.721620
8637 13:21:57.721700 Set Vref, RX VrefLevel [Byte0]: 34
8638 13:21:57.725284 [Byte1]: 34
8639 13:21:57.729468
8640 13:21:57.729548 Set Vref, RX VrefLevel [Byte0]: 35
8641 13:21:57.732578 [Byte1]: 35
8642 13:21:57.736642
8643 13:21:57.736773 Set Vref, RX VrefLevel [Byte0]: 36
8644 13:21:57.740632 [Byte1]: 36
8645 13:21:57.744688
8646 13:21:57.744781 Set Vref, RX VrefLevel [Byte0]: 37
8647 13:21:57.747939 [Byte1]: 37
8648 13:21:57.751904
8649 13:21:57.751984 Set Vref, RX VrefLevel [Byte0]: 38
8650 13:21:57.755329 [Byte1]: 38
8651 13:21:57.759804
8652 13:21:57.759884 Set Vref, RX VrefLevel [Byte0]: 39
8653 13:21:57.763105 [Byte1]: 39
8654 13:21:57.767184
8655 13:21:57.767263 Set Vref, RX VrefLevel [Byte0]: 40
8656 13:21:57.770636 [Byte1]: 40
8657 13:21:57.774876
8658 13:21:57.774955 Set Vref, RX VrefLevel [Byte0]: 41
8659 13:21:57.778278 [Byte1]: 41
8660 13:21:57.782396
8661 13:21:57.782475 Set Vref, RX VrefLevel [Byte0]: 42
8662 13:21:57.786060 [Byte1]: 42
8663 13:21:57.789985
8664 13:21:57.790064 Set Vref, RX VrefLevel [Byte0]: 43
8665 13:21:57.793415 [Byte1]: 43
8666 13:21:57.798225
8667 13:21:57.798305 Set Vref, RX VrefLevel [Byte0]: 44
8668 13:21:57.801037 [Byte1]: 44
8669 13:21:57.805841
8670 13:21:57.805920 Set Vref, RX VrefLevel [Byte0]: 45
8671 13:21:57.808586 [Byte1]: 45
8672 13:21:57.812886
8673 13:21:57.812980 Set Vref, RX VrefLevel [Byte0]: 46
8674 13:21:57.816379 [Byte1]: 46
8675 13:21:57.820633
8676 13:21:57.820760 Set Vref, RX VrefLevel [Byte0]: 47
8677 13:21:57.823879 [Byte1]: 47
8678 13:21:57.828403
8679 13:21:57.828482 Set Vref, RX VrefLevel [Byte0]: 48
8680 13:21:57.831516 [Byte1]: 48
8681 13:21:57.835728
8682 13:21:57.835811 Set Vref, RX VrefLevel [Byte0]: 49
8683 13:21:57.839362 [Byte1]: 49
8684 13:21:57.843630
8685 13:21:57.843710 Set Vref, RX VrefLevel [Byte0]: 50
8686 13:21:57.846622 [Byte1]: 50
8687 13:21:57.851015
8688 13:21:57.851110 Set Vref, RX VrefLevel [Byte0]: 51
8689 13:21:57.854620 [Byte1]: 51
8690 13:21:57.859629
8691 13:21:57.859708 Set Vref, RX VrefLevel [Byte0]: 52
8692 13:21:57.862126 [Byte1]: 52
8693 13:21:57.866064
8694 13:21:57.866144 Set Vref, RX VrefLevel [Byte0]: 53
8695 13:21:57.869477 [Byte1]: 53
8696 13:21:57.874497
8697 13:21:57.874599 Set Vref, RX VrefLevel [Byte0]: 54
8698 13:21:57.877513 [Byte1]: 54
8699 13:21:57.881758
8700 13:21:57.881838 Set Vref, RX VrefLevel [Byte0]: 55
8701 13:21:57.884587 [Byte1]: 55
8702 13:21:57.888890
8703 13:21:57.888969 Set Vref, RX VrefLevel [Byte0]: 56
8704 13:21:57.892553 [Byte1]: 56
8705 13:21:57.896590
8706 13:21:57.896677 Set Vref, RX VrefLevel [Byte0]: 57
8707 13:21:57.900285 [Byte1]: 57
8708 13:21:57.904996
8709 13:21:57.905075 Set Vref, RX VrefLevel [Byte0]: 58
8710 13:21:57.907823 [Byte1]: 58
8711 13:21:57.912088
8712 13:21:57.912168 Set Vref, RX VrefLevel [Byte0]: 59
8713 13:21:57.915600 [Byte1]: 59
8714 13:21:57.919522
8715 13:21:57.919601 Set Vref, RX VrefLevel [Byte0]: 60
8716 13:21:57.923148 [Byte1]: 60
8717 13:21:57.927071
8718 13:21:57.927150 Set Vref, RX VrefLevel [Byte0]: 61
8719 13:21:57.930472 [Byte1]: 61
8720 13:21:57.934701
8721 13:21:57.934807 Set Vref, RX VrefLevel [Byte0]: 62
8722 13:21:57.937848 [Byte1]: 62
8723 13:21:57.942710
8724 13:21:57.942818 Set Vref, RX VrefLevel [Byte0]: 63
8725 13:21:57.945646 [Byte1]: 63
8726 13:21:57.949907
8727 13:21:57.949987 Set Vref, RX VrefLevel [Byte0]: 64
8728 13:21:57.953183 [Byte1]: 64
8729 13:21:57.957510
8730 13:21:57.957590 Set Vref, RX VrefLevel [Byte0]: 65
8731 13:21:57.961026 [Byte1]: 65
8732 13:21:57.965613
8733 13:21:57.965693 Set Vref, RX VrefLevel [Byte0]: 66
8734 13:21:57.968488 [Byte1]: 66
8735 13:21:57.972932
8736 13:21:57.973012 Set Vref, RX VrefLevel [Byte0]: 67
8737 13:21:57.976055 [Byte1]: 67
8738 13:21:57.980438
8739 13:21:57.980517 Set Vref, RX VrefLevel [Byte0]: 68
8740 13:21:57.983860 [Byte1]: 68
8741 13:21:57.988863
8742 13:21:57.988942 Set Vref, RX VrefLevel [Byte0]: 69
8743 13:21:57.991563 [Byte1]: 69
8744 13:21:57.995835
8745 13:21:57.995914 Set Vref, RX VrefLevel [Byte0]: 70
8746 13:21:57.998787 [Byte1]: 70
8747 13:21:58.003347
8748 13:21:58.003426 Set Vref, RX VrefLevel [Byte0]: 71
8749 13:21:58.006807 [Byte1]: 71
8750 13:21:58.010925
8751 13:21:58.011004 Set Vref, RX VrefLevel [Byte0]: 72
8752 13:21:58.014372 [Byte1]: 72
8753 13:21:58.018289
8754 13:21:58.022442 Set Vref, RX VrefLevel [Byte0]: 73
8755 13:21:58.022522 [Byte1]: 73
8756 13:21:58.025991
8757 13:21:58.026071 Set Vref, RX VrefLevel [Byte0]: 74
8758 13:21:58.029575 [Byte1]: 74
8759 13:21:58.033585
8760 13:21:58.033664 Set Vref, RX VrefLevel [Byte0]: 75
8761 13:21:58.036825 [Byte1]: 75
8762 13:21:58.041777
8763 13:21:58.041857 Final RX Vref Byte 0 = 60 to rank0
8764 13:21:58.044822 Final RX Vref Byte 1 = 56 to rank0
8765 13:21:58.048021 Final RX Vref Byte 0 = 60 to rank1
8766 13:21:58.051394 Final RX Vref Byte 1 = 56 to rank1==
8767 13:21:58.054884 Dram Type= 6, Freq= 0, CH_1, rank 0
8768 13:21:58.058372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8769 13:21:58.061948 ==
8770 13:21:58.062028 DQS Delay:
8771 13:21:58.062090 DQS0 = 0, DQS1 = 0
8772 13:21:58.065251 DQM Delay:
8773 13:21:58.065330 DQM0 = 131, DQM1 = 124
8774 13:21:58.068082 DQ Delay:
8775 13:21:58.071565 DQ0 =136, DQ1 =124, DQ2 =120, DQ3 =128
8776 13:21:58.074710 DQ4 =130, DQ5 =142, DQ6 =144, DQ7 =126
8777 13:21:58.078470 DQ8 =110, DQ9 =112, DQ10 =126, DQ11 =118
8778 13:21:58.081811 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8779 13:21:58.081892
8780 13:21:58.081954
8781 13:21:58.082012
8782 13:21:58.085087 [DramC_TX_OE_Calibration] TA2
8783 13:21:58.088081 Original DQ_B0 (3 6) =30, OEN = 27
8784 13:21:58.091376 Original DQ_B1 (3 6) =30, OEN = 27
8785 13:21:58.091456 24, 0x0, End_B0=24 End_B1=24
8786 13:21:58.095077 25, 0x0, End_B0=25 End_B1=25
8787 13:21:58.098246 26, 0x0, End_B0=26 End_B1=26
8788 13:21:58.102458 27, 0x0, End_B0=27 End_B1=27
8789 13:21:58.105601 28, 0x0, End_B0=28 End_B1=28
8790 13:21:58.105682 29, 0x0, End_B0=29 End_B1=29
8791 13:21:58.108566 30, 0x0, End_B0=30 End_B1=30
8792 13:21:58.111662 31, 0x4545, End_B0=30 End_B1=30
8793 13:21:58.115318 Byte0 end_step=30 best_step=27
8794 13:21:58.118695 Byte1 end_step=30 best_step=27
8795 13:21:58.118775 Byte0 TX OE(2T, 0.5T) = (3, 3)
8796 13:21:58.122019 Byte1 TX OE(2T, 0.5T) = (3, 3)
8797 13:21:58.122099
8798 13:21:58.122161
8799 13:21:58.131981 [DQSOSCAuto] RK0, (LSB)MR18= 0x1600, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 398 ps
8800 13:21:58.135069 CH1 RK0: MR19=303, MR18=1600
8801 13:21:58.139155 CH1_RK0: MR19=0x303, MR18=0x1600, DQSOSC=398, MR23=63, INC=23, DEC=15
8802 13:21:58.139235
8803 13:21:58.141750 ----->DramcWriteLeveling(PI) begin...
8804 13:21:58.145192 ==
8805 13:21:58.148480 Dram Type= 6, Freq= 0, CH_1, rank 1
8806 13:21:58.151728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8807 13:21:58.151810 ==
8808 13:21:58.155374 Write leveling (Byte 0): 26 => 26
8809 13:21:58.158465 Write leveling (Byte 1): 26 => 26
8810 13:21:58.162237 DramcWriteLeveling(PI) end<-----
8811 13:21:58.162316
8812 13:21:58.162378 ==
8813 13:21:58.165774 Dram Type= 6, Freq= 0, CH_1, rank 1
8814 13:21:58.168831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8815 13:21:58.168911 ==
8816 13:21:58.172064 [Gating] SW mode calibration
8817 13:21:58.178902 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8818 13:21:58.182190 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8819 13:21:58.188553 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 13:21:58.191880 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 13:21:58.195609 1 4 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
8822 13:21:58.201904 1 4 12 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8823 13:21:58.205633 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8824 13:21:58.208858 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8825 13:21:58.215251 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8826 13:21:58.218671 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8827 13:21:58.222100 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8828 13:21:58.228644 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8829 13:21:58.231849 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
8830 13:21:58.235314 1 5 12 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
8831 13:21:58.242060 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8832 13:21:58.245564 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 13:21:58.248864 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 13:21:58.255503 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 13:21:58.258769 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 13:21:58.262782 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8837 13:21:58.265640 1 6 8 | B1->B0 | 2525 4242 | 0 0 | (0 0) (0 0)
8838 13:21:58.272318 1 6 12 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
8839 13:21:58.275704 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 13:21:58.278753 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 13:21:58.285489 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 13:21:58.288946 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 13:21:58.292489 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 13:21:58.299271 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8845 13:21:58.302144 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8846 13:21:58.305571 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8847 13:21:58.312198 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8848 13:21:58.315539 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 13:21:58.318956 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 13:21:58.325442 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 13:21:58.329022 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 13:21:58.332443 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 13:21:58.335549 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 13:21:58.342307 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 13:21:58.345531 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 13:21:58.348869 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 13:21:58.355630 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 13:21:58.360647 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 13:21:58.362517 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 13:21:58.369257 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 13:21:58.372447 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8862 13:21:58.376060 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8863 13:21:58.379262 Total UI for P1: 0, mck2ui 16
8864 13:21:58.382133 best dqsien dly found for B0: ( 1, 9, 8)
8865 13:21:58.388943 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8866 13:21:58.392464 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 13:21:58.395663 Total UI for P1: 0, mck2ui 16
8868 13:21:58.399490 best dqsien dly found for B1: ( 1, 9, 14)
8869 13:21:58.402370 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8870 13:21:58.405925 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8871 13:21:58.406005
8872 13:21:58.409007 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8873 13:21:58.413195 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8874 13:21:58.415837 [Gating] SW calibration Done
8875 13:21:58.415917 ==
8876 13:21:58.419372 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 13:21:58.422302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 13:21:58.422381 ==
8879 13:21:58.425965 RX Vref Scan: 0
8880 13:21:58.426045
8881 13:21:58.429584 RX Vref 0 -> 0, step: 1
8882 13:21:58.429664
8883 13:21:58.429726 RX Delay 0 -> 252, step: 8
8884 13:21:58.435862 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8885 13:21:58.439539 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8886 13:21:58.442482 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8887 13:21:58.445861 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8888 13:21:58.449235 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8889 13:21:58.452520 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8890 13:21:58.459200 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8891 13:21:58.462661 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8892 13:21:58.465895 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8893 13:21:58.469305 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8894 13:21:58.472514 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8895 13:21:58.479398 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8896 13:21:58.482621 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8897 13:21:58.486052 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8898 13:21:58.489643 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8899 13:21:58.496030 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8900 13:21:58.496111 ==
8901 13:21:58.499654 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 13:21:58.502784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 13:21:58.502865 ==
8904 13:21:58.502928 DQS Delay:
8905 13:21:58.505972 DQS0 = 0, DQS1 = 0
8906 13:21:58.506052 DQM Delay:
8907 13:21:58.509317 DQM0 = 132, DQM1 = 127
8908 13:21:58.509396 DQ Delay:
8909 13:21:58.512578 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8910 13:21:58.516002 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8911 13:21:58.519689 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8912 13:21:58.522636 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8913 13:21:58.522714
8914 13:21:58.522777
8915 13:21:58.522834 ==
8916 13:21:58.526323 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 13:21:58.532595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 13:21:58.532721 ==
8919 13:21:58.532836
8920 13:21:58.532927
8921 13:21:58.533013 TX Vref Scan disable
8922 13:21:58.536184 == TX Byte 0 ==
8923 13:21:58.539387 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8924 13:21:58.542752 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8925 13:21:58.546333 == TX Byte 1 ==
8926 13:21:58.549606 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8927 13:21:58.553217 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8928 13:21:58.556411 ==
8929 13:21:58.560150 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 13:21:58.563160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 13:21:58.563258 ==
8932 13:21:58.575988
8933 13:21:58.579770 TX Vref early break, caculate TX vref
8934 13:21:58.582811 TX Vref=16, minBit 0, minWin=23, winSum=377
8935 13:21:58.586292 TX Vref=18, minBit 0, minWin=24, winSum=393
8936 13:21:58.589285 TX Vref=20, minBit 5, minWin=24, winSum=399
8937 13:21:58.592639 TX Vref=22, minBit 8, minWin=24, winSum=406
8938 13:21:58.595989 TX Vref=24, minBit 0, minWin=25, winSum=416
8939 13:21:58.602827 TX Vref=26, minBit 6, minWin=25, winSum=422
8940 13:21:58.606178 TX Vref=28, minBit 0, minWin=26, winSum=424
8941 13:21:58.609379 TX Vref=30, minBit 15, minWin=25, winSum=427
8942 13:21:58.612582 TX Vref=32, minBit 0, minWin=25, winSum=418
8943 13:21:58.616087 TX Vref=34, minBit 3, minWin=24, winSum=409
8944 13:21:58.619611 TX Vref=36, minBit 0, minWin=23, winSum=399
8945 13:21:58.626016 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
8946 13:21:58.626090
8947 13:21:58.629961 Final TX Range 0 Vref 28
8948 13:21:58.630066
8949 13:21:58.630131 ==
8950 13:21:58.633265 Dram Type= 6, Freq= 0, CH_1, rank 1
8951 13:21:58.636115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8952 13:21:58.636190 ==
8953 13:21:58.636257
8954 13:21:58.636315
8955 13:21:58.639416 TX Vref Scan disable
8956 13:21:58.646097 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8957 13:21:58.646194 == TX Byte 0 ==
8958 13:21:58.649346 u2DelayCellOfst[0]=17 cells (5 PI)
8959 13:21:58.653332 u2DelayCellOfst[1]=10 cells (3 PI)
8960 13:21:58.656198 u2DelayCellOfst[2]=0 cells (0 PI)
8961 13:21:58.659553 u2DelayCellOfst[3]=7 cells (2 PI)
8962 13:21:58.662718 u2DelayCellOfst[4]=10 cells (3 PI)
8963 13:21:58.666443 u2DelayCellOfst[5]=17 cells (5 PI)
8964 13:21:58.669878 u2DelayCellOfst[6]=17 cells (5 PI)
8965 13:21:58.669951 u2DelayCellOfst[7]=7 cells (2 PI)
8966 13:21:58.676481 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8967 13:21:58.680037 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8968 13:21:58.680124 == TX Byte 1 ==
8969 13:21:58.683225 u2DelayCellOfst[8]=0 cells (0 PI)
8970 13:21:58.686486 u2DelayCellOfst[9]=3 cells (1 PI)
8971 13:21:58.689705 u2DelayCellOfst[10]=10 cells (3 PI)
8972 13:21:58.693033 u2DelayCellOfst[11]=3 cells (1 PI)
8973 13:21:58.696289 u2DelayCellOfst[12]=10 cells (3 PI)
8974 13:21:58.699502 u2DelayCellOfst[13]=14 cells (4 PI)
8975 13:21:58.703204 u2DelayCellOfst[14]=17 cells (5 PI)
8976 13:21:58.706422 u2DelayCellOfst[15]=14 cells (4 PI)
8977 13:21:58.709987 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8978 13:21:58.716423 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8979 13:21:58.716504 DramC Write-DBI on
8980 13:21:58.716566 ==
8981 13:21:58.719735 Dram Type= 6, Freq= 0, CH_1, rank 1
8982 13:21:58.722932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8983 13:21:58.723006 ==
8984 13:21:58.723071
8985 13:21:58.726195
8986 13:21:58.726268 TX Vref Scan disable
8987 13:21:58.730036 == TX Byte 0 ==
8988 13:21:58.732859 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8989 13:21:58.736148 == TX Byte 1 ==
8990 13:21:58.739937 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8991 13:21:58.740040 DramC Write-DBI off
8992 13:21:58.740133
8993 13:21:58.742797 [DATLAT]
8994 13:21:58.742909 Freq=1600, CH1 RK1
8995 13:21:58.743000
8996 13:21:58.746350 DATLAT Default: 0xf
8997 13:21:58.746457 0, 0xFFFF, sum = 0
8998 13:21:58.750108 1, 0xFFFF, sum = 0
8999 13:21:58.750194 2, 0xFFFF, sum = 0
9000 13:21:58.753202 3, 0xFFFF, sum = 0
9001 13:21:58.753276 4, 0xFFFF, sum = 0
9002 13:21:58.756246 5, 0xFFFF, sum = 0
9003 13:21:58.756349 6, 0xFFFF, sum = 0
9004 13:21:58.759463 7, 0xFFFF, sum = 0
9005 13:21:58.759538 8, 0xFFFF, sum = 0
9006 13:21:58.762740 9, 0xFFFF, sum = 0
9007 13:21:58.766851 10, 0xFFFF, sum = 0
9008 13:21:58.766950 11, 0xFFFF, sum = 0
9009 13:21:58.769524 12, 0xFFFF, sum = 0
9010 13:21:58.769599 13, 0xFFFF, sum = 0
9011 13:21:58.772953 14, 0x0, sum = 1
9012 13:21:58.773031 15, 0x0, sum = 2
9013 13:21:58.776206 16, 0x0, sum = 3
9014 13:21:58.776304 17, 0x0, sum = 4
9015 13:21:58.776392 best_step = 15
9016 13:21:58.779527
9017 13:21:58.779604 ==
9018 13:21:58.783472 Dram Type= 6, Freq= 0, CH_1, rank 1
9019 13:21:58.785997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9020 13:21:58.786103 ==
9021 13:21:58.786196 RX Vref Scan: 0
9022 13:21:58.786281
9023 13:21:58.789432 RX Vref 0 -> 0, step: 1
9024 13:21:58.789530
9025 13:21:58.793002 RX Delay 11 -> 252, step: 4
9026 13:21:58.796624 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
9027 13:21:58.799522 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9028 13:21:58.805989 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9029 13:21:58.809498 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9030 13:21:58.812874 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
9031 13:21:58.816411 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9032 13:21:58.819431 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9033 13:21:58.826307 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
9034 13:21:58.829271 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9035 13:21:58.833337 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9036 13:21:58.836064 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9037 13:21:58.839806 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
9038 13:21:58.846805 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9039 13:21:58.849626 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9040 13:21:58.853096 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9041 13:21:58.856191 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
9042 13:21:58.856290 ==
9043 13:21:58.859605 Dram Type= 6, Freq= 0, CH_1, rank 1
9044 13:21:58.866287 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9045 13:21:58.866389 ==
9046 13:21:58.866479 DQS Delay:
9047 13:21:58.866577 DQS0 = 0, DQS1 = 0
9048 13:21:58.869865 DQM Delay:
9049 13:21:58.869960 DQM0 = 130, DQM1 = 126
9050 13:21:58.873714 DQ Delay:
9051 13:21:58.876578 DQ0 =132, DQ1 =126, DQ2 =118, DQ3 =126
9052 13:21:58.879772 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126
9053 13:21:58.883101 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9054 13:21:58.886488 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
9055 13:21:58.886580
9056 13:21:58.886641
9057 13:21:58.886699
9058 13:21:58.889410 [DramC_TX_OE_Calibration] TA2
9059 13:21:58.893162 Original DQ_B0 (3 6) =30, OEN = 27
9060 13:21:58.896436 Original DQ_B1 (3 6) =30, OEN = 27
9061 13:21:58.899458 24, 0x0, End_B0=24 End_B1=24
9062 13:21:58.899560 25, 0x0, End_B0=25 End_B1=25
9063 13:21:58.902860 26, 0x0, End_B0=26 End_B1=26
9064 13:21:58.906193 27, 0x0, End_B0=27 End_B1=27
9065 13:21:58.909516 28, 0x0, End_B0=28 End_B1=28
9066 13:21:58.909587 29, 0x0, End_B0=29 End_B1=29
9067 13:21:58.913417 30, 0x0, End_B0=30 End_B1=30
9068 13:21:58.916200 31, 0x4141, End_B0=30 End_B1=30
9069 13:21:58.919445 Byte0 end_step=30 best_step=27
9070 13:21:58.923163 Byte1 end_step=30 best_step=27
9071 13:21:58.926381 Byte0 TX OE(2T, 0.5T) = (3, 3)
9072 13:21:58.926477 Byte1 TX OE(2T, 0.5T) = (3, 3)
9073 13:21:58.926564
9074 13:21:58.930029
9075 13:21:58.936246 [DQSOSCAuto] RK1, (LSB)MR18= 0x1318, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
9076 13:21:58.939619 CH1 RK1: MR19=303, MR18=1318
9077 13:21:58.946347 CH1_RK1: MR19=0x303, MR18=0x1318, DQSOSC=397, MR23=63, INC=23, DEC=15
9078 13:21:58.946422 [RxdqsGatingPostProcess] freq 1600
9079 13:21:58.953221 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9080 13:21:58.956546 best DQS0 dly(2T, 0.5T) = (1, 1)
9081 13:21:58.960037 best DQS1 dly(2T, 0.5T) = (1, 1)
9082 13:21:58.963482 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9083 13:21:58.966591 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9084 13:21:58.969919 best DQS0 dly(2T, 0.5T) = (1, 1)
9085 13:21:58.973063 best DQS1 dly(2T, 0.5T) = (1, 1)
9086 13:21:58.976637 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9087 13:21:58.979720 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9088 13:21:58.979809 Pre-setting of DQS Precalculation
9089 13:21:58.986400 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9090 13:21:58.993001 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9091 13:21:58.999871 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9092 13:21:58.999945
9093 13:21:59.000014
9094 13:21:59.003438 [Calibration Summary] 3200 Mbps
9095 13:21:59.006373 CH 0, Rank 0
9096 13:21:59.006444 SW Impedance : PASS
9097 13:21:59.009943 DUTY Scan : NO K
9098 13:21:59.010022 ZQ Calibration : PASS
9099 13:21:59.013257 Jitter Meter : NO K
9100 13:21:59.016317 CBT Training : PASS
9101 13:21:59.016397 Write leveling : PASS
9102 13:21:59.020278 RX DQS gating : PASS
9103 13:21:59.023216 RX DQ/DQS(RDDQC) : PASS
9104 13:21:59.023295 TX DQ/DQS : PASS
9105 13:21:59.026480 RX DATLAT : PASS
9106 13:21:59.030012 RX DQ/DQS(Engine): PASS
9107 13:21:59.030091 TX OE : PASS
9108 13:21:59.033083 All Pass.
9109 13:21:59.033163
9110 13:21:59.033225 CH 0, Rank 1
9111 13:21:59.036445 SW Impedance : PASS
9112 13:21:59.036525 DUTY Scan : NO K
9113 13:21:59.040164 ZQ Calibration : PASS
9114 13:21:59.043161 Jitter Meter : NO K
9115 13:21:59.043240 CBT Training : PASS
9116 13:21:59.046288 Write leveling : PASS
9117 13:21:59.049725 RX DQS gating : PASS
9118 13:21:59.049805 RX DQ/DQS(RDDQC) : PASS
9119 13:21:59.053364 TX DQ/DQS : PASS
9120 13:21:59.053444 RX DATLAT : PASS
9121 13:21:59.056578 RX DQ/DQS(Engine): PASS
9122 13:21:59.059959 TX OE : PASS
9123 13:21:59.060039 All Pass.
9124 13:21:59.060102
9125 13:21:59.060161 CH 1, Rank 0
9126 13:21:59.063177 SW Impedance : PASS
9127 13:21:59.066807 DUTY Scan : NO K
9128 13:21:59.066887 ZQ Calibration : PASS
9129 13:21:59.069899 Jitter Meter : NO K
9130 13:21:59.073134 CBT Training : PASS
9131 13:21:59.073213 Write leveling : PASS
9132 13:21:59.076468 RX DQS gating : PASS
9133 13:21:59.080045 RX DQ/DQS(RDDQC) : PASS
9134 13:21:59.080125 TX DQ/DQS : PASS
9135 13:21:59.083333 RX DATLAT : PASS
9136 13:21:59.083413 RX DQ/DQS(Engine): PASS
9137 13:21:59.086804 TX OE : PASS
9138 13:21:59.086884 All Pass.
9139 13:21:59.086948
9140 13:21:59.089914 CH 1, Rank 1
9141 13:21:59.089994 SW Impedance : PASS
9142 13:21:59.093236 DUTY Scan : NO K
9143 13:21:59.097037 ZQ Calibration : PASS
9144 13:21:59.097117 Jitter Meter : NO K
9145 13:21:59.100173 CBT Training : PASS
9146 13:21:59.103402 Write leveling : PASS
9147 13:21:59.103482 RX DQS gating : PASS
9148 13:21:59.106848 RX DQ/DQS(RDDQC) : PASS
9149 13:21:59.110281 TX DQ/DQS : PASS
9150 13:21:59.110361 RX DATLAT : PASS
9151 13:21:59.113546 RX DQ/DQS(Engine): PASS
9152 13:21:59.116903 TX OE : PASS
9153 13:21:59.116982 All Pass.
9154 13:21:59.117043
9155 13:21:59.117101 DramC Write-DBI on
9156 13:21:59.119879 PER_BANK_REFRESH: Hybrid Mode
9157 13:21:59.123370 TX_TRACKING: ON
9158 13:21:59.130280 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9159 13:21:59.140432 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9160 13:21:59.146899 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9161 13:21:59.150158 [FAST_K] Save calibration result to emmc
9162 13:21:59.153482 sync common calibartion params.
9163 13:21:59.153562 sync cbt_mode0:1, 1:1
9164 13:21:59.156676 dram_init: ddr_geometry: 2
9165 13:21:59.160337 dram_init: ddr_geometry: 2
9166 13:21:59.163777 dram_init: ddr_geometry: 2
9167 13:21:59.163857 0:dram_rank_size:100000000
9168 13:21:59.167032 1:dram_rank_size:100000000
9169 13:21:59.173253 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9170 13:21:59.173334 DFS_SHUFFLE_HW_MODE: ON
9171 13:21:59.180011 dramc_set_vcore_voltage set vcore to 725000
9172 13:21:59.180104 Read voltage for 1600, 0
9173 13:21:59.183575 Vio18 = 0
9174 13:21:59.183655 Vcore = 725000
9175 13:21:59.183717 Vdram = 0
9176 13:21:59.183776 Vddq = 0
9177 13:21:59.186865 Vmddr = 0
9178 13:21:59.186945 switch to 3200 Mbps bootup
9179 13:21:59.190266 [DramcRunTimeConfig]
9180 13:21:59.190345 PHYPLL
9181 13:21:59.193346 DPM_CONTROL_AFTERK: ON
9182 13:21:59.193425 PER_BANK_REFRESH: ON
9183 13:21:59.197011 REFRESH_OVERHEAD_REDUCTION: ON
9184 13:21:59.200190 CMD_PICG_NEW_MODE: OFF
9185 13:21:59.200269 XRTWTW_NEW_MODE: ON
9186 13:21:59.203508 XRTRTR_NEW_MODE: ON
9187 13:21:59.203589 TX_TRACKING: ON
9188 13:21:59.207113 RDSEL_TRACKING: OFF
9189 13:21:59.210713 DQS Precalculation for DVFS: ON
9190 13:21:59.210792 RX_TRACKING: OFF
9191 13:21:59.213508 HW_GATING DBG: ON
9192 13:21:59.213587 ZQCS_ENABLE_LP4: ON
9193 13:21:59.216647 RX_PICG_NEW_MODE: ON
9194 13:21:59.216768 TX_PICG_NEW_MODE: ON
9195 13:21:59.220770 ENABLE_RX_DCM_DPHY: ON
9196 13:21:59.223595 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9197 13:21:59.226945 DUMMY_READ_FOR_TRACKING: OFF
9198 13:21:59.227024 !!! SPM_CONTROL_AFTERK: OFF
9199 13:21:59.230207 !!! SPM could not control APHY
9200 13:21:59.233476 IMPEDANCE_TRACKING: ON
9201 13:21:59.233555 TEMP_SENSOR: ON
9202 13:21:59.236897 HW_SAVE_FOR_SR: OFF
9203 13:21:59.240297 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9204 13:21:59.243776 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9205 13:21:59.246971 Read ODT Tracking: ON
9206 13:21:59.247051 Refresh Rate DeBounce: ON
9207 13:21:59.250467 DFS_NO_QUEUE_FLUSH: ON
9208 13:21:59.253561 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9209 13:21:59.257172 ENABLE_DFS_RUNTIME_MRW: OFF
9210 13:21:59.257252 DDR_RESERVE_NEW_MODE: ON
9211 13:21:59.260605 MR_CBT_SWITCH_FREQ: ON
9212 13:21:59.263508 =========================
9213 13:21:59.280796 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9214 13:21:59.284087 dram_init: ddr_geometry: 2
9215 13:21:59.302202 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9216 13:21:59.305977 dram_init: dram init end (result: 0)
9217 13:21:59.312169 DRAM-K: Full calibration passed in 24555 msecs
9218 13:21:59.315763 MRC: failed to locate region type 0.
9219 13:21:59.315846 DRAM rank0 size:0x100000000,
9220 13:21:59.319072 DRAM rank1 size=0x100000000
9221 13:21:59.329140 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9222 13:21:59.335555 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9223 13:21:59.342702 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9224 13:21:59.349207 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9225 13:21:59.352327 DRAM rank0 size:0x100000000,
9226 13:21:59.355393 DRAM rank1 size=0x100000000
9227 13:21:59.355473 CBMEM:
9228 13:21:59.358981 IMD: root @ 0xfffff000 254 entries.
9229 13:21:59.362155 IMD: root @ 0xffffec00 62 entries.
9230 13:21:59.365833 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9231 13:21:59.369232 WARNING: RO_VPD is uninitialized or empty.
9232 13:21:59.375374 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9233 13:21:59.382611 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9234 13:21:59.395035 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9235 13:21:59.406898 BS: romstage times (exec / console): total (unknown) / 24063 ms
9236 13:21:59.406980
9237 13:21:59.407044
9238 13:21:59.416374 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9239 13:21:59.419862 ARM64: Exception handlers installed.
9240 13:21:59.423128 ARM64: Testing exception
9241 13:21:59.426780 ARM64: Done test exception
9242 13:21:59.426861 Enumerating buses...
9243 13:21:59.430090 Show all devs... Before device enumeration.
9244 13:21:59.433558 Root Device: enabled 1
9245 13:21:59.436781 CPU_CLUSTER: 0: enabled 1
9246 13:21:59.436881 CPU: 00: enabled 1
9247 13:21:59.439724 Compare with tree...
9248 13:21:59.439803 Root Device: enabled 1
9249 13:21:59.443446 CPU_CLUSTER: 0: enabled 1
9250 13:21:59.446606 CPU: 00: enabled 1
9251 13:21:59.446686 Root Device scanning...
9252 13:21:59.450016 scan_static_bus for Root Device
9253 13:21:59.453600 CPU_CLUSTER: 0 enabled
9254 13:21:59.456968 scan_static_bus for Root Device done
9255 13:21:59.459948 scan_bus: bus Root Device finished in 8 msecs
9256 13:21:59.460027 done
9257 13:21:59.466702 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9258 13:21:59.470158 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9259 13:21:59.476780 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9260 13:21:59.480403 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9261 13:21:59.483851 Allocating resources...
9262 13:21:59.483931 Reading resources...
9263 13:21:59.486856 Root Device read_resources bus 0 link: 0
9264 13:21:59.490062 DRAM rank0 size:0x100000000,
9265 13:21:59.493333 DRAM rank1 size=0x100000000
9266 13:21:59.496968 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9267 13:21:59.500213 CPU: 00 missing read_resources
9268 13:21:59.503921 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9269 13:21:59.506622 Root Device read_resources bus 0 link: 0 done
9270 13:21:59.510137 Done reading resources.
9271 13:21:59.517080 Show resources in subtree (Root Device)...After reading.
9272 13:21:59.520468 Root Device child on link 0 CPU_CLUSTER: 0
9273 13:21:59.524228 CPU_CLUSTER: 0 child on link 0 CPU: 00
9274 13:21:59.530178 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9275 13:21:59.533448 CPU: 00
9276 13:21:59.536772 Root Device assign_resources, bus 0 link: 0
9277 13:21:59.540221 CPU_CLUSTER: 0 missing set_resources
9278 13:21:59.543328 Root Device assign_resources, bus 0 link: 0 done
9279 13:21:59.546828 Done setting resources.
9280 13:21:59.553398 Show resources in subtree (Root Device)...After assigning values.
9281 13:21:59.556778 Root Device child on link 0 CPU_CLUSTER: 0
9282 13:21:59.560058 CPU_CLUSTER: 0 child on link 0 CPU: 00
9283 13:21:59.570499 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9284 13:21:59.570582 CPU: 00
9285 13:21:59.573867 Done allocating resources.
9286 13:21:59.577037 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9287 13:21:59.580533 Enabling resources...
9288 13:21:59.580641 done.
9289 13:21:59.583973 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9290 13:21:59.587397 Initializing devices...
9291 13:21:59.587477 Root Device init
9292 13:21:59.590476 init hardware done!
9293 13:21:59.593700 0x00000018: ctrlr->caps
9294 13:21:59.593782 52.000 MHz: ctrlr->f_max
9295 13:21:59.597577 0.400 MHz: ctrlr->f_min
9296 13:21:59.601282 0x40ff8080: ctrlr->voltages
9297 13:21:59.601364 sclk: 390625
9298 13:21:59.601427 Bus Width = 1
9299 13:21:59.603690 sclk: 390625
9300 13:21:59.603769 Bus Width = 1
9301 13:21:59.606950 Early init status = 3
9302 13:21:59.610451 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9303 13:21:59.614137 in-header: 03 fc 00 00 01 00 00 00
9304 13:21:59.617671 in-data: 00
9305 13:21:59.621050 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9306 13:21:59.626105 in-header: 03 fd 00 00 00 00 00 00
9307 13:21:59.629419 in-data:
9308 13:21:59.633241 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9309 13:21:59.637275 in-header: 03 fc 00 00 01 00 00 00
9310 13:21:59.641060 in-data: 00
9311 13:21:59.643947 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9312 13:21:59.649396 in-header: 03 fd 00 00 00 00 00 00
9313 13:21:59.652777 in-data:
9314 13:21:59.656662 [SSUSB] Setting up USB HOST controller...
9315 13:21:59.659954 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9316 13:21:59.662756 [SSUSB] phy power-on done.
9317 13:21:59.666227 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9318 13:21:59.672956 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9319 13:21:59.676224 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9320 13:21:59.683149 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9321 13:21:59.689600 read SPI 0x50eb0 0x2ad3: 1173 us, 9346 KB/s, 74.768 Mbps
9322 13:21:59.696349 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9323 13:21:59.703055 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9324 13:21:59.709863 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9325 13:21:59.709943 SPM: binary array size = 0x9dc
9326 13:21:59.716679 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9327 13:21:59.723124 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9328 13:21:59.729771 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9329 13:21:59.733237 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9330 13:21:59.736610 configure_display: Starting display init
9331 13:21:59.773117 anx7625_power_on_init: Init interface.
9332 13:21:59.776632 anx7625_disable_pd_protocol: Disabled PD feature.
9333 13:21:59.779434 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9334 13:21:59.807052 anx7625_start_dp_work: Secure OCM version=00
9335 13:21:59.810513 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9336 13:21:59.825103 sp_tx_get_edid_block: EDID Block = 1
9337 13:21:59.928075 Extracted contents:
9338 13:21:59.931141 header: 00 ff ff ff ff ff ff 00
9339 13:21:59.934961 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9340 13:21:59.937793 version: 01 04
9341 13:21:59.941390 basic params: 95 1f 11 78 0a
9342 13:21:59.944387 chroma info: 76 90 94 55 54 90 27 21 50 54
9343 13:21:59.947820 established: 00 00 00
9344 13:21:59.951343 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9345 13:21:59.957762 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9346 13:21:59.964344 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9347 13:21:59.971326 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9348 13:21:59.978252 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9349 13:21:59.978332 extensions: 00
9350 13:21:59.981056 checksum: fb
9351 13:21:59.981134
9352 13:21:59.985198 Manufacturer: IVO Model 57d Serial Number 0
9353 13:21:59.988889 Made week 0 of 2020
9354 13:21:59.988967 EDID version: 1.4
9355 13:21:59.991263 Digital display
9356 13:21:59.994825 6 bits per primary color channel
9357 13:21:59.994905 DisplayPort interface
9358 13:21:59.998274 Maximum image size: 31 cm x 17 cm
9359 13:21:59.998353 Gamma: 220%
9360 13:22:00.001771 Check DPMS levels
9361 13:22:00.004943 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9362 13:22:00.008389 First detailed timing is preferred timing
9363 13:22:00.011423 Established timings supported:
9364 13:22:00.015111 Standard timings supported:
9365 13:22:00.015216 Detailed timings
9366 13:22:00.021441 Hex of detail: 383680a07038204018303c0035ae10000019
9367 13:22:00.025188 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9368 13:22:00.028365 0780 0798 07c8 0820 hborder 0
9369 13:22:00.034779 0438 043b 0447 0458 vborder 0
9370 13:22:00.034877 -hsync -vsync
9371 13:22:00.038071 Did detailed timing
9372 13:22:00.041565 Hex of detail: 000000000000000000000000000000000000
9373 13:22:00.044958 Manufacturer-specified data, tag 0
9374 13:22:00.051278 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9375 13:22:00.051379 ASCII string: InfoVision
9376 13:22:00.058065 Hex of detail: 000000fe00523134304e574635205248200a
9377 13:22:00.058144 ASCII string: R140NWF5 RH
9378 13:22:00.061114 Checksum
9379 13:22:00.061192 Checksum: 0xfb (valid)
9380 13:22:00.068467 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9381 13:22:00.068545 DSI data_rate: 832800000 bps
9382 13:22:00.075626 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9383 13:22:00.079157 anx7625_parse_edid: pixelclock(138800).
9384 13:22:00.082284 hactive(1920), hsync(48), hfp(24), hbp(88)
9385 13:22:00.085630 vactive(1080), vsync(12), vfp(3), vbp(17)
9386 13:22:00.088635 anx7625_dsi_config: config dsi.
9387 13:22:00.095877 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9388 13:22:00.110148 anx7625_dsi_config: success to config DSI
9389 13:22:00.113510 anx7625_dp_start: MIPI phy setup OK.
9390 13:22:00.117399 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9391 13:22:00.120181 mtk_ddp_mode_set invalid vrefresh 60
9392 13:22:00.123582 main_disp_path_setup
9393 13:22:00.123681 ovl_layer_smi_id_en
9394 13:22:00.126618 ovl_layer_smi_id_en
9395 13:22:00.126687 ccorr_config
9396 13:22:00.126746 aal_config
9397 13:22:00.130323 gamma_config
9398 13:22:00.130429 postmask_config
9399 13:22:00.133305 dither_config
9400 13:22:00.136599 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9401 13:22:00.143435 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9402 13:22:00.146484 Root Device init finished in 554 msecs
9403 13:22:00.146582 CPU_CLUSTER: 0 init
9404 13:22:00.156461 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9405 13:22:00.159852 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9406 13:22:00.163523 APU_MBOX 0x190000b0 = 0x10001
9407 13:22:00.167314 APU_MBOX 0x190001b0 = 0x10001
9408 13:22:00.169925 APU_MBOX 0x190005b0 = 0x10001
9409 13:22:00.173194 APU_MBOX 0x190006b0 = 0x10001
9410 13:22:00.176403 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9411 13:22:00.188609 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9412 13:22:00.201377 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9413 13:22:00.207951 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9414 13:22:00.219629 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9415 13:22:00.228619 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9416 13:22:00.232430 CPU_CLUSTER: 0 init finished in 81 msecs
9417 13:22:00.235381 Devices initialized
9418 13:22:00.238537 Show all devs... After init.
9419 13:22:00.238607 Root Device: enabled 1
9420 13:22:00.241966 CPU_CLUSTER: 0: enabled 1
9421 13:22:00.245239 CPU: 00: enabled 1
9422 13:22:00.248650 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9423 13:22:00.252068 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9424 13:22:00.255648 ELOG: NV offset 0x57f000 size 0x1000
9425 13:22:00.262286 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9426 13:22:00.268658 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9427 13:22:00.272043 ELOG: Event(17) added with size 13 at 2023-09-06 13:22:02 UTC
9428 13:22:00.275571 out: cmd=0x121: 03 db 21 01 00 00 00 00
9429 13:22:00.280406 in-header: 03 ee 00 00 2c 00 00 00
9430 13:22:00.293235 in-data: 71 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9431 13:22:00.300202 ELOG: Event(A1) added with size 10 at 2023-09-06 13:22:02 UTC
9432 13:22:00.306570 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9433 13:22:00.313425 ELOG: Event(A0) added with size 9 at 2023-09-06 13:22:02 UTC
9434 13:22:00.316642 elog_add_boot_reason: Logged dev mode boot
9435 13:22:00.319968 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9436 13:22:00.323215 Finalize devices...
9437 13:22:00.323312 Devices finalized
9438 13:22:00.329849 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9439 13:22:00.333760 Writing coreboot table at 0xffe64000
9440 13:22:00.336870 0. 000000000010a000-0000000000113fff: RAMSTAGE
9441 13:22:00.340055 1. 0000000040000000-00000000400fffff: RAM
9442 13:22:00.343173 2. 0000000040100000-000000004032afff: RAMSTAGE
9443 13:22:00.349814 3. 000000004032b000-00000000545fffff: RAM
9444 13:22:00.352994 4. 0000000054600000-000000005465ffff: BL31
9445 13:22:00.356641 5. 0000000054660000-00000000ffe63fff: RAM
9446 13:22:00.363583 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9447 13:22:00.366820 7. 0000000100000000-000000023fffffff: RAM
9448 13:22:00.366902 Passing 5 GPIOs to payload:
9449 13:22:00.372994 NAME | PORT | POLARITY | VALUE
9450 13:22:00.376791 EC in RW | 0x000000aa | low | undefined
9451 13:22:00.383480 EC interrupt | 0x00000005 | low | undefined
9452 13:22:00.386291 TPM interrupt | 0x000000ab | high | undefined
9453 13:22:00.389744 SD card detect | 0x00000011 | high | undefined
9454 13:22:00.396528 speaker enable | 0x00000093 | high | undefined
9455 13:22:00.399794 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9456 13:22:00.402945 in-header: 03 f9 00 00 02 00 00 00
9457 13:22:00.403049 in-data: 02 00
9458 13:22:00.406862 ADC[4]: Raw value=900221 ID=7
9459 13:22:00.410108 ADC[3]: Raw value=213336 ID=1
9460 13:22:00.410179 RAM Code: 0x71
9461 13:22:00.413147 ADC[6]: Raw value=74557 ID=0
9462 13:22:00.416569 ADC[5]: Raw value=212598 ID=1
9463 13:22:00.416663 SKU Code: 0x1
9464 13:22:00.422915 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ae81
9465 13:22:00.426282 coreboot table: 964 bytes.
9466 13:22:00.429943 IMD ROOT 0. 0xfffff000 0x00001000
9467 13:22:00.433191 IMD SMALL 1. 0xffffe000 0x00001000
9468 13:22:00.436503 RO MCACHE 2. 0xffffc000 0x00001104
9469 13:22:00.440116 CONSOLE 3. 0xfff7c000 0x00080000
9470 13:22:00.443030 FMAP 4. 0xfff7b000 0x00000452
9471 13:22:00.446891 TIME STAMP 5. 0xfff7a000 0x00000910
9472 13:22:00.449658 VBOOT WORK 6. 0xfff66000 0x00014000
9473 13:22:00.452956 RAMOOPS 7. 0xffe66000 0x00100000
9474 13:22:00.456894 COREBOOT 8. 0xffe64000 0x00002000
9475 13:22:00.456973 IMD small region:
9476 13:22:00.459574 IMD ROOT 0. 0xffffec00 0x00000400
9477 13:22:00.463089 VPD 1. 0xffffeb80 0x0000006c
9478 13:22:00.466304 MMC STATUS 2. 0xffffeb60 0x00000004
9479 13:22:00.473056 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9480 13:22:00.473135 Probing TPM: done!
9481 13:22:00.479818 Connected to device vid:did:rid of 1ae0:0028:00
9482 13:22:00.486508 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9483 13:22:00.490353 Initialized TPM device CR50 revision 0
9484 13:22:00.493789 Checking cr50 for pending updates
9485 13:22:00.499716 Reading cr50 TPM mode
9486 13:22:00.508469 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9487 13:22:00.515054 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9488 13:22:00.555231 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9489 13:22:00.558643 Checking segment from ROM address 0x40100000
9490 13:22:00.561653 Checking segment from ROM address 0x4010001c
9491 13:22:00.568649 Loading segment from ROM address 0x40100000
9492 13:22:00.568764 code (compression=0)
9493 13:22:00.575313 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9494 13:22:00.585300 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9495 13:22:00.585380 it's not compressed!
9496 13:22:00.592501 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9497 13:22:00.595205 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9498 13:22:00.615642 Loading segment from ROM address 0x4010001c
9499 13:22:00.615722 Entry Point 0x80000000
9500 13:22:00.618902 Loaded segments
9501 13:22:00.621985 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9502 13:22:00.628872 Jumping to boot code at 0x80000000(0xffe64000)
9503 13:22:00.635906 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9504 13:22:00.642414 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9505 13:22:00.650070 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9506 13:22:00.653242 Checking segment from ROM address 0x40100000
9507 13:22:00.656564 Checking segment from ROM address 0x4010001c
9508 13:22:00.663326 Loading segment from ROM address 0x40100000
9509 13:22:00.663406 code (compression=1)
9510 13:22:00.669964 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9511 13:22:00.679867 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9512 13:22:00.679971 using LZMA
9513 13:22:00.688408 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9514 13:22:00.695569 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9515 13:22:00.698566 Loading segment from ROM address 0x4010001c
9516 13:22:00.698662 Entry Point 0x54601000
9517 13:22:00.701963 Loaded segments
9518 13:22:00.704836 NOTICE: MT8192 bl31_setup
9519 13:22:00.711958 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9520 13:22:00.715179 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9521 13:22:00.718974 WARNING: region 0:
9522 13:22:00.721885 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9523 13:22:00.721959 WARNING: region 1:
9524 13:22:00.729019 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9525 13:22:00.732422 WARNING: region 2:
9526 13:22:00.735742 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9527 13:22:00.738587 WARNING: region 3:
9528 13:22:00.742268 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9529 13:22:00.745596 WARNING: region 4:
9530 13:22:00.749253 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9531 13:22:00.752177 WARNING: region 5:
9532 13:22:00.755578 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9533 13:22:00.759334 WARNING: region 6:
9534 13:22:00.762658 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9535 13:22:00.762760 WARNING: region 7:
9536 13:22:00.769197 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9537 13:22:00.775933 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9538 13:22:00.779088 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9539 13:22:00.782654 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9540 13:22:00.785999 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9541 13:22:00.792648 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9542 13:22:00.795844 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9543 13:22:00.802623 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9544 13:22:00.805956 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9545 13:22:00.809347 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9546 13:22:00.816054 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9547 13:22:00.819500 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9548 13:22:00.822817 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9549 13:22:00.829450 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9550 13:22:00.832652 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9551 13:22:00.836476 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9552 13:22:00.842940 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9553 13:22:00.846575 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9554 13:22:00.849580 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9555 13:22:00.856338 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9556 13:22:00.859763 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9557 13:22:00.866388 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9558 13:22:00.869854 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9559 13:22:00.873403 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9560 13:22:00.879797 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9561 13:22:00.883157 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9562 13:22:00.890158 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9563 13:22:00.893415 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9564 13:22:00.896585 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9565 13:22:00.903357 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9566 13:22:00.906504 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9567 13:22:00.910667 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9568 13:22:00.917202 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9569 13:22:00.920574 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9570 13:22:00.923434 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9571 13:22:00.930255 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9572 13:22:00.933788 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9573 13:22:00.937040 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9574 13:22:00.940190 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9575 13:22:00.943622 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9576 13:22:00.950244 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9577 13:22:00.953626 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9578 13:22:00.957104 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9579 13:22:00.960364 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9580 13:22:00.967507 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9581 13:22:00.970744 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9582 13:22:00.974048 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9583 13:22:00.977587 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9584 13:22:00.984047 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9585 13:22:00.987307 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9586 13:22:00.994012 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9587 13:22:00.997349 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9588 13:22:01.001000 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9589 13:22:01.007403 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9590 13:22:01.010874 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9591 13:22:01.017480 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9592 13:22:01.020580 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9593 13:22:01.024378 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9594 13:22:01.030710 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9595 13:22:01.034095 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9596 13:22:01.041247 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9597 13:22:01.044292 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9598 13:22:01.050930 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9599 13:22:01.054796 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9600 13:22:01.057560 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9601 13:22:01.064135 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9602 13:22:01.067971 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9603 13:22:01.074253 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9604 13:22:01.078043 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9605 13:22:01.085259 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9606 13:22:01.087791 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9607 13:22:01.091165 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9608 13:22:01.098252 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9609 13:22:01.101292 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9610 13:22:01.107881 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9611 13:22:01.111385 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9612 13:22:01.114574 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9613 13:22:01.121707 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9614 13:22:01.124825 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9615 13:22:01.131520 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9616 13:22:01.134662 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9617 13:22:01.141391 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9618 13:22:01.144934 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9619 13:22:01.148199 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9620 13:22:01.154912 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9621 13:22:01.158308 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9622 13:22:01.164951 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9623 13:22:01.168593 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9624 13:22:01.172358 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9625 13:22:01.178645 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9626 13:22:01.182583 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9627 13:22:01.188805 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9628 13:22:01.191995 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9629 13:22:01.198740 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9630 13:22:01.202105 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9631 13:22:01.205486 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9632 13:22:01.212279 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9633 13:22:01.215647 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9634 13:22:01.218788 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9635 13:22:01.225604 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9636 13:22:01.228898 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9637 13:22:01.232414 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9638 13:22:01.235602 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9639 13:22:01.242581 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9640 13:22:01.245906 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9641 13:22:01.252629 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9642 13:22:01.255697 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9643 13:22:01.259429 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9644 13:22:01.265527 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9645 13:22:01.269153 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9646 13:22:01.276083 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9647 13:22:01.279186 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9648 13:22:01.282696 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9649 13:22:01.289444 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9650 13:22:01.292689 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9651 13:22:01.299445 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9652 13:22:01.302520 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9653 13:22:01.305818 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9654 13:22:01.309351 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9655 13:22:01.316107 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9656 13:22:01.319367 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9657 13:22:01.322962 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9658 13:22:01.326500 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9659 13:22:01.332951 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9660 13:22:01.336353 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9661 13:22:01.339606 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9662 13:22:01.346182 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9663 13:22:01.349504 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9664 13:22:01.352990 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9665 13:22:01.359774 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9666 13:22:01.363189 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9667 13:22:01.369625 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9668 13:22:01.373365 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9669 13:22:01.376604 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9670 13:22:01.383149 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9671 13:22:01.386802 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9672 13:22:01.389901 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9673 13:22:01.396981 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9674 13:22:01.400139 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9675 13:22:01.406608 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9676 13:22:01.409935 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9677 13:22:01.413385 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9678 13:22:01.420114 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9679 13:22:01.423630 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9680 13:22:01.430434 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9681 13:22:01.433952 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9682 13:22:01.436842 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9683 13:22:01.443786 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9684 13:22:01.446821 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9685 13:22:01.450566 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9686 13:22:01.457082 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9687 13:22:01.460392 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9688 13:22:01.463830 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9689 13:22:01.470739 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9690 13:22:01.474479 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9691 13:22:01.480861 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9692 13:22:01.484126 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9693 13:22:01.487882 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9694 13:22:01.494108 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9695 13:22:01.497919 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9696 13:22:01.500699 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9697 13:22:01.507255 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9698 13:22:01.510589 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9699 13:22:01.517659 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9700 13:22:01.520846 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9701 13:22:01.523953 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9702 13:22:01.530536 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9703 13:22:01.534290 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9704 13:22:01.540679 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9705 13:22:01.544020 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9706 13:22:01.547562 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9707 13:22:01.553985 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9708 13:22:01.557521 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9709 13:22:01.561187 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9710 13:22:01.567474 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9711 13:22:01.570738 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9712 13:22:01.577805 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9713 13:22:01.580900 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9714 13:22:01.584383 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9715 13:22:01.591198 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9716 13:22:01.594579 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9717 13:22:01.597687 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9718 13:22:01.604390 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9719 13:22:01.607520 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9720 13:22:01.614189 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9721 13:22:01.617654 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9722 13:22:01.620839 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9723 13:22:01.627781 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9724 13:22:01.631327 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9725 13:22:01.637991 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9726 13:22:01.641449 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9727 13:22:01.644403 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9728 13:22:01.651468 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9729 13:22:01.654370 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9730 13:22:01.660914 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9731 13:22:01.664362 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9732 13:22:01.668146 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9733 13:22:01.674622 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9734 13:22:01.677625 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9735 13:22:01.684374 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9736 13:22:01.688260 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9737 13:22:01.691339 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9738 13:22:01.697718 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9739 13:22:01.701088 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9740 13:22:01.707742 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9741 13:22:01.711105 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9742 13:22:01.717810 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9743 13:22:01.721468 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9744 13:22:01.725114 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9745 13:22:01.731368 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9746 13:22:01.734814 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9747 13:22:01.741436 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9748 13:22:01.744470 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9749 13:22:01.748042 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9750 13:22:01.754517 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9751 13:22:01.758136 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9752 13:22:01.764663 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9753 13:22:01.768103 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9754 13:22:01.771798 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9755 13:22:01.778517 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9756 13:22:01.781237 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9757 13:22:01.788035 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9758 13:22:01.791431 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9759 13:22:01.794813 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9760 13:22:01.801582 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9761 13:22:01.804911 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9762 13:22:01.811382 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9763 13:22:01.814710 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9764 13:22:01.818612 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9765 13:22:01.824630 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9766 13:22:01.828092 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9767 13:22:01.831746 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9768 13:22:01.835483 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9769 13:22:01.841503 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9770 13:22:01.845249 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9771 13:22:01.848249 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9772 13:22:01.855135 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9773 13:22:01.858534 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9774 13:22:01.861680 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9775 13:22:01.868658 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9776 13:22:01.871957 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9777 13:22:01.875382 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9778 13:22:01.881834 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9779 13:22:01.885323 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9780 13:22:01.888548 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9781 13:22:01.895913 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9782 13:22:01.898323 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9783 13:22:01.905270 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9784 13:22:01.908516 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9785 13:22:01.912055 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9786 13:22:01.918819 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9787 13:22:01.922122 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9788 13:22:01.925404 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9789 13:22:01.932468 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9790 13:22:01.935417 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9791 13:22:01.939183 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9792 13:22:01.945713 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9793 13:22:01.949037 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9794 13:22:01.955858 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9795 13:22:01.959172 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9796 13:22:01.962262 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9797 13:22:01.968831 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9798 13:22:01.972341 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9799 13:22:01.975933 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9800 13:22:01.982547 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9801 13:22:01.985601 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9802 13:22:01.988842 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9803 13:22:01.995950 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9804 13:22:01.999267 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9805 13:22:02.002450 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9806 13:22:02.008961 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9807 13:22:02.012690 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9808 13:22:02.015880 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9809 13:22:02.019086 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9810 13:22:02.022820 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9811 13:22:02.029048 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9812 13:22:02.032218 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9813 13:22:02.035541 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9814 13:22:02.039172 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9815 13:22:02.045823 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9816 13:22:02.048947 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9817 13:22:02.052238 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9818 13:22:02.059117 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9819 13:22:02.062259 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9820 13:22:02.065930 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9821 13:22:02.072381 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9822 13:22:02.076015 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9823 13:22:02.082112 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9824 13:22:02.085767 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9825 13:22:02.089258 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9826 13:22:02.095442 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9827 13:22:02.098892 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9828 13:22:02.105648 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9829 13:22:02.109246 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9830 13:22:02.112778 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9831 13:22:02.118714 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9832 13:22:02.122699 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9833 13:22:02.129351 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9834 13:22:02.132548 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9835 13:22:02.135839 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9836 13:22:02.142324 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9837 13:22:02.145526 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9838 13:22:02.152111 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9839 13:22:02.155680 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9840 13:22:02.158905 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9841 13:22:02.166443 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9842 13:22:02.169053 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9843 13:22:02.175531 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9844 13:22:02.179049 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9845 13:22:02.182583 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9846 13:22:02.189106 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9847 13:22:02.192545 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9848 13:22:02.198966 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9849 13:22:02.202511 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9850 13:22:02.205703 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9851 13:22:02.212158 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9852 13:22:02.215680 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9853 13:22:02.222337 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9854 13:22:02.225990 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9855 13:22:02.229232 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9856 13:22:02.235523 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9857 13:22:02.239150 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9858 13:22:02.245897 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9859 13:22:02.249276 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9860 13:22:02.252549 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9861 13:22:02.259471 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9862 13:22:02.262579 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9863 13:22:02.269417 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9864 13:22:02.272391 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9865 13:22:02.275977 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9866 13:22:02.282567 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9867 13:22:02.285866 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9868 13:22:02.292382 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9869 13:22:02.295875 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9870 13:22:02.299407 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9871 13:22:02.306001 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9872 13:22:02.309446 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9873 13:22:02.315873 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9874 13:22:02.319197 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9875 13:22:02.322470 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9876 13:22:02.329151 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9877 13:22:02.332487 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9878 13:22:02.339502 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9879 13:22:02.342345 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9880 13:22:02.349035 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9881 13:22:02.352351 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9882 13:22:02.356061 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9883 13:22:02.362329 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9884 13:22:02.365713 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9885 13:22:02.369101 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9886 13:22:02.376422 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9887 13:22:02.379221 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9888 13:22:02.386181 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9889 13:22:02.389725 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9890 13:22:02.392819 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9891 13:22:02.399101 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9892 13:22:02.402777 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9893 13:22:02.409371 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9894 13:22:02.412902 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9895 13:22:02.419402 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9896 13:22:02.422744 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9897 13:22:02.426377 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9898 13:22:02.432912 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9899 13:22:02.436111 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9900 13:22:02.443065 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9901 13:22:02.446403 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9902 13:22:02.452963 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9903 13:22:02.456265 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9904 13:22:02.459256 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9905 13:22:02.466117 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9906 13:22:02.469712 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9907 13:22:02.476549 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9908 13:22:02.479358 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9909 13:22:02.483214 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9910 13:22:02.489359 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9911 13:22:02.492725 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9912 13:22:02.499613 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9913 13:22:02.502739 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9914 13:22:02.509413 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9915 13:22:02.512782 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9916 13:22:02.516008 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9917 13:22:02.522731 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9918 13:22:02.525890 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9919 13:22:02.532573 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9920 13:22:02.536163 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9921 13:22:02.542727 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9922 13:22:02.546418 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9923 13:22:02.549397 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9924 13:22:02.556165 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9925 13:22:02.559670 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9926 13:22:02.566216 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9927 13:22:02.569448 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9928 13:22:02.576258 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9929 13:22:02.579742 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9930 13:22:02.582725 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9931 13:22:02.589415 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9932 13:22:02.592577 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9933 13:22:02.599795 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9934 13:22:02.602805 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9935 13:22:02.609653 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9936 13:22:02.613437 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9937 13:22:02.619722 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9938 13:22:02.622766 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9939 13:22:02.626197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9940 13:22:02.632978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9941 13:22:02.636324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9942 13:22:02.642882 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9943 13:22:02.646101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9944 13:22:02.652837 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9945 13:22:02.656556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9946 13:22:02.659677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9947 13:22:02.666256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9948 13:22:02.669657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9949 13:22:02.676429 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9950 13:22:02.679986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9951 13:22:02.686112 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9952 13:22:02.689748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9953 13:22:02.696122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9954 13:22:02.699669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9955 13:22:02.706219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9956 13:22:02.709525 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9957 13:22:02.716518 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9958 13:22:02.720148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9959 13:22:02.726312 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9960 13:22:02.729707 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9961 13:22:02.736272 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9962 13:22:02.739782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9963 13:22:02.746385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9964 13:22:02.750145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9965 13:22:02.756394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9966 13:22:02.760102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9967 13:22:02.766476 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9968 13:22:02.769956 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9969 13:22:02.776444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9970 13:22:02.779642 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9971 13:22:02.783166 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9972 13:22:02.786468 INFO: [APUAPC] vio 0
9973 13:22:02.789744 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9974 13:22:02.796326 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9975 13:22:02.799945 INFO: [APUAPC] D0_APC_0: 0x400510
9976 13:22:02.803405 INFO: [APUAPC] D0_APC_1: 0x0
9977 13:22:02.806671 INFO: [APUAPC] D0_APC_2: 0x1540
9978 13:22:02.807185 INFO: [APUAPC] D0_APC_3: 0x0
9979 13:22:02.809832 INFO: [APUAPC] D1_APC_0: 0xffffffff
9980 13:22:02.813554 INFO: [APUAPC] D1_APC_1: 0xffffffff
9981 13:22:02.816879 INFO: [APUAPC] D1_APC_2: 0x3fffff
9982 13:22:02.819711 INFO: [APUAPC] D1_APC_3: 0x0
9983 13:22:02.823191 INFO: [APUAPC] D2_APC_0: 0xffffffff
9984 13:22:02.826644 INFO: [APUAPC] D2_APC_1: 0xffffffff
9985 13:22:02.830175 INFO: [APUAPC] D2_APC_2: 0x3fffff
9986 13:22:02.833303 INFO: [APUAPC] D2_APC_3: 0x0
9987 13:22:02.836450 INFO: [APUAPC] D3_APC_0: 0xffffffff
9988 13:22:02.839918 INFO: [APUAPC] D3_APC_1: 0xffffffff
9989 13:22:02.843066 INFO: [APUAPC] D3_APC_2: 0x3fffff
9990 13:22:02.846769 INFO: [APUAPC] D3_APC_3: 0x0
9991 13:22:02.849996 INFO: [APUAPC] D4_APC_0: 0xffffffff
9992 13:22:02.853226 INFO: [APUAPC] D4_APC_1: 0xffffffff
9993 13:22:02.856600 INFO: [APUAPC] D4_APC_2: 0x3fffff
9994 13:22:02.859895 INFO: [APUAPC] D4_APC_3: 0x0
9995 13:22:02.863547 INFO: [APUAPC] D5_APC_0: 0xffffffff
9996 13:22:02.866574 INFO: [APUAPC] D5_APC_1: 0xffffffff
9997 13:22:02.870080 INFO: [APUAPC] D5_APC_2: 0x3fffff
9998 13:22:02.873404 INFO: [APUAPC] D5_APC_3: 0x0
9999 13:22:02.876736 INFO: [APUAPC] D6_APC_0: 0xffffffff
10000 13:22:02.880110 INFO: [APUAPC] D6_APC_1: 0xffffffff
10001 13:22:02.883231 INFO: [APUAPC] D6_APC_2: 0x3fffff
10002 13:22:02.886530 INFO: [APUAPC] D6_APC_3: 0x0
10003 13:22:02.889778 INFO: [APUAPC] D7_APC_0: 0xffffffff
10004 13:22:02.893206 INFO: [APUAPC] D7_APC_1: 0xffffffff
10005 13:22:02.896761 INFO: [APUAPC] D7_APC_2: 0x3fffff
10006 13:22:02.900501 INFO: [APUAPC] D7_APC_3: 0x0
10007 13:22:02.903347 INFO: [APUAPC] D8_APC_0: 0xffffffff
10008 13:22:02.906850 INFO: [APUAPC] D8_APC_1: 0xffffffff
10009 13:22:02.909961 INFO: [APUAPC] D8_APC_2: 0x3fffff
10010 13:22:02.913201 INFO: [APUAPC] D8_APC_3: 0x0
10011 13:22:02.916448 INFO: [APUAPC] D9_APC_0: 0xffffffff
10012 13:22:02.919514 INFO: [APUAPC] D9_APC_1: 0xffffffff
10013 13:22:02.923169 INFO: [APUAPC] D9_APC_2: 0x3fffff
10014 13:22:02.926318 INFO: [APUAPC] D9_APC_3: 0x0
10015 13:22:02.930220 INFO: [APUAPC] D10_APC_0: 0xffffffff
10016 13:22:02.933168 INFO: [APUAPC] D10_APC_1: 0xffffffff
10017 13:22:02.936508 INFO: [APUAPC] D10_APC_2: 0x3fffff
10018 13:22:02.939855 INFO: [APUAPC] D10_APC_3: 0x0
10019 13:22:02.943107 INFO: [APUAPC] D11_APC_0: 0xffffffff
10020 13:22:02.946235 INFO: [APUAPC] D11_APC_1: 0xffffffff
10021 13:22:02.949747 INFO: [APUAPC] D11_APC_2: 0x3fffff
10022 13:22:02.952856 INFO: [APUAPC] D11_APC_3: 0x0
10023 13:22:02.956490 INFO: [APUAPC] D12_APC_0: 0xffffffff
10024 13:22:02.959511 INFO: [APUAPC] D12_APC_1: 0xffffffff
10025 13:22:02.963022 INFO: [APUAPC] D12_APC_2: 0x3fffff
10026 13:22:02.966176 INFO: [APUAPC] D12_APC_3: 0x0
10027 13:22:02.969769 INFO: [APUAPC] D13_APC_0: 0xffffffff
10028 13:22:02.972767 INFO: [APUAPC] D13_APC_1: 0xffffffff
10029 13:22:02.976504 INFO: [APUAPC] D13_APC_2: 0x3fffff
10030 13:22:02.979662 INFO: [APUAPC] D13_APC_3: 0x0
10031 13:22:02.982723 INFO: [APUAPC] D14_APC_0: 0xffffffff
10032 13:22:02.986131 INFO: [APUAPC] D14_APC_1: 0xffffffff
10033 13:22:02.989622 INFO: [APUAPC] D14_APC_2: 0x3fffff
10034 13:22:02.992774 INFO: [APUAPC] D14_APC_3: 0x0
10035 13:22:02.996197 INFO: [APUAPC] D15_APC_0: 0xffffffff
10036 13:22:02.999543 INFO: [APUAPC] D15_APC_1: 0xffffffff
10037 13:22:03.003526 INFO: [APUAPC] D15_APC_2: 0x3fffff
10038 13:22:03.006461 INFO: [APUAPC] D15_APC_3: 0x0
10039 13:22:03.006845 INFO: [APUAPC] APC_CON: 0x4
10040 13:22:03.010165 INFO: [NOCDAPC] D0_APC_0: 0x0
10041 13:22:03.013259 INFO: [NOCDAPC] D0_APC_1: 0x0
10042 13:22:03.016588 INFO: [NOCDAPC] D1_APC_0: 0x0
10043 13:22:03.019755 INFO: [NOCDAPC] D1_APC_1: 0xfff
10044 13:22:03.023033 INFO: [NOCDAPC] D2_APC_0: 0x0
10045 13:22:03.026306 INFO: [NOCDAPC] D2_APC_1: 0xfff
10046 13:22:03.029789 INFO: [NOCDAPC] D3_APC_0: 0x0
10047 13:22:03.032856 INFO: [NOCDAPC] D3_APC_1: 0xfff
10048 13:22:03.036550 INFO: [NOCDAPC] D4_APC_0: 0x0
10049 13:22:03.037014 INFO: [NOCDAPC] D4_APC_1: 0xfff
10050 13:22:03.039567 INFO: [NOCDAPC] D5_APC_0: 0x0
10051 13:22:03.042883 INFO: [NOCDAPC] D5_APC_1: 0xfff
10052 13:22:03.046445 INFO: [NOCDAPC] D6_APC_0: 0x0
10053 13:22:03.049993 INFO: [NOCDAPC] D6_APC_1: 0xfff
10054 13:22:03.053298 INFO: [NOCDAPC] D7_APC_0: 0x0
10055 13:22:03.056450 INFO: [NOCDAPC] D7_APC_1: 0xfff
10056 13:22:03.059985 INFO: [NOCDAPC] D8_APC_0: 0x0
10057 13:22:03.062945 INFO: [NOCDAPC] D8_APC_1: 0xfff
10058 13:22:03.066578 INFO: [NOCDAPC] D9_APC_0: 0x0
10059 13:22:03.067023 INFO: [NOCDAPC] D9_APC_1: 0xfff
10060 13:22:03.069925 INFO: [NOCDAPC] D10_APC_0: 0x0
10061 13:22:03.073212 INFO: [NOCDAPC] D10_APC_1: 0xfff
10062 13:22:03.076538 INFO: [NOCDAPC] D11_APC_0: 0x0
10063 13:22:03.079719 INFO: [NOCDAPC] D11_APC_1: 0xfff
10064 13:22:03.083355 INFO: [NOCDAPC] D12_APC_0: 0x0
10065 13:22:03.086589 INFO: [NOCDAPC] D12_APC_1: 0xfff
10066 13:22:03.090194 INFO: [NOCDAPC] D13_APC_0: 0x0
10067 13:22:03.093205 INFO: [NOCDAPC] D13_APC_1: 0xfff
10068 13:22:03.096651 INFO: [NOCDAPC] D14_APC_0: 0x0
10069 13:22:03.099951 INFO: [NOCDAPC] D14_APC_1: 0xfff
10070 13:22:03.103278 INFO: [NOCDAPC] D15_APC_0: 0x0
10071 13:22:03.106458 INFO: [NOCDAPC] D15_APC_1: 0xfff
10072 13:22:03.106857 INFO: [NOCDAPC] APC_CON: 0x4
10073 13:22:03.110272 INFO: [APUAPC] set_apusys_apc done
10074 13:22:03.113136 INFO: [DEVAPC] devapc_init done
10075 13:22:03.120061 INFO: GICv3 without legacy support detected.
10076 13:22:03.123355 INFO: ARM GICv3 driver initialized in EL3
10077 13:22:03.127025 INFO: Maximum SPI INTID supported: 639
10078 13:22:03.130383 INFO: BL31: Initializing runtime services
10079 13:22:03.136613 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10080 13:22:03.140231 INFO: SPM: enable CPC mode
10081 13:22:03.143100 INFO: mcdi ready for mcusys-off-idle and system suspend
10082 13:22:03.150470 INFO: BL31: Preparing for EL3 exit to normal world
10083 13:22:03.153198 INFO: Entry point address = 0x80000000
10084 13:22:03.153611 INFO: SPSR = 0x8
10085 13:22:03.160041
10086 13:22:03.160448
10087 13:22:03.160816
10088 13:22:03.164114 Starting depthcharge on Spherion...
10089 13:22:03.164525
10090 13:22:03.164890 Wipe memory regions:
10091 13:22:03.165195
10092 13:22:03.167744 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10093 13:22:03.168242 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10094 13:22:03.169804 Setting prompt string to ['asurada:']
10095 13:22:03.170214 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10096 13:22:03.170875 [0x00000040000000, 0x00000054600000)
10097 13:22:03.289126
10098 13:22:03.289580 [0x00000054660000, 0x00000080000000)
10099 13:22:03.549165
10100 13:22:03.549661 [0x000000821a7280, 0x000000ffe64000)
10101 13:22:04.293471
10102 13:22:04.293976 [0x00000100000000, 0x00000240000000)
10103 13:22:06.182373
10104 13:22:06.185347 Initializing XHCI USB controller at 0x11200000.
10105 13:22:07.223208
10106 13:22:07.226920 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10107 13:22:07.227368
10108 13:22:07.227811
10109 13:22:07.228245
10110 13:22:07.229120 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10112 13:22:07.330285 asurada: tftpboot 192.168.201.1 11445602/tftp-deploy-75s0rxey/kernel/image.itb 11445602/tftp-deploy-75s0rxey/kernel/cmdline
10113 13:22:07.330868 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10114 13:22:07.331386 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10115 13:22:07.336233 tftpboot 192.168.201.1 11445602/tftp-deploy-75s0rxey/kernel/image.ittp-deploy-75s0rxey/kernel/cmdline
10116 13:22:07.336706
10117 13:22:07.337147 Waiting for link
10118 13:22:07.496558
10119 13:22:07.497105 R8152: Initializing
10120 13:22:07.497563
10121 13:22:07.499613 Version 6 (ocp_data = 5c30)
10122 13:22:07.500011
10123 13:22:07.502876 R8152: Done initializing
10124 13:22:07.503267
10125 13:22:07.503717 Adding net device
10126 13:22:09.433406
10127 13:22:09.433922 done.
10128 13:22:09.434267
10129 13:22:09.434580 MAC: 00:24:32:30:78:52
10130 13:22:09.434883
10131 13:22:09.436902 Sending DHCP discover... done.
10132 13:22:09.437331
10133 13:22:09.439711 Waiting for reply... done.
10134 13:22:09.440130
10135 13:22:09.443106 Sending DHCP request... done.
10136 13:22:09.443539
10137 13:22:09.448657 Waiting for reply... done.
10138 13:22:09.449270
10139 13:22:09.449640 My ip is 192.168.201.14
10140 13:22:09.449988
10141 13:22:09.452587 The DHCP server ip is 192.168.201.1
10142 13:22:09.453092
10143 13:22:09.458930 TFTP server IP predefined by user: 192.168.201.1
10144 13:22:09.459357
10145 13:22:09.465442 Bootfile predefined by user: 11445602/tftp-deploy-75s0rxey/kernel/image.itb
10146 13:22:09.465869
10147 13:22:09.466207 Sending tftp read request... done.
10148 13:22:09.468418
10149 13:22:09.475151 Waiting for the transfer...
10150 13:22:09.475610
10151 13:22:10.117892 00000000 ################################################################
10152 13:22:10.118554
10153 13:22:10.777095 00080000 ################################################################
10154 13:22:10.777608
10155 13:22:11.516124 00100000 ################################################################
10156 13:22:11.516739
10157 13:22:12.207176 00180000 ################################################################
10158 13:22:12.207706
10159 13:22:12.933400 00200000 ################################################################
10160 13:22:12.933885
10161 13:22:13.652657 00280000 ################################################################
10162 13:22:13.653176
10163 13:22:14.363040 00300000 ################################################################
10164 13:22:14.363531
10165 13:22:15.090388 00380000 ################################################################
10166 13:22:15.090890
10167 13:22:15.806134 00400000 ################################################################
10168 13:22:15.806625
10169 13:22:16.498237 00480000 ################################################################
10170 13:22:16.498731
10171 13:22:17.194377 00500000 ################################################################
10172 13:22:17.194880
10173 13:22:17.898686 00580000 ################################################################
10174 13:22:17.899227
10175 13:22:18.628744 00600000 ################################################################
10176 13:22:18.629307
10177 13:22:19.344887 00680000 ################################################################
10178 13:22:19.345449
10179 13:22:20.045131 00700000 ################################################################
10180 13:22:20.045693
10181 13:22:20.751177 00780000 ################################################################
10182 13:22:20.751740
10183 13:22:21.477288 00800000 ################################################################
10184 13:22:21.477844
10185 13:22:22.173004 00880000 ################################################################
10186 13:22:22.173546
10187 13:22:22.891474 00900000 ################################################################
10188 13:22:22.891985
10189 13:22:23.603855 00980000 ################################################################
10190 13:22:23.604376
10191 13:22:24.333984 00a00000 ################################################################
10192 13:22:24.334495
10193 13:22:25.037936 00a80000 ################################################################
10194 13:22:25.038523
10195 13:22:25.728703 00b00000 ################################################################
10196 13:22:25.729241
10197 13:22:26.446727 00b80000 ################################################################
10198 13:22:26.447237
10199 13:22:27.156328 00c00000 ################################################################
10200 13:22:27.156913
10201 13:22:27.877103 00c80000 ################################################################
10202 13:22:27.877692
10203 13:22:28.611049 00d00000 ################################################################
10204 13:22:28.611615
10205 13:22:29.329874 00d80000 ################################################################
10206 13:22:29.330568
10207 13:22:30.058897 00e00000 ################################################################
10208 13:22:30.059390
10209 13:22:30.780909 00e80000 ################################################################
10210 13:22:30.781439
10211 13:22:31.495932 00f00000 ################################################################
10212 13:22:31.496418
10213 13:22:32.203884 00f80000 ################################################################
10214 13:22:32.204366
10215 13:22:32.906016 01000000 ################################################################
10216 13:22:32.906516
10217 13:22:33.621321 01080000 ################################################################
10218 13:22:33.621916
10219 13:22:34.339266 01100000 ################################################################
10220 13:22:34.339843
10221 13:22:35.048216 01180000 ################################################################
10222 13:22:35.048369
10223 13:22:35.761143 01200000 ################################################################
10224 13:22:35.761707
10225 13:22:36.440172 01280000 ################################################################
10226 13:22:36.440322
10227 13:22:37.117642 01300000 ################################################################
10228 13:22:37.118171
10229 13:22:37.827889 01380000 ################################################################
10230 13:22:37.828417
10231 13:22:38.553808 01400000 ################################################################
10232 13:22:38.554370
10233 13:22:39.274407 01480000 ################################################################
10234 13:22:39.274974
10235 13:22:39.993279 01500000 ################################################################
10236 13:22:39.993819
10237 13:22:40.718534 01580000 ################################################################
10238 13:22:40.719113
10239 13:22:41.438464 01600000 ################################################################
10240 13:22:41.438991
10241 13:22:42.165066 01680000 ################################################################
10242 13:22:42.165619
10243 13:22:42.903940 01700000 ################################################################
10244 13:22:42.904450
10245 13:22:43.622005 01780000 ################################################################
10246 13:22:43.622512
10247 13:22:44.311807 01800000 ################################################################
10248 13:22:44.312309
10249 13:22:45.018783 01880000 ################################################################
10250 13:22:45.019311
10251 13:22:45.734423 01900000 ################################################################
10252 13:22:45.734933
10253 13:22:46.448358 01980000 ################################################################
10254 13:22:46.448917
10255 13:22:47.170078 01a00000 ################################################################
10256 13:22:47.170677
10257 13:22:47.881911 01a80000 ################################################################
10258 13:22:47.882443
10259 13:22:48.580792 01b00000 ################################################################
10260 13:22:48.581398
10261 13:22:48.614501 01b80000 #### done.
10262 13:22:48.615003
10263 13:22:48.618147 The bootfile was 28862250 bytes long.
10264 13:22:48.618561
10265 13:22:48.621216 Sending tftp read request... done.
10266 13:22:48.621629
10267 13:22:48.624992 Waiting for the transfer...
10268 13:22:48.625447
10269 13:22:48.628170 00000000 # done.
10270 13:22:48.628618
10271 13:22:48.634639 Command line loaded dynamically from TFTP file: 11445602/tftp-deploy-75s0rxey/kernel/cmdline
10272 13:22:48.635066
10273 13:22:48.658935 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11445602/extract-nfsrootfs-n61gzwea,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10274 13:22:48.659515
10275 13:22:48.660010 Loading FIT.
10276 13:22:48.660460
10277 13:22:48.661771 Image ramdisk-1 has 17774713 bytes.
10278 13:22:48.662174
10279 13:22:48.664469 Image fdt-1 has 47278 bytes.
10280 13:22:48.664992
10281 13:22:48.668009 Image kernel-1 has 11038222 bytes.
10282 13:22:48.668479
10283 13:22:48.678553 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10284 13:22:48.679117
10285 13:22:48.695369 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10286 13:22:48.695952
10287 13:22:48.698256 Choosing best match conf-1 for compat google,spherion-rev2.
10288 13:22:48.703542
10289 13:22:48.708852 Connected to device vid:did:rid of 1ae0:0028:00
10290 13:22:48.716383
10291 13:22:48.719758 tpm_get_response: command 0x17b, return code 0x0
10292 13:22:48.720310
10293 13:22:48.722797 ec_init: CrosEC protocol v3 supported (256, 248)
10294 13:22:48.727373
10295 13:22:48.729991 tpm_cleanup: add release locality here.
10296 13:22:48.730497
10297 13:22:48.731083 Shutting down all USB controllers.
10298 13:22:48.733908
10299 13:22:48.734454 Removing current net device
10300 13:22:48.734818
10301 13:22:48.740789 Exiting depthcharge with code 4 at timestamp: 74956880
10302 13:22:48.741343
10303 13:22:48.743778 LZMA decompressing kernel-1 to 0x821a6718
10304 13:22:48.744237
10305 13:22:48.747320 LZMA decompressing kernel-1 to 0x40000000
10306 13:22:50.135025
10307 13:22:50.135564 jumping to kernel
10308 13:22:50.137383 end: 2.2.4 bootloader-commands (duration 00:00:47) [common]
10309 13:22:50.137926 start: 2.2.5 auto-login-action (timeout 00:03:38) [common]
10310 13:22:50.138331 Setting prompt string to ['Linux version [0-9]']
10311 13:22:50.138712 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10312 13:22:50.139085 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10313 13:22:50.216795
10314 13:22:50.220254 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10315 13:22:50.223833 start: 2.2.5.1 login-action (timeout 00:03:38) [common]
10316 13:22:50.224396 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10317 13:22:50.224849 Setting prompt string to []
10318 13:22:50.225274 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10319 13:22:50.225660 Using line separator: #'\n'#
10320 13:22:50.225987 No login prompt set.
10321 13:22:50.226535 Parsing kernel messages
10322 13:22:50.226864 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10323 13:22:50.227421 [login-action] Waiting for messages, (timeout 00:03:38)
10324 13:22:50.243326 [ 0.000000] Linux version 6.1.46-cip4 (KernelCI@build-j36642-arm64-gcc-10-defconfig-arm64-chromebook-rxg94) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Sep 6 13:11:19 UTC 2023
10325 13:22:50.246779 [ 0.000000] random: crng init done
10326 13:22:50.249837 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10327 13:22:50.253622 [ 0.000000] efi: UEFI not found.
10328 13:22:50.263679 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10329 13:22:50.270064 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10330 13:22:50.280387 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10331 13:22:50.290107 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10332 13:22:50.296778 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10333 13:22:50.300450 [ 0.000000] printk: bootconsole [mtk8250] enabled
10334 13:22:50.308628 [ 0.000000] NUMA: No NUMA configuration found
10335 13:22:50.315529 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10336 13:22:50.322121 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10337 13:22:50.322680 [ 0.000000] Zone ranges:
10338 13:22:50.328593 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10339 13:22:50.331520 [ 0.000000] DMA32 empty
10340 13:22:50.338485 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10341 13:22:50.341700 [ 0.000000] Movable zone start for each node
10342 13:22:50.345383 [ 0.000000] Early memory node ranges
10343 13:22:50.351900 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10344 13:22:50.358584 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10345 13:22:50.365329 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10346 13:22:50.371763 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10347 13:22:50.379018 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10348 13:22:50.385158 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10349 13:22:50.441050 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10350 13:22:50.447650 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10351 13:22:50.454538 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10352 13:22:50.457361 [ 0.000000] psci: probing for conduit method from DT.
10353 13:22:50.464160 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10354 13:22:50.467762 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10355 13:22:50.474643 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10356 13:22:50.477649 [ 0.000000] psci: SMC Calling Convention v1.2
10357 13:22:50.483898 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10358 13:22:50.487424 [ 0.000000] Detected VIPT I-cache on CPU0
10359 13:22:50.493937 [ 0.000000] CPU features: detected: GIC system register CPU interface
10360 13:22:50.500899 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10361 13:22:50.508231 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10362 13:22:50.514225 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10363 13:22:50.520901 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10364 13:22:50.527711 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10365 13:22:50.534136 [ 0.000000] alternatives: applying boot alternatives
10366 13:22:50.538158 [ 0.000000] Fallback order for Node 0: 0
10367 13:22:50.544784 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10368 13:22:50.547806 [ 0.000000] Policy zone: Normal
10369 13:22:50.571378 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11445602/extract-nfsrootfs-n61gzwea,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10370 13:22:50.581628 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10371 13:22:50.594210 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10372 13:22:50.604031 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10373 13:22:50.610591 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10374 13:22:50.613956 <6>[ 0.000000] software IO TLB: area num 8.
10375 13:22:50.670570 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10376 13:22:50.819513 <6>[ 0.000000] Memory: 7952196K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 400572K reserved, 32768K cma-reserved)
10377 13:22:50.826073 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10378 13:22:50.832438 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10379 13:22:50.835519 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10380 13:22:50.842642 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10381 13:22:50.848857 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10382 13:22:50.852446 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10383 13:22:50.862510 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10384 13:22:50.869406 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10385 13:22:50.873244 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10386 13:22:50.880558 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10387 13:22:50.883722 <6>[ 0.000000] GICv3: 608 SPIs implemented
10388 13:22:50.890278 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10389 13:22:50.893583 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10390 13:22:50.897078 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10391 13:22:50.907282 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10392 13:22:50.917070 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10393 13:22:50.930261 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10394 13:22:50.936427 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10395 13:22:50.945425 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10396 13:22:50.959042 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10397 13:22:50.965843 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10398 13:22:50.973139 <6>[ 0.009187] Console: colour dummy device 80x25
10399 13:22:50.982337 <6>[ 0.013943] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10400 13:22:50.985944 <6>[ 0.024450] pid_max: default: 32768 minimum: 301
10401 13:22:50.992097 <6>[ 0.029322] LSM: Security Framework initializing
10402 13:22:50.999734 <6>[ 0.034261] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10403 13:22:51.009322 <6>[ 0.042075] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10404 13:22:51.015593 <6>[ 0.051505] cblist_init_generic: Setting adjustable number of callback queues.
10405 13:22:51.022435 <6>[ 0.058951] cblist_init_generic: Setting shift to 3 and lim to 1.
10406 13:22:51.029300 <6>[ 0.065291] cblist_init_generic: Setting adjustable number of callback queues.
10407 13:22:51.036017 <6>[ 0.072717] cblist_init_generic: Setting shift to 3 and lim to 1.
10408 13:22:51.042315 <6>[ 0.079154] rcu: Hierarchical SRCU implementation.
10409 13:22:51.048919 <6>[ 0.084199] rcu: Max phase no-delay instances is 1000.
10410 13:22:51.055653 <6>[ 0.091232] EFI services will not be available.
10411 13:22:51.058745 <6>[ 0.096233] smp: Bringing up secondary CPUs ...
10412 13:22:51.066495 <6>[ 0.101286] Detected VIPT I-cache on CPU1
10413 13:22:51.073448 <6>[ 0.101357] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10414 13:22:51.080016 <6>[ 0.101388] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10415 13:22:51.083499 <6>[ 0.101730] Detected VIPT I-cache on CPU2
10416 13:22:51.089988 <6>[ 0.101782] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10417 13:22:51.096873 <6>[ 0.101798] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10418 13:22:51.102979 <6>[ 0.102058] Detected VIPT I-cache on CPU3
10419 13:22:51.109879 <6>[ 0.102104] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10420 13:22:51.116887 <6>[ 0.102118] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10421 13:22:51.119976 <6>[ 0.102426] CPU features: detected: Spectre-v4
10422 13:22:51.126577 <6>[ 0.102432] CPU features: detected: Spectre-BHB
10423 13:22:51.129680 <6>[ 0.102437] Detected PIPT I-cache on CPU4
10424 13:22:51.136818 <6>[ 0.102492] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10425 13:22:51.143344 <6>[ 0.102508] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10426 13:22:51.146598 <6>[ 0.102806] Detected PIPT I-cache on CPU5
10427 13:22:51.156821 <6>[ 0.102867] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10428 13:22:51.163448 <6>[ 0.102884] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10429 13:22:51.166625 <6>[ 0.103170] Detected PIPT I-cache on CPU6
10430 13:22:51.173434 <6>[ 0.103235] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10431 13:22:51.180258 <6>[ 0.103252] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10432 13:22:51.183824 <6>[ 0.103551] Detected PIPT I-cache on CPU7
10433 13:22:51.193663 <6>[ 0.103614] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10434 13:22:51.200118 <6>[ 0.103631] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10435 13:22:51.203113 <6>[ 0.103677] smp: Brought up 1 node, 8 CPUs
10436 13:22:51.206749 <6>[ 0.244979] SMP: Total of 8 processors activated.
10437 13:22:51.214105 <6>[ 0.249900] CPU features: detected: 32-bit EL0 Support
10438 13:22:51.223387 <6>[ 0.255262] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10439 13:22:51.229858 <6>[ 0.264062] CPU features: detected: Common not Private translations
10440 13:22:51.232904 <6>[ 0.270537] CPU features: detected: CRC32 instructions
10441 13:22:51.240227 <6>[ 0.275921] CPU features: detected: RCpc load-acquire (LDAPR)
10442 13:22:51.246737 <6>[ 0.281918] CPU features: detected: LSE atomic instructions
10443 13:22:51.252659 <6>[ 0.287735] CPU features: detected: Privileged Access Never
10444 13:22:51.256200 <6>[ 0.293514] CPU features: detected: RAS Extension Support
10445 13:22:51.263232 <6>[ 0.299157] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10446 13:22:51.269339 <6>[ 0.306378] CPU: All CPU(s) started at EL2
10447 13:22:51.273018 <6>[ 0.310721] alternatives: applying system-wide alternatives
10448 13:22:51.284503 <6>[ 0.321417] devtmpfs: initialized
10449 13:22:51.296770 <6>[ 0.330396] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10450 13:22:51.307057 <6>[ 0.340356] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10451 13:22:51.313199 <6>[ 0.348388] pinctrl core: initialized pinctrl subsystem
10452 13:22:51.316689 <6>[ 0.355031] DMI not present or invalid.
10453 13:22:51.323447 <6>[ 0.359438] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10454 13:22:51.330192 <6>[ 0.366306] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10455 13:22:51.340493 <6>[ 0.373888] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10456 13:22:51.347219 <6>[ 0.382098] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10457 13:22:51.353476 <6>[ 0.390341] audit: initializing netlink subsys (disabled)
10458 13:22:51.363588 <5>[ 0.396034] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10459 13:22:51.366758 <6>[ 0.396745] thermal_sys: Registered thermal governor 'step_wise'
10460 13:22:51.373725 <6>[ 0.404004] thermal_sys: Registered thermal governor 'power_allocator'
10461 13:22:51.380191 <6>[ 0.410257] cpuidle: using governor menu
10462 13:22:51.383624 <6>[ 0.421222] NET: Registered PF_QIPCRTR protocol family
10463 13:22:51.390345 <6>[ 0.426715] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10464 13:22:51.396837 <6>[ 0.433822] ASID allocator initialised with 32768 entries
10465 13:22:51.403184 <6>[ 0.440383] Serial: AMBA PL011 UART driver
10466 13:22:51.412309 <4>[ 0.449150] Trying to register duplicate clock ID: 134
10467 13:22:51.468552 <6>[ 0.508549] KASLR enabled
10468 13:22:51.482921 <6>[ 0.516302] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10469 13:22:51.489534 <6>[ 0.523313] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10470 13:22:51.496059 <6>[ 0.529800] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10471 13:22:51.502387 <6>[ 0.536804] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10472 13:22:51.509754 <6>[ 0.543291] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10473 13:22:51.515701 <6>[ 0.550297] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10474 13:22:51.522540 <6>[ 0.556784] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10475 13:22:51.529219 <6>[ 0.563789] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10476 13:22:51.532226 <6>[ 0.571301] ACPI: Interpreter disabled.
10477 13:22:51.540369 <6>[ 0.577705] iommu: Default domain type: Translated
10478 13:22:51.547480 <6>[ 0.582815] iommu: DMA domain TLB invalidation policy: strict mode
10479 13:22:51.550432 <5>[ 0.589472] SCSI subsystem initialized
10480 13:22:51.557056 <6>[ 0.593636] usbcore: registered new interface driver usbfs
10481 13:22:51.564541 <6>[ 0.599365] usbcore: registered new interface driver hub
10482 13:22:51.567644 <6>[ 0.604918] usbcore: registered new device driver usb
10483 13:22:51.574066 <6>[ 0.611014] pps_core: LinuxPPS API ver. 1 registered
10484 13:22:51.584645 <6>[ 0.616208] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10485 13:22:51.587332 <6>[ 0.625556] PTP clock support registered
10486 13:22:51.590566 <6>[ 0.629798] EDAC MC: Ver: 3.0.0
10487 13:22:51.597769 <6>[ 0.634957] FPGA manager framework
10488 13:22:51.601140 <6>[ 0.638639] Advanced Linux Sound Architecture Driver Initialized.
10489 13:22:51.604924 <6>[ 0.645418] vgaarb: loaded
10490 13:22:51.611813 <6>[ 0.648595] clocksource: Switched to clocksource arch_sys_counter
10491 13:22:51.618052 <5>[ 0.655028] VFS: Disk quotas dquot_6.6.0
10492 13:22:51.625119 <6>[ 0.659215] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10493 13:22:51.628485 <6>[ 0.666405] pnp: PnP ACPI: disabled
10494 13:22:51.635983 <6>[ 0.673094] NET: Registered PF_INET protocol family
10495 13:22:51.642805 <6>[ 0.678679] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10496 13:22:51.658276 <6>[ 0.690978] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10497 13:22:51.667252 <6>[ 0.699792] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10498 13:22:51.673892 <6>[ 0.707761] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10499 13:22:51.681039 <6>[ 0.716461] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10500 13:22:51.692531 <6>[ 0.726191] TCP: Hash tables configured (established 65536 bind 65536)
10501 13:22:51.699671 <6>[ 0.733049] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10502 13:22:51.705516 <6>[ 0.740248] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10503 13:22:51.712568 <6>[ 0.747947] NET: Registered PF_UNIX/PF_LOCAL protocol family
10504 13:22:51.719438 <6>[ 0.754122] RPC: Registered named UNIX socket transport module.
10505 13:22:51.722379 <6>[ 0.760277] RPC: Registered udp transport module.
10506 13:22:51.729047 <6>[ 0.765209] RPC: Registered tcp transport module.
10507 13:22:51.735712 <6>[ 0.770141] RPC: Registered tcp NFSv4.1 backchannel transport module.
10508 13:22:51.738907 <6>[ 0.776813] PCI: CLS 0 bytes, default 64
10509 13:22:51.742079 <6>[ 0.781163] Unpacking initramfs...
10510 13:22:51.752178 <6>[ 0.785310] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10511 13:22:51.759742 <6>[ 0.793943] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10512 13:22:51.765706 <6>[ 0.802824] kvm [1]: IPA Size Limit: 40 bits
10513 13:22:51.769215 <6>[ 0.807367] kvm [1]: GICv3: no GICV resource entry
10514 13:22:51.775668 <6>[ 0.812388] kvm [1]: disabling GICv2 emulation
10515 13:22:51.782841 <6>[ 0.817076] kvm [1]: GIC system register CPU interface enabled
10516 13:22:51.785547 <6>[ 0.823240] kvm [1]: vgic interrupt IRQ18
10517 13:22:51.792172 <6>[ 0.827598] kvm [1]: VHE mode initialized successfully
10518 13:22:51.795681 <5>[ 0.834110] Initialise system trusted keyrings
10519 13:22:51.802319 <6>[ 0.838944] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10520 13:22:51.811838 <6>[ 0.849091] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10521 13:22:51.818788 <5>[ 0.855478] NFS: Registering the id_resolver key type
10522 13:22:51.822300 <5>[ 0.860783] Key type id_resolver registered
10523 13:22:51.828518 <5>[ 0.865198] Key type id_legacy registered
10524 13:22:51.835140 <6>[ 0.869479] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10525 13:22:51.841934 <6>[ 0.876403] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10526 13:22:51.848707 <6>[ 0.884112] 9p: Installing v9fs 9p2000 file system support
10527 13:22:51.885076 <5>[ 0.922318] Key type asymmetric registered
10528 13:22:51.888174 <5>[ 0.926648] Asymmetric key parser 'x509' registered
10529 13:22:51.898945 <6>[ 0.931788] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10530 13:22:51.902220 <6>[ 0.939403] io scheduler mq-deadline registered
10531 13:22:51.904804 <6>[ 0.944165] io scheduler kyber registered
10532 13:22:51.924396 <6>[ 0.961200] EINJ: ACPI disabled.
10533 13:22:51.957164 <4>[ 0.987236] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10534 13:22:51.966491 <4>[ 0.997884] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10535 13:22:51.981637 <6>[ 1.018742] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10536 13:22:51.989902 <6>[ 1.026666] printk: console [ttyS0] disabled
10537 13:22:52.017981 <6>[ 1.051321] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10538 13:22:52.024271 <6>[ 1.060844] printk: console [ttyS0] enabled
10539 13:22:52.027705 <6>[ 1.060844] printk: console [ttyS0] enabled
10540 13:22:52.034132 <6>[ 1.069737] printk: bootconsole [mtk8250] disabled
10541 13:22:52.037688 <6>[ 1.069737] printk: bootconsole [mtk8250] disabled
10542 13:22:52.044275 <6>[ 1.081151] SuperH (H)SCI(F) driver initialized
10543 13:22:52.047230 <6>[ 1.086428] msm_serial: driver initialized
10544 13:22:52.061427 <6>[ 1.095419] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10545 13:22:52.071535 <6>[ 1.103969] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10546 13:22:52.078347 <6>[ 1.112510] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10547 13:22:52.088408 <6>[ 1.121140] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10548 13:22:52.094620 <6>[ 1.129848] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10549 13:22:52.105044 <6>[ 1.138562] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10550 13:22:52.115157 <6>[ 1.147111] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10551 13:22:52.121527 <6>[ 1.155922] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10552 13:22:52.131717 <6>[ 1.164466] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10553 13:22:52.143135 <6>[ 1.180122] loop: module loaded
10554 13:22:52.149990 <6>[ 1.186162] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10555 13:22:52.172402 <4>[ 1.209772] mtk-pmic-keys: Failed to locate of_node [id: -1]
10556 13:22:52.179641 <6>[ 1.216842] megasas: 07.719.03.00-rc1
10557 13:22:52.189246 <6>[ 1.226495] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10558 13:22:52.199453 <6>[ 1.235973] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10559 13:22:52.215704 <6>[ 1.252741] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10560 13:22:52.272800 <6>[ 1.303163] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10561 13:22:52.527831 <6>[ 1.564483] Freeing initrd memory: 17356K
10562 13:22:52.537595 <6>[ 1.575004] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10563 13:22:52.548432 <6>[ 1.585830] tun: Universal TUN/TAP device driver, 1.6
10564 13:22:52.551838 <6>[ 1.591886] thunder_xcv, ver 1.0
10565 13:22:52.555318 <6>[ 1.595389] thunder_bgx, ver 1.0
10566 13:22:52.558445 <6>[ 1.598884] nicpf, ver 1.0
10567 13:22:52.569388 <6>[ 1.602895] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10568 13:22:52.572318 <6>[ 1.610369] hns3: Copyright (c) 2017 Huawei Corporation.
10569 13:22:52.575518 <6>[ 1.615957] hclge is initializing
10570 13:22:52.582271 <6>[ 1.619531] e1000: Intel(R) PRO/1000 Network Driver
10571 13:22:52.589229 <6>[ 1.624661] e1000: Copyright (c) 1999-2006 Intel Corporation.
10572 13:22:52.592107 <6>[ 1.630673] e1000e: Intel(R) PRO/1000 Network Driver
10573 13:22:52.599903 <6>[ 1.635889] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10574 13:22:52.606053 <6>[ 1.642079] igb: Intel(R) Gigabit Ethernet Network Driver
10575 13:22:52.612525 <6>[ 1.647729] igb: Copyright (c) 2007-2014 Intel Corporation.
10576 13:22:52.619153 <6>[ 1.653565] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10577 13:22:52.625707 <6>[ 1.660084] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10578 13:22:52.629175 <6>[ 1.666542] sky2: driver version 1.30
10579 13:22:52.635227 <6>[ 1.671533] VFIO - User Level meta-driver version: 0.3
10580 13:22:52.642624 <6>[ 1.679752] usbcore: registered new interface driver usb-storage
10581 13:22:52.648959 <6>[ 1.686199] usbcore: registered new device driver onboard-usb-hub
10582 13:22:52.658210 <6>[ 1.695301] mt6397-rtc mt6359-rtc: registered as rtc0
10583 13:22:52.668413 <6>[ 1.700769] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-06T13:22:54 UTC (1694006574)
10584 13:22:52.671473 <6>[ 1.710327] i2c_dev: i2c /dev entries driver
10585 13:22:52.688557 <6>[ 1.722070] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10586 13:22:52.709046 <6>[ 1.746056] cpu cpu0: EM: created perf domain
10587 13:22:52.712089 <6>[ 1.751144] cpu cpu4: EM: created perf domain
10588 13:22:52.719446 <6>[ 1.756746] sdhci: Secure Digital Host Controller Interface driver
10589 13:22:52.726688 <6>[ 1.763176] sdhci: Copyright(c) Pierre Ossman
10590 13:22:52.733502 <6>[ 1.768140] Synopsys Designware Multimedia Card Interface Driver
10591 13:22:52.740241 <6>[ 1.774780] sdhci-pltfm: SDHCI platform and OF driver helper
10592 13:22:52.743453 <6>[ 1.774902] mmc0: CQHCI version 5.10
10593 13:22:52.749748 <6>[ 1.784783] ledtrig-cpu: registered to indicate activity on CPUs
10594 13:22:52.756229 <6>[ 1.791752] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10595 13:22:52.763811 <6>[ 1.798801] usbcore: registered new interface driver usbhid
10596 13:22:52.766395 <6>[ 1.804624] usbhid: USB HID core driver
10597 13:22:52.773054 <6>[ 1.808825] spi_master spi0: will run message pump with realtime priority
10598 13:22:52.815884 <6>[ 1.846290] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10599 13:22:52.830585 <6>[ 1.861276] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10600 13:22:52.837869 <6>[ 1.874890] mmc0: Command Queue Engine enabled
10601 13:22:52.845026 <6>[ 1.879655] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10602 13:22:52.852117 <6>[ 1.886618] cros-ec-spi spi0.0: Chrome EC device registered
10603 13:22:52.854733 <6>[ 1.887053] mmcblk0: mmc0:0001 DA4128 116 GiB
10604 13:22:52.864065 <6>[ 1.900959] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10605 13:22:52.871212 <6>[ 1.908417] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10606 13:22:52.877483 <6>[ 1.914259] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10607 13:22:52.884796 <6>[ 1.920135] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10608 13:22:52.899800 <6>[ 1.933349] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10609 13:22:52.907462 <6>[ 1.944320] NET: Registered PF_PACKET protocol family
10610 13:22:52.910987 <6>[ 1.949723] 9pnet: Installing 9P2000 support
10611 13:22:52.917343 <5>[ 1.954288] Key type dns_resolver registered
10612 13:22:52.921312 <6>[ 1.959290] registered taskstats version 1
10613 13:22:52.927438 <5>[ 1.963677] Loading compiled-in X.509 certificates
10614 13:22:52.958844 <4>[ 1.989154] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10615 13:22:52.969692 <4>[ 2.000007] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10616 13:22:52.975337 <3>[ 2.010547] debugfs: File 'uA_load' in directory '/' already present!
10617 13:22:52.981953 <3>[ 2.017255] debugfs: File 'min_uV' in directory '/' already present!
10618 13:22:52.989004 <3>[ 2.023864] debugfs: File 'max_uV' in directory '/' already present!
10619 13:22:52.995125 <3>[ 2.030471] debugfs: File 'constraint_flags' in directory '/' already present!
10620 13:22:53.006527 <3>[ 2.040172] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10621 13:22:53.021234 <6>[ 2.058003] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10622 13:22:53.028283 <6>[ 2.064873] xhci-mtk 11200000.usb: xHCI Host Controller
10623 13:22:53.034508 <6>[ 2.070403] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10624 13:22:53.045380 <6>[ 2.078279] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10625 13:22:53.051298 <6>[ 2.087714] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10626 13:22:53.057838 <6>[ 2.093820] xhci-mtk 11200000.usb: xHCI Host Controller
10627 13:22:53.064516 <6>[ 2.099308] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10628 13:22:53.070749 <6>[ 2.106965] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10629 13:22:53.078228 <6>[ 2.114822] hub 1-0:1.0: USB hub found
10630 13:22:53.081271 <6>[ 2.118844] hub 1-0:1.0: 1 port detected
10631 13:22:53.087507 <6>[ 2.123157] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10632 13:22:53.094765 <6>[ 2.131939] hub 2-0:1.0: USB hub found
10633 13:22:53.097839 <6>[ 2.135961] hub 2-0:1.0: 1 port detected
10634 13:22:53.106428 <6>[ 2.143815] mtk-msdc 11f70000.mmc: Got CD GPIO
10635 13:22:53.119648 <6>[ 2.153416] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10636 13:22:53.126543 <6>[ 2.161450] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10637 13:22:53.136441 <4>[ 2.169389] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10638 13:22:53.146412 <6>[ 2.178963] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10639 13:22:53.153060 <6>[ 2.187042] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10640 13:22:53.159799 <6>[ 2.195057] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10641 13:22:53.170125 <6>[ 2.202982] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10642 13:22:53.176562 <6>[ 2.210799] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10643 13:22:53.186748 <6>[ 2.218616] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10644 13:22:53.196649 <6>[ 2.229133] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10645 13:22:53.203381 <6>[ 2.237497] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10646 13:22:53.213115 <6>[ 2.245846] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10647 13:22:53.220358 <6>[ 2.254184] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10648 13:22:53.229771 <6>[ 2.262530] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10649 13:22:53.236579 <6>[ 2.270868] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10650 13:22:53.246601 <6>[ 2.279206] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10651 13:22:53.253503 <6>[ 2.287543] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10652 13:22:53.263697 <6>[ 2.295881] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10653 13:22:53.269746 <6>[ 2.304218] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10654 13:22:53.280850 <6>[ 2.312557] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10655 13:22:53.286524 <6>[ 2.320895] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10656 13:22:53.296651 <6>[ 2.329233] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10657 13:22:53.303636 <6>[ 2.337571] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10658 13:22:53.313244 <6>[ 2.345910] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10659 13:22:53.320276 <6>[ 2.354645] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10660 13:22:53.326624 <6>[ 2.361806] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10661 13:22:53.333365 <6>[ 2.368568] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10662 13:22:53.339843 <6>[ 2.375328] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10663 13:22:53.346688 <6>[ 2.382269] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10664 13:22:53.356935 <6>[ 2.389111] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10665 13:22:53.366299 <6>[ 2.398243] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10666 13:22:53.373319 <6>[ 2.407362] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10667 13:22:53.382866 <6>[ 2.416659] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10668 13:22:53.393027 <6>[ 2.426128] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10669 13:22:53.403034 <6>[ 2.435595] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10670 13:22:53.413145 <6>[ 2.444716] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10671 13:22:53.420027 <6>[ 2.454183] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10672 13:22:53.429661 <6>[ 2.463303] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10673 13:22:53.440141 <6>[ 2.472598] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10674 13:22:53.449724 <6>[ 2.482768] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10675 13:22:53.460549 <6>[ 2.494252] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10676 13:22:53.466989 <6>[ 2.504125] Trying to probe devices needed for running init ...
10677 13:22:53.510814 <6>[ 2.544873] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10678 13:22:53.665682 <6>[ 2.702854] hub 1-1:1.0: USB hub found
10679 13:22:53.668980 <6>[ 2.707361] hub 1-1:1.0: 4 ports detected
10680 13:22:53.791074 <6>[ 2.824867] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10681 13:22:53.816805 <6>[ 2.853920] hub 2-1:1.0: USB hub found
10682 13:22:53.820034 <6>[ 2.858392] hub 2-1:1.0: 3 ports detected
10683 13:22:53.991115 <6>[ 3.024880] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10684 13:22:54.122896 <6>[ 3.160016] hub 1-1.4:1.0: USB hub found
10685 13:22:54.125949 <6>[ 3.164545] hub 1-1.4:1.0: 2 ports detected
10686 13:22:54.203076 <6>[ 3.236925] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10687 13:22:54.423472 <6>[ 3.456881] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10688 13:22:54.615219 <6>[ 3.648911] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10689 13:23:05.763911 <6>[ 14.805909] ALSA device list:
10690 13:23:05.770424 <6>[ 14.809199] No soundcards found.
10691 13:23:05.778204 <6>[ 14.817158] Freeing unused kernel memory: 8384K
10692 13:23:05.781777 <6>[ 14.822187] Run /init as init process
10693 13:23:05.793490 Loading, please wait...
10694 13:23:05.813993 Starting version 247.3-7+deb11u2
10695 13:23:06.092287 <6>[ 15.127679] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10696 13:23:06.099241 <6>[ 15.127763] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10697 13:23:06.108998 <6>[ 15.142633] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10698 13:23:06.112275 <6>[ 15.143993] remoteproc remoteproc0: scp is available
10699 13:23:06.122667 <6>[ 15.151345] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10700 13:23:06.125995 <6>[ 15.156671] remoteproc remoteproc0: powering up scp
10701 13:23:06.133016 <6>[ 15.159861] mc: Linux media interface: v0.10
10702 13:23:06.139218 <6>[ 15.174898] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10703 13:23:06.145353 <4>[ 15.180905] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10704 13:23:06.151641 <6>[ 15.184435] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10705 13:23:06.161855 <3>[ 15.187549] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 13:23:06.168247 <3>[ 15.187568] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 13:23:06.175387 <3>[ 15.187576] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 13:23:06.185733 <3>[ 15.187696] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 13:23:06.192794 <3>[ 15.187706] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 13:23:06.202610 <3>[ 15.187713] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 13:23:06.209323 <3>[ 15.187721] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 13:23:06.216278 <3>[ 15.187729] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10713 13:23:06.225826 <3>[ 15.187769] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 13:23:06.232505 <3>[ 15.187809] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 13:23:06.242628 <3>[ 15.187817] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 13:23:06.249633 <3>[ 15.187824] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10717 13:23:06.256797 <3>[ 15.187869] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10718 13:23:06.266979 <3>[ 15.187877] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10719 13:23:06.273126 <3>[ 15.187884] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10720 13:23:06.283473 <3>[ 15.187892] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10721 13:23:06.289856 <3>[ 15.187899] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10722 13:23:06.299692 <3>[ 15.187929] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 13:23:06.306500 <6>[ 15.190323] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10724 13:23:06.312864 <4>[ 15.190739] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10725 13:23:06.319779 <6>[ 15.192204] usbcore: registered new interface driver r8152
10726 13:23:06.323449 <6>[ 15.213526] videodev: Linux video capture interface: v2.00
10727 13:23:06.333048 <4>[ 15.219284] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10728 13:23:06.339798 <4>[ 15.219284] Fallback method does not support PEC.
10729 13:23:06.346996 <3>[ 15.234563] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10730 13:23:06.353425 <6>[ 15.277142] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10731 13:23:06.359550 <6>[ 15.286158] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10732 13:23:06.373318 <6>[ 15.293249] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10733 13:23:06.379314 <3>[ 15.300437] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10734 13:23:06.386487 <6>[ 15.301804] pci_bus 0000:00: root bus resource [bus 00-ff]
10735 13:23:06.396523 <6>[ 15.302016] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10736 13:23:06.402744 <4>[ 15.316825] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10737 13:23:06.409401 <6>[ 15.317671] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10738 13:23:06.419768 <6>[ 15.317725] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10739 13:23:06.426209 <6>[ 15.317733] remoteproc remoteproc0: remote processor scp is now up
10740 13:23:06.432912 <6>[ 15.317824] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10741 13:23:06.440322 <4>[ 15.325864] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10742 13:23:06.449680 <6>[ 15.327761] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10743 13:23:06.459702 <6>[ 15.333957] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10744 13:23:06.465889 <6>[ 15.334077] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10745 13:23:06.469733 <6>[ 15.391720] r8152 2-1.3:1.0 eth0: v1.12.13
10746 13:23:06.479272 <6>[ 15.398439] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10747 13:23:06.482909 <6>[ 15.416647] usbcore: registered new interface driver cdc_ether
10748 13:23:06.489359 <6>[ 15.416681] Bluetooth: Core ver 2.22
10749 13:23:06.492468 <6>[ 15.416773] NET: Registered PF_BLUETOOTH protocol family
10750 13:23:06.499305 <6>[ 15.416777] Bluetooth: HCI device and connection manager initialized
10751 13:23:06.506638 <6>[ 15.416806] Bluetooth: HCI socket layer initialized
10752 13:23:06.509807 <6>[ 15.416827] Bluetooth: L2CAP socket layer initialized
10753 13:23:06.515840 <6>[ 15.416851] Bluetooth: SCO socket layer initialized
10754 13:23:06.519552 <6>[ 15.423841] pci 0000:00:00.0: supports D1 D2
10755 13:23:06.526165 <6>[ 15.431562] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10756 13:23:06.535990 <6>[ 15.431820] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10757 13:23:06.542678 <6>[ 15.433755] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10758 13:23:06.549205 <6>[ 15.438537] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10759 13:23:06.556100 <6>[ 15.438958] usbcore: registered new interface driver r8153_ecm
10760 13:23:06.565996 <6>[ 15.439787] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10761 13:23:06.572933 <6>[ 15.439873] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10762 13:23:06.579160 <6>[ 15.439898] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10763 13:23:06.585987 <6>[ 15.439915] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10764 13:23:06.592749 <6>[ 15.439930] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10765 13:23:06.599116 <6>[ 15.440036] pci 0000:01:00.0: supports D1 D2
10766 13:23:06.605514 <6>[ 15.440037] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10767 13:23:06.612200 <6>[ 15.448503] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10768 13:23:06.625399 <6>[ 15.448958] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10769 13:23:06.628504 <6>[ 15.449058] usbcore: registered new interface driver uvcvideo
10770 13:23:06.635230 <6>[ 15.452651] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10771 13:23:06.645142 <6>[ 15.452679] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10772 13:23:06.652003 <6>[ 15.452683] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10773 13:23:06.661504 <6>[ 15.452690] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10774 13:23:06.668479 <6>[ 15.452703] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10775 13:23:06.678995 <6>[ 15.452715] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10776 13:23:06.681627 <6>[ 15.452727] pci 0000:00:00.0: PCI bridge to [bus 01]
10777 13:23:06.691958 <6>[ 15.452733] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10778 13:23:06.694626 <6>[ 15.452854] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10779 13:23:06.701475 <6>[ 15.453335] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10780 13:23:06.708338 <6>[ 15.453789] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10781 13:23:06.715415 <6>[ 15.460088] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10782 13:23:06.721636 <6>[ 15.471200] usbcore: registered new interface driver btusb
10783 13:23:06.732241 <4>[ 15.471784] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10784 13:23:06.737942 <3>[ 15.471791] Bluetooth: hci0: Failed to load firmware file (-2)
10785 13:23:06.741309 <3>[ 15.471793] Bluetooth: hci0: Failed to set up firmware (-2)
10786 13:23:06.754880 <4>[ 15.471796] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10787 13:23:06.771483 <5>[ 15.807061] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10788 13:23:06.793135 <5>[ 15.828747] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10789 13:23:06.799978 <4>[ 15.835636] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10790 13:23:06.806322 <6>[ 15.844543] cfg80211: failed to load regulatory.db
10791 13:23:06.862256 <6>[ 15.897548] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10792 13:23:06.868691 <6>[ 15.905220] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10793 13:23:06.893079 <6>[ 15.931971] mt7921e 0000:01:00.0: ASIC revision: 79610010
10794 13:23:07.000113 <4>[ 16.032293] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10795 13:23:07.014608 Begin: Loading essential drivers ... done.
10796 13:23:07.017633 Begin: Running /scripts/init-premount ... done.
10797 13:23:07.024899 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10798 13:23:07.034357 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10799 13:23:07.037882 Device /sys/class/net/enx002432307852 found
10800 13:23:07.038340 done.
10801 13:23:07.123316 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mt<4>[ 16.153244] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10802 13:23:07.124022 u 1500 DHCP
10803 13:23:07.239891 <4>[ 16.272421] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10804 13:23:07.360073 <4>[ 16.392478] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10805 13:23:07.480609 <4>[ 16.512616] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10806 13:23:07.599885 <4>[ 16.632531] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10807 13:23:07.720323 <4>[ 16.752663] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10808 13:23:07.839851 <4>[ 16.872443] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10809 13:23:07.960346 <4>[ 16.992538] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10810 13:23:07.975440 <6>[ 17.014719] r8152 2-1.3:1.0 enx002432307852: carrier on
10811 13:23:08.080437 <4>[ 17.112515] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10812 13:23:08.161824 IP-Config: no response after 2 secs - giving up
10813 13:23:08.191321 <3>[ 17.230103] mt7921e 0000:01:00.0: hardware init failed
10814 13:23:08.209576 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10815 13:23:08.216199 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10816 13:23:08.222781 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10817 13:23:08.229049 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10818 13:23:08.236014 host : mt8192-asurada-spherion-r0-cbg-3
10819 13:23:08.242417 domain : lava-rack
10820 13:23:08.245343 rootserver: 192.168.201.1 rootpath:
10821 13:23:08.245470 filename :
10822 13:23:08.295627 done.
10823 13:23:08.303722 Begin: Running /scripts/nfs-bottom ... done.
10824 13:23:08.321037 Begin: Running /scripts/init-bottom ... done.
10825 13:23:09.585307 <6>[ 18.624191] NET: Registered PF_INET6 protocol family
10826 13:23:09.591972 <6>[ 18.631425] Segment Routing with IPv6
10827 13:23:09.595774 <6>[ 18.635483] In-situ OAM (IOAM) with IPv6
10828 13:23:09.732744 <30>[ 18.755018] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10829 13:23:09.740246 <30>[ 18.779435] systemd[1]: Detected architecture arm64.
10830 13:23:09.763263
10831 13:23:09.766403 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10832 13:23:09.766966
10833 13:23:09.784555 <30>[ 18.823875] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10834 13:23:10.787384 <30>[ 19.823102] systemd[1]: Queued start job for default target Graphical Interface.
10835 13:23:10.819534 <30>[ 19.859272] systemd[1]: Created slice system-getty.slice.
10836 13:23:10.826176 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10837 13:23:10.843085 <30>[ 19.882267] systemd[1]: Created slice system-modprobe.slice.
10838 13:23:10.849467 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10839 13:23:10.867739 <30>[ 19.906991] systemd[1]: Created slice system-serial\x2dgetty.slice.
10840 13:23:10.878136 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10841 13:23:10.890855 <30>[ 19.929979] systemd[1]: Created slice User and Session Slice.
10842 13:23:10.897464 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10843 13:23:10.917570 <30>[ 19.953711] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10844 13:23:10.927308 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10845 13:23:10.945458 <30>[ 19.981634] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10846 13:23:10.952512 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10847 13:23:10.976663 <30>[ 20.009478] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10848 13:23:10.984001 <30>[ 20.021715] systemd[1]: Reached target Local Encrypted Volumes.
10849 13:23:10.990049 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10850 13:23:11.006091 <30>[ 20.045443] systemd[1]: Reached target Paths.
10851 13:23:11.012811 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10852 13:23:11.025653 <30>[ 20.064961] systemd[1]: Reached target Remote File Systems.
10853 13:23:11.032044 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10854 13:23:11.049617 <30>[ 20.088858] systemd[1]: Reached target Slices.
10855 13:23:11.052588 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10856 13:23:11.069476 <30>[ 20.108976] systemd[1]: Reached target Swap.
10857 13:23:11.072840 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10858 13:23:11.093886 <30>[ 20.129384] systemd[1]: Listening on initctl Compatibility Named Pipe.
10859 13:23:11.099841 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10860 13:23:11.106357 <30>[ 20.145789] systemd[1]: Listening on Journal Audit Socket.
10861 13:23:11.113435 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10862 13:23:11.131212 <30>[ 20.170616] systemd[1]: Listening on Journal Socket (/dev/log).
10863 13:23:11.137712 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10864 13:23:11.154387 <30>[ 20.193438] systemd[1]: Listening on Journal Socket.
10865 13:23:11.160827 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10866 13:23:11.178830 <30>[ 20.214773] systemd[1]: Listening on Network Service Netlink Socket.
10867 13:23:11.185148 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10868 13:23:11.201383 <30>[ 20.240687] systemd[1]: Listening on udev Control Socket.
10869 13:23:11.207944 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10870 13:23:11.222186 <30>[ 20.261326] systemd[1]: Listening on udev Kernel Socket.
10871 13:23:11.228467 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10872 13:23:11.273846 <30>[ 20.313287] systemd[1]: Mounting Huge Pages File System...
10873 13:23:11.280566 Mounting [0;1;39mHuge Pages File System[0m...
10874 13:23:11.295937 <30>[ 20.335463] systemd[1]: Mounting POSIX Message Queue File System...
10875 13:23:11.302595 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10876 13:23:11.365833 <30>[ 20.405106] systemd[1]: Mounting Kernel Debug File System...
10877 13:23:11.371980 Mounting [0;1;39mKernel Debug File System[0m...
10878 13:23:11.389294 <30>[ 20.425350] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10879 13:23:11.404693 <30>[ 20.440818] systemd[1]: Starting Create list of static device nodes for the current kernel...
10880 13:23:11.411329 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10881 13:23:11.461687 <30>[ 20.501391] systemd[1]: Starting Load Kernel Module configfs...
10882 13:23:11.468204 Starting [0;1;39mLoad Kernel Module configfs[0m...
10883 13:23:11.490448 <30>[ 20.529633] systemd[1]: Starting Load Kernel Module drm...
10884 13:23:11.496391 Starting [0;1;39mLoad Kernel Module drm[0m...
10885 13:23:11.512397 <30>[ 20.552045] systemd[1]: Starting Load Kernel Module fuse...
10886 13:23:11.518947 Starting [0;1;39mLoad Kernel Module fuse[0m...
10887 13:23:11.561646 <30>[ 20.597794] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10888 13:23:11.568885 <6>[ 20.608505] fuse: init (API version 7.37)
10889 13:23:11.577162 <30>[ 20.616521] systemd[1]: Starting Journal Service...
10890 13:23:11.583794 Starting [0;1;39mJournal Service[0m...
10891 13:23:11.626039 <30>[ 20.665372] systemd[1]: Starting Load Kernel Modules...
10892 13:23:11.632533 Starting [0;1;39mLoad Kernel Modules[0m...
10893 13:23:11.658313 <30>[ 20.694558] systemd[1]: Starting Remount Root and Kernel File Systems...
10894 13:23:11.665097 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10895 13:23:11.682787 <30>[ 20.722959] systemd[1]: Starting Coldplug All udev Devices...
10896 13:23:11.689459 Starting [0;1;39mColdplug All udev Devices[0m...
10897 13:23:11.711596 <30>[ 20.751694] systemd[1]: Mounted Huge Pages File System.
10898 13:23:11.718178 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10899 13:23:11.732611 <3>[ 20.769389] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 13:23:11.739791 <30>[ 20.779573] systemd[1]: Mounted POSIX Message Queue File System.
10901 13:23:11.746922 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10902 13:23:11.761787 <30>[ 20.801120] systemd[1]: Mounted Kernel Debug File System.
10903 13:23:11.771659 <3>[ 20.802713] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 13:23:11.778154 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10905 13:23:11.802330 <30>[ 20.838465] systemd[1]: Finished Create list of static device nodes for the current kernel.
10906 13:23:11.809330 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10907 13:23:11.819703 <3>[ 20.855599] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 13:23:11.825984 <30>[ 20.865689] systemd[1]: modprobe@configfs.service: Succeeded.
10909 13:23:11.832876 <30>[ 20.872433] systemd[1]: Finished Load Kernel Module configfs.
10910 13:23:11.840144 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10911 13:23:11.850344 <3>[ 20.886085] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 13:23:11.857128 <30>[ 20.895949] systemd[1]: modprobe@drm.service: Succeeded.
10913 13:23:11.863580 <30>[ 20.902259] systemd[1]: Finished Load Kernel Module drm.
10914 13:23:11.871670 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10915 13:23:11.881588 <3>[ 20.915709] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 13:23:11.887728 <30>[ 20.925853] systemd[1]: modprobe@fuse.service: Succeeded.
10917 13:23:11.895039 <30>[ 20.932308] systemd[1]: Finished Load Kernel Module fuse.
10918 13:23:11.898243 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10919 13:23:11.910063 <3>[ 20.945951] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 13:23:11.919169 <30>[ 20.958308] systemd[1]: Finished Load Kernel Modules.
10921 13:23:11.925574 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10922 13:23:11.939948 <3>[ 20.975737] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 13:23:11.950024 <30>[ 20.986256] systemd[1]: Finished Remount Root and Kernel File Systems.
10924 13:23:11.957356 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10925 13:23:11.971674 <3>[ 21.007506] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 13:23:12.002797 <3>[ 21.039068] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 13:23:12.009348 <30>[ 21.045997] systemd[1]: Mounting FUSE Control File System...
10928 13:23:12.015934 Mounting [0;1;39mFUSE Control File System[0m...
10929 13:23:12.032363 <3>[ 21.069007] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 13:23:12.039180 <30>[ 21.071744] systemd[1]: Mounting Kernel Configuration File System...
10931 13:23:12.045659 Mounting [0;1;39mKernel Configuration File System[0m...
10932 13:23:12.071751 <30>[ 21.107086] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10933 13:23:12.081906 <30>[ 21.116225] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10934 13:23:12.102493 <30>[ 21.141511] systemd[1]: Starting Load/Save Random Seed...
10935 13:23:12.109386 Starting [0;1;39mLoad/Save Random Seed[0m...
10936 13:23:12.125488 <30>[ 21.165234] systemd[1]: Starting Apply Kernel Variables...
10937 13:23:12.132395 Starting [0;1;39mApply Kernel Variables[0m...
10938 13:23:12.157463 <4>[ 21.187185] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10939 13:23:12.164602 <3>[ 21.202901] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10940 13:23:12.170769 <30>[ 21.206592] systemd[1]: Starting Create System Users...
10941 13:23:12.177560 Starting [0;1;39mCreate System Users[0m...
10942 13:23:12.191697 <30>[ 21.230668] systemd[1]: Started Journal Service.
10943 13:23:12.194832 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10944 13:23:12.221600 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10945 13:23:12.237741 See 'systemctl status systemd-udev-trigger.service' for details.
10946 13:23:12.258413 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10947 13:23:12.278336 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10948 13:23:12.297758 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10949 13:23:12.314258 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10950 13:23:12.331610 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10951 13:23:12.367075 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10952 13:23:12.383541 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10953 13:23:12.432517 <46>[ 21.468494] systemd-journald[291]: Received client request to flush runtime journal.
10954 13:23:13.203676 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10955 13:23:13.217873 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10956 13:23:13.232860 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10957 13:23:13.289303 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10958 13:23:13.865135 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10959 13:23:13.902068 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10960 13:23:14.000764 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10961 13:23:14.050741 Starting [0;1;39mNetwork Service[0m...
10962 13:23:14.349391 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10963 13:23:14.373140 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10964 13:23:14.429147 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10965 13:23:14.646302 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10966 13:23:14.688508 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10967 13:23:14.725785 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10968 13:23:14.788514 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10969 13:23:14.805069 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10970 13:23:14.820688 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10971 13:23:14.844905 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10972 13:23:14.906269 Starting [0;1;39mNetwork Name Resolution[0m...
10973 13:23:14.934944 Starting [0;1;39mNetwork Time Synchronization[0m...
10974 13:23:14.956968 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10975 13:23:15.004459 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10976 13:23:15.158400 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10977 13:23:15.178016 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10978 13:23:15.200794 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10979 13:23:15.216770 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10980 13:23:15.233075 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10981 13:23:15.318188 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10982 13:23:15.364349 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10983 13:23:15.411391 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10984 13:23:15.436753 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10985 13:23:15.456766 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10986 13:23:15.486483 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10987 13:23:15.505154 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10988 13:23:15.521026 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10989 13:23:15.560823 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10990 13:23:16.265409 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10991 13:23:16.625483 Starting [0;1;39mUser Login Management[0m...
10992 13:23:16.642287 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10993 13:23:16.660227 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10994 13:23:16.679988 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10995 13:23:16.729670 Starting [0;1;39mPermit User Sessions[0m...
10996 13:23:16.841225 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10997 13:23:16.868122 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10998 13:23:16.909420 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10999 13:23:16.931414 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11000 13:23:16.952976 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11001 13:23:16.980493 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11002 13:23:17.000502 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11003 13:23:17.018773 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11004 13:23:17.079865 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11005 13:23:17.131958 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11006 13:23:17.199952
11007 13:23:17.200172
11008 13:23:17.202873 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11009 13:23:17.203034
11010 13:23:17.233485 debian-bullseye-arm64 login: root (automatic login)
11011 13:23:17.233891
11012 13:23:17.234210
11013 13:23:17.601425 Linux debian-bullseye-arm64 6.1.46-cip4 #1 SMP PREEMPT Wed Sep 6 13:11:19 UTC 2023 aarch64
11014 13:23:17.601925
11015 13:23:17.608014 The programs included with the Debian GNU/Linux system are free software;
11016 13:23:17.614834 the exact distribution terms for each program are described in the
11017 13:23:17.617976 individual files in /usr/share/doc/*/copyright.
11018 13:23:17.618387
11019 13:23:17.624540 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11020 13:23:17.627608 permitted by applicable law.
11021 13:23:17.752895 Matched prompt #10: / #
11023 13:23:17.754020 Setting prompt string to ['/ #']
11024 13:23:17.754468 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11026 13:23:17.755420 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11027 13:23:17.755846 start: 2.2.6 expect-shell-connection (timeout 00:03:11) [common]
11028 13:23:17.756233 Setting prompt string to ['/ #']
11029 13:23:17.756548 Forcing a shell prompt, looking for ['/ #']
11031 13:23:17.807393 / #
11032 13:23:17.808060 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11033 13:23:17.808563 Waiting using forced prompt support (timeout 00:02:30)
11034 13:23:17.813959
11035 13:23:17.814944 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11036 13:23:17.815622 start: 2.2.7 export-device-env (timeout 00:03:10) [common]
11038 13:23:17.916956 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11445602/extract-nfsrootfs-n61gzwea'
11039 13:23:17.923335 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11445602/extract-nfsrootfs-n61gzwea'
11041 13:23:18.025133 / # export NFS_SERVER_IP='192.168.201.1'
11042 13:23:18.031561 export NFS_SERVER_IP='192.168.201.1'
11043 13:23:18.032489 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11044 13:23:18.033086 end: 2.2 depthcharge-retry (duration 00:01:50) [common]
11045 13:23:18.033564 end: 2 depthcharge-action (duration 00:01:50) [common]
11046 13:23:18.034051 start: 3 lava-test-retry (timeout 00:01:00) [common]
11047 13:23:18.034499 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11048 13:23:18.034922 Using namespace: common
11050 13:23:18.136462 / # #
11051 13:23:18.137165 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11052 13:23:18.143002 #
11053 13:23:18.143885 Using /lava-11445602
11055 13:23:18.245137 / # export SHELL=/bin/sh
11056 13:23:18.252468 export SHELL=/bin/sh
11058 13:23:18.354504 / # . /lava-11445602/environment
11059 13:23:18.361171 . /lava-11445602/environment
11061 13:23:18.469635 / # /lava-11445602/bin/lava-test-runner /lava-11445602/0
11062 13:23:18.470266 Test shell timeout: 10s (minimum of the action and connection timeout)
11063 13:23:18.476394 /lava-11445602/bin/lava-test-runner /lava-11445602/0
11064 13:23:18.759719 + export TESTRUN_ID=0_dmesg
11065 13:23:18.763288 + cd /lava-11445602/0/tests/0_dmesg
11066 13:23:18.766414 + cat uuid
11067 13:23:18.784957 + UUID=11445602_<8>[ 27.822072] <LAVA_SIGNAL_STARTRUN 0_dmesg 11445602_1.6.2.3.1>
11068 13:23:18.785388 1.6.2.3.1
11069 13:23:18.785723 + set +x
11070 13:23:18.786378 Received signal: <STARTRUN> 0_dmesg 11445602_1.6.2.3.1
11071 13:23:18.786758 Starting test lava.0_dmesg (11445602_1.6.2.3.1)
11072 13:23:18.787420 Skipping test definition patterns.
11073 13:23:18.791319 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11074 13:23:18.926120 <8>[ 27.962957] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11075 13:23:18.926960 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11077 13:23:19.024392 <8>[ 28.061577] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11078 13:23:19.025270 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11080 13:23:19.128258 <8>[ 28.165288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11081 13:23:19.129069 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11083 13:23:19.131851 + set +x
11084 13:23:19.134881 <8>[ 28.174653] <LAVA_SIGNAL_ENDRUN 0_dmesg 11445602_1.6.2.3.1>
11085 13:23:19.135647 Received signal: <ENDRUN> 0_dmesg 11445602_1.6.2.3.1
11086 13:23:19.136114 Ending use of test pattern.
11087 13:23:19.136569 Ending test lava.0_dmesg (11445602_1.6.2.3.1), duration 0.35
11089 13:23:19.143405 <LAVA_TEST_RUNNER EXIT>
11090 13:23:19.144031 ok: lava_test_shell seems to have completed
11091 13:23:19.144539 alert: pass
crit: pass
emerg: pass
11092 13:23:19.145012 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11093 13:23:19.145425 end: 3 lava-test-retry (duration 00:00:01) [common]
11094 13:23:19.145829 start: 4 lava-test-retry (timeout 00:01:00) [common]
11095 13:23:19.146220 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11096 13:23:19.146531 Using namespace: common
11098 13:23:19.247575 / # #
11099 13:23:19.248212 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11100 13:23:19.248837 Using /lava-11445602
11102 13:23:19.350002 export SHELL=/bin/sh
11103 13:23:19.350816 #
11105 13:23:19.452379 / # export SHELL=/bin/sh. /lava-11445602/environment
11106 13:23:19.453176
11108 13:23:19.554674 / # . /lava-11445602/environment/lava-11445602/bin/lava-test-runner /lava-11445602/1
11109 13:23:19.555289 Test shell timeout: 10s (minimum of the action and connection timeout)
11110 13:23:19.555875
11111 13:23:19.561478 / # /lava-11445602/bin/lava-test-runner /lava-11445602/1
11112 13:23:19.721174 + export TESTRUN_ID=1_bootrr
11113 13:23:19.724480 + cd /lava-11445602/1/tests/1_bootrr
11114 13:23:19.727845 + cat uuid
11115 13:23:19.745232 + UUID=11445602_1.<8>[ 28.782304] <LAVA_SIGNAL_STARTRUN 1_bootrr 11445602_1.6.2.3.5>
11116 13:23:19.745677 6.2.3.5
11117 13:23:19.746054 + set +x
11118 13:23:19.746627 Received signal: <STARTRUN> 1_bootrr 11445602_1.6.2.3.5
11119 13:23:19.746997 Starting test lava.1_bootrr (11445602_1.6.2.3.5)
11120 13:23:19.747369 Skipping test definition patterns.
11121 13:23:19.758528 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11445602/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11122 13:23:19.761775 + cd /opt/bootrr/libexec/bootrr
11123 13:23:19.762246 + sh helpers/bootrr-auto
11124 13:23:19.858681 /lava-11445602/1/../bin/lava-test-case
11125 13:23:19.898316 <8>[ 28.935671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11126 13:23:19.899267 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11128 13:23:19.962748 /lava-11445602/1/../bin/lava-test-case
11129 13:23:20.002296 <8>[ 29.039372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11130 13:23:20.003255 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11132 13:23:20.040753 /lava-11445602/1/../bin/lava-test-case
11133 13:23:20.080627 <8>[ 29.117557] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11134 13:23:20.081406 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11136 13:23:20.158476 /lava-11445602/1/../bin/lava-test-case
11137 13:23:20.199345 <8>[ 29.236678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11138 13:23:20.200181 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11140 13:23:20.250544 /lava-11445602/1/../bin/lava-test-case
11141 13:23:20.292951 <8>[ 29.330037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11142 13:23:20.293636 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11144 13:23:20.340095 /lava-11445602/1/../bin/lava-test-case
11145 13:23:20.378559 <8>[ 29.415932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11146 13:23:20.379331 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11148 13:23:20.431381 /lava-11445602/1/../bin/lava-test-case
11149 13:23:20.471925 <8>[ 29.509128] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11150 13:23:20.472766 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11152 13:23:20.519002 /lava-11445602/1/../bin/lava-test-case
11153 13:23:20.558048 <8>[ 29.595414] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11154 13:23:20.558801 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11156 13:23:20.588977 /lava-11445602/1/../bin/lava-test-case
11157 13:23:20.626534 <8>[ 29.663748] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11158 13:23:20.627318 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11160 13:23:20.676561 /lava-11445602/1/../bin/lava-test-case
11161 13:23:20.715788 <8>[ 29.753119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11162 13:23:20.716588 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11164 13:23:20.748278 /lava-11445602/1/../bin/lava-test-case
11165 13:23:20.786753 <8>[ 29.823656] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11166 13:23:20.787546 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11168 13:23:20.835665 /lava-11445602/1/../bin/lava-test-case
11169 13:23:20.874022 <8>[ 29.911273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11170 13:23:20.874787 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11172 13:23:20.923380 /lava-11445602/1/../bin/lava-test-case
11173 13:23:20.963830 <8>[ 30.001008] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11174 13:23:20.964788 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11176 13:23:21.010456 /lava-11445602/1/../bin/lava-test-case
11177 13:23:21.048568 <8>[ 30.085654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11178 13:23:21.049405 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11180 13:23:21.100317 /lava-11445602/1/../bin/lava-test-case
11181 13:23:21.141174 <8>[ 30.178361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11182 13:23:21.142017 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11184 13:23:21.172005 /lava-11445602/1/../bin/lava-test-case
11185 13:23:21.213487 <8>[ 30.250223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11186 13:23:21.214336 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11188 13:23:21.262459 /lava-11445602/1/../bin/lava-test-case
11189 13:23:21.300172 <8>[ 30.337894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11190 13:23:21.300855 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11192 13:23:21.328918 /lava-11445602/1/../bin/lava-test-case
11193 13:23:21.365383 <8>[ 30.402859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11194 13:23:21.366125 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11196 13:23:21.412798 /lava-11445602/1/../bin/lava-test-case
11197 13:23:21.452721 <8>[ 30.490231] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11198 13:23:21.453568 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11200 13:23:21.486031 /lava-11445602/1/../bin/lava-test-case
11201 13:23:21.523636 <8>[ 30.561045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11202 13:23:21.524600 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11204 13:23:21.569314 /lava-11445602/1/../bin/lava-test-case
11205 13:23:21.607450 <8>[ 30.644963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11206 13:23:21.608248 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11208 13:23:21.637905 /lava-11445602/1/../bin/lava-test-case
11209 13:23:21.676897 <8>[ 30.714129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11210 13:23:21.677740 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11212 13:23:21.723323 /lava-11445602/1/../bin/lava-test-case
11213 13:23:21.761638 <8>[ 30.798942] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11214 13:23:21.762496 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11216 13:23:21.790975 /lava-11445602/1/../bin/lava-test-case
11217 13:23:21.827180 <8>[ 30.864458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11218 13:23:21.828096 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11220 13:23:21.879427 /lava-11445602/1/../bin/lava-test-case
11221 13:23:21.917566 <8>[ 30.954961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11222 13:23:21.918380 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11224 13:23:21.964225 /lava-11445602/1/../bin/lava-test-case
11225 13:23:22.003802 <8>[ 31.041111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11226 13:23:22.004568 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11228 13:23:22.032777 /lava-11445602/1/../bin/lava-test-case
11229 13:23:22.072356 <8>[ 31.110136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11230 13:23:22.073084 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11232 13:23:22.117760 /lava-11445602/1/../bin/lava-test-case
11233 13:23:22.156295 <8>[ 31.193732] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11234 13:23:22.157020 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11236 13:23:22.184444 /lava-11445602/1/../bin/lava-test-case
11237 13:23:22.221777 <8>[ 31.259074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11238 13:23:22.222568 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11240 13:23:22.272450 /lava-11445602/1/../bin/lava-test-case
11241 13:23:22.309585 <8>[ 31.346520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11242 13:23:22.310368 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11244 13:23:22.353562 /lava-11445602/1/../bin/lava-test-case
11245 13:23:22.391244 <8>[ 31.428425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11246 13:23:22.392052 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11248 13:23:22.437085 /lava-11445602/1/../bin/lava-test-case
11249 13:23:22.473977 <8>[ 31.511237] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11250 13:23:22.474820 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11252 13:23:22.521687 /lava-11445602/1/../bin/lava-test-case
11253 13:23:22.559463 <8>[ 31.596899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11254 13:23:22.560202 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11256 13:23:22.593357 /lava-11445602/1/../bin/lava-test-case
11257 13:23:22.632156 <8>[ 31.669610] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11258 13:23:22.633137 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11260 13:23:22.681308 /lava-11445602/1/../bin/lava-test-case
11261 13:23:22.720932 <8>[ 31.758504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11262 13:23:22.721757 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11264 13:23:22.772726 /lava-11445602/1/../bin/lava-test-case
11265 13:23:22.812079 <8>[ 31.849559] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11266 13:23:22.812831 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11268 13:23:22.842695 /lava-11445602/1/../bin/lava-test-case
11269 13:23:22.882697 <8>[ 31.920216] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11270 13:23:22.883484 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11272 13:23:22.933573 /lava-11445602/1/../bin/lava-test-case
11273 13:23:22.972586 <8>[ 32.010340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11274 13:23:22.973382 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11276 13:23:23.013026 /lava-11445602/1/../bin/lava-test-case
11277 13:23:23.049232 <8>[ 32.086695] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11278 13:23:23.050023 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11280 13:23:23.093340 /lava-11445602/1/../bin/lava-test-case
11281 13:23:23.130937 <8>[ 32.168223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11282 13:23:23.131834 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11284 13:23:23.161873 /lava-11445602/1/../bin/lava-test-case
11285 13:23:23.203615 <8>[ 32.241642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11286 13:23:23.204233 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11288 13:23:23.250617 /lava-11445602/1/../bin/lava-test-case
11289 13:23:23.279492 <8>[ 32.317756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11290 13:23:23.279804 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11292 13:23:23.307019 /lava-11445602/1/../bin/lava-test-case
11293 13:23:23.337911 <8>[ 32.376106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11294 13:23:23.338275 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11296 13:23:23.379936 /lava-11445602/1/../bin/lava-test-case
11297 13:23:23.414842 <8>[ 32.452654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11298 13:23:23.415219 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11300 13:23:23.442361 /lava-11445602/1/../bin/lava-test-case
11301 13:23:23.472418 <8>[ 32.510685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11302 13:23:23.472720 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11304 13:23:23.511818 /lava-11445602/1/../bin/lava-test-case
11305 13:23:23.542576 <8>[ 32.580821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11306 13:23:23.542886 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11308 13:23:23.570749 /lava-11445602/1/../bin/lava-test-case
11309 13:23:23.602384 <8>[ 32.640306] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11310 13:23:23.602732 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11312 13:23:23.640318 /lava-11445602/1/../bin/lava-test-case
11313 13:23:23.671352 <8>[ 32.709054] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11314 13:23:23.671674 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11316 13:23:23.695310 /lava-11445602/1/../bin/lava-test-case
11317 13:23:23.728568 <8>[ 32.766097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11318 13:23:23.729398 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11320 13:23:23.775862 /lava-11445602/1/../bin/lava-test-case
11321 13:23:23.814164 <8>[ 32.851756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11322 13:23:23.815023 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11324 13:23:23.860104 /lava-11445602/1/../bin/lava-test-case
11325 13:23:23.897315 <8>[ 32.935265] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11326 13:23:23.898151 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11328 13:23:23.932967 /lava-11445602/1/../bin/lava-test-case
11329 13:23:23.974603 <8>[ 33.012089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11330 13:23:23.975433 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11332 13:23:24.023088 /lava-11445602/1/../bin/lava-test-case
11333 13:23:24.059343 <8>[ 33.097306] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11334 13:23:24.060068 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11336 13:23:24.089730 /lava-11445602/1/../bin/lava-test-case
11337 13:23:24.131640 <8>[ 33.169508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11338 13:23:24.132462 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11340 13:23:24.179617 /lava-11445602/1/../bin/lava-test-case
11341 13:23:24.220191 <8>[ 33.257730] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11342 13:23:24.220918 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11344 13:23:24.271726 /lava-11445602/1/../bin/lava-test-case
11345 13:23:24.311286 <8>[ 33.349087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11346 13:23:24.312052 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11348 13:23:24.357789 /lava-11445602/1/../bin/lava-test-case
11349 13:23:24.394769 <8>[ 33.432406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11350 13:23:24.395620 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11352 13:23:24.439223 /lava-11445602/1/../bin/lava-test-case
11353 13:23:24.479335 <8>[ 33.517044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11354 13:23:24.480036 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11356 13:23:24.523744 /lava-11445602/1/../bin/lava-test-case
11357 13:23:24.563498 <8>[ 33.601631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11358 13:23:24.564239 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11360 13:23:24.596346 /lava-11445602/1/../bin/lava-test-case
11361 13:23:24.635930 <8>[ 33.673774] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11362 13:23:24.636849 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11364 13:23:24.682771 /lava-11445602/1/../bin/lava-test-case
11365 13:23:24.719001 <8>[ 33.757152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11366 13:23:24.719397 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11368 13:23:24.760475 /lava-11445602/1/../bin/lava-test-case
11369 13:23:24.798546 <8>[ 33.836854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11370 13:23:24.799029 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11372 13:23:24.824165 /lava-11445602/1/../bin/lava-test-case
11373 13:23:24.855455 <8>[ 33.893789] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11374 13:23:24.855756 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11376 13:23:24.896456 /lava-11445602/1/../bin/lava-test-case
11377 13:23:24.928997 <8>[ 33.966917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11378 13:23:24.929304 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11380 13:23:24.959430 /lava-11445602/1/../bin/lava-test-case
11381 13:23:24.990696 <8>[ 34.029117] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11382 13:23:24.990998 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11384 13:23:25.031149 /lava-11445602/1/../bin/lava-test-case
11385 13:23:25.067251 <8>[ 34.104890] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11386 13:23:25.067548 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11388 13:23:25.091591 /lava-11445602/1/../bin/lava-test-case
11389 13:23:25.122983 <8>[ 34.161186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11390 13:23:25.123299 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11392 13:23:25.162219 /lava-11445602/1/../bin/lava-test-case
11393 13:23:25.194712 <8>[ 34.232665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11394 13:23:25.195003 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11396 13:23:25.230767 /lava-11445602/1/../bin/lava-test-case
11397 13:23:25.263380 <8>[ 34.301083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11398 13:23:25.263705 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11400 13:23:25.305581 /lava-11445602/1/../bin/lava-test-case
11401 13:23:25.337105 <8>[ 34.375223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11402 13:23:25.337411 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11404 13:23:25.376164 /lava-11445602/1/../bin/lava-test-case
11405 13:23:25.408446 <8>[ 34.446750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11406 13:23:25.408724 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11408 13:23:25.446642 /lava-11445602/1/../bin/lava-test-case
11409 13:23:25.477477 <8>[ 34.515930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11410 13:23:25.477758 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11412 13:23:25.516255 /lava-11445602/1/../bin/lava-test-case
11413 13:23:25.549704 <8>[ 34.588052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11414 13:23:25.550005 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11416 13:23:25.591852 /lava-11445602/1/../bin/lava-test-case
11417 13:23:25.624811 <8>[ 34.662954] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11418 13:23:25.625093 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11420 13:23:25.667831 /lava-11445602/1/../bin/lava-test-case
11421 13:23:25.701695 <8>[ 34.740111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11422 13:23:25.701986 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11424 13:23:25.743811 /lava-11445602/1/../bin/lava-test-case
11425 13:23:25.778619 <8>[ 34.816759] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11426 13:23:25.778915 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11428 13:23:25.817506 /lava-11445602/1/../bin/lava-test-case
11429 13:23:25.848236 <8>[ 34.886972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11430 13:23:25.848548 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11432 13:23:25.885546 /lava-11445602/1/../bin/lava-test-case
11433 13:23:25.918532 <8>[ 34.956937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11434 13:23:25.918854 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11436 13:23:25.954883 /lava-11445602/1/../bin/lava-test-case
11437 13:23:25.986541 <8>[ 35.025139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11438 13:23:25.986880 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11440 13:23:26.028205 /lava-11445602/1/../bin/lava-test-case
11441 13:23:26.060419 <8>[ 35.098885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11442 13:23:26.060699 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11444 13:23:26.098995 /lava-11445602/1/../bin/lava-test-case
11445 13:23:26.132858 <8>[ 35.171087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11446 13:23:26.133142 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11448 13:23:26.172731 /lava-11445602/1/../bin/lava-test-case
11449 13:23:26.203468 <8>[ 35.241881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11450 13:23:26.203754 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11452 13:23:26.228082 /lava-11445602/1/../bin/lava-test-case
11453 13:23:26.260788 <8>[ 35.298716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11454 13:23:26.261061 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11456 13:23:26.306995 /lava-11445602/1/../bin/lava-test-case
11457 13:23:26.337560 <8>[ 35.375971] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11458 13:23:26.337877 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11460 13:23:26.360963 /lava-11445602/1/../bin/lava-test-case
11461 13:23:26.394871 <8>[ 35.433262] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11462 13:23:26.395183 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11464 13:23:26.434058 /lava-11445602/1/../bin/lava-test-case
11465 13:23:26.469198 <8>[ 35.507363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11466 13:23:26.469518 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11468 13:23:26.492650 /lava-11445602/1/../bin/lava-test-case
11469 13:23:26.522624 <8>[ 35.561144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11470 13:23:26.522936 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11472 13:23:26.562906 /lava-11445602/1/../bin/lava-test-case
11473 13:23:26.593926 <8>[ 35.632224] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11474 13:23:26.594239 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11476 13:23:26.624396 /lava-11445602/1/../bin/lava-test-case
11477 13:23:26.654261 <8>[ 35.692424] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11478 13:23:26.654580 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11480 13:23:26.691433 /lava-11445602/1/../bin/lava-test-case
11481 13:23:26.719899 <8>[ 35.758327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11482 13:23:26.720267 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11484 13:23:26.743587 /lava-11445602/1/../bin/lava-test-case
11485 13:23:26.772083 <8>[ 35.810407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11486 13:23:26.772399 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11488 13:23:26.810240 /lava-11445602/1/../bin/lava-test-case
11489 13:23:26.840676 <8>[ 35.879042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11490 13:23:26.841004 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11492 13:23:26.866924 /lava-11445602/1/../bin/lava-test-case
11493 13:23:26.899806 <8>[ 35.938051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11494 13:23:26.900114 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11496 13:23:26.938383 /lava-11445602/1/../bin/lava-test-case
11497 13:23:26.969828 <8>[ 36.008138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11498 13:23:26.970130 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11500 13:23:27.013879 /lava-11445602/1/../bin/lava-test-case
11501 13:23:27.048648 <8>[ 36.087359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11502 13:23:27.048976 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11504 13:23:27.075332 /lava-11445602/1/../bin/lava-test-case
11505 13:23:27.107485 <8>[ 36.145924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11506 13:23:27.107801 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11508 13:23:27.145213 /lava-11445602/1/../bin/lava-test-case
11509 13:23:27.173740 <8>[ 36.212130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11510 13:23:27.174022 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11512 13:23:27.196839 /lava-11445602/1/../bin/lava-test-case
11513 13:23:27.227290 <8>[ 36.265691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11514 13:23:27.227592 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11516 13:23:27.264067 /lava-11445602/1/../bin/lava-test-case
11517 13:23:27.292886 <8>[ 36.331575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11518 13:23:27.293179 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11520 13:23:27.317502 /lava-11445602/1/../bin/lava-test-case
11521 13:23:27.346785 <8>[ 36.385312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11522 13:23:27.347078 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11524 13:23:28.412724 /lava-11445602/1/../bin/lava-test-case
11525 13:23:28.444596 <8>[ 37.483464] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11526 13:23:28.444946 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11528 13:23:28.468216 /lava-11445602/1/../bin/lava-test-case
11529 13:23:28.501445 <8>[ 37.540171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11530 13:23:28.501757 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11532 13:23:29.554002 /lava-11445602/1/../bin/lava-test-case
11533 13:23:29.588472 <8>[ 38.626782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11534 13:23:29.588770 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11536 13:23:29.611651 /lava-11445602/1/../bin/lava-test-case
11537 13:23:29.643159 <8>[ 38.681623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11538 13:23:29.643475 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11540 13:23:30.692967 /lava-11445602/1/../bin/lava-test-case
11541 13:23:30.728899 <8>[ 39.768075] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11542 13:23:30.729216 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11544 13:23:30.753799 /lava-11445602/1/../bin/lava-test-case
11545 13:23:30.784559 <8>[ 39.823623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11546 13:23:30.784933 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11548 13:23:31.833909 /lava-11445602/1/../bin/lava-test-case
11549 13:23:31.868431 <8>[ 40.907545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11550 13:23:31.868800 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11552 13:23:31.890852 /lava-11445602/1/../bin/lava-test-case
11553 13:23:31.920957 <8>[ 40.960275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11554 13:23:31.921330 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11556 13:23:32.972509 /lava-11445602/1/../bin/lava-test-case
11557 13:23:33.005953 <8>[ 42.045249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11558 13:23:33.006317 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11560 13:23:33.030268 /lava-11445602/1/../bin/lava-test-case
11561 13:23:33.061790 <8>[ 42.101320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11562 13:23:33.062177 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11564 13:23:34.117830 /lava-11445602/1/../bin/lava-test-case
11565 13:23:34.152436 <8>[ 43.191663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11566 13:23:34.152817 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11568 13:23:34.177286 /lava-11445602/1/../bin/lava-test-case
11569 13:23:34.210718 <8>[ 43.250177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11570 13:23:34.211098 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11572 13:23:35.265026 /lava-11445602/1/../bin/lava-test-case
11573 13:23:35.296955 <8>[ 44.336294] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11574 13:23:35.297334 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11576 13:23:35.318918 /lava-11445602/1/../bin/lava-test-case
11577 13:23:35.351062 <8>[ 44.390708] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11578 13:23:35.351434 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11580 13:23:35.376604 /lava-11445602/1/../bin/lava-test-case
11581 13:23:35.411138 <8>[ 44.450824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11582 13:23:35.411508 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11584 13:23:36.464232 /lava-11445602/1/../bin/lava-test-case
11585 13:23:36.500002 <8>[ 45.539651] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11586 13:23:36.500408 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11588 13:23:36.524148 /lava-11445602/1/../bin/lava-test-case
11589 13:23:36.553831 <8>[ 45.593219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11590 13:23:36.554188 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11592 13:23:36.594608 /lava-11445602/1/../bin/lava-test-case
11593 13:23:36.624471 <8>[ 45.664082] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11594 13:23:36.624841 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11596 13:23:36.650366 /lava-11445602/1/../bin/lava-test-case
11597 13:23:36.683617 <8>[ 45.723350] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11598 13:23:36.683981 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11600 13:23:36.723911 /lava-11445602/1/../bin/lava-test-case
11601 13:23:36.758028 <8>[ 45.797888] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11602 13:23:36.758379 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11604 13:23:36.802637 /lava-11445602/1/../bin/lava-test-case
11605 13:23:36.835328 <8>[ 45.875022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11606 13:23:36.835705 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11608 13:23:36.872245 /lava-11445602/1/../bin/lava-test-case
11609 13:23:36.902955 <8>[ 45.942893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11610 13:23:36.903347 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11612 13:23:36.931500 /lava-11445602/1/../bin/lava-test-case
11613 13:23:36.963184 <8>[ 46.002228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11614 13:23:36.963564 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11616 13:23:37.003809 /lava-11445602/1/../bin/lava-test-case
11617 13:23:37.036497 <8>[ 46.075949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11618 13:23:37.036885 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11620 13:23:37.075471 /lava-11445602/1/../bin/lava-test-case
11621 13:23:37.108990 <8>[ 46.148745] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11622 13:23:37.109365 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11624 13:23:37.122746 <6>[ 46.169020] vpu: disabling
11625 13:23:37.125782 <6>[ 46.172336] vproc2: disabling
11626 13:23:37.129824 <6>[ 46.175765] vproc1: disabling
11627 13:23:37.132823 <6>[ 46.179190] vaud18: disabling
11628 13:23:37.139645 <6>[ 46.182753] vsram_others: disabling
11629 13:23:37.143110 <6>[ 46.186746] va09: disabling
11630 13:23:37.146498 <6>[ 46.189968] vsram_md: disabling
11631 13:23:37.149515 <6>[ 46.193591] Vgpu: disabling
11632 13:23:37.162719 /lava-11445602/1/../bin/lava-test-case
11633 13:23:37.196971 <8>[ 46.236814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11634 13:23:37.197320 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11636 13:23:37.234695 /lava-11445602/1/../bin/lava-test-case
11637 13:23:37.268518 <8>[ 46.308522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11638 13:23:37.268920 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11640 13:23:37.293654 /lava-11445602/1/../bin/lava-test-case
11641 13:23:37.323060 <8>[ 46.362814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11642 13:23:37.323433 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11644 13:23:37.361434 /lava-11445602/1/../bin/lava-test-case
11645 13:23:37.396313 <8>[ 46.435821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11646 13:23:37.396673 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11648 13:23:37.434961 /lava-11445602/1/../bin/lava-test-case
11649 13:23:37.465576 <8>[ 46.505184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11650 13:23:37.465941 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11652 13:23:37.505601 /lava-11445602/1/../bin/lava-test-case
11653 13:23:37.536313 <8>[ 46.575713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11654 13:23:37.536722 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11656 13:23:37.560093 /lava-11445602/1/../bin/lava-test-case
11657 13:23:37.591638 <8>[ 46.631194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11658 13:23:37.592008 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11660 13:23:37.631935 /lava-11445602/1/../bin/lava-test-case
11661 13:23:37.665593 <8>[ 46.705255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11662 13:23:37.665913 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11664 13:23:37.690869 /lava-11445602/1/../bin/lava-test-case
11665 13:23:37.724845 <8>[ 46.764739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11666 13:23:37.725165 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11668 13:23:37.771439 /lava-11445602/1/../bin/lava-test-case
11669 13:23:37.802847 <8>[ 46.842803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11670 13:23:37.803224 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11672 13:23:37.826844 /lava-11445602/1/../bin/lava-test-case
11673 13:23:37.857846 <8>[ 46.897719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11674 13:23:37.858211 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11676 13:23:38.908139 /lava-11445602/1/../bin/lava-test-case
11677 13:23:38.940719 <8>[ 47.980623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11678 13:23:38.941035 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11680 13:23:39.986614 /lava-11445602/1/../bin/lava-test-case
11681 13:23:40.021595 <8>[ 49.061707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11682 13:23:40.021920 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11684 13:23:40.045247 /lava-11445602/1/../bin/lava-test-case
11685 13:23:40.076966 <8>[ 49.117116] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11686 13:23:40.077363 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11688 13:23:40.117264 /lava-11445602/1/../bin/lava-test-case
11689 13:23:40.149730 <8>[ 49.189707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11690 13:23:40.150162 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11692 13:23:40.173792 /lava-11445602/1/../bin/lava-test-case
11693 13:23:40.204374 <8>[ 49.244754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11694 13:23:40.204768 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11696 13:23:40.241831 /lava-11445602/1/../bin/lava-test-case
11697 13:23:40.271684 <8>[ 49.311778] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11698 13:23:40.271991 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11700 13:23:40.295578 /lava-11445602/1/../bin/lava-test-case
11701 13:23:40.328546 <8>[ 49.368535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11702 13:23:40.328906 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11704 13:23:40.372610 /lava-11445602/1/../bin/lava-test-case
11705 13:23:40.405713 <8>[ 49.446065] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11706 13:23:40.406021 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11708 13:23:40.429583 /lava-11445602/1/../bin/lava-test-case
11709 13:23:40.459742 <8>[ 49.499962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11710 13:23:40.460048 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11712 13:23:40.495431 /lava-11445602/1/../bin/lava-test-case
11713 13:23:40.523757 <8>[ 49.563991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11714 13:23:40.524046 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11716 13:23:40.546233 /lava-11445602/1/../bin/lava-test-case
11717 13:23:40.573000 <8>[ 49.613050] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11718 13:23:40.573308 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11720 13:23:40.606332 /lava-11445602/1/../bin/lava-test-case
11721 13:23:40.632588 <8>[ 49.672814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11722 13:23:40.632899 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11724 13:23:40.654976 /lava-11445602/1/../bin/lava-test-case
11725 13:23:40.683118 <8>[ 49.723590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11726 13:23:40.683429 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11728 13:23:40.726997 /lava-11445602/1/../bin/lava-test-case
11729 13:23:40.753411 <8>[ 49.793674] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11730 13:23:40.753704 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11732 13:23:40.776038 /lava-11445602/1/../bin/lava-test-case
11733 13:23:40.804115 <8>[ 49.844425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11734 13:23:40.804438 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11736 13:23:40.840848 /lava-11445602/1/../bin/lava-test-case
11737 13:23:40.871394 <8>[ 49.911521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11738 13:23:40.871712 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11740 13:23:40.893555 /lava-11445602/1/../bin/lava-test-case
11741 13:23:40.921063 <8>[ 49.961575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11742 13:23:40.921414 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11744 13:23:40.956840 /lava-11445602/1/../bin/lava-test-case
11745 13:23:40.983449 <8>[ 50.023654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11746 13:23:40.983725 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11748 13:23:41.005569 /lava-11445602/1/../bin/lava-test-case
11749 13:23:41.036082 <8>[ 50.075999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11750 13:23:41.036485 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11752 13:23:41.080896 /lava-11445602/1/../bin/lava-test-case
11753 13:23:41.112800 <8>[ 50.152868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11754 13:23:41.113335 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11756 13:23:41.137074 /lava-11445602/1/../bin/lava-test-case
11757 13:23:41.171349 <8>[ 50.211597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11758 13:23:41.171732 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11760 13:23:41.207092 /lava-11445602/1/../bin/lava-test-case
11761 13:23:41.235507 <8>[ 50.275431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11762 13:23:41.236122 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11764 13:23:42.274898 /lava-11445602/1/../bin/lava-test-case
11765 13:23:42.317060 <8>[ 51.357090] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11766 13:23:42.317761 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11768 13:23:43.363180 /lava-11445602/1/../bin/lava-test-case
11769 13:23:43.397732 <8>[ 52.438201] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11770 13:23:43.398049 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11771 13:23:43.398142 Bad test result: blocked
11772 13:23:43.421607 /lava-11445602/1/../bin/lava-test-case
11773 13:23:43.452772 <8>[ 52.493107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11774 13:23:43.453096 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11776 13:23:44.507039 /lava-11445602/1/../bin/lava-test-case
11777 13:23:44.540902 <8>[ 53.581174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11778 13:23:44.541220 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11780 13:23:44.562944 /lava-11445602/1/../bin/lava-test-case
11781 13:23:44.591579 <8>[ 53.632219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11782 13:23:44.591922 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11784 13:23:44.630383 /lava-11445602/1/../bin/lava-test-case
11785 13:23:44.662286 <8>[ 53.703167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11786 13:23:44.662634 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11788 13:23:44.698251 /lava-11445602/1/../bin/lava-test-case
11789 13:23:44.729849 <8>[ 53.770644] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11790 13:23:44.730224 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11792 13:23:44.755223 /lava-11445602/1/../bin/lava-test-case
11793 13:23:44.788193 <8>[ 53.828405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11794 13:23:44.788503 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11796 13:23:44.831154 /lava-11445602/1/../bin/lava-test-case
11797 13:23:44.863544 <8>[ 53.904473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11798 13:23:44.863865 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11800 13:23:44.888713 /lava-11445602/1/../bin/lava-test-case
11801 13:23:44.919724 <8>[ 53.960408] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11802 13:23:44.920036 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11804 13:23:45.975140 /lava-11445602/1/../bin/lava-test-case
11805 13:23:46.008477 <8>[ 55.049055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11806 13:23:46.008807 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11808 13:23:46.029847 /lava-11445602/1/../bin/lava-test-case
11809 13:23:46.060093 <8>[ 55.100853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11810 13:23:46.060419 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11812 13:23:47.113603 /lava-11445602/1/../bin/lava-test-case
11813 13:23:47.146679 <8>[ 56.187463] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11814 13:23:47.147007 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11816 13:23:47.170756 /lava-11445602/1/../bin/lava-test-case
11817 13:23:47.201818 <8>[ 56.242635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11818 13:23:47.202110 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11820 13:23:48.251486 /lava-11445602/1/../bin/lava-test-case
11821 13:23:48.290763 <8>[ 57.332131] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11822 13:23:48.291087 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11824 13:23:48.315036 /lava-11445602/1/../bin/lava-test-case
11825 13:23:48.348188 <8>[ 57.389078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11826 13:23:48.348471 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11828 13:23:49.396149 /lava-11445602/1/../bin/lava-test-case
11829 13:23:49.427698 <8>[ 58.468883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11830 13:23:49.427985 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11832 13:23:49.452991 /lava-11445602/1/../bin/lava-test-case
11833 13:23:49.486364 <8>[ 58.527697] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11834 13:23:49.486688 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11836 13:23:49.526083 /lava-11445602/1/../bin/lava-test-case
11837 13:23:49.555807 <8>[ 58.597052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11838 13:23:49.556125 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11840 13:23:49.595275 /lava-11445602/1/../bin/lava-test-case
11841 13:23:49.627011 <8>[ 58.668401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11842 13:23:49.627326 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11844 13:23:49.651260 /lava-11445602/1/../bin/lava-test-case
11845 13:23:49.681427 <8>[ 58.722844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11846 13:23:49.681700 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11848 13:23:49.726298 /lava-11445602/1/../bin/lava-test-case
11849 13:23:49.757400 <8>[ 58.798475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11850 13:23:49.757687 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11852 13:23:49.785120 /lava-11445602/1/../bin/lava-test-case
11853 13:23:49.816954 <8>[ 58.858273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11854 13:23:49.817259 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11856 13:23:49.854687 /lava-11445602/1/../bin/lava-test-case
11857 13:23:49.885844 <8>[ 58.927141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11858 13:23:49.886136 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11860 13:23:49.911617 /lava-11445602/1/../bin/lava-test-case
11861 13:23:49.943547 <8>[ 58.984756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11862 13:23:49.943896 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11864 13:23:49.988493 /lava-11445602/1/../bin/lava-test-case
11865 13:23:50.023348 <8>[ 59.064877] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11866 13:23:50.023672 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11868 13:23:50.029586 + set +x
11869 13:23:50.032781 Received signal: <ENDRUN> 1_bootrr 11445602_1.6.2.3.5
11870 13:23:50.032915 Ending use of test pattern.
11871 13:23:50.032997 Ending test lava.1_bootrr (11445602_1.6.2.3.5), duration 30.29
11873 13:23:50.036030 <8>[ 59.077245] <LAVA_SIGNAL_ENDRUN 1_bootrr 11445602_1.6.2.3.5>
11874 13:23:50.041303 <LAVA_TEST_RUNNER EXIT>
11875 13:23:50.041562 ok: lava_test_shell seems to have completed
11876 13:23:50.042553 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11877 13:23:50.042711 end: 4.1 lava-test-shell (duration 00:00:31) [common]
11878 13:23:50.042813 end: 4 lava-test-retry (duration 00:00:31) [common]
11879 13:23:50.042921 start: 5 finalize (timeout 00:07:10) [common]
11880 13:23:50.043026 start: 5.1 power-off (timeout 00:00:30) [common]
11881 13:23:50.043192 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11882 13:23:50.120585 >> Command sent successfully.
11883 13:23:50.122949 Returned 0 in 0 seconds
11884 13:23:50.223330 end: 5.1 power-off (duration 00:00:00) [common]
11886 13:23:50.223698 start: 5.2 read-feedback (timeout 00:07:10) [common]
11887 13:23:50.223975 Listened to connection for namespace 'common' for up to 1s
11888 13:23:51.224782 Finalising connection for namespace 'common'
11889 13:23:51.224956 Disconnecting from shell: Finalise
11890 13:23:51.225064 / #
11891 13:23:51.325412 end: 5.2 read-feedback (duration 00:00:01) [common]
11892 13:23:51.325580 end: 5 finalize (duration 00:00:01) [common]
11893 13:23:51.325720 Cleaning after the job
11894 13:23:51.325833 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11445602/tftp-deploy-75s0rxey/ramdisk
11895 13:23:51.328289 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11445602/tftp-deploy-75s0rxey/kernel
11896 13:23:51.340694 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11445602/tftp-deploy-75s0rxey/dtb
11897 13:23:51.340896 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11445602/tftp-deploy-75s0rxey/nfsrootfs
11898 13:23:51.413999 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11445602/tftp-deploy-75s0rxey/modules
11899 13:23:51.421349 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11445602
11900 13:23:51.798999 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11445602
11901 13:23:51.799169 Job finished correctly