Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 34
- Boot result: PASS
- Warnings: 1
- Errors: 0
- Kernel Warnings: 21
1 13:20:34.544197 lava-dispatcher, installed at version: 2023.06
2 13:20:34.544410 start: 0 validate
3 13:20:34.544548 Start time: 2023-09-06 13:20:34.544540+00:00 (UTC)
4 13:20:34.544681 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:20:34.544861 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:20:34.811833 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:20:34.812026 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4-14-g09ffd7fb38ff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:21:01.585369 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:21:01.585545 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4-14-g09ffd7fb38ff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:21:01.852886 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:21:01.853049 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4-14-g09ffd7fb38ff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:21:05.116314 validate duration: 30.57
14 13:21:05.116592 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:21:05.116691 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:21:05.116813 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:21:05.116952 Not decompressing ramdisk as can be used compressed.
18 13:21:05.117042 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 13:21:05.117112 saving as /var/lib/lava/dispatcher/tmp/11445609/tftp-deploy-4jxawmcg/ramdisk/rootfs.cpio.gz
20 13:21:05.117179 total size: 34390042 (32 MB)
21 13:21:05.393979 progress 0 % (0 MB)
22 13:21:05.402785 progress 5 % (1 MB)
23 13:21:05.411768 progress 10 % (3 MB)
24 13:21:05.420843 progress 15 % (4 MB)
25 13:21:05.429882 progress 20 % (6 MB)
26 13:21:05.439074 progress 25 % (8 MB)
27 13:21:05.447936 progress 30 % (9 MB)
28 13:21:05.457167 progress 35 % (11 MB)
29 13:21:05.465956 progress 40 % (13 MB)
30 13:21:05.474842 progress 45 % (14 MB)
31 13:21:05.483519 progress 50 % (16 MB)
32 13:21:05.492369 progress 55 % (18 MB)
33 13:21:05.501102 progress 60 % (19 MB)
34 13:21:05.509974 progress 65 % (21 MB)
35 13:21:05.518676 progress 70 % (22 MB)
36 13:21:05.527566 progress 75 % (24 MB)
37 13:21:05.536317 progress 80 % (26 MB)
38 13:21:05.545456 progress 85 % (27 MB)
39 13:21:05.554380 progress 90 % (29 MB)
40 13:21:05.563261 progress 95 % (31 MB)
41 13:21:05.572221 progress 100 % (32 MB)
42 13:21:05.572424 32 MB downloaded in 0.46 s (72.04 MB/s)
43 13:21:05.572596 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:21:05.572879 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:21:05.572969 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:21:05.573054 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:21:05.573192 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4-14-g09ffd7fb38ff/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:21:05.573266 saving as /var/lib/lava/dispatcher/tmp/11445609/tftp-deploy-4jxawmcg/kernel/Image
50 13:21:05.573330 total size: 49220096 (46 MB)
51 13:21:05.573394 No compression specified
52 13:21:05.574664 progress 0 % (0 MB)
53 13:21:05.587134 progress 5 % (2 MB)
54 13:21:05.599514 progress 10 % (4 MB)
55 13:21:05.612036 progress 15 % (7 MB)
56 13:21:05.624532 progress 20 % (9 MB)
57 13:21:05.637782 progress 25 % (11 MB)
58 13:21:05.650437 progress 30 % (14 MB)
59 13:21:05.663164 progress 35 % (16 MB)
60 13:21:05.676012 progress 40 % (18 MB)
61 13:21:05.688497 progress 45 % (21 MB)
62 13:21:05.701111 progress 50 % (23 MB)
63 13:21:05.713990 progress 55 % (25 MB)
64 13:21:05.727067 progress 60 % (28 MB)
65 13:21:05.739895 progress 65 % (30 MB)
66 13:21:05.752418 progress 70 % (32 MB)
67 13:21:05.765163 progress 75 % (35 MB)
68 13:21:05.777736 progress 80 % (37 MB)
69 13:21:05.790211 progress 85 % (39 MB)
70 13:21:05.802623 progress 90 % (42 MB)
71 13:21:05.814991 progress 95 % (44 MB)
72 13:21:05.827447 progress 100 % (46 MB)
73 13:21:05.827593 46 MB downloaded in 0.25 s (184.61 MB/s)
74 13:21:05.827753 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:21:05.827988 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:21:05.828075 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:21:05.828169 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:21:05.828308 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4-14-g09ffd7fb38ff/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:21:05.828378 saving as /var/lib/lava/dispatcher/tmp/11445609/tftp-deploy-4jxawmcg/dtb/mt8192-asurada-spherion-r0.dtb
81 13:21:05.828441 total size: 47278 (0 MB)
82 13:21:05.828505 No compression specified
83 13:21:05.829714 progress 69 % (0 MB)
84 13:21:05.829992 progress 100 % (0 MB)
85 13:21:05.830150 0 MB downloaded in 0.00 s (26.43 MB/s)
86 13:21:05.830276 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:21:05.830505 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:21:05.830594 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:21:05.830679 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:21:05.830790 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4-14-g09ffd7fb38ff/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:21:05.830860 saving as /var/lib/lava/dispatcher/tmp/11445609/tftp-deploy-4jxawmcg/modules/modules.tar
93 13:21:05.830923 total size: 8610736 (8 MB)
94 13:21:05.830988 Using unxz to decompress xz
95 13:21:05.834661 progress 0 % (0 MB)
96 13:21:05.856185 progress 5 % (0 MB)
97 13:21:05.880390 progress 10 % (0 MB)
98 13:21:05.909759 progress 15 % (1 MB)
99 13:21:05.937969 progress 20 % (1 MB)
100 13:21:05.962118 progress 25 % (2 MB)
101 13:21:05.987045 progress 30 % (2 MB)
102 13:21:06.012014 progress 35 % (2 MB)
103 13:21:06.038741 progress 40 % (3 MB)
104 13:21:06.064606 progress 45 % (3 MB)
105 13:21:06.091628 progress 50 % (4 MB)
106 13:21:06.117537 progress 55 % (4 MB)
107 13:21:06.143100 progress 60 % (4 MB)
108 13:21:06.167909 progress 65 % (5 MB)
109 13:21:06.191523 progress 70 % (5 MB)
110 13:21:06.219178 progress 75 % (6 MB)
111 13:21:06.243369 progress 80 % (6 MB)
112 13:21:06.269403 progress 85 % (7 MB)
113 13:21:06.293974 progress 90 % (7 MB)
114 13:21:06.318817 progress 95 % (7 MB)
115 13:21:06.345349 progress 100 % (8 MB)
116 13:21:06.351245 8 MB downloaded in 0.52 s (15.78 MB/s)
117 13:21:06.351510 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:21:06.351802 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:21:06.351912 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:21:06.352027 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:21:06.352123 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:21:06.352233 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:21:06.352477 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz
125 13:21:06.352650 makedir: /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin
126 13:21:06.352831 makedir: /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/tests
127 13:21:06.352970 makedir: /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/results
128 13:21:06.353099 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-add-keys
129 13:21:06.353263 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-add-sources
130 13:21:06.353410 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-background-process-start
131 13:21:06.353555 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-background-process-stop
132 13:21:06.353700 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-common-functions
133 13:21:06.353869 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-echo-ipv4
134 13:21:06.354040 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-install-packages
135 13:21:06.354208 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-installed-packages
136 13:21:06.354377 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-os-build
137 13:21:06.354542 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-probe-channel
138 13:21:06.354683 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-probe-ip
139 13:21:06.354824 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-target-ip
140 13:21:06.354964 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-target-mac
141 13:21:06.355104 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-target-storage
142 13:21:06.355247 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-test-case
143 13:21:06.355392 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-test-event
144 13:21:06.355559 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-test-feedback
145 13:21:06.355728 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-test-raise
146 13:21:06.355896 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-test-reference
147 13:21:06.356061 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-test-runner
148 13:21:06.356201 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-test-set
149 13:21:06.356342 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-test-shell
150 13:21:06.356486 Updating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-install-packages (oe)
151 13:21:06.356660 Updating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/bin/lava-installed-packages (oe)
152 13:21:06.356875 Creating /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/environment
153 13:21:06.357024 LAVA metadata
154 13:21:06.357133 - LAVA_JOB_ID=11445609
155 13:21:06.357237 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:21:06.357362 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:21:06.357441 skipped lava-vland-overlay
158 13:21:06.357541 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:21:06.357666 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:21:06.357766 skipped lava-multinode-overlay
161 13:21:06.357865 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:21:06.357969 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:21:06.358090 Loading test definitions
164 13:21:06.358228 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:21:06.358314 Using /lava-11445609 at stage 0
166 13:21:06.358704 uuid=11445609_1.5.2.3.1 testdef=None
167 13:21:06.358828 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:21:06.358938 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:21:06.359665 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:21:06.360039 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:21:06.360911 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:21:06.361180 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:21:06.361805 runner path: /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/0/tests/0_cros-ec test_uuid 11445609_1.5.2.3.1
176 13:21:06.361971 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:21:06.362306 Creating lava-test-runner.conf files
179 13:21:06.362409 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11445609/lava-overlay-_k5rgydz/lava-11445609/0 for stage 0
180 13:21:06.362544 - 0_cros-ec
181 13:21:06.362681 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:21:06.362808 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:21:06.369952 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:21:06.370073 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:21:06.370176 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:21:06.370280 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:21:06.370385 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:21:07.311586 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 13:21:07.311971 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 13:21:07.312132 extracting modules file /var/lib/lava/dispatcher/tmp/11445609/tftp-deploy-4jxawmcg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11445609/extract-overlay-ramdisk-vtq4ojfd/ramdisk
191 13:21:07.529028 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:21:07.529233 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 13:21:07.529370 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11445609/compress-overlay-fgwu84h4/overlay-1.5.2.4.tar.gz to ramdisk
194 13:21:07.529473 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11445609/compress-overlay-fgwu84h4/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11445609/extract-overlay-ramdisk-vtq4ojfd/ramdisk
195 13:21:07.536088 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:21:07.536204 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 13:21:07.536296 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:21:07.536388 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 13:21:07.536466 Building ramdisk /var/lib/lava/dispatcher/tmp/11445609/extract-overlay-ramdisk-vtq4ojfd/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11445609/extract-overlay-ramdisk-vtq4ojfd/ramdisk
200 13:21:08.266277 >> 270924 blocks
201 13:21:13.001140 rename /var/lib/lava/dispatcher/tmp/11445609/extract-overlay-ramdisk-vtq4ojfd/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11445609/tftp-deploy-4jxawmcg/ramdisk/ramdisk.cpio.gz
202 13:21:13.001697 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 13:21:13.001897 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 13:21:13.002069 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 13:21:13.002237 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11445609/tftp-deploy-4jxawmcg/kernel/Image'
206 13:21:25.759105 Returned 0 in 12 seconds
207 13:21:25.859728 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11445609/tftp-deploy-4jxawmcg/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11445609/tftp-deploy-4jxawmcg/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11445609/tftp-deploy-4jxawmcg/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11445609/tftp-deploy-4jxawmcg/kernel/image.itb
208 13:21:26.528509 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:21:26.528896 output: Created: Wed Sep 6 14:21:26 2023
210 13:21:26.528979 output: Image 0 (kernel-1)
211 13:21:26.529048 output: Description:
212 13:21:26.529114 output: Created: Wed Sep 6 14:21:26 2023
213 13:21:26.529179 output: Type: Kernel Image
214 13:21:26.529241 output: Compression: lzma compressed
215 13:21:26.529302 output: Data Size: 11038222 Bytes = 10779.51 KiB = 10.53 MiB
216 13:21:26.529361 output: Architecture: AArch64
217 13:21:26.529422 output: OS: Linux
218 13:21:26.529481 output: Load Address: 0x00000000
219 13:21:26.529537 output: Entry Point: 0x00000000
220 13:21:26.529592 output: Hash algo: crc32
221 13:21:26.529648 output: Hash value: eae831c7
222 13:21:26.529703 output: Image 1 (fdt-1)
223 13:21:26.529758 output: Description: mt8192-asurada-spherion-r0
224 13:21:26.529813 output: Created: Wed Sep 6 14:21:26 2023
225 13:21:26.529869 output: Type: Flat Device Tree
226 13:21:26.529924 output: Compression: uncompressed
227 13:21:26.529978 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 13:21:26.530033 output: Architecture: AArch64
229 13:21:26.530087 output: Hash algo: crc32
230 13:21:26.530142 output: Hash value: cc4352de
231 13:21:26.530196 output: Image 2 (ramdisk-1)
232 13:21:26.530252 output: Description: unavailable
233 13:21:26.530306 output: Created: Wed Sep 6 14:21:26 2023
234 13:21:26.530377 output: Type: RAMDisk Image
235 13:21:26.530446 output: Compression: Unknown Compression
236 13:21:26.530501 output: Data Size: 47516413 Bytes = 46402.75 KiB = 45.32 MiB
237 13:21:26.530555 output: Architecture: AArch64
238 13:21:26.530609 output: OS: Linux
239 13:21:26.530664 output: Load Address: unavailable
240 13:21:26.530719 output: Entry Point: unavailable
241 13:21:26.530774 output: Hash algo: crc32
242 13:21:26.530828 output: Hash value: fd6ccb74
243 13:21:26.530882 output: Default Configuration: 'conf-1'
244 13:21:26.530936 output: Configuration 0 (conf-1)
245 13:21:26.530991 output: Description: mt8192-asurada-spherion-r0
246 13:21:26.531045 output: Kernel: kernel-1
247 13:21:26.531100 output: Init Ramdisk: ramdisk-1
248 13:21:26.531154 output: FDT: fdt-1
249 13:21:26.531209 output: Loadables: kernel-1
250 13:21:26.531262 output:
251 13:21:26.531461 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 13:21:26.531559 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 13:21:26.531661 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 13:21:26.531756 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 13:21:26.531832 No LXC device requested
256 13:21:26.531911 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:21:26.531995 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 13:21:26.532071 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:21:26.532142 Checking files for TFTP limit of 4294967296 bytes.
260 13:21:26.532708 end: 1 tftp-deploy (duration 00:00:21) [common]
261 13:21:26.532829 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:21:26.532926 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:21:26.533064 substitutions:
264 13:21:26.533148 - {DTB}: 11445609/tftp-deploy-4jxawmcg/dtb/mt8192-asurada-spherion-r0.dtb
265 13:21:26.533215 - {INITRD}: 11445609/tftp-deploy-4jxawmcg/ramdisk/ramdisk.cpio.gz
266 13:21:26.533278 - {KERNEL}: 11445609/tftp-deploy-4jxawmcg/kernel/Image
267 13:21:26.533339 - {LAVA_MAC}: None
268 13:21:26.533400 - {PRESEED_CONFIG}: None
269 13:21:26.533458 - {PRESEED_LOCAL}: None
270 13:21:26.533517 - {RAMDISK}: 11445609/tftp-deploy-4jxawmcg/ramdisk/ramdisk.cpio.gz
271 13:21:26.533576 - {ROOT_PART}: None
272 13:21:26.533636 - {ROOT}: None
273 13:21:26.533709 - {SERVER_IP}: 192.168.201.1
274 13:21:26.533769 - {TEE}: None
275 13:21:26.533827 Parsed boot commands:
276 13:21:26.533885 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:21:26.534067 Parsed boot commands: tftpboot 192.168.201.1 11445609/tftp-deploy-4jxawmcg/kernel/image.itb 11445609/tftp-deploy-4jxawmcg/kernel/cmdline
278 13:21:26.534160 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:21:26.534248 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:21:26.534348 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:21:26.534440 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:21:26.534516 Not connected, no need to disconnect.
283 13:21:26.534592 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:21:26.534674 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:21:26.534746 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 13:21:26.538218 Setting prompt string to ['lava-test: # ']
287 13:21:26.538669 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:21:26.538832 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:21:26.538997 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:21:26.539136 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:21:26.539464 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 13:21:31.673504 >> Command sent successfully.
293 13:21:31.675785 Returned 0 in 5 seconds
294 13:21:31.776156 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 13:21:31.776678 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 13:21:31.776827 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 13:21:31.776929 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:21:31.777011 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:21:31.777104 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:21:31.777488 [Enter `^Ec?' for help]
302 13:21:31.949558
303 13:21:31.949692
304 13:21:31.949796 F0: 102B 0000
305 13:21:31.949899
306 13:21:31.950003 F3: 1001 0000 [0200]
307 13:21:31.950106
308 13:21:31.953168 F3: 1001 0000
309 13:21:31.953274
310 13:21:31.953361 F7: 102D 0000
311 13:21:31.953443
312 13:21:31.953522 F1: 0000 0000
313 13:21:31.953600
314 13:21:31.956735 V0: 0000 0000 [0001]
315 13:21:31.956857
316 13:21:31.956938 00: 0007 8000
317 13:21:31.957019
318 13:21:31.960613 01: 0000 0000
319 13:21:31.960702
320 13:21:31.960830 BP: 0C00 0209 [0000]
321 13:21:31.960913
322 13:21:31.960994 G0: 1182 0000
323 13:21:31.964500
324 13:21:31.964635 EC: 0000 0021 [4000]
325 13:21:31.964744
326 13:21:31.964867 S7: 0000 0000 [0000]
327 13:21:31.968584
328 13:21:31.968671 CC: 0000 0000 [0001]
329 13:21:31.968808
330 13:21:31.971706 T0: 0000 0040 [010F]
331 13:21:31.971794
332 13:21:31.971881 Jump to BL
333 13:21:31.971962
334 13:21:31.996130
335 13:21:31.996274
336 13:21:31.996393
337 13:21:32.003083 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 13:21:32.006633 ARM64: Exception handlers installed.
339 13:21:32.010185 ARM64: Testing exception
340 13:21:32.013911 ARM64: Done test exception
341 13:21:32.021525 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 13:21:32.032147 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 13:21:32.038859 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 13:21:32.048866 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 13:21:32.055622 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 13:21:32.061952 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 13:21:32.072552 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 13:21:32.079898 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 13:21:32.098858 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 13:21:32.102174 WDT: Last reset was cold boot
351 13:21:32.105487 SPI1(PAD0) initialized at 2873684 Hz
352 13:21:32.108829 SPI5(PAD0) initialized at 992727 Hz
353 13:21:32.112148 VBOOT: Loading verstage.
354 13:21:32.118974 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 13:21:32.122247 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 13:21:32.125377 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 13:21:32.129070 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 13:21:32.136360 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 13:21:32.143098 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 13:21:32.154321 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 13:21:32.154406
362 13:21:32.154473
363 13:21:32.163961 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 13:21:32.167065 ARM64: Exception handlers installed.
365 13:21:32.170493 ARM64: Testing exception
366 13:21:32.170582 ARM64: Done test exception
367 13:21:32.177338 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 13:21:32.180996 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 13:21:32.195110 Probing TPM: . done!
370 13:21:32.195195 TPM ready after 0 ms
371 13:21:32.201759 Connected to device vid:did:rid of 1ae0:0028:00
372 13:21:32.208632 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 13:21:32.266352 Initialized TPM device CR50 revision 0
374 13:21:32.277981 tlcl_send_startup: Startup return code is 0
375 13:21:32.278120 TPM: setup succeeded
376 13:21:32.289169 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 13:21:32.297904 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 13:21:32.308353 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 13:21:32.317669 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 13:21:32.321343 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 13:21:32.329470 in-header: 03 07 00 00 08 00 00 00
382 13:21:32.333011 in-data: aa e4 47 04 13 02 00 00
383 13:21:32.336953 Chrome EC: UHEPI supported
384 13:21:32.344106 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 13:21:32.347922 in-header: 03 ad 00 00 08 00 00 00
386 13:21:32.351509 in-data: 00 20 20 08 00 00 00 00
387 13:21:32.351594 Phase 1
388 13:21:32.355486 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 13:21:32.362682 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 13:21:32.366221 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 13:21:32.369954 Recovery requested (1009000e)
392 13:21:32.378995 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 13:21:32.384423 tlcl_extend: response is 0
394 13:21:32.393607 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 13:21:32.399522 tlcl_extend: response is 0
396 13:21:32.406640 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 13:21:32.427075 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 13:21:32.433991 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 13:21:32.434077
400 13:21:32.434143
401 13:21:32.444077 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 13:21:32.447187 ARM64: Exception handlers installed.
403 13:21:32.447286 ARM64: Testing exception
404 13:21:32.450495 ARM64: Done test exception
405 13:21:32.472644 pmic_efuse_setting: Set efuses in 11 msecs
406 13:21:32.475827 pmwrap_interface_init: Select PMIF_VLD_RDY
407 13:21:32.482460 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 13:21:32.486046 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 13:21:32.489224 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 13:21:32.496142 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 13:21:32.499510 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 13:21:32.506639 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 13:21:32.510520 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 13:21:32.514669 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 13:21:32.518175 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 13:21:32.525354 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 13:21:32.528991 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 13:21:32.532934 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 13:21:32.536051 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 13:21:32.543272 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 13:21:32.550343 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 13:21:32.557201 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 13:21:32.561050 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 13:21:32.568090 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 13:21:32.571854 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 13:21:32.578956 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 13:21:32.582040 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 13:21:32.589460 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 13:21:32.596159 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 13:21:32.599277 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 13:21:32.606011 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 13:21:32.612700 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 13:21:32.616647 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 13:21:32.619777 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 13:21:32.626120 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 13:21:32.629499 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 13:21:32.636410 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 13:21:32.639670 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 13:21:32.646138 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 13:21:32.649649 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 13:21:32.656322 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 13:21:32.659462 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 13:21:32.666214 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 13:21:32.669546 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 13:21:32.676357 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 13:21:32.679590 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 13:21:32.682837 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 13:21:32.689955 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 13:21:32.693433 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 13:21:32.696893 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 13:21:32.700223 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 13:21:32.706997 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 13:21:32.710532 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 13:21:32.713866 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 13:21:32.717237 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 13:21:32.723689 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 13:21:32.727095 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 13:21:32.733785 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 13:21:32.743950 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 13:21:32.747123 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 13:21:32.757106 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 13:21:32.764156 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 13:21:32.767541 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 13:21:32.773909 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:21:32.777404 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 13:21:32.784386 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x22
467 13:21:32.791007 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 13:21:32.794503 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 13:21:32.798220 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 13:21:32.809148 [RTC]rtc_get_frequency_meter,154: input=15, output=772
471 13:21:32.818858 [RTC]rtc_get_frequency_meter,154: input=23, output=957
472 13:21:32.828074 [RTC]rtc_get_frequency_meter,154: input=19, output=864
473 13:21:32.837645 [RTC]rtc_get_frequency_meter,154: input=17, output=818
474 13:21:32.848179 [RTC]rtc_get_frequency_meter,154: input=16, output=795
475 13:21:32.851257 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 13:21:32.855103 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 13:21:32.858638 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 13:21:32.865784 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 13:21:32.869441 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 13:21:32.873006 ADC[4]: Raw value=902507 ID=7
481 13:21:32.873091 ADC[3]: Raw value=213179 ID=1
482 13:21:32.876887 RAM Code: 0x71
483 13:21:32.880518 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 13:21:32.884404 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 13:21:32.895157 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 13:21:32.899101 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 13:21:32.902327 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 13:21:32.906065 in-header: 03 07 00 00 08 00 00 00
489 13:21:32.909796 in-data: aa e4 47 04 13 02 00 00
490 13:21:32.912349 Chrome EC: UHEPI supported
491 13:21:32.919221 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 13:21:32.922530 in-header: 03 ed 00 00 08 00 00 00
493 13:21:32.925860 in-data: 80 20 60 08 00 00 00 00
494 13:21:32.929245 MRC: failed to locate region type 0.
495 13:21:32.935818 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 13:21:32.939126 DRAM-K: Running full calibration
497 13:21:32.945915 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 13:21:32.946026 header.status = 0x0
499 13:21:32.949620 header.version = 0x6 (expected: 0x6)
500 13:21:32.952621 header.size = 0xd00 (expected: 0xd00)
501 13:21:32.955957 header.flags = 0x0
502 13:21:32.962844 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 13:21:32.980334 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
504 13:21:32.987397 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 13:21:32.990763 dram_init: ddr_geometry: 2
506 13:21:32.990850 [EMI] MDL number = 2
507 13:21:32.994706 [EMI] Get MDL freq = 0
508 13:21:32.994792 dram_init: ddr_type: 0
509 13:21:32.997406 is_discrete_lpddr4: 1
510 13:21:33.000904 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 13:21:33.000990
512 13:21:33.001060
513 13:21:33.004420 [Bian_co] ETT version 0.0.0.1
514 13:21:33.007385 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 13:21:33.007471
516 13:21:33.010956 dramc_set_vcore_voltage set vcore to 650000
517 13:21:33.014652 Read voltage for 800, 4
518 13:21:33.014739 Vio18 = 0
519 13:21:33.017666 Vcore = 650000
520 13:21:33.017752 Vdram = 0
521 13:21:33.017821 Vddq = 0
522 13:21:33.021260 Vmddr = 0
523 13:21:33.021346 dram_init: config_dvfs: 1
524 13:21:33.027685 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 13:21:33.030972 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 13:21:33.037828 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
527 13:21:33.040890 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
528 13:21:33.044411 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 13:21:33.047361 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 13:21:33.051144 MEM_TYPE=3, freq_sel=18
531 13:21:33.054336 sv_algorithm_assistance_LP4_1600
532 13:21:33.057597 ============ PULL DRAM RESETB DOWN ============
533 13:21:33.060622 ========== PULL DRAM RESETB DOWN end =========
534 13:21:33.064242 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 13:21:33.067465 ===================================
536 13:21:33.070661 LPDDR4 DRAM CONFIGURATION
537 13:21:33.074227 ===================================
538 13:21:33.077695 EX_ROW_EN[0] = 0x0
539 13:21:33.077781 EX_ROW_EN[1] = 0x0
540 13:21:33.081264 LP4Y_EN = 0x0
541 13:21:33.081350 WORK_FSP = 0x0
542 13:21:33.084354 WL = 0x2
543 13:21:33.084440 RL = 0x2
544 13:21:33.088447 BL = 0x2
545 13:21:33.088533 RPST = 0x0
546 13:21:33.091044 RD_PRE = 0x0
547 13:21:33.091130 WR_PRE = 0x1
548 13:21:33.094330 WR_PST = 0x0
549 13:21:33.094416 DBI_WR = 0x0
550 13:21:33.097742 DBI_RD = 0x0
551 13:21:33.097828 OTF = 0x1
552 13:21:33.101086 ===================================
553 13:21:33.104633 ===================================
554 13:21:33.107881 ANA top config
555 13:21:33.111135 ===================================
556 13:21:33.114545 DLL_ASYNC_EN = 0
557 13:21:33.114631 ALL_SLAVE_EN = 1
558 13:21:33.118213 NEW_RANK_MODE = 1
559 13:21:33.121303 DLL_IDLE_MODE = 1
560 13:21:33.124685 LP45_APHY_COMB_EN = 1
561 13:21:33.124792 TX_ODT_DIS = 1
562 13:21:33.127901 NEW_8X_MODE = 1
563 13:21:33.131384 ===================================
564 13:21:33.134694 ===================================
565 13:21:33.137881 data_rate = 1600
566 13:21:33.141244 CKR = 1
567 13:21:33.144704 DQ_P2S_RATIO = 8
568 13:21:33.148036 ===================================
569 13:21:33.151621 CA_P2S_RATIO = 8
570 13:21:33.151721 DQ_CA_OPEN = 0
571 13:21:33.155038 DQ_SEMI_OPEN = 0
572 13:21:33.158200 CA_SEMI_OPEN = 0
573 13:21:33.161303 CA_FULL_RATE = 0
574 13:21:33.165118 DQ_CKDIV4_EN = 1
575 13:21:33.165204 CA_CKDIV4_EN = 1
576 13:21:33.168033 CA_PREDIV_EN = 0
577 13:21:33.171881 PH8_DLY = 0
578 13:21:33.174608 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 13:21:33.178102 DQ_AAMCK_DIV = 4
580 13:21:33.181186 CA_AAMCK_DIV = 4
581 13:21:33.181271 CA_ADMCK_DIV = 4
582 13:21:33.184571 DQ_TRACK_CA_EN = 0
583 13:21:33.188051 CA_PICK = 800
584 13:21:33.191105 CA_MCKIO = 800
585 13:21:33.195000 MCKIO_SEMI = 0
586 13:21:33.197906 PLL_FREQ = 3068
587 13:21:33.201523 DQ_UI_PI_RATIO = 32
588 13:21:33.201644 CA_UI_PI_RATIO = 0
589 13:21:33.204817 ===================================
590 13:21:33.208138 ===================================
591 13:21:33.211474 memory_type:LPDDR4
592 13:21:33.214850 GP_NUM : 10
593 13:21:33.214992 SRAM_EN : 1
594 13:21:33.217994 MD32_EN : 0
595 13:21:33.221447 ===================================
596 13:21:33.225217 [ANA_INIT] >>>>>>>>>>>>>>
597 13:21:33.225302 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 13:21:33.228729 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 13:21:33.232741 ===================================
600 13:21:33.236195 data_rate = 1600,PCW = 0X7600
601 13:21:33.239667 ===================================
602 13:21:33.243598 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 13:21:33.246955 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 13:21:33.255069 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 13:21:33.258407 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 13:21:33.262015 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 13:21:33.265164 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 13:21:33.268379 [ANA_INIT] flow start
609 13:21:33.268472 [ANA_INIT] PLL >>>>>>>>
610 13:21:33.271948 [ANA_INIT] PLL <<<<<<<<
611 13:21:33.275118 [ANA_INIT] MIDPI >>>>>>>>
612 13:21:33.275204 [ANA_INIT] MIDPI <<<<<<<<
613 13:21:33.279167 [ANA_INIT] DLL >>>>>>>>
614 13:21:33.282653 [ANA_INIT] flow end
615 13:21:33.286473 ============ LP4 DIFF to SE enter ============
616 13:21:33.289888 ============ LP4 DIFF to SE exit ============
617 13:21:33.289974 [ANA_INIT] <<<<<<<<<<<<<
618 13:21:33.294317 [Flow] Enable top DCM control >>>>>
619 13:21:33.297823 [Flow] Enable top DCM control <<<<<
620 13:21:33.301327 Enable DLL master slave shuffle
621 13:21:33.304995 ==============================================================
622 13:21:33.308318 Gating Mode config
623 13:21:33.312047 ==============================================================
624 13:21:33.316370 Config description:
625 13:21:33.327402 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 13:21:33.330667 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 13:21:33.337829 SELPH_MODE 0: By rank 1: By Phase
628 13:21:33.341820 ==============================================================
629 13:21:33.345364 GAT_TRACK_EN = 1
630 13:21:33.349418 RX_GATING_MODE = 2
631 13:21:33.349557 RX_GATING_TRACK_MODE = 2
632 13:21:33.353381 SELPH_MODE = 1
633 13:21:33.357086 PICG_EARLY_EN = 1
634 13:21:33.360773 VALID_LAT_VALUE = 1
635 13:21:33.364541 ==============================================================
636 13:21:33.368658 Enter into Gating configuration >>>>
637 13:21:33.372162 Exit from Gating configuration <<<<
638 13:21:33.375791 Enter into DVFS_PRE_config >>>>>
639 13:21:33.387018 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 13:21:33.390810 Exit from DVFS_PRE_config <<<<<
641 13:21:33.394540 Enter into PICG configuration >>>>
642 13:21:33.394629 Exit from PICG configuration <<<<
643 13:21:33.398133 [RX_INPUT] configuration >>>>>
644 13:21:33.401800 [RX_INPUT] configuration <<<<<
645 13:21:33.405832 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 13:21:33.412907 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 13:21:33.416886 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 13:21:33.423713 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 13:21:33.431584 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 13:21:33.438527 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 13:21:33.442456 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 13:21:33.446160 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 13:21:33.449838 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 13:21:33.453480 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 13:21:33.457381 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 13:21:33.461670 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 13:21:33.465173 ===================================
658 13:21:33.468580 LPDDR4 DRAM CONFIGURATION
659 13:21:33.472199 ===================================
660 13:21:33.472314 EX_ROW_EN[0] = 0x0
661 13:21:33.476214 EX_ROW_EN[1] = 0x0
662 13:21:33.476330 LP4Y_EN = 0x0
663 13:21:33.479578 WORK_FSP = 0x0
664 13:21:33.479710 WL = 0x2
665 13:21:33.483399 RL = 0x2
666 13:21:33.483528 BL = 0x2
667 13:21:33.483647 RPST = 0x0
668 13:21:33.487605 RD_PRE = 0x0
669 13:21:33.487732 WR_PRE = 0x1
670 13:21:33.490684 WR_PST = 0x0
671 13:21:33.490810 DBI_WR = 0x0
672 13:21:33.494636 DBI_RD = 0x0
673 13:21:33.494767 OTF = 0x1
674 13:21:33.498281 ===================================
675 13:21:33.502089 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 13:21:33.505991 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 13:21:33.509394 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 13:21:33.513605 ===================================
679 13:21:33.517101 LPDDR4 DRAM CONFIGURATION
680 13:21:33.520720 ===================================
681 13:21:33.520815 EX_ROW_EN[0] = 0x10
682 13:21:33.524727 EX_ROW_EN[1] = 0x0
683 13:21:33.524831 LP4Y_EN = 0x0
684 13:21:33.528627 WORK_FSP = 0x0
685 13:21:33.528719 WL = 0x2
686 13:21:33.531969 RL = 0x2
687 13:21:33.532059 BL = 0x2
688 13:21:33.535537 RPST = 0x0
689 13:21:33.535628 RD_PRE = 0x0
690 13:21:33.539280 WR_PRE = 0x1
691 13:21:33.539371 WR_PST = 0x0
692 13:21:33.543075 DBI_WR = 0x0
693 13:21:33.543205 DBI_RD = 0x0
694 13:21:33.543316 OTF = 0x1
695 13:21:33.547153 ===================================
696 13:21:33.553826 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 13:21:33.558670 nWR fixed to 40
698 13:21:33.562361 [ModeRegInit_LP4] CH0 RK0
699 13:21:33.562449 [ModeRegInit_LP4] CH0 RK1
700 13:21:33.565740 [ModeRegInit_LP4] CH1 RK0
701 13:21:33.565828 [ModeRegInit_LP4] CH1 RK1
702 13:21:33.569416 match AC timing 13
703 13:21:33.573125 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 13:21:33.576831 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 13:21:33.580599 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 13:21:33.588035 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 13:21:33.591188 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 13:21:33.594381 [EMI DOE] emi_dcm 0
709 13:21:33.597624 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 13:21:33.597711 ==
711 13:21:33.600847 Dram Type= 6, Freq= 0, CH_0, rank 0
712 13:21:33.604052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 13:21:33.604141 ==
714 13:21:33.611091 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 13:21:33.617644 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 13:21:33.625530 [CA 0] Center 38 (7~69) winsize 63
717 13:21:33.628916 [CA 1] Center 38 (7~69) winsize 63
718 13:21:33.632712 [CA 2] Center 35 (5~66) winsize 62
719 13:21:33.635736 [CA 3] Center 35 (5~66) winsize 62
720 13:21:33.639050 [CA 4] Center 34 (4~65) winsize 62
721 13:21:33.642355 [CA 5] Center 33 (3~64) winsize 62
722 13:21:33.642442
723 13:21:33.645936 [CmdBusTrainingLP45] Vref(ca) range 1: 34
724 13:21:33.646022
725 13:21:33.649734 [CATrainingPosCal] consider 1 rank data
726 13:21:33.652262 u2DelayCellTimex100 = 270/100 ps
727 13:21:33.655807 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
728 13:21:33.659182 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
729 13:21:33.666069 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
730 13:21:33.669294 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
731 13:21:33.672437 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
732 13:21:33.675846 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
733 13:21:33.675934
734 13:21:33.679185 CA PerBit enable=1, Macro0, CA PI delay=33
735 13:21:33.679301
736 13:21:33.682506 [CBTSetCACLKResult] CA Dly = 33
737 13:21:33.682594 CS Dly: 6 (0~37)
738 13:21:33.682665 ==
739 13:21:33.685860 Dram Type= 6, Freq= 0, CH_0, rank 1
740 13:21:33.692804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 13:21:33.692933 ==
742 13:21:33.696024 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 13:21:33.702601 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 13:21:33.712008 [CA 0] Center 38 (8~69) winsize 62
745 13:21:33.715638 [CA 1] Center 38 (8~69) winsize 62
746 13:21:33.718909 [CA 2] Center 36 (6~67) winsize 62
747 13:21:33.722154 [CA 3] Center 35 (5~66) winsize 62
748 13:21:33.725951 [CA 4] Center 35 (4~66) winsize 63
749 13:21:33.729080 [CA 5] Center 34 (4~65) winsize 62
750 13:21:33.729166
751 13:21:33.731988 [CmdBusTrainingLP45] Vref(ca) range 1: 32
752 13:21:33.732120
753 13:21:33.735490 [CATrainingPosCal] consider 2 rank data
754 13:21:33.738993 u2DelayCellTimex100 = 270/100 ps
755 13:21:33.741990 CA0 delay=38 (8~69),Diff = 4 PI (28 cell)
756 13:21:33.745628 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
757 13:21:33.752156 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 13:21:33.755742 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 13:21:33.759202 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 13:21:33.762073 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 13:21:33.762198
762 13:21:33.765360 CA PerBit enable=1, Macro0, CA PI delay=34
763 13:21:33.765485
764 13:21:33.768957 [CBTSetCACLKResult] CA Dly = 34
765 13:21:33.769089 CS Dly: 6 (0~38)
766 13:21:33.769205
767 13:21:33.772421 ----->DramcWriteLeveling(PI) begin...
768 13:21:33.772578 ==
769 13:21:33.775567 Dram Type= 6, Freq= 0, CH_0, rank 0
770 13:21:33.782170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 13:21:33.782300 ==
772 13:21:33.786036 Write leveling (Byte 0): 33 => 33
773 13:21:33.789160 Write leveling (Byte 1): 28 => 28
774 13:21:33.789289 DramcWriteLeveling(PI) end<-----
775 13:21:33.789403
776 13:21:33.792455 ==
777 13:21:33.795903 Dram Type= 6, Freq= 0, CH_0, rank 0
778 13:21:33.799457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 13:21:33.799624 ==
780 13:21:33.802393 [Gating] SW mode calibration
781 13:21:33.809905 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 13:21:33.813510 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 13:21:33.817288 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
784 13:21:33.820738 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
785 13:21:33.827758 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 13:21:33.831201 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 13:21:33.834733 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 13:21:33.841733 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 13:21:33.844778 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:21:33.848324 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:21:33.854979 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:21:33.858060 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:21:33.861645 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:21:33.864810 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:21:33.871422 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:21:33.874758 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:21:33.878131 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:21:33.884722 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:21:33.888494 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:21:33.891800 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
801 13:21:33.898372 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
802 13:21:33.901597 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:21:33.904832 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 13:21:33.911431 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 13:21:33.914785 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:21:33.918167 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:21:33.924975 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:21:33.928058 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
809 13:21:33.931332 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
810 13:21:33.934871 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
811 13:21:33.941455 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 13:21:33.945007 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 13:21:33.948537 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 13:21:33.955026 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 13:21:33.958285 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 13:21:33.961619 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (0 1)
817 13:21:33.968516 0 10 8 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
818 13:21:33.971679 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
819 13:21:33.975148 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 13:21:33.981812 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 13:21:33.984838 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 13:21:33.988361 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:21:33.995330 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:21:33.998413 0 11 4 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
825 13:21:34.001786 0 11 8 | B1->B0 | 2e2e 4646 | 1 0 | (0 0) (0 0)
826 13:21:34.008203 0 11 12 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
827 13:21:34.012264 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 13:21:34.015366 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 13:21:34.018558 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 13:21:34.025444 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 13:21:34.028396 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 13:21:34.031808 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 13:21:34.038414 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
834 13:21:34.041987 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 13:21:34.045284 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 13:21:34.052233 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 13:21:34.055272 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 13:21:34.058467 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:21:34.065326 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:21:34.068720 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:21:34.072108 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:21:34.078674 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:21:34.081804 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:21:34.085683 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:21:34.091822 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:21:34.095139 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:21:34.098776 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:21:34.101953 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
849 13:21:34.108585 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
850 13:21:34.111930 Total UI for P1: 0, mck2ui 16
851 13:21:34.115229 best dqsien dly found for B0: ( 0, 14, 4)
852 13:21:34.118610 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 13:21:34.122192 Total UI for P1: 0, mck2ui 16
854 13:21:34.125140 best dqsien dly found for B1: ( 0, 14, 8)
855 13:21:34.128568 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
856 13:21:34.132190 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
857 13:21:34.132325
858 13:21:34.135103 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
859 13:21:34.138571 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
860 13:21:34.142108 [Gating] SW calibration Done
861 13:21:34.142237 ==
862 13:21:34.145376 Dram Type= 6, Freq= 0, CH_0, rank 0
863 13:21:34.148671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
864 13:21:34.152351 ==
865 13:21:34.152481 RX Vref Scan: 0
866 13:21:34.152600
867 13:21:34.155778 RX Vref 0 -> 0, step: 1
868 13:21:34.155903
869 13:21:34.158664 RX Delay -130 -> 252, step: 16
870 13:21:34.162421 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
871 13:21:34.165774 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
872 13:21:34.169433 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
873 13:21:34.172290 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
874 13:21:34.175691 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
875 13:21:34.182307 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
876 13:21:34.185770 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
877 13:21:34.189190 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
878 13:21:34.192496 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
879 13:21:34.195783 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
880 13:21:34.202399 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
881 13:21:34.205610 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
882 13:21:34.208940 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
883 13:21:34.212408 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
884 13:21:34.215827 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
885 13:21:34.222336 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
886 13:21:34.222448 ==
887 13:21:34.225965 Dram Type= 6, Freq= 0, CH_0, rank 0
888 13:21:34.229510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
889 13:21:34.229597 ==
890 13:21:34.229664 DQS Delay:
891 13:21:34.233046 DQS0 = 0, DQS1 = 0
892 13:21:34.233130 DQM Delay:
893 13:21:34.235942 DQM0 = 94, DQM1 = 80
894 13:21:34.236027 DQ Delay:
895 13:21:34.239635 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
896 13:21:34.242608 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =109
897 13:21:34.245965 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
898 13:21:34.249522 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
899 13:21:34.249608
900 13:21:34.249675
901 13:21:34.249738 ==
902 13:21:34.252699 Dram Type= 6, Freq= 0, CH_0, rank 0
903 13:21:34.255728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 13:21:34.255814 ==
905 13:21:34.255882
906 13:21:34.259458
907 13:21:34.259543 TX Vref Scan disable
908 13:21:34.262437 == TX Byte 0 ==
909 13:21:34.265874 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
910 13:21:34.269172 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
911 13:21:34.272508 == TX Byte 1 ==
912 13:21:34.275824 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
913 13:21:34.279343 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
914 13:21:34.279429 ==
915 13:21:34.282726 Dram Type= 6, Freq= 0, CH_0, rank 0
916 13:21:34.289302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 13:21:34.289389 ==
918 13:21:34.301274 TX Vref=22, minBit 7, minWin=27, winSum=441
919 13:21:34.305028 TX Vref=24, minBit 11, minWin=27, winSum=446
920 13:21:34.308729 TX Vref=26, minBit 3, minWin=28, winSum=451
921 13:21:34.311339 TX Vref=28, minBit 3, minWin=28, winSum=453
922 13:21:34.315000 TX Vref=30, minBit 3, minWin=28, winSum=456
923 13:21:34.317959 TX Vref=32, minBit 1, minWin=28, winSum=456
924 13:21:34.324822 [TxChooseVref] Worse bit 3, Min win 28, Win sum 456, Final Vref 30
925 13:21:34.324936
926 13:21:34.328291 Final TX Range 1 Vref 30
927 13:21:34.328368
928 13:21:34.328479 ==
929 13:21:34.331775 Dram Type= 6, Freq= 0, CH_0, rank 0
930 13:21:34.334921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 13:21:34.335009 ==
932 13:21:34.335097
933 13:21:34.338784
934 13:21:34.338871 TX Vref Scan disable
935 13:21:34.342072 == TX Byte 0 ==
936 13:21:34.344659 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
937 13:21:34.351647 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
938 13:21:34.351736 == TX Byte 1 ==
939 13:21:34.354780 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
940 13:21:34.358198 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
941 13:21:34.361698
942 13:21:34.361784 [DATLAT]
943 13:21:34.361858 Freq=800, CH0 RK0
944 13:21:34.361924
945 13:21:34.365110 DATLAT Default: 0xa
946 13:21:34.365196 0, 0xFFFF, sum = 0
947 13:21:34.368449 1, 0xFFFF, sum = 0
948 13:21:34.368536 2, 0xFFFF, sum = 0
949 13:21:34.371784 3, 0xFFFF, sum = 0
950 13:21:34.371871 4, 0xFFFF, sum = 0
951 13:21:34.374999 5, 0xFFFF, sum = 0
952 13:21:34.375131 6, 0xFFFF, sum = 0
953 13:21:34.378672 7, 0xFFFF, sum = 0
954 13:21:34.378832 8, 0xFFFF, sum = 0
955 13:21:34.382064 9, 0x0, sum = 1
956 13:21:34.382211 10, 0x0, sum = 2
957 13:21:34.385342 11, 0x0, sum = 3
958 13:21:34.385455 12, 0x0, sum = 4
959 13:21:34.388693 best_step = 10
960 13:21:34.388797
961 13:21:34.388866 ==
962 13:21:34.391776 Dram Type= 6, Freq= 0, CH_0, rank 0
963 13:21:34.395119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 13:21:34.395225 ==
965 13:21:34.398558 RX Vref Scan: 1
966 13:21:34.398676
967 13:21:34.398784 Set Vref Range= 32 -> 127
968 13:21:34.398879
969 13:21:34.402082 RX Vref 32 -> 127, step: 1
970 13:21:34.402169
971 13:21:34.405473 RX Delay -95 -> 252, step: 8
972 13:21:34.405561
973 13:21:34.408652 Set Vref, RX VrefLevel [Byte0]: 32
974 13:21:34.412066 [Byte1]: 32
975 13:21:34.412154
976 13:21:34.415352 Set Vref, RX VrefLevel [Byte0]: 33
977 13:21:34.419074 [Byte1]: 33
978 13:21:34.422094
979 13:21:34.422181 Set Vref, RX VrefLevel [Byte0]: 34
980 13:21:34.425109 [Byte1]: 34
981 13:21:34.429661
982 13:21:34.429794 Set Vref, RX VrefLevel [Byte0]: 35
983 13:21:34.432823 [Byte1]: 35
984 13:21:34.436698
985 13:21:34.436829 Set Vref, RX VrefLevel [Byte0]: 36
986 13:21:34.440353 [Byte1]: 36
987 13:21:34.444707
988 13:21:34.444826 Set Vref, RX VrefLevel [Byte0]: 37
989 13:21:34.447983 [Byte1]: 37
990 13:21:34.452548
991 13:21:34.452636 Set Vref, RX VrefLevel [Byte0]: 38
992 13:21:34.456207 [Byte1]: 38
993 13:21:34.459989
994 13:21:34.460076 Set Vref, RX VrefLevel [Byte0]: 39
995 13:21:34.463040 [Byte1]: 39
996 13:21:34.467359
997 13:21:34.467445 Set Vref, RX VrefLevel [Byte0]: 40
998 13:21:34.470761 [Byte1]: 40
999 13:21:34.475557
1000 13:21:34.475679 Set Vref, RX VrefLevel [Byte0]: 41
1001 13:21:34.478754 [Byte1]: 41
1002 13:21:34.483024
1003 13:21:34.483117 Set Vref, RX VrefLevel [Byte0]: 42
1004 13:21:34.486610 [Byte1]: 42
1005 13:21:34.490853
1006 13:21:34.490962 Set Vref, RX VrefLevel [Byte0]: 43
1007 13:21:34.494038 [Byte1]: 43
1008 13:21:34.498208
1009 13:21:34.498321 Set Vref, RX VrefLevel [Byte0]: 44
1010 13:21:34.501446 [Byte1]: 44
1011 13:21:34.505818
1012 13:21:34.505928 Set Vref, RX VrefLevel [Byte0]: 45
1013 13:21:34.509070 [Byte1]: 45
1014 13:21:34.512740
1015 13:21:34.512832 Set Vref, RX VrefLevel [Byte0]: 46
1016 13:21:34.516424 [Byte1]: 46
1017 13:21:34.521016
1018 13:21:34.521102 Set Vref, RX VrefLevel [Byte0]: 47
1019 13:21:34.524041 [Byte1]: 47
1020 13:21:34.528175
1021 13:21:34.528276 Set Vref, RX VrefLevel [Byte0]: 48
1022 13:21:34.531455 [Byte1]: 48
1023 13:21:34.535682
1024 13:21:34.535793 Set Vref, RX VrefLevel [Byte0]: 49
1025 13:21:34.539310 [Byte1]: 49
1026 13:21:34.543572
1027 13:21:34.543659 Set Vref, RX VrefLevel [Byte0]: 50
1028 13:21:34.546681 [Byte1]: 50
1029 13:21:34.551133
1030 13:21:34.551226 Set Vref, RX VrefLevel [Byte0]: 51
1031 13:21:34.554200 [Byte1]: 51
1032 13:21:34.558446
1033 13:21:34.558525 Set Vref, RX VrefLevel [Byte0]: 52
1034 13:21:34.562281 [Byte1]: 52
1035 13:21:34.566055
1036 13:21:34.566134 Set Vref, RX VrefLevel [Byte0]: 53
1037 13:21:34.569513 [Byte1]: 53
1038 13:21:34.573755
1039 13:21:34.573841 Set Vref, RX VrefLevel [Byte0]: 54
1040 13:21:34.577426 [Byte1]: 54
1041 13:21:34.581262
1042 13:21:34.581352 Set Vref, RX VrefLevel [Byte0]: 55
1043 13:21:34.584813 [Byte1]: 55
1044 13:21:34.589050
1045 13:21:34.589141 Set Vref, RX VrefLevel [Byte0]: 56
1046 13:21:34.592723 [Byte1]: 56
1047 13:21:34.596482
1048 13:21:34.596611 Set Vref, RX VrefLevel [Byte0]: 57
1049 13:21:34.600119 [Byte1]: 57
1050 13:21:34.604304
1051 13:21:34.604428 Set Vref, RX VrefLevel [Byte0]: 58
1052 13:21:34.607914 [Byte1]: 58
1053 13:21:34.611847
1054 13:21:34.611928 Set Vref, RX VrefLevel [Byte0]: 59
1055 13:21:34.615065 [Byte1]: 59
1056 13:21:34.619412
1057 13:21:34.619558 Set Vref, RX VrefLevel [Byte0]: 60
1058 13:21:34.622842 [Byte1]: 60
1059 13:21:34.626822
1060 13:21:34.626947 Set Vref, RX VrefLevel [Byte0]: 61
1061 13:21:34.630419 [Byte1]: 61
1062 13:21:34.634521
1063 13:21:34.634645 Set Vref, RX VrefLevel [Byte0]: 62
1064 13:21:34.637947 [Byte1]: 62
1065 13:21:34.642164
1066 13:21:34.642303 Set Vref, RX VrefLevel [Byte0]: 63
1067 13:21:34.645267 [Byte1]: 63
1068 13:21:34.649725
1069 13:21:34.649833 Set Vref, RX VrefLevel [Byte0]: 64
1070 13:21:34.653051 [Byte1]: 64
1071 13:21:34.657198
1072 13:21:34.657302 Set Vref, RX VrefLevel [Byte0]: 65
1073 13:21:34.660731 [Byte1]: 65
1074 13:21:34.665590
1075 13:21:34.665697 Set Vref, RX VrefLevel [Byte0]: 66
1076 13:21:34.668614 [Byte1]: 66
1077 13:21:34.672390
1078 13:21:34.672496 Set Vref, RX VrefLevel [Byte0]: 67
1079 13:21:34.675778 [Byte1]: 67
1080 13:21:34.680283
1081 13:21:34.680374 Set Vref, RX VrefLevel [Byte0]: 68
1082 13:21:34.683445 [Byte1]: 68
1083 13:21:34.687561
1084 13:21:34.687648 Set Vref, RX VrefLevel [Byte0]: 69
1085 13:21:34.690931 [Byte1]: 69
1086 13:21:34.695319
1087 13:21:34.695406 Set Vref, RX VrefLevel [Byte0]: 70
1088 13:21:34.698541 [Byte1]: 70
1089 13:21:34.702960
1090 13:21:34.703073 Set Vref, RX VrefLevel [Byte0]: 71
1091 13:21:34.706382 [Byte1]: 71
1092 13:21:34.710588
1093 13:21:34.710673 Set Vref, RX VrefLevel [Byte0]: 72
1094 13:21:34.713936 [Byte1]: 72
1095 13:21:34.718171
1096 13:21:34.718256 Set Vref, RX VrefLevel [Byte0]: 73
1097 13:21:34.721510 [Byte1]: 73
1098 13:21:34.725707
1099 13:21:34.725820 Set Vref, RX VrefLevel [Byte0]: 74
1100 13:21:34.729295 [Byte1]: 74
1101 13:21:34.733403
1102 13:21:34.733492 Set Vref, RX VrefLevel [Byte0]: 75
1103 13:21:34.736579 [Byte1]: 75
1104 13:21:34.741553
1105 13:21:34.741639 Set Vref, RX VrefLevel [Byte0]: 76
1106 13:21:34.744106 [Byte1]: 76
1107 13:21:34.748604
1108 13:21:34.748716 Set Vref, RX VrefLevel [Byte0]: 77
1109 13:21:34.751939 [Byte1]: 77
1110 13:21:34.756029
1111 13:21:34.756114 Set Vref, RX VrefLevel [Byte0]: 78
1112 13:21:34.759540 [Byte1]: 78
1113 13:21:34.763818
1114 13:21:34.763904 Final RX Vref Byte 0 = 61 to rank0
1115 13:21:34.767560 Final RX Vref Byte 1 = 58 to rank0
1116 13:21:34.770340 Final RX Vref Byte 0 = 61 to rank1
1117 13:21:34.773588 Final RX Vref Byte 1 = 58 to rank1==
1118 13:21:34.776985 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 13:21:34.780461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 13:21:34.783818 ==
1121 13:21:34.783904 DQS Delay:
1122 13:21:34.783973 DQS0 = 0, DQS1 = 0
1123 13:21:34.787307 DQM Delay:
1124 13:21:34.787393 DQM0 = 93, DQM1 = 82
1125 13:21:34.790903 DQ Delay:
1126 13:21:34.790988 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1127 13:21:34.794102 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1128 13:21:34.797749 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1129 13:21:34.800647 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1130 13:21:34.800764
1131 13:21:34.804064
1132 13:21:34.811155 [DQSOSCAuto] RK0, (LSB)MR18= 0x3934, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1133 13:21:34.813955 CH0 RK0: MR19=606, MR18=3934
1134 13:21:34.820678 CH0_RK0: MR19=0x606, MR18=0x3934, DQSOSC=395, MR23=63, INC=94, DEC=63
1135 13:21:34.820791
1136 13:21:34.824266 ----->DramcWriteLeveling(PI) begin...
1137 13:21:34.824353 ==
1138 13:21:34.827857 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 13:21:34.830851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 13:21:34.830938 ==
1141 13:21:34.834046 Write leveling (Byte 0): 31 => 31
1142 13:21:34.837547 Write leveling (Byte 1): 29 => 29
1143 13:21:34.840745 DramcWriteLeveling(PI) end<-----
1144 13:21:34.840880
1145 13:21:34.840993 ==
1146 13:21:34.843883 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 13:21:34.847608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 13:21:34.847730 ==
1149 13:21:34.850710 [Gating] SW mode calibration
1150 13:21:34.857364 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 13:21:34.863834 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 13:21:34.867298 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 13:21:34.870941 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 13:21:34.877446 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1155 13:21:34.921692 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 13:21:34.922064 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 13:21:34.922155 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 13:21:34.922425 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 13:21:34.922496 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 13:21:34.922595 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 13:21:34.922849 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:21:34.922921 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:21:34.923592 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:21:34.923861 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 13:21:34.965608 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 13:21:34.965877 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 13:21:34.965951 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 13:21:34.966403 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 13:21:34.966781 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1170 13:21:34.967130 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 13:21:34.967229 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:21:34.967484 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 13:21:34.967575 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:21:34.967653 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:21:34.988680 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 13:21:34.988826 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 13:21:34.989349 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 13:21:34.989614 0 9 8 | B1->B0 | 2a2a 3434 | 1 0 | (1 1) (0 0)
1179 13:21:34.989733 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 13:21:34.992867 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 13:21:34.996010 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 13:21:34.999340 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 13:21:35.003330 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 13:21:35.009558 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1185 13:21:35.012882 0 10 4 | B1->B0 | 3232 2f2f | 0 0 | (1 0) (0 0)
1186 13:21:35.016001 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1187 13:21:35.019506 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 13:21:35.026277 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 13:21:35.029843 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 13:21:35.033139 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 13:21:35.039524 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 13:21:35.043044 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 13:21:35.046140 0 11 4 | B1->B0 | 2424 2b2b | 1 0 | (0 0) (0 0)
1194 13:21:35.052968 0 11 8 | B1->B0 | 3939 4343 | 0 0 | (0 0) (0 0)
1195 13:21:35.056631 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 13:21:35.060235 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 13:21:35.063667 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 13:21:35.071043 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 13:21:35.074509 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 13:21:35.077851 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 13:21:35.081253 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 13:21:35.088354 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 13:21:35.091583 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 13:21:35.095023 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 13:21:35.098813 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 13:21:35.105161 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:21:35.108411 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 13:21:35.112010 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 13:21:35.118712 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:21:35.121685 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 13:21:35.125224 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 13:21:35.131765 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 13:21:35.135435 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 13:21:35.138569 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 13:21:35.145407 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 13:21:35.148922 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 13:21:35.151801 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1218 13:21:35.158595 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1219 13:21:35.158703 Total UI for P1: 0, mck2ui 16
1220 13:21:35.162140 best dqsien dly found for B0: ( 0, 14, 4)
1221 13:21:35.168691 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 13:21:35.172049 Total UI for P1: 0, mck2ui 16
1223 13:21:35.175330 best dqsien dly found for B1: ( 0, 14, 8)
1224 13:21:35.178558 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1225 13:21:35.182067 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1226 13:21:35.182181
1227 13:21:35.185591 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1228 13:21:35.188704 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 13:21:35.192105 [Gating] SW calibration Done
1230 13:21:35.192217 ==
1231 13:21:35.195537 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 13:21:35.199260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 13:21:35.199374 ==
1234 13:21:35.202528 RX Vref Scan: 0
1235 13:21:35.202638
1236 13:21:35.202740 RX Vref 0 -> 0, step: 1
1237 13:21:35.202833
1238 13:21:35.205956 RX Delay -130 -> 252, step: 16
1239 13:21:35.209123 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1240 13:21:35.215653 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1241 13:21:35.219137 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1242 13:21:35.222364 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1243 13:21:35.225966 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1244 13:21:35.229212 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1245 13:21:35.236016 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1246 13:21:35.238992 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1247 13:21:35.242394 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1248 13:21:35.245813 iDelay=206, Bit 9, Center 69 (-34 ~ 173) 208
1249 13:21:35.249374 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1250 13:21:35.255936 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1251 13:21:35.259304 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1252 13:21:35.262393 iDelay=206, Bit 13, Center 77 (-34 ~ 189) 224
1253 13:21:35.266056 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1254 13:21:35.269100 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1255 13:21:35.269187 ==
1256 13:21:35.272862 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 13:21:35.279496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 13:21:35.279582 ==
1259 13:21:35.279651 DQS Delay:
1260 13:21:35.282537 DQS0 = 0, DQS1 = 0
1261 13:21:35.282622 DQM Delay:
1262 13:21:35.282691 DQM0 = 87, DQM1 = 81
1263 13:21:35.286336 DQ Delay:
1264 13:21:35.289456 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1265 13:21:35.292579 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1266 13:21:35.295754 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1267 13:21:35.299261 DQ12 =85, DQ13 =77, DQ14 =93, DQ15 =93
1268 13:21:35.299346
1269 13:21:35.299414
1270 13:21:35.299476 ==
1271 13:21:35.302641 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 13:21:35.305873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 13:21:35.305959 ==
1274 13:21:35.306027
1275 13:21:35.306091
1276 13:21:35.309696 TX Vref Scan disable
1277 13:21:35.309781 == TX Byte 0 ==
1278 13:21:35.316269 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1279 13:21:35.319217 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1280 13:21:35.319303 == TX Byte 1 ==
1281 13:21:35.325806 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1282 13:21:35.329194 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1283 13:21:35.329279 ==
1284 13:21:35.332893 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 13:21:35.335881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 13:21:35.335967 ==
1287 13:21:35.350230 TX Vref=22, minBit 3, minWin=27, winSum=443
1288 13:21:35.353592 TX Vref=24, minBit 3, minWin=27, winSum=449
1289 13:21:35.356844 TX Vref=26, minBit 8, minWin=27, winSum=451
1290 13:21:35.360403 TX Vref=28, minBit 8, minWin=27, winSum=456
1291 13:21:35.363533 TX Vref=30, minBit 8, minWin=27, winSum=457
1292 13:21:35.366940 TX Vref=32, minBit 6, minWin=28, winSum=457
1293 13:21:35.373840 [TxChooseVref] Worse bit 6, Min win 28, Win sum 457, Final Vref 32
1294 13:21:35.373956
1295 13:21:35.377289 Final TX Range 1 Vref 32
1296 13:21:35.377376
1297 13:21:35.377444 ==
1298 13:21:35.380640 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 13:21:35.383888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 13:21:35.383973 ==
1301 13:21:35.384040
1302 13:21:35.384102
1303 13:21:35.387117 TX Vref Scan disable
1304 13:21:35.390564 == TX Byte 0 ==
1305 13:21:35.393862 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1306 13:21:35.397011 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1307 13:21:35.400585 == TX Byte 1 ==
1308 13:21:35.403953 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1309 13:21:35.406946 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1310 13:21:35.407048
1311 13:21:35.410379 [DATLAT]
1312 13:21:35.410477 Freq=800, CH0 RK1
1313 13:21:35.410569
1314 13:21:35.413754 DATLAT Default: 0xa
1315 13:21:35.413838 0, 0xFFFF, sum = 0
1316 13:21:35.417032 1, 0xFFFF, sum = 0
1317 13:21:35.417116 2, 0xFFFF, sum = 0
1318 13:21:35.420295 3, 0xFFFF, sum = 0
1319 13:21:35.420380 4, 0xFFFF, sum = 0
1320 13:21:35.423891 5, 0xFFFF, sum = 0
1321 13:21:35.423977 6, 0xFFFF, sum = 0
1322 13:21:35.427189 7, 0xFFFF, sum = 0
1323 13:21:35.427274 8, 0xFFFF, sum = 0
1324 13:21:35.430462 9, 0x0, sum = 1
1325 13:21:35.430548 10, 0x0, sum = 2
1326 13:21:35.434036 11, 0x0, sum = 3
1327 13:21:35.434122 12, 0x0, sum = 4
1328 13:21:35.436985 best_step = 10
1329 13:21:35.437069
1330 13:21:35.437136 ==
1331 13:21:35.440624 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 13:21:35.443830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 13:21:35.443914 ==
1334 13:21:35.447097 RX Vref Scan: 0
1335 13:21:35.447181
1336 13:21:35.447248 RX Vref 0 -> 0, step: 1
1337 13:21:35.447313
1338 13:21:35.450520 RX Delay -79 -> 252, step: 8
1339 13:21:35.456783 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1340 13:21:35.460922 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1341 13:21:35.463853 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1342 13:21:35.467023 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1343 13:21:35.470709 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1344 13:21:35.476969 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1345 13:21:35.480609 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1346 13:21:35.483748 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1347 13:21:35.487343 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1348 13:21:35.490832 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1349 13:21:35.493957 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1350 13:21:35.500613 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1351 13:21:35.504249 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1352 13:21:35.507187 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1353 13:21:35.510785 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1354 13:21:35.517481 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1355 13:21:35.517568 ==
1356 13:21:35.520970 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 13:21:35.523800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 13:21:35.523891 ==
1359 13:21:35.523961 DQS Delay:
1360 13:21:35.527042 DQS0 = 0, DQS1 = 0
1361 13:21:35.527128 DQM Delay:
1362 13:21:35.530778 DQM0 = 90, DQM1 = 81
1363 13:21:35.530864 DQ Delay:
1364 13:21:35.534141 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1365 13:21:35.537552 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1366 13:21:35.540681 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1367 13:21:35.544133 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1368 13:21:35.544235
1369 13:21:35.544329
1370 13:21:35.550901 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f1a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1371 13:21:35.554081 CH0 RK1: MR19=606, MR18=3F1A
1372 13:21:35.560693 CH0_RK1: MR19=0x606, MR18=0x3F1A, DQSOSC=393, MR23=63, INC=95, DEC=63
1373 13:21:35.564166 [RxdqsGatingPostProcess] freq 800
1374 13:21:35.567458 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 13:21:35.571176 Pre-setting of DQS Precalculation
1376 13:21:35.577549 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 13:21:35.577636 ==
1378 13:21:35.581488 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 13:21:35.584417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 13:21:35.584561 ==
1381 13:21:35.591201 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 13:21:35.597463 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 13:21:35.605314 [CA 0] Center 36 (6~67) winsize 62
1384 13:21:35.608774 [CA 1] Center 36 (6~67) winsize 62
1385 13:21:35.611949 [CA 2] Center 34 (4~65) winsize 62
1386 13:21:35.615367 [CA 3] Center 34 (4~65) winsize 62
1387 13:21:35.618809 [CA 4] Center 34 (4~65) winsize 62
1388 13:21:35.622005 [CA 5] Center 33 (3~64) winsize 62
1389 13:21:35.622092
1390 13:21:35.625450 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1391 13:21:35.625537
1392 13:21:35.629013 [CATrainingPosCal] consider 1 rank data
1393 13:21:35.631911 u2DelayCellTimex100 = 270/100 ps
1394 13:21:35.635388 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1395 13:21:35.638878 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1396 13:21:35.645359 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1397 13:21:35.649236 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1398 13:21:35.652156 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1399 13:21:35.655568 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1400 13:21:35.655654
1401 13:21:35.658851 CA PerBit enable=1, Macro0, CA PI delay=33
1402 13:21:35.658938
1403 13:21:35.662710 [CBTSetCACLKResult] CA Dly = 33
1404 13:21:35.662796 CS Dly: 5 (0~36)
1405 13:21:35.662864 ==
1406 13:21:35.665857 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 13:21:35.672211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 13:21:35.672297 ==
1409 13:21:35.675500 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 13:21:35.682173 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 13:21:35.691498 [CA 0] Center 37 (7~67) winsize 61
1412 13:21:35.694769 [CA 1] Center 37 (6~68) winsize 63
1413 13:21:35.698429 [CA 2] Center 35 (4~66) winsize 63
1414 13:21:35.701478 [CA 3] Center 34 (4~65) winsize 62
1415 13:21:35.705048 [CA 4] Center 34 (4~65) winsize 62
1416 13:21:35.708097 [CA 5] Center 34 (3~65) winsize 63
1417 13:21:35.708182
1418 13:21:35.711720 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1419 13:21:35.711806
1420 13:21:35.714936 [CATrainingPosCal] consider 2 rank data
1421 13:21:35.718262 u2DelayCellTimex100 = 270/100 ps
1422 13:21:35.722068 CA0 delay=37 (7~67),Diff = 4 PI (28 cell)
1423 13:21:35.725231 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1424 13:21:35.728967 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1425 13:21:35.732670 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1426 13:21:35.736531 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1427 13:21:35.740348 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1428 13:21:35.740472
1429 13:21:35.744059 CA PerBit enable=1, Macro0, CA PI delay=33
1430 13:21:35.744181
1431 13:21:35.748050 [CBTSetCACLKResult] CA Dly = 33
1432 13:21:35.748172 CS Dly: 6 (0~38)
1433 13:21:35.748284
1434 13:21:35.752110 ----->DramcWriteLeveling(PI) begin...
1435 13:21:35.752235 ==
1436 13:21:35.755322 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 13:21:35.759116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 13:21:35.762213 ==
1439 13:21:35.762335 Write leveling (Byte 0): 27 => 27
1440 13:21:35.766260 Write leveling (Byte 1): 28 => 28
1441 13:21:35.768937 DramcWriteLeveling(PI) end<-----
1442 13:21:35.769060
1443 13:21:35.769171 ==
1444 13:21:35.772303 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 13:21:35.779198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 13:21:35.779324 ==
1447 13:21:35.779438 [Gating] SW mode calibration
1448 13:21:35.789058 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 13:21:35.792664 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 13:21:35.795704 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1451 13:21:35.802731 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1452 13:21:35.805819 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 13:21:35.809043 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 13:21:35.815941 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 13:21:35.819423 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:21:35.822764 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 13:21:35.829526 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:21:35.832637 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 13:21:35.835872 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 13:21:35.842745 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 13:21:35.845928 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 13:21:35.849347 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 13:21:35.852744 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 13:21:35.859479 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 13:21:35.862671 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1466 13:21:35.866449 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1467 13:21:35.872900 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1468 13:21:35.876196 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1469 13:21:35.879793 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 13:21:35.886290 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 13:21:35.889728 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 13:21:35.892857 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 13:21:35.899507 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 13:21:35.902854 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 13:21:35.906825 0 9 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1476 13:21:35.912996 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 13:21:35.916187 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 13:21:35.919537 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 13:21:35.926188 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 13:21:35.929382 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 13:21:35.932616 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 13:21:35.939673 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1483 13:21:35.942935 0 10 4 | B1->B0 | 2b2b 2f2f | 0 0 | (1 0) (1 0)
1484 13:21:35.946201 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 13:21:35.949741 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 13:21:35.956148 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 13:21:35.959287 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 13:21:35.962623 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 13:21:35.969423 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 13:21:35.972942 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 13:21:35.976233 0 11 4 | B1->B0 | 3131 3f3f | 0 0 | (1 1) (0 0)
1492 13:21:35.982839 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1493 13:21:35.986231 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 13:21:35.989350 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 13:21:35.996054 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 13:21:35.999538 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 13:21:36.003116 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 13:21:36.009287 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1499 13:21:36.012947 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1500 13:21:36.016610 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 13:21:36.022937 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 13:21:36.026436 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 13:21:36.029465 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 13:21:36.032792 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 13:21:36.039677 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 13:21:36.042819 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 13:21:36.046277 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 13:21:36.052857 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 13:21:36.056655 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 13:21:36.059697 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 13:21:36.066323 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 13:21:36.069638 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 13:21:36.072962 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 13:21:36.079644 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1515 13:21:36.083094 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1516 13:21:36.086656 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1517 13:21:36.089756 Total UI for P1: 0, mck2ui 16
1518 13:21:36.093161 best dqsien dly found for B0: ( 0, 14, 2)
1519 13:21:36.099486 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 13:21:36.099610 Total UI for P1: 0, mck2ui 16
1521 13:21:36.103070 best dqsien dly found for B1: ( 0, 14, 8)
1522 13:21:36.109591 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1523 13:21:36.113226 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1524 13:21:36.113348
1525 13:21:36.116815 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1526 13:21:36.119614 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1527 13:21:36.123100 [Gating] SW calibration Done
1528 13:21:36.123209 ==
1529 13:21:36.126417 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 13:21:36.129566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 13:21:36.129650 ==
1532 13:21:36.129717 RX Vref Scan: 0
1533 13:21:36.132890
1534 13:21:36.132973 RX Vref 0 -> 0, step: 1
1535 13:21:36.133040
1536 13:21:36.136397 RX Delay -130 -> 252, step: 16
1537 13:21:36.139567 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1538 13:21:36.142851 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1539 13:21:36.149738 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1540 13:21:36.153255 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1541 13:21:36.156595 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1542 13:21:36.159962 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1543 13:21:36.163128 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1544 13:21:36.169824 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1545 13:21:36.172892 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1546 13:21:36.176904 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1547 13:21:36.179884 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1548 13:21:36.183388 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1549 13:21:36.190075 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1550 13:21:36.193632 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1551 13:21:36.196507 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1552 13:21:36.199841 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1553 13:21:36.199927 ==
1554 13:21:36.203130 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 13:21:36.210210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 13:21:36.210296 ==
1557 13:21:36.210363 DQS Delay:
1558 13:21:36.210424 DQS0 = 0, DQS1 = 0
1559 13:21:36.213454 DQM Delay:
1560 13:21:36.213538 DQM0 = 89, DQM1 = 80
1561 13:21:36.216866 DQ Delay:
1562 13:21:36.216951 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =93
1563 13:21:36.220183 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1564 13:21:36.223465 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1565 13:21:36.226783 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1566 13:21:36.230550
1567 13:21:36.230635
1568 13:21:36.230701 ==
1569 13:21:36.233748 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 13:21:36.236876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 13:21:36.236962 ==
1572 13:21:36.237030
1573 13:21:36.237091
1574 13:21:36.240082 TX Vref Scan disable
1575 13:21:36.240172 == TX Byte 0 ==
1576 13:21:36.246694 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1577 13:21:36.250007 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1578 13:21:36.250091 == TX Byte 1 ==
1579 13:21:36.256928 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1580 13:21:36.260120 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1581 13:21:36.260205 ==
1582 13:21:36.263424 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 13:21:36.266703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 13:21:36.266788 ==
1585 13:21:36.280098 TX Vref=22, minBit 8, minWin=27, winSum=449
1586 13:21:36.283347 TX Vref=24, minBit 15, minWin=27, winSum=456
1587 13:21:36.286866 TX Vref=26, minBit 15, minWin=27, winSum=455
1588 13:21:36.290648 TX Vref=28, minBit 8, minWin=28, winSum=460
1589 13:21:36.293547 TX Vref=30, minBit 15, minWin=27, winSum=458
1590 13:21:36.300939 TX Vref=32, minBit 9, minWin=27, winSum=459
1591 13:21:36.304366 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 28
1592 13:21:36.304451
1593 13:21:36.308011 Final TX Range 1 Vref 28
1594 13:21:36.308100
1595 13:21:36.308167 ==
1596 13:21:36.311577 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 13:21:36.314834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 13:21:36.314920 ==
1599 13:21:36.314988
1600 13:21:36.315051
1601 13:21:36.317748 TX Vref Scan disable
1602 13:21:36.321106 == TX Byte 0 ==
1603 13:21:36.324860 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1604 13:21:36.328266 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1605 13:21:36.331370 == TX Byte 1 ==
1606 13:21:36.334602 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1607 13:21:36.337878 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1608 13:21:36.338008
1609 13:21:36.338125 [DATLAT]
1610 13:21:36.341522 Freq=800, CH1 RK0
1611 13:21:36.341650
1612 13:21:36.344743 DATLAT Default: 0xa
1613 13:21:36.344893 0, 0xFFFF, sum = 0
1614 13:21:36.348235 1, 0xFFFF, sum = 0
1615 13:21:36.348343 2, 0xFFFF, sum = 0
1616 13:21:36.351508 3, 0xFFFF, sum = 0
1617 13:21:36.351593 4, 0xFFFF, sum = 0
1618 13:21:36.354710 5, 0xFFFF, sum = 0
1619 13:21:36.354796 6, 0xFFFF, sum = 0
1620 13:21:36.358012 7, 0xFFFF, sum = 0
1621 13:21:36.358098 8, 0xFFFF, sum = 0
1622 13:21:36.361323 9, 0x0, sum = 1
1623 13:21:36.361435 10, 0x0, sum = 2
1624 13:21:36.365114 11, 0x0, sum = 3
1625 13:21:36.365200 12, 0x0, sum = 4
1626 13:21:36.365268 best_step = 10
1627 13:21:36.368089
1628 13:21:36.368173 ==
1629 13:21:36.371258 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 13:21:36.374560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 13:21:36.374644 ==
1632 13:21:36.374712 RX Vref Scan: 1
1633 13:21:36.374776
1634 13:21:36.378226 Set Vref Range= 32 -> 127
1635 13:21:36.378310
1636 13:21:36.381523 RX Vref 32 -> 127, step: 1
1637 13:21:36.381608
1638 13:21:36.384619 RX Delay -95 -> 252, step: 8
1639 13:21:36.384729
1640 13:21:36.388720 Set Vref, RX VrefLevel [Byte0]: 32
1641 13:21:36.391259 [Byte1]: 32
1642 13:21:36.391344
1643 13:21:36.395394 Set Vref, RX VrefLevel [Byte0]: 33
1644 13:21:36.398030 [Byte1]: 33
1645 13:21:36.398115
1646 13:21:36.401515 Set Vref, RX VrefLevel [Byte0]: 34
1647 13:21:36.404716 [Byte1]: 34
1648 13:21:36.408378
1649 13:21:36.408461 Set Vref, RX VrefLevel [Byte0]: 35
1650 13:21:36.411519 [Byte1]: 35
1651 13:21:36.415809
1652 13:21:36.415945 Set Vref, RX VrefLevel [Byte0]: 36
1653 13:21:36.419122 [Byte1]: 36
1654 13:21:36.423194
1655 13:21:36.423316 Set Vref, RX VrefLevel [Byte0]: 37
1656 13:21:36.426944 [Byte1]: 37
1657 13:21:36.430795
1658 13:21:36.430917 Set Vref, RX VrefLevel [Byte0]: 38
1659 13:21:36.434179 [Byte1]: 38
1660 13:21:36.438693
1661 13:21:36.438817 Set Vref, RX VrefLevel [Byte0]: 39
1662 13:21:36.441962 [Byte1]: 39
1663 13:21:36.446188
1664 13:21:36.446312 Set Vref, RX VrefLevel [Byte0]: 40
1665 13:21:36.449419 [Byte1]: 40
1666 13:21:36.453937
1667 13:21:36.454060 Set Vref, RX VrefLevel [Byte0]: 41
1668 13:21:36.457101 [Byte1]: 41
1669 13:21:36.461505
1670 13:21:36.461585 Set Vref, RX VrefLevel [Byte0]: 42
1671 13:21:36.464570 [Byte1]: 42
1672 13:21:36.469105
1673 13:21:36.469188 Set Vref, RX VrefLevel [Byte0]: 43
1674 13:21:36.472454 [Byte1]: 43
1675 13:21:36.476342
1676 13:21:36.476425 Set Vref, RX VrefLevel [Byte0]: 44
1677 13:21:36.479918 [Byte1]: 44
1678 13:21:36.484249
1679 13:21:36.484359 Set Vref, RX VrefLevel [Byte0]: 45
1680 13:21:36.487230 [Byte1]: 45
1681 13:21:36.491795
1682 13:21:36.491878 Set Vref, RX VrefLevel [Byte0]: 46
1683 13:21:36.494938 [Byte1]: 46
1684 13:21:36.499743
1685 13:21:36.499826 Set Vref, RX VrefLevel [Byte0]: 47
1686 13:21:36.502601 [Byte1]: 47
1687 13:21:36.507045
1688 13:21:36.507128 Set Vref, RX VrefLevel [Byte0]: 48
1689 13:21:36.510186 [Byte1]: 48
1690 13:21:36.514719
1691 13:21:36.514803 Set Vref, RX VrefLevel [Byte0]: 49
1692 13:21:36.517679 [Byte1]: 49
1693 13:21:36.522630
1694 13:21:36.522714 Set Vref, RX VrefLevel [Byte0]: 50
1695 13:21:36.525406 [Byte1]: 50
1696 13:21:36.529603
1697 13:21:36.529686 Set Vref, RX VrefLevel [Byte0]: 51
1698 13:21:36.533119 [Byte1]: 51
1699 13:21:36.537410
1700 13:21:36.537492 Set Vref, RX VrefLevel [Byte0]: 52
1701 13:21:36.540517 [Byte1]: 52
1702 13:21:36.544988
1703 13:21:36.545071 Set Vref, RX VrefLevel [Byte0]: 53
1704 13:21:36.548196 [Byte1]: 53
1705 13:21:36.552520
1706 13:21:36.552603 Set Vref, RX VrefLevel [Byte0]: 54
1707 13:21:36.555779 [Byte1]: 54
1708 13:21:36.559953
1709 13:21:36.560037 Set Vref, RX VrefLevel [Byte0]: 55
1710 13:21:36.563294 [Byte1]: 55
1711 13:21:36.567629
1712 13:21:36.567723 Set Vref, RX VrefLevel [Byte0]: 56
1713 13:21:36.571004 [Byte1]: 56
1714 13:21:36.575144
1715 13:21:36.575229 Set Vref, RX VrefLevel [Byte0]: 57
1716 13:21:36.578473 [Byte1]: 57
1717 13:21:36.582846
1718 13:21:36.582931 Set Vref, RX VrefLevel [Byte0]: 58
1719 13:21:36.586636 [Byte1]: 58
1720 13:21:36.590498
1721 13:21:36.590581 Set Vref, RX VrefLevel [Byte0]: 59
1722 13:21:36.593753 [Byte1]: 59
1723 13:21:36.598253
1724 13:21:36.598337 Set Vref, RX VrefLevel [Byte0]: 60
1725 13:21:36.601348 [Byte1]: 60
1726 13:21:36.605569
1727 13:21:36.605653 Set Vref, RX VrefLevel [Byte0]: 61
1728 13:21:36.609187 [Byte1]: 61
1729 13:21:36.613430
1730 13:21:36.613513 Set Vref, RX VrefLevel [Byte0]: 62
1731 13:21:36.616986 [Byte1]: 62
1732 13:21:36.620908
1733 13:21:36.620995 Set Vref, RX VrefLevel [Byte0]: 63
1734 13:21:36.624214 [Byte1]: 63
1735 13:21:36.629194
1736 13:21:36.629277 Set Vref, RX VrefLevel [Byte0]: 64
1737 13:21:36.631865 [Byte1]: 64
1738 13:21:36.636234
1739 13:21:36.636317 Set Vref, RX VrefLevel [Byte0]: 65
1740 13:21:36.639959 [Byte1]: 65
1741 13:21:36.643838
1742 13:21:36.643921 Set Vref, RX VrefLevel [Byte0]: 66
1743 13:21:36.646992 [Byte1]: 66
1744 13:21:36.651458
1745 13:21:36.651541 Set Vref, RX VrefLevel [Byte0]: 67
1746 13:21:36.654585 [Byte1]: 67
1747 13:21:36.659038
1748 13:21:36.659120 Set Vref, RX VrefLevel [Byte0]: 68
1749 13:21:36.662396 [Byte1]: 68
1750 13:21:36.666350
1751 13:21:36.666433 Set Vref, RX VrefLevel [Byte0]: 69
1752 13:21:36.669705 [Byte1]: 69
1753 13:21:36.674300
1754 13:21:36.674382 Set Vref, RX VrefLevel [Byte0]: 70
1755 13:21:36.677451 [Byte1]: 70
1756 13:21:36.681815
1757 13:21:36.681898 Set Vref, RX VrefLevel [Byte0]: 71
1758 13:21:36.684900 [Byte1]: 71
1759 13:21:36.689455
1760 13:21:36.689537 Set Vref, RX VrefLevel [Byte0]: 72
1761 13:21:36.692538 [Byte1]: 72
1762 13:21:36.696759
1763 13:21:36.696843 Set Vref, RX VrefLevel [Byte0]: 73
1764 13:21:36.700142 [Byte1]: 73
1765 13:21:36.704371
1766 13:21:36.704479 Set Vref, RX VrefLevel [Byte0]: 74
1767 13:21:36.707754 [Byte1]: 74
1768 13:21:36.712076
1769 13:21:36.712178 Set Vref, RX VrefLevel [Byte0]: 75
1770 13:21:36.715345 [Byte1]: 75
1771 13:21:36.719803
1772 13:21:36.719886 Set Vref, RX VrefLevel [Byte0]: 76
1773 13:21:36.723034 [Byte1]: 76
1774 13:21:36.727468
1775 13:21:36.727550 Set Vref, RX VrefLevel [Byte0]: 77
1776 13:21:36.730667 [Byte1]: 77
1777 13:21:36.735235
1778 13:21:36.735318 Set Vref, RX VrefLevel [Byte0]: 78
1779 13:21:36.738152 [Byte1]: 78
1780 13:21:36.742811
1781 13:21:36.742893 Final RX Vref Byte 0 = 52 to rank0
1782 13:21:36.745781 Final RX Vref Byte 1 = 63 to rank0
1783 13:21:36.749276 Final RX Vref Byte 0 = 52 to rank1
1784 13:21:36.752386 Final RX Vref Byte 1 = 63 to rank1==
1785 13:21:36.755698 Dram Type= 6, Freq= 0, CH_1, rank 0
1786 13:21:36.762425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1787 13:21:36.762509 ==
1788 13:21:36.762576 DQS Delay:
1789 13:21:36.762638 DQS0 = 0, DQS1 = 0
1790 13:21:36.765804 DQM Delay:
1791 13:21:36.765887 DQM0 = 93, DQM1 = 83
1792 13:21:36.769193 DQ Delay:
1793 13:21:36.772408 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1794 13:21:36.775934 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1795 13:21:36.779004 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1796 13:21:36.782402 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1797 13:21:36.782484
1798 13:21:36.782550
1799 13:21:36.788971 [DQSOSCAuto] RK0, (LSB)MR18= 0x324f, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1800 13:21:36.792408 CH1 RK0: MR19=606, MR18=324F
1801 13:21:36.799201 CH1_RK0: MR19=0x606, MR18=0x324F, DQSOSC=390, MR23=63, INC=97, DEC=64
1802 13:21:36.799284
1803 13:21:36.802442 ----->DramcWriteLeveling(PI) begin...
1804 13:21:36.802526 ==
1805 13:21:36.805724 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 13:21:36.809333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1807 13:21:36.809416 ==
1808 13:21:36.812467 Write leveling (Byte 0): 28 => 28
1809 13:21:36.815970 Write leveling (Byte 1): 29 => 29
1810 13:21:36.819494 DramcWriteLeveling(PI) end<-----
1811 13:21:36.819577
1812 13:21:36.819643 ==
1813 13:21:36.822702 Dram Type= 6, Freq= 0, CH_1, rank 1
1814 13:21:36.825918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1815 13:21:36.826001 ==
1816 13:21:36.829464 [Gating] SW mode calibration
1817 13:21:36.836057 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1818 13:21:36.842776 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1819 13:21:36.846085 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1820 13:21:36.849317 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 13:21:36.855936 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 13:21:36.859391 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 13:21:36.862895 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 13:21:36.869370 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 13:21:36.872692 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 13:21:36.876428 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 13:21:36.879596 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 13:21:36.886091 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 13:21:36.889501 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 13:21:36.892932 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 13:21:36.899467 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 13:21:36.903183 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 13:21:36.906064 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 13:21:36.912824 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 13:21:36.916315 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1836 13:21:36.919520 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1837 13:21:36.926194 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 13:21:36.929646 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 13:21:36.932933 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 13:21:36.939846 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 13:21:36.943040 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 13:21:36.946463 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 13:21:36.953320 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 13:21:36.956280 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 13:21:36.959629 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 13:21:36.962902 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 13:21:36.969492 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 13:21:36.973166 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 13:21:36.976422 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 13:21:36.983180 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 13:21:36.986360 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
1852 13:21:36.989585 0 10 4 | B1->B0 | 2c2c 2f2f | 1 1 | (1 1) (1 0)
1853 13:21:36.996587 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
1854 13:21:36.999957 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 13:21:37.003177 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 13:21:37.010166 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 13:21:37.013583 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 13:21:37.016389 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 13:21:37.023291 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 13:21:37.026608 0 11 4 | B1->B0 | 2f2f 3333 | 0 1 | (0 0) (0 0)
1861 13:21:37.030654 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 13:21:37.036489 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 13:21:37.039948 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 13:21:37.043234 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 13:21:37.046711 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 13:21:37.053553 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 13:21:37.057006 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 13:21:37.060218 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1869 13:21:37.066860 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 13:21:37.069963 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 13:21:37.073442 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 13:21:37.080276 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 13:21:37.083442 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 13:21:37.086803 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 13:21:37.093955 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 13:21:37.096978 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 13:21:37.100394 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 13:21:37.103424 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 13:21:37.110520 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 13:21:37.113821 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 13:21:37.116678 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 13:21:37.123611 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 13:21:37.126888 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1884 13:21:37.130228 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1885 13:21:37.137377 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1886 13:21:37.140550 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 13:21:37.143577 Total UI for P1: 0, mck2ui 16
1888 13:21:37.146946 best dqsien dly found for B0: ( 0, 14, 4)
1889 13:21:37.150195 Total UI for P1: 0, mck2ui 16
1890 13:21:37.153736 best dqsien dly found for B1: ( 0, 14, 4)
1891 13:21:37.157060 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1892 13:21:37.160589 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1893 13:21:37.160674
1894 13:21:37.163985 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1895 13:21:37.167183 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1896 13:21:37.170381 [Gating] SW calibration Done
1897 13:21:37.170465 ==
1898 13:21:37.173872 Dram Type= 6, Freq= 0, CH_1, rank 1
1899 13:21:37.177243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1900 13:21:37.177328 ==
1901 13:21:37.180254 RX Vref Scan: 0
1902 13:21:37.180338
1903 13:21:37.183505 RX Vref 0 -> 0, step: 1
1904 13:21:37.183589
1905 13:21:37.183657 RX Delay -130 -> 252, step: 16
1906 13:21:37.190268 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1907 13:21:37.193741 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1908 13:21:37.197349 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1909 13:21:37.200402 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1910 13:21:37.203996 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1911 13:21:37.210707 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1912 13:21:37.213818 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1913 13:21:37.217464 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1914 13:21:37.220551 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1915 13:21:37.223810 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1916 13:21:37.230522 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1917 13:21:37.233845 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1918 13:21:37.237193 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1919 13:21:37.240557 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1920 13:21:37.243881 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1921 13:21:37.250906 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1922 13:21:37.251008 ==
1923 13:21:37.253694 Dram Type= 6, Freq= 0, CH_1, rank 1
1924 13:21:37.257490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1925 13:21:37.257574 ==
1926 13:21:37.257642 DQS Delay:
1927 13:21:37.260428 DQS0 = 0, DQS1 = 0
1928 13:21:37.260512 DQM Delay:
1929 13:21:37.263897 DQM0 = 92, DQM1 = 80
1930 13:21:37.263982 DQ Delay:
1931 13:21:37.267428 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1932 13:21:37.270971 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =85
1933 13:21:37.274093 DQ8 =61, DQ9 =77, DQ10 =85, DQ11 =77
1934 13:21:37.277391 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1935 13:21:37.277475
1936 13:21:37.277542
1937 13:21:37.277604 ==
1938 13:21:37.280865 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 13:21:37.284344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 13:21:37.284429 ==
1941 13:21:37.284497
1942 13:21:37.287411
1943 13:21:37.287495 TX Vref Scan disable
1944 13:21:37.290818 == TX Byte 0 ==
1945 13:21:37.294391 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1946 13:21:37.297466 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1947 13:21:37.300936 == TX Byte 1 ==
1948 13:21:37.304277 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1949 13:21:37.307350 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1950 13:21:37.307434 ==
1951 13:21:37.310875 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 13:21:37.317340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 13:21:37.317425 ==
1954 13:21:37.328780 TX Vref=22, minBit 14, minWin=27, winSum=456
1955 13:21:37.332260 TX Vref=24, minBit 13, minWin=27, winSum=455
1956 13:21:37.335420 TX Vref=26, minBit 13, minWin=27, winSum=454
1957 13:21:37.338706 TX Vref=28, minBit 8, minWin=28, winSum=461
1958 13:21:37.342329 TX Vref=30, minBit 8, minWin=28, winSum=460
1959 13:21:37.348971 TX Vref=32, minBit 8, minWin=28, winSum=460
1960 13:21:37.352122 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 28
1961 13:21:37.352208
1962 13:21:37.355401 Final TX Range 1 Vref 28
1963 13:21:37.355486
1964 13:21:37.355571 ==
1965 13:21:37.358820 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 13:21:37.362081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 13:21:37.365455 ==
1968 13:21:37.365540
1969 13:21:37.365624
1970 13:21:37.365704 TX Vref Scan disable
1971 13:21:37.369326 == TX Byte 0 ==
1972 13:21:37.372495 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1973 13:21:37.375816 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1974 13:21:37.379213 == TX Byte 1 ==
1975 13:21:37.382272 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1976 13:21:37.385847 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1977 13:21:37.389074
1978 13:21:37.389159 [DATLAT]
1979 13:21:37.389243 Freq=800, CH1 RK1
1980 13:21:37.389323
1981 13:21:37.392409 DATLAT Default: 0xa
1982 13:21:37.392494 0, 0xFFFF, sum = 0
1983 13:21:37.395670 1, 0xFFFF, sum = 0
1984 13:21:37.395757 2, 0xFFFF, sum = 0
1985 13:21:37.398945 3, 0xFFFF, sum = 0
1986 13:21:37.399030 4, 0xFFFF, sum = 0
1987 13:21:37.402263 5, 0xFFFF, sum = 0
1988 13:21:37.402349 6, 0xFFFF, sum = 0
1989 13:21:37.405742 7, 0xFFFF, sum = 0
1990 13:21:37.409191 8, 0xFFFF, sum = 0
1991 13:21:37.409278 9, 0x0, sum = 1
1992 13:21:37.409365 10, 0x0, sum = 2
1993 13:21:37.412382 11, 0x0, sum = 3
1994 13:21:37.412468 12, 0x0, sum = 4
1995 13:21:37.415568 best_step = 10
1996 13:21:37.415652
1997 13:21:37.415736 ==
1998 13:21:37.419227 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 13:21:37.422321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 13:21:37.422407 ==
2001 13:21:37.425678 RX Vref Scan: 0
2002 13:21:37.425763
2003 13:21:37.425847 RX Vref 0 -> 0, step: 1
2004 13:21:37.425926
2005 13:21:37.428744 RX Delay -95 -> 252, step: 8
2006 13:21:37.435616 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2007 13:21:37.439333 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2008 13:21:37.442533 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2009 13:21:37.445686 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2010 13:21:37.449530 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2011 13:21:37.456032 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2012 13:21:37.459268 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2013 13:21:37.462339 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2014 13:21:37.466023 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2015 13:21:37.469302 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2016 13:21:37.473192 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2017 13:21:37.479191 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2018 13:21:37.482658 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2019 13:21:37.486240 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2020 13:21:37.489296 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2021 13:21:37.492787 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2022 13:21:37.495944 ==
2023 13:21:37.499428 Dram Type= 6, Freq= 0, CH_1, rank 1
2024 13:21:37.502654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2025 13:21:37.502739 ==
2026 13:21:37.502805 DQS Delay:
2027 13:21:37.506125 DQS0 = 0, DQS1 = 0
2028 13:21:37.506208 DQM Delay:
2029 13:21:37.509235 DQM0 = 92, DQM1 = 83
2030 13:21:37.509344 DQ Delay:
2031 13:21:37.512932 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2032 13:21:37.515875 DQ4 =92, DQ5 =108, DQ6 =96, DQ7 =88
2033 13:21:37.519353 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =80
2034 13:21:37.522596 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =96
2035 13:21:37.522679
2036 13:21:37.522745
2037 13:21:37.529689 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2038 13:21:37.532906 CH1 RK1: MR19=606, MR18=3D12
2039 13:21:37.539400 CH1_RK1: MR19=0x606, MR18=0x3D12, DQSOSC=394, MR23=63, INC=95, DEC=63
2040 13:21:37.542611 [RxdqsGatingPostProcess] freq 800
2041 13:21:37.545962 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2042 13:21:37.549331 Pre-setting of DQS Precalculation
2043 13:21:37.556124 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2044 13:21:37.562835 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2045 13:21:37.569410 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2046 13:21:37.569495
2047 13:21:37.569562
2048 13:21:37.572938 [Calibration Summary] 1600 Mbps
2049 13:21:37.573052 CH 0, Rank 0
2050 13:21:37.576497 SW Impedance : PASS
2051 13:21:37.579310 DUTY Scan : NO K
2052 13:21:37.579394 ZQ Calibration : PASS
2053 13:21:37.583134 Jitter Meter : NO K
2054 13:21:37.586227 CBT Training : PASS
2055 13:21:37.586357 Write leveling : PASS
2056 13:21:37.589426 RX DQS gating : PASS
2057 13:21:37.592954 RX DQ/DQS(RDDQC) : PASS
2058 13:21:37.593078 TX DQ/DQS : PASS
2059 13:21:37.596030 RX DATLAT : PASS
2060 13:21:37.599315 RX DQ/DQS(Engine): PASS
2061 13:21:37.599440 TX OE : NO K
2062 13:21:37.602790 All Pass.
2063 13:21:37.602914
2064 13:21:37.603025 CH 0, Rank 1
2065 13:21:37.606171 SW Impedance : PASS
2066 13:21:37.606293 DUTY Scan : NO K
2067 13:21:37.609340 ZQ Calibration : PASS
2068 13:21:37.612590 Jitter Meter : NO K
2069 13:21:37.612714 CBT Training : PASS
2070 13:21:37.616154 Write leveling : PASS
2071 13:21:37.616274 RX DQS gating : PASS
2072 13:21:37.619449 RX DQ/DQS(RDDQC) : PASS
2073 13:21:37.622964 TX DQ/DQS : PASS
2074 13:21:37.623088 RX DATLAT : PASS
2075 13:21:37.626439 RX DQ/DQS(Engine): PASS
2076 13:21:37.629812 TX OE : NO K
2077 13:21:37.629936 All Pass.
2078 13:21:37.630052
2079 13:21:37.630164 CH 1, Rank 0
2080 13:21:37.632789 SW Impedance : PASS
2081 13:21:37.636182 DUTY Scan : NO K
2082 13:21:37.636306 ZQ Calibration : PASS
2083 13:21:37.639370 Jitter Meter : NO K
2084 13:21:37.642765 CBT Training : PASS
2085 13:21:37.642867 Write leveling : PASS
2086 13:21:37.645963 RX DQS gating : PASS
2087 13:21:37.649395 RX DQ/DQS(RDDQC) : PASS
2088 13:21:37.649494 TX DQ/DQS : PASS
2089 13:21:37.652664 RX DATLAT : PASS
2090 13:21:37.652756 RX DQ/DQS(Engine): PASS
2091 13:21:37.655981 TX OE : NO K
2092 13:21:37.656099 All Pass.
2093 13:21:37.656198
2094 13:21:37.659410 CH 1, Rank 1
2095 13:21:37.659523 SW Impedance : PASS
2096 13:21:37.662835 DUTY Scan : NO K
2097 13:21:37.666344 ZQ Calibration : PASS
2098 13:21:37.666459 Jitter Meter : NO K
2099 13:21:37.669545 CBT Training : PASS
2100 13:21:37.672992 Write leveling : PASS
2101 13:21:37.673108 RX DQS gating : PASS
2102 13:21:37.676512 RX DQ/DQS(RDDQC) : PASS
2103 13:21:37.679493 TX DQ/DQS : PASS
2104 13:21:37.679604 RX DATLAT : PASS
2105 13:21:37.683067 RX DQ/DQS(Engine): PASS
2106 13:21:37.686190 TX OE : NO K
2107 13:21:37.686285 All Pass.
2108 13:21:37.686383
2109 13:21:37.686486 DramC Write-DBI off
2110 13:21:37.689638 PER_BANK_REFRESH: Hybrid Mode
2111 13:21:37.693010 TX_TRACKING: ON
2112 13:21:37.696498 [GetDramInforAfterCalByMRR] Vendor 6.
2113 13:21:37.699721 [GetDramInforAfterCalByMRR] Revision 606.
2114 13:21:37.703131 [GetDramInforAfterCalByMRR] Revision 2 0.
2115 13:21:37.703210 MR0 0x3b3b
2116 13:21:37.703275 MR8 0x5151
2117 13:21:37.709734 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2118 13:21:37.709813
2119 13:21:37.709882 MR0 0x3b3b
2120 13:21:37.709943 MR8 0x5151
2121 13:21:37.713217 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2122 13:21:37.713292
2123 13:21:37.723010 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2124 13:21:37.726776 [FAST_K] Save calibration result to emmc
2125 13:21:37.729593 [FAST_K] Save calibration result to emmc
2126 13:21:37.733226 dram_init: config_dvfs: 1
2127 13:21:37.736376 dramc_set_vcore_voltage set vcore to 662500
2128 13:21:37.739604 Read voltage for 1200, 2
2129 13:21:37.739733 Vio18 = 0
2130 13:21:37.743125 Vcore = 662500
2131 13:21:37.743236 Vdram = 0
2132 13:21:37.743332 Vddq = 0
2133 13:21:37.743424 Vmddr = 0
2134 13:21:37.749712 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2135 13:21:37.752951 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2136 13:21:37.756312 MEM_TYPE=3, freq_sel=15
2137 13:21:37.759652 sv_algorithm_assistance_LP4_1600
2138 13:21:37.763074 ============ PULL DRAM RESETB DOWN ============
2139 13:21:37.769497 ========== PULL DRAM RESETB DOWN end =========
2140 13:21:37.773084 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2141 13:21:37.776324 ===================================
2142 13:21:37.779791 LPDDR4 DRAM CONFIGURATION
2143 13:21:37.782890 ===================================
2144 13:21:37.782977 EX_ROW_EN[0] = 0x0
2145 13:21:37.786354 EX_ROW_EN[1] = 0x0
2146 13:21:37.786441 LP4Y_EN = 0x0
2147 13:21:37.789749 WORK_FSP = 0x0
2148 13:21:37.789835 WL = 0x4
2149 13:21:37.793236 RL = 0x4
2150 13:21:37.793322 BL = 0x2
2151 13:21:37.796283 RPST = 0x0
2152 13:21:37.796401 RD_PRE = 0x0
2153 13:21:37.799806 WR_PRE = 0x1
2154 13:21:37.799918 WR_PST = 0x0
2155 13:21:37.803259 DBI_WR = 0x0
2156 13:21:37.803364 DBI_RD = 0x0
2157 13:21:37.806382 OTF = 0x1
2158 13:21:37.809745 ===================================
2159 13:21:37.813171 ===================================
2160 13:21:37.813280 ANA top config
2161 13:21:37.816422 ===================================
2162 13:21:37.819515 DLL_ASYNC_EN = 0
2163 13:21:37.823204 ALL_SLAVE_EN = 0
2164 13:21:37.826572 NEW_RANK_MODE = 1
2165 13:21:37.826655 DLL_IDLE_MODE = 1
2166 13:21:37.829764 LP45_APHY_COMB_EN = 1
2167 13:21:37.832892 TX_ODT_DIS = 1
2168 13:21:37.836318 NEW_8X_MODE = 1
2169 13:21:37.840025 ===================================
2170 13:21:37.842850 ===================================
2171 13:21:37.846159 data_rate = 2400
2172 13:21:37.846232 CKR = 1
2173 13:21:37.849758 DQ_P2S_RATIO = 8
2174 13:21:37.852808 ===================================
2175 13:21:37.856384 CA_P2S_RATIO = 8
2176 13:21:37.860077 DQ_CA_OPEN = 0
2177 13:21:37.862965 DQ_SEMI_OPEN = 0
2178 13:21:37.866600 CA_SEMI_OPEN = 0
2179 13:21:37.866700 CA_FULL_RATE = 0
2180 13:21:37.870196 DQ_CKDIV4_EN = 0
2181 13:21:37.873600 CA_CKDIV4_EN = 0
2182 13:21:37.876360 CA_PREDIV_EN = 0
2183 13:21:37.879959 PH8_DLY = 17
2184 13:21:37.882940 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2185 13:21:37.883054 DQ_AAMCK_DIV = 4
2186 13:21:37.886285 CA_AAMCK_DIV = 4
2187 13:21:37.889443 CA_ADMCK_DIV = 4
2188 13:21:37.893153 DQ_TRACK_CA_EN = 0
2189 13:21:37.896160 CA_PICK = 1200
2190 13:21:37.899363 CA_MCKIO = 1200
2191 13:21:37.902744 MCKIO_SEMI = 0
2192 13:21:37.902884 PLL_FREQ = 2366
2193 13:21:37.906277 DQ_UI_PI_RATIO = 32
2194 13:21:37.909449 CA_UI_PI_RATIO = 0
2195 13:21:37.912748 ===================================
2196 13:21:37.916711 ===================================
2197 13:21:37.919579 memory_type:LPDDR4
2198 13:21:37.919706 GP_NUM : 10
2199 13:21:37.922693 SRAM_EN : 1
2200 13:21:37.926335 MD32_EN : 0
2201 13:21:37.929740 ===================================
2202 13:21:37.929841 [ANA_INIT] >>>>>>>>>>>>>>
2203 13:21:37.933064 <<<<<< [CONFIGURE PHASE]: ANA_TX
2204 13:21:37.936052 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2205 13:21:37.939678 ===================================
2206 13:21:37.943426 data_rate = 2400,PCW = 0X5b00
2207 13:21:37.946789 ===================================
2208 13:21:37.949494 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2209 13:21:37.956161 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2210 13:21:37.960113 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2211 13:21:37.966724 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2212 13:21:37.969503 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2213 13:21:37.973252 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2214 13:21:37.973377 [ANA_INIT] flow start
2215 13:21:37.976293 [ANA_INIT] PLL >>>>>>>>
2216 13:21:37.979820 [ANA_INIT] PLL <<<<<<<<
2217 13:21:37.979944 [ANA_INIT] MIDPI >>>>>>>>
2218 13:21:37.982934 [ANA_INIT] MIDPI <<<<<<<<
2219 13:21:37.986160 [ANA_INIT] DLL >>>>>>>>
2220 13:21:37.989562 [ANA_INIT] DLL <<<<<<<<
2221 13:21:37.989713 [ANA_INIT] flow end
2222 13:21:37.993283 ============ LP4 DIFF to SE enter ============
2223 13:21:37.999814 ============ LP4 DIFF to SE exit ============
2224 13:21:37.999939 [ANA_INIT] <<<<<<<<<<<<<
2225 13:21:38.003058 [Flow] Enable top DCM control >>>>>
2226 13:21:38.006204 [Flow] Enable top DCM control <<<<<
2227 13:21:38.009849 Enable DLL master slave shuffle
2228 13:21:38.016484 ==============================================================
2229 13:21:38.016569 Gating Mode config
2230 13:21:38.023081 ==============================================================
2231 13:21:38.026351 Config description:
2232 13:21:38.032986 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2233 13:21:38.039665 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2234 13:21:38.046299 SELPH_MODE 0: By rank 1: By Phase
2235 13:21:38.053001 ==============================================================
2236 13:21:38.053078 GAT_TRACK_EN = 1
2237 13:21:38.056299 RX_GATING_MODE = 2
2238 13:21:38.060014 RX_GATING_TRACK_MODE = 2
2239 13:21:38.063374 SELPH_MODE = 1
2240 13:21:38.066330 PICG_EARLY_EN = 1
2241 13:21:38.069582 VALID_LAT_VALUE = 1
2242 13:21:38.076726 ==============================================================
2243 13:21:38.079919 Enter into Gating configuration >>>>
2244 13:21:38.083260 Exit from Gating configuration <<<<
2245 13:21:38.083358 Enter into DVFS_PRE_config >>>>>
2246 13:21:38.096820 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2247 13:21:38.100337 Exit from DVFS_PRE_config <<<<<
2248 13:21:38.103241 Enter into PICG configuration >>>>
2249 13:21:38.106746 Exit from PICG configuration <<<<
2250 13:21:38.106843 [RX_INPUT] configuration >>>>>
2251 13:21:38.109989 [RX_INPUT] configuration <<<<<
2252 13:21:38.116714 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2253 13:21:38.119851 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2254 13:21:38.126784 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2255 13:21:38.133581 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2256 13:21:38.139993 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2257 13:21:38.146818 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2258 13:21:38.149991 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2259 13:21:38.153198 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2260 13:21:38.156687 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2261 13:21:38.163727 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2262 13:21:38.166744 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2263 13:21:38.170006 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2264 13:21:38.173634 ===================================
2265 13:21:38.177004 LPDDR4 DRAM CONFIGURATION
2266 13:21:38.180355 ===================================
2267 13:21:38.183310 EX_ROW_EN[0] = 0x0
2268 13:21:38.183412 EX_ROW_EN[1] = 0x0
2269 13:21:38.187013 LP4Y_EN = 0x0
2270 13:21:38.187098 WORK_FSP = 0x0
2271 13:21:38.189967 WL = 0x4
2272 13:21:38.190052 RL = 0x4
2273 13:21:38.193278 BL = 0x2
2274 13:21:38.193362 RPST = 0x0
2275 13:21:38.196735 RD_PRE = 0x0
2276 13:21:38.196860 WR_PRE = 0x1
2277 13:21:38.200228 WR_PST = 0x0
2278 13:21:38.200312 DBI_WR = 0x0
2279 13:21:38.203357 DBI_RD = 0x0
2280 13:21:38.203458 OTF = 0x1
2281 13:21:38.206904 ===================================
2282 13:21:38.210454 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2283 13:21:38.216815 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2284 13:21:38.219921 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2285 13:21:38.223376 ===================================
2286 13:21:38.226644 LPDDR4 DRAM CONFIGURATION
2287 13:21:38.230161 ===================================
2288 13:21:38.230246 EX_ROW_EN[0] = 0x10
2289 13:21:38.233127 EX_ROW_EN[1] = 0x0
2290 13:21:38.236563 LP4Y_EN = 0x0
2291 13:21:38.236676 WORK_FSP = 0x0
2292 13:21:38.240043 WL = 0x4
2293 13:21:38.240125 RL = 0x4
2294 13:21:38.243474 BL = 0x2
2295 13:21:38.243556 RPST = 0x0
2296 13:21:38.246715 RD_PRE = 0x0
2297 13:21:38.246797 WR_PRE = 0x1
2298 13:21:38.249908 WR_PST = 0x0
2299 13:21:38.249991 DBI_WR = 0x0
2300 13:21:38.253587 DBI_RD = 0x0
2301 13:21:38.253701 OTF = 0x1
2302 13:21:38.256590 ===================================
2303 13:21:38.263402 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2304 13:21:38.263485 ==
2305 13:21:38.266752 Dram Type= 6, Freq= 0, CH_0, rank 0
2306 13:21:38.270107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2307 13:21:38.270193 ==
2308 13:21:38.273583 [Duty_Offset_Calibration]
2309 13:21:38.276895 B0:2 B1:0 CA:1
2310 13:21:38.276985
2311 13:21:38.280249 [DutyScan_Calibration_Flow] k_type=0
2312 13:21:38.287502
2313 13:21:38.287584 ==CLK 0==
2314 13:21:38.290832 Final CLK duty delay cell = -4
2315 13:21:38.293987 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2316 13:21:38.297464 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2317 13:21:38.300551 [-4] AVG Duty = 4953%(X100)
2318 13:21:38.300633
2319 13:21:38.304161 CH0 CLK Duty spec in!! Max-Min= 156%
2320 13:21:38.307434 [DutyScan_Calibration_Flow] ====Done====
2321 13:21:38.307516
2322 13:21:38.310910 [DutyScan_Calibration_Flow] k_type=1
2323 13:21:38.326038
2324 13:21:38.326121 ==DQS 0 ==
2325 13:21:38.329413 Final DQS duty delay cell = 0
2326 13:21:38.332860 [0] MAX Duty = 5187%(X100), DQS PI = 30
2327 13:21:38.336205 [0] MIN Duty = 4938%(X100), DQS PI = 0
2328 13:21:38.336302 [0] AVG Duty = 5062%(X100)
2329 13:21:38.339280
2330 13:21:38.339362 ==DQS 1 ==
2331 13:21:38.342745 Final DQS duty delay cell = -4
2332 13:21:38.345987 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2333 13:21:38.349551 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2334 13:21:38.352647 [-4] AVG Duty = 5015%(X100)
2335 13:21:38.352729
2336 13:21:38.356476 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2337 13:21:38.356589
2338 13:21:38.359679 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2339 13:21:38.362691 [DutyScan_Calibration_Flow] ====Done====
2340 13:21:38.362774
2341 13:21:38.366130 [DutyScan_Calibration_Flow] k_type=3
2342 13:21:38.383139
2343 13:21:38.383224 ==DQM 0 ==
2344 13:21:38.386308 Final DQM duty delay cell = 0
2345 13:21:38.389674 [0] MAX Duty = 5062%(X100), DQS PI = 24
2346 13:21:38.393220 [0] MIN Duty = 4875%(X100), DQS PI = 0
2347 13:21:38.393304 [0] AVG Duty = 4968%(X100)
2348 13:21:38.396261
2349 13:21:38.396345 ==DQM 1 ==
2350 13:21:38.399539 Final DQM duty delay cell = 0
2351 13:21:38.403099 [0] MAX Duty = 5187%(X100), DQS PI = 32
2352 13:21:38.406567 [0] MIN Duty = 5000%(X100), DQS PI = 22
2353 13:21:38.406651 [0] AVG Duty = 5093%(X100)
2354 13:21:38.409982
2355 13:21:38.413463 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2356 13:21:38.413547
2357 13:21:38.416122 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2358 13:21:38.419827 [DutyScan_Calibration_Flow] ====Done====
2359 13:21:38.419911
2360 13:21:38.422919 [DutyScan_Calibration_Flow] k_type=2
2361 13:21:38.438753
2362 13:21:38.438852 ==DQ 0 ==
2363 13:21:38.442580 Final DQ duty delay cell = -4
2364 13:21:38.445344 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2365 13:21:38.448870 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2366 13:21:38.451971 [-4] AVG Duty = 4953%(X100)
2367 13:21:38.452055
2368 13:21:38.452122 ==DQ 1 ==
2369 13:21:38.455483 Final DQ duty delay cell = 0
2370 13:21:38.458561 [0] MAX Duty = 4938%(X100), DQS PI = 6
2371 13:21:38.461951 [0] MIN Duty = 4907%(X100), DQS PI = 0
2372 13:21:38.462035 [0] AVG Duty = 4922%(X100)
2373 13:21:38.462103
2374 13:21:38.465559 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2375 13:21:38.468689
2376 13:21:38.472236 CH0 DQ 1 Duty spec in!! Max-Min= 31%
2377 13:21:38.475766 [DutyScan_Calibration_Flow] ====Done====
2378 13:21:38.475850 ==
2379 13:21:38.478724 Dram Type= 6, Freq= 0, CH_1, rank 0
2380 13:21:38.482069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2381 13:21:38.482154 ==
2382 13:21:38.485397 [Duty_Offset_Calibration]
2383 13:21:38.485474 B0:0 B1:-1 CA:2
2384 13:21:38.485538
2385 13:21:38.488929 [DutyScan_Calibration_Flow] k_type=0
2386 13:21:38.498971
2387 13:21:38.499071 ==CLK 0==
2388 13:21:38.502318 Final CLK duty delay cell = 0
2389 13:21:38.505318 [0] MAX Duty = 5156%(X100), DQS PI = 16
2390 13:21:38.509036 [0] MIN Duty = 4969%(X100), DQS PI = 44
2391 13:21:38.509159 [0] AVG Duty = 5062%(X100)
2392 13:21:38.512143
2393 13:21:38.515424 CH1 CLK Duty spec in!! Max-Min= 187%
2394 13:21:38.518849 [DutyScan_Calibration_Flow] ====Done====
2395 13:21:38.518971
2396 13:21:38.521999 [DutyScan_Calibration_Flow] k_type=1
2397 13:21:38.538178
2398 13:21:38.538262 ==DQS 0 ==
2399 13:21:38.541629 Final DQS duty delay cell = 0
2400 13:21:38.544660 [0] MAX Duty = 5093%(X100), DQS PI = 24
2401 13:21:38.548349 [0] MIN Duty = 4969%(X100), DQS PI = 0
2402 13:21:38.548432 [0] AVG Duty = 5031%(X100)
2403 13:21:38.551594
2404 13:21:38.551677 ==DQS 1 ==
2405 13:21:38.555161 Final DQS duty delay cell = 0
2406 13:21:38.558319 [0] MAX Duty = 5156%(X100), DQS PI = 0
2407 13:21:38.561764 [0] MIN Duty = 4875%(X100), DQS PI = 34
2408 13:21:38.561847 [0] AVG Duty = 5015%(X100)
2409 13:21:38.561914
2410 13:21:38.568370 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2411 13:21:38.568453
2412 13:21:38.572098 CH1 DQS 1 Duty spec in!! Max-Min= 281%
2413 13:21:38.575240 [DutyScan_Calibration_Flow] ====Done====
2414 13:21:38.575323
2415 13:21:38.578712 [DutyScan_Calibration_Flow] k_type=3
2416 13:21:38.595747
2417 13:21:38.595830 ==DQM 0 ==
2418 13:21:38.599131 Final DQM duty delay cell = 4
2419 13:21:38.602121 [4] MAX Duty = 5093%(X100), DQS PI = 20
2420 13:21:38.605842 [4] MIN Duty = 4938%(X100), DQS PI = 46
2421 13:21:38.605925 [4] AVG Duty = 5015%(X100)
2422 13:21:38.609073
2423 13:21:38.609155 ==DQM 1 ==
2424 13:21:38.612265 Final DQM duty delay cell = 0
2425 13:21:38.615684 [0] MAX Duty = 5280%(X100), DQS PI = 60
2426 13:21:38.619374 [0] MIN Duty = 4875%(X100), DQS PI = 36
2427 13:21:38.619457 [0] AVG Duty = 5077%(X100)
2428 13:21:38.623025
2429 13:21:38.625975 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2430 13:21:38.626117
2431 13:21:38.628922 CH1 DQM 1 Duty spec in!! Max-Min= 405%
2432 13:21:38.632324 [DutyScan_Calibration_Flow] ====Done====
2433 13:21:38.632448
2434 13:21:38.635893 [DutyScan_Calibration_Flow] k_type=2
2435 13:21:38.652444
2436 13:21:38.652542 ==DQ 0 ==
2437 13:21:38.655463 Final DQ duty delay cell = 0
2438 13:21:38.658921 [0] MAX Duty = 5062%(X100), DQS PI = 22
2439 13:21:38.662503 [0] MIN Duty = 4938%(X100), DQS PI = 46
2440 13:21:38.662586 [0] AVG Duty = 5000%(X100)
2441 13:21:38.662652
2442 13:21:38.665507 ==DQ 1 ==
2443 13:21:38.668686 Final DQ duty delay cell = 0
2444 13:21:38.672577 [0] MAX Duty = 5031%(X100), DQS PI = 2
2445 13:21:38.675409 [0] MIN Duty = 4813%(X100), DQS PI = 36
2446 13:21:38.675507 [0] AVG Duty = 4922%(X100)
2447 13:21:38.675576
2448 13:21:38.678997 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2449 13:21:38.679071
2450 13:21:38.681961 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2451 13:21:38.689013 [DutyScan_Calibration_Flow] ====Done====
2452 13:21:38.692258 nWR fixed to 30
2453 13:21:38.692339 [ModeRegInit_LP4] CH0 RK0
2454 13:21:38.695326 [ModeRegInit_LP4] CH0 RK1
2455 13:21:38.698994 [ModeRegInit_LP4] CH1 RK0
2456 13:21:38.699080 [ModeRegInit_LP4] CH1 RK1
2457 13:21:38.702385 match AC timing 7
2458 13:21:38.705367 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2459 13:21:38.708877 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2460 13:21:38.715560 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2461 13:21:38.718759 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2462 13:21:38.725979 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2463 13:21:38.726065 ==
2464 13:21:38.728646 Dram Type= 6, Freq= 0, CH_0, rank 0
2465 13:21:38.732459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2466 13:21:38.732549 ==
2467 13:21:38.738863 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2468 13:21:38.742149 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2469 13:21:38.751864 [CA 0] Center 38 (8~69) winsize 62
2470 13:21:38.754907 [CA 1] Center 38 (8~69) winsize 62
2471 13:21:38.758695 [CA 2] Center 35 (5~66) winsize 62
2472 13:21:38.761965 [CA 3] Center 35 (4~66) winsize 63
2473 13:21:38.765292 [CA 4] Center 34 (4~65) winsize 62
2474 13:21:38.768638 [CA 5] Center 33 (3~64) winsize 62
2475 13:21:38.768748
2476 13:21:38.772060 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2477 13:21:38.772146
2478 13:21:38.775167 [CATrainingPosCal] consider 1 rank data
2479 13:21:38.778669 u2DelayCellTimex100 = 270/100 ps
2480 13:21:38.782162 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2481 13:21:38.785270 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2482 13:21:38.791922 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2483 13:21:38.795428 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2484 13:21:38.799080 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2485 13:21:38.801845 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2486 13:21:38.801969
2487 13:21:38.805914 CA PerBit enable=1, Macro0, CA PI delay=33
2488 13:21:38.806037
2489 13:21:38.808542 [CBTSetCACLKResult] CA Dly = 33
2490 13:21:38.808665 CS Dly: 6 (0~37)
2491 13:21:38.808815 ==
2492 13:21:38.812262 Dram Type= 6, Freq= 0, CH_0, rank 1
2493 13:21:38.818622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2494 13:21:38.818745 ==
2495 13:21:38.821753 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2496 13:21:38.828651 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2497 13:21:38.838075 [CA 0] Center 39 (8~70) winsize 63
2498 13:21:38.841304 [CA 1] Center 38 (8~69) winsize 62
2499 13:21:38.844358 [CA 2] Center 35 (5~66) winsize 62
2500 13:21:38.847452 [CA 3] Center 35 (5~66) winsize 62
2501 13:21:38.851052 [CA 4] Center 34 (4~65) winsize 62
2502 13:21:38.854351 [CA 5] Center 34 (4~64) winsize 61
2503 13:21:38.854451
2504 13:21:38.857665 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2505 13:21:38.857748
2506 13:21:38.861536 [CATrainingPosCal] consider 2 rank data
2507 13:21:38.864434 u2DelayCellTimex100 = 270/100 ps
2508 13:21:38.867800 CA0 delay=38 (8~69),Diff = 4 PI (19 cell)
2509 13:21:38.871051 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
2510 13:21:38.874405 CA2 delay=35 (5~66),Diff = 1 PI (4 cell)
2511 13:21:38.880994 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2512 13:21:38.884961 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2513 13:21:38.888016 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2514 13:21:38.888085
2515 13:21:38.891337 CA PerBit enable=1, Macro0, CA PI delay=34
2516 13:21:38.891406
2517 13:21:38.894871 [CBTSetCACLKResult] CA Dly = 34
2518 13:21:38.894941 CS Dly: 7 (0~39)
2519 13:21:38.895003
2520 13:21:38.897835 ----->DramcWriteLeveling(PI) begin...
2521 13:21:38.897910 ==
2522 13:21:38.901235 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 13:21:38.907952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 13:21:38.908027 ==
2525 13:21:38.911314 Write leveling (Byte 0): 33 => 33
2526 13:21:38.914479 Write leveling (Byte 1): 29 => 29
2527 13:21:38.914550 DramcWriteLeveling(PI) end<-----
2528 13:21:38.914611
2529 13:21:38.918141 ==
2530 13:21:38.921231 Dram Type= 6, Freq= 0, CH_0, rank 0
2531 13:21:38.924759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2532 13:21:38.924843 ==
2533 13:21:38.928386 [Gating] SW mode calibration
2534 13:21:38.934754 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2535 13:21:38.937945 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2536 13:21:38.944616 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2537 13:21:38.947976 0 15 4 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
2538 13:21:38.951698 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 13:21:38.958313 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 13:21:38.961216 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 13:21:38.964902 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 13:21:38.971550 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2543 13:21:38.975062 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2544 13:21:38.978727 1 0 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
2545 13:21:38.981527 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 13:21:38.988215 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 13:21:38.991400 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 13:21:38.995088 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 13:21:39.002027 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 13:21:39.005132 1 0 24 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
2551 13:21:39.008418 1 0 28 | B1->B0 | 2727 4646 | 1 0 | (1 1) (0 0)
2552 13:21:39.014864 1 1 0 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
2553 13:21:39.018253 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2554 13:21:39.021668 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 13:21:39.028109 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 13:21:39.031585 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 13:21:39.035027 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 13:21:39.041535 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 13:21:39.044894 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2560 13:21:39.048490 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2561 13:21:39.054928 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 13:21:39.058404 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 13:21:39.061601 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 13:21:39.064875 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 13:21:39.071714 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 13:21:39.075616 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 13:21:39.078545 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 13:21:39.085096 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 13:21:39.088447 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 13:21:39.092017 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 13:21:39.098571 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 13:21:39.102077 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 13:21:39.105402 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 13:21:39.111958 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2575 13:21:39.115629 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2576 13:21:39.119093 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2577 13:21:39.122121 Total UI for P1: 0, mck2ui 16
2578 13:21:39.126128 best dqsien dly found for B0: ( 1, 3, 26)
2579 13:21:39.128709 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 13:21:39.132163 Total UI for P1: 0, mck2ui 16
2581 13:21:39.135507 best dqsien dly found for B1: ( 1, 4, 0)
2582 13:21:39.138739 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2583 13:21:39.142789 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2584 13:21:39.142890
2585 13:21:39.148989 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2586 13:21:39.152236 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2587 13:21:39.152321 [Gating] SW calibration Done
2588 13:21:39.155479 ==
2589 13:21:39.158948 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 13:21:39.162704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2591 13:21:39.162789 ==
2592 13:21:39.162856 RX Vref Scan: 0
2593 13:21:39.162937
2594 13:21:39.165854 RX Vref 0 -> 0, step: 1
2595 13:21:39.165938
2596 13:21:39.168898 RX Delay -40 -> 252, step: 8
2597 13:21:39.172649 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2598 13:21:39.176102 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2599 13:21:39.179357 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2600 13:21:39.185547 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2601 13:21:39.189014 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2602 13:21:39.192824 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2603 13:21:39.195889 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2604 13:21:39.199215 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2605 13:21:39.205897 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2606 13:21:39.208998 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2607 13:21:39.212612 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2608 13:21:39.216077 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2609 13:21:39.219555 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2610 13:21:39.226170 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2611 13:21:39.229110 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2612 13:21:39.232467 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2613 13:21:39.232590 ==
2614 13:21:39.235755 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 13:21:39.239207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 13:21:39.239330 ==
2617 13:21:39.242784 DQS Delay:
2618 13:21:39.242904 DQS0 = 0, DQS1 = 0
2619 13:21:39.243017 DQM Delay:
2620 13:21:39.246013 DQM0 = 123, DQM1 = 110
2621 13:21:39.246134 DQ Delay:
2622 13:21:39.249510 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2623 13:21:39.252608 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2624 13:21:39.256464 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2625 13:21:39.262744 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2626 13:21:39.262821
2627 13:21:39.262889
2628 13:21:39.262951 ==
2629 13:21:39.266595 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 13:21:39.269200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 13:21:39.269327 ==
2632 13:21:39.269422
2633 13:21:39.269513
2634 13:21:39.273122 TX Vref Scan disable
2635 13:21:39.273225 == TX Byte 0 ==
2636 13:21:39.279675 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2637 13:21:39.282644 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2638 13:21:39.282728 == TX Byte 1 ==
2639 13:21:39.289367 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2640 13:21:39.292661 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2641 13:21:39.292745 ==
2642 13:21:39.296079 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 13:21:39.299725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 13:21:39.299809 ==
2645 13:21:39.312233 TX Vref=22, minBit 0, minWin=24, winSum=402
2646 13:21:39.315363 TX Vref=24, minBit 4, minWin=24, winSum=409
2647 13:21:39.318687 TX Vref=26, minBit 0, minWin=25, winSum=413
2648 13:21:39.322482 TX Vref=28, minBit 1, minWin=25, winSum=419
2649 13:21:39.325408 TX Vref=30, minBit 4, minWin=25, winSum=420
2650 13:21:39.328891 TX Vref=32, minBit 0, minWin=25, winSum=416
2651 13:21:39.335724 [TxChooseVref] Worse bit 4, Min win 25, Win sum 420, Final Vref 30
2652 13:21:39.335866
2653 13:21:39.338906 Final TX Range 1 Vref 30
2654 13:21:39.339030
2655 13:21:39.339147 ==
2656 13:21:39.342246 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 13:21:39.345636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 13:21:39.345757 ==
2659 13:21:39.345870
2660 13:21:39.345979
2661 13:21:39.348971 TX Vref Scan disable
2662 13:21:39.352520 == TX Byte 0 ==
2663 13:21:39.355791 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2664 13:21:39.358826 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2665 13:21:39.362670 == TX Byte 1 ==
2666 13:21:39.365692 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2667 13:21:39.368852 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2668 13:21:39.368974
2669 13:21:39.372212 [DATLAT]
2670 13:21:39.372340 Freq=1200, CH0 RK0
2671 13:21:39.372452
2672 13:21:39.375642 DATLAT Default: 0xd
2673 13:21:39.375761 0, 0xFFFF, sum = 0
2674 13:21:39.378883 1, 0xFFFF, sum = 0
2675 13:21:39.378991 2, 0xFFFF, sum = 0
2676 13:21:39.382204 3, 0xFFFF, sum = 0
2677 13:21:39.382311 4, 0xFFFF, sum = 0
2678 13:21:39.385681 5, 0xFFFF, sum = 0
2679 13:21:39.385765 6, 0xFFFF, sum = 0
2680 13:21:39.389128 7, 0xFFFF, sum = 0
2681 13:21:39.389213 8, 0xFFFF, sum = 0
2682 13:21:39.392448 9, 0xFFFF, sum = 0
2683 13:21:39.392576 10, 0xFFFF, sum = 0
2684 13:21:39.396183 11, 0xFFFF, sum = 0
2685 13:21:39.396283 12, 0x0, sum = 1
2686 13:21:39.399112 13, 0x0, sum = 2
2687 13:21:39.399197 14, 0x0, sum = 3
2688 13:21:39.402654 15, 0x0, sum = 4
2689 13:21:39.402739 best_step = 13
2690 13:21:39.402805
2691 13:21:39.402866 ==
2692 13:21:39.405903 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 13:21:39.412693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 13:21:39.412839 ==
2695 13:21:39.412907 RX Vref Scan: 1
2696 13:21:39.412969
2697 13:21:39.415836 Set Vref Range= 32 -> 127
2698 13:21:39.415920
2699 13:21:39.419001 RX Vref 32 -> 127, step: 1
2700 13:21:39.419085
2701 13:21:39.419151 RX Delay -13 -> 252, step: 4
2702 13:21:39.422848
2703 13:21:39.422931 Set Vref, RX VrefLevel [Byte0]: 32
2704 13:21:39.425973 [Byte1]: 32
2705 13:21:39.430298
2706 13:21:39.430416 Set Vref, RX VrefLevel [Byte0]: 33
2707 13:21:39.433868 [Byte1]: 33
2708 13:21:39.438170
2709 13:21:39.438254 Set Vref, RX VrefLevel [Byte0]: 34
2710 13:21:39.442041 [Byte1]: 34
2711 13:21:39.446554
2712 13:21:39.446638 Set Vref, RX VrefLevel [Byte0]: 35
2713 13:21:39.453014 [Byte1]: 35
2714 13:21:39.453097
2715 13:21:39.455984 Set Vref, RX VrefLevel [Byte0]: 36
2716 13:21:39.459251 [Byte1]: 36
2717 13:21:39.459334
2718 13:21:39.462534 Set Vref, RX VrefLevel [Byte0]: 37
2719 13:21:39.465733 [Byte1]: 37
2720 13:21:39.469920
2721 13:21:39.470003 Set Vref, RX VrefLevel [Byte0]: 38
2722 13:21:39.473292 [Byte1]: 38
2723 13:21:39.477911
2724 13:21:39.478011 Set Vref, RX VrefLevel [Byte0]: 39
2725 13:21:39.481216 [Byte1]: 39
2726 13:21:39.485576
2727 13:21:39.485699 Set Vref, RX VrefLevel [Byte0]: 40
2728 13:21:39.488927 [Byte1]: 40
2729 13:21:39.493322
2730 13:21:39.493490 Set Vref, RX VrefLevel [Byte0]: 41
2731 13:21:39.496597 [Byte1]: 41
2732 13:21:39.501450
2733 13:21:39.501533 Set Vref, RX VrefLevel [Byte0]: 42
2734 13:21:39.504715 [Byte1]: 42
2735 13:21:39.509095
2736 13:21:39.509178 Set Vref, RX VrefLevel [Byte0]: 43
2737 13:21:39.512699 [Byte1]: 43
2738 13:21:39.517113
2739 13:21:39.517197 Set Vref, RX VrefLevel [Byte0]: 44
2740 13:21:39.520377 [Byte1]: 44
2741 13:21:39.525161
2742 13:21:39.525264 Set Vref, RX VrefLevel [Byte0]: 45
2743 13:21:39.528429 [Byte1]: 45
2744 13:21:39.532958
2745 13:21:39.533041 Set Vref, RX VrefLevel [Byte0]: 46
2746 13:21:39.536466 [Byte1]: 46
2747 13:21:39.540856
2748 13:21:39.540939 Set Vref, RX VrefLevel [Byte0]: 47
2749 13:21:39.544007 [Byte1]: 47
2750 13:21:39.548979
2751 13:21:39.549062 Set Vref, RX VrefLevel [Byte0]: 48
2752 13:21:39.551952 [Byte1]: 48
2753 13:21:39.556571
2754 13:21:39.556655 Set Vref, RX VrefLevel [Byte0]: 49
2755 13:21:39.559682 [Byte1]: 49
2756 13:21:39.564618
2757 13:21:39.564702 Set Vref, RX VrefLevel [Byte0]: 50
2758 13:21:39.567951 [Byte1]: 50
2759 13:21:39.572398
2760 13:21:39.572483 Set Vref, RX VrefLevel [Byte0]: 51
2761 13:21:39.575926 [Byte1]: 51
2762 13:21:39.580261
2763 13:21:39.580345 Set Vref, RX VrefLevel [Byte0]: 52
2764 13:21:39.583582 [Byte1]: 52
2765 13:21:39.588276
2766 13:21:39.588359 Set Vref, RX VrefLevel [Byte0]: 53
2767 13:21:39.591625 [Byte1]: 53
2768 13:21:39.596083
2769 13:21:39.596167 Set Vref, RX VrefLevel [Byte0]: 54
2770 13:21:39.599334 [Byte1]: 54
2771 13:21:39.604072
2772 13:21:39.604156 Set Vref, RX VrefLevel [Byte0]: 55
2773 13:21:39.607187 [Byte1]: 55
2774 13:21:39.611790
2775 13:21:39.611870 Set Vref, RX VrefLevel [Byte0]: 56
2776 13:21:39.614983 [Byte1]: 56
2777 13:21:39.619697
2778 13:21:39.619791 Set Vref, RX VrefLevel [Byte0]: 57
2779 13:21:39.622948 [Byte1]: 57
2780 13:21:39.627642
2781 13:21:39.627717 Set Vref, RX VrefLevel [Byte0]: 58
2782 13:21:39.630913 [Byte1]: 58
2783 13:21:39.635653
2784 13:21:39.635731 Set Vref, RX VrefLevel [Byte0]: 59
2785 13:21:39.639156 [Byte1]: 59
2786 13:21:39.643232
2787 13:21:39.643310 Set Vref, RX VrefLevel [Byte0]: 60
2788 13:21:39.646476 [Byte1]: 60
2789 13:21:39.651317
2790 13:21:39.651400 Set Vref, RX VrefLevel [Byte0]: 61
2791 13:21:39.654632 [Byte1]: 61
2792 13:21:39.659023
2793 13:21:39.659105 Set Vref, RX VrefLevel [Byte0]: 62
2794 13:21:39.662559 [Byte1]: 62
2795 13:21:39.667000
2796 13:21:39.667083 Set Vref, RX VrefLevel [Byte0]: 63
2797 13:21:39.670648 [Byte1]: 63
2798 13:21:39.674795
2799 13:21:39.674878 Set Vref, RX VrefLevel [Byte0]: 64
2800 13:21:39.678128 [Byte1]: 64
2801 13:21:39.682734
2802 13:21:39.682817 Set Vref, RX VrefLevel [Byte0]: 65
2803 13:21:39.686150 [Byte1]: 65
2804 13:21:39.690911
2805 13:21:39.690995 Set Vref, RX VrefLevel [Byte0]: 66
2806 13:21:39.694252 [Byte1]: 66
2807 13:21:39.698849
2808 13:21:39.698945 Set Vref, RX VrefLevel [Byte0]: 67
2809 13:21:39.701911 [Byte1]: 67
2810 13:21:39.706301
2811 13:21:39.706383 Set Vref, RX VrefLevel [Byte0]: 68
2812 13:21:39.709733 [Byte1]: 68
2813 13:21:39.714196
2814 13:21:39.714280 Set Vref, RX VrefLevel [Byte0]: 69
2815 13:21:39.717568 [Byte1]: 69
2816 13:21:39.722364
2817 13:21:39.722448 Set Vref, RX VrefLevel [Byte0]: 70
2818 13:21:39.725664 [Byte1]: 70
2819 13:21:39.730373
2820 13:21:39.730456 Final RX Vref Byte 0 = 59 to rank0
2821 13:21:39.733566 Final RX Vref Byte 1 = 50 to rank0
2822 13:21:39.736702 Final RX Vref Byte 0 = 59 to rank1
2823 13:21:39.739995 Final RX Vref Byte 1 = 50 to rank1==
2824 13:21:39.743690 Dram Type= 6, Freq= 0, CH_0, rank 0
2825 13:21:39.750457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 13:21:39.750541 ==
2827 13:21:39.750607 DQS Delay:
2828 13:21:39.750670 DQS0 = 0, DQS1 = 0
2829 13:21:39.754085 DQM Delay:
2830 13:21:39.754168 DQM0 = 123, DQM1 = 109
2831 13:21:39.757172 DQ Delay:
2832 13:21:39.760698 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2833 13:21:39.763381 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2834 13:21:39.766990 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =108
2835 13:21:39.770255 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =118
2836 13:21:39.770338
2837 13:21:39.770404
2838 13:21:39.777289 [DQSOSCAuto] RK0, (LSB)MR18= 0x805, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
2839 13:21:39.780692 CH0 RK0: MR19=404, MR18=805
2840 13:21:39.787022 CH0_RK0: MR19=0x404, MR18=0x805, DQSOSC=406, MR23=63, INC=39, DEC=26
2841 13:21:39.787106
2842 13:21:39.790228 ----->DramcWriteLeveling(PI) begin...
2843 13:21:39.790357 ==
2844 13:21:39.793823 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 13:21:39.797084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 13:21:39.797208 ==
2847 13:21:39.800919 Write leveling (Byte 0): 35 => 35
2848 13:21:39.803719 Write leveling (Byte 1): 32 => 32
2849 13:21:39.807034 DramcWriteLeveling(PI) end<-----
2850 13:21:39.807157
2851 13:21:39.807265 ==
2852 13:21:39.810460 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 13:21:39.813798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 13:21:39.817024 ==
2855 13:21:39.817169 [Gating] SW mode calibration
2856 13:21:39.823930 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2857 13:21:39.830319 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2858 13:21:39.833859 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2859 13:21:39.840617 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 13:21:39.843898 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 13:21:39.847437 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 13:21:39.853891 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 13:21:39.857118 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 13:21:39.860920 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 13:21:39.867200 0 15 28 | B1->B0 | 2e2e 2d2d | 1 1 | (1 1) (1 0)
2866 13:21:39.870392 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2867 13:21:39.873854 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 13:21:39.877471 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 13:21:39.884009 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 13:21:39.887389 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 13:21:39.890848 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 13:21:39.897477 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2873 13:21:39.900639 1 0 28 | B1->B0 | 3838 3d3d | 0 0 | (0 0) (1 1)
2874 13:21:39.903886 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 13:21:39.910721 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 13:21:39.914041 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 13:21:39.917461 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 13:21:39.924576 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 13:21:39.927504 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 13:21:39.930962 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 13:21:39.937347 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2882 13:21:39.940886 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 13:21:39.944427 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 13:21:39.947981 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 13:21:39.954546 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 13:21:39.957592 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 13:21:39.960776 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 13:21:39.967848 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 13:21:39.971277 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 13:21:39.974638 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 13:21:39.981299 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 13:21:39.984339 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 13:21:39.987982 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 13:21:39.994845 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 13:21:39.997764 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 13:21:40.001087 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2897 13:21:40.004563 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2898 13:21:40.011113 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 13:21:40.014456 Total UI for P1: 0, mck2ui 16
2900 13:21:40.017955 best dqsien dly found for B0: ( 1, 3, 26)
2901 13:21:40.021217 Total UI for P1: 0, mck2ui 16
2902 13:21:40.024570 best dqsien dly found for B1: ( 1, 3, 30)
2903 13:21:40.027981 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2904 13:21:40.031632 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2905 13:21:40.031715
2906 13:21:40.034519 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2907 13:21:40.037818 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2908 13:21:40.041293 [Gating] SW calibration Done
2909 13:21:40.041376 ==
2910 13:21:40.044820 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 13:21:40.047857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 13:21:40.047932 ==
2913 13:21:40.051433 RX Vref Scan: 0
2914 13:21:40.051506
2915 13:21:40.051576 RX Vref 0 -> 0, step: 1
2916 13:21:40.051636
2917 13:21:40.054511 RX Delay -40 -> 252, step: 8
2918 13:21:40.058177 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2919 13:21:40.064596 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2920 13:21:40.067857 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2921 13:21:40.071297 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2922 13:21:40.074639 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2923 13:21:40.077848 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2924 13:21:40.084484 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2925 13:21:40.087974 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2926 13:21:40.091660 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2927 13:21:40.094323 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2928 13:21:40.097946 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2929 13:21:40.104506 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2930 13:21:40.107902 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2931 13:21:40.111178 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2932 13:21:40.114408 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2933 13:21:40.117780 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2934 13:21:40.121340 ==
2935 13:21:40.124879 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 13:21:40.128531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 13:21:40.128615 ==
2938 13:21:40.128682 DQS Delay:
2939 13:21:40.131077 DQS0 = 0, DQS1 = 0
2940 13:21:40.131160 DQM Delay:
2941 13:21:40.134524 DQM0 = 120, DQM1 = 108
2942 13:21:40.134609 DQ Delay:
2943 13:21:40.137900 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2944 13:21:40.141003 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2945 13:21:40.144501 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2946 13:21:40.148207 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2947 13:21:40.148332
2948 13:21:40.148446
2949 13:21:40.148558 ==
2950 13:21:40.151463 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 13:21:40.157724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 13:21:40.157810 ==
2953 13:21:40.157878
2954 13:21:40.157940
2955 13:21:40.158005 TX Vref Scan disable
2956 13:21:40.161123 == TX Byte 0 ==
2957 13:21:40.164886 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2958 13:21:40.167909 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2959 13:21:40.171353 == TX Byte 1 ==
2960 13:21:40.174661 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2961 13:21:40.181228 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2962 13:21:40.181313 ==
2963 13:21:40.184610 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 13:21:40.187707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 13:21:40.187792 ==
2966 13:21:40.199587 TX Vref=22, minBit 5, minWin=24, winSum=406
2967 13:21:40.202562 TX Vref=24, minBit 1, minWin=24, winSum=409
2968 13:21:40.206496 TX Vref=26, minBit 1, minWin=24, winSum=411
2969 13:21:40.209252 TX Vref=28, minBit 3, minWin=25, winSum=420
2970 13:21:40.212633 TX Vref=30, minBit 3, minWin=24, winSum=417
2971 13:21:40.215794 TX Vref=32, minBit 4, minWin=24, winSum=415
2972 13:21:40.222816 [TxChooseVref] Worse bit 3, Min win 25, Win sum 420, Final Vref 28
2973 13:21:40.222901
2974 13:21:40.225948 Final TX Range 1 Vref 28
2975 13:21:40.226033
2976 13:21:40.226100 ==
2977 13:21:40.229283 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 13:21:40.232897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 13:21:40.232982 ==
2980 13:21:40.233049
2981 13:21:40.233112
2982 13:21:40.235964 TX Vref Scan disable
2983 13:21:40.239579 == TX Byte 0 ==
2984 13:21:40.242945 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2985 13:21:40.245947 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2986 13:21:40.249328 == TX Byte 1 ==
2987 13:21:40.252720 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2988 13:21:40.256035 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2989 13:21:40.256152
2990 13:21:40.259451 [DATLAT]
2991 13:21:40.259535 Freq=1200, CH0 RK1
2992 13:21:40.259603
2993 13:21:40.262888 DATLAT Default: 0xd
2994 13:21:40.262973 0, 0xFFFF, sum = 0
2995 13:21:40.266450 1, 0xFFFF, sum = 0
2996 13:21:40.266536 2, 0xFFFF, sum = 0
2997 13:21:40.269501 3, 0xFFFF, sum = 0
2998 13:21:40.269602 4, 0xFFFF, sum = 0
2999 13:21:40.272965 5, 0xFFFF, sum = 0
3000 13:21:40.273051 6, 0xFFFF, sum = 0
3001 13:21:40.276063 7, 0xFFFF, sum = 0
3002 13:21:40.276149 8, 0xFFFF, sum = 0
3003 13:21:40.279770 9, 0xFFFF, sum = 0
3004 13:21:40.279855 10, 0xFFFF, sum = 0
3005 13:21:40.283061 11, 0xFFFF, sum = 0
3006 13:21:40.283147 12, 0x0, sum = 1
3007 13:21:40.286540 13, 0x0, sum = 2
3008 13:21:40.286626 14, 0x0, sum = 3
3009 13:21:40.290009 15, 0x0, sum = 4
3010 13:21:40.290094 best_step = 13
3011 13:21:40.290162
3012 13:21:40.290283 ==
3013 13:21:40.293195 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 13:21:40.299568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 13:21:40.299653 ==
3016 13:21:40.299721 RX Vref Scan: 0
3017 13:21:40.299784
3018 13:21:40.302870 RX Vref 0 -> 0, step: 1
3019 13:21:40.302983
3020 13:21:40.306234 RX Delay -21 -> 252, step: 4
3021 13:21:40.309536 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3022 13:21:40.313321 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3023 13:21:40.319755 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3024 13:21:40.322947 iDelay=195, Bit 3, Center 116 (51 ~ 182) 132
3025 13:21:40.326665 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3026 13:21:40.329825 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3027 13:21:40.333048 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3028 13:21:40.336540 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3029 13:21:40.343019 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3030 13:21:40.346543 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3031 13:21:40.349802 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3032 13:21:40.353425 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3033 13:21:40.356365 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3034 13:21:40.363380 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3035 13:21:40.366559 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3036 13:21:40.369720 iDelay=195, Bit 15, Center 116 (55 ~ 178) 124
3037 13:21:40.369816 ==
3038 13:21:40.373033 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 13:21:40.376537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 13:21:40.376659 ==
3041 13:21:40.379863 DQS Delay:
3042 13:21:40.379960 DQS0 = 0, DQS1 = 0
3043 13:21:40.383096 DQM Delay:
3044 13:21:40.383192 DQM0 = 120, DQM1 = 108
3045 13:21:40.383282 DQ Delay:
3046 13:21:40.389911 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =116
3047 13:21:40.393311 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =126
3048 13:21:40.396607 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3049 13:21:40.399793 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =116
3050 13:21:40.399877
3051 13:21:40.399943
3052 13:21:40.406608 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3053 13:21:40.409932 CH0 RK1: MR19=403, MR18=11F8
3054 13:21:40.416668 CH0_RK1: MR19=0x403, MR18=0x11F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3055 13:21:40.419776 [RxdqsGatingPostProcess] freq 1200
3056 13:21:40.423174 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3057 13:21:40.426637 best DQS0 dly(2T, 0.5T) = (0, 11)
3058 13:21:40.430037 best DQS1 dly(2T, 0.5T) = (0, 12)
3059 13:21:40.433613 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3060 13:21:40.436817 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3061 13:21:40.440172 best DQS0 dly(2T, 0.5T) = (0, 11)
3062 13:21:40.443454 best DQS1 dly(2T, 0.5T) = (0, 11)
3063 13:21:40.446844 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3064 13:21:40.450339 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3065 13:21:40.454096 Pre-setting of DQS Precalculation
3066 13:21:40.457017 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3067 13:21:40.457101 ==
3068 13:21:40.460426 Dram Type= 6, Freq= 0, CH_1, rank 0
3069 13:21:40.467082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3070 13:21:40.467197 ==
3071 13:21:40.470188 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3072 13:21:40.477398 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3073 13:21:40.485385 [CA 0] Center 37 (7~68) winsize 62
3074 13:21:40.488647 [CA 1] Center 37 (7~68) winsize 62
3075 13:21:40.491955 [CA 2] Center 35 (5~65) winsize 61
3076 13:21:40.495440 [CA 3] Center 34 (4~65) winsize 62
3077 13:21:40.498841 [CA 4] Center 34 (4~64) winsize 61
3078 13:21:40.502093 [CA 5] Center 33 (3~64) winsize 62
3079 13:21:40.502177
3080 13:21:40.505378 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3081 13:21:40.505462
3082 13:21:40.508797 [CATrainingPosCal] consider 1 rank data
3083 13:21:40.512005 u2DelayCellTimex100 = 270/100 ps
3084 13:21:40.515512 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3085 13:21:40.518882 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3086 13:21:40.525318 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3087 13:21:40.528926 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3088 13:21:40.532202 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3089 13:21:40.535926 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3090 13:21:40.535995
3091 13:21:40.538845 CA PerBit enable=1, Macro0, CA PI delay=33
3092 13:21:40.538930
3093 13:21:40.541958 [CBTSetCACLKResult] CA Dly = 33
3094 13:21:40.542040 CS Dly: 5 (0~36)
3095 13:21:40.542105 ==
3096 13:21:40.545339 Dram Type= 6, Freq= 0, CH_1, rank 1
3097 13:21:40.552376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 13:21:40.552464 ==
3099 13:21:40.555617 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3100 13:21:40.561947 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3101 13:21:40.570971 [CA 0] Center 38 (8~68) winsize 61
3102 13:21:40.574628 [CA 1] Center 38 (8~69) winsize 62
3103 13:21:40.577804 [CA 2] Center 35 (5~66) winsize 62
3104 13:21:40.581106 [CA 3] Center 34 (4~65) winsize 62
3105 13:21:40.584228 [CA 4] Center 35 (5~65) winsize 61
3106 13:21:40.587742 [CA 5] Center 34 (4~64) winsize 61
3107 13:21:40.587849
3108 13:21:40.591150 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3109 13:21:40.591232
3110 13:21:40.594619 [CATrainingPosCal] consider 2 rank data
3111 13:21:40.597745 u2DelayCellTimex100 = 270/100 ps
3112 13:21:40.601232 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3113 13:21:40.604601 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3114 13:21:40.611091 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3115 13:21:40.614462 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3116 13:21:40.617779 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3117 13:21:40.621004 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3118 13:21:40.621080
3119 13:21:40.624606 CA PerBit enable=1, Macro0, CA PI delay=34
3120 13:21:40.624688
3121 13:21:40.627874 [CBTSetCACLKResult] CA Dly = 34
3122 13:21:40.627955 CS Dly: 6 (0~39)
3123 13:21:40.628019
3124 13:21:40.631265 ----->DramcWriteLeveling(PI) begin...
3125 13:21:40.631339 ==
3126 13:21:40.634829 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 13:21:40.641119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 13:21:40.641199 ==
3129 13:21:40.644413 Write leveling (Byte 0): 25 => 25
3130 13:21:40.647941 Write leveling (Byte 1): 28 => 28
3131 13:21:40.648017 DramcWriteLeveling(PI) end<-----
3132 13:21:40.648081
3133 13:21:40.651071 ==
3134 13:21:40.654462 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 13:21:40.657986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 13:21:40.658066 ==
3137 13:21:40.661393 [Gating] SW mode calibration
3138 13:21:40.667905 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3139 13:21:40.671112 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3140 13:21:40.677835 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 13:21:40.681070 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 13:21:40.684873 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 13:21:40.691206 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 13:21:40.694741 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 13:21:40.697831 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3146 13:21:40.704457 0 15 24 | B1->B0 | 2b2b 2828 | 0 0 | (0 1) (0 1)
3147 13:21:40.708220 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3148 13:21:40.711353 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 13:21:40.717979 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 13:21:40.721177 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 13:21:40.724503 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 13:21:40.728122 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 13:21:40.734653 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3154 13:21:40.737943 1 0 24 | B1->B0 | 3d3d 4343 | 0 0 | (1 1) (1 1)
3155 13:21:40.741451 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 13:21:40.748122 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 13:21:40.751042 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 13:21:40.754354 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 13:21:40.761197 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 13:21:40.764560 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 13:21:40.768080 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 13:21:40.774427 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3163 13:21:40.777831 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3164 13:21:40.781339 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 13:21:40.787884 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 13:21:40.791181 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 13:21:40.794528 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 13:21:40.801315 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 13:21:40.804628 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 13:21:40.808034 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 13:21:40.814761 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 13:21:40.817903 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 13:21:40.821618 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 13:21:40.824616 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 13:21:40.831496 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 13:21:40.834886 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 13:21:40.838247 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3178 13:21:40.844828 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3179 13:21:40.848377 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 13:21:40.851739 Total UI for P1: 0, mck2ui 16
3181 13:21:40.854702 best dqsien dly found for B0: ( 1, 3, 22)
3182 13:21:40.858247 Total UI for P1: 0, mck2ui 16
3183 13:21:40.861608 best dqsien dly found for B1: ( 1, 3, 24)
3184 13:21:40.864886 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3185 13:21:40.868484 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3186 13:21:40.868596
3187 13:21:40.872101 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3188 13:21:40.874939 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3189 13:21:40.878255 [Gating] SW calibration Done
3190 13:21:40.878341 ==
3191 13:21:40.881576 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 13:21:40.885091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 13:21:40.885178 ==
3194 13:21:40.888588 RX Vref Scan: 0
3195 13:21:40.888709
3196 13:21:40.891737 RX Vref 0 -> 0, step: 1
3197 13:21:40.891823
3198 13:21:40.891892 RX Delay -40 -> 252, step: 8
3199 13:21:40.898640 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3200 13:21:40.901810 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3201 13:21:40.904961 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3202 13:21:40.908447 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3203 13:21:40.911915 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3204 13:21:40.918249 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3205 13:21:40.921563 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3206 13:21:40.925180 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3207 13:21:40.928597 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3208 13:21:40.931905 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3209 13:21:40.938256 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3210 13:21:40.941739 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3211 13:21:40.945165 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3212 13:21:40.948410 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3213 13:21:40.951740 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3214 13:21:40.958435 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3215 13:21:40.958521 ==
3216 13:21:40.962137 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 13:21:40.965322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 13:21:40.965408 ==
3219 13:21:40.965477 DQS Delay:
3220 13:21:40.969104 DQS0 = 0, DQS1 = 0
3221 13:21:40.969190 DQM Delay:
3222 13:21:40.972146 DQM0 = 120, DQM1 = 112
3223 13:21:40.972232 DQ Delay:
3224 13:21:40.975524 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3225 13:21:40.978407 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =123
3226 13:21:40.981756 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3227 13:21:40.985180 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3228 13:21:40.985266
3229 13:21:40.985334
3230 13:21:40.985398 ==
3231 13:21:40.988561 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 13:21:40.995088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 13:21:40.995174 ==
3234 13:21:40.995243
3235 13:21:40.995307
3236 13:21:40.995368 TX Vref Scan disable
3237 13:21:40.998781 == TX Byte 0 ==
3238 13:21:41.002401 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3239 13:21:41.008738 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3240 13:21:41.008833 == TX Byte 1 ==
3241 13:21:41.012103 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3242 13:21:41.015606 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3243 13:21:41.018817 ==
3244 13:21:41.022221 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 13:21:41.025601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 13:21:41.025688 ==
3247 13:21:41.036549 TX Vref=22, minBit 10, minWin=24, winSum=406
3248 13:21:41.040015 TX Vref=24, minBit 11, minWin=24, winSum=409
3249 13:21:41.043697 TX Vref=26, minBit 8, minWin=25, winSum=413
3250 13:21:41.046496 TX Vref=28, minBit 8, minWin=25, winSum=420
3251 13:21:41.050145 TX Vref=30, minBit 1, minWin=26, winSum=425
3252 13:21:41.056595 TX Vref=32, minBit 11, minWin=25, winSum=422
3253 13:21:41.059901 [TxChooseVref] Worse bit 1, Min win 26, Win sum 425, Final Vref 30
3254 13:21:41.060000
3255 13:21:41.063444 Final TX Range 1 Vref 30
3256 13:21:41.063529
3257 13:21:41.063597 ==
3258 13:21:41.066705 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 13:21:41.070087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 13:21:41.070210 ==
3261 13:21:41.073314
3262 13:21:41.073398
3263 13:21:41.073465 TX Vref Scan disable
3264 13:21:41.076459 == TX Byte 0 ==
3265 13:21:41.079818 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3266 13:21:41.083334 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3267 13:21:41.086747 == TX Byte 1 ==
3268 13:21:41.089828 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3269 13:21:41.093303 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3270 13:21:41.097010
3271 13:21:41.097093 [DATLAT]
3272 13:21:41.097160 Freq=1200, CH1 RK0
3273 13:21:41.097223
3274 13:21:41.100174 DATLAT Default: 0xd
3275 13:21:41.100258 0, 0xFFFF, sum = 0
3276 13:21:41.103489 1, 0xFFFF, sum = 0
3277 13:21:41.103576 2, 0xFFFF, sum = 0
3278 13:21:41.106819 3, 0xFFFF, sum = 0
3279 13:21:41.106905 4, 0xFFFF, sum = 0
3280 13:21:41.109859 5, 0xFFFF, sum = 0
3281 13:21:41.109944 6, 0xFFFF, sum = 0
3282 13:21:41.113657 7, 0xFFFF, sum = 0
3283 13:21:41.116600 8, 0xFFFF, sum = 0
3284 13:21:41.116686 9, 0xFFFF, sum = 0
3285 13:21:41.120434 10, 0xFFFF, sum = 0
3286 13:21:41.120533 11, 0xFFFF, sum = 0
3287 13:21:41.123295 12, 0x0, sum = 1
3288 13:21:41.123385 13, 0x0, sum = 2
3289 13:21:41.126647 14, 0x0, sum = 3
3290 13:21:41.126732 15, 0x0, sum = 4
3291 13:21:41.126801 best_step = 13
3292 13:21:41.126866
3293 13:21:41.129995 ==
3294 13:21:41.130078 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 13:21:41.136604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 13:21:41.136688 ==
3297 13:21:41.136777 RX Vref Scan: 1
3298 13:21:41.136856
3299 13:21:41.140030 Set Vref Range= 32 -> 127
3300 13:21:41.140112
3301 13:21:41.143480 RX Vref 32 -> 127, step: 1
3302 13:21:41.143588
3303 13:21:41.146747 RX Delay -13 -> 252, step: 4
3304 13:21:41.146829
3305 13:21:41.149996 Set Vref, RX VrefLevel [Byte0]: 32
3306 13:21:41.153654 [Byte1]: 32
3307 13:21:41.153737
3308 13:21:41.156730 Set Vref, RX VrefLevel [Byte0]: 33
3309 13:21:41.160277 [Byte1]: 33
3310 13:21:41.160359
3311 13:21:41.163869 Set Vref, RX VrefLevel [Byte0]: 34
3312 13:21:41.166999 [Byte1]: 34
3313 13:21:41.170723
3314 13:21:41.170804 Set Vref, RX VrefLevel [Byte0]: 35
3315 13:21:41.174495 [Byte1]: 35
3316 13:21:41.178876
3317 13:21:41.178958 Set Vref, RX VrefLevel [Byte0]: 36
3318 13:21:41.181971 [Byte1]: 36
3319 13:21:41.186690
3320 13:21:41.186787 Set Vref, RX VrefLevel [Byte0]: 37
3321 13:21:41.190014 [Byte1]: 37
3322 13:21:41.194506
3323 13:21:41.194588 Set Vref, RX VrefLevel [Byte0]: 38
3324 13:21:41.197662 [Byte1]: 38
3325 13:21:41.202541
3326 13:21:41.202622 Set Vref, RX VrefLevel [Byte0]: 39
3327 13:21:41.205660 [Byte1]: 39
3328 13:21:41.210211
3329 13:21:41.210292 Set Vref, RX VrefLevel [Byte0]: 40
3330 13:21:41.213632 [Byte1]: 40
3331 13:21:41.218091
3332 13:21:41.218224 Set Vref, RX VrefLevel [Byte0]: 41
3333 13:21:41.221452 [Byte1]: 41
3334 13:21:41.226099
3335 13:21:41.226232 Set Vref, RX VrefLevel [Byte0]: 42
3336 13:21:41.229171 [Byte1]: 42
3337 13:21:41.234298
3338 13:21:41.234404 Set Vref, RX VrefLevel [Byte0]: 43
3339 13:21:41.237325 [Byte1]: 43
3340 13:21:41.241814
3341 13:21:41.241886 Set Vref, RX VrefLevel [Byte0]: 44
3342 13:21:41.245389 [Byte1]: 44
3343 13:21:41.249546
3344 13:21:41.249614 Set Vref, RX VrefLevel [Byte0]: 45
3345 13:21:41.253131 [Byte1]: 45
3346 13:21:41.257810
3347 13:21:41.257881 Set Vref, RX VrefLevel [Byte0]: 46
3348 13:21:41.260884 [Byte1]: 46
3349 13:21:41.265605
3350 13:21:41.265673 Set Vref, RX VrefLevel [Byte0]: 47
3351 13:21:41.268928 [Byte1]: 47
3352 13:21:41.273579
3353 13:21:41.273651 Set Vref, RX VrefLevel [Byte0]: 48
3354 13:21:41.276664 [Byte1]: 48
3355 13:21:41.281054
3356 13:21:41.281130 Set Vref, RX VrefLevel [Byte0]: 49
3357 13:21:41.284442 [Byte1]: 49
3358 13:21:41.289022
3359 13:21:41.289098 Set Vref, RX VrefLevel [Byte0]: 50
3360 13:21:41.292476 [Byte1]: 50
3361 13:21:41.297067
3362 13:21:41.297138 Set Vref, RX VrefLevel [Byte0]: 51
3363 13:21:41.300123 [Byte1]: 51
3364 13:21:41.305029
3365 13:21:41.305133 Set Vref, RX VrefLevel [Byte0]: 52
3366 13:21:41.307903 [Byte1]: 52
3367 13:21:41.312623
3368 13:21:41.312708 Set Vref, RX VrefLevel [Byte0]: 53
3369 13:21:41.315933 [Byte1]: 53
3370 13:21:41.320687
3371 13:21:41.320764 Set Vref, RX VrefLevel [Byte0]: 54
3372 13:21:41.324286 [Byte1]: 54
3373 13:21:41.328538
3374 13:21:41.328607 Set Vref, RX VrefLevel [Byte0]: 55
3375 13:21:41.331875 [Byte1]: 55
3376 13:21:41.336274
3377 13:21:41.336354 Set Vref, RX VrefLevel [Byte0]: 56
3378 13:21:41.339959 [Byte1]: 56
3379 13:21:41.344225
3380 13:21:41.344301 Set Vref, RX VrefLevel [Byte0]: 57
3381 13:21:41.347726 [Byte1]: 57
3382 13:21:41.352136
3383 13:21:41.352208 Set Vref, RX VrefLevel [Byte0]: 58
3384 13:21:41.355389 [Byte1]: 58
3385 13:21:41.360063
3386 13:21:41.360137 Set Vref, RX VrefLevel [Byte0]: 59
3387 13:21:41.363451 [Byte1]: 59
3388 13:21:41.367916
3389 13:21:41.367988 Set Vref, RX VrefLevel [Byte0]: 60
3390 13:21:41.371297 [Byte1]: 60
3391 13:21:41.375873
3392 13:21:41.375950 Set Vref, RX VrefLevel [Byte0]: 61
3393 13:21:41.379499 [Byte1]: 61
3394 13:21:41.383581
3395 13:21:41.383658 Set Vref, RX VrefLevel [Byte0]: 62
3396 13:21:41.386857 [Byte1]: 62
3397 13:21:41.391695
3398 13:21:41.391801 Set Vref, RX VrefLevel [Byte0]: 63
3399 13:21:41.394838 [Byte1]: 63
3400 13:21:41.399291
3401 13:21:41.399414 Set Vref, RX VrefLevel [Byte0]: 64
3402 13:21:41.403015 [Byte1]: 64
3403 13:21:41.407783
3404 13:21:41.407910 Set Vref, RX VrefLevel [Byte0]: 65
3405 13:21:41.410765 [Byte1]: 65
3406 13:21:41.415209
3407 13:21:41.415329 Set Vref, RX VrefLevel [Byte0]: 66
3408 13:21:41.418551 [Byte1]: 66
3409 13:21:41.423148
3410 13:21:41.423269 Set Vref, RX VrefLevel [Byte0]: 67
3411 13:21:41.426567 [Byte1]: 67
3412 13:21:41.430845
3413 13:21:41.434540 Final RX Vref Byte 0 = 53 to rank0
3414 13:21:41.434663 Final RX Vref Byte 1 = 57 to rank0
3415 13:21:41.437574 Final RX Vref Byte 0 = 53 to rank1
3416 13:21:41.440989 Final RX Vref Byte 1 = 57 to rank1==
3417 13:21:41.444338 Dram Type= 6, Freq= 0, CH_1, rank 0
3418 13:21:41.450991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3419 13:21:41.451110 ==
3420 13:21:41.451220 DQS Delay:
3421 13:21:41.451331 DQS0 = 0, DQS1 = 0
3422 13:21:41.454478 DQM Delay:
3423 13:21:41.454595 DQM0 = 119, DQM1 = 113
3424 13:21:41.458218 DQ Delay:
3425 13:21:41.461785 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3426 13:21:41.464646 DQ4 =118, DQ5 =126, DQ6 =130, DQ7 =118
3427 13:21:41.467780 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3428 13:21:41.471230 DQ12 =124, DQ13 =118, DQ14 =120, DQ15 =122
3429 13:21:41.471343
3430 13:21:41.471438
3431 13:21:41.478002 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3432 13:21:41.481330 CH1 RK0: MR19=404, MR18=114
3433 13:21:41.487878 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3434 13:21:41.487961
3435 13:21:41.491370 ----->DramcWriteLeveling(PI) begin...
3436 13:21:41.491454 ==
3437 13:21:41.494711 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 13:21:41.497995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3439 13:21:41.498078 ==
3440 13:21:41.501149 Write leveling (Byte 0): 25 => 25
3441 13:21:41.504776 Write leveling (Byte 1): 30 => 30
3442 13:21:41.507744 DramcWriteLeveling(PI) end<-----
3443 13:21:41.507826
3444 13:21:41.507891 ==
3445 13:21:41.511306 Dram Type= 6, Freq= 0, CH_1, rank 1
3446 13:21:41.518522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 13:21:41.518606 ==
3448 13:21:41.518672 [Gating] SW mode calibration
3449 13:21:41.527722 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3450 13:21:41.531209 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3451 13:21:41.534631 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 13:21:41.541004 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 13:21:41.544332 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 13:21:41.547681 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 13:21:41.554592 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 13:21:41.557766 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 13:21:41.561828 0 15 24 | B1->B0 | 2e2e 3434 | 0 0 | (0 1) (0 1)
3458 13:21:41.567707 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3459 13:21:41.571017 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 13:21:41.574610 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 13:21:41.581159 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 13:21:41.584364 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 13:21:41.587727 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 13:21:41.594644 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 13:21:41.597998 1 0 24 | B1->B0 | 3a3a 2828 | 0 0 | (0 0) (0 0)
3466 13:21:41.601185 1 0 28 | B1->B0 | 4646 3f3f | 0 1 | (0 0) (0 0)
3467 13:21:41.604669 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 13:21:41.611047 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 13:21:41.614473 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 13:21:41.617728 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 13:21:41.624578 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 13:21:41.627783 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 13:21:41.631281 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3474 13:21:41.637897 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3475 13:21:41.641411 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 13:21:41.644722 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 13:21:41.651169 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 13:21:41.655036 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 13:21:41.657670 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 13:21:41.664672 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 13:21:41.667689 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 13:21:41.671325 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 13:21:41.677779 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 13:21:41.681315 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 13:21:41.684731 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 13:21:41.690903 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 13:21:41.694258 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 13:21:41.697591 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 13:21:41.704377 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3490 13:21:41.708187 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3491 13:21:41.710947 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 13:21:41.714052 Total UI for P1: 0, mck2ui 16
3493 13:21:41.717632 best dqsien dly found for B0: ( 1, 3, 26)
3494 13:21:41.721033 Total UI for P1: 0, mck2ui 16
3495 13:21:41.723938 best dqsien dly found for B1: ( 1, 3, 26)
3496 13:21:41.727347 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3497 13:21:41.730701 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3498 13:21:41.730789
3499 13:21:41.734150 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3500 13:21:41.740611 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3501 13:21:41.740730 [Gating] SW calibration Done
3502 13:21:41.740816 ==
3503 13:21:41.744046 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 13:21:41.750531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 13:21:41.750624 ==
3506 13:21:41.750701 RX Vref Scan: 0
3507 13:21:41.750773
3508 13:21:41.753992 RX Vref 0 -> 0, step: 1
3509 13:21:41.754075
3510 13:21:41.757429 RX Delay -40 -> 252, step: 8
3511 13:21:41.761247 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3512 13:21:41.764324 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3513 13:21:41.767238 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3514 13:21:41.774118 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3515 13:21:41.777122 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3516 13:21:41.780444 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3517 13:21:41.783979 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3518 13:21:41.787376 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3519 13:21:41.793885 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3520 13:21:41.797534 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3521 13:21:41.800291 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3522 13:21:41.804068 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3523 13:21:41.807602 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3524 13:21:41.813695 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3525 13:21:41.817018 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3526 13:21:41.820370 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3527 13:21:41.820458 ==
3528 13:21:41.824163 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 13:21:41.827461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 13:21:41.827548 ==
3531 13:21:41.830973 DQS Delay:
3532 13:21:41.831059 DQS0 = 0, DQS1 = 0
3533 13:21:41.831128 DQM Delay:
3534 13:21:41.834179 DQM0 = 120, DQM1 = 112
3535 13:21:41.834265 DQ Delay:
3536 13:21:41.837558 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =123
3537 13:21:41.840622 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3538 13:21:41.843933 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3539 13:21:41.850623 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3540 13:21:41.850728
3541 13:21:41.850823
3542 13:21:41.850915 ==
3543 13:21:41.853974 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 13:21:41.857273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 13:21:41.857359 ==
3546 13:21:41.857427
3547 13:21:41.857490
3548 13:21:41.860699 TX Vref Scan disable
3549 13:21:41.860839 == TX Byte 0 ==
3550 13:21:41.866910 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3551 13:21:41.870493 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3552 13:21:41.870582 == TX Byte 1 ==
3553 13:21:41.877198 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3554 13:21:41.880669 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3555 13:21:41.880765 ==
3556 13:21:41.883612 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 13:21:41.887054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 13:21:41.887161 ==
3559 13:21:41.899988 TX Vref=22, minBit 1, minWin=25, winSum=418
3560 13:21:41.903488 TX Vref=24, minBit 1, minWin=25, winSum=420
3561 13:21:41.906901 TX Vref=26, minBit 3, minWin=25, winSum=427
3562 13:21:41.910157 TX Vref=28, minBit 1, minWin=26, winSum=431
3563 13:21:41.913355 TX Vref=30, minBit 9, minWin=25, winSum=430
3564 13:21:41.916743 TX Vref=32, minBit 1, minWin=26, winSum=429
3565 13:21:41.923478 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 28
3566 13:21:41.923583
3567 13:21:41.926855 Final TX Range 1 Vref 28
3568 13:21:41.926931
3569 13:21:41.926995 ==
3570 13:21:41.930271 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 13:21:41.933303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 13:21:41.933383 ==
3573 13:21:41.936491
3574 13:21:41.936588
3575 13:21:41.936677 TX Vref Scan disable
3576 13:21:41.939978 == TX Byte 0 ==
3577 13:21:41.943272 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3578 13:21:41.946749 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3579 13:21:41.949811 == TX Byte 1 ==
3580 13:21:41.953351 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3581 13:21:41.956757 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3582 13:21:41.959953
3583 13:21:41.960050 [DATLAT]
3584 13:21:41.960143 Freq=1200, CH1 RK1
3585 13:21:41.960232
3586 13:21:41.962951 DATLAT Default: 0xd
3587 13:21:41.963025 0, 0xFFFF, sum = 0
3588 13:21:41.966500 1, 0xFFFF, sum = 0
3589 13:21:41.966570 2, 0xFFFF, sum = 0
3590 13:21:41.969778 3, 0xFFFF, sum = 0
3591 13:21:41.972978 4, 0xFFFF, sum = 0
3592 13:21:41.973053 5, 0xFFFF, sum = 0
3593 13:21:41.976285 6, 0xFFFF, sum = 0
3594 13:21:41.976416 7, 0xFFFF, sum = 0
3595 13:21:41.980258 8, 0xFFFF, sum = 0
3596 13:21:41.980360 9, 0xFFFF, sum = 0
3597 13:21:41.983128 10, 0xFFFF, sum = 0
3598 13:21:41.983234 11, 0xFFFF, sum = 0
3599 13:21:41.986360 12, 0x0, sum = 1
3600 13:21:41.986462 13, 0x0, sum = 2
3601 13:21:41.989657 14, 0x0, sum = 3
3602 13:21:41.989744 15, 0x0, sum = 4
3603 13:21:41.992904 best_step = 13
3604 13:21:41.992987
3605 13:21:41.993053 ==
3606 13:21:41.996140 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 13:21:41.999393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 13:21:41.999481 ==
3609 13:21:41.999548 RX Vref Scan: 0
3610 13:21:42.003081
3611 13:21:42.003168 RX Vref 0 -> 0, step: 1
3612 13:21:42.003236
3613 13:21:42.006306 RX Delay -13 -> 252, step: 4
3614 13:21:42.009643 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3615 13:21:42.016491 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3616 13:21:42.019497 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3617 13:21:42.023010 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3618 13:21:42.026223 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3619 13:21:42.029620 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3620 13:21:42.036037 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3621 13:21:42.039602 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3622 13:21:42.042937 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3623 13:21:42.046368 iDelay=195, Bit 9, Center 104 (39 ~ 170) 132
3624 13:21:42.049688 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3625 13:21:42.056953 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3626 13:21:42.059429 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3627 13:21:42.062797 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3628 13:21:42.066405 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3629 13:21:42.069584 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3630 13:21:42.072799 ==
3631 13:21:42.076306 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 13:21:42.079801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 13:21:42.079886 ==
3634 13:21:42.079953 DQS Delay:
3635 13:21:42.082817 DQS0 = 0, DQS1 = 0
3636 13:21:42.082900 DQM Delay:
3637 13:21:42.086501 DQM0 = 119, DQM1 = 113
3638 13:21:42.086587 DQ Delay:
3639 13:21:42.089585 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3640 13:21:42.092680 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3641 13:21:42.096329 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =108
3642 13:21:42.100424 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =124
3643 13:21:42.100509
3644 13:21:42.100576
3645 13:21:42.109467 [DQSOSCAuto] RK1, (LSB)MR18= 0xaee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3646 13:21:42.109580 CH1 RK1: MR19=403, MR18=AEE
3647 13:21:42.116210 CH1_RK1: MR19=0x403, MR18=0xAEE, DQSOSC=406, MR23=63, INC=39, DEC=26
3648 13:21:42.119477 [RxdqsGatingPostProcess] freq 1200
3649 13:21:42.126040 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3650 13:21:42.129623 best DQS0 dly(2T, 0.5T) = (0, 11)
3651 13:21:42.132993 best DQS1 dly(2T, 0.5T) = (0, 11)
3652 13:21:42.136272 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3653 13:21:42.139498 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3654 13:21:42.142578 best DQS0 dly(2T, 0.5T) = (0, 11)
3655 13:21:42.142652 best DQS1 dly(2T, 0.5T) = (0, 11)
3656 13:21:42.146423 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3657 13:21:42.149366 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3658 13:21:42.152896 Pre-setting of DQS Precalculation
3659 13:21:42.159449 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3660 13:21:42.166073 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3661 13:21:42.172568 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3662 13:21:42.172643
3663 13:21:42.172707
3664 13:21:42.176095 [Calibration Summary] 2400 Mbps
3665 13:21:42.179490 CH 0, Rank 0
3666 13:21:42.179580 SW Impedance : PASS
3667 13:21:42.182698 DUTY Scan : NO K
3668 13:21:42.182800 ZQ Calibration : PASS
3669 13:21:42.186401 Jitter Meter : NO K
3670 13:21:42.189487 CBT Training : PASS
3671 13:21:42.189576 Write leveling : PASS
3672 13:21:42.192944 RX DQS gating : PASS
3673 13:21:42.195895 RX DQ/DQS(RDDQC) : PASS
3674 13:21:42.195976 TX DQ/DQS : PASS
3675 13:21:42.199355 RX DATLAT : PASS
3676 13:21:42.202598 RX DQ/DQS(Engine): PASS
3677 13:21:42.202673 TX OE : NO K
3678 13:21:42.206094 All Pass.
3679 13:21:42.206171
3680 13:21:42.206234 CH 0, Rank 1
3681 13:21:42.209369 SW Impedance : PASS
3682 13:21:42.209469 DUTY Scan : NO K
3683 13:21:42.212619 ZQ Calibration : PASS
3684 13:21:42.215976 Jitter Meter : NO K
3685 13:21:42.216050 CBT Training : PASS
3686 13:21:42.219286 Write leveling : PASS
3687 13:21:42.222631 RX DQS gating : PASS
3688 13:21:42.222715 RX DQ/DQS(RDDQC) : PASS
3689 13:21:42.225922 TX DQ/DQS : PASS
3690 13:21:42.226025 RX DATLAT : PASS
3691 13:21:42.229356 RX DQ/DQS(Engine): PASS
3692 13:21:42.232699 TX OE : NO K
3693 13:21:42.232803 All Pass.
3694 13:21:42.232870
3695 13:21:42.232932 CH 1, Rank 0
3696 13:21:42.235882 SW Impedance : PASS
3697 13:21:42.239510 DUTY Scan : NO K
3698 13:21:42.239593 ZQ Calibration : PASS
3699 13:21:42.242902 Jitter Meter : NO K
3700 13:21:42.245962 CBT Training : PASS
3701 13:21:42.246065 Write leveling : PASS
3702 13:21:42.249598 RX DQS gating : PASS
3703 13:21:42.253024 RX DQ/DQS(RDDQC) : PASS
3704 13:21:42.253107 TX DQ/DQS : PASS
3705 13:21:42.256344 RX DATLAT : PASS
3706 13:21:42.259378 RX DQ/DQS(Engine): PASS
3707 13:21:42.259501 TX OE : NO K
3708 13:21:42.259645 All Pass.
3709 13:21:42.262568
3710 13:21:42.262703 CH 1, Rank 1
3711 13:21:42.265835 SW Impedance : PASS
3712 13:21:42.265958 DUTY Scan : NO K
3713 13:21:42.269091 ZQ Calibration : PASS
3714 13:21:42.272454 Jitter Meter : NO K
3715 13:21:42.272575 CBT Training : PASS
3716 13:21:42.275829 Write leveling : PASS
3717 13:21:42.275973 RX DQS gating : PASS
3718 13:21:42.279316 RX DQ/DQS(RDDQC) : PASS
3719 13:21:42.282554 TX DQ/DQS : PASS
3720 13:21:42.282676 RX DATLAT : PASS
3721 13:21:42.285807 RX DQ/DQS(Engine): PASS
3722 13:21:42.289209 TX OE : NO K
3723 13:21:42.289329 All Pass.
3724 13:21:42.289440
3725 13:21:42.292559 DramC Write-DBI off
3726 13:21:42.292695 PER_BANK_REFRESH: Hybrid Mode
3727 13:21:42.295846 TX_TRACKING: ON
3728 13:21:42.302693 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3729 13:21:42.309197 [FAST_K] Save calibration result to emmc
3730 13:21:42.312732 dramc_set_vcore_voltage set vcore to 650000
3731 13:21:42.312843 Read voltage for 600, 5
3732 13:21:42.316372 Vio18 = 0
3733 13:21:42.316456 Vcore = 650000
3734 13:21:42.316557 Vdram = 0
3735 13:21:42.319321 Vddq = 0
3736 13:21:42.319405 Vmddr = 0
3737 13:21:42.322787 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3738 13:21:42.329590 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3739 13:21:42.332765 MEM_TYPE=3, freq_sel=19
3740 13:21:42.336464 sv_algorithm_assistance_LP4_1600
3741 13:21:42.339703 ============ PULL DRAM RESETB DOWN ============
3742 13:21:42.343033 ========== PULL DRAM RESETB DOWN end =========
3743 13:21:42.345923 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3744 13:21:42.349405 ===================================
3745 13:21:42.352616 LPDDR4 DRAM CONFIGURATION
3746 13:21:42.355636 ===================================
3747 13:21:42.359338 EX_ROW_EN[0] = 0x0
3748 13:21:42.359425 EX_ROW_EN[1] = 0x0
3749 13:21:42.362285 LP4Y_EN = 0x0
3750 13:21:42.362371 WORK_FSP = 0x0
3751 13:21:42.365888 WL = 0x2
3752 13:21:42.365974 RL = 0x2
3753 13:21:42.369136 BL = 0x2
3754 13:21:42.369222 RPST = 0x0
3755 13:21:42.372424 RD_PRE = 0x0
3756 13:21:42.372509 WR_PRE = 0x1
3757 13:21:42.375755 WR_PST = 0x0
3758 13:21:42.379143 DBI_WR = 0x0
3759 13:21:42.379229 DBI_RD = 0x0
3760 13:21:42.382687 OTF = 0x1
3761 13:21:42.386250 ===================================
3762 13:21:42.386337 ===================================
3763 13:21:42.389084 ANA top config
3764 13:21:42.392558 ===================================
3765 13:21:42.396140 DLL_ASYNC_EN = 0
3766 13:21:42.396227 ALL_SLAVE_EN = 1
3767 13:21:42.399343 NEW_RANK_MODE = 1
3768 13:21:42.402379 DLL_IDLE_MODE = 1
3769 13:21:42.405997 LP45_APHY_COMB_EN = 1
3770 13:21:42.409552 TX_ODT_DIS = 1
3771 13:21:42.409639 NEW_8X_MODE = 1
3772 13:21:42.412390 ===================================
3773 13:21:42.415741 ===================================
3774 13:21:42.419370 data_rate = 1200
3775 13:21:42.422607 CKR = 1
3776 13:21:42.426004 DQ_P2S_RATIO = 8
3777 13:21:42.429165 ===================================
3778 13:21:42.432526 CA_P2S_RATIO = 8
3779 13:21:42.432602 DQ_CA_OPEN = 0
3780 13:21:42.435956 DQ_SEMI_OPEN = 0
3781 13:21:42.439266 CA_SEMI_OPEN = 0
3782 13:21:42.442521 CA_FULL_RATE = 0
3783 13:21:42.445808 DQ_CKDIV4_EN = 1
3784 13:21:42.449056 CA_CKDIV4_EN = 1
3785 13:21:42.449128 CA_PREDIV_EN = 0
3786 13:21:42.452675 PH8_DLY = 0
3787 13:21:42.456234 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3788 13:21:42.459022 DQ_AAMCK_DIV = 4
3789 13:21:42.462223 CA_AAMCK_DIV = 4
3790 13:21:42.465558 CA_ADMCK_DIV = 4
3791 13:21:42.465633 DQ_TRACK_CA_EN = 0
3792 13:21:42.469076 CA_PICK = 600
3793 13:21:42.472259 CA_MCKIO = 600
3794 13:21:42.475790 MCKIO_SEMI = 0
3795 13:21:42.479304 PLL_FREQ = 2288
3796 13:21:42.482679 DQ_UI_PI_RATIO = 32
3797 13:21:42.485889 CA_UI_PI_RATIO = 0
3798 13:21:42.489388 ===================================
3799 13:21:42.492396 ===================================
3800 13:21:42.492469 memory_type:LPDDR4
3801 13:21:42.495630 GP_NUM : 10
3802 13:21:42.498949 SRAM_EN : 1
3803 13:21:42.499031 MD32_EN : 0
3804 13:21:42.502237 ===================================
3805 13:21:42.505890 [ANA_INIT] >>>>>>>>>>>>>>
3806 13:21:42.508891 <<<<<< [CONFIGURE PHASE]: ANA_TX
3807 13:21:42.512546 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3808 13:21:42.515834 ===================================
3809 13:21:42.519010 data_rate = 1200,PCW = 0X5800
3810 13:21:42.522269 ===================================
3811 13:21:42.525443 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3812 13:21:42.528761 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3813 13:21:42.535340 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3814 13:21:42.538812 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3815 13:21:42.541913 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3816 13:21:42.545729 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3817 13:21:42.548666 [ANA_INIT] flow start
3818 13:21:42.552052 [ANA_INIT] PLL >>>>>>>>
3819 13:21:42.552158 [ANA_INIT] PLL <<<<<<<<
3820 13:21:42.555756 [ANA_INIT] MIDPI >>>>>>>>
3821 13:21:42.559088 [ANA_INIT] MIDPI <<<<<<<<
3822 13:21:42.559164 [ANA_INIT] DLL >>>>>>>>
3823 13:21:42.562353 [ANA_INIT] flow end
3824 13:21:42.565438 ============ LP4 DIFF to SE enter ============
3825 13:21:42.569140 ============ LP4 DIFF to SE exit ============
3826 13:21:42.572346 [ANA_INIT] <<<<<<<<<<<<<
3827 13:21:42.576060 [Flow] Enable top DCM control >>>>>
3828 13:21:42.578970 [Flow] Enable top DCM control <<<<<
3829 13:21:42.582205 Enable DLL master slave shuffle
3830 13:21:42.589010 ==============================================================
3831 13:21:42.589094 Gating Mode config
3832 13:21:42.595801 ==============================================================
3833 13:21:42.595886 Config description:
3834 13:21:42.605495 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3835 13:21:42.611891 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3836 13:21:42.618562 SELPH_MODE 0: By rank 1: By Phase
3837 13:21:42.625188 ==============================================================
3838 13:21:42.625355 GAT_TRACK_EN = 1
3839 13:21:42.628628 RX_GATING_MODE = 2
3840 13:21:42.632003 RX_GATING_TRACK_MODE = 2
3841 13:21:42.635085 SELPH_MODE = 1
3842 13:21:42.638477 PICG_EARLY_EN = 1
3843 13:21:42.642233 VALID_LAT_VALUE = 1
3844 13:21:42.648510 ==============================================================
3845 13:21:42.651768 Enter into Gating configuration >>>>
3846 13:21:42.655823 Exit from Gating configuration <<<<
3847 13:21:42.658549 Enter into DVFS_PRE_config >>>>>
3848 13:21:42.668283 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3849 13:21:42.671763 Exit from DVFS_PRE_config <<<<<
3850 13:21:42.674956 Enter into PICG configuration >>>>
3851 13:21:42.678869 Exit from PICG configuration <<<<
3852 13:21:42.682108 [RX_INPUT] configuration >>>>>
3853 13:21:42.682230 [RX_INPUT] configuration <<<<<
3854 13:21:42.688359 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3855 13:21:42.694903 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3856 13:21:42.698350 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3857 13:21:42.704767 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3858 13:21:42.711672 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3859 13:21:42.718193 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3860 13:21:42.721573 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3861 13:21:42.725019 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3862 13:21:42.731640 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3863 13:21:42.734898 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3864 13:21:42.738174 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3865 13:21:42.744956 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3866 13:21:42.748119 ===================================
3867 13:21:42.748240 LPDDR4 DRAM CONFIGURATION
3868 13:21:42.751290 ===================================
3869 13:21:42.754658 EX_ROW_EN[0] = 0x0
3870 13:21:42.754838 EX_ROW_EN[1] = 0x0
3871 13:21:42.758146 LP4Y_EN = 0x0
3872 13:21:42.758264 WORK_FSP = 0x0
3873 13:21:42.761737 WL = 0x2
3874 13:21:42.761861 RL = 0x2
3875 13:21:42.764765 BL = 0x2
3876 13:21:42.764930 RPST = 0x0
3877 13:21:42.768015 RD_PRE = 0x0
3878 13:21:42.771365 WR_PRE = 0x1
3879 13:21:42.771485 WR_PST = 0x0
3880 13:21:42.774775 DBI_WR = 0x0
3881 13:21:42.774896 DBI_RD = 0x0
3882 13:21:42.778528 OTF = 0x1
3883 13:21:42.781583 ===================================
3884 13:21:42.784903 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3885 13:21:42.788442 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3886 13:21:42.791473 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3887 13:21:42.794938 ===================================
3888 13:21:42.798300 LPDDR4 DRAM CONFIGURATION
3889 13:21:42.801577 ===================================
3890 13:21:42.804572 EX_ROW_EN[0] = 0x10
3891 13:21:42.804691 EX_ROW_EN[1] = 0x0
3892 13:21:42.807768 LP4Y_EN = 0x0
3893 13:21:42.807889 WORK_FSP = 0x0
3894 13:21:42.811586 WL = 0x2
3895 13:21:42.811706 RL = 0x2
3896 13:21:42.814817 BL = 0x2
3897 13:21:42.814936 RPST = 0x0
3898 13:21:42.818309 RD_PRE = 0x0
3899 13:21:42.818428 WR_PRE = 0x1
3900 13:21:42.821183 WR_PST = 0x0
3901 13:21:42.821304 DBI_WR = 0x0
3902 13:21:42.824923 DBI_RD = 0x0
3903 13:21:42.825043 OTF = 0x1
3904 13:21:42.827820 ===================================
3905 13:21:42.834621 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3906 13:21:42.839555 nWR fixed to 30
3907 13:21:42.842901 [ModeRegInit_LP4] CH0 RK0
3908 13:21:42.843020 [ModeRegInit_LP4] CH0 RK1
3909 13:21:42.846532 [ModeRegInit_LP4] CH1 RK0
3910 13:21:42.849628 [ModeRegInit_LP4] CH1 RK1
3911 13:21:42.849749 match AC timing 17
3912 13:21:42.856555 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3913 13:21:42.859641 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3914 13:21:42.862854 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3915 13:21:42.870120 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3916 13:21:42.873431 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3917 13:21:42.873528 ==
3918 13:21:42.876524 Dram Type= 6, Freq= 0, CH_0, rank 0
3919 13:21:42.879567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3920 13:21:42.879650 ==
3921 13:21:42.886273 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3922 13:21:42.893071 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3923 13:21:42.896055 [CA 0] Center 36 (6~66) winsize 61
3924 13:21:42.899526 [CA 1] Center 36 (6~67) winsize 62
3925 13:21:42.902784 [CA 2] Center 34 (4~65) winsize 62
3926 13:21:42.906198 [CA 3] Center 34 (3~65) winsize 63
3927 13:21:42.909929 [CA 4] Center 33 (3~64) winsize 62
3928 13:21:42.912990 [CA 5] Center 33 (2~64) winsize 63
3929 13:21:42.913073
3930 13:21:42.916506 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3931 13:21:42.916590
3932 13:21:42.919671 [CATrainingPosCal] consider 1 rank data
3933 13:21:42.922636 u2DelayCellTimex100 = 270/100 ps
3934 13:21:42.926357 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3935 13:21:42.929765 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3936 13:21:42.932617 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3937 13:21:42.936587 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3938 13:21:42.939629 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3939 13:21:42.942815 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3940 13:21:42.946078
3941 13:21:42.949411 CA PerBit enable=1, Macro0, CA PI delay=33
3942 13:21:42.949510
3943 13:21:42.952564 [CBTSetCACLKResult] CA Dly = 33
3944 13:21:42.952654 CS Dly: 5 (0~36)
3945 13:21:42.952718 ==
3946 13:21:42.955940 Dram Type= 6, Freq= 0, CH_0, rank 1
3947 13:21:42.959406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3948 13:21:42.959524 ==
3949 13:21:42.966213 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3950 13:21:42.972841 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3951 13:21:42.976316 [CA 0] Center 36 (6~67) winsize 62
3952 13:21:42.979198 [CA 1] Center 36 (6~67) winsize 62
3953 13:21:42.982607 [CA 2] Center 34 (4~65) winsize 62
3954 13:21:42.985969 [CA 3] Center 34 (4~65) winsize 62
3955 13:21:42.989400 [CA 4] Center 34 (3~65) winsize 63
3956 13:21:42.992859 [CA 5] Center 33 (3~64) winsize 62
3957 13:21:42.992942
3958 13:21:42.996172 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3959 13:21:42.996255
3960 13:21:42.999742 [CATrainingPosCal] consider 2 rank data
3961 13:21:43.002590 u2DelayCellTimex100 = 270/100 ps
3962 13:21:43.006057 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3963 13:21:43.009460 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3964 13:21:43.012985 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3965 13:21:43.015854 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3966 13:21:43.019096 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3967 13:21:43.025817 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3968 13:21:43.025902
3969 13:21:43.029071 CA PerBit enable=1, Macro0, CA PI delay=33
3970 13:21:43.029156
3971 13:21:43.032711 [CBTSetCACLKResult] CA Dly = 33
3972 13:21:43.032830 CS Dly: 5 (0~36)
3973 13:21:43.032897
3974 13:21:43.036071 ----->DramcWriteLeveling(PI) begin...
3975 13:21:43.036157 ==
3976 13:21:43.039437 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 13:21:43.042722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 13:21:43.046064 ==
3979 13:21:43.046149 Write leveling (Byte 0): 37 => 37
3980 13:21:43.049397 Write leveling (Byte 1): 29 => 29
3981 13:21:43.052779 DramcWriteLeveling(PI) end<-----
3982 13:21:43.052878
3983 13:21:43.052944 ==
3984 13:21:43.056154 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 13:21:43.062629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 13:21:43.062746 ==
3987 13:21:43.062814 [Gating] SW mode calibration
3988 13:21:43.072622 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3989 13:21:43.076324 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3990 13:21:43.079115 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 13:21:43.086365 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3992 13:21:43.089088 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3993 13:21:43.092646 0 9 12 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 0)
3994 13:21:43.099340 0 9 16 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
3995 13:21:43.102439 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 13:21:43.105888 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 13:21:43.112435 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 13:21:43.115432 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 13:21:43.118993 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 13:21:43.125374 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 13:21:43.129207 0 10 12 | B1->B0 | 2626 3938 | 0 1 | (0 0) (0 0)
4002 13:21:43.132298 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4003 13:21:43.139069 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 13:21:43.142174 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 13:21:43.145793 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 13:21:43.152092 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 13:21:43.155565 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 13:21:43.158988 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 13:21:43.165353 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 13:21:43.168593 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4011 13:21:43.172299 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 13:21:43.179058 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 13:21:43.181803 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 13:21:43.185184 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 13:21:43.191928 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 13:21:43.195008 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 13:21:43.198497 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 13:21:43.205069 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 13:21:43.208109 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 13:21:43.211540 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 13:21:43.218135 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 13:21:43.221517 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 13:21:43.224925 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 13:21:43.231330 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 13:21:43.234577 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4026 13:21:43.238273 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4027 13:21:43.241622 Total UI for P1: 0, mck2ui 16
4028 13:21:43.245080 best dqsien dly found for B0: ( 0, 13, 12)
4029 13:21:43.251262 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 13:21:43.251368 Total UI for P1: 0, mck2ui 16
4031 13:21:43.258143 best dqsien dly found for B1: ( 0, 13, 14)
4032 13:21:43.261176 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4033 13:21:43.264715 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4034 13:21:43.264836
4035 13:21:43.268085 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4036 13:21:43.271221 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4037 13:21:43.275045 [Gating] SW calibration Done
4038 13:21:43.275150 ==
4039 13:21:43.278260 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 13:21:43.281524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 13:21:43.281600 ==
4042 13:21:43.284658 RX Vref Scan: 0
4043 13:21:43.284797
4044 13:21:43.284891 RX Vref 0 -> 0, step: 1
4045 13:21:43.284990
4046 13:21:43.288322 RX Delay -230 -> 252, step: 16
4047 13:21:43.291184 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4048 13:21:43.297929 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4049 13:21:43.301256 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4050 13:21:43.304871 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4051 13:21:43.307795 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4052 13:21:43.314620 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4053 13:21:43.317997 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4054 13:21:43.321144 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4055 13:21:43.324645 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4056 13:21:43.327850 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4057 13:21:43.334753 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4058 13:21:43.338018 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4059 13:21:43.341397 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4060 13:21:43.344883 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4061 13:21:43.351472 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4062 13:21:43.354836 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4063 13:21:43.354956 ==
4064 13:21:43.358137 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 13:21:43.361330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 13:21:43.361454 ==
4067 13:21:43.364824 DQS Delay:
4068 13:21:43.364945 DQS0 = 0, DQS1 = 0
4069 13:21:43.365058 DQM Delay:
4070 13:21:43.367856 DQM0 = 53, DQM1 = 43
4071 13:21:43.367976 DQ Delay:
4072 13:21:43.371139 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4073 13:21:43.374850 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4074 13:21:43.377852 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4075 13:21:43.381412 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4076 13:21:43.381535
4077 13:21:43.381648
4078 13:21:43.381758 ==
4079 13:21:43.384692 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 13:21:43.391070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 13:21:43.391194 ==
4082 13:21:43.391308
4083 13:21:43.391419
4084 13:21:43.391531 TX Vref Scan disable
4085 13:21:43.394726 == TX Byte 0 ==
4086 13:21:43.398233 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4087 13:21:43.404724 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4088 13:21:43.404866 == TX Byte 1 ==
4089 13:21:43.407939 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4090 13:21:43.414613 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4091 13:21:43.414738 ==
4092 13:21:43.418133 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 13:21:43.421484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 13:21:43.421603 ==
4095 13:21:43.421718
4096 13:21:43.421828
4097 13:21:43.425122 TX Vref Scan disable
4098 13:21:43.428034 == TX Byte 0 ==
4099 13:21:43.431591 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4100 13:21:43.435090 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4101 13:21:43.438039 == TX Byte 1 ==
4102 13:21:43.441486 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4103 13:21:43.444639 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4104 13:21:43.444717
4105 13:21:43.444829 [DATLAT]
4106 13:21:43.448139 Freq=600, CH0 RK0
4107 13:21:43.448233
4108 13:21:43.448316 DATLAT Default: 0x9
4109 13:21:43.451781 0, 0xFFFF, sum = 0
4110 13:21:43.451909 1, 0xFFFF, sum = 0
4111 13:21:43.455070 2, 0xFFFF, sum = 0
4112 13:21:43.458193 3, 0xFFFF, sum = 0
4113 13:21:43.458291 4, 0xFFFF, sum = 0
4114 13:21:43.461404 5, 0xFFFF, sum = 0
4115 13:21:43.461501 6, 0xFFFF, sum = 0
4116 13:21:43.464538 7, 0xFFFF, sum = 0
4117 13:21:43.464638 8, 0x0, sum = 1
4118 13:21:43.467938 9, 0x0, sum = 2
4119 13:21:43.468034 10, 0x0, sum = 3
4120 13:21:43.468125 11, 0x0, sum = 4
4121 13:21:43.471293 best_step = 9
4122 13:21:43.471386
4123 13:21:43.471475 ==
4124 13:21:43.474620 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 13:21:43.478205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 13:21:43.478282 ==
4127 13:21:43.481230 RX Vref Scan: 1
4128 13:21:43.481303
4129 13:21:43.481368 RX Vref 0 -> 0, step: 1
4130 13:21:43.481428
4131 13:21:43.484900 RX Delay -163 -> 252, step: 8
4132 13:21:43.484971
4133 13:21:43.487898 Set Vref, RX VrefLevel [Byte0]: 59
4134 13:21:43.491590 [Byte1]: 50
4135 13:21:43.495261
4136 13:21:43.495383 Final RX Vref Byte 0 = 59 to rank0
4137 13:21:43.498763 Final RX Vref Byte 1 = 50 to rank0
4138 13:21:43.501820 Final RX Vref Byte 0 = 59 to rank1
4139 13:21:43.505240 Final RX Vref Byte 1 = 50 to rank1==
4140 13:21:43.508588 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 13:21:43.512042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 13:21:43.515597 ==
4143 13:21:43.515720 DQS Delay:
4144 13:21:43.515831 DQS0 = 0, DQS1 = 0
4145 13:21:43.518726 DQM Delay:
4146 13:21:43.518847 DQM0 = 48, DQM1 = 37
4147 13:21:43.522293 DQ Delay:
4148 13:21:43.525272 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4149 13:21:43.525394 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4150 13:21:43.528780 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4151 13:21:43.532257 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =48
4152 13:21:43.535571
4153 13:21:43.535692
4154 13:21:43.542370 [DQSOSCAuto] RK0, (LSB)MR18= 0x5953, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4155 13:21:43.545370 CH0 RK0: MR19=808, MR18=5953
4156 13:21:43.552258 CH0_RK0: MR19=0x808, MR18=0x5953, DQSOSC=393, MR23=63, INC=169, DEC=113
4157 13:21:43.552382
4158 13:21:43.555040 ----->DramcWriteLeveling(PI) begin...
4159 13:21:43.555159 ==
4160 13:21:43.558279 Dram Type= 6, Freq= 0, CH_0, rank 1
4161 13:21:43.561659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 13:21:43.561742 ==
4163 13:21:43.564913 Write leveling (Byte 0): 34 => 34
4164 13:21:43.568637 Write leveling (Byte 1): 29 => 29
4165 13:21:43.571650 DramcWriteLeveling(PI) end<-----
4166 13:21:43.571745
4167 13:21:43.571835 ==
4168 13:21:43.575038 Dram Type= 6, Freq= 0, CH_0, rank 1
4169 13:21:43.578152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 13:21:43.578251 ==
4171 13:21:43.581481 [Gating] SW mode calibration
4172 13:21:43.588097 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4173 13:21:43.594827 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4174 13:21:43.598080 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 13:21:43.605033 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 13:21:43.607920 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4177 13:21:43.611419 0 9 12 | B1->B0 | 3131 2f2f | 0 0 | (0 1) (0 1)
4178 13:21:43.618129 0 9 16 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4179 13:21:43.621444 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 13:21:43.624784 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 13:21:43.631184 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 13:21:43.634554 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 13:21:43.638482 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 13:21:43.641684 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 13:21:43.647790 0 10 12 | B1->B0 | 3030 3030 | 0 0 | (0 0) (0 0)
4186 13:21:43.651157 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 13:21:43.654783 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 13:21:43.661028 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 13:21:43.664266 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 13:21:43.667731 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 13:21:43.674152 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 13:21:43.677876 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 13:21:43.680976 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4194 13:21:43.687413 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 13:21:43.691225 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 13:21:43.693994 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 13:21:43.700883 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 13:21:43.704524 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 13:21:43.707583 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 13:21:43.714242 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 13:21:43.717417 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 13:21:43.720571 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 13:21:43.727360 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 13:21:43.730630 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 13:21:43.734044 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 13:21:43.740828 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 13:21:43.743826 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 13:21:43.746996 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 13:21:43.753713 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4210 13:21:43.756848 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4211 13:21:43.760250 Total UI for P1: 0, mck2ui 16
4212 13:21:43.763829 best dqsien dly found for B1: ( 0, 13, 12)
4213 13:21:43.766829 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 13:21:43.770389 Total UI for P1: 0, mck2ui 16
4215 13:21:43.774152 best dqsien dly found for B0: ( 0, 13, 14)
4216 13:21:43.776854 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4217 13:21:43.780432 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4218 13:21:43.780518
4219 13:21:43.786774 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4220 13:21:43.790267 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4221 13:21:43.793632 [Gating] SW calibration Done
4222 13:21:43.793748 ==
4223 13:21:43.797088 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 13:21:43.800236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 13:21:43.800323 ==
4226 13:21:43.800389 RX Vref Scan: 0
4227 13:21:43.800453
4228 13:21:43.803320 RX Vref 0 -> 0, step: 1
4229 13:21:43.803406
4230 13:21:43.806694 RX Delay -230 -> 252, step: 16
4231 13:21:43.810000 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4232 13:21:43.813314 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4233 13:21:43.820157 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4234 13:21:43.823208 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4235 13:21:43.826950 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4236 13:21:43.830180 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4237 13:21:43.836857 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4238 13:21:43.839895 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4239 13:21:43.843572 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4240 13:21:43.846903 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4241 13:21:43.850037 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4242 13:21:43.856602 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4243 13:21:43.859879 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4244 13:21:43.863838 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4245 13:21:43.866607 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4246 13:21:43.873203 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4247 13:21:43.873327 ==
4248 13:21:43.876558 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 13:21:43.879859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 13:21:43.879981 ==
4251 13:21:43.880088 DQS Delay:
4252 13:21:43.883018 DQS0 = 0, DQS1 = 0
4253 13:21:43.883137 DQM Delay:
4254 13:21:43.886657 DQM0 = 47, DQM1 = 41
4255 13:21:43.886835 DQ Delay:
4256 13:21:43.889864 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4257 13:21:43.893271 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4258 13:21:43.896552 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4259 13:21:43.899857 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4260 13:21:43.899976
4261 13:21:43.900090
4262 13:21:43.900201 ==
4263 13:21:43.903535 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 13:21:43.906260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 13:21:43.906382 ==
4266 13:21:43.909907
4267 13:21:43.910028
4268 13:21:43.910137 TX Vref Scan disable
4269 13:21:43.913471 == TX Byte 0 ==
4270 13:21:43.916591 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4271 13:21:43.919884 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4272 13:21:43.923003 == TX Byte 1 ==
4273 13:21:43.926386 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4274 13:21:43.929490 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4275 13:21:43.933145 ==
4276 13:21:43.933267 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 13:21:43.939418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 13:21:43.939495 ==
4279 13:21:43.939559
4280 13:21:43.939619
4281 13:21:43.943219 TX Vref Scan disable
4282 13:21:43.943285 == TX Byte 0 ==
4283 13:21:43.949580 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4284 13:21:43.952930 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4285 13:21:43.952999 == TX Byte 1 ==
4286 13:21:43.959885 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4287 13:21:43.963060 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4288 13:21:43.963130
4289 13:21:43.963191 [DATLAT]
4290 13:21:43.966224 Freq=600, CH0 RK1
4291 13:21:43.966312
4292 13:21:43.966374 DATLAT Default: 0x9
4293 13:21:43.969563 0, 0xFFFF, sum = 0
4294 13:21:43.969672 1, 0xFFFF, sum = 0
4295 13:21:43.972918 2, 0xFFFF, sum = 0
4296 13:21:43.972984 3, 0xFFFF, sum = 0
4297 13:21:43.976096 4, 0xFFFF, sum = 0
4298 13:21:43.976160 5, 0xFFFF, sum = 0
4299 13:21:43.979431 6, 0xFFFF, sum = 0
4300 13:21:43.982755 7, 0xFFFF, sum = 0
4301 13:21:43.982837 8, 0x0, sum = 1
4302 13:21:43.982898 9, 0x0, sum = 2
4303 13:21:43.986375 10, 0x0, sum = 3
4304 13:21:43.986439 11, 0x0, sum = 4
4305 13:21:43.989437 best_step = 9
4306 13:21:43.989504
4307 13:21:43.989565 ==
4308 13:21:43.992848 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 13:21:43.996502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 13:21:43.996583 ==
4311 13:21:43.999546 RX Vref Scan: 0
4312 13:21:43.999627
4313 13:21:43.999691 RX Vref 0 -> 0, step: 1
4314 13:21:43.999751
4315 13:21:44.002768 RX Delay -179 -> 252, step: 8
4316 13:21:44.009807 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4317 13:21:44.013530 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4318 13:21:44.016558 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4319 13:21:44.020376 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4320 13:21:44.023346 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4321 13:21:44.029966 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4322 13:21:44.033479 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4323 13:21:44.036632 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4324 13:21:44.040132 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4325 13:21:44.043598 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4326 13:21:44.050006 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4327 13:21:44.053341 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4328 13:21:44.057026 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4329 13:21:44.059906 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4330 13:21:44.066622 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4331 13:21:44.069929 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4332 13:21:44.070011 ==
4333 13:21:44.073743 Dram Type= 6, Freq= 0, CH_0, rank 1
4334 13:21:44.076616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 13:21:44.076722 ==
4336 13:21:44.076858 DQS Delay:
4337 13:21:44.080137 DQS0 = 0, DQS1 = 0
4338 13:21:44.080258 DQM Delay:
4339 13:21:44.083672 DQM0 = 48, DQM1 = 41
4340 13:21:44.083752 DQ Delay:
4341 13:21:44.086880 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4342 13:21:44.090098 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4343 13:21:44.093336 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4344 13:21:44.096620 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =52
4345 13:21:44.096728
4346 13:21:44.096822
4347 13:21:44.106635 [DQSOSCAuto] RK1, (LSB)MR18= 0x6331, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4348 13:21:44.106718 CH0 RK1: MR19=808, MR18=6331
4349 13:21:44.113575 CH0_RK1: MR19=0x808, MR18=0x6331, DQSOSC=391, MR23=63, INC=171, DEC=114
4350 13:21:44.116534 [RxdqsGatingPostProcess] freq 600
4351 13:21:44.123472 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4352 13:21:44.126899 Pre-setting of DQS Precalculation
4353 13:21:44.130067 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4354 13:21:44.130163 ==
4355 13:21:44.133311 Dram Type= 6, Freq= 0, CH_1, rank 0
4356 13:21:44.136430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 13:21:44.139540 ==
4358 13:21:44.142912 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4359 13:21:44.149528 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4360 13:21:44.152800 [CA 0] Center 35 (5~66) winsize 62
4361 13:21:44.156070 [CA 1] Center 35 (5~66) winsize 62
4362 13:21:44.159220 [CA 2] Center 34 (4~65) winsize 62
4363 13:21:44.162663 [CA 3] Center 34 (3~65) winsize 63
4364 13:21:44.166047 [CA 4] Center 34 (3~65) winsize 63
4365 13:21:44.169418 [CA 5] Center 34 (3~65) winsize 63
4366 13:21:44.169538
4367 13:21:44.172740 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4368 13:21:44.172877
4369 13:21:44.175901 [CATrainingPosCal] consider 1 rank data
4370 13:21:44.179010 u2DelayCellTimex100 = 270/100 ps
4371 13:21:44.182548 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4372 13:21:44.186026 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4373 13:21:44.189426 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4374 13:21:44.195864 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4375 13:21:44.199085 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
4376 13:21:44.202555 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4377 13:21:44.202637
4378 13:21:44.205483 CA PerBit enable=1, Macro0, CA PI delay=34
4379 13:21:44.205564
4380 13:21:44.209267 [CBTSetCACLKResult] CA Dly = 34
4381 13:21:44.209347 CS Dly: 4 (0~35)
4382 13:21:44.209412 ==
4383 13:21:44.212265 Dram Type= 6, Freq= 0, CH_1, rank 1
4384 13:21:44.218975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 13:21:44.219058 ==
4386 13:21:44.222199 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4387 13:21:44.228653 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4388 13:21:44.232365 [CA 0] Center 35 (5~66) winsize 62
4389 13:21:44.235783 [CA 1] Center 36 (6~66) winsize 61
4390 13:21:44.238967 [CA 2] Center 34 (4~65) winsize 62
4391 13:21:44.242546 [CA 3] Center 34 (4~65) winsize 62
4392 13:21:44.245446 [CA 4] Center 34 (4~65) winsize 62
4393 13:21:44.249019 [CA 5] Center 34 (4~65) winsize 62
4394 13:21:44.249095
4395 13:21:44.252275 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4396 13:21:44.252375
4397 13:21:44.255609 [CATrainingPosCal] consider 2 rank data
4398 13:21:44.258800 u2DelayCellTimex100 = 270/100 ps
4399 13:21:44.262325 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4400 13:21:44.265575 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4401 13:21:44.272682 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4402 13:21:44.275519 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4403 13:21:44.279088 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4404 13:21:44.282274 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4405 13:21:44.282374
4406 13:21:44.285525 CA PerBit enable=1, Macro0, CA PI delay=34
4407 13:21:44.285598
4408 13:21:44.288797 [CBTSetCACLKResult] CA Dly = 34
4409 13:21:44.288886 CS Dly: 5 (0~37)
4410 13:21:44.288955
4411 13:21:44.292380 ----->DramcWriteLeveling(PI) begin...
4412 13:21:44.295833 ==
4413 13:21:44.298910 Dram Type= 6, Freq= 0, CH_1, rank 0
4414 13:21:44.302410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 13:21:44.302508 ==
4416 13:21:44.305446 Write leveling (Byte 0): 30 => 30
4417 13:21:44.309110 Write leveling (Byte 1): 30 => 30
4418 13:21:44.312039 DramcWriteLeveling(PI) end<-----
4419 13:21:44.312108
4420 13:21:44.312168 ==
4421 13:21:44.315534 Dram Type= 6, Freq= 0, CH_1, rank 0
4422 13:21:44.318847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 13:21:44.318919 ==
4424 13:21:44.322199 [Gating] SW mode calibration
4425 13:21:44.328664 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4426 13:21:44.335358 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4427 13:21:44.338714 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4428 13:21:44.342329 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4429 13:21:44.345568 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4430 13:21:44.352482 0 9 12 | B1->B0 | 2929 2c2c | 0 0 | (1 0) (0 0)
4431 13:21:44.355482 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 13:21:44.358926 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 13:21:44.365309 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 13:21:44.368691 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 13:21:44.372042 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 13:21:44.378693 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 13:21:44.382314 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (1 1)
4438 13:21:44.385235 0 10 12 | B1->B0 | 3a3a 4343 | 0 0 | (1 1) (0 0)
4439 13:21:44.391862 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 13:21:44.395334 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 13:21:44.398862 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 13:21:44.405514 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 13:21:44.408722 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 13:21:44.412362 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 13:21:44.418765 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4446 13:21:44.421918 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4447 13:21:44.425194 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 13:21:44.432122 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 13:21:44.435363 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 13:21:44.438497 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 13:21:44.445227 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 13:21:44.448596 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 13:21:44.452362 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 13:21:44.455182 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 13:21:44.461892 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 13:21:44.465368 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 13:21:44.468347 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 13:21:44.475076 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 13:21:44.478229 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 13:21:44.481749 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 13:21:44.488285 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4462 13:21:44.491705 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4463 13:21:44.494830 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 13:21:44.498248 Total UI for P1: 0, mck2ui 16
4465 13:21:44.501790 best dqsien dly found for B0: ( 0, 13, 10)
4466 13:21:44.505005 Total UI for P1: 0, mck2ui 16
4467 13:21:44.508238 best dqsien dly found for B1: ( 0, 13, 12)
4468 13:21:44.511592 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4469 13:21:44.515152 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4470 13:21:44.515273
4471 13:21:44.521631 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4472 13:21:44.524929 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4473 13:21:44.528475 [Gating] SW calibration Done
4474 13:21:44.528627 ==
4475 13:21:44.531588 Dram Type= 6, Freq= 0, CH_1, rank 0
4476 13:21:44.534996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 13:21:44.535128 ==
4478 13:21:44.535243 RX Vref Scan: 0
4479 13:21:44.535354
4480 13:21:44.538256 RX Vref 0 -> 0, step: 1
4481 13:21:44.538377
4482 13:21:44.541755 RX Delay -230 -> 252, step: 16
4483 13:21:44.544923 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4484 13:21:44.548264 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4485 13:21:44.554956 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4486 13:21:44.558269 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4487 13:21:44.561629 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4488 13:21:44.564897 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4489 13:21:44.571830 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4490 13:21:44.575702 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4491 13:21:44.578569 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4492 13:21:44.581465 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4493 13:21:44.584584 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4494 13:21:44.591255 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4495 13:21:44.595118 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4496 13:21:44.598238 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4497 13:21:44.601659 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4498 13:21:44.608334 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4499 13:21:44.608459 ==
4500 13:21:44.611436 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 13:21:44.614970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 13:21:44.615094 ==
4503 13:21:44.615208 DQS Delay:
4504 13:21:44.617922 DQS0 = 0, DQS1 = 0
4505 13:21:44.618043 DQM Delay:
4506 13:21:44.621281 DQM0 = 49, DQM1 = 41
4507 13:21:44.621403 DQ Delay:
4508 13:21:44.624687 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4509 13:21:44.628021 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4510 13:21:44.631640 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4511 13:21:44.634841 DQ12 =57, DQ13 =41, DQ14 =41, DQ15 =41
4512 13:21:44.634967
4513 13:21:44.635079
4514 13:21:44.635194 ==
4515 13:21:44.637989 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 13:21:44.641208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 13:21:44.641333 ==
4518 13:21:44.644529
4519 13:21:44.644647
4520 13:21:44.644779 TX Vref Scan disable
4521 13:21:44.648133 == TX Byte 0 ==
4522 13:21:44.651379 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4523 13:21:44.654975 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4524 13:21:44.658051 == TX Byte 1 ==
4525 13:21:44.661553 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4526 13:21:44.664632 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4527 13:21:44.664761 ==
4528 13:21:44.668242 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 13:21:44.674731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 13:21:44.674860 ==
4531 13:21:44.674973
4532 13:21:44.675082
4533 13:21:44.675197 TX Vref Scan disable
4534 13:21:44.679158 == TX Byte 0 ==
4535 13:21:44.682278 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4536 13:21:44.689083 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4537 13:21:44.689212 == TX Byte 1 ==
4538 13:21:44.692520 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4539 13:21:44.698958 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4540 13:21:44.699083
4541 13:21:44.699195 [DATLAT]
4542 13:21:44.699305 Freq=600, CH1 RK0
4543 13:21:44.699420
4544 13:21:44.702342 DATLAT Default: 0x9
4545 13:21:44.702463 0, 0xFFFF, sum = 0
4546 13:21:44.705988 1, 0xFFFF, sum = 0
4547 13:21:44.706081 2, 0xFFFF, sum = 0
4548 13:21:44.708923 3, 0xFFFF, sum = 0
4549 13:21:44.712161 4, 0xFFFF, sum = 0
4550 13:21:44.712236 5, 0xFFFF, sum = 0
4551 13:21:44.715457 6, 0xFFFF, sum = 0
4552 13:21:44.715578 7, 0xFFFF, sum = 0
4553 13:21:44.719029 8, 0x0, sum = 1
4554 13:21:44.719103 9, 0x0, sum = 2
4555 13:21:44.719166 10, 0x0, sum = 3
4556 13:21:44.722447 11, 0x0, sum = 4
4557 13:21:44.722533 best_step = 9
4558 13:21:44.722600
4559 13:21:44.722663 ==
4560 13:21:44.725628 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 13:21:44.732257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 13:21:44.732348 ==
4563 13:21:44.732421 RX Vref Scan: 1
4564 13:21:44.732484
4565 13:21:44.735690 RX Vref 0 -> 0, step: 1
4566 13:21:44.735776
4567 13:21:44.739046 RX Delay -163 -> 252, step: 8
4568 13:21:44.739130
4569 13:21:44.742426 Set Vref, RX VrefLevel [Byte0]: 53
4570 13:21:44.745425 [Byte1]: 57
4571 13:21:44.745508
4572 13:21:44.748930 Final RX Vref Byte 0 = 53 to rank0
4573 13:21:44.752137 Final RX Vref Byte 1 = 57 to rank0
4574 13:21:44.755668 Final RX Vref Byte 0 = 53 to rank1
4575 13:21:44.758767 Final RX Vref Byte 1 = 57 to rank1==
4576 13:21:44.762043 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 13:21:44.765567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 13:21:44.765682 ==
4579 13:21:44.768955 DQS Delay:
4580 13:21:44.769081 DQS0 = 0, DQS1 = 0
4581 13:21:44.769197 DQM Delay:
4582 13:21:44.772287 DQM0 = 48, DQM1 = 39
4583 13:21:44.772409 DQ Delay:
4584 13:21:44.775759 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4585 13:21:44.778690 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4586 13:21:44.782288 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4587 13:21:44.785376 DQ12 =52, DQ13 =44, DQ14 =44, DQ15 =44
4588 13:21:44.785477
4589 13:21:44.785582
4590 13:21:44.795520 [DQSOSCAuto] RK0, (LSB)MR18= 0x486e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4591 13:21:44.799204 CH1 RK0: MR19=808, MR18=486E
4592 13:21:44.801863 CH1_RK0: MR19=0x808, MR18=0x486E, DQSOSC=389, MR23=63, INC=173, DEC=115
4593 13:21:44.801943
4594 13:21:44.805288 ----->DramcWriteLeveling(PI) begin...
4595 13:21:44.808722 ==
4596 13:21:44.811911 Dram Type= 6, Freq= 0, CH_1, rank 1
4597 13:21:44.815394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 13:21:44.815474 ==
4599 13:21:44.818563 Write leveling (Byte 0): 31 => 31
4600 13:21:44.821792 Write leveling (Byte 1): 31 => 31
4601 13:21:44.825113 DramcWriteLeveling(PI) end<-----
4602 13:21:44.825214
4603 13:21:44.825305 ==
4604 13:21:44.828940 Dram Type= 6, Freq= 0, CH_1, rank 1
4605 13:21:44.832242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 13:21:44.832319 ==
4607 13:21:44.835267 [Gating] SW mode calibration
4608 13:21:44.841986 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4609 13:21:44.848660 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4610 13:21:44.852049 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4611 13:21:44.855067 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4612 13:21:44.858737 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
4613 13:21:44.865085 0 9 12 | B1->B0 | 2a2a 3333 | 0 0 | (1 1) (1 1)
4614 13:21:44.868504 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 13:21:44.872745 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 13:21:44.878379 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 13:21:44.881969 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 13:21:44.885282 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 13:21:44.891839 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 13:21:44.895213 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 13:21:44.898338 0 10 12 | B1->B0 | 4141 3131 | 0 0 | (0 0) (1 1)
4622 13:21:44.904972 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4623 13:21:44.908592 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 13:21:44.911688 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 13:21:44.918404 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 13:21:44.921967 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 13:21:44.924998 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 13:21:44.932094 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4629 13:21:44.935020 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4630 13:21:44.938423 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 13:21:44.944968 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 13:21:44.948649 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 13:21:44.951606 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 13:21:44.958440 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 13:21:44.961493 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 13:21:44.965190 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 13:21:44.971971 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 13:21:44.975408 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 13:21:44.978413 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 13:21:44.981713 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 13:21:44.988512 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 13:21:44.991480 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 13:21:44.994895 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 13:21:45.001466 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4645 13:21:45.005167 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4646 13:21:45.008221 Total UI for P1: 0, mck2ui 16
4647 13:21:45.011630 best dqsien dly found for B0: ( 0, 13, 8)
4648 13:21:45.014820 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 13:21:45.018174 Total UI for P1: 0, mck2ui 16
4650 13:21:45.021786 best dqsien dly found for B1: ( 0, 13, 12)
4651 13:21:45.025115 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4652 13:21:45.028311 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4653 13:21:45.028395
4654 13:21:45.035090 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4655 13:21:45.038064 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4656 13:21:45.041618 [Gating] SW calibration Done
4657 13:21:45.041701 ==
4658 13:21:45.044692 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 13:21:45.048258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 13:21:45.048342 ==
4661 13:21:45.048408 RX Vref Scan: 0
4662 13:21:45.048477
4663 13:21:45.051734 RX Vref 0 -> 0, step: 1
4664 13:21:45.051848
4665 13:21:45.054913 RX Delay -230 -> 252, step: 16
4666 13:21:45.058141 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4667 13:21:45.061446 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4668 13:21:45.068514 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4669 13:21:45.071762 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4670 13:21:45.074823 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4671 13:21:45.078359 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4672 13:21:45.081868 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4673 13:21:45.088114 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4674 13:21:45.091475 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4675 13:21:45.094846 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4676 13:21:45.098059 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4677 13:21:45.104777 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4678 13:21:45.107938 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4679 13:21:45.111627 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4680 13:21:45.114502 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4681 13:21:45.121378 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4682 13:21:45.121464 ==
4683 13:21:45.124539 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 13:21:45.127961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 13:21:45.128046 ==
4686 13:21:45.128114 DQS Delay:
4687 13:21:45.131388 DQS0 = 0, DQS1 = 0
4688 13:21:45.131473 DQM Delay:
4689 13:21:45.134965 DQM0 = 50, DQM1 = 45
4690 13:21:45.135047 DQ Delay:
4691 13:21:45.137736 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4692 13:21:45.141432 DQ4 =49, DQ5 =65, DQ6 =49, DQ7 =49
4693 13:21:45.144373 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4694 13:21:45.147583 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4695 13:21:45.147655
4696 13:21:45.147716
4697 13:21:45.147779 ==
4698 13:21:45.150792 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 13:21:45.154653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 13:21:45.154722 ==
4701 13:21:45.154786
4702 13:21:45.158049
4703 13:21:45.158117 TX Vref Scan disable
4704 13:21:45.160893 == TX Byte 0 ==
4705 13:21:45.164395 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4706 13:21:45.167437 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4707 13:21:45.170655 == TX Byte 1 ==
4708 13:21:45.173973 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4709 13:21:45.177444 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4710 13:21:45.180695 ==
4711 13:21:45.180824 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 13:21:45.187592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 13:21:45.187671 ==
4714 13:21:45.187756
4715 13:21:45.187860
4716 13:21:45.190706 TX Vref Scan disable
4717 13:21:45.190780 == TX Byte 0 ==
4718 13:21:45.197268 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4719 13:21:45.200743 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4720 13:21:45.200863 == TX Byte 1 ==
4721 13:21:45.207392 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4722 13:21:45.210613 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4723 13:21:45.210692
4724 13:21:45.210785 [DATLAT]
4725 13:21:45.214214 Freq=600, CH1 RK1
4726 13:21:45.214318
4727 13:21:45.214418 DATLAT Default: 0x9
4728 13:21:45.217221 0, 0xFFFF, sum = 0
4729 13:21:45.217318 1, 0xFFFF, sum = 0
4730 13:21:45.220501 2, 0xFFFF, sum = 0
4731 13:21:45.220602 3, 0xFFFF, sum = 0
4732 13:21:45.223836 4, 0xFFFF, sum = 0
4733 13:21:45.223961 5, 0xFFFF, sum = 0
4734 13:21:45.227340 6, 0xFFFF, sum = 0
4735 13:21:45.227436 7, 0xFFFF, sum = 0
4736 13:21:45.230586 8, 0x0, sum = 1
4737 13:21:45.230675 9, 0x0, sum = 2
4738 13:21:45.234043 10, 0x0, sum = 3
4739 13:21:45.234188 11, 0x0, sum = 4
4740 13:21:45.237235 best_step = 9
4741 13:21:45.237367
4742 13:21:45.237480 ==
4743 13:21:45.240608 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 13:21:45.244184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 13:21:45.244268 ==
4746 13:21:45.247577 RX Vref Scan: 0
4747 13:21:45.247659
4748 13:21:45.247725 RX Vref 0 -> 0, step: 1
4749 13:21:45.247785
4750 13:21:45.250823 RX Delay -179 -> 252, step: 8
4751 13:21:45.257448 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4752 13:21:45.260887 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4753 13:21:45.264108 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4754 13:21:45.267289 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4755 13:21:45.270883 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4756 13:21:45.277407 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4757 13:21:45.280596 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4758 13:21:45.283796 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4759 13:21:45.287291 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4760 13:21:45.293917 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4761 13:21:45.297322 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4762 13:21:45.300733 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4763 13:21:45.304117 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4764 13:21:45.307081 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4765 13:21:45.313846 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4766 13:21:45.317140 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4767 13:21:45.317245 ==
4768 13:21:45.320433 Dram Type= 6, Freq= 0, CH_1, rank 1
4769 13:21:45.323632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4770 13:21:45.323717 ==
4771 13:21:45.327043 DQS Delay:
4772 13:21:45.327127 DQS0 = 0, DQS1 = 0
4773 13:21:45.327195 DQM Delay:
4774 13:21:45.330599 DQM0 = 48, DQM1 = 43
4775 13:21:45.330700 DQ Delay:
4776 13:21:45.333960 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4777 13:21:45.336869 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4778 13:21:45.340246 DQ8 =24, DQ9 =36, DQ10 =44, DQ11 =40
4779 13:21:45.344385 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =52
4780 13:21:45.344469
4781 13:21:45.344537
4782 13:21:45.353591 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4783 13:21:45.356966 CH1 RK1: MR19=808, MR18=5F24
4784 13:21:45.360162 CH1_RK1: MR19=0x808, MR18=0x5F24, DQSOSC=391, MR23=63, INC=171, DEC=114
4785 13:21:45.363515 [RxdqsGatingPostProcess] freq 600
4786 13:21:45.370204 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4787 13:21:45.373299 Pre-setting of DQS Precalculation
4788 13:21:45.376921 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4789 13:21:45.386745 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4790 13:21:45.393611 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4791 13:21:45.393695
4792 13:21:45.393763
4793 13:21:45.396589 [Calibration Summary] 1200 Mbps
4794 13:21:45.396674 CH 0, Rank 0
4795 13:21:45.400173 SW Impedance : PASS
4796 13:21:45.400257 DUTY Scan : NO K
4797 13:21:45.403386 ZQ Calibration : PASS
4798 13:21:45.406819 Jitter Meter : NO K
4799 13:21:45.406903 CBT Training : PASS
4800 13:21:45.410124 Write leveling : PASS
4801 13:21:45.413237 RX DQS gating : PASS
4802 13:21:45.413322 RX DQ/DQS(RDDQC) : PASS
4803 13:21:45.416433 TX DQ/DQS : PASS
4804 13:21:45.419831 RX DATLAT : PASS
4805 13:21:45.419916 RX DQ/DQS(Engine): PASS
4806 13:21:45.423406 TX OE : NO K
4807 13:21:45.423490 All Pass.
4808 13:21:45.423557
4809 13:21:45.423619 CH 0, Rank 1
4810 13:21:45.426539 SW Impedance : PASS
4811 13:21:45.430027 DUTY Scan : NO K
4812 13:21:45.430111 ZQ Calibration : PASS
4813 13:21:45.433316 Jitter Meter : NO K
4814 13:21:45.436957 CBT Training : PASS
4815 13:21:45.437041 Write leveling : PASS
4816 13:21:45.440039 RX DQS gating : PASS
4817 13:21:45.443131 RX DQ/DQS(RDDQC) : PASS
4818 13:21:45.443215 TX DQ/DQS : PASS
4819 13:21:45.446470 RX DATLAT : PASS
4820 13:21:45.449812 RX DQ/DQS(Engine): PASS
4821 13:21:45.449896 TX OE : NO K
4822 13:21:45.453063 All Pass.
4823 13:21:45.453176
4824 13:21:45.453271 CH 1, Rank 0
4825 13:21:45.456435 SW Impedance : PASS
4826 13:21:45.456523 DUTY Scan : NO K
4827 13:21:45.459937 ZQ Calibration : PASS
4828 13:21:45.463434 Jitter Meter : NO K
4829 13:21:45.463518 CBT Training : PASS
4830 13:21:45.466290 Write leveling : PASS
4831 13:21:45.466374 RX DQS gating : PASS
4832 13:21:45.469913 RX DQ/DQS(RDDQC) : PASS
4833 13:21:45.473557 TX DQ/DQS : PASS
4834 13:21:45.473642 RX DATLAT : PASS
4835 13:21:45.476333 RX DQ/DQS(Engine): PASS
4836 13:21:45.479647 TX OE : NO K
4837 13:21:45.479732 All Pass.
4838 13:21:45.479800
4839 13:21:45.479863 CH 1, Rank 1
4840 13:21:45.483172 SW Impedance : PASS
4841 13:21:45.486233 DUTY Scan : NO K
4842 13:21:45.486333 ZQ Calibration : PASS
4843 13:21:45.489848 Jitter Meter : NO K
4844 13:21:45.493139 CBT Training : PASS
4845 13:21:45.493223 Write leveling : PASS
4846 13:21:45.496276 RX DQS gating : PASS
4847 13:21:45.499928 RX DQ/DQS(RDDQC) : PASS
4848 13:21:45.500013 TX DQ/DQS : PASS
4849 13:21:45.502911 RX DATLAT : PASS
4850 13:21:45.506337 RX DQ/DQS(Engine): PASS
4851 13:21:45.506412 TX OE : NO K
4852 13:21:45.509997 All Pass.
4853 13:21:45.510071
4854 13:21:45.510134 DramC Write-DBI off
4855 13:21:45.512996 PER_BANK_REFRESH: Hybrid Mode
4856 13:21:45.513067 TX_TRACKING: ON
4857 13:21:45.523342 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4858 13:21:45.526175 [FAST_K] Save calibration result to emmc
4859 13:21:45.529854 dramc_set_vcore_voltage set vcore to 662500
4860 13:21:45.532724 Read voltage for 933, 3
4861 13:21:45.532842 Vio18 = 0
4862 13:21:45.536302 Vcore = 662500
4863 13:21:45.536384 Vdram = 0
4864 13:21:45.536450 Vddq = 0
4865 13:21:45.536542 Vmddr = 0
4866 13:21:45.543060 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4867 13:21:45.549537 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4868 13:21:45.549621 MEM_TYPE=3, freq_sel=17
4869 13:21:45.553165 sv_algorithm_assistance_LP4_1600
4870 13:21:45.556093 ============ PULL DRAM RESETB DOWN ============
4871 13:21:45.562989 ========== PULL DRAM RESETB DOWN end =========
4872 13:21:45.566468 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4873 13:21:45.569893 ===================================
4874 13:21:45.573411 LPDDR4 DRAM CONFIGURATION
4875 13:21:45.576583 ===================================
4876 13:21:45.576666 EX_ROW_EN[0] = 0x0
4877 13:21:45.580247 EX_ROW_EN[1] = 0x0
4878 13:21:45.580330 LP4Y_EN = 0x0
4879 13:21:45.583332 WORK_FSP = 0x0
4880 13:21:45.583415 WL = 0x3
4881 13:21:45.586327 RL = 0x3
4882 13:21:45.586410 BL = 0x2
4883 13:21:45.589785 RPST = 0x0
4884 13:21:45.589868 RD_PRE = 0x0
4885 13:21:45.593184 WR_PRE = 0x1
4886 13:21:45.593267 WR_PST = 0x0
4887 13:21:45.596612 DBI_WR = 0x0
4888 13:21:45.596695 DBI_RD = 0x0
4889 13:21:45.600055 OTF = 0x1
4890 13:21:45.603342 ===================================
4891 13:21:45.606644 ===================================
4892 13:21:45.606727 ANA top config
4893 13:21:45.610307 ===================================
4894 13:21:45.613304 DLL_ASYNC_EN = 0
4895 13:21:45.616496 ALL_SLAVE_EN = 1
4896 13:21:45.619939 NEW_RANK_MODE = 1
4897 13:21:45.620023 DLL_IDLE_MODE = 1
4898 13:21:45.623633 LP45_APHY_COMB_EN = 1
4899 13:21:45.626309 TX_ODT_DIS = 1
4900 13:21:45.630019 NEW_8X_MODE = 1
4901 13:21:45.633317 ===================================
4902 13:21:45.636667 ===================================
4903 13:21:45.639712 data_rate = 1866
4904 13:21:45.639795 CKR = 1
4905 13:21:45.643159 DQ_P2S_RATIO = 8
4906 13:21:45.646405 ===================================
4907 13:21:45.649735 CA_P2S_RATIO = 8
4908 13:21:45.653190 DQ_CA_OPEN = 0
4909 13:21:45.656370 DQ_SEMI_OPEN = 0
4910 13:21:45.659482 CA_SEMI_OPEN = 0
4911 13:21:45.659581 CA_FULL_RATE = 0
4912 13:21:45.662929 DQ_CKDIV4_EN = 1
4913 13:21:45.666147 CA_CKDIV4_EN = 1
4914 13:21:45.669397 CA_PREDIV_EN = 0
4915 13:21:45.672719 PH8_DLY = 0
4916 13:21:45.676123 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4917 13:21:45.676208 DQ_AAMCK_DIV = 4
4918 13:21:45.679401 CA_AAMCK_DIV = 4
4919 13:21:45.683421 CA_ADMCK_DIV = 4
4920 13:21:45.686506 DQ_TRACK_CA_EN = 0
4921 13:21:45.689637 CA_PICK = 933
4922 13:21:45.692724 CA_MCKIO = 933
4923 13:21:45.696153 MCKIO_SEMI = 0
4924 13:21:45.696253 PLL_FREQ = 3732
4925 13:21:45.699542 DQ_UI_PI_RATIO = 32
4926 13:21:45.702791 CA_UI_PI_RATIO = 0
4927 13:21:45.706516 ===================================
4928 13:21:45.709340 ===================================
4929 13:21:45.712635 memory_type:LPDDR4
4930 13:21:45.716177 GP_NUM : 10
4931 13:21:45.716305 SRAM_EN : 1
4932 13:21:45.719512 MD32_EN : 0
4933 13:21:45.722512 ===================================
4934 13:21:45.722634 [ANA_INIT] >>>>>>>>>>>>>>
4935 13:21:45.725897 <<<<<< [CONFIGURE PHASE]: ANA_TX
4936 13:21:45.729032 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4937 13:21:45.732284 ===================================
4938 13:21:45.735777 data_rate = 1866,PCW = 0X8f00
4939 13:21:45.739527 ===================================
4940 13:21:45.742400 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4941 13:21:45.749087 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4942 13:21:45.755886 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4943 13:21:45.759077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4944 13:21:45.762547 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4945 13:21:45.765679 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4946 13:21:45.768749 [ANA_INIT] flow start
4947 13:21:45.768905 [ANA_INIT] PLL >>>>>>>>
4948 13:21:45.772713 [ANA_INIT] PLL <<<<<<<<
4949 13:21:45.775515 [ANA_INIT] MIDPI >>>>>>>>
4950 13:21:45.775652 [ANA_INIT] MIDPI <<<<<<<<
4951 13:21:45.779089 [ANA_INIT] DLL >>>>>>>>
4952 13:21:45.782725 [ANA_INIT] flow end
4953 13:21:45.785663 ============ LP4 DIFF to SE enter ============
4954 13:21:45.788681 ============ LP4 DIFF to SE exit ============
4955 13:21:45.791875 [ANA_INIT] <<<<<<<<<<<<<
4956 13:21:45.795375 [Flow] Enable top DCM control >>>>>
4957 13:21:45.798954 [Flow] Enable top DCM control <<<<<
4958 13:21:45.802213 Enable DLL master slave shuffle
4959 13:21:45.805401 ==============================================================
4960 13:21:45.808602 Gating Mode config
4961 13:21:45.815379 ==============================================================
4962 13:21:45.815479 Config description:
4963 13:21:45.825703 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4964 13:21:45.832192 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4965 13:21:45.835177 SELPH_MODE 0: By rank 1: By Phase
4966 13:21:45.841845 ==============================================================
4967 13:21:45.845253 GAT_TRACK_EN = 1
4968 13:21:45.848686 RX_GATING_MODE = 2
4969 13:21:45.851917 RX_GATING_TRACK_MODE = 2
4970 13:21:45.855146 SELPH_MODE = 1
4971 13:21:45.858315 PICG_EARLY_EN = 1
4972 13:21:45.861689 VALID_LAT_VALUE = 1
4973 13:21:45.864975 ==============================================================
4974 13:21:45.868544 Enter into Gating configuration >>>>
4975 13:21:45.871901 Exit from Gating configuration <<<<
4976 13:21:45.875246 Enter into DVFS_PRE_config >>>>>
4977 13:21:45.888452 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4978 13:21:45.888539 Exit from DVFS_PRE_config <<<<<
4979 13:21:45.891645 Enter into PICG configuration >>>>
4980 13:21:45.895148 Exit from PICG configuration <<<<
4981 13:21:45.898455 [RX_INPUT] configuration >>>>>
4982 13:21:45.901513 [RX_INPUT] configuration <<<<<
4983 13:21:45.908261 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4984 13:21:45.911723 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4985 13:21:45.918258 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4986 13:21:45.925524 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4987 13:21:45.931700 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4988 13:21:45.938192 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4989 13:21:45.941709 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4990 13:21:45.944919 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4991 13:21:45.948381 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4992 13:21:45.954798 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4993 13:21:45.957989 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4994 13:21:45.961383 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4995 13:21:45.964922 ===================================
4996 13:21:45.968114 LPDDR4 DRAM CONFIGURATION
4997 13:21:45.971995 ===================================
4998 13:21:45.972107 EX_ROW_EN[0] = 0x0
4999 13:21:45.975095 EX_ROW_EN[1] = 0x0
5000 13:21:45.978180 LP4Y_EN = 0x0
5001 13:21:45.978303 WORK_FSP = 0x0
5002 13:21:45.981547 WL = 0x3
5003 13:21:45.981632 RL = 0x3
5004 13:21:45.985169 BL = 0x2
5005 13:21:45.985267 RPST = 0x0
5006 13:21:45.988478 RD_PRE = 0x0
5007 13:21:45.988564 WR_PRE = 0x1
5008 13:21:45.991382 WR_PST = 0x0
5009 13:21:45.991479 DBI_WR = 0x0
5010 13:21:45.994762 DBI_RD = 0x0
5011 13:21:45.994846 OTF = 0x1
5012 13:21:45.998002 ===================================
5013 13:21:46.001778 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5014 13:21:46.008447 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5015 13:21:46.011795 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5016 13:21:46.014916 ===================================
5017 13:21:46.018052 LPDDR4 DRAM CONFIGURATION
5018 13:21:46.021432 ===================================
5019 13:21:46.021556 EX_ROW_EN[0] = 0x10
5020 13:21:46.024712 EX_ROW_EN[1] = 0x0
5021 13:21:46.024875 LP4Y_EN = 0x0
5022 13:21:46.028372 WORK_FSP = 0x0
5023 13:21:46.028495 WL = 0x3
5024 13:21:46.031248 RL = 0x3
5025 13:21:46.031409 BL = 0x2
5026 13:21:46.034707 RPST = 0x0
5027 13:21:46.038384 RD_PRE = 0x0
5028 13:21:46.038507 WR_PRE = 0x1
5029 13:21:46.041228 WR_PST = 0x0
5030 13:21:46.041356 DBI_WR = 0x0
5031 13:21:46.044639 DBI_RD = 0x0
5032 13:21:46.044781 OTF = 0x1
5033 13:21:46.048210 ===================================
5034 13:21:46.054794 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5035 13:21:46.058323 nWR fixed to 30
5036 13:21:46.061927 [ModeRegInit_LP4] CH0 RK0
5037 13:21:46.062052 [ModeRegInit_LP4] CH0 RK1
5038 13:21:46.065238 [ModeRegInit_LP4] CH1 RK0
5039 13:21:46.068405 [ModeRegInit_LP4] CH1 RK1
5040 13:21:46.068511 match AC timing 9
5041 13:21:46.074889 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5042 13:21:46.078645 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5043 13:21:46.081710 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5044 13:21:46.088335 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5045 13:21:46.092166 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5046 13:21:46.092251 ==
5047 13:21:46.095537 Dram Type= 6, Freq= 0, CH_0, rank 0
5048 13:21:46.098578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5049 13:21:46.098664 ==
5050 13:21:46.105243 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5051 13:21:46.111786 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5052 13:21:46.115230 [CA 0] Center 38 (7~69) winsize 63
5053 13:21:46.118287 [CA 1] Center 38 (8~69) winsize 62
5054 13:21:46.122229 [CA 2] Center 35 (5~66) winsize 62
5055 13:21:46.125160 [CA 3] Center 34 (4~65) winsize 62
5056 13:21:46.128268 [CA 4] Center 34 (4~65) winsize 62
5057 13:21:46.131765 [CA 5] Center 33 (3~64) winsize 62
5058 13:21:46.131850
5059 13:21:46.135061 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5060 13:21:46.135146
5061 13:21:46.138390 [CATrainingPosCal] consider 1 rank data
5062 13:21:46.141654 u2DelayCellTimex100 = 270/100 ps
5063 13:21:46.144971 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5064 13:21:46.148376 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5065 13:21:46.151578 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5066 13:21:46.155187 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5067 13:21:46.158370 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5068 13:21:46.161544 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5069 13:21:46.161666
5070 13:21:46.168423 CA PerBit enable=1, Macro0, CA PI delay=33
5071 13:21:46.168547
5072 13:21:46.168655 [CBTSetCACLKResult] CA Dly = 33
5073 13:21:46.171610 CS Dly: 6 (0~37)
5074 13:21:46.171734 ==
5075 13:21:46.175025 Dram Type= 6, Freq= 0, CH_0, rank 1
5076 13:21:46.178253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5077 13:21:46.178376 ==
5078 13:21:46.184909 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5079 13:21:46.191299 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5080 13:21:46.194711 [CA 0] Center 38 (8~69) winsize 62
5081 13:21:46.198095 [CA 1] Center 38 (8~69) winsize 62
5082 13:21:46.201423 [CA 2] Center 36 (6~66) winsize 61
5083 13:21:46.204625 [CA 3] Center 36 (6~66) winsize 61
5084 13:21:46.208140 [CA 4] Center 34 (4~65) winsize 62
5085 13:21:46.211487 [CA 5] Center 34 (4~64) winsize 61
5086 13:21:46.211610
5087 13:21:46.215085 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5088 13:21:46.215208
5089 13:21:46.218217 [CATrainingPosCal] consider 2 rank data
5090 13:21:46.221522 u2DelayCellTimex100 = 270/100 ps
5091 13:21:46.224960 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5092 13:21:46.227787 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5093 13:21:46.231261 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5094 13:21:46.234534 CA3 delay=35 (6~65),Diff = 1 PI (6 cell)
5095 13:21:46.237642 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5096 13:21:46.244656 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5097 13:21:46.244815
5098 13:21:46.247737 CA PerBit enable=1, Macro0, CA PI delay=34
5099 13:21:46.247893
5100 13:21:46.251049 [CBTSetCACLKResult] CA Dly = 34
5101 13:21:46.251163 CS Dly: 7 (0~39)
5102 13:21:46.251278
5103 13:21:46.254432 ----->DramcWriteLeveling(PI) begin...
5104 13:21:46.254542 ==
5105 13:21:46.257755 Dram Type= 6, Freq= 0, CH_0, rank 0
5106 13:21:46.264472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 13:21:46.264593 ==
5108 13:21:46.268025 Write leveling (Byte 0): 33 => 33
5109 13:21:46.268111 Write leveling (Byte 1): 32 => 32
5110 13:21:46.271030 DramcWriteLeveling(PI) end<-----
5111 13:21:46.271143
5112 13:21:46.271239 ==
5113 13:21:46.274136 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 13:21:46.280851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 13:21:46.280936 ==
5116 13:21:46.284098 [Gating] SW mode calibration
5117 13:21:46.290589 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5118 13:21:46.294195 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5119 13:21:46.300610 0 14 0 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5120 13:21:46.303977 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 13:21:46.307248 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 13:21:46.314295 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 13:21:46.317659 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 13:21:46.321064 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 13:21:46.327359 0 14 24 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
5126 13:21:46.330355 0 14 28 | B1->B0 | 3030 2424 | 1 0 | (0 1) (0 0)
5127 13:21:46.333910 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5128 13:21:46.340321 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 13:21:46.343804 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 13:21:46.347398 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 13:21:46.353490 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 13:21:46.356915 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 13:21:46.360259 0 15 24 | B1->B0 | 2323 3636 | 0 0 | (0 0) (1 1)
5134 13:21:46.366947 0 15 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
5135 13:21:46.370042 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 13:21:46.373396 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 13:21:46.380155 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 13:21:46.383416 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 13:21:46.386782 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 13:21:46.393734 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 13:21:46.396934 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5142 13:21:46.399958 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5143 13:21:46.403229 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5144 13:21:46.409997 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 13:21:46.413301 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 13:21:46.416699 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 13:21:46.423199 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 13:21:46.426295 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 13:21:46.429744 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 13:21:46.436279 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 13:21:46.439637 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 13:21:46.443145 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 13:21:46.449495 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 13:21:46.452919 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 13:21:46.456502 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 13:21:46.463342 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 13:21:46.466331 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5158 13:21:46.469849 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5159 13:21:46.472882 Total UI for P1: 0, mck2ui 16
5160 13:21:46.476164 best dqsien dly found for B0: ( 1, 2, 24)
5161 13:21:46.483386 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 13:21:46.483471 Total UI for P1: 0, mck2ui 16
5163 13:21:46.489669 best dqsien dly found for B1: ( 1, 2, 26)
5164 13:21:46.493059 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5165 13:21:46.496433 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5166 13:21:46.496515
5167 13:21:46.499549 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5168 13:21:46.502847 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5169 13:21:46.506287 [Gating] SW calibration Done
5170 13:21:46.506369 ==
5171 13:21:46.509595 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 13:21:46.512642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 13:21:46.512757 ==
5174 13:21:46.516324 RX Vref Scan: 0
5175 13:21:46.516461
5176 13:21:46.516555 RX Vref 0 -> 0, step: 1
5177 13:21:46.516645
5178 13:21:46.519326 RX Delay -80 -> 252, step: 8
5179 13:21:46.522660 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5180 13:21:46.529618 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5181 13:21:46.532732 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5182 13:21:46.536175 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5183 13:21:46.539777 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5184 13:21:46.542729 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5185 13:21:46.549530 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5186 13:21:46.553508 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5187 13:21:46.556044 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5188 13:21:46.559904 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5189 13:21:46.563051 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5190 13:21:46.566477 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5191 13:21:46.572934 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5192 13:21:46.576271 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5193 13:21:46.579434 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5194 13:21:46.582557 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5195 13:21:46.582640 ==
5196 13:21:46.586322 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 13:21:46.589370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 13:21:46.589454 ==
5199 13:21:46.593047 DQS Delay:
5200 13:21:46.593130 DQS0 = 0, DQS1 = 0
5201 13:21:46.596177 DQM Delay:
5202 13:21:46.596259 DQM0 = 106, DQM1 = 90
5203 13:21:46.596325 DQ Delay:
5204 13:21:46.599705 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =103
5205 13:21:46.602684 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5206 13:21:46.605994 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5207 13:21:46.612544 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5208 13:21:46.612653
5209 13:21:46.612775
5210 13:21:46.612856 ==
5211 13:21:46.615968 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 13:21:46.619401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 13:21:46.619528 ==
5214 13:21:46.619642
5215 13:21:46.619755
5216 13:21:46.622378 TX Vref Scan disable
5217 13:21:46.622504 == TX Byte 0 ==
5218 13:21:46.629569 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5219 13:21:46.632289 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5220 13:21:46.632414 == TX Byte 1 ==
5221 13:21:46.639139 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5222 13:21:46.642513 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5223 13:21:46.642636 ==
5224 13:21:46.645606 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 13:21:46.648983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 13:21:46.649104 ==
5227 13:21:46.649198
5228 13:21:46.649287
5229 13:21:46.652158 TX Vref Scan disable
5230 13:21:46.655642 == TX Byte 0 ==
5231 13:21:46.659091 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5232 13:21:46.662191 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5233 13:21:46.665849 == TX Byte 1 ==
5234 13:21:46.669253 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5235 13:21:46.672650 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5236 13:21:46.672759
5237 13:21:46.675963 [DATLAT]
5238 13:21:46.676052 Freq=933, CH0 RK0
5239 13:21:46.676116
5240 13:21:46.679412 DATLAT Default: 0xd
5241 13:21:46.679521 0, 0xFFFF, sum = 0
5242 13:21:46.682786 1, 0xFFFF, sum = 0
5243 13:21:46.682872 2, 0xFFFF, sum = 0
5244 13:21:46.685699 3, 0xFFFF, sum = 0
5245 13:21:46.685801 4, 0xFFFF, sum = 0
5246 13:21:46.689050 5, 0xFFFF, sum = 0
5247 13:21:46.689136 6, 0xFFFF, sum = 0
5248 13:21:46.692266 7, 0xFFFF, sum = 0
5249 13:21:46.692392 8, 0xFFFF, sum = 0
5250 13:21:46.695779 9, 0xFFFF, sum = 0
5251 13:21:46.695864 10, 0x0, sum = 1
5252 13:21:46.699249 11, 0x0, sum = 2
5253 13:21:46.699335 12, 0x0, sum = 3
5254 13:21:46.702590 13, 0x0, sum = 4
5255 13:21:46.702675 best_step = 11
5256 13:21:46.702742
5257 13:21:46.702804 ==
5258 13:21:46.705607 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 13:21:46.712585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 13:21:46.712696 ==
5261 13:21:46.712823 RX Vref Scan: 1
5262 13:21:46.712889
5263 13:21:46.715735 RX Vref 0 -> 0, step: 1
5264 13:21:46.715820
5265 13:21:46.719247 RX Delay -53 -> 252, step: 4
5266 13:21:46.719331
5267 13:21:46.722219 Set Vref, RX VrefLevel [Byte0]: 59
5268 13:21:46.725493 [Byte1]: 50
5269 13:21:46.725578
5270 13:21:46.728885 Final RX Vref Byte 0 = 59 to rank0
5271 13:21:46.732547 Final RX Vref Byte 1 = 50 to rank0
5272 13:21:46.735422 Final RX Vref Byte 0 = 59 to rank1
5273 13:21:46.738983 Final RX Vref Byte 1 = 50 to rank1==
5274 13:21:46.741983 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 13:21:46.745373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 13:21:46.745458 ==
5277 13:21:46.748731 DQS Delay:
5278 13:21:46.748834 DQS0 = 0, DQS1 = 0
5279 13:21:46.748902 DQM Delay:
5280 13:21:46.752200 DQM0 = 107, DQM1 = 92
5281 13:21:46.752286 DQ Delay:
5282 13:21:46.755493 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =106
5283 13:21:46.758978 DQ4 =110, DQ5 =98, DQ6 =116, DQ7 =114
5284 13:21:46.762250 DQ8 =86, DQ9 =78, DQ10 =92, DQ11 =92
5285 13:21:46.765722 DQ12 =98, DQ13 =94, DQ14 =104, DQ15 =98
5286 13:21:46.765808
5287 13:21:46.765893
5288 13:21:46.775498 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
5289 13:21:46.778681 CH0 RK0: MR19=505, MR18=2420
5290 13:21:46.785508 CH0_RK0: MR19=0x505, MR18=0x2420, DQSOSC=410, MR23=63, INC=64, DEC=42
5291 13:21:46.785596
5292 13:21:46.788890 ----->DramcWriteLeveling(PI) begin...
5293 13:21:46.788999 ==
5294 13:21:46.792165 Dram Type= 6, Freq= 0, CH_0, rank 1
5295 13:21:46.795674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 13:21:46.795778 ==
5297 13:21:46.798752 Write leveling (Byte 0): 35 => 35
5298 13:21:46.802191 Write leveling (Byte 1): 30 => 30
5299 13:21:46.805716 DramcWriteLeveling(PI) end<-----
5300 13:21:46.805797
5301 13:21:46.805861 ==
5302 13:21:46.808885 Dram Type= 6, Freq= 0, CH_0, rank 1
5303 13:21:46.812126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 13:21:46.812208 ==
5305 13:21:46.815459 [Gating] SW mode calibration
5306 13:21:46.821970 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5307 13:21:46.829053 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5308 13:21:46.831896 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 13:21:46.835136 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 13:21:46.842157 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 13:21:46.845590 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 13:21:46.848711 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 13:21:46.855310 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 13:21:46.858804 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (0 0) (1 0)
5315 13:21:46.861978 0 14 28 | B1->B0 | 2b2b 2626 | 0 0 | (1 0) (1 0)
5316 13:21:46.868714 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5317 13:21:46.872082 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 13:21:46.875690 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 13:21:46.878490 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 13:21:46.885229 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 13:21:46.888723 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 13:21:46.891983 0 15 24 | B1->B0 | 2626 2828 | 0 0 | (0 0) (0 0)
5323 13:21:46.898578 0 15 28 | B1->B0 | 4040 4444 | 0 0 | (0 0) (0 0)
5324 13:21:46.901849 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 13:21:46.905478 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 13:21:46.911941 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 13:21:46.915556 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 13:21:46.918700 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 13:21:46.925498 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 13:21:46.928584 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 13:21:46.931810 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5332 13:21:46.938602 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 13:21:46.941672 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 13:21:46.945539 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 13:21:46.951518 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 13:21:46.955185 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 13:21:46.958473 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 13:21:46.965171 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 13:21:46.968399 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 13:21:46.971610 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 13:21:46.978198 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 13:21:46.981544 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 13:21:46.985156 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 13:21:46.991608 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 13:21:46.994709 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 13:21:46.998411 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5347 13:21:47.004902 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5348 13:21:47.008474 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 13:21:47.011378 Total UI for P1: 0, mck2ui 16
5350 13:21:47.014961 best dqsien dly found for B0: ( 1, 2, 26)
5351 13:21:47.018335 Total UI for P1: 0, mck2ui 16
5352 13:21:47.021458 best dqsien dly found for B1: ( 1, 2, 28)
5353 13:21:47.024988 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5354 13:21:47.027971 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5355 13:21:47.028049
5356 13:21:47.031439 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5357 13:21:47.034766 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5358 13:21:47.037902 [Gating] SW calibration Done
5359 13:21:47.038002 ==
5360 13:21:47.041385 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 13:21:47.044912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 13:21:47.044988 ==
5363 13:21:47.047993 RX Vref Scan: 0
5364 13:21:47.048092
5365 13:21:47.051254 RX Vref 0 -> 0, step: 1
5366 13:21:47.051352
5367 13:21:47.051449 RX Delay -80 -> 252, step: 8
5368 13:21:47.058108 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5369 13:21:47.061485 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5370 13:21:47.064568 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5371 13:21:47.067788 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5372 13:21:47.071182 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5373 13:21:47.074881 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5374 13:21:47.081504 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5375 13:21:47.084725 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5376 13:21:47.088511 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5377 13:21:47.091251 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5378 13:21:47.094636 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5379 13:21:47.098214 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5380 13:21:47.104976 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5381 13:21:47.107822 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5382 13:21:47.111693 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5383 13:21:47.114631 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5384 13:21:47.114714 ==
5385 13:21:47.117798 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 13:21:47.121510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 13:21:47.121610 ==
5388 13:21:47.124641 DQS Delay:
5389 13:21:47.124785 DQS0 = 0, DQS1 = 0
5390 13:21:47.127952 DQM Delay:
5391 13:21:47.128073 DQM0 = 104, DQM1 = 90
5392 13:21:47.128177 DQ Delay:
5393 13:21:47.131427 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5394 13:21:47.137812 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5395 13:21:47.137938 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5396 13:21:47.144732 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5397 13:21:47.144860
5398 13:21:47.144971
5399 13:21:47.145082 ==
5400 13:21:47.147969 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 13:21:47.151043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 13:21:47.151163 ==
5403 13:21:47.151275
5404 13:21:47.151385
5405 13:21:47.154455 TX Vref Scan disable
5406 13:21:47.154576 == TX Byte 0 ==
5407 13:21:47.161085 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5408 13:21:47.164526 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5409 13:21:47.164644 == TX Byte 1 ==
5410 13:21:47.171325 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5411 13:21:47.174338 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5412 13:21:47.174458 ==
5413 13:21:47.177975 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 13:21:47.181100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 13:21:47.181221 ==
5416 13:21:47.181329
5417 13:21:47.181434
5418 13:21:47.184569 TX Vref Scan disable
5419 13:21:47.187750 == TX Byte 0 ==
5420 13:21:47.191262 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5421 13:21:47.194397 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5422 13:21:47.197781 == TX Byte 1 ==
5423 13:21:47.200744 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5424 13:21:47.204327 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5425 13:21:47.204410
5426 13:21:47.207600 [DATLAT]
5427 13:21:47.207683 Freq=933, CH0 RK1
5428 13:21:47.207750
5429 13:21:47.211119 DATLAT Default: 0xb
5430 13:21:47.211202 0, 0xFFFF, sum = 0
5431 13:21:47.214665 1, 0xFFFF, sum = 0
5432 13:21:47.214749 2, 0xFFFF, sum = 0
5433 13:21:47.217639 3, 0xFFFF, sum = 0
5434 13:21:47.217724 4, 0xFFFF, sum = 0
5435 13:21:47.221152 5, 0xFFFF, sum = 0
5436 13:21:47.221263 6, 0xFFFF, sum = 0
5437 13:21:47.224399 7, 0xFFFF, sum = 0
5438 13:21:47.224483 8, 0xFFFF, sum = 0
5439 13:21:47.227660 9, 0xFFFF, sum = 0
5440 13:21:47.227789 10, 0x0, sum = 1
5441 13:21:47.231010 11, 0x0, sum = 2
5442 13:21:47.231138 12, 0x0, sum = 3
5443 13:21:47.234192 13, 0x0, sum = 4
5444 13:21:47.234319 best_step = 11
5445 13:21:47.234431
5446 13:21:47.234539 ==
5447 13:21:47.237867 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 13:21:47.244296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 13:21:47.244421 ==
5450 13:21:47.244536 RX Vref Scan: 0
5451 13:21:47.244649
5452 13:21:47.247621 RX Vref 0 -> 0, step: 1
5453 13:21:47.247741
5454 13:21:47.250762 RX Delay -53 -> 252, step: 4
5455 13:21:47.254292 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5456 13:21:47.257606 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5457 13:21:47.264294 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5458 13:21:47.267820 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5459 13:21:47.270977 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5460 13:21:47.274276 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5461 13:21:47.277871 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5462 13:21:47.284223 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5463 13:21:47.287422 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5464 13:21:47.290901 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5465 13:21:47.294213 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5466 13:21:47.297441 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5467 13:21:47.300721 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5468 13:21:47.307644 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5469 13:21:47.311008 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5470 13:21:47.314609 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5471 13:21:47.314720 ==
5472 13:21:47.317572 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 13:21:47.320918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 13:21:47.321036 ==
5475 13:21:47.324509 DQS Delay:
5476 13:21:47.324604 DQS0 = 0, DQS1 = 0
5477 13:21:47.327683 DQM Delay:
5478 13:21:47.327786 DQM0 = 104, DQM1 = 92
5479 13:21:47.327880 DQ Delay:
5480 13:21:47.334307 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =100
5481 13:21:47.338205 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =112
5482 13:21:47.340574 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5483 13:21:47.344211 DQ12 =98, DQ13 =94, DQ14 =102, DQ15 =98
5484 13:21:47.344313
5485 13:21:47.344404
5486 13:21:47.351032 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5487 13:21:47.354364 CH0 RK1: MR19=505, MR18=2B0B
5488 13:21:47.360986 CH0_RK1: MR19=0x505, MR18=0x2B0B, DQSOSC=408, MR23=63, INC=65, DEC=43
5489 13:21:47.364180 [RxdqsGatingPostProcess] freq 933
5490 13:21:47.367562 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5491 13:21:47.371025 best DQS0 dly(2T, 0.5T) = (0, 10)
5492 13:21:47.374395 best DQS1 dly(2T, 0.5T) = (0, 10)
5493 13:21:47.377753 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5494 13:21:47.381098 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5495 13:21:47.384640 best DQS0 dly(2T, 0.5T) = (0, 10)
5496 13:21:47.387643 best DQS1 dly(2T, 0.5T) = (0, 10)
5497 13:21:47.390811 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5498 13:21:47.394184 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5499 13:21:47.397397 Pre-setting of DQS Precalculation
5500 13:21:47.400936 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5501 13:21:47.401019 ==
5502 13:21:47.404023 Dram Type= 6, Freq= 0, CH_1, rank 0
5503 13:21:47.410690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 13:21:47.410775 ==
5505 13:21:47.414127 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5506 13:21:47.420904 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5507 13:21:47.424122 [CA 0] Center 38 (8~68) winsize 61
5508 13:21:47.427478 [CA 1] Center 38 (8~68) winsize 61
5509 13:21:47.430700 [CA 2] Center 35 (6~65) winsize 60
5510 13:21:47.434124 [CA 3] Center 35 (5~65) winsize 61
5511 13:21:47.437375 [CA 4] Center 35 (5~66) winsize 62
5512 13:21:47.440660 [CA 5] Center 34 (4~64) winsize 61
5513 13:21:47.440793
5514 13:21:47.443980 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5515 13:21:47.444097
5516 13:21:47.447351 [CATrainingPosCal] consider 1 rank data
5517 13:21:47.450707 u2DelayCellTimex100 = 270/100 ps
5518 13:21:47.453981 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5519 13:21:47.457225 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5520 13:21:47.460369 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5521 13:21:47.467165 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5522 13:21:47.470770 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5523 13:21:47.473671 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5524 13:21:47.473794
5525 13:21:47.477546 CA PerBit enable=1, Macro0, CA PI delay=34
5526 13:21:47.477683
5527 13:21:47.480734 [CBTSetCACLKResult] CA Dly = 34
5528 13:21:47.480876 CS Dly: 6 (0~37)
5529 13:21:47.480988 ==
5530 13:21:47.483652 Dram Type= 6, Freq= 0, CH_1, rank 1
5531 13:21:47.490558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 13:21:47.490658 ==
5533 13:21:47.493875 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5534 13:21:47.500234 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5535 13:21:47.504345 [CA 0] Center 38 (8~69) winsize 62
5536 13:21:47.506895 [CA 1] Center 38 (8~69) winsize 62
5537 13:21:47.510473 [CA 2] Center 35 (5~66) winsize 62
5538 13:21:47.513820 [CA 3] Center 35 (6~65) winsize 60
5539 13:21:47.516743 [CA 4] Center 35 (6~65) winsize 60
5540 13:21:47.520280 [CA 5] Center 35 (5~65) winsize 61
5541 13:21:47.520363
5542 13:21:47.523519 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5543 13:21:47.523604
5544 13:21:47.527231 [CATrainingPosCal] consider 2 rank data
5545 13:21:47.530279 u2DelayCellTimex100 = 270/100 ps
5546 13:21:47.533785 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5547 13:21:47.536890 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5548 13:21:47.544060 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5549 13:21:47.547212 CA3 delay=35 (6~65),Diff = 1 PI (6 cell)
5550 13:21:47.550241 CA4 delay=35 (6~65),Diff = 1 PI (6 cell)
5551 13:21:47.553798 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5552 13:21:47.553881
5553 13:21:47.557234 CA PerBit enable=1, Macro0, CA PI delay=34
5554 13:21:47.557316
5555 13:21:47.560498 [CBTSetCACLKResult] CA Dly = 34
5556 13:21:47.560580 CS Dly: 7 (0~39)
5557 13:21:47.560646
5558 13:21:47.563886 ----->DramcWriteLeveling(PI) begin...
5559 13:21:47.567079 ==
5560 13:21:47.567168 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 13:21:47.573786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 13:21:47.573870 ==
5563 13:21:47.576876 Write leveling (Byte 0): 26 => 26
5564 13:21:47.580097 Write leveling (Byte 1): 27 => 27
5565 13:21:47.583417 DramcWriteLeveling(PI) end<-----
5566 13:21:47.583500
5567 13:21:47.583566 ==
5568 13:21:47.586772 Dram Type= 6, Freq= 0, CH_1, rank 0
5569 13:21:47.590488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5570 13:21:47.590572 ==
5571 13:21:47.593613 [Gating] SW mode calibration
5572 13:21:47.600322 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5573 13:21:47.603698 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5574 13:21:47.610542 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 13:21:47.613491 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 13:21:47.617121 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 13:21:47.623630 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 13:21:47.626821 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 13:21:47.630085 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 13:21:47.636662 0 14 24 | B1->B0 | 3333 3131 | 0 0 | (0 0) (0 1)
5581 13:21:47.640115 0 14 28 | B1->B0 | 2525 2424 | 1 0 | (1 0) (1 0)
5582 13:21:47.643234 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 13:21:47.650332 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 13:21:47.654168 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 13:21:47.656934 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 13:21:47.664097 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 13:21:47.666778 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 13:21:47.670171 0 15 24 | B1->B0 | 2c2c 2f2f | 0 0 | (0 0) (0 0)
5589 13:21:47.676855 0 15 28 | B1->B0 | 3838 3c3c | 1 0 | (1 1) (1 1)
5590 13:21:47.680282 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 13:21:47.683440 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 13:21:47.690045 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 13:21:47.693236 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 13:21:47.696649 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 13:21:47.703418 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5596 13:21:47.706755 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5597 13:21:47.709920 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 13:21:47.713402 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 13:21:47.720067 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 13:21:47.723228 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 13:21:47.726745 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 13:21:47.733457 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 13:21:47.737315 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 13:21:47.740328 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 13:21:47.746881 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 13:21:47.750199 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 13:21:47.753593 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 13:21:47.760058 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 13:21:47.763199 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 13:21:47.766785 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 13:21:47.773552 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 13:21:47.776817 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5613 13:21:47.779989 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 13:21:47.782997 Total UI for P1: 0, mck2ui 16
5615 13:21:47.786510 best dqsien dly found for B0: ( 1, 2, 24)
5616 13:21:47.789910 Total UI for P1: 0, mck2ui 16
5617 13:21:47.793231 best dqsien dly found for B1: ( 1, 2, 24)
5618 13:21:47.796596 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5619 13:21:47.799735 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5620 13:21:47.799818
5621 13:21:47.803458 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5622 13:21:47.810133 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5623 13:21:47.810216 [Gating] SW calibration Done
5624 13:21:47.813053 ==
5625 13:21:47.813128 Dram Type= 6, Freq= 0, CH_1, rank 0
5626 13:21:47.819789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 13:21:47.819869 ==
5628 13:21:47.819951 RX Vref Scan: 0
5629 13:21:47.820036
5630 13:21:47.823088 RX Vref 0 -> 0, step: 1
5631 13:21:47.823168
5632 13:21:47.826313 RX Delay -80 -> 252, step: 8
5633 13:21:47.829770 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5634 13:21:47.833243 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5635 13:21:47.836637 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5636 13:21:47.839903 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5637 13:21:47.846795 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5638 13:21:47.849922 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5639 13:21:47.853411 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5640 13:21:47.856321 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5641 13:21:47.859556 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5642 13:21:47.863033 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5643 13:21:47.869562 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5644 13:21:47.873277 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5645 13:21:47.876360 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5646 13:21:47.879812 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5647 13:21:47.883163 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5648 13:21:47.889967 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5649 13:21:47.890093 ==
5650 13:21:47.893246 Dram Type= 6, Freq= 0, CH_1, rank 0
5651 13:21:47.896475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5652 13:21:47.896561 ==
5653 13:21:47.896628 DQS Delay:
5654 13:21:47.899670 DQS0 = 0, DQS1 = 0
5655 13:21:47.899832 DQM Delay:
5656 13:21:47.903069 DQM0 = 102, DQM1 = 94
5657 13:21:47.903152 DQ Delay:
5658 13:21:47.906471 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5659 13:21:47.909710 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5660 13:21:47.913257 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5661 13:21:47.916202 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =103
5662 13:21:47.916287
5663 13:21:47.916354
5664 13:21:47.916416 ==
5665 13:21:47.919656 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 13:21:47.923199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 13:21:47.926551 ==
5668 13:21:47.926635
5669 13:21:47.926702
5670 13:21:47.926764 TX Vref Scan disable
5671 13:21:47.929617 == TX Byte 0 ==
5672 13:21:47.933058 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5673 13:21:47.936725 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5674 13:21:47.939770 == TX Byte 1 ==
5675 13:21:47.942740 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5676 13:21:47.946179 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5677 13:21:47.949612 ==
5678 13:21:47.953764 Dram Type= 6, Freq= 0, CH_1, rank 0
5679 13:21:47.956315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5680 13:21:47.956400 ==
5681 13:21:47.956468
5682 13:21:47.956531
5683 13:21:47.959469 TX Vref Scan disable
5684 13:21:47.959553 == TX Byte 0 ==
5685 13:21:47.966018 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5686 13:21:47.969714 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5687 13:21:47.969798 == TX Byte 1 ==
5688 13:21:47.976071 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5689 13:21:47.979649 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5690 13:21:47.979733
5691 13:21:47.979800 [DATLAT]
5692 13:21:47.983297 Freq=933, CH1 RK0
5693 13:21:47.983382
5694 13:21:47.983448 DATLAT Default: 0xd
5695 13:21:47.986282 0, 0xFFFF, sum = 0
5696 13:21:47.986369 1, 0xFFFF, sum = 0
5697 13:21:47.989597 2, 0xFFFF, sum = 0
5698 13:21:47.989697 3, 0xFFFF, sum = 0
5699 13:21:47.992694 4, 0xFFFF, sum = 0
5700 13:21:47.992829 5, 0xFFFF, sum = 0
5701 13:21:47.996213 6, 0xFFFF, sum = 0
5702 13:21:47.996298 7, 0xFFFF, sum = 0
5703 13:21:47.999483 8, 0xFFFF, sum = 0
5704 13:21:47.999567 9, 0xFFFF, sum = 0
5705 13:21:48.002633 10, 0x0, sum = 1
5706 13:21:48.002718 11, 0x0, sum = 2
5707 13:21:48.005934 12, 0x0, sum = 3
5708 13:21:48.006017 13, 0x0, sum = 4
5709 13:21:48.009740 best_step = 11
5710 13:21:48.009823
5711 13:21:48.009888 ==
5712 13:21:48.012905 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 13:21:48.016452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 13:21:48.016535 ==
5715 13:21:48.019726 RX Vref Scan: 1
5716 13:21:48.019809
5717 13:21:48.019875 RX Vref 0 -> 0, step: 1
5718 13:21:48.019936
5719 13:21:48.023269 RX Delay -53 -> 252, step: 4
5720 13:21:48.023352
5721 13:21:48.026052 Set Vref, RX VrefLevel [Byte0]: 53
5722 13:21:48.029541 [Byte1]: 57
5723 13:21:48.033360
5724 13:21:48.033443 Final RX Vref Byte 0 = 53 to rank0
5725 13:21:48.036969 Final RX Vref Byte 1 = 57 to rank0
5726 13:21:48.040143 Final RX Vref Byte 0 = 53 to rank1
5727 13:21:48.043454 Final RX Vref Byte 1 = 57 to rank1==
5728 13:21:48.046812 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 13:21:48.053595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 13:21:48.053679 ==
5731 13:21:48.053747 DQS Delay:
5732 13:21:48.053810 DQS0 = 0, DQS1 = 0
5733 13:21:48.056668 DQM Delay:
5734 13:21:48.056809 DQM0 = 104, DQM1 = 97
5735 13:21:48.060195 DQ Delay:
5736 13:21:48.063588 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5737 13:21:48.066688 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5738 13:21:48.070485 DQ8 =88, DQ9 =84, DQ10 =100, DQ11 =92
5739 13:21:48.073276 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =102
5740 13:21:48.073360
5741 13:21:48.073426
5742 13:21:48.079999 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 413 ps
5743 13:21:48.083297 CH1 RK0: MR19=505, MR18=1B33
5744 13:21:48.089962 CH1_RK0: MR19=0x505, MR18=0x1B33, DQSOSC=405, MR23=63, INC=66, DEC=44
5745 13:21:48.090045
5746 13:21:48.093157 ----->DramcWriteLeveling(PI) begin...
5747 13:21:48.093242 ==
5748 13:21:48.096502 Dram Type= 6, Freq= 0, CH_1, rank 1
5749 13:21:48.099975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 13:21:48.100059 ==
5751 13:21:48.103285 Write leveling (Byte 0): 27 => 27
5752 13:21:48.106477 Write leveling (Byte 1): 27 => 27
5753 13:21:48.109947 DramcWriteLeveling(PI) end<-----
5754 13:21:48.110030
5755 13:21:48.110095 ==
5756 13:21:48.113296 Dram Type= 6, Freq= 0, CH_1, rank 1
5757 13:21:48.116540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5758 13:21:48.120236 ==
5759 13:21:48.120318 [Gating] SW mode calibration
5760 13:21:48.130024 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5761 13:21:48.133249 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5762 13:21:48.136582 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 13:21:48.143072 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 13:21:48.146975 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 13:21:48.149972 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 13:21:48.156696 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 13:21:48.159805 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 13:21:48.163258 0 14 24 | B1->B0 | 2f2f 3434 | 1 0 | (1 0) (0 0)
5769 13:21:48.169587 0 14 28 | B1->B0 | 2424 2828 | 0 0 | (1 1) (0 1)
5770 13:21:48.173525 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5771 13:21:48.176563 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 13:21:48.183142 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 13:21:48.186177 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 13:21:48.189701 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 13:21:48.196477 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 13:21:48.199401 0 15 24 | B1->B0 | 2d2d 2626 | 0 1 | (0 0) (0 0)
5777 13:21:48.202889 0 15 28 | B1->B0 | 3c3c 3434 | 0 1 | (0 0) (0 0)
5778 13:21:48.206510 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5779 13:21:48.212864 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 13:21:48.216266 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 13:21:48.219644 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 13:21:48.226290 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 13:21:48.229639 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 13:21:48.232936 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 13:21:48.239631 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5786 13:21:48.242748 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 13:21:48.246151 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 13:21:48.252748 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 13:21:48.256257 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 13:21:48.259654 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 13:21:48.266336 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 13:21:48.269396 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 13:21:48.272887 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 13:21:48.279405 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 13:21:48.282739 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 13:21:48.286413 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 13:21:48.292896 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 13:21:48.296086 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 13:21:48.299443 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 13:21:48.306193 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5801 13:21:48.309473 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5802 13:21:48.312783 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 13:21:48.316171 Total UI for P1: 0, mck2ui 16
5804 13:21:48.319503 best dqsien dly found for B0: ( 1, 2, 26)
5805 13:21:48.322578 Total UI for P1: 0, mck2ui 16
5806 13:21:48.326407 best dqsien dly found for B1: ( 1, 2, 26)
5807 13:21:48.329311 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5808 13:21:48.332740 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5809 13:21:48.332862
5810 13:21:48.336204 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5811 13:21:48.343003 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5812 13:21:48.343087 [Gating] SW calibration Done
5813 13:21:48.343171 ==
5814 13:21:48.346317 Dram Type= 6, Freq= 0, CH_1, rank 1
5815 13:21:48.352579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5816 13:21:48.352664 ==
5817 13:21:48.352731 RX Vref Scan: 0
5818 13:21:48.352834
5819 13:21:48.355874 RX Vref 0 -> 0, step: 1
5820 13:21:48.355957
5821 13:21:48.359338 RX Delay -80 -> 252, step: 8
5822 13:21:48.362699 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5823 13:21:48.366057 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5824 13:21:48.369202 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5825 13:21:48.375905 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5826 13:21:48.379323 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5827 13:21:48.382379 iDelay=200, Bit 5, Center 115 (32 ~ 199) 168
5828 13:21:48.386128 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5829 13:21:48.388937 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5830 13:21:48.392442 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5831 13:21:48.399308 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5832 13:21:48.402503 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5833 13:21:48.405788 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5834 13:21:48.409132 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5835 13:21:48.412508 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5836 13:21:48.419029 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5837 13:21:48.422602 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5838 13:21:48.422723 ==
5839 13:21:48.425756 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 13:21:48.429367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 13:21:48.429491 ==
5842 13:21:48.429605 DQS Delay:
5843 13:21:48.432289 DQS0 = 0, DQS1 = 0
5844 13:21:48.432412 DQM Delay:
5845 13:21:48.435739 DQM0 = 103, DQM1 = 96
5846 13:21:48.435865 DQ Delay:
5847 13:21:48.439198 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =103
5848 13:21:48.442658 DQ4 =103, DQ5 =115, DQ6 =107, DQ7 =103
5849 13:21:48.445717 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5850 13:21:48.448980 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5851 13:21:48.449100
5852 13:21:48.449218
5853 13:21:48.449324 ==
5854 13:21:48.452219 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 13:21:48.459170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 13:21:48.459294 ==
5857 13:21:48.459410
5858 13:21:48.459524
5859 13:21:48.459635 TX Vref Scan disable
5860 13:21:48.462853 == TX Byte 0 ==
5861 13:21:48.466337 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5862 13:21:48.472901 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5863 13:21:48.472989 == TX Byte 1 ==
5864 13:21:48.476190 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5865 13:21:48.482994 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5866 13:21:48.483077 ==
5867 13:21:48.485999 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 13:21:48.489457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 13:21:48.489534 ==
5870 13:21:48.489597
5871 13:21:48.489657
5872 13:21:48.492819 TX Vref Scan disable
5873 13:21:48.492894 == TX Byte 0 ==
5874 13:21:48.499397 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5875 13:21:48.502811 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5876 13:21:48.502886 == TX Byte 1 ==
5877 13:21:48.510014 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5878 13:21:48.512575 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5879 13:21:48.512681
5880 13:21:48.512794 [DATLAT]
5881 13:21:48.515896 Freq=933, CH1 RK1
5882 13:21:48.515970
5883 13:21:48.516033 DATLAT Default: 0xb
5884 13:21:48.519279 0, 0xFFFF, sum = 0
5885 13:21:48.519368 1, 0xFFFF, sum = 0
5886 13:21:48.522956 2, 0xFFFF, sum = 0
5887 13:21:48.523033 3, 0xFFFF, sum = 0
5888 13:21:48.525867 4, 0xFFFF, sum = 0
5889 13:21:48.525969 5, 0xFFFF, sum = 0
5890 13:21:48.529309 6, 0xFFFF, sum = 0
5891 13:21:48.529423 7, 0xFFFF, sum = 0
5892 13:21:48.532651 8, 0xFFFF, sum = 0
5893 13:21:48.535759 9, 0xFFFF, sum = 0
5894 13:21:48.535878 10, 0x0, sum = 1
5895 13:21:48.535971 11, 0x0, sum = 2
5896 13:21:48.539389 12, 0x0, sum = 3
5897 13:21:48.539494 13, 0x0, sum = 4
5898 13:21:48.542369 best_step = 11
5899 13:21:48.542474
5900 13:21:48.542565 ==
5901 13:21:48.545752 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 13:21:48.549011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 13:21:48.549111 ==
5904 13:21:48.552757 RX Vref Scan: 0
5905 13:21:48.552867
5906 13:21:48.552956 RX Vref 0 -> 0, step: 1
5907 13:21:48.553050
5908 13:21:48.555713 RX Delay -53 -> 252, step: 4
5909 13:21:48.562975 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5910 13:21:48.566583 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5911 13:21:48.570003 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5912 13:21:48.573097 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5913 13:21:48.576374 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5914 13:21:48.583365 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5915 13:21:48.586494 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5916 13:21:48.589677 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5917 13:21:48.592955 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5918 13:21:48.596268 iDelay=199, Bit 9, Center 86 (-1 ~ 174) 176
5919 13:21:48.599738 iDelay=199, Bit 10, Center 98 (11 ~ 186) 176
5920 13:21:48.606654 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5921 13:21:48.609628 iDelay=199, Bit 12, Center 108 (23 ~ 194) 172
5922 13:21:48.612744 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5923 13:21:48.616316 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5924 13:21:48.622960 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5925 13:21:48.623082 ==
5926 13:21:48.626101 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 13:21:48.629862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 13:21:48.629967 ==
5929 13:21:48.630074 DQS Delay:
5930 13:21:48.632784 DQS0 = 0, DQS1 = 0
5931 13:21:48.632897 DQM Delay:
5932 13:21:48.636563 DQM0 = 104, DQM1 = 97
5933 13:21:48.636673 DQ Delay:
5934 13:21:48.639714 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102
5935 13:21:48.642836 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
5936 13:21:48.646317 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =92
5937 13:21:48.649733 DQ12 =108, DQ13 =102, DQ14 =102, DQ15 =106
5938 13:21:48.649825
5939 13:21:48.649950
5940 13:21:48.659588 [DQSOSCAuto] RK1, (LSB)MR18= 0x20fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
5941 13:21:48.659675 CH1 RK1: MR19=504, MR18=20FD
5942 13:21:48.666107 CH1_RK1: MR19=0x504, MR18=0x20FD, DQSOSC=411, MR23=63, INC=64, DEC=42
5943 13:21:48.669785 [RxdqsGatingPostProcess] freq 933
5944 13:21:48.676258 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5945 13:21:48.679626 best DQS0 dly(2T, 0.5T) = (0, 10)
5946 13:21:48.682973 best DQS1 dly(2T, 0.5T) = (0, 10)
5947 13:21:48.686195 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5948 13:21:48.689656 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5949 13:21:48.693339 best DQS0 dly(2T, 0.5T) = (0, 10)
5950 13:21:48.693432 best DQS1 dly(2T, 0.5T) = (0, 10)
5951 13:21:48.696160 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5952 13:21:48.699436 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5953 13:21:48.702722 Pre-setting of DQS Precalculation
5954 13:21:48.710034 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5955 13:21:48.716015 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5956 13:21:48.722735 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5957 13:21:48.722820
5958 13:21:48.722886
5959 13:21:48.726711 [Calibration Summary] 1866 Mbps
5960 13:21:48.726812 CH 0, Rank 0
5961 13:21:48.729388 SW Impedance : PASS
5962 13:21:48.732764 DUTY Scan : NO K
5963 13:21:48.732862 ZQ Calibration : PASS
5964 13:21:48.736441 Jitter Meter : NO K
5965 13:21:48.739678 CBT Training : PASS
5966 13:21:48.739761 Write leveling : PASS
5967 13:21:48.742707 RX DQS gating : PASS
5968 13:21:48.745990 RX DQ/DQS(RDDQC) : PASS
5969 13:21:48.746075 TX DQ/DQS : PASS
5970 13:21:48.749564 RX DATLAT : PASS
5971 13:21:48.752975 RX DQ/DQS(Engine): PASS
5972 13:21:48.753060 TX OE : NO K
5973 13:21:48.753128 All Pass.
5974 13:21:48.756398
5975 13:21:48.756482 CH 0, Rank 1
5976 13:21:48.759560 SW Impedance : PASS
5977 13:21:48.759644 DUTY Scan : NO K
5978 13:21:48.763151 ZQ Calibration : PASS
5979 13:21:48.763236 Jitter Meter : NO K
5980 13:21:48.766103 CBT Training : PASS
5981 13:21:48.769814 Write leveling : PASS
5982 13:21:48.769898 RX DQS gating : PASS
5983 13:21:48.773217 RX DQ/DQS(RDDQC) : PASS
5984 13:21:48.776321 TX DQ/DQS : PASS
5985 13:21:48.776406 RX DATLAT : PASS
5986 13:21:48.780032 RX DQ/DQS(Engine): PASS
5987 13:21:48.782866 TX OE : NO K
5988 13:21:48.782986 All Pass.
5989 13:21:48.783079
5990 13:21:48.783169 CH 1, Rank 0
5991 13:21:48.786123 SW Impedance : PASS
5992 13:21:48.789484 DUTY Scan : NO K
5993 13:21:48.789568 ZQ Calibration : PASS
5994 13:21:48.792773 Jitter Meter : NO K
5995 13:21:48.796087 CBT Training : PASS
5996 13:21:48.796171 Write leveling : PASS
5997 13:21:48.799548 RX DQS gating : PASS
5998 13:21:48.803052 RX DQ/DQS(RDDQC) : PASS
5999 13:21:48.803137 TX DQ/DQS : PASS
6000 13:21:48.806189 RX DATLAT : PASS
6001 13:21:48.806277 RX DQ/DQS(Engine): PASS
6002 13:21:48.809304 TX OE : NO K
6003 13:21:48.809388 All Pass.
6004 13:21:48.809455
6005 13:21:48.812626 CH 1, Rank 1
6006 13:21:48.812710 SW Impedance : PASS
6007 13:21:48.816251 DUTY Scan : NO K
6008 13:21:48.819414 ZQ Calibration : PASS
6009 13:21:48.819498 Jitter Meter : NO K
6010 13:21:48.822723 CBT Training : PASS
6011 13:21:48.826056 Write leveling : PASS
6012 13:21:48.826158 RX DQS gating : PASS
6013 13:21:48.829252 RX DQ/DQS(RDDQC) : PASS
6014 13:21:48.832503 TX DQ/DQS : PASS
6015 13:21:48.832588 RX DATLAT : PASS
6016 13:21:48.836015 RX DQ/DQS(Engine): PASS
6017 13:21:48.839356 TX OE : NO K
6018 13:21:48.839456 All Pass.
6019 13:21:48.839538
6020 13:21:48.839600 DramC Write-DBI off
6021 13:21:48.843276 PER_BANK_REFRESH: Hybrid Mode
6022 13:21:48.845845 TX_TRACKING: ON
6023 13:21:48.852453 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6024 13:21:48.859255 [FAST_K] Save calibration result to emmc
6025 13:21:48.862525 dramc_set_vcore_voltage set vcore to 650000
6026 13:21:48.862615 Read voltage for 400, 6
6027 13:21:48.865729 Vio18 = 0
6028 13:21:48.865800 Vcore = 650000
6029 13:21:48.865863 Vdram = 0
6030 13:21:48.869350 Vddq = 0
6031 13:21:48.869432 Vmddr = 0
6032 13:21:48.872873 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6033 13:21:48.879040 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6034 13:21:48.882893 MEM_TYPE=3, freq_sel=20
6035 13:21:48.882995 sv_algorithm_assistance_LP4_800
6036 13:21:48.889154 ============ PULL DRAM RESETB DOWN ============
6037 13:21:48.892809 ========== PULL DRAM RESETB DOWN end =========
6038 13:21:48.895908 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6039 13:21:48.899297 ===================================
6040 13:21:48.902689 LPDDR4 DRAM CONFIGURATION
6041 13:21:48.906158 ===================================
6042 13:21:48.909254 EX_ROW_EN[0] = 0x0
6043 13:21:48.909329 EX_ROW_EN[1] = 0x0
6044 13:21:48.912883 LP4Y_EN = 0x0
6045 13:21:48.912968 WORK_FSP = 0x0
6046 13:21:48.916099 WL = 0x2
6047 13:21:48.916183 RL = 0x2
6048 13:21:48.919147 BL = 0x2
6049 13:21:48.919235 RPST = 0x0
6050 13:21:48.922591 RD_PRE = 0x0
6051 13:21:48.922677 WR_PRE = 0x1
6052 13:21:48.926086 WR_PST = 0x0
6053 13:21:48.926184 DBI_WR = 0x0
6054 13:21:48.929037 DBI_RD = 0x0
6055 13:21:48.929151 OTF = 0x1
6056 13:21:48.932303 ===================================
6057 13:21:48.936015 ===================================
6058 13:21:48.938969 ANA top config
6059 13:21:48.942280 ===================================
6060 13:21:48.945597 DLL_ASYNC_EN = 0
6061 13:21:48.945672 ALL_SLAVE_EN = 1
6062 13:21:48.948795 NEW_RANK_MODE = 1
6063 13:21:48.952272 DLL_IDLE_MODE = 1
6064 13:21:48.955692 LP45_APHY_COMB_EN = 1
6065 13:21:48.958954 TX_ODT_DIS = 1
6066 13:21:48.959030 NEW_8X_MODE = 1
6067 13:21:48.962234 ===================================
6068 13:21:48.965478 ===================================
6069 13:21:48.968963 data_rate = 800
6070 13:21:48.971980 CKR = 1
6071 13:21:48.975678 DQ_P2S_RATIO = 4
6072 13:21:48.978857 ===================================
6073 13:21:48.982385 CA_P2S_RATIO = 4
6074 13:21:48.985727 DQ_CA_OPEN = 0
6075 13:21:48.985812 DQ_SEMI_OPEN = 1
6076 13:21:48.988628 CA_SEMI_OPEN = 1
6077 13:21:48.992422 CA_FULL_RATE = 0
6078 13:21:48.995480 DQ_CKDIV4_EN = 0
6079 13:21:48.999016 CA_CKDIV4_EN = 1
6080 13:21:48.999114 CA_PREDIV_EN = 0
6081 13:21:49.002176 PH8_DLY = 0
6082 13:21:49.005744 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6083 13:21:49.008945 DQ_AAMCK_DIV = 0
6084 13:21:49.012130 CA_AAMCK_DIV = 0
6085 13:21:49.015354 CA_ADMCK_DIV = 4
6086 13:21:49.015430 DQ_TRACK_CA_EN = 0
6087 13:21:49.018957 CA_PICK = 800
6088 13:21:49.022498 CA_MCKIO = 400
6089 13:21:49.025318 MCKIO_SEMI = 400
6090 13:21:49.028945 PLL_FREQ = 3016
6091 13:21:49.032127 DQ_UI_PI_RATIO = 32
6092 13:21:49.035538 CA_UI_PI_RATIO = 32
6093 13:21:49.038610 ===================================
6094 13:21:49.042186 ===================================
6095 13:21:49.042267 memory_type:LPDDR4
6096 13:21:49.045485 GP_NUM : 10
6097 13:21:49.048873 SRAM_EN : 1
6098 13:21:49.048957 MD32_EN : 0
6099 13:21:49.051947 ===================================
6100 13:21:49.055590 [ANA_INIT] >>>>>>>>>>>>>>
6101 13:21:49.059064 <<<<<< [CONFIGURE PHASE]: ANA_TX
6102 13:21:49.062330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6103 13:21:49.065438 ===================================
6104 13:21:49.068927 data_rate = 800,PCW = 0X7400
6105 13:21:49.072409 ===================================
6106 13:21:49.075433 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6107 13:21:49.078540 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6108 13:21:49.092009 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6109 13:21:49.095191 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6110 13:21:49.098918 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6111 13:21:49.102120 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6112 13:21:49.105349 [ANA_INIT] flow start
6113 13:21:49.105454 [ANA_INIT] PLL >>>>>>>>
6114 13:21:49.108932 [ANA_INIT] PLL <<<<<<<<
6115 13:21:49.112073 [ANA_INIT] MIDPI >>>>>>>>
6116 13:21:49.115393 [ANA_INIT] MIDPI <<<<<<<<
6117 13:21:49.115494 [ANA_INIT] DLL >>>>>>>>
6118 13:21:49.118805 [ANA_INIT] flow end
6119 13:21:49.122754 ============ LP4 DIFF to SE enter ============
6120 13:21:49.125396 ============ LP4 DIFF to SE exit ============
6121 13:21:49.128873 [ANA_INIT] <<<<<<<<<<<<<
6122 13:21:49.132173 [Flow] Enable top DCM control >>>>>
6123 13:21:49.135337 [Flow] Enable top DCM control <<<<<
6124 13:21:49.138979 Enable DLL master slave shuffle
6125 13:21:49.142344 ==============================================================
6126 13:21:49.145729 Gating Mode config
6127 13:21:49.152271 ==============================================================
6128 13:21:49.152354 Config description:
6129 13:21:49.162205 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6130 13:21:49.169223 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6131 13:21:49.175750 SELPH_MODE 0: By rank 1: By Phase
6132 13:21:49.178809 ==============================================================
6133 13:21:49.182212 GAT_TRACK_EN = 0
6134 13:21:49.185402 RX_GATING_MODE = 2
6135 13:21:49.189039 RX_GATING_TRACK_MODE = 2
6136 13:21:49.192227 SELPH_MODE = 1
6137 13:21:49.195844 PICG_EARLY_EN = 1
6138 13:21:49.198716 VALID_LAT_VALUE = 1
6139 13:21:49.202300 ==============================================================
6140 13:21:49.205386 Enter into Gating configuration >>>>
6141 13:21:49.209001 Exit from Gating configuration <<<<
6142 13:21:49.211990 Enter into DVFS_PRE_config >>>>>
6143 13:21:49.225505 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6144 13:21:49.225610 Exit from DVFS_PRE_config <<<<<
6145 13:21:49.228915 Enter into PICG configuration >>>>
6146 13:21:49.232064 Exit from PICG configuration <<<<
6147 13:21:49.235462 [RX_INPUT] configuration >>>>>
6148 13:21:49.238811 [RX_INPUT] configuration <<<<<
6149 13:21:49.245447 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6150 13:21:49.248728 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6151 13:21:49.255196 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6152 13:21:49.261896 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6153 13:21:49.268647 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6154 13:21:49.275276 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6155 13:21:49.278710 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6156 13:21:49.282169 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6157 13:21:49.285244 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6158 13:21:49.292181 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6159 13:21:49.295404 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6160 13:21:49.298749 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6161 13:21:49.301846 ===================================
6162 13:21:49.305289 LPDDR4 DRAM CONFIGURATION
6163 13:21:49.308529 ===================================
6164 13:21:49.308622 EX_ROW_EN[0] = 0x0
6165 13:21:49.311753 EX_ROW_EN[1] = 0x0
6166 13:21:49.315155 LP4Y_EN = 0x0
6167 13:21:49.315239 WORK_FSP = 0x0
6168 13:21:49.318601 WL = 0x2
6169 13:21:49.318685 RL = 0x2
6170 13:21:49.321923 BL = 0x2
6171 13:21:49.322009 RPST = 0x0
6172 13:21:49.324993 RD_PRE = 0x0
6173 13:21:49.325077 WR_PRE = 0x1
6174 13:21:49.328790 WR_PST = 0x0
6175 13:21:49.328873 DBI_WR = 0x0
6176 13:21:49.331848 DBI_RD = 0x0
6177 13:21:49.331931 OTF = 0x1
6178 13:21:49.335170 ===================================
6179 13:21:49.338502 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6180 13:21:49.344994 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6181 13:21:49.348310 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6182 13:21:49.351740 ===================================
6183 13:21:49.355319 LPDDR4 DRAM CONFIGURATION
6184 13:21:49.358504 ===================================
6185 13:21:49.358588 EX_ROW_EN[0] = 0x10
6186 13:21:49.361638 EX_ROW_EN[1] = 0x0
6187 13:21:49.361725 LP4Y_EN = 0x0
6188 13:21:49.364910 WORK_FSP = 0x0
6189 13:21:49.368368 WL = 0x2
6190 13:21:49.368455 RL = 0x2
6191 13:21:49.371662 BL = 0x2
6192 13:21:49.371747 RPST = 0x0
6193 13:21:49.375249 RD_PRE = 0x0
6194 13:21:49.375334 WR_PRE = 0x1
6195 13:21:49.379156 WR_PST = 0x0
6196 13:21:49.379246 DBI_WR = 0x0
6197 13:21:49.381668 DBI_RD = 0x0
6198 13:21:49.381791 OTF = 0x1
6199 13:21:49.384985 ===================================
6200 13:21:49.391718 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6201 13:21:49.395534 nWR fixed to 30
6202 13:21:49.399570 [ModeRegInit_LP4] CH0 RK0
6203 13:21:49.399685 [ModeRegInit_LP4] CH0 RK1
6204 13:21:49.402041 [ModeRegInit_LP4] CH1 RK0
6205 13:21:49.405657 [ModeRegInit_LP4] CH1 RK1
6206 13:21:49.405741 match AC timing 19
6207 13:21:49.412468 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6208 13:21:49.415765 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6209 13:21:49.418736 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6210 13:21:49.425343 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6211 13:21:49.428997 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6212 13:21:49.429098 ==
6213 13:21:49.432174 Dram Type= 6, Freq= 0, CH_0, rank 0
6214 13:21:49.435515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6215 13:21:49.435616 ==
6216 13:21:49.442360 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6217 13:21:49.448618 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6218 13:21:49.452183 [CA 0] Center 36 (8~64) winsize 57
6219 13:21:49.455482 [CA 1] Center 36 (8~64) winsize 57
6220 13:21:49.458783 [CA 2] Center 36 (8~64) winsize 57
6221 13:21:49.458868 [CA 3] Center 36 (8~64) winsize 57
6222 13:21:49.462425 [CA 4] Center 36 (8~64) winsize 57
6223 13:21:49.466009 [CA 5] Center 36 (8~64) winsize 57
6224 13:21:49.466096
6225 13:21:49.469226 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6226 13:21:49.471997
6227 13:21:49.475709 [CATrainingPosCal] consider 1 rank data
6228 13:21:49.475794 u2DelayCellTimex100 = 270/100 ps
6229 13:21:49.482356 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 13:21:49.485275 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 13:21:49.488614 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 13:21:49.491969 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 13:21:49.495208 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 13:21:49.498591 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 13:21:49.498677
6236 13:21:49.501891 CA PerBit enable=1, Macro0, CA PI delay=36
6237 13:21:49.501977
6238 13:21:49.505197 [CBTSetCACLKResult] CA Dly = 36
6239 13:21:49.508517 CS Dly: 1 (0~32)
6240 13:21:49.508629 ==
6241 13:21:49.511994 Dram Type= 6, Freq= 0, CH_0, rank 1
6242 13:21:49.515286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6243 13:21:49.515399 ==
6244 13:21:49.522254 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6245 13:21:49.525193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6246 13:21:49.528403 [CA 0] Center 36 (8~64) winsize 57
6247 13:21:49.531879 [CA 1] Center 36 (8~64) winsize 57
6248 13:21:49.535249 [CA 2] Center 36 (8~64) winsize 57
6249 13:21:49.538422 [CA 3] Center 36 (8~64) winsize 57
6250 13:21:49.541739 [CA 4] Center 36 (8~64) winsize 57
6251 13:21:49.545023 [CA 5] Center 36 (8~64) winsize 57
6252 13:21:49.545109
6253 13:21:49.548206 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6254 13:21:49.548308
6255 13:21:49.551623 [CATrainingPosCal] consider 2 rank data
6256 13:21:49.554974 u2DelayCellTimex100 = 270/100 ps
6257 13:21:49.558591 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 13:21:49.562179 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 13:21:49.564993 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 13:21:49.571841 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 13:21:49.575041 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 13:21:49.578210 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 13:21:49.578295
6264 13:21:49.581913 CA PerBit enable=1, Macro0, CA PI delay=36
6265 13:21:49.581998
6266 13:21:49.584768 [CBTSetCACLKResult] CA Dly = 36
6267 13:21:49.584853 CS Dly: 1 (0~32)
6268 13:21:49.584917
6269 13:21:49.588269 ----->DramcWriteLeveling(PI) begin...
6270 13:21:49.588354 ==
6271 13:21:49.594782 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 13:21:49.597954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 13:21:49.598041 ==
6274 13:21:49.601398 Write leveling (Byte 0): 40 => 8
6275 13:21:49.604610 Write leveling (Byte 1): 32 => 0
6276 13:21:49.604696 DramcWriteLeveling(PI) end<-----
6277 13:21:49.607869
6278 13:21:49.607986 ==
6279 13:21:49.611393 Dram Type= 6, Freq= 0, CH_0, rank 0
6280 13:21:49.614472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6281 13:21:49.614581 ==
6282 13:21:49.618118 [Gating] SW mode calibration
6283 13:21:49.624324 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6284 13:21:49.627861 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6285 13:21:49.634796 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6286 13:21:49.638151 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6287 13:21:49.641012 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6288 13:21:49.647649 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 13:21:49.651051 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 13:21:49.654300 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 13:21:49.660962 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 13:21:49.664167 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 13:21:49.667576 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6294 13:21:49.671122 Total UI for P1: 0, mck2ui 16
6295 13:21:49.674143 best dqsien dly found for B0: ( 0, 14, 24)
6296 13:21:49.677639 Total UI for P1: 0, mck2ui 16
6297 13:21:49.681001 best dqsien dly found for B1: ( 0, 14, 24)
6298 13:21:49.684542 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6299 13:21:49.687714 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6300 13:21:49.690966
6301 13:21:49.694391 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6302 13:21:49.697523 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6303 13:21:49.701050 [Gating] SW calibration Done
6304 13:21:49.701158 ==
6305 13:21:49.704393 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 13:21:49.708020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 13:21:49.708102 ==
6308 13:21:49.708167 RX Vref Scan: 0
6309 13:21:49.708229
6310 13:21:49.711061 RX Vref 0 -> 0, step: 1
6311 13:21:49.711143
6312 13:21:49.714243 RX Delay -410 -> 252, step: 16
6313 13:21:49.717975 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6314 13:21:49.724474 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6315 13:21:49.727691 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6316 13:21:49.730836 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6317 13:21:49.734456 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6318 13:21:49.740976 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6319 13:21:49.744166 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6320 13:21:49.747815 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6321 13:21:49.751262 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6322 13:21:49.754507 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6323 13:21:49.760902 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6324 13:21:49.764442 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6325 13:21:49.767576 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6326 13:21:49.774267 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6327 13:21:49.777664 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6328 13:21:49.780901 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6329 13:21:49.780983 ==
6330 13:21:49.784233 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 13:21:49.787596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 13:21:49.787679 ==
6333 13:21:49.790905 DQS Delay:
6334 13:21:49.790986 DQS0 = 27, DQS1 = 43
6335 13:21:49.794524 DQM Delay:
6336 13:21:49.794632 DQM0 = 13, DQM1 = 12
6337 13:21:49.798336 DQ Delay:
6338 13:21:49.798417 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =8
6339 13:21:49.800883 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6340 13:21:49.804338 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6341 13:21:49.807867 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6342 13:21:49.807975
6343 13:21:49.808054
6344 13:21:49.808115 ==
6345 13:21:49.810850 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 13:21:49.817430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 13:21:49.817519 ==
6348 13:21:49.817585
6349 13:21:49.817647
6350 13:21:49.817706 TX Vref Scan disable
6351 13:21:49.820672 == TX Byte 0 ==
6352 13:21:49.824182 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6353 13:21:49.827357 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6354 13:21:49.830581 == TX Byte 1 ==
6355 13:21:49.834317 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6356 13:21:49.837124 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6357 13:21:49.840720 ==
6358 13:21:49.844316 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 13:21:49.847289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 13:21:49.847397 ==
6361 13:21:49.847475
6362 13:21:49.847580
6363 13:21:49.850712 TX Vref Scan disable
6364 13:21:49.850812 == TX Byte 0 ==
6365 13:21:49.853929 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6366 13:21:49.860944 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6367 13:21:49.861028 == TX Byte 1 ==
6368 13:21:49.863985 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6369 13:21:49.870869 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6370 13:21:49.870953
6371 13:21:49.871019 [DATLAT]
6372 13:21:49.871083 Freq=400, CH0 RK0
6373 13:21:49.871144
6374 13:21:49.874190 DATLAT Default: 0xf
6375 13:21:49.874304 0, 0xFFFF, sum = 0
6376 13:21:49.877381 1, 0xFFFF, sum = 0
6377 13:21:49.881058 2, 0xFFFF, sum = 0
6378 13:21:49.881143 3, 0xFFFF, sum = 0
6379 13:21:49.883886 4, 0xFFFF, sum = 0
6380 13:21:49.884005 5, 0xFFFF, sum = 0
6381 13:21:49.887225 6, 0xFFFF, sum = 0
6382 13:21:49.887309 7, 0xFFFF, sum = 0
6383 13:21:49.890479 8, 0xFFFF, sum = 0
6384 13:21:49.890564 9, 0xFFFF, sum = 0
6385 13:21:49.893742 10, 0xFFFF, sum = 0
6386 13:21:49.893827 11, 0xFFFF, sum = 0
6387 13:21:49.897071 12, 0xFFFF, sum = 0
6388 13:21:49.897155 13, 0x0, sum = 1
6389 13:21:49.900599 14, 0x0, sum = 2
6390 13:21:49.900684 15, 0x0, sum = 3
6391 13:21:49.904274 16, 0x0, sum = 4
6392 13:21:49.904359 best_step = 14
6393 13:21:49.904426
6394 13:21:49.904488 ==
6395 13:21:49.906984 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 13:21:49.910649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 13:21:49.913830 ==
6398 13:21:49.913961 RX Vref Scan: 1
6399 13:21:49.914074
6400 13:21:49.917219 RX Vref 0 -> 0, step: 1
6401 13:21:49.917303
6402 13:21:49.920654 RX Delay -327 -> 252, step: 8
6403 13:21:49.920760
6404 13:21:49.920843 Set Vref, RX VrefLevel [Byte0]: 59
6405 13:21:49.923672 [Byte1]: 50
6406 13:21:49.929451
6407 13:21:49.929538 Final RX Vref Byte 0 = 59 to rank0
6408 13:21:49.932961 Final RX Vref Byte 1 = 50 to rank0
6409 13:21:49.935972 Final RX Vref Byte 0 = 59 to rank1
6410 13:21:49.939374 Final RX Vref Byte 1 = 50 to rank1==
6411 13:21:49.942821 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 13:21:49.949516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 13:21:49.949615 ==
6414 13:21:49.949697 DQS Delay:
6415 13:21:49.952588 DQS0 = 24, DQS1 = 48
6416 13:21:49.952672 DQM Delay:
6417 13:21:49.952740 DQM0 = 9, DQM1 = 15
6418 13:21:49.956272 DQ Delay:
6419 13:21:49.959459 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6420 13:21:49.959543 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6421 13:21:49.962494 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6422 13:21:49.965950 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6423 13:21:49.966064
6424 13:21:49.966130
6425 13:21:49.976194 [DQSOSCAuto] RK0, (LSB)MR18= 0xafa7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6426 13:21:49.979016 CH0 RK0: MR19=C0C, MR18=AFA7
6427 13:21:49.986193 CH0_RK0: MR19=0xC0C, MR18=0xAFA7, DQSOSC=388, MR23=63, INC=392, DEC=261
6428 13:21:49.986278 ==
6429 13:21:49.989504 Dram Type= 6, Freq= 0, CH_0, rank 1
6430 13:21:49.992731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 13:21:49.992854 ==
6432 13:21:49.995792 [Gating] SW mode calibration
6433 13:21:50.002673 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6434 13:21:50.005801 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6435 13:21:50.012365 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6436 13:21:50.015733 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6437 13:21:50.018975 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6438 13:21:50.025725 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 13:21:50.029173 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 13:21:50.032194 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 13:21:50.039382 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 13:21:50.042261 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 13:21:50.045859 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6444 13:21:50.048891 Total UI for P1: 0, mck2ui 16
6445 13:21:50.052257 best dqsien dly found for B0: ( 0, 14, 24)
6446 13:21:50.055724 Total UI for P1: 0, mck2ui 16
6447 13:21:50.059260 best dqsien dly found for B1: ( 0, 14, 24)
6448 13:21:50.062291 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6449 13:21:50.065629 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6450 13:21:50.065741
6451 13:21:50.072177 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6452 13:21:50.075513 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6453 13:21:50.078885 [Gating] SW calibration Done
6454 13:21:50.079009 ==
6455 13:21:50.082249 Dram Type= 6, Freq= 0, CH_0, rank 1
6456 13:21:50.085521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 13:21:50.085642 ==
6458 13:21:50.085757 RX Vref Scan: 0
6459 13:21:50.085868
6460 13:21:50.088700 RX Vref 0 -> 0, step: 1
6461 13:21:50.088818
6462 13:21:50.092016 RX Delay -410 -> 252, step: 16
6463 13:21:50.095625 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6464 13:21:50.102045 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6465 13:21:50.105512 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6466 13:21:50.109208 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6467 13:21:50.112179 iDelay=230, Bit 4, Center -11 (-234 ~ 213) 448
6468 13:21:50.118789 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6469 13:21:50.122185 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6470 13:21:50.125810 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6471 13:21:50.129242 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6472 13:21:50.132425 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6473 13:21:50.139451 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6474 13:21:50.142214 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6475 13:21:50.145557 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6476 13:21:50.151841 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6477 13:21:50.155320 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6478 13:21:50.158760 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6479 13:21:50.158867 ==
6480 13:21:50.162314 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 13:21:50.165313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 13:21:50.165400 ==
6483 13:21:50.168890 DQS Delay:
6484 13:21:50.168976 DQS0 = 27, DQS1 = 43
6485 13:21:50.172068 DQM Delay:
6486 13:21:50.172154 DQM0 = 12, DQM1 = 16
6487 13:21:50.175307 DQ Delay:
6488 13:21:50.175394 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6489 13:21:50.178598 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6490 13:21:50.181904 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6491 13:21:50.185241 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6492 13:21:50.185327
6493 13:21:50.185396
6494 13:21:50.185460 ==
6495 13:21:50.188621 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 13:21:50.195463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 13:21:50.195550 ==
6498 13:21:50.195619
6499 13:21:50.195683
6500 13:21:50.195744 TX Vref Scan disable
6501 13:21:50.199114 == TX Byte 0 ==
6502 13:21:50.201706 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6503 13:21:50.205187 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6504 13:21:50.208503 == TX Byte 1 ==
6505 13:21:50.211800 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6506 13:21:50.215465 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6507 13:21:50.215551 ==
6508 13:21:50.218718 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 13:21:50.225357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 13:21:50.225443 ==
6511 13:21:50.225510
6512 13:21:50.225574
6513 13:21:50.225635 TX Vref Scan disable
6514 13:21:50.228518 == TX Byte 0 ==
6515 13:21:50.232215 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6516 13:21:50.235181 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6517 13:21:50.238876 == TX Byte 1 ==
6518 13:21:50.241861 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6519 13:21:50.245047 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6520 13:21:50.245158
6521 13:21:50.248325 [DATLAT]
6522 13:21:50.248417 Freq=400, CH0 RK1
6523 13:21:50.248490
6524 13:21:50.251978 DATLAT Default: 0xe
6525 13:21:50.252086 0, 0xFFFF, sum = 0
6526 13:21:50.255410 1, 0xFFFF, sum = 0
6527 13:21:50.255520 2, 0xFFFF, sum = 0
6528 13:21:50.258533 3, 0xFFFF, sum = 0
6529 13:21:50.258630 4, 0xFFFF, sum = 0
6530 13:21:50.261863 5, 0xFFFF, sum = 0
6531 13:21:50.261966 6, 0xFFFF, sum = 0
6532 13:21:50.265371 7, 0xFFFF, sum = 0
6533 13:21:50.265468 8, 0xFFFF, sum = 0
6534 13:21:50.268738 9, 0xFFFF, sum = 0
6535 13:21:50.268821 10, 0xFFFF, sum = 0
6536 13:21:50.271634 11, 0xFFFF, sum = 0
6537 13:21:50.275047 12, 0xFFFF, sum = 0
6538 13:21:50.275152 13, 0x0, sum = 1
6539 13:21:50.278651 14, 0x0, sum = 2
6540 13:21:50.278753 15, 0x0, sum = 3
6541 13:21:50.278848 16, 0x0, sum = 4
6542 13:21:50.281882 best_step = 14
6543 13:21:50.281980
6544 13:21:50.282081 ==
6545 13:21:50.285051 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 13:21:50.288330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 13:21:50.288436 ==
6548 13:21:50.291797 RX Vref Scan: 0
6549 13:21:50.291903
6550 13:21:50.291995 RX Vref 0 -> 0, step: 1
6551 13:21:50.295285
6552 13:21:50.295385 RX Delay -327 -> 252, step: 8
6553 13:21:50.303224 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6554 13:21:50.306755 iDelay=217, Bit 1, Center -20 (-247 ~ 208) 456
6555 13:21:50.310059 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6556 13:21:50.313193 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6557 13:21:50.320132 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6558 13:21:50.323265 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6559 13:21:50.326454 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6560 13:21:50.329881 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6561 13:21:50.336629 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6562 13:21:50.339977 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6563 13:21:50.343252 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6564 13:21:50.346649 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6565 13:21:50.353280 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6566 13:21:50.356516 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6567 13:21:50.360023 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6568 13:21:50.366727 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6569 13:21:50.366812 ==
6570 13:21:50.369974 Dram Type= 6, Freq= 0, CH_0, rank 1
6571 13:21:50.373067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6572 13:21:50.373153 ==
6573 13:21:50.373251 DQS Delay:
6574 13:21:50.376612 DQS0 = 28, DQS1 = 40
6575 13:21:50.376689 DQM Delay:
6576 13:21:50.379925 DQM0 = 9, DQM1 = 12
6577 13:21:50.380038 DQ Delay:
6578 13:21:50.383266 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6579 13:21:50.386697 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6580 13:21:50.389935 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6581 13:21:50.393326 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =20
6582 13:21:50.393411
6583 13:21:50.393478
6584 13:21:50.399713 [DQSOSCAuto] RK1, (LSB)MR18= 0xb86d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 386 ps
6585 13:21:50.403491 CH0 RK1: MR19=C0C, MR18=B86D
6586 13:21:50.409752 CH0_RK1: MR19=0xC0C, MR18=0xB86D, DQSOSC=386, MR23=63, INC=396, DEC=264
6587 13:21:50.413297 [RxdqsGatingPostProcess] freq 400
6588 13:21:50.416527 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6589 13:21:50.419899 best DQS0 dly(2T, 0.5T) = (0, 10)
6590 13:21:50.423263 best DQS1 dly(2T, 0.5T) = (0, 10)
6591 13:21:50.426385 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6592 13:21:50.429690 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6593 13:21:50.432988 best DQS0 dly(2T, 0.5T) = (0, 10)
6594 13:21:50.436323 best DQS1 dly(2T, 0.5T) = (0, 10)
6595 13:21:50.439683 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6596 13:21:50.443263 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6597 13:21:50.446768 Pre-setting of DQS Precalculation
6598 13:21:50.450194 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6599 13:21:50.450318 ==
6600 13:21:50.453467 Dram Type= 6, Freq= 0, CH_1, rank 0
6601 13:21:50.460317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 13:21:50.460454 ==
6603 13:21:50.463256 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6604 13:21:50.469947 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6605 13:21:50.473478 [CA 0] Center 36 (8~64) winsize 57
6606 13:21:50.476762 [CA 1] Center 36 (8~64) winsize 57
6607 13:21:50.479795 [CA 2] Center 36 (8~64) winsize 57
6608 13:21:50.483209 [CA 3] Center 36 (8~64) winsize 57
6609 13:21:50.486876 [CA 4] Center 36 (8~64) winsize 57
6610 13:21:50.490092 [CA 5] Center 36 (8~64) winsize 57
6611 13:21:50.490224
6612 13:21:50.493498 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6613 13:21:50.493602
6614 13:21:50.496551 [CATrainingPosCal] consider 1 rank data
6615 13:21:50.499745 u2DelayCellTimex100 = 270/100 ps
6616 13:21:50.503501 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 13:21:50.506677 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 13:21:50.509874 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 13:21:50.513362 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 13:21:50.516407 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 13:21:50.519687 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 13:21:50.519756
6623 13:21:50.526608 CA PerBit enable=1, Macro0, CA PI delay=36
6624 13:21:50.526701
6625 13:21:50.529935 [CBTSetCACLKResult] CA Dly = 36
6626 13:21:50.530004 CS Dly: 1 (0~32)
6627 13:21:50.530066 ==
6628 13:21:50.533106 Dram Type= 6, Freq= 0, CH_1, rank 1
6629 13:21:50.536655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6630 13:21:50.536729 ==
6631 13:21:50.542823 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6632 13:21:50.549861 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6633 13:21:50.552906 [CA 0] Center 36 (8~64) winsize 57
6634 13:21:50.556328 [CA 1] Center 36 (8~64) winsize 57
6635 13:21:50.559609 [CA 2] Center 36 (8~64) winsize 57
6636 13:21:50.562990 [CA 3] Center 36 (8~64) winsize 57
6637 13:21:50.566330 [CA 4] Center 36 (8~64) winsize 57
6638 13:21:50.566412 [CA 5] Center 36 (8~64) winsize 57
6639 13:21:50.569723
6640 13:21:50.572711 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6641 13:21:50.572813
6642 13:21:50.576288 [CATrainingPosCal] consider 2 rank data
6643 13:21:50.579992 u2DelayCellTimex100 = 270/100 ps
6644 13:21:50.582955 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 13:21:50.586380 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 13:21:50.589520 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 13:21:50.592775 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 13:21:50.596014 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 13:21:50.599575 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 13:21:50.599659
6651 13:21:50.602876 CA PerBit enable=1, Macro0, CA PI delay=36
6652 13:21:50.602960
6653 13:21:50.606202 [CBTSetCACLKResult] CA Dly = 36
6654 13:21:50.609664 CS Dly: 1 (0~32)
6655 13:21:50.609748
6656 13:21:50.612655 ----->DramcWriteLeveling(PI) begin...
6657 13:21:50.612743 ==
6658 13:21:50.615936 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 13:21:50.619537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 13:21:50.619623 ==
6661 13:21:50.622797 Write leveling (Byte 0): 40 => 8
6662 13:21:50.626242 Write leveling (Byte 1): 32 => 0
6663 13:21:50.629492 DramcWriteLeveling(PI) end<-----
6664 13:21:50.629576
6665 13:21:50.629658 ==
6666 13:21:50.632808 Dram Type= 6, Freq= 0, CH_1, rank 0
6667 13:21:50.636436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6668 13:21:50.636535 ==
6669 13:21:50.639438 [Gating] SW mode calibration
6670 13:21:50.646193 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6671 13:21:50.652954 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6672 13:21:50.656092 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6673 13:21:50.659560 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6674 13:21:50.666781 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6675 13:21:50.669348 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6676 13:21:50.672874 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 13:21:50.679274 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 13:21:50.682597 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 13:21:50.686302 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 13:21:50.692601 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6681 13:21:50.692704 Total UI for P1: 0, mck2ui 16
6682 13:21:50.699180 best dqsien dly found for B0: ( 0, 14, 24)
6683 13:21:50.699266 Total UI for P1: 0, mck2ui 16
6684 13:21:50.702846 best dqsien dly found for B1: ( 0, 14, 24)
6685 13:21:50.709208 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6686 13:21:50.712960 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6687 13:21:50.713044
6688 13:21:50.716204 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6689 13:21:50.719229 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6690 13:21:50.722603 [Gating] SW calibration Done
6691 13:21:50.722687 ==
6692 13:21:50.726029 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 13:21:50.729257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 13:21:50.729344 ==
6695 13:21:50.732773 RX Vref Scan: 0
6696 13:21:50.732899
6697 13:21:50.732995 RX Vref 0 -> 0, step: 1
6698 13:21:50.733139
6699 13:21:50.735943 RX Delay -410 -> 252, step: 16
6700 13:21:50.742717 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6701 13:21:50.745842 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6702 13:21:50.749327 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6703 13:21:50.752402 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6704 13:21:50.758988 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6705 13:21:50.762406 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6706 13:21:50.765710 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6707 13:21:50.768998 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6708 13:21:50.775481 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6709 13:21:50.778938 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6710 13:21:50.782435 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6711 13:21:50.785587 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6712 13:21:50.792253 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6713 13:21:50.795547 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6714 13:21:50.799127 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6715 13:21:50.802163 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6716 13:21:50.802256 ==
6717 13:21:50.805696 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 13:21:50.812176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 13:21:50.812263 ==
6720 13:21:50.812332 DQS Delay:
6721 13:21:50.815325 DQS0 = 27, DQS1 = 43
6722 13:21:50.815411 DQM Delay:
6723 13:21:50.818751 DQM0 = 5, DQM1 = 15
6724 13:21:50.818838 DQ Delay:
6725 13:21:50.822529 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6726 13:21:50.825459 DQ4 =8, DQ5 =8, DQ6 =16, DQ7 =0
6727 13:21:50.825546 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6728 13:21:50.829024 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6729 13:21:50.832192
6730 13:21:50.832277
6731 13:21:50.832345 ==
6732 13:21:50.835501 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 13:21:50.838813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 13:21:50.838898 ==
6735 13:21:50.838966
6736 13:21:50.839028
6737 13:21:50.842049 TX Vref Scan disable
6738 13:21:50.842133 == TX Byte 0 ==
6739 13:21:50.845685 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6740 13:21:50.852201 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6741 13:21:50.852313 == TX Byte 1 ==
6742 13:21:50.855446 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6743 13:21:50.862081 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6744 13:21:50.862165 ==
6745 13:21:50.865508 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 13:21:50.868648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 13:21:50.868766 ==
6748 13:21:50.868851
6749 13:21:50.868946
6750 13:21:50.872013 TX Vref Scan disable
6751 13:21:50.872096 == TX Byte 0 ==
6752 13:21:50.878619 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6753 13:21:50.881960 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6754 13:21:50.882044 == TX Byte 1 ==
6755 13:21:50.888579 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6756 13:21:50.892034 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6757 13:21:50.892119
6758 13:21:50.892202 [DATLAT]
6759 13:21:50.895334 Freq=400, CH1 RK0
6760 13:21:50.895433
6761 13:21:50.895500 DATLAT Default: 0xf
6762 13:21:50.898694 0, 0xFFFF, sum = 0
6763 13:21:50.898795 1, 0xFFFF, sum = 0
6764 13:21:50.901872 2, 0xFFFF, sum = 0
6765 13:21:50.901957 3, 0xFFFF, sum = 0
6766 13:21:50.905489 4, 0xFFFF, sum = 0
6767 13:21:50.905578 5, 0xFFFF, sum = 0
6768 13:21:50.908965 6, 0xFFFF, sum = 0
6769 13:21:50.909077 7, 0xFFFF, sum = 0
6770 13:21:50.912098 8, 0xFFFF, sum = 0
6771 13:21:50.912185 9, 0xFFFF, sum = 0
6772 13:21:50.915408 10, 0xFFFF, sum = 0
6773 13:21:50.915520 11, 0xFFFF, sum = 0
6774 13:21:50.918617 12, 0xFFFF, sum = 0
6775 13:21:50.918722 13, 0x0, sum = 1
6776 13:21:50.922132 14, 0x0, sum = 2
6777 13:21:50.922218 15, 0x0, sum = 3
6778 13:21:50.925276 16, 0x0, sum = 4
6779 13:21:50.925383 best_step = 14
6780 13:21:50.925474
6781 13:21:50.925569 ==
6782 13:21:50.928954 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 13:21:50.935434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 13:21:50.935520 ==
6785 13:21:50.935593 RX Vref Scan: 1
6786 13:21:50.935657
6787 13:21:50.938922 RX Vref 0 -> 0, step: 1
6788 13:21:50.939024
6789 13:21:50.941827 RX Delay -327 -> 252, step: 8
6790 13:21:50.941903
6791 13:21:50.945339 Set Vref, RX VrefLevel [Byte0]: 53
6792 13:21:50.948641 [Byte1]: 57
6793 13:21:50.948728
6794 13:21:50.952093 Final RX Vref Byte 0 = 53 to rank0
6795 13:21:50.955310 Final RX Vref Byte 1 = 57 to rank0
6796 13:21:50.958666 Final RX Vref Byte 0 = 53 to rank1
6797 13:21:50.962043 Final RX Vref Byte 1 = 57 to rank1==
6798 13:21:50.965502 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 13:21:50.968639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 13:21:50.972100 ==
6801 13:21:50.972201 DQS Delay:
6802 13:21:50.972293 DQS0 = 28, DQS1 = 44
6803 13:21:50.975523 DQM Delay:
6804 13:21:50.975598 DQM0 = 7, DQM1 = 16
6805 13:21:50.978776 DQ Delay:
6806 13:21:50.978852 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6807 13:21:50.982228 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6808 13:21:50.985562 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =16
6809 13:21:50.988820 DQ12 =28, DQ13 =24, DQ14 =20, DQ15 =20
6810 13:21:50.988902
6811 13:21:50.988969
6812 13:21:50.998524 [DQSOSCAuto] RK0, (LSB)MR18= 0x99d3, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6813 13:21:51.001788 CH1 RK0: MR19=C0C, MR18=99D3
6814 13:21:51.005231 CH1_RK0: MR19=0xC0C, MR18=0x99D3, DQSOSC=383, MR23=63, INC=402, DEC=268
6815 13:21:51.008506 ==
6816 13:21:51.011777 Dram Type= 6, Freq= 0, CH_1, rank 1
6817 13:21:51.015405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 13:21:51.015532 ==
6819 13:21:51.018564 [Gating] SW mode calibration
6820 13:21:51.025139 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6821 13:21:51.028570 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6822 13:21:51.035183 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6823 13:21:51.038477 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6824 13:21:51.042100 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6825 13:21:51.048331 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6826 13:21:51.051663 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 13:21:51.054753 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 13:21:51.061772 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 13:21:51.065010 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 13:21:51.068483 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6831 13:21:51.071839 Total UI for P1: 0, mck2ui 16
6832 13:21:51.075011 best dqsien dly found for B0: ( 0, 14, 24)
6833 13:21:51.078278 Total UI for P1: 0, mck2ui 16
6834 13:21:51.081522 best dqsien dly found for B1: ( 0, 14, 24)
6835 13:21:51.085051 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6836 13:21:51.088125 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6837 13:21:51.088210
6838 13:21:51.094663 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6839 13:21:51.098207 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6840 13:21:51.098343 [Gating] SW calibration Done
6841 13:21:51.101602 ==
6842 13:21:51.105121 Dram Type= 6, Freq= 0, CH_1, rank 1
6843 13:21:51.107937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 13:21:51.108070 ==
6845 13:21:51.108185 RX Vref Scan: 0
6846 13:21:51.108325
6847 13:21:51.111255 RX Vref 0 -> 0, step: 1
6848 13:21:51.111341
6849 13:21:51.115055 RX Delay -410 -> 252, step: 16
6850 13:21:51.118292 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6851 13:21:51.121514 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6852 13:21:51.128088 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6853 13:21:51.131475 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6854 13:21:51.134976 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6855 13:21:51.137863 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6856 13:21:51.144470 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6857 13:21:51.147780 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6858 13:21:51.151378 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6859 13:21:51.154558 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6860 13:21:51.161139 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6861 13:21:51.164318 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6862 13:21:51.168000 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6863 13:21:51.174493 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6864 13:21:51.177759 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6865 13:21:51.181375 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6866 13:21:51.181459 ==
6867 13:21:51.184885 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 13:21:51.187748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 13:21:51.187836 ==
6870 13:21:51.191191 DQS Delay:
6871 13:21:51.191274 DQS0 = 27, DQS1 = 43
6872 13:21:51.194669 DQM Delay:
6873 13:21:51.194795 DQM0 = 11, DQM1 = 20
6874 13:21:51.197968 DQ Delay:
6875 13:21:51.198101 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6876 13:21:51.201001 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6877 13:21:51.204264 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6878 13:21:51.207521 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6879 13:21:51.207645
6880 13:21:51.207761
6881 13:21:51.207871 ==
6882 13:21:51.211244 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 13:21:51.217646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 13:21:51.217731 ==
6885 13:21:51.217798
6886 13:21:51.217861
6887 13:21:51.217920 TX Vref Scan disable
6888 13:21:51.220867 == TX Byte 0 ==
6889 13:21:51.224084 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6890 13:21:51.227456 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6891 13:21:51.230590 == TX Byte 1 ==
6892 13:21:51.234263 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6893 13:21:51.237378 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6894 13:21:51.241199 ==
6895 13:21:51.241283 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 13:21:51.247243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 13:21:51.247328 ==
6898 13:21:51.247394
6899 13:21:51.247457
6900 13:21:51.250912 TX Vref Scan disable
6901 13:21:51.251055 == TX Byte 0 ==
6902 13:21:51.254065 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6903 13:21:51.257686 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6904 13:21:51.260602 == TX Byte 1 ==
6905 13:21:51.263889 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6906 13:21:51.267387 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6907 13:21:51.267499
6908 13:21:51.270945 [DATLAT]
6909 13:21:51.271025 Freq=400, CH1 RK1
6910 13:21:51.271112
6911 13:21:51.274228 DATLAT Default: 0xe
6912 13:21:51.274333 0, 0xFFFF, sum = 0
6913 13:21:51.277515 1, 0xFFFF, sum = 0
6914 13:21:51.277597 2, 0xFFFF, sum = 0
6915 13:21:51.280453 3, 0xFFFF, sum = 0
6916 13:21:51.280557 4, 0xFFFF, sum = 0
6917 13:21:51.283862 5, 0xFFFF, sum = 0
6918 13:21:51.283942 6, 0xFFFF, sum = 0
6919 13:21:51.287546 7, 0xFFFF, sum = 0
6920 13:21:51.290604 8, 0xFFFF, sum = 0
6921 13:21:51.290711 9, 0xFFFF, sum = 0
6922 13:21:51.293942 10, 0xFFFF, sum = 0
6923 13:21:51.294045 11, 0xFFFF, sum = 0
6924 13:21:51.297276 12, 0xFFFF, sum = 0
6925 13:21:51.297357 13, 0x0, sum = 1
6926 13:21:51.300554 14, 0x0, sum = 2
6927 13:21:51.300659 15, 0x0, sum = 3
6928 13:21:51.303778 16, 0x0, sum = 4
6929 13:21:51.303876 best_step = 14
6930 13:21:51.303957
6931 13:21:51.304033 ==
6932 13:21:51.307252 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 13:21:51.310292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 13:21:51.310396 ==
6935 13:21:51.313853 RX Vref Scan: 0
6936 13:21:51.313945
6937 13:21:51.317035 RX Vref 0 -> 0, step: 1
6938 13:21:51.317115
6939 13:21:51.317214 RX Delay -327 -> 252, step: 8
6940 13:21:51.325634 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6941 13:21:51.329015 iDelay=217, Bit 1, Center -24 (-239 ~ 192) 432
6942 13:21:51.332516 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6943 13:21:51.336034 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6944 13:21:51.342379 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6945 13:21:51.345625 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6946 13:21:51.349166 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6947 13:21:51.352417 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6948 13:21:51.359033 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6949 13:21:51.362218 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6950 13:21:51.365742 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6951 13:21:51.369208 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6952 13:21:51.375400 iDelay=217, Bit 12, Center -16 (-247 ~ 216) 464
6953 13:21:51.379259 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6954 13:21:51.382204 iDelay=217, Bit 14, Center -24 (-255 ~ 208) 464
6955 13:21:51.389145 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6956 13:21:51.389290 ==
6957 13:21:51.392207 Dram Type= 6, Freq= 0, CH_1, rank 1
6958 13:21:51.395346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6959 13:21:51.395469 ==
6960 13:21:51.395582 DQS Delay:
6961 13:21:51.398768 DQS0 = 32, DQS1 = 36
6962 13:21:51.398894 DQM Delay:
6963 13:21:51.401943 DQM0 = 12, DQM1 = 10
6964 13:21:51.402066 DQ Delay:
6965 13:21:51.405476 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6966 13:21:51.408890 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =8
6967 13:21:51.412029 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6968 13:21:51.415483 DQ12 =20, DQ13 =16, DQ14 =12, DQ15 =20
6969 13:21:51.415606
6970 13:21:51.415720
6971 13:21:51.422061 [DQSOSCAuto] RK1, (LSB)MR18= 0xaf56, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 388 ps
6972 13:21:51.425263 CH1 RK1: MR19=C0C, MR18=AF56
6973 13:21:51.431987 CH1_RK1: MR19=0xC0C, MR18=0xAF56, DQSOSC=388, MR23=63, INC=392, DEC=261
6974 13:21:51.435301 [RxdqsGatingPostProcess] freq 400
6975 13:21:51.441743 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6976 13:21:51.441828 best DQS0 dly(2T, 0.5T) = (0, 10)
6977 13:21:51.445567 best DQS1 dly(2T, 0.5T) = (0, 10)
6978 13:21:51.448680 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6979 13:21:51.451908 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6980 13:21:51.455448 best DQS0 dly(2T, 0.5T) = (0, 10)
6981 13:21:51.458801 best DQS1 dly(2T, 0.5T) = (0, 10)
6982 13:21:51.462008 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6983 13:21:51.465342 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6984 13:21:51.468667 Pre-setting of DQS Precalculation
6985 13:21:51.475401 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6986 13:21:51.481825 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6987 13:21:51.488500 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6988 13:21:51.488626
6989 13:21:51.488742
6990 13:21:51.491953 [Calibration Summary] 800 Mbps
6991 13:21:51.492077 CH 0, Rank 0
6992 13:21:51.495031 SW Impedance : PASS
6993 13:21:51.495153 DUTY Scan : NO K
6994 13:21:51.498325 ZQ Calibration : PASS
6995 13:21:51.502105 Jitter Meter : NO K
6996 13:21:51.502211 CBT Training : PASS
6997 13:21:51.505058 Write leveling : PASS
6998 13:21:51.508675 RX DQS gating : PASS
6999 13:21:51.508841 RX DQ/DQS(RDDQC) : PASS
7000 13:21:51.511761 TX DQ/DQS : PASS
7001 13:21:51.515135 RX DATLAT : PASS
7002 13:21:51.515262 RX DQ/DQS(Engine): PASS
7003 13:21:51.518312 TX OE : NO K
7004 13:21:51.518438 All Pass.
7005 13:21:51.518553
7006 13:21:51.521945 CH 0, Rank 1
7007 13:21:51.522103 SW Impedance : PASS
7008 13:21:51.525040 DUTY Scan : NO K
7009 13:21:51.528212 ZQ Calibration : PASS
7010 13:21:51.528334 Jitter Meter : NO K
7011 13:21:51.531523 CBT Training : PASS
7012 13:21:51.535188 Write leveling : NO K
7013 13:21:51.535316 RX DQS gating : PASS
7014 13:21:51.538456 RX DQ/DQS(RDDQC) : PASS
7015 13:21:51.538580 TX DQ/DQS : PASS
7016 13:21:51.541666 RX DATLAT : PASS
7017 13:21:51.545006 RX DQ/DQS(Engine): PASS
7018 13:21:51.545132 TX OE : NO K
7019 13:21:51.548085 All Pass.
7020 13:21:51.548206
7021 13:21:51.548322 CH 1, Rank 0
7022 13:21:51.551452 SW Impedance : PASS
7023 13:21:51.551593 DUTY Scan : NO K
7024 13:21:51.554873 ZQ Calibration : PASS
7025 13:21:51.558288 Jitter Meter : NO K
7026 13:21:51.558413 CBT Training : PASS
7027 13:21:51.561555 Write leveling : PASS
7028 13:21:51.564741 RX DQS gating : PASS
7029 13:21:51.564871 RX DQ/DQS(RDDQC) : PASS
7030 13:21:51.568143 TX DQ/DQS : PASS
7031 13:21:51.571588 RX DATLAT : PASS
7032 13:21:51.571711 RX DQ/DQS(Engine): PASS
7033 13:21:51.574974 TX OE : NO K
7034 13:21:51.575100 All Pass.
7035 13:21:51.575211
7036 13:21:51.578475 CH 1, Rank 1
7037 13:21:51.578604 SW Impedance : PASS
7038 13:21:51.581404 DUTY Scan : NO K
7039 13:21:51.584896 ZQ Calibration : PASS
7040 13:21:51.585023 Jitter Meter : NO K
7041 13:21:51.588386 CBT Training : PASS
7042 13:21:51.591426 Write leveling : NO K
7043 13:21:51.591529 RX DQS gating : PASS
7044 13:21:51.594540 RX DQ/DQS(RDDQC) : PASS
7045 13:21:51.594640 TX DQ/DQS : PASS
7046 13:21:51.598295 RX DATLAT : PASS
7047 13:21:51.601269 RX DQ/DQS(Engine): PASS
7048 13:21:51.601347 TX OE : NO K
7049 13:21:51.604386 All Pass.
7050 13:21:51.604457
7051 13:21:51.604522 DramC Write-DBI off
7052 13:21:51.607892 PER_BANK_REFRESH: Hybrid Mode
7053 13:21:51.611501 TX_TRACKING: ON
7054 13:21:51.617982 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7055 13:21:51.621576 [FAST_K] Save calibration result to emmc
7056 13:21:51.624636 dramc_set_vcore_voltage set vcore to 725000
7057 13:21:51.627675 Read voltage for 1600, 0
7058 13:21:51.627750 Vio18 = 0
7059 13:21:51.631282 Vcore = 725000
7060 13:21:51.631356 Vdram = 0
7061 13:21:51.631419 Vddq = 0
7062 13:21:51.634627 Vmddr = 0
7063 13:21:51.637782 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7064 13:21:51.644780 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7065 13:21:51.644892 MEM_TYPE=3, freq_sel=13
7066 13:21:51.647813 sv_algorithm_assistance_LP4_3733
7067 13:21:51.654437 ============ PULL DRAM RESETB DOWN ============
7068 13:21:51.657643 ========== PULL DRAM RESETB DOWN end =========
7069 13:21:51.661147 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7070 13:21:51.664582 ===================================
7071 13:21:51.667713 LPDDR4 DRAM CONFIGURATION
7072 13:21:51.671031 ===================================
7073 13:21:51.674432 EX_ROW_EN[0] = 0x0
7074 13:21:51.674508 EX_ROW_EN[1] = 0x0
7075 13:21:51.677766 LP4Y_EN = 0x0
7076 13:21:51.677841 WORK_FSP = 0x1
7077 13:21:51.681022 WL = 0x5
7078 13:21:51.681096 RL = 0x5
7079 13:21:51.684214 BL = 0x2
7080 13:21:51.684286 RPST = 0x0
7081 13:21:51.687525 RD_PRE = 0x0
7082 13:21:51.687599 WR_PRE = 0x1
7083 13:21:51.691197 WR_PST = 0x1
7084 13:21:51.691284 DBI_WR = 0x0
7085 13:21:51.694492 DBI_RD = 0x0
7086 13:21:51.694578 OTF = 0x1
7087 13:21:51.697427 ===================================
7088 13:21:51.701019 ===================================
7089 13:21:51.704177 ANA top config
7090 13:21:51.707485 ===================================
7091 13:21:51.710947 DLL_ASYNC_EN = 0
7092 13:21:51.711021 ALL_SLAVE_EN = 0
7093 13:21:51.714064 NEW_RANK_MODE = 1
7094 13:21:51.717467 DLL_IDLE_MODE = 1
7095 13:21:51.721170 LP45_APHY_COMB_EN = 1
7096 13:21:51.721244 TX_ODT_DIS = 0
7097 13:21:51.724099 NEW_8X_MODE = 1
7098 13:21:51.727358 ===================================
7099 13:21:51.730835 ===================================
7100 13:21:51.733995 data_rate = 3200
7101 13:21:51.737267 CKR = 1
7102 13:21:51.740521 DQ_P2S_RATIO = 8
7103 13:21:51.744063 ===================================
7104 13:21:51.747563 CA_P2S_RATIO = 8
7105 13:21:51.747694 DQ_CA_OPEN = 0
7106 13:21:51.750613 DQ_SEMI_OPEN = 0
7107 13:21:51.753963 CA_SEMI_OPEN = 0
7108 13:21:51.757516 CA_FULL_RATE = 0
7109 13:21:51.760675 DQ_CKDIV4_EN = 0
7110 13:21:51.764048 CA_CKDIV4_EN = 0
7111 13:21:51.764170 CA_PREDIV_EN = 0
7112 13:21:51.767568 PH8_DLY = 12
7113 13:21:51.770708 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7114 13:21:51.774209 DQ_AAMCK_DIV = 4
7115 13:21:51.777525 CA_AAMCK_DIV = 4
7116 13:21:51.780933 CA_ADMCK_DIV = 4
7117 13:21:51.781060 DQ_TRACK_CA_EN = 0
7118 13:21:51.783978 CA_PICK = 1600
7119 13:21:51.787102 CA_MCKIO = 1600
7120 13:21:51.790625 MCKIO_SEMI = 0
7121 13:21:51.793931 PLL_FREQ = 3068
7122 13:21:51.797111 DQ_UI_PI_RATIO = 32
7123 13:21:51.800680 CA_UI_PI_RATIO = 0
7124 13:21:51.803864 ===================================
7125 13:21:51.807218 ===================================
7126 13:21:51.807351 memory_type:LPDDR4
7127 13:21:51.810503 GP_NUM : 10
7128 13:21:51.813720 SRAM_EN : 1
7129 13:21:51.813843 MD32_EN : 0
7130 13:21:51.817164 ===================================
7131 13:21:51.820555 [ANA_INIT] >>>>>>>>>>>>>>
7132 13:21:51.823783 <<<<<< [CONFIGURE PHASE]: ANA_TX
7133 13:21:51.827181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7134 13:21:51.830753 ===================================
7135 13:21:51.833738 data_rate = 3200,PCW = 0X7600
7136 13:21:51.837223 ===================================
7137 13:21:51.840504 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7138 13:21:51.843821 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7139 13:21:51.850672 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7140 13:21:51.853842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7141 13:21:51.857077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7142 13:21:51.860290 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7143 13:21:51.863501 [ANA_INIT] flow start
7144 13:21:51.866855 [ANA_INIT] PLL >>>>>>>>
7145 13:21:51.866993 [ANA_INIT] PLL <<<<<<<<
7146 13:21:51.870198 [ANA_INIT] MIDPI >>>>>>>>
7147 13:21:51.873682 [ANA_INIT] MIDPI <<<<<<<<
7148 13:21:51.873808 [ANA_INIT] DLL >>>>>>>>
7149 13:21:51.876839 [ANA_INIT] DLL <<<<<<<<
7150 13:21:51.880183 [ANA_INIT] flow end
7151 13:21:51.883798 ============ LP4 DIFF to SE enter ============
7152 13:21:51.886856 ============ LP4 DIFF to SE exit ============
7153 13:21:51.890136 [ANA_INIT] <<<<<<<<<<<<<
7154 13:21:51.893881 [Flow] Enable top DCM control >>>>>
7155 13:21:51.897211 [Flow] Enable top DCM control <<<<<
7156 13:21:51.900262 Enable DLL master slave shuffle
7157 13:21:51.903647 ==============================================================
7158 13:21:51.906909 Gating Mode config
7159 13:21:51.913697 ==============================================================
7160 13:21:51.913772 Config description:
7161 13:21:51.923654 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7162 13:21:51.930524 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7163 13:21:51.933557 SELPH_MODE 0: By rank 1: By Phase
7164 13:21:51.940364 ==============================================================
7165 13:21:51.943872 GAT_TRACK_EN = 1
7166 13:21:51.946906 RX_GATING_MODE = 2
7167 13:21:51.950209 RX_GATING_TRACK_MODE = 2
7168 13:21:51.953420 SELPH_MODE = 1
7169 13:21:51.956979 PICG_EARLY_EN = 1
7170 13:21:51.960172 VALID_LAT_VALUE = 1
7171 13:21:51.963360 ==============================================================
7172 13:21:51.967236 Enter into Gating configuration >>>>
7173 13:21:51.969981 Exit from Gating configuration <<<<
7174 13:21:51.973557 Enter into DVFS_PRE_config >>>>>
7175 13:21:51.986708 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7176 13:21:51.986822 Exit from DVFS_PRE_config <<<<<
7177 13:21:51.989966 Enter into PICG configuration >>>>
7178 13:21:51.993458 Exit from PICG configuration <<<<
7179 13:21:51.996770 [RX_INPUT] configuration >>>>>
7180 13:21:51.999979 [RX_INPUT] configuration <<<<<
7181 13:21:52.006529 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7182 13:21:52.009766 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7183 13:21:52.016779 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7184 13:21:52.023239 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7185 13:21:52.030285 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7186 13:21:52.036672 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7187 13:21:52.039855 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7188 13:21:52.043372 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7189 13:21:52.046637 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7190 13:21:52.053314 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7191 13:21:52.056619 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7192 13:21:52.060368 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7193 13:21:52.063602 ===================================
7194 13:21:52.066839 LPDDR4 DRAM CONFIGURATION
7195 13:21:52.070008 ===================================
7196 13:21:52.070090 EX_ROW_EN[0] = 0x0
7197 13:21:52.073379 EX_ROW_EN[1] = 0x0
7198 13:21:52.076508 LP4Y_EN = 0x0
7199 13:21:52.076584 WORK_FSP = 0x1
7200 13:21:52.079876 WL = 0x5
7201 13:21:52.079952 RL = 0x5
7202 13:21:52.083245 BL = 0x2
7203 13:21:52.083321 RPST = 0x0
7204 13:21:52.086638 RD_PRE = 0x0
7205 13:21:52.086746 WR_PRE = 0x1
7206 13:21:52.090121 WR_PST = 0x1
7207 13:21:52.090203 DBI_WR = 0x0
7208 13:21:52.093310 DBI_RD = 0x0
7209 13:21:52.093383 OTF = 0x1
7210 13:21:52.096684 ===================================
7211 13:21:52.099776 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7212 13:21:52.106497 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7213 13:21:52.110622 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7214 13:21:52.113408 ===================================
7215 13:21:52.116578 LPDDR4 DRAM CONFIGURATION
7216 13:21:52.119880 ===================================
7217 13:21:52.119952 EX_ROW_EN[0] = 0x10
7218 13:21:52.123203 EX_ROW_EN[1] = 0x0
7219 13:21:52.123275 LP4Y_EN = 0x0
7220 13:21:52.126474 WORK_FSP = 0x1
7221 13:21:52.126549 WL = 0x5
7222 13:21:52.129699 RL = 0x5
7223 13:21:52.133617 BL = 0x2
7224 13:21:52.133691 RPST = 0x0
7225 13:21:52.136547 RD_PRE = 0x0
7226 13:21:52.136623 WR_PRE = 0x1
7227 13:21:52.140005 WR_PST = 0x1
7228 13:21:52.140079 DBI_WR = 0x0
7229 13:21:52.143134 DBI_RD = 0x0
7230 13:21:52.143204 OTF = 0x1
7231 13:21:52.146722 ===================================
7232 13:21:52.152910 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7233 13:21:52.152982 ==
7234 13:21:52.156284 Dram Type= 6, Freq= 0, CH_0, rank 0
7235 13:21:52.159556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7236 13:21:52.159628 ==
7237 13:21:52.162861 [Duty_Offset_Calibration]
7238 13:21:52.166349 B0:2 B1:0 CA:1
7239 13:21:52.166420
7240 13:21:52.169582 [DutyScan_Calibration_Flow] k_type=0
7241 13:21:52.177102
7242 13:21:52.177213 ==CLK 0==
7243 13:21:52.180702 Final CLK duty delay cell = -4
7244 13:21:52.183818 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7245 13:21:52.187211 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7246 13:21:52.190416 [-4] AVG Duty = 4906%(X100)
7247 13:21:52.190500
7248 13:21:52.193854 CH0 CLK Duty spec in!! Max-Min= 187%
7249 13:21:52.197044 [DutyScan_Calibration_Flow] ====Done====
7250 13:21:52.197130
7251 13:21:52.200368 [DutyScan_Calibration_Flow] k_type=1
7252 13:21:52.216567
7253 13:21:52.216652 ==DQS 0 ==
7254 13:21:52.219816 Final DQS duty delay cell = 0
7255 13:21:52.223112 [0] MAX Duty = 5249%(X100), DQS PI = 32
7256 13:21:52.226811 [0] MIN Duty = 4969%(X100), DQS PI = 2
7257 13:21:52.226897 [0] AVG Duty = 5109%(X100)
7258 13:21:52.229806
7259 13:21:52.229890 ==DQS 1 ==
7260 13:21:52.233351 Final DQS duty delay cell = -4
7261 13:21:52.236650 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7262 13:21:52.240547 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7263 13:21:52.243547 [-4] AVG Duty = 4969%(X100)
7264 13:21:52.243631
7265 13:21:52.246819 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7266 13:21:52.246903
7267 13:21:52.249937 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7268 13:21:52.253298 [DutyScan_Calibration_Flow] ====Done====
7269 13:21:52.253383
7270 13:21:52.256613 [DutyScan_Calibration_Flow] k_type=3
7271 13:21:52.273890
7272 13:21:52.273976 ==DQM 0 ==
7273 13:21:52.277368 Final DQM duty delay cell = 0
7274 13:21:52.280638 [0] MAX Duty = 5093%(X100), DQS PI = 26
7275 13:21:52.284101 [0] MIN Duty = 4813%(X100), DQS PI = 50
7276 13:21:52.287248 [0] AVG Duty = 4953%(X100)
7277 13:21:52.287346
7278 13:21:52.287438 ==DQM 1 ==
7279 13:21:52.290712 Final DQM duty delay cell = 0
7280 13:21:52.293960 [0] MAX Duty = 5249%(X100), DQS PI = 28
7281 13:21:52.297193 [0] MIN Duty = 5000%(X100), DQS PI = 20
7282 13:21:52.300869 [0] AVG Duty = 5124%(X100)
7283 13:21:52.301007
7284 13:21:52.303941 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7285 13:21:52.304062
7286 13:21:52.307407 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7287 13:21:52.310574 [DutyScan_Calibration_Flow] ====Done====
7288 13:21:52.310696
7289 13:21:52.313823 [DutyScan_Calibration_Flow] k_type=2
7290 13:21:52.332337
7291 13:21:52.332461 ==DQ 0 ==
7292 13:21:52.335545 Final DQ duty delay cell = 0
7293 13:21:52.338785 [0] MAX Duty = 5156%(X100), DQS PI = 38
7294 13:21:52.342010 [0] MIN Duty = 5000%(X100), DQS PI = 16
7295 13:21:52.342127 [0] AVG Duty = 5078%(X100)
7296 13:21:52.345466
7297 13:21:52.345584 ==DQ 1 ==
7298 13:21:52.348788 Final DQ duty delay cell = 4
7299 13:21:52.351933 [4] MAX Duty = 5125%(X100), DQS PI = 2
7300 13:21:52.355264 [4] MIN Duty = 5062%(X100), DQS PI = 0
7301 13:21:52.355375 [4] AVG Duty = 5093%(X100)
7302 13:21:52.355486
7303 13:21:52.358582 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7304 13:21:52.361931
7305 13:21:52.365177 CH0 DQ 1 Duty spec in!! Max-Min= 63%
7306 13:21:52.368604 [DutyScan_Calibration_Flow] ====Done====
7307 13:21:52.368725 ==
7308 13:21:52.371991 Dram Type= 6, Freq= 0, CH_1, rank 0
7309 13:21:52.375141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7310 13:21:52.375243 ==
7311 13:21:52.378649 [Duty_Offset_Calibration]
7312 13:21:52.378749 B0:0 B1:-1 CA:2
7313 13:21:52.378841
7314 13:21:52.381888 [DutyScan_Calibration_Flow] k_type=0
7315 13:21:52.391900
7316 13:21:52.392024 ==CLK 0==
7317 13:21:52.395920 Final CLK duty delay cell = 0
7318 13:21:52.398710 [0] MAX Duty = 5156%(X100), DQS PI = 10
7319 13:21:52.402564 [0] MIN Duty = 4938%(X100), DQS PI = 44
7320 13:21:52.402646 [0] AVG Duty = 5047%(X100)
7321 13:21:52.405523
7322 13:21:52.405604 CH1 CLK Duty spec in!! Max-Min= 218%
7323 13:21:52.412005 [DutyScan_Calibration_Flow] ====Done====
7324 13:21:52.412087
7325 13:21:52.415281 [DutyScan_Calibration_Flow] k_type=1
7326 13:21:52.432223
7327 13:21:52.432303 ==DQS 0 ==
7328 13:21:52.435204 Final DQS duty delay cell = 0
7329 13:21:52.438411 [0] MAX Duty = 5124%(X100), DQS PI = 26
7330 13:21:52.441731 [0] MIN Duty = 4969%(X100), DQS PI = 2
7331 13:21:52.441811 [0] AVG Duty = 5046%(X100)
7332 13:21:52.445341
7333 13:21:52.445422 ==DQS 1 ==
7334 13:21:52.448414 Final DQS duty delay cell = 0
7335 13:21:52.452077 [0] MAX Duty = 5187%(X100), DQS PI = 0
7336 13:21:52.455259 [0] MIN Duty = 4844%(X100), DQS PI = 34
7337 13:21:52.455341 [0] AVG Duty = 5015%(X100)
7338 13:21:52.458652
7339 13:21:52.462324 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7340 13:21:52.462406
7341 13:21:52.465205 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7342 13:21:52.468461 [DutyScan_Calibration_Flow] ====Done====
7343 13:21:52.468616
7344 13:21:52.472004 [DutyScan_Calibration_Flow] k_type=3
7345 13:21:52.489430
7346 13:21:52.489554 ==DQM 0 ==
7347 13:21:52.492877 Final DQM duty delay cell = 4
7348 13:21:52.496003 [4] MAX Duty = 5125%(X100), DQS PI = 8
7349 13:21:52.499459 [4] MIN Duty = 5000%(X100), DQS PI = 32
7350 13:21:52.502686 [4] AVG Duty = 5062%(X100)
7351 13:21:52.502789
7352 13:21:52.502891 ==DQM 1 ==
7353 13:21:52.506074 Final DQM duty delay cell = 0
7354 13:21:52.509132 [0] MAX Duty = 5281%(X100), DQS PI = 58
7355 13:21:52.512891 [0] MIN Duty = 4876%(X100), DQS PI = 34
7356 13:21:52.516215 [0] AVG Duty = 5078%(X100)
7357 13:21:52.516314
7358 13:21:52.519163 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7359 13:21:52.519238
7360 13:21:52.522386 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7361 13:21:52.525921 [DutyScan_Calibration_Flow] ====Done====
7362 13:21:52.525997
7363 13:21:52.528947 [DutyScan_Calibration_Flow] k_type=2
7364 13:21:52.546175
7365 13:21:52.546275 ==DQ 0 ==
7366 13:21:52.549501 Final DQ duty delay cell = 0
7367 13:21:52.553247 [0] MAX Duty = 5093%(X100), DQS PI = 22
7368 13:21:52.556682 [0] MIN Duty = 4969%(X100), DQS PI = 48
7369 13:21:52.556805 [0] AVG Duty = 5031%(X100)
7370 13:21:52.559519
7371 13:21:52.559616 ==DQ 1 ==
7372 13:21:52.562862 Final DQ duty delay cell = 0
7373 13:21:52.566411 [0] MAX Duty = 5094%(X100), DQS PI = 2
7374 13:21:52.569622 [0] MIN Duty = 4844%(X100), DQS PI = 32
7375 13:21:52.569700 [0] AVG Duty = 4969%(X100)
7376 13:21:52.569774
7377 13:21:52.572959 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7378 13:21:52.575913
7379 13:21:52.579466 CH1 DQ 1 Duty spec in!! Max-Min= 250%
7380 13:21:52.582891 [DutyScan_Calibration_Flow] ====Done====
7381 13:21:52.586229 nWR fixed to 30
7382 13:21:52.586306 [ModeRegInit_LP4] CH0 RK0
7383 13:21:52.589243 [ModeRegInit_LP4] CH0 RK1
7384 13:21:52.592765 [ModeRegInit_LP4] CH1 RK0
7385 13:21:52.592856 [ModeRegInit_LP4] CH1 RK1
7386 13:21:52.596457 match AC timing 5
7387 13:21:52.599941 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7388 13:21:52.602879 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7389 13:21:52.609584 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7390 13:21:52.612903 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7391 13:21:52.619475 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7392 13:21:52.619553 [MiockJmeterHQA]
7393 13:21:52.619625
7394 13:21:52.623134 [DramcMiockJmeter] u1RxGatingPI = 0
7395 13:21:52.626459 0 : 4255, 4027
7396 13:21:52.626536 4 : 4253, 4026
7397 13:21:52.626607 8 : 4253, 4026
7398 13:21:52.629925 12 : 4253, 4027
7399 13:21:52.630015 16 : 4252, 4027
7400 13:21:52.633153 20 : 4363, 4137
7401 13:21:52.633228 24 : 4253, 4027
7402 13:21:52.636530 28 : 4363, 4138
7403 13:21:52.636607 32 : 4253, 4027
7404 13:21:52.636680 36 : 4252, 4027
7405 13:21:52.639694 40 : 4253, 4026
7406 13:21:52.639769 44 : 4255, 4030
7407 13:21:52.642928 48 : 4363, 4137
7408 13:21:52.643012 52 : 4252, 4027
7409 13:21:52.646203 56 : 4363, 4138
7410 13:21:52.646289 60 : 4250, 4027
7411 13:21:52.649625 64 : 4250, 4027
7412 13:21:52.649720 68 : 4250, 4027
7413 13:21:52.649784 72 : 4360, 4137
7414 13:21:52.652997 76 : 4250, 4027
7415 13:21:52.653115 80 : 4360, 4137
7416 13:21:52.656012 84 : 4250, 4026
7417 13:21:52.656106 88 : 4250, 3481
7418 13:21:52.659599 92 : 4250, 0
7419 13:21:52.659688 96 : 4360, 0
7420 13:21:52.659759 100 : 4250, 0
7421 13:21:52.662710 104 : 4253, 0
7422 13:21:52.662799 108 : 4250, 0
7423 13:21:52.662861 112 : 4249, 0
7424 13:21:52.665962 116 : 4252, 0
7425 13:21:52.666049 120 : 4250, 0
7426 13:21:52.669351 124 : 4361, 0
7427 13:21:52.669442 128 : 4360, 0
7428 13:21:52.669513 132 : 4250, 0
7429 13:21:52.672768 136 : 4250, 0
7430 13:21:52.672857 140 : 4250, 0
7431 13:21:52.676067 144 : 4250, 0
7432 13:21:52.676151 148 : 4250, 0
7433 13:21:52.676242 152 : 4250, 0
7434 13:21:52.679191 156 : 4253, 0
7435 13:21:52.679267 160 : 4250, 0
7436 13:21:52.682553 164 : 4249, 0
7437 13:21:52.682641 168 : 4252, 0
7438 13:21:52.682704 172 : 4250, 0
7439 13:21:52.686036 176 : 4361, 0
7440 13:21:52.686129 180 : 4361, 0
7441 13:21:52.686200 184 : 4250, 0
7442 13:21:52.689589 188 : 4250, 0
7443 13:21:52.689737 192 : 4250, 0
7444 13:21:52.692626 196 : 4252, 0
7445 13:21:52.692730 200 : 4250, 0
7446 13:21:52.695946 204 : 4250, 2327
7447 13:21:52.696086 208 : 4250, 4027
7448 13:21:52.696179 212 : 4360, 4137
7449 13:21:52.699233 216 : 4250, 4026
7450 13:21:52.699351 220 : 4250, 4027
7451 13:21:52.702669 224 : 4361, 4138
7452 13:21:52.702769 228 : 4360, 4137
7453 13:21:52.705747 232 : 4250, 4027
7454 13:21:52.705824 236 : 4363, 4140
7455 13:21:52.709048 240 : 4250, 4027
7456 13:21:52.709124 244 : 4250, 4027
7457 13:21:52.712352 248 : 4250, 4026
7458 13:21:52.712428 252 : 4253, 4029
7459 13:21:52.715922 256 : 4250, 4027
7460 13:21:52.716007 260 : 4250, 4027
7461 13:21:52.719170 264 : 4250, 4026
7462 13:21:52.719248 268 : 4253, 4029
7463 13:21:52.719349 272 : 4250, 4027
7464 13:21:52.722376 276 : 4361, 4138
7465 13:21:52.722485 280 : 4360, 4137
7466 13:21:52.725756 284 : 4250, 4027
7467 13:21:52.725832 288 : 4363, 4140
7468 13:21:52.729391 292 : 4250, 4027
7469 13:21:52.729522 296 : 4250, 4027
7470 13:21:52.732366 300 : 4250, 4026
7471 13:21:52.732467 304 : 4253, 4029
7472 13:21:52.736308 308 : 4250, 4027
7473 13:21:52.736408 312 : 4250, 3863
7474 13:21:52.739294 316 : 4250, 2069
7475 13:21:52.739379
7476 13:21:52.739445 MIOCK jitter meter ch=0
7477 13:21:52.739507
7478 13:21:52.742537 1T = (316-92) = 224 dly cells
7479 13:21:52.749062 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7480 13:21:52.749146 ==
7481 13:21:52.752486 Dram Type= 6, Freq= 0, CH_0, rank 0
7482 13:21:52.755717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7483 13:21:52.755801 ==
7484 13:21:52.762581 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7485 13:21:52.765814 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7486 13:21:52.769002 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7487 13:21:52.775708 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7488 13:21:52.785326 [CA 0] Center 42 (12~72) winsize 61
7489 13:21:52.788411 [CA 1] Center 42 (12~72) winsize 61
7490 13:21:52.792088 [CA 2] Center 37 (7~67) winsize 61
7491 13:21:52.795149 [CA 3] Center 37 (7~67) winsize 61
7492 13:21:52.798544 [CA 4] Center 35 (5~66) winsize 62
7493 13:21:52.801752 [CA 5] Center 35 (5~65) winsize 61
7494 13:21:52.801836
7495 13:21:52.805094 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7496 13:21:52.805177
7497 13:21:52.808444 [CATrainingPosCal] consider 1 rank data
7498 13:21:52.811722 u2DelayCellTimex100 = 290/100 ps
7499 13:21:52.815093 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7500 13:21:52.821732 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7501 13:21:52.825051 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7502 13:21:52.828480 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7503 13:21:52.831824 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7504 13:21:52.834843 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7505 13:21:52.834926
7506 13:21:52.838240 CA PerBit enable=1, Macro0, CA PI delay=35
7507 13:21:52.838324
7508 13:21:52.841767 [CBTSetCACLKResult] CA Dly = 35
7509 13:21:52.845342 CS Dly: 10 (0~41)
7510 13:21:52.848549 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7511 13:21:52.851505 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7512 13:21:52.851589 ==
7513 13:21:52.854625 Dram Type= 6, Freq= 0, CH_0, rank 1
7514 13:21:52.857838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7515 13:21:52.861272 ==
7516 13:21:52.864911 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7517 13:21:52.867684 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7518 13:21:52.874589 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7519 13:21:52.878353 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7520 13:21:52.888611 [CA 0] Center 43 (13~73) winsize 61
7521 13:21:52.892084 [CA 1] Center 43 (13~73) winsize 61
7522 13:21:52.895219 [CA 2] Center 38 (9~67) winsize 59
7523 13:21:52.898330 [CA 3] Center 38 (8~68) winsize 61
7524 13:21:52.901653 [CA 4] Center 37 (7~67) winsize 61
7525 13:21:52.904922 [CA 5] Center 36 (6~66) winsize 61
7526 13:21:52.905008
7527 13:21:52.908313 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7528 13:21:52.908389
7529 13:21:52.911688 [CATrainingPosCal] consider 2 rank data
7530 13:21:52.914847 u2DelayCellTimex100 = 290/100 ps
7531 13:21:52.918350 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7532 13:21:52.924878 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7533 13:21:52.928217 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7534 13:21:52.931642 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7535 13:21:52.935231 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7536 13:21:52.938168 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7537 13:21:52.938251
7538 13:21:52.941629 CA PerBit enable=1, Macro0, CA PI delay=35
7539 13:21:52.941712
7540 13:21:52.945226 [CBTSetCACLKResult] CA Dly = 35
7541 13:21:52.948155 CS Dly: 11 (0~44)
7542 13:21:52.951482 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7543 13:21:52.955155 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7544 13:21:52.955238
7545 13:21:52.958726 ----->DramcWriteLeveling(PI) begin...
7546 13:21:52.958810 ==
7547 13:21:52.961441 Dram Type= 6, Freq= 0, CH_0, rank 0
7548 13:21:52.968222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7549 13:21:52.968306 ==
7550 13:21:52.971316 Write leveling (Byte 0): 35 => 35
7551 13:21:52.971400 Write leveling (Byte 1): 31 => 31
7552 13:21:52.974744 DramcWriteLeveling(PI) end<-----
7553 13:21:52.974827
7554 13:21:52.974892 ==
7555 13:21:52.978277 Dram Type= 6, Freq= 0, CH_0, rank 0
7556 13:21:52.984747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7557 13:21:52.984900 ==
7558 13:21:52.987988 [Gating] SW mode calibration
7559 13:21:52.994752 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7560 13:21:52.997954 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7561 13:21:53.004673 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 13:21:53.008173 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7563 13:21:53.011324 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7564 13:21:53.017860 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7565 13:21:53.021317 1 4 16 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
7566 13:21:53.024622 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7567 13:21:53.028423 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7568 13:21:53.034507 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7569 13:21:53.038145 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7570 13:21:53.041222 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7571 13:21:53.048184 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 0)
7572 13:21:53.051629 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7573 13:21:53.054855 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7574 13:21:53.061549 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
7575 13:21:53.064851 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 13:21:53.068297 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 13:21:53.074878 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 13:21:53.078101 1 6 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7579 13:21:53.081457 1 6 8 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7580 13:21:53.088172 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7581 13:21:53.091395 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7582 13:21:53.094972 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7583 13:21:53.101480 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7584 13:21:53.105155 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 13:21:53.108716 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 13:21:53.114837 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 13:21:53.118118 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 13:21:53.121599 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7589 13:21:53.124972 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7590 13:21:53.131365 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7591 13:21:53.134646 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 13:21:53.138181 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 13:21:53.144798 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 13:21:53.148239 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 13:21:53.151378 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 13:21:53.157996 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 13:21:53.161562 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 13:21:53.164480 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 13:21:53.171134 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 13:21:53.174529 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 13:21:53.178076 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 13:21:53.184546 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 13:21:53.187729 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7604 13:21:53.190907 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7605 13:21:53.194231 Total UI for P1: 0, mck2ui 16
7606 13:21:53.197793 best dqsien dly found for B0: ( 1, 9, 8)
7607 13:21:53.204678 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7608 13:21:53.207709 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7609 13:21:53.211136 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 13:21:53.214313 Total UI for P1: 0, mck2ui 16
7611 13:21:53.218026 best dqsien dly found for B1: ( 1, 9, 18)
7612 13:21:53.221020 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7613 13:21:53.224195 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7614 13:21:53.224281
7615 13:21:53.227719 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7616 13:21:53.234697 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7617 13:21:53.234797 [Gating] SW calibration Done
7618 13:21:53.234897 ==
7619 13:21:53.237737 Dram Type= 6, Freq= 0, CH_0, rank 0
7620 13:21:53.244331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7621 13:21:53.244433 ==
7622 13:21:53.244520 RX Vref Scan: 0
7623 13:21:53.244602
7624 13:21:53.247523 RX Vref 0 -> 0, step: 1
7625 13:21:53.247612
7626 13:21:53.250857 RX Delay 0 -> 252, step: 8
7627 13:21:53.254533 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7628 13:21:53.257633 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7629 13:21:53.260818 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7630 13:21:53.264140 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7631 13:21:53.270859 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7632 13:21:53.274311 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7633 13:21:53.277681 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7634 13:21:53.280660 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7635 13:21:53.284372 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7636 13:21:53.291463 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7637 13:21:53.294439 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7638 13:21:53.297447 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7639 13:21:53.300738 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7640 13:21:53.307413 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7641 13:21:53.310926 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7642 13:21:53.314173 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
7643 13:21:53.314260 ==
7644 13:21:53.317378 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 13:21:53.320703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 13:21:53.320813 ==
7647 13:21:53.324214 DQS Delay:
7648 13:21:53.324300 DQS0 = 0, DQS1 = 0
7649 13:21:53.324386 DQM Delay:
7650 13:21:53.327327 DQM0 = 138, DQM1 = 126
7651 13:21:53.327413 DQ Delay:
7652 13:21:53.330706 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7653 13:21:53.333840 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7654 13:21:53.340522 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7655 13:21:53.343868 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =131
7656 13:21:53.343976
7657 13:21:53.344061
7658 13:21:53.344143 ==
7659 13:21:53.347642 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 13:21:53.350530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 13:21:53.350645 ==
7662 13:21:53.350751
7663 13:21:53.350853
7664 13:21:53.353976 TX Vref Scan disable
7665 13:21:53.357172 == TX Byte 0 ==
7666 13:21:53.360712 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7667 13:21:53.364123 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7668 13:21:53.367154 == TX Byte 1 ==
7669 13:21:53.370591 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7670 13:21:53.373847 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7671 13:21:53.373936 ==
7672 13:21:53.377454 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 13:21:53.380608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 13:21:53.380697 ==
7675 13:21:53.395940
7676 13:21:53.399387 TX Vref early break, caculate TX vref
7677 13:21:53.403062 TX Vref=16, minBit 4, minWin=23, winSum=377
7678 13:21:53.406013 TX Vref=18, minBit 7, minWin=23, winSum=386
7679 13:21:53.409128 TX Vref=20, minBit 2, minWin=24, winSum=397
7680 13:21:53.412553 TX Vref=22, minBit 12, minWin=24, winSum=405
7681 13:21:53.415887 TX Vref=24, minBit 5, minWin=25, winSum=416
7682 13:21:53.422594 TX Vref=26, minBit 5, minWin=25, winSum=423
7683 13:21:53.426229 TX Vref=28, minBit 0, minWin=26, winSum=431
7684 13:21:53.429369 TX Vref=30, minBit 7, minWin=25, winSum=428
7685 13:21:53.432523 TX Vref=32, minBit 0, minWin=24, winSum=416
7686 13:21:53.435793 TX Vref=34, minBit 1, minWin=25, winSum=409
7687 13:21:53.439140 TX Vref=36, minBit 0, minWin=24, winSum=395
7688 13:21:53.446076 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
7689 13:21:53.446218
7690 13:21:53.449176 Final TX Range 0 Vref 28
7691 13:21:53.449263
7692 13:21:53.449349 ==
7693 13:21:53.452479 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 13:21:53.456131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 13:21:53.456219 ==
7696 13:21:53.456305
7697 13:21:53.456386
7698 13:21:53.459350 TX Vref Scan disable
7699 13:21:53.465763 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7700 13:21:53.465880 == TX Byte 0 ==
7701 13:21:53.469583 u2DelayCellOfst[0]=13 cells (4 PI)
7702 13:21:53.472894 u2DelayCellOfst[1]=16 cells (5 PI)
7703 13:21:53.475997 u2DelayCellOfst[2]=10 cells (3 PI)
7704 13:21:53.479085 u2DelayCellOfst[3]=10 cells (3 PI)
7705 13:21:53.482492 u2DelayCellOfst[4]=6 cells (2 PI)
7706 13:21:53.485840 u2DelayCellOfst[5]=0 cells (0 PI)
7707 13:21:53.489043 u2DelayCellOfst[6]=16 cells (5 PI)
7708 13:21:53.492475 u2DelayCellOfst[7]=16 cells (5 PI)
7709 13:21:53.495907 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7710 13:21:53.499302 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7711 13:21:53.502719 == TX Byte 1 ==
7712 13:21:53.502823 u2DelayCellOfst[8]=3 cells (1 PI)
7713 13:21:53.505859 u2DelayCellOfst[9]=0 cells (0 PI)
7714 13:21:53.509343 u2DelayCellOfst[10]=10 cells (3 PI)
7715 13:21:53.512424 u2DelayCellOfst[11]=3 cells (1 PI)
7716 13:21:53.516051 u2DelayCellOfst[12]=16 cells (5 PI)
7717 13:21:53.519312 u2DelayCellOfst[13]=13 cells (4 PI)
7718 13:21:53.522826 u2DelayCellOfst[14]=16 cells (5 PI)
7719 13:21:53.525986 u2DelayCellOfst[15]=13 cells (4 PI)
7720 13:21:53.529246 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7721 13:21:53.535932 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7722 13:21:53.536061 DramC Write-DBI on
7723 13:21:53.536182 ==
7724 13:21:53.539322 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 13:21:53.542576 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 13:21:53.545780 ==
7727 13:21:53.545902
7728 13:21:53.546017
7729 13:21:53.546132 TX Vref Scan disable
7730 13:21:53.549245 == TX Byte 0 ==
7731 13:21:53.553024 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7732 13:21:53.555848 == TX Byte 1 ==
7733 13:21:53.559348 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7734 13:21:53.562536 DramC Write-DBI off
7735 13:21:53.562661
7736 13:21:53.562774 [DATLAT]
7737 13:21:53.562885 Freq=1600, CH0 RK0
7738 13:21:53.562993
7739 13:21:53.566201 DATLAT Default: 0xf
7740 13:21:53.566340 0, 0xFFFF, sum = 0
7741 13:21:53.569201 1, 0xFFFF, sum = 0
7742 13:21:53.569330 2, 0xFFFF, sum = 0
7743 13:21:53.572957 3, 0xFFFF, sum = 0
7744 13:21:53.575891 4, 0xFFFF, sum = 0
7745 13:21:53.576018 5, 0xFFFF, sum = 0
7746 13:21:53.579440 6, 0xFFFF, sum = 0
7747 13:21:53.579581 7, 0xFFFF, sum = 0
7748 13:21:53.582660 8, 0xFFFF, sum = 0
7749 13:21:53.582785 9, 0xFFFF, sum = 0
7750 13:21:53.586559 10, 0xFFFF, sum = 0
7751 13:21:53.586683 11, 0xFFFF, sum = 0
7752 13:21:53.589323 12, 0xFFFF, sum = 0
7753 13:21:53.589459 13, 0xFFFF, sum = 0
7754 13:21:53.592517 14, 0x0, sum = 1
7755 13:21:53.592637 15, 0x0, sum = 2
7756 13:21:53.595736 16, 0x0, sum = 3
7757 13:21:53.595860 17, 0x0, sum = 4
7758 13:21:53.599161 best_step = 15
7759 13:21:53.599284
7760 13:21:53.599395 ==
7761 13:21:53.602659 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 13:21:53.606036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 13:21:53.606161 ==
7764 13:21:53.606277 RX Vref Scan: 1
7765 13:21:53.609369
7766 13:21:53.609507 Set Vref Range= 24 -> 127
7767 13:21:53.609651
7768 13:21:53.612581 RX Vref 24 -> 127, step: 1
7769 13:21:53.612705
7770 13:21:53.615990 RX Delay 19 -> 252, step: 4
7771 13:21:53.616113
7772 13:21:53.619245 Set Vref, RX VrefLevel [Byte0]: 24
7773 13:21:53.622897 [Byte1]: 24
7774 13:21:53.623034
7775 13:21:53.625886 Set Vref, RX VrefLevel [Byte0]: 25
7776 13:21:53.629324 [Byte1]: 25
7777 13:21:53.629448
7778 13:21:53.632968 Set Vref, RX VrefLevel [Byte0]: 26
7779 13:21:53.636036 [Byte1]: 26
7780 13:21:53.639526
7781 13:21:53.639661 Set Vref, RX VrefLevel [Byte0]: 27
7782 13:21:53.642974 [Byte1]: 27
7783 13:21:53.647365
7784 13:21:53.647493 Set Vref, RX VrefLevel [Byte0]: 28
7785 13:21:53.650638 [Byte1]: 28
7786 13:21:53.654774
7787 13:21:53.654896 Set Vref, RX VrefLevel [Byte0]: 29
7788 13:21:53.658353 [Byte1]: 29
7789 13:21:53.662259
7790 13:21:53.662394 Set Vref, RX VrefLevel [Byte0]: 30
7791 13:21:53.665626 [Byte1]: 30
7792 13:21:53.669815
7793 13:21:53.669934 Set Vref, RX VrefLevel [Byte0]: 31
7794 13:21:53.673422 [Byte1]: 31
7795 13:21:53.677879
7796 13:21:53.677964 Set Vref, RX VrefLevel [Byte0]: 32
7797 13:21:53.680710 [Byte1]: 32
7798 13:21:53.685075
7799 13:21:53.685193 Set Vref, RX VrefLevel [Byte0]: 33
7800 13:21:53.688272 [Byte1]: 33
7801 13:21:53.692481
7802 13:21:53.692598 Set Vref, RX VrefLevel [Byte0]: 34
7803 13:21:53.695806 [Byte1]: 34
7804 13:21:53.700343
7805 13:21:53.700426 Set Vref, RX VrefLevel [Byte0]: 35
7806 13:21:53.703510 [Byte1]: 35
7807 13:21:53.707982
7808 13:21:53.708082 Set Vref, RX VrefLevel [Byte0]: 36
7809 13:21:53.711576 [Byte1]: 36
7810 13:21:53.715318
7811 13:21:53.715412 Set Vref, RX VrefLevel [Byte0]: 37
7812 13:21:53.718617 [Byte1]: 37
7813 13:21:53.722890
7814 13:21:53.722977 Set Vref, RX VrefLevel [Byte0]: 38
7815 13:21:53.726754 [Byte1]: 38
7816 13:21:53.730672
7817 13:21:53.730765 Set Vref, RX VrefLevel [Byte0]: 39
7818 13:21:53.733883 [Byte1]: 39
7819 13:21:53.738037
7820 13:21:53.738121 Set Vref, RX VrefLevel [Byte0]: 40
7821 13:21:53.741373 [Byte1]: 40
7822 13:21:53.745832
7823 13:21:53.745935 Set Vref, RX VrefLevel [Byte0]: 41
7824 13:21:53.748879 [Byte1]: 41
7825 13:21:53.753460
7826 13:21:53.753544 Set Vref, RX VrefLevel [Byte0]: 42
7827 13:21:53.756692 [Byte1]: 42
7828 13:21:53.761122
7829 13:21:53.761208 Set Vref, RX VrefLevel [Byte0]: 43
7830 13:21:53.764075 [Byte1]: 43
7831 13:21:53.768397
7832 13:21:53.768497 Set Vref, RX VrefLevel [Byte0]: 44
7833 13:21:53.771786 [Byte1]: 44
7834 13:21:53.776013
7835 13:21:53.776102 Set Vref, RX VrefLevel [Byte0]: 45
7836 13:21:53.779089 [Byte1]: 45
7837 13:21:53.783489
7838 13:21:53.783575 Set Vref, RX VrefLevel [Byte0]: 46
7839 13:21:53.787485 [Byte1]: 46
7840 13:21:53.790999
7841 13:21:53.791100 Set Vref, RX VrefLevel [Byte0]: 47
7842 13:21:53.794334 [Byte1]: 47
7843 13:21:53.798746
7844 13:21:53.798832 Set Vref, RX VrefLevel [Byte0]: 48
7845 13:21:53.802199 [Byte1]: 48
7846 13:21:53.806120
7847 13:21:53.806206 Set Vref, RX VrefLevel [Byte0]: 49
7848 13:21:53.809586 [Byte1]: 49
7849 13:21:53.814188
7850 13:21:53.814274 Set Vref, RX VrefLevel [Byte0]: 50
7851 13:21:53.817236 [Byte1]: 50
7852 13:21:53.821564
7853 13:21:53.821650 Set Vref, RX VrefLevel [Byte0]: 51
7854 13:21:53.824687 [Byte1]: 51
7855 13:21:53.828788
7856 13:21:53.828874 Set Vref, RX VrefLevel [Byte0]: 52
7857 13:21:53.832367 [Byte1]: 52
7858 13:21:53.836657
7859 13:21:53.836746 Set Vref, RX VrefLevel [Byte0]: 53
7860 13:21:53.839730 [Byte1]: 53
7861 13:21:53.844337
7862 13:21:53.844423 Set Vref, RX VrefLevel [Byte0]: 54
7863 13:21:53.850610 [Byte1]: 54
7864 13:21:53.850697
7865 13:21:53.853820 Set Vref, RX VrefLevel [Byte0]: 55
7866 13:21:53.857444 [Byte1]: 55
7867 13:21:53.857530
7868 13:21:53.860616 Set Vref, RX VrefLevel [Byte0]: 56
7869 13:21:53.863810 [Byte1]: 56
7870 13:21:53.863910
7871 13:21:53.867049 Set Vref, RX VrefLevel [Byte0]: 57
7872 13:21:53.870318 [Byte1]: 57
7873 13:21:53.874322
7874 13:21:53.874463 Set Vref, RX VrefLevel [Byte0]: 58
7875 13:21:53.877782 [Byte1]: 58
7876 13:21:53.881763
7877 13:21:53.881841 Set Vref, RX VrefLevel [Byte0]: 59
7878 13:21:53.885540 [Byte1]: 59
7879 13:21:53.889477
7880 13:21:53.889568 Set Vref, RX VrefLevel [Byte0]: 60
7881 13:21:53.892946 [Byte1]: 60
7882 13:21:53.897059
7883 13:21:53.897132 Set Vref, RX VrefLevel [Byte0]: 61
7884 13:21:53.900425 [Byte1]: 61
7885 13:21:53.904819
7886 13:21:53.904916 Set Vref, RX VrefLevel [Byte0]: 62
7887 13:21:53.908093 [Byte1]: 62
7888 13:21:53.912159
7889 13:21:53.912260 Set Vref, RX VrefLevel [Byte0]: 63
7890 13:21:53.915388 [Byte1]: 63
7891 13:21:53.919907
7892 13:21:53.919994 Set Vref, RX VrefLevel [Byte0]: 64
7893 13:21:53.923107 [Byte1]: 64
7894 13:21:53.927570
7895 13:21:53.927656 Set Vref, RX VrefLevel [Byte0]: 65
7896 13:21:53.930736 [Byte1]: 65
7897 13:21:53.934813
7898 13:21:53.934916 Set Vref, RX VrefLevel [Byte0]: 66
7899 13:21:53.938196 [Byte1]: 66
7900 13:21:53.942538
7901 13:21:53.942608 Set Vref, RX VrefLevel [Byte0]: 67
7902 13:21:53.946236 [Byte1]: 67
7903 13:21:53.949882
7904 13:21:53.949952 Set Vref, RX VrefLevel [Byte0]: 68
7905 13:21:53.953378 [Byte1]: 68
7906 13:21:53.957500
7907 13:21:53.957570 Set Vref, RX VrefLevel [Byte0]: 69
7908 13:21:53.960927 [Byte1]: 69
7909 13:21:53.965216
7910 13:21:53.965287 Set Vref, RX VrefLevel [Byte0]: 70
7911 13:21:53.968640 [Byte1]: 70
7912 13:21:53.972935
7913 13:21:53.973012 Set Vref, RX VrefLevel [Byte0]: 71
7914 13:21:53.976412 [Byte1]: 71
7915 13:21:53.980489
7916 13:21:53.980627 Set Vref, RX VrefLevel [Byte0]: 72
7917 13:21:53.983685 [Byte1]: 72
7918 13:21:53.988321
7919 13:21:53.988440 Set Vref, RX VrefLevel [Byte0]: 73
7920 13:21:53.991284 [Byte1]: 73
7921 13:21:53.995557
7922 13:21:53.995643 Set Vref, RX VrefLevel [Byte0]: 74
7923 13:21:53.999016 [Byte1]: 74
7924 13:21:54.003066
7925 13:21:54.003157 Set Vref, RX VrefLevel [Byte0]: 75
7926 13:21:54.006530 [Byte1]: 75
7927 13:21:54.010815
7928 13:21:54.010917 Set Vref, RX VrefLevel [Byte0]: 76
7929 13:21:54.013908 [Byte1]: 76
7930 13:21:54.018402
7931 13:21:54.018477 Set Vref, RX VrefLevel [Byte0]: 77
7932 13:21:54.021901 [Byte1]: 77
7933 13:21:54.026087
7934 13:21:54.026163 Set Vref, RX VrefLevel [Byte0]: 78
7935 13:21:54.029224 [Byte1]: 78
7936 13:21:54.033171
7937 13:21:54.033246 Set Vref, RX VrefLevel [Byte0]: 79
7938 13:21:54.036699 [Byte1]: 79
7939 13:21:54.041040
7940 13:21:54.041115 Set Vref, RX VrefLevel [Byte0]: 80
7941 13:21:54.044146 [Byte1]: 80
7942 13:21:54.048436
7943 13:21:54.048540 Final RX Vref Byte 0 = 64 to rank0
7944 13:21:54.051756 Final RX Vref Byte 1 = 60 to rank0
7945 13:21:54.055118 Final RX Vref Byte 0 = 64 to rank1
7946 13:21:54.058357 Final RX Vref Byte 1 = 60 to rank1==
7947 13:21:54.061748 Dram Type= 6, Freq= 0, CH_0, rank 0
7948 13:21:54.068212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7949 13:21:54.068299 ==
7950 13:21:54.068367 DQS Delay:
7951 13:21:54.068431 DQS0 = 0, DQS1 = 0
7952 13:21:54.071609 DQM Delay:
7953 13:21:54.071741 DQM0 = 136, DQM1 = 123
7954 13:21:54.075205 DQ Delay:
7955 13:21:54.078368 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7956 13:21:54.081674 DQ4 =138, DQ5 =126, DQ6 =144, DQ7 =142
7957 13:21:54.085277 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
7958 13:21:54.088736 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =130
7959 13:21:54.088843
7960 13:21:54.088928
7961 13:21:54.089005
7962 13:21:54.091590 [DramC_TX_OE_Calibration] TA2
7963 13:21:54.095544 Original DQ_B0 (3 6) =30, OEN = 27
7964 13:21:54.098304 Original DQ_B1 (3 6) =30, OEN = 27
7965 13:21:54.102128 24, 0x0, End_B0=24 End_B1=24
7966 13:21:54.102214 25, 0x0, End_B0=25 End_B1=25
7967 13:21:54.105175 26, 0x0, End_B0=26 End_B1=26
7968 13:21:54.108283 27, 0x0, End_B0=27 End_B1=27
7969 13:21:54.112098 28, 0x0, End_B0=28 End_B1=28
7970 13:21:54.112184 29, 0x0, End_B0=29 End_B1=29
7971 13:21:54.114998 30, 0x0, End_B0=30 End_B1=30
7972 13:21:54.118569 31, 0x4141, End_B0=30 End_B1=30
7973 13:21:54.121823 Byte0 end_step=30 best_step=27
7974 13:21:54.125311 Byte1 end_step=30 best_step=27
7975 13:21:54.128336 Byte0 TX OE(2T, 0.5T) = (3, 3)
7976 13:21:54.128420 Byte1 TX OE(2T, 0.5T) = (3, 3)
7977 13:21:54.131692
7978 13:21:54.131822
7979 13:21:54.138361 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
7980 13:21:54.141752 CH0 RK0: MR19=303, MR18=1E1C
7981 13:21:54.148236 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
7982 13:21:54.148363
7983 13:21:54.151543 ----->DramcWriteLeveling(PI) begin...
7984 13:21:54.151670 ==
7985 13:21:54.154880 Dram Type= 6, Freq= 0, CH_0, rank 1
7986 13:21:54.158307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 13:21:54.158428 ==
7988 13:21:54.161883 Write leveling (Byte 0): 38 => 38
7989 13:21:54.165229 Write leveling (Byte 1): 28 => 28
7990 13:21:54.168578 DramcWriteLeveling(PI) end<-----
7991 13:21:54.168699
7992 13:21:54.168850 ==
7993 13:21:54.171677 Dram Type= 6, Freq= 0, CH_0, rank 1
7994 13:21:54.175207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7995 13:21:54.175332 ==
7996 13:21:54.178361 [Gating] SW mode calibration
7997 13:21:54.184930 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7998 13:21:54.191666 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7999 13:21:54.194951 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 13:21:54.198319 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 13:21:54.204929 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 13:21:54.208112 1 4 12 | B1->B0 | 2727 3131 | 0 0 | (0 0) (0 0)
8003 13:21:54.212025 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8004 13:21:54.218125 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8005 13:21:54.221512 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8006 13:21:54.224790 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8007 13:21:54.231680 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8008 13:21:54.235030 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 13:21:54.238484 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8010 13:21:54.245223 1 5 12 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
8011 13:21:54.248685 1 5 16 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8012 13:21:54.251968 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 13:21:54.255305 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 13:21:54.261778 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 13:21:54.265216 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 13:21:54.268214 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 13:21:54.274989 1 6 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8018 13:21:54.278479 1 6 12 | B1->B0 | 2e2e 4444 | 1 0 | (0 0) (0 0)
8019 13:21:54.281384 1 6 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8020 13:21:54.288232 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 13:21:54.291665 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 13:21:54.295061 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8023 13:21:54.301561 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 13:21:54.304935 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 13:21:54.308218 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8026 13:21:54.314762 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8027 13:21:54.318117 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8028 13:21:54.321333 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 13:21:54.327969 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 13:21:54.331773 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 13:21:54.334703 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 13:21:54.341323 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 13:21:54.344645 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 13:21:54.347995 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 13:21:54.354574 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 13:21:54.357783 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 13:21:54.361200 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 13:21:54.367870 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 13:21:54.371227 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 13:21:54.374544 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 13:21:54.381347 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8042 13:21:54.384248 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8043 13:21:54.387736 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 13:21:54.391125 Total UI for P1: 0, mck2ui 16
8045 13:21:54.394210 best dqsien dly found for B0: ( 1, 9, 10)
8046 13:21:54.397871 Total UI for P1: 0, mck2ui 16
8047 13:21:54.401068 best dqsien dly found for B1: ( 1, 9, 14)
8048 13:21:54.404208 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8049 13:21:54.407738 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8050 13:21:54.407865
8051 13:21:54.411136 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8052 13:21:54.417640 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8053 13:21:54.417764 [Gating] SW calibration Done
8054 13:21:54.417876 ==
8055 13:21:54.421206 Dram Type= 6, Freq= 0, CH_0, rank 1
8056 13:21:54.427711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8057 13:21:54.427837 ==
8058 13:21:54.427952 RX Vref Scan: 0
8059 13:21:54.428065
8060 13:21:54.430904 RX Vref 0 -> 0, step: 1
8061 13:21:54.431028
8062 13:21:54.434101 RX Delay 0 -> 252, step: 8
8063 13:21:54.437396 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8064 13:21:54.440787 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8065 13:21:54.444426 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8066 13:21:54.450962 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8067 13:21:54.453991 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8068 13:21:54.457584 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8069 13:21:54.460655 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8070 13:21:54.464131 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8071 13:21:54.467572 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8072 13:21:54.474348 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8073 13:21:54.477636 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8074 13:21:54.480741 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8075 13:21:54.484453 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8076 13:21:54.490849 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8077 13:21:54.494143 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8078 13:21:54.497356 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8079 13:21:54.497500 ==
8080 13:21:54.500662 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 13:21:54.504339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 13:21:54.504437 ==
8083 13:21:54.507741 DQS Delay:
8084 13:21:54.507837 DQS0 = 0, DQS1 = 0
8085 13:21:54.510580 DQM Delay:
8086 13:21:54.510703 DQM0 = 136, DQM1 = 125
8087 13:21:54.510796 DQ Delay:
8088 13:21:54.514373 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8089 13:21:54.517586 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8090 13:21:54.524384 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
8091 13:21:54.527303 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8092 13:21:54.527386
8093 13:21:54.527452
8094 13:21:54.527513 ==
8095 13:21:54.530768 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 13:21:54.534312 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 13:21:54.534396 ==
8098 13:21:54.534462
8099 13:21:54.534523
8100 13:21:54.537410 TX Vref Scan disable
8101 13:21:54.540599 == TX Byte 0 ==
8102 13:21:54.544010 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8103 13:21:54.547782 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8104 13:21:54.550702 == TX Byte 1 ==
8105 13:21:54.553952 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8106 13:21:54.557425 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8107 13:21:54.557550 ==
8108 13:21:54.560442 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 13:21:54.564056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 13:21:54.564156 ==
8111 13:21:54.580481
8112 13:21:54.583964 TX Vref early break, caculate TX vref
8113 13:21:54.587294 TX Vref=16, minBit 0, minWin=23, winSum=390
8114 13:21:54.590760 TX Vref=18, minBit 8, minWin=23, winSum=404
8115 13:21:54.594231 TX Vref=20, minBit 0, minWin=25, winSum=409
8116 13:21:54.597195 TX Vref=22, minBit 0, minWin=25, winSum=417
8117 13:21:54.600553 TX Vref=24, minBit 2, minWin=25, winSum=427
8118 13:21:54.607154 TX Vref=26, minBit 0, minWin=26, winSum=433
8119 13:21:54.610174 TX Vref=28, minBit 0, minWin=26, winSum=431
8120 13:21:54.613510 TX Vref=30, minBit 0, minWin=25, winSum=428
8121 13:21:54.617364 TX Vref=32, minBit 0, minWin=25, winSum=421
8122 13:21:54.620222 TX Vref=34, minBit 4, minWin=24, winSum=412
8123 13:21:54.623861 TX Vref=36, minBit 2, minWin=24, winSum=401
8124 13:21:54.630473 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 26
8125 13:21:54.630557
8126 13:21:54.633811 Final TX Range 0 Vref 26
8127 13:21:54.633894
8128 13:21:54.633960 ==
8129 13:21:54.637085 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 13:21:54.640320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 13:21:54.640403 ==
8132 13:21:54.640470
8133 13:21:54.643967
8134 13:21:54.644049 TX Vref Scan disable
8135 13:21:54.650040 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8136 13:21:54.650124 == TX Byte 0 ==
8137 13:21:54.653306 u2DelayCellOfst[0]=13 cells (4 PI)
8138 13:21:54.656971 u2DelayCellOfst[1]=20 cells (6 PI)
8139 13:21:54.660083 u2DelayCellOfst[2]=13 cells (4 PI)
8140 13:21:54.663358 u2DelayCellOfst[3]=13 cells (4 PI)
8141 13:21:54.666685 u2DelayCellOfst[4]=10 cells (3 PI)
8142 13:21:54.670267 u2DelayCellOfst[5]=0 cells (0 PI)
8143 13:21:54.673399 u2DelayCellOfst[6]=20 cells (6 PI)
8144 13:21:54.676646 u2DelayCellOfst[7]=20 cells (6 PI)
8145 13:21:54.680326 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8146 13:21:54.683560 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8147 13:21:54.686478 == TX Byte 1 ==
8148 13:21:54.689806 u2DelayCellOfst[8]=0 cells (0 PI)
8149 13:21:54.693413 u2DelayCellOfst[9]=0 cells (0 PI)
8150 13:21:54.696555 u2DelayCellOfst[10]=6 cells (2 PI)
8151 13:21:54.696638 u2DelayCellOfst[11]=3 cells (1 PI)
8152 13:21:54.699875 u2DelayCellOfst[12]=10 cells (3 PI)
8153 13:21:54.703323 u2DelayCellOfst[13]=10 cells (3 PI)
8154 13:21:54.706406 u2DelayCellOfst[14]=13 cells (4 PI)
8155 13:21:54.709807 u2DelayCellOfst[15]=10 cells (3 PI)
8156 13:21:54.716312 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8157 13:21:54.720137 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8158 13:21:54.720220 DramC Write-DBI on
8159 13:21:54.722985 ==
8160 13:21:54.723068 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 13:21:54.729824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 13:21:54.729908 ==
8163 13:21:54.729975
8164 13:21:54.730036
8165 13:21:54.732916 TX Vref Scan disable
8166 13:21:54.732998 == TX Byte 0 ==
8167 13:21:54.739618 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8168 13:21:54.739703 == TX Byte 1 ==
8169 13:21:54.742959 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8170 13:21:54.746159 DramC Write-DBI off
8171 13:21:54.746242
8172 13:21:54.746308 [DATLAT]
8173 13:21:54.750095 Freq=1600, CH0 RK1
8174 13:21:54.750179
8175 13:21:54.750245 DATLAT Default: 0xf
8176 13:21:54.753161 0, 0xFFFF, sum = 0
8177 13:21:54.753276 1, 0xFFFF, sum = 0
8178 13:21:54.756104 2, 0xFFFF, sum = 0
8179 13:21:54.756188 3, 0xFFFF, sum = 0
8180 13:21:54.759791 4, 0xFFFF, sum = 0
8181 13:21:54.759877 5, 0xFFFF, sum = 0
8182 13:21:54.763276 6, 0xFFFF, sum = 0
8183 13:21:54.763360 7, 0xFFFF, sum = 0
8184 13:21:54.766132 8, 0xFFFF, sum = 0
8185 13:21:54.766216 9, 0xFFFF, sum = 0
8186 13:21:54.769727 10, 0xFFFF, sum = 0
8187 13:21:54.773087 11, 0xFFFF, sum = 0
8188 13:21:54.773171 12, 0xFFFF, sum = 0
8189 13:21:54.776347 13, 0xFFFF, sum = 0
8190 13:21:54.776431 14, 0x0, sum = 1
8191 13:21:54.779643 15, 0x0, sum = 2
8192 13:21:54.779727 16, 0x0, sum = 3
8193 13:21:54.779795 17, 0x0, sum = 4
8194 13:21:54.783171 best_step = 15
8195 13:21:54.783275
8196 13:21:54.783384 ==
8197 13:21:54.786508 Dram Type= 6, Freq= 0, CH_0, rank 1
8198 13:21:54.789783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8199 13:21:54.789854 ==
8200 13:21:54.792748 RX Vref Scan: 0
8201 13:21:54.792888
8202 13:21:54.796181 RX Vref 0 -> 0, step: 1
8203 13:21:54.796278
8204 13:21:54.796384 RX Delay 11 -> 252, step: 4
8205 13:21:54.803164 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8206 13:21:54.806645 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8207 13:21:54.809599 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8208 13:21:54.813274 iDelay=191, Bit 3, Center 128 (79 ~ 178) 100
8209 13:21:54.816249 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8210 13:21:54.823506 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8211 13:21:54.826524 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8212 13:21:54.829761 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8213 13:21:54.833240 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8214 13:21:54.836460 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8215 13:21:54.843046 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8216 13:21:54.846095 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8217 13:21:54.849600 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8218 13:21:54.852857 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8219 13:21:54.856191 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8220 13:21:54.862920 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8221 13:21:54.863000 ==
8222 13:21:54.866407 Dram Type= 6, Freq= 0, CH_0, rank 1
8223 13:21:54.869614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 13:21:54.869686 ==
8225 13:21:54.869756 DQS Delay:
8226 13:21:54.872967 DQS0 = 0, DQS1 = 0
8227 13:21:54.873038 DQM Delay:
8228 13:21:54.876113 DQM0 = 133, DQM1 = 123
8229 13:21:54.876193 DQ Delay:
8230 13:21:54.879386 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =128
8231 13:21:54.882842 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8232 13:21:54.886126 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8233 13:21:54.889497 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8234 13:21:54.893123
8235 13:21:54.893198
8236 13:21:54.893262
8237 13:21:54.893321 [DramC_TX_OE_Calibration] TA2
8238 13:21:54.896265 Original DQ_B0 (3 6) =30, OEN = 27
8239 13:21:54.899589 Original DQ_B1 (3 6) =30, OEN = 27
8240 13:21:54.902773 24, 0x0, End_B0=24 End_B1=24
8241 13:21:54.906194 25, 0x0, End_B0=25 End_B1=25
8242 13:21:54.909780 26, 0x0, End_B0=26 End_B1=26
8243 13:21:54.909863 27, 0x0, End_B0=27 End_B1=27
8244 13:21:54.913124 28, 0x0, End_B0=28 End_B1=28
8245 13:21:54.915879 29, 0x0, End_B0=29 End_B1=29
8246 13:21:54.919282 30, 0x0, End_B0=30 End_B1=30
8247 13:21:54.922658 31, 0x4141, End_B0=30 End_B1=30
8248 13:21:54.922733 Byte0 end_step=30 best_step=27
8249 13:21:54.926080 Byte1 end_step=30 best_step=27
8250 13:21:54.929299 Byte0 TX OE(2T, 0.5T) = (3, 3)
8251 13:21:54.932578 Byte1 TX OE(2T, 0.5T) = (3, 3)
8252 13:21:54.932691
8253 13:21:54.932794
8254 13:21:54.942652 [DQSOSCAuto] RK1, (LSB)MR18= 0x200d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8255 13:21:54.942737 CH0 RK1: MR19=303, MR18=200D
8256 13:21:54.949280 CH0_RK1: MR19=0x303, MR18=0x200D, DQSOSC=393, MR23=63, INC=23, DEC=15
8257 13:21:54.952434 [RxdqsGatingPostProcess] freq 1600
8258 13:21:54.959279 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8259 13:21:54.962942 best DQS0 dly(2T, 0.5T) = (1, 1)
8260 13:21:54.966390 best DQS1 dly(2T, 0.5T) = (1, 1)
8261 13:21:54.966474 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8262 13:21:54.969632 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8263 13:21:54.972467 best DQS0 dly(2T, 0.5T) = (1, 1)
8264 13:21:54.975859 best DQS1 dly(2T, 0.5T) = (1, 1)
8265 13:21:54.979213 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8266 13:21:54.982837 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8267 13:21:54.986161 Pre-setting of DQS Precalculation
8268 13:21:54.989616 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8269 13:21:54.992863 ==
8270 13:21:54.996041 Dram Type= 6, Freq= 0, CH_1, rank 0
8271 13:21:54.999547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8272 13:21:54.999633 ==
8273 13:21:55.002814 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8274 13:21:55.009646 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8275 13:21:55.012788 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8276 13:21:55.019576 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8277 13:21:55.027361 [CA 0] Center 42 (12~72) winsize 61
8278 13:21:55.031283 [CA 1] Center 42 (12~72) winsize 61
8279 13:21:55.034292 [CA 2] Center 38 (9~68) winsize 60
8280 13:21:55.037228 [CA 3] Center 37 (8~67) winsize 60
8281 13:21:55.040498 [CA 4] Center 37 (7~68) winsize 62
8282 13:21:55.043901 [CA 5] Center 37 (7~67) winsize 61
8283 13:21:55.044017
8284 13:21:55.047253 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8285 13:21:55.047377
8286 13:21:55.050356 [CATrainingPosCal] consider 1 rank data
8287 13:21:55.053846 u2DelayCellTimex100 = 290/100 ps
8288 13:21:55.056926 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8289 13:21:55.063599 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8290 13:21:55.067064 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8291 13:21:55.070283 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8292 13:21:55.074086 CA4 delay=37 (7~68),Diff = 0 PI (0 cell)
8293 13:21:55.077020 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8294 13:21:55.077102
8295 13:21:55.080217 CA PerBit enable=1, Macro0, CA PI delay=37
8296 13:21:55.080299
8297 13:21:55.083597 [CBTSetCACLKResult] CA Dly = 37
8298 13:21:55.087211 CS Dly: 9 (0~40)
8299 13:21:55.090398 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8300 13:21:55.093545 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8301 13:21:55.093643 ==
8302 13:21:55.096842 Dram Type= 6, Freq= 0, CH_1, rank 1
8303 13:21:55.100514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 13:21:55.103765 ==
8305 13:21:55.106935 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8306 13:21:55.110408 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8307 13:21:55.116927 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8308 13:21:55.120299 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8309 13:21:55.130176 [CA 0] Center 42 (13~72) winsize 60
8310 13:21:55.133578 [CA 1] Center 42 (13~72) winsize 60
8311 13:21:55.136984 [CA 2] Center 38 (9~68) winsize 60
8312 13:21:55.140274 [CA 3] Center 37 (8~67) winsize 60
8313 13:21:55.143333 [CA 4] Center 38 (9~68) winsize 60
8314 13:21:55.146883 [CA 5] Center 37 (8~67) winsize 60
8315 13:21:55.147010
8316 13:21:55.150304 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8317 13:21:55.150427
8318 13:21:55.153325 [CATrainingPosCal] consider 2 rank data
8319 13:21:55.156921 u2DelayCellTimex100 = 290/100 ps
8320 13:21:55.163363 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8321 13:21:55.166995 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8322 13:21:55.170413 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8323 13:21:55.173223 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8324 13:21:55.176641 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8325 13:21:55.180212 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8326 13:21:55.180331
8327 13:21:55.183495 CA PerBit enable=1, Macro0, CA PI delay=37
8328 13:21:55.183617
8329 13:21:55.186703 [CBTSetCACLKResult] CA Dly = 37
8330 13:21:55.189955 CS Dly: 10 (0~43)
8331 13:21:55.193260 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8332 13:21:55.196900 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8333 13:21:55.197024
8334 13:21:55.199922 ----->DramcWriteLeveling(PI) begin...
8335 13:21:55.200047 ==
8336 13:21:55.203318 Dram Type= 6, Freq= 0, CH_1, rank 0
8337 13:21:55.210057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 13:21:55.210183 ==
8339 13:21:55.213304 Write leveling (Byte 0): 24 => 24
8340 13:21:55.213424 Write leveling (Byte 1): 28 => 28
8341 13:21:55.216658 DramcWriteLeveling(PI) end<-----
8342 13:21:55.216814
8343 13:21:55.216924 ==
8344 13:21:55.219784 Dram Type= 6, Freq= 0, CH_1, rank 0
8345 13:21:55.226347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8346 13:21:55.226446 ==
8347 13:21:55.229929 [Gating] SW mode calibration
8348 13:21:55.236349 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8349 13:21:55.239894 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8350 13:21:55.246664 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 13:21:55.249971 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 13:21:55.253101 1 4 8 | B1->B0 | 2424 3131 | 0 1 | (0 0) (0 0)
8353 13:21:55.259995 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8354 13:21:55.263053 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8355 13:21:55.266666 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8356 13:21:55.273171 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8357 13:21:55.276582 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8358 13:21:55.279584 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8359 13:21:55.283102 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 13:21:55.289768 1 5 8 | B1->B0 | 3131 2a2a | 0 1 | (0 1) (1 0)
8361 13:21:55.293013 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8362 13:21:55.296445 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8363 13:21:55.302860 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 13:21:55.306442 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 13:21:55.309879 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 13:21:55.316257 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 13:21:55.319577 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8368 13:21:55.323227 1 6 8 | B1->B0 | 3737 4545 | 1 0 | (0 0) (0 0)
8369 13:21:55.329489 1 6 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
8370 13:21:55.332954 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 13:21:55.336431 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 13:21:55.343246 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 13:21:55.346013 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 13:21:55.349376 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 13:21:55.355973 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8376 13:21:55.359306 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8377 13:21:55.362897 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8378 13:21:55.369394 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 13:21:55.373183 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 13:21:55.376004 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 13:21:55.382847 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 13:21:55.386104 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 13:21:55.389258 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 13:21:55.392927 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 13:21:55.399528 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 13:21:55.402864 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 13:21:55.406207 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 13:21:55.412859 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 13:21:55.416203 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 13:21:55.419741 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 13:21:55.425991 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8392 13:21:55.429432 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8393 13:21:55.432588 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8394 13:21:55.436269 Total UI for P1: 0, mck2ui 16
8395 13:21:55.439578 best dqsien dly found for B0: ( 1, 9, 6)
8396 13:21:55.446195 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 13:21:55.446265 Total UI for P1: 0, mck2ui 16
8398 13:21:55.452877 best dqsien dly found for B1: ( 1, 9, 12)
8399 13:21:55.456277 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8400 13:21:55.459457 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8401 13:21:55.459557
8402 13:21:55.462582 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8403 13:21:55.466126 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8404 13:21:55.469474 [Gating] SW calibration Done
8405 13:21:55.469572 ==
8406 13:21:55.472806 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 13:21:55.476110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 13:21:55.476209 ==
8409 13:21:55.479233 RX Vref Scan: 0
8410 13:21:55.479330
8411 13:21:55.479420 RX Vref 0 -> 0, step: 1
8412 13:21:55.479511
8413 13:21:55.482597 RX Delay 0 -> 252, step: 8
8414 13:21:55.486249 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8415 13:21:55.492962 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8416 13:21:55.496035 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8417 13:21:55.499380 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8418 13:21:55.502786 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8419 13:21:55.506020 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8420 13:21:55.509334 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8421 13:21:55.515832 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8422 13:21:55.519270 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8423 13:21:55.522944 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8424 13:21:55.525807 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8425 13:21:55.529243 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8426 13:21:55.536279 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8427 13:21:55.539189 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8428 13:21:55.542662 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8429 13:21:55.545856 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8430 13:21:55.545928 ==
8431 13:21:55.549119 Dram Type= 6, Freq= 0, CH_1, rank 0
8432 13:21:55.555899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8433 13:21:55.555981 ==
8434 13:21:55.556047 DQS Delay:
8435 13:21:55.556109 DQS0 = 0, DQS1 = 0
8436 13:21:55.559322 DQM Delay:
8437 13:21:55.559394 DQM0 = 139, DQM1 = 131
8438 13:21:55.562519 DQ Delay:
8439 13:21:55.565769 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8440 13:21:55.569770 DQ4 =139, DQ5 =147, DQ6 =147, DQ7 =135
8441 13:21:55.572222 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8442 13:21:55.575659 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8443 13:21:55.575735
8444 13:21:55.575798
8445 13:21:55.575858 ==
8446 13:21:55.579031 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 13:21:55.582635 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 13:21:55.585982 ==
8449 13:21:55.586057
8450 13:21:55.586121
8451 13:21:55.586181 TX Vref Scan disable
8452 13:21:55.589190 == TX Byte 0 ==
8453 13:21:55.592360 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8454 13:21:55.595828 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8455 13:21:55.599004 == TX Byte 1 ==
8456 13:21:55.602010 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8457 13:21:55.605279 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8458 13:21:55.608882 ==
8459 13:21:55.608978 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 13:21:55.615430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 13:21:55.615558 ==
8462 13:21:55.627825
8463 13:21:55.631310 TX Vref early break, caculate TX vref
8464 13:21:55.634135 TX Vref=16, minBit 10, minWin=22, winSum=371
8465 13:21:55.637223 TX Vref=18, minBit 10, minWin=23, winSum=385
8466 13:21:55.640741 TX Vref=20, minBit 3, minWin=24, winSum=393
8467 13:21:55.643993 TX Vref=22, minBit 12, minWin=24, winSum=401
8468 13:21:55.651072 TX Vref=24, minBit 15, minWin=24, winSum=418
8469 13:21:55.654083 TX Vref=26, minBit 3, minWin=25, winSum=418
8470 13:21:55.657447 TX Vref=28, minBit 15, minWin=25, winSum=426
8471 13:21:55.660538 TX Vref=30, minBit 10, minWin=24, winSum=417
8472 13:21:55.663970 TX Vref=32, minBit 10, minWin=25, winSum=418
8473 13:21:55.667559 TX Vref=34, minBit 10, minWin=24, winSum=402
8474 13:21:55.674024 [TxChooseVref] Worse bit 15, Min win 25, Win sum 426, Final Vref 28
8475 13:21:55.674150
8476 13:21:55.677474 Final TX Range 0 Vref 28
8477 13:21:55.677595
8478 13:21:55.677707 ==
8479 13:21:55.680989 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 13:21:55.684117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 13:21:55.684239 ==
8482 13:21:55.684353
8483 13:21:55.684462
8484 13:21:55.687461 TX Vref Scan disable
8485 13:21:55.693992 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8486 13:21:55.694116 == TX Byte 0 ==
8487 13:21:55.697410 u2DelayCellOfst[0]=16 cells (5 PI)
8488 13:21:55.700705 u2DelayCellOfst[1]=6 cells (2 PI)
8489 13:21:55.703756 u2DelayCellOfst[2]=0 cells (0 PI)
8490 13:21:55.707355 u2DelayCellOfst[3]=6 cells (2 PI)
8491 13:21:55.710391 u2DelayCellOfst[4]=6 cells (2 PI)
8492 13:21:55.713796 u2DelayCellOfst[5]=16 cells (5 PI)
8493 13:21:55.717266 u2DelayCellOfst[6]=16 cells (5 PI)
8494 13:21:55.720896 u2DelayCellOfst[7]=3 cells (1 PI)
8495 13:21:55.723936 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8496 13:21:55.727400 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8497 13:21:55.730535 == TX Byte 1 ==
8498 13:21:55.734244 u2DelayCellOfst[8]=0 cells (0 PI)
8499 13:21:55.734315 u2DelayCellOfst[9]=0 cells (0 PI)
8500 13:21:55.737880 u2DelayCellOfst[10]=6 cells (2 PI)
8501 13:21:55.740905 u2DelayCellOfst[11]=3 cells (1 PI)
8502 13:21:55.744192 u2DelayCellOfst[12]=13 cells (4 PI)
8503 13:21:55.747226 u2DelayCellOfst[13]=13 cells (4 PI)
8504 13:21:55.750666 u2DelayCellOfst[14]=13 cells (4 PI)
8505 13:21:55.754207 u2DelayCellOfst[15]=10 cells (3 PI)
8506 13:21:55.757952 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8507 13:21:55.763917 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8508 13:21:55.763997 DramC Write-DBI on
8509 13:21:55.764062 ==
8510 13:21:55.767340 Dram Type= 6, Freq= 0, CH_1, rank 0
8511 13:21:55.770795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8512 13:21:55.774150 ==
8513 13:21:55.774256
8514 13:21:55.774347
8515 13:21:55.774434 TX Vref Scan disable
8516 13:21:55.777641 == TX Byte 0 ==
8517 13:21:55.780591 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8518 13:21:55.784462 == TX Byte 1 ==
8519 13:21:55.787171 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8520 13:21:55.790600 DramC Write-DBI off
8521 13:21:55.790683
8522 13:21:55.790750 [DATLAT]
8523 13:21:55.790842 Freq=1600, CH1 RK0
8524 13:21:55.790903
8525 13:21:55.793880 DATLAT Default: 0xf
8526 13:21:55.793963 0, 0xFFFF, sum = 0
8527 13:21:55.797371 1, 0xFFFF, sum = 0
8528 13:21:55.800612 2, 0xFFFF, sum = 0
8529 13:21:55.800697 3, 0xFFFF, sum = 0
8530 13:21:55.803919 4, 0xFFFF, sum = 0
8531 13:21:55.804003 5, 0xFFFF, sum = 0
8532 13:21:55.807869 6, 0xFFFF, sum = 0
8533 13:21:55.808029 7, 0xFFFF, sum = 0
8534 13:21:55.810177 8, 0xFFFF, sum = 0
8535 13:21:55.810262 9, 0xFFFF, sum = 0
8536 13:21:55.813753 10, 0xFFFF, sum = 0
8537 13:21:55.813839 11, 0xFFFF, sum = 0
8538 13:21:55.817079 12, 0xFFFF, sum = 0
8539 13:21:55.817211 13, 0xFFFF, sum = 0
8540 13:21:55.820193 14, 0x0, sum = 1
8541 13:21:55.820278 15, 0x0, sum = 2
8542 13:21:55.823670 16, 0x0, sum = 3
8543 13:21:55.823755 17, 0x0, sum = 4
8544 13:21:55.827461 best_step = 15
8545 13:21:55.827544
8546 13:21:55.827611 ==
8547 13:21:55.830416 Dram Type= 6, Freq= 0, CH_1, rank 0
8548 13:21:55.833395 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8549 13:21:55.833480 ==
8550 13:21:55.837016 RX Vref Scan: 1
8551 13:21:55.837099
8552 13:21:55.837166 Set Vref Range= 24 -> 127
8553 13:21:55.837227
8554 13:21:55.840728 RX Vref 24 -> 127, step: 1
8555 13:21:55.840850
8556 13:21:55.843458 RX Delay 19 -> 252, step: 4
8557 13:21:55.843558
8558 13:21:55.847290 Set Vref, RX VrefLevel [Byte0]: 24
8559 13:21:55.850253 [Byte1]: 24
8560 13:21:55.850393
8561 13:21:55.853807 Set Vref, RX VrefLevel [Byte0]: 25
8562 13:21:55.856988 [Byte1]: 25
8563 13:21:55.857109
8564 13:21:55.860671 Set Vref, RX VrefLevel [Byte0]: 26
8565 13:21:55.863302 [Byte1]: 26
8566 13:21:55.867423
8567 13:21:55.867537 Set Vref, RX VrefLevel [Byte0]: 27
8568 13:21:55.871146 [Byte1]: 27
8569 13:21:55.875176
8570 13:21:55.875302 Set Vref, RX VrefLevel [Byte0]: 28
8571 13:21:55.878177 [Byte1]: 28
8572 13:21:55.882983
8573 13:21:55.883108 Set Vref, RX VrefLevel [Byte0]: 29
8574 13:21:55.886035 [Byte1]: 29
8575 13:21:55.890418
8576 13:21:55.890537 Set Vref, RX VrefLevel [Byte0]: 30
8577 13:21:55.893419 [Byte1]: 30
8578 13:21:55.897662
8579 13:21:55.897800 Set Vref, RX VrefLevel [Byte0]: 31
8580 13:21:55.901147 [Byte1]: 31
8581 13:21:55.905374
8582 13:21:55.905496 Set Vref, RX VrefLevel [Byte0]: 32
8583 13:21:55.909056 [Byte1]: 32
8584 13:21:55.913163
8585 13:21:55.913277 Set Vref, RX VrefLevel [Byte0]: 33
8586 13:21:55.916115 [Byte1]: 33
8587 13:21:55.920661
8588 13:21:55.920791 Set Vref, RX VrefLevel [Byte0]: 34
8589 13:21:55.923826 [Byte1]: 34
8590 13:21:55.928127
8591 13:21:55.928211 Set Vref, RX VrefLevel [Byte0]: 35
8592 13:21:55.931353 [Byte1]: 35
8593 13:21:55.935526
8594 13:21:55.935611 Set Vref, RX VrefLevel [Byte0]: 36
8595 13:21:55.939088 [Byte1]: 36
8596 13:21:55.943505
8597 13:21:55.943591 Set Vref, RX VrefLevel [Byte0]: 37
8598 13:21:55.946513 [Byte1]: 37
8599 13:21:55.950739
8600 13:21:55.950828 Set Vref, RX VrefLevel [Byte0]: 38
8601 13:21:55.953984 [Byte1]: 38
8602 13:21:55.958539
8603 13:21:55.958624 Set Vref, RX VrefLevel [Byte0]: 39
8604 13:21:55.961717 [Byte1]: 39
8605 13:21:55.965860
8606 13:21:55.965945 Set Vref, RX VrefLevel [Byte0]: 40
8607 13:21:55.969143 [Byte1]: 40
8608 13:21:55.973673
8609 13:21:55.973758 Set Vref, RX VrefLevel [Byte0]: 41
8610 13:21:55.976667 [Byte1]: 41
8611 13:21:55.980936
8612 13:21:55.981021 Set Vref, RX VrefLevel [Byte0]: 42
8613 13:21:55.984247 [Byte1]: 42
8614 13:21:55.988532
8615 13:21:55.988617 Set Vref, RX VrefLevel [Byte0]: 43
8616 13:21:55.991896 [Byte1]: 43
8617 13:21:55.995953
8618 13:21:55.996038 Set Vref, RX VrefLevel [Byte0]: 44
8619 13:21:55.999595 [Byte1]: 44
8620 13:21:56.004105
8621 13:21:56.004190 Set Vref, RX VrefLevel [Byte0]: 45
8622 13:21:56.007107 [Byte1]: 45
8623 13:21:56.011615
8624 13:21:56.011700 Set Vref, RX VrefLevel [Byte0]: 46
8625 13:21:56.015252 [Byte1]: 46
8626 13:21:56.019001
8627 13:21:56.019079 Set Vref, RX VrefLevel [Byte0]: 47
8628 13:21:56.022244 [Byte1]: 47
8629 13:21:56.026490
8630 13:21:56.026601 Set Vref, RX VrefLevel [Byte0]: 48
8631 13:21:56.029865 [Byte1]: 48
8632 13:21:56.034047
8633 13:21:56.034148 Set Vref, RX VrefLevel [Byte0]: 49
8634 13:21:56.037129 [Byte1]: 49
8635 13:21:56.041418
8636 13:21:56.041547 Set Vref, RX VrefLevel [Byte0]: 50
8637 13:21:56.044896 [Byte1]: 50
8638 13:21:56.049220
8639 13:21:56.049335 Set Vref, RX VrefLevel [Byte0]: 51
8640 13:21:56.052348 [Byte1]: 51
8641 13:21:56.056589
8642 13:21:56.056675 Set Vref, RX VrefLevel [Byte0]: 52
8643 13:21:56.059990 [Byte1]: 52
8644 13:21:56.064419
8645 13:21:56.064505 Set Vref, RX VrefLevel [Byte0]: 53
8646 13:21:56.067783 [Byte1]: 53
8647 13:21:56.072135
8648 13:21:56.072248 Set Vref, RX VrefLevel [Byte0]: 54
8649 13:21:56.075180 [Byte1]: 54
8650 13:21:56.079510
8651 13:21:56.079596 Set Vref, RX VrefLevel [Byte0]: 55
8652 13:21:56.082614 [Byte1]: 55
8653 13:21:56.086891
8654 13:21:56.087024 Set Vref, RX VrefLevel [Byte0]: 56
8655 13:21:56.090394 [Byte1]: 56
8656 13:21:56.094458
8657 13:21:56.094544 Set Vref, RX VrefLevel [Byte0]: 57
8658 13:21:56.098231 [Byte1]: 57
8659 13:21:56.102399
8660 13:21:56.102485 Set Vref, RX VrefLevel [Byte0]: 58
8661 13:21:56.105428 [Byte1]: 58
8662 13:21:56.110242
8663 13:21:56.110331 Set Vref, RX VrefLevel [Byte0]: 59
8664 13:21:56.113593 [Byte1]: 59
8665 13:21:56.117297
8666 13:21:56.117383 Set Vref, RX VrefLevel [Byte0]: 60
8667 13:21:56.120612 [Byte1]: 60
8668 13:21:56.124813
8669 13:21:56.124900 Set Vref, RX VrefLevel [Byte0]: 61
8670 13:21:56.128379 [Byte1]: 61
8671 13:21:56.132647
8672 13:21:56.132736 Set Vref, RX VrefLevel [Byte0]: 62
8673 13:21:56.135761 [Byte1]: 62
8674 13:21:56.140330
8675 13:21:56.140416 Set Vref, RX VrefLevel [Byte0]: 63
8676 13:21:56.143505 [Byte1]: 63
8677 13:21:56.147772
8678 13:21:56.147858 Set Vref, RX VrefLevel [Byte0]: 64
8679 13:21:56.151128 [Byte1]: 64
8680 13:21:56.155455
8681 13:21:56.155541 Set Vref, RX VrefLevel [Byte0]: 65
8682 13:21:56.158611 [Byte1]: 65
8683 13:21:56.162925
8684 13:21:56.163011 Set Vref, RX VrefLevel [Byte0]: 66
8685 13:21:56.166595 [Byte1]: 66
8686 13:21:56.170381
8687 13:21:56.170466 Set Vref, RX VrefLevel [Byte0]: 67
8688 13:21:56.173641 [Byte1]: 67
8689 13:21:56.178036
8690 13:21:56.178119 Set Vref, RX VrefLevel [Byte0]: 68
8691 13:21:56.181097 [Byte1]: 68
8692 13:21:56.185859
8693 13:21:56.185942 Set Vref, RX VrefLevel [Byte0]: 69
8694 13:21:56.189016 [Byte1]: 69
8695 13:21:56.193235
8696 13:21:56.193318 Set Vref, RX VrefLevel [Byte0]: 70
8697 13:21:56.196223 [Byte1]: 70
8698 13:21:56.200758
8699 13:21:56.200854 Set Vref, RX VrefLevel [Byte0]: 71
8700 13:21:56.203844 [Byte1]: 71
8701 13:21:56.208148
8702 13:21:56.208232 Set Vref, RX VrefLevel [Byte0]: 72
8703 13:21:56.211907 [Byte1]: 72
8704 13:21:56.215771
8705 13:21:56.215844 Set Vref, RX VrefLevel [Byte0]: 73
8706 13:21:56.219033 [Byte1]: 73
8707 13:21:56.223446
8708 13:21:56.223529 Set Vref, RX VrefLevel [Byte0]: 74
8709 13:21:56.226599 [Byte1]: 74
8710 13:21:56.230826
8711 13:21:56.230911 Final RX Vref Byte 0 = 60 to rank0
8712 13:21:56.234423 Final RX Vref Byte 1 = 62 to rank0
8713 13:21:56.237978 Final RX Vref Byte 0 = 60 to rank1
8714 13:21:56.241166 Final RX Vref Byte 1 = 62 to rank1==
8715 13:21:56.244366 Dram Type= 6, Freq= 0, CH_1, rank 0
8716 13:21:56.251007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8717 13:21:56.251091 ==
8718 13:21:56.251158 DQS Delay:
8719 13:21:56.251221 DQS0 = 0, DQS1 = 0
8720 13:21:56.254612 DQM Delay:
8721 13:21:56.254696 DQM0 = 135, DQM1 = 128
8722 13:21:56.257546 DQ Delay:
8723 13:21:56.260807 DQ0 =138, DQ1 =130, DQ2 =124, DQ3 =132
8724 13:21:56.264214 DQ4 =134, DQ5 =146, DQ6 =148, DQ7 =132
8725 13:21:56.267493 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
8726 13:21:56.270971 DQ12 =138, DQ13 =134, DQ14 =136, DQ15 =134
8727 13:21:56.271055
8728 13:21:56.271123
8729 13:21:56.271185
8730 13:21:56.274275 [DramC_TX_OE_Calibration] TA2
8731 13:21:56.277949 Original DQ_B0 (3 6) =30, OEN = 27
8732 13:21:56.280848 Original DQ_B1 (3 6) =30, OEN = 27
8733 13:21:56.284170 24, 0x0, End_B0=24 End_B1=24
8734 13:21:56.284285 25, 0x0, End_B0=25 End_B1=25
8735 13:21:56.287586 26, 0x0, End_B0=26 End_B1=26
8736 13:21:56.291026 27, 0x0, End_B0=27 End_B1=27
8737 13:21:56.294386 28, 0x0, End_B0=28 End_B1=28
8738 13:21:56.294471 29, 0x0, End_B0=29 End_B1=29
8739 13:21:56.297379 30, 0x0, End_B0=30 End_B1=30
8740 13:21:56.301166 31, 0x4141, End_B0=30 End_B1=30
8741 13:21:56.304140 Byte0 end_step=30 best_step=27
8742 13:21:56.307480 Byte1 end_step=30 best_step=27
8743 13:21:56.310987 Byte0 TX OE(2T, 0.5T) = (3, 3)
8744 13:21:56.311087 Byte1 TX OE(2T, 0.5T) = (3, 3)
8745 13:21:56.314027
8746 13:21:56.314125
8747 13:21:56.320609 [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8748 13:21:56.324240 CH1 RK0: MR19=303, MR18=1624
8749 13:21:56.330671 CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16
8750 13:21:56.330755
8751 13:21:56.334358 ----->DramcWriteLeveling(PI) begin...
8752 13:21:56.334443 ==
8753 13:21:56.337185 Dram Type= 6, Freq= 0, CH_1, rank 1
8754 13:21:56.341204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8755 13:21:56.341288 ==
8756 13:21:56.344125 Write leveling (Byte 0): 24 => 24
8757 13:21:56.347237 Write leveling (Byte 1): 29 => 29
8758 13:21:56.350828 DramcWriteLeveling(PI) end<-----
8759 13:21:56.350911
8760 13:21:56.350977 ==
8761 13:21:56.353978 Dram Type= 6, Freq= 0, CH_1, rank 1
8762 13:21:56.357597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8763 13:21:56.357694 ==
8764 13:21:56.360475 [Gating] SW mode calibration
8765 13:21:56.367115 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8766 13:21:56.373921 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8767 13:21:56.377082 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 13:21:56.380358 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 13:21:56.387177 1 4 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8770 13:21:56.390384 1 4 12 | B1->B0 | 3434 2525 | 0 0 | (0 0) (0 0)
8771 13:21:56.393795 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 13:21:56.400638 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 13:21:56.403547 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 13:21:56.406907 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 13:21:56.413749 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 13:21:56.416988 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 13:21:56.420460 1 5 8 | B1->B0 | 2a2a 3434 | 0 1 | (1 0) (1 0)
8778 13:21:56.427015 1 5 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 1)
8779 13:21:56.430514 1 5 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8780 13:21:56.433605 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 13:21:56.440608 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 13:21:56.443958 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 13:21:56.447026 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 13:21:56.453709 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 13:21:56.457009 1 6 8 | B1->B0 | 3e3e 2323 | 0 0 | (0 0) (0 0)
8786 13:21:56.460317 1 6 12 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
8787 13:21:56.466829 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 13:21:56.470232 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 13:21:56.473507 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 13:21:56.477062 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 13:21:56.484174 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 13:21:56.486900 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 13:21:56.490402 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8794 13:21:56.496782 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8795 13:21:56.500188 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 13:21:56.503314 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 13:21:56.510369 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 13:21:56.513433 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 13:21:56.516921 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 13:21:56.523327 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 13:21:56.526609 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 13:21:56.530038 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 13:21:56.536489 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 13:21:56.540306 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 13:21:56.543278 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 13:21:56.549770 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 13:21:56.553199 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 13:21:56.556649 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 13:21:56.563104 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8810 13:21:56.566498 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8811 13:21:56.569934 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 13:21:56.573505 Total UI for P1: 0, mck2ui 16
8813 13:21:56.576487 best dqsien dly found for B0: ( 1, 9, 10)
8814 13:21:56.580111 Total UI for P1: 0, mck2ui 16
8815 13:21:56.582921 best dqsien dly found for B1: ( 1, 9, 10)
8816 13:21:56.586505 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8817 13:21:56.590056 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8818 13:21:56.590140
8819 13:21:56.596521 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8820 13:21:56.600052 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8821 13:21:56.600135 [Gating] SW calibration Done
8822 13:21:56.603131 ==
8823 13:21:56.606344 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 13:21:56.609972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 13:21:56.610056 ==
8826 13:21:56.610121 RX Vref Scan: 0
8827 13:21:56.610182
8828 13:21:56.613312 RX Vref 0 -> 0, step: 1
8829 13:21:56.613394
8830 13:21:56.616725 RX Delay 0 -> 252, step: 8
8831 13:21:56.619888 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8832 13:21:56.623299 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8833 13:21:56.626350 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8834 13:21:56.633145 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8835 13:21:56.636582 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8836 13:21:56.640101 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8837 13:21:56.643324 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8838 13:21:56.646428 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8839 13:21:56.649572 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8840 13:21:56.656233 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8841 13:21:56.659708 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8842 13:21:56.662972 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8843 13:21:56.666400 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8844 13:21:56.673062 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8845 13:21:56.676181 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8846 13:21:56.679547 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8847 13:21:56.679648 ==
8848 13:21:56.682956 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 13:21:56.686367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 13:21:56.686452 ==
8851 13:21:56.689729 DQS Delay:
8852 13:21:56.689814 DQS0 = 0, DQS1 = 0
8853 13:21:56.689881 DQM Delay:
8854 13:21:56.692874 DQM0 = 139, DQM1 = 132
8855 13:21:56.692958 DQ Delay:
8856 13:21:56.696175 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =139
8857 13:21:56.700021 DQ4 =139, DQ5 =151, DQ6 =143, DQ7 =139
8858 13:21:56.706116 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8859 13:21:56.709500 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8860 13:21:56.709597
8861 13:21:56.709663
8862 13:21:56.709725 ==
8863 13:21:56.712867 Dram Type= 6, Freq= 0, CH_1, rank 1
8864 13:21:56.716170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8865 13:21:56.716253 ==
8866 13:21:56.716319
8867 13:21:56.716398
8868 13:21:56.719592 TX Vref Scan disable
8869 13:21:56.722996 == TX Byte 0 ==
8870 13:21:56.726225 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8871 13:21:56.729539 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8872 13:21:56.732520 == TX Byte 1 ==
8873 13:21:56.735872 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8874 13:21:56.739263 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8875 13:21:56.739382 ==
8876 13:21:56.742413 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 13:21:56.745771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 13:21:56.749029 ==
8879 13:21:56.760216
8880 13:21:56.763810 TX Vref early break, caculate TX vref
8881 13:21:56.767168 TX Vref=16, minBit 13, minWin=22, winSum=383
8882 13:21:56.770545 TX Vref=18, minBit 9, minWin=22, winSum=393
8883 13:21:56.773769 TX Vref=20, minBit 13, minWin=23, winSum=403
8884 13:21:56.777006 TX Vref=22, minBit 9, minWin=24, winSum=413
8885 13:21:56.780383 TX Vref=24, minBit 15, minWin=24, winSum=417
8886 13:21:56.786914 TX Vref=26, minBit 9, minWin=25, winSum=425
8887 13:21:56.790347 TX Vref=28, minBit 10, minWin=25, winSum=425
8888 13:21:56.794290 TX Vref=30, minBit 10, minWin=25, winSum=419
8889 13:21:56.796991 TX Vref=32, minBit 11, minWin=24, winSum=410
8890 13:21:56.800556 TX Vref=34, minBit 10, minWin=23, winSum=401
8891 13:21:56.807332 [TxChooseVref] Worse bit 9, Min win 25, Win sum 425, Final Vref 26
8892 13:21:56.807468
8893 13:21:56.810488 Final TX Range 0 Vref 26
8894 13:21:56.810620
8895 13:21:56.810732 ==
8896 13:21:56.813884 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 13:21:56.817224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 13:21:56.817348 ==
8899 13:21:56.817467
8900 13:21:56.817578
8901 13:21:56.820713 TX Vref Scan disable
8902 13:21:56.826982 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8903 13:21:56.827069 == TX Byte 0 ==
8904 13:21:56.830523 u2DelayCellOfst[0]=13 cells (4 PI)
8905 13:21:56.833916 u2DelayCellOfst[1]=10 cells (3 PI)
8906 13:21:56.837436 u2DelayCellOfst[2]=0 cells (0 PI)
8907 13:21:56.840494 u2DelayCellOfst[3]=3 cells (1 PI)
8908 13:21:56.843751 u2DelayCellOfst[4]=6 cells (2 PI)
8909 13:21:56.847253 u2DelayCellOfst[5]=16 cells (5 PI)
8910 13:21:56.850422 u2DelayCellOfst[6]=13 cells (4 PI)
8911 13:21:56.853680 u2DelayCellOfst[7]=3 cells (1 PI)
8912 13:21:56.857190 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8913 13:21:56.860518 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8914 13:21:56.863768 == TX Byte 1 ==
8915 13:21:56.863840 u2DelayCellOfst[8]=0 cells (0 PI)
8916 13:21:56.866905 u2DelayCellOfst[9]=3 cells (1 PI)
8917 13:21:56.869947 u2DelayCellOfst[10]=10 cells (3 PI)
8918 13:21:56.873440 u2DelayCellOfst[11]=3 cells (1 PI)
8919 13:21:56.876674 u2DelayCellOfst[12]=13 cells (4 PI)
8920 13:21:56.880205 u2DelayCellOfst[13]=13 cells (4 PI)
8921 13:21:56.883386 u2DelayCellOfst[14]=16 cells (5 PI)
8922 13:21:56.886992 u2DelayCellOfst[15]=13 cells (4 PI)
8923 13:21:56.890136 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8924 13:21:56.897135 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8925 13:21:56.897261 DramC Write-DBI on
8926 13:21:56.897381 ==
8927 13:21:56.900723 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 13:21:56.903303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 13:21:56.906802 ==
8930 13:21:56.906934
8931 13:21:56.907052
8932 13:21:56.907165 TX Vref Scan disable
8933 13:21:56.910363 == TX Byte 0 ==
8934 13:21:56.913780 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8935 13:21:56.916998 == TX Byte 1 ==
8936 13:21:56.920316 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8937 13:21:56.923677 DramC Write-DBI off
8938 13:21:56.923778
8939 13:21:56.923873 [DATLAT]
8940 13:21:56.923962 Freq=1600, CH1 RK1
8941 13:21:56.924050
8942 13:21:56.926823 DATLAT Default: 0xf
8943 13:21:56.926927 0, 0xFFFF, sum = 0
8944 13:21:56.930158 1, 0xFFFF, sum = 0
8945 13:21:56.933683 2, 0xFFFF, sum = 0
8946 13:21:56.933762 3, 0xFFFF, sum = 0
8947 13:21:56.936876 4, 0xFFFF, sum = 0
8948 13:21:56.936952 5, 0xFFFF, sum = 0
8949 13:21:56.940403 6, 0xFFFF, sum = 0
8950 13:21:56.940479 7, 0xFFFF, sum = 0
8951 13:21:56.943527 8, 0xFFFF, sum = 0
8952 13:21:56.943626 9, 0xFFFF, sum = 0
8953 13:21:56.947258 10, 0xFFFF, sum = 0
8954 13:21:56.947360 11, 0xFFFF, sum = 0
8955 13:21:56.950043 12, 0xFFFF, sum = 0
8956 13:21:56.950118 13, 0xFFFF, sum = 0
8957 13:21:56.953926 14, 0x0, sum = 1
8958 13:21:56.954028 15, 0x0, sum = 2
8959 13:21:56.957050 16, 0x0, sum = 3
8960 13:21:56.957135 17, 0x0, sum = 4
8961 13:21:56.960320 best_step = 15
8962 13:21:56.960416
8963 13:21:56.960538 ==
8964 13:21:56.963575 Dram Type= 6, Freq= 0, CH_1, rank 1
8965 13:21:56.967016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8966 13:21:56.967100 ==
8967 13:21:56.967165 RX Vref Scan: 0
8968 13:21:56.969984
8969 13:21:56.970066 RX Vref 0 -> 0, step: 1
8970 13:21:56.970132
8971 13:21:56.973281 RX Delay 19 -> 252, step: 4
8972 13:21:56.976931 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8973 13:21:56.983683 iDelay=195, Bit 1, Center 132 (87 ~ 178) 92
8974 13:21:56.986682 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8975 13:21:56.990100 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8976 13:21:56.993765 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8977 13:21:56.996608 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8978 13:21:56.999953 iDelay=195, Bit 6, Center 144 (99 ~ 190) 92
8979 13:21:57.006956 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8980 13:21:57.009794 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8981 13:21:57.013323 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8982 13:21:57.016559 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8983 13:21:57.020006 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8984 13:21:57.026320 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8985 13:21:57.029837 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8986 13:21:57.033335 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8987 13:21:57.036239 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8988 13:21:57.036337 ==
8989 13:21:57.040196 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 13:21:57.046244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 13:21:57.046344 ==
8992 13:21:57.046445 DQS Delay:
8993 13:21:57.050003 DQS0 = 0, DQS1 = 0
8994 13:21:57.050086 DQM Delay:
8995 13:21:57.053261 DQM0 = 134, DQM1 = 129
8996 13:21:57.053344 DQ Delay:
8997 13:21:57.056368 DQ0 =138, DQ1 =132, DQ2 =120, DQ3 =132
8998 13:21:57.059689 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132
8999 13:21:57.062947 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
9000 13:21:57.066333 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =140
9001 13:21:57.066416
9002 13:21:57.066482
9003 13:21:57.066543
9004 13:21:57.069538 [DramC_TX_OE_Calibration] TA2
9005 13:21:57.073161 Original DQ_B0 (3 6) =30, OEN = 27
9006 13:21:57.076479 Original DQ_B1 (3 6) =30, OEN = 27
9007 13:21:57.079701 24, 0x0, End_B0=24 End_B1=24
9008 13:21:57.079785 25, 0x0, End_B0=25 End_B1=25
9009 13:21:57.082960 26, 0x0, End_B0=26 End_B1=26
9010 13:21:57.086596 27, 0x0, End_B0=27 End_B1=27
9011 13:21:57.089781 28, 0x0, End_B0=28 End_B1=28
9012 13:21:57.093142 29, 0x0, End_B0=29 End_B1=29
9013 13:21:57.093226 30, 0x0, End_B0=30 End_B1=30
9014 13:21:57.096331 31, 0x4141, End_B0=30 End_B1=30
9015 13:21:57.099609 Byte0 end_step=30 best_step=27
9016 13:21:57.103086 Byte1 end_step=30 best_step=27
9017 13:21:57.106485 Byte0 TX OE(2T, 0.5T) = (3, 3)
9018 13:21:57.109676 Byte1 TX OE(2T, 0.5T) = (3, 3)
9019 13:21:57.109775
9020 13:21:57.109864
9021 13:21:57.116271 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
9022 13:21:57.119586 CH1 RK1: MR19=303, MR18=1F0A
9023 13:21:57.126066 CH1_RK1: MR19=0x303, MR18=0x1F0A, DQSOSC=394, MR23=63, INC=23, DEC=15
9024 13:21:57.129475 [RxdqsGatingPostProcess] freq 1600
9025 13:21:57.132895 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9026 13:21:57.136087 best DQS0 dly(2T, 0.5T) = (1, 1)
9027 13:21:57.139559 best DQS1 dly(2T, 0.5T) = (1, 1)
9028 13:21:57.142953 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9029 13:21:57.146147 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9030 13:21:57.149593 best DQS0 dly(2T, 0.5T) = (1, 1)
9031 13:21:57.153078 best DQS1 dly(2T, 0.5T) = (1, 1)
9032 13:21:57.156190 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9033 13:21:57.159561 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9034 13:21:57.163034 Pre-setting of DQS Precalculation
9035 13:21:57.166219 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9036 13:21:57.172713 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9037 13:21:57.179502 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9038 13:21:57.179611
9039 13:21:57.182799
9040 13:21:57.182878 [Calibration Summary] 3200 Mbps
9041 13:21:57.186060 CH 0, Rank 0
9042 13:21:57.186138 SW Impedance : PASS
9043 13:21:57.189544 DUTY Scan : NO K
9044 13:21:57.192841 ZQ Calibration : PASS
9045 13:21:57.192916 Jitter Meter : NO K
9046 13:21:57.196524 CBT Training : PASS
9047 13:21:57.199551 Write leveling : PASS
9048 13:21:57.199626 RX DQS gating : PASS
9049 13:21:57.202967 RX DQ/DQS(RDDQC) : PASS
9050 13:21:57.206107 TX DQ/DQS : PASS
9051 13:21:57.206202 RX DATLAT : PASS
9052 13:21:57.209267 RX DQ/DQS(Engine): PASS
9053 13:21:57.212670 TX OE : PASS
9054 13:21:57.212792 All Pass.
9055 13:21:57.212862
9056 13:21:57.212923 CH 0, Rank 1
9057 13:21:57.215902 SW Impedance : PASS
9058 13:21:57.219315 DUTY Scan : NO K
9059 13:21:57.219390 ZQ Calibration : PASS
9060 13:21:57.222571 Jitter Meter : NO K
9061 13:21:57.226101 CBT Training : PASS
9062 13:21:57.226194 Write leveling : PASS
9063 13:21:57.229337 RX DQS gating : PASS
9064 13:21:57.229416 RX DQ/DQS(RDDQC) : PASS
9065 13:21:57.233079 TX DQ/DQS : PASS
9066 13:21:57.235658 RX DATLAT : PASS
9067 13:21:57.235734 RX DQ/DQS(Engine): PASS
9068 13:21:57.239225 TX OE : PASS
9069 13:21:57.239302 All Pass.
9070 13:21:57.239366
9071 13:21:57.242342 CH 1, Rank 0
9072 13:21:57.242418 SW Impedance : PASS
9073 13:21:57.245724 DUTY Scan : NO K
9074 13:21:57.248992 ZQ Calibration : PASS
9075 13:21:57.249065 Jitter Meter : NO K
9076 13:21:57.252543 CBT Training : PASS
9077 13:21:57.255853 Write leveling : PASS
9078 13:21:57.255928 RX DQS gating : PASS
9079 13:21:57.259215 RX DQ/DQS(RDDQC) : PASS
9080 13:21:57.262483 TX DQ/DQS : PASS
9081 13:21:57.262557 RX DATLAT : PASS
9082 13:21:57.265964 RX DQ/DQS(Engine): PASS
9083 13:21:57.269082 TX OE : PASS
9084 13:21:57.269158 All Pass.
9085 13:21:57.269223
9086 13:21:57.269286 CH 1, Rank 1
9087 13:21:57.272560 SW Impedance : PASS
9088 13:21:57.275477 DUTY Scan : NO K
9089 13:21:57.275551 ZQ Calibration : PASS
9090 13:21:57.279098 Jitter Meter : NO K
9091 13:21:57.279172 CBT Training : PASS
9092 13:21:57.282641 Write leveling : PASS
9093 13:21:57.285616 RX DQS gating : PASS
9094 13:21:57.285694 RX DQ/DQS(RDDQC) : PASS
9095 13:21:57.289133 TX DQ/DQS : PASS
9096 13:21:57.292186 RX DATLAT : PASS
9097 13:21:57.292265 RX DQ/DQS(Engine): PASS
9098 13:21:57.295725 TX OE : PASS
9099 13:21:57.295815 All Pass.
9100 13:21:57.295911
9101 13:21:57.299411 DramC Write-DBI on
9102 13:21:57.302318 PER_BANK_REFRESH: Hybrid Mode
9103 13:21:57.302396 TX_TRACKING: ON
9104 13:21:57.312319 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9105 13:21:57.318934 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9106 13:21:57.325388 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9107 13:21:57.332212 [FAST_K] Save calibration result to emmc
9108 13:21:57.332334 sync common calibartion params.
9109 13:21:57.335549 sync cbt_mode0:1, 1:1
9110 13:21:57.338700 dram_init: ddr_geometry: 2
9111 13:21:57.338858 dram_init: ddr_geometry: 2
9112 13:21:57.341939 dram_init: ddr_geometry: 2
9113 13:21:57.345390 0:dram_rank_size:100000000
9114 13:21:57.348591 1:dram_rank_size:100000000
9115 13:21:57.351841 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9116 13:21:57.355557 DFS_SHUFFLE_HW_MODE: ON
9117 13:21:57.358677 dramc_set_vcore_voltage set vcore to 725000
9118 13:21:57.362240 Read voltage for 1600, 0
9119 13:21:57.362341 Vio18 = 0
9120 13:21:57.365057 Vcore = 725000
9121 13:21:57.365161 Vdram = 0
9122 13:21:57.365253 Vddq = 0
9123 13:21:57.365342 Vmddr = 0
9124 13:21:57.368803 switch to 3200 Mbps bootup
9125 13:21:57.371701 [DramcRunTimeConfig]
9126 13:21:57.371774 PHYPLL
9127 13:21:57.375332 DPM_CONTROL_AFTERK: ON
9128 13:21:57.375403 PER_BANK_REFRESH: ON
9129 13:21:57.378346 REFRESH_OVERHEAD_REDUCTION: ON
9130 13:21:57.381870 CMD_PICG_NEW_MODE: OFF
9131 13:21:57.381942 XRTWTW_NEW_MODE: ON
9132 13:21:57.385073 XRTRTR_NEW_MODE: ON
9133 13:21:57.385147 TX_TRACKING: ON
9134 13:21:57.388647 RDSEL_TRACKING: OFF
9135 13:21:57.388717 DQS Precalculation for DVFS: ON
9136 13:21:57.391722 RX_TRACKING: OFF
9137 13:21:57.391791 HW_GATING DBG: ON
9138 13:21:57.394979 ZQCS_ENABLE_LP4: ON
9139 13:21:57.398447 RX_PICG_NEW_MODE: ON
9140 13:21:57.398518 TX_PICG_NEW_MODE: ON
9141 13:21:57.401765 ENABLE_RX_DCM_DPHY: ON
9142 13:21:57.404831 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9143 13:21:57.404943 DUMMY_READ_FOR_TRACKING: OFF
9144 13:21:57.408189 !!! SPM_CONTROL_AFTERK: OFF
9145 13:21:57.411680 !!! SPM could not control APHY
9146 13:21:57.414919 IMPEDANCE_TRACKING: ON
9147 13:21:57.415016 TEMP_SENSOR: ON
9148 13:21:57.418865 HW_SAVE_FOR_SR: OFF
9149 13:21:57.418948 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9150 13:21:57.425117 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9151 13:21:57.425213 Read ODT Tracking: ON
9152 13:21:57.428393 Refresh Rate DeBounce: ON
9153 13:21:57.432278 DFS_NO_QUEUE_FLUSH: ON
9154 13:21:57.435034 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9155 13:21:57.435117 ENABLE_DFS_RUNTIME_MRW: OFF
9156 13:21:57.438293 DDR_RESERVE_NEW_MODE: ON
9157 13:21:57.441599 MR_CBT_SWITCH_FREQ: ON
9158 13:21:57.441683 =========================
9159 13:21:57.461577 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9160 13:21:57.464527 dram_init: ddr_geometry: 2
9161 13:21:57.482794 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9162 13:21:57.486256 dram_init: dram init end (result: 0)
9163 13:21:57.492890 DRAM-K: Full calibration passed in 24541 msecs
9164 13:21:57.496447 MRC: failed to locate region type 0.
9165 13:21:57.496531 DRAM rank0 size:0x100000000,
9166 13:21:57.499518 DRAM rank1 size=0x100000000
9167 13:21:57.509267 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9168 13:21:57.516212 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9169 13:21:57.522915 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9170 13:21:57.529366 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9171 13:21:57.532729 DRAM rank0 size:0x100000000,
9172 13:21:57.536268 DRAM rank1 size=0x100000000
9173 13:21:57.536352 CBMEM:
9174 13:21:57.539195 IMD: root @ 0xfffff000 254 entries.
9175 13:21:57.542776 IMD: root @ 0xffffec00 62 entries.
9176 13:21:57.545810 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9177 13:21:57.549256 WARNING: RO_VPD is uninitialized or empty.
9178 13:21:57.555841 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9179 13:21:57.562819 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9180 13:21:57.575944 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9181 13:21:57.587036 BS: romstage times (exec / console): total (unknown) / 24034 ms
9182 13:21:57.587128
9183 13:21:57.587216
9184 13:21:57.597012 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9185 13:21:57.600480 ARM64: Exception handlers installed.
9186 13:21:57.603932 ARM64: Testing exception
9187 13:21:57.607010 ARM64: Done test exception
9188 13:21:57.607134 Enumerating buses...
9189 13:21:57.610405 Show all devs... Before device enumeration.
9190 13:21:57.614109 Root Device: enabled 1
9191 13:21:57.617353 CPU_CLUSTER: 0: enabled 1
9192 13:21:57.617494 CPU: 00: enabled 1
9193 13:21:57.620347 Compare with tree...
9194 13:21:57.620482 Root Device: enabled 1
9195 13:21:57.623891 CPU_CLUSTER: 0: enabled 1
9196 13:21:57.627159 CPU: 00: enabled 1
9197 13:21:57.627282 Root Device scanning...
9198 13:21:57.630562 scan_static_bus for Root Device
9199 13:21:57.633864 CPU_CLUSTER: 0 enabled
9200 13:21:57.637036 scan_static_bus for Root Device done
9201 13:21:57.640310 scan_bus: bus Root Device finished in 8 msecs
9202 13:21:57.640432 done
9203 13:21:57.646900 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9204 13:21:57.650343 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9205 13:21:57.656865 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9206 13:21:57.660267 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9207 13:21:57.663543 Allocating resources...
9208 13:21:57.663670 Reading resources...
9209 13:21:57.670261 Root Device read_resources bus 0 link: 0
9210 13:21:57.670388 DRAM rank0 size:0x100000000,
9211 13:21:57.673745 DRAM rank1 size=0x100000000
9212 13:21:57.676962 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9213 13:21:57.679961 CPU: 00 missing read_resources
9214 13:21:57.683690 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9215 13:21:57.689964 Root Device read_resources bus 0 link: 0 done
9216 13:21:57.690045 Done reading resources.
9217 13:21:57.696674 Show resources in subtree (Root Device)...After reading.
9218 13:21:57.700011 Root Device child on link 0 CPU_CLUSTER: 0
9219 13:21:57.703265 CPU_CLUSTER: 0 child on link 0 CPU: 00
9220 13:21:57.713546 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9221 13:21:57.713631 CPU: 00
9222 13:21:57.716606 Root Device assign_resources, bus 0 link: 0
9223 13:21:57.719862 CPU_CLUSTER: 0 missing set_resources
9224 13:21:57.723639 Root Device assign_resources, bus 0 link: 0 done
9225 13:21:57.726784 Done setting resources.
9226 13:21:57.733443 Show resources in subtree (Root Device)...After assigning values.
9227 13:21:57.736144 Root Device child on link 0 CPU_CLUSTER: 0
9228 13:21:57.739533 CPU_CLUSTER: 0 child on link 0 CPU: 00
9229 13:21:57.749784 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9230 13:21:57.749868 CPU: 00
9231 13:21:57.752935 Done allocating resources.
9232 13:21:57.756290 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9233 13:21:57.759798 Enabling resources...
9234 13:21:57.759882 done.
9235 13:21:57.766245 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9236 13:21:57.766328 Initializing devices...
9237 13:21:57.769509 Root Device init
9238 13:21:57.769592 init hardware done!
9239 13:21:57.772928 0x00000018: ctrlr->caps
9240 13:21:57.776360 52.000 MHz: ctrlr->f_max
9241 13:21:57.776444 0.400 MHz: ctrlr->f_min
9242 13:21:57.779438 0x40ff8080: ctrlr->voltages
9243 13:21:57.779523 sclk: 390625
9244 13:21:57.782728 Bus Width = 1
9245 13:21:57.782811 sclk: 390625
9246 13:21:57.786115 Bus Width = 1
9247 13:21:57.786237 Early init status = 3
9248 13:21:57.792733 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9249 13:21:57.796040 in-header: 03 fc 00 00 01 00 00 00
9250 13:21:57.799283 in-data: 00
9251 13:21:57.802453 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9252 13:21:57.807619 in-header: 03 fd 00 00 00 00 00 00
9253 13:21:57.811055 in-data:
9254 13:21:57.814354 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9255 13:21:57.818589 in-header: 03 fc 00 00 01 00 00 00
9256 13:21:57.821841 in-data: 00
9257 13:21:57.825064 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9258 13:21:57.830861 in-header: 03 fd 00 00 00 00 00 00
9259 13:21:57.834178 in-data:
9260 13:21:57.837934 [SSUSB] Setting up USB HOST controller...
9261 13:21:57.841014 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9262 13:21:57.844215 [SSUSB] phy power-on done.
9263 13:21:57.847386 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9264 13:21:57.854318 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9265 13:21:57.857458 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9266 13:21:57.864173 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9267 13:21:57.870737 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9268 13:21:57.877297 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9269 13:21:57.884052 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9270 13:21:57.890601 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9271 13:21:57.894091 SPM: binary array size = 0x9dc
9272 13:21:57.897208 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9273 13:21:57.903994 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9274 13:21:57.910821 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9275 13:21:57.913815 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9276 13:21:57.917503 configure_display: Starting display init
9277 13:21:57.954018 anx7625_power_on_init: Init interface.
9278 13:21:57.957658 anx7625_disable_pd_protocol: Disabled PD feature.
9279 13:21:57.960473 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9280 13:21:57.988518 anx7625_start_dp_work: Secure OCM version=00
9281 13:21:57.991676 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9282 13:21:58.006468 sp_tx_get_edid_block: EDID Block = 1
9283 13:21:58.109260 Extracted contents:
9284 13:21:58.112362 header: 00 ff ff ff ff ff ff 00
9285 13:21:58.115672 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9286 13:21:58.118949 version: 01 04
9287 13:21:58.122478 basic params: 95 1f 11 78 0a
9288 13:21:58.125782 chroma info: 76 90 94 55 54 90 27 21 50 54
9289 13:21:58.128840 established: 00 00 00
9290 13:21:58.135580 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9291 13:21:58.139287 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9292 13:21:58.145786 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9293 13:21:58.152398 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9294 13:21:58.158938 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9295 13:21:58.162189 extensions: 00
9296 13:21:58.162269 checksum: fb
9297 13:21:58.162333
9298 13:21:58.165517 Manufacturer: IVO Model 57d Serial Number 0
9299 13:21:58.168894 Made week 0 of 2020
9300 13:21:58.168993 EDID version: 1.4
9301 13:21:58.172193 Digital display
9302 13:21:58.175748 6 bits per primary color channel
9303 13:21:58.175823 DisplayPort interface
9304 13:21:58.179189 Maximum image size: 31 cm x 17 cm
9305 13:21:58.182127 Gamma: 220%
9306 13:21:58.182197 Check DPMS levels
9307 13:21:58.185494 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9308 13:21:58.188978 First detailed timing is preferred timing
9309 13:21:58.192372 Established timings supported:
9310 13:21:58.195727 Standard timings supported:
9311 13:21:58.195799 Detailed timings
9312 13:21:58.202438 Hex of detail: 383680a07038204018303c0035ae10000019
9313 13:21:58.205612 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9314 13:21:58.212113 0780 0798 07c8 0820 hborder 0
9315 13:21:58.215470 0438 043b 0447 0458 vborder 0
9316 13:21:58.215574 -hsync -vsync
9317 13:21:58.218922 Did detailed timing
9318 13:21:58.222245 Hex of detail: 000000000000000000000000000000000000
9319 13:21:58.225712 Manufacturer-specified data, tag 0
9320 13:21:58.232253 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9321 13:21:58.232330 ASCII string: InfoVision
9322 13:21:58.238655 Hex of detail: 000000fe00523134304e574635205248200a
9323 13:21:58.242210 ASCII string: R140NWF5 RH
9324 13:21:58.242308 Checksum
9325 13:21:58.242370 Checksum: 0xfb (valid)
9326 13:21:58.248955 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9327 13:21:58.252278 DSI data_rate: 832800000 bps
9328 13:21:58.255539 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9329 13:21:58.258728 anx7625_parse_edid: pixelclock(138800).
9330 13:21:58.265447 hactive(1920), hsync(48), hfp(24), hbp(88)
9331 13:21:58.268719 vactive(1080), vsync(12), vfp(3), vbp(17)
9332 13:21:58.272227 anx7625_dsi_config: config dsi.
9333 13:21:58.278665 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9334 13:21:58.291232 anx7625_dsi_config: success to config DSI
9335 13:21:58.294361 anx7625_dp_start: MIPI phy setup OK.
9336 13:21:58.298098 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9337 13:21:58.301005 mtk_ddp_mode_set invalid vrefresh 60
9338 13:21:58.304554 main_disp_path_setup
9339 13:21:58.304655 ovl_layer_smi_id_en
9340 13:21:58.307969 ovl_layer_smi_id_en
9341 13:21:58.308049 ccorr_config
9342 13:21:58.308110 aal_config
9343 13:21:58.311747 gamma_config
9344 13:21:58.311824 postmask_config
9345 13:21:58.314446 dither_config
9346 13:21:58.317654 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9347 13:21:58.324526 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9348 13:21:58.328082 Root Device init finished in 555 msecs
9349 13:21:58.328158 CPU_CLUSTER: 0 init
9350 13:21:58.337699 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9351 13:21:58.340894 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9352 13:21:58.344496 APU_MBOX 0x190000b0 = 0x10001
9353 13:21:58.347540 APU_MBOX 0x190001b0 = 0x10001
9354 13:21:58.351381 APU_MBOX 0x190005b0 = 0x10001
9355 13:21:58.354292 APU_MBOX 0x190006b0 = 0x10001
9356 13:21:58.357565 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9357 13:21:58.370026 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9358 13:21:58.382849 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9359 13:21:58.389051 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9360 13:21:58.400562 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9361 13:21:58.410005 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9362 13:21:58.413194 CPU_CLUSTER: 0 init finished in 81 msecs
9363 13:21:58.416451 Devices initialized
9364 13:21:58.419922 Show all devs... After init.
9365 13:21:58.419998 Root Device: enabled 1
9366 13:21:58.423254 CPU_CLUSTER: 0: enabled 1
9367 13:21:58.426377 CPU: 00: enabled 1
9368 13:21:58.429740 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9369 13:21:58.433424 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9370 13:21:58.436641 ELOG: NV offset 0x57f000 size 0x1000
9371 13:21:58.443116 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9372 13:21:58.449854 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9373 13:21:58.453172 ELOG: Event(17) added with size 13 at 2023-09-06 13:21:54 UTC
9374 13:21:58.456601 out: cmd=0x121: 03 db 21 01 00 00 00 00
9375 13:21:58.460333 in-header: 03 0c 00 00 2c 00 00 00
9376 13:21:58.473483 in-data: 53 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9377 13:21:58.480190 ELOG: Event(A1) added with size 10 at 2023-09-06 13:21:54 UTC
9378 13:21:58.486950 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9379 13:21:58.493690 ELOG: Event(A0) added with size 9 at 2023-09-06 13:21:54 UTC
9380 13:21:58.496871 elog_add_boot_reason: Logged dev mode boot
9381 13:21:58.499980 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9382 13:21:58.503408 Finalize devices...
9383 13:21:58.503493 Devices finalized
9384 13:21:58.510051 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9385 13:21:58.513233 Writing coreboot table at 0xffe64000
9386 13:21:58.517081 0. 000000000010a000-0000000000113fff: RAMSTAGE
9387 13:21:58.519827 1. 0000000040000000-00000000400fffff: RAM
9388 13:21:58.523281 2. 0000000040100000-000000004032afff: RAMSTAGE
9389 13:21:58.529927 3. 000000004032b000-00000000545fffff: RAM
9390 13:21:58.533424 4. 0000000054600000-000000005465ffff: BL31
9391 13:21:58.536572 5. 0000000054660000-00000000ffe63fff: RAM
9392 13:21:58.540380 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9393 13:21:58.546770 7. 0000000100000000-000000023fffffff: RAM
9394 13:21:58.546855 Passing 5 GPIOs to payload:
9395 13:21:58.553184 NAME | PORT | POLARITY | VALUE
9396 13:21:58.556691 EC in RW | 0x000000aa | low | undefined
9397 13:21:58.563440 EC interrupt | 0x00000005 | low | undefined
9398 13:21:58.566771 TPM interrupt | 0x000000ab | high | undefined
9399 13:21:58.569785 SD card detect | 0x00000011 | high | undefined
9400 13:21:58.577261 speaker enable | 0x00000093 | high | undefined
9401 13:21:58.579996 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9402 13:21:58.583251 in-header: 03 f9 00 00 02 00 00 00
9403 13:21:58.583337 in-data: 02 00
9404 13:21:58.586560 ADC[4]: Raw value=901032 ID=7
9405 13:21:58.590102 ADC[3]: Raw value=213179 ID=1
9406 13:21:58.590187 RAM Code: 0x71
9407 13:21:58.593109 ADC[6]: Raw value=74502 ID=0
9408 13:21:58.596716 ADC[5]: Raw value=212072 ID=1
9409 13:21:58.596842 SKU Code: 0x1
9410 13:21:58.603199 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5bd8
9411 13:21:58.606606 coreboot table: 964 bytes.
9412 13:21:58.609781 IMD ROOT 0. 0xfffff000 0x00001000
9413 13:21:58.613312 IMD SMALL 1. 0xffffe000 0x00001000
9414 13:21:58.616564 RO MCACHE 2. 0xffffc000 0x00001104
9415 13:21:58.620089 CONSOLE 3. 0xfff7c000 0x00080000
9416 13:21:58.623125 FMAP 4. 0xfff7b000 0x00000452
9417 13:21:58.626651 TIME STAMP 5. 0xfff7a000 0x00000910
9418 13:21:58.629985 VBOOT WORK 6. 0xfff66000 0x00014000
9419 13:21:58.633264 RAMOOPS 7. 0xffe66000 0x00100000
9420 13:21:58.636418 COREBOOT 8. 0xffe64000 0x00002000
9421 13:21:58.636505 IMD small region:
9422 13:21:58.639848 IMD ROOT 0. 0xffffec00 0x00000400
9423 13:21:58.643345 VPD 1. 0xffffeb80 0x0000006c
9424 13:21:58.646311 MMC STATUS 2. 0xffffeb60 0x00000004
9425 13:21:58.653276 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9426 13:21:58.653363 Probing TPM: done!
9427 13:21:58.659811 Connected to device vid:did:rid of 1ae0:0028:00
9428 13:21:58.666457 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9429 13:21:58.669985 Initialized TPM device CR50 revision 0
9430 13:21:58.674037 Checking cr50 for pending updates
9431 13:21:58.679641 Reading cr50 TPM mode
9432 13:21:58.688090 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9433 13:21:58.694938 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9434 13:21:58.734830 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9435 13:21:58.738576 Checking segment from ROM address 0x40100000
9436 13:21:58.741628 Checking segment from ROM address 0x4010001c
9437 13:21:58.748330 Loading segment from ROM address 0x40100000
9438 13:21:58.748459 code (compression=0)
9439 13:21:58.755661 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9440 13:21:58.764792 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9441 13:21:58.764893 it's not compressed!
9442 13:21:58.771739 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9443 13:21:58.775457 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9444 13:21:58.795219 Loading segment from ROM address 0x4010001c
9445 13:21:58.795302 Entry Point 0x80000000
9446 13:21:58.798550 Loaded segments
9447 13:21:58.802626 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9448 13:21:58.808654 Jumping to boot code at 0x80000000(0xffe64000)
9449 13:21:58.815291 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9450 13:21:58.821977 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9451 13:21:58.830107 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9452 13:21:58.833128 Checking segment from ROM address 0x40100000
9453 13:21:58.836570 Checking segment from ROM address 0x4010001c
9454 13:21:58.843248 Loading segment from ROM address 0x40100000
9455 13:21:58.843332 code (compression=1)
9456 13:21:58.849787 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9457 13:21:58.859895 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9458 13:21:58.859980 using LZMA
9459 13:21:58.868275 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9460 13:21:58.875195 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9461 13:21:58.878231 Loading segment from ROM address 0x4010001c
9462 13:21:58.878316 Entry Point 0x54601000
9463 13:21:58.881515 Loaded segments
9464 13:21:58.884708 NOTICE: MT8192 bl31_setup
9465 13:21:58.891644 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9466 13:21:58.895098 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9467 13:21:58.898487 WARNING: region 0:
9468 13:21:58.901678 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9469 13:21:58.901762 WARNING: region 1:
9470 13:21:58.908428 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9471 13:21:58.911744 WARNING: region 2:
9472 13:21:58.915375 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9473 13:21:58.918802 WARNING: region 3:
9474 13:21:58.922101 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9475 13:21:58.925231 WARNING: region 4:
9476 13:21:58.928721 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9477 13:21:58.931994 WARNING: region 5:
9478 13:21:58.935440 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 13:21:58.938988 WARNING: region 6:
9480 13:21:58.942122 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 13:21:58.942199 WARNING: region 7:
9482 13:21:58.948883 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 13:21:58.955602 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9484 13:21:58.958875 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9485 13:21:58.961896 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9486 13:21:58.969030 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9487 13:21:58.972141 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9488 13:21:58.975354 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9489 13:21:58.982160 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9490 13:21:58.985361 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9491 13:21:58.989016 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9492 13:21:58.996145 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9493 13:21:58.998886 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9494 13:21:59.002543 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9495 13:21:59.008780 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9496 13:21:59.012656 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9497 13:21:59.019123 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9498 13:21:59.022457 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9499 13:21:59.025596 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9500 13:21:59.032587 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9501 13:21:59.036035 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9502 13:21:59.038898 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9503 13:21:59.046078 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9504 13:21:59.049135 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9505 13:21:59.055959 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9506 13:21:59.059240 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9507 13:21:59.062965 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9508 13:21:59.069190 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9509 13:21:59.072596 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9510 13:21:59.075873 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9511 13:21:59.082425 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9512 13:21:59.086255 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9513 13:21:59.092599 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9514 13:21:59.096211 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9515 13:21:59.099442 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9516 13:21:59.105692 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9517 13:21:59.108900 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9518 13:21:59.112701 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9519 13:21:59.115753 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9520 13:21:59.122272 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9521 13:21:59.125745 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9522 13:21:59.129220 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9523 13:21:59.132619 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9524 13:21:59.139033 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9525 13:21:59.142246 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9526 13:21:59.146294 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9527 13:21:59.149224 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9528 13:21:59.155702 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9529 13:21:59.158907 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9530 13:21:59.162498 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9531 13:21:59.169162 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9532 13:21:59.172265 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9533 13:21:59.175498 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9534 13:21:59.182580 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9535 13:21:59.185914 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9536 13:21:59.192783 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9537 13:21:59.195834 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9538 13:21:59.199167 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9539 13:21:59.205949 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9540 13:21:59.208893 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9541 13:21:59.215738 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9542 13:21:59.219129 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9543 13:21:59.225986 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9544 13:21:59.229280 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9545 13:21:59.235777 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9546 13:21:59.239154 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9547 13:21:59.242986 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9548 13:21:59.249459 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9549 13:21:59.252451 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9550 13:21:59.259300 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9551 13:21:59.262591 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9552 13:21:59.266303 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9553 13:21:59.272630 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9554 13:21:59.276025 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9555 13:21:59.282961 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9556 13:21:59.286089 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9557 13:21:59.292808 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9558 13:21:59.296072 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9559 13:21:59.299452 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9560 13:21:59.306416 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9561 13:21:59.309224 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9562 13:21:59.316154 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9563 13:21:59.319438 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9564 13:21:59.326098 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9565 13:21:59.329597 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9566 13:21:59.335879 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9567 13:21:59.339441 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9568 13:21:59.342782 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9569 13:21:59.349260 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9570 13:21:59.352653 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9571 13:21:59.359460 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9572 13:21:59.362896 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9573 13:21:59.366005 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9574 13:21:59.372950 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9575 13:21:59.376587 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9576 13:21:59.383260 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9577 13:21:59.386298 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9578 13:21:59.392917 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9579 13:21:59.396360 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9580 13:21:59.399789 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9581 13:21:59.403238 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9582 13:21:59.410025 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9583 13:21:59.413487 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9584 13:21:59.416674 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9585 13:21:59.423452 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9586 13:21:59.426836 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9587 13:21:59.430291 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9588 13:21:59.436617 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9589 13:21:59.440218 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9590 13:21:59.446650 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9591 13:21:59.450153 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9592 13:21:59.453367 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9593 13:21:59.459891 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9594 13:21:59.463315 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9595 13:21:59.470148 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9596 13:21:59.473436 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9597 13:21:59.476627 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9598 13:21:59.483822 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9599 13:21:59.486749 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9600 13:21:59.490692 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9601 13:21:59.496783 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9602 13:21:59.500266 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9603 13:21:59.503544 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9604 13:21:59.506949 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9605 13:21:59.510110 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9606 13:21:59.516733 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9607 13:21:59.520267 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9608 13:21:59.523512 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9609 13:21:59.530410 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9610 13:21:59.533613 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9611 13:21:59.540460 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9612 13:21:59.543798 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9613 13:21:59.547188 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9614 13:21:59.553691 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9615 13:21:59.557018 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9616 13:21:59.564325 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9617 13:21:59.567202 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9618 13:21:59.570849 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9619 13:21:59.577448 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9620 13:21:59.580975 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9621 13:21:59.584463 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9622 13:21:59.590873 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9623 13:21:59.593960 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9624 13:21:59.600813 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9625 13:21:59.604483 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9626 13:21:59.607438 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9627 13:21:59.614296 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9628 13:21:59.617530 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9629 13:21:59.620746 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9630 13:21:59.627577 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9631 13:21:59.631022 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9632 13:21:59.637653 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9633 13:21:59.640906 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9634 13:21:59.644177 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9635 13:21:59.650659 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9636 13:21:59.654238 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9637 13:21:59.657320 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9638 13:21:59.664522 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9639 13:21:59.667478 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9640 13:21:59.674542 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9641 13:21:59.677689 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9642 13:21:59.681154 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9643 13:21:59.687430 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9644 13:21:59.690752 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9645 13:21:59.697963 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9646 13:21:59.701064 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9647 13:21:59.704153 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9648 13:21:59.710806 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9649 13:21:59.714017 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9650 13:21:59.717279 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9651 13:21:59.723974 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9652 13:21:59.727236 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9653 13:21:59.734066 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9654 13:21:59.737360 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9655 13:21:59.740723 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9656 13:21:59.747291 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9657 13:21:59.750809 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9658 13:21:59.757621 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9659 13:21:59.760689 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9660 13:21:59.763825 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9661 13:21:59.770720 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9662 13:21:59.774069 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9663 13:21:59.780961 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9664 13:21:59.783642 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9665 13:21:59.787302 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9666 13:21:59.794188 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9667 13:21:59.797467 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9668 13:21:59.803652 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9669 13:21:59.806962 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9670 13:21:59.810314 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9671 13:21:59.817011 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9672 13:21:59.820449 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9673 13:21:59.827101 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9674 13:21:59.830346 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9675 13:21:59.834229 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9676 13:21:59.840285 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9677 13:21:59.843878 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9678 13:21:59.850400 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9679 13:21:59.853576 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9680 13:21:59.857043 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9681 13:21:59.863917 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9682 13:21:59.866819 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9683 13:21:59.873686 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9684 13:21:59.877129 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9685 13:21:59.880493 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9686 13:21:59.886745 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9687 13:21:59.890281 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9688 13:21:59.897064 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9689 13:21:59.900475 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9690 13:21:59.907123 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9691 13:21:59.910409 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9692 13:21:59.913520 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9693 13:21:59.920193 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9694 13:21:59.923608 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9695 13:21:59.930298 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9696 13:21:59.933849 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9697 13:21:59.937013 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9698 13:21:59.943636 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9699 13:21:59.946899 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9700 13:21:59.954017 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9701 13:21:59.956965 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9702 13:21:59.963868 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9703 13:21:59.967133 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9704 13:21:59.970734 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9705 13:21:59.977045 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9706 13:21:59.980197 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9707 13:21:59.986855 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9708 13:21:59.989919 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9709 13:21:59.993672 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9710 13:21:59.999943 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9711 13:22:00.003259 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9712 13:22:00.006669 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9713 13:22:00.013211 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9714 13:22:00.016880 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9715 13:22:00.020120 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9716 13:22:00.023274 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9717 13:22:00.029862 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9718 13:22:00.033239 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9719 13:22:00.040175 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9720 13:22:00.043105 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9721 13:22:00.046509 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9722 13:22:00.053433 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9723 13:22:00.056510 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9724 13:22:00.059853 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9725 13:22:00.066625 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9726 13:22:00.069775 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9727 13:22:00.073612 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9728 13:22:00.079786 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9729 13:22:00.083349 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9730 13:22:00.089740 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9731 13:22:00.093313 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9732 13:22:00.096528 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9733 13:22:00.103271 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9734 13:22:00.106626 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9735 13:22:00.109789 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9736 13:22:00.116732 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9737 13:22:00.119554 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9738 13:22:00.123215 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9739 13:22:00.129692 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9740 13:22:00.133005 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9741 13:22:00.136211 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9742 13:22:00.142948 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9743 13:22:00.146107 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9744 13:22:00.152738 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9745 13:22:00.155966 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9746 13:22:00.159242 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9747 13:22:00.166352 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9748 13:22:00.169508 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9749 13:22:00.172624 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9750 13:22:00.179250 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9751 13:22:00.182577 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9752 13:22:00.186280 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9753 13:22:00.192825 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9754 13:22:00.196101 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9755 13:22:00.199242 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9756 13:22:00.202577 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9757 13:22:00.205859 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9758 13:22:00.212735 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9759 13:22:00.216299 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9760 13:22:00.219491 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9761 13:22:00.222812 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9762 13:22:00.229723 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9763 13:22:00.233332 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9764 13:22:00.236055 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9765 13:22:00.243119 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9766 13:22:00.246311 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9767 13:22:00.249576 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9768 13:22:00.256480 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9769 13:22:00.259486 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9770 13:22:00.266190 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9771 13:22:00.269497 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9772 13:22:00.272902 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9773 13:22:00.279464 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9774 13:22:00.282578 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9775 13:22:00.289642 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9776 13:22:00.292457 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9777 13:22:00.299270 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9778 13:22:00.302434 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9779 13:22:00.306017 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9780 13:22:00.312574 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9781 13:22:00.316141 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9782 13:22:00.322432 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9783 13:22:00.325818 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9784 13:22:00.329055 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9785 13:22:00.335872 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9786 13:22:00.339177 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9787 13:22:00.345585 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9788 13:22:00.349126 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9789 13:22:00.352194 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9790 13:22:00.359051 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9791 13:22:00.362389 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9792 13:22:00.368742 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9793 13:22:00.372642 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9794 13:22:00.379240 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9795 13:22:00.382275 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9796 13:22:00.385595 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9797 13:22:00.392027 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9798 13:22:00.395661 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9799 13:22:00.402177 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9800 13:22:00.405516 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9801 13:22:00.408810 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9802 13:22:00.415732 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9803 13:22:00.419001 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9804 13:22:00.425427 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9805 13:22:00.428726 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9806 13:22:00.432135 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9807 13:22:00.438597 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9808 13:22:00.442248 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9809 13:22:00.448618 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9810 13:22:00.452081 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9811 13:22:00.459015 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9812 13:22:00.462045 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9813 13:22:00.465238 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9814 13:22:00.471991 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9815 13:22:00.475173 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9816 13:22:00.478780 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9817 13:22:00.485051 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9818 13:22:00.488372 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9819 13:22:00.495217 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9820 13:22:00.498278 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9821 13:22:00.501677 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9822 13:22:00.508437 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9823 13:22:00.511683 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9824 13:22:00.518331 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9825 13:22:00.521797 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9826 13:22:00.528563 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9827 13:22:00.531805 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9828 13:22:00.535398 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9829 13:22:00.541489 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9830 13:22:00.545099 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9831 13:22:00.551678 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9832 13:22:00.554769 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9833 13:22:00.558196 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9834 13:22:00.565136 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9835 13:22:00.568426 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9836 13:22:00.574949 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9837 13:22:00.578808 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9838 13:22:00.581598 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9839 13:22:00.588010 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9840 13:22:00.591492 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9841 13:22:00.598322 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9842 13:22:00.601809 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9843 13:22:00.608174 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9844 13:22:00.611591 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9845 13:22:00.614933 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9846 13:22:00.621435 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9847 13:22:00.624479 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9848 13:22:00.631952 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9849 13:22:00.634910 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9850 13:22:00.641249 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9851 13:22:00.644732 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9852 13:22:00.648022 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9853 13:22:00.654873 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9854 13:22:00.658361 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9855 13:22:00.664519 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9856 13:22:00.667835 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9857 13:22:00.674716 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9858 13:22:00.678075 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9859 13:22:00.684651 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9860 13:22:00.687642 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9861 13:22:00.690987 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9862 13:22:00.697673 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9863 13:22:00.701054 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9864 13:22:00.707893 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9865 13:22:00.711427 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9866 13:22:00.717585 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9867 13:22:00.721295 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9868 13:22:00.724446 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9869 13:22:00.730995 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9870 13:22:00.734515 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9871 13:22:00.741337 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9872 13:22:00.744484 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9873 13:22:00.750916 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9874 13:22:00.754199 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9875 13:22:00.761165 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9876 13:22:00.764253 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9877 13:22:00.767855 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9878 13:22:00.774345 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9879 13:22:00.777499 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9880 13:22:00.784155 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9881 13:22:00.787793 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9882 13:22:00.794447 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9883 13:22:00.797672 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9884 13:22:00.801084 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9885 13:22:00.807645 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9886 13:22:00.811122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9887 13:22:00.817458 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9888 13:22:00.820762 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9889 13:22:00.824175 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9890 13:22:00.831384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9891 13:22:00.834210 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9892 13:22:00.841104 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9893 13:22:00.844081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9894 13:22:00.851036 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9895 13:22:00.854499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9896 13:22:00.861297 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9897 13:22:00.864044 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9898 13:22:00.870801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9899 13:22:00.874088 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9900 13:22:00.880901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9901 13:22:00.884501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9902 13:22:00.890813 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9903 13:22:00.894108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9904 13:22:00.900722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9905 13:22:00.904173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9906 13:22:00.911322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9907 13:22:00.914513 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9908 13:22:00.920817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9909 13:22:00.924212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9910 13:22:00.931014 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9911 13:22:00.934066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9912 13:22:00.941021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9913 13:22:00.944196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9914 13:22:00.950607 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9915 13:22:00.954196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9916 13:22:00.960665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9917 13:22:00.963953 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9918 13:22:00.964051 INFO: [APUAPC] vio 0
9919 13:22:00.971506 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9920 13:22:00.974914 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9921 13:22:00.978499 INFO: [APUAPC] D0_APC_0: 0x400510
9922 13:22:00.981871 INFO: [APUAPC] D0_APC_1: 0x0
9923 13:22:00.984911 INFO: [APUAPC] D0_APC_2: 0x1540
9924 13:22:00.988227 INFO: [APUAPC] D0_APC_3: 0x0
9925 13:22:00.991535 INFO: [APUAPC] D1_APC_0: 0xffffffff
9926 13:22:00.994755 INFO: [APUAPC] D1_APC_1: 0xffffffff
9927 13:22:00.998130 INFO: [APUAPC] D1_APC_2: 0x3fffff
9928 13:22:01.001273 INFO: [APUAPC] D1_APC_3: 0x0
9929 13:22:01.004889 INFO: [APUAPC] D2_APC_0: 0xffffffff
9930 13:22:01.008229 INFO: [APUAPC] D2_APC_1: 0xffffffff
9931 13:22:01.011695 INFO: [APUAPC] D2_APC_2: 0x3fffff
9932 13:22:01.014671 INFO: [APUAPC] D2_APC_3: 0x0
9933 13:22:01.019000 INFO: [APUAPC] D3_APC_0: 0xffffffff
9934 13:22:01.021465 INFO: [APUAPC] D3_APC_1: 0xffffffff
9935 13:22:01.024600 INFO: [APUAPC] D3_APC_2: 0x3fffff
9936 13:22:01.024711 INFO: [APUAPC] D3_APC_3: 0x0
9937 13:22:01.031349 INFO: [APUAPC] D4_APC_0: 0xffffffff
9938 13:22:01.034707 INFO: [APUAPC] D4_APC_1: 0xffffffff
9939 13:22:01.038276 INFO: [APUAPC] D4_APC_2: 0x3fffff
9940 13:22:01.038379 INFO: [APUAPC] D4_APC_3: 0x0
9941 13:22:01.041291 INFO: [APUAPC] D5_APC_0: 0xffffffff
9942 13:22:01.044600 INFO: [APUAPC] D5_APC_1: 0xffffffff
9943 13:22:01.048391 INFO: [APUAPC] D5_APC_2: 0x3fffff
9944 13:22:01.051438 INFO: [APUAPC] D5_APC_3: 0x0
9945 13:22:01.054790 INFO: [APUAPC] D6_APC_0: 0xffffffff
9946 13:22:01.057993 INFO: [APUAPC] D6_APC_1: 0xffffffff
9947 13:22:01.061320 INFO: [APUAPC] D6_APC_2: 0x3fffff
9948 13:22:01.064642 INFO: [APUAPC] D6_APC_3: 0x0
9949 13:22:01.068132 INFO: [APUAPC] D7_APC_0: 0xffffffff
9950 13:22:01.071326 INFO: [APUAPC] D7_APC_1: 0xffffffff
9951 13:22:01.074899 INFO: [APUAPC] D7_APC_2: 0x3fffff
9952 13:22:01.077943 INFO: [APUAPC] D7_APC_3: 0x0
9953 13:22:01.081307 INFO: [APUAPC] D8_APC_0: 0xffffffff
9954 13:22:01.084622 INFO: [APUAPC] D8_APC_1: 0xffffffff
9955 13:22:01.087868 INFO: [APUAPC] D8_APC_2: 0x3fffff
9956 13:22:01.091019 INFO: [APUAPC] D8_APC_3: 0x0
9957 13:22:01.094718 INFO: [APUAPC] D9_APC_0: 0xffffffff
9958 13:22:01.098146 INFO: [APUAPC] D9_APC_1: 0xffffffff
9959 13:22:01.101239 INFO: [APUAPC] D9_APC_2: 0x3fffff
9960 13:22:01.104453 INFO: [APUAPC] D9_APC_3: 0x0
9961 13:22:01.107741 INFO: [APUAPC] D10_APC_0: 0xffffffff
9962 13:22:01.110960 INFO: [APUAPC] D10_APC_1: 0xffffffff
9963 13:22:01.114299 INFO: [APUAPC] D10_APC_2: 0x3fffff
9964 13:22:01.117903 INFO: [APUAPC] D10_APC_3: 0x0
9965 13:22:01.121038 INFO: [APUAPC] D11_APC_0: 0xffffffff
9966 13:22:01.124401 INFO: [APUAPC] D11_APC_1: 0xffffffff
9967 13:22:01.127666 INFO: [APUAPC] D11_APC_2: 0x3fffff
9968 13:22:01.131013 INFO: [APUAPC] D11_APC_3: 0x0
9969 13:22:01.134727 INFO: [APUAPC] D12_APC_0: 0xffffffff
9970 13:22:01.137598 INFO: [APUAPC] D12_APC_1: 0xffffffff
9971 13:22:01.141305 INFO: [APUAPC] D12_APC_2: 0x3fffff
9972 13:22:01.144532 INFO: [APUAPC] D12_APC_3: 0x0
9973 13:22:01.147940 INFO: [APUAPC] D13_APC_0: 0xffffffff
9974 13:22:01.151063 INFO: [APUAPC] D13_APC_1: 0xffffffff
9975 13:22:01.154850 INFO: [APUAPC] D13_APC_2: 0x3fffff
9976 13:22:01.157961 INFO: [APUAPC] D13_APC_3: 0x0
9977 13:22:01.161420 INFO: [APUAPC] D14_APC_0: 0xffffffff
9978 13:22:01.164342 INFO: [APUAPC] D14_APC_1: 0xffffffff
9979 13:22:01.167768 INFO: [APUAPC] D14_APC_2: 0x3fffff
9980 13:22:01.170780 INFO: [APUAPC] D14_APC_3: 0x0
9981 13:22:01.174492 INFO: [APUAPC] D15_APC_0: 0xffffffff
9982 13:22:01.178109 INFO: [APUAPC] D15_APC_1: 0xffffffff
9983 13:22:01.180892 INFO: [APUAPC] D15_APC_2: 0x3fffff
9984 13:22:01.184230 INFO: [APUAPC] D15_APC_3: 0x0
9985 13:22:01.187639 INFO: [APUAPC] APC_CON: 0x4
9986 13:22:01.191264 INFO: [NOCDAPC] D0_APC_0: 0x0
9987 13:22:01.194392 INFO: [NOCDAPC] D0_APC_1: 0x0
9988 13:22:01.197512 INFO: [NOCDAPC] D1_APC_0: 0x0
9989 13:22:01.197595 INFO: [NOCDAPC] D1_APC_1: 0xfff
9990 13:22:01.200965 INFO: [NOCDAPC] D2_APC_0: 0x0
9991 13:22:01.204147 INFO: [NOCDAPC] D2_APC_1: 0xfff
9992 13:22:01.207557 INFO: [NOCDAPC] D3_APC_0: 0x0
9993 13:22:01.210988 INFO: [NOCDAPC] D3_APC_1: 0xfff
9994 13:22:01.214467 INFO: [NOCDAPC] D4_APC_0: 0x0
9995 13:22:01.218322 INFO: [NOCDAPC] D4_APC_1: 0xfff
9996 13:22:01.220915 INFO: [NOCDAPC] D5_APC_0: 0x0
9997 13:22:01.224445 INFO: [NOCDAPC] D5_APC_1: 0xfff
9998 13:22:01.227475 INFO: [NOCDAPC] D6_APC_0: 0x0
9999 13:22:01.230904 INFO: [NOCDAPC] D6_APC_1: 0xfff
10000 13:22:01.230988 INFO: [NOCDAPC] D7_APC_0: 0x0
10001 13:22:01.234516 INFO: [NOCDAPC] D7_APC_1: 0xfff
10002 13:22:01.237454 INFO: [NOCDAPC] D8_APC_0: 0x0
10003 13:22:01.240782 INFO: [NOCDAPC] D8_APC_1: 0xfff
10004 13:22:01.244359 INFO: [NOCDAPC] D9_APC_0: 0x0
10005 13:22:01.247693 INFO: [NOCDAPC] D9_APC_1: 0xfff
10006 13:22:01.250695 INFO: [NOCDAPC] D10_APC_0: 0x0
10007 13:22:01.254425 INFO: [NOCDAPC] D10_APC_1: 0xfff
10008 13:22:01.257448 INFO: [NOCDAPC] D11_APC_0: 0x0
10009 13:22:01.260742 INFO: [NOCDAPC] D11_APC_1: 0xfff
10010 13:22:01.264089 INFO: [NOCDAPC] D12_APC_0: 0x0
10011 13:22:01.267443 INFO: [NOCDAPC] D12_APC_1: 0xfff
10012 13:22:01.267564 INFO: [NOCDAPC] D13_APC_0: 0x0
10013 13:22:01.270744 INFO: [NOCDAPC] D13_APC_1: 0xfff
10014 13:22:01.274204 INFO: [NOCDAPC] D14_APC_0: 0x0
10015 13:22:01.277585 INFO: [NOCDAPC] D14_APC_1: 0xfff
10016 13:22:01.281104 INFO: [NOCDAPC] D15_APC_0: 0x0
10017 13:22:01.284463 INFO: [NOCDAPC] D15_APC_1: 0xfff
10018 13:22:01.287416 INFO: [NOCDAPC] APC_CON: 0x4
10019 13:22:01.290748 INFO: [APUAPC] set_apusys_apc done
10020 13:22:01.294032 INFO: [DEVAPC] devapc_init done
10021 13:22:01.297520 INFO: GICv3 without legacy support detected.
10022 13:22:01.300583 INFO: ARM GICv3 driver initialized in EL3
10023 13:22:01.307595 INFO: Maximum SPI INTID supported: 639
10024 13:22:01.310842 INFO: BL31: Initializing runtime services
10025 13:22:01.314147 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10026 13:22:01.317421 INFO: SPM: enable CPC mode
10027 13:22:01.324041 INFO: mcdi ready for mcusys-off-idle and system suspend
10028 13:22:01.327462 INFO: BL31: Preparing for EL3 exit to normal world
10029 13:22:01.330784 INFO: Entry point address = 0x80000000
10030 13:22:01.333926 INFO: SPSR = 0x8
10031 13:22:01.339801
10032 13:22:01.339887
10033 13:22:01.339955
10034 13:22:01.342964 Starting depthcharge on Spherion...
10035 13:22:01.343089
10036 13:22:01.343185 Wipe memory regions:
10037 13:22:01.343308
10038 13:22:01.344168 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10039 13:22:01.344300 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10040 13:22:01.344417 Setting prompt string to ['asurada:']
10041 13:22:01.344530 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10042 13:22:01.346121 [0x00000040000000, 0x00000054600000)
10043 13:22:01.468249
10044 13:22:01.468382 [0x00000054660000, 0x00000080000000)
10045 13:22:01.728780
10046 13:22:01.728935 [0x000000821a7280, 0x000000ffe64000)
10047 13:22:02.472376
10048 13:22:02.472522 [0x00000100000000, 0x00000240000000)
10049 13:22:04.359562
10050 13:22:04.362240 Initializing XHCI USB controller at 0x11200000.
10051 13:22:05.399967
10052 13:22:05.403516 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10053 13:22:05.403651
10054 13:22:05.403816
10055 13:22:05.403939
10056 13:22:05.404280 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10058 13:22:05.504692 asurada: tftpboot 192.168.201.1 11445609/tftp-deploy-4jxawmcg/kernel/image.itb 11445609/tftp-deploy-4jxawmcg/kernel/cmdline
10059 13:22:05.504936 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10060 13:22:05.505128 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10061 13:22:05.509387 tftpboot 192.168.201.1 11445609/tftp-deploy-4jxawmcg/kernel/image.ittp-deploy-4jxawmcg/kernel/cmdline
10062 13:22:05.509516
10063 13:22:05.509629 Waiting for link
10064 13:22:05.669672
10065 13:22:05.669793 R8152: Initializing
10066 13:22:05.669864
10067 13:22:05.673385 Version 9 (ocp_data = 6010)
10068 13:22:05.673470
10069 13:22:05.676660 R8152: Done initializing
10070 13:22:05.676792
10071 13:22:05.676883 Adding net device
10072 13:22:07.621704
10073 13:22:07.621915 done.
10074 13:22:07.622038
10075 13:22:07.622151 MAC: 00:e0:4c:72:2d:d6
10076 13:22:07.622266
10077 13:22:07.625221 Sending DHCP discover... done.
10078 13:22:07.625333
10079 13:22:07.628219 Waiting for reply... done.
10080 13:22:07.628353
10081 13:22:07.631355 Sending DHCP request... done.
10082 13:22:07.631455
10083 13:22:07.631548 Waiting for reply... done.
10084 13:22:07.631638
10085 13:22:07.634731 My ip is 192.168.201.21
10086 13:22:07.634845
10087 13:22:07.637986 The DHCP server ip is 192.168.201.1
10088 13:22:07.638083
10089 13:22:07.641723 TFTP server IP predefined by user: 192.168.201.1
10090 13:22:07.641797
10091 13:22:07.648216 Bootfile predefined by user: 11445609/tftp-deploy-4jxawmcg/kernel/image.itb
10092 13:22:07.648299
10093 13:22:07.651822 Sending tftp read request... done.
10094 13:22:07.651903
10095 13:22:07.654528 Waiting for the transfer...
10096 13:22:07.654631
10097 13:22:07.904299 00000000 ################################################################
10098 13:22:07.904518
10099 13:22:08.150941 00080000 ################################################################
10100 13:22:08.151144
10101 13:22:08.403152 00100000 ################################################################
10102 13:22:08.403299
10103 13:22:08.657334 00180000 ################################################################
10104 13:22:08.657483
10105 13:22:08.903891 00200000 ################################################################
10106 13:22:08.904036
10107 13:22:09.150419 00280000 ################################################################
10108 13:22:09.150568
10109 13:22:09.398170 00300000 ################################################################
10110 13:22:09.398330
10111 13:22:09.649684 00380000 ################################################################
10112 13:22:09.649837
10113 13:22:09.900326 00400000 ################################################################
10114 13:22:09.900474
10115 13:22:10.154985 00480000 ################################################################
10116 13:22:10.155162
10117 13:22:10.415270 00500000 ################################################################
10118 13:22:10.415471
10119 13:22:10.668310 00580000 ################################################################
10120 13:22:10.668469
10121 13:22:10.917904 00600000 ################################################################
10122 13:22:10.918081
10123 13:22:11.177044 00680000 ################################################################
10124 13:22:11.177266
10125 13:22:11.436616 00700000 ################################################################
10126 13:22:11.436831
10127 13:22:11.683929 00780000 ################################################################
10128 13:22:11.684074
10129 13:22:11.940973 00800000 ################################################################
10130 13:22:11.941122
10131 13:22:12.190043 00880000 ################################################################
10132 13:22:12.190203
10133 13:22:12.443976 00900000 ################################################################
10134 13:22:12.444113
10135 13:22:12.698071 00980000 ################################################################
10136 13:22:12.698215
10137 13:22:12.952711 00a00000 ################################################################
10138 13:22:12.952935
10139 13:22:13.208205 00a80000 ################################################################
10140 13:22:13.208351
10141 13:22:13.466208 00b00000 ################################################################
10142 13:22:13.466388
10143 13:22:13.721949 00b80000 ################################################################
10144 13:22:13.722110
10145 13:22:13.998573 00c00000 ################################################################
10146 13:22:13.998776
10147 13:22:14.285887 00c80000 ################################################################
10148 13:22:14.286099
10149 13:22:14.546868 00d00000 ################################################################
10150 13:22:14.547068
10151 13:22:14.800506 00d80000 ################################################################
10152 13:22:14.800677
10153 13:22:15.050737 00e00000 ################################################################
10154 13:22:15.050877
10155 13:22:15.304012 00e80000 ################################################################
10156 13:22:15.304173
10157 13:22:15.554690 00f00000 ################################################################
10158 13:22:15.554846
10159 13:22:15.805998 00f80000 ################################################################
10160 13:22:15.806184
10161 13:22:16.059875 01000000 ################################################################
10162 13:22:16.060037
10163 13:22:16.319672 01080000 ################################################################
10164 13:22:16.319877
10165 13:22:16.569536 01100000 ################################################################
10166 13:22:16.569723
10167 13:22:16.819476 01180000 ################################################################
10168 13:22:16.819661
10169 13:22:17.079342 01200000 ################################################################
10170 13:22:17.079502
10171 13:22:17.369475 01280000 ################################################################
10172 13:22:17.369632
10173 13:22:17.650403 01300000 ################################################################
10174 13:22:17.650562
10175 13:22:17.915122 01380000 ################################################################
10176 13:22:17.915318
10177 13:22:18.167702 01400000 ################################################################
10178 13:22:18.167850
10179 13:22:18.422605 01480000 ################################################################
10180 13:22:18.422752
10181 13:22:18.676314 01500000 ################################################################
10182 13:22:18.676447
10183 13:22:18.934249 01580000 ################################################################
10184 13:22:18.934409
10185 13:22:19.192372 01600000 ################################################################
10186 13:22:19.192563
10187 13:22:19.469660 01680000 ################################################################
10188 13:22:19.469830
10189 13:22:19.749997 01700000 ################################################################
10190 13:22:19.750141
10191 13:22:20.011460 01780000 ################################################################
10192 13:22:20.011604
10193 13:22:20.292216 01800000 ################################################################
10194 13:22:20.292352
10195 13:22:20.574400 01880000 ################################################################
10196 13:22:20.574588
10197 13:22:20.836266 01900000 ################################################################
10198 13:22:20.836432
10199 13:22:21.125302 01980000 ################################################################
10200 13:22:21.125468
10201 13:22:21.417307 01a00000 ################################################################
10202 13:22:21.417511
10203 13:22:21.708103 01a80000 ################################################################
10204 13:22:21.708250
10205 13:22:21.991527 01b00000 ################################################################
10206 13:22:21.991670
10207 13:22:22.274828 01b80000 ################################################################
10208 13:22:22.275028
10209 13:22:22.536687 01c00000 ################################################################
10210 13:22:22.536850
10211 13:22:22.806156 01c80000 ################################################################
10212 13:22:22.806297
10213 13:22:23.095395 01d00000 ################################################################
10214 13:22:23.095534
10215 13:22:23.396511 01d80000 ################################################################
10216 13:22:23.396655
10217 13:22:23.698319 01e00000 ################################################################
10218 13:22:23.698513
10219 13:22:23.995124 01e80000 ################################################################
10220 13:22:23.995324
10221 13:22:24.291436 01f00000 ################################################################
10222 13:22:24.291578
10223 13:22:24.563944 01f80000 ################################################################
10224 13:22:24.564088
10225 13:22:24.859166 02000000 ################################################################
10226 13:22:24.859363
10227 13:22:25.161424 02080000 ################################################################
10228 13:22:25.161600
10229 13:22:25.451589 02100000 ################################################################
10230 13:22:25.451740
10231 13:22:25.744724 02180000 ################################################################
10232 13:22:25.744894
10233 13:22:26.013763 02200000 ################################################################
10234 13:22:26.013902
10235 13:22:26.302264 02280000 ################################################################
10236 13:22:26.302406
10237 13:22:26.570521 02300000 ################################################################
10238 13:22:26.570673
10239 13:22:26.869125 02380000 ################################################################
10240 13:22:26.869269
10241 13:22:27.168324 02400000 ################################################################
10242 13:22:27.168463
10243 13:22:27.464351 02480000 ################################################################
10244 13:22:27.464496
10245 13:22:27.751856 02500000 ################################################################
10246 13:22:27.752003
10247 13:22:28.031998 02580000 ################################################################
10248 13:22:28.032141
10249 13:22:28.307075 02600000 ################################################################
10250 13:22:28.307282
10251 13:22:28.591098 02680000 ################################################################
10252 13:22:28.591239
10253 13:22:28.864618 02700000 ################################################################
10254 13:22:28.864770
10255 13:22:29.137920 02780000 ################################################################
10256 13:22:29.138061
10257 13:22:29.433897 02800000 ################################################################
10258 13:22:29.434036
10259 13:22:29.722470 02880000 ################################################################
10260 13:22:29.722625
10261 13:22:30.006415 02900000 ################################################################
10262 13:22:30.006557
10263 13:22:30.275648 02980000 ################################################################
10264 13:22:30.275793
10265 13:22:30.534943 02a00000 ################################################################
10266 13:22:30.535134
10267 13:22:30.813699 02a80000 ################################################################
10268 13:22:30.813912
10269 13:22:31.107442 02b00000 ################################################################
10270 13:22:31.107581
10271 13:22:31.386312 02b80000 ################################################################
10272 13:22:31.386473
10273 13:22:31.650471 02c00000 ################################################################
10274 13:22:31.650609
10275 13:22:31.918328 02c80000 ################################################################
10276 13:22:31.918469
10277 13:22:32.177446 02d00000 ################################################################
10278 13:22:32.177590
10279 13:22:32.461506 02d80000 ################################################################
10280 13:22:32.461651
10281 13:22:32.733642 02e00000 ################################################################
10282 13:22:32.733791
10283 13:22:33.015168 02e80000 ################################################################
10284 13:22:33.015335
10285 13:22:33.292704 02f00000 ################################################################
10286 13:22:33.292855
10287 13:22:33.583287 02f80000 ################################################################
10288 13:22:33.583482
10289 13:22:33.863042 03000000 ################################################################
10290 13:22:33.863215
10291 13:22:34.155222 03080000 ################################################################
10292 13:22:34.155362
10293 13:22:34.447389 03100000 ################################################################
10294 13:22:34.447557
10295 13:22:34.743907 03180000 ################################################################
10296 13:22:34.744043
10297 13:22:35.030604 03200000 ################################################################
10298 13:22:35.030817
10299 13:22:35.317428 03280000 ################################################################
10300 13:22:35.317715
10301 13:22:35.576202 03300000 ################################################################
10302 13:22:35.576390
10303 13:22:35.832518 03380000 ################################################################
10304 13:22:35.832683
10305 13:22:36.090298 03400000 ################################################################
10306 13:22:36.090434
10307 13:22:36.345872 03480000 ################################################################
10308 13:22:36.346005
10309 13:22:36.607341 03500000 ################################################################
10310 13:22:36.607482
10311 13:22:36.885735 03580000 ################################################################
10312 13:22:36.885877
10313 13:22:37.141019 03600000 ################################################################
10314 13:22:37.141154
10315 13:22:37.393646 03680000 ################################################################
10316 13:22:37.393828
10317 13:22:37.653564 03700000 ################################################################
10318 13:22:37.653727
10319 13:22:37.851447 03780000 ################################################## done.
10320 13:22:37.851629
10321 13:22:37.855086 The bootfile was 58603950 bytes long.
10322 13:22:37.855216
10323 13:22:37.858639 Sending tftp read request... done.
10324 13:22:37.858766
10325 13:22:37.858883 Waiting for the transfer...
10326 13:22:37.858997
10327 13:22:37.861604 00000000 # done.
10328 13:22:37.861731
10329 13:22:37.868320 Command line loaded dynamically from TFTP file: 11445609/tftp-deploy-4jxawmcg/kernel/cmdline
10330 13:22:37.868412
10331 13:22:37.881949 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10332 13:22:37.882038
10333 13:22:37.885143 Loading FIT.
10334 13:22:37.885229
10335 13:22:37.888349 Image ramdisk-1 has 47516413 bytes.
10336 13:22:37.888434
10337 13:22:37.888501 Image fdt-1 has 47278 bytes.
10338 13:22:37.888565
10339 13:22:37.891813 Image kernel-1 has 11038222 bytes.
10340 13:22:37.891899
10341 13:22:37.901437 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10342 13:22:37.901524
10343 13:22:37.918214 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10344 13:22:37.918305
10345 13:22:37.925165 Choosing best match conf-1 for compat google,spherion-rev2.
10346 13:22:37.929097
10347 13:22:37.933616 Connected to device vid:did:rid of 1ae0:0028:00
10348 13:22:37.941640
10349 13:22:37.945551 tpm_get_response: command 0x17b, return code 0x0
10350 13:22:37.945635
10351 13:22:37.948298 ec_init: CrosEC protocol v3 supported (256, 248)
10352 13:22:37.953673
10353 13:22:37.957109 tpm_cleanup: add release locality here.
10354 13:22:37.957210
10355 13:22:37.957280 Shutting down all USB controllers.
10356 13:22:37.960245
10357 13:22:37.960328 Removing current net device
10358 13:22:37.960416
10359 13:22:37.967115 Exiting depthcharge with code 4 at timestamp: 65967402
10360 13:22:37.967223
10361 13:22:37.970476 LZMA decompressing kernel-1 to 0x821a6718
10362 13:22:37.970552
10363 13:22:37.973492 LZMA decompressing kernel-1 to 0x40000000
10364 13:22:39.361638
10365 13:22:39.361779 jumping to kernel
10366 13:22:39.362212 end: 2.2.4 bootloader-commands (duration 00:00:38) [common]
10367 13:22:39.362311 start: 2.2.5 auto-login-action (timeout 00:03:47) [common]
10368 13:22:39.362390 Setting prompt string to ['Linux version [0-9]']
10369 13:22:39.362459 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10370 13:22:39.362527 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10371 13:22:39.443402
10372 13:22:39.446663 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10373 13:22:39.450393 start: 2.2.5.1 login-action (timeout 00:03:47) [common]
10374 13:22:39.450487 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10375 13:22:39.450560 Setting prompt string to []
10376 13:22:39.450639 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10377 13:22:39.450714 Using line separator: #'\n'#
10378 13:22:39.450775 No login prompt set.
10379 13:22:39.450837 Parsing kernel messages
10380 13:22:39.450894 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10381 13:22:39.450993 [login-action] Waiting for messages, (timeout 00:03:47)
10382 13:22:39.469965 [ 0.000000] Linux version 6.1.46-cip4 (KernelCI@build-j36642-arm64-gcc-10-defconfig-arm64-chromebook-rxg94) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Sep 6 13:11:19 UTC 2023
10383 13:22:39.473695 [ 0.000000] random: crng init done
10384 13:22:39.476727 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10385 13:22:39.480143 [ 0.000000] efi: UEFI not found.
10386 13:22:39.490239 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10387 13:22:39.496696 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10388 13:22:39.506582 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10389 13:22:39.516955 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10390 13:22:39.523113 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10391 13:22:39.526565 [ 0.000000] printk: bootconsole [mtk8250] enabled
10392 13:22:39.535147 [ 0.000000] NUMA: No NUMA configuration found
10393 13:22:39.541567 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10394 13:22:39.548230 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10395 13:22:39.548337 [ 0.000000] Zone ranges:
10396 13:22:39.555060 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10397 13:22:39.558184 [ 0.000000] DMA32 empty
10398 13:22:39.565028 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10399 13:22:39.567973 [ 0.000000] Movable zone start for each node
10400 13:22:39.571908 [ 0.000000] Early memory node ranges
10401 13:22:39.577988 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10402 13:22:39.584735 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10403 13:22:39.591354 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10404 13:22:39.598067 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10405 13:22:39.604656 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10406 13:22:39.611346 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10407 13:22:39.667857 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10408 13:22:39.674106 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10409 13:22:39.680970 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10410 13:22:39.684346 [ 0.000000] psci: probing for conduit method from DT.
10411 13:22:39.690841 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10412 13:22:39.694078 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10413 13:22:39.701009 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10414 13:22:39.704081 [ 0.000000] psci: SMC Calling Convention v1.2
10415 13:22:39.710928 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10416 13:22:39.714026 [ 0.000000] Detected VIPT I-cache on CPU0
10417 13:22:39.720658 [ 0.000000] CPU features: detected: GIC system register CPU interface
10418 13:22:39.727573 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10419 13:22:39.733947 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10420 13:22:39.740568 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10421 13:22:39.747279 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10422 13:22:39.756937 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10423 13:22:39.760860 [ 0.000000] alternatives: applying boot alternatives
10424 13:22:39.766769 [ 0.000000] Fallback order for Node 0: 0
10425 13:22:39.773782 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10426 13:22:39.777078 [ 0.000000] Policy zone: Normal
10427 13:22:39.790308 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10428 13:22:39.800233 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10429 13:22:39.812229 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10430 13:22:39.822012 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10431 13:22:39.828331 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10432 13:22:39.831579 <6>[ 0.000000] software IO TLB: area num 8.
10433 13:22:39.888328 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10434 13:22:40.037543 <6>[ 0.000000] Memory: 7923152K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 429616K reserved, 32768K cma-reserved)
10435 13:22:40.044046 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10436 13:22:40.050745 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10437 13:22:40.054161 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10438 13:22:40.060605 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10439 13:22:40.067271 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10440 13:22:40.070536 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10441 13:22:40.080308 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10442 13:22:40.087384 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10443 13:22:40.094114 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10444 13:22:40.100544 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10445 13:22:40.103852 <6>[ 0.000000] GICv3: 608 SPIs implemented
10446 13:22:40.107068 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10447 13:22:40.113986 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10448 13:22:40.116979 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10449 13:22:40.123860 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10450 13:22:40.137466 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10451 13:22:40.146888 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10452 13:22:40.157037 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10453 13:22:40.164143 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10454 13:22:40.177210 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10455 13:22:40.184170 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10456 13:22:40.190346 <6>[ 0.009182] Console: colour dummy device 80x25
10457 13:22:40.200254 <6>[ 0.013940] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10458 13:22:40.207136 <6>[ 0.024382] pid_max: default: 32768 minimum: 301
10459 13:22:40.210189 <6>[ 0.029253] LSM: Security Framework initializing
10460 13:22:40.217027 <6>[ 0.034193] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10461 13:22:40.227696 <6>[ 0.042006] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10462 13:22:40.233660 <6>[ 0.051426] cblist_init_generic: Setting adjustable number of callback queues.
10463 13:22:40.240190 <6>[ 0.058872] cblist_init_generic: Setting shift to 3 and lim to 1.
10464 13:22:40.250047 <6>[ 0.065251] cblist_init_generic: Setting adjustable number of callback queues.
10465 13:22:40.256991 <6>[ 0.072676] cblist_init_generic: Setting shift to 3 and lim to 1.
10466 13:22:40.260032 <6>[ 0.079115] rcu: Hierarchical SRCU implementation.
10467 13:22:40.266539 <6>[ 0.084127] rcu: Max phase no-delay instances is 1000.
10468 13:22:40.273363 <6>[ 0.091160] EFI services will not be available.
10469 13:22:40.276384 <6>[ 0.096131] smp: Bringing up secondary CPUs ...
10470 13:22:40.284786 <6>[ 0.101187] Detected VIPT I-cache on CPU1
10471 13:22:40.291257 <6>[ 0.101255] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10472 13:22:40.298180 <6>[ 0.101289] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10473 13:22:40.301429 <6>[ 0.101610] Detected VIPT I-cache on CPU2
10474 13:22:40.307837 <6>[ 0.101653] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10475 13:22:40.317728 <6>[ 0.101668] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10476 13:22:40.321344 <6>[ 0.101916] Detected VIPT I-cache on CPU3
10477 13:22:40.327931 <6>[ 0.101962] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10478 13:22:40.334604 <6>[ 0.101977] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10479 13:22:40.337937 <6>[ 0.102286] CPU features: detected: Spectre-v4
10480 13:22:40.344403 <6>[ 0.102292] CPU features: detected: Spectre-BHB
10481 13:22:40.347606 <6>[ 0.102297] Detected PIPT I-cache on CPU4
10482 13:22:40.354395 <6>[ 0.102352] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10483 13:22:40.360766 <6>[ 0.102370] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10484 13:22:40.367560 <6>[ 0.102661] Detected PIPT I-cache on CPU5
10485 13:22:40.373990 <6>[ 0.102723] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10486 13:22:40.381053 <6>[ 0.102739] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10487 13:22:40.384157 <6>[ 0.103024] Detected PIPT I-cache on CPU6
10488 13:22:40.391045 <6>[ 0.103087] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10489 13:22:40.397177 <6>[ 0.103104] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10490 13:22:40.403955 <6>[ 0.103400] Detected PIPT I-cache on CPU7
10491 13:22:40.410347 <6>[ 0.103463] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10492 13:22:40.417045 <6>[ 0.103480] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10493 13:22:40.420401 <6>[ 0.103526] smp: Brought up 1 node, 8 CPUs
10494 13:22:40.426861 <6>[ 0.244878] SMP: Total of 8 processors activated.
10495 13:22:40.430338 <6>[ 0.249799] CPU features: detected: 32-bit EL0 Support
10496 13:22:40.440227 <6>[ 0.255162] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10497 13:22:40.446753 <6>[ 0.263962] CPU features: detected: Common not Private translations
10498 13:22:40.453724 <6>[ 0.270438] CPU features: detected: CRC32 instructions
10499 13:22:40.456592 <6>[ 0.275789] CPU features: detected: RCpc load-acquire (LDAPR)
10500 13:22:40.463382 <6>[ 0.281749] CPU features: detected: LSE atomic instructions
10501 13:22:40.469838 <6>[ 0.287531] CPU features: detected: Privileged Access Never
10502 13:22:40.476352 <6>[ 0.293311] CPU features: detected: RAS Extension Support
10503 13:22:40.483129 <6>[ 0.298919] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10504 13:22:40.486563 <6>[ 0.306185] CPU: All CPU(s) started at EL2
10505 13:22:40.492879 <6>[ 0.310528] alternatives: applying system-wide alternatives
10506 13:22:40.502520 <6>[ 0.321238] devtmpfs: initialized
10507 13:22:40.514992 <6>[ 0.330124] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10508 13:22:40.524654 <6>[ 0.340086] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10509 13:22:40.531034 <6>[ 0.348100] pinctrl core: initialized pinctrl subsystem
10510 13:22:40.534312 <6>[ 0.354748] DMI not present or invalid.
10511 13:22:40.540958 <6>[ 0.359151] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10512 13:22:40.550938 <6>[ 0.365996] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10513 13:22:40.557729 <6>[ 0.373575] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10514 13:22:40.567728 <6>[ 0.381791] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10515 13:22:40.570971 <6>[ 0.390030] audit: initializing netlink subsys (disabled)
10516 13:22:40.580679 <5>[ 0.395724] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10517 13:22:40.587153 <6>[ 0.396429] thermal_sys: Registered thermal governor 'step_wise'
10518 13:22:40.594166 <6>[ 0.403694] thermal_sys: Registered thermal governor 'power_allocator'
10519 13:22:40.597612 <6>[ 0.409947] cpuidle: using governor menu
10520 13:22:40.603707 <6>[ 0.420907] NET: Registered PF_QIPCRTR protocol family
10521 13:22:40.610822 <6>[ 0.426388] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10522 13:22:40.613768 <6>[ 0.433490] ASID allocator initialised with 32768 entries
10523 13:22:40.621414 <6>[ 0.440051] Serial: AMBA PL011 UART driver
10524 13:22:40.630199 <4>[ 0.448787] Trying to register duplicate clock ID: 134
10525 13:22:40.684034 <6>[ 0.506151] KASLR enabled
10526 13:22:40.698348 <6>[ 0.513813] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10527 13:22:40.704965 <6>[ 0.520827] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10528 13:22:40.711350 <6>[ 0.527316] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10529 13:22:40.718077 <6>[ 0.534320] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10530 13:22:40.724719 <6>[ 0.540808] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10531 13:22:40.731138 <6>[ 0.547813] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10532 13:22:40.737983 <6>[ 0.554300] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10533 13:22:40.744762 <6>[ 0.561303] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10534 13:22:40.747881 <6>[ 0.568747] ACPI: Interpreter disabled.
10535 13:22:40.756268 <6>[ 0.575192] iommu: Default domain type: Translated
10536 13:22:40.762848 <6>[ 0.580305] iommu: DMA domain TLB invalidation policy: strict mode
10537 13:22:40.766496 <5>[ 0.586965] SCSI subsystem initialized
10538 13:22:40.773116 <6>[ 0.591211] usbcore: registered new interface driver usbfs
10539 13:22:40.779558 <6>[ 0.596942] usbcore: registered new interface driver hub
10540 13:22:40.783094 <6>[ 0.602495] usbcore: registered new device driver usb
10541 13:22:40.789757 <6>[ 0.608609] pps_core: LinuxPPS API ver. 1 registered
10542 13:22:40.799941 <6>[ 0.613803] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10543 13:22:40.803153 <6>[ 0.623147] PTP clock support registered
10544 13:22:40.806486 <6>[ 0.627389] EDAC MC: Ver: 3.0.0
10545 13:22:40.813939 <6>[ 0.632577] FPGA manager framework
10546 13:22:40.817091 <6>[ 0.636254] Advanced Linux Sound Architecture Driver Initialized.
10547 13:22:40.820798 <6>[ 0.643017] vgaarb: loaded
10548 13:22:40.827928 <6>[ 0.646191] clocksource: Switched to clocksource arch_sys_counter
10549 13:22:40.834611 <5>[ 0.652637] VFS: Disk quotas dquot_6.6.0
10550 13:22:40.840759 <6>[ 0.656824] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10551 13:22:40.844208 <6>[ 0.664016] pnp: PnP ACPI: disabled
10552 13:22:40.852057 <6>[ 0.670682] NET: Registered PF_INET protocol family
10553 13:22:40.862197 <6>[ 0.676272] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10554 13:22:40.873188 <6>[ 0.688518] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10555 13:22:40.882999 <6>[ 0.697334] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10556 13:22:40.889483 <6>[ 0.705303] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10557 13:22:40.896312 <6>[ 0.714000] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10558 13:22:40.908091 <6>[ 0.723720] TCP: Hash tables configured (established 65536 bind 65536)
10559 13:22:40.914695 <6>[ 0.730585] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10560 13:22:40.921205 <6>[ 0.737784] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10561 13:22:40.927892 <6>[ 0.745483] NET: Registered PF_UNIX/PF_LOCAL protocol family
10562 13:22:40.934509 <6>[ 0.751651] RPC: Registered named UNIX socket transport module.
10563 13:22:40.938162 <6>[ 0.757804] RPC: Registered udp transport module.
10564 13:22:40.944375 <6>[ 0.762736] RPC: Registered tcp transport module.
10565 13:22:40.950969 <6>[ 0.767667] RPC: Registered tcp NFSv4.1 backchannel transport module.
10566 13:22:40.954485 <6>[ 0.774337] PCI: CLS 0 bytes, default 64
10567 13:22:40.957942 <6>[ 0.778737] Unpacking initramfs...
10568 13:22:40.982634 <6>[ 0.798312] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10569 13:22:40.992780 <6>[ 0.806971] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10570 13:22:40.996127 <6>[ 0.815826] kvm [1]: IPA Size Limit: 40 bits
10571 13:22:41.003185 <6>[ 0.820355] kvm [1]: GICv3: no GICV resource entry
10572 13:22:41.005824 <6>[ 0.825378] kvm [1]: disabling GICv2 emulation
10573 13:22:41.012729 <6>[ 0.830063] kvm [1]: GIC system register CPU interface enabled
10574 13:22:41.016447 <6>[ 0.836251] kvm [1]: vgic interrupt IRQ18
10575 13:22:41.022311 <6>[ 0.840622] kvm [1]: VHE mode initialized successfully
10576 13:22:41.029182 <5>[ 0.847216] Initialise system trusted keyrings
10577 13:22:41.035824 <6>[ 0.852056] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10578 13:22:41.043696 <6>[ 0.862045] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10579 13:22:41.049577 <5>[ 0.868441] NFS: Registering the id_resolver key type
10580 13:22:41.052902 <5>[ 0.873740] Key type id_resolver registered
10581 13:22:41.059653 <5>[ 0.878156] Key type id_legacy registered
10582 13:22:41.066208 <6>[ 0.882437] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10583 13:22:41.073043 <6>[ 0.889358] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10584 13:22:41.079596 <6>[ 0.897072] 9p: Installing v9fs 9p2000 file system support
10585 13:22:41.115397 <5>[ 0.934242] Key type asymmetric registered
10586 13:22:41.118551 <5>[ 0.938575] Asymmetric key parser 'x509' registered
10587 13:22:41.128889 <6>[ 0.943721] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10588 13:22:41.131761 <6>[ 0.951334] io scheduler mq-deadline registered
10589 13:22:41.135196 <6>[ 0.956110] io scheduler kyber registered
10590 13:22:41.153945 <6>[ 0.973035] EINJ: ACPI disabled.
10591 13:22:41.186395 <4>[ 0.998658] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10592 13:22:41.196184 <4>[ 1.009280] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10593 13:22:41.211172 <6>[ 1.029874] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10594 13:22:41.218974 <6>[ 1.037879] printk: console [ttyS0] disabled
10595 13:22:41.246886 <6>[ 1.062528] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10596 13:22:41.253884 <6>[ 1.072005] printk: console [ttyS0] enabled
10597 13:22:41.256971 <6>[ 1.072005] printk: console [ttyS0] enabled
10598 13:22:41.263638 <6>[ 1.080900] printk: bootconsole [mtk8250] disabled
10599 13:22:41.267142 <6>[ 1.080900] printk: bootconsole [mtk8250] disabled
10600 13:22:41.273720 <6>[ 1.092157] SuperH (H)SCI(F) driver initialized
10601 13:22:41.277291 <6>[ 1.097448] msm_serial: driver initialized
10602 13:22:41.290974 <6>[ 1.106451] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10603 13:22:41.300738 <6>[ 1.114998] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10604 13:22:41.307975 <6>[ 1.123539] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10605 13:22:41.317585 <6>[ 1.132167] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10606 13:22:41.324628 <6>[ 1.140878] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10607 13:22:41.334214 <6>[ 1.149598] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10608 13:22:41.344433 <6>[ 1.158138] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10609 13:22:41.350710 <6>[ 1.166969] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10610 13:22:41.360621 <6>[ 1.175511] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10611 13:22:41.372467 <6>[ 1.191037] loop: module loaded
10612 13:22:41.379086 <6>[ 1.197025] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10613 13:22:41.401672 <4>[ 1.220289] mtk-pmic-keys: Failed to locate of_node [id: -1]
10614 13:22:41.408310 <6>[ 1.227131] megasas: 07.719.03.00-rc1
10615 13:22:41.417640 <6>[ 1.236683] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10616 13:22:41.426635 <6>[ 1.245575] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10617 13:22:41.443540 <6>[ 1.262220] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10618 13:22:41.500612 <6>[ 1.312582] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10619 13:22:42.980782 <6>[ 2.799828] Freeing initrd memory: 46400K
10620 13:22:42.991197 <6>[ 2.810052] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10621 13:22:43.001713 <6>[ 2.820851] tun: Universal TUN/TAP device driver, 1.6
10622 13:22:43.005394 <6>[ 2.826924] thunder_xcv, ver 1.0
10623 13:22:43.008800 <6>[ 2.830429] thunder_bgx, ver 1.0
10624 13:22:43.011551 <6>[ 2.833919] nicpf, ver 1.0
10625 13:22:43.022564 <6>[ 2.837928] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10626 13:22:43.025716 <6>[ 2.845403] hns3: Copyright (c) 2017 Huawei Corporation.
10627 13:22:43.028862 <6>[ 2.850990] hclge is initializing
10628 13:22:43.035394 <6>[ 2.854569] e1000: Intel(R) PRO/1000 Network Driver
10629 13:22:43.042000 <6>[ 2.859698] e1000: Copyright (c) 1999-2006 Intel Corporation.
10630 13:22:43.045355 <6>[ 2.865711] e1000e: Intel(R) PRO/1000 Network Driver
10631 13:22:43.052303 <6>[ 2.870927] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10632 13:22:43.058597 <6>[ 2.877111] igb: Intel(R) Gigabit Ethernet Network Driver
10633 13:22:43.065721 <6>[ 2.882760] igb: Copyright (c) 2007-2014 Intel Corporation.
10634 13:22:43.072126 <6>[ 2.888599] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10635 13:22:43.078586 <6>[ 2.895117] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10636 13:22:43.081818 <6>[ 2.901575] sky2: driver version 1.30
10637 13:22:43.088436 <6>[ 2.906573] VFIO - User Level meta-driver version: 0.3
10638 13:22:43.096171 <6>[ 2.914824] usbcore: registered new interface driver usb-storage
10639 13:22:43.102185 <6>[ 2.921268] usbcore: registered new device driver onboard-usb-hub
10640 13:22:43.111687 <6>[ 2.930362] mt6397-rtc mt6359-rtc: registered as rtc0
10641 13:22:43.121297 <6>[ 2.935827] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-06T13:22:39 UTC (1694006559)
10642 13:22:43.124910 <6>[ 2.945391] i2c_dev: i2c /dev entries driver
10643 13:22:43.141215 <6>[ 2.957019] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10644 13:22:43.160815 <6>[ 2.980008] cpu cpu0: EM: created perf domain
10645 13:22:43.164084 <6>[ 2.985023] cpu cpu4: EM: created perf domain
10646 13:22:43.171525 <6>[ 2.990633] sdhci: Secure Digital Host Controller Interface driver
10647 13:22:43.178157 <6>[ 2.997062] sdhci: Copyright(c) Pierre Ossman
10648 13:22:43.184804 <6>[ 3.002028] Synopsys Designware Multimedia Card Interface Driver
10649 13:22:43.188032 <6>[ 3.008649] mmc0: CQHCI version 5.10
10650 13:22:43.195210 <6>[ 3.008665] sdhci-pltfm: SDHCI platform and OF driver helper
10651 13:22:43.201444 <6>[ 3.019750] ledtrig-cpu: registered to indicate activity on CPUs
10652 13:22:43.207896 <6>[ 3.026945] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10653 13:22:43.214775 <6>[ 3.034004] usbcore: registered new interface driver usbhid
10654 13:22:43.218234 <6>[ 3.039826] usbhid: USB HID core driver
10655 13:22:43.228258 <6>[ 3.044021] spi_master spi0: will run message pump with realtime priority
10656 13:22:43.267660 <6>[ 3.080285] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10657 13:22:43.286312 <6>[ 3.095343] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10658 13:22:43.289597 <6>[ 3.108878] mmc0: Command Queue Engine enabled
10659 13:22:43.296109 <6>[ 3.113631] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10660 13:22:43.302640 <6>[ 3.121219] mmcblk0: mmc0:0001 DA4128 116 GiB
10661 13:22:43.309689 <6>[ 3.126174] cros-ec-spi spi0.0: Chrome EC device registered
10662 13:22:43.312675 <6>[ 3.129689] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10663 13:22:43.319901 <6>[ 3.138912] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10664 13:22:43.326950 <6>[ 3.144942] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10665 13:22:43.333300 <6>[ 3.150857] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10666 13:22:43.350660 <6>[ 3.166607] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10667 13:22:43.358357 <6>[ 3.177225] NET: Registered PF_PACKET protocol family
10668 13:22:43.361681 <6>[ 3.182630] 9pnet: Installing 9P2000 support
10669 13:22:43.368363 <5>[ 3.187193] Key type dns_resolver registered
10670 13:22:43.371381 <6>[ 3.192158] registered taskstats version 1
10671 13:22:43.378325 <5>[ 3.196544] Loading compiled-in X.509 certificates
10672 13:22:43.407660 <4>[ 3.220089] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10673 13:22:43.417782 <4>[ 3.230960] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10674 13:22:43.424079 <3>[ 3.241522] debugfs: File 'uA_load' in directory '/' already present!
10675 13:22:43.430695 <3>[ 3.248250] debugfs: File 'min_uV' in directory '/' already present!
10676 13:22:43.437416 <3>[ 3.254885] debugfs: File 'max_uV' in directory '/' already present!
10677 13:22:43.444074 <3>[ 3.261497] debugfs: File 'constraint_flags' in directory '/' already present!
10678 13:22:43.455389 <3>[ 3.271126] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10679 13:22:43.467672 <6>[ 3.286929] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10680 13:22:43.474538 <6>[ 3.293733] xhci-mtk 11200000.usb: xHCI Host Controller
10681 13:22:43.481126 <6>[ 3.299235] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10682 13:22:43.491538 <6>[ 3.307179] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10683 13:22:43.498392 <6>[ 3.316614] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10684 13:22:43.504979 <6>[ 3.322688] xhci-mtk 11200000.usb: xHCI Host Controller
10685 13:22:43.511631 <6>[ 3.328167] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10686 13:22:43.518230 <6>[ 3.335814] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10687 13:22:43.525024 <6>[ 3.343622] hub 1-0:1.0: USB hub found
10688 13:22:43.527911 <6>[ 3.347638] hub 1-0:1.0: 1 port detected
10689 13:22:43.534426 <6>[ 3.351909] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10690 13:22:43.541753 <6>[ 3.360605] hub 2-0:1.0: USB hub found
10691 13:22:43.544979 <6>[ 3.364631] hub 2-0:1.0: 1 port detected
10692 13:22:43.552291 <6>[ 3.371199] mtk-msdc 11f70000.mmc: Got CD GPIO
10693 13:22:43.564450 <6>[ 3.380211] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10694 13:22:43.571208 <6>[ 3.388249] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10695 13:22:43.580902 <4>[ 3.396166] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10696 13:22:43.590931 <6>[ 3.405691] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10697 13:22:43.597584 <6>[ 3.413767] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10698 13:22:43.604632 <6>[ 3.421869] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10699 13:22:43.614267 <6>[ 3.429817] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10700 13:22:43.620745 <6>[ 3.437635] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10701 13:22:43.630810 <6>[ 3.445452] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10702 13:22:43.640504 <6>[ 3.455956] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10703 13:22:43.647152 <6>[ 3.464319] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10704 13:22:43.656955 <6>[ 3.472658] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10705 13:22:43.663580 <6>[ 3.480996] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10706 13:22:43.673547 <6>[ 3.489334] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10707 13:22:43.683481 <6>[ 3.497673] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10708 13:22:43.689875 <6>[ 3.506011] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10709 13:22:43.700120 <6>[ 3.514349] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10710 13:22:43.706409 <6>[ 3.522687] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10711 13:22:43.716312 <6>[ 3.531025] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10712 13:22:43.722885 <6>[ 3.539363] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10713 13:22:43.733069 <6>[ 3.547701] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10714 13:22:43.739652 <6>[ 3.556039] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10715 13:22:43.749763 <6>[ 3.564391] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10716 13:22:43.756130 <6>[ 3.572731] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10717 13:22:43.762589 <6>[ 3.581530] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10718 13:22:43.769564 <6>[ 3.588706] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10719 13:22:43.776201 <6>[ 3.595461] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10720 13:22:43.786201 <6>[ 3.602233] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10721 13:22:43.792862 <6>[ 3.609173] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10722 13:22:43.799635 <6>[ 3.616014] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10723 13:22:43.810005 <6>[ 3.625146] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10724 13:22:43.819484 <6>[ 3.634266] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10725 13:22:43.829807 <6>[ 3.643561] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10726 13:22:43.839064 <6>[ 3.653030] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10727 13:22:43.848973 <6>[ 3.662497] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10728 13:22:43.855553 <6>[ 3.671618] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10729 13:22:43.865600 <6>[ 3.681087] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10730 13:22:43.875343 <6>[ 3.690206] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10731 13:22:43.885561 <6>[ 3.699501] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10732 13:22:43.895375 <6>[ 3.709662] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10733 13:22:43.905751 <6>[ 3.721542] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10734 13:22:43.935050 <6>[ 3.750733] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10735 13:22:43.962748 <6>[ 3.781921] hub 2-1:1.0: USB hub found
10736 13:22:43.966200 <6>[ 3.786407] hub 2-1:1.0: 3 ports detected
10737 13:22:44.086330 <6>[ 3.902384] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10738 13:22:44.241297 <6>[ 4.060495] hub 1-1:1.0: USB hub found
10739 13:22:44.244466 <6>[ 4.064997] hub 1-1:1.0: 4 ports detected
10740 13:22:44.318883 <6>[ 4.134769] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10741 13:22:44.566649 <6>[ 4.382514] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10742 13:22:44.699052 <6>[ 4.518329] hub 1-1.4:1.0: USB hub found
10743 13:22:44.702127 <6>[ 4.522996] hub 1-1.4:1.0: 2 ports detected
10744 13:22:44.998289 <6>[ 4.814490] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10745 13:22:45.190597 <6>[ 5.006489] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10746 13:22:56.191662 <6>[ 16.015477] ALSA device list:
10747 13:22:56.198067 <6>[ 16.018765] No soundcards found.
10748 13:22:56.206054 <6>[ 16.026735] Freeing unused kernel memory: 8384K
10749 13:22:56.209321 <6>[ 16.031827] Run /init as init process
10750 13:22:56.257359 <6>[ 16.077950] NET: Registered PF_INET6 protocol family
10751 13:22:56.264345 <6>[ 16.084107] Segment Routing with IPv6
10752 13:22:56.267219 <6>[ 16.088050] In-situ OAM (IOAM) with IPv6
10753 13:22:56.298881 <30>[ 16.102751] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10754 13:22:56.306159 <30>[ 16.126732] systemd[1]: Detected architecture arm64.
10755 13:22:56.306269
10756 13:22:56.312535 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10757 13:22:56.312652
10758 13:22:56.326058 <30>[ 16.146519] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10759 13:22:56.484087 <30>[ 16.301299] systemd[1]: Queued start job for default target Graphical Interface.
10760 13:22:56.526573 <30>[ 16.347243] systemd[1]: Created slice system-getty.slice.
10761 13:22:56.533252 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10762 13:22:56.550245 <30>[ 16.371003] systemd[1]: Created slice system-modprobe.slice.
10763 13:22:56.557170 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10764 13:22:56.575561 <30>[ 16.395714] systemd[1]: Created slice system-serial\x2dgetty.slice.
10765 13:22:56.584964 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10766 13:22:56.598136 <30>[ 16.418823] systemd[1]: Created slice User and Session Slice.
10767 13:22:56.605057 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10768 13:22:56.625916 <30>[ 16.443095] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10769 13:22:56.635905 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10770 13:22:56.653463 <30>[ 16.470531] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10771 13:22:56.659777 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10772 13:22:56.680909 <30>[ 16.494556] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10773 13:22:56.687701 <30>[ 16.506695] systemd[1]: Reached target Local Encrypted Volumes.
10774 13:22:56.693934 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10775 13:22:56.710406 <30>[ 16.531012] systemd[1]: Reached target Paths.
10776 13:22:56.713611 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10777 13:22:56.729930 <30>[ 16.550469] systemd[1]: Reached target Remote File Systems.
10778 13:22:56.736359 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10779 13:22:56.754337 <30>[ 16.574859] systemd[1]: Reached target Slices.
10780 13:22:56.760647 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10781 13:22:56.774296 <30>[ 16.594479] systemd[1]: Reached target Swap.
10782 13:22:56.777018 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10783 13:22:56.797518 <30>[ 16.614978] systemd[1]: Listening on initctl Compatibility Named Pipe.
10784 13:22:56.804705 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10785 13:22:56.810866 <30>[ 16.630132] systemd[1]: Listening on Journal Audit Socket.
10786 13:22:56.817466 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10787 13:22:56.830356 <30>[ 16.650951] systemd[1]: Listening on Journal Socket (/dev/log).
10788 13:22:56.837036 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10789 13:22:56.855160 <30>[ 16.675725] systemd[1]: Listening on Journal Socket.
10790 13:22:56.862071 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10791 13:22:56.877904 <30>[ 16.695154] systemd[1]: Listening on Network Service Netlink Socket.
10792 13:22:56.884452 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10793 13:22:56.899084 <30>[ 16.719689] systemd[1]: Listening on udev Control Socket.
10794 13:22:56.905741 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10795 13:22:56.923167 <30>[ 16.743552] systemd[1]: Listening on udev Kernel Socket.
10796 13:22:56.929464 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10797 13:22:56.969948 <30>[ 16.790652] systemd[1]: Mounting Huge Pages File System...
10798 13:22:56.976630 Mounting [0;1;39mHuge Pages File System[0m...
10799 13:22:56.992639 <30>[ 16.812905] systemd[1]: Mounting POSIX Message Queue File System...
10800 13:22:56.998846 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10801 13:22:57.017910 <30>[ 16.838599] systemd[1]: Mounting Kernel Debug File System...
10802 13:22:57.024654 Mounting [0;1;39mKernel Debug File System[0m...
10803 13:22:57.041395 <30>[ 16.858662] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10804 13:22:57.052128 <30>[ 16.869560] systemd[1]: Starting Create list of static device nodes for the current kernel...
10805 13:22:57.058798 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10806 13:22:57.077292 <30>[ 16.897690] systemd[1]: Starting Load Kernel Module configfs...
10807 13:22:57.083603 Starting [0;1;39mLoad Kernel Module configfs[0m...
10808 13:22:57.101091 <30>[ 16.921791] systemd[1]: Starting Load Kernel Module drm...
10809 13:22:57.107777 Starting [0;1;39mLoad Kernel Module drm[0m...
10810 13:22:57.125165 <30>[ 16.942879] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10811 13:22:57.139806 <30>[ 16.960625] systemd[1]: Starting Journal Service...
10812 13:22:57.143419 Starting [0;1;39mJournal Service[0m...
10813 13:22:57.167982 <30>[ 16.988480] systemd[1]: Starting Load Kernel Modules...
10814 13:22:57.174547 Starting [0;1;39mLoad Kernel Modules[0m...
10815 13:22:57.226137 <30>[ 17.043368] systemd[1]: Starting Remount Root and Kernel File Systems...
10816 13:22:57.232595 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10817 13:22:57.248943 <30>[ 17.069303] systemd[1]: Starting Coldplug All udev Devices...
10818 13:22:57.255515 Starting [0;1;39mColdplug All udev Devices[0m...
10819 13:22:57.273271 <30>[ 17.093632] systemd[1]: Started Journal Service.
10820 13:22:57.279686 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10821 13:22:57.295767 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10822 13:22:57.311399 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10823 13:22:57.326854 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10824 13:22:57.346897 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10825 13:22:57.364657 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10826 13:22:57.384296 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10827 13:22:57.404044 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10828 13:22:57.423832 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10829 13:22:57.438016 See 'systemctl status systemd-remount-fs.service' for details.
10830 13:22:57.495209 Mounting [0;1;39mKernel Configuration File System[0m...
10831 13:22:57.512680 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10832 13:22:57.526379 <46>[ 17.343885] systemd-journald[189]: Received client request to flush runtime journal.
10833 13:22:57.537810 Starting [0;1;39mLoad/Save Random Seed[0m...
10834 13:22:57.558173 Starting [0;1;39mApply Kernel Variables[0m...
10835 13:22:57.579087 Starting [0;1;39mCreate System Users[0m...
10836 13:22:57.600742 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10837 13:22:57.618890 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10838 13:22:57.642798 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10839 13:22:57.655377 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10840 13:22:57.675488 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10841 13:22:57.691797 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10842 13:22:57.738504 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10843 13:22:57.766716 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10844 13:22:57.778230 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10845 13:22:57.794081 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10846 13:22:57.834167 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10847 13:22:57.858249 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10848 13:22:57.878946 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10849 13:22:57.899389 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10850 13:22:57.946942 Starting [0;1;39mNetwork Service[0m...
10851 13:22:57.968232 Starting [0;1;39mNetwork Time Synchronization[0m...
10852 13:22:57.992439 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10853 13:22:58.015697 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10854 13:22:58.048737 Starting [0;1;39mNetwork Name Resolution[0m...
10855 13:22:58.070388 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10856 13:22:58.106290 <6>[ 17.923805] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10857 13:22:58.117866 <4>[ 17.935111] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10858 13:22:58.121112 <6>[ 17.937890] remoteproc remoteproc0: scp is available
10859 13:22:58.127905 <4>[ 17.943033] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10860 13:22:58.134538 <6>[ 17.950770] remoteproc remoteproc0: powering up scp
10861 13:22:58.144419 <6>[ 17.960256] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10862 13:22:58.147361 <6>[ 17.960287] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10863 13:22:58.154513 <6>[ 17.963716] usbcore: registered new interface driver r8152
10864 13:22:58.160845 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10865 13:22:58.173869 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10866 13:22:58.188086 <3>[ 18.005495] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10867 13:22:58.194641 <6>[ 18.005675] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10868 13:22:58.204703 <3>[ 18.013631] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10869 13:22:58.211491 <3>[ 18.013637] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10870 13:22:58.217862 <6>[ 18.022242] mc: Linux media interface: v0.10
10871 13:22:58.224622 <3>[ 18.025425] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10872 13:22:58.231254 <3>[ 18.025461] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10873 13:22:58.240970 <3>[ 18.025476] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10874 13:22:58.247490 <3>[ 18.025490] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10875 13:22:58.257585 <3>[ 18.025504] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10876 13:22:58.267554 <6>[ 18.029618] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10877 13:22:58.277880 <6>[ 18.039177] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10878 13:22:58.284023 <6>[ 18.042402] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10879 13:22:58.294206 <3>[ 18.044381] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10880 13:22:58.301055 <6>[ 18.051428] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10881 13:22:58.310610 <3>[ 18.063138] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10882 13:22:58.317216 <6>[ 18.063647] videodev: Linux video capture interface: v2.00
10883 13:22:58.323588 <6>[ 18.065267] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10884 13:22:58.330478 <6>[ 18.069289] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10885 13:22:58.340428 <3>[ 18.075023] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10886 13:22:58.347087 <6>[ 18.086173] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10887 13:22:58.357294 <3>[ 18.092061] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10888 13:22:58.363923 <6>[ 18.105738] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10889 13:22:58.373684 <6>[ 18.110636] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10890 13:22:58.376935 <6>[ 18.110651] remoteproc remoteproc0: remote processor scp is now up
10891 13:22:58.387268 <3>[ 18.110857] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10892 13:22:58.393494 <6>[ 18.119647] usbcore: registered new interface driver cdc_ether
10893 13:22:58.400579 <3>[ 18.128341] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10894 13:22:58.406707 <6>[ 18.134863] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10895 13:22:58.413573 <6>[ 18.142767] usbcore: registered new interface driver r8153_ecm
10896 13:22:58.423235 <3>[ 18.150221] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10897 13:22:58.430383 <4>[ 18.153549] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10898 13:22:58.436899 <4>[ 18.153549] Fallback method does not support PEC.
10899 13:22:58.440237 <6>[ 18.176137] Bluetooth: Core ver 2.22
10900 13:22:58.446897 <6>[ 18.180028] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10901 13:22:58.453386 <6>[ 18.180036] pci_bus 0000:00: root bus resource [bus 00-ff]
10902 13:22:58.460688 <6>[ 18.180041] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10903 13:22:58.470152 <6>[ 18.180047] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10904 13:22:58.476907 <6>[ 18.180077] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10905 13:22:58.483400 <6>[ 18.180097] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10906 13:22:58.486463 <6>[ 18.180177] pci 0000:00:00.0: supports D1 D2
10907 13:22:58.493579 <6>[ 18.180180] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10908 13:22:58.503114 <6>[ 18.181859] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10909 13:22:58.509615 <6>[ 18.182010] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10910 13:22:58.516396 <6>[ 18.182045] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10911 13:22:58.523013 <6>[ 18.182066] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10912 13:22:58.532685 <6>[ 18.182085] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10913 13:22:58.536440 <6>[ 18.182316] pci 0000:01:00.0: supports D1 D2
10914 13:22:58.542866 <3>[ 18.182474] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10915 13:22:58.553393 <3>[ 18.182490] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10916 13:22:58.559928 <3>[ 18.182565] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10917 13:22:58.567105 <6>[ 18.190770] NET: Registered PF_BLUETOOTH protocol family
10918 13:22:58.574163 <6>[ 18.197989] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10919 13:22:58.577771 <6>[ 18.204434] Bluetooth: HCI device and connection manager initialized
10920 13:22:58.584450 <6>[ 18.207292] r8152 2-1.3:1.0 eth0: v1.12.13
10921 13:22:58.591548 <6>[ 18.209469] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10922 13:22:58.597999 <6>[ 18.233838] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10923 13:22:58.610681 <6>[ 18.234032] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10924 13:22:58.617690 <6>[ 18.237483] usbcore: registered new interface driver uvcvideo
10925 13:22:58.620728 <6>[ 18.240583] Bluetooth: HCI socket layer initialized
10926 13:22:58.627614 <6>[ 18.242315] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10927 13:22:58.634476 <6>[ 18.248233] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10928 13:22:58.640543 <6>[ 18.251587] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10929 13:22:58.647257 <6>[ 18.261907] Bluetooth: L2CAP socket layer initialized
10930 13:22:58.654034 <6>[ 18.265362] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10931 13:22:58.664154 <6>[ 18.265451] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10932 13:22:58.667584 <6>[ 18.272210] Bluetooth: SCO socket layer initialized
10933 13:22:58.674051 <6>[ 18.309554] usbcore: registered new interface driver btusb
10934 13:22:58.680509 <6>[ 18.313643] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10935 13:22:58.693765 <4>[ 18.313990] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10936 13:22:58.697343 <3>[ 18.314008] Bluetooth: hci0: Failed to load firmware file (-2)
10937 13:22:58.703867 <3>[ 18.314014] Bluetooth: hci0: Failed to set up firmware (-2)
10938 13:22:58.713598 <4>[ 18.314023] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10939 13:22:58.723636 <6>[ 18.317445] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10940 13:22:58.733251 <3>[ 18.320250] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 13:22:58.740261 <3>[ 18.395049] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 13:22:58.749951 <6>[ 18.398538] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10943 13:22:58.757729 <6>[ 18.574614] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10944 13:22:58.764001 <3>[ 18.576366] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 13:22:58.774615 <3>[ 18.577010] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10946 13:22:58.781256 <6>[ 18.582635] pci 0000:00:00.0: PCI bridge to [bus 01]
10947 13:22:58.788454 [[0;32m OK [<6>[ 18.582642] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10948 13:22:58.798121 0m] Started [0;<6>[ 18.582850] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10949 13:22:58.804385 <3>[ 18.583258] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 13:22:58.815090 <3>[ 18.611177] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 13:22:58.821608 1;39mNetwork Nam<6>[ 18.615346] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10952 13:22:58.831870 e Resolution[0m<3>[ 18.642563] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 13:22:58.831956 .
10954 13:22:58.838264 <6>[ 18.648006] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10955 13:22:58.856913 <5>[ 18.673945] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10956 13:22:58.863345 <3>[ 18.678134] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10957 13:22:58.877692 <5>[ 18.695195] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10958 13:22:58.884920 <4>[ 18.702127] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10959 13:22:58.891459 <6>[ 18.711003] cfg80211: failed to load regulatory.db
10960 13:22:58.898264 <3>[ 18.711361] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 13:22:58.914191 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10962 13:22:58.928899 <3>[ 18.746549] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 13:22:58.935423 <6>[ 18.755548] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10964 13:22:58.942156 <6>[ 18.763058] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10965 13:22:58.949260 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10966 13:22:58.961463 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10967 13:22:58.968729 <6>[ 18.789719] mt7921e 0000:01:00.0: ASIC revision: 79610010
10968 13:22:58.978293 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10969 13:22:58.993727 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10970 13:22:59.009498 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10971 13:22:59.029782 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10972 13:22:59.075505 Startin<4>[ 18.890577] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10973 13:22:59.081954 g [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10974 13:22:59.103171 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10975 13:22:59.118482 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10976 13:22:59.141884 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10977 13:22:59.161296 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10978 13:22:59.180258 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10979 13:22:59.195085 <4>[ 19.009428] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10980 13:22:59.207161 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10981 13:22:59.222003 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10982 13:22:59.241779 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10983 13:22:59.282487 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10984 13:22:59.314844 <4>[ 19.129261] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10985 13:22:59.328868 Starting [0;1;39mUser Login Management[0m...
10986 13:22:59.351514 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10987 13:22:59.371205 Starting [0;1;39mPermit User Sessions[0m...
10988 13:22:59.387418 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10989 13:22:59.396132 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10990 13:22:59.437747 [[0;32m OK [0m] Started [0;<4>[ 19.250477] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10991 13:22:59.437836 1;39mGetty on tty1[0m.
10992 13:22:59.474439 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10993 13:22:59.489858 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10994 13:22:59.507097 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10995 13:22:59.515131 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10996 13:22:59.530773 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10997 13:22:59.554695 <4>[ 19.368934] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10998 13:22:59.588234 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10999 13:22:59.624715 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11000 13:22:59.674995 <4>[ 19.489412] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11001 13:22:59.684615
11002 13:22:59.684726
11003 13:22:59.688345 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11004 13:22:59.688430
11005 13:22:59.691373 debian-bullseye-arm64 login: root (automatic login)
11006 13:22:59.691457
11007 13:22:59.691524
11008 13:22:59.724776 Linux debian-bullseye-arm64 6.1.46-cip4 #1 SMP PREEMPT Wed Sep 6 13:11:19 UTC 2023 aarch64
11009 13:22:59.724877
11010 13:22:59.731277 The programs included with the Debian GNU/Linux system are free software;
11011 13:22:59.737754 the exact distribution terms for each program are described in the
11012 13:22:59.741340 individual files in /usr/share/doc/*/copyright.
11013 13:22:59.741424
11014 13:22:59.747554 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11015 13:22:59.751389 permitted by applicable law.
11016 13:22:59.751757 Matched prompt #10: / #
11018 13:22:59.751963 Setting prompt string to ['/ #']
11019 13:22:59.752058 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11021 13:22:59.752252 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11022 13:22:59.752341 start: 2.2.6 expect-shell-connection (timeout 00:03:27) [common]
11023 13:22:59.752414 Setting prompt string to ['/ #']
11024 13:22:59.752477 Forcing a shell prompt, looking for ['/ #']
11026 13:22:59.802691 / #
11027 13:22:59.802793 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11028 13:22:59.802888 Waiting using forced prompt support (timeout 00:02:30)
11029 13:22:59.802988 <4>[ 19.609376] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11030 13:22:59.808152
11031 13:22:59.849107 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11032 13:22:59.849215 start: 2.2.7 export-device-env (timeout 00:03:27) [common]
11033 13:22:59.849312 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11034 13:22:59.849403 end: 2.2 depthcharge-retry (duration 00:01:33) [common]
11035 13:22:59.849488 end: 2 depthcharge-action (duration 00:01:33) [common]
11036 13:22:59.849577 start: 3 lava-test-retry (timeout 00:05:00) [common]
11037 13:22:59.849662 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11038 13:22:59.849740 Using namespace: common
11040 13:22:59.950072 / # #
11041 13:22:59.950188 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11042 13:22:59.950312 <4>[ 19.729221] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11043 13:22:59.955117 #
11044 13:22:59.955381 Using /lava-11445609
11046 13:23:00.055706 / # export SHELL=/bin/sh
11047 13:23:00.055844 export SHELL=/bin/sh<6>[ 19.846574] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomes ready
11048 13:23:00.055927 <4>[ 19.854530] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11049 13:23:00.055994 <6>[ 19.854769] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
11050 13:23:00.060718
11052 13:23:00.161280 / # . /lava-11445609/environment
11053 13:23:00.204902 . /lava-11445609/environment<4>[ 19.980929] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11054 13:23:00.205011
11056 13:23:00.305522 / # /lava-11445609/bin/lava-test-runner /lava-11445609/0
11057 13:23:00.305633 Test shell timeout: 10s (minimum of the action and connection timeout)
11058 13:23:00.305966 /lava-11445609/bin/lava-test-runner /lava-11445609/0<3>[ 20.098767] mt7921e 0000:01:00.0: hardware init failed
11059 13:23:00.310932
11060 13:23:00.352880 + export TESTRUN_ID=0_cros-ec
11061 13:23:00.352968 +<8>[ 20.158054] <LAVA_SIGNAL_STARTRUN 0_cros-ec 11445609_1.5.2.3.1>
11062 13:23:00.353037 cd /lava-11445609/0/tests/0_cros-ec
11063 13:23:00.353102 + cat uuid
11064 13:23:00.353163 + UUID=11445609_1.5.2.3.1
11065 13:23:00.353223 + set +x
11066 13:23:00.353281 + python3 -m cros.runners.lava_runner -v
11067 13:23:00.353513 Received signal: <STARTRUN> 0_cros-ec 11445609_1.5.2.3.1
11068 13:23:00.353581 Starting test lava.0_cros-ec (11445609_1.5.2.3.1)
11069 13:23:00.353660 Skipping test definition patterns.
11070 13:23:00.732377 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11071 13:23:00.742651 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11072 13:23:00.742741
11073 13:23:00.749192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11074 13:23:00.749448 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11076 13:23:00.755841 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11077 13:23:00.762282 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11078 13:23:00.765792
11079 13:23:00.772316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11080 13:23:00.772567 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11082 13:23:00.779343 test_cros_ec<8>[ 20.598441] <LAVA_SIGNAL_ENDRUN 0_cros-ec 11445609_1.5.2.3.1>
11083 13:23:00.779596 Received signal: <ENDRUN> 0_cros-ec 11445609_1.5.2.3.1
11084 13:23:00.779677 Ending use of test pattern.
11085 13:23:00.779741 Ending test lava.0_cros-ec (11445609_1.5.2.3.1), duration 0.43
11087 13:23:00.782290 _gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11088 13:23:00.789158 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11089 13:23:00.789241
11090 13:23:00.795335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11091 13:23:00.795587 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11093 13:23:00.802369 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11094 13:23:00.808709 Checks the standard ABI for the main Embedded Controller. ... ok
11095 13:23:00.808838
11096 13:23:00.812208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11097 13:23:00.812461 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11099 13:23:00.818501 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11100 13:23:00.825113 Checks the main Embedded controller character device. ... ok
11101 13:23:00.825195
11102 13:23:00.828876 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11104 13:23:00.831811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11105 13:23:00.835143 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11106 13:23:00.841788 Checks basic comunication with the main Embedded controller. ... ok
11107 13:23:00.841871
11108 13:23:00.848443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11109 13:23:00.848700 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11111 13:23:00.851472 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11112 13:23:00.861393 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11113 13:23:00.861477
11114 13:23:00.865156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11115 13:23:00.865410 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11117 13:23:00.871652 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11118 13:23:00.878672 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11119 13:23:00.878757
11120 13:23:00.884524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11121 13:23:00.884787 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11123 13:23:00.891343 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11124 13:23:00.897976 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11125 13:23:00.898060
11126 13:23:00.904542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11127 13:23:00.904803 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11129 13:23:00.908161 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11130 13:23:00.917537 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11131 13:23:00.917621
11132 13:23:00.920915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11133 13:23:00.921168 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11135 13:23:00.927822 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11136 13:23:00.937452 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11137 13:23:00.937536
11138 13:23:00.940923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11139 13:23:00.941175 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11141 13:23:00.947232 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11142 13:23:00.953805 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11143 13:23:00.953888
11144 13:23:00.960843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11145 13:23:00.961095 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11147 13:23:00.967719 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11148 13:23:00.973894 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11149 13:23:00.973978
11150 13:23:00.980650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11151 13:23:00.980932 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11153 13:23:00.987088 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11154 13:23:00.994085 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11155 13:23:00.994170
11156 13:23:01.000610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11157 13:23:01.000889 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11159 13:23:01.007024 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11160 13:23:01.013610 Check the cros battery ABI. ... skipped 'No BAT found'
11161 13:23:01.013694
11162 13:23:01.020242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11163 13:23:01.020495 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11165 13:23:01.026861 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11166 13:23:01.033378 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11167 13:23:01.033461
11168 13:23:01.040094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11169 13:23:01.040346 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11171 13:23:01.043270 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11172 13:23:01.050079 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11173 13:23:01.050163
11174 13:23:01.056996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11175 13:23:01.057277 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11177 13:23:01.063530 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11178 13:23:01.069676 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11179 13:23:01.069759
11180 13:23:01.076501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11181 13:23:01.076585
11182 13:23:01.076833 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11184 13:23:01.083084 ----------------------------------------------------------------------
11185 13:23:01.087009 Ran 18 tests in 0.010s
11186 13:23:01.087092
11187 13:23:01.087158 OK (skipped=15)
11188 13:23:01.087221 + set +x
11189 13:23:01.089664 <LAVA_TEST_RUNNER EXIT>
11190 13:23:01.089917 ok: lava_test_shell seems to have completed
11191 13:23:01.090093 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11192 13:23:01.090189 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11193 13:23:01.090274 end: 3 lava-test-retry (duration 00:00:01) [common]
11194 13:23:01.090360 start: 4 finalize (timeout 00:08:04) [common]
11195 13:23:01.090452 start: 4.1 power-off (timeout 00:00:30) [common]
11196 13:23:01.090601 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11197 13:23:01.165397 >> Command sent successfully.
11198 13:23:01.167896 Returned 0 in 0 seconds
11199 13:23:01.268306 end: 4.1 power-off (duration 00:00:00) [common]
11201 13:23:01.268639 start: 4.2 read-feedback (timeout 00:08:04) [common]
11202 13:23:01.268944 Listened to connection for namespace 'common' for up to 1s
11203 13:23:02.268875 Finalising connection for namespace 'common'
11204 13:23:02.269057 Disconnecting from shell: Finalise
11205 13:23:02.269134 / #
11206 13:23:02.369455 end: 4.2 read-feedback (duration 00:00:01) [common]
11207 13:23:02.369611 end: 4 finalize (duration 00:00:01) [common]
11208 13:23:02.369724 Cleaning after the job
11209 13:23:02.369826 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11445609/tftp-deploy-4jxawmcg/ramdisk
11210 13:23:02.375039 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11445609/tftp-deploy-4jxawmcg/kernel
11211 13:23:02.381398 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11445609/tftp-deploy-4jxawmcg/dtb
11212 13:23:02.381554 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11445609/tftp-deploy-4jxawmcg/modules
11213 13:23:02.387006 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11445609
11214 13:23:02.486722 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11445609
11215 13:23:02.486909 Job finished correctly