Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 274
- Boot result: PASS
- Warnings: 1
- Errors: 0
- Kernel Warnings: 101
1 13:20:18.140425 lava-dispatcher, installed at version: 2023.06
2 13:20:18.140652 start: 0 validate
3 13:20:18.140787 Start time: 2023-09-06 13:20:18.140780+00:00 (UTC)
4 13:20:18.140914 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:20:18.141073 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:20:18.690086 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:20:18.690924 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4-14-g09ffd7fb38ff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:20:18.952278 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:20:18.953034 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4-14-g09ffd7fb38ff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:21:06.143778 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:21:06.144461 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4-14-g09ffd7fb38ff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:21:06.675967 validate duration: 48.54
14 13:21:06.677239 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:21:06.677783 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:21:06.678499 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:21:06.679251 Not decompressing ramdisk as can be used compressed.
18 13:21:06.679733 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 13:21:06.680101 saving as /var/lib/lava/dispatcher/tmp/11445605/tftp-deploy-guggq_nz/ramdisk/rootfs.cpio.gz
20 13:21:06.680473 total size: 84918747 (80 MB)
21 13:21:10.578558 progress 0 % (0 MB)
22 13:21:10.640543 progress 5 % (4 MB)
23 13:21:10.663666 progress 10 % (8 MB)
24 13:21:10.685286 progress 15 % (12 MB)
25 13:21:10.707151 progress 20 % (16 MB)
26 13:21:10.728830 progress 25 % (20 MB)
27 13:21:10.750694 progress 30 % (24 MB)
28 13:21:10.772632 progress 35 % (28 MB)
29 13:21:10.794048 progress 40 % (32 MB)
30 13:21:10.816167 progress 45 % (36 MB)
31 13:21:10.838070 progress 50 % (40 MB)
32 13:21:10.859996 progress 55 % (44 MB)
33 13:21:10.881779 progress 60 % (48 MB)
34 13:21:10.903473 progress 65 % (52 MB)
35 13:21:10.925350 progress 70 % (56 MB)
36 13:21:10.946946 progress 75 % (60 MB)
37 13:21:10.968901 progress 80 % (64 MB)
38 13:21:10.990395 progress 85 % (68 MB)
39 13:21:11.011801 progress 90 % (72 MB)
40 13:21:11.033490 progress 95 % (76 MB)
41 13:21:11.054750 progress 100 % (80 MB)
42 13:21:11.054997 80 MB downloaded in 4.37 s (18.51 MB/s)
43 13:21:11.055258 end: 1.1.1 http-download (duration 00:00:04) [common]
45 13:21:11.055496 end: 1.1 download-retry (duration 00:00:04) [common]
46 13:21:11.055582 start: 1.2 download-retry (timeout 00:09:56) [common]
47 13:21:11.055663 start: 1.2.1 http-download (timeout 00:09:56) [common]
48 13:21:11.055799 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4-14-g09ffd7fb38ff/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:21:11.055868 saving as /var/lib/lava/dispatcher/tmp/11445605/tftp-deploy-guggq_nz/kernel/Image
50 13:21:11.055928 total size: 49220096 (46 MB)
51 13:21:11.055987 No compression specified
52 13:21:11.057111 progress 0 % (0 MB)
53 13:21:11.069738 progress 5 % (2 MB)
54 13:21:11.082238 progress 10 % (4 MB)
55 13:21:11.094686 progress 15 % (7 MB)
56 13:21:11.107085 progress 20 % (9 MB)
57 13:21:11.119478 progress 25 % (11 MB)
58 13:21:11.131974 progress 30 % (14 MB)
59 13:21:11.144565 progress 35 % (16 MB)
60 13:21:11.157338 progress 40 % (18 MB)
61 13:21:11.170002 progress 45 % (21 MB)
62 13:21:11.182753 progress 50 % (23 MB)
63 13:21:11.195050 progress 55 % (25 MB)
64 13:21:11.207545 progress 60 % (28 MB)
65 13:21:11.219943 progress 65 % (30 MB)
66 13:21:11.232321 progress 70 % (32 MB)
67 13:21:11.244870 progress 75 % (35 MB)
68 13:21:11.257698 progress 80 % (37 MB)
69 13:21:11.270733 progress 85 % (39 MB)
70 13:21:11.283654 progress 90 % (42 MB)
71 13:21:11.297100 progress 95 % (44 MB)
72 13:21:11.309753 progress 100 % (46 MB)
73 13:21:11.309880 46 MB downloaded in 0.25 s (184.84 MB/s)
74 13:21:11.310027 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:21:11.310251 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:21:11.310336 start: 1.3 download-retry (timeout 00:09:55) [common]
78 13:21:11.310430 start: 1.3.1 http-download (timeout 00:09:55) [common]
79 13:21:11.310565 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4-14-g09ffd7fb38ff/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:21:11.310678 saving as /var/lib/lava/dispatcher/tmp/11445605/tftp-deploy-guggq_nz/dtb/mt8192-asurada-spherion-r0.dtb
81 13:21:11.310738 total size: 47278 (0 MB)
82 13:21:11.310797 No compression specified
83 13:21:11.311914 progress 69 % (0 MB)
84 13:21:11.312185 progress 100 % (0 MB)
85 13:21:11.312339 0 MB downloaded in 0.00 s (28.22 MB/s)
86 13:21:11.312456 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:21:11.312672 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:21:11.312755 start: 1.4 download-retry (timeout 00:09:55) [common]
90 13:21:11.312835 start: 1.4.1 http-download (timeout 00:09:55) [common]
91 13:21:11.312944 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4-14-g09ffd7fb38ff/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:21:11.313009 saving as /var/lib/lava/dispatcher/tmp/11445605/tftp-deploy-guggq_nz/modules/modules.tar
93 13:21:11.313066 total size: 8610736 (8 MB)
94 13:21:11.313126 Using unxz to decompress xz
95 13:21:11.317138 progress 0 % (0 MB)
96 13:21:11.337475 progress 5 % (0 MB)
97 13:21:11.360711 progress 10 % (0 MB)
98 13:21:11.389675 progress 15 % (1 MB)
99 13:21:11.417471 progress 20 % (1 MB)
100 13:21:11.440681 progress 25 % (2 MB)
101 13:21:11.464188 progress 30 % (2 MB)
102 13:21:11.488083 progress 35 % (2 MB)
103 13:21:11.514034 progress 40 % (3 MB)
104 13:21:11.539479 progress 45 % (3 MB)
105 13:21:11.564299 progress 50 % (4 MB)
106 13:21:11.589073 progress 55 % (4 MB)
107 13:21:11.613107 progress 60 % (4 MB)
108 13:21:11.637238 progress 65 % (5 MB)
109 13:21:11.660266 progress 70 % (5 MB)
110 13:21:11.687231 progress 75 % (6 MB)
111 13:21:11.710473 progress 80 % (6 MB)
112 13:21:11.738015 progress 85 % (7 MB)
113 13:21:11.762586 progress 90 % (7 MB)
114 13:21:11.786128 progress 95 % (7 MB)
115 13:21:11.811792 progress 100 % (8 MB)
116 13:21:11.817469 8 MB downloaded in 0.50 s (16.28 MB/s)
117 13:21:11.817707 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:21:11.817962 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:21:11.818054 start: 1.5 prepare-tftp-overlay (timeout 00:09:55) [common]
121 13:21:11.818150 start: 1.5.1 extract-nfsrootfs (timeout 00:09:55) [common]
122 13:21:11.818232 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:21:11.818320 start: 1.5.2 lava-overlay (timeout 00:09:55) [common]
124 13:21:11.818561 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti
125 13:21:11.818774 makedir: /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin
126 13:21:11.818877 makedir: /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/tests
127 13:21:11.818975 makedir: /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/results
128 13:21:11.819090 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-add-keys
129 13:21:11.819238 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-add-sources
130 13:21:11.819368 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-background-process-start
131 13:21:11.819499 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-background-process-stop
132 13:21:11.819624 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-common-functions
133 13:21:11.819748 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-echo-ipv4
134 13:21:11.819873 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-install-packages
135 13:21:11.819997 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-installed-packages
136 13:21:11.820120 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-os-build
137 13:21:11.820244 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-probe-channel
138 13:21:11.820369 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-probe-ip
139 13:21:11.820492 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-target-ip
140 13:21:11.820615 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-target-mac
141 13:21:11.820737 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-target-storage
142 13:21:11.820863 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-test-case
143 13:21:11.820989 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-test-event
144 13:21:11.821112 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-test-feedback
145 13:21:11.821235 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-test-raise
146 13:21:11.821360 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-test-reference
147 13:21:11.821486 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-test-runner
148 13:21:11.821610 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-test-set
149 13:21:11.821736 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-test-shell
150 13:21:11.821863 Updating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-install-packages (oe)
151 13:21:11.822016 Updating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/bin/lava-installed-packages (oe)
152 13:21:11.822138 Creating /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/environment
153 13:21:11.822244 LAVA metadata
154 13:21:11.822327 - LAVA_JOB_ID=11445605
155 13:21:11.822391 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:21:11.822494 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:55) [common]
157 13:21:11.822560 skipped lava-vland-overlay
158 13:21:11.822662 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:21:11.822755 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:55) [common]
160 13:21:11.822815 skipped lava-multinode-overlay
161 13:21:11.822887 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:21:11.822970 start: 1.5.2.3 test-definition (timeout 00:09:55) [common]
163 13:21:11.823041 Loading test definitions
164 13:21:11.823127 start: 1.5.2.3.1 git-repo-action (timeout 00:09:55) [common]
165 13:21:11.823199 Using /lava-11445605 at stage 0
166 13:21:11.823292 Fetching tests from https://github.com/kernelci/kernelci-core
167 13:21:11.823375 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/0/tests/0_sleep'
168 13:21:12.587120 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/0/tests/0_sleep
169 13:21:12.588895 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 13:21:12.589396 uuid=11445605_1.5.2.3.1 testdef=None
171 13:21:12.589591 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 13:21:12.589934 start: 1.5.2.3.2 test-overlay (timeout 00:09:54) [common]
174 13:21:12.590671 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 13:21:12.590992 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:54) [common]
177 13:21:12.592266 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 13:21:12.592621 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:54) [common]
180 13:21:12.593530 runner path: /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/0/tests/0_sleep test_uuid 11445605_1.5.2.3.1
181 13:21:12.593644 sleep_params='mem freeze'
182 13:21:12.593848 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 13:21:12.594279 Creating lava-test-runner.conf files
185 13:21:12.594381 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11445605/lava-overlay-c11zf_ti/lava-11445605/0 for stage 0
186 13:21:12.594556 - 0_sleep
187 13:21:12.594723 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 13:21:12.594851 start: 1.5.2.4 compress-overlay (timeout 00:09:54) [common]
189 13:21:12.724155 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 13:21:12.724315 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:54) [common]
191 13:21:12.724428 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 13:21:12.724544 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 13:21:12.724649 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
194 13:21:15.133386 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 13:21:15.133796 start: 1.5.4 extract-modules (timeout 00:09:52) [common]
196 13:21:15.133934 extracting modules file /var/lib/lava/dispatcher/tmp/11445605/tftp-deploy-guggq_nz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11445605/extract-overlay-ramdisk-l5blknos/ramdisk
197 13:21:15.358604 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 13:21:15.358817 start: 1.5.5 apply-overlay-tftp (timeout 00:09:51) [common]
199 13:21:15.358933 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11445605/compress-overlay-x6_76npw/overlay-1.5.2.4.tar.gz to ramdisk
200 13:21:15.359017 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11445605/compress-overlay-x6_76npw/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11445605/extract-overlay-ramdisk-l5blknos/ramdisk
201 13:21:15.454054 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 13:21:15.454234 start: 1.5.6 configure-preseed-file (timeout 00:09:51) [common]
203 13:21:15.454348 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 13:21:15.454454 start: 1.5.7 compress-ramdisk (timeout 00:09:51) [common]
205 13:21:15.454568 Building ramdisk /var/lib/lava/dispatcher/tmp/11445605/extract-overlay-ramdisk-l5blknos/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11445605/extract-overlay-ramdisk-l5blknos/ramdisk
206 13:21:17.036776 >> 563347 blocks
207 13:21:26.473315 rename /var/lib/lava/dispatcher/tmp/11445605/extract-overlay-ramdisk-l5blknos/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11445605/tftp-deploy-guggq_nz/ramdisk/ramdisk.cpio.gz
208 13:21:26.473749 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 13:21:26.473865 start: 1.5.8 prepare-kernel (timeout 00:09:40) [common]
210 13:21:26.473962 start: 1.5.8.1 prepare-fit (timeout 00:09:40) [common]
211 13:21:26.474076 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11445605/tftp-deploy-guggq_nz/kernel/Image'
212 13:21:38.382447 Returned 0 in 11 seconds
213 13:21:38.483499 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11445605/tftp-deploy-guggq_nz/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11445605/tftp-deploy-guggq_nz/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11445605/tftp-deploy-guggq_nz/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11445605/tftp-deploy-guggq_nz/kernel/image.itb
214 13:21:39.826175 output: FIT description: Kernel Image image with one or more FDT blobs
215 13:21:39.826547 output: Created: Wed Sep 6 14:21:39 2023
216 13:21:39.826671 output: Image 0 (kernel-1)
217 13:21:39.826748 output: Description:
218 13:21:39.826810 output: Created: Wed Sep 6 14:21:39 2023
219 13:21:39.826871 output: Type: Kernel Image
220 13:21:39.826933 output: Compression: lzma compressed
221 13:21:39.826991 output: Data Size: 11038222 Bytes = 10779.51 KiB = 10.53 MiB
222 13:21:39.827050 output: Architecture: AArch64
223 13:21:39.827110 output: OS: Linux
224 13:21:39.827165 output: Load Address: 0x00000000
225 13:21:39.827218 output: Entry Point: 0x00000000
226 13:21:39.827269 output: Hash algo: crc32
227 13:21:39.827321 output: Hash value: eae831c7
228 13:21:39.827372 output: Image 1 (fdt-1)
229 13:21:39.827424 output: Description: mt8192-asurada-spherion-r0
230 13:21:39.827476 output: Created: Wed Sep 6 14:21:39 2023
231 13:21:39.827527 output: Type: Flat Device Tree
232 13:21:39.827579 output: Compression: uncompressed
233 13:21:39.827631 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 13:21:39.827682 output: Architecture: AArch64
235 13:21:39.827733 output: Hash algo: crc32
236 13:21:39.827784 output: Hash value: cc4352de
237 13:21:39.827835 output: Image 2 (ramdisk-1)
238 13:21:39.827886 output: Description: unavailable
239 13:21:39.827938 output: Created: Wed Sep 6 14:21:39 2023
240 13:21:39.827989 output: Type: RAMDisk Image
241 13:21:39.828041 output: Compression: Unknown Compression
242 13:21:39.828093 output: Data Size: 98307255 Bytes = 96003.18 KiB = 93.75 MiB
243 13:21:39.828145 output: Architecture: AArch64
244 13:21:39.828196 output: OS: Linux
245 13:21:39.828247 output: Load Address: unavailable
246 13:21:39.828298 output: Entry Point: unavailable
247 13:21:39.828350 output: Hash algo: crc32
248 13:21:39.828401 output: Hash value: 6f8991da
249 13:21:39.828452 output: Default Configuration: 'conf-1'
250 13:21:39.828503 output: Configuration 0 (conf-1)
251 13:21:39.828554 output: Description: mt8192-asurada-spherion-r0
252 13:21:39.828605 output: Kernel: kernel-1
253 13:21:39.828656 output: Init Ramdisk: ramdisk-1
254 13:21:39.828708 output: FDT: fdt-1
255 13:21:39.828759 output: Loadables: kernel-1
256 13:21:39.828810 output:
257 13:21:39.829006 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
258 13:21:39.829097 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
259 13:21:39.829200 end: 1.5 prepare-tftp-overlay (duration 00:00:28) [common]
260 13:21:39.829297 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:27) [common]
261 13:21:39.829379 No LXC device requested
262 13:21:39.829459 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 13:21:39.829542 start: 1.7 deploy-device-env (timeout 00:09:27) [common]
264 13:21:39.829619 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 13:21:39.829688 Checking files for TFTP limit of 4294967296 bytes.
266 13:21:39.830179 end: 1 tftp-deploy (duration 00:00:33) [common]
267 13:21:39.830285 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 13:21:39.830376 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 13:21:39.830504 substitutions:
270 13:21:39.830569 - {DTB}: 11445605/tftp-deploy-guggq_nz/dtb/mt8192-asurada-spherion-r0.dtb
271 13:21:39.830688 - {INITRD}: 11445605/tftp-deploy-guggq_nz/ramdisk/ramdisk.cpio.gz
272 13:21:39.830759 - {KERNEL}: 11445605/tftp-deploy-guggq_nz/kernel/Image
273 13:21:39.830815 - {LAVA_MAC}: None
274 13:21:39.830873 - {PRESEED_CONFIG}: None
275 13:21:39.830927 - {PRESEED_LOCAL}: None
276 13:21:39.830981 - {RAMDISK}: 11445605/tftp-deploy-guggq_nz/ramdisk/ramdisk.cpio.gz
277 13:21:39.831035 - {ROOT_PART}: None
278 13:21:39.831088 - {ROOT}: None
279 13:21:39.831141 - {SERVER_IP}: 192.168.201.1
280 13:21:39.831193 - {TEE}: None
281 13:21:39.831246 Parsed boot commands:
282 13:21:39.831299 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 13:21:39.831475 Parsed boot commands: tftpboot 192.168.201.1 11445605/tftp-deploy-guggq_nz/kernel/image.itb 11445605/tftp-deploy-guggq_nz/kernel/cmdline
284 13:21:39.831566 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 13:21:39.831647 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 13:21:39.831737 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 13:21:39.831823 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 13:21:39.831894 Not connected, no need to disconnect.
289 13:21:39.831965 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 13:21:39.832045 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 13:21:39.832113 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
292 13:21:39.836055 Setting prompt string to ['lava-test: # ']
293 13:21:39.836401 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 13:21:39.836503 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 13:21:39.836601 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 13:21:39.836713 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 13:21:39.836956 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
298 13:21:44.984695 >> Command sent successfully.
299 13:21:44.995906 Returned 0 in 5 seconds
300 13:21:45.097242 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 13:21:45.098849 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 13:21:45.099400 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 13:21:45.099894 Setting prompt string to 'Starting depthcharge on Spherion...'
305 13:21:45.100274 Changing prompt to 'Starting depthcharge on Spherion...'
306 13:21:45.100662 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 13:21:45.101972 [Enter `^Ec?' for help]
308 13:21:45.262149
309 13:21:45.262758
310 13:21:45.263136 F0: 102B 0000
311 13:21:45.263482
312 13:21:45.263808 F3: 1001 0000 [0200]
313 13:21:45.264131
314 13:21:45.264849 F3: 1001 0000
315 13:21:45.265481
316 13:21:45.265865 F7: 102D 0000
317 13:21:45.266214
318 13:21:45.266547 F1: 0000 0000
319 13:21:45.268013
320 13:21:45.268476 V0: 0000 0000 [0001]
321 13:21:45.268985
322 13:21:45.269607 00: 0007 8000
323 13:21:45.270053
324 13:21:45.272354 01: 0000 0000
325 13:21:45.273163
326 13:21:45.273689 BP: 0C00 0209 [0000]
327 13:21:45.274059
328 13:21:45.275778 G0: 1182 0000
329 13:21:45.276366
330 13:21:45.276760 EC: 0000 0021 [4000]
331 13:21:45.277110
332 13:21:45.279446 S7: 0000 0000 [0000]
333 13:21:45.279985
334 13:21:45.280362 CC: 0000 0000 [0001]
335 13:21:45.280705
336 13:21:45.283193 T0: 0000 0040 [010F]
337 13:21:45.283844
338 13:21:45.284230 Jump to BL
339 13:21:45.284580
340 13:21:45.308670
341 13:21:45.309228
342 13:21:45.309596
343 13:21:45.314795 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 13:21:45.318294 ARM64: Exception handlers installed.
345 13:21:45.321698 ARM64: Testing exception
346 13:21:45.325368 ARM64: Done test exception
347 13:21:45.332228 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 13:21:45.343127 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 13:21:45.350254 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 13:21:45.361408 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 13:21:45.364601 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 13:21:45.375273 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 13:21:45.385791 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 13:21:45.391924 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 13:21:45.410427 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 13:21:45.413984 WDT: Last reset was cold boot
357 13:21:45.417557 SPI1(PAD0) initialized at 2873684 Hz
358 13:21:45.420571 SPI5(PAD0) initialized at 992727 Hz
359 13:21:45.424002 VBOOT: Loading verstage.
360 13:21:45.430391 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 13:21:45.434385 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 13:21:45.437202 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 13:21:45.440274 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 13:21:45.447883 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 13:21:45.455043 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 13:21:45.466490 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 13:21:45.467138
368 13:21:45.467513
369 13:21:45.475553 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 13:21:45.478780 ARM64: Exception handlers installed.
371 13:21:45.482542 ARM64: Testing exception
372 13:21:45.483165 ARM64: Done test exception
373 13:21:45.488998 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 13:21:45.492200 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 13:21:45.506680 Probing TPM: . done!
376 13:21:45.507243 TPM ready after 0 ms
377 13:21:45.513216 Connected to device vid:did:rid of 1ae0:0028:00
378 13:21:45.523473 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
379 13:21:45.561405 Initialized TPM device CR50 revision 0
380 13:21:45.573826 tlcl_send_startup: Startup return code is 0
381 13:21:45.574389 TPM: setup succeeded
382 13:21:45.585273 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 13:21:45.593477 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 13:21:45.604440 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 13:21:45.612534 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 13:21:45.616199 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 13:21:45.619401 in-header: 03 07 00 00 08 00 00 00
388 13:21:45.622660 in-data: aa e4 47 04 13 02 00 00
389 13:21:45.626267 Chrome EC: UHEPI supported
390 13:21:45.632421 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 13:21:45.635499 in-header: 03 ad 00 00 08 00 00 00
392 13:21:45.638981 in-data: 00 20 20 08 00 00 00 00
393 13:21:45.639447 Phase 1
394 13:21:45.642425 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 13:21:45.650161 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 13:21:45.655543 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 13:21:45.659346 Recovery requested (1009000e)
398 13:21:45.666250 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 13:21:45.671200 tlcl_extend: response is 0
400 13:21:45.679647 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 13:21:45.685589 tlcl_extend: response is 0
402 13:21:45.691524 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 13:21:45.712238 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
404 13:21:45.718717 BS: bootblock times (exec / console): total (unknown) / 149 ms
405 13:21:45.719276
406 13:21:45.719647
407 13:21:45.729240 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 13:21:45.733121 ARM64: Exception handlers installed.
409 13:21:45.733873 ARM64: Testing exception
410 13:21:45.736373 ARM64: Done test exception
411 13:21:45.757751 pmic_efuse_setting: Set efuses in 11 msecs
412 13:21:45.761905 pmwrap_interface_init: Select PMIF_VLD_RDY
413 13:21:45.764974 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 13:21:45.772258 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 13:21:45.775067 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 13:21:45.782087 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 13:21:45.785208 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 13:21:45.791923 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 13:21:45.795369 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 13:21:45.802440 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 13:21:45.805850 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 13:21:45.808647 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 13:21:45.815683 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 13:21:45.818970 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 13:21:45.822440 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 13:21:45.829186 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 13:21:45.835528 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 13:21:45.842019 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 13:21:45.845719 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 13:21:45.852079 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 13:21:45.858781 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 13:21:45.865567 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 13:21:45.868945 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 13:21:45.875903 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 13:21:45.879875 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 13:21:45.887369 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 13:21:45.891105 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 13:21:45.897196 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 13:21:45.901065 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 13:21:45.907637 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 13:21:45.911697 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 13:21:45.914913 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 13:21:45.921862 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 13:21:45.926681 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 13:21:45.933436 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 13:21:45.936173 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 13:21:45.942906 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 13:21:45.946061 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 13:21:45.952776 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 13:21:45.956142 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 13:21:45.959891 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 13:21:45.967599 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 13:21:45.970666 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 13:21:45.975102 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 13:21:45.978103 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 13:21:45.981671 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 13:21:45.987886 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 13:21:45.991134 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 13:21:45.994809 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 13:21:46.001138 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 13:21:46.004448 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 13:21:46.007642 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 13:21:46.010952 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 13:21:46.021158 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 13:21:46.027958 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 13:21:46.034870 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 13:21:46.041518 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 13:21:46.050864 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 13:21:46.054746 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 13:21:46.058277 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 13:21:46.064370 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 13:21:46.070771 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x37
473 13:21:46.077851 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 13:21:46.080542 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
475 13:21:46.083924 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 13:21:46.094748 [RTC]rtc_get_frequency_meter,154: input=15, output=835
477 13:21:46.104136 [RTC]rtc_get_frequency_meter,154: input=7, output=709
478 13:21:46.113868 [RTC]rtc_get_frequency_meter,154: input=11, output=772
479 13:21:46.123110 [RTC]rtc_get_frequency_meter,154: input=13, output=804
480 13:21:46.132534 [RTC]rtc_get_frequency_meter,154: input=12, output=787
481 13:21:46.142209 [RTC]rtc_get_frequency_meter,154: input=12, output=789
482 13:21:46.151914 [RTC]rtc_get_frequency_meter,154: input=13, output=804
483 13:21:46.154897 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
484 13:21:46.162349 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
485 13:21:46.165204 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 13:21:46.168658 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 13:21:46.175318 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 13:21:46.178680 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 13:21:46.182027 ADC[4]: Raw value=905988 ID=7
490 13:21:46.182659 ADC[3]: Raw value=213282 ID=1
491 13:21:46.185415 RAM Code: 0x71
492 13:21:46.188672 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 13:21:46.195525 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 13:21:46.201857 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 13:21:46.207986 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 13:21:46.212817 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 13:21:46.215137 in-header: 03 07 00 00 08 00 00 00
498 13:21:46.219286 in-data: aa e4 47 04 13 02 00 00
499 13:21:46.221745 Chrome EC: UHEPI supported
500 13:21:46.228475 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 13:21:46.231724 in-header: 03 dd 00 00 08 00 00 00
502 13:21:46.234908 in-data: 90 20 60 08 00 00 00 00
503 13:21:46.238906 MRC: failed to locate region type 0.
504 13:21:46.245304 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 13:21:46.249215 DRAM-K: Running full calibration
506 13:21:46.255015 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 13:21:46.255619 header.status = 0x0
508 13:21:46.258790 header.version = 0x6 (expected: 0x6)
509 13:21:46.261538 header.size = 0xd00 (expected: 0xd00)
510 13:21:46.265261 header.flags = 0x0
511 13:21:46.271674 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 13:21:46.288562 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
513 13:21:46.295149 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 13:21:46.298804 dram_init: ddr_geometry: 2
515 13:21:46.301671 [EMI] MDL number = 2
516 13:21:46.302341 [EMI] Get MDL freq = 0
517 13:21:46.305111 dram_init: ddr_type: 0
518 13:21:46.305584 is_discrete_lpddr4: 1
519 13:21:46.309131 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 13:21:46.309713
521 13:21:46.310097
522 13:21:46.312179 [Bian_co] ETT version 0.0.0.1
523 13:21:46.318916 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 13:21:46.319497
525 13:21:46.321632 dramc_set_vcore_voltage set vcore to 650000
526 13:21:46.322158 Read voltage for 800, 4
527 13:21:46.325463 Vio18 = 0
528 13:21:46.326035 Vcore = 650000
529 13:21:46.326417 Vdram = 0
530 13:21:46.328452 Vddq = 0
531 13:21:46.329033 Vmddr = 0
532 13:21:46.332120 dram_init: config_dvfs: 1
533 13:21:46.335146 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 13:21:46.342195 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 13:21:46.345035 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
536 13:21:46.348315 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
537 13:21:46.351571 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
538 13:21:46.355439 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
539 13:21:46.358216 MEM_TYPE=3, freq_sel=18
540 13:21:46.361931 sv_algorithm_assistance_LP4_1600
541 13:21:46.364550 ============ PULL DRAM RESETB DOWN ============
542 13:21:46.371446 ========== PULL DRAM RESETB DOWN end =========
543 13:21:46.375002 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 13:21:46.377922 ===================================
545 13:21:46.381475 LPDDR4 DRAM CONFIGURATION
546 13:21:46.384909 ===================================
547 13:21:46.385377 EX_ROW_EN[0] = 0x0
548 13:21:46.388414 EX_ROW_EN[1] = 0x0
549 13:21:46.388990 LP4Y_EN = 0x0
550 13:21:46.391551 WORK_FSP = 0x0
551 13:21:46.392118 WL = 0x2
552 13:21:46.395315 RL = 0x2
553 13:21:46.395892 BL = 0x2
554 13:21:46.398224 RPST = 0x0
555 13:21:46.398845 RD_PRE = 0x0
556 13:21:46.401250 WR_PRE = 0x1
557 13:21:46.404445 WR_PST = 0x0
558 13:21:46.404919 DBI_WR = 0x0
559 13:21:46.407927 DBI_RD = 0x0
560 13:21:46.408395 OTF = 0x1
561 13:21:46.410918 ===================================
562 13:21:46.414657 ===================================
563 13:21:46.415228 ANA top config
564 13:21:46.417846 ===================================
565 13:21:46.421516 DLL_ASYNC_EN = 0
566 13:21:46.424341 ALL_SLAVE_EN = 1
567 13:21:46.427744 NEW_RANK_MODE = 1
568 13:21:46.431387 DLL_IDLE_MODE = 1
569 13:21:46.431959 LP45_APHY_COMB_EN = 1
570 13:21:46.434205 TX_ODT_DIS = 1
571 13:21:46.437692 NEW_8X_MODE = 1
572 13:21:46.441117 ===================================
573 13:21:46.444640 ===================================
574 13:21:46.447682 data_rate = 1600
575 13:21:46.451684 CKR = 1
576 13:21:46.452265 DQ_P2S_RATIO = 8
577 13:21:46.454305 ===================================
578 13:21:46.457623 CA_P2S_RATIO = 8
579 13:21:46.461190 DQ_CA_OPEN = 0
580 13:21:46.464387 DQ_SEMI_OPEN = 0
581 13:21:46.468143 CA_SEMI_OPEN = 0
582 13:21:46.470845 CA_FULL_RATE = 0
583 13:21:46.471318 DQ_CKDIV4_EN = 1
584 13:21:46.474639 CA_CKDIV4_EN = 1
585 13:21:46.477970 CA_PREDIV_EN = 0
586 13:21:46.480839 PH8_DLY = 0
587 13:21:46.484506 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 13:21:46.487798 DQ_AAMCK_DIV = 4
589 13:21:46.488376 CA_AAMCK_DIV = 4
590 13:21:46.490912 CA_ADMCK_DIV = 4
591 13:21:46.494377 DQ_TRACK_CA_EN = 0
592 13:21:46.497656 CA_PICK = 800
593 13:21:46.500574 CA_MCKIO = 800
594 13:21:46.504117 MCKIO_SEMI = 0
595 13:21:46.507281 PLL_FREQ = 3068
596 13:21:46.507757 DQ_UI_PI_RATIO = 32
597 13:21:46.510938 CA_UI_PI_RATIO = 0
598 13:21:46.514125 ===================================
599 13:21:46.517233 ===================================
600 13:21:46.520345 memory_type:LPDDR4
601 13:21:46.523832 GP_NUM : 10
602 13:21:46.524411 SRAM_EN : 1
603 13:21:46.527287 MD32_EN : 0
604 13:21:46.531071 ===================================
605 13:21:46.533714 [ANA_INIT] >>>>>>>>>>>>>>
606 13:21:46.534187 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 13:21:46.536905 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 13:21:46.540509 ===================================
609 13:21:46.544515 data_rate = 1600,PCW = 0X7600
610 13:21:46.547263 ===================================
611 13:21:46.550352 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 13:21:46.557029 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 13:21:46.563591 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 13:21:46.566917 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 13:21:46.570477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 13:21:46.574074 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 13:21:46.577028 [ANA_INIT] flow start
618 13:21:46.577623 [ANA_INIT] PLL >>>>>>>>
619 13:21:46.580344 [ANA_INIT] PLL <<<<<<<<
620 13:21:46.584093 [ANA_INIT] MIDPI >>>>>>>>
621 13:21:46.584679 [ANA_INIT] MIDPI <<<<<<<<
622 13:21:46.586796 [ANA_INIT] DLL >>>>>>>>
623 13:21:46.590769 [ANA_INIT] flow end
624 13:21:46.594001 ============ LP4 DIFF to SE enter ============
625 13:21:46.596999 ============ LP4 DIFF to SE exit ============
626 13:21:46.600615 [ANA_INIT] <<<<<<<<<<<<<
627 13:21:46.603283 [Flow] Enable top DCM control >>>>>
628 13:21:46.607316 [Flow] Enable top DCM control <<<<<
629 13:21:46.610078 Enable DLL master slave shuffle
630 13:21:46.613726 ==============================================================
631 13:21:46.617116 Gating Mode config
632 13:21:46.623520 ==============================================================
633 13:21:46.624175 Config description:
634 13:21:46.633247 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 13:21:46.639975 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 13:21:46.646749 SELPH_MODE 0: By rank 1: By Phase
637 13:21:46.650144 ==============================================================
638 13:21:46.653396 GAT_TRACK_EN = 1
639 13:21:46.656760 RX_GATING_MODE = 2
640 13:21:46.659890 RX_GATING_TRACK_MODE = 2
641 13:21:46.663344 SELPH_MODE = 1
642 13:21:46.666799 PICG_EARLY_EN = 1
643 13:21:46.669922 VALID_LAT_VALUE = 1
644 13:21:46.674092 ==============================================================
645 13:21:46.676789 Enter into Gating configuration >>>>
646 13:21:46.680062 Exit from Gating configuration <<<<
647 13:21:46.683297 Enter into DVFS_PRE_config >>>>>
648 13:21:46.696516 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 13:21:46.697190 Exit from DVFS_PRE_config <<<<<
650 13:21:46.700329 Enter into PICG configuration >>>>
651 13:21:46.703345 Exit from PICG configuration <<<<
652 13:21:46.706507 [RX_INPUT] configuration >>>>>
653 13:21:46.709858 [RX_INPUT] configuration <<<<<
654 13:21:46.716454 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 13:21:46.720094 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 13:21:46.727027 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 13:21:46.734577 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 13:21:46.738193 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 13:21:46.745525 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 13:21:46.749039 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 13:21:46.752494 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 13:21:46.756452 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 13:21:46.763884 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 13:21:46.767288 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 13:21:46.771064 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 13:21:46.774663 ===================================
667 13:21:46.778240 LPDDR4 DRAM CONFIGURATION
668 13:21:46.778868 ===================================
669 13:21:46.781699 EX_ROW_EN[0] = 0x0
670 13:21:46.782279 EX_ROW_EN[1] = 0x0
671 13:21:46.785528 LP4Y_EN = 0x0
672 13:21:46.786367 WORK_FSP = 0x0
673 13:21:46.789296 WL = 0x2
674 13:21:46.789985 RL = 0x2
675 13:21:46.792367 BL = 0x2
676 13:21:46.792834 RPST = 0x0
677 13:21:46.795708 RD_PRE = 0x0
678 13:21:46.796175 WR_PRE = 0x1
679 13:21:46.799750 WR_PST = 0x0
680 13:21:46.800317 DBI_WR = 0x0
681 13:21:46.803357 DBI_RD = 0x0
682 13:21:46.803822 OTF = 0x1
683 13:21:46.806902 ===================================
684 13:21:46.810932 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 13:21:46.814489 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 13:21:46.821032 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 13:21:46.824873 ===================================
688 13:21:46.825414 LPDDR4 DRAM CONFIGURATION
689 13:21:46.828435 ===================================
690 13:21:46.832049 EX_ROW_EN[0] = 0x10
691 13:21:46.832509 EX_ROW_EN[1] = 0x0
692 13:21:46.836118 LP4Y_EN = 0x0
693 13:21:46.836604 WORK_FSP = 0x0
694 13:21:46.839154 WL = 0x2
695 13:21:46.839583 RL = 0x2
696 13:21:46.842778 BL = 0x2
697 13:21:46.843204 RPST = 0x0
698 13:21:46.847033 RD_PRE = 0x0
699 13:21:46.847462 WR_PRE = 0x1
700 13:21:46.847803 WR_PST = 0x0
701 13:21:46.850676 DBI_WR = 0x0
702 13:21:46.851105 DBI_RD = 0x0
703 13:21:46.854445 OTF = 0x1
704 13:21:46.857640 ===================================
705 13:21:46.861819 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 13:21:46.867672 nWR fixed to 40
707 13:21:46.871051 [ModeRegInit_LP4] CH0 RK0
708 13:21:46.871481 [ModeRegInit_LP4] CH0 RK1
709 13:21:46.875257 [ModeRegInit_LP4] CH1 RK0
710 13:21:46.875776 [ModeRegInit_LP4] CH1 RK1
711 13:21:46.877994 match AC timing 13
712 13:21:46.881733 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 13:21:46.885064 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 13:21:46.891950 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 13:21:46.895118 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 13:21:46.899124 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 13:21:46.902067 [EMI DOE] emi_dcm 0
718 13:21:46.905399 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 13:21:46.905783 ==
720 13:21:46.908599 Dram Type= 6, Freq= 0, CH_0, rank 0
721 13:21:46.915165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 13:21:46.915678 ==
723 13:21:46.919559 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 13:21:46.926965 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 13:21:46.934261 [CA 0] Center 37 (7~68) winsize 62
726 13:21:46.937383 [CA 1] Center 36 (6~67) winsize 62
727 13:21:46.940648 [CA 2] Center 34 (4~65) winsize 62
728 13:21:46.944108 [CA 3] Center 34 (4~65) winsize 62
729 13:21:46.947784 [CA 4] Center 33 (3~64) winsize 62
730 13:21:46.951403 [CA 5] Center 33 (3~64) winsize 62
731 13:21:46.951874
732 13:21:46.954684 [CmdBusTrainingLP45] Vref(ca) range 1: 32
733 13:21:46.955154
734 13:21:46.958721 [CATrainingPosCal] consider 1 rank data
735 13:21:46.961614 u2DelayCellTimex100 = 270/100 ps
736 13:21:46.965025 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
737 13:21:46.968821 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
738 13:21:46.972109 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
739 13:21:46.975410 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
740 13:21:46.981844 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
741 13:21:46.984726 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
742 13:21:46.985294
743 13:21:46.988203 CA PerBit enable=1, Macro0, CA PI delay=33
744 13:21:46.988765
745 13:21:46.991187 [CBTSetCACLKResult] CA Dly = 33
746 13:21:46.991661 CS Dly: 6 (0~37)
747 13:21:46.992076 ==
748 13:21:46.994985 Dram Type= 6, Freq= 0, CH_0, rank 1
749 13:21:47.001250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 13:21:47.001835 ==
751 13:21:47.005171 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 13:21:47.011445 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 13:21:47.020523 [CA 0] Center 37 (6~68) winsize 63
754 13:21:47.023599 [CA 1] Center 37 (7~68) winsize 62
755 13:21:47.027643 [CA 2] Center 34 (4~65) winsize 62
756 13:21:47.030873 [CA 3] Center 34 (4~65) winsize 62
757 13:21:47.033677 [CA 4] Center 33 (3~64) winsize 62
758 13:21:47.036664 [CA 5] Center 33 (3~64) winsize 62
759 13:21:47.037136
760 13:21:47.040488 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 13:21:47.040957
762 13:21:47.043871 [CATrainingPosCal] consider 2 rank data
763 13:21:47.047084 u2DelayCellTimex100 = 270/100 ps
764 13:21:47.050559 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
765 13:21:47.057302 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
766 13:21:47.060458 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
767 13:21:47.064656 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
768 13:21:47.069098 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
769 13:21:47.071863 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 13:21:47.072445
771 13:21:47.075663 CA PerBit enable=1, Macro0, CA PI delay=33
772 13:21:47.076454
773 13:21:47.076919 [CBTSetCACLKResult] CA Dly = 33
774 13:21:47.079889 CS Dly: 6 (0~38)
775 13:21:47.080355
776 13:21:47.083000 ----->DramcWriteLeveling(PI) begin...
777 13:21:47.083474 ==
778 13:21:47.086208 Dram Type= 6, Freq= 0, CH_0, rank 0
779 13:21:47.089678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 13:21:47.090263 ==
781 13:21:47.093452 Write leveling (Byte 0): 33 => 33
782 13:21:47.096711 Write leveling (Byte 1): 27 => 27
783 13:21:47.100025 DramcWriteLeveling(PI) end<-----
784 13:21:47.100593
785 13:21:47.100965 ==
786 13:21:47.103052 Dram Type= 6, Freq= 0, CH_0, rank 0
787 13:21:47.106434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 13:21:47.107060 ==
789 13:21:47.109878 [Gating] SW mode calibration
790 13:21:47.116277 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 13:21:47.123284 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 13:21:47.126326 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 13:21:47.129573 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
794 13:21:47.136323 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
795 13:21:47.140142 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
796 13:21:47.142860 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:21:47.149667 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:21:47.152824 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:21:47.156028 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:21:47.163086 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:21:47.166279 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:21:47.169616 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:21:47.173725 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 13:21:47.179600 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 13:21:47.183296 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:21:47.186423 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:21:47.193194 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:21:47.196031 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:21:47.199328 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
810 13:21:47.206498 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
811 13:21:47.209441 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 13:21:47.212983 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 13:21:47.219528 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 13:21:47.222772 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 13:21:47.225826 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 13:21:47.232577 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 13:21:47.235943 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 13:21:47.238923 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
819 13:21:47.245904 0 9 12 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
820 13:21:47.249114 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 13:21:47.252372 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 13:21:47.258857 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 13:21:47.262235 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 13:21:47.265891 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 13:21:47.272041 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
826 13:21:47.275372 0 10 8 | B1->B0 | 3434 2e2e | 0 0 | (0 1) (0 0)
827 13:21:47.278998 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
828 13:21:47.285431 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 13:21:47.288790 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 13:21:47.292125 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 13:21:47.298682 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 13:21:47.302156 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 13:21:47.305381 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
834 13:21:47.311984 0 11 8 | B1->B0 | 2424 3939 | 0 1 | (0 0) (0 0)
835 13:21:47.315486 0 11 12 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
836 13:21:47.319282 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 13:21:47.325143 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 13:21:47.328543 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 13:21:47.332362 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 13:21:47.335934 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 13:21:47.343323 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 13:21:47.347496 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
843 13:21:47.351667 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:21:47.354723 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
845 13:21:47.358781 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:21:47.362406 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:21:47.369264 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:21:47.372967 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:21:47.377141 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:21:47.380598 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:21:47.384379 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 13:21:47.391538 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 13:21:47.395193 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 13:21:47.398505 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 13:21:47.401683 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 13:21:47.408055 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 13:21:47.411351 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 13:21:47.415135 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
859 13:21:47.421805 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
860 13:21:47.424951 Total UI for P1: 0, mck2ui 16
861 13:21:47.428244 best dqsien dly found for B0: ( 0, 14, 8)
862 13:21:47.428822 Total UI for P1: 0, mck2ui 16
863 13:21:47.434808 best dqsien dly found for B1: ( 0, 14, 8)
864 13:21:47.437828 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
865 13:21:47.441336 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
866 13:21:47.441812
867 13:21:47.445118 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
868 13:21:47.449070 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 13:21:47.452011 [Gating] SW calibration Done
870 13:21:47.452484 ==
871 13:21:47.455882 Dram Type= 6, Freq= 0, CH_0, rank 0
872 13:21:47.459534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
873 13:21:47.460025 ==
874 13:21:47.460406 RX Vref Scan: 0
875 13:21:47.460753
876 13:21:47.463315 RX Vref 0 -> 0, step: 1
877 13:21:47.463785
878 13:21:47.467483 RX Delay -130 -> 252, step: 16
879 13:21:47.471180 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
880 13:21:47.474267 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
881 13:21:47.477861 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
882 13:21:47.481910 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
883 13:21:47.484764 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
884 13:21:47.488468 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
885 13:21:47.494709 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
886 13:21:47.498211 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
887 13:21:47.501475 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
888 13:21:47.504613 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
889 13:21:47.508336 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
890 13:21:47.514886 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
891 13:21:47.518054 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
892 13:21:47.521599 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
893 13:21:47.525118 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
894 13:21:47.528772 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
895 13:21:47.531390 ==
896 13:21:47.535099 Dram Type= 6, Freq= 0, CH_0, rank 0
897 13:21:47.537775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 13:21:47.538265 ==
899 13:21:47.538671 DQS Delay:
900 13:21:47.541150 DQS0 = 0, DQS1 = 0
901 13:21:47.541621 DQM Delay:
902 13:21:47.546001 DQM0 = 86, DQM1 = 74
903 13:21:47.546581 DQ Delay:
904 13:21:47.547754 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
905 13:21:47.551619 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
906 13:21:47.554524 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
907 13:21:47.557605 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
908 13:21:47.558076
909 13:21:47.558450
910 13:21:47.558839 ==
911 13:21:47.561055 Dram Type= 6, Freq= 0, CH_0, rank 0
912 13:21:47.564740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 13:21:47.565216 ==
914 13:21:47.565593
915 13:21:47.565942
916 13:21:47.568167 TX Vref Scan disable
917 13:21:47.570800 == TX Byte 0 ==
918 13:21:47.574424 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
919 13:21:47.577686 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
920 13:21:47.581639 == TX Byte 1 ==
921 13:21:47.584041 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
922 13:21:47.587244 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
923 13:21:47.587574 ==
924 13:21:47.590297 Dram Type= 6, Freq= 0, CH_0, rank 0
925 13:21:47.597240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 13:21:47.597441 ==
927 13:21:47.609078 TX Vref=22, minBit 3, minWin=27, winSum=439
928 13:21:47.612774 TX Vref=24, minBit 8, minWin=27, winSum=445
929 13:21:47.615768 TX Vref=26, minBit 8, minWin=27, winSum=447
930 13:21:47.619052 TX Vref=28, minBit 8, minWin=27, winSum=445
931 13:21:47.622144 TX Vref=30, minBit 8, minWin=27, winSum=448
932 13:21:47.628628 TX Vref=32, minBit 9, minWin=26, winSum=443
933 13:21:47.632461 [TxChooseVref] Worse bit 8, Min win 27, Win sum 448, Final Vref 30
934 13:21:47.632547
935 13:21:47.635472 Final TX Range 1 Vref 30
936 13:21:47.635556
937 13:21:47.635622 ==
938 13:21:47.638672 Dram Type= 6, Freq= 0, CH_0, rank 0
939 13:21:47.642244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 13:21:47.645907 ==
941 13:21:47.645991
942 13:21:47.646056
943 13:21:47.646116 TX Vref Scan disable
944 13:21:47.649838 == TX Byte 0 ==
945 13:21:47.653326 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
946 13:21:47.657061 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
947 13:21:47.660606 == TX Byte 1 ==
948 13:21:47.664079 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
949 13:21:47.667745 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
950 13:21:47.668070
951 13:21:47.668307 [DATLAT]
952 13:21:47.671351 Freq=800, CH0 RK0
953 13:21:47.671597
954 13:21:47.671788 DATLAT Default: 0xa
955 13:21:47.675090 0, 0xFFFF, sum = 0
956 13:21:47.675277 1, 0xFFFF, sum = 0
957 13:21:47.678829 2, 0xFFFF, sum = 0
958 13:21:47.678987 3, 0xFFFF, sum = 0
959 13:21:47.683036 4, 0xFFFF, sum = 0
960 13:21:47.683200 5, 0xFFFF, sum = 0
961 13:21:47.683309 6, 0xFFFF, sum = 0
962 13:21:47.686030 7, 0xFFFF, sum = 0
963 13:21:47.686164 8, 0xFFFF, sum = 0
964 13:21:47.689649 9, 0x0, sum = 1
965 13:21:47.689768 10, 0x0, sum = 2
966 13:21:47.693394 11, 0x0, sum = 3
967 13:21:47.693511 12, 0x0, sum = 4
968 13:21:47.696960 best_step = 10
969 13:21:47.697076
970 13:21:47.697167 ==
971 13:21:47.700442 Dram Type= 6, Freq= 0, CH_0, rank 0
972 13:21:47.704315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 13:21:47.704471 ==
974 13:21:47.704624 RX Vref Scan: 1
975 13:21:47.704752
976 13:21:47.707682 Set Vref Range= 32 -> 127
977 13:21:47.707798
978 13:21:47.710987 RX Vref 32 -> 127, step: 1
979 13:21:47.711113
980 13:21:47.711209 RX Delay -111 -> 252, step: 8
981 13:21:47.711295
982 13:21:47.714923 Set Vref, RX VrefLevel [Byte0]: 32
983 13:21:47.717976 [Byte1]: 32
984 13:21:47.722346
985 13:21:47.722472 Set Vref, RX VrefLevel [Byte0]: 33
986 13:21:47.725675 [Byte1]: 33
987 13:21:47.730224
988 13:21:47.730339 Set Vref, RX VrefLevel [Byte0]: 34
989 13:21:47.732825 [Byte1]: 34
990 13:21:47.737480
991 13:21:47.737598 Set Vref, RX VrefLevel [Byte0]: 35
992 13:21:47.740553 [Byte1]: 35
993 13:21:47.745165
994 13:21:47.745281 Set Vref, RX VrefLevel [Byte0]: 36
995 13:21:47.748473 [Byte1]: 36
996 13:21:47.752438
997 13:21:47.752554 Set Vref, RX VrefLevel [Byte0]: 37
998 13:21:47.756043 [Byte1]: 37
999 13:21:47.760635
1000 13:21:47.760754 Set Vref, RX VrefLevel [Byte0]: 38
1001 13:21:47.764355 [Byte1]: 38
1002 13:21:47.768312
1003 13:21:47.768434 Set Vref, RX VrefLevel [Byte0]: 39
1004 13:21:47.771586 [Byte1]: 39
1005 13:21:47.776024
1006 13:21:47.776143 Set Vref, RX VrefLevel [Byte0]: 40
1007 13:21:47.780067 [Byte1]: 40
1008 13:21:47.783420
1009 13:21:47.783537 Set Vref, RX VrefLevel [Byte0]: 41
1010 13:21:47.787061 [Byte1]: 41
1011 13:21:47.790943
1012 13:21:47.791062 Set Vref, RX VrefLevel [Byte0]: 42
1013 13:21:47.795372 [Byte1]: 42
1014 13:21:47.798843
1015 13:21:47.798959 Set Vref, RX VrefLevel [Byte0]: 43
1016 13:21:47.802278 [Byte1]: 43
1017 13:21:47.806088
1018 13:21:47.809282 Set Vref, RX VrefLevel [Byte0]: 44
1019 13:21:47.809418 [Byte1]: 44
1020 13:21:47.814336
1021 13:21:47.814453 Set Vref, RX VrefLevel [Byte0]: 45
1022 13:21:47.817933 [Byte1]: 45
1023 13:21:47.822258
1024 13:21:47.822373 Set Vref, RX VrefLevel [Byte0]: 46
1025 13:21:47.825023 [Byte1]: 46
1026 13:21:47.829157
1027 13:21:47.829271 Set Vref, RX VrefLevel [Byte0]: 47
1028 13:21:47.832747 [Byte1]: 47
1029 13:21:47.837263
1030 13:21:47.837377 Set Vref, RX VrefLevel [Byte0]: 48
1031 13:21:47.840073 [Byte1]: 48
1032 13:21:47.844659
1033 13:21:47.844772 Set Vref, RX VrefLevel [Byte0]: 49
1034 13:21:47.847905 [Byte1]: 49
1035 13:21:47.852433
1036 13:21:47.852625 Set Vref, RX VrefLevel [Byte0]: 50
1037 13:21:47.856234 [Byte1]: 50
1038 13:21:47.859808
1039 13:21:47.859976 Set Vref, RX VrefLevel [Byte0]: 51
1040 13:21:47.863739 [Byte1]: 51
1041 13:21:47.867756
1042 13:21:47.867948 Set Vref, RX VrefLevel [Byte0]: 52
1043 13:21:47.870818 [Byte1]: 52
1044 13:21:47.875392
1045 13:21:47.875628 Set Vref, RX VrefLevel [Byte0]: 53
1046 13:21:47.878782 [Byte1]: 53
1047 13:21:47.883153
1048 13:21:47.883432 Set Vref, RX VrefLevel [Byte0]: 54
1049 13:21:47.886509 [Byte1]: 54
1050 13:21:47.890604
1051 13:21:47.890818 Set Vref, RX VrefLevel [Byte0]: 55
1052 13:21:47.894107 [Byte1]: 55
1053 13:21:47.898188
1054 13:21:47.898513 Set Vref, RX VrefLevel [Byte0]: 56
1055 13:21:47.901849 [Byte1]: 56
1056 13:21:47.906704
1057 13:21:47.907216 Set Vref, RX VrefLevel [Byte0]: 57
1058 13:21:47.909365 [Byte1]: 57
1059 13:21:47.914089
1060 13:21:47.914551 Set Vref, RX VrefLevel [Byte0]: 58
1061 13:21:47.917009 [Byte1]: 58
1062 13:21:47.921459
1063 13:21:47.921874 Set Vref, RX VrefLevel [Byte0]: 59
1064 13:21:47.924892 [Byte1]: 59
1065 13:21:47.929509
1066 13:21:47.930055 Set Vref, RX VrefLevel [Byte0]: 60
1067 13:21:47.932351 [Byte1]: 60
1068 13:21:47.937193
1069 13:21:47.937771 Set Vref, RX VrefLevel [Byte0]: 61
1070 13:21:47.940036 [Byte1]: 61
1071 13:21:47.944467
1072 13:21:47.944976 Set Vref, RX VrefLevel [Byte0]: 62
1073 13:21:47.947390 [Byte1]: 62
1074 13:21:47.952524
1075 13:21:47.952962 Set Vref, RX VrefLevel [Byte0]: 63
1076 13:21:47.955732 [Byte1]: 63
1077 13:21:47.959569
1078 13:21:47.960317 Set Vref, RX VrefLevel [Byte0]: 64
1079 13:21:47.962756 [Byte1]: 64
1080 13:21:47.967715
1081 13:21:47.968132 Set Vref, RX VrefLevel [Byte0]: 65
1082 13:21:47.970542 [Byte1]: 65
1083 13:21:47.975340
1084 13:21:47.975756 Set Vref, RX VrefLevel [Byte0]: 66
1085 13:21:47.978230 [Byte1]: 66
1086 13:21:47.982068
1087 13:21:47.986111 Set Vref, RX VrefLevel [Byte0]: 67
1088 13:21:47.986672 [Byte1]: 67
1089 13:21:47.990265
1090 13:21:47.990721 Set Vref, RX VrefLevel [Byte0]: 68
1091 13:21:47.993393 [Byte1]: 68
1092 13:21:47.997972
1093 13:21:47.998388 Set Vref, RX VrefLevel [Byte0]: 69
1094 13:21:48.001347 [Byte1]: 69
1095 13:21:48.005391
1096 13:21:48.006169 Set Vref, RX VrefLevel [Byte0]: 70
1097 13:21:48.009118 [Byte1]: 70
1098 13:21:48.013378
1099 13:21:48.013839 Set Vref, RX VrefLevel [Byte0]: 71
1100 13:21:48.016767 [Byte1]: 71
1101 13:21:48.020952
1102 13:21:48.021521 Set Vref, RX VrefLevel [Byte0]: 72
1103 13:21:48.023714 [Byte1]: 72
1104 13:21:48.028027
1105 13:21:48.028441 Set Vref, RX VrefLevel [Byte0]: 73
1106 13:21:48.031563 [Byte1]: 73
1107 13:21:48.036385
1108 13:21:48.036800 Set Vref, RX VrefLevel [Byte0]: 74
1109 13:21:48.039184 [Byte1]: 74
1110 13:21:48.043711
1111 13:21:48.044126 Set Vref, RX VrefLevel [Byte0]: 75
1112 13:21:48.047040 [Byte1]: 75
1113 13:21:48.051098
1114 13:21:48.051620 Set Vref, RX VrefLevel [Byte0]: 76
1115 13:21:48.055296 [Byte1]: 76
1116 13:21:48.058941
1117 13:21:48.059350 Set Vref, RX VrefLevel [Byte0]: 77
1118 13:21:48.062042 [Byte1]: 77
1119 13:21:48.066738
1120 13:21:48.067153 Set Vref, RX VrefLevel [Byte0]: 78
1121 13:21:48.069753 [Byte1]: 78
1122 13:21:48.074646
1123 13:21:48.075151 Set Vref, RX VrefLevel [Byte0]: 79
1124 13:21:48.077682 [Byte1]: 79
1125 13:21:48.082121
1126 13:21:48.082639 Set Vref, RX VrefLevel [Byte0]: 80
1127 13:21:48.085411 [Byte1]: 80
1128 13:21:48.089429
1129 13:21:48.089873 Final RX Vref Byte 0 = 63 to rank0
1130 13:21:48.093475 Final RX Vref Byte 1 = 60 to rank0
1131 13:21:48.097605 Final RX Vref Byte 0 = 63 to rank1
1132 13:21:48.100071 Final RX Vref Byte 1 = 60 to rank1==
1133 13:21:48.103864 Dram Type= 6, Freq= 0, CH_0, rank 0
1134 13:21:48.107403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1135 13:21:48.107964 ==
1136 13:21:48.108486 DQS Delay:
1137 13:21:48.110936 DQS0 = 0, DQS1 = 0
1138 13:21:48.111393 DQM Delay:
1139 13:21:48.115047 DQM0 = 86, DQM1 = 75
1140 13:21:48.115459 DQ Delay:
1141 13:21:48.119046 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =80
1142 13:21:48.122446 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =100
1143 13:21:48.125892 DQ8 =68, DQ9 =68, DQ10 =76, DQ11 =72
1144 13:21:48.130191 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =80
1145 13:21:48.130770
1146 13:21:48.131116
1147 13:21:48.137537 [DQSOSCAuto] RK0, (LSB)MR18= 0x4526, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
1148 13:21:48.138081 CH0 RK0: MR19=606, MR18=4526
1149 13:21:48.144067 CH0_RK0: MR19=0x606, MR18=0x4526, DQSOSC=392, MR23=63, INC=96, DEC=64
1150 13:21:48.144593
1151 13:21:48.147918 ----->DramcWriteLeveling(PI) begin...
1152 13:21:48.148497 ==
1153 13:21:48.150697 Dram Type= 6, Freq= 0, CH_0, rank 1
1154 13:21:48.157401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1155 13:21:48.157912 ==
1156 13:21:48.161116 Write leveling (Byte 0): 31 => 31
1157 13:21:48.161529 Write leveling (Byte 1): 31 => 31
1158 13:21:48.164565 DramcWriteLeveling(PI) end<-----
1159 13:21:48.164977
1160 13:21:48.168084 ==
1161 13:21:48.168498 Dram Type= 6, Freq= 0, CH_0, rank 1
1162 13:21:48.174419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1163 13:21:48.174989 ==
1164 13:21:48.177503 [Gating] SW mode calibration
1165 13:21:48.225019 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1166 13:21:48.225804 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1167 13:21:48.226340 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1168 13:21:48.227254 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1169 13:21:48.227673 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1170 13:21:48.228016 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1171 13:21:48.228340 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:21:48.228656 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 13:21:48.228967 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:21:48.229343 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:21:48.234223 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 13:21:48.237303 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 13:21:48.237833 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 13:21:48.240800 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 13:21:48.244659 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 13:21:48.251158 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 13:21:48.254003 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 13:21:48.257113 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 13:21:48.263740 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 13:21:48.267244 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 13:21:48.270992 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1186 13:21:48.277585 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1187 13:21:48.280379 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 13:21:48.283847 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 13:21:48.290740 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 13:21:48.293866 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 13:21:48.297536 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 13:21:48.303734 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 13:21:48.306950 0 9 8 | B1->B0 | 2626 3131 | 0 0 | (1 1) (0 0)
1194 13:21:48.310264 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 13:21:48.316907 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 13:21:48.320347 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 13:21:48.323998 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 13:21:48.330391 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1199 13:21:48.333266 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 13:21:48.337200 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1201 13:21:48.343709 0 10 8 | B1->B0 | 2d2d 2828 | 1 0 | (1 0) (0 0)
1202 13:21:48.347146 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
1203 13:21:48.350018 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 13:21:48.356586 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 13:21:48.360075 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 13:21:48.363585 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 13:21:48.369879 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 13:21:48.373550 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1209 13:21:48.376915 0 11 8 | B1->B0 | 3030 3c3c | 0 0 | (0 0) (1 1)
1210 13:21:48.383262 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1211 13:21:48.386437 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 13:21:48.389850 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 13:21:48.396974 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 13:21:48.399985 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 13:21:48.402947 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 13:21:48.409702 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 13:21:48.414169 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1218 13:21:48.415966 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 13:21:48.423140 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 13:21:48.426056 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 13:21:48.429977 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 13:21:48.435998 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 13:21:48.439370 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 13:21:48.442710 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 13:21:48.449385 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 13:21:48.452864 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 13:21:48.455359 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 13:21:48.462353 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 13:21:48.465463 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 13:21:48.468592 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 13:21:48.475558 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 13:21:48.478799 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 13:21:48.482166 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1234 13:21:48.489314 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 13:21:48.489914 Total UI for P1: 0, mck2ui 16
1236 13:21:48.493593 best dqsien dly found for B0: ( 0, 14, 8)
1237 13:21:48.495213 Total UI for P1: 0, mck2ui 16
1238 13:21:48.498958 best dqsien dly found for B1: ( 0, 14, 8)
1239 13:21:48.502190 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1240 13:21:48.508501 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1241 13:21:48.509315
1242 13:21:48.512030 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1243 13:21:48.516064 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1244 13:21:48.518477 [Gating] SW calibration Done
1245 13:21:48.519026 ==
1246 13:21:48.522646 Dram Type= 6, Freq= 0, CH_0, rank 1
1247 13:21:48.525160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1248 13:21:48.525643 ==
1249 13:21:48.526160 RX Vref Scan: 0
1250 13:21:48.528230
1251 13:21:48.528706 RX Vref 0 -> 0, step: 1
1252 13:21:48.529192
1253 13:21:48.532588 RX Delay -130 -> 252, step: 16
1254 13:21:48.535276 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1255 13:21:48.538857 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1256 13:21:48.545022 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1257 13:21:48.548460 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1258 13:21:48.552151 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1259 13:21:48.555315 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1260 13:21:48.562108 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1261 13:21:48.564826 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1262 13:21:48.567981 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1263 13:21:48.571295 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1264 13:21:48.574547 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1265 13:21:48.582127 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1266 13:21:48.584814 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1267 13:21:48.588431 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1268 13:21:48.591177 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1269 13:21:48.594707 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1270 13:21:48.597990 ==
1271 13:21:48.601675 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 13:21:48.605030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 13:21:48.605570 ==
1274 13:21:48.606024 DQS Delay:
1275 13:21:48.607922 DQS0 = 0, DQS1 = 0
1276 13:21:48.608354 DQM Delay:
1277 13:21:48.611794 DQM0 = 87, DQM1 = 78
1278 13:21:48.612225 DQ Delay:
1279 13:21:48.614782 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1280 13:21:48.618289 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1281 13:21:48.621286 DQ8 =69, DQ9 =61, DQ10 =85, DQ11 =69
1282 13:21:48.624706 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1283 13:21:48.625220
1284 13:21:48.625552
1285 13:21:48.625861 ==
1286 13:21:48.627820 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 13:21:48.631168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 13:21:48.631604 ==
1289 13:21:48.631940
1290 13:21:48.632245
1291 13:21:48.634367 TX Vref Scan disable
1292 13:21:48.638320 == TX Byte 0 ==
1293 13:21:48.640992 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1294 13:21:48.644308 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1295 13:21:48.647984 == TX Byte 1 ==
1296 13:21:48.651299 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1297 13:21:48.654471 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1298 13:21:48.655086 ==
1299 13:21:48.657468 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 13:21:48.664063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 13:21:48.664522 ==
1302 13:21:48.675409 TX Vref=22, minBit 9, minWin=27, winSum=444
1303 13:21:48.678744 TX Vref=24, minBit 12, minWin=27, winSum=446
1304 13:21:48.681837 TX Vref=26, minBit 9, minWin=27, winSum=446
1305 13:21:48.685665 TX Vref=28, minBit 9, minWin=27, winSum=447
1306 13:21:48.688729 TX Vref=30, minBit 9, minWin=27, winSum=447
1307 13:21:48.695335 TX Vref=32, minBit 9, minWin=27, winSum=445
1308 13:21:48.699178 [TxChooseVref] Worse bit 9, Min win 27, Win sum 447, Final Vref 28
1309 13:21:48.699639
1310 13:21:48.702921 Final TX Range 1 Vref 28
1311 13:21:48.703377
1312 13:21:48.703734 ==
1313 13:21:48.705650 Dram Type= 6, Freq= 0, CH_0, rank 1
1314 13:21:48.709221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1315 13:21:48.712117 ==
1316 13:21:48.712535
1317 13:21:48.712859
1318 13:21:48.713163 TX Vref Scan disable
1319 13:21:48.716039 == TX Byte 0 ==
1320 13:21:48.719896 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1321 13:21:48.725997 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1322 13:21:48.726527 == TX Byte 1 ==
1323 13:21:48.728941 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1324 13:21:48.735829 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1325 13:21:48.736380
1326 13:21:48.736743 [DATLAT]
1327 13:21:48.737078 Freq=800, CH0 RK1
1328 13:21:48.737403
1329 13:21:48.738685 DATLAT Default: 0xa
1330 13:21:48.739144 0, 0xFFFF, sum = 0
1331 13:21:48.742004 1, 0xFFFF, sum = 0
1332 13:21:48.745376 2, 0xFFFF, sum = 0
1333 13:21:48.745841 3, 0xFFFF, sum = 0
1334 13:21:48.749237 4, 0xFFFF, sum = 0
1335 13:21:48.749788 5, 0xFFFF, sum = 0
1336 13:21:48.752489 6, 0xFFFF, sum = 0
1337 13:21:48.753045 7, 0xFFFF, sum = 0
1338 13:21:48.755514 8, 0xFFFF, sum = 0
1339 13:21:48.756081 9, 0x0, sum = 1
1340 13:21:48.759273 10, 0x0, sum = 2
1341 13:21:48.759827 11, 0x0, sum = 3
1342 13:21:48.760207 12, 0x0, sum = 4
1343 13:21:48.762840 best_step = 10
1344 13:21:48.763389
1345 13:21:48.763753 ==
1346 13:21:48.765796 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 13:21:48.768474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 13:21:48.768933 ==
1349 13:21:48.772195 RX Vref Scan: 0
1350 13:21:48.772743
1351 13:21:48.773103 RX Vref 0 -> 0, step: 1
1352 13:21:48.775528
1353 13:21:48.775982 RX Delay -111 -> 252, step: 8
1354 13:21:48.782559 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1355 13:21:48.785846 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1356 13:21:48.789324 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1357 13:21:48.793016 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1358 13:21:48.795653 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1359 13:21:48.802860 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1360 13:21:48.806049 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1361 13:21:48.808963 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1362 13:21:48.812479 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1363 13:21:48.816108 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1364 13:21:48.822788 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1365 13:21:48.826192 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1366 13:21:48.830663 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1367 13:21:48.833618 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1368 13:21:48.838733 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1369 13:21:48.842045 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1370 13:21:48.842504 ==
1371 13:21:48.845372 Dram Type= 6, Freq= 0, CH_0, rank 1
1372 13:21:48.848535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1373 13:21:48.848998 ==
1374 13:21:48.852505 DQS Delay:
1375 13:21:48.853056 DQS0 = 0, DQS1 = 0
1376 13:21:48.853420 DQM Delay:
1377 13:21:48.855456 DQM0 = 86, DQM1 = 77
1378 13:21:48.855949 DQ Delay:
1379 13:21:48.858663 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =84
1380 13:21:48.862258 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1381 13:21:48.865403 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1382 13:21:48.868399 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1383 13:21:48.868859
1384 13:21:48.869219
1385 13:21:48.878786 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e04, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
1386 13:21:48.879337 CH0 RK1: MR19=606, MR18=3E04
1387 13:21:48.885207 CH0_RK1: MR19=0x606, MR18=0x3E04, DQSOSC=394, MR23=63, INC=95, DEC=63
1388 13:21:48.889038 [RxdqsGatingPostProcess] freq 800
1389 13:21:48.895262 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1390 13:21:48.898452 Pre-setting of DQS Precalculation
1391 13:21:48.901916 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1392 13:21:48.902496 ==
1393 13:21:48.905263 Dram Type= 6, Freq= 0, CH_1, rank 0
1394 13:21:48.911723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 13:21:48.912373 ==
1396 13:21:48.914980 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1397 13:21:48.921535 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1398 13:21:48.931376 [CA 0] Center 36 (6~67) winsize 62
1399 13:21:48.934569 [CA 1] Center 36 (6~67) winsize 62
1400 13:21:48.937682 [CA 2] Center 34 (4~65) winsize 62
1401 13:21:48.941066 [CA 3] Center 34 (3~65) winsize 63
1402 13:21:48.944432 [CA 4] Center 34 (4~65) winsize 62
1403 13:21:48.947420 [CA 5] Center 34 (3~65) winsize 63
1404 13:21:48.947915
1405 13:21:48.950973 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1406 13:21:48.951525
1407 13:21:48.954309 [CATrainingPosCal] consider 1 rank data
1408 13:21:48.957213 u2DelayCellTimex100 = 270/100 ps
1409 13:21:48.961067 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1410 13:21:48.965306 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1411 13:21:48.970681 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1412 13:21:48.974504 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1413 13:21:48.978119 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1414 13:21:48.980736 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1415 13:21:48.981300
1416 13:21:48.984700 CA PerBit enable=1, Macro0, CA PI delay=34
1417 13:21:48.985269
1418 13:21:48.987277 [CBTSetCACLKResult] CA Dly = 34
1419 13:21:48.987735 CS Dly: 4 (0~35)
1420 13:21:48.991675 ==
1421 13:21:48.992133 Dram Type= 6, Freq= 0, CH_1, rank 1
1422 13:21:48.997665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1423 13:21:48.998242 ==
1424 13:21:49.001245 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1425 13:21:49.007264 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1426 13:21:49.017132 [CA 0] Center 36 (6~67) winsize 62
1427 13:21:49.020390 [CA 1] Center 36 (6~67) winsize 62
1428 13:21:49.023272 [CA 2] Center 34 (3~65) winsize 63
1429 13:21:49.026664 [CA 3] Center 34 (3~65) winsize 63
1430 13:21:49.030015 [CA 4] Center 34 (4~65) winsize 62
1431 13:21:49.033990 [CA 5] Center 33 (3~64) winsize 62
1432 13:21:49.034548
1433 13:21:49.036795 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1434 13:21:49.037346
1435 13:21:49.039891 [CATrainingPosCal] consider 2 rank data
1436 13:21:49.043330 u2DelayCellTimex100 = 270/100 ps
1437 13:21:49.046482 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1438 13:21:49.053492 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1439 13:21:49.056404 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1440 13:21:49.060102 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1441 13:21:49.063182 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1442 13:21:49.066426 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1443 13:21:49.066944
1444 13:21:49.069921 CA PerBit enable=1, Macro0, CA PI delay=33
1445 13:21:49.070483
1446 13:21:49.073435 [CBTSetCACLKResult] CA Dly = 33
1447 13:21:49.076705 CS Dly: 5 (0~38)
1448 13:21:49.077262
1449 13:21:49.080253 ----->DramcWriteLeveling(PI) begin...
1450 13:21:49.080811 ==
1451 13:21:49.083197 Dram Type= 6, Freq= 0, CH_1, rank 0
1452 13:21:49.086829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1453 13:21:49.087377 ==
1454 13:21:49.089965 Write leveling (Byte 0): 28 => 28
1455 13:21:49.093422 Write leveling (Byte 1): 28 => 28
1456 13:21:49.096624 DramcWriteLeveling(PI) end<-----
1457 13:21:49.097177
1458 13:21:49.097541 ==
1459 13:21:49.100283 Dram Type= 6, Freq= 0, CH_1, rank 0
1460 13:21:49.102878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1461 13:21:49.103441 ==
1462 13:21:49.105889 [Gating] SW mode calibration
1463 13:21:49.112974 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1464 13:21:49.119367 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1465 13:21:49.122773 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1466 13:21:49.126257 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1467 13:21:49.132562 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 13:21:49.135838 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 13:21:49.139478 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 13:21:49.145597 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 13:21:49.148924 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 13:21:49.152756 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 13:21:49.159329 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 13:21:49.162843 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 13:21:49.165886 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 13:21:49.172416 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 13:21:49.176094 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 13:21:49.179184 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 13:21:49.185603 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 13:21:49.189111 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 13:21:49.192739 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 13:21:49.199132 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1483 13:21:49.202236 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 13:21:49.205931 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 13:21:49.213179 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 13:21:49.215714 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 13:21:49.219450 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 13:21:49.225341 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 13:21:49.228447 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 13:21:49.232080 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1491 13:21:49.238873 0 9 8 | B1->B0 | 2929 2e2e | 0 1 | (0 0) (1 1)
1492 13:21:49.242561 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 13:21:49.245283 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 13:21:49.248681 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 13:21:49.254836 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 13:21:49.258864 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 13:21:49.262011 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1498 13:21:49.268300 0 10 4 | B1->B0 | 3434 3232 | 0 0 | (0 1) (0 0)
1499 13:21:49.271823 0 10 8 | B1->B0 | 2e2e 2c2c | 0 0 | (0 0) (0 0)
1500 13:21:49.274834 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 13:21:49.281995 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 13:21:49.285271 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 13:21:49.288127 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 13:21:49.295350 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 13:21:49.298107 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 13:21:49.301520 0 11 4 | B1->B0 | 2626 2727 | 0 0 | (0 0) (1 1)
1507 13:21:49.308065 0 11 8 | B1->B0 | 3b3a 3a3a | 1 0 | (0 0) (0 0)
1508 13:21:49.311369 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 13:21:49.315047 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 13:21:49.321420 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 13:21:49.324643 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 13:21:49.327888 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 13:21:49.335001 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 13:21:49.338077 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1515 13:21:49.341912 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 13:21:49.347727 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 13:21:49.351263 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 13:21:49.354416 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 13:21:49.361128 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 13:21:49.364464 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 13:21:49.367872 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 13:21:49.374704 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 13:21:49.377787 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 13:21:49.381103 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 13:21:49.387621 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 13:21:49.390968 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 13:21:49.394144 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 13:21:49.400437 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 13:21:49.404411 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 13:21:49.407678 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1531 13:21:49.410328 Total UI for P1: 0, mck2ui 16
1532 13:21:49.414057 best dqsien dly found for B0: ( 0, 14, 2)
1533 13:21:49.421014 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 13:21:49.421570 Total UI for P1: 0, mck2ui 16
1535 13:21:49.427221 best dqsien dly found for B1: ( 0, 14, 4)
1536 13:21:49.430424 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1537 13:21:49.434229 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1538 13:21:49.434824
1539 13:21:49.437299 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1540 13:21:49.441465 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1541 13:21:49.444151 [Gating] SW calibration Done
1542 13:21:49.444707 ==
1543 13:21:49.447271 Dram Type= 6, Freq= 0, CH_1, rank 0
1544 13:21:49.450451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1545 13:21:49.451055 ==
1546 13:21:49.453926 RX Vref Scan: 0
1547 13:21:49.454475
1548 13:21:49.454884 RX Vref 0 -> 0, step: 1
1549 13:21:49.455225
1550 13:21:49.457146 RX Delay -130 -> 252, step: 16
1551 13:21:49.460256 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1552 13:21:49.467237 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1553 13:21:49.470713 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1554 13:21:49.473445 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1555 13:21:49.477352 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1556 13:21:49.480535 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1557 13:21:49.486954 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1558 13:21:49.489830 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1559 13:21:49.493870 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1560 13:21:49.496764 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1561 13:21:49.503170 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1562 13:21:49.507142 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1563 13:21:49.510123 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1564 13:21:49.513159 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1565 13:21:49.516434 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1566 13:21:49.523261 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1567 13:21:49.523816 ==
1568 13:21:49.526222 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 13:21:49.529602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 13:21:49.530154 ==
1571 13:21:49.530519 DQS Delay:
1572 13:21:49.533040 DQS0 = 0, DQS1 = 0
1573 13:21:49.533591 DQM Delay:
1574 13:21:49.536267 DQM0 = 89, DQM1 = 78
1575 13:21:49.536725 DQ Delay:
1576 13:21:49.539639 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1577 13:21:49.542876 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1578 13:21:49.546558 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1579 13:21:49.549738 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1580 13:21:49.550229
1581 13:21:49.550623
1582 13:21:49.550970 ==
1583 13:21:49.553230 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 13:21:49.556301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 13:21:49.559522 ==
1586 13:21:49.560075
1587 13:21:49.560437
1588 13:21:49.560775 TX Vref Scan disable
1589 13:21:49.563384 == TX Byte 0 ==
1590 13:21:49.566111 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1591 13:21:49.569329 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1592 13:21:49.572748 == TX Byte 1 ==
1593 13:21:49.576119 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1594 13:21:49.580009 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1595 13:21:49.582869 ==
1596 13:21:49.586041 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 13:21:49.589843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 13:21:49.590396 ==
1599 13:21:49.602094 TX Vref=22, minBit 15, minWin=26, winSum=445
1600 13:21:49.605078 TX Vref=24, minBit 8, minWin=27, winSum=448
1601 13:21:49.608161 TX Vref=26, minBit 8, minWin=27, winSum=449
1602 13:21:49.611585 TX Vref=28, minBit 0, minWin=28, winSum=451
1603 13:21:49.614650 TX Vref=30, minBit 9, minWin=27, winSum=452
1604 13:21:49.621478 TX Vref=32, minBit 8, minWin=27, winSum=447
1605 13:21:49.625805 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 28
1606 13:21:49.626360
1607 13:21:49.627809 Final TX Range 1 Vref 28
1608 13:21:49.628265
1609 13:21:49.628627 ==
1610 13:21:49.631170 Dram Type= 6, Freq= 0, CH_1, rank 0
1611 13:21:49.635016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1612 13:21:49.637883 ==
1613 13:21:49.638430
1614 13:21:49.638856
1615 13:21:49.639201 TX Vref Scan disable
1616 13:21:49.641381 == TX Byte 0 ==
1617 13:21:49.644949 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1618 13:21:49.651833 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1619 13:21:49.652408 == TX Byte 1 ==
1620 13:21:49.654573 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1621 13:21:49.661705 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1622 13:21:49.662272
1623 13:21:49.662693 [DATLAT]
1624 13:21:49.663053 Freq=800, CH1 RK0
1625 13:21:49.663384
1626 13:21:49.664705 DATLAT Default: 0xa
1627 13:21:49.665161 0, 0xFFFF, sum = 0
1628 13:21:49.668293 1, 0xFFFF, sum = 0
1629 13:21:49.668868 2, 0xFFFF, sum = 0
1630 13:21:49.671526 3, 0xFFFF, sum = 0
1631 13:21:49.672188 4, 0xFFFF, sum = 0
1632 13:21:49.674853 5, 0xFFFF, sum = 0
1633 13:21:49.678456 6, 0xFFFF, sum = 0
1634 13:21:49.679080 7, 0xFFFF, sum = 0
1635 13:21:49.681484 8, 0xFFFF, sum = 0
1636 13:21:49.682053 9, 0x0, sum = 1
1637 13:21:49.682428 10, 0x0, sum = 2
1638 13:21:49.684967 11, 0x0, sum = 3
1639 13:21:49.685535 12, 0x0, sum = 4
1640 13:21:49.688532 best_step = 10
1641 13:21:49.689094
1642 13:21:49.689462 ==
1643 13:21:49.691225 Dram Type= 6, Freq= 0, CH_1, rank 0
1644 13:21:49.694861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1645 13:21:49.695431 ==
1646 13:21:49.698106 RX Vref Scan: 1
1647 13:21:49.698707
1648 13:21:49.699082 Set Vref Range= 32 -> 127
1649 13:21:49.701965
1650 13:21:49.702543 RX Vref 32 -> 127, step: 1
1651 13:21:49.702975
1652 13:21:49.704817 RX Delay -95 -> 252, step: 8
1653 13:21:49.705377
1654 13:21:49.708054 Set Vref, RX VrefLevel [Byte0]: 32
1655 13:21:49.711242 [Byte1]: 32
1656 13:21:49.711807
1657 13:21:49.714539 Set Vref, RX VrefLevel [Byte0]: 33
1658 13:21:49.718481 [Byte1]: 33
1659 13:21:49.721674
1660 13:21:49.725049 Set Vref, RX VrefLevel [Byte0]: 34
1661 13:21:49.728550 [Byte1]: 34
1662 13:21:49.729118
1663 13:21:49.731463 Set Vref, RX VrefLevel [Byte0]: 35
1664 13:21:49.736514 [Byte1]: 35
1665 13:21:49.737086
1666 13:21:49.737994 Set Vref, RX VrefLevel [Byte0]: 36
1667 13:21:49.742405 [Byte1]: 36
1668 13:21:49.745216
1669 13:21:49.745764 Set Vref, RX VrefLevel [Byte0]: 37
1670 13:21:49.748642 [Byte1]: 37
1671 13:21:49.752177
1672 13:21:49.752723 Set Vref, RX VrefLevel [Byte0]: 38
1673 13:21:49.755709 [Byte1]: 38
1674 13:21:49.759790
1675 13:21:49.760343 Set Vref, RX VrefLevel [Byte0]: 39
1676 13:21:49.762796 [Byte1]: 39
1677 13:21:49.767197
1678 13:21:49.767649 Set Vref, RX VrefLevel [Byte0]: 40
1679 13:21:49.771041 [Byte1]: 40
1680 13:21:49.774941
1681 13:21:49.775401 Set Vref, RX VrefLevel [Byte0]: 41
1682 13:21:49.778779 [Byte1]: 41
1683 13:21:49.782537
1684 13:21:49.783147 Set Vref, RX VrefLevel [Byte0]: 42
1685 13:21:49.785847 [Byte1]: 42
1686 13:21:49.790266
1687 13:21:49.790880 Set Vref, RX VrefLevel [Byte0]: 43
1688 13:21:49.793541 [Byte1]: 43
1689 13:21:49.797730
1690 13:21:49.798291 Set Vref, RX VrefLevel [Byte0]: 44
1691 13:21:49.801210 [Byte1]: 44
1692 13:21:49.805951
1693 13:21:49.806509 Set Vref, RX VrefLevel [Byte0]: 45
1694 13:21:49.809256 [Byte1]: 45
1695 13:21:49.813713
1696 13:21:49.814276 Set Vref, RX VrefLevel [Byte0]: 46
1697 13:21:49.816419 [Byte1]: 46
1698 13:21:49.820643
1699 13:21:49.823752 Set Vref, RX VrefLevel [Byte0]: 47
1700 13:21:49.824319 [Byte1]: 47
1701 13:21:49.828217
1702 13:21:49.828782 Set Vref, RX VrefLevel [Byte0]: 48
1703 13:21:49.831312 [Byte1]: 48
1704 13:21:49.836042
1705 13:21:49.836604 Set Vref, RX VrefLevel [Byte0]: 49
1706 13:21:49.839058 [Byte1]: 49
1707 13:21:49.843529
1708 13:21:49.843986 Set Vref, RX VrefLevel [Byte0]: 50
1709 13:21:49.846940 [Byte1]: 50
1710 13:21:49.850585
1711 13:21:49.851101 Set Vref, RX VrefLevel [Byte0]: 51
1712 13:21:49.857612 [Byte1]: 51
1713 13:21:49.858164
1714 13:21:49.860580 Set Vref, RX VrefLevel [Byte0]: 52
1715 13:21:49.864446 [Byte1]: 52
1716 13:21:49.865017
1717 13:21:49.867340 Set Vref, RX VrefLevel [Byte0]: 53
1718 13:21:49.870692 [Byte1]: 53
1719 13:21:49.871258
1720 13:21:49.874286 Set Vref, RX VrefLevel [Byte0]: 54
1721 13:21:49.877556 [Byte1]: 54
1722 13:21:49.881432
1723 13:21:49.881982 Set Vref, RX VrefLevel [Byte0]: 55
1724 13:21:49.884520 [Byte1]: 55
1725 13:21:49.888832
1726 13:21:49.889293 Set Vref, RX VrefLevel [Byte0]: 56
1727 13:21:49.892400 [Byte1]: 56
1728 13:21:49.896624
1729 13:21:49.897171 Set Vref, RX VrefLevel [Byte0]: 57
1730 13:21:49.899827 [Byte1]: 57
1731 13:21:49.904507
1732 13:21:49.905054 Set Vref, RX VrefLevel [Byte0]: 58
1733 13:21:49.907825 [Byte1]: 58
1734 13:21:49.911894
1735 13:21:49.912438 Set Vref, RX VrefLevel [Byte0]: 59
1736 13:21:49.914873 [Byte1]: 59
1737 13:21:49.919828
1738 13:21:49.920300 Set Vref, RX VrefLevel [Byte0]: 60
1739 13:21:49.923037 [Byte1]: 60
1740 13:21:49.926936
1741 13:21:49.927478 Set Vref, RX VrefLevel [Byte0]: 61
1742 13:21:49.930329 [Byte1]: 61
1743 13:21:49.935248
1744 13:21:49.935708 Set Vref, RX VrefLevel [Byte0]: 62
1745 13:21:49.937721 [Byte1]: 62
1746 13:21:49.942014
1747 13:21:49.942473 Set Vref, RX VrefLevel [Byte0]: 63
1748 13:21:49.945301 [Byte1]: 63
1749 13:21:49.949608
1750 13:21:49.950160 Set Vref, RX VrefLevel [Byte0]: 64
1751 13:21:49.956182 [Byte1]: 64
1752 13:21:49.956741
1753 13:21:49.960007 Set Vref, RX VrefLevel [Byte0]: 65
1754 13:21:49.963173 [Byte1]: 65
1755 13:21:49.963637
1756 13:21:49.966116 Set Vref, RX VrefLevel [Byte0]: 66
1757 13:21:49.969641 [Byte1]: 66
1758 13:21:49.970201
1759 13:21:49.972407 Set Vref, RX VrefLevel [Byte0]: 67
1760 13:21:49.976254 [Byte1]: 67
1761 13:21:49.979943
1762 13:21:49.980488 Set Vref, RX VrefLevel [Byte0]: 68
1763 13:21:49.983073 [Byte1]: 68
1764 13:21:49.988083
1765 13:21:49.988663 Set Vref, RX VrefLevel [Byte0]: 69
1766 13:21:49.990888 [Byte1]: 69
1767 13:21:49.995284
1768 13:21:49.995829 Set Vref, RX VrefLevel [Byte0]: 70
1769 13:21:49.998626 [Byte1]: 70
1770 13:21:50.002898
1771 13:21:50.003442 Set Vref, RX VrefLevel [Byte0]: 71
1772 13:21:50.006746 [Byte1]: 71
1773 13:21:50.010695
1774 13:21:50.011256 Set Vref, RX VrefLevel [Byte0]: 72
1775 13:21:50.013738 [Byte1]: 72
1776 13:21:50.018242
1777 13:21:50.018749 Final RX Vref Byte 0 = 57 to rank0
1778 13:21:50.021560 Final RX Vref Byte 1 = 64 to rank0
1779 13:21:50.024882 Final RX Vref Byte 0 = 57 to rank1
1780 13:21:50.027672 Final RX Vref Byte 1 = 64 to rank1==
1781 13:21:50.031507 Dram Type= 6, Freq= 0, CH_1, rank 0
1782 13:21:50.038222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1783 13:21:50.038828 ==
1784 13:21:50.039207 DQS Delay:
1785 13:21:50.039553 DQS0 = 0, DQS1 = 0
1786 13:21:50.041117 DQM Delay:
1787 13:21:50.041614 DQM0 = 86, DQM1 = 79
1788 13:21:50.044625 DQ Delay:
1789 13:21:50.048025 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1790 13:21:50.051258 DQ4 =80, DQ5 =100, DQ6 =100, DQ7 =80
1791 13:21:50.054509 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1792 13:21:50.057978 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1793 13:21:50.058531
1794 13:21:50.058967
1795 13:21:50.064779 [DQSOSCAuto] RK0, (LSB)MR18= 0x301c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1796 13:21:50.067653 CH1 RK0: MR19=606, MR18=301C
1797 13:21:50.074407 CH1_RK0: MR19=0x606, MR18=0x301C, DQSOSC=397, MR23=63, INC=93, DEC=62
1798 13:21:50.075017
1799 13:21:50.078148 ----->DramcWriteLeveling(PI) begin...
1800 13:21:50.078759 ==
1801 13:21:50.081366 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 13:21:50.084455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 13:21:50.085006 ==
1804 13:21:50.088617 Write leveling (Byte 0): 26 => 26
1805 13:21:50.091151 Write leveling (Byte 1): 31 => 31
1806 13:21:50.094619 DramcWriteLeveling(PI) end<-----
1807 13:21:50.095191
1808 13:21:50.095556 ==
1809 13:21:50.098127 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 13:21:50.101257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 13:21:50.101723 ==
1812 13:21:50.104528 [Gating] SW mode calibration
1813 13:21:50.111207 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1814 13:21:50.117384 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1815 13:21:50.121016 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1816 13:21:50.127750 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1817 13:21:50.130943 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1818 13:21:50.134497 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 13:21:50.141399 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 13:21:50.144370 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 13:21:50.148508 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 13:21:50.150377 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 13:21:50.158410 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 13:21:50.160511 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 13:21:50.164264 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 13:21:50.170548 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 13:21:50.174257 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 13:21:50.177643 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 13:21:50.184288 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 13:21:50.187484 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 13:21:50.190893 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1832 13:21:50.197487 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1833 13:21:50.200888 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 13:21:50.203973 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 13:21:50.210690 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 13:21:50.213800 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 13:21:50.216938 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 13:21:50.223397 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 13:21:50.227312 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 13:21:50.230001 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 13:21:50.237188 0 9 8 | B1->B0 | 3333 2827 | 0 1 | (0 0) (0 0)
1842 13:21:50.240607 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 13:21:50.243201 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 13:21:50.249905 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 13:21:50.253437 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 13:21:50.256672 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 13:21:50.264025 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 13:21:50.266347 0 10 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 0)
1849 13:21:50.269718 0 10 8 | B1->B0 | 2323 2e2e | 0 1 | (1 0) (1 0)
1850 13:21:50.276606 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 13:21:50.280691 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 13:21:50.282930 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 13:21:50.289935 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 13:21:50.293237 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 13:21:50.297117 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 13:21:50.303213 0 11 4 | B1->B0 | 2f2f 2323 | 1 1 | (0 0) (0 0)
1857 13:21:50.306381 0 11 8 | B1->B0 | 3e3e 3838 | 0 0 | (1 1) (1 1)
1858 13:21:50.309395 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 13:21:50.316157 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 13:21:50.319295 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 13:21:50.323427 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 13:21:50.329469 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 13:21:50.332834 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 13:21:50.336063 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1865 13:21:50.342869 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1866 13:21:50.346175 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 13:21:50.348920 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 13:21:50.356362 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 13:21:50.359524 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 13:21:50.362836 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 13:21:50.369097 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 13:21:50.372530 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 13:21:50.376315 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 13:21:50.382545 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 13:21:50.385766 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 13:21:50.389303 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 13:21:50.395537 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 13:21:50.399298 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 13:21:50.402244 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 13:21:50.409472 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1881 13:21:50.412409 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 13:21:50.415749 Total UI for P1: 0, mck2ui 16
1883 13:21:50.419171 best dqsien dly found for B0: ( 0, 14, 4)
1884 13:21:50.421867 Total UI for P1: 0, mck2ui 16
1885 13:21:50.425368 best dqsien dly found for B1: ( 0, 14, 4)
1886 13:21:50.429066 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1887 13:21:50.431913 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1888 13:21:50.432380
1889 13:21:50.435330 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1890 13:21:50.438860 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1891 13:21:50.442163 [Gating] SW calibration Done
1892 13:21:50.442802 ==
1893 13:21:50.446111 Dram Type= 6, Freq= 0, CH_1, rank 1
1894 13:21:50.448393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1895 13:21:50.448858 ==
1896 13:21:50.451983 RX Vref Scan: 0
1897 13:21:50.452468
1898 13:21:50.452882 RX Vref 0 -> 0, step: 1
1899 13:21:50.454950
1900 13:21:50.455406 RX Delay -130 -> 252, step: 16
1901 13:21:50.462029 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1902 13:21:50.465366 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1903 13:21:50.468357 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1904 13:21:50.471856 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1905 13:21:50.475053 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1906 13:21:50.481750 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1907 13:21:50.485620 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1908 13:21:50.488295 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1909 13:21:50.491612 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1910 13:21:50.495181 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1911 13:21:50.501486 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1912 13:21:50.504864 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1913 13:21:50.507812 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1914 13:21:50.511061 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1915 13:21:50.517701 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1916 13:21:50.521572 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1917 13:21:50.521992 ==
1918 13:21:50.524658 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 13:21:50.529138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 13:21:50.529669 ==
1921 13:21:50.531334 DQS Delay:
1922 13:21:50.531757 DQS0 = 0, DQS1 = 0
1923 13:21:50.532091 DQM Delay:
1924 13:21:50.534251 DQM0 = 87, DQM1 = 79
1925 13:21:50.534717 DQ Delay:
1926 13:21:50.538530 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1927 13:21:50.541154 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1928 13:21:50.544643 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1929 13:21:50.547996 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1930 13:21:50.548529
1931 13:21:50.548865
1932 13:21:50.549174 ==
1933 13:21:50.550913 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 13:21:50.557668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 13:21:50.558203 ==
1936 13:21:50.558546
1937 13:21:50.558918
1938 13:21:50.559219 TX Vref Scan disable
1939 13:21:50.561272 == TX Byte 0 ==
1940 13:21:50.564799 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1941 13:21:50.571110 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1942 13:21:50.571531 == TX Byte 1 ==
1943 13:21:50.574346 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1944 13:21:50.581505 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1945 13:21:50.582030 ==
1946 13:21:50.585509 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 13:21:50.587883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 13:21:50.588408 ==
1949 13:21:50.601046 TX Vref=22, minBit 8, minWin=26, winSum=442
1950 13:21:50.604015 TX Vref=24, minBit 8, minWin=27, winSum=448
1951 13:21:50.607792 TX Vref=26, minBit 9, minWin=26, winSum=448
1952 13:21:50.610732 TX Vref=28, minBit 8, minWin=27, winSum=450
1953 13:21:50.613869 TX Vref=30, minBit 8, minWin=27, winSum=448
1954 13:21:50.620532 TX Vref=32, minBit 8, minWin=27, winSum=450
1955 13:21:50.624367 [TxChooseVref] Worse bit 8, Min win 27, Win sum 450, Final Vref 28
1956 13:21:50.624795
1957 13:21:50.627144 Final TX Range 1 Vref 28
1958 13:21:50.627670
1959 13:21:50.628010 ==
1960 13:21:50.630433 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 13:21:50.633659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 13:21:50.637400 ==
1963 13:21:50.637923
1964 13:21:50.638259
1965 13:21:50.638570 TX Vref Scan disable
1966 13:21:50.641626 == TX Byte 0 ==
1967 13:21:50.644152 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1968 13:21:50.647329 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1969 13:21:50.650832 == TX Byte 1 ==
1970 13:21:50.653875 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1971 13:21:50.660700 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1972 13:21:50.661250
1973 13:21:50.661591 [DATLAT]
1974 13:21:50.661903 Freq=800, CH1 RK1
1975 13:21:50.662202
1976 13:21:50.663917 DATLAT Default: 0xa
1977 13:21:50.664336 0, 0xFFFF, sum = 0
1978 13:21:50.667565 1, 0xFFFF, sum = 0
1979 13:21:50.668099 2, 0xFFFF, sum = 0
1980 13:21:50.671093 3, 0xFFFF, sum = 0
1981 13:21:50.671522 4, 0xFFFF, sum = 0
1982 13:21:50.673779 5, 0xFFFF, sum = 0
1983 13:21:50.677905 6, 0xFFFF, sum = 0
1984 13:21:50.678446 7, 0xFFFF, sum = 0
1985 13:21:50.680833 8, 0xFFFF, sum = 0
1986 13:21:50.681365 9, 0x0, sum = 1
1987 13:21:50.683411 10, 0x0, sum = 2
1988 13:21:50.683843 11, 0x0, sum = 3
1989 13:21:50.684185 12, 0x0, sum = 4
1990 13:21:50.687162 best_step = 10
1991 13:21:50.687580
1992 13:21:50.687911 ==
1993 13:21:50.690398 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 13:21:50.693864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 13:21:50.694393 ==
1996 13:21:50.696994 RX Vref Scan: 0
1997 13:21:50.697410
1998 13:21:50.697737 RX Vref 0 -> 0, step: 1
1999 13:21:50.700452
2000 13:21:50.700870 RX Delay -95 -> 252, step: 8
2001 13:21:50.707288 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2002 13:21:50.710699 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2003 13:21:50.714489 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2004 13:21:50.717189 iDelay=217, Bit 3, Center 88 (-23 ~ 200) 224
2005 13:21:50.721170 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2006 13:21:50.727251 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2007 13:21:50.730480 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2008 13:21:50.734250 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2009 13:21:50.736981 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2010 13:21:50.744078 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2011 13:21:50.747474 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2012 13:21:50.750249 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2013 13:21:50.753802 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2014 13:21:50.757300 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2015 13:21:50.764141 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2016 13:21:50.767061 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2017 13:21:50.767586 ==
2018 13:21:50.770373 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 13:21:50.773623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 13:21:50.774145 ==
2021 13:21:50.777031 DQS Delay:
2022 13:21:50.777542 DQS0 = 0, DQS1 = 0
2023 13:21:50.777878 DQM Delay:
2024 13:21:50.780433 DQM0 = 87, DQM1 = 78
2025 13:21:50.780991 DQ Delay:
2026 13:21:50.783145 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =88
2027 13:21:50.786667 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2028 13:21:50.789847 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =68
2029 13:21:50.793519 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2030 13:21:50.794079
2031 13:21:50.794447
2032 13:21:50.803327 [DQSOSCAuto] RK1, (LSB)MR18= 0x1812, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2033 13:21:50.806516 CH1 RK1: MR19=606, MR18=1812
2034 13:21:50.810179 CH1_RK1: MR19=0x606, MR18=0x1812, DQSOSC=403, MR23=63, INC=90, DEC=60
2035 13:21:50.812968 [RxdqsGatingPostProcess] freq 800
2036 13:21:50.820172 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2037 13:21:50.823250 Pre-setting of DQS Precalculation
2038 13:21:50.826351 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2039 13:21:50.836834 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2040 13:21:50.842677 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2041 13:21:50.843234
2042 13:21:50.843602
2043 13:21:50.846212 [Calibration Summary] 1600 Mbps
2044 13:21:50.846727 CH 0, Rank 0
2045 13:21:50.849766 SW Impedance : PASS
2046 13:21:50.850343 DUTY Scan : NO K
2047 13:21:50.852862 ZQ Calibration : PASS
2048 13:21:50.856110 Jitter Meter : NO K
2049 13:21:50.856663 CBT Training : PASS
2050 13:21:50.859578 Write leveling : PASS
2051 13:21:50.863326 RX DQS gating : PASS
2052 13:21:50.863881 RX DQ/DQS(RDDQC) : PASS
2053 13:21:50.865927 TX DQ/DQS : PASS
2054 13:21:50.869380 RX DATLAT : PASS
2055 13:21:50.869841 RX DQ/DQS(Engine): PASS
2056 13:21:50.873124 TX OE : NO K
2057 13:21:50.873722 All Pass.
2058 13:21:50.874093
2059 13:21:50.876590 CH 0, Rank 1
2060 13:21:50.877146 SW Impedance : PASS
2061 13:21:50.879193 DUTY Scan : NO K
2062 13:21:50.883148 ZQ Calibration : PASS
2063 13:21:50.883609 Jitter Meter : NO K
2064 13:21:50.886178 CBT Training : PASS
2065 13:21:50.888988 Write leveling : PASS
2066 13:21:50.889451 RX DQS gating : PASS
2067 13:21:50.892300 RX DQ/DQS(RDDQC) : PASS
2068 13:21:50.896443 TX DQ/DQS : PASS
2069 13:21:50.897004 RX DATLAT : PASS
2070 13:21:50.898853 RX DQ/DQS(Engine): PASS
2071 13:21:50.899318 TX OE : NO K
2072 13:21:50.902479 All Pass.
2073 13:21:50.903087
2074 13:21:50.903459 CH 1, Rank 0
2075 13:21:50.905698 SW Impedance : PASS
2076 13:21:50.906249 DUTY Scan : NO K
2077 13:21:50.909124 ZQ Calibration : PASS
2078 13:21:50.912275 Jitter Meter : NO K
2079 13:21:50.912832 CBT Training : PASS
2080 13:21:50.915547 Write leveling : PASS
2081 13:21:50.918897 RX DQS gating : PASS
2082 13:21:50.919367 RX DQ/DQS(RDDQC) : PASS
2083 13:21:50.922173 TX DQ/DQS : PASS
2084 13:21:50.925370 RX DATLAT : PASS
2085 13:21:50.925923 RX DQ/DQS(Engine): PASS
2086 13:21:50.929057 TX OE : NO K
2087 13:21:50.929612 All Pass.
2088 13:21:50.929982
2089 13:21:50.932190 CH 1, Rank 1
2090 13:21:50.932667 SW Impedance : PASS
2091 13:21:50.935270 DUTY Scan : NO K
2092 13:21:50.938886 ZQ Calibration : PASS
2093 13:21:50.939524 Jitter Meter : NO K
2094 13:21:50.941772 CBT Training : PASS
2095 13:21:50.945171 Write leveling : PASS
2096 13:21:50.945673 RX DQS gating : PASS
2097 13:21:50.948593 RX DQ/DQS(RDDQC) : PASS
2098 13:21:50.952119 TX DQ/DQS : PASS
2099 13:21:50.952585 RX DATLAT : PASS
2100 13:21:50.955237 RX DQ/DQS(Engine): PASS
2101 13:21:50.958563 TX OE : NO K
2102 13:21:50.959166 All Pass.
2103 13:21:50.959536
2104 13:21:50.959878 DramC Write-DBI off
2105 13:21:50.961636 PER_BANK_REFRESH: Hybrid Mode
2106 13:21:50.965132 TX_TRACKING: ON
2107 13:21:50.968638 [GetDramInforAfterCalByMRR] Vendor 6.
2108 13:21:50.972065 [GetDramInforAfterCalByMRR] Revision 606.
2109 13:21:50.975048 [GetDramInforAfterCalByMRR] Revision 2 0.
2110 13:21:50.975508 MR0 0x3b3b
2111 13:21:50.978667 MR8 0x5151
2112 13:21:50.981597 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2113 13:21:50.982062
2114 13:21:50.982429 MR0 0x3b3b
2115 13:21:50.982834 MR8 0x5151
2116 13:21:50.985127 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2117 13:21:50.985699
2118 13:21:50.995175 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2119 13:21:50.998817 [FAST_K] Save calibration result to emmc
2120 13:21:51.002079 [FAST_K] Save calibration result to emmc
2121 13:21:51.005831 dram_init: config_dvfs: 1
2122 13:21:51.008741 dramc_set_vcore_voltage set vcore to 662500
2123 13:21:51.011365 Read voltage for 1200, 2
2124 13:21:51.011828 Vio18 = 0
2125 13:21:51.015497 Vcore = 662500
2126 13:21:51.016052 Vdram = 0
2127 13:21:51.016424 Vddq = 0
2128 13:21:51.016763 Vmddr = 0
2129 13:21:51.021202 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2130 13:21:51.028481 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2131 13:21:51.029043 MEM_TYPE=3, freq_sel=15
2132 13:21:51.031360 sv_algorithm_assistance_LP4_1600
2133 13:21:51.035606 ============ PULL DRAM RESETB DOWN ============
2134 13:21:51.041712 ========== PULL DRAM RESETB DOWN end =========
2135 13:21:51.044590 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2136 13:21:51.048376 ===================================
2137 13:21:51.051464 LPDDR4 DRAM CONFIGURATION
2138 13:21:51.054968 ===================================
2139 13:21:51.055500 EX_ROW_EN[0] = 0x0
2140 13:21:51.058281 EX_ROW_EN[1] = 0x0
2141 13:21:51.058863 LP4Y_EN = 0x0
2142 13:21:51.061576 WORK_FSP = 0x0
2143 13:21:51.062089 WL = 0x4
2144 13:21:51.064884 RL = 0x4
2145 13:21:51.068056 BL = 0x2
2146 13:21:51.068475 RPST = 0x0
2147 13:21:51.071034 RD_PRE = 0x0
2148 13:21:51.071450 WR_PRE = 0x1
2149 13:21:51.074248 WR_PST = 0x0
2150 13:21:51.074697 DBI_WR = 0x0
2151 13:21:51.077857 DBI_RD = 0x0
2152 13:21:51.078275 OTF = 0x1
2153 13:21:51.080809 ===================================
2154 13:21:51.084781 ===================================
2155 13:21:51.087819 ANA top config
2156 13:21:51.091251 ===================================
2157 13:21:51.091670 DLL_ASYNC_EN = 0
2158 13:21:51.093970 ALL_SLAVE_EN = 0
2159 13:21:51.097403 NEW_RANK_MODE = 1
2160 13:21:51.101235 DLL_IDLE_MODE = 1
2161 13:21:51.101748 LP45_APHY_COMB_EN = 1
2162 13:21:51.104469 TX_ODT_DIS = 1
2163 13:21:51.108016 NEW_8X_MODE = 1
2164 13:21:51.110967 ===================================
2165 13:21:51.115097 ===================================
2166 13:21:51.117381 data_rate = 2400
2167 13:21:51.120887 CKR = 1
2168 13:21:51.124534 DQ_P2S_RATIO = 8
2169 13:21:51.127917 ===================================
2170 13:21:51.128444 CA_P2S_RATIO = 8
2171 13:21:51.131588 DQ_CA_OPEN = 0
2172 13:21:51.134775 DQ_SEMI_OPEN = 0
2173 13:21:51.137831 CA_SEMI_OPEN = 0
2174 13:21:51.140624 CA_FULL_RATE = 0
2175 13:21:51.143934 DQ_CKDIV4_EN = 0
2176 13:21:51.144413 CA_CKDIV4_EN = 0
2177 13:21:51.147355 CA_PREDIV_EN = 0
2178 13:21:51.151074 PH8_DLY = 17
2179 13:21:51.153820 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2180 13:21:51.157181 DQ_AAMCK_DIV = 4
2181 13:21:51.160450 CA_AAMCK_DIV = 4
2182 13:21:51.161031 CA_ADMCK_DIV = 4
2183 13:21:51.164361 DQ_TRACK_CA_EN = 0
2184 13:21:51.166968 CA_PICK = 1200
2185 13:21:51.170289 CA_MCKIO = 1200
2186 13:21:51.174199 MCKIO_SEMI = 0
2187 13:21:51.177521 PLL_FREQ = 2366
2188 13:21:51.180415 DQ_UI_PI_RATIO = 32
2189 13:21:51.181003 CA_UI_PI_RATIO = 0
2190 13:21:51.184019 ===================================
2191 13:21:51.187353 ===================================
2192 13:21:51.190374 memory_type:LPDDR4
2193 13:21:51.193902 GP_NUM : 10
2194 13:21:51.194488 SRAM_EN : 1
2195 13:21:51.197185 MD32_EN : 0
2196 13:21:51.200684 ===================================
2197 13:21:51.203939 [ANA_INIT] >>>>>>>>>>>>>>
2198 13:21:51.207093 <<<<<< [CONFIGURE PHASE]: ANA_TX
2199 13:21:51.210324 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2200 13:21:51.213740 ===================================
2201 13:21:51.214282 data_rate = 2400,PCW = 0X5b00
2202 13:21:51.216952 ===================================
2203 13:21:51.220727 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2204 13:21:51.227098 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 13:21:51.233473 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2206 13:21:51.237285 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2207 13:21:51.240718 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2208 13:21:51.244302 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2209 13:21:51.247058 [ANA_INIT] flow start
2210 13:21:51.250840 [ANA_INIT] PLL >>>>>>>>
2211 13:21:51.251386 [ANA_INIT] PLL <<<<<<<<
2212 13:21:51.253742 [ANA_INIT] MIDPI >>>>>>>>
2213 13:21:51.256690 [ANA_INIT] MIDPI <<<<<<<<
2214 13:21:51.257126 [ANA_INIT] DLL >>>>>>>>
2215 13:21:51.260800 [ANA_INIT] DLL <<<<<<<<
2216 13:21:51.264188 [ANA_INIT] flow end
2217 13:21:51.267498 ============ LP4 DIFF to SE enter ============
2218 13:21:51.270731 ============ LP4 DIFF to SE exit ============
2219 13:21:51.273807 [ANA_INIT] <<<<<<<<<<<<<
2220 13:21:51.277352 [Flow] Enable top DCM control >>>>>
2221 13:21:51.280744 [Flow] Enable top DCM control <<<<<
2222 13:21:51.283668 Enable DLL master slave shuffle
2223 13:21:51.286538 ==============================================================
2224 13:21:51.291057 Gating Mode config
2225 13:21:51.297337 ==============================================================
2226 13:21:51.297866 Config description:
2227 13:21:51.307285 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2228 13:21:51.313536 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2229 13:21:51.316899 SELPH_MODE 0: By rank 1: By Phase
2230 13:21:51.323312 ==============================================================
2231 13:21:51.326684 GAT_TRACK_EN = 1
2232 13:21:51.331186 RX_GATING_MODE = 2
2233 13:21:51.333212 RX_GATING_TRACK_MODE = 2
2234 13:21:51.336738 SELPH_MODE = 1
2235 13:21:51.340026 PICG_EARLY_EN = 1
2236 13:21:51.340566 VALID_LAT_VALUE = 1
2237 13:21:51.346738 ==============================================================
2238 13:21:51.350493 Enter into Gating configuration >>>>
2239 13:21:51.353526 Exit from Gating configuration <<<<
2240 13:21:51.357735 Enter into DVFS_PRE_config >>>>>
2241 13:21:51.366554 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2242 13:21:51.370074 Exit from DVFS_PRE_config <<<<<
2243 13:21:51.372935 Enter into PICG configuration >>>>
2244 13:21:51.376727 Exit from PICG configuration <<<<
2245 13:21:51.380361 [RX_INPUT] configuration >>>>>
2246 13:21:51.383410 [RX_INPUT] configuration <<<<<
2247 13:21:51.389709 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2248 13:21:51.393103 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2249 13:21:51.399754 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 13:21:51.406341 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 13:21:51.413156 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2252 13:21:51.419572 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2253 13:21:51.423317 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2254 13:21:51.426340 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2255 13:21:51.429502 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2256 13:21:51.435907 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2257 13:21:51.439149 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2258 13:21:51.442415 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2259 13:21:51.445640 ===================================
2260 13:21:51.449122 LPDDR4 DRAM CONFIGURATION
2261 13:21:51.452827 ===================================
2262 13:21:51.453268 EX_ROW_EN[0] = 0x0
2263 13:21:51.456002 EX_ROW_EN[1] = 0x0
2264 13:21:51.459228 LP4Y_EN = 0x0
2265 13:21:51.459760 WORK_FSP = 0x0
2266 13:21:51.462667 WL = 0x4
2267 13:21:51.463100 RL = 0x4
2268 13:21:51.466002 BL = 0x2
2269 13:21:51.466534 RPST = 0x0
2270 13:21:51.468962 RD_PRE = 0x0
2271 13:21:51.469396 WR_PRE = 0x1
2272 13:21:51.473595 WR_PST = 0x0
2273 13:21:51.474157 DBI_WR = 0x0
2274 13:21:51.475778 DBI_RD = 0x0
2275 13:21:51.476215 OTF = 0x1
2276 13:21:51.479605 ===================================
2277 13:21:51.482957 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2278 13:21:51.488974 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2279 13:21:51.492673 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2280 13:21:51.495804 ===================================
2281 13:21:51.499290 LPDDR4 DRAM CONFIGURATION
2282 13:21:51.502118 ===================================
2283 13:21:51.502696 EX_ROW_EN[0] = 0x10
2284 13:21:51.506016 EX_ROW_EN[1] = 0x0
2285 13:21:51.506554 LP4Y_EN = 0x0
2286 13:21:51.509270 WORK_FSP = 0x0
2287 13:21:51.512459 WL = 0x4
2288 13:21:51.512991 RL = 0x4
2289 13:21:51.515570 BL = 0x2
2290 13:21:51.516007 RPST = 0x0
2291 13:21:51.518992 RD_PRE = 0x0
2292 13:21:51.519427 WR_PRE = 0x1
2293 13:21:51.522101 WR_PST = 0x0
2294 13:21:51.522534 DBI_WR = 0x0
2295 13:21:51.525780 DBI_RD = 0x0
2296 13:21:51.526229 OTF = 0x1
2297 13:21:51.528764 ===================================
2298 13:21:51.535643 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2299 13:21:51.536196 ==
2300 13:21:51.538874 Dram Type= 6, Freq= 0, CH_0, rank 0
2301 13:21:51.542043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2302 13:21:51.542412 ==
2303 13:21:51.545270 [Duty_Offset_Calibration]
2304 13:21:51.548450 B0:1 B1:-1 CA:0
2305 13:21:51.548738
2306 13:21:51.552458 [DutyScan_Calibration_Flow] k_type=0
2307 13:21:51.560218
2308 13:21:51.560480 ==CLK 0==
2309 13:21:51.563333 Final CLK duty delay cell = 0
2310 13:21:51.566944 [0] MAX Duty = 5125%(X100), DQS PI = 24
2311 13:21:51.570423 [0] MIN Duty = 4907%(X100), DQS PI = 6
2312 13:21:51.570728 [0] AVG Duty = 5016%(X100)
2313 13:21:51.573780
2314 13:21:51.574065 CH0 CLK Duty spec in!! Max-Min= 218%
2315 13:21:51.580293 [DutyScan_Calibration_Flow] ====Done====
2316 13:21:51.580814
2317 13:21:51.583493 [DutyScan_Calibration_Flow] k_type=1
2318 13:21:51.597849
2319 13:21:51.598363 ==DQS 0 ==
2320 13:21:51.601205 Final DQS duty delay cell = -4
2321 13:21:51.605004 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2322 13:21:51.608764 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2323 13:21:51.611080 [-4] AVG Duty = 4968%(X100)
2324 13:21:51.611495
2325 13:21:51.611821 ==DQS 1 ==
2326 13:21:51.614997 Final DQS duty delay cell = -4
2327 13:21:51.618341 [-4] MAX Duty = 5000%(X100), DQS PI = 8
2328 13:21:51.621481 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2329 13:21:51.625000 [-4] AVG Duty = 4938%(X100)
2330 13:21:51.625519
2331 13:21:51.627805 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2332 13:21:51.628324
2333 13:21:51.631570 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2334 13:21:51.634246 [DutyScan_Calibration_Flow] ====Done====
2335 13:21:51.634693
2336 13:21:51.638165 [DutyScan_Calibration_Flow] k_type=3
2337 13:21:51.656357
2338 13:21:51.656906 ==DQM 0 ==
2339 13:21:51.659841 Final DQM duty delay cell = 0
2340 13:21:51.662863 [0] MAX Duty = 5062%(X100), DQS PI = 24
2341 13:21:51.666526 [0] MIN Duty = 4875%(X100), DQS PI = 8
2342 13:21:51.667138 [0] AVG Duty = 4968%(X100)
2343 13:21:51.669633
2344 13:21:51.670222 ==DQM 1 ==
2345 13:21:51.672705 Final DQM duty delay cell = 4
2346 13:21:51.676310 [4] MAX Duty = 5187%(X100), DQS PI = 14
2347 13:21:51.680032 [4] MIN Duty = 5000%(X100), DQS PI = 24
2348 13:21:51.680615 [4] AVG Duty = 5093%(X100)
2349 13:21:51.683040
2350 13:21:51.686381 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2351 13:21:51.687004
2352 13:21:51.689465 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2353 13:21:51.693519 [DutyScan_Calibration_Flow] ====Done====
2354 13:21:51.694095
2355 13:21:51.696633 [DutyScan_Calibration_Flow] k_type=2
2356 13:21:51.711005
2357 13:21:51.711575 ==DQ 0 ==
2358 13:21:51.714479 Final DQ duty delay cell = -4
2359 13:21:51.717746 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2360 13:21:51.720945 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2361 13:21:51.724422 [-4] AVG Duty = 4969%(X100)
2362 13:21:51.724898
2363 13:21:51.725389 ==DQ 1 ==
2364 13:21:51.727533 Final DQ duty delay cell = -4
2365 13:21:51.730998 [-4] MAX Duty = 5000%(X100), DQS PI = 56
2366 13:21:51.734462 [-4] MIN Duty = 4876%(X100), DQS PI = 14
2367 13:21:51.737147 [-4] AVG Duty = 4938%(X100)
2368 13:21:51.737722
2369 13:21:51.740566 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2370 13:21:51.741144
2371 13:21:51.744249 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2372 13:21:51.747052 [DutyScan_Calibration_Flow] ====Done====
2373 13:21:51.747531 ==
2374 13:21:51.750231 Dram Type= 6, Freq= 0, CH_1, rank 0
2375 13:21:51.753790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2376 13:21:51.754374 ==
2377 13:21:51.757113 [Duty_Offset_Calibration]
2378 13:21:51.760517 B0:-1 B1:1 CA:1
2379 13:21:51.761094
2380 13:21:51.763325 [DutyScan_Calibration_Flow] k_type=0
2381 13:21:51.771757
2382 13:21:51.772337 ==CLK 0==
2383 13:21:51.774944 Final CLK duty delay cell = 0
2384 13:21:51.778704 [0] MAX Duty = 5156%(X100), DQS PI = 20
2385 13:21:51.781872 [0] MIN Duty = 4969%(X100), DQS PI = 62
2386 13:21:51.782352 [0] AVG Duty = 5062%(X100)
2387 13:21:51.784857
2388 13:21:51.788596 CH1 CLK Duty spec in!! Max-Min= 187%
2389 13:21:51.791704 [DutyScan_Calibration_Flow] ====Done====
2390 13:21:51.792342
2391 13:21:51.794970 [DutyScan_Calibration_Flow] k_type=1
2392 13:21:51.811187
2393 13:21:51.811761 ==DQS 0 ==
2394 13:21:51.814922 Final DQS duty delay cell = 0
2395 13:21:51.817939 [0] MAX Duty = 5156%(X100), DQS PI = 48
2396 13:21:51.821812 [0] MIN Duty = 4907%(X100), DQS PI = 8
2397 13:21:51.822292 [0] AVG Duty = 5031%(X100)
2398 13:21:51.824856
2399 13:21:51.825411 ==DQS 1 ==
2400 13:21:51.828406 Final DQS duty delay cell = 0
2401 13:21:51.831147 [0] MAX Duty = 5062%(X100), DQS PI = 10
2402 13:21:51.834099 [0] MIN Duty = 4969%(X100), DQS PI = 56
2403 13:21:51.834573 [0] AVG Duty = 5015%(X100)
2404 13:21:51.837728
2405 13:21:51.841064 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2406 13:21:51.841663
2407 13:21:51.846013 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2408 13:21:51.847609 [DutyScan_Calibration_Flow] ====Done====
2409 13:21:51.848083
2410 13:21:51.851106 [DutyScan_Calibration_Flow] k_type=3
2411 13:21:51.866713
2412 13:21:51.867283 ==DQM 0 ==
2413 13:21:51.870876 Final DQM duty delay cell = -4
2414 13:21:51.874040 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2415 13:21:51.876407 [-4] MIN Duty = 4876%(X100), DQS PI = 8
2416 13:21:51.880097 [-4] AVG Duty = 4969%(X100)
2417 13:21:51.880674
2418 13:21:51.881160 ==DQM 1 ==
2419 13:21:51.883096 Final DQM duty delay cell = 0
2420 13:21:51.886869 [0] MAX Duty = 5187%(X100), DQS PI = 6
2421 13:21:51.890092 [0] MIN Duty = 4969%(X100), DQS PI = 28
2422 13:21:51.893613 [0] AVG Duty = 5078%(X100)
2423 13:21:51.894190
2424 13:21:51.896591 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2425 13:21:51.897159
2426 13:21:51.899843 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2427 13:21:51.902884 [DutyScan_Calibration_Flow] ====Done====
2428 13:21:51.903344
2429 13:21:51.906655 [DutyScan_Calibration_Flow] k_type=2
2430 13:21:51.923797
2431 13:21:51.924350 ==DQ 0 ==
2432 13:21:51.926852 Final DQ duty delay cell = 0
2433 13:21:51.929843 [0] MAX Duty = 5156%(X100), DQS PI = 28
2434 13:21:51.933527 [0] MIN Duty = 4907%(X100), DQS PI = 6
2435 13:21:51.934077 [0] AVG Duty = 5031%(X100)
2436 13:21:51.936763
2437 13:21:51.937353 ==DQ 1 ==
2438 13:21:51.939722 Final DQ duty delay cell = 0
2439 13:21:51.943198 [0] MAX Duty = 5124%(X100), DQS PI = 10
2440 13:21:51.946541 [0] MIN Duty = 4969%(X100), DQS PI = 0
2441 13:21:51.947244 [0] AVG Duty = 5046%(X100)
2442 13:21:51.947635
2443 13:21:51.952799 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2444 13:21:51.953359
2445 13:21:51.956456 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2446 13:21:51.959615 [DutyScan_Calibration_Flow] ====Done====
2447 13:21:51.962808 nWR fixed to 30
2448 13:21:51.963231 [ModeRegInit_LP4] CH0 RK0
2449 13:21:51.966691 [ModeRegInit_LP4] CH0 RK1
2450 13:21:51.969795 [ModeRegInit_LP4] CH1 RK0
2451 13:21:51.973107 [ModeRegInit_LP4] CH1 RK1
2452 13:21:51.973620 match AC timing 7
2453 13:21:51.976265 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2454 13:21:51.983162 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2455 13:21:51.986241 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2456 13:21:51.992755 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2457 13:21:51.996614 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2458 13:21:51.997130 ==
2459 13:21:52.000134 Dram Type= 6, Freq= 0, CH_0, rank 0
2460 13:21:52.003062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2461 13:21:52.003579 ==
2462 13:21:52.009543 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2463 13:21:52.016129 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2464 13:21:52.023550 [CA 0] Center 39 (9~70) winsize 62
2465 13:21:52.027211 [CA 1] Center 39 (9~69) winsize 61
2466 13:21:52.029534 [CA 2] Center 35 (5~66) winsize 62
2467 13:21:52.033391 [CA 3] Center 35 (5~66) winsize 62
2468 13:21:52.036864 [CA 4] Center 33 (4~63) winsize 60
2469 13:21:52.039907 [CA 5] Center 33 (3~63) winsize 61
2470 13:21:52.040465
2471 13:21:52.042964 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2472 13:21:52.043419
2473 13:21:52.046540 [CATrainingPosCal] consider 1 rank data
2474 13:21:52.049565 u2DelayCellTimex100 = 270/100 ps
2475 13:21:52.053098 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2476 13:21:52.060308 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2477 13:21:52.062981 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2478 13:21:52.066338 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2479 13:21:52.069698 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2480 13:21:52.073290 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2481 13:21:52.073845
2482 13:21:52.076813 CA PerBit enable=1, Macro0, CA PI delay=33
2483 13:21:52.077389
2484 13:21:52.079364 [CBTSetCACLKResult] CA Dly = 33
2485 13:21:52.079819 CS Dly: 8 (0~39)
2486 13:21:52.082957 ==
2487 13:21:52.086466 Dram Type= 6, Freq= 0, CH_0, rank 1
2488 13:21:52.089543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2489 13:21:52.090017 ==
2490 13:21:52.093730 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2491 13:21:52.099770 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2492 13:21:52.108970 [CA 0] Center 39 (8~70) winsize 63
2493 13:21:52.112202 [CA 1] Center 39 (9~70) winsize 62
2494 13:21:52.115372 [CA 2] Center 35 (5~66) winsize 62
2495 13:21:52.118542 [CA 3] Center 35 (5~65) winsize 61
2496 13:21:52.122052 [CA 4] Center 33 (3~64) winsize 62
2497 13:21:52.125441 [CA 5] Center 33 (3~63) winsize 61
2498 13:21:52.126057
2499 13:21:52.128832 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2500 13:21:52.129287
2501 13:21:52.132891 [CATrainingPosCal] consider 2 rank data
2502 13:21:52.135449 u2DelayCellTimex100 = 270/100 ps
2503 13:21:52.138897 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2504 13:21:52.145495 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2505 13:21:52.149035 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2506 13:21:52.151908 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2507 13:21:52.155013 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2508 13:21:52.158542 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2509 13:21:52.159113
2510 13:21:52.161763 CA PerBit enable=1, Macro0, CA PI delay=33
2511 13:21:52.162320
2512 13:21:52.165383 [CBTSetCACLKResult] CA Dly = 33
2513 13:21:52.168598 CS Dly: 9 (0~41)
2514 13:21:52.169168
2515 13:21:52.171474 ----->DramcWriteLeveling(PI) begin...
2516 13:21:52.171932 ==
2517 13:21:52.175429 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 13:21:52.178194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 13:21:52.178740 ==
2520 13:21:52.181632 Write leveling (Byte 0): 32 => 32
2521 13:21:52.185620 Write leveling (Byte 1): 30 => 30
2522 13:21:52.188611 DramcWriteLeveling(PI) end<-----
2523 13:21:52.189164
2524 13:21:52.189537 ==
2525 13:21:52.191947 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 13:21:52.194994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 13:21:52.195547 ==
2528 13:21:52.198921 [Gating] SW mode calibration
2529 13:21:52.204804 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2530 13:21:52.211840 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2531 13:21:52.214841 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2532 13:21:52.218460 0 15 4 | B1->B0 | 2626 3434 | 0 1 | (1 1) (1 1)
2533 13:21:52.225269 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 13:21:52.228060 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 13:21:52.230906 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 13:21:52.237793 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 13:21:52.241220 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2538 13:21:52.244409 0 15 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
2539 13:21:52.251051 1 0 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
2540 13:21:52.254202 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 13:21:52.257621 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 13:21:52.264221 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 13:21:52.267890 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 13:21:52.271188 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 13:21:52.278104 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 13:21:52.281159 1 0 28 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
2547 13:21:52.284623 1 1 0 | B1->B0 | 2727 4545 | 1 0 | (0 0) (0 0)
2548 13:21:52.290946 1 1 4 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
2549 13:21:52.294436 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 13:21:52.297818 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 13:21:52.304293 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 13:21:52.308250 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 13:21:52.311216 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 13:21:52.317833 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2555 13:21:52.320476 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2556 13:21:52.324093 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2557 13:21:52.331264 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 13:21:52.334047 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 13:21:52.337397 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 13:21:52.343862 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 13:21:52.347053 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 13:21:52.350192 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 13:21:52.354180 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 13:21:52.361037 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 13:21:52.364333 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 13:21:52.367183 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 13:21:52.373642 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 13:21:52.377307 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 13:21:52.380649 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2570 13:21:52.387523 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2571 13:21:52.390402 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2572 13:21:52.394219 Total UI for P1: 0, mck2ui 16
2573 13:21:52.397046 best dqsien dly found for B0: ( 1, 3, 26)
2574 13:21:52.400252 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 13:21:52.404020 Total UI for P1: 0, mck2ui 16
2576 13:21:52.407148 best dqsien dly found for B1: ( 1, 4, 0)
2577 13:21:52.410248 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2578 13:21:52.414539 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2579 13:21:52.415143
2580 13:21:52.420375 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2581 13:21:52.423392 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2582 13:21:52.423858 [Gating] SW calibration Done
2583 13:21:52.426998 ==
2584 13:21:52.430410 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 13:21:52.433732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 13:21:52.434190 ==
2587 13:21:52.434551 RX Vref Scan: 0
2588 13:21:52.434927
2589 13:21:52.436995 RX Vref 0 -> 0, step: 1
2590 13:21:52.437451
2591 13:21:52.439961 RX Delay -40 -> 252, step: 8
2592 13:21:52.443273 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2593 13:21:52.446875 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2594 13:21:52.453254 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2595 13:21:52.456648 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2596 13:21:52.460116 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2597 13:21:52.463634 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2598 13:21:52.467046 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2599 13:21:52.473202 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2600 13:21:52.476509 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2601 13:21:52.479733 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2602 13:21:52.483294 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2603 13:21:52.486403 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2604 13:21:52.493111 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2605 13:21:52.496515 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2606 13:21:52.499938 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2607 13:21:52.503559 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2608 13:21:52.504112 ==
2609 13:21:52.506532 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 13:21:52.509779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 13:21:52.513212 ==
2612 13:21:52.513767 DQS Delay:
2613 13:21:52.514131 DQS0 = 0, DQS1 = 0
2614 13:21:52.516411 DQM Delay:
2615 13:21:52.516966 DQM0 = 119, DQM1 = 107
2616 13:21:52.519884 DQ Delay:
2617 13:21:52.522812 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2618 13:21:52.526638 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2619 13:21:52.529900 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2620 13:21:52.532737 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2621 13:21:52.533200
2622 13:21:52.533560
2623 13:21:52.533898 ==
2624 13:21:52.536059 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 13:21:52.539336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 13:21:52.539802 ==
2627 13:21:52.540168
2628 13:21:52.543289
2629 13:21:52.543747 TX Vref Scan disable
2630 13:21:52.546556 == TX Byte 0 ==
2631 13:21:52.549680 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2632 13:21:52.553219 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2633 13:21:52.555798 == TX Byte 1 ==
2634 13:21:52.559632 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2635 13:21:52.562350 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2636 13:21:52.562805 ==
2637 13:21:52.565859 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 13:21:52.572604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 13:21:52.573135 ==
2640 13:21:52.583601 TX Vref=22, minBit 1, minWin=25, winSum=414
2641 13:21:52.586945 TX Vref=24, minBit 7, minWin=25, winSum=422
2642 13:21:52.589844 TX Vref=26, minBit 4, minWin=26, winSum=427
2643 13:21:52.593259 TX Vref=28, minBit 5, minWin=26, winSum=432
2644 13:21:52.596636 TX Vref=30, minBit 5, minWin=26, winSum=431
2645 13:21:52.604004 TX Vref=32, minBit 4, minWin=26, winSum=429
2646 13:21:52.606117 [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 28
2647 13:21:52.606572
2648 13:21:52.610424 Final TX Range 1 Vref 28
2649 13:21:52.611027
2650 13:21:52.611387 ==
2651 13:21:52.613386 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 13:21:52.616377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2653 13:21:52.616933 ==
2654 13:21:52.619460
2655 13:21:52.619911
2656 13:21:52.620266 TX Vref Scan disable
2657 13:21:52.622750 == TX Byte 0 ==
2658 13:21:52.626975 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2659 13:21:52.633633 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2660 13:21:52.634187 == TX Byte 1 ==
2661 13:21:52.636132 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2662 13:21:52.642531 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2663 13:21:52.643119
2664 13:21:52.643481 [DATLAT]
2665 13:21:52.643818 Freq=1200, CH0 RK0
2666 13:21:52.644143
2667 13:21:52.645889 DATLAT Default: 0xd
2668 13:21:52.646340 0, 0xFFFF, sum = 0
2669 13:21:52.649230 1, 0xFFFF, sum = 0
2670 13:21:52.652860 2, 0xFFFF, sum = 0
2671 13:21:52.653424 3, 0xFFFF, sum = 0
2672 13:21:52.656265 4, 0xFFFF, sum = 0
2673 13:21:52.656829 5, 0xFFFF, sum = 0
2674 13:21:52.659200 6, 0xFFFF, sum = 0
2675 13:21:52.659663 7, 0xFFFF, sum = 0
2676 13:21:52.662534 8, 0xFFFF, sum = 0
2677 13:21:52.663044 9, 0xFFFF, sum = 0
2678 13:21:52.666167 10, 0xFFFF, sum = 0
2679 13:21:52.666776 11, 0xFFFF, sum = 0
2680 13:21:52.669068 12, 0x0, sum = 1
2681 13:21:52.669530 13, 0x0, sum = 2
2682 13:21:52.672543 14, 0x0, sum = 3
2683 13:21:52.673102 15, 0x0, sum = 4
2684 13:21:52.675858 best_step = 13
2685 13:21:52.676414
2686 13:21:52.676774 ==
2687 13:21:52.679557 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 13:21:52.683206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 13:21:52.683765 ==
2690 13:21:52.684127 RX Vref Scan: 1
2691 13:21:52.685840
2692 13:21:52.686391 Set Vref Range= 32 -> 127
2693 13:21:52.686801
2694 13:21:52.689349 RX Vref 32 -> 127, step: 1
2695 13:21:52.689960
2696 13:21:52.692199 RX Delay -21 -> 252, step: 4
2697 13:21:52.692657
2698 13:21:52.696130 Set Vref, RX VrefLevel [Byte0]: 32
2699 13:21:52.699318 [Byte1]: 32
2700 13:21:52.699868
2701 13:21:52.702697 Set Vref, RX VrefLevel [Byte0]: 33
2702 13:21:52.705814 [Byte1]: 33
2703 13:21:52.709694
2704 13:21:52.710249 Set Vref, RX VrefLevel [Byte0]: 34
2705 13:21:52.712744 [Byte1]: 34
2706 13:21:52.717337
2707 13:21:52.717899 Set Vref, RX VrefLevel [Byte0]: 35
2708 13:21:52.720488 [Byte1]: 35
2709 13:21:52.725314
2710 13:21:52.725877 Set Vref, RX VrefLevel [Byte0]: 36
2711 13:21:52.732072 [Byte1]: 36
2712 13:21:52.732642
2713 13:21:52.735150 Set Vref, RX VrefLevel [Byte0]: 37
2714 13:21:52.738392 [Byte1]: 37
2715 13:21:52.739001
2716 13:21:52.742453 Set Vref, RX VrefLevel [Byte0]: 38
2717 13:21:52.744971 [Byte1]: 38
2718 13:21:52.748859
2719 13:21:52.749320 Set Vref, RX VrefLevel [Byte0]: 39
2720 13:21:52.752217 [Byte1]: 39
2721 13:21:52.757002
2722 13:21:52.757578 Set Vref, RX VrefLevel [Byte0]: 40
2723 13:21:52.760486 [Byte1]: 40
2724 13:21:52.765243
2725 13:21:52.765805 Set Vref, RX VrefLevel [Byte0]: 41
2726 13:21:52.768107 [Byte1]: 41
2727 13:21:52.772965
2728 13:21:52.773515 Set Vref, RX VrefLevel [Byte0]: 42
2729 13:21:52.777308 [Byte1]: 42
2730 13:21:52.780766
2731 13:21:52.781227 Set Vref, RX VrefLevel [Byte0]: 43
2732 13:21:52.784422 [Byte1]: 43
2733 13:21:52.788784
2734 13:21:52.789352 Set Vref, RX VrefLevel [Byte0]: 44
2735 13:21:52.791914 [Byte1]: 44
2736 13:21:52.796972
2737 13:21:52.797525 Set Vref, RX VrefLevel [Byte0]: 45
2738 13:21:52.800004 [Byte1]: 45
2739 13:21:52.805023
2740 13:21:52.805585 Set Vref, RX VrefLevel [Byte0]: 46
2741 13:21:52.807901 [Byte1]: 46
2742 13:21:52.812407
2743 13:21:52.812992 Set Vref, RX VrefLevel [Byte0]: 47
2744 13:21:52.815701 [Byte1]: 47
2745 13:21:52.820534
2746 13:21:52.821120 Set Vref, RX VrefLevel [Byte0]: 48
2747 13:21:52.824024 [Byte1]: 48
2748 13:21:52.827980
2749 13:21:52.828438 Set Vref, RX VrefLevel [Byte0]: 49
2750 13:21:52.831690 [Byte1]: 49
2751 13:21:52.837138
2752 13:21:52.837777 Set Vref, RX VrefLevel [Byte0]: 50
2753 13:21:52.839445 [Byte1]: 50
2754 13:21:52.844324
2755 13:21:52.844888 Set Vref, RX VrefLevel [Byte0]: 51
2756 13:21:52.847588 [Byte1]: 51
2757 13:21:52.852127
2758 13:21:52.852686 Set Vref, RX VrefLevel [Byte0]: 52
2759 13:21:52.855392 [Byte1]: 52
2760 13:21:52.860307
2761 13:21:52.860871 Set Vref, RX VrefLevel [Byte0]: 53
2762 13:21:52.863578 [Byte1]: 53
2763 13:21:52.868215
2764 13:21:52.868774 Set Vref, RX VrefLevel [Byte0]: 54
2765 13:21:52.871216 [Byte1]: 54
2766 13:21:52.876199
2767 13:21:52.876779 Set Vref, RX VrefLevel [Byte0]: 55
2768 13:21:52.879687 [Byte1]: 55
2769 13:21:52.884023
2770 13:21:52.884583 Set Vref, RX VrefLevel [Byte0]: 56
2771 13:21:52.887192 [Byte1]: 56
2772 13:21:52.891543
2773 13:21:52.892106 Set Vref, RX VrefLevel [Byte0]: 57
2774 13:21:52.894790 [Byte1]: 57
2775 13:21:52.899733
2776 13:21:52.900191 Set Vref, RX VrefLevel [Byte0]: 58
2777 13:21:52.903043 [Byte1]: 58
2778 13:21:52.908568
2779 13:21:52.909130 Set Vref, RX VrefLevel [Byte0]: 59
2780 13:21:52.911044 [Byte1]: 59
2781 13:21:52.915618
2782 13:21:52.916182 Set Vref, RX VrefLevel [Byte0]: 60
2783 13:21:52.919206 [Byte1]: 60
2784 13:21:52.923647
2785 13:21:52.924108 Set Vref, RX VrefLevel [Byte0]: 61
2786 13:21:52.926714 [Byte1]: 61
2787 13:21:52.931326
2788 13:21:52.931927 Set Vref, RX VrefLevel [Byte0]: 62
2789 13:21:52.934928 [Byte1]: 62
2790 13:21:52.939108
2791 13:21:52.939568 Set Vref, RX VrefLevel [Byte0]: 63
2792 13:21:52.943300 [Byte1]: 63
2793 13:21:52.947244
2794 13:21:52.947802 Set Vref, RX VrefLevel [Byte0]: 64
2795 13:21:52.950983 [Byte1]: 64
2796 13:21:52.955499
2797 13:21:52.956076 Set Vref, RX VrefLevel [Byte0]: 65
2798 13:21:52.958837 [Byte1]: 65
2799 13:21:52.963197
2800 13:21:52.963659 Set Vref, RX VrefLevel [Byte0]: 66
2801 13:21:52.966673 [Byte1]: 66
2802 13:21:52.971298
2803 13:21:52.971856 Set Vref, RX VrefLevel [Byte0]: 67
2804 13:21:52.974762 [Byte1]: 67
2805 13:21:52.979071
2806 13:21:52.979772 Set Vref, RX VrefLevel [Byte0]: 68
2807 13:21:52.982140 [Byte1]: 68
2808 13:21:52.986991
2809 13:21:52.987554 Set Vref, RX VrefLevel [Byte0]: 69
2810 13:21:52.990510 [Byte1]: 69
2811 13:21:52.995031
2812 13:21:52.995582 Set Vref, RX VrefLevel [Byte0]: 70
2813 13:21:52.998481 [Byte1]: 70
2814 13:21:53.003260
2815 13:21:53.003808 Set Vref, RX VrefLevel [Byte0]: 71
2816 13:21:53.006141 [Byte1]: 71
2817 13:21:53.010911
2818 13:21:53.011460 Set Vref, RX VrefLevel [Byte0]: 72
2819 13:21:53.013934 [Byte1]: 72
2820 13:21:53.018700
2821 13:21:53.019246 Set Vref, RX VrefLevel [Byte0]: 73
2822 13:21:53.021891 [Byte1]: 73
2823 13:21:53.026555
2824 13:21:53.027149 Set Vref, RX VrefLevel [Byte0]: 74
2825 13:21:53.030330 [Byte1]: 74
2826 13:21:53.034540
2827 13:21:53.035174 Set Vref, RX VrefLevel [Byte0]: 75
2828 13:21:53.037684 [Byte1]: 75
2829 13:21:53.042829
2830 13:21:53.043395 Set Vref, RX VrefLevel [Byte0]: 76
2831 13:21:53.046390 [Byte1]: 76
2832 13:21:53.050406
2833 13:21:53.050927 Set Vref, RX VrefLevel [Byte0]: 77
2834 13:21:53.053410 [Byte1]: 77
2835 13:21:53.058361
2836 13:21:53.058975 Final RX Vref Byte 0 = 61 to rank0
2837 13:21:53.061617 Final RX Vref Byte 1 = 48 to rank0
2838 13:21:53.065135 Final RX Vref Byte 0 = 61 to rank1
2839 13:21:53.068483 Final RX Vref Byte 1 = 48 to rank1==
2840 13:21:53.072014 Dram Type= 6, Freq= 0, CH_0, rank 0
2841 13:21:53.078765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2842 13:21:53.079324 ==
2843 13:21:53.079683 DQS Delay:
2844 13:21:53.080017 DQS0 = 0, DQS1 = 0
2845 13:21:53.081187 DQM Delay:
2846 13:21:53.081637 DQM0 = 119, DQM1 = 106
2847 13:21:53.084376 DQ Delay:
2848 13:21:53.087964 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2849 13:21:53.091206 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
2850 13:21:53.094830 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =100
2851 13:21:53.098322 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =116
2852 13:21:53.098938
2853 13:21:53.099301
2854 13:21:53.107910 [DQSOSCAuto] RK0, (LSB)MR18= 0x11fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2855 13:21:53.108474 CH0 RK0: MR19=403, MR18=11FC
2856 13:21:53.114447 CH0_RK0: MR19=0x403, MR18=0x11FC, DQSOSC=403, MR23=63, INC=40, DEC=26
2857 13:21:53.115062
2858 13:21:53.117962 ----->DramcWriteLeveling(PI) begin...
2859 13:21:53.118527 ==
2860 13:21:53.121181 Dram Type= 6, Freq= 0, CH_0, rank 1
2861 13:21:53.127546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2862 13:21:53.128119 ==
2863 13:21:53.131320 Write leveling (Byte 0): 32 => 32
2864 13:21:53.134224 Write leveling (Byte 1): 32 => 32
2865 13:21:53.134836 DramcWriteLeveling(PI) end<-----
2866 13:21:53.135230
2867 13:21:53.137451 ==
2868 13:21:53.141563 Dram Type= 6, Freq= 0, CH_0, rank 1
2869 13:21:53.144308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2870 13:21:53.144811 ==
2871 13:21:53.147349 [Gating] SW mode calibration
2872 13:21:53.154772 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2873 13:21:53.157880 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2874 13:21:53.164332 0 15 0 | B1->B0 | 2424 3131 | 1 1 | (1 1) (1 1)
2875 13:21:53.167622 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2876 13:21:53.171160 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2877 13:21:53.178207 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2878 13:21:53.181644 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2879 13:21:53.185110 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2880 13:21:53.190871 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2881 13:21:53.194002 0 15 28 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
2882 13:21:53.197994 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
2883 13:21:53.204172 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2884 13:21:53.207370 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2885 13:21:53.210699 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2886 13:21:53.217521 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2887 13:21:53.220370 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2888 13:21:53.223842 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2889 13:21:53.230472 1 0 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
2890 13:21:53.234293 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2891 13:21:53.236992 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2892 13:21:53.243973 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 13:21:53.246948 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2894 13:21:53.250807 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2895 13:21:53.253728 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 13:21:53.260020 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 13:21:53.263603 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2898 13:21:53.267103 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2899 13:21:53.273296 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 13:21:53.277096 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 13:21:53.280131 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 13:21:53.286862 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 13:21:53.290194 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 13:21:53.293245 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 13:21:53.300127 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 13:21:53.303763 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 13:21:53.306822 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 13:21:53.313468 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 13:21:53.317019 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 13:21:53.320804 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 13:21:53.326804 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 13:21:53.329972 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2913 13:21:53.333282 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2914 13:21:53.339642 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2915 13:21:53.340124 Total UI for P1: 0, mck2ui 16
2916 13:21:53.346824 best dqsien dly found for B0: ( 1, 3, 26)
2917 13:21:53.350115 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 13:21:53.353655 Total UI for P1: 0, mck2ui 16
2919 13:21:53.356135 best dqsien dly found for B1: ( 1, 3, 30)
2920 13:21:53.359789 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2921 13:21:53.363048 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2922 13:21:53.363598
2923 13:21:53.367135 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2924 13:21:53.369769 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2925 13:21:53.373119 [Gating] SW calibration Done
2926 13:21:53.373675 ==
2927 13:21:53.376585 Dram Type= 6, Freq= 0, CH_0, rank 1
2928 13:21:53.379807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2929 13:21:53.383128 ==
2930 13:21:53.383683 RX Vref Scan: 0
2931 13:21:53.384047
2932 13:21:53.386410 RX Vref 0 -> 0, step: 1
2933 13:21:53.387055
2934 13:21:53.389796 RX Delay -40 -> 252, step: 8
2935 13:21:53.392659 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2936 13:21:53.396535 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2937 13:21:53.399176 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2938 13:21:53.403021 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2939 13:21:53.409622 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2940 13:21:53.413019 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2941 13:21:53.416034 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2942 13:21:53.419404 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2943 13:21:53.422715 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2944 13:21:53.425923 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2945 13:21:53.433018 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2946 13:21:53.436222 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2947 13:21:53.439439 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2948 13:21:53.442878 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2949 13:21:53.449289 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2950 13:21:53.453001 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2951 13:21:53.453567 ==
2952 13:21:53.455866 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 13:21:53.458967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 13:21:53.459425 ==
2955 13:21:53.462709 DQS Delay:
2956 13:21:53.463265 DQS0 = 0, DQS1 = 0
2957 13:21:53.463631 DQM Delay:
2958 13:21:53.465888 DQM0 = 117, DQM1 = 108
2959 13:21:53.466440 DQ Delay:
2960 13:21:53.468900 DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115
2961 13:21:53.472646 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2962 13:21:53.475932 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2963 13:21:53.482498 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
2964 13:21:53.483109
2965 13:21:53.483473
2966 13:21:53.483803 ==
2967 13:21:53.486286 Dram Type= 6, Freq= 0, CH_0, rank 1
2968 13:21:53.489697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2969 13:21:53.490247 ==
2970 13:21:53.490664
2971 13:21:53.491021
2972 13:21:53.492116 TX Vref Scan disable
2973 13:21:53.492570 == TX Byte 0 ==
2974 13:21:53.498694 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2975 13:21:53.501991 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2976 13:21:53.505158 == TX Byte 1 ==
2977 13:21:53.508552 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2978 13:21:53.512251 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2979 13:21:53.512799 ==
2980 13:21:53.515224 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 13:21:53.518773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 13:21:53.521918 ==
2983 13:21:53.531385 TX Vref=22, minBit 6, minWin=25, winSum=418
2984 13:21:53.534670 TX Vref=24, minBit 1, minWin=26, winSum=424
2985 13:21:53.538737 TX Vref=26, minBit 1, minWin=26, winSum=427
2986 13:21:53.541410 TX Vref=28, minBit 1, minWin=27, winSum=433
2987 13:21:53.544508 TX Vref=30, minBit 12, minWin=26, winSum=434
2988 13:21:53.552750 TX Vref=32, minBit 9, minWin=26, winSum=428
2989 13:21:53.554402 [TxChooseVref] Worse bit 1, Min win 27, Win sum 433, Final Vref 28
2990 13:21:53.554920
2991 13:21:53.557894 Final TX Range 1 Vref 28
2992 13:21:53.558349
2993 13:21:53.558758 ==
2994 13:21:53.561047 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 13:21:53.565358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 13:21:53.567851 ==
2997 13:21:53.568403
2998 13:21:53.568763
2999 13:21:53.569093 TX Vref Scan disable
3000 13:21:53.571333 == TX Byte 0 ==
3001 13:21:53.574673 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3002 13:21:53.581565 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3003 13:21:53.582120 == TX Byte 1 ==
3004 13:21:53.585058 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3005 13:21:53.587739 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3006 13:21:53.591327
3007 13:21:53.591926 [DATLAT]
3008 13:21:53.592390 Freq=1200, CH0 RK1
3009 13:21:53.592741
3010 13:21:53.594479 DATLAT Default: 0xd
3011 13:21:53.595020 0, 0xFFFF, sum = 0
3012 13:21:53.597947 1, 0xFFFF, sum = 0
3013 13:21:53.598405 2, 0xFFFF, sum = 0
3014 13:21:53.601853 3, 0xFFFF, sum = 0
3015 13:21:53.602312 4, 0xFFFF, sum = 0
3016 13:21:53.604328 5, 0xFFFF, sum = 0
3017 13:21:53.608510 6, 0xFFFF, sum = 0
3018 13:21:53.608991 7, 0xFFFF, sum = 0
3019 13:21:53.611929 8, 0xFFFF, sum = 0
3020 13:21:53.612347 9, 0xFFFF, sum = 0
3021 13:21:53.614280 10, 0xFFFF, sum = 0
3022 13:21:53.614746 11, 0xFFFF, sum = 0
3023 13:21:53.618161 12, 0x0, sum = 1
3024 13:21:53.618725 13, 0x0, sum = 2
3025 13:21:53.621970 14, 0x0, sum = 3
3026 13:21:53.622508 15, 0x0, sum = 4
3027 13:21:53.624657 best_step = 13
3028 13:21:53.625086
3029 13:21:53.625421 ==
3030 13:21:53.628152 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 13:21:53.630993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 13:21:53.631415 ==
3033 13:21:53.631747 RX Vref Scan: 0
3034 13:21:53.632056
3035 13:21:53.634646 RX Vref 0 -> 0, step: 1
3036 13:21:53.635181
3037 13:21:53.637754 RX Delay -21 -> 252, step: 4
3038 13:21:53.640974 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3039 13:21:53.647564 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3040 13:21:53.650768 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3041 13:21:53.654874 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3042 13:21:53.657395 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3043 13:21:53.660907 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3044 13:21:53.667991 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3045 13:21:53.670855 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3046 13:21:53.674339 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3047 13:21:53.677491 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3048 13:21:53.680950 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3049 13:21:53.687356 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3050 13:21:53.691499 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3051 13:21:53.693732 iDelay=195, Bit 13, Center 114 (47 ~ 182) 136
3052 13:21:53.697289 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3053 13:21:53.704270 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3054 13:21:53.704838 ==
3055 13:21:53.707484 Dram Type= 6, Freq= 0, CH_0, rank 1
3056 13:21:53.711002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3057 13:21:53.711561 ==
3058 13:21:53.711932 DQS Delay:
3059 13:21:53.714431 DQS0 = 0, DQS1 = 0
3060 13:21:53.715032 DQM Delay:
3061 13:21:53.717375 DQM0 = 116, DQM1 = 107
3062 13:21:53.717836 DQ Delay:
3063 13:21:53.720677 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3064 13:21:53.724191 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3065 13:21:53.726943 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3066 13:21:53.730462 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3067 13:21:53.730975
3068 13:21:53.731341
3069 13:21:53.740324 [DQSOSCAuto] RK1, (LSB)MR18= 0xce6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3070 13:21:53.743477 CH0 RK1: MR19=403, MR18=CE6
3071 13:21:53.747074 CH0_RK1: MR19=0x403, MR18=0xCE6, DQSOSC=405, MR23=63, INC=39, DEC=26
3072 13:21:53.750529 [RxdqsGatingPostProcess] freq 1200
3073 13:21:53.756777 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3074 13:21:53.759897 best DQS0 dly(2T, 0.5T) = (0, 11)
3075 13:21:53.763808 best DQS1 dly(2T, 0.5T) = (0, 12)
3076 13:21:53.766967 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3077 13:21:53.769961 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3078 13:21:53.773538 best DQS0 dly(2T, 0.5T) = (0, 11)
3079 13:21:53.776790 best DQS1 dly(2T, 0.5T) = (0, 11)
3080 13:21:53.780371 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3081 13:21:53.783436 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3082 13:21:53.783903 Pre-setting of DQS Precalculation
3083 13:21:53.790014 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3084 13:21:53.790569 ==
3085 13:21:53.793346 Dram Type= 6, Freq= 0, CH_1, rank 0
3086 13:21:53.796436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3087 13:21:53.796896 ==
3088 13:21:53.803157 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3089 13:21:53.809932 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3090 13:21:53.818197 [CA 0] Center 37 (7~68) winsize 62
3091 13:21:53.820827 [CA 1] Center 38 (8~68) winsize 61
3092 13:21:53.824185 [CA 2] Center 34 (4~64) winsize 61
3093 13:21:53.827566 [CA 3] Center 33 (3~64) winsize 62
3094 13:21:53.831209 [CA 4] Center 34 (4~64) winsize 61
3095 13:21:53.834373 [CA 5] Center 33 (3~64) winsize 62
3096 13:21:53.834854
3097 13:21:53.837316 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3098 13:21:53.837773
3099 13:21:53.840356 [CATrainingPosCal] consider 1 rank data
3100 13:21:53.844292 u2DelayCellTimex100 = 270/100 ps
3101 13:21:53.847322 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3102 13:21:53.854073 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3103 13:21:53.857160 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3104 13:21:53.861216 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3105 13:21:53.864348 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3106 13:21:53.867181 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3107 13:21:53.867641
3108 13:21:53.870656 CA PerBit enable=1, Macro0, CA PI delay=33
3109 13:21:53.871232
3110 13:21:53.874131 [CBTSetCACLKResult] CA Dly = 33
3111 13:21:53.874722 CS Dly: 6 (0~37)
3112 13:21:53.877387 ==
3113 13:21:53.877843 Dram Type= 6, Freq= 0, CH_1, rank 1
3114 13:21:53.884016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 13:21:53.884558 ==
3116 13:21:53.887141 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3117 13:21:53.893982 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3118 13:21:53.903034 [CA 0] Center 37 (7~68) winsize 62
3119 13:21:53.906466 [CA 1] Center 38 (8~68) winsize 61
3120 13:21:53.910097 [CA 2] Center 34 (4~65) winsize 62
3121 13:21:53.913615 [CA 3] Center 33 (3~64) winsize 62
3122 13:21:53.916260 [CA 4] Center 34 (3~65) winsize 63
3123 13:21:53.919704 [CA 5] Center 33 (3~64) winsize 62
3124 13:21:53.920257
3125 13:21:53.923043 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3126 13:21:53.923598
3127 13:21:53.926186 [CATrainingPosCal] consider 2 rank data
3128 13:21:53.929990 u2DelayCellTimex100 = 270/100 ps
3129 13:21:53.932942 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3130 13:21:53.940283 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3131 13:21:53.943039 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3132 13:21:53.946063 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3133 13:21:53.949587 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3134 13:21:53.952148 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3135 13:21:53.952609
3136 13:21:53.955810 CA PerBit enable=1, Macro0, CA PI delay=33
3137 13:21:53.956364
3138 13:21:53.958671 [CBTSetCACLKResult] CA Dly = 33
3139 13:21:53.962302 CS Dly: 7 (0~40)
3140 13:21:53.962902
3141 13:21:53.965594 ----->DramcWriteLeveling(PI) begin...
3142 13:21:53.966194 ==
3143 13:21:53.968915 Dram Type= 6, Freq= 0, CH_1, rank 0
3144 13:21:53.972017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3145 13:21:53.972518 ==
3146 13:21:53.975432 Write leveling (Byte 0): 24 => 24
3147 13:21:53.979289 Write leveling (Byte 1): 26 => 26
3148 13:21:53.982228 DramcWriteLeveling(PI) end<-----
3149 13:21:53.982826
3150 13:21:53.983197 ==
3151 13:21:53.985202 Dram Type= 6, Freq= 0, CH_1, rank 0
3152 13:21:53.988609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3153 13:21:53.989071 ==
3154 13:21:53.992233 [Gating] SW mode calibration
3155 13:21:53.999174 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3156 13:21:54.005997 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3157 13:21:54.008947 0 15 0 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
3158 13:21:54.012205 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3159 13:21:54.018735 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3160 13:21:54.021661 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3161 13:21:54.025051 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3162 13:21:54.032467 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3163 13:21:54.035159 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (0 0) (0 1)
3164 13:21:54.038725 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
3165 13:21:54.045138 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3166 13:21:54.048381 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3167 13:21:54.051393 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3168 13:21:54.058207 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3169 13:21:54.061206 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3170 13:21:54.064791 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3171 13:21:54.071540 1 0 24 | B1->B0 | 2525 3737 | 0 0 | (0 0) (1 1)
3172 13:21:54.074791 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3173 13:21:54.078454 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 13:21:54.084521 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 13:21:54.087773 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 13:21:54.091267 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 13:21:54.097636 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 13:21:54.101034 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 13:21:54.104555 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3180 13:21:54.110993 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3181 13:21:54.114248 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 13:21:54.118112 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 13:21:54.124128 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 13:21:54.127159 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 13:21:54.131507 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 13:21:54.137471 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 13:21:54.140484 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 13:21:54.143609 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 13:21:54.150724 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 13:21:54.154064 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 13:21:54.156995 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 13:21:54.163966 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 13:21:54.166830 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 13:21:54.170335 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 13:21:54.177393 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3196 13:21:54.180515 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3197 13:21:54.183117 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 13:21:54.187045 Total UI for P1: 0, mck2ui 16
3199 13:21:54.190362 best dqsien dly found for B0: ( 1, 3, 26)
3200 13:21:54.193418 Total UI for P1: 0, mck2ui 16
3201 13:21:54.197201 best dqsien dly found for B1: ( 1, 3, 28)
3202 13:21:54.199723 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3203 13:21:54.203446 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3204 13:21:54.204006
3205 13:21:54.210267 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3206 13:21:54.213076 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3207 13:21:54.216627 [Gating] SW calibration Done
3208 13:21:54.217188 ==
3209 13:21:54.219855 Dram Type= 6, Freq= 0, CH_1, rank 0
3210 13:21:54.222834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3211 13:21:54.223329 ==
3212 13:21:54.223698 RX Vref Scan: 0
3213 13:21:54.226575
3214 13:21:54.227069 RX Vref 0 -> 0, step: 1
3215 13:21:54.227433
3216 13:21:54.229647 RX Delay -40 -> 252, step: 8
3217 13:21:54.232975 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3218 13:21:54.236079 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3219 13:21:54.242849 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3220 13:21:54.246203 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3221 13:21:54.249621 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3222 13:21:54.253121 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3223 13:21:54.256195 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3224 13:21:54.263008 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3225 13:21:54.266250 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3226 13:21:54.269636 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3227 13:21:54.272757 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3228 13:21:54.276498 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3229 13:21:54.282681 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3230 13:21:54.286175 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3231 13:21:54.289246 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3232 13:21:54.292727 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3233 13:21:54.293287 ==
3234 13:21:54.296173 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 13:21:54.302339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 13:21:54.302968 ==
3237 13:21:54.303335 DQS Delay:
3238 13:21:54.305578 DQS0 = 0, DQS1 = 0
3239 13:21:54.306146 DQM Delay:
3240 13:21:54.308999 DQM0 = 117, DQM1 = 108
3241 13:21:54.309557 DQ Delay:
3242 13:21:54.312102 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3243 13:21:54.315932 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3244 13:21:54.319271 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3245 13:21:54.322232 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =119
3246 13:21:54.322842
3247 13:21:54.323215
3248 13:21:54.323550 ==
3249 13:21:54.325467 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 13:21:54.329121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 13:21:54.332506 ==
3252 13:21:54.333062
3253 13:21:54.333424
3254 13:21:54.333762 TX Vref Scan disable
3255 13:21:54.335872 == TX Byte 0 ==
3256 13:21:54.338980 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3257 13:21:54.342262 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3258 13:21:54.345315 == TX Byte 1 ==
3259 13:21:54.348425 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3260 13:21:54.351957 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3261 13:21:54.355181 ==
3262 13:21:54.358799 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 13:21:54.361596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 13:21:54.362059 ==
3265 13:21:54.372896 TX Vref=22, minBit 9, minWin=25, winSum=418
3266 13:21:54.376303 TX Vref=24, minBit 10, minWin=25, winSum=423
3267 13:21:54.379418 TX Vref=26, minBit 8, minWin=26, winSum=431
3268 13:21:54.383145 TX Vref=28, minBit 10, minWin=25, winSum=429
3269 13:21:54.386718 TX Vref=30, minBit 9, minWin=25, winSum=432
3270 13:21:54.392700 TX Vref=32, minBit 9, minWin=25, winSum=428
3271 13:21:54.396079 [TxChooseVref] Worse bit 8, Min win 26, Win sum 431, Final Vref 26
3272 13:21:54.396634
3273 13:21:54.399292 Final TX Range 1 Vref 26
3274 13:21:54.399751
3275 13:21:54.400109 ==
3276 13:21:54.402769 Dram Type= 6, Freq= 0, CH_1, rank 0
3277 13:21:54.406109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3278 13:21:54.409802 ==
3279 13:21:54.410355
3280 13:21:54.410777
3281 13:21:54.411125 TX Vref Scan disable
3282 13:21:54.412940 == TX Byte 0 ==
3283 13:21:54.416346 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3284 13:21:54.422770 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3285 13:21:54.423322 == TX Byte 1 ==
3286 13:21:54.426173 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3287 13:21:54.430006 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3288 13:21:54.432808
3289 13:21:54.433356 [DATLAT]
3290 13:21:54.433722 Freq=1200, CH1 RK0
3291 13:21:54.434064
3292 13:21:54.435741 DATLAT Default: 0xd
3293 13:21:54.436197 0, 0xFFFF, sum = 0
3294 13:21:54.439543 1, 0xFFFF, sum = 0
3295 13:21:54.440109 2, 0xFFFF, sum = 0
3296 13:21:54.442507 3, 0xFFFF, sum = 0
3297 13:21:54.446706 4, 0xFFFF, sum = 0
3298 13:21:54.447259 5, 0xFFFF, sum = 0
3299 13:21:54.449213 6, 0xFFFF, sum = 0
3300 13:21:54.449673 7, 0xFFFF, sum = 0
3301 13:21:54.452639 8, 0xFFFF, sum = 0
3302 13:21:54.453102 9, 0xFFFF, sum = 0
3303 13:21:54.455811 10, 0xFFFF, sum = 0
3304 13:21:54.456304 11, 0xFFFF, sum = 0
3305 13:21:54.458959 12, 0x0, sum = 1
3306 13:21:54.459420 13, 0x0, sum = 2
3307 13:21:54.462691 14, 0x0, sum = 3
3308 13:21:54.463153 15, 0x0, sum = 4
3309 13:21:54.463522 best_step = 13
3310 13:21:54.465929
3311 13:21:54.466379 ==
3312 13:21:54.469689 Dram Type= 6, Freq= 0, CH_1, rank 0
3313 13:21:54.472338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3314 13:21:54.472846 ==
3315 13:21:54.473218 RX Vref Scan: 1
3316 13:21:54.473554
3317 13:21:54.475611 Set Vref Range= 32 -> 127
3318 13:21:54.476062
3319 13:21:54.478959 RX Vref 32 -> 127, step: 1
3320 13:21:54.479368
3321 13:21:54.482687 RX Delay -21 -> 252, step: 4
3322 13:21:54.483191
3323 13:21:54.485597 Set Vref, RX VrefLevel [Byte0]: 32
3324 13:21:54.489168 [Byte1]: 32
3325 13:21:54.489693
3326 13:21:54.492331 Set Vref, RX VrefLevel [Byte0]: 33
3327 13:21:54.495778 [Byte1]: 33
3328 13:21:54.498930
3329 13:21:54.499343 Set Vref, RX VrefLevel [Byte0]: 34
3330 13:21:54.502928 [Byte1]: 34
3331 13:21:54.507114
3332 13:21:54.507524 Set Vref, RX VrefLevel [Byte0]: 35
3333 13:21:54.510733 [Byte1]: 35
3334 13:21:54.514717
3335 13:21:54.515226 Set Vref, RX VrefLevel [Byte0]: 36
3336 13:21:54.518338 [Byte1]: 36
3337 13:21:54.522954
3338 13:21:54.523466 Set Vref, RX VrefLevel [Byte0]: 37
3339 13:21:54.525968 [Byte1]: 37
3340 13:21:54.530811
3341 13:21:54.531359 Set Vref, RX VrefLevel [Byte0]: 38
3342 13:21:54.534267 [Byte1]: 38
3343 13:21:54.538827
3344 13:21:54.539420 Set Vref, RX VrefLevel [Byte0]: 39
3345 13:21:54.542179 [Byte1]: 39
3346 13:21:54.546935
3347 13:21:54.550460 Set Vref, RX VrefLevel [Byte0]: 40
3348 13:21:54.551048 [Byte1]: 40
3349 13:21:54.554364
3350 13:21:54.554868 Set Vref, RX VrefLevel [Byte0]: 41
3351 13:21:54.557918 [Byte1]: 41
3352 13:21:54.562896
3353 13:21:54.563455 Set Vref, RX VrefLevel [Byte0]: 42
3354 13:21:54.565853 [Byte1]: 42
3355 13:21:54.570448
3356 13:21:54.571036 Set Vref, RX VrefLevel [Byte0]: 43
3357 13:21:54.573942 [Byte1]: 43
3358 13:21:54.579211
3359 13:21:54.579770 Set Vref, RX VrefLevel [Byte0]: 44
3360 13:21:54.582316 [Byte1]: 44
3361 13:21:54.586277
3362 13:21:54.586786 Set Vref, RX VrefLevel [Byte0]: 45
3363 13:21:54.589799 [Byte1]: 45
3364 13:21:54.594122
3365 13:21:54.594727 Set Vref, RX VrefLevel [Byte0]: 46
3366 13:21:54.597451 [Byte1]: 46
3367 13:21:54.602168
3368 13:21:54.602655 Set Vref, RX VrefLevel [Byte0]: 47
3369 13:21:54.605659 [Byte1]: 47
3370 13:21:54.610003
3371 13:21:54.610721 Set Vref, RX VrefLevel [Byte0]: 48
3372 13:21:54.613337 [Byte1]: 48
3373 13:21:54.618030
3374 13:21:54.618626 Set Vref, RX VrefLevel [Byte0]: 49
3375 13:21:54.621210 [Byte1]: 49
3376 13:21:54.626066
3377 13:21:54.626576 Set Vref, RX VrefLevel [Byte0]: 50
3378 13:21:54.629117 [Byte1]: 50
3379 13:21:54.634548
3380 13:21:54.635151 Set Vref, RX VrefLevel [Byte0]: 51
3381 13:21:54.636788 [Byte1]: 51
3382 13:21:54.642349
3383 13:21:54.642984 Set Vref, RX VrefLevel [Byte0]: 52
3384 13:21:54.645405 [Byte1]: 52
3385 13:21:54.649947
3386 13:21:54.650492 Set Vref, RX VrefLevel [Byte0]: 53
3387 13:21:54.652957 [Byte1]: 53
3388 13:21:54.658398
3389 13:21:54.659008 Set Vref, RX VrefLevel [Byte0]: 54
3390 13:21:54.661024 [Byte1]: 54
3391 13:21:54.665672
3392 13:21:54.666120 Set Vref, RX VrefLevel [Byte0]: 55
3393 13:21:54.668782 [Byte1]: 55
3394 13:21:54.673662
3395 13:21:54.674110 Set Vref, RX VrefLevel [Byte0]: 56
3396 13:21:54.676809 [Byte1]: 56
3397 13:21:54.681336
3398 13:21:54.681878 Set Vref, RX VrefLevel [Byte0]: 57
3399 13:21:54.685034 [Byte1]: 57
3400 13:21:54.689406
3401 13:21:54.689956 Set Vref, RX VrefLevel [Byte0]: 58
3402 13:21:54.692669 [Byte1]: 58
3403 13:21:54.697276
3404 13:21:54.697824 Set Vref, RX VrefLevel [Byte0]: 59
3405 13:21:54.700228 [Byte1]: 59
3406 13:21:54.705328
3407 13:21:54.705792 Set Vref, RX VrefLevel [Byte0]: 60
3408 13:21:54.709177 [Byte1]: 60
3409 13:21:54.713045
3410 13:21:54.713588 Set Vref, RX VrefLevel [Byte0]: 61
3411 13:21:54.716335 [Byte1]: 61
3412 13:21:54.721356
3413 13:21:54.721900 Set Vref, RX VrefLevel [Byte0]: 62
3414 13:21:54.724368 [Byte1]: 62
3415 13:21:54.729377
3416 13:21:54.729993 Set Vref, RX VrefLevel [Byte0]: 63
3417 13:21:54.732152 [Byte1]: 63
3418 13:21:54.737130
3419 13:21:54.737681 Set Vref, RX VrefLevel [Byte0]: 64
3420 13:21:54.740648 [Byte1]: 64
3421 13:21:54.744578
3422 13:21:54.745153 Set Vref, RX VrefLevel [Byte0]: 65
3423 13:21:54.747920 [Byte1]: 65
3424 13:21:54.752333
3425 13:21:54.752803 Set Vref, RX VrefLevel [Byte0]: 66
3426 13:21:54.755889 [Byte1]: 66
3427 13:21:54.760948
3428 13:21:54.761397 Set Vref, RX VrefLevel [Byte0]: 67
3429 13:21:54.763635 [Byte1]: 67
3430 13:21:54.768513
3431 13:21:54.769067 Set Vref, RX VrefLevel [Byte0]: 68
3432 13:21:54.772715 [Byte1]: 68
3433 13:21:54.776245
3434 13:21:54.776993 Final RX Vref Byte 0 = 50 to rank0
3435 13:21:54.780222 Final RX Vref Byte 1 = 54 to rank0
3436 13:21:54.783251 Final RX Vref Byte 0 = 50 to rank1
3437 13:21:54.786089 Final RX Vref Byte 1 = 54 to rank1==
3438 13:21:54.789306 Dram Type= 6, Freq= 0, CH_1, rank 0
3439 13:21:54.796792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3440 13:21:54.797364 ==
3441 13:21:54.797728 DQS Delay:
3442 13:21:54.798067 DQS0 = 0, DQS1 = 0
3443 13:21:54.800431 DQM Delay:
3444 13:21:54.800987 DQM0 = 115, DQM1 = 110
3445 13:21:54.803113 DQ Delay:
3446 13:21:54.806046 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =110
3447 13:21:54.810036 DQ4 =114, DQ5 =128, DQ6 =124, DQ7 =112
3448 13:21:54.813713 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =100
3449 13:21:54.816120 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3450 13:21:54.816679
3451 13:21:54.817042
3452 13:21:54.825922 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 409 ps
3453 13:21:54.826569 CH1 RK0: MR19=403, MR18=1F5
3454 13:21:54.832920 CH1_RK0: MR19=0x403, MR18=0x1F5, DQSOSC=409, MR23=63, INC=39, DEC=26
3455 13:21:54.833462
3456 13:21:54.835784 ----->DramcWriteLeveling(PI) begin...
3457 13:21:54.836248 ==
3458 13:21:54.840133 Dram Type= 6, Freq= 0, CH_1, rank 1
3459 13:21:54.845729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 13:21:54.846273 ==
3461 13:21:54.849053 Write leveling (Byte 0): 25 => 25
3462 13:21:54.849610 Write leveling (Byte 1): 30 => 30
3463 13:21:54.852126 DramcWriteLeveling(PI) end<-----
3464 13:21:54.852582
3465 13:21:54.852940 ==
3466 13:21:54.855650 Dram Type= 6, Freq= 0, CH_1, rank 1
3467 13:21:54.862214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3468 13:21:54.862737 ==
3469 13:21:54.866388 [Gating] SW mode calibration
3470 13:21:54.872189 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3471 13:21:54.875729 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3472 13:21:54.882058 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3473 13:21:54.885172 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3474 13:21:54.888539 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3475 13:21:54.895226 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3476 13:21:54.899263 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3477 13:21:54.902017 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 13:21:54.908614 0 15 24 | B1->B0 | 2f2f 3434 | 0 0 | (0 1) (0 0)
3479 13:21:54.911983 0 15 28 | B1->B0 | 2424 2525 | 0 0 | (1 0) (0 0)
3480 13:21:54.915894 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3481 13:21:54.922145 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3482 13:21:54.925234 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 13:21:54.928937 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 13:21:54.935098 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 13:21:54.938928 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3486 13:21:54.941425 1 0 24 | B1->B0 | 3a3a 3131 | 0 1 | (0 0) (1 1)
3487 13:21:54.948039 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 13:21:54.951277 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 13:21:54.954889 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 13:21:54.961362 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 13:21:54.964507 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 13:21:54.967803 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 13:21:54.975056 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 13:21:54.978194 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 13:21:54.981288 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3496 13:21:54.987761 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 13:21:54.991271 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 13:21:54.994240 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 13:21:55.001475 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 13:21:55.004836 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 13:21:55.007693 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 13:21:55.014452 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 13:21:55.018438 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 13:21:55.021036 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 13:21:55.027280 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 13:21:55.031006 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 13:21:55.034456 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 13:21:55.040718 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 13:21:55.044053 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 13:21:55.046926 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3511 13:21:55.053905 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3512 13:21:55.054468 Total UI for P1: 0, mck2ui 16
3513 13:21:55.060236 best dqsien dly found for B1: ( 1, 3, 24)
3514 13:21:55.064102 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 13:21:55.066870 Total UI for P1: 0, mck2ui 16
3516 13:21:55.069967 best dqsien dly found for B0: ( 1, 3, 28)
3517 13:21:55.073988 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3518 13:21:55.077813 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3519 13:21:55.078388
3520 13:21:55.081069 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3521 13:21:55.083800 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3522 13:21:55.086798 [Gating] SW calibration Done
3523 13:21:55.087349 ==
3524 13:21:55.090280 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 13:21:55.093711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 13:21:55.097106 ==
3527 13:21:55.097659 RX Vref Scan: 0
3528 13:21:55.098025
3529 13:21:55.100036 RX Vref 0 -> 0, step: 1
3530 13:21:55.100548
3531 13:21:55.103812 RX Delay -40 -> 252, step: 8
3532 13:21:55.106492 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3533 13:21:55.110008 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3534 13:21:55.113118 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3535 13:21:55.116753 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3536 13:21:55.123008 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3537 13:21:55.126904 iDelay=208, Bit 5, Center 123 (48 ~ 199) 152
3538 13:21:55.129564 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3539 13:21:55.132788 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3540 13:21:55.136442 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3541 13:21:55.143437 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3542 13:21:55.146322 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3543 13:21:55.149304 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3544 13:21:55.152801 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3545 13:21:55.156017 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3546 13:21:55.162869 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3547 13:21:55.166200 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3548 13:21:55.166831 ==
3549 13:21:55.169434 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 13:21:55.172680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 13:21:55.173251 ==
3552 13:21:55.176058 DQS Delay:
3553 13:21:55.176510 DQS0 = 0, DQS1 = 0
3554 13:21:55.176875 DQM Delay:
3555 13:21:55.179228 DQM0 = 116, DQM1 = 110
3556 13:21:55.179778 DQ Delay:
3557 13:21:55.182780 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3558 13:21:55.186143 DQ4 =115, DQ5 =123, DQ6 =131, DQ7 =115
3559 13:21:55.192289 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =103
3560 13:21:55.195395 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3561 13:21:55.195850
3562 13:21:55.196207
3563 13:21:55.196535 ==
3564 13:21:55.198753 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 13:21:55.202350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 13:21:55.202959 ==
3567 13:21:55.203322
3568 13:21:55.203669
3569 13:21:55.205242 TX Vref Scan disable
3570 13:21:55.209302 == TX Byte 0 ==
3571 13:21:55.211983 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3572 13:21:55.215739 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3573 13:21:55.218555 == TX Byte 1 ==
3574 13:21:55.222355 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3575 13:21:55.225201 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3576 13:21:55.225655 ==
3577 13:21:55.228458 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 13:21:55.231661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 13:21:55.234989 ==
3580 13:21:55.245800 TX Vref=22, minBit 9, minWin=24, winSum=420
3581 13:21:55.249402 TX Vref=24, minBit 8, minWin=25, winSum=425
3582 13:21:55.252030 TX Vref=26, minBit 9, minWin=24, winSum=426
3583 13:21:55.255391 TX Vref=28, minBit 8, minWin=26, winSum=434
3584 13:21:55.258523 TX Vref=30, minBit 8, minWin=26, winSum=433
3585 13:21:55.266007 TX Vref=32, minBit 8, minWin=26, winSum=431
3586 13:21:55.268686 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 28
3587 13:21:55.269245
3588 13:21:55.272031 Final TX Range 1 Vref 28
3589 13:21:55.272589
3590 13:21:55.272958 ==
3591 13:21:55.274998 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 13:21:55.278379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 13:21:55.282395 ==
3594 13:21:55.283007
3595 13:21:55.283373
3596 13:21:55.283709 TX Vref Scan disable
3597 13:21:55.285420 == TX Byte 0 ==
3598 13:21:55.289046 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3599 13:21:55.295506 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3600 13:21:55.296089 == TX Byte 1 ==
3601 13:21:55.298828 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3602 13:21:55.304985 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3603 13:21:55.305440
3604 13:21:55.305800 [DATLAT]
3605 13:21:55.306134 Freq=1200, CH1 RK1
3606 13:21:55.306586
3607 13:21:55.308327 DATLAT Default: 0xd
3608 13:21:55.311170 0, 0xFFFF, sum = 0
3609 13:21:55.311637 1, 0xFFFF, sum = 0
3610 13:21:55.314850 2, 0xFFFF, sum = 0
3611 13:21:55.315431 3, 0xFFFF, sum = 0
3612 13:21:55.318303 4, 0xFFFF, sum = 0
3613 13:21:55.318898 5, 0xFFFF, sum = 0
3614 13:21:55.321339 6, 0xFFFF, sum = 0
3615 13:21:55.321914 7, 0xFFFF, sum = 0
3616 13:21:55.324842 8, 0xFFFF, sum = 0
3617 13:21:55.325401 9, 0xFFFF, sum = 0
3618 13:21:55.327963 10, 0xFFFF, sum = 0
3619 13:21:55.328425 11, 0xFFFF, sum = 0
3620 13:21:55.330913 12, 0x0, sum = 1
3621 13:21:55.331376 13, 0x0, sum = 2
3622 13:21:55.334631 14, 0x0, sum = 3
3623 13:21:55.335227 15, 0x0, sum = 4
3624 13:21:55.338648 best_step = 13
3625 13:21:55.339233
3626 13:21:55.339732 ==
3627 13:21:55.341018 Dram Type= 6, Freq= 0, CH_1, rank 1
3628 13:21:55.344272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3629 13:21:55.344754 ==
3630 13:21:55.347829 RX Vref Scan: 0
3631 13:21:55.348428
3632 13:21:55.348929 RX Vref 0 -> 0, step: 1
3633 13:21:55.349390
3634 13:21:55.351001 RX Delay -21 -> 252, step: 4
3635 13:21:55.358106 iDelay=203, Bit 0, Center 120 (51 ~ 190) 140
3636 13:21:55.361073 iDelay=203, Bit 1, Center 110 (43 ~ 178) 136
3637 13:21:55.364214 iDelay=203, Bit 2, Center 108 (43 ~ 174) 132
3638 13:21:55.367884 iDelay=203, Bit 3, Center 112 (47 ~ 178) 132
3639 13:21:55.371120 iDelay=203, Bit 4, Center 116 (47 ~ 186) 140
3640 13:21:55.377834 iDelay=203, Bit 5, Center 126 (59 ~ 194) 136
3641 13:21:55.380553 iDelay=203, Bit 6, Center 130 (59 ~ 202) 144
3642 13:21:55.383962 iDelay=203, Bit 7, Center 116 (51 ~ 182) 132
3643 13:21:55.387427 iDelay=203, Bit 8, Center 98 (31 ~ 166) 136
3644 13:21:55.390669 iDelay=203, Bit 9, Center 100 (35 ~ 166) 132
3645 13:21:55.397497 iDelay=203, Bit 10, Center 110 (43 ~ 178) 136
3646 13:21:55.400338 iDelay=203, Bit 11, Center 100 (35 ~ 166) 132
3647 13:21:55.403710 iDelay=203, Bit 12, Center 118 (51 ~ 186) 136
3648 13:21:55.407082 iDelay=203, Bit 13, Center 118 (51 ~ 186) 136
3649 13:21:55.413819 iDelay=203, Bit 14, Center 118 (51 ~ 186) 136
3650 13:21:55.416899 iDelay=203, Bit 15, Center 120 (51 ~ 190) 140
3651 13:21:55.417456 ==
3652 13:21:55.420045 Dram Type= 6, Freq= 0, CH_1, rank 1
3653 13:21:55.424007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3654 13:21:55.424476 ==
3655 13:21:55.426566 DQS Delay:
3656 13:21:55.427083 DQS0 = 0, DQS1 = 0
3657 13:21:55.427510 DQM Delay:
3658 13:21:55.430350 DQM0 = 117, DQM1 = 110
3659 13:21:55.430960 DQ Delay:
3660 13:21:55.433601 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3661 13:21:55.436738 DQ4 =116, DQ5 =126, DQ6 =130, DQ7 =116
3662 13:21:55.443483 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =100
3663 13:21:55.446503 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3664 13:21:55.447111
3665 13:21:55.447482
3666 13:21:55.452722 [DQSOSCAuto] RK1, (LSB)MR18= 0xf4ef, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3667 13:21:55.456066 CH1 RK1: MR19=303, MR18=F4EF
3668 13:21:55.462940 CH1_RK1: MR19=0x303, MR18=0xF4EF, DQSOSC=415, MR23=63, INC=38, DEC=25
3669 13:21:55.466395 [RxdqsGatingPostProcess] freq 1200
3670 13:21:55.472847 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3671 13:21:55.473410 best DQS0 dly(2T, 0.5T) = (0, 11)
3672 13:21:55.476256 best DQS1 dly(2T, 0.5T) = (0, 11)
3673 13:21:55.479384 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3674 13:21:55.482704 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3675 13:21:55.485878 best DQS0 dly(2T, 0.5T) = (0, 11)
3676 13:21:55.489242 best DQS1 dly(2T, 0.5T) = (0, 11)
3677 13:21:55.492686 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3678 13:21:55.497004 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3679 13:21:55.498877 Pre-setting of DQS Precalculation
3680 13:21:55.506207 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3681 13:21:55.512319 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3682 13:21:55.519018 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3683 13:21:55.519574
3684 13:21:55.519939
3685 13:21:55.522182 [Calibration Summary] 2400 Mbps
3686 13:21:55.522786 CH 0, Rank 0
3687 13:21:55.526032 SW Impedance : PASS
3688 13:21:55.528913 DUTY Scan : NO K
3689 13:21:55.529378 ZQ Calibration : PASS
3690 13:21:55.532373 Jitter Meter : NO K
3691 13:21:55.535464 CBT Training : PASS
3692 13:21:55.536017 Write leveling : PASS
3693 13:21:55.538669 RX DQS gating : PASS
3694 13:21:55.542453 RX DQ/DQS(RDDQC) : PASS
3695 13:21:55.543087 TX DQ/DQS : PASS
3696 13:21:55.545928 RX DATLAT : PASS
3697 13:21:55.548604 RX DQ/DQS(Engine): PASS
3698 13:21:55.549295 TX OE : NO K
3699 13:21:55.549785 All Pass.
3700 13:21:55.551987
3701 13:21:55.552578 CH 0, Rank 1
3702 13:21:55.555062 SW Impedance : PASS
3703 13:21:55.555538 DUTY Scan : NO K
3704 13:21:55.558489 ZQ Calibration : PASS
3705 13:21:55.561927 Jitter Meter : NO K
3706 13:21:55.562419 CBT Training : PASS
3707 13:21:55.565360 Write leveling : PASS
3708 13:21:55.565938 RX DQS gating : PASS
3709 13:21:55.568665 RX DQ/DQS(RDDQC) : PASS
3710 13:21:55.571385 TX DQ/DQS : PASS
3711 13:21:55.571864 RX DATLAT : PASS
3712 13:21:55.575338 RX DQ/DQS(Engine): PASS
3713 13:21:55.578675 TX OE : NO K
3714 13:21:55.579262 All Pass.
3715 13:21:55.579764
3716 13:21:55.580227 CH 1, Rank 0
3717 13:21:55.581542 SW Impedance : PASS
3718 13:21:55.585150 DUTY Scan : NO K
3719 13:21:55.585732 ZQ Calibration : PASS
3720 13:21:55.588351 Jitter Meter : NO K
3721 13:21:55.591392 CBT Training : PASS
3722 13:21:55.591869 Write leveling : PASS
3723 13:21:55.595176 RX DQS gating : PASS
3724 13:21:55.598785 RX DQ/DQS(RDDQC) : PASS
3725 13:21:55.599357 TX DQ/DQS : PASS
3726 13:21:55.601851 RX DATLAT : PASS
3727 13:21:55.604546 RX DQ/DQS(Engine): PASS
3728 13:21:55.605023 TX OE : NO K
3729 13:21:55.608315 All Pass.
3730 13:21:55.608895
3731 13:21:55.609388 CH 1, Rank 1
3732 13:21:55.611124 SW Impedance : PASS
3733 13:21:55.611602 DUTY Scan : NO K
3734 13:21:55.614703 ZQ Calibration : PASS
3735 13:21:55.617978 Jitter Meter : NO K
3736 13:21:55.618564 CBT Training : PASS
3737 13:21:55.621249 Write leveling : PASS
3738 13:21:55.625115 RX DQS gating : PASS
3739 13:21:55.625692 RX DQ/DQS(RDDQC) : PASS
3740 13:21:55.627849 TX DQ/DQS : PASS
3741 13:21:55.628333 RX DATLAT : PASS
3742 13:21:55.631296 RX DQ/DQS(Engine): PASS
3743 13:21:55.634279 TX OE : NO K
3744 13:21:55.634888 All Pass.
3745 13:21:55.635305
3746 13:21:55.637935 DramC Write-DBI off
3747 13:21:55.638687 PER_BANK_REFRESH: Hybrid Mode
3748 13:21:55.641192 TX_TRACKING: ON
3749 13:21:55.650862 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3750 13:21:55.654765 [FAST_K] Save calibration result to emmc
3751 13:21:55.657551 dramc_set_vcore_voltage set vcore to 650000
3752 13:21:55.658160 Read voltage for 600, 5
3753 13:21:55.660871 Vio18 = 0
3754 13:21:55.661452 Vcore = 650000
3755 13:21:55.661845 Vdram = 0
3756 13:21:55.664617 Vddq = 0
3757 13:21:55.665253 Vmddr = 0
3758 13:21:55.671050 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3759 13:21:55.674127 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3760 13:21:55.678051 MEM_TYPE=3, freq_sel=19
3761 13:21:55.681227 sv_algorithm_assistance_LP4_1600
3762 13:21:55.685347 ============ PULL DRAM RESETB DOWN ============
3763 13:21:55.687247 ========== PULL DRAM RESETB DOWN end =========
3764 13:21:55.694155 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3765 13:21:55.696954 ===================================
3766 13:21:55.697431 LPDDR4 DRAM CONFIGURATION
3767 13:21:55.700908 ===================================
3768 13:21:55.704786 EX_ROW_EN[0] = 0x0
3769 13:21:55.707038 EX_ROW_EN[1] = 0x0
3770 13:21:55.707509 LP4Y_EN = 0x0
3771 13:21:55.710201 WORK_FSP = 0x0
3772 13:21:55.710849 WL = 0x2
3773 13:21:55.714018 RL = 0x2
3774 13:21:55.714472 BL = 0x2
3775 13:21:55.717310 RPST = 0x0
3776 13:21:55.717932 RD_PRE = 0x0
3777 13:21:55.720432 WR_PRE = 0x1
3778 13:21:55.720986 WR_PST = 0x0
3779 13:21:55.723901 DBI_WR = 0x0
3780 13:21:55.724477 DBI_RD = 0x0
3781 13:21:55.726764 OTF = 0x1
3782 13:21:55.729940 ===================================
3783 13:21:55.733618 ===================================
3784 13:21:55.734177 ANA top config
3785 13:21:55.737272 ===================================
3786 13:21:55.741038 DLL_ASYNC_EN = 0
3787 13:21:55.743386 ALL_SLAVE_EN = 1
3788 13:21:55.746766 NEW_RANK_MODE = 1
3789 13:21:55.747223 DLL_IDLE_MODE = 1
3790 13:21:55.749748 LP45_APHY_COMB_EN = 1
3791 13:21:55.753347 TX_ODT_DIS = 1
3792 13:21:55.757798 NEW_8X_MODE = 1
3793 13:21:55.759392 ===================================
3794 13:21:55.763355 ===================================
3795 13:21:55.766335 data_rate = 1200
3796 13:21:55.769758 CKR = 1
3797 13:21:55.770313 DQ_P2S_RATIO = 8
3798 13:21:55.772776 ===================================
3799 13:21:55.776298 CA_P2S_RATIO = 8
3800 13:21:55.779161 DQ_CA_OPEN = 0
3801 13:21:55.782758 DQ_SEMI_OPEN = 0
3802 13:21:55.786200 CA_SEMI_OPEN = 0
3803 13:21:55.789482 CA_FULL_RATE = 0
3804 13:21:55.790035 DQ_CKDIV4_EN = 1
3805 13:21:55.792777 CA_CKDIV4_EN = 1
3806 13:21:55.795730 CA_PREDIV_EN = 0
3807 13:21:55.799040 PH8_DLY = 0
3808 13:21:55.802794 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3809 13:21:55.806493 DQ_AAMCK_DIV = 4
3810 13:21:55.807099 CA_AAMCK_DIV = 4
3811 13:21:55.809412 CA_ADMCK_DIV = 4
3812 13:21:55.813216 DQ_TRACK_CA_EN = 0
3813 13:21:55.816221 CA_PICK = 600
3814 13:21:55.818910 CA_MCKIO = 600
3815 13:21:55.822679 MCKIO_SEMI = 0
3816 13:21:55.825647 PLL_FREQ = 2288
3817 13:21:55.826225 DQ_UI_PI_RATIO = 32
3818 13:21:55.829687 CA_UI_PI_RATIO = 0
3819 13:21:55.832688 ===================================
3820 13:21:55.836361 ===================================
3821 13:21:55.839015 memory_type:LPDDR4
3822 13:21:55.842959 GP_NUM : 10
3823 13:21:55.843616 SRAM_EN : 1
3824 13:21:55.845552 MD32_EN : 0
3825 13:21:55.848764 ===================================
3826 13:21:55.851848 [ANA_INIT] >>>>>>>>>>>>>>
3827 13:21:55.855418 <<<<<< [CONFIGURE PHASE]: ANA_TX
3828 13:21:55.858684 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3829 13:21:55.861959 ===================================
3830 13:21:55.862415 data_rate = 1200,PCW = 0X5800
3831 13:21:55.865614 ===================================
3832 13:21:55.868533 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3833 13:21:55.875259 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3834 13:21:55.881988 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3835 13:21:55.885508 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3836 13:21:55.888420 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3837 13:21:55.892836 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3838 13:21:55.896087 [ANA_INIT] flow start
3839 13:21:55.896637 [ANA_INIT] PLL >>>>>>>>
3840 13:21:55.898258 [ANA_INIT] PLL <<<<<<<<
3841 13:21:55.901891 [ANA_INIT] MIDPI >>>>>>>>
3842 13:21:55.904956 [ANA_INIT] MIDPI <<<<<<<<
3843 13:21:55.905530 [ANA_INIT] DLL >>>>>>>>
3844 13:21:55.908334 [ANA_INIT] flow end
3845 13:21:55.911705 ============ LP4 DIFF to SE enter ============
3846 13:21:55.914902 ============ LP4 DIFF to SE exit ============
3847 13:21:55.918878 [ANA_INIT] <<<<<<<<<<<<<
3848 13:21:55.921348 [Flow] Enable top DCM control >>>>>
3849 13:21:55.925291 [Flow] Enable top DCM control <<<<<
3850 13:21:55.928064 Enable DLL master slave shuffle
3851 13:21:55.934823 ==============================================================
3852 13:21:55.935378 Gating Mode config
3853 13:21:55.941228 ==============================================================
3854 13:21:55.941788 Config description:
3855 13:21:55.951237 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3856 13:21:55.957335 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3857 13:21:55.964382 SELPH_MODE 0: By rank 1: By Phase
3858 13:21:55.970669 ==============================================================
3859 13:21:55.971210 GAT_TRACK_EN = 1
3860 13:21:55.974683 RX_GATING_MODE = 2
3861 13:21:55.977706 RX_GATING_TRACK_MODE = 2
3862 13:21:55.980805 SELPH_MODE = 1
3863 13:21:55.984017 PICG_EARLY_EN = 1
3864 13:21:55.988330 VALID_LAT_VALUE = 1
3865 13:21:55.993861 ==============================================================
3866 13:21:55.997824 Enter into Gating configuration >>>>
3867 13:21:56.000592 Exit from Gating configuration <<<<
3868 13:21:56.003982 Enter into DVFS_PRE_config >>>>>
3869 13:21:56.013562 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3870 13:21:56.017340 Exit from DVFS_PRE_config <<<<<
3871 13:21:56.020246 Enter into PICG configuration >>>>
3872 13:21:56.023483 Exit from PICG configuration <<<<
3873 13:21:56.027042 [RX_INPUT] configuration >>>>>
3874 13:21:56.030145 [RX_INPUT] configuration <<<<<
3875 13:21:56.033281 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3876 13:21:56.040143 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3877 13:21:56.047458 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3878 13:21:56.052920 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3879 13:21:56.056403 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3880 13:21:56.062803 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3881 13:21:56.066930 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3882 13:21:56.072941 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3883 13:21:56.076517 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3884 13:21:56.080104 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3885 13:21:56.082987 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3886 13:21:56.089434 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3887 13:21:56.092940 ===================================
3888 13:21:56.093412 LPDDR4 DRAM CONFIGURATION
3889 13:21:56.095913 ===================================
3890 13:21:56.099867 EX_ROW_EN[0] = 0x0
3891 13:21:56.103093 EX_ROW_EN[1] = 0x0
3892 13:21:56.103551 LP4Y_EN = 0x0
3893 13:21:56.105863 WORK_FSP = 0x0
3894 13:21:56.106274 WL = 0x2
3895 13:21:56.109562 RL = 0x2
3896 13:21:56.110077 BL = 0x2
3897 13:21:56.112747 RPST = 0x0
3898 13:21:56.113260 RD_PRE = 0x0
3899 13:21:56.116298 WR_PRE = 0x1
3900 13:21:56.116877 WR_PST = 0x0
3901 13:21:56.119014 DBI_WR = 0x0
3902 13:21:56.119425 DBI_RD = 0x0
3903 13:21:56.122515 OTF = 0x1
3904 13:21:56.126092 ===================================
3905 13:21:56.129050 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3906 13:21:56.132656 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3907 13:21:56.139279 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3908 13:21:56.142499 ===================================
3909 13:21:56.145856 LPDDR4 DRAM CONFIGURATION
3910 13:21:56.148928 ===================================
3911 13:21:56.149495 EX_ROW_EN[0] = 0x10
3912 13:21:56.151987 EX_ROW_EN[1] = 0x0
3913 13:21:56.152448 LP4Y_EN = 0x0
3914 13:21:56.155632 WORK_FSP = 0x0
3915 13:21:56.156103 WL = 0x2
3916 13:21:56.158858 RL = 0x2
3917 13:21:56.159411 BL = 0x2
3918 13:21:56.161918 RPST = 0x0
3919 13:21:56.162374 RD_PRE = 0x0
3920 13:21:56.165428 WR_PRE = 0x1
3921 13:21:56.165979 WR_PST = 0x0
3922 13:21:56.168802 DBI_WR = 0x0
3923 13:21:56.169354 DBI_RD = 0x0
3924 13:21:56.172099 OTF = 0x1
3925 13:21:56.175196 ===================================
3926 13:21:56.182010 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3927 13:21:56.185010 nWR fixed to 30
3928 13:21:56.188719 [ModeRegInit_LP4] CH0 RK0
3929 13:21:56.189319 [ModeRegInit_LP4] CH0 RK1
3930 13:21:56.191572 [ModeRegInit_LP4] CH1 RK0
3931 13:21:56.194806 [ModeRegInit_LP4] CH1 RK1
3932 13:21:56.195262 match AC timing 17
3933 13:21:56.201711 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3934 13:21:56.205358 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3935 13:21:56.208423 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3936 13:21:56.215601 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3937 13:21:56.217794 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3938 13:21:56.218251 ==
3939 13:21:56.221759 Dram Type= 6, Freq= 0, CH_0, rank 0
3940 13:21:56.225474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3941 13:21:56.226026 ==
3942 13:21:56.231304 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3943 13:21:56.238562 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3944 13:21:56.241492 [CA 0] Center 36 (6~66) winsize 61
3945 13:21:56.244587 [CA 1] Center 36 (6~66) winsize 61
3946 13:21:56.247870 [CA 2] Center 34 (4~65) winsize 62
3947 13:21:56.251577 [CA 3] Center 34 (3~65) winsize 63
3948 13:21:56.254710 [CA 4] Center 33 (3~64) winsize 62
3949 13:21:56.257995 [CA 5] Center 33 (3~64) winsize 62
3950 13:21:56.258549
3951 13:21:56.261839 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3952 13:21:56.262564
3953 13:21:56.264433 [CATrainingPosCal] consider 1 rank data
3954 13:21:56.268171 u2DelayCellTimex100 = 270/100 ps
3955 13:21:56.270912 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3956 13:21:56.274447 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3957 13:21:56.278373 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3958 13:21:56.283897 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3959 13:21:56.287182 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3960 13:21:56.291108 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3961 13:21:56.291613
3962 13:21:56.294288 CA PerBit enable=1, Macro0, CA PI delay=33
3963 13:21:56.294885
3964 13:21:56.297432 [CBTSetCACLKResult] CA Dly = 33
3965 13:21:56.297998 CS Dly: 6 (0~37)
3966 13:21:56.298362 ==
3967 13:21:56.300646 Dram Type= 6, Freq= 0, CH_0, rank 1
3968 13:21:56.307057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 13:21:56.307514 ==
3970 13:21:56.310331 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3971 13:21:56.317770 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3972 13:21:56.320739 [CA 0] Center 36 (6~66) winsize 61
3973 13:21:56.323929 [CA 1] Center 36 (6~66) winsize 61
3974 13:21:56.327336 [CA 2] Center 34 (3~65) winsize 63
3975 13:21:56.330034 [CA 3] Center 34 (4~64) winsize 61
3976 13:21:56.334023 [CA 4] Center 33 (3~64) winsize 62
3977 13:21:56.337289 [CA 5] Center 33 (3~64) winsize 62
3978 13:21:56.337820
3979 13:21:56.340120 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3980 13:21:56.340549
3981 13:21:56.343696 [CATrainingPosCal] consider 2 rank data
3982 13:21:56.346887 u2DelayCellTimex100 = 270/100 ps
3983 13:21:56.350082 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3984 13:21:56.356855 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3985 13:21:56.360204 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3986 13:21:56.363868 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3987 13:21:56.366753 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3988 13:21:56.370386 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3989 13:21:56.370971
3990 13:21:56.373662 CA PerBit enable=1, Macro0, CA PI delay=33
3991 13:21:56.374192
3992 13:21:56.376930 [CBTSetCACLKResult] CA Dly = 33
3993 13:21:56.380532 CS Dly: 5 (0~36)
3994 13:21:56.381064
3995 13:21:56.383085 ----->DramcWriteLeveling(PI) begin...
3996 13:21:56.383505 ==
3997 13:21:56.386275 Dram Type= 6, Freq= 0, CH_0, rank 0
3998 13:21:56.390498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3999 13:21:56.391061 ==
4000 13:21:56.393473 Write leveling (Byte 0): 33 => 33
4001 13:21:56.397264 Write leveling (Byte 1): 32 => 32
4002 13:21:56.399755 DramcWriteLeveling(PI) end<-----
4003 13:21:56.400267
4004 13:21:56.400597 ==
4005 13:21:56.403461 Dram Type= 6, Freq= 0, CH_0, rank 0
4006 13:21:56.406793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 13:21:56.407349 ==
4008 13:21:56.409847 [Gating] SW mode calibration
4009 13:21:56.416295 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4010 13:21:56.423077 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4011 13:21:56.426555 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4012 13:21:56.430066 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4013 13:21:56.436129 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4014 13:21:56.439776 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4015 13:21:56.442465 0 9 16 | B1->B0 | 2727 2424 | 1 0 | (1 0) (0 0)
4016 13:21:56.449378 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 13:21:56.453089 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 13:21:56.455861 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 13:21:56.462356 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 13:21:56.466137 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 13:21:56.469551 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 13:21:56.475518 0 10 12 | B1->B0 | 2929 2424 | 0 0 | (0 0) (0 0)
4023 13:21:56.479359 0 10 16 | B1->B0 | 3535 4242 | 0 0 | (0 0) (0 0)
4024 13:21:56.482323 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 13:21:56.488518 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 13:21:56.492171 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 13:21:56.496132 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 13:21:56.501919 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 13:21:56.505495 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 13:21:56.508513 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4031 13:21:56.516001 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4032 13:21:56.518190 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 13:21:56.522309 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 13:21:56.528273 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 13:21:56.531730 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 13:21:56.535411 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 13:21:56.541954 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 13:21:56.544820 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 13:21:56.548627 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 13:21:56.555038 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 13:21:56.558199 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 13:21:56.561285 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 13:21:56.569318 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 13:21:56.571112 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 13:21:56.574980 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 13:21:56.581382 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 13:21:56.584598 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 13:21:56.587657 Total UI for P1: 0, mck2ui 16
4049 13:21:56.591210 best dqsien dly found for B0: ( 0, 13, 14)
4050 13:21:56.595051 Total UI for P1: 0, mck2ui 16
4051 13:21:56.598446 best dqsien dly found for B1: ( 0, 13, 14)
4052 13:21:56.601276 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4053 13:21:56.605169 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4054 13:21:56.605741
4055 13:21:56.607963 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4056 13:21:56.611336 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4057 13:21:56.614653 [Gating] SW calibration Done
4058 13:21:56.615228 ==
4059 13:21:56.617599 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 13:21:56.624356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 13:21:56.624942 ==
4062 13:21:56.625436 RX Vref Scan: 0
4063 13:21:56.625895
4064 13:21:56.627306 RX Vref 0 -> 0, step: 1
4065 13:21:56.627793
4066 13:21:56.630766 RX Delay -230 -> 252, step: 16
4067 13:21:56.634820 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4068 13:21:56.637580 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4069 13:21:56.640924 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4070 13:21:56.647428 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4071 13:21:56.651014 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4072 13:21:56.654344 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4073 13:21:56.657401 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4074 13:21:56.663751 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4075 13:21:56.667564 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4076 13:21:56.671020 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4077 13:21:56.673560 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4078 13:21:56.680806 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4079 13:21:56.683387 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4080 13:21:56.686658 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4081 13:21:56.689936 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4082 13:21:56.696701 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4083 13:21:56.697254 ==
4084 13:21:56.699876 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 13:21:56.702970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 13:21:56.703430 ==
4087 13:21:56.703789 DQS Delay:
4088 13:21:56.706836 DQS0 = 0, DQS1 = 0
4089 13:21:56.707297 DQM Delay:
4090 13:21:56.710055 DQM0 = 42, DQM1 = 29
4091 13:21:56.710465 DQ Delay:
4092 13:21:56.712971 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4093 13:21:56.716583 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =49
4094 13:21:56.719954 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4095 13:21:56.723445 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4096 13:21:56.723949
4097 13:21:56.724281
4098 13:21:56.724585 ==
4099 13:21:56.726658 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 13:21:56.729319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 13:21:56.729737 ==
4102 13:21:56.730125
4103 13:21:56.732898
4104 13:21:56.733311 TX Vref Scan disable
4105 13:21:56.736248 == TX Byte 0 ==
4106 13:21:56.739638 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4107 13:21:56.742999 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4108 13:21:56.746185 == TX Byte 1 ==
4109 13:21:56.750019 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4110 13:21:56.752429 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4111 13:21:56.755827 ==
4112 13:21:56.756244 Dram Type= 6, Freq= 0, CH_0, rank 0
4113 13:21:56.762921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4114 13:21:56.763445 ==
4115 13:21:56.763782
4116 13:21:56.764085
4117 13:21:56.765941 TX Vref Scan disable
4118 13:21:56.766354 == TX Byte 0 ==
4119 13:21:56.772256 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4120 13:21:56.776101 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4121 13:21:56.776662 == TX Byte 1 ==
4122 13:21:56.782718 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4123 13:21:56.786487 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4124 13:21:56.787095
4125 13:21:56.787471 [DATLAT]
4126 13:21:56.789435 Freq=600, CH0 RK0
4127 13:21:56.789906
4128 13:21:56.790263 DATLAT Default: 0x9
4129 13:21:56.792950 0, 0xFFFF, sum = 0
4130 13:21:56.793515 1, 0xFFFF, sum = 0
4131 13:21:56.796304 2, 0xFFFF, sum = 0
4132 13:21:56.796871 3, 0xFFFF, sum = 0
4133 13:21:56.799051 4, 0xFFFF, sum = 0
4134 13:21:56.802420 5, 0xFFFF, sum = 0
4135 13:21:56.802921 6, 0xFFFF, sum = 0
4136 13:21:56.805581 7, 0xFFFF, sum = 0
4137 13:21:56.806041 8, 0x0, sum = 1
4138 13:21:56.806409 9, 0x0, sum = 2
4139 13:21:56.809109 10, 0x0, sum = 3
4140 13:21:56.809670 11, 0x0, sum = 4
4141 13:21:56.813104 best_step = 9
4142 13:21:56.813669
4143 13:21:56.814033 ==
4144 13:21:56.815415 Dram Type= 6, Freq= 0, CH_0, rank 0
4145 13:21:56.819183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 13:21:56.819747 ==
4147 13:21:56.822358 RX Vref Scan: 1
4148 13:21:56.822953
4149 13:21:56.823322 RX Vref 0 -> 0, step: 1
4150 13:21:56.823660
4151 13:21:56.825899 RX Delay -195 -> 252, step: 8
4152 13:21:56.826461
4153 13:21:56.828574 Set Vref, RX VrefLevel [Byte0]: 61
4154 13:21:56.831910 [Byte1]: 48
4155 13:21:56.836404
4156 13:21:56.836955 Final RX Vref Byte 0 = 61 to rank0
4157 13:21:56.839741 Final RX Vref Byte 1 = 48 to rank0
4158 13:21:56.842841 Final RX Vref Byte 0 = 61 to rank1
4159 13:21:56.845930 Final RX Vref Byte 1 = 48 to rank1==
4160 13:21:56.849474 Dram Type= 6, Freq= 0, CH_0, rank 0
4161 13:21:56.855778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 13:21:56.856243 ==
4163 13:21:56.856609 DQS Delay:
4164 13:21:56.859340 DQS0 = 0, DQS1 = 0
4165 13:21:56.859797 DQM Delay:
4166 13:21:56.860156 DQM0 = 43, DQM1 = 32
4167 13:21:56.862574 DQ Delay:
4168 13:21:56.865774 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4169 13:21:56.869376 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4170 13:21:56.872965 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =24
4171 13:21:56.876077 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4172 13:21:56.876629
4173 13:21:56.876988
4174 13:21:56.882753 [DQSOSCAuto] RK0, (LSB)MR18= 0x6b42, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 389 ps
4175 13:21:56.886643 CH0 RK0: MR19=808, MR18=6B42
4176 13:21:56.892501 CH0_RK0: MR19=0x808, MR18=0x6B42, DQSOSC=389, MR23=63, INC=173, DEC=115
4177 13:21:56.893075
4178 13:21:56.896090 ----->DramcWriteLeveling(PI) begin...
4179 13:21:56.896553 ==
4180 13:21:56.898891 Dram Type= 6, Freq= 0, CH_0, rank 1
4181 13:21:56.902902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 13:21:56.903459 ==
4183 13:21:56.905761 Write leveling (Byte 0): 31 => 31
4184 13:21:56.909238 Write leveling (Byte 1): 30 => 30
4185 13:21:56.912418 DramcWriteLeveling(PI) end<-----
4186 13:21:56.912970
4187 13:21:56.913330 ==
4188 13:21:56.915283 Dram Type= 6, Freq= 0, CH_0, rank 1
4189 13:21:56.918782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 13:21:56.922466 ==
4191 13:21:56.923071 [Gating] SW mode calibration
4192 13:21:56.931940 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4193 13:21:56.934906 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4194 13:21:56.939040 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4195 13:21:56.945099 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4196 13:21:56.948534 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4197 13:21:56.951641 0 9 12 | B1->B0 | 3434 3333 | 0 1 | (0 1) (1 0)
4198 13:21:56.958010 0 9 16 | B1->B0 | 2e2e 2929 | 1 0 | (1 0) (0 0)
4199 13:21:56.961472 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 13:21:56.964701 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 13:21:56.971415 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 13:21:56.974745 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 13:21:56.978219 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 13:21:56.984753 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 13:21:56.988433 0 10 12 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
4206 13:21:56.991494 0 10 16 | B1->B0 | 3b3b 3f3f | 0 0 | (0 0) (0 0)
4207 13:21:56.997564 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 13:21:57.001526 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 13:21:57.004256 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 13:21:57.010781 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 13:21:57.014675 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 13:21:57.017369 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4213 13:21:57.024055 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4214 13:21:57.027809 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 13:21:57.030534 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 13:21:57.037338 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 13:21:57.040856 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 13:21:57.044249 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 13:21:57.050474 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 13:21:57.053995 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 13:21:57.057395 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 13:21:57.063551 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 13:21:57.067097 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 13:21:57.070565 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 13:21:57.076883 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 13:21:57.080308 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 13:21:57.083593 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 13:21:57.090142 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 13:21:57.093960 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 13:21:57.096877 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4231 13:21:57.099980 Total UI for P1: 0, mck2ui 16
4232 13:21:57.103828 best dqsien dly found for B0: ( 0, 13, 14)
4233 13:21:57.110676 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 13:21:57.111230 Total UI for P1: 0, mck2ui 16
4235 13:21:57.116916 best dqsien dly found for B1: ( 0, 13, 16)
4236 13:21:57.119987 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4237 13:21:57.122984 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4238 13:21:57.123445
4239 13:21:57.126086 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4240 13:21:57.129693 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4241 13:21:57.132803 [Gating] SW calibration Done
4242 13:21:57.133259 ==
4243 13:21:57.136476 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 13:21:57.140530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 13:21:57.141096 ==
4246 13:21:57.143102 RX Vref Scan: 0
4247 13:21:57.143570
4248 13:21:57.146329 RX Vref 0 -> 0, step: 1
4249 13:21:57.146946
4250 13:21:57.147315 RX Delay -230 -> 252, step: 16
4251 13:21:57.153262 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4252 13:21:57.155796 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4253 13:21:57.159240 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4254 13:21:57.163019 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4255 13:21:57.169412 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4256 13:21:57.172657 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4257 13:21:57.175822 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4258 13:21:57.179945 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4259 13:21:57.185965 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4260 13:21:57.189408 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4261 13:21:57.192261 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4262 13:21:57.195541 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4263 13:21:57.202234 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4264 13:21:57.205993 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4265 13:21:57.208627 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4266 13:21:57.212100 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4267 13:21:57.212655 ==
4268 13:21:57.215215 Dram Type= 6, Freq= 0, CH_0, rank 1
4269 13:21:57.222442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4270 13:21:57.223044 ==
4271 13:21:57.223415 DQS Delay:
4272 13:21:57.225611 DQS0 = 0, DQS1 = 0
4273 13:21:57.226167 DQM Delay:
4274 13:21:57.226679 DQM0 = 47, DQM1 = 42
4275 13:21:57.230424 DQ Delay:
4276 13:21:57.232085 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4277 13:21:57.235138 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =57
4278 13:21:57.238242 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4279 13:21:57.241441 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4280 13:21:57.241901
4281 13:21:57.242265
4282 13:21:57.242650 ==
4283 13:21:57.245265 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 13:21:57.248060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 13:21:57.248523 ==
4286 13:21:57.248887
4287 13:21:57.249218
4288 13:21:57.251493 TX Vref Scan disable
4289 13:21:57.254702 == TX Byte 0 ==
4290 13:21:57.258214 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4291 13:21:57.261168 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4292 13:21:57.265213 == TX Byte 1 ==
4293 13:21:57.267839 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4294 13:21:57.271299 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4295 13:21:57.271852 ==
4296 13:21:57.274984 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 13:21:57.281221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 13:21:57.281775 ==
4299 13:21:57.282139
4300 13:21:57.282474
4301 13:21:57.282889 TX Vref Scan disable
4302 13:21:57.285115 == TX Byte 0 ==
4303 13:21:57.288779 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4304 13:21:57.295062 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4305 13:21:57.295517 == TX Byte 1 ==
4306 13:21:57.298416 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4307 13:21:57.304931 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4308 13:21:57.305341
4309 13:21:57.305665 [DATLAT]
4310 13:21:57.305970 Freq=600, CH0 RK1
4311 13:21:57.306263
4312 13:21:57.307865 DATLAT Default: 0x9
4313 13:21:57.311758 0, 0xFFFF, sum = 0
4314 13:21:57.312279 1, 0xFFFF, sum = 0
4315 13:21:57.315313 2, 0xFFFF, sum = 0
4316 13:21:57.315728 3, 0xFFFF, sum = 0
4317 13:21:57.317986 4, 0xFFFF, sum = 0
4318 13:21:57.318400 5, 0xFFFF, sum = 0
4319 13:21:57.321163 6, 0xFFFF, sum = 0
4320 13:21:57.321579 7, 0xFFFF, sum = 0
4321 13:21:57.325081 8, 0x0, sum = 1
4322 13:21:57.325593 9, 0x0, sum = 2
4323 13:21:57.327989 10, 0x0, sum = 3
4324 13:21:57.328563 11, 0x0, sum = 4
4325 13:21:57.328912 best_step = 9
4326 13:21:57.329215
4327 13:21:57.331356 ==
4328 13:21:57.334630 Dram Type= 6, Freq= 0, CH_0, rank 1
4329 13:21:57.337932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 13:21:57.338446 ==
4331 13:21:57.338846 RX Vref Scan: 0
4332 13:21:57.339157
4333 13:21:57.341265 RX Vref 0 -> 0, step: 1
4334 13:21:57.341774
4335 13:21:57.345086 RX Delay -179 -> 252, step: 8
4336 13:21:57.351269 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4337 13:21:57.354753 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4338 13:21:57.358259 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4339 13:21:57.360748 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4340 13:21:57.367170 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4341 13:21:57.371273 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4342 13:21:57.374395 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4343 13:21:57.378526 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4344 13:21:57.381208 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4345 13:21:57.388149 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4346 13:21:57.390553 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4347 13:21:57.394532 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4348 13:21:57.397127 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4349 13:21:57.403738 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4350 13:21:57.407268 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4351 13:21:57.410653 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4352 13:21:57.411198 ==
4353 13:21:57.414538 Dram Type= 6, Freq= 0, CH_0, rank 1
4354 13:21:57.420763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 13:21:57.421314 ==
4356 13:21:57.421680 DQS Delay:
4357 13:21:57.422018 DQS0 = 0, DQS1 = 0
4358 13:21:57.423568 DQM Delay:
4359 13:21:57.424091 DQM0 = 41, DQM1 = 36
4360 13:21:57.427035 DQ Delay:
4361 13:21:57.430266 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4362 13:21:57.433500 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4363 13:21:57.436759 DQ8 =24, DQ9 =20, DQ10 =40, DQ11 =28
4364 13:21:57.440241 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4365 13:21:57.440826
4366 13:21:57.441398
4367 13:21:57.446737 [DQSOSCAuto] RK1, (LSB)MR18= 0x6114, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4368 13:21:57.449866 CH0 RK1: MR19=808, MR18=6114
4369 13:21:57.456763 CH0_RK1: MR19=0x808, MR18=0x6114, DQSOSC=391, MR23=63, INC=171, DEC=114
4370 13:21:57.459860 [RxdqsGatingPostProcess] freq 600
4371 13:21:57.463123 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4372 13:21:57.466883 Pre-setting of DQS Precalculation
4373 13:21:57.473030 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4374 13:21:57.473583 ==
4375 13:21:57.476495 Dram Type= 6, Freq= 0, CH_1, rank 0
4376 13:21:57.480452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4377 13:21:57.481148 ==
4378 13:21:57.487271 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4379 13:21:57.492673 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4380 13:21:57.496163 [CA 0] Center 35 (5~66) winsize 62
4381 13:21:57.500070 [CA 1] Center 35 (5~66) winsize 62
4382 13:21:57.503027 [CA 2] Center 34 (4~65) winsize 62
4383 13:21:57.506672 [CA 3] Center 33 (3~64) winsize 62
4384 13:21:57.509571 [CA 4] Center 34 (4~64) winsize 61
4385 13:21:57.513377 [CA 5] Center 33 (3~64) winsize 62
4386 13:21:57.513921
4387 13:21:57.515829 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4388 13:21:57.516378
4389 13:21:57.519196 [CATrainingPosCal] consider 1 rank data
4390 13:21:57.522730 u2DelayCellTimex100 = 270/100 ps
4391 13:21:57.526077 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4392 13:21:57.529673 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4393 13:21:57.532315 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4394 13:21:57.536221 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4395 13:21:57.539523 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4396 13:21:57.543097 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4397 13:21:57.543648
4398 13:21:57.548748 CA PerBit enable=1, Macro0, CA PI delay=33
4399 13:21:57.549275
4400 13:21:57.552872 [CBTSetCACLKResult] CA Dly = 33
4401 13:21:57.553433 CS Dly: 5 (0~36)
4402 13:21:57.553808 ==
4403 13:21:57.555406 Dram Type= 6, Freq= 0, CH_1, rank 1
4404 13:21:57.559252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 13:21:57.559712 ==
4406 13:21:57.565573 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4407 13:21:57.571740 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4408 13:21:57.575705 [CA 0] Center 35 (5~66) winsize 62
4409 13:21:57.578841 [CA 1] Center 36 (6~66) winsize 61
4410 13:21:57.581638 [CA 2] Center 34 (4~65) winsize 62
4411 13:21:57.585551 [CA 3] Center 34 (3~65) winsize 63
4412 13:21:57.588373 [CA 4] Center 34 (4~65) winsize 62
4413 13:21:57.591635 [CA 5] Center 34 (3~65) winsize 63
4414 13:21:57.592096
4415 13:21:57.595159 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4416 13:21:57.595614
4417 13:21:57.598186 [CATrainingPosCal] consider 2 rank data
4418 13:21:57.601993 u2DelayCellTimex100 = 270/100 ps
4419 13:21:57.605691 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4420 13:21:57.608200 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4421 13:21:57.611359 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4422 13:21:57.614540 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4423 13:21:57.621891 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4424 13:21:57.624670 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4425 13:21:57.625132
4426 13:21:57.627709 CA PerBit enable=1, Macro0, CA PI delay=33
4427 13:21:57.628166
4428 13:21:57.630986 [CBTSetCACLKResult] CA Dly = 33
4429 13:21:57.631444 CS Dly: 5 (0~36)
4430 13:21:57.631843
4431 13:21:57.634745 ----->DramcWriteLeveling(PI) begin...
4432 13:21:57.635212 ==
4433 13:21:57.638296 Dram Type= 6, Freq= 0, CH_1, rank 0
4434 13:21:57.645326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4435 13:21:57.645883 ==
4436 13:21:57.647911 Write leveling (Byte 0): 29 => 29
4437 13:21:57.650866 Write leveling (Byte 1): 29 => 29
4438 13:21:57.654665 DramcWriteLeveling(PI) end<-----
4439 13:21:57.655215
4440 13:21:57.655583 ==
4441 13:21:57.657734 Dram Type= 6, Freq= 0, CH_1, rank 0
4442 13:21:57.661331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4443 13:21:57.661796 ==
4444 13:21:57.664658 [Gating] SW mode calibration
4445 13:21:57.671010 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4446 13:21:57.675174 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4447 13:21:57.680898 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4448 13:21:57.684689 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4449 13:21:57.687489 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4450 13:21:57.694035 0 9 12 | B1->B0 | 3131 3131 | 0 0 | (0 1) (0 1)
4451 13:21:57.697446 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 13:21:57.700788 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 13:21:57.708520 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 13:21:57.710725 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 13:21:57.714235 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 13:21:57.720846 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 13:21:57.723622 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 13:21:57.726791 0 10 12 | B1->B0 | 3131 3939 | 0 0 | (0 0) (0 0)
4459 13:21:57.733283 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 13:21:57.736887 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 13:21:57.740731 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 13:21:57.746641 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 13:21:57.750067 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 13:21:57.756478 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 13:21:57.759674 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 13:21:57.763121 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4467 13:21:57.769615 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 13:21:57.772933 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 13:21:57.776426 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 13:21:57.782868 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 13:21:57.786647 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 13:21:57.789888 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 13:21:57.796760 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 13:21:57.798937 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 13:21:57.802409 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 13:21:57.809142 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 13:21:57.812750 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 13:21:57.816408 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 13:21:57.822406 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 13:21:57.825641 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 13:21:57.828650 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 13:21:57.835306 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4483 13:21:57.835767 Total UI for P1: 0, mck2ui 16
4484 13:21:57.842259 best dqsien dly found for B0: ( 0, 13, 10)
4485 13:21:57.845695 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 13:21:57.848832 Total UI for P1: 0, mck2ui 16
4487 13:21:57.851569 best dqsien dly found for B1: ( 0, 13, 14)
4488 13:21:57.854831 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4489 13:21:57.858181 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4490 13:21:57.858795
4491 13:21:57.861712 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4492 13:21:57.865005 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4493 13:21:57.867962 [Gating] SW calibration Done
4494 13:21:57.868441 ==
4495 13:21:57.871303 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 13:21:57.878325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 13:21:57.878910 ==
4498 13:21:57.879275 RX Vref Scan: 0
4499 13:21:57.879610
4500 13:21:57.881748 RX Vref 0 -> 0, step: 1
4501 13:21:57.882300
4502 13:21:57.884908 RX Delay -230 -> 252, step: 16
4503 13:21:57.887937 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4504 13:21:57.891012 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4505 13:21:57.894703 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4506 13:21:57.901246 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4507 13:21:57.904277 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4508 13:21:57.907904 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4509 13:21:57.910769 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4510 13:21:57.917622 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4511 13:21:57.920771 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4512 13:21:57.924592 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4513 13:21:57.927307 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4514 13:21:57.933633 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4515 13:21:57.937220 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4516 13:21:57.940383 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4517 13:21:57.943902 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4518 13:21:57.950321 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4519 13:21:57.950917 ==
4520 13:21:57.953921 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 13:21:57.957442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 13:21:57.958006 ==
4523 13:21:57.958370 DQS Delay:
4524 13:21:57.960319 DQS0 = 0, DQS1 = 0
4525 13:21:57.960771 DQM Delay:
4526 13:21:57.963247 DQM0 = 48, DQM1 = 37
4527 13:21:57.963697 DQ Delay:
4528 13:21:57.966719 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =41
4529 13:21:57.970470 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =49
4530 13:21:57.974157 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4531 13:21:57.976563 DQ12 =49, DQ13 =41, DQ14 =49, DQ15 =57
4532 13:21:57.977018
4533 13:21:57.977374
4534 13:21:57.977705 ==
4535 13:21:57.980205 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 13:21:57.983840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 13:21:57.984385 ==
4538 13:21:57.986471
4539 13:21:57.986976
4540 13:21:57.987339 TX Vref Scan disable
4541 13:21:57.990170 == TX Byte 0 ==
4542 13:21:57.993590 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4543 13:21:57.996570 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4544 13:21:57.999950 == TX Byte 1 ==
4545 13:21:58.003692 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4546 13:21:58.006370 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4547 13:21:58.009817 ==
4548 13:21:58.010274 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 13:21:58.016506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 13:21:58.017056 ==
4551 13:21:58.017421
4552 13:21:58.017756
4553 13:21:58.019948 TX Vref Scan disable
4554 13:21:58.020511 == TX Byte 0 ==
4555 13:21:58.026423 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4556 13:21:58.030001 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4557 13:21:58.030552 == TX Byte 1 ==
4558 13:21:58.036938 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4559 13:21:58.040735 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4560 13:21:58.041290
4561 13:21:58.041656 [DATLAT]
4562 13:21:58.043137 Freq=600, CH1 RK0
4563 13:21:58.043590
4564 13:21:58.043951 DATLAT Default: 0x9
4565 13:21:58.045917 0, 0xFFFF, sum = 0
4566 13:21:58.046373 1, 0xFFFF, sum = 0
4567 13:21:58.049848 2, 0xFFFF, sum = 0
4568 13:21:58.052592 3, 0xFFFF, sum = 0
4569 13:21:58.053056 4, 0xFFFF, sum = 0
4570 13:21:58.056138 5, 0xFFFF, sum = 0
4571 13:21:58.056596 6, 0xFFFF, sum = 0
4572 13:21:58.059226 7, 0xFFFF, sum = 0
4573 13:21:58.059690 8, 0x0, sum = 1
4574 13:21:58.060127 9, 0x0, sum = 2
4575 13:21:58.062406 10, 0x0, sum = 3
4576 13:21:58.062958 11, 0x0, sum = 4
4577 13:21:58.065956 best_step = 9
4578 13:21:58.066427
4579 13:21:58.066941 ==
4580 13:21:58.069046 Dram Type= 6, Freq= 0, CH_1, rank 0
4581 13:21:58.072290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 13:21:58.072846 ==
4583 13:21:58.075906 RX Vref Scan: 1
4584 13:21:58.076378
4585 13:21:58.076863 RX Vref 0 -> 0, step: 1
4586 13:21:58.079347
4587 13:21:58.079776 RX Delay -195 -> 252, step: 8
4588 13:21:58.080215
4589 13:21:58.082446 Set Vref, RX VrefLevel [Byte0]: 50
4590 13:21:58.085598 [Byte1]: 54
4591 13:21:58.090344
4592 13:21:58.090927 Final RX Vref Byte 0 = 50 to rank0
4593 13:21:58.093515 Final RX Vref Byte 1 = 54 to rank0
4594 13:21:58.096900 Final RX Vref Byte 0 = 50 to rank1
4595 13:21:58.099817 Final RX Vref Byte 1 = 54 to rank1==
4596 13:21:58.102905 Dram Type= 6, Freq= 0, CH_1, rank 0
4597 13:21:58.109904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 13:21:58.110440 ==
4599 13:21:58.110938 DQS Delay:
4600 13:21:58.113289 DQS0 = 0, DQS1 = 0
4601 13:21:58.113822 DQM Delay:
4602 13:21:58.114271 DQM0 = 48, DQM1 = 38
4603 13:21:58.116442 DQ Delay:
4604 13:21:58.119347 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =44
4605 13:21:58.122778 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4606 13:21:58.126203 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4607 13:21:58.129491 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4608 13:21:58.130018
4609 13:21:58.130470
4610 13:21:58.136176 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f34, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4611 13:21:58.139128 CH1 RK0: MR19=808, MR18=4F34
4612 13:21:58.146202 CH1_RK0: MR19=0x808, MR18=0x4F34, DQSOSC=394, MR23=63, INC=168, DEC=112
4613 13:21:58.146799
4614 13:21:58.149456 ----->DramcWriteLeveling(PI) begin...
4615 13:21:58.149994 ==
4616 13:21:58.152482 Dram Type= 6, Freq= 0, CH_1, rank 1
4617 13:21:58.156085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 13:21:58.156610 ==
4619 13:21:58.159227 Write leveling (Byte 0): 29 => 29
4620 13:21:58.162747 Write leveling (Byte 1): 29 => 29
4621 13:21:58.165649 DramcWriteLeveling(PI) end<-----
4622 13:21:58.166084
4623 13:21:58.166521 ==
4624 13:21:58.169270 Dram Type= 6, Freq= 0, CH_1, rank 1
4625 13:21:58.175499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 13:21:58.176010 ==
4627 13:21:58.176460 [Gating] SW mode calibration
4628 13:21:58.185613 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4629 13:21:58.189179 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4630 13:21:58.192007 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4631 13:21:58.198923 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4632 13:21:58.202580 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4633 13:21:58.205122 0 9 12 | B1->B0 | 2f2f 3333 | 1 0 | (1 0) (0 0)
4634 13:21:58.211623 0 9 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
4635 13:21:58.215036 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 13:21:58.218302 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4637 13:21:58.225400 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4638 13:21:58.228732 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 13:21:58.231394 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 13:21:58.238153 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 13:21:58.241468 0 10 12 | B1->B0 | 3333 2929 | 1 0 | (0 0) (0 0)
4642 13:21:58.248294 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 13:21:58.251159 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 13:21:58.254500 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 13:21:58.257996 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 13:21:58.264395 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 13:21:58.268325 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 13:21:58.270921 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 13:21:58.277689 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 13:21:58.281448 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 13:21:58.284523 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 13:21:58.290692 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 13:21:58.294237 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 13:21:58.297242 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 13:21:58.304280 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 13:21:58.307846 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 13:21:58.310422 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 13:21:58.317204 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 13:21:58.320631 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 13:21:58.323770 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 13:21:58.330855 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 13:21:58.333522 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 13:21:58.337159 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 13:21:58.343938 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 13:21:58.346812 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4666 13:21:58.350521 Total UI for P1: 0, mck2ui 16
4667 13:21:58.353288 best dqsien dly found for B1: ( 0, 13, 10)
4668 13:21:58.357055 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 13:21:58.360015 Total UI for P1: 0, mck2ui 16
4670 13:21:58.363486 best dqsien dly found for B0: ( 0, 13, 12)
4671 13:21:58.366778 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4672 13:21:58.373328 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4673 13:21:58.373877
4674 13:21:58.376920 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4675 13:21:58.380410 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4676 13:21:58.383412 [Gating] SW calibration Done
4677 13:21:58.383966 ==
4678 13:21:58.387112 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 13:21:58.390319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 13:21:58.390937 ==
4681 13:21:58.393578 RX Vref Scan: 0
4682 13:21:58.394129
4683 13:21:58.394491 RX Vref 0 -> 0, step: 1
4684 13:21:58.394978
4685 13:21:58.396329 RX Delay -230 -> 252, step: 16
4686 13:21:58.400507 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4687 13:21:58.405911 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4688 13:21:58.409591 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4689 13:21:58.412744 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4690 13:21:58.416045 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4691 13:21:58.423109 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4692 13:21:58.426475 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4693 13:21:58.429406 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4694 13:21:58.432830 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4695 13:21:58.439696 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4696 13:21:58.442840 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4697 13:21:58.446171 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4698 13:21:58.449159 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4699 13:21:58.455755 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4700 13:21:58.459376 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4701 13:21:58.462576 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4702 13:21:58.463267 ==
4703 13:21:58.465578 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 13:21:58.469152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 13:21:58.469728 ==
4706 13:21:58.472112 DQS Delay:
4707 13:21:58.472664 DQS0 = 0, DQS1 = 0
4708 13:21:58.475940 DQM Delay:
4709 13:21:58.476391 DQM0 = 43, DQM1 = 38
4710 13:21:58.476752 DQ Delay:
4711 13:21:58.478550 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4712 13:21:58.482211 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =33
4713 13:21:58.485329 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4714 13:21:58.488771 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4715 13:21:58.489318
4716 13:21:58.492413
4717 13:21:58.492953 ==
4718 13:21:58.495078 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 13:21:58.498307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 13:21:58.498797 ==
4721 13:21:58.499161
4722 13:21:58.499598
4723 13:21:58.502052 TX Vref Scan disable
4724 13:21:58.502511 == TX Byte 0 ==
4725 13:21:58.508864 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4726 13:21:58.511685 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4727 13:21:58.512141 == TX Byte 1 ==
4728 13:21:58.518531 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4729 13:21:58.522718 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4730 13:21:58.523268 ==
4731 13:21:58.524661 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 13:21:58.528381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 13:21:58.528935 ==
4734 13:21:58.529297
4735 13:21:58.529628
4736 13:21:58.531945 TX Vref Scan disable
4737 13:21:58.534716 == TX Byte 0 ==
4738 13:21:58.539333 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4739 13:21:58.545731 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4740 13:21:58.546458 == TX Byte 1 ==
4741 13:21:58.548981 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4742 13:21:58.554917 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4743 13:21:58.555374
4744 13:21:58.555735 [DATLAT]
4745 13:21:58.556071 Freq=600, CH1 RK1
4746 13:21:58.556394
4747 13:21:58.557729 DATLAT Default: 0x9
4748 13:21:58.558189 0, 0xFFFF, sum = 0
4749 13:21:58.561548 1, 0xFFFF, sum = 0
4750 13:21:58.564809 2, 0xFFFF, sum = 0
4751 13:21:58.565271 3, 0xFFFF, sum = 0
4752 13:21:58.567690 4, 0xFFFF, sum = 0
4753 13:21:58.568150 5, 0xFFFF, sum = 0
4754 13:21:58.571165 6, 0xFFFF, sum = 0
4755 13:21:58.571686 7, 0xFFFF, sum = 0
4756 13:21:58.574483 8, 0x0, sum = 1
4757 13:21:58.574997 9, 0x0, sum = 2
4758 13:21:58.575385 10, 0x0, sum = 3
4759 13:21:58.578301 11, 0x0, sum = 4
4760 13:21:58.578936 best_step = 9
4761 13:21:58.579302
4762 13:21:58.579636 ==
4763 13:21:58.581670 Dram Type= 6, Freq= 0, CH_1, rank 1
4764 13:21:58.587251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4765 13:21:58.587711 ==
4766 13:21:58.588114 RX Vref Scan: 0
4767 13:21:58.588454
4768 13:21:58.590566 RX Vref 0 -> 0, step: 1
4769 13:21:58.591069
4770 13:21:58.594747 RX Delay -195 -> 252, step: 8
4771 13:21:58.601174 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4772 13:21:58.603740 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4773 13:21:58.607363 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4774 13:21:58.611280 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4775 13:21:58.613733 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4776 13:21:58.620580 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4777 13:21:58.624117 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4778 13:21:58.627145 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4779 13:21:58.630806 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4780 13:21:58.633568 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4781 13:21:58.640769 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4782 13:21:58.643396 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4783 13:21:58.647478 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4784 13:21:58.653723 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4785 13:21:58.656518 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4786 13:21:58.660435 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4787 13:21:58.661009 ==
4788 13:21:58.663517 Dram Type= 6, Freq= 0, CH_1, rank 1
4789 13:21:58.667014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4790 13:21:58.667619 ==
4791 13:21:58.669944 DQS Delay:
4792 13:21:58.670512 DQS0 = 0, DQS1 = 0
4793 13:21:58.673533 DQM Delay:
4794 13:21:58.674084 DQM0 = 45, DQM1 = 37
4795 13:21:58.674451 DQ Delay:
4796 13:21:58.676648 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4797 13:21:58.680222 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4798 13:21:58.683181 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4799 13:21:58.686689 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4800 13:21:58.687244
4801 13:21:58.687610
4802 13:21:58.696779 [DQSOSCAuto] RK1, (LSB)MR18= 0x3226, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 400 ps
4803 13:21:58.700082 CH1 RK1: MR19=808, MR18=3226
4804 13:21:58.706898 CH1_RK1: MR19=0x808, MR18=0x3226, DQSOSC=400, MR23=63, INC=163, DEC=109
4805 13:21:58.709772 [RxdqsGatingPostProcess] freq 600
4806 13:21:58.714004 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4807 13:21:58.716287 Pre-setting of DQS Precalculation
4808 13:21:58.723298 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4809 13:21:58.729900 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4810 13:21:58.736029 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4811 13:21:58.736568
4812 13:21:58.736973
4813 13:21:58.739140 [Calibration Summary] 1200 Mbps
4814 13:21:58.739595 CH 0, Rank 0
4815 13:21:58.742302 SW Impedance : PASS
4816 13:21:58.746332 DUTY Scan : NO K
4817 13:21:58.746841 ZQ Calibration : PASS
4818 13:21:58.748704 Jitter Meter : NO K
4819 13:21:58.752723 CBT Training : PASS
4820 13:21:58.753301 Write leveling : PASS
4821 13:21:58.755831 RX DQS gating : PASS
4822 13:21:58.756325 RX DQ/DQS(RDDQC) : PASS
4823 13:21:58.759112 TX DQ/DQS : PASS
4824 13:21:58.762148 RX DATLAT : PASS
4825 13:21:58.762637 RX DQ/DQS(Engine): PASS
4826 13:21:58.766271 TX OE : NO K
4827 13:21:58.766789 All Pass.
4828 13:21:58.767414
4829 13:21:58.769211 CH 0, Rank 1
4830 13:21:58.769660 SW Impedance : PASS
4831 13:21:58.773256 DUTY Scan : NO K
4832 13:21:58.776072 ZQ Calibration : PASS
4833 13:21:58.776629 Jitter Meter : NO K
4834 13:21:58.779336 CBT Training : PASS
4835 13:21:58.782542 Write leveling : PASS
4836 13:21:58.783233 RX DQS gating : PASS
4837 13:21:58.785679 RX DQ/DQS(RDDQC) : PASS
4838 13:21:58.789310 TX DQ/DQS : PASS
4839 13:21:58.789927 RX DATLAT : PASS
4840 13:21:58.792066 RX DQ/DQS(Engine): PASS
4841 13:21:58.796582 TX OE : NO K
4842 13:21:58.797138 All Pass.
4843 13:21:58.797500
4844 13:21:58.797830 CH 1, Rank 0
4845 13:21:58.798626 SW Impedance : PASS
4846 13:21:58.802093 DUTY Scan : NO K
4847 13:21:58.802711 ZQ Calibration : PASS
4848 13:21:58.805586 Jitter Meter : NO K
4849 13:21:58.808443 CBT Training : PASS
4850 13:21:58.808898 Write leveling : PASS
4851 13:21:58.812157 RX DQS gating : PASS
4852 13:21:58.815079 RX DQ/DQS(RDDQC) : PASS
4853 13:21:58.815540 TX DQ/DQS : PASS
4854 13:21:58.818271 RX DATLAT : PASS
4855 13:21:58.821764 RX DQ/DQS(Engine): PASS
4856 13:21:58.822317 TX OE : NO K
4857 13:21:58.822757 All Pass.
4858 13:21:58.825218
4859 13:21:58.825775 CH 1, Rank 1
4860 13:21:58.829285 SW Impedance : PASS
4861 13:21:58.829843 DUTY Scan : NO K
4862 13:21:58.831681 ZQ Calibration : PASS
4863 13:21:58.832178 Jitter Meter : NO K
4864 13:21:58.835435 CBT Training : PASS
4865 13:21:58.838732 Write leveling : PASS
4866 13:21:58.839279 RX DQS gating : PASS
4867 13:21:58.841470 RX DQ/DQS(RDDQC) : PASS
4868 13:21:58.844742 TX DQ/DQS : PASS
4869 13:21:58.845296 RX DATLAT : PASS
4870 13:21:58.848154 RX DQ/DQS(Engine): PASS
4871 13:21:58.851317 TX OE : NO K
4872 13:21:58.851909 All Pass.
4873 13:21:58.852282
4874 13:21:58.854776 DramC Write-DBI off
4875 13:21:58.855323 PER_BANK_REFRESH: Hybrid Mode
4876 13:21:58.858193 TX_TRACKING: ON
4877 13:21:58.867813 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4878 13:21:58.871334 [FAST_K] Save calibration result to emmc
4879 13:21:58.874404 dramc_set_vcore_voltage set vcore to 662500
4880 13:21:58.874948 Read voltage for 933, 3
4881 13:21:58.877892 Vio18 = 0
4882 13:21:58.878441 Vcore = 662500
4883 13:21:58.878866 Vdram = 0
4884 13:21:58.881384 Vddq = 0
4885 13:21:58.881937 Vmddr = 0
4886 13:21:58.884693 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4887 13:21:58.891742 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4888 13:21:58.894455 MEM_TYPE=3, freq_sel=17
4889 13:21:58.898045 sv_algorithm_assistance_LP4_1600
4890 13:21:58.901555 ============ PULL DRAM RESETB DOWN ============
4891 13:21:58.904522 ========== PULL DRAM RESETB DOWN end =========
4892 13:21:58.911478 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4893 13:21:58.914410 ===================================
4894 13:21:58.915018 LPDDR4 DRAM CONFIGURATION
4895 13:21:58.917640 ===================================
4896 13:21:58.921041 EX_ROW_EN[0] = 0x0
4897 13:21:58.924438 EX_ROW_EN[1] = 0x0
4898 13:21:58.924892 LP4Y_EN = 0x0
4899 13:21:58.927746 WORK_FSP = 0x0
4900 13:21:58.928297 WL = 0x3
4901 13:21:58.930645 RL = 0x3
4902 13:21:58.931104 BL = 0x2
4903 13:21:58.933987 RPST = 0x0
4904 13:21:58.934467 RD_PRE = 0x0
4905 13:21:58.937633 WR_PRE = 0x1
4906 13:21:58.938207 WR_PST = 0x0
4907 13:21:58.941166 DBI_WR = 0x0
4908 13:21:58.941730 DBI_RD = 0x0
4909 13:21:58.944448 OTF = 0x1
4910 13:21:58.947690 ===================================
4911 13:21:58.951048 ===================================
4912 13:21:58.951621 ANA top config
4913 13:21:58.954228 ===================================
4914 13:21:58.957237 DLL_ASYNC_EN = 0
4915 13:21:58.960435 ALL_SLAVE_EN = 1
4916 13:21:58.963598 NEW_RANK_MODE = 1
4917 13:21:58.964178 DLL_IDLE_MODE = 1
4918 13:21:58.967131 LP45_APHY_COMB_EN = 1
4919 13:21:58.971005 TX_ODT_DIS = 1
4920 13:21:58.974016 NEW_8X_MODE = 1
4921 13:21:58.976940 ===================================
4922 13:21:58.980380 ===================================
4923 13:21:58.983530 data_rate = 1866
4924 13:21:58.984062 CKR = 1
4925 13:21:58.987043 DQ_P2S_RATIO = 8
4926 13:21:58.990387 ===================================
4927 13:21:58.993436 CA_P2S_RATIO = 8
4928 13:21:58.996738 DQ_CA_OPEN = 0
4929 13:21:59.000522 DQ_SEMI_OPEN = 0
4930 13:21:59.003280 CA_SEMI_OPEN = 0
4931 13:21:59.003833 CA_FULL_RATE = 0
4932 13:21:59.006764 DQ_CKDIV4_EN = 1
4933 13:21:59.009988 CA_CKDIV4_EN = 1
4934 13:21:59.013324 CA_PREDIV_EN = 0
4935 13:21:59.016267 PH8_DLY = 0
4936 13:21:59.019903 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4937 13:21:59.020353 DQ_AAMCK_DIV = 4
4938 13:21:59.023296 CA_AAMCK_DIV = 4
4939 13:21:59.026511 CA_ADMCK_DIV = 4
4940 13:21:59.029734 DQ_TRACK_CA_EN = 0
4941 13:21:59.032782 CA_PICK = 933
4942 13:21:59.036500 CA_MCKIO = 933
4943 13:21:59.040134 MCKIO_SEMI = 0
4944 13:21:59.040877 PLL_FREQ = 3732
4945 13:21:59.042906 DQ_UI_PI_RATIO = 32
4946 13:21:59.046445 CA_UI_PI_RATIO = 0
4947 13:21:59.049773 ===================================
4948 13:21:59.052498 ===================================
4949 13:21:59.056189 memory_type:LPDDR4
4950 13:21:59.059644 GP_NUM : 10
4951 13:21:59.060200 SRAM_EN : 1
4952 13:21:59.062342 MD32_EN : 0
4953 13:21:59.065918 ===================================
4954 13:21:59.068919 [ANA_INIT] >>>>>>>>>>>>>>
4955 13:21:59.069408 <<<<<< [CONFIGURE PHASE]: ANA_TX
4956 13:21:59.072672 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4957 13:21:59.076135 ===================================
4958 13:21:59.079051 data_rate = 1866,PCW = 0X8f00
4959 13:21:59.083083 ===================================
4960 13:21:59.085735 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4961 13:21:59.092114 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4962 13:21:59.098943 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4963 13:21:59.102842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4964 13:21:59.105671 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4965 13:21:59.109223 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4966 13:21:59.112834 [ANA_INIT] flow start
4967 13:21:59.113287 [ANA_INIT] PLL >>>>>>>>
4968 13:21:59.115507 [ANA_INIT] PLL <<<<<<<<
4969 13:21:59.118870 [ANA_INIT] MIDPI >>>>>>>>
4970 13:21:59.119517 [ANA_INIT] MIDPI <<<<<<<<
4971 13:21:59.122860 [ANA_INIT] DLL >>>>>>>>
4972 13:21:59.125453 [ANA_INIT] flow end
4973 13:21:59.128798 ============ LP4 DIFF to SE enter ============
4974 13:21:59.132677 ============ LP4 DIFF to SE exit ============
4975 13:21:59.135988 [ANA_INIT] <<<<<<<<<<<<<
4976 13:21:59.138196 [Flow] Enable top DCM control >>>>>
4977 13:21:59.142050 [Flow] Enable top DCM control <<<<<
4978 13:21:59.146158 Enable DLL master slave shuffle
4979 13:21:59.151703 ==============================================================
4980 13:21:59.152176 Gating Mode config
4981 13:21:59.158972 ==============================================================
4982 13:21:59.159528 Config description:
4983 13:21:59.168841 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4984 13:21:59.175797 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4985 13:21:59.182078 SELPH_MODE 0: By rank 1: By Phase
4986 13:21:59.184996 ==============================================================
4987 13:21:59.188484 GAT_TRACK_EN = 1
4988 13:21:59.191888 RX_GATING_MODE = 2
4989 13:21:59.194868 RX_GATING_TRACK_MODE = 2
4990 13:21:59.198423 SELPH_MODE = 1
4991 13:21:59.201758 PICG_EARLY_EN = 1
4992 13:21:59.205670 VALID_LAT_VALUE = 1
4993 13:21:59.208230 ==============================================================
4994 13:21:59.212055 Enter into Gating configuration >>>>
4995 13:21:59.214986 Exit from Gating configuration <<<<
4996 13:21:59.218391 Enter into DVFS_PRE_config >>>>>
4997 13:21:59.231515 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4998 13:21:59.234989 Exit from DVFS_PRE_config <<<<<
4999 13:21:59.237968 Enter into PICG configuration >>>>
5000 13:21:59.241657 Exit from PICG configuration <<<<
5001 13:21:59.242213 [RX_INPUT] configuration >>>>>
5002 13:21:59.244929 [RX_INPUT] configuration <<<<<
5003 13:21:59.251273 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5004 13:21:59.254639 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5005 13:21:59.261664 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5006 13:21:59.267881 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5007 13:21:59.274254 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5008 13:21:59.281161 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5009 13:21:59.284145 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5010 13:21:59.287771 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5011 13:21:59.294341 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5012 13:21:59.297348 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5013 13:21:59.300985 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5014 13:21:59.307384 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5015 13:21:59.310974 ===================================
5016 13:21:59.311426 LPDDR4 DRAM CONFIGURATION
5017 13:21:59.313566 ===================================
5018 13:21:59.317552 EX_ROW_EN[0] = 0x0
5019 13:21:59.318123 EX_ROW_EN[1] = 0x0
5020 13:21:59.320532 LP4Y_EN = 0x0
5021 13:21:59.321109 WORK_FSP = 0x0
5022 13:21:59.323860 WL = 0x3
5023 13:21:59.327252 RL = 0x3
5024 13:21:59.327702 BL = 0x2
5025 13:21:59.330430 RPST = 0x0
5026 13:21:59.330950 RD_PRE = 0x0
5027 13:21:59.333540 WR_PRE = 0x1
5028 13:21:59.334090 WR_PST = 0x0
5029 13:21:59.336868 DBI_WR = 0x0
5030 13:21:59.337319 DBI_RD = 0x0
5031 13:21:59.339916 OTF = 0x1
5032 13:21:59.343287 ===================================
5033 13:21:59.346758 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5034 13:21:59.350392 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5035 13:21:59.356509 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5036 13:21:59.359465 ===================================
5037 13:21:59.359884 LPDDR4 DRAM CONFIGURATION
5038 13:21:59.362705 ===================================
5039 13:21:59.366787 EX_ROW_EN[0] = 0x10
5040 13:21:59.369513 EX_ROW_EN[1] = 0x0
5041 13:21:59.370028 LP4Y_EN = 0x0
5042 13:21:59.373435 WORK_FSP = 0x0
5043 13:21:59.374148 WL = 0x3
5044 13:21:59.376335 RL = 0x3
5045 13:21:59.376861 BL = 0x2
5046 13:21:59.379333 RPST = 0x0
5047 13:21:59.379739 RD_PRE = 0x0
5048 13:21:59.382468 WR_PRE = 0x1
5049 13:21:59.382914 WR_PST = 0x0
5050 13:21:59.386421 DBI_WR = 0x0
5051 13:21:59.386977 DBI_RD = 0x0
5052 13:21:59.389857 OTF = 0x1
5053 13:21:59.393026 ===================================
5054 13:21:59.399268 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5055 13:21:59.402525 nWR fixed to 30
5056 13:21:59.403224 [ModeRegInit_LP4] CH0 RK0
5057 13:21:59.405865 [ModeRegInit_LP4] CH0 RK1
5058 13:21:59.409019 [ModeRegInit_LP4] CH1 RK0
5059 13:21:59.412143 [ModeRegInit_LP4] CH1 RK1
5060 13:21:59.412551 match AC timing 9
5061 13:21:59.418936 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5062 13:21:59.422155 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5063 13:21:59.425698 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5064 13:21:59.432416 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5065 13:21:59.435793 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5066 13:21:59.436214 ==
5067 13:21:59.438693 Dram Type= 6, Freq= 0, CH_0, rank 0
5068 13:21:59.442314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5069 13:21:59.442932 ==
5070 13:21:59.448712 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5071 13:21:59.454858 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5072 13:21:59.458226 [CA 0] Center 37 (7~68) winsize 62
5073 13:21:59.462053 [CA 1] Center 37 (7~68) winsize 62
5074 13:21:59.465304 [CA 2] Center 34 (4~65) winsize 62
5075 13:21:59.468918 [CA 3] Center 35 (5~65) winsize 61
5076 13:21:59.471498 [CA 4] Center 33 (3~64) winsize 62
5077 13:21:59.475071 [CA 5] Center 33 (3~64) winsize 62
5078 13:21:59.475523
5079 13:21:59.478548 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5080 13:21:59.479039
5081 13:21:59.481878 [CATrainingPosCal] consider 1 rank data
5082 13:21:59.485039 u2DelayCellTimex100 = 270/100 ps
5083 13:21:59.488350 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5084 13:21:59.491738 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5085 13:21:59.495123 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5086 13:21:59.498287 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5087 13:21:59.501349 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5088 13:21:59.508172 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5089 13:21:59.508722
5090 13:21:59.511647 CA PerBit enable=1, Macro0, CA PI delay=33
5091 13:21:59.512102
5092 13:21:59.514892 [CBTSetCACLKResult] CA Dly = 33
5093 13:21:59.515446 CS Dly: 7 (0~38)
5094 13:21:59.515810 ==
5095 13:21:59.517899 Dram Type= 6, Freq= 0, CH_0, rank 1
5096 13:21:59.520893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 13:21:59.524450 ==
5098 13:21:59.527839 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5099 13:21:59.534147 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5100 13:21:59.537740 [CA 0] Center 37 (7~68) winsize 62
5101 13:21:59.540833 [CA 1] Center 37 (7~68) winsize 62
5102 13:21:59.544883 [CA 2] Center 34 (4~65) winsize 62
5103 13:21:59.547205 [CA 3] Center 34 (4~65) winsize 62
5104 13:21:59.550801 [CA 4] Center 33 (3~64) winsize 62
5105 13:21:59.553807 [CA 5] Center 32 (2~63) winsize 62
5106 13:21:59.554217
5107 13:21:59.557667 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5108 13:21:59.558179
5109 13:21:59.561231 [CATrainingPosCal] consider 2 rank data
5110 13:21:59.563945 u2DelayCellTimex100 = 270/100 ps
5111 13:21:59.567550 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5112 13:21:59.570701 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5113 13:21:59.573793 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5114 13:21:59.580537 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5115 13:21:59.584269 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5116 13:21:59.587850 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5117 13:21:59.588403
5118 13:21:59.590665 CA PerBit enable=1, Macro0, CA PI delay=33
5119 13:21:59.591140
5120 13:21:59.593864 [CBTSetCACLKResult] CA Dly = 33
5121 13:21:59.594416 CS Dly: 7 (0~39)
5122 13:21:59.594905
5123 13:21:59.597288 ----->DramcWriteLeveling(PI) begin...
5124 13:21:59.600204 ==
5125 13:21:59.603625 Dram Type= 6, Freq= 0, CH_0, rank 0
5126 13:21:59.607206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5127 13:21:59.607762 ==
5128 13:21:59.610771 Write leveling (Byte 0): 31 => 31
5129 13:21:59.613859 Write leveling (Byte 1): 29 => 29
5130 13:21:59.617295 DramcWriteLeveling(PI) end<-----
5131 13:21:59.617859
5132 13:21:59.618223 ==
5133 13:21:59.620372 Dram Type= 6, Freq= 0, CH_0, rank 0
5134 13:21:59.623426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 13:21:59.623881 ==
5136 13:21:59.627220 [Gating] SW mode calibration
5137 13:21:59.633686 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5138 13:21:59.640143 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5139 13:21:59.643533 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
5140 13:21:59.646709 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5141 13:21:59.653671 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 13:21:59.656643 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 13:21:59.659861 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 13:21:59.667203 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 13:21:59.669989 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5146 13:21:59.672882 0 14 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
5147 13:21:59.679901 0 15 0 | B1->B0 | 3131 2323 | 1 0 | (1 1) (0 0)
5148 13:21:59.683153 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 13:21:59.687569 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 13:21:59.689930 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 13:21:59.696791 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 13:21:59.699322 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 13:21:59.702852 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 13:21:59.709724 0 15 28 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
5155 13:21:59.712730 1 0 0 | B1->B0 | 3131 4141 | 1 0 | (0 0) (0 0)
5156 13:21:59.716680 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 13:21:59.722577 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 13:21:59.726670 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 13:21:59.729592 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 13:21:59.736297 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 13:21:59.739101 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 13:21:59.742745 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5163 13:21:59.749183 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 13:21:59.752640 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5165 13:21:59.755502 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 13:21:59.762722 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 13:21:59.765284 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 13:21:59.769034 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 13:21:59.775254 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 13:21:59.778463 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 13:21:59.782168 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 13:21:59.789763 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 13:21:59.792370 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 13:21:59.795433 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 13:21:59.802022 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 13:21:59.805278 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 13:21:59.808827 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5178 13:21:59.815144 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5179 13:21:59.818832 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5180 13:21:59.821485 Total UI for P1: 0, mck2ui 16
5181 13:21:59.825248 best dqsien dly found for B0: ( 1, 2, 26)
5182 13:21:59.828525 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 13:21:59.831270 Total UI for P1: 0, mck2ui 16
5184 13:21:59.834701 best dqsien dly found for B1: ( 1, 3, 0)
5185 13:21:59.838441 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5186 13:21:59.841642 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5187 13:21:59.845001
5188 13:21:59.848067 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5189 13:21:59.851342 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5190 13:21:59.855173 [Gating] SW calibration Done
5191 13:21:59.855735 ==
5192 13:21:59.858235 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 13:21:59.861234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 13:21:59.861851 ==
5195 13:21:59.862229 RX Vref Scan: 0
5196 13:21:59.864345
5197 13:21:59.864803 RX Vref 0 -> 0, step: 1
5198 13:21:59.865172
5199 13:21:59.867634 RX Delay -80 -> 252, step: 8
5200 13:21:59.871211 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5201 13:21:59.874486 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5202 13:21:59.881436 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5203 13:21:59.884599 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5204 13:21:59.887907 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5205 13:21:59.890945 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5206 13:21:59.894573 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5207 13:21:59.897920 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5208 13:21:59.904756 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5209 13:21:59.907639 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5210 13:21:59.911070 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5211 13:21:59.914268 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5212 13:21:59.917428 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5213 13:21:59.924540 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5214 13:21:59.927476 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5215 13:21:59.931355 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5216 13:21:59.931922 ==
5217 13:21:59.933795 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 13:21:59.937070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 13:21:59.937530 ==
5220 13:21:59.941685 DQS Delay:
5221 13:21:59.942234 DQS0 = 0, DQS1 = 0
5222 13:21:59.943778 DQM Delay:
5223 13:21:59.944265 DQM0 = 96, DQM1 = 86
5224 13:21:59.944632 DQ Delay:
5225 13:21:59.947170 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5226 13:21:59.950706 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5227 13:21:59.954020 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5228 13:21:59.957068 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5229 13:21:59.960101
5230 13:21:59.960554
5231 13:21:59.960911 ==
5232 13:21:59.963432 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 13:21:59.967222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 13:21:59.967638 ==
5235 13:21:59.967979
5236 13:21:59.968286
5237 13:21:59.970505 TX Vref Scan disable
5238 13:21:59.971077 == TX Byte 0 ==
5239 13:21:59.977356 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5240 13:21:59.979898 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5241 13:21:59.980414 == TX Byte 1 ==
5242 13:21:59.987424 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5243 13:21:59.989787 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5244 13:21:59.990339 ==
5245 13:21:59.993283 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 13:21:59.996587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 13:21:59.997212 ==
5248 13:21:59.997574
5249 13:21:59.997908
5250 13:22:00.000177 TX Vref Scan disable
5251 13:22:00.003078 == TX Byte 0 ==
5252 13:22:00.006506 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5253 13:22:00.010272 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5254 13:22:00.013692 == TX Byte 1 ==
5255 13:22:00.016004 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5256 13:22:00.019306 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5257 13:22:00.023179
5258 13:22:00.023634 [DATLAT]
5259 13:22:00.023995 Freq=933, CH0 RK0
5260 13:22:00.024333
5261 13:22:00.025921 DATLAT Default: 0xd
5262 13:22:00.026373 0, 0xFFFF, sum = 0
5263 13:22:00.029279 1, 0xFFFF, sum = 0
5264 13:22:00.029738 2, 0xFFFF, sum = 0
5265 13:22:00.032825 3, 0xFFFF, sum = 0
5266 13:22:00.033281 4, 0xFFFF, sum = 0
5267 13:22:00.036137 5, 0xFFFF, sum = 0
5268 13:22:00.036597 6, 0xFFFF, sum = 0
5269 13:22:00.039235 7, 0xFFFF, sum = 0
5270 13:22:00.042624 8, 0xFFFF, sum = 0
5271 13:22:00.043161 9, 0xFFFF, sum = 0
5272 13:22:00.046042 10, 0x0, sum = 1
5273 13:22:00.046459 11, 0x0, sum = 2
5274 13:22:00.046864 12, 0x0, sum = 3
5275 13:22:00.049639 13, 0x0, sum = 4
5276 13:22:00.050162 best_step = 11
5277 13:22:00.050491
5278 13:22:00.050877 ==
5279 13:22:00.053247 Dram Type= 6, Freq= 0, CH_0, rank 0
5280 13:22:00.059742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 13:22:00.060266 ==
5282 13:22:00.060596 RX Vref Scan: 1
5283 13:22:00.060895
5284 13:22:00.062439 RX Vref 0 -> 0, step: 1
5285 13:22:00.062917
5286 13:22:00.066165 RX Delay -61 -> 252, step: 4
5287 13:22:00.066728
5288 13:22:00.069544 Set Vref, RX VrefLevel [Byte0]: 61
5289 13:22:00.072397 [Byte1]: 48
5290 13:22:00.072909
5291 13:22:00.075786 Final RX Vref Byte 0 = 61 to rank0
5292 13:22:00.078930 Final RX Vref Byte 1 = 48 to rank0
5293 13:22:00.082186 Final RX Vref Byte 0 = 61 to rank1
5294 13:22:00.085593 Final RX Vref Byte 1 = 48 to rank1==
5295 13:22:00.088852 Dram Type= 6, Freq= 0, CH_0, rank 0
5296 13:22:00.092152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5297 13:22:00.095977 ==
5298 13:22:00.096452 DQS Delay:
5299 13:22:00.096784 DQS0 = 0, DQS1 = 0
5300 13:22:00.098519 DQM Delay:
5301 13:22:00.098975 DQM0 = 96, DQM1 = 85
5302 13:22:00.101937 DQ Delay:
5303 13:22:00.105261 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5304 13:22:00.108386 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =106
5305 13:22:00.111673 DQ8 =78, DQ9 =74, DQ10 =84, DQ11 =78
5306 13:22:00.115123 DQ12 =92, DQ13 =88, DQ14 =96, DQ15 =94
5307 13:22:00.115530
5308 13:22:00.115848
5309 13:22:00.121823 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5310 13:22:00.125236 CH0 RK0: MR19=505, MR18=2E15
5311 13:22:00.131256 CH0_RK0: MR19=0x505, MR18=0x2E15, DQSOSC=407, MR23=63, INC=65, DEC=43
5312 13:22:00.131945
5313 13:22:00.134710 ----->DramcWriteLeveling(PI) begin...
5314 13:22:00.135130 ==
5315 13:22:00.138560 Dram Type= 6, Freq= 0, CH_0, rank 1
5316 13:22:00.141194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 13:22:00.141607 ==
5318 13:22:00.144789 Write leveling (Byte 0): 31 => 31
5319 13:22:00.148236 Write leveling (Byte 1): 31 => 31
5320 13:22:00.151354 DramcWriteLeveling(PI) end<-----
5321 13:22:00.151946
5322 13:22:00.152450 ==
5323 13:22:00.154285 Dram Type= 6, Freq= 0, CH_0, rank 1
5324 13:22:00.157962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5325 13:22:00.158425 ==
5326 13:22:00.161247 [Gating] SW mode calibration
5327 13:22:00.167507 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5328 13:22:00.174452 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5329 13:22:00.177896 0 14 0 | B1->B0 | 2828 3232 | 0 0 | (0 0) (0 0)
5330 13:22:00.184657 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5331 13:22:00.187432 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 13:22:00.190663 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 13:22:00.198452 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 13:22:00.200945 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 13:22:00.204442 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 13:22:00.210731 0 14 28 | B1->B0 | 3232 2828 | 1 0 | (1 1) (0 1)
5337 13:22:00.214669 0 15 0 | B1->B0 | 2f2f 2929 | 0 0 | (0 0) (0 0)
5338 13:22:00.217403 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 13:22:00.224176 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 13:22:00.227553 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 13:22:00.230783 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 13:22:00.237087 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 13:22:00.240564 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 13:22:00.243849 0 15 28 | B1->B0 | 2525 3535 | 0 0 | (0 0) (0 0)
5345 13:22:00.251011 1 0 0 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
5346 13:22:00.253606 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 13:22:00.256726 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 13:22:00.263491 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 13:22:00.267045 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 13:22:00.270755 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 13:22:00.276923 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 13:22:00.280521 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5353 13:22:00.283512 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5354 13:22:00.290463 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 13:22:00.293844 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 13:22:00.296663 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 13:22:00.303370 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 13:22:00.306449 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 13:22:00.309922 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 13:22:00.317025 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 13:22:00.320040 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 13:22:00.322946 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 13:22:00.329940 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 13:22:00.333410 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 13:22:00.336987 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 13:22:00.343131 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 13:22:00.346267 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 13:22:00.349795 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5369 13:22:00.355910 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 13:22:00.356448 Total UI for P1: 0, mck2ui 16
5371 13:22:00.363326 best dqsien dly found for B0: ( 1, 2, 28)
5372 13:22:00.363895 Total UI for P1: 0, mck2ui 16
5373 13:22:00.369404 best dqsien dly found for B1: ( 1, 2, 30)
5374 13:22:00.372691 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5375 13:22:00.375872 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5376 13:22:00.376344
5377 13:22:00.379359 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5378 13:22:00.382530 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5379 13:22:00.385946 [Gating] SW calibration Done
5380 13:22:00.386513 ==
5381 13:22:00.389328 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 13:22:00.393397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 13:22:00.393954 ==
5384 13:22:00.395498 RX Vref Scan: 0
5385 13:22:00.395953
5386 13:22:00.396315 RX Vref 0 -> 0, step: 1
5387 13:22:00.396652
5388 13:22:00.399237 RX Delay -80 -> 252, step: 8
5389 13:22:00.402071 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5390 13:22:00.408678 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5391 13:22:00.412406 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5392 13:22:00.415429 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5393 13:22:00.418895 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5394 13:22:00.421592 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5395 13:22:00.425089 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5396 13:22:00.432049 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5397 13:22:00.435074 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5398 13:22:00.438645 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5399 13:22:00.441709 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5400 13:22:00.445285 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5401 13:22:00.451762 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5402 13:22:00.455145 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5403 13:22:00.458155 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5404 13:22:00.461615 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5405 13:22:00.462126 ==
5406 13:22:00.464946 Dram Type= 6, Freq= 0, CH_0, rank 1
5407 13:22:00.468449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 13:22:00.471967 ==
5409 13:22:00.472504 DQS Delay:
5410 13:22:00.472840 DQS0 = 0, DQS1 = 0
5411 13:22:00.474736 DQM Delay:
5412 13:22:00.475155 DQM0 = 97, DQM1 = 88
5413 13:22:00.478138 DQ Delay:
5414 13:22:00.481652 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5415 13:22:00.484886 DQ4 =99, DQ5 =91, DQ6 =107, DQ7 =107
5416 13:22:00.487911 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5417 13:22:00.491080 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5418 13:22:00.491514
5419 13:22:00.491842
5420 13:22:00.492147 ==
5421 13:22:00.494666 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 13:22:00.497557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 13:22:00.498015 ==
5424 13:22:00.498349
5425 13:22:00.498704
5426 13:22:00.501120 TX Vref Scan disable
5427 13:22:00.501527 == TX Byte 0 ==
5428 13:22:00.507678 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5429 13:22:00.511061 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5430 13:22:00.511472 == TX Byte 1 ==
5431 13:22:00.517800 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5432 13:22:00.520725 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5433 13:22:00.521139 ==
5434 13:22:00.524433 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 13:22:00.527944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 13:22:00.528461 ==
5437 13:22:00.528793
5438 13:22:00.530549
5439 13:22:00.530999 TX Vref Scan disable
5440 13:22:00.534580 == TX Byte 0 ==
5441 13:22:00.537334 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5442 13:22:00.540565 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5443 13:22:00.543876 == TX Byte 1 ==
5444 13:22:00.547111 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5445 13:22:00.554647 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5446 13:22:00.555215
5447 13:22:00.555579 [DATLAT]
5448 13:22:00.555913 Freq=933, CH0 RK1
5449 13:22:00.556241
5450 13:22:00.557096 DATLAT Default: 0xb
5451 13:22:00.557556 0, 0xFFFF, sum = 0
5452 13:22:00.560884 1, 0xFFFF, sum = 0
5453 13:22:00.561355 2, 0xFFFF, sum = 0
5454 13:22:00.563651 3, 0xFFFF, sum = 0
5455 13:22:00.567336 4, 0xFFFF, sum = 0
5456 13:22:00.567911 5, 0xFFFF, sum = 0
5457 13:22:00.570755 6, 0xFFFF, sum = 0
5458 13:22:00.571320 7, 0xFFFF, sum = 0
5459 13:22:00.574491 8, 0xFFFF, sum = 0
5460 13:22:00.575182 9, 0xFFFF, sum = 0
5461 13:22:00.577135 10, 0x0, sum = 1
5462 13:22:00.577723 11, 0x0, sum = 2
5463 13:22:00.580315 12, 0x0, sum = 3
5464 13:22:00.580885 13, 0x0, sum = 4
5465 13:22:00.581262 best_step = 11
5466 13:22:00.581603
5467 13:22:00.584136 ==
5468 13:22:00.587496 Dram Type= 6, Freq= 0, CH_0, rank 1
5469 13:22:00.590230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5470 13:22:00.590851 ==
5471 13:22:00.591230 RX Vref Scan: 0
5472 13:22:00.591572
5473 13:22:00.593297 RX Vref 0 -> 0, step: 1
5474 13:22:00.593755
5475 13:22:00.596990 RX Delay -69 -> 252, step: 4
5476 13:22:00.603529 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5477 13:22:00.606751 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5478 13:22:00.610263 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5479 13:22:00.614102 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5480 13:22:00.616656 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5481 13:22:00.620039 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5482 13:22:00.626650 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5483 13:22:00.629866 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5484 13:22:00.633548 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5485 13:22:00.636277 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5486 13:22:00.639354 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5487 13:22:00.646890 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5488 13:22:00.649902 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5489 13:22:00.652642 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5490 13:22:00.656107 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5491 13:22:00.659072 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5492 13:22:00.663023 ==
5493 13:22:00.663589 Dram Type= 6, Freq= 0, CH_0, rank 1
5494 13:22:00.669589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5495 13:22:00.670137 ==
5496 13:22:00.670506 DQS Delay:
5497 13:22:00.672681 DQS0 = 0, DQS1 = 0
5498 13:22:00.673141 DQM Delay:
5499 13:22:00.675578 DQM0 = 95, DQM1 = 86
5500 13:22:00.676046 DQ Delay:
5501 13:22:00.679315 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94
5502 13:22:00.683559 DQ4 =94, DQ5 =86, DQ6 =104, DQ7 =104
5503 13:22:00.685923 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5504 13:22:00.689204 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
5505 13:22:00.689759
5506 13:22:00.690128
5507 13:22:00.695861 [DQSOSCAuto] RK1, (LSB)MR18= 0x26f6, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5508 13:22:00.699463 CH0 RK1: MR19=504, MR18=26F6
5509 13:22:00.705382 CH0_RK1: MR19=0x504, MR18=0x26F6, DQSOSC=409, MR23=63, INC=64, DEC=43
5510 13:22:00.709531 [RxdqsGatingPostProcess] freq 933
5511 13:22:00.715612 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5512 13:22:00.719395 best DQS0 dly(2T, 0.5T) = (0, 10)
5513 13:22:00.719959 best DQS1 dly(2T, 0.5T) = (0, 11)
5514 13:22:00.722150 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5515 13:22:00.725733 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5516 13:22:00.729236 best DQS0 dly(2T, 0.5T) = (0, 10)
5517 13:22:00.732524 best DQS1 dly(2T, 0.5T) = (0, 10)
5518 13:22:00.735412 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5519 13:22:00.739087 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5520 13:22:00.742084 Pre-setting of DQS Precalculation
5521 13:22:00.748554 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5522 13:22:00.749111 ==
5523 13:22:00.751962 Dram Type= 6, Freq= 0, CH_1, rank 0
5524 13:22:00.755291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5525 13:22:00.755760 ==
5526 13:22:00.762020 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5527 13:22:00.765694 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5528 13:22:00.770444 [CA 0] Center 37 (7~67) winsize 61
5529 13:22:00.772988 [CA 1] Center 37 (7~68) winsize 62
5530 13:22:00.775747 [CA 2] Center 34 (4~65) winsize 62
5531 13:22:00.779126 [CA 3] Center 34 (4~64) winsize 61
5532 13:22:00.782731 [CA 4] Center 34 (5~64) winsize 60
5533 13:22:00.785657 [CA 5] Center 34 (4~64) winsize 61
5534 13:22:00.786215
5535 13:22:00.789013 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5536 13:22:00.789472
5537 13:22:00.792118 [CATrainingPosCal] consider 1 rank data
5538 13:22:00.795970 u2DelayCellTimex100 = 270/100 ps
5539 13:22:00.802496 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5540 13:22:00.805692 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5541 13:22:00.809087 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5542 13:22:00.812293 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5543 13:22:00.815676 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5544 13:22:00.818679 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5545 13:22:00.819154
5546 13:22:00.822130 CA PerBit enable=1, Macro0, CA PI delay=34
5547 13:22:00.822545
5548 13:22:00.825674 [CBTSetCACLKResult] CA Dly = 34
5549 13:22:00.828517 CS Dly: 6 (0~37)
5550 13:22:00.828942 ==
5551 13:22:00.832418 Dram Type= 6, Freq= 0, CH_1, rank 1
5552 13:22:00.835491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 13:22:00.836045 ==
5554 13:22:00.842924 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5555 13:22:00.845565 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5556 13:22:00.849385 [CA 0] Center 36 (6~67) winsize 62
5557 13:22:00.852612 [CA 1] Center 37 (7~67) winsize 61
5558 13:22:00.856168 [CA 2] Center 34 (4~65) winsize 62
5559 13:22:00.859506 [CA 3] Center 34 (4~65) winsize 62
5560 13:22:00.862560 [CA 4] Center 34 (4~65) winsize 62
5561 13:22:00.865751 [CA 5] Center 33 (3~64) winsize 62
5562 13:22:00.866215
5563 13:22:00.869359 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5564 13:22:00.869913
5565 13:22:00.873651 [CATrainingPosCal] consider 2 rank data
5566 13:22:00.875898 u2DelayCellTimex100 = 270/100 ps
5567 13:22:00.878835 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5568 13:22:00.885688 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5569 13:22:00.889177 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5570 13:22:00.892769 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5571 13:22:00.896266 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5572 13:22:00.898991 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5573 13:22:00.899453
5574 13:22:00.902500 CA PerBit enable=1, Macro0, CA PI delay=34
5575 13:22:00.903132
5576 13:22:00.906011 [CBTSetCACLKResult] CA Dly = 34
5577 13:22:00.908512 CS Dly: 7 (0~39)
5578 13:22:00.909011
5579 13:22:00.911799 ----->DramcWriteLeveling(PI) begin...
5580 13:22:00.912268 ==
5581 13:22:00.915021 Dram Type= 6, Freq= 0, CH_1, rank 0
5582 13:22:00.919245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 13:22:00.919821 ==
5584 13:22:00.921766 Write leveling (Byte 0): 24 => 24
5585 13:22:00.924966 Write leveling (Byte 1): 30 => 30
5586 13:22:00.928876 DramcWriteLeveling(PI) end<-----
5587 13:22:00.929424
5588 13:22:00.929788 ==
5589 13:22:00.932312 Dram Type= 6, Freq= 0, CH_1, rank 0
5590 13:22:00.935141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5591 13:22:00.935605 ==
5592 13:22:00.938208 [Gating] SW mode calibration
5593 13:22:00.945683 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5594 13:22:00.951570 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5595 13:22:00.955509 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 13:22:00.958571 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 13:22:00.964704 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 13:22:00.968989 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 13:22:00.971526 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 13:22:00.978288 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5601 13:22:00.981409 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 0)
5602 13:22:00.984574 0 14 28 | B1->B0 | 3030 2c2c | 0 0 | (1 1) (1 1)
5603 13:22:00.991363 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 13:22:00.994673 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 13:22:00.997886 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 13:22:01.004606 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 13:22:01.007966 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 13:22:01.011613 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 13:22:01.017984 0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5610 13:22:01.021153 0 15 28 | B1->B0 | 3737 3838 | 0 0 | (0 0) (0 0)
5611 13:22:01.024274 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 13:22:01.031054 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 13:22:01.034394 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 13:22:01.037468 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 13:22:01.044033 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 13:22:01.048072 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5617 13:22:01.050655 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5618 13:22:01.057859 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5619 13:22:01.061161 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 13:22:01.063904 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 13:22:01.070224 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 13:22:01.073978 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 13:22:01.077515 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 13:22:01.084599 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 13:22:01.087081 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 13:22:01.090524 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 13:22:01.097473 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 13:22:01.100848 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 13:22:01.103588 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 13:22:01.110760 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 13:22:01.113549 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 13:22:01.116959 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 13:22:01.123585 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 13:22:01.126870 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5635 13:22:01.130185 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 13:22:01.133566 Total UI for P1: 0, mck2ui 16
5637 13:22:01.136858 best dqsien dly found for B0: ( 1, 2, 28)
5638 13:22:01.139627 Total UI for P1: 0, mck2ui 16
5639 13:22:01.143141 best dqsien dly found for B1: ( 1, 2, 28)
5640 13:22:01.146842 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5641 13:22:01.149788 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5642 13:22:01.150342
5643 13:22:01.156581 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5644 13:22:01.159578 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5645 13:22:01.163163 [Gating] SW calibration Done
5646 13:22:01.163796 ==
5647 13:22:01.166121 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 13:22:01.169664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 13:22:01.170221 ==
5650 13:22:01.170641 RX Vref Scan: 0
5651 13:22:01.171041
5652 13:22:01.173667 RX Vref 0 -> 0, step: 1
5653 13:22:01.174218
5654 13:22:01.176045 RX Delay -80 -> 252, step: 8
5655 13:22:01.180016 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5656 13:22:01.182678 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5657 13:22:01.189431 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5658 13:22:01.193148 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5659 13:22:01.196091 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5660 13:22:01.199193 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5661 13:22:01.202722 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5662 13:22:01.206172 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5663 13:22:01.212788 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5664 13:22:01.216293 iDelay=208, Bit 9, Center 79 (-24 ~ 183) 208
5665 13:22:01.219338 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5666 13:22:01.222494 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5667 13:22:01.225852 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5668 13:22:01.232432 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5669 13:22:01.235390 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5670 13:22:01.238566 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5671 13:22:01.239093 ==
5672 13:22:01.242794 Dram Type= 6, Freq= 0, CH_1, rank 0
5673 13:22:01.245483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5674 13:22:01.245949 ==
5675 13:22:01.248634 DQS Delay:
5676 13:22:01.249094 DQS0 = 0, DQS1 = 0
5677 13:22:01.249458 DQM Delay:
5678 13:22:01.251882 DQM0 = 102, DQM1 = 90
5679 13:22:01.252409 DQ Delay:
5680 13:22:01.255318 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =99
5681 13:22:01.259305 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5682 13:22:01.263054 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5683 13:22:01.265183 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5684 13:22:01.265646
5685 13:22:01.266025
5686 13:22:01.268792 ==
5687 13:22:01.271803 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 13:22:01.275343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 13:22:01.275899 ==
5690 13:22:01.276266
5691 13:22:01.276604
5692 13:22:01.278409 TX Vref Scan disable
5693 13:22:01.278923 == TX Byte 0 ==
5694 13:22:01.285035 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5695 13:22:01.288243 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5696 13:22:01.288703 == TX Byte 1 ==
5697 13:22:01.295202 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5698 13:22:01.298427 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5699 13:22:01.298892 ==
5700 13:22:01.301907 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 13:22:01.305615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 13:22:01.306037 ==
5703 13:22:01.306368
5704 13:22:01.306724
5705 13:22:01.308212 TX Vref Scan disable
5706 13:22:01.311448 == TX Byte 0 ==
5707 13:22:01.314777 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5708 13:22:01.319547 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5709 13:22:01.321776 == TX Byte 1 ==
5710 13:22:01.325191 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5711 13:22:01.328109 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5712 13:22:01.328529
5713 13:22:01.331269 [DATLAT]
5714 13:22:01.331686 Freq=933, CH1 RK0
5715 13:22:01.332022
5716 13:22:01.334430 DATLAT Default: 0xd
5717 13:22:01.334910 0, 0xFFFF, sum = 0
5718 13:22:01.338189 1, 0xFFFF, sum = 0
5719 13:22:01.338657 2, 0xFFFF, sum = 0
5720 13:22:01.341875 3, 0xFFFF, sum = 0
5721 13:22:01.342393 4, 0xFFFF, sum = 0
5722 13:22:01.344853 5, 0xFFFF, sum = 0
5723 13:22:01.345378 6, 0xFFFF, sum = 0
5724 13:22:01.347878 7, 0xFFFF, sum = 0
5725 13:22:01.348301 8, 0xFFFF, sum = 0
5726 13:22:01.351320 9, 0xFFFF, sum = 0
5727 13:22:01.351747 10, 0x0, sum = 1
5728 13:22:01.354636 11, 0x0, sum = 2
5729 13:22:01.355065 12, 0x0, sum = 3
5730 13:22:01.357990 13, 0x0, sum = 4
5731 13:22:01.358414 best_step = 11
5732 13:22:01.358805
5733 13:22:01.359117 ==
5734 13:22:01.361418 Dram Type= 6, Freq= 0, CH_1, rank 0
5735 13:22:01.368093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 13:22:01.368611 ==
5737 13:22:01.368949 RX Vref Scan: 1
5738 13:22:01.369258
5739 13:22:01.371318 RX Vref 0 -> 0, step: 1
5740 13:22:01.371739
5741 13:22:01.374209 RX Delay -69 -> 252, step: 4
5742 13:22:01.374679
5743 13:22:01.377697 Set Vref, RX VrefLevel [Byte0]: 50
5744 13:22:01.381079 [Byte1]: 54
5745 13:22:01.381554
5746 13:22:01.384659 Final RX Vref Byte 0 = 50 to rank0
5747 13:22:01.388248 Final RX Vref Byte 1 = 54 to rank0
5748 13:22:01.390635 Final RX Vref Byte 0 = 50 to rank1
5749 13:22:01.394866 Final RX Vref Byte 1 = 54 to rank1==
5750 13:22:01.398178 Dram Type= 6, Freq= 0, CH_1, rank 0
5751 13:22:01.401110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 13:22:01.401661 ==
5753 13:22:01.404601 DQS Delay:
5754 13:22:01.405154 DQS0 = 0, DQS1 = 0
5755 13:22:01.407101 DQM Delay:
5756 13:22:01.407558 DQM0 = 100, DQM1 = 94
5757 13:22:01.407923 DQ Delay:
5758 13:22:01.410922 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5759 13:22:01.414094 DQ4 =98, DQ5 =112, DQ6 =108, DQ7 =96
5760 13:22:01.417270 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =86
5761 13:22:01.423949 DQ12 =102, DQ13 =98, DQ14 =102, DQ15 =102
5762 13:22:01.424545
5763 13:22:01.424919
5764 13:22:01.431066 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b0a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5765 13:22:01.434209 CH1 RK0: MR19=505, MR18=1B0A
5766 13:22:01.440079 CH1_RK0: MR19=0x505, MR18=0x1B0A, DQSOSC=413, MR23=63, INC=63, DEC=42
5767 13:22:01.440625
5768 13:22:01.443494 ----->DramcWriteLeveling(PI) begin...
5769 13:22:01.443964 ==
5770 13:22:01.446694 Dram Type= 6, Freq= 0, CH_1, rank 1
5771 13:22:01.450508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 13:22:01.451116 ==
5773 13:22:01.453358 Write leveling (Byte 0): 26 => 26
5774 13:22:01.457133 Write leveling (Byte 1): 30 => 30
5775 13:22:01.460602 DramcWriteLeveling(PI) end<-----
5776 13:22:01.461063
5777 13:22:01.461426 ==
5778 13:22:01.463644 Dram Type= 6, Freq= 0, CH_1, rank 1
5779 13:22:01.466725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 13:22:01.467191 ==
5781 13:22:01.470631 [Gating] SW mode calibration
5782 13:22:01.476987 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5783 13:22:01.484896 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5784 13:22:01.486443 0 14 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5785 13:22:01.493405 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 13:22:01.497031 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 13:22:01.500432 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 13:22:01.506809 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 13:22:01.509830 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 13:22:01.513480 0 14 24 | B1->B0 | 3131 3434 | 0 1 | (0 1) (1 1)
5791 13:22:01.516465 0 14 28 | B1->B0 | 2828 2f2f | 0 1 | (0 0) (1 0)
5792 13:22:01.523357 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5793 13:22:01.526408 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 13:22:01.533408 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 13:22:01.536457 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 13:22:01.539633 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 13:22:01.543043 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 13:22:01.549673 0 15 24 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5799 13:22:01.553418 0 15 28 | B1->B0 | 3c3c 3434 | 0 0 | (0 0) (0 0)
5800 13:22:01.556487 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (1 1)
5801 13:22:01.562819 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 13:22:01.566003 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 13:22:01.572360 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 13:22:01.575822 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 13:22:01.579171 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 13:22:01.583426 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 13:22:01.589247 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5808 13:22:01.592699 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 13:22:01.596251 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 13:22:01.602566 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 13:22:01.605916 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 13:22:01.609529 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 13:22:01.615723 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 13:22:01.619364 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 13:22:01.622463 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 13:22:01.629175 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 13:22:01.632220 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 13:22:01.635779 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 13:22:01.642190 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 13:22:01.645197 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 13:22:01.648575 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 13:22:01.655018 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5823 13:22:01.658717 Total UI for P1: 0, mck2ui 16
5824 13:22:01.661841 best dqsien dly found for B1: ( 1, 2, 22)
5825 13:22:01.665319 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5826 13:22:01.668288 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5827 13:22:01.675132 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 13:22:01.677912 Total UI for P1: 0, mck2ui 16
5829 13:22:01.681758 best dqsien dly found for B0: ( 1, 2, 28)
5830 13:22:01.684631 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5831 13:22:01.688159 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5832 13:22:01.688724
5833 13:22:01.691149 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5834 13:22:01.694495 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5835 13:22:01.698435 [Gating] SW calibration Done
5836 13:22:01.699052 ==
5837 13:22:01.701218 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 13:22:01.704533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 13:22:01.705108 ==
5840 13:22:01.707803 RX Vref Scan: 0
5841 13:22:01.708356
5842 13:22:01.710880 RX Vref 0 -> 0, step: 1
5843 13:22:01.711426
5844 13:22:01.711787 RX Delay -80 -> 252, step: 8
5845 13:22:01.717719 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5846 13:22:01.721102 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5847 13:22:01.724332 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5848 13:22:01.727456 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5849 13:22:01.731264 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5850 13:22:01.738808 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5851 13:22:01.740943 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5852 13:22:01.745013 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5853 13:22:01.747884 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5854 13:22:01.750877 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5855 13:22:01.754007 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5856 13:22:01.760435 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5857 13:22:01.763972 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5858 13:22:01.767052 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5859 13:22:01.770429 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5860 13:22:01.773590 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5861 13:22:01.776926 ==
5862 13:22:01.777482 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 13:22:01.783502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 13:22:01.784167 ==
5865 13:22:01.784661 DQS Delay:
5866 13:22:01.786695 DQS0 = 0, DQS1 = 0
5867 13:22:01.787152 DQM Delay:
5868 13:22:01.790060 DQM0 = 100, DQM1 = 91
5869 13:22:01.790519 DQ Delay:
5870 13:22:01.793411 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5871 13:22:01.796866 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5872 13:22:01.799914 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =83
5873 13:22:01.802916 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5874 13:22:01.803443
5875 13:22:01.803837
5876 13:22:01.804176 ==
5877 13:22:01.806361 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 13:22:01.809757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 13:22:01.810210 ==
5880 13:22:01.810568
5881 13:22:01.813129
5882 13:22:01.813683 TX Vref Scan disable
5883 13:22:01.816553 == TX Byte 0 ==
5884 13:22:01.820054 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5885 13:22:01.823475 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5886 13:22:01.826382 == TX Byte 1 ==
5887 13:22:01.829482 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5888 13:22:01.833013 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5889 13:22:01.833515 ==
5890 13:22:01.836094 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 13:22:01.842648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 13:22:01.843064 ==
5893 13:22:01.843391
5894 13:22:01.843694
5895 13:22:01.843983 TX Vref Scan disable
5896 13:22:01.847281 == TX Byte 0 ==
5897 13:22:01.850470 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5898 13:22:01.857060 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5899 13:22:01.857573 == TX Byte 1 ==
5900 13:22:01.860205 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5901 13:22:01.867227 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5902 13:22:01.867715
5903 13:22:01.868055 [DATLAT]
5904 13:22:01.868416 Freq=933, CH1 RK1
5905 13:22:01.868744
5906 13:22:01.870318 DATLAT Default: 0xb
5907 13:22:01.870829 0, 0xFFFF, sum = 0
5908 13:22:01.873498 1, 0xFFFF, sum = 0
5909 13:22:01.876813 2, 0xFFFF, sum = 0
5910 13:22:01.877237 3, 0xFFFF, sum = 0
5911 13:22:01.880299 4, 0xFFFF, sum = 0
5912 13:22:01.880725 5, 0xFFFF, sum = 0
5913 13:22:01.883906 6, 0xFFFF, sum = 0
5914 13:22:01.884426 7, 0xFFFF, sum = 0
5915 13:22:01.886515 8, 0xFFFF, sum = 0
5916 13:22:01.887005 9, 0xFFFF, sum = 0
5917 13:22:01.890253 10, 0x0, sum = 1
5918 13:22:01.890845 11, 0x0, sum = 2
5919 13:22:01.893236 12, 0x0, sum = 3
5920 13:22:01.893753 13, 0x0, sum = 4
5921 13:22:01.894094 best_step = 11
5922 13:22:01.896735
5923 13:22:01.897267 ==
5924 13:22:01.899918 Dram Type= 6, Freq= 0, CH_1, rank 1
5925 13:22:01.903102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5926 13:22:01.903528 ==
5927 13:22:01.903860 RX Vref Scan: 0
5928 13:22:01.904168
5929 13:22:01.906537 RX Vref 0 -> 0, step: 1
5930 13:22:01.907000
5931 13:22:01.909921 RX Delay -61 -> 252, step: 4
5932 13:22:01.916540 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5933 13:22:01.919567 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5934 13:22:01.922984 iDelay=207, Bit 2, Center 92 (7 ~ 178) 172
5935 13:22:01.926398 iDelay=207, Bit 3, Center 100 (19 ~ 182) 164
5936 13:22:01.929851 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
5937 13:22:01.935924 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5938 13:22:01.939441 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
5939 13:22:01.942545 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5940 13:22:01.946458 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
5941 13:22:01.949114 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5942 13:22:01.952610 iDelay=207, Bit 10, Center 92 (3 ~ 182) 180
5943 13:22:01.959002 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5944 13:22:01.962668 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
5945 13:22:01.965937 iDelay=207, Bit 13, Center 102 (15 ~ 190) 176
5946 13:22:01.969581 iDelay=207, Bit 14, Center 102 (15 ~ 190) 176
5947 13:22:01.975995 iDelay=207, Bit 15, Center 104 (15 ~ 194) 180
5948 13:22:01.976550 ==
5949 13:22:01.978977 Dram Type= 6, Freq= 0, CH_1, rank 1
5950 13:22:01.982494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5951 13:22:01.983105 ==
5952 13:22:01.983479 DQS Delay:
5953 13:22:01.985792 DQS0 = 0, DQS1 = 0
5954 13:22:01.986349 DQM Delay:
5955 13:22:01.989214 DQM0 = 102, DQM1 = 94
5956 13:22:01.989764 DQ Delay:
5957 13:22:01.992350 DQ0 =106, DQ1 =94, DQ2 =92, DQ3 =100
5958 13:22:01.995583 DQ4 =100, DQ5 =110, DQ6 =116, DQ7 =98
5959 13:22:01.999506 DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =84
5960 13:22:02.001930 DQ12 =104, DQ13 =102, DQ14 =102, DQ15 =104
5961 13:22:02.002390
5962 13:22:02.002811
5963 13:22:02.013177 [DQSOSCAuto] RK1, (LSB)MR18= 0x801, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
5964 13:22:02.013739 CH1 RK1: MR19=505, MR18=801
5965 13:22:02.018624 CH1_RK1: MR19=0x505, MR18=0x801, DQSOSC=419, MR23=63, INC=61, DEC=41
5966 13:22:02.021935 [RxdqsGatingPostProcess] freq 933
5967 13:22:02.028455 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5968 13:22:02.031904 best DQS0 dly(2T, 0.5T) = (0, 10)
5969 13:22:02.034873 best DQS1 dly(2T, 0.5T) = (0, 10)
5970 13:22:02.038938 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5971 13:22:02.042746 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5972 13:22:02.045609 best DQS0 dly(2T, 0.5T) = (0, 10)
5973 13:22:02.048485 best DQS1 dly(2T, 0.5T) = (0, 10)
5974 13:22:02.051888 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5975 13:22:02.052445 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5976 13:22:02.055728 Pre-setting of DQS Precalculation
5977 13:22:02.062242 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5978 13:22:02.068948 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5979 13:22:02.074694 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5980 13:22:02.075250
5981 13:22:02.075613
5982 13:22:02.078359 [Calibration Summary] 1866 Mbps
5983 13:22:02.081685 CH 0, Rank 0
5984 13:22:02.082238 SW Impedance : PASS
5985 13:22:02.084719 DUTY Scan : NO K
5986 13:22:02.088203 ZQ Calibration : PASS
5987 13:22:02.088752 Jitter Meter : NO K
5988 13:22:02.091227 CBT Training : PASS
5989 13:22:02.094586 Write leveling : PASS
5990 13:22:02.095185 RX DQS gating : PASS
5991 13:22:02.098024 RX DQ/DQS(RDDQC) : PASS
5992 13:22:02.098568 TX DQ/DQS : PASS
5993 13:22:02.101096 RX DATLAT : PASS
5994 13:22:02.105262 RX DQ/DQS(Engine): PASS
5995 13:22:02.105720 TX OE : NO K
5996 13:22:02.108141 All Pass.
5997 13:22:02.108597
5998 13:22:02.108956 CH 0, Rank 1
5999 13:22:02.111040 SW Impedance : PASS
6000 13:22:02.111496 DUTY Scan : NO K
6001 13:22:02.114862 ZQ Calibration : PASS
6002 13:22:02.117684 Jitter Meter : NO K
6003 13:22:02.118344 CBT Training : PASS
6004 13:22:02.121339 Write leveling : PASS
6005 13:22:02.124524 RX DQS gating : PASS
6006 13:22:02.125076 RX DQ/DQS(RDDQC) : PASS
6007 13:22:02.127479 TX DQ/DQS : PASS
6008 13:22:02.130863 RX DATLAT : PASS
6009 13:22:02.131411 RX DQ/DQS(Engine): PASS
6010 13:22:02.134364 TX OE : NO K
6011 13:22:02.134961 All Pass.
6012 13:22:02.135332
6013 13:22:02.137558 CH 1, Rank 0
6014 13:22:02.138017 SW Impedance : PASS
6015 13:22:02.140504 DUTY Scan : NO K
6016 13:22:02.143940 ZQ Calibration : PASS
6017 13:22:02.144415 Jitter Meter : NO K
6018 13:22:02.147222 CBT Training : PASS
6019 13:22:02.150373 Write leveling : PASS
6020 13:22:02.150872 RX DQS gating : PASS
6021 13:22:02.153803 RX DQ/DQS(RDDQC) : PASS
6022 13:22:02.157349 TX DQ/DQS : PASS
6023 13:22:02.157905 RX DATLAT : PASS
6024 13:22:02.160667 RX DQ/DQS(Engine): PASS
6025 13:22:02.164422 TX OE : NO K
6026 13:22:02.164982 All Pass.
6027 13:22:02.165350
6028 13:22:02.165685 CH 1, Rank 1
6029 13:22:02.167609 SW Impedance : PASS
6030 13:22:02.170780 DUTY Scan : NO K
6031 13:22:02.171334 ZQ Calibration : PASS
6032 13:22:02.173933 Jitter Meter : NO K
6033 13:22:02.177062 CBT Training : PASS
6034 13:22:02.177613 Write leveling : PASS
6035 13:22:02.180593 RX DQS gating : PASS
6036 13:22:02.181145 RX DQ/DQS(RDDQC) : PASS
6037 13:22:02.183799 TX DQ/DQS : PASS
6038 13:22:02.186871 RX DATLAT : PASS
6039 13:22:02.187436 RX DQ/DQS(Engine): PASS
6040 13:22:02.190662 TX OE : NO K
6041 13:22:02.191220 All Pass.
6042 13:22:02.191586
6043 13:22:02.193843 DramC Write-DBI off
6044 13:22:02.196711 PER_BANK_REFRESH: Hybrid Mode
6045 13:22:02.197172 TX_TRACKING: ON
6046 13:22:02.206860 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6047 13:22:02.209867 [FAST_K] Save calibration result to emmc
6048 13:22:02.213385 dramc_set_vcore_voltage set vcore to 650000
6049 13:22:02.216480 Read voltage for 400, 6
6050 13:22:02.217032 Vio18 = 0
6051 13:22:02.219407 Vcore = 650000
6052 13:22:02.219869 Vdram = 0
6053 13:22:02.220232 Vddq = 0
6054 13:22:02.220571 Vmddr = 0
6055 13:22:02.226770 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6056 13:22:02.233379 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6057 13:22:02.234007 MEM_TYPE=3, freq_sel=20
6058 13:22:02.236087 sv_algorithm_assistance_LP4_800
6059 13:22:02.239531 ============ PULL DRAM RESETB DOWN ============
6060 13:22:02.245841 ========== PULL DRAM RESETB DOWN end =========
6061 13:22:02.249545 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6062 13:22:02.253028 ===================================
6063 13:22:02.256030 LPDDR4 DRAM CONFIGURATION
6064 13:22:02.259302 ===================================
6065 13:22:02.259784 EX_ROW_EN[0] = 0x0
6066 13:22:02.262842 EX_ROW_EN[1] = 0x0
6067 13:22:02.263304 LP4Y_EN = 0x0
6068 13:22:02.266165 WORK_FSP = 0x0
6069 13:22:02.266777 WL = 0x2
6070 13:22:02.269300 RL = 0x2
6071 13:22:02.273417 BL = 0x2
6072 13:22:02.273967 RPST = 0x0
6073 13:22:02.276039 RD_PRE = 0x0
6074 13:22:02.276595 WR_PRE = 0x1
6075 13:22:02.279317 WR_PST = 0x0
6076 13:22:02.279791 DBI_WR = 0x0
6077 13:22:02.282668 DBI_RD = 0x0
6078 13:22:02.283126 OTF = 0x1
6079 13:22:02.286140 ===================================
6080 13:22:02.289081 ===================================
6081 13:22:02.292703 ANA top config
6082 13:22:02.295863 ===================================
6083 13:22:02.296425 DLL_ASYNC_EN = 0
6084 13:22:02.299528 ALL_SLAVE_EN = 1
6085 13:22:02.302299 NEW_RANK_MODE = 1
6086 13:22:02.306251 DLL_IDLE_MODE = 1
6087 13:22:02.308976 LP45_APHY_COMB_EN = 1
6088 13:22:02.309528 TX_ODT_DIS = 1
6089 13:22:02.312735 NEW_8X_MODE = 1
6090 13:22:02.315213 ===================================
6091 13:22:02.319814 ===================================
6092 13:22:02.322232 data_rate = 800
6093 13:22:02.325802 CKR = 1
6094 13:22:02.329300 DQ_P2S_RATIO = 4
6095 13:22:02.332130 ===================================
6096 13:22:02.332685 CA_P2S_RATIO = 4
6097 13:22:02.335209 DQ_CA_OPEN = 0
6098 13:22:02.338997 DQ_SEMI_OPEN = 1
6099 13:22:02.342010 CA_SEMI_OPEN = 1
6100 13:22:02.345033 CA_FULL_RATE = 0
6101 13:22:02.348296 DQ_CKDIV4_EN = 0
6102 13:22:02.351893 CA_CKDIV4_EN = 1
6103 13:22:02.352447 CA_PREDIV_EN = 0
6104 13:22:02.354873 PH8_DLY = 0
6105 13:22:02.358630 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6106 13:22:02.361995 DQ_AAMCK_DIV = 0
6107 13:22:02.365047 CA_AAMCK_DIV = 0
6108 13:22:02.367986 CA_ADMCK_DIV = 4
6109 13:22:02.368446 DQ_TRACK_CA_EN = 0
6110 13:22:02.372337 CA_PICK = 800
6111 13:22:02.374829 CA_MCKIO = 400
6112 13:22:02.377966 MCKIO_SEMI = 400
6113 13:22:02.381315 PLL_FREQ = 3016
6114 13:22:02.384432 DQ_UI_PI_RATIO = 32
6115 13:22:02.387687 CA_UI_PI_RATIO = 32
6116 13:22:02.390866 ===================================
6117 13:22:02.394540 ===================================
6118 13:22:02.395146 memory_type:LPDDR4
6119 13:22:02.397852 GP_NUM : 10
6120 13:22:02.401134 SRAM_EN : 1
6121 13:22:02.401686 MD32_EN : 0
6122 13:22:02.404916 ===================================
6123 13:22:02.407368 [ANA_INIT] >>>>>>>>>>>>>>
6124 13:22:02.410987 <<<<<< [CONFIGURE PHASE]: ANA_TX
6125 13:22:02.414162 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6126 13:22:02.417478 ===================================
6127 13:22:02.420508 data_rate = 800,PCW = 0X7400
6128 13:22:02.424165 ===================================
6129 13:22:02.427188 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6130 13:22:02.430793 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6131 13:22:02.443668 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6132 13:22:02.447068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6133 13:22:02.450435 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6134 13:22:02.453668 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6135 13:22:02.457132 [ANA_INIT] flow start
6136 13:22:02.460581 [ANA_INIT] PLL >>>>>>>>
6137 13:22:02.461137 [ANA_INIT] PLL <<<<<<<<
6138 13:22:02.463641 [ANA_INIT] MIDPI >>>>>>>>
6139 13:22:02.467203 [ANA_INIT] MIDPI <<<<<<<<
6140 13:22:02.470511 [ANA_INIT] DLL >>>>>>>>
6141 13:22:02.471114 [ANA_INIT] flow end
6142 13:22:02.474244 ============ LP4 DIFF to SE enter ============
6143 13:22:02.480452 ============ LP4 DIFF to SE exit ============
6144 13:22:02.481027 [ANA_INIT] <<<<<<<<<<<<<
6145 13:22:02.484109 [Flow] Enable top DCM control >>>>>
6146 13:22:02.486698 [Flow] Enable top DCM control <<<<<
6147 13:22:02.490019 Enable DLL master slave shuffle
6148 13:22:02.496649 ==============================================================
6149 13:22:02.497217 Gating Mode config
6150 13:22:02.503318 ==============================================================
6151 13:22:02.506448 Config description:
6152 13:22:02.517303 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6153 13:22:02.523500 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6154 13:22:02.526704 SELPH_MODE 0: By rank 1: By Phase
6155 13:22:02.533257 ==============================================================
6156 13:22:02.536404 GAT_TRACK_EN = 0
6157 13:22:02.539539 RX_GATING_MODE = 2
6158 13:22:02.540091 RX_GATING_TRACK_MODE = 2
6159 13:22:02.542575 SELPH_MODE = 1
6160 13:22:02.546369 PICG_EARLY_EN = 1
6161 13:22:02.549376 VALID_LAT_VALUE = 1
6162 13:22:02.556252 ==============================================================
6163 13:22:02.559738 Enter into Gating configuration >>>>
6164 13:22:02.562644 Exit from Gating configuration <<<<
6165 13:22:02.566056 Enter into DVFS_PRE_config >>>>>
6166 13:22:02.576045 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6167 13:22:02.579563 Exit from DVFS_PRE_config <<<<<
6168 13:22:02.582586 Enter into PICG configuration >>>>
6169 13:22:02.586151 Exit from PICG configuration <<<<
6170 13:22:02.589297 [RX_INPUT] configuration >>>>>
6171 13:22:02.592704 [RX_INPUT] configuration <<<<<
6172 13:22:02.595586 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6173 13:22:02.602625 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6174 13:22:02.608952 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6175 13:22:02.615385 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6176 13:22:02.621841 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6177 13:22:02.625766 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6178 13:22:02.632352 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6179 13:22:02.636327 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6180 13:22:02.639244 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6181 13:22:02.642337 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6182 13:22:02.648478 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6183 13:22:02.652390 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6184 13:22:02.655356 ===================================
6185 13:22:02.658771 LPDDR4 DRAM CONFIGURATION
6186 13:22:02.662306 ===================================
6187 13:22:02.662915 EX_ROW_EN[0] = 0x0
6188 13:22:02.665114 EX_ROW_EN[1] = 0x0
6189 13:22:02.665665 LP4Y_EN = 0x0
6190 13:22:02.667983 WORK_FSP = 0x0
6191 13:22:02.668445 WL = 0x2
6192 13:22:02.671542 RL = 0x2
6193 13:22:02.672068 BL = 0x2
6194 13:22:02.675067 RPST = 0x0
6195 13:22:02.678337 RD_PRE = 0x0
6196 13:22:02.678931 WR_PRE = 0x1
6197 13:22:02.681592 WR_PST = 0x0
6198 13:22:02.682142 DBI_WR = 0x0
6199 13:22:02.684990 DBI_RD = 0x0
6200 13:22:02.685542 OTF = 0x1
6201 13:22:02.687921 ===================================
6202 13:22:02.691464 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6203 13:22:02.697960 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6204 13:22:02.701432 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6205 13:22:02.704861 ===================================
6206 13:22:02.708611 LPDDR4 DRAM CONFIGURATION
6207 13:22:02.710809 ===================================
6208 13:22:02.711276 EX_ROW_EN[0] = 0x10
6209 13:22:02.714679 EX_ROW_EN[1] = 0x0
6210 13:22:02.715232 LP4Y_EN = 0x0
6211 13:22:02.717719 WORK_FSP = 0x0
6212 13:22:02.718270 WL = 0x2
6213 13:22:02.720534 RL = 0x2
6214 13:22:02.725177 BL = 0x2
6215 13:22:02.725732 RPST = 0x0
6216 13:22:02.727738 RD_PRE = 0x0
6217 13:22:02.728290 WR_PRE = 0x1
6218 13:22:02.730524 WR_PST = 0x0
6219 13:22:02.731039 DBI_WR = 0x0
6220 13:22:02.734405 DBI_RD = 0x0
6221 13:22:02.735023 OTF = 0x1
6222 13:22:02.737371 ===================================
6223 13:22:02.743677 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6224 13:22:02.747672 nWR fixed to 30
6225 13:22:02.752072 [ModeRegInit_LP4] CH0 RK0
6226 13:22:02.752623 [ModeRegInit_LP4] CH0 RK1
6227 13:22:02.754522 [ModeRegInit_LP4] CH1 RK0
6228 13:22:02.758272 [ModeRegInit_LP4] CH1 RK1
6229 13:22:02.758873 match AC timing 19
6230 13:22:02.764541 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6231 13:22:02.767984 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6232 13:22:02.770900 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6233 13:22:02.777800 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6234 13:22:02.780860 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6235 13:22:02.781315 ==
6236 13:22:02.784341 Dram Type= 6, Freq= 0, CH_0, rank 0
6237 13:22:02.787718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6238 13:22:02.788271 ==
6239 13:22:02.793958 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6240 13:22:02.800426 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6241 13:22:02.804727 [CA 0] Center 36 (8~64) winsize 57
6242 13:22:02.807007 [CA 1] Center 36 (8~64) winsize 57
6243 13:22:02.810568 [CA 2] Center 36 (8~64) winsize 57
6244 13:22:02.814104 [CA 3] Center 36 (8~64) winsize 57
6245 13:22:02.817529 [CA 4] Center 36 (8~64) winsize 57
6246 13:22:02.820394 [CA 5] Center 36 (8~64) winsize 57
6247 13:22:02.820847
6248 13:22:02.823790 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6249 13:22:02.824344
6250 13:22:02.827369 [CATrainingPosCal] consider 1 rank data
6251 13:22:02.830216 u2DelayCellTimex100 = 270/100 ps
6252 13:22:02.833581 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 13:22:02.836964 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 13:22:02.840682 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 13:22:02.843543 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 13:22:02.847060 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 13:22:02.850124 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 13:22:02.850773
6259 13:22:02.856486 CA PerBit enable=1, Macro0, CA PI delay=36
6260 13:22:02.857054
6261 13:22:02.857434 [CBTSetCACLKResult] CA Dly = 36
6262 13:22:02.859709 CS Dly: 1 (0~32)
6263 13:22:02.860161 ==
6264 13:22:02.863021 Dram Type= 6, Freq= 0, CH_0, rank 1
6265 13:22:02.866250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 13:22:02.866778 ==
6267 13:22:02.873119 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6268 13:22:02.879577 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6269 13:22:02.883047 [CA 0] Center 36 (8~64) winsize 57
6270 13:22:02.886181 [CA 1] Center 36 (8~64) winsize 57
6271 13:22:02.889646 [CA 2] Center 36 (8~64) winsize 57
6272 13:22:02.893051 [CA 3] Center 36 (8~64) winsize 57
6273 13:22:02.893634 [CA 4] Center 36 (8~64) winsize 57
6274 13:22:02.896312 [CA 5] Center 36 (8~64) winsize 57
6275 13:22:02.896886
6276 13:22:02.903497 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6277 13:22:02.904066
6278 13:22:02.906285 [CATrainingPosCal] consider 2 rank data
6279 13:22:02.909652 u2DelayCellTimex100 = 270/100 ps
6280 13:22:02.912790 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 13:22:02.915853 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 13:22:02.920000 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 13:22:02.922508 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 13:22:02.926489 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 13:22:02.929805 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 13:22:02.930370
6287 13:22:02.932280 CA PerBit enable=1, Macro0, CA PI delay=36
6288 13:22:02.932758
6289 13:22:02.935987 [CBTSetCACLKResult] CA Dly = 36
6290 13:22:02.939412 CS Dly: 1 (0~32)
6291 13:22:02.939964
6292 13:22:02.942571 ----->DramcWriteLeveling(PI) begin...
6293 13:22:02.943245 ==
6294 13:22:02.945700 Dram Type= 6, Freq= 0, CH_0, rank 0
6295 13:22:02.949427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 13:22:02.949998 ==
6297 13:22:02.952800 Write leveling (Byte 0): 40 => 8
6298 13:22:02.955612 Write leveling (Byte 1): 32 => 0
6299 13:22:02.959041 DramcWriteLeveling(PI) end<-----
6300 13:22:02.959622
6301 13:22:02.960125 ==
6302 13:22:02.962249 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 13:22:02.965189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 13:22:02.965755 ==
6305 13:22:02.968423 [Gating] SW mode calibration
6306 13:22:02.974907 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6307 13:22:02.982000 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6308 13:22:02.985307 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6309 13:22:02.992137 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6310 13:22:02.994880 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6311 13:22:02.998884 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6312 13:22:03.004940 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6313 13:22:03.008744 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6314 13:22:03.011656 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6315 13:22:03.018421 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6316 13:22:03.021930 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6317 13:22:03.024824 Total UI for P1: 0, mck2ui 16
6318 13:22:03.028602 best dqsien dly found for B0: ( 0, 14, 24)
6319 13:22:03.031907 Total UI for P1: 0, mck2ui 16
6320 13:22:03.034559 best dqsien dly found for B1: ( 0, 14, 24)
6321 13:22:03.038292 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6322 13:22:03.041296 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6323 13:22:03.041757
6324 13:22:03.044809 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6325 13:22:03.047929 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6326 13:22:03.051369 [Gating] SW calibration Done
6327 13:22:03.051825 ==
6328 13:22:03.054678 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 13:22:03.058677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 13:22:03.061606 ==
6331 13:22:03.062150 RX Vref Scan: 0
6332 13:22:03.062513
6333 13:22:03.064370 RX Vref 0 -> 0, step: 1
6334 13:22:03.064830
6335 13:22:03.068311 RX Delay -410 -> 252, step: 16
6336 13:22:03.071062 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6337 13:22:03.074654 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6338 13:22:03.078490 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6339 13:22:03.084591 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6340 13:22:03.087609 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6341 13:22:03.091099 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6342 13:22:03.094707 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6343 13:22:03.100782 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6344 13:22:03.103938 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6345 13:22:03.107095 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6346 13:22:03.114002 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6347 13:22:03.117174 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6348 13:22:03.120548 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6349 13:22:03.123619 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6350 13:22:03.130567 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6351 13:22:03.133920 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6352 13:22:03.134375 ==
6353 13:22:03.137206 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 13:22:03.140368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 13:22:03.140832 ==
6356 13:22:03.143531 DQS Delay:
6357 13:22:03.144006 DQS0 = 43, DQS1 = 59
6358 13:22:03.148416 DQM Delay:
6359 13:22:03.148961 DQM0 = 10, DQM1 = 12
6360 13:22:03.149320 DQ Delay:
6361 13:22:03.150464 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6362 13:22:03.153607 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6363 13:22:03.157102 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6364 13:22:03.160390 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6365 13:22:03.160941
6366 13:22:03.161296
6367 13:22:03.161626 ==
6368 13:22:03.163914 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 13:22:03.169901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 13:22:03.170440 ==
6371 13:22:03.170861
6372 13:22:03.171200
6373 13:22:03.171520 TX Vref Scan disable
6374 13:22:03.173377 == TX Byte 0 ==
6375 13:22:03.176499 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 13:22:03.180281 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 13:22:03.183103 == TX Byte 1 ==
6378 13:22:03.187221 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6379 13:22:03.189853 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6380 13:22:03.193280 ==
6381 13:22:03.196372 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 13:22:03.199949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 13:22:03.200516 ==
6384 13:22:03.200878
6385 13:22:03.201208
6386 13:22:03.203072 TX Vref Scan disable
6387 13:22:03.203520 == TX Byte 0 ==
6388 13:22:03.206375 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6389 13:22:03.212762 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6390 13:22:03.213311 == TX Byte 1 ==
6391 13:22:03.216058 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6392 13:22:03.222874 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6393 13:22:03.223413
6394 13:22:03.223791 [DATLAT]
6395 13:22:03.224132 Freq=400, CH0 RK0
6396 13:22:03.224453
6397 13:22:03.226200 DATLAT Default: 0xf
6398 13:22:03.229525 0, 0xFFFF, sum = 0
6399 13:22:03.230081 1, 0xFFFF, sum = 0
6400 13:22:03.232480 2, 0xFFFF, sum = 0
6401 13:22:03.233032 3, 0xFFFF, sum = 0
6402 13:22:03.235844 4, 0xFFFF, sum = 0
6403 13:22:03.236304 5, 0xFFFF, sum = 0
6404 13:22:03.239176 6, 0xFFFF, sum = 0
6405 13:22:03.239634 7, 0xFFFF, sum = 0
6406 13:22:03.242365 8, 0xFFFF, sum = 0
6407 13:22:03.243004 9, 0xFFFF, sum = 0
6408 13:22:03.245788 10, 0xFFFF, sum = 0
6409 13:22:03.246278 11, 0xFFFF, sum = 0
6410 13:22:03.248970 12, 0xFFFF, sum = 0
6411 13:22:03.249423 13, 0x0, sum = 1
6412 13:22:03.252137 14, 0x0, sum = 2
6413 13:22:03.252705 15, 0x0, sum = 3
6414 13:22:03.255715 16, 0x0, sum = 4
6415 13:22:03.256313 best_step = 14
6416 13:22:03.256677
6417 13:22:03.257011 ==
6418 13:22:03.258988 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 13:22:03.265391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 13:22:03.265847 ==
6421 13:22:03.266338 RX Vref Scan: 1
6422 13:22:03.266866
6423 13:22:03.268648 RX Vref 0 -> 0, step: 1
6424 13:22:03.269102
6425 13:22:03.272180 RX Delay -359 -> 252, step: 8
6426 13:22:03.272729
6427 13:22:03.275227 Set Vref, RX VrefLevel [Byte0]: 61
6428 13:22:03.278917 [Byte1]: 48
6429 13:22:03.281905
6430 13:22:03.282460 Final RX Vref Byte 0 = 61 to rank0
6431 13:22:03.285586 Final RX Vref Byte 1 = 48 to rank0
6432 13:22:03.288542 Final RX Vref Byte 0 = 61 to rank1
6433 13:22:03.292677 Final RX Vref Byte 1 = 48 to rank1==
6434 13:22:03.295276 Dram Type= 6, Freq= 0, CH_0, rank 0
6435 13:22:03.301822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 13:22:03.302368 ==
6437 13:22:03.302807 DQS Delay:
6438 13:22:03.305279 DQS0 = 48, DQS1 = 60
6439 13:22:03.305829 DQM Delay:
6440 13:22:03.306196 DQM0 = 11, DQM1 = 12
6441 13:22:03.308414 DQ Delay:
6442 13:22:03.311558 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6443 13:22:03.312015 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6444 13:22:03.315074 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6445 13:22:03.318920 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6446 13:22:03.319465
6447 13:22:03.321775
6448 13:22:03.328075 [DQSOSCAuto] RK0, (LSB)MR18= 0xc587, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 385 ps
6449 13:22:03.331806 CH0 RK0: MR19=C0C, MR18=C587
6450 13:22:03.338764 CH0_RK0: MR19=0xC0C, MR18=0xC587, DQSOSC=385, MR23=63, INC=398, DEC=265
6451 13:22:03.339318 ==
6452 13:22:03.341498 Dram Type= 6, Freq= 0, CH_0, rank 1
6453 13:22:03.344930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 13:22:03.345387 ==
6455 13:22:03.347993 [Gating] SW mode calibration
6456 13:22:03.354883 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6457 13:22:03.361646 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6458 13:22:03.364474 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6459 13:22:03.367755 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6460 13:22:03.374574 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6461 13:22:03.377837 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6462 13:22:03.381497 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6463 13:22:03.387901 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6464 13:22:03.391293 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6465 13:22:03.393992 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6466 13:22:03.400895 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6467 13:22:03.401444 Total UI for P1: 0, mck2ui 16
6468 13:22:03.407513 best dqsien dly found for B0: ( 0, 14, 24)
6469 13:22:03.407969 Total UI for P1: 0, mck2ui 16
6470 13:22:03.413942 best dqsien dly found for B1: ( 0, 14, 24)
6471 13:22:03.417886 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6472 13:22:03.420679 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6473 13:22:03.421232
6474 13:22:03.424025 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6475 13:22:03.427077 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6476 13:22:03.430421 [Gating] SW calibration Done
6477 13:22:03.431012 ==
6478 13:22:03.433618 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 13:22:03.437043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 13:22:03.437600 ==
6481 13:22:03.440582 RX Vref Scan: 0
6482 13:22:03.441191
6483 13:22:03.443675 RX Vref 0 -> 0, step: 1
6484 13:22:03.444257
6485 13:22:03.444742 RX Delay -410 -> 252, step: 16
6486 13:22:03.449747 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6487 13:22:03.453512 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6488 13:22:03.456816 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6489 13:22:03.463475 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6490 13:22:03.466562 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6491 13:22:03.469721 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6492 13:22:03.473246 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6493 13:22:03.479680 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6494 13:22:03.483062 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6495 13:22:03.486309 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6496 13:22:03.489820 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6497 13:22:03.495970 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6498 13:22:03.499339 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6499 13:22:03.502313 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6500 13:22:03.509464 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6501 13:22:03.513235 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6502 13:22:03.513851 ==
6503 13:22:03.516083 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 13:22:03.519251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 13:22:03.519711 ==
6506 13:22:03.522523 DQS Delay:
6507 13:22:03.523033 DQS0 = 35, DQS1 = 59
6508 13:22:03.523394 DQM Delay:
6509 13:22:03.525870 DQM0 = 3, DQM1 = 16
6510 13:22:03.526427 DQ Delay:
6511 13:22:03.529232 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6512 13:22:03.532580 DQ4 =0, DQ5 =0, DQ6 =8, DQ7 =8
6513 13:22:03.535993 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6514 13:22:03.538831 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6515 13:22:03.539285
6516 13:22:03.539643
6517 13:22:03.539969 ==
6518 13:22:03.542423 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 13:22:03.545930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 13:22:03.546409 ==
6521 13:22:03.546842
6522 13:22:03.547187
6523 13:22:03.549024 TX Vref Scan disable
6524 13:22:03.552541 == TX Byte 0 ==
6525 13:22:03.555397 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6526 13:22:03.559532 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6527 13:22:03.562825 == TX Byte 1 ==
6528 13:22:03.566703 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6529 13:22:03.568710 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6530 13:22:03.569213 ==
6531 13:22:03.572020 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 13:22:03.575594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 13:22:03.576161 ==
6534 13:22:03.578841
6535 13:22:03.579305
6536 13:22:03.579793 TX Vref Scan disable
6537 13:22:03.581603 == TX Byte 0 ==
6538 13:22:03.585598 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6539 13:22:03.588298 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6540 13:22:03.591997 == TX Byte 1 ==
6541 13:22:03.594886 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6542 13:22:03.598489 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6543 13:22:03.599099
6544 13:22:03.599583 [DATLAT]
6545 13:22:03.601936 Freq=400, CH0 RK1
6546 13:22:03.602509
6547 13:22:03.604864 DATLAT Default: 0xe
6548 13:22:03.605330 0, 0xFFFF, sum = 0
6549 13:22:03.608230 1, 0xFFFF, sum = 0
6550 13:22:03.608829 2, 0xFFFF, sum = 0
6551 13:22:03.611830 3, 0xFFFF, sum = 0
6552 13:22:03.612428 4, 0xFFFF, sum = 0
6553 13:22:03.614904 5, 0xFFFF, sum = 0
6554 13:22:03.615369 6, 0xFFFF, sum = 0
6555 13:22:03.618124 7, 0xFFFF, sum = 0
6556 13:22:03.619057 8, 0xFFFF, sum = 0
6557 13:22:03.621314 9, 0xFFFF, sum = 0
6558 13:22:03.621789 10, 0xFFFF, sum = 0
6559 13:22:03.625311 11, 0xFFFF, sum = 0
6560 13:22:03.625874 12, 0xFFFF, sum = 0
6561 13:22:03.628129 13, 0x0, sum = 1
6562 13:22:03.628713 14, 0x0, sum = 2
6563 13:22:03.631870 15, 0x0, sum = 3
6564 13:22:03.632430 16, 0x0, sum = 4
6565 13:22:03.634735 best_step = 14
6566 13:22:03.635185
6567 13:22:03.635540 ==
6568 13:22:03.637893 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 13:22:03.641508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 13:22:03.642063 ==
6571 13:22:03.644319 RX Vref Scan: 0
6572 13:22:03.644818
6573 13:22:03.645236 RX Vref 0 -> 0, step: 1
6574 13:22:03.645582
6575 13:22:03.647848 RX Delay -359 -> 252, step: 8
6576 13:22:03.656660 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6577 13:22:03.659550 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6578 13:22:03.662508 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6579 13:22:03.669063 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6580 13:22:03.672177 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6581 13:22:03.675850 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6582 13:22:03.679838 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6583 13:22:03.685591 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6584 13:22:03.689052 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6585 13:22:03.692502 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6586 13:22:03.695395 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6587 13:22:03.702236 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6588 13:22:03.705068 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6589 13:22:03.708785 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6590 13:22:03.712309 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6591 13:22:03.718771 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6592 13:22:03.719343 ==
6593 13:22:03.721659 Dram Type= 6, Freq= 0, CH_0, rank 1
6594 13:22:03.725110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 13:22:03.725695 ==
6596 13:22:03.728292 DQS Delay:
6597 13:22:03.728837 DQS0 = 44, DQS1 = 60
6598 13:22:03.729278 DQM Delay:
6599 13:22:03.731297 DQM0 = 7, DQM1 = 15
6600 13:22:03.731880 DQ Delay:
6601 13:22:03.735214 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6602 13:22:03.737957 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6603 13:22:03.741663 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6604 13:22:03.745546 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6605 13:22:03.746003
6606 13:22:03.746361
6607 13:22:03.751792 [DQSOSCAuto] RK1, (LSB)MR18= 0xb53f, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6608 13:22:03.754537 CH0 RK1: MR19=C0C, MR18=B53F
6609 13:22:03.761285 CH0_RK1: MR19=0xC0C, MR18=0xB53F, DQSOSC=387, MR23=63, INC=394, DEC=262
6610 13:22:03.764597 [RxdqsGatingPostProcess] freq 400
6611 13:22:03.771257 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6612 13:22:03.774667 best DQS0 dly(2T, 0.5T) = (0, 10)
6613 13:22:03.778119 best DQS1 dly(2T, 0.5T) = (0, 10)
6614 13:22:03.781244 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6615 13:22:03.784051 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6616 13:22:03.787584 best DQS0 dly(2T, 0.5T) = (0, 10)
6617 13:22:03.788275 best DQS1 dly(2T, 0.5T) = (0, 10)
6618 13:22:03.791262 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6619 13:22:03.794355 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6620 13:22:03.797948 Pre-setting of DQS Precalculation
6621 13:22:03.804258 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6622 13:22:03.804812 ==
6623 13:22:03.807316 Dram Type= 6, Freq= 0, CH_1, rank 0
6624 13:22:03.810451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 13:22:03.810972 ==
6626 13:22:03.817510 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6627 13:22:03.824490 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6628 13:22:03.827802 [CA 0] Center 36 (8~64) winsize 57
6629 13:22:03.830465 [CA 1] Center 36 (8~64) winsize 57
6630 13:22:03.833752 [CA 2] Center 36 (8~64) winsize 57
6631 13:22:03.834306 [CA 3] Center 36 (8~64) winsize 57
6632 13:22:03.837565 [CA 4] Center 36 (8~64) winsize 57
6633 13:22:03.840487 [CA 5] Center 36 (8~64) winsize 57
6634 13:22:03.841042
6635 13:22:03.846702 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6636 13:22:03.847155
6637 13:22:03.850253 [CATrainingPosCal] consider 1 rank data
6638 13:22:03.853774 u2DelayCellTimex100 = 270/100 ps
6639 13:22:03.856522 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 13:22:03.860094 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 13:22:03.863557 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 13:22:03.867201 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 13:22:03.870761 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 13:22:03.873711 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 13:22:03.874274
6646 13:22:03.876750 CA PerBit enable=1, Macro0, CA PI delay=36
6647 13:22:03.877202
6648 13:22:03.880385 [CBTSetCACLKResult] CA Dly = 36
6649 13:22:03.883410 CS Dly: 1 (0~32)
6650 13:22:03.884051 ==
6651 13:22:03.887361 Dram Type= 6, Freq= 0, CH_1, rank 1
6652 13:22:03.889999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 13:22:03.890467 ==
6654 13:22:03.896170 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6655 13:22:03.902987 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6656 13:22:03.906168 [CA 0] Center 36 (8~64) winsize 57
6657 13:22:03.906669 [CA 1] Center 36 (8~64) winsize 57
6658 13:22:03.909988 [CA 2] Center 36 (8~64) winsize 57
6659 13:22:03.912601 [CA 3] Center 36 (8~64) winsize 57
6660 13:22:03.916176 [CA 4] Center 36 (8~64) winsize 57
6661 13:22:03.919312 [CA 5] Center 36 (8~64) winsize 57
6662 13:22:03.919773
6663 13:22:03.923397 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6664 13:22:03.923859
6665 13:22:03.929361 [CATrainingPosCal] consider 2 rank data
6666 13:22:03.929943 u2DelayCellTimex100 = 270/100 ps
6667 13:22:03.936285 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 13:22:03.939591 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 13:22:03.942869 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 13:22:03.945862 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 13:22:03.949447 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 13:22:03.952524 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 13:22:03.952988
6674 13:22:03.955536 CA PerBit enable=1, Macro0, CA PI delay=36
6675 13:22:03.955999
6676 13:22:03.959354 [CBTSetCACLKResult] CA Dly = 36
6677 13:22:03.962229 CS Dly: 1 (0~32)
6678 13:22:03.962734
6679 13:22:03.965633 ----->DramcWriteLeveling(PI) begin...
6680 13:22:03.966204 ==
6681 13:22:03.968963 Dram Type= 6, Freq= 0, CH_1, rank 0
6682 13:22:03.972399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 13:22:03.972869 ==
6684 13:22:03.975534 Write leveling (Byte 0): 40 => 8
6685 13:22:03.979081 Write leveling (Byte 1): 40 => 8
6686 13:22:03.982179 DramcWriteLeveling(PI) end<-----
6687 13:22:03.982788
6688 13:22:03.983163 ==
6689 13:22:03.985899 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 13:22:03.988646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 13:22:03.989109 ==
6692 13:22:03.992622 [Gating] SW mode calibration
6693 13:22:03.998865 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6694 13:22:04.005522 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6695 13:22:04.008807 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6696 13:22:04.011785 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6697 13:22:04.018793 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6698 13:22:04.022466 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6699 13:22:04.025337 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6700 13:22:04.031822 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6701 13:22:04.035296 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6702 13:22:04.038779 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6703 13:22:04.044861 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6704 13:22:04.048384 Total UI for P1: 0, mck2ui 16
6705 13:22:04.051189 best dqsien dly found for B0: ( 0, 14, 24)
6706 13:22:04.051651 Total UI for P1: 0, mck2ui 16
6707 13:22:04.058198 best dqsien dly found for B1: ( 0, 14, 24)
6708 13:22:04.061631 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6709 13:22:04.064663 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6710 13:22:04.065224
6711 13:22:04.067756 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6712 13:22:04.071500 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6713 13:22:04.074992 [Gating] SW calibration Done
6714 13:22:04.075558 ==
6715 13:22:04.077930 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 13:22:04.081494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 13:22:04.082060 ==
6718 13:22:04.084333 RX Vref Scan: 0
6719 13:22:04.084793
6720 13:22:04.087730 RX Vref 0 -> 0, step: 1
6721 13:22:04.088298
6722 13:22:04.088755 RX Delay -410 -> 252, step: 16
6723 13:22:04.094877 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6724 13:22:04.097939 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6725 13:22:04.101146 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6726 13:22:04.107744 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6727 13:22:04.110984 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6728 13:22:04.114483 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6729 13:22:04.117736 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6730 13:22:04.124075 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6731 13:22:04.127336 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6732 13:22:04.131115 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6733 13:22:04.134274 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6734 13:22:04.140962 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6735 13:22:04.143982 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6736 13:22:04.147342 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6737 13:22:04.150795 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6738 13:22:04.157158 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6739 13:22:04.157730 ==
6740 13:22:04.160352 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 13:22:04.163520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 13:22:04.164005 ==
6743 13:22:04.164407 DQS Delay:
6744 13:22:04.166988 DQS0 = 43, DQS1 = 51
6745 13:22:04.167454 DQM Delay:
6746 13:22:04.170682 DQM0 = 12, DQM1 = 14
6747 13:22:04.171329 DQ Delay:
6748 13:22:04.173487 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6749 13:22:04.176594 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6750 13:22:04.180132 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6751 13:22:04.183344 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6752 13:22:04.183801
6753 13:22:04.184238
6754 13:22:04.184594 ==
6755 13:22:04.186391 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 13:22:04.190097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 13:22:04.190716 ==
6758 13:22:04.193351
6759 13:22:04.193900
6760 13:22:04.194259 TX Vref Scan disable
6761 13:22:04.196590 == TX Byte 0 ==
6762 13:22:04.200346 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 13:22:04.203286 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 13:22:04.207016 == TX Byte 1 ==
6765 13:22:04.210369 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 13:22:04.213487 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 13:22:04.214040 ==
6768 13:22:04.216127 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 13:22:04.220038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 13:22:04.223120 ==
6771 13:22:04.223680
6772 13:22:04.224050
6773 13:22:04.224388 TX Vref Scan disable
6774 13:22:04.226534 == TX Byte 0 ==
6775 13:22:04.229602 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 13:22:04.232618 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 13:22:04.236084 == TX Byte 1 ==
6778 13:22:04.239476 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 13:22:04.243009 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 13:22:04.243572
6781 13:22:04.246143 [DATLAT]
6782 13:22:04.246679 Freq=400, CH1 RK0
6783 13:22:04.247059
6784 13:22:04.249856 DATLAT Default: 0xf
6785 13:22:04.250478 0, 0xFFFF, sum = 0
6786 13:22:04.252568 1, 0xFFFF, sum = 0
6787 13:22:04.253039 2, 0xFFFF, sum = 0
6788 13:22:04.255746 3, 0xFFFF, sum = 0
6789 13:22:04.256215 4, 0xFFFF, sum = 0
6790 13:22:04.259487 5, 0xFFFF, sum = 0
6791 13:22:04.260048 6, 0xFFFF, sum = 0
6792 13:22:04.262476 7, 0xFFFF, sum = 0
6793 13:22:04.262972 8, 0xFFFF, sum = 0
6794 13:22:04.266390 9, 0xFFFF, sum = 0
6795 13:22:04.267002 10, 0xFFFF, sum = 0
6796 13:22:04.269278 11, 0xFFFF, sum = 0
6797 13:22:04.272899 12, 0xFFFF, sum = 0
6798 13:22:04.273368 13, 0x0, sum = 1
6799 13:22:04.273736 14, 0x0, sum = 2
6800 13:22:04.275980 15, 0x0, sum = 3
6801 13:22:04.276445 16, 0x0, sum = 4
6802 13:22:04.279047 best_step = 14
6803 13:22:04.279599
6804 13:22:04.279965 ==
6805 13:22:04.282404 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 13:22:04.285871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 13:22:04.286422 ==
6808 13:22:04.288960 RX Vref Scan: 1
6809 13:22:04.289530
6810 13:22:04.289895 RX Vref 0 -> 0, step: 1
6811 13:22:04.292134
6812 13:22:04.292589 RX Delay -343 -> 252, step: 8
6813 13:22:04.292951
6814 13:22:04.295591 Set Vref, RX VrefLevel [Byte0]: 50
6815 13:22:04.298534 [Byte1]: 54
6816 13:22:04.303962
6817 13:22:04.304510 Final RX Vref Byte 0 = 50 to rank0
6818 13:22:04.307176 Final RX Vref Byte 1 = 54 to rank0
6819 13:22:04.311193 Final RX Vref Byte 0 = 50 to rank1
6820 13:22:04.314154 Final RX Vref Byte 1 = 54 to rank1==
6821 13:22:04.317898 Dram Type= 6, Freq= 0, CH_1, rank 0
6822 13:22:04.323729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 13:22:04.324312 ==
6824 13:22:04.324682 DQS Delay:
6825 13:22:04.327563 DQS0 = 44, DQS1 = 56
6826 13:22:04.328115 DQM Delay:
6827 13:22:04.328479 DQM0 = 7, DQM1 = 12
6828 13:22:04.330668 DQ Delay:
6829 13:22:04.333956 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6830 13:22:04.334508 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6831 13:22:04.337136 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6832 13:22:04.340236 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =20
6833 13:22:04.340784
6834 13:22:04.343554
6835 13:22:04.351744 [DQSOSCAuto] RK0, (LSB)MR18= 0xa278, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 389 ps
6836 13:22:04.353325 CH1 RK0: MR19=C0C, MR18=A278
6837 13:22:04.360315 CH1_RK0: MR19=0xC0C, MR18=0xA278, DQSOSC=389, MR23=63, INC=390, DEC=260
6838 13:22:04.360870 ==
6839 13:22:04.363365 Dram Type= 6, Freq= 0, CH_1, rank 1
6840 13:22:04.366952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 13:22:04.367508 ==
6842 13:22:04.370341 [Gating] SW mode calibration
6843 13:22:04.377112 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6844 13:22:04.383592 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6845 13:22:04.386982 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6846 13:22:04.389945 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6847 13:22:04.396922 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6848 13:22:04.399583 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6849 13:22:04.403127 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6850 13:22:04.409622 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6851 13:22:04.413396 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6852 13:22:04.416965 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6853 13:22:04.423318 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6854 13:22:04.423875 Total UI for P1: 0, mck2ui 16
6855 13:22:04.429387 best dqsien dly found for B0: ( 0, 14, 24)
6856 13:22:04.429954 Total UI for P1: 0, mck2ui 16
6857 13:22:04.433030 best dqsien dly found for B1: ( 0, 14, 24)
6858 13:22:04.439497 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6859 13:22:04.442818 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6860 13:22:04.443279
6861 13:22:04.445750 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6862 13:22:04.449447 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6863 13:22:04.452642 [Gating] SW calibration Done
6864 13:22:04.453106 ==
6865 13:22:04.456007 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 13:22:04.459470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 13:22:04.460019 ==
6868 13:22:04.462249 RX Vref Scan: 0
6869 13:22:04.462747
6870 13:22:04.463118 RX Vref 0 -> 0, step: 1
6871 13:22:04.463461
6872 13:22:04.465938 RX Delay -410 -> 252, step: 16
6873 13:22:04.472748 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6874 13:22:04.475431 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6875 13:22:04.479249 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6876 13:22:04.482445 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6877 13:22:04.489056 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6878 13:22:04.492219 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6879 13:22:04.495209 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6880 13:22:04.498865 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6881 13:22:04.505327 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6882 13:22:04.508901 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6883 13:22:04.511643 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6884 13:22:04.515179 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6885 13:22:04.522009 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6886 13:22:04.525319 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6887 13:22:04.528753 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6888 13:22:04.535388 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6889 13:22:04.535944 ==
6890 13:22:04.538625 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 13:22:04.541844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 13:22:04.542403 ==
6893 13:22:04.542837 DQS Delay:
6894 13:22:04.545648 DQS0 = 51, DQS1 = 51
6895 13:22:04.546109 DQM Delay:
6896 13:22:04.548375 DQM0 = 20, DQM1 = 15
6897 13:22:04.548832 DQ Delay:
6898 13:22:04.551716 DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16
6899 13:22:04.555065 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6900 13:22:04.558555 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6901 13:22:04.562234 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6902 13:22:04.562839
6903 13:22:04.563211
6904 13:22:04.563551 ==
6905 13:22:04.565343 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 13:22:04.567879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 13:22:04.568346 ==
6908 13:22:04.568763
6909 13:22:04.569174
6910 13:22:04.571212 TX Vref Scan disable
6911 13:22:04.574515 == TX Byte 0 ==
6912 13:22:04.578214 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6913 13:22:04.581261 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6914 13:22:04.584664 == TX Byte 1 ==
6915 13:22:04.587804 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6916 13:22:04.591293 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6917 13:22:04.591845 ==
6918 13:22:04.594944 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 13:22:04.597996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 13:22:04.598547 ==
6921 13:22:04.598975
6922 13:22:04.601312
6923 13:22:04.601764 TX Vref Scan disable
6924 13:22:04.604650 == TX Byte 0 ==
6925 13:22:04.607556 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6926 13:22:04.611922 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6927 13:22:04.614382 == TX Byte 1 ==
6928 13:22:04.618188 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6929 13:22:04.621779 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6930 13:22:04.622330
6931 13:22:04.622742 [DATLAT]
6932 13:22:04.624355 Freq=400, CH1 RK1
6933 13:22:04.624811
6934 13:22:04.625173 DATLAT Default: 0xe
6935 13:22:04.627846 0, 0xFFFF, sum = 0
6936 13:22:04.631254 1, 0xFFFF, sum = 0
6937 13:22:04.631819 2, 0xFFFF, sum = 0
6938 13:22:04.634877 3, 0xFFFF, sum = 0
6939 13:22:04.635430 4, 0xFFFF, sum = 0
6940 13:22:04.638063 5, 0xFFFF, sum = 0
6941 13:22:04.638672 6, 0xFFFF, sum = 0
6942 13:22:04.641152 7, 0xFFFF, sum = 0
6943 13:22:04.641710 8, 0xFFFF, sum = 0
6944 13:22:04.644379 9, 0xFFFF, sum = 0
6945 13:22:04.644937 10, 0xFFFF, sum = 0
6946 13:22:04.647713 11, 0xFFFF, sum = 0
6947 13:22:04.648174 12, 0xFFFF, sum = 0
6948 13:22:04.651319 13, 0x0, sum = 1
6949 13:22:04.651801 14, 0x0, sum = 2
6950 13:22:04.653787 15, 0x0, sum = 3
6951 13:22:04.654253 16, 0x0, sum = 4
6952 13:22:04.657446 best_step = 14
6953 13:22:04.657898
6954 13:22:04.658259 ==
6955 13:22:04.660841 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 13:22:04.664258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 13:22:04.664720 ==
6958 13:22:04.667667 RX Vref Scan: 0
6959 13:22:04.668213
6960 13:22:04.668576 RX Vref 0 -> 0, step: 1
6961 13:22:04.669034
6962 13:22:04.670576 RX Delay -343 -> 252, step: 8
6963 13:22:04.678552 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
6964 13:22:04.681678 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6965 13:22:04.685024 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
6966 13:22:04.691340 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6967 13:22:04.694845 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6968 13:22:04.698031 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
6969 13:22:04.701358 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6970 13:22:04.707630 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6971 13:22:04.710802 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6972 13:22:04.714493 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6973 13:22:04.718074 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
6974 13:22:04.724212 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
6975 13:22:04.727451 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6976 13:22:04.731051 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6977 13:22:04.734369 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6978 13:22:04.740903 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
6979 13:22:04.741458 ==
6980 13:22:04.744015 Dram Type= 6, Freq= 0, CH_1, rank 1
6981 13:22:04.747914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6982 13:22:04.748376 ==
6983 13:22:04.750824 DQS Delay:
6984 13:22:04.751283 DQS0 = 44, DQS1 = 56
6985 13:22:04.751650 DQM Delay:
6986 13:22:04.754629 DQM0 = 8, DQM1 = 11
6987 13:22:04.755188 DQ Delay:
6988 13:22:04.757235 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6989 13:22:04.761074 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
6990 13:22:04.763814 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6991 13:22:04.767311 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6992 13:22:04.767869
6993 13:22:04.768227
6994 13:22:04.777380 [DQSOSCAuto] RK1, (LSB)MR18= 0x695a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
6995 13:22:04.777938 CH1 RK1: MR19=C0C, MR18=695A
6996 13:22:04.783954 CH1_RK1: MR19=0xC0C, MR18=0x695A, DQSOSC=396, MR23=63, INC=376, DEC=251
6997 13:22:04.786920 [RxdqsGatingPostProcess] freq 400
6998 13:22:04.793940 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6999 13:22:04.796927 best DQS0 dly(2T, 0.5T) = (0, 10)
7000 13:22:04.800199 best DQS1 dly(2T, 0.5T) = (0, 10)
7001 13:22:04.802939 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7002 13:22:04.806445 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7003 13:22:04.809812 best DQS0 dly(2T, 0.5T) = (0, 10)
7004 13:22:04.813136 best DQS1 dly(2T, 0.5T) = (0, 10)
7005 13:22:04.816501 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7006 13:22:04.819833 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7007 13:22:04.820293 Pre-setting of DQS Precalculation
7008 13:22:04.827059 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7009 13:22:04.833237 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7010 13:22:04.839355 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7011 13:22:04.839909
7012 13:22:04.840272
7013 13:22:04.842724 [Calibration Summary] 800 Mbps
7014 13:22:04.846012 CH 0, Rank 0
7015 13:22:04.846562 SW Impedance : PASS
7016 13:22:04.849099 DUTY Scan : NO K
7017 13:22:04.852578 ZQ Calibration : PASS
7018 13:22:04.853048 Jitter Meter : NO K
7019 13:22:04.856089 CBT Training : PASS
7020 13:22:04.859431 Write leveling : PASS
7021 13:22:04.859994 RX DQS gating : PASS
7022 13:22:04.862848 RX DQ/DQS(RDDQC) : PASS
7023 13:22:04.863399 TX DQ/DQS : PASS
7024 13:22:04.866366 RX DATLAT : PASS
7025 13:22:04.869506 RX DQ/DQS(Engine): PASS
7026 13:22:04.870202 TX OE : NO K
7027 13:22:04.872268 All Pass.
7028 13:22:04.872728
7029 13:22:04.873093 CH 0, Rank 1
7030 13:22:04.875488 SW Impedance : PASS
7031 13:22:04.875996 DUTY Scan : NO K
7032 13:22:04.879077 ZQ Calibration : PASS
7033 13:22:04.882364 Jitter Meter : NO K
7034 13:22:04.882963 CBT Training : PASS
7035 13:22:04.885633 Write leveling : NO K
7036 13:22:04.889651 RX DQS gating : PASS
7037 13:22:04.890203 RX DQ/DQS(RDDQC) : PASS
7038 13:22:04.892725 TX DQ/DQS : PASS
7039 13:22:04.895875 RX DATLAT : PASS
7040 13:22:04.896330 RX DQ/DQS(Engine): PASS
7041 13:22:04.899808 TX OE : NO K
7042 13:22:04.900367 All Pass.
7043 13:22:04.900731
7044 13:22:04.902031 CH 1, Rank 0
7045 13:22:04.902487 SW Impedance : PASS
7046 13:22:04.905769 DUTY Scan : NO K
7047 13:22:04.908748 ZQ Calibration : PASS
7048 13:22:04.909207 Jitter Meter : NO K
7049 13:22:04.912250 CBT Training : PASS
7050 13:22:04.915460 Write leveling : PASS
7051 13:22:04.916009 RX DQS gating : PASS
7052 13:22:04.918580 RX DQ/DQS(RDDQC) : PASS
7053 13:22:04.921957 TX DQ/DQS : PASS
7054 13:22:04.922415 RX DATLAT : PASS
7055 13:22:04.925356 RX DQ/DQS(Engine): PASS
7056 13:22:04.928334 TX OE : NO K
7057 13:22:04.928794 All Pass.
7058 13:22:04.929264
7059 13:22:04.929737 CH 1, Rank 1
7060 13:22:04.932089 SW Impedance : PASS
7061 13:22:04.934900 DUTY Scan : NO K
7062 13:22:04.935372 ZQ Calibration : PASS
7063 13:22:04.938266 Jitter Meter : NO K
7064 13:22:04.938859 CBT Training : PASS
7065 13:22:04.941910 Write leveling : NO K
7066 13:22:04.944690 RX DQS gating : PASS
7067 13:22:04.945151 RX DQ/DQS(RDDQC) : PASS
7068 13:22:04.949199 TX DQ/DQS : PASS
7069 13:22:04.951499 RX DATLAT : PASS
7070 13:22:04.951984 RX DQ/DQS(Engine): PASS
7071 13:22:04.954978 TX OE : NO K
7072 13:22:04.955439 All Pass.
7073 13:22:04.955802
7074 13:22:04.958567 DramC Write-DBI off
7075 13:22:04.961738 PER_BANK_REFRESH: Hybrid Mode
7076 13:22:04.962289 TX_TRACKING: ON
7077 13:22:04.971900 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7078 13:22:04.974721 [FAST_K] Save calibration result to emmc
7079 13:22:04.978153 dramc_set_vcore_voltage set vcore to 725000
7080 13:22:04.981418 Read voltage for 1600, 0
7081 13:22:04.982013 Vio18 = 0
7082 13:22:04.984718 Vcore = 725000
7083 13:22:04.985268 Vdram = 0
7084 13:22:04.985637 Vddq = 0
7085 13:22:04.985975 Vmddr = 0
7086 13:22:04.991366 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7087 13:22:04.998352 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7088 13:22:04.998973 MEM_TYPE=3, freq_sel=13
7089 13:22:05.001140 sv_algorithm_assistance_LP4_3733
7090 13:22:05.004779 ============ PULL DRAM RESETB DOWN ============
7091 13:22:05.011497 ========== PULL DRAM RESETB DOWN end =========
7092 13:22:05.014540 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7093 13:22:05.018072 ===================================
7094 13:22:05.020826 LPDDR4 DRAM CONFIGURATION
7095 13:22:05.024082 ===================================
7096 13:22:05.024547 EX_ROW_EN[0] = 0x0
7097 13:22:05.027545 EX_ROW_EN[1] = 0x0
7098 13:22:05.028095 LP4Y_EN = 0x0
7099 13:22:05.031454 WORK_FSP = 0x1
7100 13:22:05.032003 WL = 0x5
7101 13:22:05.034873 RL = 0x5
7102 13:22:05.035424 BL = 0x2
7103 13:22:05.037759 RPST = 0x0
7104 13:22:05.041066 RD_PRE = 0x0
7105 13:22:05.041621 WR_PRE = 0x1
7106 13:22:05.044757 WR_PST = 0x1
7107 13:22:05.045311 DBI_WR = 0x0
7108 13:22:05.047618 DBI_RD = 0x0
7109 13:22:05.048075 OTF = 0x1
7110 13:22:05.050636 ===================================
7111 13:22:05.054172 ===================================
7112 13:22:05.057530 ANA top config
7113 13:22:05.060493 ===================================
7114 13:22:05.061216 DLL_ASYNC_EN = 0
7115 13:22:05.063784 ALL_SLAVE_EN = 0
7116 13:22:05.067396 NEW_RANK_MODE = 1
7117 13:22:05.071106 DLL_IDLE_MODE = 1
7118 13:22:05.071564 LP45_APHY_COMB_EN = 1
7119 13:22:05.073948 TX_ODT_DIS = 0
7120 13:22:05.077170 NEW_8X_MODE = 1
7121 13:22:05.080758 ===================================
7122 13:22:05.083942 ===================================
7123 13:22:05.087180 data_rate = 3200
7124 13:22:05.090437 CKR = 1
7125 13:22:05.093608 DQ_P2S_RATIO = 8
7126 13:22:05.096983 ===================================
7127 13:22:05.097445 CA_P2S_RATIO = 8
7128 13:22:05.100679 DQ_CA_OPEN = 0
7129 13:22:05.103614 DQ_SEMI_OPEN = 0
7130 13:22:05.106360 CA_SEMI_OPEN = 0
7131 13:22:05.110275 CA_FULL_RATE = 0
7132 13:22:05.113432 DQ_CKDIV4_EN = 0
7133 13:22:05.113983 CA_CKDIV4_EN = 0
7134 13:22:05.116661 CA_PREDIV_EN = 0
7135 13:22:05.120080 PH8_DLY = 12
7136 13:22:05.123379 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7137 13:22:05.126968 DQ_AAMCK_DIV = 4
7138 13:22:05.130043 CA_AAMCK_DIV = 4
7139 13:22:05.133088 CA_ADMCK_DIV = 4
7140 13:22:05.133646 DQ_TRACK_CA_EN = 0
7141 13:22:05.136455 CA_PICK = 1600
7142 13:22:05.140055 CA_MCKIO = 1600
7143 13:22:05.143342 MCKIO_SEMI = 0
7144 13:22:05.146575 PLL_FREQ = 3068
7145 13:22:05.149781 DQ_UI_PI_RATIO = 32
7146 13:22:05.153057 CA_UI_PI_RATIO = 0
7147 13:22:05.156475 ===================================
7148 13:22:05.159473 ===================================
7149 13:22:05.159938 memory_type:LPDDR4
7150 13:22:05.163109 GP_NUM : 10
7151 13:22:05.165881 SRAM_EN : 1
7152 13:22:05.166431 MD32_EN : 0
7153 13:22:05.169366 ===================================
7154 13:22:05.172456 [ANA_INIT] >>>>>>>>>>>>>>
7155 13:22:05.176008 <<<<<< [CONFIGURE PHASE]: ANA_TX
7156 13:22:05.179482 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7157 13:22:05.182409 ===================================
7158 13:22:05.185793 data_rate = 3200,PCW = 0X7600
7159 13:22:05.189482 ===================================
7160 13:22:05.192219 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7161 13:22:05.195766 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7162 13:22:05.202406 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7163 13:22:05.208663 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7164 13:22:05.211935 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7165 13:22:05.215530 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7166 13:22:05.215995 [ANA_INIT] flow start
7167 13:22:05.218862 [ANA_INIT] PLL >>>>>>>>
7168 13:22:05.221942 [ANA_INIT] PLL <<<<<<<<
7169 13:22:05.222404 [ANA_INIT] MIDPI >>>>>>>>
7170 13:22:05.225144 [ANA_INIT] MIDPI <<<<<<<<
7171 13:22:05.228561 [ANA_INIT] DLL >>>>>>>>
7172 13:22:05.229112 [ANA_INIT] DLL <<<<<<<<
7173 13:22:05.232558 [ANA_INIT] flow end
7174 13:22:05.234802 ============ LP4 DIFF to SE enter ============
7175 13:22:05.242019 ============ LP4 DIFF to SE exit ============
7176 13:22:05.242577 [ANA_INIT] <<<<<<<<<<<<<
7177 13:22:05.245316 [Flow] Enable top DCM control >>>>>
7178 13:22:05.248858 [Flow] Enable top DCM control <<<<<
7179 13:22:05.251693 Enable DLL master slave shuffle
7180 13:22:05.259159 ==============================================================
7181 13:22:05.259719 Gating Mode config
7182 13:22:05.265943 ==============================================================
7183 13:22:05.268711 Config description:
7184 13:22:05.275023 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7185 13:22:05.281479 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7186 13:22:05.287719 SELPH_MODE 0: By rank 1: By Phase
7187 13:22:05.294691 ==============================================================
7188 13:22:05.297593 GAT_TRACK_EN = 1
7189 13:22:05.298057 RX_GATING_MODE = 2
7190 13:22:05.301076 RX_GATING_TRACK_MODE = 2
7191 13:22:05.304499 SELPH_MODE = 1
7192 13:22:05.307487 PICG_EARLY_EN = 1
7193 13:22:05.310987 VALID_LAT_VALUE = 1
7194 13:22:05.317614 ==============================================================
7195 13:22:05.322138 Enter into Gating configuration >>>>
7196 13:22:05.325293 Exit from Gating configuration <<<<
7197 13:22:05.327314 Enter into DVFS_PRE_config >>>>>
7198 13:22:05.337637 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7199 13:22:05.341404 Exit from DVFS_PRE_config <<<<<
7200 13:22:05.344536 Enter into PICG configuration >>>>
7201 13:22:05.347224 Exit from PICG configuration <<<<
7202 13:22:05.350801 [RX_INPUT] configuration >>>>>
7203 13:22:05.354166 [RX_INPUT] configuration <<<<<
7204 13:22:05.357197 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7205 13:22:05.363360 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7206 13:22:05.370184 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7207 13:22:05.376787 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7208 13:22:05.383350 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7209 13:22:05.386516 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7210 13:22:05.393133 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7211 13:22:05.396869 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7212 13:22:05.399952 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7213 13:22:05.403223 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7214 13:22:05.410153 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7215 13:22:05.412796 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7216 13:22:05.415954 ===================================
7217 13:22:05.419719 LPDDR4 DRAM CONFIGURATION
7218 13:22:05.423131 ===================================
7219 13:22:05.423686 EX_ROW_EN[0] = 0x0
7220 13:22:05.425884 EX_ROW_EN[1] = 0x0
7221 13:22:05.426342 LP4Y_EN = 0x0
7222 13:22:05.430032 WORK_FSP = 0x1
7223 13:22:05.430583 WL = 0x5
7224 13:22:05.432866 RL = 0x5
7225 13:22:05.433417 BL = 0x2
7226 13:22:05.436074 RPST = 0x0
7227 13:22:05.439115 RD_PRE = 0x0
7228 13:22:05.439573 WR_PRE = 0x1
7229 13:22:05.442891 WR_PST = 0x1
7230 13:22:05.443451 DBI_WR = 0x0
7231 13:22:05.446213 DBI_RD = 0x0
7232 13:22:05.446806 OTF = 0x1
7233 13:22:05.448710 ===================================
7234 13:22:05.452634 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7235 13:22:05.459215 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7236 13:22:05.463378 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7237 13:22:05.465891 ===================================
7238 13:22:05.469507 LPDDR4 DRAM CONFIGURATION
7239 13:22:05.472754 ===================================
7240 13:22:05.473311 EX_ROW_EN[0] = 0x10
7241 13:22:05.475282 EX_ROW_EN[1] = 0x0
7242 13:22:05.475771 LP4Y_EN = 0x0
7243 13:22:05.478880 WORK_FSP = 0x1
7244 13:22:05.482388 WL = 0x5
7245 13:22:05.483002 RL = 0x5
7246 13:22:05.485484 BL = 0x2
7247 13:22:05.486037 RPST = 0x0
7248 13:22:05.488500 RD_PRE = 0x0
7249 13:22:05.488958 WR_PRE = 0x1
7250 13:22:05.491982 WR_PST = 0x1
7251 13:22:05.492533 DBI_WR = 0x0
7252 13:22:05.495429 DBI_RD = 0x0
7253 13:22:05.495984 OTF = 0x1
7254 13:22:05.498533 ===================================
7255 13:22:05.504997 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7256 13:22:05.505688 ==
7257 13:22:05.508470 Dram Type= 6, Freq= 0, CH_0, rank 0
7258 13:22:05.511338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7259 13:22:05.514870 ==
7260 13:22:05.515677 [Duty_Offset_Calibration]
7261 13:22:05.518240 B0:1 B1:-1 CA:0
7262 13:22:05.518841
7263 13:22:05.521587 [DutyScan_Calibration_Flow] k_type=0
7264 13:22:05.530380
7265 13:22:05.530971 ==CLK 0==
7266 13:22:05.533716 Final CLK duty delay cell = 0
7267 13:22:05.537518 [0] MAX Duty = 5156%(X100), DQS PI = 24
7268 13:22:05.540307 [0] MIN Duty = 4907%(X100), DQS PI = 4
7269 13:22:05.543520 [0] AVG Duty = 5031%(X100)
7270 13:22:05.544072
7271 13:22:05.546701 CH0 CLK Duty spec in!! Max-Min= 249%
7272 13:22:05.549968 [DutyScan_Calibration_Flow] ====Done====
7273 13:22:05.550423
7274 13:22:05.553509 [DutyScan_Calibration_Flow] k_type=1
7275 13:22:05.569815
7276 13:22:05.570486 ==DQS 0 ==
7277 13:22:05.572921 Final DQS duty delay cell = -4
7278 13:22:05.575832 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7279 13:22:05.579570 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7280 13:22:05.582847 [-4] AVG Duty = 4922%(X100)
7281 13:22:05.583310
7282 13:22:05.583673 ==DQS 1 ==
7283 13:22:05.586088 Final DQS duty delay cell = 0
7284 13:22:05.589670 [0] MAX Duty = 5156%(X100), DQS PI = 2
7285 13:22:05.592272 [0] MIN Duty = 5031%(X100), DQS PI = 20
7286 13:22:05.596369 [0] AVG Duty = 5093%(X100)
7287 13:22:05.596825
7288 13:22:05.599208 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7289 13:22:05.599756
7290 13:22:05.602353 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7291 13:22:05.605979 [DutyScan_Calibration_Flow] ====Done====
7292 13:22:05.606542
7293 13:22:05.609081 [DutyScan_Calibration_Flow] k_type=3
7294 13:22:05.627767
7295 13:22:05.628320 ==DQM 0 ==
7296 13:22:05.630636 Final DQM duty delay cell = 0
7297 13:22:05.634047 [0] MAX Duty = 5124%(X100), DQS PI = 20
7298 13:22:05.637238 [0] MIN Duty = 4907%(X100), DQS PI = 10
7299 13:22:05.640126 [0] AVG Duty = 5015%(X100)
7300 13:22:05.640577
7301 13:22:05.640932 ==DQM 1 ==
7302 13:22:05.643945 Final DQM duty delay cell = 0
7303 13:22:05.646650 [0] MAX Duty = 5031%(X100), DQS PI = 52
7304 13:22:05.649674 [0] MIN Duty = 4813%(X100), DQS PI = 20
7305 13:22:05.653401 [0] AVG Duty = 4922%(X100)
7306 13:22:05.653853
7307 13:22:05.656656 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7308 13:22:05.657108
7309 13:22:05.660187 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7310 13:22:05.662862 [DutyScan_Calibration_Flow] ====Done====
7311 13:22:05.663316
7312 13:22:05.666556 [DutyScan_Calibration_Flow] k_type=2
7313 13:22:05.683699
7314 13:22:05.684257 ==DQ 0 ==
7315 13:22:05.686759 Final DQ duty delay cell = -4
7316 13:22:05.690172 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7317 13:22:05.693532 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7318 13:22:05.697099 [-4] AVG Duty = 4953%(X100)
7319 13:22:05.697663
7320 13:22:05.698021 ==DQ 1 ==
7321 13:22:05.699811 Final DQ duty delay cell = 0
7322 13:22:05.703171 [0] MAX Duty = 5125%(X100), DQS PI = 4
7323 13:22:05.706683 [0] MIN Duty = 5000%(X100), DQS PI = 36
7324 13:22:05.709715 [0] AVG Duty = 5062%(X100)
7325 13:22:05.710169
7326 13:22:05.713112 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7327 13:22:05.713566
7328 13:22:05.716708 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7329 13:22:05.719686 [DutyScan_Calibration_Flow] ====Done====
7330 13:22:05.720254 ==
7331 13:22:05.722929 Dram Type= 6, Freq= 0, CH_1, rank 0
7332 13:22:05.726280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7333 13:22:05.726770 ==
7334 13:22:05.729858 [Duty_Offset_Calibration]
7335 13:22:05.730407 B0:-1 B1:1 CA:2
7336 13:22:05.730815
7337 13:22:05.733375 [DutyScan_Calibration_Flow] k_type=0
7338 13:22:05.744299
7339 13:22:05.744842 ==CLK 0==
7340 13:22:05.747280 Final CLK duty delay cell = 0
7341 13:22:05.750912 [0] MAX Duty = 5187%(X100), DQS PI = 22
7342 13:22:05.754187 [0] MIN Duty = 4969%(X100), DQS PI = 0
7343 13:22:05.757643 [0] AVG Duty = 5078%(X100)
7344 13:22:05.758188
7345 13:22:05.760581 CH1 CLK Duty spec in!! Max-Min= 218%
7346 13:22:05.763876 [DutyScan_Calibration_Flow] ====Done====
7347 13:22:05.764426
7348 13:22:05.767070 [DutyScan_Calibration_Flow] k_type=1
7349 13:22:05.783765
7350 13:22:05.784310 ==DQS 0 ==
7351 13:22:05.787330 Final DQS duty delay cell = 0
7352 13:22:05.790279 [0] MAX Duty = 5156%(X100), DQS PI = 18
7353 13:22:05.794365 [0] MIN Duty = 4907%(X100), DQS PI = 10
7354 13:22:05.797383 [0] AVG Duty = 5031%(X100)
7355 13:22:05.797928
7356 13:22:05.798289 ==DQS 1 ==
7357 13:22:05.800158 Final DQS duty delay cell = 0
7358 13:22:05.803388 [0] MAX Duty = 5093%(X100), DQS PI = 26
7359 13:22:05.807029 [0] MIN Duty = 4969%(X100), DQS PI = 56
7360 13:22:05.810239 [0] AVG Duty = 5031%(X100)
7361 13:22:05.810955
7362 13:22:05.813049 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7363 13:22:05.813500
7364 13:22:05.816406 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7365 13:22:05.820005 [DutyScan_Calibration_Flow] ====Done====
7366 13:22:05.820460
7367 13:22:05.822995 [DutyScan_Calibration_Flow] k_type=3
7368 13:22:05.840086
7369 13:22:05.840641 ==DQM 0 ==
7370 13:22:05.843029 Final DQM duty delay cell = -4
7371 13:22:05.846379 [-4] MAX Duty = 5062%(X100), DQS PI = 18
7372 13:22:05.850034 [-4] MIN Duty = 4782%(X100), DQS PI = 10
7373 13:22:05.852933 [-4] AVG Duty = 4922%(X100)
7374 13:22:05.853389
7375 13:22:05.853752 ==DQM 1 ==
7376 13:22:05.856321 Final DQM duty delay cell = 0
7377 13:22:05.860078 [0] MAX Duty = 5156%(X100), DQS PI = 2
7378 13:22:05.863567 [0] MIN Duty = 4969%(X100), DQS PI = 28
7379 13:22:05.866225 [0] AVG Duty = 5062%(X100)
7380 13:22:05.866732
7381 13:22:05.869478 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7382 13:22:05.870033
7383 13:22:05.872698 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7384 13:22:05.876099 [DutyScan_Calibration_Flow] ====Done====
7385 13:22:05.876556
7386 13:22:05.879964 [DutyScan_Calibration_Flow] k_type=2
7387 13:22:05.897317
7388 13:22:05.897866 ==DQ 0 ==
7389 13:22:05.900717 Final DQ duty delay cell = 0
7390 13:22:05.903521 [0] MAX Duty = 5156%(X100), DQS PI = 32
7391 13:22:05.906858 [0] MIN Duty = 4906%(X100), DQS PI = 10
7392 13:22:05.910218 [0] AVG Duty = 5031%(X100)
7393 13:22:05.910817
7394 13:22:05.911193 ==DQ 1 ==
7395 13:22:05.914365 Final DQ duty delay cell = 0
7396 13:22:05.917048 [0] MAX Duty = 5156%(X100), DQS PI = 8
7397 13:22:05.920057 [0] MIN Duty = 4969%(X100), DQS PI = 56
7398 13:22:05.920518 [0] AVG Duty = 5062%(X100)
7399 13:22:05.923354
7400 13:22:05.926446 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7401 13:22:05.926942
7402 13:22:05.930285 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7403 13:22:05.933724 [DutyScan_Calibration_Flow] ====Done====
7404 13:22:05.936886 nWR fixed to 30
7405 13:22:05.937441 [ModeRegInit_LP4] CH0 RK0
7406 13:22:05.940035 [ModeRegInit_LP4] CH0 RK1
7407 13:22:05.943089 [ModeRegInit_LP4] CH1 RK0
7408 13:22:05.946229 [ModeRegInit_LP4] CH1 RK1
7409 13:22:05.946734 match AC timing 5
7410 13:22:05.952767 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7411 13:22:05.956761 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7412 13:22:05.959627 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7413 13:22:05.966470 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7414 13:22:05.969291 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7415 13:22:05.969846 [MiockJmeterHQA]
7416 13:22:05.970213
7417 13:22:05.972758 [DramcMiockJmeter] u1RxGatingPI = 0
7418 13:22:05.976352 0 : 4363, 4137
7419 13:22:05.976852 4 : 4252, 4026
7420 13:22:05.979472 8 : 4363, 4137
7421 13:22:05.979941 12 : 4253, 4027
7422 13:22:05.982750 16 : 4253, 4026
7423 13:22:05.983168 20 : 4363, 4137
7424 13:22:05.983505 24 : 4363, 4137
7425 13:22:05.985969 28 : 4253, 4027
7426 13:22:05.986386 32 : 4253, 4027
7427 13:22:05.989391 36 : 4252, 4027
7428 13:22:05.989910 40 : 4363, 4137
7429 13:22:05.993188 44 : 4253, 4027
7430 13:22:05.993705 48 : 4363, 4138
7431 13:22:05.996416 52 : 4253, 4026
7432 13:22:05.996930 56 : 4252, 4027
7433 13:22:05.997271 60 : 4250, 4027
7434 13:22:05.999336 64 : 4253, 4029
7435 13:22:05.999756 68 : 4360, 4137
7436 13:22:06.002356 72 : 4250, 4026
7437 13:22:06.002800 76 : 4360, 4138
7438 13:22:06.005906 80 : 4249, 4027
7439 13:22:06.006325 84 : 4250, 4027
7440 13:22:06.009271 88 : 4249, 4027
7441 13:22:06.009690 92 : 4360, 785
7442 13:22:06.010027 96 : 4253, 0
7443 13:22:06.012572 100 : 4250, 0
7444 13:22:06.013094 104 : 4361, 0
7445 13:22:06.013434 108 : 4360, 0
7446 13:22:06.015989 112 : 4363, 0
7447 13:22:06.016508 116 : 4250, 0
7448 13:22:06.019150 120 : 4250, 0
7449 13:22:06.019573 124 : 4363, 0
7450 13:22:06.019908 128 : 4250, 0
7451 13:22:06.022329 132 : 4250, 0
7452 13:22:06.022781 136 : 4250, 0
7453 13:22:06.025755 140 : 4252, 0
7454 13:22:06.026177 144 : 4250, 0
7455 13:22:06.026512 148 : 4250, 0
7456 13:22:06.029173 152 : 4253, 0
7457 13:22:06.029688 156 : 4250, 0
7458 13:22:06.032224 160 : 4360, 0
7459 13:22:06.032744 164 : 4250, 0
7460 13:22:06.033079 168 : 4250, 0
7461 13:22:06.035576 172 : 4249, 0
7462 13:22:06.036107 176 : 4250, 0
7463 13:22:06.038218 180 : 4250, 0
7464 13:22:06.038685 184 : 4252, 0
7465 13:22:06.039031 188 : 4249, 0
7466 13:22:06.041491 192 : 4253, 0
7467 13:22:06.041911 196 : 4360, 0
7468 13:22:06.045079 200 : 4249, 0
7469 13:22:06.045498 204 : 4250, 0
7470 13:22:06.045834 208 : 4361, 0
7471 13:22:06.048679 212 : 4361, 0
7472 13:22:06.049100 216 : 4363, 0
7473 13:22:06.051358 220 : 4250, 0
7474 13:22:06.051775 224 : 4250, 209
7475 13:22:06.052111 228 : 4253, 3425
7476 13:22:06.055265 232 : 4361, 4137
7477 13:22:06.055756 236 : 4250, 4027
7478 13:22:06.058373 240 : 4249, 4027
7479 13:22:06.058835 244 : 4250, 4026
7480 13:22:06.061437 248 : 4253, 4029
7481 13:22:06.061857 252 : 4250, 4027
7482 13:22:06.064797 256 : 4249, 4027
7483 13:22:06.065218 260 : 4250, 4026
7484 13:22:06.068130 264 : 4250, 4027
7485 13:22:06.068548 268 : 4250, 4027
7486 13:22:06.071408 272 : 4361, 4138
7487 13:22:06.071827 276 : 4360, 4137
7488 13:22:06.074567 280 : 4250, 4027
7489 13:22:06.075053 284 : 4363, 4140
7490 13:22:06.077716 288 : 4250, 4027
7491 13:22:06.078135 292 : 4250, 4027
7492 13:22:06.078473 296 : 4250, 4026
7493 13:22:06.081057 300 : 4253, 4029
7494 13:22:06.081439 304 : 4250, 4027
7495 13:22:06.084396 308 : 4250, 4027
7496 13:22:06.084817 312 : 4250, 4026
7497 13:22:06.087550 316 : 4253, 4029
7498 13:22:06.087971 320 : 4250, 4027
7499 13:22:06.090946 324 : 4361, 4138
7500 13:22:06.091371 328 : 4360, 4137
7501 13:22:06.094635 332 : 4250, 4027
7502 13:22:06.095060 336 : 4363, 3991
7503 13:22:06.097954 340 : 4250, 1817
7504 13:22:06.098371
7505 13:22:06.098748 MIOCK jitter meter ch=0
7506 13:22:06.099065
7507 13:22:06.100878 1T = (340-92) = 248 dly cells
7508 13:22:06.108055 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7509 13:22:06.108721 ==
7510 13:22:06.111080 Dram Type= 6, Freq= 0, CH_0, rank 0
7511 13:22:06.114325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7512 13:22:06.114910 ==
7513 13:22:06.121163 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7514 13:22:06.124242 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7515 13:22:06.130694 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7516 13:22:06.134455 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7517 13:22:06.144134 [CA 0] Center 43 (13~74) winsize 62
7518 13:22:06.147404 [CA 1] Center 43 (13~74) winsize 62
7519 13:22:06.150853 [CA 2] Center 39 (10~69) winsize 60
7520 13:22:06.154366 [CA 3] Center 39 (10~68) winsize 59
7521 13:22:06.157519 [CA 4] Center 37 (8~66) winsize 59
7522 13:22:06.160551 [CA 5] Center 36 (7~66) winsize 60
7523 13:22:06.161100
7524 13:22:06.163819 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7525 13:22:06.164280
7526 13:22:06.170497 [CATrainingPosCal] consider 1 rank data
7527 13:22:06.171107 u2DelayCellTimex100 = 262/100 ps
7528 13:22:06.177214 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7529 13:22:06.180462 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7530 13:22:06.183689 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7531 13:22:06.186705 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7532 13:22:06.190449 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7533 13:22:06.194323 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7534 13:22:06.194939
7535 13:22:06.196971 CA PerBit enable=1, Macro0, CA PI delay=36
7536 13:22:06.200552
7537 13:22:06.201101 [CBTSetCACLKResult] CA Dly = 36
7538 13:22:06.203308 CS Dly: 11 (0~42)
7539 13:22:06.207052 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7540 13:22:06.209881 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7541 13:22:06.210340 ==
7542 13:22:06.213433 Dram Type= 6, Freq= 0, CH_0, rank 1
7543 13:22:06.219776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7544 13:22:06.220317 ==
7545 13:22:06.223541 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7546 13:22:06.230400 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7547 13:22:06.233246 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7548 13:22:06.239568 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7549 13:22:06.247984 [CA 0] Center 43 (13~74) winsize 62
7550 13:22:06.251512 [CA 1] Center 44 (14~74) winsize 61
7551 13:22:06.255025 [CA 2] Center 38 (9~68) winsize 60
7552 13:22:06.258075 [CA 3] Center 38 (9~68) winsize 60
7553 13:22:06.261339 [CA 4] Center 36 (7~66) winsize 60
7554 13:22:06.264756 [CA 5] Center 36 (6~66) winsize 61
7555 13:22:06.265317
7556 13:22:06.267701 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7557 13:22:06.268238
7558 13:22:06.271355 [CATrainingPosCal] consider 2 rank data
7559 13:22:06.274798 u2DelayCellTimex100 = 262/100 ps
7560 13:22:06.281385 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7561 13:22:06.284946 CA1 delay=44 (14~74),Diff = 8 PI (29 cell)
7562 13:22:06.287966 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7563 13:22:06.291109 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7564 13:22:06.295026 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7565 13:22:06.297732 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7566 13:22:06.298283
7567 13:22:06.300990 CA PerBit enable=1, Macro0, CA PI delay=36
7568 13:22:06.301544
7569 13:22:06.305372 [CBTSetCACLKResult] CA Dly = 36
7570 13:22:06.307538 CS Dly: 12 (0~44)
7571 13:22:06.310774 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7572 13:22:06.314135 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7573 13:22:06.314747
7574 13:22:06.318197 ----->DramcWriteLeveling(PI) begin...
7575 13:22:06.318825 ==
7576 13:22:06.320598 Dram Type= 6, Freq= 0, CH_0, rank 0
7577 13:22:06.328302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7578 13:22:06.328903 ==
7579 13:22:06.330518 Write leveling (Byte 0): 35 => 35
7580 13:22:06.334224 Write leveling (Byte 1): 26 => 26
7581 13:22:06.334837 DramcWriteLeveling(PI) end<-----
7582 13:22:06.337228
7583 13:22:06.337782 ==
7584 13:22:06.341135 Dram Type= 6, Freq= 0, CH_0, rank 0
7585 13:22:06.344223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7586 13:22:06.344779 ==
7587 13:22:06.347083 [Gating] SW mode calibration
7588 13:22:06.353820 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7589 13:22:06.360325 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7590 13:22:06.363581 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 13:22:06.366984 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 13:22:06.373470 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 13:22:06.377000 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7594 13:22:06.380626 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7595 13:22:06.386728 1 4 20 | B1->B0 | 2222 3434 | 1 1 | (0 0) (1 1)
7596 13:22:06.390251 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 13:22:06.393569 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7598 13:22:06.400546 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7599 13:22:06.403595 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 13:22:06.406647 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7601 13:22:06.409840 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
7602 13:22:06.416743 1 5 16 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
7603 13:22:06.419736 1 5 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
7604 13:22:06.426773 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7605 13:22:06.429601 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 13:22:06.433244 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 13:22:06.436487 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 13:22:06.442910 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 13:22:06.445883 1 6 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7610 13:22:06.449421 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7611 13:22:06.455824 1 6 20 | B1->B0 | 2e2e 4646 | 1 0 | (0 0) (0 0)
7612 13:22:06.458988 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7613 13:22:06.465980 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 13:22:06.469130 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 13:22:06.472264 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 13:22:06.478728 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 13:22:06.482699 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7618 13:22:06.485998 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7619 13:22:06.492627 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7620 13:22:06.495361 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7621 13:22:06.498711 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 13:22:06.505151 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 13:22:06.508987 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 13:22:06.511951 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 13:22:06.518749 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 13:22:06.521747 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 13:22:06.525029 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 13:22:06.531446 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 13:22:06.535029 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 13:22:06.538554 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 13:22:06.544994 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 13:22:06.547942 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7633 13:22:06.551984 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7634 13:22:06.554577 Total UI for P1: 0, mck2ui 16
7635 13:22:06.558278 best dqsien dly found for B0: ( 1, 9, 8)
7636 13:22:06.561374 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7637 13:22:06.568056 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7638 13:22:06.570884 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 13:22:06.574349 Total UI for P1: 0, mck2ui 16
7640 13:22:06.577709 best dqsien dly found for B1: ( 1, 9, 20)
7641 13:22:06.581433 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7642 13:22:06.584321 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7643 13:22:06.584882
7644 13:22:06.588188 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7645 13:22:06.594762 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7646 13:22:06.595312 [Gating] SW calibration Done
7647 13:22:06.597869 ==
7648 13:22:06.598420 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 13:22:06.604595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 13:22:06.605147 ==
7651 13:22:06.605515 RX Vref Scan: 0
7652 13:22:06.605856
7653 13:22:06.607737 RX Vref 0 -> 0, step: 1
7654 13:22:06.608291
7655 13:22:06.610446 RX Delay 0 -> 252, step: 8
7656 13:22:06.614389 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7657 13:22:06.617366 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7658 13:22:06.620916 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7659 13:22:06.627263 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7660 13:22:06.631086 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7661 13:22:06.634170 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7662 13:22:06.637215 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7663 13:22:06.640337 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7664 13:22:06.647146 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7665 13:22:06.651185 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7666 13:22:06.653885 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7667 13:22:06.657320 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7668 13:22:06.660696 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7669 13:22:06.667062 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7670 13:22:06.670183 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7671 13:22:06.673702 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7672 13:22:06.674255 ==
7673 13:22:06.676683 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 13:22:06.680004 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 13:22:06.683211 ==
7676 13:22:06.683666 DQS Delay:
7677 13:22:06.684030 DQS0 = 0, DQS1 = 0
7678 13:22:06.686474 DQM Delay:
7679 13:22:06.686984 DQM0 = 135, DQM1 = 126
7680 13:22:06.690177 DQ Delay:
7681 13:22:06.693401 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7682 13:22:06.696554 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =147
7683 13:22:06.699894 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7684 13:22:06.703259 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7685 13:22:06.703814
7686 13:22:06.704178
7687 13:22:06.704522 ==
7688 13:22:06.706161 Dram Type= 6, Freq= 0, CH_0, rank 0
7689 13:22:06.710010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7690 13:22:06.710569 ==
7691 13:22:06.713003
7692 13:22:06.713455
7693 13:22:06.713815 TX Vref Scan disable
7694 13:22:06.717117 == TX Byte 0 ==
7695 13:22:06.719707 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7696 13:22:06.723136 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7697 13:22:06.726578 == TX Byte 1 ==
7698 13:22:06.729533 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7699 13:22:06.732937 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7700 13:22:06.733491 ==
7701 13:22:06.736217 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 13:22:06.742825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 13:22:06.743285 ==
7704 13:22:06.756653
7705 13:22:06.758698 TX Vref early break, caculate TX vref
7706 13:22:06.761899 TX Vref=16, minBit 6, minWin=22, winSum=371
7707 13:22:06.765397 TX Vref=18, minBit 0, minWin=23, winSum=378
7708 13:22:06.768659 TX Vref=20, minBit 3, minWin=23, winSum=385
7709 13:22:06.772863 TX Vref=22, minBit 4, minWin=24, winSum=401
7710 13:22:06.775673 TX Vref=24, minBit 1, minWin=25, winSum=412
7711 13:22:06.781860 TX Vref=26, minBit 7, minWin=24, winSum=413
7712 13:22:06.785363 TX Vref=28, minBit 0, minWin=25, winSum=418
7713 13:22:06.789036 TX Vref=30, minBit 0, minWin=24, winSum=406
7714 13:22:06.791641 TX Vref=32, minBit 0, minWin=24, winSum=398
7715 13:22:06.795311 TX Vref=34, minBit 4, minWin=22, winSum=386
7716 13:22:06.801852 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
7717 13:22:06.802421
7718 13:22:06.805669 Final TX Range 0 Vref 28
7719 13:22:06.806218
7720 13:22:06.806584 ==
7721 13:22:06.808260 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 13:22:06.811439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 13:22:06.811942 ==
7724 13:22:06.812375
7725 13:22:06.812941
7726 13:22:06.814523 TX Vref Scan disable
7727 13:22:06.821431 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7728 13:22:06.821890 == TX Byte 0 ==
7729 13:22:06.824932 u2DelayCellOfst[0]=14 cells (4 PI)
7730 13:22:06.828333 u2DelayCellOfst[1]=18 cells (5 PI)
7731 13:22:06.831527 u2DelayCellOfst[2]=14 cells (4 PI)
7732 13:22:06.834644 u2DelayCellOfst[3]=14 cells (4 PI)
7733 13:22:06.838247 u2DelayCellOfst[4]=11 cells (3 PI)
7734 13:22:06.841679 u2DelayCellOfst[5]=0 cells (0 PI)
7735 13:22:06.844471 u2DelayCellOfst[6]=18 cells (5 PI)
7736 13:22:06.847605 u2DelayCellOfst[7]=22 cells (6 PI)
7737 13:22:06.850911 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7738 13:22:06.854222 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7739 13:22:06.857506 == TX Byte 1 ==
7740 13:22:06.861170 u2DelayCellOfst[8]=0 cells (0 PI)
7741 13:22:06.864116 u2DelayCellOfst[9]=3 cells (1 PI)
7742 13:22:06.867302 u2DelayCellOfst[10]=7 cells (2 PI)
7743 13:22:06.867761 u2DelayCellOfst[11]=3 cells (1 PI)
7744 13:22:06.870919 u2DelayCellOfst[12]=14 cells (4 PI)
7745 13:22:06.874250 u2DelayCellOfst[13]=14 cells (4 PI)
7746 13:22:06.877589 u2DelayCellOfst[14]=14 cells (4 PI)
7747 13:22:06.880644 u2DelayCellOfst[15]=11 cells (3 PI)
7748 13:22:06.887553 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7749 13:22:06.891055 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7750 13:22:06.891637 DramC Write-DBI on
7751 13:22:06.894741 ==
7752 13:22:06.897662 Dram Type= 6, Freq= 0, CH_0, rank 0
7753 13:22:06.900818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7754 13:22:06.901373 ==
7755 13:22:06.901739
7756 13:22:06.902076
7757 13:22:06.903356 TX Vref Scan disable
7758 13:22:06.903814 == TX Byte 0 ==
7759 13:22:06.910870 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7760 13:22:06.911437 == TX Byte 1 ==
7761 13:22:06.913520 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7762 13:22:06.917278 DramC Write-DBI off
7763 13:22:06.917829
7764 13:22:06.918193 [DATLAT]
7765 13:22:06.920722 Freq=1600, CH0 RK0
7766 13:22:06.921176
7767 13:22:06.921532 DATLAT Default: 0xf
7768 13:22:06.923207 0, 0xFFFF, sum = 0
7769 13:22:06.923672 1, 0xFFFF, sum = 0
7770 13:22:06.926752 2, 0xFFFF, sum = 0
7771 13:22:06.929653 3, 0xFFFF, sum = 0
7772 13:22:06.930113 4, 0xFFFF, sum = 0
7773 13:22:06.933436 5, 0xFFFF, sum = 0
7774 13:22:06.934008 6, 0xFFFF, sum = 0
7775 13:22:06.936675 7, 0xFFFF, sum = 0
7776 13:22:06.937236 8, 0xFFFF, sum = 0
7777 13:22:06.939927 9, 0xFFFF, sum = 0
7778 13:22:06.940488 10, 0xFFFF, sum = 0
7779 13:22:06.943514 11, 0xFFFF, sum = 0
7780 13:22:06.944079 12, 0xFFFF, sum = 0
7781 13:22:06.946104 13, 0xFFFF, sum = 0
7782 13:22:06.946582 14, 0x0, sum = 1
7783 13:22:06.949659 15, 0x0, sum = 2
7784 13:22:06.950120 16, 0x0, sum = 3
7785 13:22:06.952710 17, 0x0, sum = 4
7786 13:22:06.953173 best_step = 15
7787 13:22:06.953535
7788 13:22:06.953871 ==
7789 13:22:06.956585 Dram Type= 6, Freq= 0, CH_0, rank 0
7790 13:22:06.962829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7791 13:22:06.963376 ==
7792 13:22:06.963743 RX Vref Scan: 1
7793 13:22:06.964081
7794 13:22:06.966526 Set Vref Range= 24 -> 127
7795 13:22:06.967019
7796 13:22:06.969114 RX Vref 24 -> 127, step: 1
7797 13:22:06.969570
7798 13:22:06.969931 RX Delay 19 -> 252, step: 4
7799 13:22:06.973089
7800 13:22:06.973549 Set Vref, RX VrefLevel [Byte0]: 24
7801 13:22:06.975595 [Byte1]: 24
7802 13:22:06.981031
7803 13:22:06.981636 Set Vref, RX VrefLevel [Byte0]: 25
7804 13:22:06.984073 [Byte1]: 25
7805 13:22:06.988314
7806 13:22:06.988872 Set Vref, RX VrefLevel [Byte0]: 26
7807 13:22:06.991198 [Byte1]: 26
7808 13:22:06.995395
7809 13:22:06.995951 Set Vref, RX VrefLevel [Byte0]: 27
7810 13:22:06.998692 [Byte1]: 27
7811 13:22:07.003183
7812 13:22:07.003738 Set Vref, RX VrefLevel [Byte0]: 28
7813 13:22:07.006648 [Byte1]: 28
7814 13:22:07.010339
7815 13:22:07.010918 Set Vref, RX VrefLevel [Byte0]: 29
7816 13:22:07.013915 [Byte1]: 29
7817 13:22:07.017880
7818 13:22:07.018708 Set Vref, RX VrefLevel [Byte0]: 30
7819 13:22:07.021593 [Byte1]: 30
7820 13:22:07.026254
7821 13:22:07.026980 Set Vref, RX VrefLevel [Byte0]: 31
7822 13:22:07.029580 [Byte1]: 31
7823 13:22:07.033785
7824 13:22:07.034492 Set Vref, RX VrefLevel [Byte0]: 32
7825 13:22:07.036960 [Byte1]: 32
7826 13:22:07.040820
7827 13:22:07.041617 Set Vref, RX VrefLevel [Byte0]: 33
7828 13:22:07.043826 [Byte1]: 33
7829 13:22:07.048625
7830 13:22:07.049175 Set Vref, RX VrefLevel [Byte0]: 34
7831 13:22:07.051662 [Byte1]: 34
7832 13:22:07.056435
7833 13:22:07.056999 Set Vref, RX VrefLevel [Byte0]: 35
7834 13:22:07.059199 [Byte1]: 35
7835 13:22:07.064022
7836 13:22:07.064488 Set Vref, RX VrefLevel [Byte0]: 36
7837 13:22:07.066818 [Byte1]: 36
7838 13:22:07.071323
7839 13:22:07.071898 Set Vref, RX VrefLevel [Byte0]: 37
7840 13:22:07.074395 [Byte1]: 37
7841 13:22:07.078841
7842 13:22:07.079409 Set Vref, RX VrefLevel [Byte0]: 38
7843 13:22:07.082459 [Byte1]: 38
7844 13:22:07.086642
7845 13:22:07.087224 Set Vref, RX VrefLevel [Byte0]: 39
7846 13:22:07.089940 [Byte1]: 39
7847 13:22:07.093719
7848 13:22:07.094374 Set Vref, RX VrefLevel [Byte0]: 40
7849 13:22:07.097298 [Byte1]: 40
7850 13:22:07.101450
7851 13:22:07.102010 Set Vref, RX VrefLevel [Byte0]: 41
7852 13:22:07.104526 [Byte1]: 41
7853 13:22:07.108998
7854 13:22:07.109548 Set Vref, RX VrefLevel [Byte0]: 42
7855 13:22:07.112319 [Byte1]: 42
7856 13:22:07.116399
7857 13:22:07.116953 Set Vref, RX VrefLevel [Byte0]: 43
7858 13:22:07.119975 [Byte1]: 43
7859 13:22:07.124051
7860 13:22:07.124618 Set Vref, RX VrefLevel [Byte0]: 44
7861 13:22:07.127283 [Byte1]: 44
7862 13:22:07.131782
7863 13:22:07.132329 Set Vref, RX VrefLevel [Byte0]: 45
7864 13:22:07.134985 [Byte1]: 45
7865 13:22:07.139568
7866 13:22:07.140121 Set Vref, RX VrefLevel [Byte0]: 46
7867 13:22:07.142910 [Byte1]: 46
7868 13:22:07.146517
7869 13:22:07.147264 Set Vref, RX VrefLevel [Byte0]: 47
7870 13:22:07.150441 [Byte1]: 47
7871 13:22:07.154781
7872 13:22:07.155329 Set Vref, RX VrefLevel [Byte0]: 48
7873 13:22:07.157345 [Byte1]: 48
7874 13:22:07.162302
7875 13:22:07.162911 Set Vref, RX VrefLevel [Byte0]: 49
7876 13:22:07.165218 [Byte1]: 49
7877 13:22:07.169306
7878 13:22:07.169765 Set Vref, RX VrefLevel [Byte0]: 50
7879 13:22:07.173250 [Byte1]: 50
7880 13:22:07.177735
7881 13:22:07.178285 Set Vref, RX VrefLevel [Byte0]: 51
7882 13:22:07.180195 [Byte1]: 51
7883 13:22:07.184664
7884 13:22:07.185215 Set Vref, RX VrefLevel [Byte0]: 52
7885 13:22:07.188805 [Byte1]: 52
7886 13:22:07.192791
7887 13:22:07.193251 Set Vref, RX VrefLevel [Byte0]: 53
7888 13:22:07.196231 [Byte1]: 53
7889 13:22:07.199986
7890 13:22:07.200539 Set Vref, RX VrefLevel [Byte0]: 54
7891 13:22:07.203440 [Byte1]: 54
7892 13:22:07.207352
7893 13:22:07.207905 Set Vref, RX VrefLevel [Byte0]: 55
7894 13:22:07.210548 [Byte1]: 55
7895 13:22:07.214837
7896 13:22:07.215295 Set Vref, RX VrefLevel [Byte0]: 56
7897 13:22:07.218381 [Byte1]: 56
7898 13:22:07.223170
7899 13:22:07.223720 Set Vref, RX VrefLevel [Byte0]: 57
7900 13:22:07.225899 [Byte1]: 57
7901 13:22:07.230061
7902 13:22:07.230519 Set Vref, RX VrefLevel [Byte0]: 58
7903 13:22:07.233355 [Byte1]: 58
7904 13:22:07.237766
7905 13:22:07.238322 Set Vref, RX VrefLevel [Byte0]: 59
7906 13:22:07.241081 [Byte1]: 59
7907 13:22:07.245268
7908 13:22:07.245812 Set Vref, RX VrefLevel [Byte0]: 60
7909 13:22:07.248449 [Byte1]: 60
7910 13:22:07.253227
7911 13:22:07.256101 Set Vref, RX VrefLevel [Byte0]: 61
7912 13:22:07.258920 [Byte1]: 61
7913 13:22:07.259383
7914 13:22:07.262699 Set Vref, RX VrefLevel [Byte0]: 62
7915 13:22:07.266319 [Byte1]: 62
7916 13:22:07.266941
7917 13:22:07.269366 Set Vref, RX VrefLevel [Byte0]: 63
7918 13:22:07.272318 [Byte1]: 63
7919 13:22:07.272879
7920 13:22:07.275995 Set Vref, RX VrefLevel [Byte0]: 64
7921 13:22:07.279240 [Byte1]: 64
7922 13:22:07.283262
7923 13:22:07.283810 Set Vref, RX VrefLevel [Byte0]: 65
7924 13:22:07.289196 [Byte1]: 65
7925 13:22:07.289741
7926 13:22:07.293156 Set Vref, RX VrefLevel [Byte0]: 66
7927 13:22:07.296260 [Byte1]: 66
7928 13:22:07.296818
7929 13:22:07.299561 Set Vref, RX VrefLevel [Byte0]: 67
7930 13:22:07.302857 [Byte1]: 67
7931 13:22:07.303415
7932 13:22:07.306061 Set Vref, RX VrefLevel [Byte0]: 68
7933 13:22:07.309761 [Byte1]: 68
7934 13:22:07.313806
7935 13:22:07.314359 Set Vref, RX VrefLevel [Byte0]: 69
7936 13:22:07.316370 [Byte1]: 69
7937 13:22:07.321428
7938 13:22:07.321975 Set Vref, RX VrefLevel [Byte0]: 70
7939 13:22:07.324753 [Byte1]: 70
7940 13:22:07.328807
7941 13:22:07.329361 Set Vref, RX VrefLevel [Byte0]: 71
7942 13:22:07.331893 [Byte1]: 71
7943 13:22:07.336238
7944 13:22:07.336790 Set Vref, RX VrefLevel [Byte0]: 72
7945 13:22:07.339308 [Byte1]: 72
7946 13:22:07.344496
7947 13:22:07.345049 Set Vref, RX VrefLevel [Byte0]: 73
7948 13:22:07.347556 [Byte1]: 73
7949 13:22:07.351255
7950 13:22:07.351716 Set Vref, RX VrefLevel [Byte0]: 74
7951 13:22:07.354287 [Byte1]: 74
7952 13:22:07.359028
7953 13:22:07.359575 Set Vref, RX VrefLevel [Byte0]: 75
7954 13:22:07.362474 [Byte1]: 75
7955 13:22:07.366130
7956 13:22:07.366587 Set Vref, RX VrefLevel [Byte0]: 76
7957 13:22:07.370182 [Byte1]: 76
7958 13:22:07.373641
7959 13:22:07.374103 Set Vref, RX VrefLevel [Byte0]: 77
7960 13:22:07.377116 [Byte1]: 77
7961 13:22:07.381498
7962 13:22:07.382047 Set Vref, RX VrefLevel [Byte0]: 78
7963 13:22:07.384782 [Byte1]: 78
7964 13:22:07.389307
7965 13:22:07.389862 Set Vref, RX VrefLevel [Byte0]: 79
7966 13:22:07.392568 [Byte1]: 79
7967 13:22:07.396991
7968 13:22:07.397541 Final RX Vref Byte 0 = 68 to rank0
7969 13:22:07.399964 Final RX Vref Byte 1 = 60 to rank0
7970 13:22:07.403447 Final RX Vref Byte 0 = 68 to rank1
7971 13:22:07.406847 Final RX Vref Byte 1 = 60 to rank1==
7972 13:22:07.409539 Dram Type= 6, Freq= 0, CH_0, rank 0
7973 13:22:07.416180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7974 13:22:07.416719 ==
7975 13:22:07.417087 DQS Delay:
7976 13:22:07.419748 DQS0 = 0, DQS1 = 0
7977 13:22:07.420301 DQM Delay:
7978 13:22:07.420669 DQM0 = 133, DQM1 = 123
7979 13:22:07.423246 DQ Delay:
7980 13:22:07.426283 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =132
7981 13:22:07.429335 DQ4 =134, DQ5 =122, DQ6 =142, DQ7 =142
7982 13:22:07.432890 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
7983 13:22:07.436660 DQ12 =128, DQ13 =126, DQ14 =136, DQ15 =128
7984 13:22:07.437209
7985 13:22:07.437576
7986 13:22:07.437914
7987 13:22:07.439772 [DramC_TX_OE_Calibration] TA2
7988 13:22:07.443069 Original DQ_B0 (3 6) =30, OEN = 27
7989 13:22:07.446788 Original DQ_B1 (3 6) =30, OEN = 27
7990 13:22:07.449618 24, 0x0, End_B0=24 End_B1=24
7991 13:22:07.452537 25, 0x0, End_B0=25 End_B1=25
7992 13:22:07.453007 26, 0x0, End_B0=26 End_B1=26
7993 13:22:07.456120 27, 0x0, End_B0=27 End_B1=27
7994 13:22:07.459336 28, 0x0, End_B0=28 End_B1=28
7995 13:22:07.462689 29, 0x0, End_B0=29 End_B1=29
7996 13:22:07.463246 30, 0x0, End_B0=30 End_B1=30
7997 13:22:07.466047 31, 0x5151, End_B0=30 End_B1=30
7998 13:22:07.469153 Byte0 end_step=30 best_step=27
7999 13:22:07.472056 Byte1 end_step=30 best_step=27
8000 13:22:07.476523 Byte0 TX OE(2T, 0.5T) = (3, 3)
8001 13:22:07.479139 Byte1 TX OE(2T, 0.5T) = (3, 3)
8002 13:22:07.479601
8003 13:22:07.479963
8004 13:22:07.485529 [DQSOSCAuto] RK0, (LSB)MR18= 0x2214, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
8005 13:22:07.488901 CH0 RK0: MR19=303, MR18=2214
8006 13:22:07.496702 CH0_RK0: MR19=0x303, MR18=0x2214, DQSOSC=392, MR23=63, INC=24, DEC=16
8007 13:22:07.497256
8008 13:22:07.498740 ----->DramcWriteLeveling(PI) begin...
8009 13:22:07.499211 ==
8010 13:22:07.502085 Dram Type= 6, Freq= 0, CH_0, rank 1
8011 13:22:07.505814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8012 13:22:07.506368 ==
8013 13:22:07.509062 Write leveling (Byte 0): 35 => 35
8014 13:22:07.512669 Write leveling (Byte 1): 29 => 29
8015 13:22:07.515159 DramcWriteLeveling(PI) end<-----
8016 13:22:07.515615
8017 13:22:07.515977 ==
8018 13:22:07.518213 Dram Type= 6, Freq= 0, CH_0, rank 1
8019 13:22:07.525351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8020 13:22:07.525908 ==
8021 13:22:07.526276 [Gating] SW mode calibration
8022 13:22:07.535608 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8023 13:22:07.538225 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8024 13:22:07.541560 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 13:22:07.548144 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 13:22:07.551301 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 13:22:07.554666 1 4 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8028 13:22:07.561743 1 4 16 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8029 13:22:07.564826 1 4 20 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
8030 13:22:07.571331 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8031 13:22:07.574288 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8032 13:22:07.577501 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8033 13:22:07.584094 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8034 13:22:07.588079 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8035 13:22:07.591386 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8036 13:22:07.597760 1 5 16 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
8037 13:22:07.600990 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
8038 13:22:07.604409 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 13:22:07.611017 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 13:22:07.614200 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 13:22:07.617190 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 13:22:07.624013 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 13:22:07.627086 1 6 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8044 13:22:07.630464 1 6 16 | B1->B0 | 2424 4444 | 0 0 | (0 0) (0 0)
8045 13:22:07.637365 1 6 20 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
8046 13:22:07.640922 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 13:22:07.643345 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 13:22:07.650724 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8049 13:22:07.653341 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8050 13:22:07.656617 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8051 13:22:07.663127 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8052 13:22:07.666579 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8053 13:22:07.669999 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8054 13:22:07.676369 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 13:22:07.679775 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 13:22:07.683026 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 13:22:07.690176 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 13:22:07.692674 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 13:22:07.696503 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 13:22:07.703049 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 13:22:07.706360 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 13:22:07.709794 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 13:22:07.716093 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 13:22:07.719277 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 13:22:07.722744 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 13:22:07.729830 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8067 13:22:07.732549 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8068 13:22:07.736133 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8069 13:22:07.739425 Total UI for P1: 0, mck2ui 16
8070 13:22:07.743284 best dqsien dly found for B0: ( 1, 9, 10)
8071 13:22:07.746518 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8072 13:22:07.752354 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8073 13:22:07.755673 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 13:22:07.759364 Total UI for P1: 0, mck2ui 16
8075 13:22:07.762136 best dqsien dly found for B1: ( 1, 9, 20)
8076 13:22:07.765472 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8077 13:22:07.768836 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8078 13:22:07.769386
8079 13:22:07.772113 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8080 13:22:07.778862 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8081 13:22:07.779387 [Gating] SW calibration Done
8082 13:22:07.781906 ==
8083 13:22:07.785414 Dram Type= 6, Freq= 0, CH_0, rank 1
8084 13:22:07.788623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8085 13:22:07.789179 ==
8086 13:22:07.789546 RX Vref Scan: 0
8087 13:22:07.789883
8088 13:22:07.792038 RX Vref 0 -> 0, step: 1
8089 13:22:07.792590
8090 13:22:07.795264 RX Delay 0 -> 252, step: 8
8091 13:22:07.799620 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8092 13:22:07.802486 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8093 13:22:07.804844 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8094 13:22:07.812148 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8095 13:22:07.815288 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8096 13:22:07.818295 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8097 13:22:07.821551 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8098 13:22:07.825489 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8099 13:22:07.831391 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8100 13:22:07.834745 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8101 13:22:07.839155 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8102 13:22:07.842092 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8103 13:22:07.848125 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8104 13:22:07.851713 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8105 13:22:07.854810 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8106 13:22:07.858029 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8107 13:22:07.858582 ==
8108 13:22:07.860999 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 13:22:07.867981 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 13:22:07.868538 ==
8111 13:22:07.868905 DQS Delay:
8112 13:22:07.869245 DQS0 = 0, DQS1 = 0
8113 13:22:07.871395 DQM Delay:
8114 13:22:07.871850 DQM0 = 133, DQM1 = 128
8115 13:22:07.875322 DQ Delay:
8116 13:22:07.878953 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8117 13:22:07.881088 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8118 13:22:07.884521 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8119 13:22:07.887734 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8120 13:22:07.888290
8121 13:22:07.888653
8122 13:22:07.888994 ==
8123 13:22:07.890994 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 13:22:07.894021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 13:22:07.897747 ==
8126 13:22:07.898296
8127 13:22:07.898704
8128 13:22:07.899046 TX Vref Scan disable
8129 13:22:07.901117 == TX Byte 0 ==
8130 13:22:07.904744 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8131 13:22:07.907540 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8132 13:22:07.911166 == TX Byte 1 ==
8133 13:22:07.914386 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8134 13:22:07.917608 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8135 13:22:07.920780 ==
8136 13:22:07.924187 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 13:22:07.927325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 13:22:07.927890 ==
8139 13:22:07.940668
8140 13:22:07.943237 TX Vref early break, caculate TX vref
8141 13:22:07.946376 TX Vref=16, minBit 1, minWin=22, winSum=381
8142 13:22:07.950142 TX Vref=18, minBit 1, minWin=23, winSum=389
8143 13:22:07.953111 TX Vref=20, minBit 1, minWin=23, winSum=396
8144 13:22:07.956960 TX Vref=22, minBit 0, minWin=24, winSum=408
8145 13:22:07.959826 TX Vref=24, minBit 3, minWin=24, winSum=413
8146 13:22:07.966901 TX Vref=26, minBit 0, minWin=25, winSum=418
8147 13:22:07.969867 TX Vref=28, minBit 0, minWin=24, winSum=415
8148 13:22:07.972653 TX Vref=30, minBit 1, minWin=24, winSum=410
8149 13:22:07.976403 TX Vref=32, minBit 0, minWin=24, winSum=397
8150 13:22:07.979461 TX Vref=34, minBit 6, minWin=23, winSum=393
8151 13:22:07.986437 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 26
8152 13:22:07.987043
8153 13:22:07.989252 Final TX Range 0 Vref 26
8154 13:22:07.989808
8155 13:22:07.990167 ==
8156 13:22:07.993053 Dram Type= 6, Freq= 0, CH_0, rank 1
8157 13:22:07.995569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8158 13:22:07.996033 ==
8159 13:22:07.996401
8160 13:22:07.996739
8161 13:22:07.998904 TX Vref Scan disable
8162 13:22:08.005869 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8163 13:22:08.006424 == TX Byte 0 ==
8164 13:22:08.009250 u2DelayCellOfst[0]=14 cells (4 PI)
8165 13:22:08.012483 u2DelayCellOfst[1]=18 cells (5 PI)
8166 13:22:08.015229 u2DelayCellOfst[2]=14 cells (4 PI)
8167 13:22:08.018748 u2DelayCellOfst[3]=18 cells (5 PI)
8168 13:22:08.022309 u2DelayCellOfst[4]=11 cells (3 PI)
8169 13:22:08.025749 u2DelayCellOfst[5]=0 cells (0 PI)
8170 13:22:08.029054 u2DelayCellOfst[6]=22 cells (6 PI)
8171 13:22:08.032431 u2DelayCellOfst[7]=22 cells (6 PI)
8172 13:22:08.035987 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8173 13:22:08.038753 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8174 13:22:08.041866 == TX Byte 1 ==
8175 13:22:08.045064 u2DelayCellOfst[8]=0 cells (0 PI)
8176 13:22:08.048297 u2DelayCellOfst[9]=3 cells (1 PI)
8177 13:22:08.051455 u2DelayCellOfst[10]=7 cells (2 PI)
8178 13:22:08.054782 u2DelayCellOfst[11]=3 cells (1 PI)
8179 13:22:08.058028 u2DelayCellOfst[12]=14 cells (4 PI)
8180 13:22:08.061866 u2DelayCellOfst[13]=11 cells (3 PI)
8181 13:22:08.062332 u2DelayCellOfst[14]=18 cells (5 PI)
8182 13:22:08.064810 u2DelayCellOfst[15]=11 cells (3 PI)
8183 13:22:08.071250 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8184 13:22:08.074669 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8185 13:22:08.078258 DramC Write-DBI on
8186 13:22:08.078850 ==
8187 13:22:08.081260 Dram Type= 6, Freq= 0, CH_0, rank 1
8188 13:22:08.084904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8189 13:22:08.085420 ==
8190 13:22:08.085757
8191 13:22:08.086069
8192 13:22:08.088417 TX Vref Scan disable
8193 13:22:08.088933 == TX Byte 0 ==
8194 13:22:08.095138 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8195 13:22:08.095662 == TX Byte 1 ==
8196 13:22:08.098764 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8197 13:22:08.101762 DramC Write-DBI off
8198 13:22:08.102270
8199 13:22:08.102646 [DATLAT]
8200 13:22:08.104293 Freq=1600, CH0 RK1
8201 13:22:08.104807
8202 13:22:08.105142 DATLAT Default: 0xf
8203 13:22:08.107300 0, 0xFFFF, sum = 0
8204 13:22:08.111344 1, 0xFFFF, sum = 0
8205 13:22:08.111860 2, 0xFFFF, sum = 0
8206 13:22:08.114340 3, 0xFFFF, sum = 0
8207 13:22:08.114916 4, 0xFFFF, sum = 0
8208 13:22:08.118112 5, 0xFFFF, sum = 0
8209 13:22:08.118856 6, 0xFFFF, sum = 0
8210 13:22:08.120830 7, 0xFFFF, sum = 0
8211 13:22:08.121431 8, 0xFFFF, sum = 0
8212 13:22:08.123942 9, 0xFFFF, sum = 0
8213 13:22:08.124366 10, 0xFFFF, sum = 0
8214 13:22:08.127517 11, 0xFFFF, sum = 0
8215 13:22:08.127945 12, 0xFFFF, sum = 0
8216 13:22:08.130486 13, 0xFFFF, sum = 0
8217 13:22:08.130942 14, 0x0, sum = 1
8218 13:22:08.134022 15, 0x0, sum = 2
8219 13:22:08.134445 16, 0x0, sum = 3
8220 13:22:08.137951 17, 0x0, sum = 4
8221 13:22:08.138483 best_step = 15
8222 13:22:08.138884
8223 13:22:08.139201 ==
8224 13:22:08.141121 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 13:22:08.147090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 13:22:08.147616 ==
8227 13:22:08.147962 RX Vref Scan: 0
8228 13:22:08.148270
8229 13:22:08.150805 RX Vref 0 -> 0, step: 1
8230 13:22:08.151371
8231 13:22:08.154481 RX Delay 11 -> 252, step: 4
8232 13:22:08.157581 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8233 13:22:08.160354 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8234 13:22:08.163746 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8235 13:22:08.170438 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8236 13:22:08.173680 iDelay=191, Bit 4, Center 132 (79 ~ 186) 108
8237 13:22:08.177314 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8238 13:22:08.180359 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8239 13:22:08.183854 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8240 13:22:08.190486 iDelay=191, Bit 8, Center 116 (63 ~ 170) 108
8241 13:22:08.193758 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8242 13:22:08.196898 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8243 13:22:08.200391 iDelay=191, Bit 11, Center 120 (67 ~ 174) 108
8244 13:22:08.207218 iDelay=191, Bit 12, Center 130 (75 ~ 186) 112
8245 13:22:08.210200 iDelay=191, Bit 13, Center 132 (79 ~ 186) 108
8246 13:22:08.213655 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8247 13:22:08.216909 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8248 13:22:08.217427 ==
8249 13:22:08.219984 Dram Type= 6, Freq= 0, CH_0, rank 1
8250 13:22:08.226782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8251 13:22:08.227328 ==
8252 13:22:08.227676 DQS Delay:
8253 13:22:08.227986 DQS0 = 0, DQS1 = 0
8254 13:22:08.230087 DQM Delay:
8255 13:22:08.230633 DQM0 = 129, DQM1 = 125
8256 13:22:08.233167 DQ Delay:
8257 13:22:08.236834 DQ0 =126, DQ1 =132, DQ2 =124, DQ3 =126
8258 13:22:08.239574 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
8259 13:22:08.242892 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8260 13:22:08.246242 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8261 13:22:08.246783
8262 13:22:08.247117
8263 13:22:08.247423
8264 13:22:08.249878 [DramC_TX_OE_Calibration] TA2
8265 13:22:08.252781 Original DQ_B0 (3 6) =30, OEN = 27
8266 13:22:08.256622 Original DQ_B1 (3 6) =30, OEN = 27
8267 13:22:08.260277 24, 0x0, End_B0=24 End_B1=24
8268 13:22:08.262395 25, 0x0, End_B0=25 End_B1=25
8269 13:22:08.262879 26, 0x0, End_B0=26 End_B1=26
8270 13:22:08.265978 27, 0x0, End_B0=27 End_B1=27
8271 13:22:08.270270 28, 0x0, End_B0=28 End_B1=28
8272 13:22:08.272628 29, 0x0, End_B0=29 End_B1=29
8273 13:22:08.273051 30, 0x0, End_B0=30 End_B1=30
8274 13:22:08.276080 31, 0x4141, End_B0=30 End_B1=30
8275 13:22:08.279072 Byte0 end_step=30 best_step=27
8276 13:22:08.282304 Byte1 end_step=30 best_step=27
8277 13:22:08.285751 Byte0 TX OE(2T, 0.5T) = (3, 3)
8278 13:22:08.289118 Byte1 TX OE(2T, 0.5T) = (3, 3)
8279 13:22:08.289645
8280 13:22:08.289979
8281 13:22:08.295563 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e01, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8282 13:22:08.298950 CH0 RK1: MR19=303, MR18=1E01
8283 13:22:08.305913 CH0_RK1: MR19=0x303, MR18=0x1E01, DQSOSC=394, MR23=63, INC=23, DEC=15
8284 13:22:08.308947 [RxdqsGatingPostProcess] freq 1600
8285 13:22:08.312790 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8286 13:22:08.315456 best DQS0 dly(2T, 0.5T) = (1, 1)
8287 13:22:08.318556 best DQS1 dly(2T, 0.5T) = (1, 1)
8288 13:22:08.322371 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8289 13:22:08.325578 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8290 13:22:08.328694 best DQS0 dly(2T, 0.5T) = (1, 1)
8291 13:22:08.331989 best DQS1 dly(2T, 0.5T) = (1, 1)
8292 13:22:08.336042 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8293 13:22:08.338634 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8294 13:22:08.342206 Pre-setting of DQS Precalculation
8295 13:22:08.345689 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8296 13:22:08.346242 ==
8297 13:22:08.348357 Dram Type= 6, Freq= 0, CH_1, rank 0
8298 13:22:08.355597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8299 13:22:08.356059 ==
8300 13:22:08.358195 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8301 13:22:08.364831 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8302 13:22:08.367890 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8303 13:22:08.374674 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8304 13:22:08.382410 [CA 0] Center 41 (12~71) winsize 60
8305 13:22:08.385887 [CA 1] Center 42 (12~72) winsize 61
8306 13:22:08.389087 [CA 2] Center 37 (8~66) winsize 59
8307 13:22:08.392292 [CA 3] Center 35 (6~65) winsize 60
8308 13:22:08.395829 [CA 4] Center 36 (7~66) winsize 60
8309 13:22:08.399337 [CA 5] Center 36 (7~66) winsize 60
8310 13:22:08.399752
8311 13:22:08.402446 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8312 13:22:08.403016
8313 13:22:08.405374 [CATrainingPosCal] consider 1 rank data
8314 13:22:08.408764 u2DelayCellTimex100 = 262/100 ps
8315 13:22:08.415556 CA0 delay=41 (12~71),Diff = 6 PI (22 cell)
8316 13:22:08.418493 CA1 delay=42 (12~72),Diff = 7 PI (26 cell)
8317 13:22:08.422308 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8318 13:22:08.425745 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8319 13:22:08.428891 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
8320 13:22:08.431964 CA5 delay=36 (7~66),Diff = 1 PI (3 cell)
8321 13:22:08.432375
8322 13:22:08.435322 CA PerBit enable=1, Macro0, CA PI delay=35
8323 13:22:08.435870
8324 13:22:08.438695 [CBTSetCACLKResult] CA Dly = 35
8325 13:22:08.442085 CS Dly: 10 (0~41)
8326 13:22:08.446251 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8327 13:22:08.448545 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8328 13:22:08.449091 ==
8329 13:22:08.452101 Dram Type= 6, Freq= 0, CH_1, rank 1
8330 13:22:08.458376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8331 13:22:08.458967 ==
8332 13:22:08.461933 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8333 13:22:08.468420 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8334 13:22:08.471472 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8335 13:22:08.478055 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8336 13:22:08.486034 [CA 0] Center 42 (12~72) winsize 61
8337 13:22:08.489169 [CA 1] Center 42 (13~72) winsize 60
8338 13:22:08.492206 [CA 2] Center 37 (8~67) winsize 60
8339 13:22:08.496144 [CA 3] Center 36 (7~66) winsize 60
8340 13:22:08.499073 [CA 4] Center 37 (8~67) winsize 60
8341 13:22:08.502633 [CA 5] Center 36 (7~66) winsize 60
8342 13:22:08.503186
8343 13:22:08.506122 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8344 13:22:08.506708
8345 13:22:08.509978 [CATrainingPosCal] consider 2 rank data
8346 13:22:08.511989 u2DelayCellTimex100 = 262/100 ps
8347 13:22:08.518911 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8348 13:22:08.522424 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8349 13:22:08.525088 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8350 13:22:08.528523 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8351 13:22:08.531906 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8352 13:22:08.535152 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8353 13:22:08.535609
8354 13:22:08.538245 CA PerBit enable=1, Macro0, CA PI delay=36
8355 13:22:08.538743
8356 13:22:08.542009 [CBTSetCACLKResult] CA Dly = 36
8357 13:22:08.545603 CS Dly: 11 (0~44)
8358 13:22:08.548775 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8359 13:22:08.552678 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8360 13:22:08.553227
8361 13:22:08.555565 ----->DramcWriteLeveling(PI) begin...
8362 13:22:08.556189 ==
8363 13:22:08.559217 Dram Type= 6, Freq= 0, CH_1, rank 0
8364 13:22:08.565120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8365 13:22:08.565670 ==
8366 13:22:08.568090 Write leveling (Byte 0): 24 => 24
8367 13:22:08.571599 Write leveling (Byte 1): 26 => 26
8368 13:22:08.572162 DramcWriteLeveling(PI) end<-----
8369 13:22:08.574840
8370 13:22:08.575381 ==
8371 13:22:08.578399 Dram Type= 6, Freq= 0, CH_1, rank 0
8372 13:22:08.581618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8373 13:22:08.582165 ==
8374 13:22:08.585189 [Gating] SW mode calibration
8375 13:22:08.591267 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8376 13:22:08.597459 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8377 13:22:08.601221 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 13:22:08.604306 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 13:22:08.611199 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (1 0)
8380 13:22:08.614369 1 4 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
8381 13:22:08.617649 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 13:22:08.624561 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 13:22:08.627811 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 13:22:08.630749 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 13:22:08.637881 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 13:22:08.640860 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 13:22:08.643813 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8388 13:22:08.650463 1 5 12 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (1 0)
8389 13:22:08.654038 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 13:22:08.656878 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 13:22:08.663522 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 13:22:08.666904 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 13:22:08.670390 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 13:22:08.674240 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 13:22:08.680147 1 6 8 | B1->B0 | 2727 2323 | 0 1 | (0 0) (0 0)
8396 13:22:08.685034 1 6 12 | B1->B0 | 3d3d 4444 | 0 0 | (0 0) (0 0)
8397 13:22:08.686927 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 13:22:08.693398 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 13:22:08.696841 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 13:22:08.703257 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 13:22:08.706693 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 13:22:08.709918 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 13:22:08.713611 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8404 13:22:08.720420 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8405 13:22:08.723106 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8406 13:22:08.726282 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 13:22:08.733046 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 13:22:08.736606 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 13:22:08.740029 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 13:22:08.746125 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 13:22:08.749857 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 13:22:08.752803 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 13:22:08.759611 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 13:22:08.762735 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 13:22:08.766106 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 13:22:08.772607 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 13:22:08.775782 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 13:22:08.782115 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 13:22:08.786002 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8420 13:22:08.789233 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8421 13:22:08.795540 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8422 13:22:08.796095 Total UI for P1: 0, mck2ui 16
8423 13:22:08.798927 best dqsien dly found for B0: ( 1, 9, 10)
8424 13:22:08.802405 Total UI for P1: 0, mck2ui 16
8425 13:22:08.805639 best dqsien dly found for B1: ( 1, 9, 10)
8426 13:22:08.812079 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8427 13:22:08.815892 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8428 13:22:08.816450
8429 13:22:08.818556 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8430 13:22:08.823223 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8431 13:22:08.825022 [Gating] SW calibration Done
8432 13:22:08.825505 ==
8433 13:22:08.828773 Dram Type= 6, Freq= 0, CH_1, rank 0
8434 13:22:08.831507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8435 13:22:08.831973 ==
8436 13:22:08.835867 RX Vref Scan: 0
8437 13:22:08.836421
8438 13:22:08.836783 RX Vref 0 -> 0, step: 1
8439 13:22:08.837122
8440 13:22:08.838183 RX Delay 0 -> 252, step: 8
8441 13:22:08.842007 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8442 13:22:08.848651 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8443 13:22:08.851338 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8444 13:22:08.854815 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8445 13:22:08.857937 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8446 13:22:08.861579 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8447 13:22:08.868021 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8448 13:22:08.871342 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8449 13:22:08.874784 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8450 13:22:08.877808 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8451 13:22:08.880944 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8452 13:22:08.887575 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8453 13:22:08.891006 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8454 13:22:08.894428 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8455 13:22:08.897565 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8456 13:22:08.904405 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8457 13:22:08.904971 ==
8458 13:22:08.907466 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 13:22:08.911229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 13:22:08.911832 ==
8461 13:22:08.912209 DQS Delay:
8462 13:22:08.914179 DQS0 = 0, DQS1 = 0
8463 13:22:08.914659 DQM Delay:
8464 13:22:08.917366 DQM0 = 136, DQM1 = 129
8465 13:22:08.917927 DQ Delay:
8466 13:22:08.921044 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =131
8467 13:22:08.923819 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8468 13:22:08.927192 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8469 13:22:08.930214 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8470 13:22:08.933735
8471 13:22:08.934293
8472 13:22:08.934704 ==
8473 13:22:08.937247 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 13:22:08.940487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 13:22:08.941057 ==
8476 13:22:08.941427
8477 13:22:08.941760
8478 13:22:08.943341 TX Vref Scan disable
8479 13:22:08.943802 == TX Byte 0 ==
8480 13:22:08.950226 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8481 13:22:08.953460 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8482 13:22:08.953924 == TX Byte 1 ==
8483 13:22:08.960064 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8484 13:22:08.963593 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8485 13:22:08.964093 ==
8486 13:22:08.966810 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 13:22:08.970179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 13:22:08.970683 ==
8489 13:22:08.983771
8490 13:22:08.987023 TX Vref early break, caculate TX vref
8491 13:22:08.990154 TX Vref=16, minBit 0, minWin=22, winSum=377
8492 13:22:08.993050 TX Vref=18, minBit 0, minWin=22, winSum=384
8493 13:22:08.996457 TX Vref=20, minBit 5, minWin=23, winSum=397
8494 13:22:08.999876 TX Vref=22, minBit 5, minWin=23, winSum=401
8495 13:22:09.002915 TX Vref=24, minBit 5, minWin=24, winSum=415
8496 13:22:09.009948 TX Vref=26, minBit 0, minWin=24, winSum=422
8497 13:22:09.013111 TX Vref=28, minBit 0, minWin=25, winSum=422
8498 13:22:09.016422 TX Vref=30, minBit 1, minWin=24, winSum=414
8499 13:22:09.019177 TX Vref=32, minBit 5, minWin=23, winSum=403
8500 13:22:09.023291 TX Vref=34, minBit 0, minWin=24, winSum=398
8501 13:22:09.029682 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 28
8502 13:22:09.030238
8503 13:22:09.032711 Final TX Range 0 Vref 28
8504 13:22:09.033175
8505 13:22:09.033535 ==
8506 13:22:09.035947 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 13:22:09.039454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 13:22:09.040012 ==
8509 13:22:09.040383
8510 13:22:09.040723
8511 13:22:09.042519 TX Vref Scan disable
8512 13:22:09.049579 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8513 13:22:09.050138 == TX Byte 0 ==
8514 13:22:09.052745 u2DelayCellOfst[0]=18 cells (5 PI)
8515 13:22:09.055606 u2DelayCellOfst[1]=11 cells (3 PI)
8516 13:22:09.059167 u2DelayCellOfst[2]=0 cells (0 PI)
8517 13:22:09.062935 u2DelayCellOfst[3]=3 cells (1 PI)
8518 13:22:09.065652 u2DelayCellOfst[4]=11 cells (3 PI)
8519 13:22:09.069160 u2DelayCellOfst[5]=22 cells (6 PI)
8520 13:22:09.072553 u2DelayCellOfst[6]=18 cells (5 PI)
8521 13:22:09.075572 u2DelayCellOfst[7]=3 cells (1 PI)
8522 13:22:09.078681 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8523 13:22:09.081998 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8524 13:22:09.085538 == TX Byte 1 ==
8525 13:22:09.088746 u2DelayCellOfst[8]=0 cells (0 PI)
8526 13:22:09.092126 u2DelayCellOfst[9]=3 cells (1 PI)
8527 13:22:09.095301 u2DelayCellOfst[10]=11 cells (3 PI)
8528 13:22:09.096000 u2DelayCellOfst[11]=7 cells (2 PI)
8529 13:22:09.098507 u2DelayCellOfst[12]=14 cells (4 PI)
8530 13:22:09.101930 u2DelayCellOfst[13]=18 cells (5 PI)
8531 13:22:09.105252 u2DelayCellOfst[14]=18 cells (5 PI)
8532 13:22:09.108807 u2DelayCellOfst[15]=18 cells (5 PI)
8533 13:22:09.115231 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8534 13:22:09.119264 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8535 13:22:09.119784 DramC Write-DBI on
8536 13:22:09.122286 ==
8537 13:22:09.125446 Dram Type= 6, Freq= 0, CH_1, rank 0
8538 13:22:09.128556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8539 13:22:09.129070 ==
8540 13:22:09.129475
8541 13:22:09.129792
8542 13:22:09.132100 TX Vref Scan disable
8543 13:22:09.132610 == TX Byte 0 ==
8544 13:22:09.138153 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8545 13:22:09.138706 == TX Byte 1 ==
8546 13:22:09.141942 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8547 13:22:09.145048 DramC Write-DBI off
8548 13:22:09.145575
8549 13:22:09.145911 [DATLAT]
8550 13:22:09.148011 Freq=1600, CH1 RK0
8551 13:22:09.148526
8552 13:22:09.148861 DATLAT Default: 0xf
8553 13:22:09.151331 0, 0xFFFF, sum = 0
8554 13:22:09.151757 1, 0xFFFF, sum = 0
8555 13:22:09.154838 2, 0xFFFF, sum = 0
8556 13:22:09.155357 3, 0xFFFF, sum = 0
8557 13:22:09.158070 4, 0xFFFF, sum = 0
8558 13:22:09.158628 5, 0xFFFF, sum = 0
8559 13:22:09.161390 6, 0xFFFF, sum = 0
8560 13:22:09.164441 7, 0xFFFF, sum = 0
8561 13:22:09.164866 8, 0xFFFF, sum = 0
8562 13:22:09.168074 9, 0xFFFF, sum = 0
8563 13:22:09.168541 10, 0xFFFF, sum = 0
8564 13:22:09.171216 11, 0xFFFF, sum = 0
8565 13:22:09.171736 12, 0xFFFF, sum = 0
8566 13:22:09.174669 13, 0xFFFF, sum = 0
8567 13:22:09.175185 14, 0x0, sum = 1
8568 13:22:09.177807 15, 0x0, sum = 2
8569 13:22:09.178325 16, 0x0, sum = 3
8570 13:22:09.180915 17, 0x0, sum = 4
8571 13:22:09.181452 best_step = 15
8572 13:22:09.181794
8573 13:22:09.182274 ==
8574 13:22:09.184283 Dram Type= 6, Freq= 0, CH_1, rank 0
8575 13:22:09.187299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8576 13:22:09.190835 ==
8577 13:22:09.191345 RX Vref Scan: 1
8578 13:22:09.191682
8579 13:22:09.194647 Set Vref Range= 24 -> 127
8580 13:22:09.195063
8581 13:22:09.197806 RX Vref 24 -> 127, step: 1
8582 13:22:09.198332
8583 13:22:09.198710 RX Delay 11 -> 252, step: 4
8584 13:22:09.199030
8585 13:22:09.200853 Set Vref, RX VrefLevel [Byte0]: 24
8586 13:22:09.203631 [Byte1]: 24
8587 13:22:09.207794
8588 13:22:09.208300 Set Vref, RX VrefLevel [Byte0]: 25
8589 13:22:09.211316 [Byte1]: 25
8590 13:22:09.215446
8591 13:22:09.215935 Set Vref, RX VrefLevel [Byte0]: 26
8592 13:22:09.218540 [Byte1]: 26
8593 13:22:09.223153
8594 13:22:09.223664 Set Vref, RX VrefLevel [Byte0]: 27
8595 13:22:09.226479 [Byte1]: 27
8596 13:22:09.230682
8597 13:22:09.231100 Set Vref, RX VrefLevel [Byte0]: 28
8598 13:22:09.233913 [Byte1]: 28
8599 13:22:09.238923
8600 13:22:09.239337 Set Vref, RX VrefLevel [Byte0]: 29
8601 13:22:09.241609 [Byte1]: 29
8602 13:22:09.245977
8603 13:22:09.246482 Set Vref, RX VrefLevel [Byte0]: 30
8604 13:22:09.249339 [Byte1]: 30
8605 13:22:09.253574
8606 13:22:09.254081 Set Vref, RX VrefLevel [Byte0]: 31
8607 13:22:09.256715 [Byte1]: 31
8608 13:22:09.261498
8609 13:22:09.262024 Set Vref, RX VrefLevel [Byte0]: 32
8610 13:22:09.264347 [Byte1]: 32
8611 13:22:09.269196
8612 13:22:09.269703 Set Vref, RX VrefLevel [Byte0]: 33
8613 13:22:09.272296 [Byte1]: 33
8614 13:22:09.276527
8615 13:22:09.277033 Set Vref, RX VrefLevel [Byte0]: 34
8616 13:22:09.280266 [Byte1]: 34
8617 13:22:09.285216
8618 13:22:09.285729 Set Vref, RX VrefLevel [Byte0]: 35
8619 13:22:09.287381 [Byte1]: 35
8620 13:22:09.292249
8621 13:22:09.292751 Set Vref, RX VrefLevel [Byte0]: 36
8622 13:22:09.294675 [Byte1]: 36
8623 13:22:09.299429
8624 13:22:09.302391 Set Vref, RX VrefLevel [Byte0]: 37
8625 13:22:09.305782 [Byte1]: 37
8626 13:22:09.306288
8627 13:22:09.309325 Set Vref, RX VrefLevel [Byte0]: 38
8628 13:22:09.312908 [Byte1]: 38
8629 13:22:09.313418
8630 13:22:09.315533 Set Vref, RX VrefLevel [Byte0]: 39
8631 13:22:09.318907 [Byte1]: 39
8632 13:22:09.322290
8633 13:22:09.322840 Set Vref, RX VrefLevel [Byte0]: 40
8634 13:22:09.325434 [Byte1]: 40
8635 13:22:09.330033
8636 13:22:09.330728 Set Vref, RX VrefLevel [Byte0]: 41
8637 13:22:09.333293 [Byte1]: 41
8638 13:22:09.337190
8639 13:22:09.337610 Set Vref, RX VrefLevel [Byte0]: 42
8640 13:22:09.340869 [Byte1]: 42
8641 13:22:09.344762
8642 13:22:09.345273 Set Vref, RX VrefLevel [Byte0]: 43
8643 13:22:09.348636 [Byte1]: 43
8644 13:22:09.352755
8645 13:22:09.353268 Set Vref, RX VrefLevel [Byte0]: 44
8646 13:22:09.356426 [Byte1]: 44
8647 13:22:09.360337
8648 13:22:09.360855 Set Vref, RX VrefLevel [Byte0]: 45
8649 13:22:09.363349 [Byte1]: 45
8650 13:22:09.367508
8651 13:22:09.368014 Set Vref, RX VrefLevel [Byte0]: 46
8652 13:22:09.370786 [Byte1]: 46
8653 13:22:09.375273
8654 13:22:09.375801 Set Vref, RX VrefLevel [Byte0]: 47
8655 13:22:09.378707 [Byte1]: 47
8656 13:22:09.383166
8657 13:22:09.383682 Set Vref, RX VrefLevel [Byte0]: 48
8658 13:22:09.386903 [Byte1]: 48
8659 13:22:09.390681
8660 13:22:09.391070 Set Vref, RX VrefLevel [Byte0]: 49
8661 13:22:09.393688 [Byte1]: 49
8662 13:22:09.398741
8663 13:22:09.399256 Set Vref, RX VrefLevel [Byte0]: 50
8664 13:22:09.401736 [Byte1]: 50
8665 13:22:09.405879
8666 13:22:09.406394 Set Vref, RX VrefLevel [Byte0]: 51
8667 13:22:09.409232 [Byte1]: 51
8668 13:22:09.413566
8669 13:22:09.414076 Set Vref, RX VrefLevel [Byte0]: 52
8670 13:22:09.417554 [Byte1]: 52
8671 13:22:09.421253
8672 13:22:09.421764 Set Vref, RX VrefLevel [Byte0]: 53
8673 13:22:09.424648 [Byte1]: 53
8674 13:22:09.429363
8675 13:22:09.429906 Set Vref, RX VrefLevel [Byte0]: 54
8676 13:22:09.435265 [Byte1]: 54
8677 13:22:09.435781
8678 13:22:09.438330 Set Vref, RX VrefLevel [Byte0]: 55
8679 13:22:09.441599 [Byte1]: 55
8680 13:22:09.442124
8681 13:22:09.445056 Set Vref, RX VrefLevel [Byte0]: 56
8682 13:22:09.448973 [Byte1]: 56
8683 13:22:09.451315
8684 13:22:09.451733 Set Vref, RX VrefLevel [Byte0]: 57
8685 13:22:09.454475 [Byte1]: 57
8686 13:22:09.459032
8687 13:22:09.459450 Set Vref, RX VrefLevel [Byte0]: 58
8688 13:22:09.462291 [Byte1]: 58
8689 13:22:09.466453
8690 13:22:09.466913 Set Vref, RX VrefLevel [Byte0]: 59
8691 13:22:09.470421 [Byte1]: 59
8692 13:22:09.474731
8693 13:22:09.475236 Set Vref, RX VrefLevel [Byte0]: 60
8694 13:22:09.477321 [Byte1]: 60
8695 13:22:09.481909
8696 13:22:09.482440 Set Vref, RX VrefLevel [Byte0]: 61
8697 13:22:09.485148 [Byte1]: 61
8698 13:22:09.489607
8699 13:22:09.490024 Set Vref, RX VrefLevel [Byte0]: 62
8700 13:22:09.493420 [Byte1]: 62
8701 13:22:09.497165
8702 13:22:09.497586 Set Vref, RX VrefLevel [Byte0]: 63
8703 13:22:09.500588 [Byte1]: 63
8704 13:22:09.505157
8705 13:22:09.505670 Set Vref, RX VrefLevel [Byte0]: 64
8706 13:22:09.508182 [Byte1]: 64
8707 13:22:09.512310
8708 13:22:09.512820 Set Vref, RX VrefLevel [Byte0]: 65
8709 13:22:09.515555 [Byte1]: 65
8710 13:22:09.520474
8711 13:22:09.520988 Set Vref, RX VrefLevel [Byte0]: 66
8712 13:22:09.523502 [Byte1]: 66
8713 13:22:09.527777
8714 13:22:09.528200 Set Vref, RX VrefLevel [Byte0]: 67
8715 13:22:09.530700 [Byte1]: 67
8716 13:22:09.535401
8717 13:22:09.535818 Set Vref, RX VrefLevel [Byte0]: 68
8718 13:22:09.538589 [Byte1]: 68
8719 13:22:09.542642
8720 13:22:09.543064 Set Vref, RX VrefLevel [Byte0]: 69
8721 13:22:09.546188 [Byte1]: 69
8722 13:22:09.550489
8723 13:22:09.551031 Set Vref, RX VrefLevel [Byte0]: 70
8724 13:22:09.554214 [Byte1]: 70
8725 13:22:09.558453
8726 13:22:09.558918 Set Vref, RX VrefLevel [Byte0]: 71
8727 13:22:09.562313 [Byte1]: 71
8728 13:22:09.565673
8729 13:22:09.566089 Set Vref, RX VrefLevel [Byte0]: 72
8730 13:22:09.569318 [Byte1]: 72
8731 13:22:09.573271
8732 13:22:09.573792 Set Vref, RX VrefLevel [Byte0]: 73
8733 13:22:09.576266 [Byte1]: 73
8734 13:22:09.580946
8735 13:22:09.581364 Set Vref, RX VrefLevel [Byte0]: 74
8736 13:22:09.584174 [Byte1]: 74
8737 13:22:09.588899
8738 13:22:09.589425 Set Vref, RX VrefLevel [Byte0]: 75
8739 13:22:09.592315 [Byte1]: 75
8740 13:22:09.596298
8741 13:22:09.596814 Set Vref, RX VrefLevel [Byte0]: 76
8742 13:22:09.599168 [Byte1]: 76
8743 13:22:09.603674
8744 13:22:09.604195 Final RX Vref Byte 0 = 53 to rank0
8745 13:22:09.607500 Final RX Vref Byte 1 = 58 to rank0
8746 13:22:09.610457 Final RX Vref Byte 0 = 53 to rank1
8747 13:22:09.613660 Final RX Vref Byte 1 = 58 to rank1==
8748 13:22:09.617746 Dram Type= 6, Freq= 0, CH_1, rank 0
8749 13:22:09.623689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8750 13:22:09.624279 ==
8751 13:22:09.624654 DQS Delay:
8752 13:22:09.627496 DQS0 = 0, DQS1 = 0
8753 13:22:09.627999 DQM Delay:
8754 13:22:09.628617 DQM0 = 133, DQM1 = 128
8755 13:22:09.630691 DQ Delay:
8756 13:22:09.633127 DQ0 =140, DQ1 =126, DQ2 =122, DQ3 =130
8757 13:22:09.636667 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =128
8758 13:22:09.640460 DQ8 =116, DQ9 =116, DQ10 =130, DQ11 =116
8759 13:22:09.643318 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8760 13:22:09.643783
8761 13:22:09.644151
8762 13:22:09.644487
8763 13:22:09.646551 [DramC_TX_OE_Calibration] TA2
8764 13:22:09.649858 Original DQ_B0 (3 6) =30, OEN = 27
8765 13:22:09.653428 Original DQ_B1 (3 6) =30, OEN = 27
8766 13:22:09.656754 24, 0x0, End_B0=24 End_B1=24
8767 13:22:09.660582 25, 0x0, End_B0=25 End_B1=25
8768 13:22:09.661154 26, 0x0, End_B0=26 End_B1=26
8769 13:22:09.662641 27, 0x0, End_B0=27 End_B1=27
8770 13:22:09.666755 28, 0x0, End_B0=28 End_B1=28
8771 13:22:09.669922 29, 0x0, End_B0=29 End_B1=29
8772 13:22:09.673025 30, 0x0, End_B0=30 End_B1=30
8773 13:22:09.673598 31, 0x4141, End_B0=30 End_B1=30
8774 13:22:09.675707 Byte0 end_step=30 best_step=27
8775 13:22:09.679630 Byte1 end_step=30 best_step=27
8776 13:22:09.682718 Byte0 TX OE(2T, 0.5T) = (3, 3)
8777 13:22:09.685830 Byte1 TX OE(2T, 0.5T) = (3, 3)
8778 13:22:09.686344
8779 13:22:09.686766
8780 13:22:09.692728 [DQSOSCAuto] RK0, (LSB)MR18= 0x170d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8781 13:22:09.695774 CH1 RK0: MR19=303, MR18=170D
8782 13:22:09.702403 CH1_RK0: MR19=0x303, MR18=0x170D, DQSOSC=398, MR23=63, INC=23, DEC=15
8783 13:22:09.703027
8784 13:22:09.705868 ----->DramcWriteLeveling(PI) begin...
8785 13:22:09.706441 ==
8786 13:22:09.709095 Dram Type= 6, Freq= 0, CH_1, rank 1
8787 13:22:09.712587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8788 13:22:09.713146 ==
8789 13:22:09.716420 Write leveling (Byte 0): 24 => 24
8790 13:22:09.719143 Write leveling (Byte 1): 25 => 25
8791 13:22:09.722691 DramcWriteLeveling(PI) end<-----
8792 13:22:09.723249
8793 13:22:09.723619 ==
8794 13:22:09.725897 Dram Type= 6, Freq= 0, CH_1, rank 1
8795 13:22:09.732648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8796 13:22:09.733195 ==
8797 13:22:09.733564 [Gating] SW mode calibration
8798 13:22:09.742337 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8799 13:22:09.745675 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8800 13:22:09.748772 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 13:22:09.755631 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 13:22:09.758431 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8803 13:22:09.765742 1 4 12 | B1->B0 | 3434 2424 | 0 0 | (0 0) (0 0)
8804 13:22:09.767985 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 13:22:09.771932 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 13:22:09.777966 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 13:22:09.781216 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8808 13:22:09.784827 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8809 13:22:09.791332 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8810 13:22:09.794754 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8811 13:22:09.797684 1 5 12 | B1->B0 | 2323 3434 | 0 0 | (1 0) (0 1)
8812 13:22:09.804167 1 5 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8813 13:22:09.807716 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 13:22:09.810745 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 13:22:09.817740 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 13:22:09.820721 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 13:22:09.824138 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 13:22:09.831134 1 6 8 | B1->B0 | 2e2e 2323 | 1 0 | (0 0) (0 0)
8819 13:22:09.833902 1 6 12 | B1->B0 | 4545 2626 | 0 0 | (0 0) (0 0)
8820 13:22:09.838226 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 13:22:09.844097 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 13:22:09.847787 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 13:22:09.850500 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 13:22:09.857007 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 13:22:09.860559 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 13:22:09.863723 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8827 13:22:09.870161 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8828 13:22:09.873983 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8829 13:22:09.877535 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 13:22:09.884143 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 13:22:09.887028 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 13:22:09.890341 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 13:22:09.897284 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 13:22:09.901062 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 13:22:09.903298 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 13:22:09.909841 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 13:22:09.913551 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 13:22:09.916866 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 13:22:09.923630 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 13:22:09.926415 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 13:22:09.929884 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8842 13:22:09.936918 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8843 13:22:09.939349 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8844 13:22:09.942999 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 13:22:09.946673 Total UI for P1: 0, mck2ui 16
8846 13:22:09.949398 best dqsien dly found for B0: ( 1, 9, 10)
8847 13:22:09.953938 Total UI for P1: 0, mck2ui 16
8848 13:22:09.955764 best dqsien dly found for B1: ( 1, 9, 8)
8849 13:22:09.959879 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8850 13:22:09.963208 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8851 13:22:09.963777
8852 13:22:09.969396 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8853 13:22:09.972946 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8854 13:22:09.973505 [Gating] SW calibration Done
8855 13:22:09.975714 ==
8856 13:22:09.979085 Dram Type= 6, Freq= 0, CH_1, rank 1
8857 13:22:09.982791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8858 13:22:09.983349 ==
8859 13:22:09.983821 RX Vref Scan: 0
8860 13:22:09.984209
8861 13:22:09.985833 RX Vref 0 -> 0, step: 1
8862 13:22:09.986290
8863 13:22:09.989350 RX Delay 0 -> 252, step: 8
8864 13:22:09.992750 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8865 13:22:09.995985 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8866 13:22:09.999119 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8867 13:22:10.005744 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8868 13:22:10.009484 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8869 13:22:10.012205 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8870 13:22:10.015552 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8871 13:22:10.018484 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8872 13:22:10.025609 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8873 13:22:10.029353 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8874 13:22:10.031734 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8875 13:22:10.035059 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8876 13:22:10.041747 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8877 13:22:10.045384 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8878 13:22:10.048976 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8879 13:22:10.051852 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8880 13:22:10.052404 ==
8881 13:22:10.055200 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 13:22:10.061650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 13:22:10.062210 ==
8884 13:22:10.062582 DQS Delay:
8885 13:22:10.063016 DQS0 = 0, DQS1 = 0
8886 13:22:10.064962 DQM Delay:
8887 13:22:10.065416 DQM0 = 137, DQM1 = 129
8888 13:22:10.068125 DQ Delay:
8889 13:22:10.071970 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8890 13:22:10.075116 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8891 13:22:10.078327 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8892 13:22:10.081401 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8893 13:22:10.081958
8894 13:22:10.082327
8895 13:22:10.082730 ==
8896 13:22:10.084565 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 13:22:10.088015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 13:22:10.091696 ==
8899 13:22:10.092260
8900 13:22:10.092625
8901 13:22:10.092966 TX Vref Scan disable
8902 13:22:10.094669 == TX Byte 0 ==
8903 13:22:10.097808 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8904 13:22:10.101724 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8905 13:22:10.104649 == TX Byte 1 ==
8906 13:22:10.107731 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8907 13:22:10.111335 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8908 13:22:10.114703 ==
8909 13:22:10.117806 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 13:22:10.120847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 13:22:10.121315 ==
8912 13:22:10.133213
8913 13:22:10.136803 TX Vref early break, caculate TX vref
8914 13:22:10.139678 TX Vref=16, minBit 1, minWin=22, winSum=384
8915 13:22:10.142766 TX Vref=18, minBit 0, minWin=23, winSum=394
8916 13:22:10.146068 TX Vref=20, minBit 0, minWin=24, winSum=405
8917 13:22:10.149566 TX Vref=22, minBit 1, minWin=24, winSum=414
8918 13:22:10.152794 TX Vref=24, minBit 5, minWin=24, winSum=417
8919 13:22:10.160087 TX Vref=26, minBit 0, minWin=25, winSum=423
8920 13:22:10.163145 TX Vref=28, minBit 0, minWin=24, winSum=426
8921 13:22:10.165904 TX Vref=30, minBit 0, minWin=24, winSum=418
8922 13:22:10.169535 TX Vref=32, minBit 0, minWin=23, winSum=407
8923 13:22:10.172918 TX Vref=34, minBit 0, minWin=23, winSum=400
8924 13:22:10.179489 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 26
8925 13:22:10.180237
8926 13:22:10.182881 Final TX Range 0 Vref 26
8927 13:22:10.183438
8928 13:22:10.183809 ==
8929 13:22:10.186001 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 13:22:10.189473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 13:22:10.190047 ==
8932 13:22:10.190421
8933 13:22:10.190836
8934 13:22:10.192809 TX Vref Scan disable
8935 13:22:10.199128 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8936 13:22:10.199716 == TX Byte 0 ==
8937 13:22:10.202899 u2DelayCellOfst[0]=18 cells (5 PI)
8938 13:22:10.205734 u2DelayCellOfst[1]=11 cells (3 PI)
8939 13:22:10.209276 u2DelayCellOfst[2]=0 cells (0 PI)
8940 13:22:10.212711 u2DelayCellOfst[3]=3 cells (1 PI)
8941 13:22:10.216375 u2DelayCellOfst[4]=7 cells (2 PI)
8942 13:22:10.219019 u2DelayCellOfst[5]=22 cells (6 PI)
8943 13:22:10.222148 u2DelayCellOfst[6]=18 cells (5 PI)
8944 13:22:10.225821 u2DelayCellOfst[7]=3 cells (1 PI)
8945 13:22:10.228837 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8946 13:22:10.232970 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8947 13:22:10.235567 == TX Byte 1 ==
8948 13:22:10.238728 u2DelayCellOfst[8]=0 cells (0 PI)
8949 13:22:10.239192 u2DelayCellOfst[9]=7 cells (2 PI)
8950 13:22:10.241999 u2DelayCellOfst[10]=14 cells (4 PI)
8951 13:22:10.245552 u2DelayCellOfst[11]=3 cells (1 PI)
8952 13:22:10.248668 u2DelayCellOfst[12]=18 cells (5 PI)
8953 13:22:10.251865 u2DelayCellOfst[13]=18 cells (5 PI)
8954 13:22:10.255338 u2DelayCellOfst[14]=18 cells (5 PI)
8955 13:22:10.258827 u2DelayCellOfst[15]=18 cells (5 PI)
8956 13:22:10.262284 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8957 13:22:10.268649 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8958 13:22:10.269111 DramC Write-DBI on
8959 13:22:10.269480 ==
8960 13:22:10.271948 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 13:22:10.278727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 13:22:10.279291 ==
8963 13:22:10.279662
8964 13:22:10.280005
8965 13:22:10.280330 TX Vref Scan disable
8966 13:22:10.282291 == TX Byte 0 ==
8967 13:22:10.285984 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8968 13:22:10.290159 == TX Byte 1 ==
8969 13:22:10.292798 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8970 13:22:10.295567 DramC Write-DBI off
8971 13:22:10.296117
8972 13:22:10.296488 [DATLAT]
8973 13:22:10.296853 Freq=1600, CH1 RK1
8974 13:22:10.297249
8975 13:22:10.299116 DATLAT Default: 0xf
8976 13:22:10.302119 0, 0xFFFF, sum = 0
8977 13:22:10.302589 1, 0xFFFF, sum = 0
8978 13:22:10.305556 2, 0xFFFF, sum = 0
8979 13:22:10.306114 3, 0xFFFF, sum = 0
8980 13:22:10.308811 4, 0xFFFF, sum = 0
8981 13:22:10.309381 5, 0xFFFF, sum = 0
8982 13:22:10.312317 6, 0xFFFF, sum = 0
8983 13:22:10.312892 7, 0xFFFF, sum = 0
8984 13:22:10.315517 8, 0xFFFF, sum = 0
8985 13:22:10.316080 9, 0xFFFF, sum = 0
8986 13:22:10.319294 10, 0xFFFF, sum = 0
8987 13:22:10.319910 11, 0xFFFF, sum = 0
8988 13:22:10.321837 12, 0xFFFF, sum = 0
8989 13:22:10.322305 13, 0xFFFF, sum = 0
8990 13:22:10.325745 14, 0x0, sum = 1
8991 13:22:10.326320 15, 0x0, sum = 2
8992 13:22:10.328732 16, 0x0, sum = 3
8993 13:22:10.329198 17, 0x0, sum = 4
8994 13:22:10.332328 best_step = 15
8995 13:22:10.332933
8996 13:22:10.333307 ==
8997 13:22:10.335131 Dram Type= 6, Freq= 0, CH_1, rank 1
8998 13:22:10.338468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8999 13:22:10.339080 ==
9000 13:22:10.341417 RX Vref Scan: 0
9001 13:22:10.341877
9002 13:22:10.342251 RX Vref 0 -> 0, step: 1
9003 13:22:10.342638
9004 13:22:10.345186 RX Delay 11 -> 252, step: 4
9005 13:22:10.351768 iDelay=203, Bit 0, Center 140 (87 ~ 194) 108
9006 13:22:10.354802 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9007 13:22:10.358080 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9008 13:22:10.361884 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9009 13:22:10.364608 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9010 13:22:10.371112 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
9011 13:22:10.374780 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9012 13:22:10.378540 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9013 13:22:10.381368 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9014 13:22:10.385084 iDelay=203, Bit 9, Center 114 (59 ~ 170) 112
9015 13:22:10.391312 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9016 13:22:10.394732 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9017 13:22:10.397588 iDelay=203, Bit 12, Center 138 (83 ~ 194) 112
9018 13:22:10.401194 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9019 13:22:10.408436 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9020 13:22:10.412066 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9021 13:22:10.412591 ==
9022 13:22:10.414308 Dram Type= 6, Freq= 0, CH_1, rank 1
9023 13:22:10.417314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9024 13:22:10.417730 ==
9025 13:22:10.420881 DQS Delay:
9026 13:22:10.421430 DQS0 = 0, DQS1 = 0
9027 13:22:10.421797 DQM Delay:
9028 13:22:10.424059 DQM0 = 134, DQM1 = 127
9029 13:22:10.424614 DQ Delay:
9030 13:22:10.427187 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9031 13:22:10.431273 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9032 13:22:10.433921 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =118
9033 13:22:10.440910 DQ12 =138, DQ13 =136, DQ14 =134, DQ15 =138
9034 13:22:10.441451
9035 13:22:10.441812
9036 13:22:10.442147
9037 13:22:10.443718 [DramC_TX_OE_Calibration] TA2
9038 13:22:10.447330 Original DQ_B0 (3 6) =30, OEN = 27
9039 13:22:10.447889 Original DQ_B1 (3 6) =30, OEN = 27
9040 13:22:10.450702 24, 0x0, End_B0=24 End_B1=24
9041 13:22:10.453867 25, 0x0, End_B0=25 End_B1=25
9042 13:22:10.457348 26, 0x0, End_B0=26 End_B1=26
9043 13:22:10.460474 27, 0x0, End_B0=27 End_B1=27
9044 13:22:10.461034 28, 0x0, End_B0=28 End_B1=28
9045 13:22:10.463524 29, 0x0, End_B0=29 End_B1=29
9046 13:22:10.467159 30, 0x0, End_B0=30 End_B1=30
9047 13:22:10.470263 31, 0x4141, End_B0=30 End_B1=30
9048 13:22:10.473552 Byte0 end_step=30 best_step=27
9049 13:22:10.476945 Byte1 end_step=30 best_step=27
9050 13:22:10.477683 Byte0 TX OE(2T, 0.5T) = (3, 3)
9051 13:22:10.480371 Byte1 TX OE(2T, 0.5T) = (3, 3)
9052 13:22:10.480823
9053 13:22:10.481176
9054 13:22:10.489919 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
9055 13:22:10.493426 CH1 RK1: MR19=303, MR18=F0B
9056 13:22:10.497049 CH1_RK1: MR19=0x303, MR18=0xF0B, DQSOSC=402, MR23=63, INC=22, DEC=15
9057 13:22:10.500175 [RxdqsGatingPostProcess] freq 1600
9058 13:22:10.506749 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9059 13:22:10.509971 best DQS0 dly(2T, 0.5T) = (1, 1)
9060 13:22:10.512882 best DQS1 dly(2T, 0.5T) = (1, 1)
9061 13:22:10.516270 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9062 13:22:10.519834 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9063 13:22:10.522972 best DQS0 dly(2T, 0.5T) = (1, 1)
9064 13:22:10.526728 best DQS1 dly(2T, 0.5T) = (1, 1)
9065 13:22:10.527303 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9066 13:22:10.530013 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9067 13:22:10.532641 Pre-setting of DQS Precalculation
9068 13:22:10.539832 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9069 13:22:10.546229 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9070 13:22:10.552868 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9071 13:22:10.553431
9072 13:22:10.553798
9073 13:22:10.556270 [Calibration Summary] 3200 Mbps
9074 13:22:10.559176 CH 0, Rank 0
9075 13:22:10.559637 SW Impedance : PASS
9076 13:22:10.563330 DUTY Scan : NO K
9077 13:22:10.565853 ZQ Calibration : PASS
9078 13:22:10.566312 Jitter Meter : NO K
9079 13:22:10.569736 CBT Training : PASS
9080 13:22:10.570288 Write leveling : PASS
9081 13:22:10.572770 RX DQS gating : PASS
9082 13:22:10.575831 RX DQ/DQS(RDDQC) : PASS
9083 13:22:10.576400 TX DQ/DQS : PASS
9084 13:22:10.578825 RX DATLAT : PASS
9085 13:22:10.582349 RX DQ/DQS(Engine): PASS
9086 13:22:10.582988 TX OE : PASS
9087 13:22:10.585597 All Pass.
9088 13:22:10.586050
9089 13:22:10.586412 CH 0, Rank 1
9090 13:22:10.588861 SW Impedance : PASS
9091 13:22:10.589314 DUTY Scan : NO K
9092 13:22:10.592170 ZQ Calibration : PASS
9093 13:22:10.595986 Jitter Meter : NO K
9094 13:22:10.596539 CBT Training : PASS
9095 13:22:10.599224 Write leveling : PASS
9096 13:22:10.602110 RX DQS gating : PASS
9097 13:22:10.602716 RX DQ/DQS(RDDQC) : PASS
9098 13:22:10.605354 TX DQ/DQS : PASS
9099 13:22:10.608872 RX DATLAT : PASS
9100 13:22:10.609427 RX DQ/DQS(Engine): PASS
9101 13:22:10.612126 TX OE : PASS
9102 13:22:10.612694 All Pass.
9103 13:22:10.613056
9104 13:22:10.615053 CH 1, Rank 0
9105 13:22:10.615507 SW Impedance : PASS
9106 13:22:10.618588 DUTY Scan : NO K
9107 13:22:10.623142 ZQ Calibration : PASS
9108 13:22:10.623691 Jitter Meter : NO K
9109 13:22:10.625281 CBT Training : PASS
9110 13:22:10.628799 Write leveling : PASS
9111 13:22:10.629351 RX DQS gating : PASS
9112 13:22:10.632623 RX DQ/DQS(RDDQC) : PASS
9113 13:22:10.635846 TX DQ/DQS : PASS
9114 13:22:10.636304 RX DATLAT : PASS
9115 13:22:10.638359 RX DQ/DQS(Engine): PASS
9116 13:22:10.638957 TX OE : PASS
9117 13:22:10.641770 All Pass.
9118 13:22:10.642218
9119 13:22:10.642575 CH 1, Rank 1
9120 13:22:10.644923 SW Impedance : PASS
9121 13:22:10.645396 DUTY Scan : NO K
9122 13:22:10.648449 ZQ Calibration : PASS
9123 13:22:10.651971 Jitter Meter : NO K
9124 13:22:10.652524 CBT Training : PASS
9125 13:22:10.654675 Write leveling : PASS
9126 13:22:10.658263 RX DQS gating : PASS
9127 13:22:10.658892 RX DQ/DQS(RDDQC) : PASS
9128 13:22:10.661998 TX DQ/DQS : PASS
9129 13:22:10.665439 RX DATLAT : PASS
9130 13:22:10.666215 RX DQ/DQS(Engine): PASS
9131 13:22:10.667861 TX OE : PASS
9132 13:22:10.668313 All Pass.
9133 13:22:10.668674
9134 13:22:10.671567 DramC Write-DBI on
9135 13:22:10.675064 PER_BANK_REFRESH: Hybrid Mode
9136 13:22:10.675620 TX_TRACKING: ON
9137 13:22:10.684589 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9138 13:22:10.691288 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9139 13:22:10.698831 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9140 13:22:10.704652 [FAST_K] Save calibration result to emmc
9141 13:22:10.705206 sync common calibartion params.
9142 13:22:10.707305 sync cbt_mode0:1, 1:1
9143 13:22:10.711438 dram_init: ddr_geometry: 2
9144 13:22:10.714760 dram_init: ddr_geometry: 2
9145 13:22:10.715316 dram_init: ddr_geometry: 2
9146 13:22:10.717910 0:dram_rank_size:100000000
9147 13:22:10.721230 1:dram_rank_size:100000000
9148 13:22:10.724390 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9149 13:22:10.727962 DFS_SHUFFLE_HW_MODE: ON
9150 13:22:10.731077 dramc_set_vcore_voltage set vcore to 725000
9151 13:22:10.734427 Read voltage for 1600, 0
9152 13:22:10.735045 Vio18 = 0
9153 13:22:10.737060 Vcore = 725000
9154 13:22:10.737516 Vdram = 0
9155 13:22:10.737879 Vddq = 0
9156 13:22:10.738214 Vmddr = 0
9157 13:22:10.740545 switch to 3200 Mbps bootup
9158 13:22:10.743868 [DramcRunTimeConfig]
9159 13:22:10.744416 PHYPLL
9160 13:22:10.747793 DPM_CONTROL_AFTERK: ON
9161 13:22:10.748255 PER_BANK_REFRESH: ON
9162 13:22:10.750704 REFRESH_OVERHEAD_REDUCTION: ON
9163 13:22:10.754033 CMD_PICG_NEW_MODE: OFF
9164 13:22:10.754587 XRTWTW_NEW_MODE: ON
9165 13:22:10.757400 XRTRTR_NEW_MODE: ON
9166 13:22:10.758085 TX_TRACKING: ON
9167 13:22:10.760154 RDSEL_TRACKING: OFF
9168 13:22:10.763794 DQS Precalculation for DVFS: ON
9169 13:22:10.764250 RX_TRACKING: OFF
9170 13:22:10.766712 HW_GATING DBG: ON
9171 13:22:10.767165 ZQCS_ENABLE_LP4: ON
9172 13:22:10.770183 RX_PICG_NEW_MODE: ON
9173 13:22:10.770779 TX_PICG_NEW_MODE: ON
9174 13:22:10.773561 ENABLE_RX_DCM_DPHY: ON
9175 13:22:10.777083 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9176 13:22:10.780634 DUMMY_READ_FOR_TRACKING: OFF
9177 13:22:10.781088 !!! SPM_CONTROL_AFTERK: OFF
9178 13:22:10.783951 !!! SPM could not control APHY
9179 13:22:10.786626 IMPEDANCE_TRACKING: ON
9180 13:22:10.787083 TEMP_SENSOR: ON
9181 13:22:10.790314 HW_SAVE_FOR_SR: OFF
9182 13:22:10.793544 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9183 13:22:10.796881 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9184 13:22:10.797433 Read ODT Tracking: ON
9185 13:22:10.799937 Refresh Rate DeBounce: ON
9186 13:22:10.803287 DFS_NO_QUEUE_FLUSH: ON
9187 13:22:10.806886 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9188 13:22:10.809847 ENABLE_DFS_RUNTIME_MRW: OFF
9189 13:22:10.810399 DDR_RESERVE_NEW_MODE: ON
9190 13:22:10.813130 MR_CBT_SWITCH_FREQ: ON
9191 13:22:10.817021 =========================
9192 13:22:10.833681 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9193 13:22:10.836715 dram_init: ddr_geometry: 2
9194 13:22:10.855054 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9195 13:22:10.859024 dram_init: dram init end (result: 0)
9196 13:22:10.865470 DRAM-K: Full calibration passed in 24605 msecs
9197 13:22:10.868716 MRC: failed to locate region type 0.
9198 13:22:10.869170 DRAM rank0 size:0x100000000,
9199 13:22:10.871609 DRAM rank1 size=0x100000000
9200 13:22:10.881734 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9201 13:22:10.888134 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9202 13:22:10.894710 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9203 13:22:10.904739 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9204 13:22:10.905501 DRAM rank0 size:0x100000000,
9205 13:22:10.907997 DRAM rank1 size=0x100000000
9206 13:22:10.908447 CBMEM:
9207 13:22:10.911156 IMD: root @ 0xfffff000 254 entries.
9208 13:22:10.914305 IMD: root @ 0xffffec00 62 entries.
9209 13:22:10.918525 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9210 13:22:10.924426 WARNING: RO_VPD is uninitialized or empty.
9211 13:22:10.928296 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9212 13:22:10.935551 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9213 13:22:10.948475 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9214 13:22:10.959594 BS: romstage times (exec / console): total (unknown) / 24101 ms
9215 13:22:10.960294
9216 13:22:10.960670
9217 13:22:10.969472 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9218 13:22:10.972976 ARM64: Exception handlers installed.
9219 13:22:10.976114 ARM64: Testing exception
9220 13:22:10.979227 ARM64: Done test exception
9221 13:22:10.979687 Enumerating buses...
9222 13:22:10.982523 Show all devs... Before device enumeration.
9223 13:22:10.985806 Root Device: enabled 1
9224 13:22:10.988980 CPU_CLUSTER: 0: enabled 1
9225 13:22:10.989437 CPU: 00: enabled 1
9226 13:22:10.992498 Compare with tree...
9227 13:22:10.993048 Root Device: enabled 1
9228 13:22:10.995861 CPU_CLUSTER: 0: enabled 1
9229 13:22:10.998901 CPU: 00: enabled 1
9230 13:22:10.999357 Root Device scanning...
9231 13:22:11.002382 scan_static_bus for Root Device
9232 13:22:11.006278 CPU_CLUSTER: 0 enabled
9233 13:22:11.009037 scan_static_bus for Root Device done
9234 13:22:11.012146 scan_bus: bus Root Device finished in 8 msecs
9235 13:22:11.012608 done
9236 13:22:11.018843 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9237 13:22:11.022429 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9238 13:22:11.028939 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9239 13:22:11.032351 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9240 13:22:11.035610 Allocating resources...
9241 13:22:11.038925 Reading resources...
9242 13:22:11.042113 Root Device read_resources bus 0 link: 0
9243 13:22:11.045226 DRAM rank0 size:0x100000000,
9244 13:22:11.045773 DRAM rank1 size=0x100000000
9245 13:22:11.049014 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9246 13:22:11.052372 CPU: 00 missing read_resources
9247 13:22:11.058479 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9248 13:22:11.061709 Root Device read_resources bus 0 link: 0 done
9249 13:22:11.064892 Done reading resources.
9250 13:22:11.068592 Show resources in subtree (Root Device)...After reading.
9251 13:22:11.071878 Root Device child on link 0 CPU_CLUSTER: 0
9252 13:22:11.075131 CPU_CLUSTER: 0 child on link 0 CPU: 00
9253 13:22:11.084471 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9254 13:22:11.085022 CPU: 00
9255 13:22:11.088681 Root Device assign_resources, bus 0 link: 0
9256 13:22:11.092326 CPU_CLUSTER: 0 missing set_resources
9257 13:22:11.098241 Root Device assign_resources, bus 0 link: 0 done
9258 13:22:11.098858 Done setting resources.
9259 13:22:11.104600 Show resources in subtree (Root Device)...After assigning values.
9260 13:22:11.108271 Root Device child on link 0 CPU_CLUSTER: 0
9261 13:22:11.111165 CPU_CLUSTER: 0 child on link 0 CPU: 00
9262 13:22:11.120917 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9263 13:22:11.121471 CPU: 00
9264 13:22:11.124280 Done allocating resources.
9265 13:22:11.130964 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9266 13:22:11.131513 Enabling resources...
9267 13:22:11.133981 done.
9268 13:22:11.137376 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9269 13:22:11.140928 Initializing devices...
9270 13:22:11.141491 Root Device init
9271 13:22:11.143889 init hardware done!
9272 13:22:11.144441 0x00000018: ctrlr->caps
9273 13:22:11.147317 52.000 MHz: ctrlr->f_max
9274 13:22:11.150700 0.400 MHz: ctrlr->f_min
9275 13:22:11.151269 0x40ff8080: ctrlr->voltages
9276 13:22:11.153814 sclk: 390625
9277 13:22:11.154366 Bus Width = 1
9278 13:22:11.157322 sclk: 390625
9279 13:22:11.157872 Bus Width = 1
9280 13:22:11.160382 Early init status = 3
9281 13:22:11.163926 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9282 13:22:11.166947 in-header: 03 fc 00 00 01 00 00 00
9283 13:22:11.170111 in-data: 00
9284 13:22:11.173470 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9285 13:22:11.178285 in-header: 03 fd 00 00 00 00 00 00
9286 13:22:11.181283 in-data:
9287 13:22:11.184752 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9288 13:22:11.188194 in-header: 03 fc 00 00 01 00 00 00
9289 13:22:11.191855 in-data: 00
9290 13:22:11.195257 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9291 13:22:11.199784 in-header: 03 fd 00 00 00 00 00 00
9292 13:22:11.202808 in-data:
9293 13:22:11.206514 [SSUSB] Setting up USB HOST controller...
9294 13:22:11.209830 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9295 13:22:11.213120 [SSUSB] phy power-on done.
9296 13:22:11.216179 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9297 13:22:11.223214 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9298 13:22:11.225974 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9299 13:22:11.232433 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9300 13:22:11.240004 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9301 13:22:11.245557 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9302 13:22:11.252026 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9303 13:22:11.259037 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9304 13:22:11.262547 SPM: binary array size = 0x9dc
9305 13:22:11.265632 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9306 13:22:11.272209 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9307 13:22:11.278668 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9308 13:22:11.285039 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9309 13:22:11.288782 configure_display: Starting display init
9310 13:22:11.322984 anx7625_power_on_init: Init interface.
9311 13:22:11.326295 anx7625_disable_pd_protocol: Disabled PD feature.
9312 13:22:11.329941 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9313 13:22:11.358211 anx7625_start_dp_work: Secure OCM version=00
9314 13:22:11.360959 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9315 13:22:11.375591 sp_tx_get_edid_block: EDID Block = 1
9316 13:22:11.478304 Extracted contents:
9317 13:22:11.481719 header: 00 ff ff ff ff ff ff 00
9318 13:22:11.484666 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9319 13:22:11.487856 version: 01 04
9320 13:22:11.491216 basic params: 95 1f 11 78 0a
9321 13:22:11.494483 chroma info: 76 90 94 55 54 90 27 21 50 54
9322 13:22:11.497890 established: 00 00 00
9323 13:22:11.504452 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9324 13:22:11.507791 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9325 13:22:11.514491 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9326 13:22:11.521771 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9327 13:22:11.527752 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9328 13:22:11.530901 extensions: 00
9329 13:22:11.531453 checksum: fb
9330 13:22:11.531817
9331 13:22:11.534279 Manufacturer: IVO Model 57d Serial Number 0
9332 13:22:11.537337 Made week 0 of 2020
9333 13:22:11.540665 EDID version: 1.4
9334 13:22:11.541141 Digital display
9335 13:22:11.543844 6 bits per primary color channel
9336 13:22:11.544402 DisplayPort interface
9337 13:22:11.547968 Maximum image size: 31 cm x 17 cm
9338 13:22:11.550494 Gamma: 220%
9339 13:22:11.550988 Check DPMS levels
9340 13:22:11.557420 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9341 13:22:11.560690 First detailed timing is preferred timing
9342 13:22:11.563871 Established timings supported:
9343 13:22:11.564517 Standard timings supported:
9344 13:22:11.566799 Detailed timings
9345 13:22:11.570762 Hex of detail: 383680a07038204018303c0035ae10000019
9346 13:22:11.576778 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9347 13:22:11.580099 0780 0798 07c8 0820 hborder 0
9348 13:22:11.583611 0438 043b 0447 0458 vborder 0
9349 13:22:11.586498 -hsync -vsync
9350 13:22:11.587007 Did detailed timing
9351 13:22:11.593441 Hex of detail: 000000000000000000000000000000000000
9352 13:22:11.597458 Manufacturer-specified data, tag 0
9353 13:22:11.600303 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9354 13:22:11.603400 ASCII string: InfoVision
9355 13:22:11.606175 Hex of detail: 000000fe00523134304e574635205248200a
9356 13:22:11.609368 ASCII string: R140NWF5 RH
9357 13:22:11.609837 Checksum
9358 13:22:11.612941 Checksum: 0xfb (valid)
9359 13:22:11.616565 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9360 13:22:11.619756 DSI data_rate: 832800000 bps
9361 13:22:11.626433 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9362 13:22:11.629754 anx7625_parse_edid: pixelclock(138800).
9363 13:22:11.633114 hactive(1920), hsync(48), hfp(24), hbp(88)
9364 13:22:11.636221 vactive(1080), vsync(12), vfp(3), vbp(17)
9365 13:22:11.639560 anx7625_dsi_config: config dsi.
9366 13:22:11.645944 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9367 13:22:11.660378 anx7625_dsi_config: success to config DSI
9368 13:22:11.663667 anx7625_dp_start: MIPI phy setup OK.
9369 13:22:11.667040 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9370 13:22:11.670383 mtk_ddp_mode_set invalid vrefresh 60
9371 13:22:11.673144 main_disp_path_setup
9372 13:22:11.673602 ovl_layer_smi_id_en
9373 13:22:11.676776 ovl_layer_smi_id_en
9374 13:22:11.677339 ccorr_config
9375 13:22:11.677710 aal_config
9376 13:22:11.680098 gamma_config
9377 13:22:11.680660 postmask_config
9378 13:22:11.683252 dither_config
9379 13:22:11.687074 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9380 13:22:11.693597 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9381 13:22:11.696687 Root Device init finished in 551 msecs
9382 13:22:11.699698 CPU_CLUSTER: 0 init
9383 13:22:11.706222 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9384 13:22:11.712859 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9385 13:22:11.713423 APU_MBOX 0x190000b0 = 0x10001
9386 13:22:11.716203 APU_MBOX 0x190001b0 = 0x10001
9387 13:22:11.719494 APU_MBOX 0x190005b0 = 0x10001
9388 13:22:11.722835 APU_MBOX 0x190006b0 = 0x10001
9389 13:22:11.730075 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9390 13:22:11.739129 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9391 13:22:11.751645 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9392 13:22:11.758173 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9393 13:22:11.769611 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9394 13:22:11.778701 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9395 13:22:11.782187 CPU_CLUSTER: 0 init finished in 81 msecs
9396 13:22:11.785766 Devices initialized
9397 13:22:11.789130 Show all devs... After init.
9398 13:22:11.789597 Root Device: enabled 1
9399 13:22:11.792053 CPU_CLUSTER: 0: enabled 1
9400 13:22:11.795701 CPU: 00: enabled 1
9401 13:22:11.798424 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9402 13:22:11.802793 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9403 13:22:11.805023 ELOG: NV offset 0x57f000 size 0x1000
9404 13:22:11.812270 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9405 13:22:11.818517 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9406 13:22:11.822048 ELOG: Event(17) added with size 13 at 2023-09-06 13:22:15 UTC
9407 13:22:11.828807 out: cmd=0x121: 03 db 21 01 00 00 00 00
9408 13:22:11.832306 in-header: 03 d9 00 00 2c 00 00 00
9409 13:22:11.841260 in-data: 86 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9410 13:22:11.848894 ELOG: Event(A1) added with size 10 at 2023-09-06 13:22:15 UTC
9411 13:22:11.855214 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9412 13:22:11.861244 ELOG: Event(A0) added with size 9 at 2023-09-06 13:22:15 UTC
9413 13:22:11.865468 elog_add_boot_reason: Logged dev mode boot
9414 13:22:11.871318 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9415 13:22:11.871877 Finalize devices...
9416 13:22:11.874306 Devices finalized
9417 13:22:11.877832 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9418 13:22:11.881629 Writing coreboot table at 0xffe64000
9419 13:22:11.884243 0. 000000000010a000-0000000000113fff: RAMSTAGE
9420 13:22:11.891324 1. 0000000040000000-00000000400fffff: RAM
9421 13:22:11.894773 2. 0000000040100000-000000004032afff: RAMSTAGE
9422 13:22:11.897701 3. 000000004032b000-00000000545fffff: RAM
9423 13:22:11.901302 4. 0000000054600000-000000005465ffff: BL31
9424 13:22:11.904662 5. 0000000054660000-00000000ffe63fff: RAM
9425 13:22:11.910823 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9426 13:22:11.914505 7. 0000000100000000-000000023fffffff: RAM
9427 13:22:11.917474 Passing 5 GPIOs to payload:
9428 13:22:11.920935 NAME | PORT | POLARITY | VALUE
9429 13:22:11.927949 EC in RW | 0x000000aa | low | undefined
9430 13:22:11.930779 EC interrupt | 0x00000005 | low | undefined
9431 13:22:11.934066 TPM interrupt | 0x000000ab | high | undefined
9432 13:22:11.940642 SD card detect | 0x00000011 | high | undefined
9433 13:22:11.943887 speaker enable | 0x00000093 | high | undefined
9434 13:22:11.946917 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9435 13:22:11.950536 in-header: 03 f9 00 00 02 00 00 00
9436 13:22:11.953940 in-data: 02 00
9437 13:22:11.957167 ADC[4]: Raw value=903400 ID=7
9438 13:22:11.957732 ADC[3]: Raw value=213282 ID=1
9439 13:22:11.961236 RAM Code: 0x71
9440 13:22:11.963773 ADC[6]: Raw value=75036 ID=0
9441 13:22:11.967491 ADC[5]: Raw value=213652 ID=1
9442 13:22:11.968058 SKU Code: 0x1
9443 13:22:11.973962 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a16d
9444 13:22:11.974554 coreboot table: 964 bytes.
9445 13:22:11.977102 IMD ROOT 0. 0xfffff000 0x00001000
9446 13:22:11.980617 IMD SMALL 1. 0xffffe000 0x00001000
9447 13:22:11.983589 RO MCACHE 2. 0xffffc000 0x00001104
9448 13:22:11.986831 CONSOLE 3. 0xfff7c000 0x00080000
9449 13:22:11.990171 FMAP 4. 0xfff7b000 0x00000452
9450 13:22:11.993711 TIME STAMP 5. 0xfff7a000 0x00000910
9451 13:22:11.996610 VBOOT WORK 6. 0xfff66000 0x00014000
9452 13:22:12.000048 RAMOOPS 7. 0xffe66000 0x00100000
9453 13:22:12.003339 COREBOOT 8. 0xffe64000 0x00002000
9454 13:22:12.006331 IMD small region:
9455 13:22:12.010122 IMD ROOT 0. 0xffffec00 0x00000400
9456 13:22:12.013205 VPD 1. 0xffffeb80 0x0000006c
9457 13:22:12.016656 MMC STATUS 2. 0xffffeb60 0x00000004
9458 13:22:12.023570 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9459 13:22:12.024143 Probing TPM: done!
9460 13:22:12.026735 Connected to device vid:did:rid of 1ae0:0028:00
9461 13:22:12.037918 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9462 13:22:12.041231 Initialized TPM device CR50 revision 0
9463 13:22:12.044639 Checking cr50 for pending updates
9464 13:22:12.048774 Reading cr50 TPM mode
9465 13:22:12.057700 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9466 13:22:12.063937 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9467 13:22:12.103997 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9468 13:22:12.107317 Checking segment from ROM address 0x40100000
9469 13:22:12.113799 Checking segment from ROM address 0x4010001c
9470 13:22:12.117056 Loading segment from ROM address 0x40100000
9471 13:22:12.117629 code (compression=0)
9472 13:22:12.127602 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9473 13:22:12.134473 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9474 13:22:12.135107 it's not compressed!
9475 13:22:12.140701 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9476 13:22:12.146752 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9477 13:22:12.164115 Loading segment from ROM address 0x4010001c
9478 13:22:12.164666 Entry Point 0x80000000
9479 13:22:12.168391 Loaded segments
9480 13:22:12.170810 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9481 13:22:12.177702 Jumping to boot code at 0x80000000(0xffe64000)
9482 13:22:12.183878 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9483 13:22:12.190744 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9484 13:22:12.198934 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9485 13:22:12.202041 Checking segment from ROM address 0x40100000
9486 13:22:12.205054 Checking segment from ROM address 0x4010001c
9487 13:22:12.211603 Loading segment from ROM address 0x40100000
9488 13:22:12.212073 code (compression=1)
9489 13:22:12.218520 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9490 13:22:12.228588 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9491 13:22:12.229166 using LZMA
9492 13:22:12.237212 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9493 13:22:12.243585 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9494 13:22:12.247615 Loading segment from ROM address 0x4010001c
9495 13:22:12.251050 Entry Point 0x54601000
9496 13:22:12.251611 Loaded segments
9497 13:22:12.253459 NOTICE: MT8192 bl31_setup
9498 13:22:12.261463 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9499 13:22:12.263969 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9500 13:22:12.267427 WARNING: region 0:
9501 13:22:12.271013 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9502 13:22:12.271582 WARNING: region 1:
9503 13:22:12.277849 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9504 13:22:12.281047 WARNING: region 2:
9505 13:22:12.284009 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9506 13:22:12.287442 WARNING: region 3:
9507 13:22:12.290575 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9508 13:22:12.293739 WARNING: region 4:
9509 13:22:12.300390 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9510 13:22:12.300956 WARNING: region 5:
9511 13:22:12.304178 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9512 13:22:12.307764 WARNING: region 6:
9513 13:22:12.310680 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9514 13:22:12.313943 WARNING: region 7:
9515 13:22:12.317704 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9516 13:22:12.325191 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9517 13:22:12.327771 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9518 13:22:12.330299 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9519 13:22:12.336886 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9520 13:22:12.341083 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9521 13:22:12.343616 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9522 13:22:12.350700 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9523 13:22:12.354057 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9524 13:22:12.360609 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9525 13:22:12.364275 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9526 13:22:12.366715 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9527 13:22:12.373967 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9528 13:22:12.376552 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9529 13:22:12.383301 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9530 13:22:12.386930 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9531 13:22:12.390006 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9532 13:22:12.396793 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9533 13:22:12.399936 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9534 13:22:12.403420 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9535 13:22:12.409988 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9536 13:22:12.413844 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9537 13:22:12.419946 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9538 13:22:12.422874 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9539 13:22:12.426793 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9540 13:22:12.433158 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9541 13:22:12.436372 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9542 13:22:12.443000 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9543 13:22:12.446017 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9544 13:22:12.450365 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9545 13:22:12.456443 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9546 13:22:12.459969 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9547 13:22:12.466665 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9548 13:22:12.469604 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9549 13:22:12.472891 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9550 13:22:12.476407 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9551 13:22:12.483043 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9552 13:22:12.486306 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9553 13:22:12.489674 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9554 13:22:12.493025 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9555 13:22:12.500325 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9556 13:22:12.502947 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9557 13:22:12.506584 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9558 13:22:12.509442 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9559 13:22:12.516903 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9560 13:22:12.519447 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9561 13:22:12.523107 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9562 13:22:12.526196 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9563 13:22:12.533274 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9564 13:22:12.536119 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9565 13:22:12.543103 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9566 13:22:12.546209 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9567 13:22:12.549359 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9568 13:22:12.555910 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9569 13:22:12.559256 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9570 13:22:12.565947 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9571 13:22:12.568933 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9572 13:22:12.575734 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9573 13:22:12.579494 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9574 13:22:12.582506 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9575 13:22:12.589570 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9576 13:22:12.592932 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9577 13:22:12.598706 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9578 13:22:12.602422 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9579 13:22:12.609132 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9580 13:22:12.612245 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9581 13:22:12.618941 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9582 13:22:12.622218 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9583 13:22:12.625681 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9584 13:22:12.632306 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9585 13:22:12.635567 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9586 13:22:12.642098 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9587 13:22:12.645746 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9588 13:22:12.651718 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9589 13:22:12.654962 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9590 13:22:12.661902 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9591 13:22:12.665147 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9592 13:22:12.668411 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9593 13:22:12.675106 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9594 13:22:12.678353 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9595 13:22:12.685413 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9596 13:22:12.687964 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9597 13:22:12.694784 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9598 13:22:12.698508 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9599 13:22:12.704549 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9600 13:22:12.707739 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9601 13:22:12.711532 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9602 13:22:12.719122 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9603 13:22:12.721437 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9604 13:22:12.728134 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9605 13:22:12.731145 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9606 13:22:12.737944 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9607 13:22:12.741447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9608 13:22:12.747976 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9609 13:22:12.751510 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9610 13:22:12.754697 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9611 13:22:12.760927 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9612 13:22:12.764695 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9613 13:22:12.767686 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9614 13:22:12.774146 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9615 13:22:12.777514 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9616 13:22:12.780664 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9617 13:22:12.787019 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9618 13:22:12.791037 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9619 13:22:12.797491 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9620 13:22:12.801016 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9621 13:22:12.803509 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9622 13:22:12.810655 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9623 13:22:12.813666 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9624 13:22:12.821213 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9625 13:22:12.823417 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9626 13:22:12.827312 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9627 13:22:12.833748 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9628 13:22:12.837336 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9629 13:22:12.843532 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9630 13:22:12.847035 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9631 13:22:12.850516 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9632 13:22:12.853685 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9633 13:22:12.860314 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9634 13:22:12.863435 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9635 13:22:12.867074 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9636 13:22:12.873487 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9637 13:22:12.876866 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9638 13:22:12.879696 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9639 13:22:12.883318 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9640 13:22:12.890496 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9641 13:22:12.892940 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9642 13:22:12.899958 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9643 13:22:12.904799 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9644 13:22:12.909815 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9645 13:22:12.913439 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9646 13:22:12.916333 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9647 13:22:12.923520 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9648 13:22:12.926196 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9649 13:22:12.929730 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9650 13:22:12.936800 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9651 13:22:12.940852 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9652 13:22:12.946670 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9653 13:22:12.949716 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9654 13:22:12.952802 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9655 13:22:12.959584 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9656 13:22:12.963196 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9657 13:22:12.969790 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9658 13:22:12.973931 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9659 13:22:12.976072 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9660 13:22:12.982754 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9661 13:22:12.986382 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9662 13:22:12.992411 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9663 13:22:12.996405 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9664 13:22:12.999391 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9665 13:22:13.006228 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9666 13:22:13.009454 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9667 13:22:13.012634 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9668 13:22:13.019473 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9669 13:22:13.022416 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9670 13:22:13.029600 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9671 13:22:13.032633 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9672 13:22:13.036226 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9673 13:22:13.042339 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9674 13:22:13.045856 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9675 13:22:13.052348 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9676 13:22:13.055793 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9677 13:22:13.058730 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9678 13:22:13.065202 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9679 13:22:13.068488 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9680 13:22:13.075316 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9681 13:22:13.079160 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9682 13:22:13.081953 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9683 13:22:13.088605 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9684 13:22:13.091874 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9685 13:22:13.098576 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9686 13:22:13.101756 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9687 13:22:13.105027 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9688 13:22:13.111301 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9689 13:22:13.114781 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9690 13:22:13.121692 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9691 13:22:13.125139 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9692 13:22:13.128485 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9693 13:22:13.134978 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9694 13:22:13.138105 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9695 13:22:13.144607 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9696 13:22:13.148850 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9697 13:22:13.151583 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9698 13:22:13.157945 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9699 13:22:13.161288 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9700 13:22:13.168000 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9701 13:22:13.171339 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9702 13:22:13.174742 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9703 13:22:13.181733 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9704 13:22:13.184553 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9705 13:22:13.191014 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9706 13:22:13.193860 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9707 13:22:13.201104 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9708 13:22:13.204144 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9709 13:22:13.207606 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9710 13:22:13.213921 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9711 13:22:13.217718 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9712 13:22:13.224097 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9713 13:22:13.226934 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9714 13:22:13.233617 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9715 13:22:13.237280 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9716 13:22:13.240403 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9717 13:22:13.247154 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9718 13:22:13.250328 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9719 13:22:13.257669 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9720 13:22:13.260896 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9721 13:22:13.263296 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9722 13:22:13.269992 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9723 13:22:13.273682 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9724 13:22:13.280384 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9725 13:22:13.284219 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9726 13:22:13.290082 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9727 13:22:13.293204 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9728 13:22:13.297255 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9729 13:22:13.303155 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9730 13:22:13.306908 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9731 13:22:13.313252 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9732 13:22:13.317276 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9733 13:22:13.322889 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9734 13:22:13.326268 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9735 13:22:13.329359 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9736 13:22:13.336157 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9737 13:22:13.339561 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9738 13:22:13.346711 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9739 13:22:13.349302 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9740 13:22:13.356156 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9741 13:22:13.359585 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9742 13:22:13.362752 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9743 13:22:13.369569 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9744 13:22:13.372658 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9745 13:22:13.375518 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9746 13:22:13.382964 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9747 13:22:13.385608 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9748 13:22:13.389341 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9749 13:22:13.392920 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9750 13:22:13.398872 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9751 13:22:13.402437 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9752 13:22:13.408758 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9753 13:22:13.411863 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9754 13:22:13.415302 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9755 13:22:13.422032 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9756 13:22:13.425021 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9757 13:22:13.428490 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9758 13:22:13.434947 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9759 13:22:13.438093 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9760 13:22:13.444588 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9761 13:22:13.447753 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9762 13:22:13.450965 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9763 13:22:13.457812 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9764 13:22:13.460974 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9765 13:22:13.464091 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9766 13:22:13.471677 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9767 13:22:13.474236 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9768 13:22:13.481205 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9769 13:22:13.484190 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9770 13:22:13.487729 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9771 13:22:13.494104 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9772 13:22:13.498246 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9773 13:22:13.501586 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9774 13:22:13.507994 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9775 13:22:13.511356 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9776 13:22:13.514767 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9777 13:22:13.521618 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9778 13:22:13.524978 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9779 13:22:13.531040 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9780 13:22:13.534311 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9781 13:22:13.537827 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9782 13:22:13.544372 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9783 13:22:13.547590 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9784 13:22:13.551496 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9785 13:22:13.557674 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9786 13:22:13.560620 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9787 13:22:13.564076 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9788 13:22:13.567713 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9789 13:22:13.570499 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9790 13:22:13.577220 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9791 13:22:13.580649 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9792 13:22:13.584808 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9793 13:22:13.587074 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9794 13:22:13.594007 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9795 13:22:13.597164 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9796 13:22:13.600293 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9797 13:22:13.607197 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9798 13:22:13.610569 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9799 13:22:13.613673 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9800 13:22:13.620552 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9801 13:22:13.623843 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9802 13:22:13.630636 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9803 13:22:13.633483 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9804 13:22:13.640266 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9805 13:22:13.643851 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9806 13:22:13.646655 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9807 13:22:13.653491 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9808 13:22:13.656709 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9809 13:22:13.663308 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9810 13:22:13.666396 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9811 13:22:13.673607 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9812 13:22:13.676166 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9813 13:22:13.679748 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9814 13:22:13.686455 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9815 13:22:13.689786 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9816 13:22:13.695748 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9817 13:22:13.698938 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9818 13:22:13.705948 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9819 13:22:13.709023 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9820 13:22:13.712746 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9821 13:22:13.719374 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9822 13:22:13.723577 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9823 13:22:13.728792 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9824 13:22:13.732294 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9825 13:22:13.735566 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9826 13:22:13.742032 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9827 13:22:13.745787 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9828 13:22:13.751831 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9829 13:22:13.755202 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9830 13:22:13.758405 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9831 13:22:13.765263 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9832 13:22:13.769176 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9833 13:22:13.775059 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9834 13:22:13.778656 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9835 13:22:13.784678 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9836 13:22:13.788420 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9837 13:22:13.791297 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9838 13:22:13.798293 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9839 13:22:13.801200 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9840 13:22:13.808025 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9841 13:22:13.811331 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9842 13:22:13.818011 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9843 13:22:13.821829 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9844 13:22:13.824187 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9845 13:22:13.831240 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9846 13:22:13.834904 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9847 13:22:13.841266 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9848 13:22:13.844723 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9849 13:22:13.847622 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9850 13:22:13.854896 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9851 13:22:13.857908 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9852 13:22:13.864202 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9853 13:22:13.867883 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9854 13:22:13.871024 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9855 13:22:13.877789 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9856 13:22:13.880810 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9857 13:22:13.887547 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9858 13:22:13.890585 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9859 13:22:13.897390 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9860 13:22:13.900807 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9861 13:22:13.903787 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9862 13:22:13.910692 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9863 13:22:13.913667 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9864 13:22:13.921439 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9865 13:22:13.923463 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9866 13:22:13.930019 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9867 13:22:13.933857 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9868 13:22:13.937158 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9869 13:22:13.943190 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9870 13:22:13.946869 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9871 13:22:13.953323 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9872 13:22:13.956547 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9873 13:22:13.963236 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9874 13:22:13.966125 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9875 13:22:13.973148 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9876 13:22:13.976282 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9877 13:22:13.979684 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9878 13:22:13.987060 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9879 13:22:13.989662 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9880 13:22:13.995831 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9881 13:22:13.999251 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9882 13:22:14.006099 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9883 13:22:14.009386 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9884 13:22:14.016095 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9885 13:22:14.018863 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9886 13:22:14.022125 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9887 13:22:14.028592 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9888 13:22:14.032113 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9889 13:22:14.039061 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9890 13:22:14.042311 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9891 13:22:14.048686 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9892 13:22:14.051867 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9893 13:22:14.055157 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9894 13:22:14.061927 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9895 13:22:14.065303 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9896 13:22:14.071510 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9897 13:22:14.075187 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9898 13:22:14.081892 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9899 13:22:14.084866 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9900 13:22:14.091738 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9901 13:22:14.094824 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9902 13:22:14.098009 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9903 13:22:14.104770 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9904 13:22:14.108244 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9905 13:22:14.114766 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9906 13:22:14.118007 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9907 13:22:14.124864 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9908 13:22:14.128051 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9909 13:22:14.134583 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9910 13:22:14.138236 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9911 13:22:14.140922 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9912 13:22:14.148022 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9913 13:22:14.150895 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9914 13:22:14.157771 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9915 13:22:14.160795 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9916 13:22:14.167187 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9917 13:22:14.170643 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9918 13:22:14.174274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9919 13:22:14.180692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9920 13:22:14.183679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9921 13:22:14.190801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9922 13:22:14.193682 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9923 13:22:14.201116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9924 13:22:14.203699 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9925 13:22:14.210560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9926 13:22:14.213481 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9927 13:22:14.220351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9928 13:22:14.223821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9929 13:22:14.230200 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9930 13:22:14.233494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9931 13:22:14.240265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9932 13:22:14.243421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9933 13:22:14.249649 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9934 13:22:14.253342 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9935 13:22:14.259822 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9936 13:22:14.262674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9937 13:22:14.269431 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9938 13:22:14.272387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9939 13:22:14.278913 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9940 13:22:14.283208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9941 13:22:14.288978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9942 13:22:14.292368 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9943 13:22:14.298793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9944 13:22:14.302743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9945 13:22:14.308674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9946 13:22:14.312831 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9947 13:22:14.319714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9948 13:22:14.322776 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9949 13:22:14.328903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9950 13:22:14.332404 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9951 13:22:14.335280 INFO: [APUAPC] vio 0
9952 13:22:14.338883 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9953 13:22:14.345628 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9954 13:22:14.348546 INFO: [APUAPC] D0_APC_0: 0x400510
9955 13:22:14.352133 INFO: [APUAPC] D0_APC_1: 0x0
9956 13:22:14.352697 INFO: [APUAPC] D0_APC_2: 0x1540
9957 13:22:14.355516 INFO: [APUAPC] D0_APC_3: 0x0
9958 13:22:14.358721 INFO: [APUAPC] D1_APC_0: 0xffffffff
9959 13:22:14.362379 INFO: [APUAPC] D1_APC_1: 0xffffffff
9960 13:22:14.365446 INFO: [APUAPC] D1_APC_2: 0x3fffff
9961 13:22:14.368549 INFO: [APUAPC] D1_APC_3: 0x0
9962 13:22:14.371663 INFO: [APUAPC] D2_APC_0: 0xffffffff
9963 13:22:14.375155 INFO: [APUAPC] D2_APC_1: 0xffffffff
9964 13:22:14.378034 INFO: [APUAPC] D2_APC_2: 0x3fffff
9965 13:22:14.381980 INFO: [APUAPC] D2_APC_3: 0x0
9966 13:22:14.385502 INFO: [APUAPC] D3_APC_0: 0xffffffff
9967 13:22:14.388531 INFO: [APUAPC] D3_APC_1: 0xffffffff
9968 13:22:14.391929 INFO: [APUAPC] D3_APC_2: 0x3fffff
9969 13:22:14.395123 INFO: [APUAPC] D3_APC_3: 0x0
9970 13:22:14.398712 INFO: [APUAPC] D4_APC_0: 0xffffffff
9971 13:22:14.401595 INFO: [APUAPC] D4_APC_1: 0xffffffff
9972 13:22:14.404919 INFO: [APUAPC] D4_APC_2: 0x3fffff
9973 13:22:14.408431 INFO: [APUAPC] D4_APC_3: 0x0
9974 13:22:14.411578 INFO: [APUAPC] D5_APC_0: 0xffffffff
9975 13:22:14.414840 INFO: [APUAPC] D5_APC_1: 0xffffffff
9976 13:22:14.418181 INFO: [APUAPC] D5_APC_2: 0x3fffff
9977 13:22:14.421321 INFO: [APUAPC] D5_APC_3: 0x0
9978 13:22:14.424401 INFO: [APUAPC] D6_APC_0: 0xffffffff
9979 13:22:14.428139 INFO: [APUAPC] D6_APC_1: 0xffffffff
9980 13:22:14.431851 INFO: [APUAPC] D6_APC_2: 0x3fffff
9981 13:22:14.434346 INFO: [APUAPC] D6_APC_3: 0x0
9982 13:22:14.437959 INFO: [APUAPC] D7_APC_0: 0xffffffff
9983 13:22:14.442165 INFO: [APUAPC] D7_APC_1: 0xffffffff
9984 13:22:14.444819 INFO: [APUAPC] D7_APC_2: 0x3fffff
9985 13:22:14.447379 INFO: [APUAPC] D7_APC_3: 0x0
9986 13:22:14.450657 INFO: [APUAPC] D8_APC_0: 0xffffffff
9987 13:22:14.454517 INFO: [APUAPC] D8_APC_1: 0xffffffff
9988 13:22:14.457468 INFO: [APUAPC] D8_APC_2: 0x3fffff
9989 13:22:14.461182 INFO: [APUAPC] D8_APC_3: 0x0
9990 13:22:14.464009 INFO: [APUAPC] D9_APC_0: 0xffffffff
9991 13:22:14.467283 INFO: [APUAPC] D9_APC_1: 0xffffffff
9992 13:22:14.470877 INFO: [APUAPC] D9_APC_2: 0x3fffff
9993 13:22:14.474450 INFO: [APUAPC] D9_APC_3: 0x0
9994 13:22:14.477375 INFO: [APUAPC] D10_APC_0: 0xffffffff
9995 13:22:14.480404 INFO: [APUAPC] D10_APC_1: 0xffffffff
9996 13:22:14.483756 INFO: [APUAPC] D10_APC_2: 0x3fffff
9997 13:22:14.487011 INFO: [APUAPC] D10_APC_3: 0x0
9998 13:22:14.490402 INFO: [APUAPC] D11_APC_0: 0xffffffff
9999 13:22:14.493746 INFO: [APUAPC] D11_APC_1: 0xffffffff
10000 13:22:14.496863 INFO: [APUAPC] D11_APC_2: 0x3fffff
10001 13:22:14.500333 INFO: [APUAPC] D11_APC_3: 0x0
10002 13:22:14.503524 INFO: [APUAPC] D12_APC_0: 0xffffffff
10003 13:22:14.507074 INFO: [APUAPC] D12_APC_1: 0xffffffff
10004 13:22:14.510209 INFO: [APUAPC] D12_APC_2: 0x3fffff
10005 13:22:14.513801 INFO: [APUAPC] D12_APC_3: 0x0
10006 13:22:14.517020 INFO: [APUAPC] D13_APC_0: 0xffffffff
10007 13:22:14.520148 INFO: [APUAPC] D13_APC_1: 0xffffffff
10008 13:22:14.523083 INFO: [APUAPC] D13_APC_2: 0x3fffff
10009 13:22:14.526348 INFO: [APUAPC] D13_APC_3: 0x0
10010 13:22:14.530211 INFO: [APUAPC] D14_APC_0: 0xffffffff
10011 13:22:14.533449 INFO: [APUAPC] D14_APC_1: 0xffffffff
10012 13:22:14.536211 INFO: [APUAPC] D14_APC_2: 0x3fffff
10013 13:22:14.540112 INFO: [APUAPC] D14_APC_3: 0x0
10014 13:22:14.542735 INFO: [APUAPC] D15_APC_0: 0xffffffff
10015 13:22:14.546499 INFO: [APUAPC] D15_APC_1: 0xffffffff
10016 13:22:14.549824 INFO: [APUAPC] D15_APC_2: 0x3fffff
10017 13:22:14.553000 INFO: [APUAPC] D15_APC_3: 0x0
10018 13:22:14.556446 INFO: [APUAPC] APC_CON: 0x4
10019 13:22:14.559503 INFO: [NOCDAPC] D0_APC_0: 0x0
10020 13:22:14.562685 INFO: [NOCDAPC] D0_APC_1: 0x0
10021 13:22:14.566328 INFO: [NOCDAPC] D1_APC_0: 0x0
10022 13:22:14.569601 INFO: [NOCDAPC] D1_APC_1: 0xfff
10023 13:22:14.572521 INFO: [NOCDAPC] D2_APC_0: 0x0
10024 13:22:14.573080 INFO: [NOCDAPC] D2_APC_1: 0xfff
10025 13:22:14.576701 INFO: [NOCDAPC] D3_APC_0: 0x0
10026 13:22:14.579239 INFO: [NOCDAPC] D3_APC_1: 0xfff
10027 13:22:14.583500 INFO: [NOCDAPC] D4_APC_0: 0x0
10028 13:22:14.585883 INFO: [NOCDAPC] D4_APC_1: 0xfff
10029 13:22:14.589593 INFO: [NOCDAPC] D5_APC_0: 0x0
10030 13:22:14.592273 INFO: [NOCDAPC] D5_APC_1: 0xfff
10031 13:22:14.595796 INFO: [NOCDAPC] D6_APC_0: 0x0
10032 13:22:14.598950 INFO: [NOCDAPC] D6_APC_1: 0xfff
10033 13:22:14.602215 INFO: [NOCDAPC] D7_APC_0: 0x0
10034 13:22:14.605286 INFO: [NOCDAPC] D7_APC_1: 0xfff
10035 13:22:14.609001 INFO: [NOCDAPC] D8_APC_0: 0x0
10036 13:22:14.609565 INFO: [NOCDAPC] D8_APC_1: 0xfff
10037 13:22:14.611970 INFO: [NOCDAPC] D9_APC_0: 0x0
10038 13:22:14.615575 INFO: [NOCDAPC] D9_APC_1: 0xfff
10039 13:22:14.618460 INFO: [NOCDAPC] D10_APC_0: 0x0
10040 13:22:14.622288 INFO: [NOCDAPC] D10_APC_1: 0xfff
10041 13:22:14.625705 INFO: [NOCDAPC] D11_APC_0: 0x0
10042 13:22:14.628757 INFO: [NOCDAPC] D11_APC_1: 0xfff
10043 13:22:14.632073 INFO: [NOCDAPC] D12_APC_0: 0x0
10044 13:22:14.635532 INFO: [NOCDAPC] D12_APC_1: 0xfff
10045 13:22:14.639419 INFO: [NOCDAPC] D13_APC_0: 0x0
10046 13:22:14.641865 INFO: [NOCDAPC] D13_APC_1: 0xfff
10047 13:22:14.645123 INFO: [NOCDAPC] D14_APC_0: 0x0
10048 13:22:14.648723 INFO: [NOCDAPC] D14_APC_1: 0xfff
10049 13:22:14.652870 INFO: [NOCDAPC] D15_APC_0: 0x0
10050 13:22:14.654851 INFO: [NOCDAPC] D15_APC_1: 0xfff
10051 13:22:14.655319 INFO: [NOCDAPC] APC_CON: 0x4
10052 13:22:14.658385 INFO: [APUAPC] set_apusys_apc done
10053 13:22:14.661969 INFO: [DEVAPC] devapc_init done
10054 13:22:14.668790 INFO: GICv3 without legacy support detected.
10055 13:22:14.671157 INFO: ARM GICv3 driver initialized in EL3
10056 13:22:14.674363 INFO: Maximum SPI INTID supported: 639
10057 13:22:14.677971 INFO: BL31: Initializing runtime services
10058 13:22:14.684735 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10059 13:22:14.687950 INFO: SPM: enable CPC mode
10060 13:22:14.691328 INFO: mcdi ready for mcusys-off-idle and system suspend
10061 13:22:14.698066 INFO: BL31: Preparing for EL3 exit to normal world
10062 13:22:14.701318 INFO: Entry point address = 0x80000000
10063 13:22:14.704375 INFO: SPSR = 0x8
10064 13:22:14.708516
10065 13:22:14.708979
10066 13:22:14.709342
10067 13:22:14.711696 Starting depthcharge on Spherion...
10068 13:22:14.712156
10069 13:22:14.712594 Wipe memory regions:
10070 13:22:14.712961
10071 13:22:14.715514 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10072 13:22:14.716102 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10073 13:22:14.716581 Setting prompt string to ['asurada:']
10074 13:22:14.717025 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10075 13:22:14.717737 [0x00000040000000, 0x00000054600000)
10076 13:22:14.837775
10077 13:22:14.838330 [0x00000054660000, 0x00000080000000)
10078 13:22:15.098222
10079 13:22:15.098829 [0x000000821a7280, 0x000000ffe64000)
10080 13:22:15.843681
10081 13:22:15.844233 [0x00000100000000, 0x00000240000000)
10082 13:22:17.733646
10083 13:22:17.736413 Initializing XHCI USB controller at 0x11200000.
10084 13:22:18.718405
10085 13:22:18.719016 R8152: Initializing
10086 13:22:18.719391
10087 13:22:18.721016 Version 9 (ocp_data = 6010)
10088 13:22:18.721480
10089 13:22:18.724797 R8152: Done initializing
10090 13:22:18.725260
10091 13:22:18.725623 Adding net device
10092 13:22:19.246746
10093 13:22:19.249453 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10094 13:22:19.249917
10095 13:22:19.250283
10096 13:22:19.250667
10097 13:22:19.251511 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10099 13:22:19.353012 asurada: tftpboot 192.168.201.1 11445605/tftp-deploy-guggq_nz/kernel/image.itb 11445605/tftp-deploy-guggq_nz/kernel/cmdline
10100 13:22:19.353677 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10101 13:22:19.354179 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10102 13:22:19.358566 tftpboot 192.168.201.1 11445605/tftp-deploy-guggq_nz/kernel/image.itp-deploy-guggq_nz/kernel/cmdline
10103 13:22:19.359071
10104 13:22:19.359520 Waiting for link
10105 13:22:19.561136
10106 13:22:19.561873 done.
10107 13:22:19.562334
10108 13:22:19.562777 MAC: f4:f5:e8:50:de:0a
10109 13:22:19.563208
10110 13:22:19.564119 Sending DHCP discover... done.
10111 13:22:19.564580
10112 13:22:19.567801 Waiting for reply... done.
10113 13:22:19.568260
10114 13:22:19.570985 Sending DHCP request... done.
10115 13:22:19.571557
10116 13:22:19.575639 Waiting for reply... done.
10117 13:22:19.576208
10118 13:22:19.576577 My ip is 192.168.201.14
10119 13:22:19.576919
10120 13:22:19.578824 The DHCP server ip is 192.168.201.1
10121 13:22:19.579485
10122 13:22:19.586105 TFTP server IP predefined by user: 192.168.201.1
10123 13:22:19.586736
10124 13:22:19.592219 Bootfile predefined by user: 11445605/tftp-deploy-guggq_nz/kernel/image.itb
10125 13:22:19.592685
10126 13:22:19.593079 Sending tftp read request... done.
10127 13:22:19.595604
10128 13:22:19.601930 Waiting for the transfer...
10129 13:22:19.602388
10130 13:22:19.854645 00000000 ################################################################
10131 13:22:19.854783
10132 13:22:20.089733 00080000 ################################################################
10133 13:22:20.089871
10134 13:22:20.322311 00100000 ################################################################
10135 13:22:20.322471
10136 13:22:20.561099 00180000 ################################################################
10137 13:22:20.561238
10138 13:22:20.805667 00200000 ################################################################
10139 13:22:20.805805
10140 13:22:21.052193 00280000 ################################################################
10141 13:22:21.052339
10142 13:22:21.286999 00300000 ################################################################
10143 13:22:21.287140
10144 13:22:21.540005 00380000 ################################################################
10145 13:22:21.540154
10146 13:22:21.801716 00400000 ################################################################
10147 13:22:21.801854
10148 13:22:22.040926 00480000 ################################################################
10149 13:22:22.041074
10150 13:22:22.278975 00500000 ################################################################
10151 13:22:22.279105
10152 13:22:22.519574 00580000 ################################################################
10153 13:22:22.519704
10154 13:22:22.782411 00600000 ################################################################
10155 13:22:22.782580
10156 13:22:23.032753 00680000 ################################################################
10157 13:22:23.032900
10158 13:22:23.273084 00700000 ################################################################
10159 13:22:23.273219
10160 13:22:23.533324 00780000 ################################################################
10161 13:22:23.533465
10162 13:22:23.790860 00800000 ################################################################
10163 13:22:23.791007
10164 13:22:24.042100 00880000 ################################################################
10165 13:22:24.042237
10166 13:22:24.297774 00900000 ################################################################
10167 13:22:24.297918
10168 13:22:24.549538 00980000 ################################################################
10169 13:22:24.549680
10170 13:22:24.814793 00a00000 ################################################################
10171 13:22:24.814938
10172 13:22:25.065081 00a80000 ################################################################
10173 13:22:25.065222
10174 13:22:25.312240 00b00000 ################################################################
10175 13:22:25.312382
10176 13:22:25.552515 00b80000 ################################################################
10177 13:22:25.552652
10178 13:22:25.803992 00c00000 ################################################################
10179 13:22:25.804138
10180 13:22:26.038321 00c80000 ################################################################
10181 13:22:26.038458
10182 13:22:26.287133 00d00000 ################################################################
10183 13:22:26.287279
10184 13:22:26.521347 00d80000 ################################################################
10185 13:22:26.521485
10186 13:22:26.758984 00e00000 ################################################################
10187 13:22:26.759124
10188 13:22:26.993508 00e80000 ################################################################
10189 13:22:26.993642
10190 13:22:27.251296 00f00000 ################################################################
10191 13:22:27.251438
10192 13:22:27.502890 00f80000 ################################################################
10193 13:22:27.503030
10194 13:22:27.756087 01000000 ################################################################
10195 13:22:27.756231
10196 13:22:28.011072 01080000 ################################################################
10197 13:22:28.011210
10198 13:22:28.283775 01100000 ################################################################
10199 13:22:28.283915
10200 13:22:28.547209 01180000 ################################################################
10201 13:22:28.547368
10202 13:22:28.808122 01200000 ################################################################
10203 13:22:28.808264
10204 13:22:29.079988 01280000 ################################################################
10205 13:22:29.080130
10206 13:22:29.338418 01300000 ################################################################
10207 13:22:29.338583
10208 13:22:29.581036 01380000 ################################################################
10209 13:22:29.581175
10210 13:22:29.809710 01400000 ################################################################
10211 13:22:29.809850
10212 13:22:30.055450 01480000 ################################################################
10213 13:22:30.055588
10214 13:22:30.322878 01500000 ################################################################
10215 13:22:30.323018
10216 13:22:30.583257 01580000 ################################################################
10217 13:22:30.583394
10218 13:22:30.827376 01600000 ################################################################
10219 13:22:30.827519
10220 13:22:31.099958 01680000 ################################################################
10221 13:22:31.100103
10222 13:22:31.364148 01700000 ################################################################
10223 13:22:31.364284
10224 13:22:31.623674 01780000 ################################################################
10225 13:22:31.623809
10226 13:22:31.887395 01800000 ################################################################
10227 13:22:31.887539
10228 13:22:32.150482 01880000 ################################################################
10229 13:22:32.150648
10230 13:22:32.416210 01900000 ################################################################
10231 13:22:32.416351
10232 13:22:32.656414 01980000 ################################################################
10233 13:22:32.656553
10234 13:22:32.926064 01a00000 ################################################################
10235 13:22:32.926200
10236 13:22:33.193148 01a80000 ################################################################
10237 13:22:33.193285
10238 13:22:33.419520 01b00000 ################################################################
10239 13:22:33.419656
10240 13:22:33.656363 01b80000 ################################################################
10241 13:22:33.656505
10242 13:22:33.924501 01c00000 ################################################################
10243 13:22:33.924640
10244 13:22:34.190544 01c80000 ################################################################
10245 13:22:34.190726
10246 13:22:34.459683 01d00000 ################################################################
10247 13:22:34.459813
10248 13:22:34.732780 01d80000 ################################################################
10249 13:22:34.732920
10250 13:22:35.004026 01e00000 ################################################################
10251 13:22:35.004170
10252 13:22:35.277249 01e80000 ################################################################
10253 13:22:35.277389
10254 13:22:35.548148 01f00000 ################################################################
10255 13:22:35.548287
10256 13:22:35.818098 01f80000 ################################################################
10257 13:22:35.818239
10258 13:22:36.086160 02000000 ################################################################
10259 13:22:36.086305
10260 13:22:36.345520 02080000 ################################################################
10261 13:22:36.345656
10262 13:22:36.618068 02100000 ################################################################
10263 13:22:36.618204
10264 13:22:36.889753 02180000 ################################################################
10265 13:22:36.889931
10266 13:22:37.156947 02200000 ################################################################
10267 13:22:37.157084
10268 13:22:37.400846 02280000 ################################################################
10269 13:22:37.400986
10270 13:22:37.666040 02300000 ################################################################
10271 13:22:37.666179
10272 13:22:37.932975 02380000 ################################################################
10273 13:22:37.933119
10274 13:22:38.189839 02400000 ################################################################
10275 13:22:38.189980
10276 13:22:38.459461 02480000 ################################################################
10277 13:22:38.459612
10278 13:22:38.728486 02500000 ################################################################
10279 13:22:38.728627
10280 13:22:38.987061 02580000 ################################################################
10281 13:22:38.987204
10282 13:22:39.245310 02600000 ################################################################
10283 13:22:39.245450
10284 13:22:39.504355 02680000 ################################################################
10285 13:22:39.504525
10286 13:22:39.776588 02700000 ################################################################
10287 13:22:39.776728
10288 13:22:40.048789 02780000 ################################################################
10289 13:22:40.048931
10290 13:22:40.314116 02800000 ################################################################
10291 13:22:40.314259
10292 13:22:40.546211 02880000 ################################################################
10293 13:22:40.546351
10294 13:22:40.773422 02900000 ################################################################
10295 13:22:40.773555
10296 13:22:40.999836 02980000 ################################################################
10297 13:22:40.999980
10298 13:22:41.226346 02a00000 ################################################################
10299 13:22:41.226483
10300 13:22:41.480316 02a80000 ################################################################
10301 13:22:41.480461
10302 13:22:41.712101 02b00000 ################################################################
10303 13:22:41.712234
10304 13:22:41.982274 02b80000 ################################################################
10305 13:22:41.982416
10306 13:22:42.240700 02c00000 ################################################################
10307 13:22:42.240846
10308 13:22:42.481982 02c80000 ################################################################
10309 13:22:42.482123
10310 13:22:42.754211 02d00000 ################################################################
10311 13:22:42.754347
10312 13:22:43.022378 02d80000 ################################################################
10313 13:22:43.022529
10314 13:22:43.250166 02e00000 ################################################################
10315 13:22:43.250311
10316 13:22:43.480483 02e80000 ################################################################
10317 13:22:43.480674
10318 13:22:43.731186 02f00000 ################################################################
10319 13:22:43.731331
10320 13:22:43.998438 02f80000 ################################################################
10321 13:22:43.998578
10322 13:22:44.268828 03000000 ################################################################
10323 13:22:44.268968
10324 13:22:44.521593 03080000 ################################################################
10325 13:22:44.521741
10326 13:22:44.761183 03100000 ################################################################
10327 13:22:44.761315
10328 13:22:44.992342 03180000 ################################################################
10329 13:22:44.992475
10330 13:22:45.229658 03200000 ################################################################
10331 13:22:45.229798
10332 13:22:45.459488 03280000 ################################################################
10333 13:22:45.459632
10334 13:22:45.713973 03300000 ################################################################
10335 13:22:45.714107
10336 13:22:45.955592 03380000 ################################################################
10337 13:22:45.955733
10338 13:22:46.186744 03400000 ################################################################
10339 13:22:46.186888
10340 13:22:46.414796 03480000 ################################################################
10341 13:22:46.414929
10342 13:22:46.661684 03500000 ################################################################
10343 13:22:46.661820
10344 13:22:46.906525 03580000 ################################################################
10345 13:22:46.906695
10346 13:22:47.159917 03600000 ################################################################
10347 13:22:47.160057
10348 13:22:47.427517 03680000 ################################################################
10349 13:22:47.427656
10350 13:22:47.698638 03700000 ################################################################
10351 13:22:47.698776
10352 13:22:47.970069 03780000 ################################################################
10353 13:22:47.970208
10354 13:22:48.242315 03800000 ################################################################
10355 13:22:48.242457
10356 13:22:48.514331 03880000 ################################################################
10357 13:22:48.514474
10358 13:22:48.786112 03900000 ################################################################
10359 13:22:48.786256
10360 13:22:49.052592 03980000 ################################################################
10361 13:22:49.052730
10362 13:22:49.325006 03a00000 ################################################################
10363 13:22:49.325154
10364 13:22:49.597443 03a80000 ################################################################
10365 13:22:49.597596
10366 13:22:49.869325 03b00000 ################################################################
10367 13:22:49.869465
10368 13:22:50.141840 03b80000 ################################################################
10369 13:22:50.141977
10370 13:22:50.377244 03c00000 ################################################################
10371 13:22:50.377384
10372 13:22:50.603988 03c80000 ################################################################
10373 13:22:50.604126
10374 13:22:50.833367 03d00000 ################################################################
10375 13:22:50.833498
10376 13:22:51.091705 03d80000 ################################################################
10377 13:22:51.091841
10378 13:22:51.365001 03e00000 ################################################################
10379 13:22:51.365142
10380 13:22:51.618355 03e80000 ################################################################
10381 13:22:51.618491
10382 13:22:51.891151 03f00000 ################################################################
10383 13:22:51.891290
10384 13:22:52.162322 03f80000 ################################################################
10385 13:22:52.162460
10386 13:22:52.433925 04000000 ################################################################
10387 13:22:52.434066
10388 13:22:52.703644 04080000 ################################################################
10389 13:22:52.703788
10390 13:22:52.972416 04100000 ################################################################
10391 13:22:52.972560
10392 13:22:53.220533 04180000 ################################################################
10393 13:22:53.220671
10394 13:22:53.458844 04200000 ################################################################
10395 13:22:53.458983
10396 13:22:53.720369 04280000 ################################################################
10397 13:22:53.720511
10398 13:22:53.964128 04300000 ################################################################
10399 13:22:53.964267
10400 13:22:54.191727 04380000 ################################################################
10401 13:22:54.191863
10402 13:22:54.430899 04400000 ################################################################
10403 13:22:54.431033
10404 13:22:54.700573 04480000 ################################################################
10405 13:22:54.700732
10406 13:22:54.972425 04500000 ################################################################
10407 13:22:54.972560
10408 13:22:55.244519 04580000 ################################################################
10409 13:22:55.244655
10410 13:22:55.515148 04600000 ################################################################
10411 13:22:55.515284
10412 13:22:55.780025 04680000 ################################################################
10413 13:22:55.780167
10414 13:22:56.043393 04700000 ################################################################
10415 13:22:56.043531
10416 13:22:56.308608 04780000 ################################################################
10417 13:22:56.308743
10418 13:22:56.576383 04800000 ################################################################
10419 13:22:56.576521
10420 13:22:56.848302 04880000 ################################################################
10421 13:22:56.848483
10422 13:22:57.119371 04900000 ################################################################
10423 13:22:57.119511
10424 13:22:57.392090 04980000 ################################################################
10425 13:22:57.392230
10426 13:22:57.664520 04a00000 ################################################################
10427 13:22:57.664659
10428 13:22:57.937301 04a80000 ################################################################
10429 13:22:57.937443
10430 13:22:58.199657 04b00000 ################################################################
10431 13:22:58.199801
10432 13:22:58.469949 04b80000 ################################################################
10433 13:22:58.470087
10434 13:22:58.712074 04c00000 ################################################################
10435 13:22:58.712210
10436 13:22:58.969440 04c80000 ################################################################
10437 13:22:58.969580
10438 13:22:59.208073 04d00000 ################################################################
10439 13:22:59.208213
10440 13:22:59.454477 04d80000 ################################################################
10441 13:22:59.454666
10442 13:22:59.705354 04e00000 ################################################################
10443 13:22:59.705493
10444 13:22:59.953390 04e80000 ################################################################
10445 13:22:59.953535
10446 13:23:00.184007 04f00000 ################################################################
10447 13:23:00.184140
10448 13:23:00.433265 04f80000 ################################################################
10449 13:23:00.433400
10450 13:23:00.668448 05000000 ################################################################
10451 13:23:00.668584
10452 13:23:00.913072 05080000 ################################################################
10453 13:23:00.913216
10454 13:23:01.184196 05100000 ################################################################
10455 13:23:01.184340
10456 13:23:01.437873 05180000 ################################################################
10457 13:23:01.438012
10458 13:23:01.704089 05200000 ################################################################
10459 13:23:01.704233
10460 13:23:01.965228 05280000 ################################################################
10461 13:23:01.965376
10462 13:23:02.232589 05300000 ################################################################
10463 13:23:02.232734
10464 13:23:02.472165 05380000 ################################################################
10465 13:23:02.472299
10466 13:23:02.723932 05400000 ################################################################
10467 13:23:02.724067
10468 13:23:02.975240 05480000 ################################################################
10469 13:23:02.975383
10470 13:23:03.222652 05500000 ################################################################
10471 13:23:03.222790
10472 13:23:03.450616 05580000 ################################################################
10473 13:23:03.450747
10474 13:23:03.682403 05600000 ################################################################
10475 13:23:03.682542
10476 13:23:03.923937 05680000 ################################################################
10477 13:23:03.924073
10478 13:23:04.174882 05700000 ################################################################
10479 13:23:04.175029
10480 13:23:04.444298 05780000 ################################################################
10481 13:23:04.444439
10482 13:23:04.722237 05800000 ################################################################
10483 13:23:04.722376
10484 13:23:04.973939 05880000 ################################################################
10485 13:23:04.974078
10486 13:23:05.233185 05900000 ################################################################
10487 13:23:05.233327
10488 13:23:05.483011 05980000 ################################################################
10489 13:23:05.483151
10490 13:23:05.737830 05a00000 ################################################################
10491 13:23:05.737965
10492 13:23:05.992888 05a80000 ################################################################
10493 13:23:05.993027
10494 13:23:06.265677 05b00000 ################################################################
10495 13:23:06.265819
10496 13:23:06.533040 05b80000 ################################################################
10497 13:23:06.533180
10498 13:23:06.800817 05c00000 ################################################################
10499 13:23:06.800955
10500 13:23:07.070220 05c80000 ################################################################
10501 13:23:07.070362
10502 13:23:07.340858 05d00000 ################################################################
10503 13:23:07.341001
10504 13:23:07.614329 05d80000 ################################################################
10505 13:23:07.614466
10506 13:23:07.886960 05e00000 ################################################################
10507 13:23:07.887103
10508 13:23:08.160104 05e80000 ################################################################
10509 13:23:08.160245
10510 13:23:08.433640 05f00000 ################################################################
10511 13:23:08.433782
10512 13:23:08.706323 05f80000 ################################################################
10513 13:23:08.706460
10514 13:23:08.977278 06000000 ################################################################
10515 13:23:08.977425
10516 13:23:09.239784 06080000 ################################################################
10517 13:23:09.239927
10518 13:23:09.502177 06100000 ################################################################
10519 13:23:09.502319
10520 13:23:09.738489 06180000 ################################################################
10521 13:23:09.738631
10522 13:23:09.988629 06200000 ################################################################
10523 13:23:09.988768
10524 13:23:10.258829 06280000 ################################################################
10525 13:23:10.258970
10526 13:23:10.503110 06300000 ################################################################
10527 13:23:10.503251
10528 13:23:10.772610 06380000 ################################################################
10529 13:23:10.772746
10530 13:23:11.031238 06400000 ################################################################
10531 13:23:11.031380
10532 13:23:11.295088 06480000 ################################################################
10533 13:23:11.295227
10534 13:23:11.565868 06500000 ################################################################
10535 13:23:11.566009
10536 13:23:11.838400 06580000 ################################################################
10537 13:23:11.838539
10538 13:23:12.105511 06600000 ################################################################
10539 13:23:12.105657
10540 13:23:12.376818 06680000 ################################################################
10541 13:23:12.376959
10542 13:23:12.644959 06700000 ################################################################
10543 13:23:12.645101
10544 13:23:12.898504 06780000 ################################################################
10545 13:23:12.898646
10546 13:23:13.075019 06800000 ########################################## done.
10547 13:23:13.075155
10548 13:23:13.077694 The bootfile was 109394790 bytes long.
10549 13:23:13.077784
10550 13:23:13.081446 Sending tftp read request... done.
10551 13:23:13.081623
10552 13:23:13.081713 Waiting for the transfer...
10553 13:23:13.084401
10554 13:23:13.084578 00000000 # done.
10555 13:23:13.084670
10556 13:23:13.091003 Command line loaded dynamically from TFTP file: 11445605/tftp-deploy-guggq_nz/kernel/cmdline
10557 13:23:13.091193
10558 13:23:13.104005 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10559 13:23:13.107706
10560 13:23:13.107938 Loading FIT.
10561 13:23:13.108095
10562 13:23:13.111135 Image ramdisk-1 has 98307255 bytes.
10563 13:23:13.111313
10564 13:23:13.114456 Image fdt-1 has 47278 bytes.
10565 13:23:13.114809
10566 13:23:13.118066 Image kernel-1 has 11038222 bytes.
10567 13:23:13.118274
10568 13:23:13.123606 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10569 13:23:13.123869
10570 13:23:13.143242 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10571 13:23:13.143339
10572 13:23:13.146784 Choosing best match conf-1 for compat google,spherion-rev2.
10573 13:23:13.151673
10574 13:23:13.156037 Connected to device vid:did:rid of 1ae0:0028:00
10575 13:23:13.163407
10576 13:23:13.166657 tpm_get_response: command 0x17b, return code 0x0
10577 13:23:13.166849
10578 13:23:13.173516 ec_init: CrosEC protocol v3 supported (256, 248)
10579 13:23:13.173741
10580 13:23:13.176702 tpm_cleanup: add release locality here.
10581 13:23:13.176872
10582 13:23:13.180349 Shutting down all USB controllers.
10583 13:23:13.180600
10584 13:23:13.183140 Removing current net device
10585 13:23:13.183317
10586 13:23:13.186251 Exiting depthcharge with code 4 at timestamp: 87877259
10587 13:23:13.186450
10588 13:23:13.190156 LZMA decompressing kernel-1 to 0x821a6718
10589 13:23:13.190460
10590 13:23:13.196310 LZMA decompressing kernel-1 to 0x40000000
10591 13:23:14.583872
10592 13:23:14.584424 jumping to kernel
10593 13:23:14.586297 end: 2.2.4 bootloader-commands (duration 00:01:00) [common]
10594 13:23:14.586888 start: 2.2.5 auto-login-action (timeout 00:03:25) [common]
10595 13:23:14.587297 Setting prompt string to ['Linux version [0-9]']
10596 13:23:14.587685 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10597 13:23:14.588058 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10598 13:23:14.665997
10599 13:23:14.669053 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10600 13:23:14.672550 start: 2.2.5.1 login-action (timeout 00:03:25) [common]
10601 13:23:14.673149 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10602 13:23:14.673547 Setting prompt string to []
10603 13:23:14.673985 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10604 13:23:14.674389 Using line separator: #'\n'#
10605 13:23:14.674748 No login prompt set.
10606 13:23:14.675090 Parsing kernel messages
10607 13:23:14.675415 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10608 13:23:14.675969 [login-action] Waiting for messages, (timeout 00:03:25)
10609 13:23:14.691997 [ 0.000000] Linux version 6.1.46-cip4 (KernelCI@build-j36642-arm64-gcc-10-defconfig-arm64-chromebook-rxg94) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Sep 6 13:11:19 UTC 2023
10610 13:23:14.695574 [ 0.000000] random: crng init done
10611 13:23:14.701845 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10612 13:23:14.705028 [ 0.000000] efi: UEFI not found.
10613 13:23:14.711135 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10614 13:23:14.721245 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10615 13:23:14.727872 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10616 13:23:14.737697 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10617 13:23:14.743925 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10618 13:23:14.750698 [ 0.000000] printk: bootconsole [mtk8250] enabled
10619 13:23:14.758294 [ 0.000000] NUMA: No NUMA configuration found
10620 13:23:14.764214 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10621 13:23:14.771419 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10622 13:23:14.771988 [ 0.000000] Zone ranges:
10623 13:23:14.777416 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10624 13:23:14.780465 [ 0.000000] DMA32 empty
10625 13:23:14.787635 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10626 13:23:14.790922 [ 0.000000] Movable zone start for each node
10627 13:23:14.794072 [ 0.000000] Early memory node ranges
10628 13:23:14.800327 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10629 13:23:14.806787 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10630 13:23:14.813838 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10631 13:23:14.820121 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10632 13:23:14.827467 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10633 13:23:14.833121 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10634 13:23:14.889798 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10635 13:23:14.896159 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10636 13:23:14.903249 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10637 13:23:14.906370 [ 0.000000] psci: probing for conduit method from DT.
10638 13:23:14.912680 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10639 13:23:14.916239 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10640 13:23:14.922413 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10641 13:23:14.926023 [ 0.000000] psci: SMC Calling Convention v1.2
10642 13:23:14.932097 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10643 13:23:14.936060 [ 0.000000] Detected VIPT I-cache on CPU0
10644 13:23:14.942937 [ 0.000000] CPU features: detected: GIC system register CPU interface
10645 13:23:14.948755 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10646 13:23:14.955871 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10647 13:23:14.962254 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10648 13:23:14.971535 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10649 13:23:14.978179 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10650 13:23:14.982182 [ 0.000000] alternatives: applying boot alternatives
10651 13:23:14.988490 [ 0.000000] Fallback order for Node 0: 0
10652 13:23:14.995414 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10653 13:23:14.998846 [ 0.000000] Policy zone: Normal
10654 13:23:15.011897 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10655 13:23:15.021462 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10656 13:23:15.033916 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10657 13:23:15.043769 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10658 13:23:15.050530 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10659 13:23:15.053793 <6>[ 0.000000] software IO TLB: area num 8.
10660 13:23:15.111574 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10661 13:23:15.259944 <6>[ 0.000000] Memory: 7873552K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 479216K reserved, 32768K cma-reserved)
10662 13:23:15.266839 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10663 13:23:15.272989 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10664 13:23:15.277010 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10665 13:23:15.283192 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10666 13:23:15.290009 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10667 13:23:15.293381 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10668 13:23:15.303044 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10669 13:23:15.309538 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10670 13:23:15.316967 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10671 13:23:15.322789 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10672 13:23:15.325624 <6>[ 0.000000] GICv3: 608 SPIs implemented
10673 13:23:15.329437 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10674 13:23:15.335741 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10675 13:23:15.339057 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10676 13:23:15.346021 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10677 13:23:15.359312 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10678 13:23:15.372334 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10679 13:23:15.378804 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10680 13:23:15.387142 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10681 13:23:15.399975 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10682 13:23:15.406840 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10683 13:23:15.413350 <6>[ 0.009233] Console: colour dummy device 80x25
10684 13:23:15.423373 <6>[ 0.013958] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10685 13:23:15.430521 <6>[ 0.024401] pid_max: default: 32768 minimum: 301
10686 13:23:15.433090 <6>[ 0.029273] LSM: Security Framework initializing
10687 13:23:15.439744 <6>[ 0.034212] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10688 13:23:15.449391 <6>[ 0.042074] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10689 13:23:15.459704 <6>[ 0.051496] cblist_init_generic: Setting adjustable number of callback queues.
10690 13:23:15.462581 <6>[ 0.058988] cblist_init_generic: Setting shift to 3 and lim to 1.
10691 13:23:15.472532 <6>[ 0.065324] cblist_init_generic: Setting adjustable number of callback queues.
10692 13:23:15.479136 <6>[ 0.072750] cblist_init_generic: Setting shift to 3 and lim to 1.
10693 13:23:15.482792 <6>[ 0.079188] rcu: Hierarchical SRCU implementation.
10694 13:23:15.489268 <6>[ 0.084232] rcu: Max phase no-delay instances is 1000.
10695 13:23:15.495991 <6>[ 0.091267] EFI services will not be available.
10696 13:23:15.499037 <6>[ 0.096237] smp: Bringing up secondary CPUs ...
10697 13:23:15.507438 <6>[ 0.101290] Detected VIPT I-cache on CPU1
10698 13:23:15.514719 <6>[ 0.101359] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10699 13:23:15.521346 <6>[ 0.101393] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10700 13:23:15.524138 <6>[ 0.101726] Detected VIPT I-cache on CPU2
10701 13:23:15.530765 <6>[ 0.101775] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10702 13:23:15.540959 <6>[ 0.101790] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10703 13:23:15.543706 <6>[ 0.102048] Detected VIPT I-cache on CPU3
10704 13:23:15.550968 <6>[ 0.102095] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10705 13:23:15.557391 <6>[ 0.102109] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10706 13:23:15.560507 <6>[ 0.102415] CPU features: detected: Spectre-v4
10707 13:23:15.567502 <6>[ 0.102421] CPU features: detected: Spectre-BHB
10708 13:23:15.570182 <6>[ 0.102426] Detected PIPT I-cache on CPU4
10709 13:23:15.576989 <6>[ 0.102482] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10710 13:23:15.583753 <6>[ 0.102499] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10711 13:23:15.590011 <6>[ 0.102795] Detected PIPT I-cache on CPU5
10712 13:23:15.596636 <6>[ 0.102856] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10713 13:23:15.603323 <6>[ 0.102873] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10714 13:23:15.606281 <6>[ 0.103156] Detected PIPT I-cache on CPU6
10715 13:23:15.616051 <6>[ 0.103219] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10716 13:23:15.623261 <6>[ 0.103235] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10717 13:23:15.626002 <6>[ 0.103532] Detected PIPT I-cache on CPU7
10718 13:23:15.633269 <6>[ 0.103595] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10719 13:23:15.639355 <6>[ 0.103612] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10720 13:23:15.643070 <6>[ 0.103659] smp: Brought up 1 node, 8 CPUs
10721 13:23:15.649431 <6>[ 0.244976] SMP: Total of 8 processors activated.
10722 13:23:15.655820 <6>[ 0.249896] CPU features: detected: 32-bit EL0 Support
10723 13:23:15.662503 <6>[ 0.255259] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10724 13:23:15.669292 <6>[ 0.264059] CPU features: detected: Common not Private translations
10725 13:23:15.675796 <6>[ 0.270534] CPU features: detected: CRC32 instructions
10726 13:23:15.682394 <6>[ 0.275918] CPU features: detected: RCpc load-acquire (LDAPR)
10727 13:23:15.685601 <6>[ 0.281878] CPU features: detected: LSE atomic instructions
10728 13:23:15.692042 <6>[ 0.287659] CPU features: detected: Privileged Access Never
10729 13:23:15.698539 <6>[ 0.293439] CPU features: detected: RAS Extension Support
10730 13:23:15.705504 <6>[ 0.299048] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10731 13:23:15.708683 <6>[ 0.306267] CPU: All CPU(s) started at EL2
10732 13:23:15.715066 <6>[ 0.310610] alternatives: applying system-wide alternatives
10733 13:23:15.725803 <6>[ 0.321264] devtmpfs: initialized
10734 13:23:15.740786 <6>[ 0.330210] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10735 13:23:15.747346 <6>[ 0.340170] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10736 13:23:15.753675 <6>[ 0.348205] pinctrl core: initialized pinctrl subsystem
10737 13:23:15.757572 <6>[ 0.354845] DMI not present or invalid.
10738 13:23:15.763811 <6>[ 0.359255] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10739 13:23:15.773754 <6>[ 0.366106] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10740 13:23:15.780129 <6>[ 0.373687] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10741 13:23:15.790170 <6>[ 0.381904] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10742 13:23:15.793286 <6>[ 0.390147] audit: initializing netlink subsys (disabled)
10743 13:23:15.803288 <5>[ 0.395842] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10744 13:23:15.809974 <6>[ 0.396550] thermal_sys: Registered thermal governor 'step_wise'
10745 13:23:15.816101 <6>[ 0.403809] thermal_sys: Registered thermal governor 'power_allocator'
10746 13:23:15.819440 <6>[ 0.410063] cpuidle: using governor menu
10747 13:23:15.825976 <6>[ 0.421022] NET: Registered PF_QIPCRTR protocol family
10748 13:23:15.832760 <6>[ 0.426505] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10749 13:23:15.839488 <6>[ 0.433607] ASID allocator initialised with 32768 entries
10750 13:23:15.842770 <6>[ 0.440166] Serial: AMBA PL011 UART driver
10751 13:23:15.852543 <4>[ 0.448921] Trying to register duplicate clock ID: 134
10752 13:23:15.909548 <6>[ 0.508235] KASLR enabled
10753 13:23:15.923458 <6>[ 0.515949] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10754 13:23:15.929819 <6>[ 0.522961] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10755 13:23:15.937319 <6>[ 0.529448] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10756 13:23:15.942668 <6>[ 0.536455] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10757 13:23:15.949834 <6>[ 0.542944] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10758 13:23:15.955803 <6>[ 0.549948] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10759 13:23:15.962588 <6>[ 0.556433] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10760 13:23:15.969106 <6>[ 0.563438] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10761 13:23:15.972724 <6>[ 0.570897] ACPI: Interpreter disabled.
10762 13:23:15.981237 <6>[ 0.577317] iommu: Default domain type: Translated
10763 13:23:15.987971 <6>[ 0.582470] iommu: DMA domain TLB invalidation policy: strict mode
10764 13:23:15.991165 <5>[ 0.589126] SCSI subsystem initialized
10765 13:23:15.997879 <6>[ 0.593377] usbcore: registered new interface driver usbfs
10766 13:23:16.004359 <6>[ 0.599107] usbcore: registered new interface driver hub
10767 13:23:16.007432 <6>[ 0.604658] usbcore: registered new device driver usb
10768 13:23:16.015079 <6>[ 0.610778] pps_core: LinuxPPS API ver. 1 registered
10769 13:23:16.025178 <6>[ 0.615973] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10770 13:23:16.027744 <6>[ 0.625318] PTP clock support registered
10771 13:23:16.031378 <6>[ 0.629559] EDAC MC: Ver: 3.0.0
10772 13:23:16.039065 <6>[ 0.634748] FPGA manager framework
10773 13:23:16.045856 <6>[ 0.638425] Advanced Linux Sound Architecture Driver Initialized.
10774 13:23:16.048383 <6>[ 0.645192] vgaarb: loaded
10775 13:23:16.055605 <6>[ 0.648357] clocksource: Switched to clocksource arch_sys_counter
10776 13:23:16.058692 <5>[ 0.654804] VFS: Disk quotas dquot_6.6.0
10777 13:23:16.065241 <6>[ 0.658989] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10778 13:23:16.068716 <6>[ 0.666183] pnp: PnP ACPI: disabled
10779 13:23:16.076672 <6>[ 0.672867] NET: Registered PF_INET protocol family
10780 13:23:16.086717 <6>[ 0.678452] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10781 13:23:16.097683 <6>[ 0.690752] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10782 13:23:16.107762 <6>[ 0.699567] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10783 13:23:16.114319 <6>[ 0.707538] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10784 13:23:16.124691 <6>[ 0.716237] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10785 13:23:16.130821 <6>[ 0.725974] TCP: Hash tables configured (established 65536 bind 65536)
10786 13:23:16.137790 <6>[ 0.732840] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10787 13:23:16.147338 <6>[ 0.740039] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10788 13:23:16.154196 <6>[ 0.747743] NET: Registered PF_UNIX/PF_LOCAL protocol family
10789 13:23:16.160627 <6>[ 0.753907] RPC: Registered named UNIX socket transport module.
10790 13:23:16.164137 <6>[ 0.760063] RPC: Registered udp transport module.
10791 13:23:16.170433 <6>[ 0.764996] RPC: Registered tcp transport module.
10792 13:23:16.177053 <6>[ 0.769930] RPC: Registered tcp NFSv4.1 backchannel transport module.
10793 13:23:16.180735 <6>[ 0.776597] PCI: CLS 0 bytes, default 64
10794 13:23:16.183367 <6>[ 0.781034] Unpacking initramfs...
10795 13:23:16.193616 <6>[ 0.785239] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10796 13:23:16.200065 <6>[ 0.793884] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10797 13:23:16.206662 <6>[ 0.802661] kvm [1]: IPA Size Limit: 40 bits
10798 13:23:16.210028 <6>[ 0.807190] kvm [1]: GICv3: no GICV resource entry
10799 13:23:16.216684 <6>[ 0.812212] kvm [1]: disabling GICv2 emulation
10800 13:23:16.222834 <6>[ 0.816901] kvm [1]: GIC system register CPU interface enabled
10801 13:23:16.226407 <6>[ 0.823077] kvm [1]: vgic interrupt IRQ18
10802 13:23:16.232864 <6>[ 0.828438] kvm [1]: VHE mode initialized successfully
10803 13:23:16.239603 <5>[ 0.834867] Initialise system trusted keyrings
10804 13:23:16.246568 <6>[ 0.839680] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10805 13:23:16.254482 <6>[ 0.849759] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10806 13:23:16.260466 <5>[ 0.856148] NFS: Registering the id_resolver key type
10807 13:23:16.264089 <5>[ 0.861447] Key type id_resolver registered
10808 13:23:16.270298 <5>[ 0.865859] Key type id_legacy registered
10809 13:23:16.277175 <6>[ 0.870136] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10810 13:23:16.283507 <6>[ 0.877057] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10811 13:23:16.290276 <6>[ 0.884772] 9p: Installing v9fs 9p2000 file system support
10812 13:23:16.326952 <5>[ 0.922923] Key type asymmetric registered
10813 13:23:16.330195 <5>[ 0.927251] Asymmetric key parser 'x509' registered
10814 13:23:16.340139 <6>[ 0.932394] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10815 13:23:16.343266 <6>[ 0.940013] io scheduler mq-deadline registered
10816 13:23:16.346941 <6>[ 0.944772] io scheduler kyber registered
10817 13:23:16.365586 <6>[ 0.961741] EINJ: ACPI disabled.
10818 13:23:16.398031 <4>[ 0.987541] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10819 13:23:16.407994 <4>[ 0.998164] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10820 13:23:16.423005 <6>[ 1.018989] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10821 13:23:16.430979 <6>[ 1.026987] printk: console [ttyS0] disabled
10822 13:23:16.458774 <6>[ 1.051636] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10823 13:23:16.465456 <6>[ 1.061111] printk: console [ttyS0] enabled
10824 13:23:16.469560 <6>[ 1.061111] printk: console [ttyS0] enabled
10825 13:23:16.475419 <6>[ 1.070003] printk: bootconsole [mtk8250] disabled
10826 13:23:16.479207 <6>[ 1.070003] printk: bootconsole [mtk8250] disabled
10827 13:23:16.486127 <6>[ 1.081288] SuperH (H)SCI(F) driver initialized
10828 13:23:16.489048 <6>[ 1.086557] msm_serial: driver initialized
10829 13:23:16.502683 <6>[ 1.095549] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10830 13:23:16.513108 <6>[ 1.104095] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10831 13:23:16.519377 <6>[ 1.112637] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10832 13:23:16.529186 <6>[ 1.121265] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10833 13:23:16.539558 <6>[ 1.129973] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10834 13:23:16.545776 <6>[ 1.138695] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10835 13:23:16.555673 <6>[ 1.147239] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10836 13:23:16.562976 <6>[ 1.156047] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10837 13:23:16.572532 <6>[ 1.164590] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10838 13:23:16.584397 <6>[ 1.180379] loop: module loaded
10839 13:23:16.590936 <6>[ 1.186411] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10840 13:23:16.613763 <4>[ 1.209732] mtk-pmic-keys: Failed to locate of_node [id: -1]
10841 13:23:16.620788 <6>[ 1.216555] megasas: 07.719.03.00-rc1
10842 13:23:16.630336 <6>[ 1.226126] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10843 13:23:16.639883 <6>[ 1.235772] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10844 13:23:16.656241 <6>[ 1.252121] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10845 13:23:16.716074 <6>[ 1.305631] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10846 13:23:20.168685 <6>[ 4.764760] Freeing initrd memory: 96000K
10847 13:23:20.178058 <6>[ 4.774924] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10848 13:23:20.189681 <6>[ 4.786091] tun: Universal TUN/TAP device driver, 1.6
10849 13:23:20.192715 <6>[ 4.792162] thunder_xcv, ver 1.0
10850 13:23:20.195878 <6>[ 4.795673] thunder_bgx, ver 1.0
10851 13:23:20.199348 <6>[ 4.799170] nicpf, ver 1.0
10852 13:23:20.210083 <6>[ 4.803208] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10853 13:23:20.213359 <6>[ 4.810683] hns3: Copyright (c) 2017 Huawei Corporation.
10854 13:23:20.219978 <6>[ 4.816289] hclge is initializing
10855 13:23:20.222841 <6>[ 4.819870] e1000: Intel(R) PRO/1000 Network Driver
10856 13:23:20.229604 <6>[ 4.824999] e1000: Copyright (c) 1999-2006 Intel Corporation.
10857 13:23:20.236090 <6>[ 4.831010] e1000e: Intel(R) PRO/1000 Network Driver
10858 13:23:20.239790 <6>[ 4.836226] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10859 13:23:20.246321 <6>[ 4.842410] igb: Intel(R) Gigabit Ethernet Network Driver
10860 13:23:20.253130 <6>[ 4.848060] igb: Copyright (c) 2007-2014 Intel Corporation.
10861 13:23:20.259284 <6>[ 4.853899] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10862 13:23:20.266240 <6>[ 4.860417] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10863 13:23:20.269595 <6>[ 4.866880] sky2: driver version 1.30
10864 13:23:20.276031 <6>[ 4.871882] VFIO - User Level meta-driver version: 0.3
10865 13:23:20.283718 <6>[ 4.880141] usbcore: registered new interface driver usb-storage
10866 13:23:20.290239 <6>[ 4.886595] usbcore: registered new device driver onboard-usb-hub
10867 13:23:20.299082 <6>[ 4.895725] mt6397-rtc mt6359-rtc: registered as rtc0
10868 13:23:20.308869 <6>[ 4.901192] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-06T13:23:24 UTC (1694006604)
10869 13:23:20.312321 <6>[ 4.910767] i2c_dev: i2c /dev entries driver
10870 13:23:20.329589 <6>[ 4.922633] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10871 13:23:20.349501 <6>[ 4.945646] cpu cpu0: EM: created perf domain
10872 13:23:20.352402 <6>[ 4.950668] cpu cpu4: EM: created perf domain
10873 13:23:20.359752 <6>[ 4.956351] sdhci: Secure Digital Host Controller Interface driver
10874 13:23:20.366117 <6>[ 4.962779] sdhci: Copyright(c) Pierre Ossman
10875 13:23:20.373231 <6>[ 4.967735] Synopsys Designware Multimedia Card Interface Driver
10876 13:23:20.379813 <6>[ 4.974370] sdhci-pltfm: SDHCI platform and OF driver helper
10877 13:23:20.383460 <6>[ 4.974377] mmc0: CQHCI version 5.10
10878 13:23:20.389959 <6>[ 4.984456] ledtrig-cpu: registered to indicate activity on CPUs
10879 13:23:20.396066 <6>[ 4.991616] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10880 13:23:20.402748 <6>[ 4.998677] usbcore: registered new interface driver usbhid
10881 13:23:20.405860 <6>[ 5.004499] usbhid: USB HID core driver
10882 13:23:20.412904 <6>[ 5.008704] spi_master spi0: will run message pump with realtime priority
10883 13:23:20.460189 <6>[ 5.050110] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10884 13:23:20.479912 <6>[ 5.066151] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10885 13:23:20.483293 <6>[ 5.081174] mmc0: Command Queue Engine enabled
10886 13:23:20.489885 <6>[ 5.083658] cros-ec-spi spi0.0: Chrome EC device registered
10887 13:23:20.496441 <6>[ 5.085921] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10888 13:23:20.503583 <6>[ 5.099155] mmcblk0: mmc0:0001 DA4128 116 GiB
10889 13:23:20.513861 <6>[ 5.105975] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10890 13:23:20.519919 <6>[ 5.111173] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10891 13:23:20.526267 <6>[ 5.116296] NET: Registered PF_PACKET protocol family
10892 13:23:20.529636 <6>[ 5.122664] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10893 13:23:20.536403 <6>[ 5.126558] 9pnet: Installing 9P2000 support
10894 13:23:20.540219 <6>[ 5.132365] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10895 13:23:20.543247 <5>[ 5.136285] Key type dns_resolver registered
10896 13:23:20.549876 <6>[ 5.142106] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10897 13:23:20.556116 <6>[ 5.146545] registered taskstats version 1
10898 13:23:20.559729 <5>[ 5.156894] Loading compiled-in X.509 certificates
10899 13:23:20.595202 <4>[ 5.185193] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10900 13:23:20.605321 <4>[ 5.195908] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10901 13:23:20.612633 <3>[ 5.206436] debugfs: File 'uA_load' in directory '/' already present!
10902 13:23:20.618737 <3>[ 5.213193] debugfs: File 'min_uV' in directory '/' already present!
10903 13:23:20.624804 <3>[ 5.219808] debugfs: File 'max_uV' in directory '/' already present!
10904 13:23:20.631414 <3>[ 5.226417] debugfs: File 'constraint_flags' in directory '/' already present!
10905 13:23:20.643326 <3>[ 5.236072] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10906 13:23:20.652528 <6>[ 5.248228] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10907 13:23:20.658473 <6>[ 5.255038] xhci-mtk 11200000.usb: xHCI Host Controller
10908 13:23:20.665019 <6>[ 5.260529] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10909 13:23:20.675128 <6>[ 5.268382] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10910 13:23:20.681798 <6>[ 5.277817] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10911 13:23:20.688571 <6>[ 5.283918] xhci-mtk 11200000.usb: xHCI Host Controller
10912 13:23:20.694945 <6>[ 5.289405] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10913 13:23:20.701975 <6>[ 5.297053] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10914 13:23:20.708007 <6>[ 5.304770] hub 1-0:1.0: USB hub found
10915 13:23:20.712084 <6>[ 5.308781] hub 1-0:1.0: 1 port detected
10916 13:23:20.721474 <6>[ 5.313039] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10917 13:23:20.725256 <6>[ 5.321593] hub 2-0:1.0: USB hub found
10918 13:23:20.728571 <6>[ 5.325598] hub 2-0:1.0: 1 port detected
10919 13:23:20.737439 <6>[ 5.333742] mtk-msdc 11f70000.mmc: Got CD GPIO
10920 13:23:20.746825 <6>[ 5.340084] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10921 13:23:20.753851 <6>[ 5.348111] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10922 13:23:20.763528 <4>[ 5.356009] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10923 13:23:20.773303 <6>[ 5.365533] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10924 13:23:20.780066 <6>[ 5.373609] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10925 13:23:20.786914 <6>[ 5.381711] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10926 13:23:20.796897 <6>[ 5.389638] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10927 13:23:20.803299 <6>[ 5.397514] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10928 13:23:20.813268 <6>[ 5.405336] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10929 13:23:20.823130 <6>[ 5.415940] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10930 13:23:20.829833 <6>[ 5.424301] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10931 13:23:20.839261 <6>[ 5.432674] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10932 13:23:20.846584 <6>[ 5.441013] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10933 13:23:20.855671 <6>[ 5.449364] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10934 13:23:20.865630 <6>[ 5.457704] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10935 13:23:20.872288 <6>[ 5.466052] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10936 13:23:20.882659 <6>[ 5.474392] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10937 13:23:20.888684 <6>[ 5.482743] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10938 13:23:20.898881 <6>[ 5.491082] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10939 13:23:20.905823 <6>[ 5.499429] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10940 13:23:20.915360 <6>[ 5.507766] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10941 13:23:20.921916 <6>[ 5.516104] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10942 13:23:20.931889 <6>[ 5.524443] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10943 13:23:20.939237 <6>[ 5.532780] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10944 13:23:20.945686 <6>[ 5.541607] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10945 13:23:20.952482 <6>[ 5.548851] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10946 13:23:20.959543 <6>[ 5.555635] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10947 13:23:20.969775 <6>[ 5.562387] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10948 13:23:20.976011 <6>[ 5.569327] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10949 13:23:20.982216 <6>[ 5.576190] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10950 13:23:20.992800 <6>[ 5.585322] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10951 13:23:21.002085 <6>[ 5.594441] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10952 13:23:21.012194 <6>[ 5.603735] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10953 13:23:21.021600 <6>[ 5.613224] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10954 13:23:21.031707 <6>[ 5.622698] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10955 13:23:21.038255 <6>[ 5.631823] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10956 13:23:21.048005 <6>[ 5.641289] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10957 13:23:21.058349 <6>[ 5.650408] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10958 13:23:21.068112 <6>[ 5.659702] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10959 13:23:21.077730 <6>[ 5.669861] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10960 13:23:21.088236 <6>[ 5.681443] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10961 13:23:21.119179 <6>[ 5.712845] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10962 13:23:21.146682 <6>[ 5.743371] hub 2-1:1.0: USB hub found
10963 13:23:21.149887 <6>[ 5.747806] hub 2-1:1.0: 3 ports detected
10964 13:23:21.271609 <6>[ 5.864500] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10965 13:23:21.425562 <6>[ 6.022565] hub 1-1:1.0: USB hub found
10966 13:23:21.429353 <6>[ 6.027046] hub 1-1:1.0: 4 ports detected
10967 13:23:21.751134 <6>[ 6.344672] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10968 13:23:21.882396 <6>[ 6.478872] hub 1-1.1:1.0: USB hub found
10969 13:23:21.885072 <6>[ 6.483218] hub 1-1.1:1.0: 4 ports detected
10970 13:23:21.999180 <6>[ 6.592717] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10971 13:23:22.131157 <6>[ 6.728082] hub 1-1.4:1.0: USB hub found
10972 13:23:22.134484 <6>[ 6.732709] hub 1-1.4:1.0: 2 ports detected
10973 13:23:22.211403 <6>[ 6.804650] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10974 13:23:22.395417 <6>[ 6.988623] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10975 13:23:22.479887 <3>[ 7.076807] usb 1-1.1.4: device descriptor read/64, error -32
10976 13:23:22.671862 <3>[ 7.268810] usb 1-1.1.4: device descriptor read/64, error -32
10977 13:23:22.867061 <6>[ 7.460650] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10978 13:23:23.055128 <6>[ 7.648645] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10979 13:23:23.144035 <3>[ 7.740628] usb 1-1.1.4: device descriptor read/64, error -32
10980 13:23:23.336237 <3>[ 7.932813] usb 1-1.1.4: device descriptor read/64, error -32
10981 13:23:23.448034 <6>[ 8.045148] usb 1-1.1-port4: attempt power cycle
10982 13:23:23.535360 <6>[ 8.128669] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10983 13:23:24.058294 <6>[ 8.652655] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10984 13:23:24.065138 <4>[ 8.660062] usb 1-1.1.4: Device not responding to setup address.
10985 13:23:24.275437 <4>[ 8.872799] usb 1-1.1.4: Device not responding to setup address.
10986 13:23:24.488075 <3>[ 9.084748] usb 1-1.1.4: device not accepting address 10, error -71
10987 13:23:24.574826 <6>[ 9.168676] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10988 13:23:24.580888 <4>[ 9.176084] usb 1-1.1.4: Device not responding to setup address.
10989 13:23:24.791696 <4>[ 9.388917] usb 1-1.1.4: Device not responding to setup address.
10990 13:23:25.003409 <3>[ 9.600666] usb 1-1.1.4: device not accepting address 11, error -71
10991 13:23:25.010118 <3>[ 9.607692] usb 1-1.1-port4: unable to enumerate USB device
10992 13:23:33.372629 <6>[ 17.973653] ALSA device list:
10993 13:23:33.380038 <6>[ 17.976947] No soundcards found.
10994 13:23:33.386708 <6>[ 17.984924] Freeing unused kernel memory: 8384K
10995 13:23:33.390379 <6>[ 17.990005] Run /init as init process
10996 13:23:33.438822 <6>[ 18.036573] NET: Registered PF_INET6 protocol family
10997 13:23:33.445333 <6>[ 18.042821] Segment Routing with IPv6
10998 13:23:33.447978 <6>[ 18.046774] In-situ OAM (IOAM) with IPv6
10999 13:23:33.484195 <30>[ 18.061239] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
11000 13:23:33.486405 <30>[ 18.085065] systemd[1]: Detected architecture arm64.
11001 13:23:33.489523
11002 13:23:33.493154 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
11003 13:23:33.493715
11004 13:23:33.506407 <30>[ 18.104653] systemd[1]: Set hostname to <debian-bullseye-arm64>.
11005 13:23:33.662166 <30>[ 18.256974] systemd[1]: Queued start job for default target Graphical Interface.
11006 13:23:33.699354 <30>[ 18.297320] systemd[1]: Created slice system-getty.slice.
11007 13:23:33.705998 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
11008 13:23:33.723086 <30>[ 18.321158] systemd[1]: Created slice system-modprobe.slice.
11009 13:23:33.729411 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
11010 13:23:33.748040 <30>[ 18.345858] systemd[1]: Created slice system-serial\x2dgetty.slice.
11011 13:23:33.757731 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
11012 13:23:33.771269 <30>[ 18.369128] systemd[1]: Created slice User and Session Slice.
11013 13:23:33.777731 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
11014 13:23:33.798256 <30>[ 18.393312] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
11015 13:23:33.808356 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
11016 13:23:33.826425 <30>[ 18.421331] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
11017 13:23:33.833026 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
11018 13:23:33.857569 <30>[ 18.449110] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
11019 13:23:33.864613 <30>[ 18.461347] systemd[1]: Reached target Local Encrypted Volumes.
11020 13:23:33.870768 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
11021 13:23:33.887579 <30>[ 18.485082] systemd[1]: Reached target Paths.
11022 13:23:33.890772 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
11023 13:23:33.906416 <30>[ 18.504620] systemd[1]: Reached target Remote File Systems.
11024 13:23:33.912894 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
11025 13:23:33.926713 <30>[ 18.524580] systemd[1]: Reached target Slices.
11026 13:23:33.929727 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
11027 13:23:33.946233 <30>[ 18.544630] systemd[1]: Reached target Swap.
11028 13:23:33.949670 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
11029 13:23:33.970349 <30>[ 18.565085] systemd[1]: Listening on initctl Compatibility Named Pipe.
11030 13:23:33.976691 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
11031 13:23:33.992709 <30>[ 18.590064] systemd[1]: Listening on Journal Audit Socket.
11032 13:23:33.998579 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
11033 13:23:34.014946 <30>[ 18.613147] systemd[1]: Listening on Journal Socket (/dev/log).
11034 13:23:34.021940 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
11035 13:23:34.040010 <30>[ 18.637825] systemd[1]: Listening on Journal Socket.
11036 13:23:34.046361 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
11037 13:23:34.059087 <30>[ 18.657165] systemd[1]: Listening on udev Control Socket.
11038 13:23:34.065657 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
11039 13:23:34.083406 <30>[ 18.681625] systemd[1]: Listening on udev Kernel Socket.
11040 13:23:34.090078 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
11041 13:23:34.146701 <30>[ 18.744858] systemd[1]: Mounting Huge Pages File System...
11042 13:23:34.153044 Mounting [0;1;39mHuge Pages File System[0m...
11043 13:23:34.169102 <30>[ 18.766591] systemd[1]: Mounting POSIX Message Queue File System...
11044 13:23:34.175263 Mounting [0;1;39mPOSIX Message Queue File System[0m...
11045 13:23:34.196846 <30>[ 18.795242] systemd[1]: Mounting Kernel Debug File System...
11046 13:23:34.203520 Mounting [0;1;39mKernel Debug File System[0m...
11047 13:23:34.222422 <30>[ 18.817096] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
11048 13:23:34.234727 <30>[ 18.829744] systemd[1]: Starting Create list of static device nodes for the current kernel...
11049 13:23:34.241365 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
11050 13:23:34.263113 <30>[ 18.861367] systemd[1]: Starting Load Kernel Module configfs...
11051 13:23:34.270190 Starting [0;1;39mLoad Kernel Module configfs[0m...
11052 13:23:34.287434 <30>[ 18.885255] systemd[1]: Starting Load Kernel Module drm...
11053 13:23:34.293679 Starting [0;1;39mLoad Kernel Module drm[0m...
11054 13:23:34.310244 <30>[ 18.904983] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
11055 13:23:34.325197 <30>[ 18.922875] systemd[1]: Starting Journal Service...
11056 13:23:34.331514 Starting [0;1;39mJournal Service[0m...
11057 13:23:34.352472 <30>[ 18.950538] systemd[1]: Starting Load Kernel Modules...
11058 13:23:34.359029 Starting [0;1;39mLoad Kernel Modules[0m...
11059 13:23:34.382555 <30>[ 18.977559] systemd[1]: Starting Remount Root and Kernel File Systems...
11060 13:23:34.389517 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
11061 13:23:34.407589 <30>[ 19.005591] systemd[1]: Starting Coldplug All udev Devices...
11062 13:23:34.413863 Starting [0;1;39mColdplug All udev Devices[0m...
11063 13:23:34.429588 <30>[ 19.027609] systemd[1]: Started Journal Service.
11064 13:23:34.436110 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11065 13:23:34.452702 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
11066 13:23:34.472498 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11067 13:23:34.487392 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11068 13:23:34.507757 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11069 13:23:34.525759 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11070 13:23:34.544650 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11071 13:23:34.560247 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11072 13:23:34.580270 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11073 13:23:34.595142 See 'systemctl status systemd-remount-fs.service' for details.
11074 13:23:34.667583 Mounting [0;1;39mKernel Configuration File System[0m...
11075 13:23:34.685968 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11076 13:23:34.699631 <46>[ 19.294471] systemd-journald[181]: Received client request to flush runtime journal.
11077 13:23:34.712106 Starting [0;1;39mLoad/Save Random Seed[0m...
11078 13:23:34.731600 Starting [0;1;39mApply Kernel Variables[0m...
11079 13:23:34.755260 Starting [0;1;39mCreate System Users[0m...
11080 13:23:34.777633 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11081 13:23:34.799498 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11082 13:23:34.823471 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11083 13:23:34.840165 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11084 13:23:34.860070 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11085 13:23:34.876635 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11086 13:23:34.915107 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11087 13:23:34.941374 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11088 13:23:34.954699 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11089 13:23:34.975049 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11090 13:23:35.010736 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11091 13:23:35.039211 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11092 13:23:35.059402 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11093 13:23:35.081939 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11094 13:23:35.128167 Starting [0;1;39mNetwork Time Synchronization[0m...
11095 13:23:35.148304 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11096 13:23:35.204563 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11097 13:23:35.225472 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11098 13:23:35.237231 <6>[ 19.832168] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11099 13:23:35.260982 [[0;32m OK [0m] Found device<6>[ 19.857551] remoteproc remoteproc0: scp is available
11100 13:23:35.267550 [0;1;39m/dev/t<6>[ 19.863835] remoteproc remoteproc0: powering up scp
11101 13:23:35.268021 tyS0[0m.
11102 13:23:35.274004 <6>[ 19.864666] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11103 13:23:35.283802 <6>[ 19.870482] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11104 13:23:35.293890 <6>[ 19.878938] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11105 13:23:35.300252 <4>[ 19.887459] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11106 13:23:35.307193 <6>[ 19.887535] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11107 13:23:35.313864 <6>[ 19.904263] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11108 13:23:35.323917 [[0;32m OK [<4>[ 19.919284] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11109 13:23:35.329944 0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11110 13:23:35.343504 <3>[ 19.938386] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11111 13:23:35.353766 <3>[ 19.946988] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11112 13:23:35.360233 <3>[ 19.955139] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11113 13:23:35.363248 <6>[ 19.958804] mc: Linux media interface: v0.10
11114 13:23:35.372922 <3>[ 19.959905] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11115 13:23:35.379969 <3>[ 19.959918] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11116 13:23:35.389858 <3>[ 19.959922] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11117 13:23:35.399648 [[0;32m OK [<3>[ 19.959928] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11118 13:23:35.409343 0m] Reached targ<3>[ 19.959932] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11119 13:23:35.416246 et [0;1;39mSyst<6>[ 19.962721] usbcore: registered new interface driver r8152
11120 13:23:35.425698 em Time Set[0m.<6>[ 19.965030] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11121 13:23:35.426120
11122 13:23:35.435713 <3>[ 19.968222] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11123 13:23:35.446066 <6>[ 19.992873] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11124 13:23:35.452523 <3>[ 20.011284] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11125 13:23:35.462453 <6>[ 20.013222] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11126 13:23:35.468849 <6>[ 20.013231] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11127 13:23:35.475330 <6>[ 20.013235] remoteproc remoteproc0: remote processor scp is now up
11128 13:23:35.478990 <6>[ 20.016656] videodev: Linux video capture interface: v2.00
11129 13:23:35.488351 <6>[ 20.020893] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11130 13:23:35.494982 <3>[ 20.029917] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11131 13:23:35.505096 <3>[ 20.029936] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11132 13:23:35.511813 <3>[ 20.030038] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11133 13:23:35.521300 <3>[ 20.030043] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11134 13:23:35.528474 <3>[ 20.030046] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11135 13:23:35.537844 <3>[ 20.030056] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11136 13:23:35.544578 <3>[ 20.030059] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11137 13:23:35.551354 <3>[ 20.030097] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11138 13:23:35.561030 <6>[ 20.045776] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11139 13:23:35.567990 <6>[ 20.052001] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11140 13:23:35.574770 <6>[ 20.056223] pci_bus 0000:00: root bus resource [bus 00-ff]
11141 13:23:35.581021 <6>[ 20.060764] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
11142 13:23:35.587595 <6>[ 20.119410] usbcore: registered new interface driver cdc_ether
11143 13:23:35.594730 <6>[ 20.123743] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11144 13:23:35.597262 <6>[ 20.125787] Bluetooth: Core ver 2.22
11145 13:23:35.604746 <6>[ 20.125866] NET: Registered PF_BLUETOOTH protocol family
11146 13:23:35.610719 <6>[ 20.125869] Bluetooth: HCI device and connection manager initialized
11147 13:23:35.617801 <6>[ 20.125886] Bluetooth: HCI socket layer initialized
11148 13:23:35.620752 <6>[ 20.125889] Bluetooth: L2CAP socket layer initialized
11149 13:23:35.627329 <6>[ 20.125895] Bluetooth: SCO socket layer initialized
11150 13:23:35.634171 <6>[ 20.150751] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11151 13:23:35.644245 <6>[ 20.156038] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11152 13:23:35.650762 <6>[ 20.160088] usbcore: registered new interface driver r8153_ecm
11153 13:23:35.660625 <4>[ 20.173687] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11154 13:23:35.670544 <6>[ 20.174519] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11155 13:23:35.676516 <6>[ 20.174695] usbcore: registered new interface driver uvcvideo
11156 13:23:35.683331 <6>[ 20.178044] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11157 13:23:35.693289 <4>[ 20.185277] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11158 13:23:35.700061 <6>[ 20.186520] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11159 13:23:35.703312 <6>[ 20.187042] usbcore: registered new interface driver btusb
11160 13:23:35.716723 <4>[ 20.187222] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11161 13:23:35.719592 <3>[ 20.187233] Bluetooth: hci0: Failed to load firmware file (-2)
11162 13:23:35.726211 <3>[ 20.187238] Bluetooth: hci0: Failed to set up firmware (-2)
11163 13:23:35.735973 <4>[ 20.187243] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11164 13:23:35.745870 <6>[ 20.191375] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11165 13:23:35.752914 <6>[ 20.199883] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11166 13:23:35.755667 <6>[ 20.202388] pci 0000:00:00.0: supports D1 D2
11167 13:23:35.766035 <6>[ 20.202390] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11168 13:23:35.772675 <6>[ 20.203497] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11169 13:23:35.782183 <6>[ 20.210486] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11170 13:23:35.785628 <6>[ 20.214853] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11171 13:23:35.792762 <6>[ 20.248642] r8152 1-1.1.1:1.0 eth0: v1.12.13
11172 13:23:35.799007 <6>[ 20.253217] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11173 13:23:35.805241 <6>[ 20.278501] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
11174 13:23:35.812233 <6>[ 20.280823] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11175 13:23:35.818485 <6>[ 20.415982] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11176 13:23:35.825814 <6>[ 20.416104] pci 0000:01:00.0: supports D1 D2
11177 13:23:35.832005 <6>[ 20.428031] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11178 13:23:35.838448 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11179 13:23:35.853867 <6>[ 20.448554] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11180 13:23:35.860066 <6>[ 20.455606] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11181 13:23:35.870074 <4>[ 20.463608] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11182 13:23:35.873216 <4>[ 20.463608] Fallback method does not support PEC.
11183 13:23:35.883069 <6>[ 20.463699] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11184 13:23:35.890569 <6>[ 20.485316] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11185 13:23:35.897171 <6>[ 20.493318] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11186 13:23:35.904886 <6>[ 20.501319] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11187 13:23:35.912027 <6>[ 20.509321] pci 0000:00:00.0: PCI bridge to [bus 01]
11188 13:23:35.918245 <3>[ 20.509665] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11189 13:23:35.929081 <3>[ 20.510435] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11190 13:23:35.935485 <6>[ 20.514537] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11191 13:23:35.942866 <6>[ 20.514684] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11192 13:23:35.949466 <3>[ 20.525967] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11193 13:23:35.959362 <3>[ 20.527762] power_supply sbs-5-000b: driver failed to report `status' property: -6
11194 13:23:35.966489 <6>[ 20.531483] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11195 13:23:35.972990 <3>[ 20.546858] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11196 13:23:35.979094 <6>[ 20.554449] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11197 13:23:35.992906 <3>[ 20.588007] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11198 13:23:36.007215 Starting [0;1;39mLoad/Save Screen …o<5>[ 20.602415] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11199 13:23:36.010205 f leds:white:kbd_backlight[0m...
11200 13:23:36.023246 <5>[ 20.618356] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11201 13:23:36.030758 <4>[ 20.625456] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11202 13:23:36.039988 <3>[ 20.629961] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11203 13:23:36.043022 <6>[ 20.634382] cfg80211: failed to load regulatory.db
11204 13:23:36.053399 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11205 13:23:36.076173 <3>[ 20.670804] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11206 13:23:36.112363 <3>[ 20.707522] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11207 13:23:36.118939 <6>[ 20.710146] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11208 13:23:36.125712 <6>[ 20.724018] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11209 13:23:36.153220 <3>[ 20.748277] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11210 13:23:36.159844 <6>[ 20.750693] mt7921e 0000:01:00.0: ASIC revision: 79610010
11211 13:23:36.195344 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11212 13:23:36.209971 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11213 13:23:36.227488 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11214 13:23:36.245725 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11215 13:23:36.266836 [[0;32m OK [<4>[ 20.858409] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11216 13:23:36.269472 0m] Reached target [0;1;39mTimers[0m.
11217 13:23:36.290457 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11218 13:23:36.306146 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11219 13:23:36.326393 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11220 13:23:36.350533 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11221 13:23:36.385810 <4>[ 20.977198] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11222 13:23:36.408153 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11223 13:23:36.459376 Starting [0;1;39mUser Login Management[0m...
11224 13:23:36.480430 Starting [0;1;39mPermit User Sessions[0m...
11225 13:23:36.501011 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11226 13:23:36.513745 <4>[ 21.105340] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11227 13:23:36.536411 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11228 13:23:36.560189 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11229 13:23:36.578941 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11230 13:23:36.602713 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11231 13:23:36.620397 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11232 13:23:36.643613 [[0;32m OK [<4>[ 21.235004] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11233 13:23:36.650039 0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11234 13:23:36.669082 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11235 13:23:36.687091 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11236 13:23:36.730792 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11237 13:23:36.766470 <4>[ 21.358068] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11238 13:23:36.772870 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11239 13:23:36.815027
11240 13:23:36.815546
11241 13:23:36.818006 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11242 13:23:36.818468
11243 13:23:36.821486 debian-bullseye-arm64 login: root (automatic login)
11244 13:23:36.822070
11245 13:23:36.822446
11246 13:23:36.838220 Linux debian-bullseye-arm64 6.1.46-cip4 #1 SMP PREEMPT Wed Sep 6 13:11:19 UTC 2023 aarch64
11247 13:23:36.838856
11248 13:23:36.845373 The programs included with the Debian GNU/Linux system are free software;
11249 13:23:36.851443 the exact distribution terms for each program are described in the
11250 13:23:36.854436 individual files in /usr/share/doc/*/copyright.
11251 13:23:36.854939
11252 13:23:36.861937 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11253 13:23:36.864555 permitted by applicable law.
11254 13:23:36.865729 Matched prompt #10: / #
11256 13:23:36.866890 Setting prompt string to ['/ #']
11257 13:23:36.867363 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11259 13:23:36.868530 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11260 13:23:36.869013 start: 2.2.6 expect-shell-connection (timeout 00:03:03) [common]
11261 13:23:36.869411 Setting prompt string to ['/ #']
11262 13:23:36.869752 Forcing a shell prompt, looking for ['/ #']
11264 13:23:36.920573 / #
11265 13:23:36.921228 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11266 13:23:36.921658 Waiting using forced prompt support (timeout 00:02:30)
11267 13:23:36.922168 <4>[ 21.475868] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11268 13:23:36.926711
11269 13:23:36.927547 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11270 13:23:36.928083 start: 2.2.7 export-device-env (timeout 00:03:03) [common]
11271 13:23:36.928610 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11272 13:23:36.929130 end: 2.2 depthcharge-retry (duration 00:01:57) [common]
11273 13:23:36.929645 end: 2 depthcharge-action (duration 00:01:57) [common]
11274 13:23:36.930124 start: 3 lava-test-retry (timeout 00:05:00) [common]
11275 13:23:36.930654 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11276 13:23:36.931085 Using namespace: common
11278 13:23:37.032332 / # #
11279 13:23:37.032941 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11280 13:23:37.033509 #<4>[ 21.597145] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11281 13:23:37.038408
11282 13:23:37.039268 Using /lava-11445605
11284 13:23:37.140583 / # export SHELL=/bin/sh
11285 13:23:37.141360 export SHELL=/bin/sh<4>[ 21.715680] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11286 13:23:37.147226
11288 13:23:37.248748 / # . /lava-11445605/environment
11289 13:23:37.249720 . /lava-11445605/environment<4>[ 21.837085] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11290 13:23:37.255619
11292 13:23:37.357095 / # /lava-11445605/bin/lava-test-runner /lava-11445605/0
11293 13:23:37.357745 Test shell timeout: 10s (minimum of the action and connection timeout)
11294 13:23:37.369667 /lava-11445605/bin/lava-test-runner /lava-11445605/0<4>[ 21.961363] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11295 13:23:37.370287
11296 13:23:37.400191 + export TESTRUN_ID=0_sleep
11297 13:23:37.403598 + cd /lava-11445605/0/tests/0_sleep
11298 13:23:37.406615 + cat uuid
11299 13:23:37.407092 + UUID=11445605_1.5.2.3.1
11300 13:23:37.409555 + set +x
11301 13:23:37.413146 <LAVA_SIGNAL_STARTRUN 0_sleep 11445605_1.5.2.3.1>
11302 13:23:37.413909 Received signal: <STARTRUN> 0_sleep 11445605_1.5.2.3.1
11303 13:23:37.414354 Starting test lava.0_sleep (11445605_1.5.2.3.1)
11304 13:23:37.414851 Skipping test definition patterns.
11305 13:23:37.416259 + ./config/lava/sleep/sleep.sh mem freeze
11306 13:23:37.419916 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11308 13:23:37.422948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11309 13:23:37.426387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11310 13:23:37.427149 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11312 13:23:37.429490 rtcwake: assuming RTC uses UTC ...
11313 13:23:37.436041 rtcwake: wakeup from "mem" u<6>[ 22.035812] PM: suspend entry (deep)
11314 13:23:37.442672 sing rtc0 at Wed<6>[ 22.040452] Filesystems sync: 0.000 seconds
11315 13:23:37.449491 Sep 6 13:23:47<6>[ 22.047330] Freezing user space processes
11316 13:23:37.449984 2023
11317 13:23:37.456456 <6>[ 22.053603] Freezing user space processes completed (elapsed 0.001 seconds)
11318 13:23:37.462538 <6>[ 22.061022] OOM killer disabled.
11319 13:23:37.465891 <6>[ 22.064518] Freezing remaining freezable tasks
11320 13:23:37.475558 <6>[ 22.070827] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11321 13:23:37.482210 <6>[ 22.078520] printk: Suspending console(s) (use no_console_suspend to debug)
11322 13:23:37.488730 <3>[ 22.081072] mt7921e 0000:01:00.0: hardware init failed
11323 13:23:40.838940 <3>[ 25.172739] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11324 13:23:40.848776 <3>[ 25.172789] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11325 13:23:40.858979 <3>[ 25.172833] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11326 13:23:40.865596 <3>[ 25.172871] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11327 13:23:40.875960 <3>[ 25.173373] PM: Some devices failed to suspend, or early wake event detected
11328 13:23:40.882033 <4>[ 25.189892] typec port0-partner: PM: parent port0 should not be sleeping
11329 13:23:40.888715 <4>[ 25.207504] typec port0-cable: PM: parent port0 should not be sleeping
11330 13:23:40.892030 <6>[ 25.491896] OOM killer enabled.
11331 13:23:40.898837 <6>[ 25.495305] Restarting tasks ... done.
11332 13:23:40.902325 <5>[ 25.501422] random: crng reseeded on system resumption
11333 13:23:40.905902 <6>[ 25.508323] PM: suspend exit
11334 13:23:40.909008 rtcwake: write error
11335 13:23:40.916419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11336 13:23:40.917036 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11338 13:23:40.919596 rtcwake: assuming RTC uses UTC ...
11339 13:23:40.926310 rtcwake: wakeup from "mem" using rtc0 at Wed Sep 6 13:23:50 2023
11340 13:23:40.940089 <6>[ 25.539046] PM: suspend entry (deep)
11341 13:23:40.943508 <6>[ 25.542941] Filesystems sync: 0.000 seconds
11342 13:23:40.950029 <6>[ 25.548144] Freezing user space processes
11343 13:23:40.956204 <6>[ 25.554327] Freezing user space processes completed (elapsed 0.001 seconds)
11344 13:23:40.959875 <6>[ 25.561620] OOM killer disabled.
11345 13:23:40.966554 <6>[ 25.565110] Freezing remaining freezable tasks
11346 13:23:40.980242 <6>[ 25.576437] usb 1-1.1.4: new full-speed USB device number 12 using xhci-mtk
11347 13:23:41.061267 <3>[ 25.660577] usb 1-1.1.4: device descriptor read/64, error -32
11348 13:23:41.253714 <3>[ 25.852723] usb 1-1.1.4: device descriptor read/64, error -32
11349 13:23:41.448789 <6>[ 26.044532] usb 1-1.1.4: new full-speed USB device number 13 using xhci-mtk
11350 13:23:41.529816 <3>[ 26.128581] usb 1-1.1.4: device descriptor read/64, error -32
11351 13:23:41.721578 <3>[ 26.320744] usb 1-1.1.4: device descriptor read/64, error -32
11352 13:23:41.833940 <6>[ 26.432922] usb 1-1.1-port4: attempt power cycle
11353 13:23:42.444664 <6>[ 27.040675] usb 1-1.1.4: new full-speed USB device number 14 using xhci-mtk
11354 13:23:42.451291 <4>[ 27.048064] usb 1-1.1.4: Device not responding to setup address.
11355 13:23:42.661595 <4>[ 27.260823] usb 1-1.1.4: Device not responding to setup address.
11356 13:23:42.873500 <3>[ 27.472508] usb 1-1.1.4: device not accepting address 14, error -71
11357 13:23:42.960816 <6>[ 27.556540] usb 1-1.1.4: new full-speed USB device number 15 using xhci-mtk
11358 13:23:42.967389 <4>[ 27.563917] usb 1-1.1.4: Device not responding to setup address.
11359 13:23:43.177482 <4>[ 27.776708] usb 1-1.1.4: Device not responding to setup address.
11360 13:23:43.389048 <3>[ 27.988563] usb 1-1.1.4: device not accepting address 15, error -71
11361 13:23:43.395819 <3>[ 27.995405] usb 1-1.1-port4: unable to enumerate USB device
11362 13:23:43.407414 <6>[ 28.003605] Freezing remaining freezable tasks completed (elapsed 2.433 seconds)
11363 13:23:43.414158 <6>[ 28.011296] printk: Suspending console(s) (use no_console_suspend to debug)
11364 13:23:46.730968 <3>[ 31.060693] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11365 13:23:46.740776 <3>[ 31.060724] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11366 13:23:46.750920 <3>[ 31.060771] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11367 13:23:46.757112 <3>[ 31.060812] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11368 13:23:46.767160 <3>[ 31.061061] PM: Some devices failed to suspend, or early wake event detected
11369 13:23:46.770850 <6>[ 31.370814] OOM killer enabled.
11370 13:23:46.774130 <6>[ 31.374227] Restarting tasks ... done.
11371 13:23:46.780570 <5>[ 31.380563] random: crng reseeded on system resumption
11372 13:23:46.784425 <6>[ 31.387677] PM: suspend exit
11373 13:23:46.787356 rtcwake: write error
11374 13:23:46.795694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11375 13:23:46.795961 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11377 13:23:46.798850 rtcwake: assuming RTC uses UTC ...
11378 13:23:46.805363 rtcwake: wakeup from "mem" using rtc0 at Wed Sep 6 13:23:56 2023
11379 13:23:46.817674 <6>[ 31.417869] PM: suspend entry (deep)
11380 13:23:46.820939 <6>[ 31.421791] Filesystems sync: 0.000 seconds
11381 13:23:46.824586 <6>[ 31.426840] Freezing user space processes
11382 13:23:46.835744 <6>[ 31.432474] Freezing user space processes completed (elapsed 0.001 seconds)
11383 13:23:46.839129 <6>[ 31.439691] OOM killer disabled.
11384 13:23:46.842231 <6>[ 31.443178] Freezing remaining freezable tasks
11385 13:23:46.859625 <6>[ 31.456539] usb 1-1.1.4: new full-speed USB device number 16 using xhci-mtk
11386 13:23:46.940455 <3>[ 31.540529] usb 1-1.1.4: device descriptor read/64, error -32
11387 13:23:47.132876 <3>[ 31.732730] usb 1-1.1.4: device descriptor read/64, error -32
11388 13:23:47.327985 <6>[ 31.924685] usb 1-1.1.4: new full-speed USB device number 17 using xhci-mtk
11389 13:23:47.412602 <3>[ 32.012761] usb 1-1.1.4: device descriptor read/64, error -32
11390 13:23:47.604883 <3>[ 32.204715] usb 1-1.1.4: device descriptor read/64, error -32
11391 13:23:47.717018 <6>[ 32.316919] usb 1-1.1-port4: attempt power cycle
11392 13:23:48.328072 <6>[ 32.924677] usb 1-1.1.4: new full-speed USB device number 18 using xhci-mtk
11393 13:23:48.334765 <4>[ 32.932056] usb 1-1.1.4: Device not responding to setup address.
11394 13:23:48.544851 <4>[ 33.144796] usb 1-1.1.4: Device not responding to setup address.
11395 13:23:48.756827 <3>[ 33.356668] usb 1-1.1.4: device not accepting address 18, error -71
11396 13:23:48.843940 <6>[ 33.440515] usb 1-1.1.4: new full-speed USB device number 19 using xhci-mtk
11397 13:23:48.850927 <4>[ 33.447886] usb 1-1.1.4: Device not responding to setup address.
11398 13:23:49.060601 <4>[ 33.660719] usb 1-1.1.4: Device not responding to setup address.
11399 13:23:49.272497 <3>[ 33.872531] usb 1-1.1.4: device not accepting address 19, error -71
11400 13:23:49.279289 <3>[ 33.879400] usb 1-1.1-port4: unable to enumerate USB device
11401 13:23:49.290703 <6>[ 33.887249] Freezing remaining freezable tasks completed (elapsed 2.439 seconds)
11402 13:23:49.297241 <6>[ 33.894940] printk: Suspending console(s) (use no_console_suspend to debug)
11403 13:23:52.622375 <3>[ 36.948684] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11404 13:23:52.632397 <3>[ 36.948716] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11405 13:23:52.642524 <3>[ 36.948762] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11406 13:23:52.648541 <3>[ 36.948808] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11407 13:23:52.659115 <3>[ 36.949077] PM: Some devices failed to suspend, or early wake event detected
11408 13:23:52.661619 <6>[ 37.262877] OOM killer enabled.
11409 13:23:52.668670 <6>[ 37.266290] Restarting tasks ... done.
11410 13:23:52.675130 <5>[ 37.273872] random: crng reseeded on system resumption
11411 13:23:52.678281 <6>[ 37.281742] PM: suspend exit
11412 13:23:52.681938 rtcwake: write error
11413 13:23:52.688448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11414 13:23:52.688719 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11416 13:23:52.691548 rtcwake: assuming RTC uses UTC ...
11417 13:23:52.698187 rtcwake: wakeup from "mem" using rtc0 at Wed Sep 6 13:24:02 2023
11418 13:23:52.710851 <6>[ 37.311640] PM: suspend entry (deep)
11419 13:23:52.714511 <6>[ 37.315534] Filesystems sync: 0.000 seconds
11420 13:23:52.720917 <6>[ 37.320607] Freezing user space processes
11421 13:23:52.727696 <6>[ 37.326572] Freezing user space processes completed (elapsed 0.001 seconds)
11422 13:23:52.730901 <6>[ 37.333823] OOM killer disabled.
11423 13:23:52.737103 <6>[ 37.337306] Freezing remaining freezable tasks
11424 13:23:52.751053 <6>[ 37.348568] usb 1-1.1.4: new full-speed USB device number 20 using xhci-mtk
11425 13:23:52.836024 <3>[ 37.436676] usb 1-1.1.4: device descriptor read/64, error -32
11426 13:23:53.028125 <3>[ 37.628588] usb 1-1.1.4: device descriptor read/64, error -32
11427 13:23:53.223174 <6>[ 37.820686] usb 1-1.1.4: new full-speed USB device number 21 using xhci-mtk
11428 13:23:53.307808 <3>[ 37.908579] usb 1-1.1.4: device descriptor read/64, error -32
11429 13:23:53.499814 <3>[ 38.100712] usb 1-1.1.4: device descriptor read/64, error -32
11430 13:23:53.612515 <6>[ 38.212920] usb 1-1.1-port4: attempt power cycle
11431 13:23:54.223625 <6>[ 38.820676] usb 1-1.1.4: new full-speed USB device number 22 using xhci-mtk
11432 13:23:54.229711 <4>[ 38.828064] usb 1-1.1.4: Device not responding to setup address.
11433 13:23:54.440090 <4>[ 39.040839] usb 1-1.1.4: Device not responding to setup address.
11434 13:23:54.651922 <3>[ 39.252666] usb 1-1.1.4: device not accepting address 22, error -71
11435 13:23:54.739141 <6>[ 39.336673] usb 1-1.1.4: new full-speed USB device number 23 using xhci-mtk
11436 13:23:54.745685 <4>[ 39.344054] usb 1-1.1.4: Device not responding to setup address.
11437 13:23:54.955964 <4>[ 39.556699] usb 1-1.1.4: Device not responding to setup address.
11438 13:23:55.167626 <3>[ 39.768531] usb 1-1.1.4: device not accepting address 23, error -71
11439 13:23:55.174346 <3>[ 39.775376] usb 1-1.1-port4: unable to enumerate USB device
11440 13:23:55.186575 <6>[ 39.784146] Freezing remaining freezable tasks completed (elapsed 2.442 seconds)
11441 13:23:55.193216 <6>[ 39.791837] printk: Suspending console(s) (use no_console_suspend to debug)
11442 13:23:58.505166 <3>[ 42.836563] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11443 13:23:58.515445 <3>[ 42.836596] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11444 13:23:58.525451 <3>[ 42.836643] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11445 13:23:58.532228 <3>[ 42.836683] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11446 13:23:58.542006 <3>[ 42.836930] PM: Some devices failed to suspend, or early wake event detected
11447 13:23:58.544887 <6>[ 43.146651] OOM killer enabled.
11448 13:23:58.551942 <6>[ 43.150064] Restarting tasks ... done.
11449 13:23:58.555101 <5>[ 43.156562] random: crng reseeded on system resumption
11450 13:23:58.558876 <6>[ 43.163450] PM: suspend exit
11451 13:23:58.562282 rtcwake: write error
11452 13:23:58.569028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11453 13:23:58.569284 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11455 13:23:58.572354 rtcwake: assuming RTC uses UTC ...
11456 13:23:58.578962 rtcwake: wakeup from "mem" using rtc0 at Wed Sep 6 13:24:08 2023
11457 13:23:58.591008 <6>[ 43.192646] PM: suspend entry (deep)
11458 13:23:58.594589 <6>[ 43.196537] Filesystems sync: 0.000 seconds
11459 13:23:58.597925 <6>[ 43.201544] Freezing user space processes
11460 13:23:58.609418 <6>[ 43.207505] Freezing user space processes completed (elapsed 0.001 seconds)
11461 13:23:58.612656 <6>[ 43.214757] OOM killer disabled.
11462 13:23:58.616139 <6>[ 43.218239] Freezing remaining freezable tasks
11463 13:23:58.650319 <6>[ 43.248602] usb 1-1.1.4: new full-speed USB device number 24 using xhci-mtk
11464 13:23:58.730886 <3>[ 43.332541] usb 1-1.1.4: device descriptor read/64, error -32
11465 13:23:58.923723 <3>[ 43.524742] usb 1-1.1.4: device descriptor read/64, error -32
11466 13:23:59.118800 <6>[ 43.716541] usb 1-1.1.4: new full-speed USB device number 25 using xhci-mtk
11467 13:23:59.202879 <3>[ 43.804570] usb 1-1.1.4: device descriptor read/64, error -32
11468 13:23:59.395437 <3>[ 43.996943] usb 1-1.1.4: device descriptor read/64, error -32
11469 13:23:59.507504 <6>[ 44.108764] usb 1-1.1-port4: attempt power cycle
11470 13:24:00.118799 <6>[ 44.716676] usb 1-1.1.4: new full-speed USB device number 26 using xhci-mtk
11471 13:24:00.125165 <4>[ 44.724055] usb 1-1.1.4: Device not responding to setup address.
11472 13:24:00.334904 <4>[ 44.936706] usb 1-1.1.4: Device not responding to setup address.
11473 13:24:00.547337 <3>[ 45.148677] usb 1-1.1.4: device not accepting address 26, error -71
11474 13:24:00.634275 <6>[ 45.232553] usb 1-1.1.4: new full-speed USB device number 27 using xhci-mtk
11475 13:24:00.640606 <4>[ 45.239938] usb 1-1.1.4: Device not responding to setup address.
11476 13:24:00.851398 <4>[ 45.452788] usb 1-1.1.4: Device not responding to setup address.
11477 13:24:01.063119 <3>[ 45.664683] usb 1-1.1.4: device not accepting address 27, error -71
11478 13:24:01.069705 <3>[ 45.671523] usb 1-1.1-port4: unable to enumerate USB device
11479 13:24:01.082028 <6>[ 45.680648] Freezing remaining freezable tasks completed (elapsed 2.457 seconds)
11480 13:24:01.088869 <6>[ 45.688385] printk: Suspending console(s) (use no_console_suspend to debug)
11481 13:24:04.393251 <6>[ 48.212954] vpu: disabling
11482 13:24:04.397010 <6>[ 48.213080] vproc2: disabling
11483 13:24:04.400172 <6>[ 48.213136] vproc1: disabling
11484 13:24:04.403953 <6>[ 48.213192] vaud18: disabling
11485 13:24:04.406764 <6>[ 48.213444] vsram_others: disabling
11486 13:24:04.409884 <6>[ 48.213650] va09: disabling
11487 13:24:04.413272 <6>[ 48.213729] vsram_md: disabling
11488 13:24:04.416397 <6>[ 48.213860] Vgpu: disabling
11489 13:24:04.423194 <3>[ 48.724683] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11490 13:24:04.433126 <3>[ 48.724716] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11491 13:24:04.442962 <3>[ 48.724761] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11492 13:24:04.449909 <3>[ 48.724805] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11493 13:24:04.456718 <3>[ 48.725055] PM: Some devices failed to suspend, or early wake event detected
11494 13:24:04.459983 <6>[ 49.064611] OOM killer enabled.
11495 13:24:04.468329 <6>[ 49.068011] Restarting tasks ... done.
11496 13:24:04.471300 <5>[ 49.073809] random: crng reseeded on system resumption
11497 13:24:04.475045 <6>[ 49.080566] PM: suspend exit
11498 13:24:04.478391 rtcwake: write error
11499 13:24:04.485054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11500 13:24:04.485315 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11502 13:24:04.488191 rtcwake: assuming RTC uses UTC ...
11503 13:24:04.494827 rtcwake: wakeup from "mem" using rtc0 at Wed Sep 6 13:24:14 2023
11504 13:24:04.507586 <6>[ 49.109648] PM: suspend entry (deep)
11505 13:24:04.510702 <6>[ 49.113545] Filesystems sync: 0.000 seconds
11506 13:24:04.514003 <6>[ 49.118598] Freezing user space processes
11507 13:24:04.525693 <6>[ 49.124472] Freezing user space processes completed (elapsed 0.001 seconds)
11508 13:24:04.529087 <6>[ 49.131694] OOM killer disabled.
11509 13:24:04.532217 <6>[ 49.135175] Freezing remaining freezable tasks
11510 13:24:04.549826 <6>[ 49.148598] usb 1-1.1.4: new full-speed USB device number 28 using xhci-mtk
11511 13:24:04.630452 <3>[ 49.232450] usb 1-1.1.4: device descriptor read/64, error -32
11512 13:24:04.822626 <3>[ 49.424726] usb 1-1.1.4: device descriptor read/64, error -32
11513 13:24:05.017624 <6>[ 49.616534] usb 1-1.1.4: new full-speed USB device number 29 using xhci-mtk
11514 13:24:05.102385 <3>[ 49.704718] usb 1-1.1.4: device descriptor read/64, error -32
11515 13:24:05.294598 <3>[ 49.896574] usb 1-1.1.4: device descriptor read/64, error -32
11516 13:24:05.406583 <6>[ 50.008955] usb 1-1.1-port4: attempt power cycle
11517 13:24:06.017520 <6>[ 50.616687] usb 1-1.1.4: new full-speed USB device number 30 using xhci-mtk
11518 13:24:06.024138 <4>[ 50.624066] usb 1-1.1.4: Device not responding to setup address.
11519 13:24:06.234095 <4>[ 50.836694] usb 1-1.1.4: Device not responding to setup address.
11520 13:24:06.446316 <3>[ 51.048590] usb 1-1.1.4: device not accepting address 30, error -71
11521 13:24:06.533880 <6>[ 51.132553] usb 1-1.1.4: new full-speed USB device number 31 using xhci-mtk
11522 13:24:06.540121 <4>[ 51.139927] usb 1-1.1.4: Device not responding to setup address.
11523 13:24:06.750542 <4>[ 51.352794] usb 1-1.1.4: Device not responding to setup address.
11524 13:24:06.962301 <3>[ 51.564673] usb 1-1.1.4: device not accepting address 31, error -71
11525 13:24:06.969127 <3>[ 51.571508] usb 1-1.1-port4: unable to enumerate USB device
11526 13:24:06.981602 <6>[ 51.580650] Freezing remaining freezable tasks completed (elapsed 2.440 seconds)
11527 13:24:06.988344 <6>[ 51.588385] printk: Suspending console(s) (use no_console_suspend to debug)
11528 13:24:10.280215 <3>[ 54.612686] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11529 13:24:10.289987 <3>[ 54.612718] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11530 13:24:10.299971 <3>[ 54.612764] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11531 13:24:10.307019 <3>[ 54.612805] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11532 13:24:10.317198 <3>[ 54.613078] PM: Some devices failed to suspend, or early wake event detected
11533 13:24:10.319860 <6>[ 54.922980] OOM killer enabled.
11534 13:24:10.323384 <6>[ 54.926394] Restarting tasks ... done.
11535 13:24:10.329693 <5>[ 54.932634] random: crng reseeded on system resumption
11536 13:24:10.333547 <6>[ 54.939407] PM: suspend exit
11537 13:24:10.336778 rtcwake: write error
11538 13:24:10.343752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11539 13:24:10.344013 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11541 13:24:10.346613 rtcwake: assuming RTC uses UTC ...
11542 13:24:10.353325 rtcwake: wakeup from "mem" using rtc0 at Wed Sep 6 13:24:20 2023
11543 13:24:10.365859 <6>[ 54.968682] PM: suspend entry (deep)
11544 13:24:10.369176 <6>[ 54.972589] Filesystems sync: 0.000 seconds
11545 13:24:10.372627 <6>[ 54.977672] Freezing user space processes
11546 13:24:10.384618 <6>[ 54.983697] Freezing user space processes completed (elapsed 0.001 seconds)
11547 13:24:10.387339 <6>[ 54.990933] OOM killer disabled.
11548 13:24:10.390691 <6>[ 54.994415] Freezing remaining freezable tasks
11549 13:24:10.409022 <6>[ 55.008624] usb 1-1.1.4: new full-speed USB device number 32 using xhci-mtk
11550 13:24:10.493959 <3>[ 55.096674] usb 1-1.1.4: device descriptor read/64, error -32
11551 13:24:10.685757 <3>[ 55.288590] usb 1-1.1.4: device descriptor read/64, error -32
11552 13:24:10.881112 <6>[ 55.480560] usb 1-1.1.4: new full-speed USB device number 33 using xhci-mtk
11553 13:24:10.965440 <3>[ 55.568576] usb 1-1.1.4: device descriptor read/64, error -32
11554 13:24:11.157787 <3>[ 55.760712] usb 1-1.1.4: device descriptor read/64, error -32
11555 13:24:11.270308 <6>[ 55.872802] usb 1-1.1-port4: attempt power cycle
11556 13:24:11.881389 <6>[ 56.480539] usb 1-1.1.4: new full-speed USB device number 34 using xhci-mtk
11557 13:24:11.887653 <4>[ 56.487916] usb 1-1.1.4: Device not responding to setup address.
11558 13:24:12.097969 <4>[ 56.700695] usb 1-1.1.4: Device not responding to setup address.
11559 13:24:12.309861 <3>[ 56.912533] usb 1-1.1.4: device not accepting address 34, error -71
11560 13:24:12.397461 <6>[ 56.996755] usb 1-1.1.4: new full-speed USB device number 35 using xhci-mtk
11561 13:24:12.403860 <4>[ 57.004123] usb 1-1.1.4: Device not responding to setup address.
11562 13:24:12.614251 <4>[ 57.216773] usb 1-1.1.4: Device not responding to setup address.
11563 13:24:12.826341 <3>[ 57.428667] usb 1-1.1.4: device not accepting address 35, error -71
11564 13:24:12.832526 <3>[ 57.435505] usb 1-1.1-port4: unable to enumerate USB device
11565 13:24:12.845370 <6>[ 57.444649] Freezing remaining freezable tasks completed (elapsed 2.445 seconds)
11566 13:24:12.852342 <6>[ 57.452386] printk: Suspending console(s) (use no_console_suspend to debug)
11567 13:24:16.172011 <3>[ 60.500686] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11568 13:24:16.185269 <3>[ 60.500719] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11569 13:24:16.192138 <3>[ 60.500764] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11570 13:24:16.198532 <3>[ 60.500806] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11571 13:24:16.208649 <3>[ 60.501068] PM: Some devices failed to suspend, or early wake event detected
11572 13:24:16.211874 <6>[ 60.815019] OOM killer enabled.
11573 13:24:16.214989 <6>[ 60.818433] Restarting tasks ... done.
11574 13:24:16.221664 <5>[ 60.824555] random: crng reseeded on system resumption
11575 13:24:16.225342 <6>[ 60.831632] PM: suspend exit
11576 13:24:16.228747 rtcwake: write error
11577 13:24:16.235489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11578 13:24:16.236193 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11580 13:24:16.239014 rtcwake: assuming RTC uses UTC ...
11581 13:24:16.245676 rtcwake: wakeup from "mem" using rtc0 at Wed Sep 6 13:24:26 2023
11582 13:24:16.258700 <6>[ 60.860994] PM: suspend entry (deep)
11583 13:24:16.261450 <6>[ 60.864903] Filesystems sync: 0.000 seconds
11584 13:24:16.264848 <6>[ 60.869902] Freezing user space processes
11585 13:24:16.275929 <6>[ 60.875686] Freezing user space processes completed (elapsed 0.001 seconds)
11586 13:24:16.279222 <6>[ 60.882905] OOM killer disabled.
11587 13:24:16.282516 <6>[ 60.886384] Freezing remaining freezable tasks
11588 13:24:16.300851 <6>[ 60.900502] usb 1-1.1.4: new full-speed USB device number 36 using xhci-mtk
11589 13:24:16.381591 <3>[ 60.984541] usb 1-1.1.4: device descriptor read/64, error -32
11590 13:24:16.573639 <3>[ 61.176608] usb 1-1.1.4: device descriptor read/64, error -32
11591 13:24:16.768892 <6>[ 61.368696] usb 1-1.1.4: new full-speed USB device number 37 using xhci-mtk
11592 13:24:16.853891 <3>[ 61.456762] usb 1-1.1.4: device descriptor read/64, error -32
11593 13:24:17.045315 <3>[ 61.648578] usb 1-1.1.4: device descriptor read/64, error -32
11594 13:24:17.157805 <6>[ 61.760925] usb 1-1.1-port4: attempt power cycle
11595 13:24:17.768963 <6>[ 62.368677] usb 1-1.1.4: new full-speed USB device number 38 using xhci-mtk
11596 13:24:17.775632 <4>[ 62.376067] usb 1-1.1.4: Device not responding to setup address.
11597 13:24:17.985602 <4>[ 62.588786] usb 1-1.1.4: Device not responding to setup address.
11598 13:24:18.197440 <3>[ 62.800664] usb 1-1.1.4: device not accepting address 38, error -71
11599 13:24:18.284850 <6>[ 62.884516] usb 1-1.1.4: new full-speed USB device number 39 using xhci-mtk
11600 13:24:18.291013 <4>[ 62.891893] usb 1-1.1.4: Device not responding to setup address.
11601 13:24:18.501626 <4>[ 63.104741] usb 1-1.1.4: Device not responding to setup address.
11602 13:24:18.713123 <3>[ 63.316530] usb 1-1.1.4: device not accepting address 39, error -71
11603 13:24:18.720506 <3>[ 63.323374] usb 1-1.1-port4: unable to enumerate USB device
11604 13:24:18.731534 <6>[ 63.331375] Freezing remaining freezable tasks completed (elapsed 2.440 seconds)
11605 13:24:18.737991 <6>[ 63.339074] printk: Suspending console(s) (use no_console_suspend to debug)
11606 13:24:22.059261 <3>[ 66.388685] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11607 13:24:22.072519 <3>[ 66.388718] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11608 13:24:22.079255 <3>[ 66.388764] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11609 13:24:22.085978 <3>[ 66.388806] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11610 13:24:22.095518 <3>[ 66.389068] PM: Some devices failed to suspend, or early wake event detected
11611 13:24:22.098881 <6>[ 66.702792] OOM killer enabled.
11612 13:24:22.108546 <6>[ 66.706203] Restarting tasks ... done.
11613 13:24:22.111512 <5>[ 66.716169] random: crng reseeded on system resumption
11614 13:24:22.116271 <6>[ 66.722938] PM: suspend exit
11615 13:24:22.119156 rtcwake: write error
11616 13:24:22.126335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11617 13:24:22.127211 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11619 13:24:22.129088 rtcwake: assuming RTC uses UTC ...
11620 13:24:22.135959 rtcwake: wakeup from "mem" using rtc0 at Wed Sep 6 13:24:31 2023
11621 13:24:22.148699 <6>[ 66.752184] PM: suspend entry (deep)
11622 13:24:22.152150 <6>[ 66.756083] Filesystems sync: 0.000 seconds
11623 13:24:22.155117 <6>[ 66.761141] Freezing user space processes
11624 13:24:22.166756 <6>[ 66.767082] Freezing user space processes completed (elapsed 0.001 seconds)
11625 13:24:22.170199 <6>[ 66.774314] OOM killer disabled.
11626 13:24:22.173380 <6>[ 66.777794] Freezing remaining freezable tasks
11627 13:24:22.188317 <6>[ 66.788640] usb 1-1.1.4: new full-speed USB device number 40 using xhci-mtk
11628 13:24:22.272638 <3>[ 66.876500] usb 1-1.1.4: device descriptor read/64, error -32
11629 13:24:22.464975 <3>[ 67.068609] usb 1-1.1.4: device descriptor read/64, error -32
11630 13:24:22.660087 <6>[ 67.260553] usb 1-1.1.4: new full-speed USB device number 41 using xhci-mtk
11631 13:24:22.745088 <3>[ 67.348551] usb 1-1.1.4: device descriptor read/64, error -32
11632 13:24:22.937103 <3>[ 67.540566] usb 1-1.1.4: device descriptor read/64, error -32
11633 13:24:23.048901 <6>[ 67.652737] usb 1-1.1-port4: attempt power cycle
11634 13:24:23.660048 <6>[ 68.260577] usb 1-1.1.4: new full-speed USB device number 42 using xhci-mtk
11635 13:24:23.666437 <4>[ 68.267964] usb 1-1.1.4: Device not responding to setup address.
11636 13:24:23.876260 <4>[ 68.480658] usb 1-1.1.4: Device not responding to setup address.
11637 13:24:24.088709 <3>[ 68.692494] usb 1-1.1.4: device not accepting address 42, error -71
11638 13:24:24.175910 <6>[ 68.776547] usb 1-1.1.4: new full-speed USB device number 43 using xhci-mtk
11639 13:24:24.182673 <4>[ 68.783912] usb 1-1.1.4: Device not responding to setup address.
11640 13:24:24.393175 <4>[ 68.996701] usb 1-1.1.4: Device not responding to setup address.
11641 13:24:24.604385 <3>[ 69.208515] usb 1-1.1.4: device not accepting address 43, error -71
11642 13:24:24.611735 <3>[ 69.215376] usb 1-1.1-port4: unable to enumerate USB device
11643 13:24:24.623763 <6>[ 69.224589] Freezing remaining freezable tasks completed (elapsed 2.442 seconds)
11644 13:24:24.630275 <6>[ 69.232313] printk: Suspending console(s) (use no_console_suspend to debug)
11645 13:24:27.947054 <3>[ 72.276684] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11646 13:24:27.956489 <3>[ 72.276716] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11647 13:24:27.966511 <3>[ 72.276762] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11648 13:24:27.973442 <3>[ 72.276804] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11649 13:24:27.983174 <3>[ 72.277069] PM: Some devices failed to suspend, or early wake event detected
11650 13:24:27.986229 <6>[ 72.590848] OOM killer enabled.
11651 13:24:27.989488 <6>[ 72.594261] Restarting tasks ... done.
11652 13:24:27.996148 <5>[ 72.600129] random: crng reseeded on system resumption
11653 13:24:28.000116 <6>[ 72.606793] PM: suspend exit
11654 13:24:28.003276 rtcwake: write error
11655 13:24:28.010280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11656 13:24:28.011163 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11658 13:24:28.013476 rtcwake: assuming RTC uses UTC ...
11659 13:24:28.019626 rtcwake: wakeup from "mem" using rtc0 at Wed Sep 6 13:24:37 2023
11660 13:24:28.031696 <6>[ 72.636104] PM: suspend entry (deep)
11661 13:24:28.035261 <6>[ 72.639999] Filesystems sync: 0.000 seconds
11662 13:24:28.038362 <6>[ 72.645061] Freezing user space processes
11663 13:24:28.050478 <6>[ 72.651004] Freezing user space processes completed (elapsed 0.001 seconds)
11664 13:24:28.053283 <6>[ 72.658236] OOM killer disabled.
11665 13:24:28.056592 <6>[ 72.661718] Freezing remaining freezable tasks
11666 13:24:28.075468 <6>[ 72.676559] usb 1-1.1.4: new full-speed USB device number 44 using xhci-mtk
11667 13:24:28.156161 <3>[ 72.760537] usb 1-1.1.4: device descriptor read/64, error -32
11668 13:24:28.348708 <3>[ 72.952735] usb 1-1.1.4: device descriptor read/64, error -32
11669 13:24:28.543724 <6>[ 73.144683] usb 1-1.1.4: new full-speed USB device number 45 using xhci-mtk
11670 13:24:28.628488 <3>[ 73.232735] usb 1-1.1.4: device descriptor read/64, error -32
11671 13:24:28.820046 <3>[ 73.424576] usb 1-1.1.4: device descriptor read/64, error -32
11672 13:24:28.932467 <6>[ 73.536928] usb 1-1.1-port4: attempt power cycle
11673 13:24:29.544277 <6>[ 74.144676] usb 1-1.1.4: new full-speed USB device number 46 using xhci-mtk
11674 13:24:29.549986 <4>[ 74.152056] usb 1-1.1.4: Device not responding to setup address.
11675 13:24:29.760090 <4>[ 74.364687] usb 1-1.1.4: Device not responding to setup address.
11676 13:24:29.972197 <3>[ 74.576522] usb 1-1.1.4: device not accepting address 46, error -71
11677 13:24:30.059161 <6>[ 74.660539] usb 1-1.1.4: new full-speed USB device number 47 using xhci-mtk
11678 13:24:30.065744 <4>[ 74.667918] usb 1-1.1.4: Device not responding to setup address.
11679 13:24:30.276576 <4>[ 74.880700] usb 1-1.1.4: Device not responding to setup address.
11680 13:24:30.488333 <3>[ 75.092714] usb 1-1.1.4: device not accepting address 47, error -71
11681 13:24:30.494852 <3>[ 75.099579] usb 1-1.1-port4: unable to enumerate USB device
11682 13:24:30.508344 <6>[ 75.109572] Freezing remaining freezable tasks completed (elapsed 2.443 seconds)
11683 13:24:30.515053 <6>[ 75.117263] printk: Suspending console(s) (use no_console_suspend to debug)
11684 13:24:33.830752 <3>[ 78.164720] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11685 13:24:33.840026 <3>[ 78.164752] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11686 13:24:33.849435 <3>[ 78.164798] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11687 13:24:33.856797 <3>[ 78.164840] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11688 13:24:33.866087 <3>[ 78.165168] PM: Some devices failed to suspend, or early wake event detected
11689 13:24:33.869509 <6>[ 78.474775] OOM killer enabled.
11690 13:24:33.876423 <6>[ 78.478186] Restarting tasks ... done.
11691 13:24:33.879237 <5>[ 78.485178] random: crng reseeded on system resumption
11692 13:24:33.886759 <6>[ 78.494226] PM: suspend exit
11693 13:24:33.889935 rtcwake: write error
11694 13:24:33.896370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11695 13:24:33.897235 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11697 13:24:33.899678 rtcwake: assuming RTC uses UTC ...
11698 13:24:33.906545 rtcwake: wakeup from "freeze" using rtc0 at Wed Sep 6 13:24:43 2023
11699 13:24:33.920112 <6>[ 78.525087] PM: suspend entry (s2idle)
11700 13:24:33.923435 <6>[ 78.529223] Filesystems sync: 0.000 seconds
11701 13:24:33.930576 <6>[ 78.534223] Freezing user space processes
11702 13:24:33.937194 <6>[ 78.540201] Freezing user space processes completed (elapsed 0.001 seconds)
11703 13:24:33.940478 <6>[ 78.547430] OOM killer disabled.
11704 13:24:33.947305 <6>[ 78.550911] Freezing remaining freezable tasks
11705 13:24:33.959280 <6>[ 78.560655] usb 1-1.1.4: new full-speed USB device number 48 using xhci-mtk
11706 13:24:34.043699 <3>[ 78.648508] usb 1-1.1.4: device descriptor read/64, error -32
11707 13:24:34.235954 <3>[ 78.840598] usb 1-1.1.4: device descriptor read/64, error -32
11708 13:24:34.431033 <6>[ 79.032558] usb 1-1.1.4: new full-speed USB device number 49 using xhci-mtk
11709 13:24:34.511749 <3>[ 79.116743] usb 1-1.1.4: device descriptor read/64, error -32
11710 13:24:34.704113 <3>[ 79.308578] usb 1-1.1.4: device descriptor read/64, error -32
11711 13:24:34.816003 <6>[ 79.420957] usb 1-1.1-port4: attempt power cycle
11712 13:24:35.427257 <6>[ 80.028674] usb 1-1.1.4: new full-speed USB device number 50 using xhci-mtk
11713 13:24:35.433182 <4>[ 80.036052] usb 1-1.1.4: Device not responding to setup address.
11714 13:24:35.643733 <4>[ 80.248706] usb 1-1.1.4: Device not responding to setup address.
11715 13:24:35.855268 <3>[ 80.460546] usb 1-1.1.4: device not accepting address 50, error -71
11716 13:24:35.942646 <6>[ 80.544552] usb 1-1.1.4: new full-speed USB device number 51 using xhci-mtk
11717 13:24:35.949426 <4>[ 80.551932] usb 1-1.1.4: Device not responding to setup address.
11718 13:24:36.159528 <4>[ 80.764784] usb 1-1.1.4: Device not responding to setup address.
11719 13:24:36.371675 <3>[ 80.976730] usb 1-1.1.4: device not accepting address 51, error -71
11720 13:24:36.378269 <3>[ 80.983563] usb 1-1.1-port4: unable to enumerate USB device
11721 13:24:36.390720 <6>[ 80.992648] Freezing remaining freezable tasks completed (elapsed 2.437 seconds)
11722 13:24:36.397337 <6>[ 81.000383] printk: Suspending console(s) (use no_console_suspend to debug)
11723 13:24:39.717475 <3>[ 84.052686] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11724 13:24:39.727423 <3>[ 84.052717] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11725 13:24:39.737131 <3>[ 84.052764] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11726 13:24:39.743649 <3>[ 84.052806] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11727 13:24:39.750588 <3>[ 84.053072] PM: Some devices failed to suspend, or early wake event detected
11728 13:24:39.756968 <6>[ 84.362823] OOM killer enabled.
11729 13:24:39.764766 <6>[ 84.366238] Restarting tasks ... done.
11730 13:24:39.768047 <5>[ 84.374345] random: crng reseeded on system resumption
11731 13:24:39.773859 <6>[ 84.382823] PM: suspend exit
11732 13:24:39.777636 rtcwake: write error
11733 13:24:39.784277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11734 13:24:39.785122 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11736 13:24:39.787458 rtcwake: assuming RTC uses UTC ...
11737 13:24:39.794027 rtcwake: wakeup from "freeze" using rtc0 at Wed Sep 6 13:24:49 2023
11738 13:24:39.806461 <6>[ 84.412282] PM: suspend entry (s2idle)
11739 13:24:39.810176 <6>[ 84.416383] Filesystems sync: 0.000 seconds
11740 13:24:39.814285 <6>[ 84.421331] Freezing user space processes
11741 13:24:39.825628 <6>[ 84.427379] Freezing user space processes completed (elapsed 0.001 seconds)
11742 13:24:39.828644 <6>[ 84.434616] OOM killer disabled.
11743 13:24:39.831676 <6>[ 84.438103] Freezing remaining freezable tasks
11744 13:24:39.846867 <6>[ 84.448637] usb 1-1.1.4: new full-speed USB device number 52 using xhci-mtk
11745 13:24:39.931108 <3>[ 84.536462] usb 1-1.1.4: device descriptor read/64, error -32
11746 13:24:40.123013 <3>[ 84.728506] usb 1-1.1.4: device descriptor read/64, error -32
11747 13:24:40.318514 <6>[ 84.920468] usb 1-1.1.4: new full-speed USB device number 53 using xhci-mtk
11748 13:24:40.399644 <3>[ 85.004598] usb 1-1.1.4: device descriptor read/64, error -32
11749 13:24:40.590422 <3>[ 85.196735] usb 1-1.1.4: device descriptor read/64, error -32
11750 13:24:40.703082 <6>[ 85.308735] usb 1-1.1-port4: attempt power cycle
11751 13:24:41.314430 <6>[ 85.916528] usb 1-1.1.4: new full-speed USB device number 54 using xhci-mtk
11752 13:24:41.321043 <4>[ 85.923898] usb 1-1.1.4: Device not responding to setup address.
11753 13:24:41.530787 <4>[ 86.136667] usb 1-1.1.4: Device not responding to setup address.
11754 13:24:41.743434 <3>[ 86.348521] usb 1-1.1.4: device not accepting address 54, error -71
11755 13:24:41.830202 <6>[ 86.432531] usb 1-1.1.4: new full-speed USB device number 55 using xhci-mtk
11756 13:24:41.836382 <4>[ 86.439910] usb 1-1.1.4: Device not responding to setup address.
11757 13:24:42.047138 <4>[ 86.652688] usb 1-1.1.4: Device not responding to setup address.
11758 13:24:42.259077 <3>[ 86.864532] usb 1-1.1.4: device not accepting address 55, error -71
11759 13:24:42.266280 <3>[ 86.871402] usb 1-1.1-port4: unable to enumerate USB device
11760 13:24:42.277677 <6>[ 86.880407] Freezing remaining freezable tasks completed (elapsed 2.437 seconds)
11761 13:24:42.284600 <6>[ 86.888085] printk: Suspending console(s) (use no_console_suspend to debug)
11762 13:24:45.609164 <3>[ 89.940684] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11763 13:24:45.618737 <3>[ 89.940716] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11764 13:24:45.628916 <3>[ 89.940762] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11765 13:24:45.635205 <3>[ 89.940803] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11766 13:24:45.644756 <3>[ 89.941141] PM: Some devices failed to suspend, or early wake event detected
11767 13:24:45.648181 <6>[ 90.254635] OOM killer enabled.
11768 13:24:45.661281 <6>[ 90.258048] Restarting tasks ... done.
11769 13:24:45.664289 <5>[ 90.271270] random: crng reseeded on system resumption
11770 13:24:45.668917 <6>[ 90.278272] PM: suspend exit
11771 13:24:45.672159 rtcwake: write error
11772 13:24:45.679482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11773 13:24:45.680377 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11775 13:24:45.682532 rtcwake: assuming RTC uses UTC ...
11776 13:24:45.689677 rtcwake: wakeup from "freeze" using rtc0 at Wed Sep 6 13:24:55 2023
11777 13:24:45.701427 <6>[ 90.307870] PM: suspend entry (s2idle)
11778 13:24:45.705273 <6>[ 90.311948] Filesystems sync: 0.000 seconds
11779 13:24:45.711748 <6>[ 90.317068] Freezing user space processes
11780 13:24:45.718674 <6>[ 90.323057] Freezing user space processes completed (elapsed 0.001 seconds)
11781 13:24:45.721770 <6>[ 90.330297] OOM killer disabled.
11782 13:24:45.728031 <6>[ 90.333778] Freezing remaining freezable tasks
11783 13:24:45.734992 <6>[ 90.336445] usb 1-1.1.4: new full-speed USB device number 56 using xhci-mtk
11784 13:24:45.818511 <3>[ 90.424495] usb 1-1.1.4: device descriptor read/64, error -32
11785 13:24:46.010443 <3>[ 90.616585] usb 1-1.1.4: device descriptor read/64, error -32
11786 13:24:46.205949 <6>[ 90.808549] usb 1-1.1.4: new full-speed USB device number 57 using xhci-mtk
11787 13:24:46.286987 <3>[ 90.892585] usb 1-1.1.4: device descriptor read/64, error -32
11788 13:24:46.478648 <3>[ 91.084717] usb 1-1.1.4: device descriptor read/64, error -32
11789 13:24:46.590531 <6>[ 91.196802] usb 1-1.1-port4: attempt power cycle
11790 13:24:47.201641 <6>[ 91.804540] usb 1-1.1.4: new full-speed USB device number 58 using xhci-mtk
11791 13:24:47.208315 <4>[ 91.811916] usb 1-1.1.4: Device not responding to setup address.
11792 13:24:47.418226 <4>[ 92.024804] usb 1-1.1.4: Device not responding to setup address.
11793 13:24:47.633662 <3>[ 92.236667] usb 1-1.1.4: device not accepting address 58, error -71
11794 13:24:47.717858 <6>[ 92.320676] usb 1-1.1.4: new full-speed USB device number 59 using xhci-mtk
11795 13:24:47.724186 <4>[ 92.328059] usb 1-1.1.4: Device not responding to setup address.
11796 13:24:47.935240 <4>[ 92.540910] usb 1-1.1.4: Device not responding to setup address.
11797 13:24:48.146496 <3>[ 92.752666] usb 1-1.1.4: device not accepting address 59, error -71
11798 13:24:48.152889 <3>[ 92.759494] usb 1-1.1-port4: unable to enumerate USB device
11799 13:24:48.169862 <6>[ 92.772925] Freezing remaining freezable tasks completed (elapsed 2.434 seconds)
11800 13:24:48.176653 <6>[ 92.780617] printk: Suspending console(s) (use no_console_suspend to debug)
11801 13:24:51.492445 <3>[ 95.828689] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11802 13:24:51.503244 <3>[ 95.828721] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11803 13:24:51.512484 <3>[ 95.828768] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11804 13:24:51.518824 <3>[ 95.828810] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11805 13:24:51.525073 <3>[ 95.829079] PM: Some devices failed to suspend, or early wake event detected
11806 13:24:51.531976 <6>[ 96.138881] OOM killer enabled.
11807 13:24:51.535451 <6>[ 96.142294] Restarting tasks ... done.
11808 13:24:51.542013 <5>[ 96.148195] random: crng reseeded on system resumption
11809 13:24:51.545607 <6>[ 96.154761] PM: suspend exit
11810 13:24:51.548579 rtcwake: write error
11811 13:24:51.555360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11812 13:24:51.556225 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11814 13:24:51.559630 rtcwake: assuming RTC uses UTC ...
11815 13:24:51.565057 rtcwake: wakeup from "freeze" using rtc0 at Wed Sep 6 13:25:01 2023
11816 13:24:51.576449 <6>[ 96.183562] PM: suspend entry (s2idle)
11817 13:24:51.580293 <6>[ 96.187625] Filesystems sync: 0.000 seconds
11818 13:24:51.586702 <6>[ 96.192731] Freezing user space processes
11819 13:24:51.593575 <6>[ 96.198657] Freezing user space processes completed (elapsed 0.001 seconds)
11820 13:24:51.596732 <6>[ 96.205888] OOM killer disabled.
11821 13:24:51.602966 <6>[ 96.209369] Freezing remaining freezable tasks
11822 13:24:51.625561 <6>[ 96.228663] usb 1-1.1.4: new full-speed USB device number 60 using xhci-mtk
11823 13:24:51.710497 <3>[ 96.316535] usb 1-1.1.4: device descriptor read/64, error -32
11824 13:24:51.902232 <3>[ 96.508588] usb 1-1.1.4: device descriptor read/64, error -32
11825 13:24:52.097298 <6>[ 96.700559] usb 1-1.1.4: new full-speed USB device number 61 using xhci-mtk
11826 13:24:52.178115 <3>[ 96.784732] usb 1-1.1.4: device descriptor read/64, error -32
11827 13:24:52.370322 <3>[ 96.976735] usb 1-1.1.4: device descriptor read/64, error -32
11828 13:24:52.482483 <6>[ 97.088925] usb 1-1.1-port4: attempt power cycle
11829 13:24:53.092951 <6>[ 97.696676] usb 1-1.1.4: new full-speed USB device number 62 using xhci-mtk
11830 13:24:53.099369 <4>[ 97.704056] usb 1-1.1.4: Device not responding to setup address.
11831 13:24:53.309751 <4>[ 97.916860] usb 1-1.1.4: Device not responding to setup address.
11832 13:24:53.521416 <3>[ 98.128672] usb 1-1.1.4: device not accepting address 62, error -71
11833 13:24:53.608792 <6>[ 98.212553] usb 1-1.1.4: new full-speed USB device number 63 using xhci-mtk
11834 13:24:53.615211 <4>[ 98.219995] usb 1-1.1.4: Device not responding to setup address.
11835 13:24:53.825772 <4>[ 98.432784] usb 1-1.1.4: Device not responding to setup address.
11836 13:24:54.037675 <3>[ 98.644543] usb 1-1.1.4: device not accepting address 63, error -71
11837 13:24:54.044212 <3>[ 98.651373] usb 1-1.1-port4: unable to enumerate USB device
11838 13:24:54.056546 <6>[ 98.660647] Freezing remaining freezable tasks completed (elapsed 2.446 seconds)
11839 13:24:54.063745 <6>[ 98.668384] printk: Suspending console(s) (use no_console_suspend to debug)
11840 13:24:57.379241 <3>[ 101.716688] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11841 13:24:57.389362 <3>[ 101.716720] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11842 13:24:57.398947 <3>[ 101.716766] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11843 13:24:57.405788 <3>[ 101.716807] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11844 13:24:57.412363 <3>[ 101.717058] PM: Some devices failed to suspend, or early wake event detected
11845 13:24:57.418915 <6>[ 102.026501] OOM killer enabled.
11846 13:24:57.426409 <6>[ 102.029913] Restarting tasks ... done.
11847 13:24:57.430198 <5>[ 102.038191] random: crng reseeded on system resumption
11848 13:24:57.434377 <6>[ 102.044887] PM: suspend exit
11849 13:24:57.437190 rtcwake: write error
11850 13:24:57.444988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11851 13:24:57.445855 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11853 13:24:57.447477 rtcwake: assuming RTC uses UTC ...
11854 13:24:57.454243 rtcwake: wakeup from "freeze" using rtc0 at Wed Sep 6 13:25:07 2023
11855 13:24:57.466803 <6>[ 102.074243] PM: suspend entry (s2idle)
11856 13:24:57.470217 <6>[ 102.078334] Filesystems sync: 0.000 seconds
11857 13:24:57.476871 <6>[ 102.083377] Freezing user space processes
11858 13:24:57.483304 <6>[ 102.089206] Freezing user space processes completed (elapsed 0.001 seconds)
11859 13:24:57.486666 <6>[ 102.096428] OOM killer disabled.
11860 13:24:57.493210 <6>[ 102.099905] Freezing remaining freezable tasks
11861 13:24:57.504243 <6>[ 102.108496] usb 1-1.1.4: new full-speed USB device number 64 using xhci-mtk
11862 13:24:57.585423 <3>[ 102.192508] usb 1-1.1.4: device descriptor read/64, error -32
11863 13:24:57.777206 <3>[ 102.384604] usb 1-1.1.4: device descriptor read/64, error -32
11864 13:24:57.972431 <6>[ 102.576683] usb 1-1.1.4: new full-speed USB device number 65 using xhci-mtk
11865 13:24:58.057562 <3>[ 102.664742] usb 1-1.1.4: device descriptor read/64, error -32
11866 13:24:58.249267 <3>[ 102.856581] usb 1-1.1.4: device descriptor read/64, error -32
11867 13:24:58.361861 <6>[ 102.969118] usb 1-1.1-port4: attempt power cycle
11868 13:24:58.972475 <6>[ 103.576676] usb 1-1.1.4: new full-speed USB device number 66 using xhci-mtk
11869 13:24:58.978880 <4>[ 103.584055] usb 1-1.1.4: Device not responding to setup address.
11870 13:24:59.189719 <4>[ 103.796700] usb 1-1.1.4: Device not responding to setup address.
11871 13:24:59.401265 <3>[ 104.008576] usb 1-1.1.4: device not accepting address 66, error -71
11872 13:24:59.488355 <6>[ 104.092539] usb 1-1.1.4: new full-speed USB device number 67 using xhci-mtk
11873 13:24:59.495689 <4>[ 104.099961] usb 1-1.1.4: Device not responding to setup address.
11874 13:24:59.705357 <4>[ 104.312700] usb 1-1.1.4: Device not responding to setup address.
11875 13:24:59.916820 <3>[ 104.524578] usb 1-1.1.4: device not accepting address 67, error -71
11876 13:24:59.923668 <3>[ 104.531443] usb 1-1.1-port4: unable to enumerate USB device
11877 13:24:59.933469 <6>[ 104.537517] Freezing remaining freezable tasks completed (elapsed 2.432 seconds)
11878 13:24:59.940734 <6>[ 104.545209] printk: Suspending console(s) (use no_console_suspend to debug)
11879 13:25:03.270785 <3>[ 107.604682] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11880 13:25:03.280556 <3>[ 107.604715] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11881 13:25:03.290786 <3>[ 107.604760] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11882 13:25:03.297269 <3>[ 107.604802] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11883 13:25:03.307009 <3>[ 107.604989] PM: Some devices failed to suspend, or early wake event detected
11884 13:25:03.310395 <6>[ 107.918761] OOM killer enabled.
11885 13:25:03.314243 <6>[ 107.922173] Restarting tasks ... done.
11886 13:25:03.320475 <5>[ 107.928206] random: crng reseeded on system resumption
11887 13:25:03.323693 <6>[ 107.934820] PM: suspend exit
11888 13:25:03.327122 rtcwake: write error
11889 13:25:03.333837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11890 13:25:03.334770 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11892 13:25:03.337110 rtcwake: assuming RTC uses UTC ...
11893 13:25:03.344745 rtcwake: wakeup from "freeze" using rtc0 at Wed Sep 6 13:25:13 2023
11894 13:25:03.356472 <6>[ 107.964195] PM: suspend entry (s2idle)
11895 13:25:03.359136 <6>[ 107.968282] Filesystems sync: 0.000 seconds
11896 13:25:03.367318 <6>[ 107.973306] Freezing user space processes
11897 13:25:03.372401 <6>[ 107.979296] Freezing user space processes completed (elapsed 0.001 seconds)
11898 13:25:03.375779 <6>[ 107.986526] OOM killer disabled.
11899 13:25:03.382259 <6>[ 107.990008] Freezing remaining freezable tasks
11900 13:25:03.399696 <6>[ 108.004475] usb 1-1.1.4: new full-speed USB device number 68 using xhci-mtk
11901 13:25:03.480714 <3>[ 108.088948] usb 1-1.1.4: device descriptor read/64, error -32
11902 13:25:03.672699 <3>[ 108.280637] usb 1-1.1.4: device descriptor read/64, error -32
11903 13:25:03.867558 <6>[ 108.472443] usb 1-1.1.4: new full-speed USB device number 69 using xhci-mtk
11904 13:25:03.949286 <3>[ 108.556640] usb 1-1.1.4: device descriptor read/64, error -32
11905 13:25:04.140873 <3>[ 108.748947] usb 1-1.1.4: device descriptor read/64, error -32
11906 13:25:04.252411 <6>[ 108.860766] usb 1-1.1-port4: attempt power cycle
11907 13:25:04.864069 <6>[ 109.468498] usb 1-1.1.4: new full-speed USB device number 70 using xhci-mtk
11908 13:25:04.870129 <4>[ 109.476032] usb 1-1.1.4: Device not responding to setup address.
11909 13:25:05.080276 <4>[ 109.688672] usb 1-1.1.4: Device not responding to setup address.
11910 13:25:05.292114 <3>[ 109.900603] usb 1-1.1.4: device not accepting address 70, error -71
11911 13:25:05.379533 <6>[ 109.984485] usb 1-1.1.4: new full-speed USB device number 71 using xhci-mtk
11912 13:25:05.386227 <4>[ 109.992042] usb 1-1.1.4: Device not responding to setup address.
11913 13:25:05.596538 <4>[ 110.204787] usb 1-1.1.4: Device not responding to setup address.
11914 13:25:05.808181 <3>[ 110.416437] usb 1-1.1.4: device not accepting address 71, error -71
11915 13:25:05.815302 <3>[ 110.423446] usb 1-1.1-port4: unable to enumerate USB device
11916 13:25:05.831471 <6>[ 110.436500] Freezing remaining freezable tasks completed (elapsed 2.441 seconds)
11917 13:25:05.837765 <6>[ 110.444197] printk: Suspending console(s) (use no_console_suspend to debug)
11918 13:25:09.153709 <3>[ 113.492688] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11919 13:25:09.164081 <3>[ 113.492720] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11920 13:25:09.174011 <3>[ 113.492766] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11921 13:25:09.180457 <3>[ 113.492808] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11922 13:25:09.187387 <3>[ 113.493138] PM: Some devices failed to suspend, or early wake event detected
11923 13:25:09.190730 <6>[ 113.802648] OOM killer enabled.
11924 13:25:09.208241 <6>[ 113.806062] Restarting tasks ... done.
11925 13:25:09.211880 <5>[ 113.821257] random: crng reseeded on system resumption
11926 13:25:09.216816 <6>[ 113.828648] PM: suspend exit
11927 13:25:09.219814 rtcwake: write error
11928 13:25:09.227462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11929 13:25:09.228327 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11931 13:25:09.229528 rtcwake: assuming RTC uses UTC ...
11932 13:25:09.236759 rtcwake: wakeup from "freeze" using rtc0 at Wed Sep 6 13:25:19 2023
11933 13:25:09.249470 <6>[ 113.857847] PM: suspend entry (s2idle)
11934 13:25:09.252275 <6>[ 113.861926] Filesystems sync: 0.000 seconds
11935 13:25:09.259516 <6>[ 113.866980] Freezing user space processes
11936 13:25:09.265882 <6>[ 113.872495] Freezing user space processes completed (elapsed 0.001 seconds)
11937 13:25:09.268655 <6>[ 113.879719] OOM killer disabled.
11938 13:25:09.275307 <6>[ 113.883198] Freezing remaining freezable tasks
11939 13:25:09.281924 <6>[ 113.884500] usb 1-1.1.4: new full-speed USB device number 72 using xhci-mtk
11940 13:25:09.363843 <3>[ 113.972459] usb 1-1.1.4: device descriptor read/64, error -32
11941 13:25:09.556126 <3>[ 114.164551] usb 1-1.1.4: device descriptor read/64, error -32
11942 13:25:09.751818 <6>[ 114.356565] usb 1-1.1.4: new full-speed USB device number 73 using xhci-mtk
11943 13:25:09.831670 <3>[ 114.440718] usb 1-1.1.4: device descriptor read/64, error -32
11944 13:25:10.023352 <3>[ 114.632555] usb 1-1.1.4: device descriptor read/64, error -32
11945 13:25:10.135861 <6>[ 114.744744] usb 1-1.1-port4: attempt power cycle
11946 13:25:10.747046 <6>[ 115.352673] usb 1-1.1.4: new full-speed USB device number 74 using xhci-mtk
11947 13:25:10.753523 <4>[ 115.360055] usb 1-1.1.4: Device not responding to setup address.
11948 13:25:10.963887 <4>[ 115.572615] usb 1-1.1.4: Device not responding to setup address.
11949 13:25:11.176224 <3>[ 115.784609] usb 1-1.1.4: device not accepting address 74, error -71
11950 13:25:11.262940 <6>[ 115.868675] usb 1-1.1.4: new full-speed USB device number 75 using xhci-mtk
11951 13:25:11.269818 <4>[ 115.876115] usb 1-1.1.4: Device not responding to setup address.
11952 13:25:11.479587 <4>[ 116.088774] usb 1-1.1.4: Device not responding to setup address.
11953 13:25:11.691649 <3>[ 116.300666] usb 1-1.1.4: device not accepting address 75, error -71
11954 13:25:11.698659 <3>[ 116.307533] usb 1-1.1-port4: unable to enumerate USB device
11955 13:25:11.708133 <6>[ 116.313644] Freezing remaining freezable tasks completed (elapsed 2.425 seconds)
11956 13:25:11.715041 <6>[ 116.321336] printk: Suspending console(s) (use no_console_suspend to debug)
11957 13:25:15.041340 <3>[ 119.380695] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11958 13:25:15.051648 <3>[ 119.380727] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11959 13:25:15.061430 <3>[ 119.380773] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11960 13:25:15.067872 <3>[ 119.380815] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11961 13:25:15.077321 <3>[ 119.381088] PM: Some devices failed to suspend, or early wake event detected
11962 13:25:15.080562 <6>[ 119.690882] OOM killer enabled.
11963 13:25:15.093541 <6>[ 119.694296] Restarting tasks ... done.
11964 13:25:15.096832 <5>[ 119.707573] random: crng reseeded on system resumption
11965 13:25:15.101175 <6>[ 119.714528] PM: suspend exit
11966 13:25:15.104969 rtcwake: write error
11967 13:25:15.111422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11968 13:25:15.111811 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11970 13:25:15.115514 rtcwake: assuming RTC uses UTC ...
11971 13:25:15.121793 rtcwake: wakeup from "freeze" using rtc0 at Wed Sep 6 13:25:24 2023
11972 13:25:15.134281 <6>[ 119.743790] PM: suspend entry (s2idle)
11973 13:25:15.137838 <6>[ 119.747852] Filesystems sync: 0.000 seconds
11974 13:25:15.144200 <6>[ 119.752982] Freezing user space processes
11975 13:25:15.150815 <6>[ 119.758964] Freezing user space processes completed (elapsed 0.001 seconds)
11976 13:25:15.154053 <6>[ 119.766206] OOM killer disabled.
11977 13:25:15.160815 <6>[ 119.769687] Freezing remaining freezable tasks
11978 13:25:15.170508 <6>[ 119.776602] usb 1-1.1.4: new full-speed USB device number 76 using xhci-mtk
11979 13:25:15.255458 <3>[ 119.864669] usb 1-1.1.4: device descriptor read/64, error -32
11980 13:25:15.446986 <3>[ 120.056559] usb 1-1.1.4: device descriptor read/64, error -32
11981 13:25:15.642328 <6>[ 120.248541] usb 1-1.1.4: new full-speed USB device number 77 using xhci-mtk
11982 13:25:15.723218 <3>[ 120.332594] usb 1-1.1.4: device descriptor read/64, error -32
11983 13:25:15.914964 <3>[ 120.524578] usb 1-1.1.4: device descriptor read/64, error -32
11984 13:25:16.027324 <6>[ 120.636922] usb 1-1.1-port4: attempt power cycle
11985 13:25:16.638144 <6>[ 121.244686] usb 1-1.1.4: new full-speed USB device number 78 using xhci-mtk
11986 13:25:16.644767 <4>[ 121.252066] usb 1-1.1.4: Device not responding to setup address.
11987 13:25:16.855195 <4>[ 121.464811] usb 1-1.1.4: Device not responding to setup address.
11988 13:25:17.067051 <3>[ 121.676532] usb 1-1.1.4: device not accepting address 78, error -71
11989 13:25:17.154307 <6>[ 121.760539] usb 1-1.1.4: new full-speed USB device number 79 using xhci-mtk
11990 13:25:17.160448 <4>[ 121.767918] usb 1-1.1.4: Device not responding to setup address.
11991 13:25:17.371137 <4>[ 121.980759] usb 1-1.1.4: Device not responding to setup address.
11992 13:25:17.583104 <3>[ 122.192552] usb 1-1.1.4: device not accepting address 79, error -71
11993 13:25:17.590122 <3>[ 122.199387] usb 1-1.1-port4: unable to enumerate USB device
11994 13:25:17.602824 <6>[ 122.209153] Freezing remaining freezable tasks completed (elapsed 2.434 seconds)
11995 13:25:17.609186 <6>[ 122.216843] printk: Suspending console(s) (use no_console_suspend to debug)
11996 13:25:20.933128 <3>[ 125.268719] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11997 13:25:20.942695 <3>[ 125.268755] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11998 13:25:20.952963 <3>[ 125.268816] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11999 13:25:20.959347 <3>[ 125.268856] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
12000 13:25:20.966096 <3>[ 125.269171] PM: Some devices failed to suspend, or early wake event detected
12001 13:25:20.973187 <6>[ 125.582791] OOM killer enabled.
12002 13:25:20.976367 <6>[ 125.586202] Restarting tasks ... done.
12003 13:25:20.982410 <5>[ 125.592178] random: crng reseeded on system resumption
12004 13:25:20.986344 <6>[ 125.599182] PM: suspend exit
12005 13:25:20.989379 rtcwake: write error
12006 13:25:20.995764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
12007 13:25:20.996603 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
12009 13:25:20.999081 rtcwake: assuming RTC uses UTC ...
12010 13:25:21.006463 rtcwake: wakeup from "freeze" using rtc0 at Wed Sep 6 13:25:30 2023
12011 13:25:21.018766 <6>[ 125.628595] PM: suspend entry (s2idle)
12012 13:25:21.022181 <6>[ 125.632665] Filesystems sync: 0.000 seconds
12013 13:25:21.028498 <6>[ 125.637713] Freezing user space processes
12014 13:25:21.035344 <6>[ 125.643658] Freezing user space processes completed (elapsed 0.001 seconds)
12015 13:25:21.038064 <6>[ 125.650907] OOM killer disabled.
12016 13:25:21.045246 <6>[ 125.654389] Freezing remaining freezable tasks
12017 13:25:21.065633 <6>[ 125.672489] usb 1-1.1.4: new full-speed USB device number 80 using xhci-mtk
12018 13:25:21.146754 <3>[ 125.756672] usb 1-1.1.4: device descriptor read/64, error -32
12019 13:25:21.338928 <3>[ 125.948590] usb 1-1.1.4: device descriptor read/64, error -32
12020 13:25:21.533885 <6>[ 126.140688] usb 1-1.1.4: new full-speed USB device number 81 using xhci-mtk
12021 13:25:21.618771 <3>[ 126.228581] usb 1-1.1.4: device descriptor read/64, error -32
12022 13:25:21.811122 <3>[ 126.420714] usb 1-1.1.4: device descriptor read/64, error -32
12023 13:25:21.923146 <6>[ 126.532923] usb 1-1.1-port4: attempt power cycle
12024 13:25:22.534176 <6>[ 127.140676] usb 1-1.1.4: new full-speed USB device number 82 using xhci-mtk
12025 13:25:22.540188 <4>[ 127.148057] usb 1-1.1.4: Device not responding to setup address.
12026 13:25:22.750581 <4>[ 127.360795] usb 1-1.1.4: Device not responding to setup address.
12027 13:25:22.962370 <3>[ 127.572666] usb 1-1.1.4: device not accepting address 82, error -71
12028 13:25:23.050027 <6>[ 127.656675] usb 1-1.1.4: new full-speed USB device number 83 using xhci-mtk
12029 13:25:23.056338 <4>[ 127.664056] usb 1-1.1.4: Device not responding to setup address.
12030 13:25:23.266415 <4>[ 127.876680] usb 1-1.1.4: Device not responding to setup address.
12031 13:25:23.478406 <3>[ 128.088571] usb 1-1.1.4: device not accepting address 83, error -71
12032 13:25:23.485386 <3>[ 128.095416] usb 1-1.1-port4: unable to enumerate USB device
12033 13:25:23.497903 <6>[ 128.104553] Freezing remaining freezable tasks completed (elapsed 2.445 seconds)
12034 13:25:23.503737 <6>[ 128.112251] printk: Suspending console(s) (use no_console_suspend to debug)
12035 13:25:26.820509 <3>[ 131.156684] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
12036 13:25:26.830239 <3>[ 131.156716] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
12037 13:25:26.840143 <3>[ 131.156763] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
12038 13:25:26.846762 <3>[ 131.156805] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
12039 13:25:26.853620 <3>[ 131.157075] PM: Some devices failed to suspend, or early wake event detected
12040 13:25:26.859961 <6>[ 131.470880] OOM killer enabled.
12041 13:25:26.863382 <6>[ 131.474294] Restarting tasks ... done.
12042 13:25:26.870202 <5>[ 131.480158] random: crng reseeded on system resumption
12043 13:25:26.873421 <6>[ 131.486970] PM: suspend exit
12044 13:25:26.876899 rtcwake: write error
12045 13:25:26.883092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
12046 13:25:26.883966 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
12048 13:25:26.887199 rtcwake: assuming RTC uses UTC ...
12049 13:25:26.893070 rtcwake: wakeup from "freeze" using rtc0 at Wed Sep 6 13:25:36 2023
12050 13:25:26.905378 <6>[ 131.516147] PM: suspend entry (s2idle)
12051 13:25:26.908427 <6>[ 131.520215] Filesystems sync: 0.000 seconds
12052 13:25:26.915457 <6>[ 131.525261] Freezing user space processes
12053 13:25:26.921995 <6>[ 131.531246] Freezing user space processes completed (elapsed 0.001 seconds)
12054 13:25:26.925615 <6>[ 131.538478] OOM killer disabled.
12055 13:25:26.931948 <6>[ 131.541959] Freezing remaining freezable tasks
12056 13:25:26.953262 <6>[ 131.560512] usb 1-1.1.4: new full-speed USB device number 84 using xhci-mtk
12057 13:25:27.034086 <3>[ 131.644922] usb 1-1.1.4: device descriptor read/64, error -32
12058 13:25:27.225946 <3>[ 131.836816] usb 1-1.1.4: device descriptor read/64, error -32
12059 13:25:27.421417 <6>[ 132.028655] usb 1-1.1.4: new full-speed USB device number 85 using xhci-mtk
12060 13:25:27.505913 <3>[ 132.116568] usb 1-1.1.4: device descriptor read/64, error -32
12061 13:25:27.698199 <3>[ 132.309028] usb 1-1.1.4: device descriptor read/64, error -32
12062 13:25:27.810267 <6>[ 132.420683] usb 1-1.1-port4: attempt power cycle
12063 13:25:28.421661 <6>[ 133.028703] usb 1-1.1.4: new full-speed USB device number 86 using xhci-mtk
12064 13:25:28.427749 <4>[ 133.036374] usb 1-1.1.4: Device not responding to setup address.
12065 13:25:28.638241 <4>[ 133.248702] usb 1-1.1.4: Device not responding to setup address.
12066 13:25:28.849923 <3>[ 133.460520] usb 1-1.1.4: device not accepting address 86, error -71
12067 13:25:28.937357 <6>[ 133.545002] usb 1-1.1.4: new full-speed USB device number 87 using xhci-mtk
12068 13:25:28.943807 <4>[ 133.552509] usb 1-1.1.4: Device not responding to setup address.
12069 13:25:29.153780 <4>[ 133.765112] usb 1-1.1.4: Device not responding to setup address.
12070 13:25:29.365637 <3>[ 133.976821] usb 1-1.1.4: device not accepting address 87, error -71
12071 13:25:29.372347 <3>[ 133.983673] usb 1-1.1-port4: unable to enumerate USB device
12072 13:25:29.388915 <6>[ 133.996645] Freezing remaining freezable tasks completed (elapsed 2.449 seconds)
12073 13:25:29.395848 <6>[ 134.004343] printk: Suspending console(s) (use no_console_suspend to debug)
12074 13:25:32.699601 <3>[ 137.044696] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
12075 13:25:32.712887 <3>[ 137.044729] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
12076 13:25:32.719371 <3>[ 137.044774] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
12077 13:25:32.725712 <3>[ 137.044817] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
12078 13:25:32.735986 <3>[ 137.045079] PM: Some devices failed to suspend, or early wake event detected
12079 13:25:32.739090 <6>[ 137.351076] OOM killer enabled.
12080 13:25:32.746690 <6>[ 137.354491] Restarting tasks ... done.
12081 13:25:32.749873 <5>[ 137.362239] random: crng reseeded on system resumption
12082 13:25:32.755218 <6>[ 137.369846] PM: suspend exit
12083 13:25:32.758456 rtcwake: write error
12084 13:25:32.767088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
12085 13:25:32.767978 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
12087 13:25:32.770432 + set +x
12088 13:25:32.773944 <LAVA_SIGNAL_ENDRUN 0_sleep 11445605_1.5.2.3.1>
12089 13:25:32.774501 <LAVA_TEST_RUNNER EXIT>
12090 13:25:32.775219 Received signal: <ENDRUN> 0_sleep 11445605_1.5.2.3.1
12091 13:25:32.775647 Ending use of test pattern.
12092 13:25:32.775988 Ending test lava.0_sleep (11445605_1.5.2.3.1), duration 115.36
12094 13:25:32.777197 ok: lava_test_shell seems to have completed
12095 13:25:32.778236 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
12096 13:25:32.778773 end: 3.1 lava-test-shell (duration 00:01:56) [common]
12097 13:25:32.779250 end: 3 lava-test-retry (duration 00:01:56) [common]
12098 13:25:32.779713 start: 4 finalize (timeout 00:05:34) [common]
12099 13:25:32.780198 start: 4.1 power-off (timeout 00:00:30) [common]
12100 13:25:32.781022 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
12101 13:25:32.860913 >> Command sent successfully.
12102 13:25:32.864463 Returned 0 in 0 seconds
12103 13:25:32.965361 end: 4.1 power-off (duration 00:00:00) [common]
12105 13:25:32.967271 start: 4.2 read-feedback (timeout 00:05:34) [common]
12106 13:25:32.968597 Listened to connection for namespace 'common' for up to 1s
12108 13:25:32.969949 Listened to connection for namespace 'common' for up to 1s
12109 13:25:33.969266 Finalising connection for namespace 'common'
12110 13:25:33.969976 Disconnecting from shell: Finalise
12111 13:25:34.071086 end: 4.2 read-feedback (duration 00:00:01) [common]
12112 13:25:34.071816 end: 4 finalize (duration 00:00:01) [common]
12113 13:25:34.072773 Cleaning after the job
12114 13:25:34.073395 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11445605/tftp-deploy-guggq_nz/ramdisk
12115 13:25:34.119131 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11445605/tftp-deploy-guggq_nz/kernel
12116 13:25:34.146694 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11445605/tftp-deploy-guggq_nz/dtb
12117 13:25:34.146926 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11445605/tftp-deploy-guggq_nz/modules
12118 13:25:34.153570 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11445605
12119 13:25:34.322451 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11445605
12120 13:25:34.322862 Job finished correctly