Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 35
- Boot result: PASS
- Warnings: 1
- Errors: 1
- Kernel Warnings: 65
1 13:20:24.303328 lava-dispatcher, installed at version: 2023.06
2 13:20:24.303545 start: 0 validate
3 13:20:24.303679 Start time: 2023-09-06 13:20:24.303670+00:00 (UTC)
4 13:20:24.303815 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:20:24.304004 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:20:24.574474 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:20:24.575270 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4-14-g09ffd7fb38ff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:21:09.088601 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:21:09.089346 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4-14-g09ffd7fb38ff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:21:09.342225 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:21:09.342925 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4-14-g09ffd7fb38ff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:21:12.600992 validate duration: 48.30
14 13:21:12.602261 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:21:12.602801 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:21:12.603298 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:21:12.603967 Not decompressing ramdisk as can be used compressed.
18 13:21:12.604442 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 13:21:12.604817 saving as /var/lib/lava/dispatcher/tmp/11445616/tftp-deploy-92azwfrb/ramdisk/rootfs.cpio.gz
20 13:21:12.605178 total size: 26246609 (25 MB)
21 13:21:12.866077 progress 0 % (0 MB)
22 13:21:12.873340 progress 5 % (1 MB)
23 13:21:12.880209 progress 10 % (2 MB)
24 13:21:12.887184 progress 15 % (3 MB)
25 13:21:12.894007 progress 20 % (5 MB)
26 13:21:12.900776 progress 25 % (6 MB)
27 13:21:12.907541 progress 30 % (7 MB)
28 13:21:12.914322 progress 35 % (8 MB)
29 13:21:12.921107 progress 40 % (10 MB)
30 13:21:12.927888 progress 45 % (11 MB)
31 13:21:12.934727 progress 50 % (12 MB)
32 13:21:12.941550 progress 55 % (13 MB)
33 13:21:12.948562 progress 60 % (15 MB)
34 13:21:12.955375 progress 65 % (16 MB)
35 13:21:12.962261 progress 70 % (17 MB)
36 13:21:12.969099 progress 75 % (18 MB)
37 13:21:12.975943 progress 80 % (20 MB)
38 13:21:12.982826 progress 85 % (21 MB)
39 13:21:12.989556 progress 90 % (22 MB)
40 13:21:12.996303 progress 95 % (23 MB)
41 13:21:13.002970 progress 100 % (25 MB)
42 13:21:13.003220 25 MB downloaded in 0.40 s (62.88 MB/s)
43 13:21:13.003375 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:21:13.003616 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:21:13.003706 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:21:13.003789 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:21:13.003955 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4-14-g09ffd7fb38ff/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:21:13.004041 saving as /var/lib/lava/dispatcher/tmp/11445616/tftp-deploy-92azwfrb/kernel/Image
50 13:21:13.004102 total size: 49220096 (46 MB)
51 13:21:13.004162 No compression specified
52 13:21:13.005268 progress 0 % (0 MB)
53 13:21:13.017935 progress 5 % (2 MB)
54 13:21:13.030704 progress 10 % (4 MB)
55 13:21:13.043535 progress 15 % (7 MB)
56 13:21:13.056392 progress 20 % (9 MB)
57 13:21:13.069349 progress 25 % (11 MB)
58 13:21:13.082124 progress 30 % (14 MB)
59 13:21:13.095047 progress 35 % (16 MB)
60 13:21:13.107779 progress 40 % (18 MB)
61 13:21:13.120542 progress 45 % (21 MB)
62 13:21:13.133498 progress 50 % (23 MB)
63 13:21:13.146227 progress 55 % (25 MB)
64 13:21:13.158847 progress 60 % (28 MB)
65 13:21:13.171661 progress 65 % (30 MB)
66 13:21:13.184482 progress 70 % (32 MB)
67 13:21:13.197324 progress 75 % (35 MB)
68 13:21:13.210266 progress 80 % (37 MB)
69 13:21:13.223035 progress 85 % (39 MB)
70 13:21:13.235754 progress 90 % (42 MB)
71 13:21:13.248322 progress 95 % (44 MB)
72 13:21:13.260975 progress 100 % (46 MB)
73 13:21:13.261140 46 MB downloaded in 0.26 s (182.62 MB/s)
74 13:21:13.261297 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:21:13.261528 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:21:13.261615 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:21:13.261704 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:21:13.261845 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4-14-g09ffd7fb38ff/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:21:13.261915 saving as /var/lib/lava/dispatcher/tmp/11445616/tftp-deploy-92azwfrb/dtb/mt8192-asurada-spherion-r0.dtb
81 13:21:13.261976 total size: 47278 (0 MB)
82 13:21:13.262036 No compression specified
83 13:21:13.263176 progress 69 % (0 MB)
84 13:21:13.263454 progress 100 % (0 MB)
85 13:21:13.263610 0 MB downloaded in 0.00 s (27.63 MB/s)
86 13:21:13.263732 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:21:13.263993 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:21:13.264077 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:21:13.264160 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:21:13.264272 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4-14-g09ffd7fb38ff/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:21:13.264339 saving as /var/lib/lava/dispatcher/tmp/11445616/tftp-deploy-92azwfrb/modules/modules.tar
93 13:21:13.264399 total size: 8610736 (8 MB)
94 13:21:13.264459 Using unxz to decompress xz
95 13:21:13.268827 progress 0 % (0 MB)
96 13:21:13.290043 progress 5 % (0 MB)
97 13:21:13.313735 progress 10 % (0 MB)
98 13:21:13.343603 progress 15 % (1 MB)
99 13:21:13.372616 progress 20 % (1 MB)
100 13:21:13.397079 progress 25 % (2 MB)
101 13:21:13.420969 progress 30 % (2 MB)
102 13:21:13.445593 progress 35 % (2 MB)
103 13:21:13.472526 progress 40 % (3 MB)
104 13:21:13.499173 progress 45 % (3 MB)
105 13:21:13.524920 progress 50 % (4 MB)
106 13:21:13.550882 progress 55 % (4 MB)
107 13:21:13.576063 progress 60 % (4 MB)
108 13:21:13.600788 progress 65 % (5 MB)
109 13:21:13.624380 progress 70 % (5 MB)
110 13:21:13.652124 progress 75 % (6 MB)
111 13:21:13.676281 progress 80 % (6 MB)
112 13:21:13.702487 progress 85 % (7 MB)
113 13:21:13.727613 progress 90 % (7 MB)
114 13:21:13.753421 progress 95 % (7 MB)
115 13:21:13.779747 progress 100 % (8 MB)
116 13:21:13.785686 8 MB downloaded in 0.52 s (15.75 MB/s)
117 13:21:13.785945 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:21:13.786206 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:21:13.786301 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:21:13.786398 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:21:13.786480 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:21:13.786572 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:21:13.786796 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1
125 13:21:13.786932 makedir: /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin
126 13:21:13.787037 makedir: /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/tests
127 13:21:13.787136 makedir: /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/results
128 13:21:13.787255 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-add-keys
129 13:21:13.787401 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-add-sources
130 13:21:13.787540 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-background-process-start
131 13:21:13.787674 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-background-process-stop
132 13:21:13.787802 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-common-functions
133 13:21:13.787974 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-echo-ipv4
134 13:21:13.788152 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-install-packages
135 13:21:13.788284 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-installed-packages
136 13:21:13.788410 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-os-build
137 13:21:13.788536 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-probe-channel
138 13:21:13.788661 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-probe-ip
139 13:21:13.788785 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-target-ip
140 13:21:13.788914 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-target-mac
141 13:21:13.789038 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-target-storage
142 13:21:13.789168 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-test-case
143 13:21:13.789292 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-test-event
144 13:21:13.789416 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-test-feedback
145 13:21:13.789540 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-test-raise
146 13:21:13.789666 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-test-reference
147 13:21:13.789793 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-test-runner
148 13:21:13.789917 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-test-set
149 13:21:13.790088 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-test-shell
150 13:21:13.790216 Updating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-install-packages (oe)
151 13:21:13.790376 Updating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/bin/lava-installed-packages (oe)
152 13:21:13.790501 Creating /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/environment
153 13:21:13.790606 LAVA metadata
154 13:21:13.790680 - LAVA_JOB_ID=11445616
155 13:21:13.790744 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:21:13.790846 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:21:13.790912 skipped lava-vland-overlay
158 13:21:13.790986 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:21:13.791067 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:21:13.791128 skipped lava-multinode-overlay
161 13:21:13.791200 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:21:13.791282 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:21:13.791359 Loading test definitions
164 13:21:13.791448 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:21:13.791521 Using /lava-11445616 at stage 0
166 13:21:13.791834 uuid=11445616_1.5.2.3.1 testdef=None
167 13:21:13.791948 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:21:13.792085 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:21:13.792609 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:21:13.792825 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:21:13.793443 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:21:13.793671 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:21:13.794278 runner path: /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 11445616_1.5.2.3.1
176 13:21:13.794432 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:21:13.794636 Creating lava-test-runner.conf files
179 13:21:13.794698 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11445616/lava-overlay-ih6_doy1/lava-11445616/0 for stage 0
180 13:21:13.794788 - 0_v4l2-compliance-mtk-vcodec-enc
181 13:21:13.794885 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:21:13.794973 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:21:13.801854 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:21:13.801967 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:21:13.802053 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:21:13.802138 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:21:13.802223 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:21:14.525089 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 13:21:14.525478 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 13:21:14.525596 extracting modules file /var/lib/lava/dispatcher/tmp/11445616/tftp-deploy-92azwfrb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11445616/extract-overlay-ramdisk-tght_hso/ramdisk
191 13:21:14.758257 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:21:14.758439 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 13:21:14.758546 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11445616/compress-overlay-v9624wk9/overlay-1.5.2.4.tar.gz to ramdisk
194 13:21:14.758619 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11445616/compress-overlay-v9624wk9/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11445616/extract-overlay-ramdisk-tght_hso/ramdisk
195 13:21:14.765367 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:21:14.765488 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 13:21:14.765581 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:21:14.765668 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 13:21:14.765746 Building ramdisk /var/lib/lava/dispatcher/tmp/11445616/extract-overlay-ramdisk-tght_hso/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11445616/extract-overlay-ramdisk-tght_hso/ramdisk
200 13:21:15.436280 >> 228284 blocks
201 13:21:19.349710 rename /var/lib/lava/dispatcher/tmp/11445616/extract-overlay-ramdisk-tght_hso/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11445616/tftp-deploy-92azwfrb/ramdisk/ramdisk.cpio.gz
202 13:21:19.350190 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 13:21:19.350339 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 13:21:19.350474 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 13:21:19.350616 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11445616/tftp-deploy-92azwfrb/kernel/Image'
206 13:21:32.470005 Returned 0 in 13 seconds
207 13:21:32.570662 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11445616/tftp-deploy-92azwfrb/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11445616/tftp-deploy-92azwfrb/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11445616/tftp-deploy-92azwfrb/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11445616/tftp-deploy-92azwfrb/kernel/image.itb
208 13:21:33.192421 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:21:33.192795 output: Created: Wed Sep 6 14:21:33 2023
210 13:21:33.192872 output: Image 0 (kernel-1)
211 13:21:33.192938 output: Description:
212 13:21:33.192998 output: Created: Wed Sep 6 14:21:33 2023
213 13:21:33.193059 output: Type: Kernel Image
214 13:21:33.193121 output: Compression: lzma compressed
215 13:21:33.193179 output: Data Size: 11038222 Bytes = 10779.51 KiB = 10.53 MiB
216 13:21:33.193238 output: Architecture: AArch64
217 13:21:33.193298 output: OS: Linux
218 13:21:33.193353 output: Load Address: 0x00000000
219 13:21:33.193408 output: Entry Point: 0x00000000
220 13:21:33.193464 output: Hash algo: crc32
221 13:21:33.193526 output: Hash value: eae831c7
222 13:21:33.193578 output: Image 1 (fdt-1)
223 13:21:33.193630 output: Description: mt8192-asurada-spherion-r0
224 13:21:33.193682 output: Created: Wed Sep 6 14:21:33 2023
225 13:21:33.193735 output: Type: Flat Device Tree
226 13:21:33.193786 output: Compression: uncompressed
227 13:21:33.193839 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 13:21:33.193891 output: Architecture: AArch64
229 13:21:33.193943 output: Hash algo: crc32
230 13:21:33.193995 output: Hash value: cc4352de
231 13:21:33.194047 output: Image 2 (ramdisk-1)
232 13:21:33.194099 output: Description: unavailable
233 13:21:33.194151 output: Created: Wed Sep 6 14:21:33 2023
234 13:21:33.194203 output: Type: RAMDisk Image
235 13:21:33.194255 output: Compression: Unknown Compression
236 13:21:33.194306 output: Data Size: 39340497 Bytes = 38418.45 KiB = 37.52 MiB
237 13:21:33.194358 output: Architecture: AArch64
238 13:21:33.194410 output: OS: Linux
239 13:21:33.194461 output: Load Address: unavailable
240 13:21:33.194512 output: Entry Point: unavailable
241 13:21:33.194564 output: Hash algo: crc32
242 13:21:33.194614 output: Hash value: 93f8f617
243 13:21:33.194665 output: Default Configuration: 'conf-1'
244 13:21:33.194716 output: Configuration 0 (conf-1)
245 13:21:33.194768 output: Description: mt8192-asurada-spherion-r0
246 13:21:33.194819 output: Kernel: kernel-1
247 13:21:33.194870 output: Init Ramdisk: ramdisk-1
248 13:21:33.194922 output: FDT: fdt-1
249 13:21:33.194973 output: Loadables: kernel-1
250 13:21:33.195024 output:
251 13:21:33.195221 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 13:21:33.195318 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 13:21:33.195424 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 13:21:33.195531 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 13:21:33.195640 No LXC device requested
256 13:21:33.195750 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:21:33.195866 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 13:21:33.195971 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:21:33.196043 Checking files for TFTP limit of 4294967296 bytes.
260 13:21:33.196537 end: 1 tftp-deploy (duration 00:00:21) [common]
261 13:21:33.196639 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:21:33.196730 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:21:33.196849 substitutions:
264 13:21:33.196915 - {DTB}: 11445616/tftp-deploy-92azwfrb/dtb/mt8192-asurada-spherion-r0.dtb
265 13:21:33.196978 - {INITRD}: 11445616/tftp-deploy-92azwfrb/ramdisk/ramdisk.cpio.gz
266 13:21:33.197036 - {KERNEL}: 11445616/tftp-deploy-92azwfrb/kernel/Image
267 13:21:33.197092 - {LAVA_MAC}: None
268 13:21:33.197146 - {PRESEED_CONFIG}: None
269 13:21:33.197200 - {PRESEED_LOCAL}: None
270 13:21:33.197253 - {RAMDISK}: 11445616/tftp-deploy-92azwfrb/ramdisk/ramdisk.cpio.gz
271 13:21:33.197306 - {ROOT_PART}: None
272 13:21:33.197359 - {ROOT}: None
273 13:21:33.197411 - {SERVER_IP}: 192.168.201.1
274 13:21:33.197463 - {TEE}: None
275 13:21:33.197516 Parsed boot commands:
276 13:21:33.197567 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:21:33.197743 Parsed boot commands: tftpboot 192.168.201.1 11445616/tftp-deploy-92azwfrb/kernel/image.itb 11445616/tftp-deploy-92azwfrb/kernel/cmdline
278 13:21:33.197831 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:21:33.197917 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:21:33.198007 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:21:33.198090 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:21:33.198159 Not connected, no need to disconnect.
283 13:21:33.198230 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:21:33.198306 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:21:33.198372 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 13:21:33.202308 Setting prompt string to ['lava-test: # ']
287 13:21:33.202660 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:21:33.202764 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:21:33.202865 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:21:33.202952 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:21:33.203144 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
292 13:21:38.353737 >> Command sent successfully.
293 13:21:38.364179 Returned 0 in 5 seconds
294 13:21:38.465167 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 13:21:38.466701 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 13:21:38.467275 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 13:21:38.467755 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:21:38.468276 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:21:38.468720 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:21:38.470095 [Enter `^Ec?' for help]
302 13:21:38.632020
303 13:21:38.632554
304 13:21:38.633058 F0: 102B 0000
305 13:21:38.633485
306 13:21:38.633894 F3: 1001 0000 [0200]
307 13:21:38.634298
308 13:21:38.636078 F3: 1001 0000
309 13:21:38.636511
310 13:21:38.636954 F7: 102D 0000
311 13:21:38.637466
312 13:21:38.637882 F1: 0000 0000
313 13:21:38.638286
314 13:21:38.638974 V0: 0000 0000 [0001]
315 13:21:38.639329
316 13:21:38.639728 00: 0007 8000
317 13:21:38.640182
318 13:21:38.643021 01: 0000 0000
319 13:21:38.643536
320 13:21:38.643993 BP: 0C00 0209 [0000]
321 13:21:38.644400
322 13:21:38.646409 G0: 1182 0000
323 13:21:38.646870
324 13:21:38.647308 EC: 0000 0021 [4000]
325 13:21:38.647721
326 13:21:38.650157 S7: 0000 0000 [0000]
327 13:21:38.650589
328 13:21:38.651161 CC: 0000 0000 [0001]
329 13:21:38.651650
330 13:21:38.653326 T0: 0000 0040 [010F]
331 13:21:38.653761
332 13:21:38.654199 Jump to BL
333 13:21:38.654612
334 13:21:38.678710
335 13:21:38.679238
336 13:21:38.679684
337 13:21:38.686072 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 13:21:38.689593 ARM64: Exception handlers installed.
339 13:21:38.693064 ARM64: Testing exception
340 13:21:38.697228 ARM64: Done test exception
341 13:21:38.704729 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 13:21:38.711753 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 13:21:38.718887 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 13:21:38.729082 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 13:21:38.736301 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 13:21:38.746074 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 13:21:38.756463 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 13:21:38.762946 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 13:21:38.781001 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 13:21:38.783939 WDT: Last reset was cold boot
351 13:21:38.787718 SPI1(PAD0) initialized at 2873684 Hz
352 13:21:38.791332 SPI5(PAD0) initialized at 992727 Hz
353 13:21:38.794602 VBOOT: Loading verstage.
354 13:21:38.801207 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 13:21:38.803959 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 13:21:38.807267 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 13:21:38.811060 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 13:21:38.818860 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 13:21:38.825564 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 13:21:38.836396 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 13:21:38.836837
362 13:21:38.837174
363 13:21:38.846248 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 13:21:38.849656 ARM64: Exception handlers installed.
365 13:21:38.852558 ARM64: Testing exception
366 13:21:38.852984 ARM64: Done test exception
367 13:21:38.859995 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 13:21:38.863232 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 13:21:38.877297 Probing TPM: . done!
370 13:21:38.877741 TPM ready after 0 ms
371 13:21:38.884701 Connected to device vid:did:rid of 1ae0:0028:00
372 13:21:38.891773 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 13:21:38.949865 Initialized TPM device CR50 revision 0
374 13:21:38.961088 tlcl_send_startup: Startup return code is 0
375 13:21:38.961713 TPM: setup succeeded
376 13:21:38.972987 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 13:21:38.982332 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 13:21:38.993348 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 13:21:39.003901 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 13:21:39.008011 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 13:21:39.012673 in-header: 03 07 00 00 08 00 00 00
382 13:21:39.016035 in-data: aa e4 47 04 13 02 00 00
383 13:21:39.019173 Chrome EC: UHEPI supported
384 13:21:39.026487 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 13:21:39.030400 in-header: 03 95 00 00 08 00 00 00
386 13:21:39.033584 in-data: 18 20 20 08 00 00 00 00
387 13:21:39.034204 Phase 1
388 13:21:39.037234 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 13:21:39.044626 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 13:21:39.048508 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 13:21:39.052307 Recovery requested (1009000e)
392 13:21:39.061739 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 13:21:39.067019 tlcl_extend: response is 0
394 13:21:39.076107 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 13:21:39.081293 tlcl_extend: response is 0
396 13:21:39.088542 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 13:21:39.108227 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 13:21:39.115227 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 13:21:39.115716
400 13:21:39.116222
401 13:21:39.124938 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 13:21:39.128207 ARM64: Exception handlers installed.
403 13:21:39.131670 ARM64: Testing exception
404 13:21:39.132138 ARM64: Done test exception
405 13:21:39.153940 pmic_efuse_setting: Set efuses in 11 msecs
406 13:21:39.156986 pmwrap_interface_init: Select PMIF_VLD_RDY
407 13:21:39.163807 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 13:21:39.167157 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 13:21:39.174576 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 13:21:39.178092 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 13:21:39.181868 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 13:21:39.188587 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 13:21:39.193702 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 13:21:39.196666 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 13:21:39.200324 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 13:21:39.207155 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 13:21:39.210799 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 13:21:39.214741 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 13:21:39.221800 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 13:21:39.225183 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 13:21:39.233154 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 13:21:39.236509 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 13:21:39.244037 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 13:21:39.247978 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 13:21:39.254458 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 13:21:39.262543 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 13:21:39.265575 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 13:21:39.273367 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 13:21:39.276546 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 13:21:39.284202 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 13:21:39.287532 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 13:21:39.295255 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 13:21:39.298351 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 13:21:39.302379 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 13:21:39.309236 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 13:21:39.312957 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 13:21:39.317198 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 13:21:39.324295 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 13:21:39.327587 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 13:21:39.331503 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 13:21:39.338240 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 13:21:39.342069 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 13:21:39.349316 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 13:21:39.353473 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 13:21:39.356491 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 13:21:39.359885 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 13:21:39.367824 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 13:21:39.370969 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 13:21:39.374742 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 13:21:39.378618 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 13:21:39.382499 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 13:21:39.389833 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 13:21:39.393373 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 13:21:39.396839 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 13:21:39.400718 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 13:21:39.404277 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 13:21:39.407882 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 13:21:39.418401 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 13:21:39.426351 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 13:21:39.429964 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 13:21:39.436605 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 13:21:39.447732 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 13:21:39.451659 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 13:21:39.454998 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:21:39.458707 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 13:21:39.467777 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x2b
467 13:21:39.470713 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 13:21:39.479203 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
469 13:21:39.482662 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 13:21:39.491402 [RTC]rtc_get_frequency_meter,154: input=15, output=852
471 13:21:39.500605 [RTC]rtc_get_frequency_meter,154: input=7, output=725
472 13:21:39.510395 [RTC]rtc_get_frequency_meter,154: input=11, output=789
473 13:21:39.519770 [RTC]rtc_get_frequency_meter,154: input=13, output=820
474 13:21:39.529578 [RTC]rtc_get_frequency_meter,154: input=12, output=805
475 13:21:39.539062 [RTC]rtc_get_frequency_meter,154: input=11, output=789
476 13:21:39.548419 [RTC]rtc_get_frequency_meter,154: input=12, output=804
477 13:21:39.552132 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
478 13:21:39.559488 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
479 13:21:39.563734 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 13:21:39.567454 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 13:21:39.570817 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 13:21:39.575029 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 13:21:39.579016 ADC[4]: Raw value=905172 ID=7
484 13:21:39.579483 ADC[3]: Raw value=213916 ID=1
485 13:21:39.582111 RAM Code: 0x71
486 13:21:39.587412 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 13:21:39.590422 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 13:21:39.601451 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 13:21:39.604697 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 13:21:39.608021 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 13:21:39.611757 in-header: 03 07 00 00 08 00 00 00
492 13:21:39.615536 in-data: aa e4 47 04 13 02 00 00
493 13:21:39.618978 Chrome EC: UHEPI supported
494 13:21:39.626238 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 13:21:39.629924 in-header: 03 95 00 00 08 00 00 00
496 13:21:39.634045 in-data: 18 20 20 08 00 00 00 00
497 13:21:39.637212 MRC: failed to locate region type 0.
498 13:21:39.640933 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 13:21:39.645034 DRAM-K: Running full calibration
500 13:21:39.652504 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 13:21:39.652934 header.status = 0x0
502 13:21:39.656312 header.version = 0x6 (expected: 0x6)
503 13:21:39.659718 header.size = 0xd00 (expected: 0xd00)
504 13:21:39.663273 header.flags = 0x0
505 13:21:39.666677 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 13:21:39.686828 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
507 13:21:39.694242 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 13:21:39.694436 dram_init: ddr_geometry: 2
509 13:21:39.697582 [EMI] MDL number = 2
510 13:21:39.701566 [EMI] Get MDL freq = 0
511 13:21:39.701758 dram_init: ddr_type: 0
512 13:21:39.705319 is_discrete_lpddr4: 1
513 13:21:39.708914 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 13:21:39.709098
515 13:21:39.709262
516 13:21:39.709440 [Bian_co] ETT version 0.0.0.1
517 13:21:39.716497 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 13:21:39.716679
519 13:21:39.720055 dramc_set_vcore_voltage set vcore to 650000
520 13:21:39.720244 Read voltage for 800, 4
521 13:21:39.722909 Vio18 = 0
522 13:21:39.723093 Vcore = 650000
523 13:21:39.723256 Vdram = 0
524 13:21:39.723426 Vddq = 0
525 13:21:39.726742 Vmddr = 0
526 13:21:39.726942 dram_init: config_dvfs: 1
527 13:21:39.733122 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 13:21:39.740985 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 13:21:39.743700 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 13:21:39.748275 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 13:21:39.750970 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 13:21:39.755037 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 13:21:39.755430 MEM_TYPE=3, freq_sel=18
534 13:21:39.759276 sv_algorithm_assistance_LP4_1600
535 13:21:39.762518 ============ PULL DRAM RESETB DOWN ============
536 13:21:39.768991 ========== PULL DRAM RESETB DOWN end =========
537 13:21:39.772003 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 13:21:39.775753 ===================================
539 13:21:39.779196 LPDDR4 DRAM CONFIGURATION
540 13:21:39.783336 ===================================
541 13:21:39.783885 EX_ROW_EN[0] = 0x0
542 13:21:39.786741 EX_ROW_EN[1] = 0x0
543 13:21:39.787283 LP4Y_EN = 0x0
544 13:21:39.789808 WORK_FSP = 0x0
545 13:21:39.790353 WL = 0x2
546 13:21:39.793489 RL = 0x2
547 13:21:39.794015 BL = 0x2
548 13:21:39.796416 RPST = 0x0
549 13:21:39.796842 RD_PRE = 0x0
550 13:21:39.799936 WR_PRE = 0x1
551 13:21:39.800488 WR_PST = 0x0
552 13:21:39.803029 DBI_WR = 0x0
553 13:21:39.803452 DBI_RD = 0x0
554 13:21:39.806488 OTF = 0x1
555 13:21:39.810095 ===================================
556 13:21:39.813649 ===================================
557 13:21:39.814179 ANA top config
558 13:21:39.816402 ===================================
559 13:21:39.820053 DLL_ASYNC_EN = 0
560 13:21:39.822963 ALL_SLAVE_EN = 1
561 13:21:39.826266 NEW_RANK_MODE = 1
562 13:21:39.826797 DLL_IDLE_MODE = 1
563 13:21:39.829762 LP45_APHY_COMB_EN = 1
564 13:21:39.833093 TX_ODT_DIS = 1
565 13:21:39.836906 NEW_8X_MODE = 1
566 13:21:39.839360 ===================================
567 13:21:39.842978 ===================================
568 13:21:39.846539 data_rate = 1600
569 13:21:39.846959 CKR = 1
570 13:21:39.849552 DQ_P2S_RATIO = 8
571 13:21:39.853067 ===================================
572 13:21:39.856143 CA_P2S_RATIO = 8
573 13:21:39.859649 DQ_CA_OPEN = 0
574 13:21:39.863325 DQ_SEMI_OPEN = 0
575 13:21:39.863748 CA_SEMI_OPEN = 0
576 13:21:39.866102 CA_FULL_RATE = 0
577 13:21:39.870212 DQ_CKDIV4_EN = 1
578 13:21:39.873133 CA_CKDIV4_EN = 1
579 13:21:39.876585 CA_PREDIV_EN = 0
580 13:21:39.880046 PH8_DLY = 0
581 13:21:39.880573 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 13:21:39.883097 DQ_AAMCK_DIV = 4
583 13:21:39.886997 CA_AAMCK_DIV = 4
584 13:21:39.889560 CA_ADMCK_DIV = 4
585 13:21:39.893006 DQ_TRACK_CA_EN = 0
586 13:21:39.896156 CA_PICK = 800
587 13:21:39.896675 CA_MCKIO = 800
588 13:21:39.899883 MCKIO_SEMI = 0
589 13:21:39.903571 PLL_FREQ = 3068
590 13:21:39.908037 DQ_UI_PI_RATIO = 32
591 13:21:39.911204 CA_UI_PI_RATIO = 0
592 13:21:39.915411 ===================================
593 13:21:39.916002 ===================================
594 13:21:39.918338 memory_type:LPDDR4
595 13:21:39.921744 GP_NUM : 10
596 13:21:39.922166 SRAM_EN : 1
597 13:21:39.925801 MD32_EN : 0
598 13:21:39.929979 ===================================
599 13:21:39.930501 [ANA_INIT] >>>>>>>>>>>>>>
600 13:21:39.933000 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 13:21:39.937005 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 13:21:39.940191 ===================================
603 13:21:39.943987 data_rate = 1600,PCW = 0X7600
604 13:21:39.946955 ===================================
605 13:21:39.950464 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 13:21:39.953709 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 13:21:39.960605 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 13:21:39.963618 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 13:21:39.966528 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 13:21:39.970594 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 13:21:39.973270 [ANA_INIT] flow start
612 13:21:39.976694 [ANA_INIT] PLL >>>>>>>>
613 13:21:39.977116 [ANA_INIT] PLL <<<<<<<<
614 13:21:39.980040 [ANA_INIT] MIDPI >>>>>>>>
615 13:21:39.983327 [ANA_INIT] MIDPI <<<<<<<<
616 13:21:39.986622 [ANA_INIT] DLL >>>>>>>>
617 13:21:39.987101 [ANA_INIT] flow end
618 13:21:39.989782 ============ LP4 DIFF to SE enter ============
619 13:21:39.997031 ============ LP4 DIFF to SE exit ============
620 13:21:39.997596 [ANA_INIT] <<<<<<<<<<<<<
621 13:21:39.999832 [Flow] Enable top DCM control >>>>>
622 13:21:40.003352 [Flow] Enable top DCM control <<<<<
623 13:21:40.007092 Enable DLL master slave shuffle
624 13:21:40.013300 ==============================================================
625 13:21:40.013786 Gating Mode config
626 13:21:40.019886 ==============================================================
627 13:21:40.023659 Config description:
628 13:21:40.030318 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 13:21:40.036497 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 13:21:40.043032 SELPH_MODE 0: By rank 1: By Phase
631 13:21:40.050051 ==============================================================
632 13:21:40.050134 GAT_TRACK_EN = 1
633 13:21:40.052580 RX_GATING_MODE = 2
634 13:21:40.055792 RX_GATING_TRACK_MODE = 2
635 13:21:40.059502 SELPH_MODE = 1
636 13:21:40.062616 PICG_EARLY_EN = 1
637 13:21:40.066124 VALID_LAT_VALUE = 1
638 13:21:40.073267 ==============================================================
639 13:21:40.076622 Enter into Gating configuration >>>>
640 13:21:40.079871 Exit from Gating configuration <<<<
641 13:21:40.082757 Enter into DVFS_PRE_config >>>>>
642 13:21:40.092877 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 13:21:40.096329 Exit from DVFS_PRE_config <<<<<
644 13:21:40.099676 Enter into PICG configuration >>>>
645 13:21:40.102766 Exit from PICG configuration <<<<
646 13:21:40.105752 [RX_INPUT] configuration >>>>>
647 13:21:40.105836 [RX_INPUT] configuration <<<<<
648 13:21:40.112435 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 13:21:40.119139 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 13:21:40.123353 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 13:21:40.129108 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 13:21:40.135652 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 13:21:40.142420 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 13:21:40.145932 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 13:21:40.149566 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 13:21:40.155873 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 13:21:40.159153 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 13:21:40.162563 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 13:21:40.169217 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 13:21:40.172657 ===================================
661 13:21:40.172770 LPDDR4 DRAM CONFIGURATION
662 13:21:40.176047 ===================================
663 13:21:40.179182 EX_ROW_EN[0] = 0x0
664 13:21:40.179297 EX_ROW_EN[1] = 0x0
665 13:21:40.182512 LP4Y_EN = 0x0
666 13:21:40.182623 WORK_FSP = 0x0
667 13:21:40.185899 WL = 0x2
668 13:21:40.186036 RL = 0x2
669 13:21:40.190120 BL = 0x2
670 13:21:40.192350 RPST = 0x0
671 13:21:40.192442 RD_PRE = 0x0
672 13:21:40.196535 WR_PRE = 0x1
673 13:21:40.196613 WR_PST = 0x0
674 13:21:40.199354 DBI_WR = 0x0
675 13:21:40.199450 DBI_RD = 0x0
676 13:21:40.202864 OTF = 0x1
677 13:21:40.205926 ===================================
678 13:21:40.209000 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 13:21:40.212721 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 13:21:40.216230 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 13:21:40.219264 ===================================
682 13:21:40.222048 LPDDR4 DRAM CONFIGURATION
683 13:21:40.225684 ===================================
684 13:21:40.229046 EX_ROW_EN[0] = 0x10
685 13:21:40.229145 EX_ROW_EN[1] = 0x0
686 13:21:40.232761 LP4Y_EN = 0x0
687 13:21:40.232836 WORK_FSP = 0x0
688 13:21:40.235872 WL = 0x2
689 13:21:40.235975 RL = 0x2
690 13:21:40.238907 BL = 0x2
691 13:21:40.238977 RPST = 0x0
692 13:21:40.241973 RD_PRE = 0x0
693 13:21:40.242042 WR_PRE = 0x1
694 13:21:40.246036 WR_PST = 0x0
695 13:21:40.249121 DBI_WR = 0x0
696 13:21:40.249221 DBI_RD = 0x0
697 13:21:40.252210 OTF = 0x1
698 13:21:40.255623 ===================================
699 13:21:40.258594 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 13:21:40.263703 nWR fixed to 40
701 13:21:40.267788 [ModeRegInit_LP4] CH0 RK0
702 13:21:40.267890 [ModeRegInit_LP4] CH0 RK1
703 13:21:40.270437 [ModeRegInit_LP4] CH1 RK0
704 13:21:40.273670 [ModeRegInit_LP4] CH1 RK1
705 13:21:40.273780 match AC timing 13
706 13:21:40.280385 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 13:21:40.283727 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 13:21:40.287991 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 13:21:40.293922 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 13:21:40.297433 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 13:21:40.297537 [EMI DOE] emi_dcm 0
712 13:21:40.303867 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 13:21:40.304010 ==
714 13:21:40.307212 Dram Type= 6, Freq= 0, CH_0, rank 0
715 13:21:40.310240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 13:21:40.310339 ==
717 13:21:40.316871 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 13:21:40.323515 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 13:21:40.332674 [CA 0] Center 38 (7~69) winsize 63
720 13:21:40.334797 [CA 1] Center 37 (6~68) winsize 63
721 13:21:40.338476 [CA 2] Center 34 (4~65) winsize 62
722 13:21:40.341337 [CA 3] Center 35 (4~66) winsize 63
723 13:21:40.345475 [CA 4] Center 33 (3~64) winsize 62
724 13:21:40.348278 [CA 5] Center 33 (3~64) winsize 62
725 13:21:40.348358
726 13:21:40.351233 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 13:21:40.351333
728 13:21:40.354823 [CATrainingPosCal] consider 1 rank data
729 13:21:40.358410 u2DelayCellTimex100 = 270/100 ps
730 13:21:40.361127 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
731 13:21:40.368387 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 13:21:40.371078 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 13:21:40.374520 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
734 13:21:40.378438 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 13:21:40.381820 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 13:21:40.381948
737 13:21:40.384808 CA PerBit enable=1, Macro0, CA PI delay=33
738 13:21:40.384909
739 13:21:40.388116 [CBTSetCACLKResult] CA Dly = 33
740 13:21:40.388216 CS Dly: 5 (0~36)
741 13:21:40.391530 ==
742 13:21:40.394333 Dram Type= 6, Freq= 0, CH_0, rank 1
743 13:21:40.397571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 13:21:40.397671 ==
745 13:21:40.401644 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 13:21:40.407384 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 13:21:40.417783 [CA 0] Center 38 (7~69) winsize 63
748 13:21:40.421772 [CA 1] Center 37 (7~68) winsize 62
749 13:21:40.424642 [CA 2] Center 35 (4~66) winsize 63
750 13:21:40.427941 [CA 3] Center 35 (4~66) winsize 63
751 13:21:40.431270 [CA 4] Center 34 (3~65) winsize 63
752 13:21:40.434695 [CA 5] Center 33 (3~64) winsize 62
753 13:21:40.434776
754 13:21:40.437632 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 13:21:40.437715
756 13:21:40.440899 [CATrainingPosCal] consider 2 rank data
757 13:21:40.444500 u2DelayCellTimex100 = 270/100 ps
758 13:21:40.447598 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
759 13:21:40.454065 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 13:21:40.457757 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 13:21:40.460978 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
762 13:21:40.464690 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 13:21:40.467493 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 13:21:40.467575
765 13:21:40.470936 CA PerBit enable=1, Macro0, CA PI delay=33
766 13:21:40.471019
767 13:21:40.474280 [CBTSetCACLKResult] CA Dly = 33
768 13:21:40.477621 CS Dly: 6 (0~38)
769 13:21:40.477703
770 13:21:40.480685 ----->DramcWriteLeveling(PI) begin...
771 13:21:40.480769 ==
772 13:21:40.484160 Dram Type= 6, Freq= 0, CH_0, rank 0
773 13:21:40.488024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 13:21:40.488173 ==
775 13:21:40.491888 Write leveling (Byte 0): 30 => 30
776 13:21:40.492016 Write leveling (Byte 1): 28 => 28
777 13:21:40.495797 DramcWriteLeveling(PI) end<-----
778 13:21:40.495878
779 13:21:40.495986 ==
780 13:21:40.499521 Dram Type= 6, Freq= 0, CH_0, rank 0
781 13:21:40.503110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 13:21:40.506164 ==
783 13:21:40.506246 [Gating] SW mode calibration
784 13:21:40.513068 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 13:21:40.519758 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 13:21:40.522851 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 13:21:40.529553 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 13:21:40.532733 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
789 13:21:40.536237 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:21:40.542796 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:21:40.546311 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:21:40.549368 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:21:40.557104 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:21:40.559092 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:21:40.562716 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:21:40.568909 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:21:40.572251 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:21:40.575590 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:21:40.582232 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:21:40.585547 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:21:40.589124 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:21:40.592546 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:21:40.599289 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 13:21:40.602512 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 13:21:40.606397 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:21:40.612253 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:21:40.615561 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:21:40.619374 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:21:40.625724 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:21:40.628880 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 13:21:40.631814 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 13:21:40.639009 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
813 13:21:40.642050 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
814 13:21:40.645370 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 13:21:40.652605 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 13:21:40.655100 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 13:21:40.658729 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 13:21:40.665110 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 13:21:40.668477 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
820 13:21:40.671986 0 10 8 | B1->B0 | 3434 2929 | 1 0 | (1 0) (1 1)
821 13:21:40.678637 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
822 13:21:40.681616 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:21:40.685625 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:21:40.691880 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 13:21:40.694973 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 13:21:40.698227 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 13:21:40.704864 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
828 13:21:40.708330 0 11 8 | B1->B0 | 2424 4343 | 0 0 | (0 0) (0 0)
829 13:21:40.712196 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
830 13:21:40.718251 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 13:21:40.722118 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 13:21:40.725171 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 13:21:40.731852 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 13:21:40.735256 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 13:21:40.738543 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 13:21:40.744956 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 13:21:40.748058 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 13:21:40.751622 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:21:40.754845 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:21:40.761562 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:21:40.765174 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:21:40.768448 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:21:40.774665 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:21:40.778684 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:21:40.781103 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:21:40.788626 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:21:40.791838 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:21:40.794960 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:21:40.801356 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:21:40.805032 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:21:40.808078 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 13:21:40.814763 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 13:21:40.818447 Total UI for P1: 0, mck2ui 16
854 13:21:40.821648 best dqsien dly found for B0: ( 0, 14, 4)
855 13:21:40.825277 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 13:21:40.827810 Total UI for P1: 0, mck2ui 16
857 13:21:40.831094 best dqsien dly found for B1: ( 0, 14, 8)
858 13:21:40.834751 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 13:21:40.838225 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 13:21:40.838307
861 13:21:40.842199 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 13:21:40.844411 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 13:21:40.848246 [Gating] SW calibration Done
864 13:21:40.848336 ==
865 13:21:40.851435 Dram Type= 6, Freq= 0, CH_0, rank 0
866 13:21:40.854917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 13:21:40.854999 ==
868 13:21:40.858566 RX Vref Scan: 0
869 13:21:40.858673
870 13:21:40.858767 RX Vref 0 -> 0, step: 1
871 13:21:40.858861
872 13:21:40.862038 RX Delay -130 -> 252, step: 16
873 13:21:40.868630 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
874 13:21:40.872572 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 13:21:40.875245 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 13:21:40.878841 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 13:21:40.882358 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 13:21:40.885349 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 13:21:40.891744 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 13:21:40.894951 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 13:21:40.898773 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 13:21:40.902137 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
883 13:21:40.908356 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 13:21:40.911660 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 13:21:40.915015 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 13:21:40.918126 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 13:21:40.921465 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 13:21:40.928729 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 13:21:40.928810 ==
890 13:21:40.931480 Dram Type= 6, Freq= 0, CH_0, rank 0
891 13:21:40.935501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 13:21:40.935583 ==
893 13:21:40.935648 DQS Delay:
894 13:21:40.938323 DQS0 = 0, DQS1 = 0
895 13:21:40.938407 DQM Delay:
896 13:21:40.941974 DQM0 = 89, DQM1 = 76
897 13:21:40.942055 DQ Delay:
898 13:21:40.944855 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
899 13:21:40.948147 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
900 13:21:40.951625 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =69
901 13:21:40.954713 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 13:21:40.954795
903 13:21:40.954860
904 13:21:40.954920 ==
905 13:21:40.958506 Dram Type= 6, Freq= 0, CH_0, rank 0
906 13:21:40.962266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 13:21:40.962348 ==
908 13:21:40.964789
909 13:21:40.964870
910 13:21:40.964935 TX Vref Scan disable
911 13:21:40.968203 == TX Byte 0 ==
912 13:21:40.971659 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
913 13:21:40.975264 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
914 13:21:40.978004 == TX Byte 1 ==
915 13:21:40.981255 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
916 13:21:40.985062 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
917 13:21:40.985144 ==
918 13:21:40.988664 Dram Type= 6, Freq= 0, CH_0, rank 0
919 13:21:40.995060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 13:21:40.995142 ==
921 13:21:41.007247 TX Vref=22, minBit 0, minWin=27, winSum=439
922 13:21:41.010201 TX Vref=24, minBit 2, minWin=27, winSum=444
923 13:21:41.013578 TX Vref=26, minBit 3, minWin=27, winSum=449
924 13:21:41.016603 TX Vref=28, minBit 0, minWin=27, winSum=446
925 13:21:41.019700 TX Vref=30, minBit 1, minWin=27, winSum=449
926 13:21:41.026788 TX Vref=32, minBit 2, minWin=27, winSum=448
927 13:21:41.029713 [TxChooseVref] Worse bit 3, Min win 27, Win sum 449, Final Vref 26
928 13:21:41.029786
929 13:21:41.033144 Final TX Range 1 Vref 26
930 13:21:41.033226
931 13:21:41.033292 ==
932 13:21:41.036515 Dram Type= 6, Freq= 0, CH_0, rank 0
933 13:21:41.039545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 13:21:41.043357 ==
935 13:21:41.043439
936 13:21:41.043504
937 13:21:41.043563 TX Vref Scan disable
938 13:21:41.046468 == TX Byte 0 ==
939 13:21:41.050113 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
940 13:21:41.053439 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
941 13:21:41.056838 == TX Byte 1 ==
942 13:21:41.059704 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 13:21:41.066866 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 13:21:41.066952
945 13:21:41.067017 [DATLAT]
946 13:21:41.067076 Freq=800, CH0 RK0
947 13:21:41.067134
948 13:21:41.070701 DATLAT Default: 0xa
949 13:21:41.070782 0, 0xFFFF, sum = 0
950 13:21:41.073567 1, 0xFFFF, sum = 0
951 13:21:41.073652 2, 0xFFFF, sum = 0
952 13:21:41.076522 3, 0xFFFF, sum = 0
953 13:21:41.076604 4, 0xFFFF, sum = 0
954 13:21:41.080222 5, 0xFFFF, sum = 0
955 13:21:41.083257 6, 0xFFFF, sum = 0
956 13:21:41.083340 7, 0xFFFF, sum = 0
957 13:21:41.087069 8, 0xFFFF, sum = 0
958 13:21:41.087152 9, 0x0, sum = 1
959 13:21:41.087217 10, 0x0, sum = 2
960 13:21:41.089890 11, 0x0, sum = 3
961 13:21:41.089973 12, 0x0, sum = 4
962 13:21:41.093751 best_step = 10
963 13:21:41.093832
964 13:21:41.093896 ==
965 13:21:41.096298 Dram Type= 6, Freq= 0, CH_0, rank 0
966 13:21:41.099673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 13:21:41.099754 ==
968 13:21:41.103431 RX Vref Scan: 1
969 13:21:41.103512
970 13:21:41.103583 Set Vref Range= 32 -> 127
971 13:21:41.106505
972 13:21:41.106586 RX Vref 32 -> 127, step: 1
973 13:21:41.106652
974 13:21:41.110256 RX Delay -111 -> 252, step: 8
975 13:21:41.110337
976 13:21:41.113417 Set Vref, RX VrefLevel [Byte0]: 32
977 13:21:41.116787 [Byte1]: 32
978 13:21:41.116897
979 13:21:41.120531 Set Vref, RX VrefLevel [Byte0]: 33
980 13:21:41.123057 [Byte1]: 33
981 13:21:41.127361
982 13:21:41.127471 Set Vref, RX VrefLevel [Byte0]: 34
983 13:21:41.130526 [Byte1]: 34
984 13:21:41.134541
985 13:21:41.134647 Set Vref, RX VrefLevel [Byte0]: 35
986 13:21:41.138343 [Byte1]: 35
987 13:21:41.142229
988 13:21:41.142310 Set Vref, RX VrefLevel [Byte0]: 36
989 13:21:41.145549 [Byte1]: 36
990 13:21:41.149621
991 13:21:41.153530 Set Vref, RX VrefLevel [Byte0]: 37
992 13:21:41.153612 [Byte1]: 37
993 13:21:41.158406
994 13:21:41.158513 Set Vref, RX VrefLevel [Byte0]: 38
995 13:21:41.162233 [Byte1]: 38
996 13:21:41.165875
997 13:21:41.165956 Set Vref, RX VrefLevel [Byte0]: 39
998 13:21:41.169317 [Byte1]: 39
999 13:21:41.173742
1000 13:21:41.173823 Set Vref, RX VrefLevel [Byte0]: 40
1001 13:21:41.176707 [Byte1]: 40
1002 13:21:41.181122
1003 13:21:41.181203 Set Vref, RX VrefLevel [Byte0]: 41
1004 13:21:41.184267 [Byte1]: 41
1005 13:21:41.188010
1006 13:21:41.188091 Set Vref, RX VrefLevel [Byte0]: 42
1007 13:21:41.194861 [Byte1]: 42
1008 13:21:41.194952
1009 13:21:41.198446 Set Vref, RX VrefLevel [Byte0]: 43
1010 13:21:41.201335 [Byte1]: 43
1011 13:21:41.201417
1012 13:21:41.204310 Set Vref, RX VrefLevel [Byte0]: 44
1013 13:21:41.208140 [Byte1]: 44
1014 13:21:41.211186
1015 13:21:41.211267 Set Vref, RX VrefLevel [Byte0]: 45
1016 13:21:41.214578 [Byte1]: 45
1017 13:21:41.218686
1018 13:21:41.218768 Set Vref, RX VrefLevel [Byte0]: 46
1019 13:21:41.222278 [Byte1]: 46
1020 13:21:41.226881
1021 13:21:41.226971 Set Vref, RX VrefLevel [Byte0]: 47
1022 13:21:41.230121 [Byte1]: 47
1023 13:21:41.234081
1024 13:21:41.234162 Set Vref, RX VrefLevel [Byte0]: 48
1025 13:21:41.238209 [Byte1]: 48
1026 13:21:41.241506
1027 13:21:41.241586 Set Vref, RX VrefLevel [Byte0]: 49
1028 13:21:41.245170 [Byte1]: 49
1029 13:21:41.249651
1030 13:21:41.249732 Set Vref, RX VrefLevel [Byte0]: 50
1031 13:21:41.252812 [Byte1]: 50
1032 13:21:41.257292
1033 13:21:41.260518 Set Vref, RX VrefLevel [Byte0]: 51
1034 13:21:41.260599 [Byte1]: 51
1035 13:21:41.264643
1036 13:21:41.264723 Set Vref, RX VrefLevel [Byte0]: 52
1037 13:21:41.267818 [Byte1]: 52
1038 13:21:41.272586
1039 13:21:41.272666 Set Vref, RX VrefLevel [Byte0]: 53
1040 13:21:41.276074 [Byte1]: 53
1041 13:21:41.280194
1042 13:21:41.280275 Set Vref, RX VrefLevel [Byte0]: 54
1043 13:21:41.283028 [Byte1]: 54
1044 13:21:41.287850
1045 13:21:41.287980 Set Vref, RX VrefLevel [Byte0]: 55
1046 13:21:41.291135 [Byte1]: 55
1047 13:21:41.295074
1048 13:21:41.295154 Set Vref, RX VrefLevel [Byte0]: 56
1049 13:21:41.298947 [Byte1]: 56
1050 13:21:41.303112
1051 13:21:41.303192 Set Vref, RX VrefLevel [Byte0]: 57
1052 13:21:41.306132 [Byte1]: 57
1053 13:21:41.311077
1054 13:21:41.311158 Set Vref, RX VrefLevel [Byte0]: 58
1055 13:21:41.314157 [Byte1]: 58
1056 13:21:41.318072
1057 13:21:41.318152 Set Vref, RX VrefLevel [Byte0]: 59
1058 13:21:41.321654 [Byte1]: 59
1059 13:21:41.326517
1060 13:21:41.326598 Set Vref, RX VrefLevel [Byte0]: 60
1061 13:21:41.329413 [Byte1]: 60
1062 13:21:41.333552
1063 13:21:41.333632 Set Vref, RX VrefLevel [Byte0]: 61
1064 13:21:41.337143 [Byte1]: 61
1065 13:21:41.341205
1066 13:21:41.341284 Set Vref, RX VrefLevel [Byte0]: 62
1067 13:21:41.344343 [Byte1]: 62
1068 13:21:41.349009
1069 13:21:41.349141 Set Vref, RX VrefLevel [Byte0]: 63
1070 13:21:41.352315 [Byte1]: 63
1071 13:21:41.356104
1072 13:21:41.356210 Set Vref, RX VrefLevel [Byte0]: 64
1073 13:21:41.359548 [Byte1]: 64
1074 13:21:41.363713
1075 13:21:41.363819 Set Vref, RX VrefLevel [Byte0]: 65
1076 13:21:41.367406 [Byte1]: 65
1077 13:21:41.371533
1078 13:21:41.371638 Set Vref, RX VrefLevel [Byte0]: 66
1079 13:21:41.375193 [Byte1]: 66
1080 13:21:41.379710
1081 13:21:41.379821 Set Vref, RX VrefLevel [Byte0]: 67
1082 13:21:41.382678 [Byte1]: 67
1083 13:21:41.387269
1084 13:21:41.387349 Set Vref, RX VrefLevel [Byte0]: 68
1085 13:21:41.390496 [Byte1]: 68
1086 13:21:41.394650
1087 13:21:41.394730 Set Vref, RX VrefLevel [Byte0]: 69
1088 13:21:41.397668 [Byte1]: 69
1089 13:21:41.402753
1090 13:21:41.402877 Set Vref, RX VrefLevel [Byte0]: 70
1091 13:21:41.405679 [Byte1]: 70
1092 13:21:41.410153
1093 13:21:41.410233 Set Vref, RX VrefLevel [Byte0]: 71
1094 13:21:41.413119 [Byte1]: 71
1095 13:21:41.418234
1096 13:21:41.418313 Set Vref, RX VrefLevel [Byte0]: 72
1097 13:21:41.421077 [Byte1]: 72
1098 13:21:41.425278
1099 13:21:41.425363 Set Vref, RX VrefLevel [Byte0]: 73
1100 13:21:41.428861 [Byte1]: 73
1101 13:21:41.432829
1102 13:21:41.432908 Set Vref, RX VrefLevel [Byte0]: 74
1103 13:21:41.436118 [Byte1]: 74
1104 13:21:41.440912
1105 13:21:41.440992 Final RX Vref Byte 0 = 56 to rank0
1106 13:21:41.443850 Final RX Vref Byte 1 = 61 to rank0
1107 13:21:41.447027 Final RX Vref Byte 0 = 56 to rank1
1108 13:21:41.450875 Final RX Vref Byte 1 = 61 to rank1==
1109 13:21:41.454216 Dram Type= 6, Freq= 0, CH_0, rank 0
1110 13:21:41.460513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1111 13:21:41.460595 ==
1112 13:21:41.460659 DQS Delay:
1113 13:21:41.463489 DQS0 = 0, DQS1 = 0
1114 13:21:41.463568 DQM Delay:
1115 13:21:41.463632 DQM0 = 88, DQM1 = 76
1116 13:21:41.467142 DQ Delay:
1117 13:21:41.470267 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1118 13:21:41.473574 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1119 13:21:41.477171 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1120 13:21:41.480437 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1121 13:21:41.480517
1122 13:21:41.480580
1123 13:21:41.486540 [DQSOSCAuto] RK0, (LSB)MR18= 0x312b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1124 13:21:41.490309 CH0 RK0: MR19=606, MR18=312B
1125 13:21:41.497198 CH0_RK0: MR19=0x606, MR18=0x312B, DQSOSC=397, MR23=63, INC=93, DEC=62
1126 13:21:41.497281
1127 13:21:41.500708 ----->DramcWriteLeveling(PI) begin...
1128 13:21:41.500790 ==
1129 13:21:41.503656 Dram Type= 6, Freq= 0, CH_0, rank 1
1130 13:21:41.506860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1131 13:21:41.506941 ==
1132 13:21:41.510212 Write leveling (Byte 0): 30 => 30
1133 13:21:41.514171 Write leveling (Byte 1): 29 => 29
1134 13:21:41.516861 DramcWriteLeveling(PI) end<-----
1135 13:21:41.516941
1136 13:21:41.517005 ==
1137 13:21:41.519771 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 13:21:41.523259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 13:21:41.523340 ==
1140 13:21:41.526971 [Gating] SW mode calibration
1141 13:21:41.533082 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1142 13:21:41.540391 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1143 13:21:41.543181 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1144 13:21:41.587331 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1145 13:21:41.587921 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 13:21:41.588209 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 13:21:41.588281 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 13:21:41.588541 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 13:21:41.589296 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 13:21:41.589594 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 13:21:41.590059 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 13:21:41.590140 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 13:21:41.590389 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 13:21:41.631555 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 13:21:41.632010 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 13:21:41.632398 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 13:21:41.632489 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 13:21:41.632734 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 13:21:41.632809 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1160 13:21:41.632880 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1161 13:21:41.633127 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1162 13:21:41.633198 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:21:41.633305 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:21:41.666596 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 13:21:41.666878 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 13:21:41.666976 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 13:21:41.667066 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 13:21:41.667358 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1169 13:21:41.667957 0 9 8 | B1->B0 | 2525 3434 | 1 0 | (1 1) (0 0)
1170 13:21:41.668235 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1171 13:21:41.671431 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 13:21:41.671538 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 13:21:41.674315 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 13:21:41.681831 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 13:21:41.684555 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 13:21:41.687488 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
1177 13:21:41.694477 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
1178 13:21:41.697603 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 13:21:41.700859 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 13:21:41.707896 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 13:21:41.710633 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 13:21:41.714315 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 13:21:41.720766 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 13:21:41.724648 0 11 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1185 13:21:41.728470 0 11 8 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
1186 13:21:41.731080 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1187 13:21:41.739100 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 13:21:41.742984 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 13:21:41.746930 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 13:21:41.749796 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 13:21:41.757545 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1192 13:21:41.760219 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1193 13:21:41.763451 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1194 13:21:41.766733 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 13:21:41.773239 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 13:21:41.776462 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 13:21:41.780343 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 13:21:41.786521 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 13:21:41.790163 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 13:21:41.793345 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 13:21:41.799866 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 13:21:41.803195 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 13:21:41.806480 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 13:21:41.813154 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 13:21:41.816540 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 13:21:41.819515 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:21:41.826341 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1208 13:21:41.829659 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1209 13:21:41.833006 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1210 13:21:41.840059 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 13:21:41.840139 Total UI for P1: 0, mck2ui 16
1212 13:21:41.846435 best dqsien dly found for B0: ( 0, 14, 4)
1213 13:21:41.846516 Total UI for P1: 0, mck2ui 16
1214 13:21:41.849777 best dqsien dly found for B1: ( 0, 14, 8)
1215 13:21:41.855977 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1216 13:21:41.859265 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1217 13:21:41.859345
1218 13:21:41.862477 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1219 13:21:41.865759 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1220 13:21:41.869304 [Gating] SW calibration Done
1221 13:21:41.869385 ==
1222 13:21:41.872657 Dram Type= 6, Freq= 0, CH_0, rank 1
1223 13:21:41.875878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1224 13:21:41.875995 ==
1225 13:21:41.879330 RX Vref Scan: 0
1226 13:21:41.879415
1227 13:21:41.879478 RX Vref 0 -> 0, step: 1
1228 13:21:41.879537
1229 13:21:41.883192 RX Delay -130 -> 252, step: 16
1230 13:21:41.885618 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1231 13:21:41.892526 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1232 13:21:41.895848 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1233 13:21:41.899186 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1234 13:21:41.902707 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1235 13:21:41.905646 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1236 13:21:41.912845 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1237 13:21:41.915826 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1238 13:21:41.919589 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1239 13:21:41.922522 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1240 13:21:41.925749 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1241 13:21:41.932440 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1242 13:21:41.936344 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1243 13:21:41.939381 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1244 13:21:41.942287 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1245 13:21:41.946153 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1246 13:21:41.949102 ==
1247 13:21:41.952033 Dram Type= 6, Freq= 0, CH_0, rank 1
1248 13:21:41.955509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1249 13:21:41.955615 ==
1250 13:21:41.955707 DQS Delay:
1251 13:21:41.959273 DQS0 = 0, DQS1 = 0
1252 13:21:41.959378 DQM Delay:
1253 13:21:41.962385 DQM0 = 85, DQM1 = 76
1254 13:21:41.962465 DQ Delay:
1255 13:21:41.966017 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1256 13:21:41.968853 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
1257 13:21:41.972323 DQ8 =69, DQ9 =53, DQ10 =85, DQ11 =69
1258 13:21:41.975325 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1259 13:21:41.975405
1260 13:21:41.975468
1261 13:21:41.975528 ==
1262 13:21:41.978528 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 13:21:41.982150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 13:21:41.982231 ==
1265 13:21:41.982295
1266 13:21:41.982354
1267 13:21:41.985303 TX Vref Scan disable
1268 13:21:41.988633 == TX Byte 0 ==
1269 13:21:41.992584 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1270 13:21:41.994936 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1271 13:21:41.999076 == TX Byte 1 ==
1272 13:21:42.001787 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1273 13:21:42.004926 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1274 13:21:42.005006 ==
1275 13:21:42.008137 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 13:21:42.015039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 13:21:42.015119 ==
1278 13:21:42.026980 TX Vref=22, minBit 0, minWin=27, winSum=441
1279 13:21:42.030345 TX Vref=24, minBit 3, minWin=27, winSum=445
1280 13:21:42.033909 TX Vref=26, minBit 1, minWin=27, winSum=445
1281 13:21:42.036631 TX Vref=28, minBit 1, minWin=27, winSum=447
1282 13:21:42.040015 TX Vref=30, minBit 6, minWin=27, winSum=449
1283 13:21:42.046377 TX Vref=32, minBit 7, minWin=27, winSum=448
1284 13:21:42.049718 [TxChooseVref] Worse bit 6, Min win 27, Win sum 449, Final Vref 30
1285 13:21:42.049802
1286 13:21:42.053246 Final TX Range 1 Vref 30
1287 13:21:42.053326
1288 13:21:42.053389 ==
1289 13:21:42.056192 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 13:21:42.059867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 13:21:42.059985 ==
1292 13:21:42.062944
1293 13:21:42.063024
1294 13:21:42.063086 TX Vref Scan disable
1295 13:21:42.066899 == TX Byte 0 ==
1296 13:21:42.069661 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1297 13:21:42.073120 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1298 13:21:42.076226 == TX Byte 1 ==
1299 13:21:42.079702 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1300 13:21:42.086929 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1301 13:21:42.087008
1302 13:21:42.087071 [DATLAT]
1303 13:21:42.087129 Freq=800, CH0 RK1
1304 13:21:42.087186
1305 13:21:42.089831 DATLAT Default: 0xa
1306 13:21:42.089911 0, 0xFFFF, sum = 0
1307 13:21:42.093301 1, 0xFFFF, sum = 0
1308 13:21:42.093382 2, 0xFFFF, sum = 0
1309 13:21:42.096625 3, 0xFFFF, sum = 0
1310 13:21:42.099384 4, 0xFFFF, sum = 0
1311 13:21:42.099464 5, 0xFFFF, sum = 0
1312 13:21:42.103609 6, 0xFFFF, sum = 0
1313 13:21:42.103720 7, 0xFFFF, sum = 0
1314 13:21:42.106537 8, 0xFFFF, sum = 0
1315 13:21:42.106618 9, 0x0, sum = 1
1316 13:21:42.106682 10, 0x0, sum = 2
1317 13:21:42.109795 11, 0x0, sum = 3
1318 13:21:42.109876 12, 0x0, sum = 4
1319 13:21:42.113025 best_step = 10
1320 13:21:42.113104
1321 13:21:42.113166 ==
1322 13:21:42.116291 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 13:21:42.119495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 13:21:42.119586 ==
1325 13:21:42.123156 RX Vref Scan: 0
1326 13:21:42.123235
1327 13:21:42.123298 RX Vref 0 -> 0, step: 1
1328 13:21:42.123357
1329 13:21:42.126694 RX Delay -111 -> 252, step: 8
1330 13:21:42.133038 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1331 13:21:42.136623 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1332 13:21:42.139500 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1333 13:21:42.143435 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1334 13:21:42.149666 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1335 13:21:42.152799 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1336 13:21:42.156351 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1337 13:21:42.159507 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1338 13:21:42.162927 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1339 13:21:42.169735 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1340 13:21:42.173325 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1341 13:21:42.176369 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1342 13:21:42.179500 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1343 13:21:42.183026 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1344 13:21:42.189139 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1345 13:21:42.192585 iDelay=209, Bit 15, Center 80 (-31 ~ 192) 224
1346 13:21:42.192665 ==
1347 13:21:42.196094 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 13:21:42.198939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 13:21:42.199018 ==
1350 13:21:42.202470 DQS Delay:
1351 13:21:42.202549 DQS0 = 0, DQS1 = 0
1352 13:21:42.202625 DQM Delay:
1353 13:21:42.206303 DQM0 = 86, DQM1 = 75
1354 13:21:42.206382 DQ Delay:
1355 13:21:42.208897 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1356 13:21:42.212502 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1357 13:21:42.215580 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1358 13:21:42.219307 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =80
1359 13:21:42.219390
1360 13:21:42.219452
1361 13:21:42.229681 [DQSOSCAuto] RK1, (LSB)MR18= 0x2825, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1362 13:21:42.232374 CH0 RK1: MR19=606, MR18=2825
1363 13:21:42.236416 CH0_RK1: MR19=0x606, MR18=0x2825, DQSOSC=399, MR23=63, INC=92, DEC=61
1364 13:21:42.239132 [RxdqsGatingPostProcess] freq 800
1365 13:21:42.246529 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1366 13:21:42.249402 Pre-setting of DQS Precalculation
1367 13:21:42.252237 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1368 13:21:42.252317 ==
1369 13:21:42.255331 Dram Type= 6, Freq= 0, CH_1, rank 0
1370 13:21:42.262091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 13:21:42.262172 ==
1372 13:21:42.265626 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1373 13:21:42.272167 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1374 13:21:42.281651 [CA 0] Center 37 (6~68) winsize 63
1375 13:21:42.284692 [CA 1] Center 37 (6~68) winsize 63
1376 13:21:42.288322 [CA 2] Center 34 (4~65) winsize 62
1377 13:21:42.291553 [CA 3] Center 34 (4~65) winsize 62
1378 13:21:42.295157 [CA 4] Center 34 (4~65) winsize 62
1379 13:21:42.298224 [CA 5] Center 34 (3~65) winsize 63
1380 13:21:42.298304
1381 13:21:42.301437 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1382 13:21:42.301517
1383 13:21:42.304739 [CATrainingPosCal] consider 1 rank data
1384 13:21:42.307685 u2DelayCellTimex100 = 270/100 ps
1385 13:21:42.311135 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1386 13:21:42.317543 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1387 13:21:42.321106 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1388 13:21:42.324590 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1389 13:21:42.327550 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1390 13:21:42.330825 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1391 13:21:42.330906
1392 13:21:42.334350 CA PerBit enable=1, Macro0, CA PI delay=34
1393 13:21:42.334431
1394 13:21:42.338444 [CBTSetCACLKResult] CA Dly = 34
1395 13:21:42.340794 CS Dly: 4 (0~35)
1396 13:21:42.340874 ==
1397 13:21:42.344118 Dram Type= 6, Freq= 0, CH_1, rank 1
1398 13:21:42.347728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 13:21:42.347809 ==
1400 13:21:42.354079 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1401 13:21:42.357462 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1402 13:21:42.367584 [CA 0] Center 36 (6~67) winsize 62
1403 13:21:42.371426 [CA 1] Center 37 (6~68) winsize 63
1404 13:21:42.374410 [CA 2] Center 34 (4~65) winsize 62
1405 13:21:42.378044 [CA 3] Center 34 (3~65) winsize 63
1406 13:21:42.381028 [CA 4] Center 34 (3~65) winsize 63
1407 13:21:42.384312 [CA 5] Center 34 (3~65) winsize 63
1408 13:21:42.384392
1409 13:21:42.387814 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1410 13:21:42.387894
1411 13:21:42.391088 [CATrainingPosCal] consider 2 rank data
1412 13:21:42.394704 u2DelayCellTimex100 = 270/100 ps
1413 13:21:42.397963 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1414 13:21:42.401874 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1415 13:21:42.405316 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1416 13:21:42.409613 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1417 13:21:42.413763 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1418 13:21:42.417543 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1419 13:21:42.417623
1420 13:21:42.420625 CA PerBit enable=1, Macro0, CA PI delay=34
1421 13:21:42.420706
1422 13:21:42.424942 [CBTSetCACLKResult] CA Dly = 34
1423 13:21:42.425068 CS Dly: 5 (0~37)
1424 13:21:42.425131
1425 13:21:42.428398 ----->DramcWriteLeveling(PI) begin...
1426 13:21:42.428479 ==
1427 13:21:42.431347 Dram Type= 6, Freq= 0, CH_1, rank 0
1428 13:21:42.438354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1429 13:21:42.438436 ==
1430 13:21:42.441383 Write leveling (Byte 0): 28 => 28
1431 13:21:42.441464 Write leveling (Byte 1): 30 => 30
1432 13:21:42.444538 DramcWriteLeveling(PI) end<-----
1433 13:21:42.444618
1434 13:21:42.448439 ==
1435 13:21:42.448519 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 13:21:42.454841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 13:21:42.454922 ==
1438 13:21:42.457911 [Gating] SW mode calibration
1439 13:21:42.464635 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1440 13:21:42.468004 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1441 13:21:42.475182 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1442 13:21:42.478259 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1443 13:21:42.482368 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1444 13:21:42.488295 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 13:21:42.491393 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 13:21:42.495648 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 13:21:42.501288 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 13:21:42.504600 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 13:21:42.508091 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 13:21:42.514386 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 13:21:42.517835 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 13:21:42.521216 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 13:21:42.527767 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 13:21:42.530870 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 13:21:42.534304 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:21:42.537750 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 13:21:42.544362 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:21:42.547661 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1459 13:21:42.550869 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 13:21:42.557787 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 13:21:42.561254 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 13:21:42.564494 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 13:21:42.571020 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 13:21:42.574060 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 13:21:42.577436 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 13:21:42.584349 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 13:21:42.587836 0 9 8 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
1468 13:21:42.590937 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 13:21:42.597269 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 13:21:42.601688 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 13:21:42.604281 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 13:21:42.610674 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 13:21:42.614003 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 13:21:42.617310 0 10 4 | B1->B0 | 3131 2f2f | 0 0 | (1 1) (0 1)
1475 13:21:42.624390 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1476 13:21:42.627557 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 13:21:42.631169 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 13:21:42.637181 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 13:21:42.640738 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 13:21:42.644145 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 13:21:42.650728 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 13:21:42.654581 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1483 13:21:42.657011 0 11 8 | B1->B0 | 3a3a 4444 | 0 0 | (0 0) (0 0)
1484 13:21:42.664242 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 13:21:42.667712 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 13:21:42.670475 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 13:21:42.676920 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 13:21:42.680465 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 13:21:42.683707 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1490 13:21:42.687261 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1491 13:21:42.693762 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 13:21:42.697496 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 13:21:42.700550 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 13:21:42.707785 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 13:21:42.710401 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 13:21:42.713543 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 13:21:42.720744 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 13:21:42.723852 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 13:21:42.726864 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 13:21:42.733390 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 13:21:42.737040 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 13:21:42.740428 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 13:21:42.746609 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 13:21:42.749874 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 13:21:42.753875 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 13:21:42.760023 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1507 13:21:42.763598 Total UI for P1: 0, mck2ui 16
1508 13:21:42.766464 best dqsien dly found for B0: ( 0, 14, 2)
1509 13:21:42.770055 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1510 13:21:42.773660 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 13:21:42.776624 Total UI for P1: 0, mck2ui 16
1512 13:21:42.779776 best dqsien dly found for B1: ( 0, 14, 8)
1513 13:21:42.783430 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1514 13:21:42.786802 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1515 13:21:42.786882
1516 13:21:42.793471 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1517 13:21:42.796825 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1518 13:21:42.796905 [Gating] SW calibration Done
1519 13:21:42.800422 ==
1520 13:21:42.800502 Dram Type= 6, Freq= 0, CH_1, rank 0
1521 13:21:42.807128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1522 13:21:42.807208 ==
1523 13:21:42.807272 RX Vref Scan: 0
1524 13:21:42.807332
1525 13:21:42.810214 RX Vref 0 -> 0, step: 1
1526 13:21:42.810294
1527 13:21:42.814162 RX Delay -130 -> 252, step: 16
1528 13:21:42.816571 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1529 13:21:42.819821 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1530 13:21:42.823514 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1531 13:21:42.829940 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1532 13:21:42.833881 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1533 13:21:42.836488 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1534 13:21:42.839710 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1535 13:21:42.843353 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1536 13:21:42.849757 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1537 13:21:42.853228 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1538 13:21:42.856216 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1539 13:21:42.859555 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1540 13:21:42.863286 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1541 13:21:42.869546 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1542 13:21:42.873062 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1543 13:21:42.876656 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1544 13:21:42.876737 ==
1545 13:21:42.879492 Dram Type= 6, Freq= 0, CH_1, rank 0
1546 13:21:42.883210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1547 13:21:42.886883 ==
1548 13:21:42.886963 DQS Delay:
1549 13:21:42.887027 DQS0 = 0, DQS1 = 0
1550 13:21:42.889654 DQM Delay:
1551 13:21:42.889733 DQM0 = 87, DQM1 = 79
1552 13:21:42.894439 DQ Delay:
1553 13:21:42.894518 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1554 13:21:42.896729 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1555 13:21:42.899577 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1556 13:21:42.903821 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1557 13:21:42.906168
1558 13:21:42.906247
1559 13:21:42.906310 ==
1560 13:21:42.909793 Dram Type= 6, Freq= 0, CH_1, rank 0
1561 13:21:42.912990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1562 13:21:42.913096 ==
1563 13:21:42.913161
1564 13:21:42.913220
1565 13:21:42.916042 TX Vref Scan disable
1566 13:21:42.916122 == TX Byte 0 ==
1567 13:21:42.923100 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1568 13:21:42.926072 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1569 13:21:42.926152 == TX Byte 1 ==
1570 13:21:42.932535 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1571 13:21:42.936321 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1572 13:21:42.936401 ==
1573 13:21:42.939203 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 13:21:42.942483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 13:21:42.942563 ==
1576 13:21:42.956862 TX Vref=22, minBit 0, minWin=27, winSum=444
1577 13:21:42.959898 TX Vref=24, minBit 1, minWin=27, winSum=442
1578 13:21:42.963370 TX Vref=26, minBit 1, minWin=27, winSum=451
1579 13:21:42.966486 TX Vref=28, minBit 1, minWin=27, winSum=452
1580 13:21:42.969728 TX Vref=30, minBit 5, minWin=27, winSum=453
1581 13:21:42.973038 TX Vref=32, minBit 0, minWin=27, winSum=451
1582 13:21:42.980789 [TxChooseVref] Worse bit 5, Min win 27, Win sum 453, Final Vref 30
1583 13:21:42.980871
1584 13:21:42.984167 Final TX Range 1 Vref 30
1585 13:21:42.984247
1586 13:21:42.984311 ==
1587 13:21:42.987665 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 13:21:42.990696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 13:21:42.990777 ==
1590 13:21:42.990841
1591 13:21:42.990900
1592 13:21:42.994525 TX Vref Scan disable
1593 13:21:42.997529 == TX Byte 0 ==
1594 13:21:43.000536 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1595 13:21:43.004495 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1596 13:21:43.007230 == TX Byte 1 ==
1597 13:21:43.010877 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1598 13:21:43.013916 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1599 13:21:43.013996
1600 13:21:43.017478 [DATLAT]
1601 13:21:43.017558 Freq=800, CH1 RK0
1602 13:21:43.017622
1603 13:21:43.020661 DATLAT Default: 0xa
1604 13:21:43.020741 0, 0xFFFF, sum = 0
1605 13:21:43.024132 1, 0xFFFF, sum = 0
1606 13:21:43.024214 2, 0xFFFF, sum = 0
1607 13:21:43.027103 3, 0xFFFF, sum = 0
1608 13:21:43.027185 4, 0xFFFF, sum = 0
1609 13:21:43.030556 5, 0xFFFF, sum = 0
1610 13:21:43.030638 6, 0xFFFF, sum = 0
1611 13:21:43.033962 7, 0xFFFF, sum = 0
1612 13:21:43.034044 8, 0xFFFF, sum = 0
1613 13:21:43.036956 9, 0x0, sum = 1
1614 13:21:43.037038 10, 0x0, sum = 2
1615 13:21:43.040204 11, 0x0, sum = 3
1616 13:21:43.040285 12, 0x0, sum = 4
1617 13:21:43.043317 best_step = 10
1618 13:21:43.043398
1619 13:21:43.043461 ==
1620 13:21:43.047374 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 13:21:43.050024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 13:21:43.050105 ==
1623 13:21:43.053366 RX Vref Scan: 1
1624 13:21:43.053446
1625 13:21:43.053510 Set Vref Range= 32 -> 127
1626 13:21:43.053570
1627 13:21:43.057338 RX Vref 32 -> 127, step: 1
1628 13:21:43.057419
1629 13:21:43.059732 RX Delay -95 -> 252, step: 8
1630 13:21:43.059812
1631 13:21:43.063182 Set Vref, RX VrefLevel [Byte0]: 32
1632 13:21:43.066828 [Byte1]: 32
1633 13:21:43.066909
1634 13:21:43.069897 Set Vref, RX VrefLevel [Byte0]: 33
1635 13:21:43.073560 [Byte1]: 33
1636 13:21:43.076792
1637 13:21:43.076871 Set Vref, RX VrefLevel [Byte0]: 34
1638 13:21:43.080083 [Byte1]: 34
1639 13:21:43.084773
1640 13:21:43.084853 Set Vref, RX VrefLevel [Byte0]: 35
1641 13:21:43.087591 [Byte1]: 35
1642 13:21:43.092354
1643 13:21:43.092438 Set Vref, RX VrefLevel [Byte0]: 36
1644 13:21:43.095478 [Byte1]: 36
1645 13:21:43.099671
1646 13:21:43.099752 Set Vref, RX VrefLevel [Byte0]: 37
1647 13:21:43.103013 [Byte1]: 37
1648 13:21:43.107032
1649 13:21:43.107112 Set Vref, RX VrefLevel [Byte0]: 38
1650 13:21:43.110763 [Byte1]: 38
1651 13:21:43.115284
1652 13:21:43.115365 Set Vref, RX VrefLevel [Byte0]: 39
1653 13:21:43.118275 [Byte1]: 39
1654 13:21:43.122263
1655 13:21:43.122344 Set Vref, RX VrefLevel [Byte0]: 40
1656 13:21:43.126098 [Byte1]: 40
1657 13:21:43.129920
1658 13:21:43.130000 Set Vref, RX VrefLevel [Byte0]: 41
1659 13:21:43.133295 [Byte1]: 41
1660 13:21:43.137620
1661 13:21:43.137701 Set Vref, RX VrefLevel [Byte0]: 42
1662 13:21:43.141419 [Byte1]: 42
1663 13:21:43.145857
1664 13:21:43.145938 Set Vref, RX VrefLevel [Byte0]: 43
1665 13:21:43.148564 [Byte1]: 43
1666 13:21:43.152532
1667 13:21:43.152613 Set Vref, RX VrefLevel [Byte0]: 44
1668 13:21:43.156257 [Byte1]: 44
1669 13:21:43.160947
1670 13:21:43.161026 Set Vref, RX VrefLevel [Byte0]: 45
1671 13:21:43.164091 [Byte1]: 45
1672 13:21:43.168070
1673 13:21:43.168150 Set Vref, RX VrefLevel [Byte0]: 46
1674 13:21:43.171255 [Byte1]: 46
1675 13:21:43.175496
1676 13:21:43.175577 Set Vref, RX VrefLevel [Byte0]: 47
1677 13:21:43.179028 [Byte1]: 47
1678 13:21:43.183350
1679 13:21:43.183431 Set Vref, RX VrefLevel [Byte0]: 48
1680 13:21:43.187022 [Byte1]: 48
1681 13:21:43.190659
1682 13:21:43.190747 Set Vref, RX VrefLevel [Byte0]: 49
1683 13:21:43.194340 [Byte1]: 49
1684 13:21:43.198497
1685 13:21:43.198581 Set Vref, RX VrefLevel [Byte0]: 50
1686 13:21:43.201593 [Byte1]: 50
1687 13:21:43.206090
1688 13:21:43.206171 Set Vref, RX VrefLevel [Byte0]: 51
1689 13:21:43.209158 [Byte1]: 51
1690 13:21:43.213437
1691 13:21:43.213517 Set Vref, RX VrefLevel [Byte0]: 52
1692 13:21:43.217211 [Byte1]: 52
1693 13:21:43.221391
1694 13:21:43.221470 Set Vref, RX VrefLevel [Byte0]: 53
1695 13:21:43.224360 [Byte1]: 53
1696 13:21:43.229243
1697 13:21:43.229323 Set Vref, RX VrefLevel [Byte0]: 54
1698 13:21:43.232748 [Byte1]: 54
1699 13:21:43.236309
1700 13:21:43.236389 Set Vref, RX VrefLevel [Byte0]: 55
1701 13:21:43.239749 [Byte1]: 55
1702 13:21:43.243810
1703 13:21:43.243890 Set Vref, RX VrefLevel [Byte0]: 56
1704 13:21:43.247269 [Byte1]: 56
1705 13:21:43.252277
1706 13:21:43.252356 Set Vref, RX VrefLevel [Byte0]: 57
1707 13:21:43.254731 [Byte1]: 57
1708 13:21:43.259489
1709 13:21:43.259570 Set Vref, RX VrefLevel [Byte0]: 58
1710 13:21:43.262894 [Byte1]: 58
1711 13:21:43.266539
1712 13:21:43.266625 Set Vref, RX VrefLevel [Byte0]: 59
1713 13:21:43.270068 [Byte1]: 59
1714 13:21:43.275004
1715 13:21:43.275083 Set Vref, RX VrefLevel [Byte0]: 60
1716 13:21:43.277651 [Byte1]: 60
1717 13:21:43.282280
1718 13:21:43.282386 Set Vref, RX VrefLevel [Byte0]: 61
1719 13:21:43.285302 [Byte1]: 61
1720 13:21:43.289905
1721 13:21:43.289985 Set Vref, RX VrefLevel [Byte0]: 62
1722 13:21:43.292868 [Byte1]: 62
1723 13:21:43.297328
1724 13:21:43.297408 Set Vref, RX VrefLevel [Byte0]: 63
1725 13:21:43.300914 [Byte1]: 63
1726 13:21:43.305003
1727 13:21:43.305083 Set Vref, RX VrefLevel [Byte0]: 64
1728 13:21:43.307897 [Byte1]: 64
1729 13:21:43.312288
1730 13:21:43.312368 Set Vref, RX VrefLevel [Byte0]: 65
1731 13:21:43.316007 [Byte1]: 65
1732 13:21:43.319854
1733 13:21:43.319956 Set Vref, RX VrefLevel [Byte0]: 66
1734 13:21:43.323058 [Byte1]: 66
1735 13:21:43.327266
1736 13:21:43.327369 Set Vref, RX VrefLevel [Byte0]: 67
1737 13:21:43.331237 [Byte1]: 67
1738 13:21:43.335355
1739 13:21:43.335435 Set Vref, RX VrefLevel [Byte0]: 68
1740 13:21:43.338745 [Byte1]: 68
1741 13:21:43.342871
1742 13:21:43.342952 Set Vref, RX VrefLevel [Byte0]: 69
1743 13:21:43.346177 [Byte1]: 69
1744 13:21:43.350432
1745 13:21:43.350541 Set Vref, RX VrefLevel [Byte0]: 70
1746 13:21:43.353703 [Byte1]: 70
1747 13:21:43.357836
1748 13:21:43.357931 Set Vref, RX VrefLevel [Byte0]: 71
1749 13:21:43.361647 [Byte1]: 71
1750 13:21:43.366150
1751 13:21:43.366256 Set Vref, RX VrefLevel [Byte0]: 72
1752 13:21:43.369024 [Byte1]: 72
1753 13:21:43.373322
1754 13:21:43.373403 Set Vref, RX VrefLevel [Byte0]: 73
1755 13:21:43.376353 [Byte1]: 73
1756 13:21:43.380862
1757 13:21:43.380942 Set Vref, RX VrefLevel [Byte0]: 74
1758 13:21:43.384414 [Byte1]: 74
1759 13:21:43.389531
1760 13:21:43.389627 Set Vref, RX VrefLevel [Byte0]: 75
1761 13:21:43.391673 [Byte1]: 75
1762 13:21:43.395936
1763 13:21:43.396032 Final RX Vref Byte 0 = 61 to rank0
1764 13:21:43.400204 Final RX Vref Byte 1 = 54 to rank0
1765 13:21:43.402604 Final RX Vref Byte 0 = 61 to rank1
1766 13:21:43.406222 Final RX Vref Byte 1 = 54 to rank1==
1767 13:21:43.409262 Dram Type= 6, Freq= 0, CH_1, rank 0
1768 13:21:43.415796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1769 13:21:43.415877 ==
1770 13:21:43.415952 DQS Delay:
1771 13:21:43.416013 DQS0 = 0, DQS1 = 0
1772 13:21:43.419584 DQM Delay:
1773 13:21:43.419665 DQM0 = 86, DQM1 = 80
1774 13:21:43.422815 DQ Delay:
1775 13:21:43.425787 DQ0 =88, DQ1 =84, DQ2 =76, DQ3 =84
1776 13:21:43.425897 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1777 13:21:43.429499 DQ8 =64, DQ9 =68, DQ10 =80, DQ11 =76
1778 13:21:43.436197 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1779 13:21:43.436278
1780 13:21:43.436342
1781 13:21:43.442288 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a2d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1782 13:21:43.445796 CH1 RK0: MR19=606, MR18=1A2D
1783 13:21:43.452633 CH1_RK0: MR19=0x606, MR18=0x1A2D, DQSOSC=398, MR23=63, INC=93, DEC=62
1784 13:21:43.452715
1785 13:21:43.456607 ----->DramcWriteLeveling(PI) begin...
1786 13:21:43.456689 ==
1787 13:21:43.458942 Dram Type= 6, Freq= 0, CH_1, rank 1
1788 13:21:43.462200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1789 13:21:43.462281 ==
1790 13:21:43.465724 Write leveling (Byte 0): 25 => 25
1791 13:21:43.469034 Write leveling (Byte 1): 27 => 27
1792 13:21:43.472279 DramcWriteLeveling(PI) end<-----
1793 13:21:43.472360
1794 13:21:43.472423 ==
1795 13:21:43.475552 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 13:21:43.478970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1797 13:21:43.479052 ==
1798 13:21:43.482475 [Gating] SW mode calibration
1799 13:21:43.489159 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1800 13:21:43.495789 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1801 13:21:43.499019 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1802 13:21:43.502271 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1803 13:21:43.508992 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 13:21:43.512647 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 13:21:43.515154 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 13:21:43.522182 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 13:21:43.525482 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 13:21:43.529233 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 13:21:43.535692 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 13:21:43.538934 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 13:21:43.542116 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 13:21:43.548841 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 13:21:43.552067 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 13:21:43.555333 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 13:21:43.561724 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 13:21:43.565493 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 13:21:43.568471 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1818 13:21:43.575134 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1819 13:21:43.578626 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 13:21:43.582045 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 13:21:43.589050 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 13:21:43.591914 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 13:21:43.596009 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 13:21:43.601550 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 13:21:43.605103 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 13:21:43.608430 0 9 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1827 13:21:43.615172 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1828 13:21:43.618492 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 13:21:43.622199 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 13:21:43.628138 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 13:21:43.631835 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 13:21:43.635221 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 13:21:43.641587 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 13:21:43.644490 0 10 4 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (1 1)
1835 13:21:43.648420 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1836 13:21:43.655013 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 13:21:43.658763 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 13:21:43.661266 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 13:21:43.668813 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 13:21:43.672245 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 13:21:43.674535 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1842 13:21:43.681364 0 11 4 | B1->B0 | 2424 3c3c | 0 1 | (1 1) (0 0)
1843 13:21:43.684237 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1844 13:21:43.687784 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 13:21:43.690843 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 13:21:43.697896 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 13:21:43.701094 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 13:21:43.704540 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 13:21:43.711417 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1850 13:21:43.714478 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1851 13:21:43.717769 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 13:21:43.724791 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 13:21:43.727722 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 13:21:43.730946 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 13:21:43.737511 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 13:21:43.741037 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 13:21:43.744464 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 13:21:43.750957 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 13:21:43.754031 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 13:21:43.758037 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 13:21:43.764495 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 13:21:43.767748 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 13:21:43.771010 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 13:21:43.778106 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 13:21:43.780603 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 13:21:43.784052 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1867 13:21:43.786940 Total UI for P1: 0, mck2ui 16
1868 13:21:43.790255 best dqsien dly found for B0: ( 0, 14, 2)
1869 13:21:43.797221 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 13:21:43.797302 Total UI for P1: 0, mck2ui 16
1871 13:21:43.803600 best dqsien dly found for B1: ( 0, 14, 4)
1872 13:21:43.806925 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1873 13:21:43.810301 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1874 13:21:43.810381
1875 13:21:43.814016 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1876 13:21:43.816906 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1877 13:21:43.820498 [Gating] SW calibration Done
1878 13:21:43.820578 ==
1879 13:21:43.823613 Dram Type= 6, Freq= 0, CH_1, rank 1
1880 13:21:43.827017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1881 13:21:43.827098 ==
1882 13:21:43.831017 RX Vref Scan: 0
1883 13:21:43.831097
1884 13:21:43.831161 RX Vref 0 -> 0, step: 1
1885 13:21:43.831221
1886 13:21:43.833352 RX Delay -130 -> 252, step: 16
1887 13:21:43.837047 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1888 13:21:43.844096 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1889 13:21:43.846923 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1890 13:21:43.850295 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1891 13:21:43.853545 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1892 13:21:43.856664 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1893 13:21:43.863693 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1894 13:21:43.866673 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1895 13:21:43.870283 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1896 13:21:43.873430 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1897 13:21:43.876652 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1898 13:21:43.883618 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1899 13:21:43.886855 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1900 13:21:43.890063 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1901 13:21:43.893296 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1902 13:21:43.896262 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1903 13:21:43.900216 ==
1904 13:21:43.903119 Dram Type= 6, Freq= 0, CH_1, rank 1
1905 13:21:43.906246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1906 13:21:43.906327 ==
1907 13:21:43.906391 DQS Delay:
1908 13:21:43.910118 DQS0 = 0, DQS1 = 0
1909 13:21:43.910198 DQM Delay:
1910 13:21:43.913485 DQM0 = 84, DQM1 = 86
1911 13:21:43.913565 DQ Delay:
1912 13:21:43.916374 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1913 13:21:43.920024 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1914 13:21:43.922998 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1915 13:21:43.926667 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1916 13:21:43.926746
1917 13:21:43.926810
1918 13:21:43.926869 ==
1919 13:21:43.929838 Dram Type= 6, Freq= 0, CH_1, rank 1
1920 13:21:43.933720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1921 13:21:43.933802 ==
1922 13:21:43.933867
1923 13:21:43.933925
1924 13:21:43.936469 TX Vref Scan disable
1925 13:21:43.939826 == TX Byte 0 ==
1926 13:21:43.943069 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1927 13:21:43.946252 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1928 13:21:43.950003 == TX Byte 1 ==
1929 13:21:43.953101 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1930 13:21:43.956237 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1931 13:21:43.956318 ==
1932 13:21:43.959779 Dram Type= 6, Freq= 0, CH_1, rank 1
1933 13:21:43.966646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1934 13:21:43.966728 ==
1935 13:21:43.977802 TX Vref=22, minBit 0, minWin=27, winSum=442
1936 13:21:43.981565 TX Vref=24, minBit 1, minWin=27, winSum=447
1937 13:21:43.984775 TX Vref=26, minBit 1, minWin=27, winSum=450
1938 13:21:43.987801 TX Vref=28, minBit 4, minWin=27, winSum=454
1939 13:21:43.991028 TX Vref=30, minBit 1, minWin=28, winSum=457
1940 13:21:43.994409 TX Vref=32, minBit 2, minWin=27, winSum=455
1941 13:21:44.001021 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 30
1942 13:21:44.001102
1943 13:21:44.004790 Final TX Range 1 Vref 30
1944 13:21:44.004871
1945 13:21:44.004935 ==
1946 13:21:44.008155 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 13:21:44.010901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 13:21:44.010982 ==
1949 13:21:44.014304
1950 13:21:44.014405
1951 13:21:44.014470 TX Vref Scan disable
1952 13:21:44.017542 == TX Byte 0 ==
1953 13:21:44.020913 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1954 13:21:44.028025 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1955 13:21:44.028131 == TX Byte 1 ==
1956 13:21:44.030927 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1957 13:21:44.037634 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1958 13:21:44.037714
1959 13:21:44.037778 [DATLAT]
1960 13:21:44.037837 Freq=800, CH1 RK1
1961 13:21:44.037899
1962 13:21:44.041405 DATLAT Default: 0xa
1963 13:21:44.041485 0, 0xFFFF, sum = 0
1964 13:21:44.044235 1, 0xFFFF, sum = 0
1965 13:21:44.044317 2, 0xFFFF, sum = 0
1966 13:21:44.047663 3, 0xFFFF, sum = 0
1967 13:21:44.050898 4, 0xFFFF, sum = 0
1968 13:21:44.050981 5, 0xFFFF, sum = 0
1969 13:21:44.054315 6, 0xFFFF, sum = 0
1970 13:21:44.054397 7, 0xFFFF, sum = 0
1971 13:21:44.057381 8, 0xFFFF, sum = 0
1972 13:21:44.057463 9, 0x0, sum = 1
1973 13:21:44.060707 10, 0x0, sum = 2
1974 13:21:44.060790 11, 0x0, sum = 3
1975 13:21:44.060856 12, 0x0, sum = 4
1976 13:21:44.064221 best_step = 10
1977 13:21:44.064302
1978 13:21:44.064366 ==
1979 13:21:44.067590 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 13:21:44.070653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 13:21:44.070735 ==
1982 13:21:44.074280 RX Vref Scan: 0
1983 13:21:44.074362
1984 13:21:44.074427 RX Vref 0 -> 0, step: 1
1985 13:21:44.077797
1986 13:21:44.077878 RX Delay -95 -> 252, step: 8
1987 13:21:44.084316 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1988 13:21:44.087565 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1989 13:21:44.091271 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1990 13:21:44.094430 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1991 13:21:44.098007 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1992 13:21:44.103871 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1993 13:21:44.107642 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1994 13:21:44.110918 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1995 13:21:44.113966 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1996 13:21:44.117263 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1997 13:21:44.124500 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
1998 13:21:44.127572 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1999 13:21:44.131379 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2000 13:21:44.134154 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2001 13:21:44.140561 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
2002 13:21:44.144239 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2003 13:21:44.144321 ==
2004 13:21:44.147423 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 13:21:44.150731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 13:21:44.150813 ==
2007 13:21:44.153998 DQS Delay:
2008 13:21:44.154079 DQS0 = 0, DQS1 = 0
2009 13:21:44.154145 DQM Delay:
2010 13:21:44.157360 DQM0 = 86, DQM1 = 82
2011 13:21:44.157442 DQ Delay:
2012 13:21:44.160434 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2013 13:21:44.163770 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2014 13:21:44.166951 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =76
2015 13:21:44.170603 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =88
2016 13:21:44.170684
2017 13:21:44.170749
2018 13:21:44.180190 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c37, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2019 13:21:44.180273 CH1 RK1: MR19=606, MR18=1C37
2020 13:21:44.186911 CH1_RK1: MR19=0x606, MR18=0x1C37, DQSOSC=395, MR23=63, INC=94, DEC=63
2021 13:21:44.190204 [RxdqsGatingPostProcess] freq 800
2022 13:21:44.197762 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2023 13:21:44.200531 Pre-setting of DQS Precalculation
2024 13:21:44.203551 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2025 13:21:44.210419 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2026 13:21:44.220551 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2027 13:21:44.220635
2028 13:21:44.220699
2029 13:21:44.223451 [Calibration Summary] 1600 Mbps
2030 13:21:44.223532 CH 0, Rank 0
2031 13:21:44.226694 SW Impedance : PASS
2032 13:21:44.226776 DUTY Scan : NO K
2033 13:21:44.230772 ZQ Calibration : PASS
2034 13:21:44.234065 Jitter Meter : NO K
2035 13:21:44.234147 CBT Training : PASS
2036 13:21:44.236771 Write leveling : PASS
2037 13:21:44.240349 RX DQS gating : PASS
2038 13:21:44.240430 RX DQ/DQS(RDDQC) : PASS
2039 13:21:44.243741 TX DQ/DQS : PASS
2040 13:21:44.243822 RX DATLAT : PASS
2041 13:21:44.246581 RX DQ/DQS(Engine): PASS
2042 13:21:44.250675 TX OE : NO K
2043 13:21:44.250758 All Pass.
2044 13:21:44.250822
2045 13:21:44.250882 CH 0, Rank 1
2046 13:21:44.253947 SW Impedance : PASS
2047 13:21:44.257162 DUTY Scan : NO K
2048 13:21:44.257243 ZQ Calibration : PASS
2049 13:21:44.260916 Jitter Meter : NO K
2050 13:21:44.263307 CBT Training : PASS
2051 13:21:44.263388 Write leveling : PASS
2052 13:21:44.266294 RX DQS gating : PASS
2053 13:21:44.269664 RX DQ/DQS(RDDQC) : PASS
2054 13:21:44.269745 TX DQ/DQS : PASS
2055 13:21:44.273705 RX DATLAT : PASS
2056 13:21:44.276201 RX DQ/DQS(Engine): PASS
2057 13:21:44.276282 TX OE : NO K
2058 13:21:44.279820 All Pass.
2059 13:21:44.279901
2060 13:21:44.279976 CH 1, Rank 0
2061 13:21:44.283470 SW Impedance : PASS
2062 13:21:44.283551 DUTY Scan : NO K
2063 13:21:44.286876 ZQ Calibration : PASS
2064 13:21:44.289863 Jitter Meter : NO K
2065 13:21:44.289945 CBT Training : PASS
2066 13:21:44.293065 Write leveling : PASS
2067 13:21:44.296776 RX DQS gating : PASS
2068 13:21:44.296858 RX DQ/DQS(RDDQC) : PASS
2069 13:21:44.300105 TX DQ/DQS : PASS
2070 13:21:44.300187 RX DATLAT : PASS
2071 13:21:44.302740 RX DQ/DQS(Engine): PASS
2072 13:21:44.306496 TX OE : NO K
2073 13:21:44.306578 All Pass.
2074 13:21:44.306643
2075 13:21:44.306703 CH 1, Rank 1
2076 13:21:44.309650 SW Impedance : PASS
2077 13:21:44.313225 DUTY Scan : NO K
2078 13:21:44.313308 ZQ Calibration : PASS
2079 13:21:44.316351 Jitter Meter : NO K
2080 13:21:44.319544 CBT Training : PASS
2081 13:21:44.319625 Write leveling : PASS
2082 13:21:44.322777 RX DQS gating : PASS
2083 13:21:44.326763 RX DQ/DQS(RDDQC) : PASS
2084 13:21:44.326844 TX DQ/DQS : PASS
2085 13:21:44.330195 RX DATLAT : PASS
2086 13:21:44.332918 RX DQ/DQS(Engine): PASS
2087 13:21:44.333000 TX OE : NO K
2088 13:21:44.336666 All Pass.
2089 13:21:44.336748
2090 13:21:44.336812 DramC Write-DBI off
2091 13:21:44.339715 PER_BANK_REFRESH: Hybrid Mode
2092 13:21:44.339796 TX_TRACKING: ON
2093 13:21:44.343278 [GetDramInforAfterCalByMRR] Vendor 6.
2094 13:21:44.349294 [GetDramInforAfterCalByMRR] Revision 606.
2095 13:21:44.352582 [GetDramInforAfterCalByMRR] Revision 2 0.
2096 13:21:44.352665 MR0 0x3b3b
2097 13:21:44.352731 MR8 0x5151
2098 13:21:44.356381 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2099 13:21:44.356480
2100 13:21:44.359784 MR0 0x3b3b
2101 13:21:44.359865 MR8 0x5151
2102 13:21:44.362958 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2103 13:21:44.363040
2104 13:21:44.372708 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2105 13:21:44.375887 [FAST_K] Save calibration result to emmc
2106 13:21:44.379490 [FAST_K] Save calibration result to emmc
2107 13:21:44.382837 dram_init: config_dvfs: 1
2108 13:21:44.385870 dramc_set_vcore_voltage set vcore to 662500
2109 13:21:44.389214 Read voltage for 1200, 2
2110 13:21:44.389295 Vio18 = 0
2111 13:21:44.389360 Vcore = 662500
2112 13:21:44.392618 Vdram = 0
2113 13:21:44.392718 Vddq = 0
2114 13:21:44.392826 Vmddr = 0
2115 13:21:44.399227 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2116 13:21:44.402485 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2117 13:21:44.406029 MEM_TYPE=3, freq_sel=15
2118 13:21:44.408926 sv_algorithm_assistance_LP4_1600
2119 13:21:44.412558 ============ PULL DRAM RESETB DOWN ============
2120 13:21:44.416189 ========== PULL DRAM RESETB DOWN end =========
2121 13:21:44.422604 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2122 13:21:44.425562 ===================================
2123 13:21:44.425644 LPDDR4 DRAM CONFIGURATION
2124 13:21:44.429435 ===================================
2125 13:21:44.432739 EX_ROW_EN[0] = 0x0
2126 13:21:44.435520 EX_ROW_EN[1] = 0x0
2127 13:21:44.435601 LP4Y_EN = 0x0
2128 13:21:44.438984 WORK_FSP = 0x0
2129 13:21:44.439066 WL = 0x4
2130 13:21:44.442583 RL = 0x4
2131 13:21:44.442664 BL = 0x2
2132 13:21:44.445615 RPST = 0x0
2133 13:21:44.445696 RD_PRE = 0x0
2134 13:21:44.449126 WR_PRE = 0x1
2135 13:21:44.449207 WR_PST = 0x0
2136 13:21:44.452237 DBI_WR = 0x0
2137 13:21:44.452318 DBI_RD = 0x0
2138 13:21:44.455779 OTF = 0x1
2139 13:21:44.458983 ===================================
2140 13:21:44.463136 ===================================
2141 13:21:44.463218 ANA top config
2142 13:21:44.465933 ===================================
2143 13:21:44.468961 DLL_ASYNC_EN = 0
2144 13:21:44.472982 ALL_SLAVE_EN = 0
2145 13:21:44.473064 NEW_RANK_MODE = 1
2146 13:21:44.475917 DLL_IDLE_MODE = 1
2147 13:21:44.479799 LP45_APHY_COMB_EN = 1
2148 13:21:44.482827 TX_ODT_DIS = 1
2149 13:21:44.485902 NEW_8X_MODE = 1
2150 13:21:44.489561 ===================================
2151 13:21:44.492603 ===================================
2152 13:21:44.492685 data_rate = 2400
2153 13:21:44.495861 CKR = 1
2154 13:21:44.498946 DQ_P2S_RATIO = 8
2155 13:21:44.502864 ===================================
2156 13:21:44.505776 CA_P2S_RATIO = 8
2157 13:21:44.509130 DQ_CA_OPEN = 0
2158 13:21:44.512798 DQ_SEMI_OPEN = 0
2159 13:21:44.512880 CA_SEMI_OPEN = 0
2160 13:21:44.515961 CA_FULL_RATE = 0
2161 13:21:44.519025 DQ_CKDIV4_EN = 0
2162 13:21:44.522093 CA_CKDIV4_EN = 0
2163 13:21:44.525458 CA_PREDIV_EN = 0
2164 13:21:44.529024 PH8_DLY = 17
2165 13:21:44.529106 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2166 13:21:44.532454 DQ_AAMCK_DIV = 4
2167 13:21:44.535466 CA_AAMCK_DIV = 4
2168 13:21:44.539369 CA_ADMCK_DIV = 4
2169 13:21:44.542200 DQ_TRACK_CA_EN = 0
2170 13:21:44.545515 CA_PICK = 1200
2171 13:21:44.549047 CA_MCKIO = 1200
2172 13:21:44.549132 MCKIO_SEMI = 0
2173 13:21:44.552476 PLL_FREQ = 2366
2174 13:21:44.555458 DQ_UI_PI_RATIO = 32
2175 13:21:44.559198 CA_UI_PI_RATIO = 0
2176 13:21:44.562018 ===================================
2177 13:21:44.565753 ===================================
2178 13:21:44.568855 memory_type:LPDDR4
2179 13:21:44.568937 GP_NUM : 10
2180 13:21:44.571955 SRAM_EN : 1
2181 13:21:44.575591 MD32_EN : 0
2182 13:21:44.579215 ===================================
2183 13:21:44.579297 [ANA_INIT] >>>>>>>>>>>>>>
2184 13:21:44.582187 <<<<<< [CONFIGURE PHASE]: ANA_TX
2185 13:21:44.585393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2186 13:21:44.589397 ===================================
2187 13:21:44.591864 data_rate = 2400,PCW = 0X5b00
2188 13:21:44.595676 ===================================
2189 13:21:44.598928 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2190 13:21:44.605075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2191 13:21:44.609005 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2192 13:21:44.615301 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2193 13:21:44.618669 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2194 13:21:44.621981 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2195 13:21:44.622062 [ANA_INIT] flow start
2196 13:21:44.626197 [ANA_INIT] PLL >>>>>>>>
2197 13:21:44.628210 [ANA_INIT] PLL <<<<<<<<
2198 13:21:44.631824 [ANA_INIT] MIDPI >>>>>>>>
2199 13:21:44.631913 [ANA_INIT] MIDPI <<<<<<<<
2200 13:21:44.635071 [ANA_INIT] DLL >>>>>>>>
2201 13:21:44.638248 [ANA_INIT] DLL <<<<<<<<
2202 13:21:44.638328 [ANA_INIT] flow end
2203 13:21:44.641304 ============ LP4 DIFF to SE enter ============
2204 13:21:44.648150 ============ LP4 DIFF to SE exit ============
2205 13:21:44.648231 [ANA_INIT] <<<<<<<<<<<<<
2206 13:21:44.651366 [Flow] Enable top DCM control >>>>>
2207 13:21:44.654570 [Flow] Enable top DCM control <<<<<
2208 13:21:44.657738 Enable DLL master slave shuffle
2209 13:21:44.665098 ==============================================================
2210 13:21:44.668256 Gating Mode config
2211 13:21:44.671191 ==============================================================
2212 13:21:44.674625 Config description:
2213 13:21:44.684578 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2214 13:21:44.691382 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2215 13:21:44.694801 SELPH_MODE 0: By rank 1: By Phase
2216 13:21:44.701125 ==============================================================
2217 13:21:44.704410 GAT_TRACK_EN = 1
2218 13:21:44.708036 RX_GATING_MODE = 2
2219 13:21:44.711241 RX_GATING_TRACK_MODE = 2
2220 13:21:44.711333 SELPH_MODE = 1
2221 13:21:44.714220 PICG_EARLY_EN = 1
2222 13:21:44.717903 VALID_LAT_VALUE = 1
2223 13:21:44.724571 ==============================================================
2224 13:21:44.727353 Enter into Gating configuration >>>>
2225 13:21:44.731040 Exit from Gating configuration <<<<
2226 13:21:44.734787 Enter into DVFS_PRE_config >>>>>
2227 13:21:44.744287 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2228 13:21:44.747282 Exit from DVFS_PRE_config <<<<<
2229 13:21:44.750656 Enter into PICG configuration >>>>
2230 13:21:44.754193 Exit from PICG configuration <<<<
2231 13:21:44.757308 [RX_INPUT] configuration >>>>>
2232 13:21:44.760762 [RX_INPUT] configuration <<<<<
2233 13:21:44.763622 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2234 13:21:44.770405 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2235 13:21:44.777112 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2236 13:21:44.783649 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2237 13:21:44.790583 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2238 13:21:44.794332 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2239 13:21:44.800790 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2240 13:21:44.804373 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2241 13:21:44.807219 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2242 13:21:44.810485 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2243 13:21:44.813967 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2244 13:21:44.820325 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2245 13:21:44.824235 ===================================
2246 13:21:44.827283 LPDDR4 DRAM CONFIGURATION
2247 13:21:44.830749 ===================================
2248 13:21:44.830830 EX_ROW_EN[0] = 0x0
2249 13:21:44.833577 EX_ROW_EN[1] = 0x0
2250 13:21:44.833657 LP4Y_EN = 0x0
2251 13:21:44.836774 WORK_FSP = 0x0
2252 13:21:44.836855 WL = 0x4
2253 13:21:44.840714 RL = 0x4
2254 13:21:44.840795 BL = 0x2
2255 13:21:44.844996 RPST = 0x0
2256 13:21:44.845076 RD_PRE = 0x0
2257 13:21:44.847104 WR_PRE = 0x1
2258 13:21:44.847184 WR_PST = 0x0
2259 13:21:44.850491 DBI_WR = 0x0
2260 13:21:44.850572 DBI_RD = 0x0
2261 13:21:44.853394 OTF = 0x1
2262 13:21:44.857065 ===================================
2263 13:21:44.860332 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2264 13:21:44.863659 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2265 13:21:44.870296 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2266 13:21:44.873509 ===================================
2267 13:21:44.873590 LPDDR4 DRAM CONFIGURATION
2268 13:21:44.876977 ===================================
2269 13:21:44.880212 EX_ROW_EN[0] = 0x10
2270 13:21:44.883666 EX_ROW_EN[1] = 0x0
2271 13:21:44.883746 LP4Y_EN = 0x0
2272 13:21:44.886841 WORK_FSP = 0x0
2273 13:21:44.886922 WL = 0x4
2274 13:21:44.889962 RL = 0x4
2275 13:21:44.890043 BL = 0x2
2276 13:21:44.893611 RPST = 0x0
2277 13:21:44.893705 RD_PRE = 0x0
2278 13:21:44.896658 WR_PRE = 0x1
2279 13:21:44.896739 WR_PST = 0x0
2280 13:21:44.899838 DBI_WR = 0x0
2281 13:21:44.899956 DBI_RD = 0x0
2282 13:21:44.903349 OTF = 0x1
2283 13:21:44.906642 ===================================
2284 13:21:44.914203 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2285 13:21:44.914284 ==
2286 13:21:44.917368 Dram Type= 6, Freq= 0, CH_0, rank 0
2287 13:21:44.920259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2288 13:21:44.920341 ==
2289 13:21:44.923760 [Duty_Offset_Calibration]
2290 13:21:44.923840 B0:2 B1:0 CA:4
2291 13:21:44.923912
2292 13:21:44.926684 [DutyScan_Calibration_Flow] k_type=0
2293 13:21:44.936150
2294 13:21:44.936231 ==CLK 0==
2295 13:21:44.939854 Final CLK duty delay cell = -4
2296 13:21:44.942904 [-4] MAX Duty = 5031%(X100), DQS PI = 18
2297 13:21:44.946068 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2298 13:21:44.949835 [-4] AVG Duty = 4937%(X100)
2299 13:21:44.949916
2300 13:21:44.952910 CH0 CLK Duty spec in!! Max-Min= 187%
2301 13:21:44.956292 [DutyScan_Calibration_Flow] ====Done====
2302 13:21:44.956372
2303 13:21:44.959149 [DutyScan_Calibration_Flow] k_type=1
2304 13:21:44.975758
2305 13:21:44.975838 ==DQS 0 ==
2306 13:21:44.979490 Final DQS duty delay cell = 0
2307 13:21:44.982918 [0] MAX Duty = 5156%(X100), DQS PI = 18
2308 13:21:44.985972 [0] MIN Duty = 5093%(X100), DQS PI = 0
2309 13:21:44.986052 [0] AVG Duty = 5124%(X100)
2310 13:21:44.989029
2311 13:21:44.989148 ==DQS 1 ==
2312 13:21:44.992699 Final DQS duty delay cell = 0
2313 13:21:44.995609 [0] MAX Duty = 5125%(X100), DQS PI = 4
2314 13:21:44.999147 [0] MIN Duty = 5000%(X100), DQS PI = 0
2315 13:21:45.002515 [0] AVG Duty = 5062%(X100)
2316 13:21:45.002595
2317 13:21:45.005457 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2318 13:21:45.005538
2319 13:21:45.009271 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2320 13:21:45.012304 [DutyScan_Calibration_Flow] ====Done====
2321 13:21:45.012408
2322 13:21:45.015300 [DutyScan_Calibration_Flow] k_type=3
2323 13:21:45.032006
2324 13:21:45.032142 ==DQM 0 ==
2325 13:21:45.035303 Final DQM duty delay cell = 0
2326 13:21:45.039346 [0] MAX Duty = 5125%(X100), DQS PI = 20
2327 13:21:45.042460 [0] MIN Duty = 4844%(X100), DQS PI = 54
2328 13:21:45.045530 [0] AVG Duty = 4984%(X100)
2329 13:21:45.045611
2330 13:21:45.045675 ==DQM 1 ==
2331 13:21:45.048943 Final DQM duty delay cell = 0
2332 13:21:45.051954 [0] MAX Duty = 4969%(X100), DQS PI = 2
2333 13:21:45.055542 [0] MIN Duty = 4907%(X100), DQS PI = 12
2334 13:21:45.055649 [0] AVG Duty = 4938%(X100)
2335 13:21:45.058722
2336 13:21:45.062074 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2337 13:21:45.062166
2338 13:21:45.065208 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2339 13:21:45.069174 [DutyScan_Calibration_Flow] ====Done====
2340 13:21:45.069273
2341 13:21:45.071947 [DutyScan_Calibration_Flow] k_type=2
2342 13:21:45.089704
2343 13:21:45.089798 ==DQ 0 ==
2344 13:21:45.091982 Final DQ duty delay cell = 0
2345 13:21:45.095218 [0] MAX Duty = 5125%(X100), DQS PI = 18
2346 13:21:45.098500 [0] MIN Duty = 4969%(X100), DQS PI = 52
2347 13:21:45.098591 [0] AVG Duty = 5047%(X100)
2348 13:21:45.101486
2349 13:21:45.101577 ==DQ 1 ==
2350 13:21:45.105586 Final DQ duty delay cell = 0
2351 13:21:45.108316 [0] MAX Duty = 5125%(X100), DQS PI = 4
2352 13:21:45.111886 [0] MIN Duty = 4938%(X100), DQS PI = 14
2353 13:21:45.111995 [0] AVG Duty = 5031%(X100)
2354 13:21:45.114972
2355 13:21:45.118266 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2356 13:21:45.118348
2357 13:21:45.121602 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2358 13:21:45.125394 [DutyScan_Calibration_Flow] ====Done====
2359 13:21:45.125476 ==
2360 13:21:45.128324 Dram Type= 6, Freq= 0, CH_1, rank 0
2361 13:21:45.131564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2362 13:21:45.131700 ==
2363 13:21:45.135270 [Duty_Offset_Calibration]
2364 13:21:45.135353 B0:0 B1:-1 CA:3
2365 13:21:45.135418
2366 13:21:45.137981 [DutyScan_Calibration_Flow] k_type=0
2367 13:21:45.147550
2368 13:21:45.147676 ==CLK 0==
2369 13:21:45.150821 Final CLK duty delay cell = -4
2370 13:21:45.154392 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2371 13:21:45.157833 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2372 13:21:45.161356 [-4] AVG Duty = 4938%(X100)
2373 13:21:45.161438
2374 13:21:45.164976 CH1 CLK Duty spec in!! Max-Min= 124%
2375 13:21:45.168066 [DutyScan_Calibration_Flow] ====Done====
2376 13:21:45.168179
2377 13:21:45.170686 [DutyScan_Calibration_Flow] k_type=1
2378 13:21:45.187074
2379 13:21:45.187196 ==DQS 0 ==
2380 13:21:45.189598 Final DQS duty delay cell = 0
2381 13:21:45.192912 [0] MAX Duty = 5187%(X100), DQS PI = 28
2382 13:21:45.196377 [0] MIN Duty = 4907%(X100), DQS PI = 38
2383 13:21:45.199526 [0] AVG Duty = 5047%(X100)
2384 13:21:45.199631
2385 13:21:45.199722 ==DQS 1 ==
2386 13:21:45.203294 Final DQS duty delay cell = -4
2387 13:21:45.206546 [-4] MAX Duty = 5000%(X100), DQS PI = 10
2388 13:21:45.209783 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2389 13:21:45.212744 [-4] AVG Duty = 4937%(X100)
2390 13:21:45.212847
2391 13:21:45.216252 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2392 13:21:45.216334
2393 13:21:45.220330 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2394 13:21:45.222704 [DutyScan_Calibration_Flow] ====Done====
2395 13:21:45.222786
2396 13:21:45.225963 [DutyScan_Calibration_Flow] k_type=3
2397 13:21:45.243329
2398 13:21:45.243411 ==DQM 0 ==
2399 13:21:45.246671 Final DQM duty delay cell = 0
2400 13:21:45.249850 [0] MAX Duty = 5031%(X100), DQS PI = 28
2401 13:21:45.253299 [0] MIN Duty = 4813%(X100), DQS PI = 38
2402 13:21:45.256740 [0] AVG Duty = 4922%(X100)
2403 13:21:45.256822
2404 13:21:45.256886 ==DQM 1 ==
2405 13:21:45.259737 Final DQM duty delay cell = 0
2406 13:21:45.263477 [0] MAX Duty = 5000%(X100), DQS PI = 34
2407 13:21:45.266818 [0] MIN Duty = 4844%(X100), DQS PI = 0
2408 13:21:45.269797 [0] AVG Duty = 4922%(X100)
2409 13:21:45.269879
2410 13:21:45.272971 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2411 13:21:45.273053
2412 13:21:45.276544 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2413 13:21:45.279588 [DutyScan_Calibration_Flow] ====Done====
2414 13:21:45.279669
2415 13:21:45.282872 [DutyScan_Calibration_Flow] k_type=2
2416 13:21:45.299456
2417 13:21:45.299537 ==DQ 0 ==
2418 13:21:45.302277 Final DQ duty delay cell = -4
2419 13:21:45.305665 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2420 13:21:45.309392 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2421 13:21:45.313137 [-4] AVG Duty = 4937%(X100)
2422 13:21:45.313218
2423 13:21:45.313282 ==DQ 1 ==
2424 13:21:45.315630 Final DQ duty delay cell = 0
2425 13:21:45.319114 [0] MAX Duty = 5031%(X100), DQS PI = 34
2426 13:21:45.323076 [0] MIN Duty = 4844%(X100), DQS PI = 62
2427 13:21:45.325846 [0] AVG Duty = 4937%(X100)
2428 13:21:45.325928
2429 13:21:45.328808 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2430 13:21:45.328890
2431 13:21:45.332538 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2432 13:21:45.335640 [DutyScan_Calibration_Flow] ====Done====
2433 13:21:45.338852 nWR fixed to 30
2434 13:21:45.342524 [ModeRegInit_LP4] CH0 RK0
2435 13:21:45.342606 [ModeRegInit_LP4] CH0 RK1
2436 13:21:45.345667 [ModeRegInit_LP4] CH1 RK0
2437 13:21:45.348970 [ModeRegInit_LP4] CH1 RK1
2438 13:21:45.349053 match AC timing 7
2439 13:21:45.355587 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2440 13:21:45.358815 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2441 13:21:45.362869 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2442 13:21:45.369068 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2443 13:21:45.372432 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2444 13:21:45.372514 ==
2445 13:21:45.375759 Dram Type= 6, Freq= 0, CH_0, rank 0
2446 13:21:45.379109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2447 13:21:45.379191 ==
2448 13:21:45.385567 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2449 13:21:45.392059 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2450 13:21:45.399600 [CA 0] Center 39 (9~70) winsize 62
2451 13:21:45.402557 [CA 1] Center 39 (9~70) winsize 62
2452 13:21:45.405943 [CA 2] Center 35 (5~66) winsize 62
2453 13:21:45.409319 [CA 3] Center 35 (5~66) winsize 62
2454 13:21:45.412610 [CA 4] Center 33 (3~64) winsize 62
2455 13:21:45.415924 [CA 5] Center 33 (3~64) winsize 62
2456 13:21:45.416006
2457 13:21:45.419396 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2458 13:21:45.419476
2459 13:21:45.422893 [CATrainingPosCal] consider 1 rank data
2460 13:21:45.425724 u2DelayCellTimex100 = 270/100 ps
2461 13:21:45.430159 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2462 13:21:45.436204 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2463 13:21:45.439469 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2464 13:21:45.442625 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2465 13:21:45.446228 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2466 13:21:45.448958 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2467 13:21:45.449039
2468 13:21:45.452670 CA PerBit enable=1, Macro0, CA PI delay=33
2469 13:21:45.452751
2470 13:21:45.455609 [CBTSetCACLKResult] CA Dly = 33
2471 13:21:45.455690 CS Dly: 7 (0~38)
2472 13:21:45.459331 ==
2473 13:21:45.462579 Dram Type= 6, Freq= 0, CH_0, rank 1
2474 13:21:45.465583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2475 13:21:45.465665 ==
2476 13:21:45.468874 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2477 13:21:45.475828 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2478 13:21:45.485439 [CA 0] Center 39 (9~70) winsize 62
2479 13:21:45.488839 [CA 1] Center 39 (9~70) winsize 62
2480 13:21:45.492017 [CA 2] Center 35 (5~66) winsize 62
2481 13:21:45.495107 [CA 3] Center 35 (5~66) winsize 62
2482 13:21:45.498443 [CA 4] Center 34 (4~65) winsize 62
2483 13:21:45.501968 [CA 5] Center 33 (3~64) winsize 62
2484 13:21:45.502048
2485 13:21:45.505392 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2486 13:21:45.505473
2487 13:21:45.508598 [CATrainingPosCal] consider 2 rank data
2488 13:21:45.511741 u2DelayCellTimex100 = 270/100 ps
2489 13:21:45.515354 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2490 13:21:45.518477 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2491 13:21:45.524932 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2492 13:21:45.529316 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2493 13:21:45.531808 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2494 13:21:45.536094 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2495 13:21:45.536176
2496 13:21:45.538287 CA PerBit enable=1, Macro0, CA PI delay=33
2497 13:21:45.538368
2498 13:21:45.541963 [CBTSetCACLKResult] CA Dly = 33
2499 13:21:45.542044 CS Dly: 8 (0~41)
2500 13:21:45.542108
2501 13:21:45.545128 ----->DramcWriteLeveling(PI) begin...
2502 13:21:45.548358 ==
2503 13:21:45.551922 Dram Type= 6, Freq= 0, CH_0, rank 0
2504 13:21:45.555215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2505 13:21:45.555296 ==
2506 13:21:45.558758 Write leveling (Byte 0): 29 => 29
2507 13:21:45.561741 Write leveling (Byte 1): 29 => 29
2508 13:21:45.565201 DramcWriteLeveling(PI) end<-----
2509 13:21:45.565282
2510 13:21:45.565346 ==
2511 13:21:45.568489 Dram Type= 6, Freq= 0, CH_0, rank 0
2512 13:21:45.571297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 13:21:45.571378 ==
2514 13:21:45.575345 [Gating] SW mode calibration
2515 13:21:45.581425 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2516 13:21:45.588053 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2517 13:21:45.591703 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2518 13:21:45.594621 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2519 13:21:45.601300 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 13:21:45.605236 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 13:21:45.607919 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 13:21:45.614345 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 13:21:45.617718 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2524 13:21:45.621191 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2525 13:21:45.627871 1 0 0 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
2526 13:21:45.631941 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2527 13:21:45.634438 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 13:21:45.637970 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 13:21:45.644576 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 13:21:45.647848 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 13:21:45.651096 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2532 13:21:45.657705 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2533 13:21:45.660737 1 1 0 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
2534 13:21:45.664255 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2535 13:21:45.671216 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 13:21:45.674238 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 13:21:45.677626 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 13:21:45.683922 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 13:21:45.687491 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 13:21:45.690571 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2541 13:21:45.697485 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2542 13:21:45.700797 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 13:21:45.704472 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 13:21:45.710875 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 13:21:45.714015 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 13:21:45.717747 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 13:21:45.724990 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 13:21:45.727620 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 13:21:45.730828 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 13:21:45.737128 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 13:21:45.740425 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 13:21:45.744163 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 13:21:45.750466 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 13:21:45.753669 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 13:21:45.756994 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2556 13:21:45.764281 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2557 13:21:45.764363 Total UI for P1: 0, mck2ui 16
2558 13:21:45.770765 best dqsien dly found for B0: ( 1, 3, 24)
2559 13:21:45.774219 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2560 13:21:45.777200 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 13:21:45.780469 Total UI for P1: 0, mck2ui 16
2562 13:21:45.783887 best dqsien dly found for B1: ( 1, 4, 0)
2563 13:21:45.787027 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2564 13:21:45.790968 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2565 13:21:45.791049
2566 13:21:45.793475 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2567 13:21:45.800826 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2568 13:21:45.800907 [Gating] SW calibration Done
2569 13:21:45.800971 ==
2570 13:21:45.804028 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 13:21:45.810380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 13:21:45.810475 ==
2573 13:21:45.810539 RX Vref Scan: 0
2574 13:21:45.810599
2575 13:21:45.813555 RX Vref 0 -> 0, step: 1
2576 13:21:45.813635
2577 13:21:45.817123 RX Delay -40 -> 252, step: 8
2578 13:21:45.820177 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2579 13:21:45.823606 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2580 13:21:45.826891 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2581 13:21:45.833277 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2582 13:21:45.836766 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2583 13:21:45.840128 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2584 13:21:45.842946 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2585 13:21:45.846921 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2586 13:21:45.852980 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2587 13:21:45.856277 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2588 13:21:45.859711 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2589 13:21:45.863164 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2590 13:21:45.866840 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2591 13:21:45.873418 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2592 13:21:45.876507 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2593 13:21:45.879437 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2594 13:21:45.879517 ==
2595 13:21:45.882897 Dram Type= 6, Freq= 0, CH_0, rank 0
2596 13:21:45.886731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2597 13:21:45.886812 ==
2598 13:21:45.889823 DQS Delay:
2599 13:21:45.889904 DQS0 = 0, DQS1 = 0
2600 13:21:45.893202 DQM Delay:
2601 13:21:45.893282 DQM0 = 118, DQM1 = 108
2602 13:21:45.896080 DQ Delay:
2603 13:21:45.899696 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =115
2604 13:21:45.902729 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =127
2605 13:21:45.906616 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2606 13:21:45.909693 DQ12 =119, DQ13 =115, DQ14 =119, DQ15 =115
2607 13:21:45.909774
2608 13:21:45.909855
2609 13:21:45.909928 ==
2610 13:21:45.913861 Dram Type= 6, Freq= 0, CH_0, rank 0
2611 13:21:45.916320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2612 13:21:45.916400 ==
2613 13:21:45.916464
2614 13:21:45.916523
2615 13:21:45.919302 TX Vref Scan disable
2616 13:21:45.922952 == TX Byte 0 ==
2617 13:21:45.926280 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2618 13:21:45.929970 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2619 13:21:45.932901 == TX Byte 1 ==
2620 13:21:45.935848 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2621 13:21:45.939778 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2622 13:21:45.939858 ==
2623 13:21:45.942711 Dram Type= 6, Freq= 0, CH_0, rank 0
2624 13:21:45.945811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2625 13:21:45.949260 ==
2626 13:21:45.959197 TX Vref=22, minBit 1, minWin=24, winSum=411
2627 13:21:45.962822 TX Vref=24, minBit 4, minWin=25, winSum=420
2628 13:21:45.966012 TX Vref=26, minBit 0, minWin=26, winSum=426
2629 13:21:45.969776 TX Vref=28, minBit 1, minWin=26, winSum=428
2630 13:21:45.972824 TX Vref=30, minBit 10, minWin=26, winSum=430
2631 13:21:45.979041 TX Vref=32, minBit 0, minWin=26, winSum=427
2632 13:21:45.982203 [TxChooseVref] Worse bit 10, Min win 26, Win sum 430, Final Vref 30
2633 13:21:45.982284
2634 13:21:45.985502 Final TX Range 1 Vref 30
2635 13:21:45.985583
2636 13:21:45.985647 ==
2637 13:21:45.989491 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 13:21:45.992187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 13:21:45.995450 ==
2640 13:21:45.995559
2641 13:21:45.995624
2642 13:21:45.995684 TX Vref Scan disable
2643 13:21:45.999448 == TX Byte 0 ==
2644 13:21:46.002317 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2645 13:21:46.009444 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2646 13:21:46.009525 == TX Byte 1 ==
2647 13:21:46.012285 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2648 13:21:46.019070 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2649 13:21:46.019151
2650 13:21:46.019214 [DATLAT]
2651 13:21:46.019274 Freq=1200, CH0 RK0
2652 13:21:46.019332
2653 13:21:46.022410 DATLAT Default: 0xd
2654 13:21:46.022495 0, 0xFFFF, sum = 0
2655 13:21:46.026143 1, 0xFFFF, sum = 0
2656 13:21:46.028891 2, 0xFFFF, sum = 0
2657 13:21:46.028990 3, 0xFFFF, sum = 0
2658 13:21:46.032458 4, 0xFFFF, sum = 0
2659 13:21:46.032533 5, 0xFFFF, sum = 0
2660 13:21:46.035299 6, 0xFFFF, sum = 0
2661 13:21:46.035394 7, 0xFFFF, sum = 0
2662 13:21:46.039303 8, 0xFFFF, sum = 0
2663 13:21:46.039398 9, 0xFFFF, sum = 0
2664 13:21:46.041994 10, 0xFFFF, sum = 0
2665 13:21:46.042065 11, 0xFFFF, sum = 0
2666 13:21:46.045866 12, 0x0, sum = 1
2667 13:21:46.045934 13, 0x0, sum = 2
2668 13:21:46.048815 14, 0x0, sum = 3
2669 13:21:46.048891 15, 0x0, sum = 4
2670 13:21:46.052081 best_step = 13
2671 13:21:46.052180
2672 13:21:46.052270 ==
2673 13:21:46.055597 Dram Type= 6, Freq= 0, CH_0, rank 0
2674 13:21:46.059012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2675 13:21:46.059112 ==
2676 13:21:46.059201 RX Vref Scan: 1
2677 13:21:46.062024
2678 13:21:46.062122 Set Vref Range= 32 -> 127
2679 13:21:46.062209
2680 13:21:46.065693 RX Vref 32 -> 127, step: 1
2681 13:21:46.065775
2682 13:21:46.069058 RX Delay -21 -> 252, step: 4
2683 13:21:46.069138
2684 13:21:46.072173 Set Vref, RX VrefLevel [Byte0]: 32
2685 13:21:46.075533 [Byte1]: 32
2686 13:21:46.075613
2687 13:21:46.078790 Set Vref, RX VrefLevel [Byte0]: 33
2688 13:21:46.081977 [Byte1]: 33
2689 13:21:46.085921
2690 13:21:46.086000 Set Vref, RX VrefLevel [Byte0]: 34
2691 13:21:46.088946 [Byte1]: 34
2692 13:21:46.093513
2693 13:21:46.093593 Set Vref, RX VrefLevel [Byte0]: 35
2694 13:21:46.097027 [Byte1]: 35
2695 13:21:46.102164
2696 13:21:46.102248 Set Vref, RX VrefLevel [Byte0]: 36
2697 13:21:46.104729 [Byte1]: 36
2698 13:21:46.109180
2699 13:21:46.109260 Set Vref, RX VrefLevel [Byte0]: 37
2700 13:21:46.112549 [Byte1]: 37
2701 13:21:46.117465
2702 13:21:46.117546 Set Vref, RX VrefLevel [Byte0]: 38
2703 13:21:46.120817 [Byte1]: 38
2704 13:21:46.125039
2705 13:21:46.125119 Set Vref, RX VrefLevel [Byte0]: 39
2706 13:21:46.128920 [Byte1]: 39
2707 13:21:46.133120
2708 13:21:46.133200 Set Vref, RX VrefLevel [Byte0]: 40
2709 13:21:46.136363 [Byte1]: 40
2710 13:21:46.141458
2711 13:21:46.141539 Set Vref, RX VrefLevel [Byte0]: 41
2712 13:21:46.144461 [Byte1]: 41
2713 13:21:46.149099
2714 13:21:46.149179 Set Vref, RX VrefLevel [Byte0]: 42
2715 13:21:46.153054 [Byte1]: 42
2716 13:21:46.157069
2717 13:21:46.157149 Set Vref, RX VrefLevel [Byte0]: 43
2718 13:21:46.160611 [Byte1]: 43
2719 13:21:46.164901
2720 13:21:46.164981 Set Vref, RX VrefLevel [Byte0]: 44
2721 13:21:46.167918 [Byte1]: 44
2722 13:21:46.173349
2723 13:21:46.173429 Set Vref, RX VrefLevel [Byte0]: 45
2724 13:21:46.176076 [Byte1]: 45
2725 13:21:46.180869
2726 13:21:46.180949 Set Vref, RX VrefLevel [Byte0]: 46
2727 13:21:46.184261 [Byte1]: 46
2728 13:21:46.189321
2729 13:21:46.189400 Set Vref, RX VrefLevel [Byte0]: 47
2730 13:21:46.191868 [Byte1]: 47
2731 13:21:46.196759
2732 13:21:46.196839 Set Vref, RX VrefLevel [Byte0]: 48
2733 13:21:46.200285 [Byte1]: 48
2734 13:21:46.204809
2735 13:21:46.204889 Set Vref, RX VrefLevel [Byte0]: 49
2736 13:21:46.207787 [Byte1]: 49
2737 13:21:46.212698
2738 13:21:46.212803 Set Vref, RX VrefLevel [Byte0]: 50
2739 13:21:46.216109 [Byte1]: 50
2740 13:21:46.220491
2741 13:21:46.220571 Set Vref, RX VrefLevel [Byte0]: 51
2742 13:21:46.224420 [Byte1]: 51
2743 13:21:46.228269
2744 13:21:46.228348 Set Vref, RX VrefLevel [Byte0]: 52
2745 13:21:46.231739 [Byte1]: 52
2746 13:21:46.236708
2747 13:21:46.236788 Set Vref, RX VrefLevel [Byte0]: 53
2748 13:21:46.239510 [Byte1]: 53
2749 13:21:46.244369
2750 13:21:46.244450 Set Vref, RX VrefLevel [Byte0]: 54
2751 13:21:46.247497 [Byte1]: 54
2752 13:21:46.251814
2753 13:21:46.251895 Set Vref, RX VrefLevel [Byte0]: 55
2754 13:21:46.255531 [Byte1]: 55
2755 13:21:46.260656
2756 13:21:46.260736 Set Vref, RX VrefLevel [Byte0]: 56
2757 13:21:46.263695 [Byte1]: 56
2758 13:21:46.268351
2759 13:21:46.268435 Set Vref, RX VrefLevel [Byte0]: 57
2760 13:21:46.271103 [Byte1]: 57
2761 13:21:46.275779
2762 13:21:46.275859 Set Vref, RX VrefLevel [Byte0]: 58
2763 13:21:46.279043 [Byte1]: 58
2764 13:21:46.283695
2765 13:21:46.283775 Set Vref, RX VrefLevel [Byte0]: 59
2766 13:21:46.287282 [Byte1]: 59
2767 13:21:46.292397
2768 13:21:46.292477 Set Vref, RX VrefLevel [Byte0]: 60
2769 13:21:46.295192 [Byte1]: 60
2770 13:21:46.299569
2771 13:21:46.299649 Set Vref, RX VrefLevel [Byte0]: 61
2772 13:21:46.302860 [Byte1]: 61
2773 13:21:46.307504
2774 13:21:46.307584 Set Vref, RX VrefLevel [Byte0]: 62
2775 13:21:46.311035 [Byte1]: 62
2776 13:21:46.315588
2777 13:21:46.315668 Set Vref, RX VrefLevel [Byte0]: 63
2778 13:21:46.318667 [Byte1]: 63
2779 13:21:46.323423
2780 13:21:46.323503 Set Vref, RX VrefLevel [Byte0]: 64
2781 13:21:46.326881 [Byte1]: 64
2782 13:21:46.331407
2783 13:21:46.331487 Set Vref, RX VrefLevel [Byte0]: 65
2784 13:21:46.334613 [Byte1]: 65
2785 13:21:46.339280
2786 13:21:46.339359 Set Vref, RX VrefLevel [Byte0]: 66
2787 13:21:46.342519 [Byte1]: 66
2788 13:21:46.347109
2789 13:21:46.347190 Set Vref, RX VrefLevel [Byte0]: 67
2790 13:21:46.350530 [Byte1]: 67
2791 13:21:46.355244
2792 13:21:46.355324 Final RX Vref Byte 0 = 50 to rank0
2793 13:21:46.358451 Final RX Vref Byte 1 = 58 to rank0
2794 13:21:46.361749 Final RX Vref Byte 0 = 50 to rank1
2795 13:21:46.365244 Final RX Vref Byte 1 = 58 to rank1==
2796 13:21:46.368709 Dram Type= 6, Freq= 0, CH_0, rank 0
2797 13:21:46.375113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2798 13:21:46.375194 ==
2799 13:21:46.375258 DQS Delay:
2800 13:21:46.375349 DQS0 = 0, DQS1 = 0
2801 13:21:46.379264 DQM Delay:
2802 13:21:46.379344 DQM0 = 117, DQM1 = 105
2803 13:21:46.381818 DQ Delay:
2804 13:21:46.385106 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2805 13:21:46.388666 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2806 13:21:46.391828 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2807 13:21:46.394982 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =112
2808 13:21:46.395063
2809 13:21:46.395126
2810 13:21:46.401425 [DQSOSCAuto] RK0, (LSB)MR18= 0xfb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
2811 13:21:46.405377 CH0 RK0: MR19=403, MR18=FB
2812 13:21:46.411647 CH0_RK0: MR19=0x403, MR18=0xFB, DQSOSC=410, MR23=63, INC=39, DEC=26
2813 13:21:46.411729
2814 13:21:46.414492 ----->DramcWriteLeveling(PI) begin...
2815 13:21:46.414574 ==
2816 13:21:46.418466 Dram Type= 6, Freq= 0, CH_0, rank 1
2817 13:21:46.421563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2818 13:21:46.421648 ==
2819 13:21:46.425022 Write leveling (Byte 0): 32 => 32
2820 13:21:46.427991 Write leveling (Byte 1): 28 => 28
2821 13:21:46.431485 DramcWriteLeveling(PI) end<-----
2822 13:21:46.431565
2823 13:21:46.431629 ==
2824 13:21:46.434527 Dram Type= 6, Freq= 0, CH_0, rank 1
2825 13:21:46.441843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 13:21:46.441923 ==
2827 13:21:46.441987 [Gating] SW mode calibration
2828 13:21:46.450887 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2829 13:21:46.454598 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2830 13:21:46.461263 0 15 0 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
2831 13:21:46.464762 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2832 13:21:46.467901 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2833 13:21:46.470834 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 13:21:46.477579 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 13:21:46.480894 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 13:21:46.484126 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
2837 13:21:46.490736 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
2838 13:21:46.494258 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2839 13:21:46.497812 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2840 13:21:46.504506 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2841 13:21:46.507548 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 13:21:46.511048 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 13:21:46.517737 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 13:21:46.521067 1 0 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2845 13:21:46.524039 1 0 28 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2846 13:21:46.531064 1 1 0 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
2847 13:21:46.534252 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2848 13:21:46.537107 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2849 13:21:46.543730 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 13:21:46.547064 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 13:21:46.550321 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 13:21:46.557032 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2853 13:21:46.560800 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2854 13:21:46.563898 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2855 13:21:46.570511 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2856 13:21:46.573998 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 13:21:46.577479 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 13:21:46.584833 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 13:21:46.587288 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 13:21:46.590620 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 13:21:46.597232 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 13:21:46.600934 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 13:21:46.604177 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 13:21:46.610279 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 13:21:46.613775 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 13:21:46.616781 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 13:21:46.620647 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 13:21:46.626882 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2869 13:21:46.630311 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2870 13:21:46.633891 Total UI for P1: 0, mck2ui 16
2871 13:21:46.637116 best dqsien dly found for B0: ( 1, 3, 24)
2872 13:21:46.640169 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2873 13:21:46.646703 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 13:21:46.650047 Total UI for P1: 0, mck2ui 16
2875 13:21:46.653644 best dqsien dly found for B1: ( 1, 3, 30)
2876 13:21:46.656888 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2877 13:21:46.660558 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2878 13:21:46.660640
2879 13:21:46.663803 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2880 13:21:46.666655 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2881 13:21:46.670158 [Gating] SW calibration Done
2882 13:21:46.670239 ==
2883 13:21:46.674092 Dram Type= 6, Freq= 0, CH_0, rank 1
2884 13:21:46.677286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2885 13:21:46.677368 ==
2886 13:21:46.680235 RX Vref Scan: 0
2887 13:21:46.680317
2888 13:21:46.684056 RX Vref 0 -> 0, step: 1
2889 13:21:46.684137
2890 13:21:46.684216 RX Delay -40 -> 252, step: 8
2891 13:21:46.690049 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2892 13:21:46.694408 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2893 13:21:46.696601 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2894 13:21:46.700129 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2895 13:21:46.703292 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2896 13:21:46.710561 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2897 13:21:46.713078 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2898 13:21:46.716262 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2899 13:21:46.720584 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2900 13:21:46.723139 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2901 13:21:46.729839 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2902 13:21:46.732961 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2903 13:21:46.736716 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2904 13:21:46.740128 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
2905 13:21:46.742795 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2906 13:21:46.749738 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2907 13:21:46.749819 ==
2908 13:21:46.752692 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 13:21:46.756427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 13:21:46.756508 ==
2911 13:21:46.756604 DQS Delay:
2912 13:21:46.759749 DQS0 = 0, DQS1 = 0
2913 13:21:46.759829 DQM Delay:
2914 13:21:46.762673 DQM0 = 116, DQM1 = 109
2915 13:21:46.762754 DQ Delay:
2916 13:21:46.765822 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2917 13:21:46.769465 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =119
2918 13:21:46.772617 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
2919 13:21:46.775891 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2920 13:21:46.775993
2921 13:21:46.776056
2922 13:21:46.779496 ==
2923 13:21:46.782553 Dram Type= 6, Freq= 0, CH_0, rank 1
2924 13:21:46.786263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2925 13:21:46.786348 ==
2926 13:21:46.786411
2927 13:21:46.786471
2928 13:21:46.789427 TX Vref Scan disable
2929 13:21:46.789509 == TX Byte 0 ==
2930 13:21:46.795774 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2931 13:21:46.799615 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2932 13:21:46.799737 == TX Byte 1 ==
2933 13:21:46.805784 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2934 13:21:46.809171 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2935 13:21:46.809253 ==
2936 13:21:46.812240 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 13:21:46.815413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 13:21:46.815499 ==
2939 13:21:46.828445 TX Vref=22, minBit 9, minWin=25, winSum=417
2940 13:21:46.831418 TX Vref=24, minBit 5, minWin=25, winSum=423
2941 13:21:46.834583 TX Vref=26, minBit 0, minWin=26, winSum=425
2942 13:21:46.838013 TX Vref=28, minBit 5, minWin=26, winSum=430
2943 13:21:46.841547 TX Vref=30, minBit 12, minWin=25, winSum=429
2944 13:21:46.848149 TX Vref=32, minBit 14, minWin=25, winSum=426
2945 13:21:46.851481 [TxChooseVref] Worse bit 5, Min win 26, Win sum 430, Final Vref 28
2946 13:21:46.851563
2947 13:21:46.854812 Final TX Range 1 Vref 28
2948 13:21:46.854893
2949 13:21:46.854958 ==
2950 13:21:46.858072 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 13:21:46.861467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 13:21:46.864844 ==
2953 13:21:46.864925
2954 13:21:46.864989
2955 13:21:46.865048 TX Vref Scan disable
2956 13:21:46.867928 == TX Byte 0 ==
2957 13:21:46.871413 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2958 13:21:46.878009 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2959 13:21:46.878091 == TX Byte 1 ==
2960 13:21:46.881405 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2961 13:21:46.887800 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2962 13:21:46.887883
2963 13:21:46.887958 [DATLAT]
2964 13:21:46.888020 Freq=1200, CH0 RK1
2965 13:21:46.888079
2966 13:21:46.891095 DATLAT Default: 0xd
2967 13:21:46.891176 0, 0xFFFF, sum = 0
2968 13:21:46.894564 1, 0xFFFF, sum = 0
2969 13:21:46.898341 2, 0xFFFF, sum = 0
2970 13:21:46.898423 3, 0xFFFF, sum = 0
2971 13:21:46.901580 4, 0xFFFF, sum = 0
2972 13:21:46.901677 5, 0xFFFF, sum = 0
2973 13:21:46.904416 6, 0xFFFF, sum = 0
2974 13:21:46.904498 7, 0xFFFF, sum = 0
2975 13:21:46.907746 8, 0xFFFF, sum = 0
2976 13:21:46.907828 9, 0xFFFF, sum = 0
2977 13:21:46.910990 10, 0xFFFF, sum = 0
2978 13:21:46.911073 11, 0xFFFF, sum = 0
2979 13:21:46.914457 12, 0x0, sum = 1
2980 13:21:46.914540 13, 0x0, sum = 2
2981 13:21:46.917795 14, 0x0, sum = 3
2982 13:21:46.917877 15, 0x0, sum = 4
2983 13:21:46.921481 best_step = 13
2984 13:21:46.921562
2985 13:21:46.921626 ==
2986 13:21:46.925111 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 13:21:46.927713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 13:21:46.927795 ==
2989 13:21:46.927860 RX Vref Scan: 0
2990 13:21:46.930760
2991 13:21:46.930841 RX Vref 0 -> 0, step: 1
2992 13:21:46.930906
2993 13:21:46.934543 RX Delay -21 -> 252, step: 4
2994 13:21:46.941603 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
2995 13:21:46.944058 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
2996 13:21:46.947609 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
2997 13:21:46.950671 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
2998 13:21:46.954395 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
2999 13:21:46.957346 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3000 13:21:46.964128 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3001 13:21:46.967532 iDelay=195, Bit 7, Center 120 (55 ~ 186) 132
3002 13:21:46.970688 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3003 13:21:46.974060 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3004 13:21:46.977964 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3005 13:21:46.984056 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3006 13:21:46.987467 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3007 13:21:46.990760 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3008 13:21:46.994309 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3009 13:21:47.000965 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3010 13:21:47.001046 ==
3011 13:21:47.003914 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 13:21:47.007350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 13:21:47.007458 ==
3014 13:21:47.007549 DQS Delay:
3015 13:21:47.010633 DQS0 = 0, DQS1 = 0
3016 13:21:47.010714 DQM Delay:
3017 13:21:47.014557 DQM0 = 115, DQM1 = 107
3018 13:21:47.014638 DQ Delay:
3019 13:21:47.017893 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3020 13:21:47.020522 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =120
3021 13:21:47.024058 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102
3022 13:21:47.027595 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =112
3023 13:21:47.027676
3024 13:21:47.027740
3025 13:21:47.037133 [DQSOSCAuto] RK1, (LSB)MR18= 0xfefc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3026 13:21:47.040789 CH0 RK1: MR19=303, MR18=FEFC
3027 13:21:47.043881 CH0_RK1: MR19=0x303, MR18=0xFEFC, DQSOSC=410, MR23=63, INC=39, DEC=26
3028 13:21:47.047088 [RxdqsGatingPostProcess] freq 1200
3029 13:21:47.053625 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3030 13:21:47.057407 best DQS0 dly(2T, 0.5T) = (0, 11)
3031 13:21:47.060390 best DQS1 dly(2T, 0.5T) = (0, 12)
3032 13:21:47.064060 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3033 13:21:47.067076 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3034 13:21:47.070361 best DQS0 dly(2T, 0.5T) = (0, 11)
3035 13:21:47.074032 best DQS1 dly(2T, 0.5T) = (0, 11)
3036 13:21:47.078055 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3037 13:21:47.080629 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3038 13:21:47.080711 Pre-setting of DQS Precalculation
3039 13:21:47.087301 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3040 13:21:47.087383 ==
3041 13:21:47.090809 Dram Type= 6, Freq= 0, CH_1, rank 0
3042 13:21:47.094092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3043 13:21:47.094174 ==
3044 13:21:47.100593 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3045 13:21:47.107217 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3046 13:21:47.114891 [CA 0] Center 38 (8~68) winsize 61
3047 13:21:47.117928 [CA 1] Center 37 (7~68) winsize 62
3048 13:21:47.121351 [CA 2] Center 35 (5~65) winsize 61
3049 13:21:47.124689 [CA 3] Center 34 (4~64) winsize 61
3050 13:21:47.127535 [CA 4] Center 34 (4~65) winsize 62
3051 13:21:47.131180 [CA 5] Center 34 (4~64) winsize 61
3052 13:21:47.131261
3053 13:21:47.134715 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3054 13:21:47.134796
3055 13:21:47.138414 [CATrainingPosCal] consider 1 rank data
3056 13:21:47.140787 u2DelayCellTimex100 = 270/100 ps
3057 13:21:47.144736 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3058 13:21:47.150827 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3059 13:21:47.154298 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3060 13:21:47.157665 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3061 13:21:47.161218 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3062 13:21:47.163708 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3063 13:21:47.163789
3064 13:21:47.167236 CA PerBit enable=1, Macro0, CA PI delay=34
3065 13:21:47.167317
3066 13:21:47.170814 [CBTSetCACLKResult] CA Dly = 34
3067 13:21:47.173964 CS Dly: 5 (0~36)
3068 13:21:47.174045 ==
3069 13:21:47.177112 Dram Type= 6, Freq= 0, CH_1, rank 1
3070 13:21:47.180493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 13:21:47.180575 ==
3072 13:21:47.186918 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3073 13:21:47.190429 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3074 13:21:47.200179 [CA 0] Center 37 (7~68) winsize 62
3075 13:21:47.203630 [CA 1] Center 38 (8~68) winsize 61
3076 13:21:47.206823 [CA 2] Center 34 (4~65) winsize 62
3077 13:21:47.209797 [CA 3] Center 33 (3~64) winsize 62
3078 13:21:47.213343 [CA 4] Center 34 (4~64) winsize 61
3079 13:21:47.216992 [CA 5] Center 33 (3~63) winsize 61
3080 13:21:47.217074
3081 13:21:47.219707 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3082 13:21:47.219789
3083 13:21:47.223482 [CATrainingPosCal] consider 2 rank data
3084 13:21:47.226390 u2DelayCellTimex100 = 270/100 ps
3085 13:21:47.229840 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3086 13:21:47.236640 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3087 13:21:47.240130 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3088 13:21:47.243300 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3089 13:21:47.246234 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3090 13:21:47.249759 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3091 13:21:47.249841
3092 13:21:47.253474 CA PerBit enable=1, Macro0, CA PI delay=33
3093 13:21:47.253584
3094 13:21:47.257103 [CBTSetCACLKResult] CA Dly = 33
3095 13:21:47.257199 CS Dly: 6 (0~39)
3096 13:21:47.259510
3097 13:21:47.263165 ----->DramcWriteLeveling(PI) begin...
3098 13:21:47.263248 ==
3099 13:21:47.266236 Dram Type= 6, Freq= 0, CH_1, rank 0
3100 13:21:47.269692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 13:21:47.269804 ==
3102 13:21:47.273646 Write leveling (Byte 0): 24 => 24
3103 13:21:47.276210 Write leveling (Byte 1): 30 => 30
3104 13:21:47.279614 DramcWriteLeveling(PI) end<-----
3105 13:21:47.279724
3106 13:21:47.279788 ==
3107 13:21:47.283059 Dram Type= 6, Freq= 0, CH_1, rank 0
3108 13:21:47.286518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 13:21:47.286605 ==
3110 13:21:47.290071 [Gating] SW mode calibration
3111 13:21:47.296133 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3112 13:21:47.302952 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3113 13:21:47.306051 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3114 13:21:47.309522 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3115 13:21:47.316450 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 13:21:47.319805 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 13:21:47.322678 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 13:21:47.329937 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 13:21:47.332513 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
3120 13:21:47.335932 0 15 28 | B1->B0 | 2b2b 2424 | 1 0 | (1 0) (0 0)
3121 13:21:47.342662 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3122 13:21:47.346285 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3123 13:21:47.349434 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 13:21:47.355815 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 13:21:47.359063 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 13:21:47.362684 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 13:21:47.365745 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
3128 13:21:47.372632 1 0 28 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
3129 13:21:47.375663 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3130 13:21:47.379106 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 13:21:47.385812 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 13:21:47.389364 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 13:21:47.392215 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 13:21:47.398852 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 13:21:47.402126 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3136 13:21:47.405744 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3137 13:21:47.412128 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 13:21:47.415814 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 13:21:47.418903 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 13:21:47.426367 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 13:21:47.428939 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 13:21:47.432566 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 13:21:47.439329 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 13:21:47.442092 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 13:21:47.445602 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 13:21:47.452498 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 13:21:47.455253 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 13:21:47.458715 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 13:21:47.465717 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 13:21:47.468932 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 13:21:47.472088 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3152 13:21:47.479075 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3153 13:21:47.479177 Total UI for P1: 0, mck2ui 16
3154 13:21:47.482272 best dqsien dly found for B0: ( 1, 3, 24)
3155 13:21:47.488700 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 13:21:47.492381 Total UI for P1: 0, mck2ui 16
3157 13:21:47.495252 best dqsien dly found for B1: ( 1, 3, 28)
3158 13:21:47.498566 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3159 13:21:47.501927 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3160 13:21:47.502023
3161 13:21:47.505294 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3162 13:21:47.508794 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3163 13:21:47.512149 [Gating] SW calibration Done
3164 13:21:47.512260 ==
3165 13:21:47.515563 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 13:21:47.518484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 13:21:47.518566 ==
3168 13:21:47.522114 RX Vref Scan: 0
3169 13:21:47.522248
3170 13:21:47.525036 RX Vref 0 -> 0, step: 1
3171 13:21:47.525166
3172 13:21:47.525234 RX Delay -40 -> 252, step: 8
3173 13:21:47.531823 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3174 13:21:47.535414 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3175 13:21:47.538395 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3176 13:21:47.541691 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3177 13:21:47.545032 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3178 13:21:47.551605 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3179 13:21:47.554889 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3180 13:21:47.558579 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3181 13:21:47.561561 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3182 13:21:47.564983 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3183 13:21:47.571513 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3184 13:21:47.575037 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3185 13:21:47.578522 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3186 13:21:47.581614 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3187 13:21:47.585035 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3188 13:21:47.591593 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3189 13:21:47.591675 ==
3190 13:21:47.595510 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 13:21:47.598210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 13:21:47.598309 ==
3193 13:21:47.598373 DQS Delay:
3194 13:21:47.601967 DQS0 = 0, DQS1 = 0
3195 13:21:47.602048 DQM Delay:
3196 13:21:47.605425 DQM0 = 115, DQM1 = 112
3197 13:21:47.605506 DQ Delay:
3198 13:21:47.608484 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3199 13:21:47.611945 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3200 13:21:47.614757 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3201 13:21:47.618314 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3202 13:21:47.618396
3203 13:21:47.618459
3204 13:21:47.621705 ==
3205 13:21:47.625247 Dram Type= 6, Freq= 0, CH_1, rank 0
3206 13:21:47.628369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 13:21:47.628450 ==
3208 13:21:47.628514
3209 13:21:47.628572
3210 13:21:47.631931 TX Vref Scan disable
3211 13:21:47.632025 == TX Byte 0 ==
3212 13:21:47.638225 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3213 13:21:47.641312 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3214 13:21:47.641393 == TX Byte 1 ==
3215 13:21:47.648464 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3216 13:21:47.651603 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3217 13:21:47.651684 ==
3218 13:21:47.654959 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 13:21:47.657841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 13:21:47.657923 ==
3221 13:21:47.670515 TX Vref=22, minBit 3, minWin=25, winSum=414
3222 13:21:47.673952 TX Vref=24, minBit 3, minWin=24, winSum=416
3223 13:21:47.677565 TX Vref=26, minBit 2, minWin=25, winSum=421
3224 13:21:47.680588 TX Vref=28, minBit 2, minWin=26, winSum=424
3225 13:21:47.683810 TX Vref=30, minBit 2, minWin=26, winSum=431
3226 13:21:47.690649 TX Vref=32, minBit 14, minWin=25, winSum=427
3227 13:21:47.693916 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 30
3228 13:21:47.693997
3229 13:21:47.697462 Final TX Range 1 Vref 30
3230 13:21:47.697569
3231 13:21:47.697658 ==
3232 13:21:47.700258 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 13:21:47.704215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 13:21:47.706946 ==
3235 13:21:47.707027
3236 13:21:47.707090
3237 13:21:47.707149 TX Vref Scan disable
3238 13:21:47.710467 == TX Byte 0 ==
3239 13:21:47.713689 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3240 13:21:47.720362 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3241 13:21:47.720483 == TX Byte 1 ==
3242 13:21:47.724139 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3243 13:21:47.731384 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3244 13:21:47.731458
3245 13:21:47.731521 [DATLAT]
3246 13:21:47.731588 Freq=1200, CH1 RK0
3247 13:21:47.731647
3248 13:21:47.733541 DATLAT Default: 0xd
3249 13:21:47.733611 0, 0xFFFF, sum = 0
3250 13:21:47.737154 1, 0xFFFF, sum = 0
3251 13:21:47.740128 2, 0xFFFF, sum = 0
3252 13:21:47.740205 3, 0xFFFF, sum = 0
3253 13:21:47.743385 4, 0xFFFF, sum = 0
3254 13:21:47.743460 5, 0xFFFF, sum = 0
3255 13:21:47.747093 6, 0xFFFF, sum = 0
3256 13:21:47.747169 7, 0xFFFF, sum = 0
3257 13:21:47.750645 8, 0xFFFF, sum = 0
3258 13:21:47.750719 9, 0xFFFF, sum = 0
3259 13:21:47.754184 10, 0xFFFF, sum = 0
3260 13:21:47.754264 11, 0xFFFF, sum = 0
3261 13:21:47.757138 12, 0x0, sum = 1
3262 13:21:47.757218 13, 0x0, sum = 2
3263 13:21:47.760499 14, 0x0, sum = 3
3264 13:21:47.760573 15, 0x0, sum = 4
3265 13:21:47.760641 best_step = 13
3266 13:21:47.763726
3267 13:21:47.763829 ==
3268 13:21:47.766737 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 13:21:47.770319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 13:21:47.770401 ==
3271 13:21:47.770465 RX Vref Scan: 1
3272 13:21:47.770524
3273 13:21:47.773615 Set Vref Range= 32 -> 127
3274 13:21:47.773687
3275 13:21:47.776779 RX Vref 32 -> 127, step: 1
3276 13:21:47.776851
3277 13:21:47.780392 RX Delay -13 -> 252, step: 4
3278 13:21:47.780472
3279 13:21:47.783338 Set Vref, RX VrefLevel [Byte0]: 32
3280 13:21:47.786740 [Byte1]: 32
3281 13:21:47.786824
3282 13:21:47.789872 Set Vref, RX VrefLevel [Byte0]: 33
3283 13:21:47.793286 [Byte1]: 33
3284 13:21:47.796939
3285 13:21:47.797027 Set Vref, RX VrefLevel [Byte0]: 34
3286 13:21:47.800089 [Byte1]: 34
3287 13:21:47.804993
3288 13:21:47.805066 Set Vref, RX VrefLevel [Byte0]: 35
3289 13:21:47.807800 [Byte1]: 35
3290 13:21:47.812899
3291 13:21:47.812980 Set Vref, RX VrefLevel [Byte0]: 36
3292 13:21:47.816077 [Byte1]: 36
3293 13:21:47.820442
3294 13:21:47.820520 Set Vref, RX VrefLevel [Byte0]: 37
3295 13:21:47.824082 [Byte1]: 37
3296 13:21:47.828133
3297 13:21:47.828207 Set Vref, RX VrefLevel [Byte0]: 38
3298 13:21:47.832052 [Byte1]: 38
3299 13:21:47.836768
3300 13:21:47.836845 Set Vref, RX VrefLevel [Byte0]: 39
3301 13:21:47.839512 [Byte1]: 39
3302 13:21:47.844820
3303 13:21:47.844891 Set Vref, RX VrefLevel [Byte0]: 40
3304 13:21:47.848047 [Byte1]: 40
3305 13:21:47.852055
3306 13:21:47.852133 Set Vref, RX VrefLevel [Byte0]: 41
3307 13:21:47.855381 [Byte1]: 41
3308 13:21:47.860114
3309 13:21:47.860182 Set Vref, RX VrefLevel [Byte0]: 42
3310 13:21:47.863097 [Byte1]: 42
3311 13:21:47.867568
3312 13:21:47.867642 Set Vref, RX VrefLevel [Byte0]: 43
3313 13:21:47.870870 [Byte1]: 43
3314 13:21:47.875486
3315 13:21:47.875578 Set Vref, RX VrefLevel [Byte0]: 44
3316 13:21:47.879110 [Byte1]: 44
3317 13:21:47.883617
3318 13:21:47.883690 Set Vref, RX VrefLevel [Byte0]: 45
3319 13:21:47.886977 [Byte1]: 45
3320 13:21:47.891828
3321 13:21:47.891909 Set Vref, RX VrefLevel [Byte0]: 46
3322 13:21:47.894608 [Byte1]: 46
3323 13:21:47.899127
3324 13:21:47.899202 Set Vref, RX VrefLevel [Byte0]: 47
3325 13:21:47.902789 [Byte1]: 47
3326 13:21:47.907513
3327 13:21:47.907587 Set Vref, RX VrefLevel [Byte0]: 48
3328 13:21:47.910384 [Byte1]: 48
3329 13:21:47.914910
3330 13:21:47.914989 Set Vref, RX VrefLevel [Byte0]: 49
3331 13:21:47.919240 [Byte1]: 49
3332 13:21:47.923261
3333 13:21:47.923344 Set Vref, RX VrefLevel [Byte0]: 50
3334 13:21:47.926310 [Byte1]: 50
3335 13:21:47.930900
3336 13:21:47.930976 Set Vref, RX VrefLevel [Byte0]: 51
3337 13:21:47.934049 [Byte1]: 51
3338 13:21:47.938678
3339 13:21:47.938752 Set Vref, RX VrefLevel [Byte0]: 52
3340 13:21:47.942471 [Byte1]: 52
3341 13:21:47.946469
3342 13:21:47.946586 Set Vref, RX VrefLevel [Byte0]: 53
3343 13:21:47.950750 [Byte1]: 53
3344 13:21:47.954621
3345 13:21:47.954694 Set Vref, RX VrefLevel [Byte0]: 54
3346 13:21:47.957885 [Byte1]: 54
3347 13:21:47.962664
3348 13:21:47.962737 Set Vref, RX VrefLevel [Byte0]: 55
3349 13:21:47.965534 [Byte1]: 55
3350 13:21:47.970340
3351 13:21:47.970423 Set Vref, RX VrefLevel [Byte0]: 56
3352 13:21:47.974068 [Byte1]: 56
3353 13:21:47.978380
3354 13:21:47.978454 Set Vref, RX VrefLevel [Byte0]: 57
3355 13:21:47.981953 [Byte1]: 57
3356 13:21:47.986198
3357 13:21:47.986276 Set Vref, RX VrefLevel [Byte0]: 58
3358 13:21:47.989211 [Byte1]: 58
3359 13:21:47.993618
3360 13:21:47.993692 Set Vref, RX VrefLevel [Byte0]: 59
3361 13:21:47.996888 [Byte1]: 59
3362 13:21:48.001519
3363 13:21:48.001596 Set Vref, RX VrefLevel [Byte0]: 60
3364 13:21:48.005054 [Byte1]: 60
3365 13:21:48.009857
3366 13:21:48.009937 Set Vref, RX VrefLevel [Byte0]: 61
3367 13:21:48.012683 [Byte1]: 61
3368 13:21:48.017686
3369 13:21:48.017764 Set Vref, RX VrefLevel [Byte0]: 62
3370 13:21:48.020529 [Byte1]: 62
3371 13:21:48.025417
3372 13:21:48.025491 Set Vref, RX VrefLevel [Byte0]: 63
3373 13:21:48.028618 [Byte1]: 63
3374 13:21:48.033265
3375 13:21:48.033336 Set Vref, RX VrefLevel [Byte0]: 64
3376 13:21:48.036982 [Byte1]: 64
3377 13:21:48.041142
3378 13:21:48.041219 Set Vref, RX VrefLevel [Byte0]: 65
3379 13:21:48.044822 [Byte1]: 65
3380 13:21:48.049148
3381 13:21:48.049218 Final RX Vref Byte 0 = 52 to rank0
3382 13:21:48.052517 Final RX Vref Byte 1 = 53 to rank0
3383 13:21:48.056099 Final RX Vref Byte 0 = 52 to rank1
3384 13:21:48.058893 Final RX Vref Byte 1 = 53 to rank1==
3385 13:21:48.062600 Dram Type= 6, Freq= 0, CH_1, rank 0
3386 13:21:48.068675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3387 13:21:48.068758 ==
3388 13:21:48.068822 DQS Delay:
3389 13:21:48.068882 DQS0 = 0, DQS1 = 0
3390 13:21:48.072297 DQM Delay:
3391 13:21:48.072377 DQM0 = 114, DQM1 = 113
3392 13:21:48.076481 DQ Delay:
3393 13:21:48.078833 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3394 13:21:48.082040 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3395 13:21:48.085490 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3396 13:21:48.088911 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =122
3397 13:21:48.088991
3398 13:21:48.089056
3399 13:21:48.099323 [DQSOSCAuto] RK0, (LSB)MR18= 0xf2ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3400 13:21:48.099405 CH1 RK0: MR19=303, MR18=F2FF
3401 13:21:48.105250 CH1_RK0: MR19=0x303, MR18=0xF2FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3402 13:21:48.105330
3403 13:21:48.108537 ----->DramcWriteLeveling(PI) begin...
3404 13:21:48.108619 ==
3405 13:21:48.112116 Dram Type= 6, Freq= 0, CH_1, rank 1
3406 13:21:48.118586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3407 13:21:48.118668 ==
3408 13:21:48.121837 Write leveling (Byte 0): 26 => 26
3409 13:21:48.121919 Write leveling (Byte 1): 29 => 29
3410 13:21:48.126061 DramcWriteLeveling(PI) end<-----
3411 13:21:48.126142
3412 13:21:48.126206 ==
3413 13:21:48.128666 Dram Type= 6, Freq= 0, CH_1, rank 1
3414 13:21:48.135499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3415 13:21:48.135639 ==
3416 13:21:48.138628 [Gating] SW mode calibration
3417 13:21:48.145486 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3418 13:21:48.149111 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3419 13:21:48.155206 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3420 13:21:48.158620 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3421 13:21:48.162204 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3422 13:21:48.169519 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3423 13:21:48.171871 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3424 13:21:48.175167 0 15 20 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
3425 13:21:48.178727 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
3426 13:21:48.185244 0 15 28 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
3427 13:21:48.188486 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3428 13:21:48.191813 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3429 13:21:48.199276 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3430 13:21:48.202283 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3431 13:21:48.205461 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3432 13:21:48.211932 1 0 20 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
3433 13:21:48.215297 1 0 24 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
3434 13:21:48.218251 1 0 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
3435 13:21:48.224738 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3436 13:21:48.228427 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3437 13:21:48.232040 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3438 13:21:48.238085 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3439 13:21:48.241384 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3440 13:21:48.245104 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3441 13:21:48.251240 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3442 13:21:48.254566 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3443 13:21:48.257631 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3444 13:21:48.264496 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3445 13:21:48.268116 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3446 13:21:48.271153 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3447 13:21:48.277368 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3448 13:21:48.281189 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 13:21:48.284257 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 13:21:48.290582 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 13:21:48.294085 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 13:21:48.297534 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 13:21:48.304150 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 13:21:48.307326 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 13:21:48.310393 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 13:21:48.316822 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 13:21:48.320488 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3458 13:21:48.323926 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3459 13:21:48.327031 Total UI for P1: 0, mck2ui 16
3460 13:21:48.330089 best dqsien dly found for B0: ( 1, 3, 24)
3461 13:21:48.336904 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 13:21:48.340211 Total UI for P1: 0, mck2ui 16
3463 13:21:48.343183 best dqsien dly found for B1: ( 1, 3, 28)
3464 13:21:48.347185 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3465 13:21:48.350222 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3466 13:21:48.350303
3467 13:21:48.353388 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3468 13:21:48.356546 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3469 13:21:48.359810 [Gating] SW calibration Done
3470 13:21:48.359890 ==
3471 13:21:48.363147 Dram Type= 6, Freq= 0, CH_1, rank 1
3472 13:21:48.366323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3473 13:21:48.366447 ==
3474 13:21:48.370048 RX Vref Scan: 0
3475 13:21:48.370131
3476 13:21:48.373586 RX Vref 0 -> 0, step: 1
3477 13:21:48.373667
3478 13:21:48.373731 RX Delay -40 -> 252, step: 8
3479 13:21:48.379770 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3480 13:21:48.382772 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3481 13:21:48.386376 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3482 13:21:48.390707 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3483 13:21:48.396403 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3484 13:21:48.399215 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3485 13:21:48.403371 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3486 13:21:48.406571 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3487 13:21:48.410000 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3488 13:21:48.412425 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3489 13:21:48.419085 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3490 13:21:48.423018 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3491 13:21:48.426112 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3492 13:21:48.429048 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3493 13:21:48.435946 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3494 13:21:48.438757 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3495 13:21:48.438868 ==
3496 13:21:48.442079 Dram Type= 6, Freq= 0, CH_1, rank 1
3497 13:21:48.445329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3498 13:21:48.445411 ==
3499 13:21:48.448834 DQS Delay:
3500 13:21:48.448915 DQS0 = 0, DQS1 = 0
3501 13:21:48.452359 DQM Delay:
3502 13:21:48.452440 DQM0 = 115, DQM1 = 112
3503 13:21:48.452505 DQ Delay:
3504 13:21:48.455055 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3505 13:21:48.461652 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3506 13:21:48.465259 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3507 13:21:48.468419 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3508 13:21:48.468500
3509 13:21:48.468564
3510 13:21:48.468623 ==
3511 13:21:48.471557 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 13:21:48.475318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 13:21:48.475401 ==
3514 13:21:48.475465
3515 13:21:48.475525
3516 13:21:48.478277 TX Vref Scan disable
3517 13:21:48.482246 == TX Byte 0 ==
3518 13:21:48.484914 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3519 13:21:48.488199 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3520 13:21:48.491402 == TX Byte 1 ==
3521 13:21:48.495180 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3522 13:21:48.498946 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3523 13:21:48.499027 ==
3524 13:21:48.501262 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 13:21:48.507867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 13:21:48.507991 ==
3527 13:21:48.518851 TX Vref=22, minBit 1, minWin=25, winSum=417
3528 13:21:48.521606 TX Vref=24, minBit 9, minWin=25, winSum=423
3529 13:21:48.524788 TX Vref=26, minBit 3, minWin=26, winSum=433
3530 13:21:48.528206 TX Vref=28, minBit 1, minWin=26, winSum=431
3531 13:21:48.531719 TX Vref=30, minBit 1, minWin=26, winSum=433
3532 13:21:48.538947 TX Vref=32, minBit 1, minWin=26, winSum=431
3533 13:21:48.541502 [TxChooseVref] Worse bit 3, Min win 26, Win sum 433, Final Vref 26
3534 13:21:48.541583
3535 13:21:48.545088 Final TX Range 1 Vref 26
3536 13:21:48.545170
3537 13:21:48.545234 ==
3538 13:21:48.548267 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 13:21:48.551264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 13:21:48.554578 ==
3541 13:21:48.554659
3542 13:21:48.554723
3543 13:21:48.554783 TX Vref Scan disable
3544 13:21:48.558292 == TX Byte 0 ==
3545 13:21:48.561234 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3546 13:21:48.568364 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3547 13:21:48.568446 == TX Byte 1 ==
3548 13:21:48.571401 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3549 13:21:48.577879 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3550 13:21:48.577960
3551 13:21:48.578024 [DATLAT]
3552 13:21:48.578085 Freq=1200, CH1 RK1
3553 13:21:48.578144
3554 13:21:48.581333 DATLAT Default: 0xd
3555 13:21:48.584556 0, 0xFFFF, sum = 0
3556 13:21:48.584639 1, 0xFFFF, sum = 0
3557 13:21:48.587722 2, 0xFFFF, sum = 0
3558 13:21:48.587804 3, 0xFFFF, sum = 0
3559 13:21:48.591194 4, 0xFFFF, sum = 0
3560 13:21:48.591302 5, 0xFFFF, sum = 0
3561 13:21:48.594225 6, 0xFFFF, sum = 0
3562 13:21:48.594307 7, 0xFFFF, sum = 0
3563 13:21:48.597535 8, 0xFFFF, sum = 0
3564 13:21:48.597617 9, 0xFFFF, sum = 0
3565 13:21:48.601529 10, 0xFFFF, sum = 0
3566 13:21:48.601611 11, 0xFFFF, sum = 0
3567 13:21:48.604311 12, 0x0, sum = 1
3568 13:21:48.604394 13, 0x0, sum = 2
3569 13:21:48.607531 14, 0x0, sum = 3
3570 13:21:48.607628 15, 0x0, sum = 4
3571 13:21:48.610714 best_step = 13
3572 13:21:48.610860
3573 13:21:48.610953 ==
3574 13:21:48.614224 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 13:21:48.617385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 13:21:48.617467 ==
3577 13:21:48.620777 RX Vref Scan: 0
3578 13:21:48.620858
3579 13:21:48.620922 RX Vref 0 -> 0, step: 1
3580 13:21:48.620983
3581 13:21:48.624766 RX Delay -13 -> 252, step: 4
3582 13:21:48.630713 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3583 13:21:48.633953 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3584 13:21:48.637269 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3585 13:21:48.640611 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3586 13:21:48.644598 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3587 13:21:48.650487 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3588 13:21:48.653443 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3589 13:21:48.657290 iDelay=195, Bit 7, Center 114 (47 ~ 182) 136
3590 13:21:48.660087 iDelay=195, Bit 8, Center 102 (43 ~ 162) 120
3591 13:21:48.663952 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3592 13:21:48.669994 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3593 13:21:48.673297 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3594 13:21:48.676604 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3595 13:21:48.680139 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3596 13:21:48.686855 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3597 13:21:48.690049 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3598 13:21:48.690130 ==
3599 13:21:48.693109 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 13:21:48.696481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 13:21:48.696563 ==
3602 13:21:48.700261 DQS Delay:
3603 13:21:48.700410 DQS0 = 0, DQS1 = 0
3604 13:21:48.700505 DQM Delay:
3605 13:21:48.703384 DQM0 = 115, DQM1 = 112
3606 13:21:48.703465 DQ Delay:
3607 13:21:48.706633 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =112
3608 13:21:48.709872 DQ4 =116, DQ5 =124, DQ6 =120, DQ7 =114
3609 13:21:48.713192 DQ8 =102, DQ9 =104, DQ10 =114, DQ11 =106
3610 13:21:48.720068 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =122
3611 13:21:48.720150
3612 13:21:48.720213
3613 13:21:48.726359 [DQSOSCAuto] RK1, (LSB)MR18= 0xf507, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
3614 13:21:48.729551 CH1 RK1: MR19=304, MR18=F507
3615 13:21:48.736682 CH1_RK1: MR19=0x304, MR18=0xF507, DQSOSC=407, MR23=63, INC=39, DEC=26
3616 13:21:48.739678 [RxdqsGatingPostProcess] freq 1200
3617 13:21:48.746200 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3618 13:21:48.746282 best DQS0 dly(2T, 0.5T) = (0, 11)
3619 13:21:48.749402 best DQS1 dly(2T, 0.5T) = (0, 11)
3620 13:21:48.753041 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3621 13:21:48.755960 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3622 13:21:48.760089 best DQS0 dly(2T, 0.5T) = (0, 11)
3623 13:21:48.762411 best DQS1 dly(2T, 0.5T) = (0, 11)
3624 13:21:48.765723 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3625 13:21:48.769194 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3626 13:21:48.772499 Pre-setting of DQS Precalculation
3627 13:21:48.778786 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3628 13:21:48.785165 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3629 13:21:48.792028 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3630 13:21:48.792110
3631 13:21:48.792176
3632 13:21:48.795484 [Calibration Summary] 2400 Mbps
3633 13:21:48.795579 CH 0, Rank 0
3634 13:21:48.798692 SW Impedance : PASS
3635 13:21:48.802196 DUTY Scan : NO K
3636 13:21:48.802277 ZQ Calibration : PASS
3637 13:21:48.805098 Jitter Meter : NO K
3638 13:21:48.808613 CBT Training : PASS
3639 13:21:48.808695 Write leveling : PASS
3640 13:21:48.812061 RX DQS gating : PASS
3641 13:21:48.815213 RX DQ/DQS(RDDQC) : PASS
3642 13:21:48.815293 TX DQ/DQS : PASS
3643 13:21:48.818706 RX DATLAT : PASS
3644 13:21:48.818787 RX DQ/DQS(Engine): PASS
3645 13:21:48.821866 TX OE : NO K
3646 13:21:48.821946 All Pass.
3647 13:21:48.822010
3648 13:21:48.824919 CH 0, Rank 1
3649 13:21:48.824999 SW Impedance : PASS
3650 13:21:48.828858 DUTY Scan : NO K
3651 13:21:48.831741 ZQ Calibration : PASS
3652 13:21:48.831821 Jitter Meter : NO K
3653 13:21:48.834957 CBT Training : PASS
3654 13:21:48.838637 Write leveling : PASS
3655 13:21:48.838718 RX DQS gating : PASS
3656 13:21:48.841642 RX DQ/DQS(RDDQC) : PASS
3657 13:21:48.845147 TX DQ/DQS : PASS
3658 13:21:48.845228 RX DATLAT : PASS
3659 13:21:48.847838 RX DQ/DQS(Engine): PASS
3660 13:21:48.851423 TX OE : NO K
3661 13:21:48.851504 All Pass.
3662 13:21:48.851569
3663 13:21:48.851627 CH 1, Rank 0
3664 13:21:48.854758 SW Impedance : PASS
3665 13:21:48.857713 DUTY Scan : NO K
3666 13:21:48.857793 ZQ Calibration : PASS
3667 13:21:48.861437 Jitter Meter : NO K
3668 13:21:48.864519 CBT Training : PASS
3669 13:21:48.864600 Write leveling : PASS
3670 13:21:48.867886 RX DQS gating : PASS
3671 13:21:48.871020 RX DQ/DQS(RDDQC) : PASS
3672 13:21:48.871139 TX DQ/DQS : PASS
3673 13:21:48.874654 RX DATLAT : PASS
3674 13:21:48.877492 RX DQ/DQS(Engine): PASS
3675 13:21:48.877577 TX OE : NO K
3676 13:21:48.880719 All Pass.
3677 13:21:48.880799
3678 13:21:48.880863 CH 1, Rank 1
3679 13:21:48.884245 SW Impedance : PASS
3680 13:21:48.884325 DUTY Scan : NO K
3681 13:21:48.887811 ZQ Calibration : PASS
3682 13:21:48.890954 Jitter Meter : NO K
3683 13:21:48.891035 CBT Training : PASS
3684 13:21:48.894003 Write leveling : PASS
3685 13:21:48.897164 RX DQS gating : PASS
3686 13:21:48.897245 RX DQ/DQS(RDDQC) : PASS
3687 13:21:48.900866 TX DQ/DQS : PASS
3688 13:21:48.903837 RX DATLAT : PASS
3689 13:21:48.903976 RX DQ/DQS(Engine): PASS
3690 13:21:48.907784 TX OE : NO K
3691 13:21:48.907890 All Pass.
3692 13:21:48.907998
3693 13:21:48.910645 DramC Write-DBI off
3694 13:21:48.913737 PER_BANK_REFRESH: Hybrid Mode
3695 13:21:48.913818 TX_TRACKING: ON
3696 13:21:48.923838 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3697 13:21:48.927007 [FAST_K] Save calibration result to emmc
3698 13:21:48.930168 dramc_set_vcore_voltage set vcore to 650000
3699 13:21:48.933774 Read voltage for 600, 5
3700 13:21:48.933844 Vio18 = 0
3701 13:21:48.933905 Vcore = 650000
3702 13:21:48.936737 Vdram = 0
3703 13:21:48.936842 Vddq = 0
3704 13:21:48.936933 Vmddr = 0
3705 13:21:48.943796 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3706 13:21:48.946875 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3707 13:21:48.949906 MEM_TYPE=3, freq_sel=19
3708 13:21:48.953483 sv_algorithm_assistance_LP4_1600
3709 13:21:48.956843 ============ PULL DRAM RESETB DOWN ============
3710 13:21:48.959725 ========== PULL DRAM RESETB DOWN end =========
3711 13:21:48.966748 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3712 13:21:48.970019 ===================================
3713 13:21:48.973091 LPDDR4 DRAM CONFIGURATION
3714 13:21:48.976425 ===================================
3715 13:21:48.976508 EX_ROW_EN[0] = 0x0
3716 13:21:48.979494 EX_ROW_EN[1] = 0x0
3717 13:21:48.979600 LP4Y_EN = 0x0
3718 13:21:48.983554 WORK_FSP = 0x0
3719 13:21:48.983660 WL = 0x2
3720 13:21:48.986266 RL = 0x2
3721 13:21:48.986347 BL = 0x2
3722 13:21:48.989315 RPST = 0x0
3723 13:21:48.989396 RD_PRE = 0x0
3724 13:21:48.993009 WR_PRE = 0x1
3725 13:21:48.993115 WR_PST = 0x0
3726 13:21:48.996432 DBI_WR = 0x0
3727 13:21:48.996512 DBI_RD = 0x0
3728 13:21:48.999705 OTF = 0x1
3729 13:21:49.002918 ===================================
3730 13:21:49.005847 ===================================
3731 13:21:49.005974 ANA top config
3732 13:21:49.009720 ===================================
3733 13:21:49.013009 DLL_ASYNC_EN = 0
3734 13:21:49.015821 ALL_SLAVE_EN = 1
3735 13:21:49.018894 NEW_RANK_MODE = 1
3736 13:21:49.022261 DLL_IDLE_MODE = 1
3737 13:21:49.022342 LP45_APHY_COMB_EN = 1
3738 13:21:49.025803 TX_ODT_DIS = 1
3739 13:21:49.028901 NEW_8X_MODE = 1
3740 13:21:49.032395 ===================================
3741 13:21:49.035405 ===================================
3742 13:21:49.038969 data_rate = 1200
3743 13:21:49.042356 CKR = 1
3744 13:21:49.042436 DQ_P2S_RATIO = 8
3745 13:21:49.045814 ===================================
3746 13:21:49.048749 CA_P2S_RATIO = 8
3747 13:21:49.052082 DQ_CA_OPEN = 0
3748 13:21:49.055094 DQ_SEMI_OPEN = 0
3749 13:21:49.058585 CA_SEMI_OPEN = 0
3750 13:21:49.061839 CA_FULL_RATE = 0
3751 13:21:49.065201 DQ_CKDIV4_EN = 1
3752 13:21:49.065282 CA_CKDIV4_EN = 1
3753 13:21:49.068371 CA_PREDIV_EN = 0
3754 13:21:49.071673 PH8_DLY = 0
3755 13:21:49.075444 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3756 13:21:49.078321 DQ_AAMCK_DIV = 4
3757 13:21:49.081844 CA_AAMCK_DIV = 4
3758 13:21:49.081925 CA_ADMCK_DIV = 4
3759 13:21:49.085518 DQ_TRACK_CA_EN = 0
3760 13:21:49.088150 CA_PICK = 600
3761 13:21:49.091354 CA_MCKIO = 600
3762 13:21:49.094515 MCKIO_SEMI = 0
3763 13:21:49.098102 PLL_FREQ = 2288
3764 13:21:49.101678 DQ_UI_PI_RATIO = 32
3765 13:21:49.101761 CA_UI_PI_RATIO = 0
3766 13:21:49.104695 ===================================
3767 13:21:49.107957 ===================================
3768 13:21:49.111238 memory_type:LPDDR4
3769 13:21:49.115046 GP_NUM : 10
3770 13:21:49.115127 SRAM_EN : 1
3771 13:21:49.118268 MD32_EN : 0
3772 13:21:49.120984 ===================================
3773 13:21:49.124873 [ANA_INIT] >>>>>>>>>>>>>>
3774 13:21:49.128441 <<<<<< [CONFIGURE PHASE]: ANA_TX
3775 13:21:49.131044 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3776 13:21:49.134141 ===================================
3777 13:21:49.134222 data_rate = 1200,PCW = 0X5800
3778 13:21:49.137803 ===================================
3779 13:21:49.144045 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3780 13:21:49.147178 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3781 13:21:49.154391 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3782 13:21:49.157414 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3783 13:21:49.161311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3784 13:21:49.164088 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3785 13:21:49.168198 [ANA_INIT] flow start
3786 13:21:49.170977 [ANA_INIT] PLL >>>>>>>>
3787 13:21:49.171057 [ANA_INIT] PLL <<<<<<<<
3788 13:21:49.173940 [ANA_INIT] MIDPI >>>>>>>>
3789 13:21:49.177073 [ANA_INIT] MIDPI <<<<<<<<
3790 13:21:49.180266 [ANA_INIT] DLL >>>>>>>>
3791 13:21:49.180349 [ANA_INIT] flow end
3792 13:21:49.183582 ============ LP4 DIFF to SE enter ============
3793 13:21:49.190309 ============ LP4 DIFF to SE exit ============
3794 13:21:49.190390 [ANA_INIT] <<<<<<<<<<<<<
3795 13:21:49.193389 [Flow] Enable top DCM control >>>>>
3796 13:21:49.196650 [Flow] Enable top DCM control <<<<<
3797 13:21:49.200517 Enable DLL master slave shuffle
3798 13:21:49.206802 ==============================================================
3799 13:21:49.206884 Gating Mode config
3800 13:21:49.213419 ==============================================================
3801 13:21:49.216643 Config description:
3802 13:21:49.226263 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3803 13:21:49.232863 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3804 13:21:49.236357 SELPH_MODE 0: By rank 1: By Phase
3805 13:21:49.243193 ==============================================================
3806 13:21:49.246074 GAT_TRACK_EN = 1
3807 13:21:49.249474 RX_GATING_MODE = 2
3808 13:21:49.249555 RX_GATING_TRACK_MODE = 2
3809 13:21:49.253039 SELPH_MODE = 1
3810 13:21:49.255948 PICG_EARLY_EN = 1
3811 13:21:49.259174 VALID_LAT_VALUE = 1
3812 13:21:49.266107 ==============================================================
3813 13:21:49.269151 Enter into Gating configuration >>>>
3814 13:21:49.272788 Exit from Gating configuration <<<<
3815 13:21:49.276360 Enter into DVFS_PRE_config >>>>>
3816 13:21:49.286357 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3817 13:21:49.289314 Exit from DVFS_PRE_config <<<<<
3818 13:21:49.292630 Enter into PICG configuration >>>>
3819 13:21:49.295665 Exit from PICG configuration <<<<
3820 13:21:49.299152 [RX_INPUT] configuration >>>>>
3821 13:21:49.302674 [RX_INPUT] configuration <<<<<
3822 13:21:49.305730 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3823 13:21:49.312863 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3824 13:21:49.319029 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3825 13:21:49.325458 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3826 13:21:49.332398 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3827 13:21:49.336109 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3828 13:21:49.342173 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3829 13:21:49.345708 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3830 13:21:49.348660 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3831 13:21:49.352184 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3832 13:21:49.358403 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3833 13:21:49.361621 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3834 13:21:49.364917 ===================================
3835 13:21:49.368163 LPDDR4 DRAM CONFIGURATION
3836 13:21:49.371730 ===================================
3837 13:21:49.371811 EX_ROW_EN[0] = 0x0
3838 13:21:49.374782 EX_ROW_EN[1] = 0x0
3839 13:21:49.374863 LP4Y_EN = 0x0
3840 13:21:49.378267 WORK_FSP = 0x0
3841 13:21:49.378349 WL = 0x2
3842 13:21:49.381482 RL = 0x2
3843 13:21:49.385077 BL = 0x2
3844 13:21:49.385158 RPST = 0x0
3845 13:21:49.388191 RD_PRE = 0x0
3846 13:21:49.388271 WR_PRE = 0x1
3847 13:21:49.392185 WR_PST = 0x0
3848 13:21:49.392282 DBI_WR = 0x0
3849 13:21:49.395298 DBI_RD = 0x0
3850 13:21:49.395378 OTF = 0x1
3851 13:21:49.397831 ===================================
3852 13:21:49.401692 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3853 13:21:49.407648 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3854 13:21:49.411278 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3855 13:21:49.415143 ===================================
3856 13:21:49.417927 LPDDR4 DRAM CONFIGURATION
3857 13:21:49.421379 ===================================
3858 13:21:49.421459 EX_ROW_EN[0] = 0x10
3859 13:21:49.424820 EX_ROW_EN[1] = 0x0
3860 13:21:49.424900 LP4Y_EN = 0x0
3861 13:21:49.427939 WORK_FSP = 0x0
3862 13:21:49.430852 WL = 0x2
3863 13:21:49.430932 RL = 0x2
3864 13:21:49.434384 BL = 0x2
3865 13:21:49.434483 RPST = 0x0
3866 13:21:49.437236 RD_PRE = 0x0
3867 13:21:49.437317 WR_PRE = 0x1
3868 13:21:49.440569 WR_PST = 0x0
3869 13:21:49.440649 DBI_WR = 0x0
3870 13:21:49.443737 DBI_RD = 0x0
3871 13:21:49.443817 OTF = 0x1
3872 13:21:49.448051 ===================================
3873 13:21:49.453758 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3874 13:21:49.457991 nWR fixed to 30
3875 13:21:49.461495 [ModeRegInit_LP4] CH0 RK0
3876 13:21:49.461576 [ModeRegInit_LP4] CH0 RK1
3877 13:21:49.464779 [ModeRegInit_LP4] CH1 RK0
3878 13:21:49.468190 [ModeRegInit_LP4] CH1 RK1
3879 13:21:49.468273 match AC timing 17
3880 13:21:49.474500 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3881 13:21:49.478146 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3882 13:21:49.481507 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3883 13:21:49.488498 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3884 13:21:49.491630 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3885 13:21:49.491711 ==
3886 13:21:49.495026 Dram Type= 6, Freq= 0, CH_0, rank 0
3887 13:21:49.497929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3888 13:21:49.498010 ==
3889 13:21:49.504289 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3890 13:21:49.511367 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3891 13:21:49.514398 [CA 0] Center 36 (6~67) winsize 62
3892 13:21:49.517662 [CA 1] Center 35 (5~66) winsize 62
3893 13:21:49.521762 [CA 2] Center 34 (4~65) winsize 62
3894 13:21:49.524181 [CA 3] Center 34 (4~65) winsize 62
3895 13:21:49.527329 [CA 4] Center 33 (3~64) winsize 62
3896 13:21:49.530739 [CA 5] Center 33 (3~64) winsize 62
3897 13:21:49.530824
3898 13:21:49.534137 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3899 13:21:49.534234
3900 13:21:49.537635 [CATrainingPosCal] consider 1 rank data
3901 13:21:49.540830 u2DelayCellTimex100 = 270/100 ps
3902 13:21:49.544522 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3903 13:21:49.547420 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3904 13:21:49.550496 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3905 13:21:49.557004 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3906 13:21:49.560247 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3907 13:21:49.563490 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3908 13:21:49.563587
3909 13:21:49.566793 CA PerBit enable=1, Macro0, CA PI delay=33
3910 13:21:49.566870
3911 13:21:49.570125 [CBTSetCACLKResult] CA Dly = 33
3912 13:21:49.570225 CS Dly: 4 (0~35)
3913 13:21:49.570321 ==
3914 13:21:49.573449 Dram Type= 6, Freq= 0, CH_0, rank 1
3915 13:21:49.579958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3916 13:21:49.580034 ==
3917 13:21:49.583077 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3918 13:21:49.589630 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3919 13:21:49.593544 [CA 0] Center 36 (6~67) winsize 62
3920 13:21:49.596907 [CA 1] Center 36 (6~67) winsize 62
3921 13:21:49.599863 [CA 2] Center 34 (4~65) winsize 62
3922 13:21:49.603101 [CA 3] Center 34 (4~65) winsize 62
3923 13:21:49.606781 [CA 4] Center 34 (3~65) winsize 63
3924 13:21:49.610393 [CA 5] Center 33 (3~64) winsize 62
3925 13:21:49.610467
3926 13:21:49.613154 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3927 13:21:49.613224
3928 13:21:49.616561 [CATrainingPosCal] consider 2 rank data
3929 13:21:49.619800 u2DelayCellTimex100 = 270/100 ps
3930 13:21:49.626330 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3931 13:21:49.630187 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3932 13:21:49.632740 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3933 13:21:49.636297 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3934 13:21:49.639665 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3935 13:21:49.642865 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3936 13:21:49.642946
3937 13:21:49.646283 CA PerBit enable=1, Macro0, CA PI delay=33
3938 13:21:49.646364
3939 13:21:49.649533 [CBTSetCACLKResult] CA Dly = 33
3940 13:21:49.652899 CS Dly: 5 (0~37)
3941 13:21:49.652980
3942 13:21:49.656033 ----->DramcWriteLeveling(PI) begin...
3943 13:21:49.656115 ==
3944 13:21:49.659601 Dram Type= 6, Freq= 0, CH_0, rank 0
3945 13:21:49.662359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3946 13:21:49.662441 ==
3947 13:21:49.665381 Write leveling (Byte 0): 33 => 33
3948 13:21:49.668733 Write leveling (Byte 1): 33 => 33
3949 13:21:49.672181 DramcWriteLeveling(PI) end<-----
3950 13:21:49.672263
3951 13:21:49.672327 ==
3952 13:21:49.675431 Dram Type= 6, Freq= 0, CH_0, rank 0
3953 13:21:49.678702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3954 13:21:49.678784 ==
3955 13:21:49.682233 [Gating] SW mode calibration
3956 13:21:49.688809 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3957 13:21:49.695748 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3958 13:21:49.699123 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3959 13:21:49.705159 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3960 13:21:49.708158 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3961 13:21:49.711450 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
3962 13:21:49.718479 0 9 16 | B1->B0 | 2f2f 2626 | 0 0 | (0 1) (0 0)
3963 13:21:49.721761 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3964 13:21:49.725202 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3965 13:21:49.731394 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3966 13:21:49.734888 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3967 13:21:49.737839 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3968 13:21:49.744405 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3969 13:21:49.747616 0 10 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
3970 13:21:49.751216 0 10 16 | B1->B0 | 3838 4444 | 0 0 | (1 1) (0 0)
3971 13:21:49.758003 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3972 13:21:49.761460 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3973 13:21:49.764293 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3974 13:21:49.770769 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3975 13:21:49.774687 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3976 13:21:49.777746 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3977 13:21:49.784155 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 13:21:49.787211 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3979 13:21:49.790806 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3980 13:21:49.797605 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3981 13:21:49.800794 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3982 13:21:49.804278 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 13:21:49.810340 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 13:21:49.814155 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 13:21:49.817077 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 13:21:49.824119 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 13:21:49.826532 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 13:21:49.830180 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 13:21:49.836772 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 13:21:49.840139 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 13:21:49.843298 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 13:21:49.851065 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 13:21:49.853548 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3994 13:21:49.857024 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3995 13:21:49.860121 Total UI for P1: 0, mck2ui 16
3996 13:21:49.863007 best dqsien dly found for B0: ( 0, 13, 12)
3997 13:21:49.870175 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 13:21:49.870283 Total UI for P1: 0, mck2ui 16
3999 13:21:49.876563 best dqsien dly found for B1: ( 0, 13, 16)
4000 13:21:49.879284 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4001 13:21:49.883155 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4002 13:21:49.883236
4003 13:21:49.886031 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4004 13:21:49.889376 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4005 13:21:49.892937 [Gating] SW calibration Done
4006 13:21:49.893018 ==
4007 13:21:49.895942 Dram Type= 6, Freq= 0, CH_0, rank 0
4008 13:21:49.899167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4009 13:21:49.899265 ==
4010 13:21:49.902694 RX Vref Scan: 0
4011 13:21:49.902821
4012 13:21:49.902885 RX Vref 0 -> 0, step: 1
4013 13:21:49.906496
4014 13:21:49.906576 RX Delay -230 -> 252, step: 16
4015 13:21:49.913073 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4016 13:21:49.916039 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4017 13:21:49.919561 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4018 13:21:49.922144 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4019 13:21:49.929102 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4020 13:21:49.932182 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4021 13:21:49.935362 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4022 13:21:49.938794 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4023 13:21:49.945615 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4024 13:21:49.948792 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4025 13:21:49.952526 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4026 13:21:49.956847 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4027 13:21:49.962028 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4028 13:21:49.964950 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4029 13:21:49.968150 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4030 13:21:49.972859 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4031 13:21:49.972959 ==
4032 13:21:49.975117 Dram Type= 6, Freq= 0, CH_0, rank 0
4033 13:21:49.981669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4034 13:21:49.981750 ==
4035 13:21:49.981815 DQS Delay:
4036 13:21:49.985101 DQS0 = 0, DQS1 = 0
4037 13:21:49.985182 DQM Delay:
4038 13:21:49.985246 DQM0 = 44, DQM1 = 33
4039 13:21:49.988201 DQ Delay:
4040 13:21:49.991900 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4041 13:21:49.994470 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4042 13:21:49.997878 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4043 13:21:50.001467 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4044 13:21:50.001565
4045 13:21:50.001644
4046 13:21:50.001704 ==
4047 13:21:50.004825 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 13:21:50.008026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 13:21:50.008161 ==
4050 13:21:50.008316
4051 13:21:50.008415
4052 13:21:50.011122 TX Vref Scan disable
4053 13:21:50.014273 == TX Byte 0 ==
4054 13:21:50.017868 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4055 13:21:50.020675 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4056 13:21:50.024196 == TX Byte 1 ==
4057 13:21:50.027851 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4058 13:21:50.030845 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4059 13:21:50.030927 ==
4060 13:21:50.034391 Dram Type= 6, Freq= 0, CH_0, rank 0
4061 13:21:50.040529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 13:21:50.040612 ==
4063 13:21:50.040676
4064 13:21:50.040753
4065 13:21:50.040855 TX Vref Scan disable
4066 13:21:50.045036 == TX Byte 0 ==
4067 13:21:50.048323 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4068 13:21:50.054771 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4069 13:21:50.054853 == TX Byte 1 ==
4070 13:21:50.058824 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4071 13:21:50.064955 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4072 13:21:50.065100
4073 13:21:50.065165 [DATLAT]
4074 13:21:50.065226 Freq=600, CH0 RK0
4075 13:21:50.065284
4076 13:21:50.068450 DATLAT Default: 0x9
4077 13:21:50.071438 0, 0xFFFF, sum = 0
4078 13:21:50.071521 1, 0xFFFF, sum = 0
4079 13:21:50.074681 2, 0xFFFF, sum = 0
4080 13:21:50.074764 3, 0xFFFF, sum = 0
4081 13:21:50.077932 4, 0xFFFF, sum = 0
4082 13:21:50.078019 5, 0xFFFF, sum = 0
4083 13:21:50.081047 6, 0xFFFF, sum = 0
4084 13:21:50.081130 7, 0xFFFF, sum = 0
4085 13:21:50.084526 8, 0x0, sum = 1
4086 13:21:50.084608 9, 0x0, sum = 2
4087 13:21:50.087406 10, 0x0, sum = 3
4088 13:21:50.087489 11, 0x0, sum = 4
4089 13:21:50.087555 best_step = 9
4090 13:21:50.087615
4091 13:21:50.091026 ==
4092 13:21:50.094242 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 13:21:50.097650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 13:21:50.097732 ==
4095 13:21:50.097796 RX Vref Scan: 1
4096 13:21:50.097856
4097 13:21:50.101087 RX Vref 0 -> 0, step: 1
4098 13:21:50.101168
4099 13:21:50.104374 RX Delay -195 -> 252, step: 8
4100 13:21:50.104455
4101 13:21:50.107415 Set Vref, RX VrefLevel [Byte0]: 50
4102 13:21:50.110438 [Byte1]: 58
4103 13:21:50.110520
4104 13:21:50.113957 Final RX Vref Byte 0 = 50 to rank0
4105 13:21:50.117394 Final RX Vref Byte 1 = 58 to rank0
4106 13:21:50.120720 Final RX Vref Byte 0 = 50 to rank1
4107 13:21:50.123772 Final RX Vref Byte 1 = 58 to rank1==
4108 13:21:50.126949 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 13:21:50.133604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 13:21:50.133685 ==
4111 13:21:50.133749 DQS Delay:
4112 13:21:50.133809 DQS0 = 0, DQS1 = 0
4113 13:21:50.137453 DQM Delay:
4114 13:21:50.137533 DQM0 = 42, DQM1 = 32
4115 13:21:50.140174 DQ Delay:
4116 13:21:50.143594 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4117 13:21:50.147200 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4118 13:21:50.150019 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4119 13:21:50.153531 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4120 13:21:50.153612
4121 13:21:50.153676
4122 13:21:50.160151 [DQSOSCAuto] RK0, (LSB)MR18= 0x5047, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
4123 13:21:50.163919 CH0 RK0: MR19=808, MR18=5047
4124 13:21:50.170048 CH0_RK0: MR19=0x808, MR18=0x5047, DQSOSC=394, MR23=63, INC=168, DEC=112
4125 13:21:50.170129
4126 13:21:50.173172 ----->DramcWriteLeveling(PI) begin...
4127 13:21:50.173287 ==
4128 13:21:50.176544 Dram Type= 6, Freq= 0, CH_0, rank 1
4129 13:21:50.179833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 13:21:50.179924 ==
4131 13:21:50.182942 Write leveling (Byte 0): 33 => 33
4132 13:21:50.186232 Write leveling (Byte 1): 30 => 30
4133 13:21:50.189839 DramcWriteLeveling(PI) end<-----
4134 13:21:50.189919
4135 13:21:50.189983 ==
4136 13:21:50.193129 Dram Type= 6, Freq= 0, CH_0, rank 1
4137 13:21:50.195810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4138 13:21:50.199435 ==
4139 13:21:50.199516 [Gating] SW mode calibration
4140 13:21:50.209366 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4141 13:21:50.212412 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4142 13:21:50.216213 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4143 13:21:50.223025 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4144 13:21:50.226186 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4145 13:21:50.229280 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4146 13:21:50.235610 0 9 16 | B1->B0 | 2f2f 2b2b | 0 0 | (0 0) (0 0)
4147 13:21:50.238852 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4148 13:21:50.242914 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4149 13:21:50.248707 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4150 13:21:50.251874 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4151 13:21:50.255585 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4152 13:21:50.261770 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4153 13:21:50.265638 0 10 12 | B1->B0 | 2727 3838 | 0 0 | (0 0) (0 0)
4154 13:21:50.268275 0 10 16 | B1->B0 | 4343 4545 | 1 0 | (0 0) (0 0)
4155 13:21:50.275273 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4156 13:21:50.278454 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4157 13:21:50.281775 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4158 13:21:50.288224 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4159 13:21:50.291309 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4160 13:21:50.294912 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4161 13:21:50.301465 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4162 13:21:50.304656 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4163 13:21:50.308159 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4164 13:21:50.314677 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4165 13:21:50.317600 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4166 13:21:50.320930 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4167 13:21:50.327556 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 13:21:50.330795 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 13:21:50.337421 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 13:21:50.340757 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 13:21:50.343753 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 13:21:50.347159 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 13:21:50.354067 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 13:21:50.357422 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 13:21:50.364138 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 13:21:50.367551 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 13:21:50.370421 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 13:21:50.373631 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 13:21:50.377102 Total UI for P1: 0, mck2ui 16
4180 13:21:50.380199 best dqsien dly found for B0: ( 0, 13, 14)
4181 13:21:50.383506 Total UI for P1: 0, mck2ui 16
4182 13:21:50.386855 best dqsien dly found for B1: ( 0, 13, 14)
4183 13:21:50.390628 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4184 13:21:50.397004 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4185 13:21:50.397117
4186 13:21:50.400526 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4187 13:21:50.403697 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4188 13:21:50.407090 [Gating] SW calibration Done
4189 13:21:50.407198 ==
4190 13:21:50.410140 Dram Type= 6, Freq= 0, CH_0, rank 1
4191 13:21:50.413489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 13:21:50.413594 ==
4193 13:21:50.416723 RX Vref Scan: 0
4194 13:21:50.416827
4195 13:21:50.416922 RX Vref 0 -> 0, step: 1
4196 13:21:50.417018
4197 13:21:50.419801 RX Delay -230 -> 252, step: 16
4198 13:21:50.426530 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4199 13:21:50.429440 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4200 13:21:50.433079 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4201 13:21:50.436562 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4202 13:21:50.439709 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4203 13:21:50.446278 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4204 13:21:50.449425 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4205 13:21:50.452866 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4206 13:21:50.455856 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4207 13:21:50.462468 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4208 13:21:50.465776 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4209 13:21:50.468884 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4210 13:21:50.472291 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4211 13:21:50.479175 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4212 13:21:50.481889 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4213 13:21:50.485269 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4214 13:21:50.485367 ==
4215 13:21:50.488591 Dram Type= 6, Freq= 0, CH_0, rank 1
4216 13:21:50.495671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 13:21:50.495790 ==
4218 13:21:50.495911 DQS Delay:
4219 13:21:50.496017 DQS0 = 0, DQS1 = 0
4220 13:21:50.499557 DQM Delay:
4221 13:21:50.499661 DQM0 = 41, DQM1 = 33
4222 13:21:50.502379 DQ Delay:
4223 13:21:50.505147 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4224 13:21:50.509267 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4225 13:21:50.511740 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4226 13:21:50.514712 DQ12 =41, DQ13 =33, DQ14 =49, DQ15 =41
4227 13:21:50.514818
4228 13:21:50.514914
4229 13:21:50.515001 ==
4230 13:21:50.518523 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 13:21:50.521222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 13:21:50.521307 ==
4233 13:21:50.521371
4234 13:21:50.521432
4235 13:21:50.524976 TX Vref Scan disable
4236 13:21:50.528074 == TX Byte 0 ==
4237 13:21:50.531265 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4238 13:21:50.534334 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4239 13:21:50.537603 == TX Byte 1 ==
4240 13:21:50.542069 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4241 13:21:50.544593 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4242 13:21:50.544693 ==
4243 13:21:50.547795 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 13:21:50.550951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 13:21:50.554767 ==
4246 13:21:50.554876
4247 13:21:50.554966
4248 13:21:50.555053 TX Vref Scan disable
4249 13:21:50.558174 == TX Byte 0 ==
4250 13:21:50.561629 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4251 13:21:50.568410 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4252 13:21:50.568512 == TX Byte 1 ==
4253 13:21:50.571509 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4254 13:21:50.578243 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4255 13:21:50.578343
4256 13:21:50.578443 [DATLAT]
4257 13:21:50.578533 Freq=600, CH0 RK1
4258 13:21:50.578621
4259 13:21:50.581634 DATLAT Default: 0x9
4260 13:21:50.581740 0, 0xFFFF, sum = 0
4261 13:21:50.585077 1, 0xFFFF, sum = 0
4262 13:21:50.588253 2, 0xFFFF, sum = 0
4263 13:21:50.588360 3, 0xFFFF, sum = 0
4264 13:21:50.591276 4, 0xFFFF, sum = 0
4265 13:21:50.591382 5, 0xFFFF, sum = 0
4266 13:21:50.594932 6, 0xFFFF, sum = 0
4267 13:21:50.595008 7, 0xFFFF, sum = 0
4268 13:21:50.598321 8, 0x0, sum = 1
4269 13:21:50.598425 9, 0x0, sum = 2
4270 13:21:50.598518 10, 0x0, sum = 3
4271 13:21:50.601011 11, 0x0, sum = 4
4272 13:21:50.601110 best_step = 9
4273 13:21:50.601209
4274 13:21:50.604985 ==
4275 13:21:50.605090 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 13:21:50.611459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 13:21:50.611560 ==
4278 13:21:50.611659 RX Vref Scan: 0
4279 13:21:50.611750
4280 13:21:50.614690 RX Vref 0 -> 0, step: 1
4281 13:21:50.614787
4282 13:21:50.617872 RX Delay -195 -> 252, step: 8
4283 13:21:50.624711 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4284 13:21:50.627573 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4285 13:21:50.631183 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4286 13:21:50.634140 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4287 13:21:50.638102 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4288 13:21:50.644128 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4289 13:21:50.647678 iDelay=205, Bit 6, Center 48 (-99 ~ 196) 296
4290 13:21:50.650867 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4291 13:21:50.653969 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4292 13:21:50.660629 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4293 13:21:50.664024 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4294 13:21:50.667164 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4295 13:21:50.670272 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4296 13:21:50.676833 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4297 13:21:50.680352 iDelay=205, Bit 14, Center 44 (-115 ~ 204) 320
4298 13:21:50.683594 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4299 13:21:50.683696 ==
4300 13:21:50.686714 Dram Type= 6, Freq= 0, CH_0, rank 1
4301 13:21:50.689963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4302 13:21:50.693741 ==
4303 13:21:50.693848 DQS Delay:
4304 13:21:50.693942 DQS0 = 0, DQS1 = 0
4305 13:21:50.697027 DQM Delay:
4306 13:21:50.697132 DQM0 = 41, DQM1 = 33
4307 13:21:50.700171 DQ Delay:
4308 13:21:50.703222 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4309 13:21:50.706443 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48
4310 13:21:50.706554 DQ8 =24, DQ9 =16, DQ10 =40, DQ11 =24
4311 13:21:50.713313 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4312 13:21:50.713425
4313 13:21:50.713527
4314 13:21:50.719584 [DQSOSCAuto] RK1, (LSB)MR18= 0x4743, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4315 13:21:50.722867 CH0 RK1: MR19=808, MR18=4743
4316 13:21:50.729570 CH0_RK1: MR19=0x808, MR18=0x4743, DQSOSC=396, MR23=63, INC=167, DEC=111
4317 13:21:50.732638 [RxdqsGatingPostProcess] freq 600
4318 13:21:50.736972 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4319 13:21:50.740086 Pre-setting of DQS Precalculation
4320 13:21:50.746524 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4321 13:21:50.746624 ==
4322 13:21:50.749632 Dram Type= 6, Freq= 0, CH_1, rank 0
4323 13:21:50.752880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 13:21:50.752986 ==
4325 13:21:50.759108 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4326 13:21:50.766127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4327 13:21:50.769308 [CA 0] Center 36 (6~66) winsize 61
4328 13:21:50.772106 [CA 1] Center 35 (5~66) winsize 62
4329 13:21:50.775639 [CA 2] Center 34 (4~65) winsize 62
4330 13:21:50.779004 [CA 3] Center 34 (3~65) winsize 63
4331 13:21:50.782276 [CA 4] Center 34 (4~65) winsize 62
4332 13:21:50.785520 [CA 5] Center 33 (3~64) winsize 62
4333 13:21:50.785620
4334 13:21:50.788758 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4335 13:21:50.788862
4336 13:21:50.792064 [CATrainingPosCal] consider 1 rank data
4337 13:21:50.795303 u2DelayCellTimex100 = 270/100 ps
4338 13:21:50.798774 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4339 13:21:50.802096 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4340 13:21:50.805012 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4341 13:21:50.808519 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4342 13:21:50.811556 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4343 13:21:50.815326 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4344 13:21:50.815431
4345 13:21:50.821578 CA PerBit enable=1, Macro0, CA PI delay=33
4346 13:21:50.821682
4347 13:21:50.824969 [CBTSetCACLKResult] CA Dly = 33
4348 13:21:50.825067 CS Dly: 5 (0~36)
4349 13:21:50.825166 ==
4350 13:21:50.828815 Dram Type= 6, Freq= 0, CH_1, rank 1
4351 13:21:50.831898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4352 13:21:50.832033 ==
4353 13:21:50.838483 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4354 13:21:50.844863 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4355 13:21:50.848293 [CA 0] Center 35 (5~66) winsize 62
4356 13:21:50.851299 [CA 1] Center 35 (5~66) winsize 62
4357 13:21:50.855351 [CA 2] Center 34 (4~65) winsize 62
4358 13:21:50.858431 [CA 3] Center 34 (3~65) winsize 63
4359 13:21:50.861169 [CA 4] Center 34 (4~65) winsize 62
4360 13:21:50.864275 [CA 5] Center 33 (3~64) winsize 62
4361 13:21:50.864382
4362 13:21:50.867632 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4363 13:21:50.867740
4364 13:21:50.871228 [CATrainingPosCal] consider 2 rank data
4365 13:21:50.874366 u2DelayCellTimex100 = 270/100 ps
4366 13:21:50.877421 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4367 13:21:50.880910 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4368 13:21:50.884241 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4369 13:21:50.890614 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4370 13:21:50.894297 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4371 13:21:50.897314 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4372 13:21:50.897422
4373 13:21:50.900911 CA PerBit enable=1, Macro0, CA PI delay=33
4374 13:21:50.901007
4375 13:21:50.903719 [CBTSetCACLKResult] CA Dly = 33
4376 13:21:50.903823 CS Dly: 5 (0~36)
4377 13:21:50.903935
4378 13:21:50.907376 ----->DramcWriteLeveling(PI) begin...
4379 13:21:50.910667 ==
4380 13:21:50.914063 Dram Type= 6, Freq= 0, CH_1, rank 0
4381 13:21:50.917187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4382 13:21:50.917293 ==
4383 13:21:50.920466 Write leveling (Byte 0): 28 => 28
4384 13:21:50.923896 Write leveling (Byte 1): 29 => 29
4385 13:21:50.927147 DramcWriteLeveling(PI) end<-----
4386 13:21:50.927251
4387 13:21:50.927349 ==
4388 13:21:50.930006 Dram Type= 6, Freq= 0, CH_1, rank 0
4389 13:21:50.933419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 13:21:50.933516 ==
4391 13:21:50.936799 [Gating] SW mode calibration
4392 13:21:50.943244 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4393 13:21:50.951018 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4394 13:21:50.953097 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4395 13:21:50.956384 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4396 13:21:50.962799 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4397 13:21:50.966542 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (1 1)
4398 13:21:50.969501 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4399 13:21:50.976082 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4400 13:21:50.979315 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4401 13:21:50.982609 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4402 13:21:50.989519 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4403 13:21:50.992865 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4404 13:21:50.996206 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 13:21:51.002688 0 10 12 | B1->B0 | 3030 3838 | 0 0 | (0 0) (0 0)
4406 13:21:51.005888 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4407 13:21:51.009782 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4408 13:21:51.016416 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4409 13:21:51.019616 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4410 13:21:51.022204 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4411 13:21:51.029213 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4412 13:21:51.032460 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 13:21:51.035433 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4414 13:21:51.042340 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4415 13:21:51.045305 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 13:21:51.048733 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 13:21:51.056085 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 13:21:51.058588 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 13:21:51.062326 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 13:21:51.068717 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 13:21:51.072013 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 13:21:51.075466 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 13:21:51.081507 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 13:21:51.084874 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 13:21:51.088101 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 13:21:51.094835 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 13:21:51.098276 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 13:21:51.101814 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 13:21:51.108054 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 13:21:51.111230 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 13:21:51.114520 Total UI for P1: 0, mck2ui 16
4432 13:21:51.118296 best dqsien dly found for B0: ( 0, 13, 14)
4433 13:21:51.122017 Total UI for P1: 0, mck2ui 16
4434 13:21:51.124557 best dqsien dly found for B1: ( 0, 13, 14)
4435 13:21:51.128293 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4436 13:21:51.130921 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4437 13:21:51.131016
4438 13:21:51.134741 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4439 13:21:51.141453 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4440 13:21:51.141546 [Gating] SW calibration Done
4441 13:21:51.141644 ==
4442 13:21:51.144342 Dram Type= 6, Freq= 0, CH_1, rank 0
4443 13:21:51.150806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 13:21:51.150907 ==
4445 13:21:51.151007 RX Vref Scan: 0
4446 13:21:51.151103
4447 13:21:51.154018 RX Vref 0 -> 0, step: 1
4448 13:21:51.154093
4449 13:21:51.157095 RX Delay -230 -> 252, step: 16
4450 13:21:51.160814 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4451 13:21:51.163661 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4452 13:21:51.166885 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4453 13:21:51.173753 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4454 13:21:51.176849 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4455 13:21:51.180260 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4456 13:21:51.183846 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4457 13:21:51.190821 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4458 13:21:51.193818 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4459 13:21:51.196776 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4460 13:21:51.200649 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4461 13:21:51.206740 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4462 13:21:51.210022 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4463 13:21:51.213618 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4464 13:21:51.216605 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4465 13:21:51.223622 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4466 13:21:51.223707 ==
4467 13:21:51.226338 Dram Type= 6, Freq= 0, CH_1, rank 0
4468 13:21:51.230317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4469 13:21:51.230401 ==
4470 13:21:51.230467 DQS Delay:
4471 13:21:51.233223 DQS0 = 0, DQS1 = 0
4472 13:21:51.233306 DQM Delay:
4473 13:21:51.236514 DQM0 = 43, DQM1 = 38
4474 13:21:51.236598 DQ Delay:
4475 13:21:51.239796 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4476 13:21:51.243840 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4477 13:21:51.246410 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4478 13:21:51.249449 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4479 13:21:51.249538
4480 13:21:51.249604
4481 13:21:51.249665 ==
4482 13:21:51.252845 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 13:21:51.255807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 13:21:51.259280 ==
4485 13:21:51.259363
4486 13:21:51.259427
4487 13:21:51.259488 TX Vref Scan disable
4488 13:21:51.262566 == TX Byte 0 ==
4489 13:21:51.265799 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4490 13:21:51.272458 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4491 13:21:51.272547 == TX Byte 1 ==
4492 13:21:51.275659 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4493 13:21:51.282215 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4494 13:21:51.282317 ==
4495 13:21:51.285985 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 13:21:51.289195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 13:21:51.289299 ==
4498 13:21:51.289402
4499 13:21:51.289496
4500 13:21:51.292536 TX Vref Scan disable
4501 13:21:51.295622 == TX Byte 0 ==
4502 13:21:51.299005 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4503 13:21:51.302140 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4504 13:21:51.305420 == TX Byte 1 ==
4505 13:21:51.308884 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4506 13:21:51.312162 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4507 13:21:51.312238
4508 13:21:51.312300 [DATLAT]
4509 13:21:51.315624 Freq=600, CH1 RK0
4510 13:21:51.315726
4511 13:21:51.318580 DATLAT Default: 0x9
4512 13:21:51.318680 0, 0xFFFF, sum = 0
4513 13:21:51.321729 1, 0xFFFF, sum = 0
4514 13:21:51.321832 2, 0xFFFF, sum = 0
4515 13:21:51.325224 3, 0xFFFF, sum = 0
4516 13:21:51.325300 4, 0xFFFF, sum = 0
4517 13:21:51.328939 5, 0xFFFF, sum = 0
4518 13:21:51.329016 6, 0xFFFF, sum = 0
4519 13:21:51.332174 7, 0xFFFF, sum = 0
4520 13:21:51.332250 8, 0x0, sum = 1
4521 13:21:51.335287 9, 0x0, sum = 2
4522 13:21:51.335359 10, 0x0, sum = 3
4523 13:21:51.338620 11, 0x0, sum = 4
4524 13:21:51.338716 best_step = 9
4525 13:21:51.338804
4526 13:21:51.338893 ==
4527 13:21:51.341815 Dram Type= 6, Freq= 0, CH_1, rank 0
4528 13:21:51.344949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4529 13:21:51.345017 ==
4530 13:21:51.348490 RX Vref Scan: 1
4531 13:21:51.348555
4532 13:21:51.351485 RX Vref 0 -> 0, step: 1
4533 13:21:51.351580
4534 13:21:51.351670 RX Delay -179 -> 252, step: 8
4535 13:21:51.354768
4536 13:21:51.354860 Set Vref, RX VrefLevel [Byte0]: 52
4537 13:21:51.358672 [Byte1]: 53
4538 13:21:51.362899
4539 13:21:51.362993 Final RX Vref Byte 0 = 52 to rank0
4540 13:21:51.366673 Final RX Vref Byte 1 = 53 to rank0
4541 13:21:51.369697 Final RX Vref Byte 0 = 52 to rank1
4542 13:21:51.373040 Final RX Vref Byte 1 = 53 to rank1==
4543 13:21:51.376144 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 13:21:51.383175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 13:21:51.383274 ==
4546 13:21:51.383367 DQS Delay:
4547 13:21:51.386072 DQS0 = 0, DQS1 = 0
4548 13:21:51.386155 DQM Delay:
4549 13:21:51.386219 DQM0 = 42, DQM1 = 34
4550 13:21:51.389386 DQ Delay:
4551 13:21:51.392487 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4552 13:21:51.395973 DQ4 =36, DQ5 =48, DQ6 =56, DQ7 =36
4553 13:21:51.399326 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4554 13:21:51.402812 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =40
4555 13:21:51.402894
4556 13:21:51.402957
4557 13:21:51.409472 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e48, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4558 13:21:51.412277 CH1 RK0: MR19=808, MR18=2E48
4559 13:21:51.418936 CH1_RK0: MR19=0x808, MR18=0x2E48, DQSOSC=396, MR23=63, INC=167, DEC=111
4560 13:21:51.419032
4561 13:21:51.422664 ----->DramcWriteLeveling(PI) begin...
4562 13:21:51.422746 ==
4563 13:21:51.425652 Dram Type= 6, Freq= 0, CH_1, rank 1
4564 13:21:51.429225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 13:21:51.429306 ==
4566 13:21:51.433011 Write leveling (Byte 0): 28 => 28
4567 13:21:51.435505 Write leveling (Byte 1): 29 => 29
4568 13:21:51.438801 DramcWriteLeveling(PI) end<-----
4569 13:21:51.438883
4570 13:21:51.438947 ==
4571 13:21:51.442201 Dram Type= 6, Freq= 0, CH_1, rank 1
4572 13:21:51.445511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 13:21:51.448739 ==
4574 13:21:51.448846 [Gating] SW mode calibration
4575 13:21:51.458707 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4576 13:21:51.462274 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4577 13:21:51.465050 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4578 13:21:51.472046 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4579 13:21:51.474886 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4580 13:21:51.478026 0 9 12 | B1->B0 | 3131 2828 | 1 0 | (1 1) (1 0)
4581 13:21:51.484969 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4582 13:21:51.488206 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4583 13:21:51.491358 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4584 13:21:51.498637 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4585 13:21:51.501235 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4586 13:21:51.504447 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4587 13:21:51.510911 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4588 13:21:51.515023 0 10 12 | B1->B0 | 3232 3c3c | 1 1 | (0 0) (0 0)
4589 13:21:51.518025 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4590 13:21:51.524454 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4591 13:21:51.527971 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4592 13:21:51.530804 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4593 13:21:51.537444 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4594 13:21:51.540839 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4595 13:21:51.544200 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4596 13:21:51.551116 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4597 13:21:51.553636 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4598 13:21:51.557736 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4599 13:21:51.563482 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4600 13:21:51.566812 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4601 13:21:51.573513 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4602 13:21:51.576697 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 13:21:51.580082 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 13:21:51.586980 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 13:21:51.589764 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 13:21:51.593530 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 13:21:51.599911 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 13:21:51.603375 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 13:21:51.606400 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 13:21:51.613296 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 13:21:51.616433 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 13:21:51.620203 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4613 13:21:51.626108 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 13:21:51.626208 Total UI for P1: 0, mck2ui 16
4615 13:21:51.629668 best dqsien dly found for B0: ( 0, 13, 12)
4616 13:21:51.632492 Total UI for P1: 0, mck2ui 16
4617 13:21:51.636417 best dqsien dly found for B1: ( 0, 13, 12)
4618 13:21:51.642709 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4619 13:21:51.646081 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4620 13:21:51.646178
4621 13:21:51.649155 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4622 13:21:51.652733 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4623 13:21:51.655638 [Gating] SW calibration Done
4624 13:21:51.655709 ==
4625 13:21:51.659327 Dram Type= 6, Freq= 0, CH_1, rank 1
4626 13:21:51.662791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 13:21:51.662895 ==
4628 13:21:51.666046 RX Vref Scan: 0
4629 13:21:51.666149
4630 13:21:51.666241 RX Vref 0 -> 0, step: 1
4631 13:21:51.666327
4632 13:21:51.669109 RX Delay -230 -> 252, step: 16
4633 13:21:51.676310 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4634 13:21:51.678900 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4635 13:21:51.682655 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4636 13:21:51.685740 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4637 13:21:51.692258 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4638 13:21:51.695424 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4639 13:21:51.698158 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4640 13:21:51.701426 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4641 13:21:51.705147 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4642 13:21:51.712020 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4643 13:21:51.715479 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4644 13:21:51.718584 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4645 13:21:51.721728 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4646 13:21:51.728110 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4647 13:21:51.731584 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4648 13:21:51.734778 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4649 13:21:51.734848 ==
4650 13:21:51.737617 Dram Type= 6, Freq= 0, CH_1, rank 1
4651 13:21:51.744354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 13:21:51.744429 ==
4653 13:21:51.744507 DQS Delay:
4654 13:21:51.748021 DQS0 = 0, DQS1 = 0
4655 13:21:51.748088 DQM Delay:
4656 13:21:51.748147 DQM0 = 44, DQM1 = 41
4657 13:21:51.751057 DQ Delay:
4658 13:21:51.754005 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4659 13:21:51.757589 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4660 13:21:51.760934 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4661 13:21:51.764134 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =57
4662 13:21:51.764214
4663 13:21:51.764277
4664 13:21:51.764335 ==
4665 13:21:51.767645 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 13:21:51.770576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 13:21:51.770650 ==
4668 13:21:51.770711
4669 13:21:51.770770
4670 13:21:51.773988 TX Vref Scan disable
4671 13:21:51.777451 == TX Byte 0 ==
4672 13:21:51.780461 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4673 13:21:51.784050 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4674 13:21:51.787205 == TX Byte 1 ==
4675 13:21:51.790628 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4676 13:21:51.793985 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4677 13:21:51.794053 ==
4678 13:21:51.797385 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 13:21:51.800323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 13:21:51.803406 ==
4681 13:21:51.803485
4682 13:21:51.803545
4683 13:21:51.803604 TX Vref Scan disable
4684 13:21:51.807854 == TX Byte 0 ==
4685 13:21:51.811002 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4686 13:21:51.817694 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4687 13:21:51.817765 == TX Byte 1 ==
4688 13:21:51.820919 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4689 13:21:51.827453 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4690 13:21:51.827561
4691 13:21:51.827655 [DATLAT]
4692 13:21:51.827751 Freq=600, CH1 RK1
4693 13:21:51.827844
4694 13:21:51.831210 DATLAT Default: 0x9
4695 13:21:51.833680 0, 0xFFFF, sum = 0
4696 13:21:51.833785 1, 0xFFFF, sum = 0
4697 13:21:51.836987 2, 0xFFFF, sum = 0
4698 13:21:51.837059 3, 0xFFFF, sum = 0
4699 13:21:51.840728 4, 0xFFFF, sum = 0
4700 13:21:51.840806 5, 0xFFFF, sum = 0
4701 13:21:51.843801 6, 0xFFFF, sum = 0
4702 13:21:51.843911 7, 0xFFFF, sum = 0
4703 13:21:51.847366 8, 0x0, sum = 1
4704 13:21:51.847470 9, 0x0, sum = 2
4705 13:21:51.850081 10, 0x0, sum = 3
4706 13:21:51.850182 11, 0x0, sum = 4
4707 13:21:51.850281 best_step = 9
4708 13:21:51.850380
4709 13:21:51.853424 ==
4710 13:21:51.856751 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 13:21:51.860642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 13:21:51.860749 ==
4713 13:21:51.860885 RX Vref Scan: 0
4714 13:21:51.860972
4715 13:21:51.863587 RX Vref 0 -> 0, step: 1
4716 13:21:51.863685
4717 13:21:51.866620 RX Delay -179 -> 252, step: 8
4718 13:21:51.873058 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4719 13:21:51.876874 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4720 13:21:51.879661 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4721 13:21:51.883060 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4722 13:21:51.890157 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4723 13:21:51.893220 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4724 13:21:51.896794 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4725 13:21:51.899774 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4726 13:21:51.903239 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4727 13:21:51.909804 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4728 13:21:51.912982 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4729 13:21:51.916577 iDelay=205, Bit 11, Center 28 (-131 ~ 188) 320
4730 13:21:51.919831 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4731 13:21:51.926235 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4732 13:21:51.929955 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4733 13:21:51.933034 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4734 13:21:51.933115 ==
4735 13:21:51.936045 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 13:21:51.940047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 13:21:51.942798 ==
4738 13:21:51.942872 DQS Delay:
4739 13:21:51.942935 DQS0 = 0, DQS1 = 0
4740 13:21:51.946177 DQM Delay:
4741 13:21:51.946254 DQM0 = 37, DQM1 = 35
4742 13:21:51.949256 DQ Delay:
4743 13:21:51.952612 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4744 13:21:51.952692 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4745 13:21:51.956331 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4746 13:21:51.962319 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4747 13:21:51.962418
4748 13:21:51.962517
4749 13:21:51.969303 [DQSOSCAuto] RK1, (LSB)MR18= 0x3358, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4750 13:21:51.972117 CH1 RK1: MR19=808, MR18=3358
4751 13:21:51.979222 CH1_RK1: MR19=0x808, MR18=0x3358, DQSOSC=393, MR23=63, INC=169, DEC=113
4752 13:21:51.982346 [RxdqsGatingPostProcess] freq 600
4753 13:21:51.985783 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4754 13:21:51.989116 Pre-setting of DQS Precalculation
4755 13:21:51.995468 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4756 13:21:52.002188 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4757 13:21:52.008592 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4758 13:21:52.008701
4759 13:21:52.008796
4760 13:21:52.011812 [Calibration Summary] 1200 Mbps
4761 13:21:52.011936 CH 0, Rank 0
4762 13:21:52.015542 SW Impedance : PASS
4763 13:21:52.018090 DUTY Scan : NO K
4764 13:21:52.018197 ZQ Calibration : PASS
4765 13:21:52.021498 Jitter Meter : NO K
4766 13:21:52.026043 CBT Training : PASS
4767 13:21:52.026144 Write leveling : PASS
4768 13:21:52.028574 RX DQS gating : PASS
4769 13:21:52.031439 RX DQ/DQS(RDDQC) : PASS
4770 13:21:52.031536 TX DQ/DQS : PASS
4771 13:21:52.034718 RX DATLAT : PASS
4772 13:21:52.038052 RX DQ/DQS(Engine): PASS
4773 13:21:52.038148 TX OE : NO K
4774 13:21:52.042040 All Pass.
4775 13:21:52.042136
4776 13:21:52.042228 CH 0, Rank 1
4777 13:21:52.045013 SW Impedance : PASS
4778 13:21:52.045108 DUTY Scan : NO K
4779 13:21:52.048168 ZQ Calibration : PASS
4780 13:21:52.051894 Jitter Meter : NO K
4781 13:21:52.052007 CBT Training : PASS
4782 13:21:52.055118 Write leveling : PASS
4783 13:21:52.057910 RX DQS gating : PASS
4784 13:21:52.058004 RX DQ/DQS(RDDQC) : PASS
4785 13:21:52.061407 TX DQ/DQS : PASS
4786 13:21:52.064624 RX DATLAT : PASS
4787 13:21:52.064696 RX DQ/DQS(Engine): PASS
4788 13:21:52.067599 TX OE : NO K
4789 13:21:52.067694 All Pass.
4790 13:21:52.067790
4791 13:21:52.071526 CH 1, Rank 0
4792 13:21:52.071622 SW Impedance : PASS
4793 13:21:52.074443 DUTY Scan : NO K
4794 13:21:52.077823 ZQ Calibration : PASS
4795 13:21:52.077930 Jitter Meter : NO K
4796 13:21:52.081000 CBT Training : PASS
4797 13:21:52.081109 Write leveling : PASS
4798 13:21:52.084401 RX DQS gating : PASS
4799 13:21:52.088135 RX DQ/DQS(RDDQC) : PASS
4800 13:21:52.088243 TX DQ/DQS : PASS
4801 13:21:52.091052 RX DATLAT : PASS
4802 13:21:52.094308 RX DQ/DQS(Engine): PASS
4803 13:21:52.094403 TX OE : NO K
4804 13:21:52.097801 All Pass.
4805 13:21:52.097899
4806 13:21:52.097986 CH 1, Rank 1
4807 13:21:52.100701 SW Impedance : PASS
4808 13:21:52.100796 DUTY Scan : NO K
4809 13:21:52.103956 ZQ Calibration : PASS
4810 13:21:52.107059 Jitter Meter : NO K
4811 13:21:52.107147 CBT Training : PASS
4812 13:21:52.111349 Write leveling : PASS
4813 13:21:52.113763 RX DQS gating : PASS
4814 13:21:52.113856 RX DQ/DQS(RDDQC) : PASS
4815 13:21:52.116924 TX DQ/DQS : PASS
4816 13:21:52.120748 RX DATLAT : PASS
4817 13:21:52.120845 RX DQ/DQS(Engine): PASS
4818 13:21:52.124121 TX OE : NO K
4819 13:21:52.124197 All Pass.
4820 13:21:52.124258
4821 13:21:52.127464 DramC Write-DBI off
4822 13:21:52.130553 PER_BANK_REFRESH: Hybrid Mode
4823 13:21:52.130649 TX_TRACKING: ON
4824 13:21:52.140088 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4825 13:21:52.143777 [FAST_K] Save calibration result to emmc
4826 13:21:52.147135 dramc_set_vcore_voltage set vcore to 662500
4827 13:21:52.150603 Read voltage for 933, 3
4828 13:21:52.150697 Vio18 = 0
4829 13:21:52.150788 Vcore = 662500
4830 13:21:52.153095 Vdram = 0
4831 13:21:52.153198 Vddq = 0
4832 13:21:52.153282 Vmddr = 0
4833 13:21:52.160211 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4834 13:21:52.163675 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4835 13:21:52.166485 MEM_TYPE=3, freq_sel=17
4836 13:21:52.169679 sv_algorithm_assistance_LP4_1600
4837 13:21:52.173036 ============ PULL DRAM RESETB DOWN ============
4838 13:21:52.179754 ========== PULL DRAM RESETB DOWN end =========
4839 13:21:52.182892 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4840 13:21:52.186184 ===================================
4841 13:21:52.189259 LPDDR4 DRAM CONFIGURATION
4842 13:21:52.192764 ===================================
4843 13:21:52.192867 EX_ROW_EN[0] = 0x0
4844 13:21:52.196215 EX_ROW_EN[1] = 0x0
4845 13:21:52.196317 LP4Y_EN = 0x0
4846 13:21:52.199373 WORK_FSP = 0x0
4847 13:21:52.199470 WL = 0x3
4848 13:21:52.202867 RL = 0x3
4849 13:21:52.202967 BL = 0x2
4850 13:21:52.206279 RPST = 0x0
4851 13:21:52.209308 RD_PRE = 0x0
4852 13:21:52.209407 WR_PRE = 0x1
4853 13:21:52.212490 WR_PST = 0x0
4854 13:21:52.212591 DBI_WR = 0x0
4855 13:21:52.215735 DBI_RD = 0x0
4856 13:21:52.215832 OTF = 0x1
4857 13:21:52.219240 ===================================
4858 13:21:52.223472 ===================================
4859 13:21:52.226002 ANA top config
4860 13:21:52.229473 ===================================
4861 13:21:52.229550 DLL_ASYNC_EN = 0
4862 13:21:52.232469 ALL_SLAVE_EN = 1
4863 13:21:52.236214 NEW_RANK_MODE = 1
4864 13:21:52.238697 DLL_IDLE_MODE = 1
4865 13:21:52.238805 LP45_APHY_COMB_EN = 1
4866 13:21:52.241996 TX_ODT_DIS = 1
4867 13:21:52.245325 NEW_8X_MODE = 1
4868 13:21:52.248727 ===================================
4869 13:21:52.252297 ===================================
4870 13:21:52.255771 data_rate = 1866
4871 13:21:52.258882 CKR = 1
4872 13:21:52.261822 DQ_P2S_RATIO = 8
4873 13:21:52.265208 ===================================
4874 13:21:52.265284 CA_P2S_RATIO = 8
4875 13:21:52.268710 DQ_CA_OPEN = 0
4876 13:21:52.271971 DQ_SEMI_OPEN = 0
4877 13:21:52.275350 CA_SEMI_OPEN = 0
4878 13:21:52.278850 CA_FULL_RATE = 0
4879 13:21:52.282323 DQ_CKDIV4_EN = 1
4880 13:21:52.282422 CA_CKDIV4_EN = 1
4881 13:21:52.285047 CA_PREDIV_EN = 0
4882 13:21:52.288662 PH8_DLY = 0
4883 13:21:52.291936 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4884 13:21:52.295099 DQ_AAMCK_DIV = 4
4885 13:21:52.298351 CA_AAMCK_DIV = 4
4886 13:21:52.298440 CA_ADMCK_DIV = 4
4887 13:21:52.301471 DQ_TRACK_CA_EN = 0
4888 13:21:52.305214 CA_PICK = 933
4889 13:21:52.308080 CA_MCKIO = 933
4890 13:21:52.311505 MCKIO_SEMI = 0
4891 13:21:52.314751 PLL_FREQ = 3732
4892 13:21:52.318050 DQ_UI_PI_RATIO = 32
4893 13:21:52.321395 CA_UI_PI_RATIO = 0
4894 13:21:52.324384 ===================================
4895 13:21:52.328164 ===================================
4896 13:21:52.328237 memory_type:LPDDR4
4897 13:21:52.331400 GP_NUM : 10
4898 13:21:52.334937 SRAM_EN : 1
4899 13:21:52.335007 MD32_EN : 0
4900 13:21:52.337524 ===================================
4901 13:21:52.340989 [ANA_INIT] >>>>>>>>>>>>>>
4902 13:21:52.344583 <<<<<< [CONFIGURE PHASE]: ANA_TX
4903 13:21:52.347572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4904 13:21:52.350819 ===================================
4905 13:21:52.354406 data_rate = 1866,PCW = 0X8f00
4906 13:21:52.357717 ===================================
4907 13:21:52.360673 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4908 13:21:52.363963 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4909 13:21:52.370908 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4910 13:21:52.374323 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4911 13:21:52.377674 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4912 13:21:52.380847 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4913 13:21:52.383705 [ANA_INIT] flow start
4914 13:21:52.387071 [ANA_INIT] PLL >>>>>>>>
4915 13:21:52.387174 [ANA_INIT] PLL <<<<<<<<
4916 13:21:52.390427 [ANA_INIT] MIDPI >>>>>>>>
4917 13:21:52.393900 [ANA_INIT] MIDPI <<<<<<<<
4918 13:21:52.397347 [ANA_INIT] DLL >>>>>>>>
4919 13:21:52.397457 [ANA_INIT] flow end
4920 13:21:52.400909 ============ LP4 DIFF to SE enter ============
4921 13:21:52.406946 ============ LP4 DIFF to SE exit ============
4922 13:21:52.407034 [ANA_INIT] <<<<<<<<<<<<<
4923 13:21:52.410197 [Flow] Enable top DCM control >>>>>
4924 13:21:52.413588 [Flow] Enable top DCM control <<<<<
4925 13:21:52.417685 Enable DLL master slave shuffle
4926 13:21:52.423575 ==============================================================
4927 13:21:52.423659 Gating Mode config
4928 13:21:52.429866 ==============================================================
4929 13:21:52.433098 Config description:
4930 13:21:52.443307 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4931 13:21:52.449510 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4932 13:21:52.453128 SELPH_MODE 0: By rank 1: By Phase
4933 13:21:52.459522 ==============================================================
4934 13:21:52.462754 GAT_TRACK_EN = 1
4935 13:21:52.466310 RX_GATING_MODE = 2
4936 13:21:52.469467 RX_GATING_TRACK_MODE = 2
4937 13:21:52.469572 SELPH_MODE = 1
4938 13:21:52.472913 PICG_EARLY_EN = 1
4939 13:21:52.476037 VALID_LAT_VALUE = 1
4940 13:21:52.483132 ==============================================================
4941 13:21:52.486125 Enter into Gating configuration >>>>
4942 13:21:52.489813 Exit from Gating configuration <<<<
4943 13:21:52.492562 Enter into DVFS_PRE_config >>>>>
4944 13:21:52.502895 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4945 13:21:52.505567 Exit from DVFS_PRE_config <<<<<
4946 13:21:52.509059 Enter into PICG configuration >>>>
4947 13:21:52.512564 Exit from PICG configuration <<<<
4948 13:21:52.515592 [RX_INPUT] configuration >>>>>
4949 13:21:52.518865 [RX_INPUT] configuration <<<<<
4950 13:21:52.522625 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4951 13:21:52.528735 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4952 13:21:52.535223 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4953 13:21:52.542139 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4954 13:21:52.548087 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4955 13:21:52.554669 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4956 13:21:52.557917 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4957 13:21:52.561296 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4958 13:21:52.564650 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4959 13:21:52.571443 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4960 13:21:52.574708 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4961 13:21:52.577803 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4962 13:21:52.582077 ===================================
4963 13:21:52.585445 LPDDR4 DRAM CONFIGURATION
4964 13:21:52.588140 ===================================
4965 13:21:52.590720 EX_ROW_EN[0] = 0x0
4966 13:21:52.590806 EX_ROW_EN[1] = 0x0
4967 13:21:52.594736 LP4Y_EN = 0x0
4968 13:21:52.594814 WORK_FSP = 0x0
4969 13:21:52.597220 WL = 0x3
4970 13:21:52.597316 RL = 0x3
4971 13:21:52.600832 BL = 0x2
4972 13:21:52.600901 RPST = 0x0
4973 13:21:52.604332 RD_PRE = 0x0
4974 13:21:52.604441 WR_PRE = 0x1
4975 13:21:52.607128 WR_PST = 0x0
4976 13:21:52.607232 DBI_WR = 0x0
4977 13:21:52.610989 DBI_RD = 0x0
4978 13:21:52.611100 OTF = 0x1
4979 13:21:52.614187 ===================================
4980 13:21:52.621170 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4981 13:21:52.624076 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4982 13:21:52.627172 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4983 13:21:52.630499 ===================================
4984 13:21:52.633580 LPDDR4 DRAM CONFIGURATION
4985 13:21:52.637431 ===================================
4986 13:21:52.640247 EX_ROW_EN[0] = 0x10
4987 13:21:52.640325 EX_ROW_EN[1] = 0x0
4988 13:21:52.643923 LP4Y_EN = 0x0
4989 13:21:52.644001 WORK_FSP = 0x0
4990 13:21:52.647102 WL = 0x3
4991 13:21:52.647204 RL = 0x3
4992 13:21:52.649942 BL = 0x2
4993 13:21:52.650046 RPST = 0x0
4994 13:21:52.653853 RD_PRE = 0x0
4995 13:21:52.653954 WR_PRE = 0x1
4996 13:21:52.656587 WR_PST = 0x0
4997 13:21:52.656664 DBI_WR = 0x0
4998 13:21:52.659815 DBI_RD = 0x0
4999 13:21:52.659928 OTF = 0x1
5000 13:21:52.663439 ===================================
5001 13:21:52.669632 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5002 13:21:52.674845 nWR fixed to 30
5003 13:21:52.678326 [ModeRegInit_LP4] CH0 RK0
5004 13:21:52.678432 [ModeRegInit_LP4] CH0 RK1
5005 13:21:52.681620 [ModeRegInit_LP4] CH1 RK0
5006 13:21:52.684443 [ModeRegInit_LP4] CH1 RK1
5007 13:21:52.684522 match AC timing 9
5008 13:21:52.691997 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5009 13:21:52.694543 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5010 13:21:52.698003 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5011 13:21:52.704511 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5012 13:21:52.708232 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5013 13:21:52.708333 ==
5014 13:21:52.711263 Dram Type= 6, Freq= 0, CH_0, rank 0
5015 13:21:52.714598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5016 13:21:52.714707 ==
5017 13:21:52.721078 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5018 13:21:52.727320 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5019 13:21:52.730610 [CA 0] Center 37 (7~68) winsize 62
5020 13:21:52.734036 [CA 1] Center 37 (7~68) winsize 62
5021 13:21:52.737492 [CA 2] Center 34 (4~64) winsize 61
5022 13:21:52.740635 [CA 3] Center 34 (3~65) winsize 63
5023 13:21:52.744196 [CA 4] Center 32 (2~63) winsize 62
5024 13:21:52.747625 [CA 5] Center 32 (2~63) winsize 62
5025 13:21:52.747743
5026 13:21:52.750454 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5027 13:21:52.750532
5028 13:21:52.753983 [CATrainingPosCal] consider 1 rank data
5029 13:21:52.757309 u2DelayCellTimex100 = 270/100 ps
5030 13:21:52.760205 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5031 13:21:52.763804 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5032 13:21:52.770704 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5033 13:21:52.773787 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5034 13:21:52.777498 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5035 13:21:52.780246 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5036 13:21:52.780360
5037 13:21:52.783160 CA PerBit enable=1, Macro0, CA PI delay=32
5038 13:21:52.783277
5039 13:21:52.786602 [CBTSetCACLKResult] CA Dly = 32
5040 13:21:52.786719 CS Dly: 5 (0~36)
5041 13:21:52.789790 ==
5042 13:21:52.793764 Dram Type= 6, Freq= 0, CH_0, rank 1
5043 13:21:52.796638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5044 13:21:52.796740 ==
5045 13:21:52.799933 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5046 13:21:52.806461 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5047 13:21:52.810016 [CA 0] Center 37 (7~68) winsize 62
5048 13:21:52.813858 [CA 1] Center 37 (7~68) winsize 62
5049 13:21:52.817056 [CA 2] Center 34 (4~65) winsize 62
5050 13:21:52.819926 [CA 3] Center 34 (4~65) winsize 62
5051 13:21:52.823013 [CA 4] Center 33 (3~64) winsize 62
5052 13:21:52.826285 [CA 5] Center 32 (2~63) winsize 62
5053 13:21:52.826382
5054 13:21:52.829419 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5055 13:21:52.829513
5056 13:21:52.835834 [CATrainingPosCal] consider 2 rank data
5057 13:21:52.835942 u2DelayCellTimex100 = 270/100 ps
5058 13:21:52.842977 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5059 13:21:52.846465 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5060 13:21:52.849088 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5061 13:21:52.853538 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5062 13:21:52.855753 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5063 13:21:52.859209 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5064 13:21:52.859308
5065 13:21:52.862717 CA PerBit enable=1, Macro0, CA PI delay=32
5066 13:21:52.862821
5067 13:21:52.865512 [CBTSetCACLKResult] CA Dly = 32
5068 13:21:52.868917 CS Dly: 6 (0~39)
5069 13:21:52.869013
5070 13:21:52.872362 ----->DramcWriteLeveling(PI) begin...
5071 13:21:52.872459 ==
5072 13:21:52.875833 Dram Type= 6, Freq= 0, CH_0, rank 0
5073 13:21:52.878689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5074 13:21:52.878783 ==
5075 13:21:52.882353 Write leveling (Byte 0): 30 => 30
5076 13:21:52.885548 Write leveling (Byte 1): 28 => 28
5077 13:21:52.888742 DramcWriteLeveling(PI) end<-----
5078 13:21:52.888841
5079 13:21:52.888935 ==
5080 13:21:52.892497 Dram Type= 6, Freq= 0, CH_0, rank 0
5081 13:21:52.896015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5082 13:21:52.898402 ==
5083 13:21:52.898499 [Gating] SW mode calibration
5084 13:21:52.908733 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5085 13:21:52.911707 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5086 13:21:52.915015 0 14 0 | B1->B0 | 2828 3434 | 0 0 | (1 1) (0 0)
5087 13:21:52.921267 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5088 13:21:52.924642 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5089 13:21:52.927924 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5090 13:21:52.934839 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5091 13:21:52.938965 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5092 13:21:52.941122 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5093 13:21:52.948100 0 14 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
5094 13:21:52.950904 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
5095 13:21:52.954701 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5096 13:21:52.961265 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5097 13:21:52.964291 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5098 13:21:52.967655 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5099 13:21:52.974191 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5100 13:21:52.978005 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5101 13:21:52.981219 0 15 28 | B1->B0 | 2323 3a39 | 0 1 | (0 0) (0 0)
5102 13:21:52.987219 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5103 13:21:52.990532 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5104 13:21:52.993751 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5105 13:21:53.000410 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5106 13:21:53.003862 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5107 13:21:53.007138 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5108 13:21:53.013474 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5109 13:21:53.017448 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5110 13:21:53.021046 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5111 13:21:53.026690 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5112 13:21:53.030097 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5113 13:21:53.033118 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 13:21:53.040066 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 13:21:53.043540 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 13:21:53.046470 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 13:21:53.053423 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 13:21:53.056160 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 13:21:53.059730 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 13:21:53.066358 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 13:21:53.069441 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 13:21:53.076652 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 13:21:53.079683 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 13:21:53.083245 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 13:21:53.089142 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5126 13:21:53.092335 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5127 13:21:53.096021 Total UI for P1: 0, mck2ui 16
5128 13:21:53.099005 best dqsien dly found for B0: ( 1, 2, 28)
5129 13:21:53.102342 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 13:21:53.105310 Total UI for P1: 0, mck2ui 16
5131 13:21:53.108972 best dqsien dly found for B1: ( 1, 3, 0)
5132 13:21:53.112034 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5133 13:21:53.115887 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5134 13:21:53.115974
5135 13:21:53.118939 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5136 13:21:53.125342 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5137 13:21:53.125424 [Gating] SW calibration Done
5138 13:21:53.125520 ==
5139 13:21:53.128434 Dram Type= 6, Freq= 0, CH_0, rank 0
5140 13:21:53.135064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5141 13:21:53.135168 ==
5142 13:21:53.135270 RX Vref Scan: 0
5143 13:21:53.135371
5144 13:21:53.138471 RX Vref 0 -> 0, step: 1
5145 13:21:53.138554
5146 13:21:53.142288 RX Delay -80 -> 252, step: 8
5147 13:21:53.145110 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5148 13:21:53.148108 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5149 13:21:53.151619 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5150 13:21:53.158036 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5151 13:21:53.161433 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5152 13:21:53.164660 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5153 13:21:53.167871 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5154 13:21:53.170965 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5155 13:21:53.174526 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5156 13:21:53.181683 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5157 13:21:53.184445 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5158 13:21:53.187643 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5159 13:21:53.191579 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5160 13:21:53.194240 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5161 13:21:53.201479 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5162 13:21:53.204141 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5163 13:21:53.204243 ==
5164 13:21:53.207940 Dram Type= 6, Freq= 0, CH_0, rank 0
5165 13:21:53.210918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5166 13:21:53.210994 ==
5167 13:21:53.211090 DQS Delay:
5168 13:21:53.214395 DQS0 = 0, DQS1 = 0
5169 13:21:53.214501 DQM Delay:
5170 13:21:53.217387 DQM0 = 101, DQM1 = 89
5171 13:21:53.217485 DQ Delay:
5172 13:21:53.221441 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5173 13:21:53.223828 DQ4 =103, DQ5 =91, DQ6 =111, DQ7 =111
5174 13:21:53.227204 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =83
5175 13:21:53.230587 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5176 13:21:53.230676
5177 13:21:53.230739
5178 13:21:53.230798 ==
5179 13:21:53.234039 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 13:21:53.240758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 13:21:53.240856 ==
5182 13:21:53.240951
5183 13:21:53.241016
5184 13:21:53.241073 TX Vref Scan disable
5185 13:21:53.243994 == TX Byte 0 ==
5186 13:21:53.247265 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5187 13:21:53.254250 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5188 13:21:53.254325 == TX Byte 1 ==
5189 13:21:53.257406 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5190 13:21:53.263664 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5191 13:21:53.263763 ==
5192 13:21:53.267751 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 13:21:53.270406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 13:21:53.270478 ==
5195 13:21:53.270561
5196 13:21:53.270648
5197 13:21:53.273531 TX Vref Scan disable
5198 13:21:53.277181 == TX Byte 0 ==
5199 13:21:53.280853 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5200 13:21:53.283698 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5201 13:21:53.287091 == TX Byte 1 ==
5202 13:21:53.290273 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5203 13:21:53.293763 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5204 13:21:53.293864
5205 13:21:53.293956 [DATLAT]
5206 13:21:53.297147 Freq=933, CH0 RK0
5207 13:21:53.297242
5208 13:21:53.297342 DATLAT Default: 0xd
5209 13:21:53.300411 0, 0xFFFF, sum = 0
5210 13:21:53.303612 1, 0xFFFF, sum = 0
5211 13:21:53.303717 2, 0xFFFF, sum = 0
5212 13:21:53.306473 3, 0xFFFF, sum = 0
5213 13:21:53.306582 4, 0xFFFF, sum = 0
5214 13:21:53.310449 5, 0xFFFF, sum = 0
5215 13:21:53.310550 6, 0xFFFF, sum = 0
5216 13:21:53.313767 7, 0xFFFF, sum = 0
5217 13:21:53.313868 8, 0xFFFF, sum = 0
5218 13:21:53.316681 9, 0xFFFF, sum = 0
5219 13:21:53.316788 10, 0x0, sum = 1
5220 13:21:53.320503 11, 0x0, sum = 2
5221 13:21:53.320579 12, 0x0, sum = 3
5222 13:21:53.323371 13, 0x0, sum = 4
5223 13:21:53.323473 best_step = 11
5224 13:21:53.323570
5225 13:21:53.323662 ==
5226 13:21:53.326823 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 13:21:53.329828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 13:21:53.333341 ==
5229 13:21:53.333439 RX Vref Scan: 1
5230 13:21:53.333527
5231 13:21:53.336388 RX Vref 0 -> 0, step: 1
5232 13:21:53.336457
5233 13:21:53.339383 RX Delay -61 -> 252, step: 4
5234 13:21:53.339483
5235 13:21:53.342665 Set Vref, RX VrefLevel [Byte0]: 50
5236 13:21:53.346641 [Byte1]: 58
5237 13:21:53.346739
5238 13:21:53.349437 Final RX Vref Byte 0 = 50 to rank0
5239 13:21:53.352580 Final RX Vref Byte 1 = 58 to rank0
5240 13:21:53.356162 Final RX Vref Byte 0 = 50 to rank1
5241 13:21:53.359292 Final RX Vref Byte 1 = 58 to rank1==
5242 13:21:53.362908 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 13:21:53.365989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 13:21:53.366063 ==
5245 13:21:53.369180 DQS Delay:
5246 13:21:53.369276 DQS0 = 0, DQS1 = 0
5247 13:21:53.369350 DQM Delay:
5248 13:21:53.372681 DQM0 = 98, DQM1 = 88
5249 13:21:53.372758 DQ Delay:
5250 13:21:53.375789 DQ0 =100, DQ1 =98, DQ2 =94, DQ3 =92
5251 13:21:53.379157 DQ4 =100, DQ5 =90, DQ6 =110, DQ7 =104
5252 13:21:53.382333 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =84
5253 13:21:53.385917 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =96
5254 13:21:53.386021
5255 13:21:53.386113
5256 13:21:53.395558 [DQSOSCAuto] RK0, (LSB)MR18= 0x1812, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5257 13:21:53.398795 CH0 RK0: MR19=505, MR18=1812
5258 13:21:53.405832 CH0_RK0: MR19=0x505, MR18=0x1812, DQSOSC=414, MR23=63, INC=63, DEC=42
5259 13:21:53.405933
5260 13:21:53.408791 ----->DramcWriteLeveling(PI) begin...
5261 13:21:53.408867 ==
5262 13:21:53.411819 Dram Type= 6, Freq= 0, CH_0, rank 1
5263 13:21:53.415685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 13:21:53.415791 ==
5265 13:21:53.418405 Write leveling (Byte 0): 30 => 30
5266 13:21:53.421643 Write leveling (Byte 1): 30 => 30
5267 13:21:53.425197 DramcWriteLeveling(PI) end<-----
5268 13:21:53.425271
5269 13:21:53.425333 ==
5270 13:21:53.428745 Dram Type= 6, Freq= 0, CH_0, rank 1
5271 13:21:53.431696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 13:21:53.431791 ==
5273 13:21:53.435263 [Gating] SW mode calibration
5274 13:21:53.441818 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5275 13:21:53.448141 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5276 13:21:53.451603 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5277 13:21:53.457960 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5278 13:21:53.461489 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5279 13:21:53.464533 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5280 13:21:53.468048 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5281 13:21:53.474407 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5282 13:21:53.477636 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5283 13:21:53.484160 0 14 28 | B1->B0 | 3434 2929 | 1 0 | (0 0) (0 0)
5284 13:21:53.487706 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
5285 13:21:53.490797 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5286 13:21:53.497479 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5287 13:21:53.501061 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5288 13:21:53.504016 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5289 13:21:53.510824 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5290 13:21:53.513597 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5291 13:21:53.517307 0 15 28 | B1->B0 | 2828 4444 | 0 0 | (0 0) (0 0)
5292 13:21:53.524483 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5293 13:21:53.526782 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5294 13:21:53.530506 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5295 13:21:53.536989 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5296 13:21:53.540447 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5297 13:21:53.543063 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5298 13:21:53.549969 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5299 13:21:53.553659 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5300 13:21:53.556675 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5301 13:21:53.563002 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5302 13:21:53.566288 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5303 13:21:53.569586 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5304 13:21:53.576436 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5305 13:21:53.579777 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 13:21:53.582421 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 13:21:53.589064 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 13:21:53.592621 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 13:21:53.596216 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 13:21:53.602660 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 13:21:53.605787 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 13:21:53.609255 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 13:21:53.615716 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 13:21:53.618731 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5315 13:21:53.621957 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5316 13:21:53.628660 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5317 13:21:53.628738 Total UI for P1: 0, mck2ui 16
5318 13:21:53.635100 best dqsien dly found for B0: ( 1, 2, 26)
5319 13:21:53.639419 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 13:21:53.641908 Total UI for P1: 0, mck2ui 16
5321 13:21:53.645069 best dqsien dly found for B1: ( 1, 3, 0)
5322 13:21:53.648215 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5323 13:21:53.651510 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5324 13:21:53.651609
5325 13:21:53.654955 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5326 13:21:53.658302 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5327 13:21:53.661990 [Gating] SW calibration Done
5328 13:21:53.662083 ==
5329 13:21:53.665315 Dram Type= 6, Freq= 0, CH_0, rank 1
5330 13:21:53.668187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5331 13:21:53.671445 ==
5332 13:21:53.671542 RX Vref Scan: 0
5333 13:21:53.671642
5334 13:21:53.675677 RX Vref 0 -> 0, step: 1
5335 13:21:53.675780
5336 13:21:53.678230 RX Delay -80 -> 252, step: 8
5337 13:21:53.681885 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5338 13:21:53.684700 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5339 13:21:53.688142 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5340 13:21:53.691819 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5341 13:21:53.694884 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5342 13:21:53.701102 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5343 13:21:53.704408 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5344 13:21:53.707575 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5345 13:21:53.710775 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5346 13:21:53.714857 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5347 13:21:53.720565 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5348 13:21:53.724159 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5349 13:21:53.727517 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5350 13:21:53.731107 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5351 13:21:53.734127 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5352 13:21:53.740572 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5353 13:21:53.740647 ==
5354 13:21:53.744087 Dram Type= 6, Freq= 0, CH_0, rank 1
5355 13:21:53.746922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5356 13:21:53.747029 ==
5357 13:21:53.747122 DQS Delay:
5358 13:21:53.751084 DQS0 = 0, DQS1 = 0
5359 13:21:53.751204 DQM Delay:
5360 13:21:53.753442 DQM0 = 97, DQM1 = 90
5361 13:21:53.753514 DQ Delay:
5362 13:21:53.756577 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =95
5363 13:21:53.760200 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5364 13:21:53.763923 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5365 13:21:53.766785 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5366 13:21:53.766878
5367 13:21:53.766978
5368 13:21:53.767074 ==
5369 13:21:53.770274 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 13:21:53.773621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 13:21:53.776586 ==
5372 13:21:53.776685
5373 13:21:53.776783
5374 13:21:53.776878 TX Vref Scan disable
5375 13:21:53.780096 == TX Byte 0 ==
5376 13:21:53.783936 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5377 13:21:53.786582 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5378 13:21:53.789567 == TX Byte 1 ==
5379 13:21:53.792927 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5380 13:21:53.796110 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5381 13:21:53.799493 ==
5382 13:21:53.799593 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 13:21:53.806437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 13:21:53.806536 ==
5385 13:21:53.806663
5386 13:21:53.806759
5387 13:21:53.809794 TX Vref Scan disable
5388 13:21:53.809892 == TX Byte 0 ==
5389 13:21:53.815926 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5390 13:21:53.819550 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5391 13:21:53.819650 == TX Byte 1 ==
5392 13:21:53.825954 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5393 13:21:53.829024 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5394 13:21:53.829100
5395 13:21:53.829204 [DATLAT]
5396 13:21:53.832629 Freq=933, CH0 RK1
5397 13:21:53.832703
5398 13:21:53.832781 DATLAT Default: 0xb
5399 13:21:53.836003 0, 0xFFFF, sum = 0
5400 13:21:53.836081 1, 0xFFFF, sum = 0
5401 13:21:53.839042 2, 0xFFFF, sum = 0
5402 13:21:53.839144 3, 0xFFFF, sum = 0
5403 13:21:53.843119 4, 0xFFFF, sum = 0
5404 13:21:53.845563 5, 0xFFFF, sum = 0
5405 13:21:53.845638 6, 0xFFFF, sum = 0
5406 13:21:53.849274 7, 0xFFFF, sum = 0
5407 13:21:53.849353 8, 0xFFFF, sum = 0
5408 13:21:53.852232 9, 0xFFFF, sum = 0
5409 13:21:53.852308 10, 0x0, sum = 1
5410 13:21:53.855978 11, 0x0, sum = 2
5411 13:21:53.856071 12, 0x0, sum = 3
5412 13:21:53.858619 13, 0x0, sum = 4
5413 13:21:53.858718 best_step = 11
5414 13:21:53.858814
5415 13:21:53.858911 ==
5416 13:21:53.861985 Dram Type= 6, Freq= 0, CH_0, rank 1
5417 13:21:53.865271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5418 13:21:53.865370 ==
5419 13:21:53.868877 RX Vref Scan: 0
5420 13:21:53.868987
5421 13:21:53.872050 RX Vref 0 -> 0, step: 1
5422 13:21:53.872126
5423 13:21:53.872207 RX Delay -53 -> 252, step: 4
5424 13:21:53.879690 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5425 13:21:53.883036 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5426 13:21:53.886264 iDelay=195, Bit 2, Center 92 (-1 ~ 186) 188
5427 13:21:53.890600 iDelay=195, Bit 3, Center 94 (7 ~ 182) 176
5428 13:21:53.893228 iDelay=195, Bit 4, Center 102 (11 ~ 194) 184
5429 13:21:53.899608 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5430 13:21:53.902883 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5431 13:21:53.906825 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5432 13:21:53.909170 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5433 13:21:53.912467 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5434 13:21:53.916119 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5435 13:21:53.922811 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5436 13:21:53.925874 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5437 13:21:53.929270 iDelay=195, Bit 13, Center 96 (7 ~ 186) 180
5438 13:21:53.932214 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5439 13:21:53.936246 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5440 13:21:53.939225 ==
5441 13:21:53.939343 Dram Type= 6, Freq= 0, CH_0, rank 1
5442 13:21:53.945547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5443 13:21:53.945651 ==
5444 13:21:53.945743 DQS Delay:
5445 13:21:53.949301 DQS0 = 0, DQS1 = 0
5446 13:21:53.949370 DQM Delay:
5447 13:21:53.952077 DQM0 = 97, DQM1 = 89
5448 13:21:53.952148 DQ Delay:
5449 13:21:53.955845 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5450 13:21:53.958999 DQ4 =102, DQ5 =86, DQ6 =106, DQ7 =106
5451 13:21:53.962059 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =84
5452 13:21:53.965542 DQ12 =94, DQ13 =96, DQ14 =98, DQ15 =96
5453 13:21:53.965610
5454 13:21:53.965675
5455 13:21:53.972022 [DQSOSCAuto] RK1, (LSB)MR18= 0x1512, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5456 13:21:53.975208 CH0 RK1: MR19=505, MR18=1512
5457 13:21:53.981648 CH0_RK1: MR19=0x505, MR18=0x1512, DQSOSC=415, MR23=63, INC=62, DEC=41
5458 13:21:53.985197 [RxdqsGatingPostProcess] freq 933
5459 13:21:53.992037 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5460 13:21:53.995267 best DQS0 dly(2T, 0.5T) = (0, 10)
5461 13:21:53.998261 best DQS1 dly(2T, 0.5T) = (0, 11)
5462 13:21:54.001287 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5463 13:21:54.005219 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5464 13:21:54.005324 best DQS0 dly(2T, 0.5T) = (0, 10)
5465 13:21:54.008406 best DQS1 dly(2T, 0.5T) = (0, 11)
5466 13:21:54.011515 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5467 13:21:54.014791 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5468 13:21:54.018391 Pre-setting of DQS Precalculation
5469 13:21:54.024692 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5470 13:21:54.024800 ==
5471 13:21:54.028616 Dram Type= 6, Freq= 0, CH_1, rank 0
5472 13:21:54.031075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5473 13:21:54.031172 ==
5474 13:21:54.037749 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5475 13:21:54.044765 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5476 13:21:54.047793 [CA 0] Center 36 (6~67) winsize 62
5477 13:21:54.051119 [CA 1] Center 36 (6~67) winsize 62
5478 13:21:54.054756 [CA 2] Center 34 (4~65) winsize 62
5479 13:21:54.057970 [CA 3] Center 34 (3~65) winsize 63
5480 13:21:54.060812 [CA 4] Center 34 (4~65) winsize 62
5481 13:21:54.064209 [CA 5] Center 33 (3~64) winsize 62
5482 13:21:54.064282
5483 13:21:54.067815 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5484 13:21:54.067938
5485 13:21:54.070885 [CATrainingPosCal] consider 1 rank data
5486 13:21:54.074243 u2DelayCellTimex100 = 270/100 ps
5487 13:21:54.077483 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5488 13:21:54.080828 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5489 13:21:54.083816 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5490 13:21:54.087018 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5491 13:21:54.090252 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5492 13:21:54.093861 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5493 13:21:54.093960
5494 13:21:54.100690 CA PerBit enable=1, Macro0, CA PI delay=33
5495 13:21:54.100797
5496 13:21:54.103619 [CBTSetCACLKResult] CA Dly = 33
5497 13:21:54.103714 CS Dly: 5 (0~36)
5498 13:21:54.103805 ==
5499 13:21:54.107065 Dram Type= 6, Freq= 0, CH_1, rank 1
5500 13:21:54.110507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5501 13:21:54.110603 ==
5502 13:21:54.116747 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5503 13:21:54.123741 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5504 13:21:54.126871 [CA 0] Center 36 (6~67) winsize 62
5505 13:21:54.130546 [CA 1] Center 36 (6~67) winsize 62
5506 13:21:54.133314 [CA 2] Center 34 (4~65) winsize 62
5507 13:21:54.136580 [CA 3] Center 33 (3~64) winsize 62
5508 13:21:54.140055 [CA 4] Center 34 (3~65) winsize 63
5509 13:21:54.143275 [CA 5] Center 33 (3~64) winsize 62
5510 13:21:54.143375
5511 13:21:54.146710 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5512 13:21:54.146814
5513 13:21:54.150382 [CATrainingPosCal] consider 2 rank data
5514 13:21:54.153112 u2DelayCellTimex100 = 270/100 ps
5515 13:21:54.156668 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5516 13:21:54.159464 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5517 13:21:54.163440 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5518 13:21:54.166969 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5519 13:21:54.172941 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5520 13:21:54.176219 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5521 13:21:54.176319
5522 13:21:54.179472 CA PerBit enable=1, Macro0, CA PI delay=33
5523 13:21:54.179570
5524 13:21:54.182767 [CBTSetCACLKResult] CA Dly = 33
5525 13:21:54.182860 CS Dly: 6 (0~38)
5526 13:21:54.182949
5527 13:21:54.186152 ----->DramcWriteLeveling(PI) begin...
5528 13:21:54.186248 ==
5529 13:21:54.189317 Dram Type= 6, Freq= 0, CH_1, rank 0
5530 13:21:54.196042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5531 13:21:54.196121 ==
5532 13:21:54.199487 Write leveling (Byte 0): 27 => 27
5533 13:21:54.202426 Write leveling (Byte 1): 26 => 26
5534 13:21:54.202524 DramcWriteLeveling(PI) end<-----
5535 13:21:54.205962
5536 13:21:54.206056 ==
5537 13:21:54.209541 Dram Type= 6, Freq= 0, CH_1, rank 0
5538 13:21:54.212450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 13:21:54.212553 ==
5540 13:21:54.215845 [Gating] SW mode calibration
5541 13:21:54.222307 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5542 13:21:54.225742 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5543 13:21:54.232591 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5544 13:21:54.235780 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5545 13:21:54.239149 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5546 13:21:54.245722 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5547 13:21:54.248806 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5548 13:21:54.252153 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 13:21:54.258676 0 14 24 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
5550 13:21:54.261788 0 14 28 | B1->B0 | 2d2d 2525 | 0 0 | (0 1) (0 1)
5551 13:21:54.265241 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5552 13:21:54.271646 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5553 13:21:54.274738 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5554 13:21:54.278215 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5555 13:21:54.285242 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5556 13:21:54.288337 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 13:21:54.291587 0 15 24 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
5558 13:21:54.298024 0 15 28 | B1->B0 | 3939 4040 | 1 0 | (0 0) (0 0)
5559 13:21:54.301250 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5560 13:21:54.304464 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5561 13:21:54.311312 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5562 13:21:54.314862 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5563 13:21:54.318068 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 13:21:54.324616 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 13:21:54.327790 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 13:21:54.331097 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5567 13:21:54.337469 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5568 13:21:54.341042 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 13:21:54.344187 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 13:21:54.350665 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 13:21:54.354079 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 13:21:54.357675 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 13:21:54.363821 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 13:21:54.367791 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 13:21:54.371166 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 13:21:54.377800 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 13:21:54.380374 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 13:21:54.386930 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 13:21:54.390346 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 13:21:54.393823 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 13:21:54.400412 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5582 13:21:54.403334 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5583 13:21:54.406710 Total UI for P1: 0, mck2ui 16
5584 13:21:54.410056 best dqsien dly found for B1: ( 1, 2, 24)
5585 13:21:54.413381 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 13:21:54.416783 Total UI for P1: 0, mck2ui 16
5587 13:21:54.419660 best dqsien dly found for B0: ( 1, 2, 26)
5588 13:21:54.423368 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5589 13:21:54.426724 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5590 13:21:54.426809
5591 13:21:54.429533 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5592 13:21:54.436471 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5593 13:21:54.436550 [Gating] SW calibration Done
5594 13:21:54.440159 ==
5595 13:21:54.442850 Dram Type= 6, Freq= 0, CH_1, rank 0
5596 13:21:54.446097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5597 13:21:54.446199 ==
5598 13:21:54.446289 RX Vref Scan: 0
5599 13:21:54.446378
5600 13:21:54.449568 RX Vref 0 -> 0, step: 1
5601 13:21:54.449704
5602 13:21:54.452790 RX Delay -80 -> 252, step: 8
5603 13:21:54.455873 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5604 13:21:54.459129 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5605 13:21:54.462343 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5606 13:21:54.468816 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5607 13:21:54.472845 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5608 13:21:54.475476 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5609 13:21:54.479000 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5610 13:21:54.482257 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5611 13:21:54.486361 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5612 13:21:54.492057 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5613 13:21:54.495900 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5614 13:21:54.499047 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5615 13:21:54.501777 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5616 13:21:54.505241 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5617 13:21:54.512533 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5618 13:21:54.515053 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5619 13:21:54.515148 ==
5620 13:21:54.518616 Dram Type= 6, Freq= 0, CH_1, rank 0
5621 13:21:54.521966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5622 13:21:54.522049 ==
5623 13:21:54.525024 DQS Delay:
5624 13:21:54.525103 DQS0 = 0, DQS1 = 0
5625 13:21:54.525171 DQM Delay:
5626 13:21:54.528500 DQM0 = 99, DQM1 = 95
5627 13:21:54.528569 DQ Delay:
5628 13:21:54.531868 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5629 13:21:54.535016 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5630 13:21:54.538170 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5631 13:21:54.541617 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5632 13:21:54.541759
5633 13:21:54.541841
5634 13:21:54.545054 ==
5635 13:21:54.549303 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 13:21:54.551689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 13:21:54.551789 ==
5638 13:21:54.551883
5639 13:21:54.551959
5640 13:21:54.555295 TX Vref Scan disable
5641 13:21:54.555391 == TX Byte 0 ==
5642 13:21:54.561281 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5643 13:21:54.564436 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5644 13:21:54.564515 == TX Byte 1 ==
5645 13:21:54.570984 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5646 13:21:54.574654 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5647 13:21:54.574755 ==
5648 13:21:54.578385 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 13:21:54.581026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 13:21:54.581144 ==
5651 13:21:54.581235
5652 13:21:54.581324
5653 13:21:54.584355 TX Vref Scan disable
5654 13:21:54.587601 == TX Byte 0 ==
5655 13:21:54.591160 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5656 13:21:54.593952 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5657 13:21:54.597691 == TX Byte 1 ==
5658 13:21:54.601146 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5659 13:21:54.603978 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5660 13:21:54.604136
5661 13:21:54.607221 [DATLAT]
5662 13:21:54.607294 Freq=933, CH1 RK0
5663 13:21:54.607356
5664 13:21:54.610509 DATLAT Default: 0xd
5665 13:21:54.610608 0, 0xFFFF, sum = 0
5666 13:21:54.613864 1, 0xFFFF, sum = 0
5667 13:21:54.613971 2, 0xFFFF, sum = 0
5668 13:21:54.617411 3, 0xFFFF, sum = 0
5669 13:21:54.617509 4, 0xFFFF, sum = 0
5670 13:21:54.620740 5, 0xFFFF, sum = 0
5671 13:21:54.620845 6, 0xFFFF, sum = 0
5672 13:21:54.624121 7, 0xFFFF, sum = 0
5673 13:21:54.627157 8, 0xFFFF, sum = 0
5674 13:21:54.627262 9, 0xFFFF, sum = 0
5675 13:21:54.630337 10, 0x0, sum = 1
5676 13:21:54.630446 11, 0x0, sum = 2
5677 13:21:54.630540 12, 0x0, sum = 3
5678 13:21:54.633579 13, 0x0, sum = 4
5679 13:21:54.633678 best_step = 11
5680 13:21:54.633767
5681 13:21:54.637272 ==
5682 13:21:54.637368 Dram Type= 6, Freq= 0, CH_1, rank 0
5683 13:21:54.644236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5684 13:21:54.644310 ==
5685 13:21:54.644373 RX Vref Scan: 1
5686 13:21:54.644434
5687 13:21:54.646979 RX Vref 0 -> 0, step: 1
5688 13:21:54.647089
5689 13:21:54.650118 RX Delay -53 -> 252, step: 4
5690 13:21:54.650212
5691 13:21:54.653327 Set Vref, RX VrefLevel [Byte0]: 52
5692 13:21:54.656637 [Byte1]: 53
5693 13:21:54.656707
5694 13:21:54.660056 Final RX Vref Byte 0 = 52 to rank0
5695 13:21:54.664235 Final RX Vref Byte 1 = 53 to rank0
5696 13:21:54.666833 Final RX Vref Byte 0 = 52 to rank1
5697 13:21:54.670332 Final RX Vref Byte 1 = 53 to rank1==
5698 13:21:54.673096 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 13:21:54.676776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 13:21:54.680587 ==
5701 13:21:54.680659 DQS Delay:
5702 13:21:54.680720 DQS0 = 0, DQS1 = 0
5703 13:21:54.683137 DQM Delay:
5704 13:21:54.683208 DQM0 = 98, DQM1 = 94
5705 13:21:54.687053 DQ Delay:
5706 13:21:54.690035 DQ0 =104, DQ1 =92, DQ2 =88, DQ3 =100
5707 13:21:54.692947 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5708 13:21:54.696632 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5709 13:21:54.699682 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5710 13:21:54.699777
5711 13:21:54.699867
5712 13:21:54.706322 [DQSOSCAuto] RK0, (LSB)MR18= 0x515, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 420 ps
5713 13:21:54.709614 CH1 RK0: MR19=505, MR18=515
5714 13:21:54.716550 CH1_RK0: MR19=0x505, MR18=0x515, DQSOSC=415, MR23=63, INC=62, DEC=41
5715 13:21:54.716624
5716 13:21:54.719280 ----->DramcWriteLeveling(PI) begin...
5717 13:21:54.719384 ==
5718 13:21:54.722817 Dram Type= 6, Freq= 0, CH_1, rank 1
5719 13:21:54.726112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 13:21:54.726187 ==
5721 13:21:54.729390 Write leveling (Byte 0): 26 => 26
5722 13:21:54.732412 Write leveling (Byte 1): 26 => 26
5723 13:21:54.736060 DramcWriteLeveling(PI) end<-----
5724 13:21:54.736151
5725 13:21:54.736218 ==
5726 13:21:54.739387 Dram Type= 6, Freq= 0, CH_1, rank 1
5727 13:21:54.742835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 13:21:54.745453 ==
5729 13:21:54.745562 [Gating] SW mode calibration
5730 13:21:54.752151 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5731 13:21:54.758739 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5732 13:21:54.762511 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5733 13:21:54.768489 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5734 13:21:54.771783 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5735 13:21:54.775469 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5736 13:21:54.781677 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5737 13:21:54.786320 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5738 13:21:54.788222 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5739 13:21:54.794964 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5740 13:21:54.798654 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5741 13:21:54.801678 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5742 13:21:54.807922 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5743 13:21:54.811281 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5744 13:21:54.814634 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5745 13:21:54.821566 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5746 13:21:54.824908 0 15 24 | B1->B0 | 2626 2f2f | 0 0 | (0 0) (0 0)
5747 13:21:54.828092 0 15 28 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
5748 13:21:54.834465 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5749 13:21:54.838222 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5750 13:21:54.841154 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5751 13:21:54.848246 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5752 13:21:54.851362 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5753 13:21:54.854252 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5754 13:21:54.860909 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5755 13:21:54.864096 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5756 13:21:54.867526 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5757 13:21:54.874326 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5758 13:21:54.877213 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5759 13:21:54.880449 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 13:21:54.887097 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 13:21:54.890488 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 13:21:54.894356 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 13:21:54.900607 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 13:21:54.903840 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 13:21:54.907600 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 13:21:54.913648 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 13:21:54.916982 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 13:21:54.920245 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 13:21:54.927171 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 13:21:54.930217 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5771 13:21:54.932991 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5772 13:21:54.936598 Total UI for P1: 0, mck2ui 16
5773 13:21:54.939767 best dqsien dly found for B0: ( 1, 2, 24)
5774 13:21:54.946315 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 13:21:54.949587 Total UI for P1: 0, mck2ui 16
5776 13:21:54.953214 best dqsien dly found for B1: ( 1, 2, 28)
5777 13:21:54.956676 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5778 13:21:54.959283 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5779 13:21:54.959389
5780 13:21:54.963248 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5781 13:21:54.966017 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5782 13:21:54.969663 [Gating] SW calibration Done
5783 13:21:54.969743 ==
5784 13:21:54.973087 Dram Type= 6, Freq= 0, CH_1, rank 1
5785 13:21:54.975816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5786 13:21:54.975943 ==
5787 13:21:54.979450 RX Vref Scan: 0
5788 13:21:54.979574
5789 13:21:54.982724 RX Vref 0 -> 0, step: 1
5790 13:21:54.982803
5791 13:21:54.982867 RX Delay -80 -> 252, step: 8
5792 13:21:54.989139 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5793 13:21:54.992465 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5794 13:21:54.996056 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5795 13:21:54.999415 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5796 13:21:55.003017 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5797 13:21:55.009303 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5798 13:21:55.012448 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5799 13:21:55.016346 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5800 13:21:55.018904 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5801 13:21:55.022702 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5802 13:21:55.026091 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5803 13:21:55.032066 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5804 13:21:55.035354 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5805 13:21:55.038479 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5806 13:21:55.042182 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5807 13:21:55.045410 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5808 13:21:55.045490 ==
5809 13:21:55.048631 Dram Type= 6, Freq= 0, CH_1, rank 1
5810 13:21:55.055030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 13:21:55.055113 ==
5812 13:21:55.055179 DQS Delay:
5813 13:21:55.058599 DQS0 = 0, DQS1 = 0
5814 13:21:55.058748 DQM Delay:
5815 13:21:55.061647 DQM0 = 97, DQM1 = 93
5816 13:21:55.061727 DQ Delay:
5817 13:21:55.065264 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5818 13:21:55.068404 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5819 13:21:55.071840 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5820 13:21:55.075198 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =103
5821 13:21:55.075322
5822 13:21:55.075385
5823 13:21:55.075444 ==
5824 13:21:55.078543 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 13:21:55.081687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 13:21:55.081794 ==
5827 13:21:55.081901
5828 13:21:55.084891
5829 13:21:55.084970 TX Vref Scan disable
5830 13:21:55.088423 == TX Byte 0 ==
5831 13:21:55.091651 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5832 13:21:55.094788 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5833 13:21:55.097960 == TX Byte 1 ==
5834 13:21:55.101527 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5835 13:21:55.104605 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5836 13:21:55.104685 ==
5837 13:21:55.107827 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 13:21:55.114348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 13:21:55.114452 ==
5840 13:21:55.114530
5841 13:21:55.114589
5842 13:21:55.117503 TX Vref Scan disable
5843 13:21:55.117583 == TX Byte 0 ==
5844 13:21:55.124245 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5845 13:21:55.127458 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5846 13:21:55.127537 == TX Byte 1 ==
5847 13:21:55.134717 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5848 13:21:55.137503 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5849 13:21:55.137579
5850 13:21:55.137640 [DATLAT]
5851 13:21:55.140562 Freq=933, CH1 RK1
5852 13:21:55.140629
5853 13:21:55.140690 DATLAT Default: 0xb
5854 13:21:55.143736 0, 0xFFFF, sum = 0
5855 13:21:55.143809 1, 0xFFFF, sum = 0
5856 13:21:55.147818 2, 0xFFFF, sum = 0
5857 13:21:55.147885 3, 0xFFFF, sum = 0
5858 13:21:55.150568 4, 0xFFFF, sum = 0
5859 13:21:55.153570 5, 0xFFFF, sum = 0
5860 13:21:55.153641 6, 0xFFFF, sum = 0
5861 13:21:55.156750 7, 0xFFFF, sum = 0
5862 13:21:55.156820 8, 0xFFFF, sum = 0
5863 13:21:55.160444 9, 0xFFFF, sum = 0
5864 13:21:55.160530 10, 0x0, sum = 1
5865 13:21:55.163583 11, 0x0, sum = 2
5866 13:21:55.163663 12, 0x0, sum = 3
5867 13:21:55.166778 13, 0x0, sum = 4
5868 13:21:55.166859 best_step = 11
5869 13:21:55.166924
5870 13:21:55.166981 ==
5871 13:21:55.170521 Dram Type= 6, Freq= 0, CH_1, rank 1
5872 13:21:55.173267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5873 13:21:55.173338 ==
5874 13:21:55.176656 RX Vref Scan: 0
5875 13:21:55.176748
5876 13:21:55.179994 RX Vref 0 -> 0, step: 1
5877 13:21:55.180066
5878 13:21:55.180132 RX Delay -61 -> 252, step: 4
5879 13:21:55.188690 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5880 13:21:55.192048 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5881 13:21:55.194932 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5882 13:21:55.197890 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5883 13:21:55.201190 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5884 13:21:55.207454 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5885 13:21:55.211284 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5886 13:21:55.214456 iDelay=199, Bit 7, Center 96 (3 ~ 190) 188
5887 13:21:55.217910 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5888 13:21:55.221045 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5889 13:21:55.224553 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5890 13:21:55.231548 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5891 13:21:55.234351 iDelay=199, Bit 12, Center 98 (7 ~ 190) 184
5892 13:21:55.237438 iDelay=199, Bit 13, Center 102 (11 ~ 194) 184
5893 13:21:55.240849 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5894 13:21:55.244267 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5895 13:21:55.247667 ==
5896 13:21:55.247747 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 13:21:55.254690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 13:21:55.254765 ==
5899 13:21:55.254826 DQS Delay:
5900 13:21:55.257137 DQS0 = 0, DQS1 = 0
5901 13:21:55.257207 DQM Delay:
5902 13:21:55.260505 DQM0 = 97, DQM1 = 92
5903 13:21:55.260576 DQ Delay:
5904 13:21:55.263901 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =94
5905 13:21:55.266809 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =96
5906 13:21:55.270649 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5907 13:21:55.274025 DQ12 =98, DQ13 =102, DQ14 =96, DQ15 =102
5908 13:21:55.274097
5909 13:21:55.274158
5910 13:21:55.280507 [DQSOSCAuto] RK1, (LSB)MR18= 0xa20, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5911 13:21:55.283391 CH1 RK1: MR19=505, MR18=A20
5912 13:21:55.290045 CH1_RK1: MR19=0x505, MR18=0xA20, DQSOSC=411, MR23=63, INC=64, DEC=42
5913 13:21:55.293132 [RxdqsGatingPostProcess] freq 933
5914 13:21:55.299582 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5915 13:21:55.303727 best DQS0 dly(2T, 0.5T) = (0, 10)
5916 13:21:55.306509 best DQS1 dly(2T, 0.5T) = (0, 10)
5917 13:21:55.309553 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5918 13:21:55.312713 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5919 13:21:55.316255 best DQS0 dly(2T, 0.5T) = (0, 10)
5920 13:21:55.316335 best DQS1 dly(2T, 0.5T) = (0, 10)
5921 13:21:55.319452 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5922 13:21:55.323042 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5923 13:21:55.326388 Pre-setting of DQS Precalculation
5924 13:21:55.332464 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5925 13:21:55.339611 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5926 13:21:55.345967 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5927 13:21:55.346046
5928 13:21:55.346118
5929 13:21:55.348921 [Calibration Summary] 1866 Mbps
5930 13:21:55.352572 CH 0, Rank 0
5931 13:21:55.352651 SW Impedance : PASS
5932 13:21:55.356172 DUTY Scan : NO K
5933 13:21:55.356246 ZQ Calibration : PASS
5934 13:21:55.359622 Jitter Meter : NO K
5935 13:21:55.362909 CBT Training : PASS
5936 13:21:55.362997 Write leveling : PASS
5937 13:21:55.366271 RX DQS gating : PASS
5938 13:21:55.368590 RX DQ/DQS(RDDQC) : PASS
5939 13:21:55.368665 TX DQ/DQS : PASS
5940 13:21:55.372237 RX DATLAT : PASS
5941 13:21:55.375290 RX DQ/DQS(Engine): PASS
5942 13:21:55.375370 TX OE : NO K
5943 13:21:55.378601 All Pass.
5944 13:21:55.378676
5945 13:21:55.378756 CH 0, Rank 1
5946 13:21:55.382316 SW Impedance : PASS
5947 13:21:55.382395 DUTY Scan : NO K
5948 13:21:55.385492 ZQ Calibration : PASS
5949 13:21:55.388830 Jitter Meter : NO K
5950 13:21:55.388904 CBT Training : PASS
5951 13:21:55.392062 Write leveling : PASS
5952 13:21:55.395315 RX DQS gating : PASS
5953 13:21:55.395395 RX DQ/DQS(RDDQC) : PASS
5954 13:21:55.398164 TX DQ/DQS : PASS
5955 13:21:55.401502 RX DATLAT : PASS
5956 13:21:55.401577 RX DQ/DQS(Engine): PASS
5957 13:21:55.404731 TX OE : NO K
5958 13:21:55.404804 All Pass.
5959 13:21:55.404887
5960 13:21:55.408257 CH 1, Rank 0
5961 13:21:55.408349 SW Impedance : PASS
5962 13:21:55.411828 DUTY Scan : NO K
5963 13:21:55.414629 ZQ Calibration : PASS
5964 13:21:55.414708 Jitter Meter : NO K
5965 13:21:55.418154 CBT Training : PASS
5966 13:21:55.421332 Write leveling : PASS
5967 13:21:55.421410 RX DQS gating : PASS
5968 13:21:55.424604 RX DQ/DQS(RDDQC) : PASS
5969 13:21:55.428347 TX DQ/DQS : PASS
5970 13:21:55.428430 RX DATLAT : PASS
5971 13:21:55.431429 RX DQ/DQS(Engine): PASS
5972 13:21:55.431529 TX OE : NO K
5973 13:21:55.434513 All Pass.
5974 13:21:55.434584
5975 13:21:55.434643 CH 1, Rank 1
5976 13:21:55.437700 SW Impedance : PASS
5977 13:21:55.441207 DUTY Scan : NO K
5978 13:21:55.441304 ZQ Calibration : PASS
5979 13:21:55.444249 Jitter Meter : NO K
5980 13:21:55.444342 CBT Training : PASS
5981 13:21:55.448116 Write leveling : PASS
5982 13:21:55.451353 RX DQS gating : PASS
5983 13:21:55.451450 RX DQ/DQS(RDDQC) : PASS
5984 13:21:55.455188 TX DQ/DQS : PASS
5985 13:21:55.457741 RX DATLAT : PASS
5986 13:21:55.457820 RX DQ/DQS(Engine): PASS
5987 13:21:55.460946 TX OE : NO K
5988 13:21:55.461026 All Pass.
5989 13:21:55.461089
5990 13:21:55.464568 DramC Write-DBI off
5991 13:21:55.467934 PER_BANK_REFRESH: Hybrid Mode
5992 13:21:55.468028 TX_TRACKING: ON
5993 13:21:55.477599 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5994 13:21:55.481050 [FAST_K] Save calibration result to emmc
5995 13:21:55.483834 dramc_set_vcore_voltage set vcore to 650000
5996 13:21:55.487773 Read voltage for 400, 6
5997 13:21:55.487882 Vio18 = 0
5998 13:21:55.490494 Vcore = 650000
5999 13:21:55.490567 Vdram = 0
6000 13:21:55.490627 Vddq = 0
6001 13:21:55.490684 Vmddr = 0
6002 13:21:55.497262 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6003 13:21:55.504576 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6004 13:21:55.504652 MEM_TYPE=3, freq_sel=20
6005 13:21:55.507453 sv_algorithm_assistance_LP4_800
6006 13:21:55.510490 ============ PULL DRAM RESETB DOWN ============
6007 13:21:55.516660 ========== PULL DRAM RESETB DOWN end =========
6008 13:21:55.520103 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6009 13:21:55.523986 ===================================
6010 13:21:55.526488 LPDDR4 DRAM CONFIGURATION
6011 13:21:55.529725 ===================================
6012 13:21:55.529797 EX_ROW_EN[0] = 0x0
6013 13:21:55.532958 EX_ROW_EN[1] = 0x0
6014 13:21:55.536437 LP4Y_EN = 0x0
6015 13:21:55.536513 WORK_FSP = 0x0
6016 13:21:55.539717 WL = 0x2
6017 13:21:55.539813 RL = 0x2
6018 13:21:55.543629 BL = 0x2
6019 13:21:55.543707 RPST = 0x0
6020 13:21:55.546385 RD_PRE = 0x0
6021 13:21:55.546473 WR_PRE = 0x1
6022 13:21:55.549497 WR_PST = 0x0
6023 13:21:55.549568 DBI_WR = 0x0
6024 13:21:55.552794 DBI_RD = 0x0
6025 13:21:55.552895 OTF = 0x1
6026 13:21:55.556586 ===================================
6027 13:21:55.559698 ===================================
6028 13:21:55.562909 ANA top config
6029 13:21:55.566285 ===================================
6030 13:21:55.566383 DLL_ASYNC_EN = 0
6031 13:21:55.569455 ALL_SLAVE_EN = 1
6032 13:21:55.572785 NEW_RANK_MODE = 1
6033 13:21:55.575817 DLL_IDLE_MODE = 1
6034 13:21:55.579467 LP45_APHY_COMB_EN = 1
6035 13:21:55.579564 TX_ODT_DIS = 1
6036 13:21:55.583407 NEW_8X_MODE = 1
6037 13:21:55.586427 ===================================
6038 13:21:55.589004 ===================================
6039 13:21:55.592511 data_rate = 800
6040 13:21:55.595862 CKR = 1
6041 13:21:55.599216 DQ_P2S_RATIO = 4
6042 13:21:55.602568 ===================================
6043 13:21:55.605649 CA_P2S_RATIO = 4
6044 13:21:55.605750 DQ_CA_OPEN = 0
6045 13:21:55.608873 DQ_SEMI_OPEN = 1
6046 13:21:55.612405 CA_SEMI_OPEN = 1
6047 13:21:55.615811 CA_FULL_RATE = 0
6048 13:21:55.618782 DQ_CKDIV4_EN = 0
6049 13:21:55.621831 CA_CKDIV4_EN = 1
6050 13:21:55.621941 CA_PREDIV_EN = 0
6051 13:21:55.625645 PH8_DLY = 0
6052 13:21:55.628739 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6053 13:21:55.632327 DQ_AAMCK_DIV = 0
6054 13:21:55.635289 CA_AAMCK_DIV = 0
6055 13:21:55.638795 CA_ADMCK_DIV = 4
6056 13:21:55.641709 DQ_TRACK_CA_EN = 0
6057 13:21:55.641823 CA_PICK = 800
6058 13:21:55.644999 CA_MCKIO = 400
6059 13:21:55.648574 MCKIO_SEMI = 400
6060 13:21:55.651566 PLL_FREQ = 3016
6061 13:21:55.654892 DQ_UI_PI_RATIO = 32
6062 13:21:55.658106 CA_UI_PI_RATIO = 32
6063 13:21:55.661439 ===================================
6064 13:21:55.664489 ===================================
6065 13:21:55.667641 memory_type:LPDDR4
6066 13:21:55.667719 GP_NUM : 10
6067 13:21:55.671060 SRAM_EN : 1
6068 13:21:55.671136 MD32_EN : 0
6069 13:21:55.674679 ===================================
6070 13:21:55.678054 [ANA_INIT] >>>>>>>>>>>>>>
6071 13:21:55.681974 <<<<<< [CONFIGURE PHASE]: ANA_TX
6072 13:21:55.684467 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6073 13:21:55.687815 ===================================
6074 13:21:55.690874 data_rate = 800,PCW = 0X7400
6075 13:21:55.694432 ===================================
6076 13:21:55.697802 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6077 13:21:55.704246 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6078 13:21:55.714706 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6079 13:21:55.717862 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6080 13:21:55.721164 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6081 13:21:55.727909 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6082 13:21:55.728001 [ANA_INIT] flow start
6083 13:21:55.730900 [ANA_INIT] PLL >>>>>>>>
6084 13:21:55.730980 [ANA_INIT] PLL <<<<<<<<
6085 13:21:55.734362 [ANA_INIT] MIDPI >>>>>>>>
6086 13:21:55.737295 [ANA_INIT] MIDPI <<<<<<<<
6087 13:21:55.740658 [ANA_INIT] DLL >>>>>>>>
6088 13:21:55.740724 [ANA_INIT] flow end
6089 13:21:55.743754 ============ LP4 DIFF to SE enter ============
6090 13:21:55.750265 ============ LP4 DIFF to SE exit ============
6091 13:21:55.750349 [ANA_INIT] <<<<<<<<<<<<<
6092 13:21:55.753758 [Flow] Enable top DCM control >>>>>
6093 13:21:55.757005 [Flow] Enable top DCM control <<<<<
6094 13:21:55.760337 Enable DLL master slave shuffle
6095 13:21:55.766811 ==============================================================
6096 13:21:55.769890 Gating Mode config
6097 13:21:55.773575 ==============================================================
6098 13:21:55.776646 Config description:
6099 13:21:55.787563 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6100 13:21:55.793293 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6101 13:21:55.796397 SELPH_MODE 0: By rank 1: By Phase
6102 13:21:55.802879 ==============================================================
6103 13:21:55.806149 GAT_TRACK_EN = 0
6104 13:21:55.809379 RX_GATING_MODE = 2
6105 13:21:55.812776 RX_GATING_TRACK_MODE = 2
6106 13:21:55.816612 SELPH_MODE = 1
6107 13:21:55.819344 PICG_EARLY_EN = 1
6108 13:21:55.819411 VALID_LAT_VALUE = 1
6109 13:21:55.826100 ==============================================================
6110 13:21:55.829103 Enter into Gating configuration >>>>
6111 13:21:55.832366 Exit from Gating configuration <<<<
6112 13:21:55.835847 Enter into DVFS_PRE_config >>>>>
6113 13:21:55.846154 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6114 13:21:55.849181 Exit from DVFS_PRE_config <<<<<
6115 13:21:55.852545 Enter into PICG configuration >>>>
6116 13:21:55.855536 Exit from PICG configuration <<<<
6117 13:21:55.859221 [RX_INPUT] configuration >>>>>
6118 13:21:55.862217 [RX_INPUT] configuration <<<<<
6119 13:21:55.869000 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6120 13:21:55.872159 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6121 13:21:55.879023 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6122 13:21:55.885302 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6123 13:21:55.891929 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6124 13:21:55.898390 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6125 13:21:55.901704 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6126 13:21:55.904883 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6127 13:21:55.909029 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6128 13:21:55.914571 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6129 13:21:55.918032 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6130 13:21:55.921644 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6131 13:21:55.924813 ===================================
6132 13:21:55.928146 LPDDR4 DRAM CONFIGURATION
6133 13:21:55.931174 ===================================
6134 13:21:55.934337 EX_ROW_EN[0] = 0x0
6135 13:21:55.934409 EX_ROW_EN[1] = 0x0
6136 13:21:55.937718 LP4Y_EN = 0x0
6137 13:21:55.937791 WORK_FSP = 0x0
6138 13:21:55.940878 WL = 0x2
6139 13:21:55.940951 RL = 0x2
6140 13:21:55.944732 BL = 0x2
6141 13:21:55.944825 RPST = 0x0
6142 13:21:55.947624 RD_PRE = 0x0
6143 13:21:55.947698 WR_PRE = 0x1
6144 13:21:55.950927 WR_PST = 0x0
6145 13:21:55.950997 DBI_WR = 0x0
6146 13:21:55.954420 DBI_RD = 0x0
6147 13:21:55.954553 OTF = 0x1
6148 13:21:55.958359 ===================================
6149 13:21:55.964409 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6150 13:21:55.967878 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6151 13:21:55.970989 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6152 13:21:55.974370 ===================================
6153 13:21:55.977631 LPDDR4 DRAM CONFIGURATION
6154 13:21:55.980577 ===================================
6155 13:21:55.983698 EX_ROW_EN[0] = 0x10
6156 13:21:55.983771 EX_ROW_EN[1] = 0x0
6157 13:21:55.986987 LP4Y_EN = 0x0
6158 13:21:55.987057 WORK_FSP = 0x0
6159 13:21:55.990576 WL = 0x2
6160 13:21:55.990646 RL = 0x2
6161 13:21:55.993799 BL = 0x2
6162 13:21:55.993868 RPST = 0x0
6163 13:21:55.996809 RD_PRE = 0x0
6164 13:21:55.996883 WR_PRE = 0x1
6165 13:21:56.000586 WR_PST = 0x0
6166 13:21:56.003885 DBI_WR = 0x0
6167 13:21:56.004022 DBI_RD = 0x0
6168 13:21:56.006789 OTF = 0x1
6169 13:21:56.010283 ===================================
6170 13:21:56.014139 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6171 13:21:56.019124 nWR fixed to 30
6172 13:21:56.022103 [ModeRegInit_LP4] CH0 RK0
6173 13:21:56.022177 [ModeRegInit_LP4] CH0 RK1
6174 13:21:56.025432 [ModeRegInit_LP4] CH1 RK0
6175 13:21:56.028935 [ModeRegInit_LP4] CH1 RK1
6176 13:21:56.029006 match AC timing 19
6177 13:21:56.035095 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6178 13:21:56.038867 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6179 13:21:56.041896 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6180 13:21:56.048692 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6181 13:21:56.051749 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6182 13:21:56.051820 ==
6183 13:21:56.055035 Dram Type= 6, Freq= 0, CH_0, rank 0
6184 13:21:56.058447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6185 13:21:56.058519 ==
6186 13:21:56.064713 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6187 13:21:56.071865 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6188 13:21:56.075348 [CA 0] Center 36 (8~64) winsize 57
6189 13:21:56.078074 [CA 1] Center 36 (8~64) winsize 57
6190 13:21:56.081269 [CA 2] Center 36 (8~64) winsize 57
6191 13:21:56.084739 [CA 3] Center 36 (8~64) winsize 57
6192 13:21:56.087656 [CA 4] Center 36 (8~64) winsize 57
6193 13:21:56.091583 [CA 5] Center 36 (8~64) winsize 57
6194 13:21:56.091658
6195 13:21:56.094491 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6196 13:21:56.094560
6197 13:21:56.097668 [CATrainingPosCal] consider 1 rank data
6198 13:21:56.101265 u2DelayCellTimex100 = 270/100 ps
6199 13:21:56.104245 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6200 13:21:56.107490 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6201 13:21:56.110980 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6202 13:21:56.114474 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6203 13:21:56.117641 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6204 13:21:56.120879 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6205 13:21:56.120952
6206 13:21:56.127322 CA PerBit enable=1, Macro0, CA PI delay=36
6207 13:21:56.127403
6208 13:21:56.127465 [CBTSetCACLKResult] CA Dly = 36
6209 13:21:56.131137 CS Dly: 1 (0~32)
6210 13:21:56.131209 ==
6211 13:21:56.134095 Dram Type= 6, Freq= 0, CH_0, rank 1
6212 13:21:56.137305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6213 13:21:56.137380 ==
6214 13:21:56.143844 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6215 13:21:56.150596 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6216 13:21:56.153934 [CA 0] Center 36 (8~64) winsize 57
6217 13:21:56.157073 [CA 1] Center 36 (8~64) winsize 57
6218 13:21:56.160623 [CA 2] Center 36 (8~64) winsize 57
6219 13:21:56.163631 [CA 3] Center 36 (8~64) winsize 57
6220 13:21:56.163707 [CA 4] Center 36 (8~64) winsize 57
6221 13:21:56.166882 [CA 5] Center 36 (8~64) winsize 57
6222 13:21:56.166949
6223 13:21:56.173603 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6224 13:21:56.173710
6225 13:21:56.176707 [CATrainingPosCal] consider 2 rank data
6226 13:21:56.180580 u2DelayCellTimex100 = 270/100 ps
6227 13:21:56.183203 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 13:21:56.186923 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 13:21:56.190456 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 13:21:56.193305 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 13:21:56.196712 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 13:21:56.200123 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 13:21:56.200194
6234 13:21:56.203522 CA PerBit enable=1, Macro0, CA PI delay=36
6235 13:21:56.206569
6236 13:21:56.206642 [CBTSetCACLKResult] CA Dly = 36
6237 13:21:56.209880 CS Dly: 1 (0~32)
6238 13:21:56.209954
6239 13:21:56.213461 ----->DramcWriteLeveling(PI) begin...
6240 13:21:56.213534 ==
6241 13:21:56.216319 Dram Type= 6, Freq= 0, CH_0, rank 0
6242 13:21:56.219717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6243 13:21:56.219790 ==
6244 13:21:56.222797 Write leveling (Byte 0): 40 => 8
6245 13:21:56.226104 Write leveling (Byte 1): 40 => 8
6246 13:21:56.229588 DramcWriteLeveling(PI) end<-----
6247 13:21:56.229660
6248 13:21:56.229721 ==
6249 13:21:56.233749 Dram Type= 6, Freq= 0, CH_0, rank 0
6250 13:21:56.236340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6251 13:21:56.239193 ==
6252 13:21:56.239288 [Gating] SW mode calibration
6253 13:21:56.249342 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6254 13:21:56.253229 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6255 13:21:56.255712 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6256 13:21:56.262240 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6257 13:21:56.266237 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6258 13:21:56.268876 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6259 13:21:56.275765 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6260 13:21:56.279614 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6261 13:21:56.282479 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6262 13:21:56.288870 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6263 13:21:56.292177 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6264 13:21:56.295074 Total UI for P1: 0, mck2ui 16
6265 13:21:56.298749 best dqsien dly found for B0: ( 0, 14, 24)
6266 13:21:56.301706 Total UI for P1: 0, mck2ui 16
6267 13:21:56.304976 best dqsien dly found for B1: ( 0, 14, 24)
6268 13:21:56.308526 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6269 13:21:56.311834 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6270 13:21:56.311920
6271 13:21:56.314926 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6272 13:21:56.321627 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6273 13:21:56.321705 [Gating] SW calibration Done
6274 13:21:56.321769 ==
6275 13:21:56.325039 Dram Type= 6, Freq= 0, CH_0, rank 0
6276 13:21:56.331806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6277 13:21:56.331881 ==
6278 13:21:56.331986 RX Vref Scan: 0
6279 13:21:56.332047
6280 13:21:56.334737 RX Vref 0 -> 0, step: 1
6281 13:21:56.334801
6282 13:21:56.337848 RX Delay -410 -> 252, step: 16
6283 13:21:56.341434 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6284 13:21:56.344689 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6285 13:21:56.351303 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6286 13:21:56.354355 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6287 13:21:56.357597 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6288 13:21:56.360897 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6289 13:21:56.367323 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6290 13:21:56.370504 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6291 13:21:56.374682 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6292 13:21:56.381154 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6293 13:21:56.384197 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6294 13:21:56.386961 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6295 13:21:56.390703 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6296 13:21:56.397005 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6297 13:21:56.400633 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6298 13:21:56.403703 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6299 13:21:56.403772 ==
6300 13:21:56.407113 Dram Type= 6, Freq= 0, CH_0, rank 0
6301 13:21:56.413596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 13:21:56.413671 ==
6303 13:21:56.413733 DQS Delay:
6304 13:21:56.417225 DQS0 = 35, DQS1 = 51
6305 13:21:56.417296 DQM Delay:
6306 13:21:56.417359 DQM0 = 5, DQM1 = 10
6307 13:21:56.420146 DQ Delay:
6308 13:21:56.423416 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6309 13:21:56.423486 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6310 13:21:56.426774 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6311 13:21:56.430015 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6312 13:21:56.430088
6313 13:21:56.430149
6314 13:21:56.433342 ==
6315 13:21:56.436522 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 13:21:56.439745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 13:21:56.439813 ==
6318 13:21:56.439871
6319 13:21:56.439970
6320 13:21:56.442857 TX Vref Scan disable
6321 13:21:56.442937 == TX Byte 0 ==
6322 13:21:56.446396 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6323 13:21:56.453625 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6324 13:21:56.453695 == TX Byte 1 ==
6325 13:21:56.456482 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6326 13:21:56.463010 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6327 13:21:56.463079 ==
6328 13:21:56.466767 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 13:21:56.469711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 13:21:56.469777 ==
6331 13:21:56.469835
6332 13:21:56.469893
6333 13:21:56.472977 TX Vref Scan disable
6334 13:21:56.473041 == TX Byte 0 ==
6335 13:21:56.479782 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6336 13:21:56.482757 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6337 13:21:56.482837 == TX Byte 1 ==
6338 13:21:56.485951 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6339 13:21:56.492603 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6340 13:21:56.492682
6341 13:21:56.492745 [DATLAT]
6342 13:21:56.496419 Freq=400, CH0 RK0
6343 13:21:56.496499
6344 13:21:56.496561 DATLAT Default: 0xf
6345 13:21:56.499303 0, 0xFFFF, sum = 0
6346 13:21:56.499384 1, 0xFFFF, sum = 0
6347 13:21:56.502492 2, 0xFFFF, sum = 0
6348 13:21:56.502572 3, 0xFFFF, sum = 0
6349 13:21:56.505917 4, 0xFFFF, sum = 0
6350 13:21:56.505998 5, 0xFFFF, sum = 0
6351 13:21:56.508777 6, 0xFFFF, sum = 0
6352 13:21:56.508857 7, 0xFFFF, sum = 0
6353 13:21:56.512087 8, 0xFFFF, sum = 0
6354 13:21:56.512168 9, 0xFFFF, sum = 0
6355 13:21:56.515496 10, 0xFFFF, sum = 0
6356 13:21:56.518738 11, 0xFFFF, sum = 0
6357 13:21:56.518819 12, 0xFFFF, sum = 0
6358 13:21:56.522318 13, 0x0, sum = 1
6359 13:21:56.522428 14, 0x0, sum = 2
6360 13:21:56.522520 15, 0x0, sum = 3
6361 13:21:56.525372 16, 0x0, sum = 4
6362 13:21:56.525470 best_step = 14
6363 13:21:56.525561
6364 13:21:56.528850 ==
6365 13:21:56.532291 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 13:21:56.535674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 13:21:56.535749 ==
6368 13:21:56.535855 RX Vref Scan: 1
6369 13:21:56.535979
6370 13:21:56.538431 RX Vref 0 -> 0, step: 1
6371 13:21:56.538497
6372 13:21:56.541554 RX Delay -343 -> 252, step: 8
6373 13:21:56.541621
6374 13:21:56.545159 Set Vref, RX VrefLevel [Byte0]: 50
6375 13:21:56.548401 [Byte1]: 58
6376 13:21:56.552161
6377 13:21:56.552229 Final RX Vref Byte 0 = 50 to rank0
6378 13:21:56.555526 Final RX Vref Byte 1 = 58 to rank0
6379 13:21:56.558470 Final RX Vref Byte 0 = 50 to rank1
6380 13:21:56.561765 Final RX Vref Byte 1 = 58 to rank1==
6381 13:21:56.565780 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 13:21:56.572024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 13:21:56.572095 ==
6384 13:21:56.572156 DQS Delay:
6385 13:21:56.575045 DQS0 = 44, DQS1 = 60
6386 13:21:56.575110 DQM Delay:
6387 13:21:56.575170 DQM0 = 10, DQM1 = 15
6388 13:21:56.578618 DQ Delay:
6389 13:21:56.581551 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6390 13:21:56.584931 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6391 13:21:56.585006 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6392 13:21:56.591641 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6393 13:21:56.591715
6394 13:21:56.591781
6395 13:21:56.598131 [DQSOSCAuto] RK0, (LSB)MR18= 0x978b, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6396 13:21:56.601300 CH0 RK0: MR19=C0C, MR18=978B
6397 13:21:56.608149 CH0_RK0: MR19=0xC0C, MR18=0x978B, DQSOSC=390, MR23=63, INC=388, DEC=258
6398 13:21:56.608225 ==
6399 13:21:56.611205 Dram Type= 6, Freq= 0, CH_0, rank 1
6400 13:21:56.615165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 13:21:56.615236 ==
6402 13:21:56.617787 [Gating] SW mode calibration
6403 13:21:56.624735 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6404 13:21:56.631145 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6405 13:21:56.634465 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6406 13:21:56.637459 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6407 13:21:56.644440 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6408 13:21:56.647789 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6409 13:21:56.650888 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6410 13:21:56.657304 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6411 13:21:56.661044 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6412 13:21:56.664496 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6413 13:21:56.670717 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6414 13:21:56.674001 Total UI for P1: 0, mck2ui 16
6415 13:21:56.677441 best dqsien dly found for B0: ( 0, 14, 24)
6416 13:21:56.680150 Total UI for P1: 0, mck2ui 16
6417 13:21:56.683727 best dqsien dly found for B1: ( 0, 14, 24)
6418 13:21:56.686912 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6419 13:21:56.690297 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6420 13:21:56.690371
6421 13:21:56.693293 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6422 13:21:56.696465 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6423 13:21:56.700155 [Gating] SW calibration Done
6424 13:21:56.700247 ==
6425 13:21:56.703626 Dram Type= 6, Freq= 0, CH_0, rank 1
6426 13:21:56.706638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 13:21:56.709879 ==
6428 13:21:56.709952 RX Vref Scan: 0
6429 13:21:56.710013
6430 13:21:56.713440 RX Vref 0 -> 0, step: 1
6431 13:21:56.713508
6432 13:21:56.716614 RX Delay -410 -> 252, step: 16
6433 13:21:56.719984 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6434 13:21:56.723552 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6435 13:21:56.726803 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6436 13:21:56.732864 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6437 13:21:56.736634 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6438 13:21:56.739624 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6439 13:21:56.742672 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6440 13:21:56.749478 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6441 13:21:56.752520 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6442 13:21:56.756076 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6443 13:21:56.759324 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6444 13:21:56.765751 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6445 13:21:56.768947 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6446 13:21:56.772298 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6447 13:21:56.779140 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6448 13:21:56.782124 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6449 13:21:56.782193 ==
6450 13:21:56.785971 Dram Type= 6, Freq= 0, CH_0, rank 1
6451 13:21:56.788956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 13:21:56.789026 ==
6453 13:21:56.792193 DQS Delay:
6454 13:21:56.792261 DQS0 = 35, DQS1 = 51
6455 13:21:56.795556 DQM Delay:
6456 13:21:56.795622 DQM0 = 8, DQM1 = 10
6457 13:21:56.795680 DQ Delay:
6458 13:21:56.798523 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6459 13:21:56.801800 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6460 13:21:56.805049 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6461 13:21:56.808594 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6462 13:21:56.808668
6463 13:21:56.808733
6464 13:21:56.808790 ==
6465 13:21:56.812034 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 13:21:56.818187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 13:21:56.818260 ==
6468 13:21:56.818324
6469 13:21:56.818384
6470 13:21:56.818438 TX Vref Scan disable
6471 13:21:56.821819 == TX Byte 0 ==
6472 13:21:56.825149 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6473 13:21:56.828184 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6474 13:21:56.831621 == TX Byte 1 ==
6475 13:21:56.835507 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6476 13:21:56.838374 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6477 13:21:56.838441 ==
6478 13:21:56.841413 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 13:21:56.848423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 13:21:56.848497 ==
6481 13:21:56.848562
6482 13:21:56.848620
6483 13:21:56.851234 TX Vref Scan disable
6484 13:21:56.851304 == TX Byte 0 ==
6485 13:21:56.854993 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6486 13:21:56.857856 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6487 13:21:56.861232 == TX Byte 1 ==
6488 13:21:56.864357 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6489 13:21:56.868548 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6490 13:21:56.868616
6491 13:21:56.871006 [DATLAT]
6492 13:21:56.871074 Freq=400, CH0 RK1
6493 13:21:56.871136
6494 13:21:56.874783 DATLAT Default: 0xe
6495 13:21:56.874851 0, 0xFFFF, sum = 0
6496 13:21:56.878452 1, 0xFFFF, sum = 0
6497 13:21:56.878524 2, 0xFFFF, sum = 0
6498 13:21:56.882505 3, 0xFFFF, sum = 0
6499 13:21:56.882575 4, 0xFFFF, sum = 0
6500 13:21:56.884315 5, 0xFFFF, sum = 0
6501 13:21:56.884392 6, 0xFFFF, sum = 0
6502 13:21:56.888149 7, 0xFFFF, sum = 0
6503 13:21:56.891490 8, 0xFFFF, sum = 0
6504 13:21:56.891564 9, 0xFFFF, sum = 0
6505 13:21:56.894233 10, 0xFFFF, sum = 0
6506 13:21:56.894361 11, 0xFFFF, sum = 0
6507 13:21:56.897929 12, 0xFFFF, sum = 0
6508 13:21:56.898012 13, 0x0, sum = 1
6509 13:21:56.900888 14, 0x0, sum = 2
6510 13:21:56.900963 15, 0x0, sum = 3
6511 13:21:56.904360 16, 0x0, sum = 4
6512 13:21:56.904462 best_step = 14
6513 13:21:56.904550
6514 13:21:56.904638 ==
6515 13:21:56.907994 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 13:21:56.910537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 13:21:56.913963 ==
6518 13:21:56.914037 RX Vref Scan: 0
6519 13:21:56.914099
6520 13:21:56.917219 RX Vref 0 -> 0, step: 1
6521 13:21:56.917316
6522 13:21:56.920328 RX Delay -343 -> 252, step: 8
6523 13:21:56.923754 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6524 13:21:56.930950 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6525 13:21:56.933540 iDelay=209, Bit 2, Center -36 (-271 ~ 200) 472
6526 13:21:56.937174 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6527 13:21:56.943797 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6528 13:21:56.946907 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6529 13:21:56.950254 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6530 13:21:56.953606 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6531 13:21:56.956910 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6532 13:21:56.963217 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6533 13:21:56.967005 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6534 13:21:56.969895 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6535 13:21:56.976625 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6536 13:21:56.979831 iDelay=209, Bit 13, Center -36 (-279 ~ 208) 488
6537 13:21:56.983212 iDelay=209, Bit 14, Center -32 (-271 ~ 208) 480
6538 13:21:56.989614 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6539 13:21:56.989716 ==
6540 13:21:56.993019 Dram Type= 6, Freq= 0, CH_0, rank 1
6541 13:21:56.996466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6542 13:21:56.996541 ==
6543 13:21:56.996603 DQS Delay:
6544 13:21:56.999348 DQS0 = 44, DQS1 = 60
6545 13:21:56.999416 DQM Delay:
6546 13:21:57.002894 DQM0 = 10, DQM1 = 16
6547 13:21:57.002965 DQ Delay:
6548 13:21:57.006280 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6549 13:21:57.009397 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6550 13:21:57.012469 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6551 13:21:57.015786 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6552 13:21:57.015863
6553 13:21:57.015966
6554 13:21:57.022606 [DQSOSCAuto] RK1, (LSB)MR18= 0x8680, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6555 13:21:57.025792 CH0 RK1: MR19=C0C, MR18=8680
6556 13:21:57.032779 CH0_RK1: MR19=0xC0C, MR18=0x8680, DQSOSC=393, MR23=63, INC=382, DEC=254
6557 13:21:57.035530 [RxdqsGatingPostProcess] freq 400
6558 13:21:57.042620 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6559 13:21:57.046048 best DQS0 dly(2T, 0.5T) = (0, 10)
6560 13:21:57.046118 best DQS1 dly(2T, 0.5T) = (0, 10)
6561 13:21:57.048751 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6562 13:21:57.052323 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6563 13:21:57.055327 best DQS0 dly(2T, 0.5T) = (0, 10)
6564 13:21:57.059170 best DQS1 dly(2T, 0.5T) = (0, 10)
6565 13:21:57.062237 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6566 13:21:57.065671 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6567 13:21:57.068950 Pre-setting of DQS Precalculation
6568 13:21:57.075198 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6569 13:21:57.075271 ==
6570 13:21:57.078569 Dram Type= 6, Freq= 0, CH_1, rank 0
6571 13:21:57.081733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6572 13:21:57.081804 ==
6573 13:21:57.088929 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6574 13:21:57.094904 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6575 13:21:57.095017 [CA 0] Center 36 (8~64) winsize 57
6576 13:21:57.098101 [CA 1] Center 36 (8~64) winsize 57
6577 13:21:57.101896 [CA 2] Center 36 (8~64) winsize 57
6578 13:21:57.105008 [CA 3] Center 36 (8~64) winsize 57
6579 13:21:57.108220 [CA 4] Center 36 (8~64) winsize 57
6580 13:21:57.112199 [CA 5] Center 36 (8~64) winsize 57
6581 13:21:57.112271
6582 13:21:57.115112 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6583 13:21:57.115209
6584 13:21:57.121449 [CATrainingPosCal] consider 1 rank data
6585 13:21:57.121528 u2DelayCellTimex100 = 270/100 ps
6586 13:21:57.127879 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6587 13:21:57.131403 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6588 13:21:57.134154 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6589 13:21:57.137773 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6590 13:21:57.141237 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6591 13:21:57.144608 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6592 13:21:57.144685
6593 13:21:57.147648 CA PerBit enable=1, Macro0, CA PI delay=36
6594 13:21:57.147722
6595 13:21:57.151631 [CBTSetCACLKResult] CA Dly = 36
6596 13:21:57.153943 CS Dly: 1 (0~32)
6597 13:21:57.154012 ==
6598 13:21:57.157661 Dram Type= 6, Freq= 0, CH_1, rank 1
6599 13:21:57.160903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 13:21:57.160971 ==
6601 13:21:57.167170 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6602 13:21:57.170897 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6603 13:21:57.173960 [CA 0] Center 36 (8~64) winsize 57
6604 13:21:57.177121 [CA 1] Center 36 (8~64) winsize 57
6605 13:21:57.180314 [CA 2] Center 36 (8~64) winsize 57
6606 13:21:57.183604 [CA 3] Center 36 (8~64) winsize 57
6607 13:21:57.186974 [CA 4] Center 36 (8~64) winsize 57
6608 13:21:57.190462 [CA 5] Center 36 (8~64) winsize 57
6609 13:21:57.190535
6610 13:21:57.194054 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6611 13:21:57.194122
6612 13:21:57.196737 [CATrainingPosCal] consider 2 rank data
6613 13:21:57.200362 u2DelayCellTimex100 = 270/100 ps
6614 13:21:57.203372 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 13:21:57.210297 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 13:21:57.213632 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 13:21:57.216991 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 13:21:57.219973 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 13:21:57.223320 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 13:21:57.223386
6621 13:21:57.227113 CA PerBit enable=1, Macro0, CA PI delay=36
6622 13:21:57.227183
6623 13:21:57.229792 [CBTSetCACLKResult] CA Dly = 36
6624 13:21:57.233310 CS Dly: 1 (0~32)
6625 13:21:57.233384
6626 13:21:57.237184 ----->DramcWriteLeveling(PI) begin...
6627 13:21:57.237253 ==
6628 13:21:57.239780 Dram Type= 6, Freq= 0, CH_1, rank 0
6629 13:21:57.243789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6630 13:21:57.243859 ==
6631 13:21:57.247019 Write leveling (Byte 0): 40 => 8
6632 13:21:57.249675 Write leveling (Byte 1): 40 => 8
6633 13:21:57.253134 DramcWriteLeveling(PI) end<-----
6634 13:21:57.253201
6635 13:21:57.253262 ==
6636 13:21:57.256460 Dram Type= 6, Freq= 0, CH_1, rank 0
6637 13:21:57.259420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6638 13:21:57.259526 ==
6639 13:21:57.262679 [Gating] SW mode calibration
6640 13:21:57.269831 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6641 13:21:57.276119 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6642 13:21:57.279397 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6643 13:21:57.282882 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6644 13:21:57.289141 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6645 13:21:57.292562 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6646 13:21:57.295681 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6647 13:21:57.302531 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6648 13:21:57.305752 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6649 13:21:57.309090 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6650 13:21:57.315306 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6651 13:21:57.318858 Total UI for P1: 0, mck2ui 16
6652 13:21:57.322072 best dqsien dly found for B0: ( 0, 14, 24)
6653 13:21:57.322171 Total UI for P1: 0, mck2ui 16
6654 13:21:57.329036 best dqsien dly found for B1: ( 0, 14, 24)
6655 13:21:57.331794 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6656 13:21:57.335211 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6657 13:21:57.335308
6658 13:21:57.338731 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6659 13:21:57.342073 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6660 13:21:57.345397 [Gating] SW calibration Done
6661 13:21:57.345480 ==
6662 13:21:57.348533 Dram Type= 6, Freq= 0, CH_1, rank 0
6663 13:21:57.352012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6664 13:21:57.352092 ==
6665 13:21:57.355075 RX Vref Scan: 0
6666 13:21:57.355169
6667 13:21:57.358547 RX Vref 0 -> 0, step: 1
6668 13:21:57.358649
6669 13:21:57.358738 RX Delay -410 -> 252, step: 16
6670 13:21:57.365229 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6671 13:21:57.368658 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6672 13:21:57.371738 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6673 13:21:57.378053 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6674 13:21:57.381364 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6675 13:21:57.384543 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6676 13:21:57.387846 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6677 13:21:57.394889 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6678 13:21:57.397945 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6679 13:21:57.401791 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6680 13:21:57.404544 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6681 13:21:57.411259 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6682 13:21:57.414298 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6683 13:21:57.417577 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6684 13:21:57.420793 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6685 13:21:57.428016 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6686 13:21:57.428118 ==
6687 13:21:57.430844 Dram Type= 6, Freq= 0, CH_1, rank 0
6688 13:21:57.434352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 13:21:57.434451 ==
6690 13:21:57.437870 DQS Delay:
6691 13:21:57.437966 DQS0 = 43, DQS1 = 51
6692 13:21:57.438064 DQM Delay:
6693 13:21:57.440895 DQM0 = 13, DQM1 = 13
6694 13:21:57.440977 DQ Delay:
6695 13:21:57.444026 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6696 13:21:57.447237 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6697 13:21:57.451231 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6698 13:21:57.453947 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6699 13:21:57.454041
6700 13:21:57.454128
6701 13:21:57.454225 ==
6702 13:21:57.457121 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 13:21:57.460738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 13:21:57.463812 ==
6705 13:21:57.463884
6706 13:21:57.463978
6707 13:21:57.464040 TX Vref Scan disable
6708 13:21:57.467266 == TX Byte 0 ==
6709 13:21:57.470122 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6710 13:21:57.473911 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6711 13:21:57.477159 == TX Byte 1 ==
6712 13:21:57.481113 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6713 13:21:57.484172 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6714 13:21:57.484246 ==
6715 13:21:57.487569 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 13:21:57.490257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 13:21:57.493944 ==
6718 13:21:57.494042
6719 13:21:57.494131
6720 13:21:57.494228 TX Vref Scan disable
6721 13:21:57.497265 == TX Byte 0 ==
6722 13:21:57.500746 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6723 13:21:57.503578 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6724 13:21:57.506698 == TX Byte 1 ==
6725 13:21:57.510254 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6726 13:21:57.513819 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6727 13:21:57.513888
6728 13:21:57.516415 [DATLAT]
6729 13:21:57.516482 Freq=400, CH1 RK0
6730 13:21:57.516542
6731 13:21:57.520318 DATLAT Default: 0xf
6732 13:21:57.520387 0, 0xFFFF, sum = 0
6733 13:21:57.523579 1, 0xFFFF, sum = 0
6734 13:21:57.523645 2, 0xFFFF, sum = 0
6735 13:21:57.526549 3, 0xFFFF, sum = 0
6736 13:21:57.526632 4, 0xFFFF, sum = 0
6737 13:21:57.529641 5, 0xFFFF, sum = 0
6738 13:21:57.529720 6, 0xFFFF, sum = 0
6739 13:21:57.533478 7, 0xFFFF, sum = 0
6740 13:21:57.533553 8, 0xFFFF, sum = 0
6741 13:21:57.536244 9, 0xFFFF, sum = 0
6742 13:21:57.539641 10, 0xFFFF, sum = 0
6743 13:21:57.539714 11, 0xFFFF, sum = 0
6744 13:21:57.542948 12, 0xFFFF, sum = 0
6745 13:21:57.543023 13, 0x0, sum = 1
6746 13:21:57.545902 14, 0x0, sum = 2
6747 13:21:57.545976 15, 0x0, sum = 3
6748 13:21:57.546037 16, 0x0, sum = 4
6749 13:21:57.549637 best_step = 14
6750 13:21:57.549712
6751 13:21:57.549775 ==
6752 13:21:57.552965 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 13:21:57.556292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 13:21:57.556365 ==
6755 13:21:57.559148 RX Vref Scan: 1
6756 13:21:57.559213
6757 13:21:57.563121 RX Vref 0 -> 0, step: 1
6758 13:21:57.563187
6759 13:21:57.563244 RX Delay -343 -> 252, step: 8
6760 13:21:57.563303
6761 13:21:57.566274 Set Vref, RX VrefLevel [Byte0]: 52
6762 13:21:57.569017 [Byte1]: 53
6763 13:21:57.574502
6764 13:21:57.574570 Final RX Vref Byte 0 = 52 to rank0
6765 13:21:57.578358 Final RX Vref Byte 1 = 53 to rank0
6766 13:21:57.581324 Final RX Vref Byte 0 = 52 to rank1
6767 13:21:57.585258 Final RX Vref Byte 1 = 53 to rank1==
6768 13:21:57.588350 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 13:21:57.594331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 13:21:57.594405 ==
6771 13:21:57.594466 DQS Delay:
6772 13:21:57.597838 DQS0 = 44, DQS1 = 52
6773 13:21:57.597904 DQM Delay:
6774 13:21:57.597961 DQM0 = 9, DQM1 = 10
6775 13:21:57.601502 DQ Delay:
6776 13:21:57.604177 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6777 13:21:57.604244 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
6778 13:21:57.607967 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6779 13:21:57.610689 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6780 13:21:57.610758
6781 13:21:57.614695
6782 13:21:57.620603 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e95, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 395 ps
6783 13:21:57.624278 CH1 RK0: MR19=C0C, MR18=6E95
6784 13:21:57.630776 CH1_RK0: MR19=0xC0C, MR18=0x6E95, DQSOSC=391, MR23=63, INC=386, DEC=257
6785 13:21:57.630860 ==
6786 13:21:57.634071 Dram Type= 6, Freq= 0, CH_1, rank 1
6787 13:21:57.637368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 13:21:57.637443 ==
6789 13:21:57.640665 [Gating] SW mode calibration
6790 13:21:57.647254 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6791 13:21:57.654024 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6792 13:21:57.657202 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6793 13:21:57.660445 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6794 13:21:57.667274 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6795 13:21:57.670089 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6796 13:21:57.673405 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6797 13:21:57.680147 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6798 13:21:57.683827 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6799 13:21:57.687035 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6800 13:21:57.693145 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6801 13:21:57.693218 Total UI for P1: 0, mck2ui 16
6802 13:21:57.699738 best dqsien dly found for B0: ( 0, 14, 24)
6803 13:21:57.699836 Total UI for P1: 0, mck2ui 16
6804 13:21:57.706550 best dqsien dly found for B1: ( 0, 14, 24)
6805 13:21:57.709641 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6806 13:21:57.712813 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6807 13:21:57.712884
6808 13:21:57.716742 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6809 13:21:57.719678 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6810 13:21:57.723002 [Gating] SW calibration Done
6811 13:21:57.723071 ==
6812 13:21:57.726643 Dram Type= 6, Freq= 0, CH_1, rank 1
6813 13:21:57.729605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 13:21:57.729676 ==
6815 13:21:57.733231 RX Vref Scan: 0
6816 13:21:57.733299
6817 13:21:57.735828 RX Vref 0 -> 0, step: 1
6818 13:21:57.735891
6819 13:21:57.735989 RX Delay -410 -> 252, step: 16
6820 13:21:57.742557 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6821 13:21:57.746040 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6822 13:21:57.748843 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6823 13:21:57.755631 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6824 13:21:57.759285 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6825 13:21:57.762212 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6826 13:21:57.765583 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6827 13:21:57.772076 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6828 13:21:57.775348 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6829 13:21:57.779103 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6830 13:21:57.781997 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6831 13:21:57.789009 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6832 13:21:57.791704 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6833 13:21:57.795199 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6834 13:21:57.799015 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6835 13:21:57.804914 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6836 13:21:57.805006 ==
6837 13:21:57.808712 Dram Type= 6, Freq= 0, CH_1, rank 1
6838 13:21:57.811606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 13:21:57.811715 ==
6840 13:21:57.814725 DQS Delay:
6841 13:21:57.814806 DQS0 = 43, DQS1 = 51
6842 13:21:57.814889 DQM Delay:
6843 13:21:57.818350 DQM0 = 9, DQM1 = 14
6844 13:21:57.818430 DQ Delay:
6845 13:21:57.821478 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6846 13:21:57.824628 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6847 13:21:57.827860 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6848 13:21:57.831186 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6849 13:21:57.831267
6850 13:21:57.831330
6851 13:21:57.831389 ==
6852 13:21:57.834614 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 13:21:57.837881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 13:21:57.841305 ==
6855 13:21:57.841372
6856 13:21:57.841434
6857 13:21:57.841490 TX Vref Scan disable
6858 13:21:57.844488 == TX Byte 0 ==
6859 13:21:57.847739 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6860 13:21:57.851390 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6861 13:21:57.854451 == TX Byte 1 ==
6862 13:21:57.858348 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6863 13:21:57.861009 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6864 13:21:57.861082 ==
6865 13:21:57.864550 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 13:21:57.871399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 13:21:57.871474 ==
6868 13:21:57.871535
6869 13:21:57.871594
6870 13:21:57.871648 TX Vref Scan disable
6871 13:21:57.874055 == TX Byte 0 ==
6872 13:21:57.877503 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6873 13:21:57.880478 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6874 13:21:57.883995 == TX Byte 1 ==
6875 13:21:57.887356 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6876 13:21:57.890408 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6877 13:21:57.890490
6878 13:21:57.894049 [DATLAT]
6879 13:21:57.894130 Freq=400, CH1 RK1
6880 13:21:57.894195
6881 13:21:57.897229 DATLAT Default: 0xe
6882 13:21:57.897354 0, 0xFFFF, sum = 0
6883 13:21:57.900529 1, 0xFFFF, sum = 0
6884 13:21:57.900611 2, 0xFFFF, sum = 0
6885 13:21:57.904296 3, 0xFFFF, sum = 0
6886 13:21:57.904378 4, 0xFFFF, sum = 0
6887 13:21:57.907078 5, 0xFFFF, sum = 0
6888 13:21:57.907160 6, 0xFFFF, sum = 0
6889 13:21:57.910462 7, 0xFFFF, sum = 0
6890 13:21:57.910544 8, 0xFFFF, sum = 0
6891 13:21:57.913547 9, 0xFFFF, sum = 0
6892 13:21:57.917490 10, 0xFFFF, sum = 0
6893 13:21:57.917572 11, 0xFFFF, sum = 0
6894 13:21:57.920706 12, 0xFFFF, sum = 0
6895 13:21:57.920788 13, 0x0, sum = 1
6896 13:21:57.923948 14, 0x0, sum = 2
6897 13:21:57.924030 15, 0x0, sum = 3
6898 13:21:57.924095 16, 0x0, sum = 4
6899 13:21:57.926879 best_step = 14
6900 13:21:57.926959
6901 13:21:57.927023 ==
6902 13:21:57.930713 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 13:21:57.933954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 13:21:57.934035 ==
6905 13:21:57.936490 RX Vref Scan: 0
6906 13:21:57.936570
6907 13:21:57.940070 RX Vref 0 -> 0, step: 1
6908 13:21:57.940150
6909 13:21:57.940214 RX Delay -343 -> 252, step: 8
6910 13:21:57.948794 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6911 13:21:57.952020 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6912 13:21:57.955302 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6913 13:21:57.962054 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6914 13:21:57.965130 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6915 13:21:57.968063 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6916 13:21:57.971337 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6917 13:21:57.978165 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6918 13:21:57.982088 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6919 13:21:57.984607 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6920 13:21:57.987936 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6921 13:21:57.994981 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6922 13:21:57.998144 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6923 13:21:58.001251 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6924 13:21:58.004986 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6925 13:21:58.011411 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6926 13:21:58.011491 ==
6927 13:21:58.014488 Dram Type= 6, Freq= 0, CH_1, rank 1
6928 13:21:58.017657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6929 13:21:58.017738 ==
6930 13:21:58.017803 DQS Delay:
6931 13:21:58.021378 DQS0 = 48, DQS1 = 52
6932 13:21:58.021452 DQM Delay:
6933 13:21:58.024735 DQM0 = 10, DQM1 = 10
6934 13:21:58.024811 DQ Delay:
6935 13:21:58.027697 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6936 13:21:58.031191 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
6937 13:21:58.034357 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6938 13:21:58.037384 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6939 13:21:58.037465
6940 13:21:58.037528
6941 13:21:58.047523 [DQSOSCAuto] RK1, (LSB)MR18= 0x73ab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
6942 13:21:58.047605 CH1 RK1: MR19=C0C, MR18=73AB
6943 13:21:58.054316 CH1_RK1: MR19=0xC0C, MR18=0x73AB, DQSOSC=388, MR23=63, INC=392, DEC=261
6944 13:21:58.057339 [RxdqsGatingPostProcess] freq 400
6945 13:21:58.063581 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6946 13:21:58.067032 best DQS0 dly(2T, 0.5T) = (0, 10)
6947 13:21:58.070825 best DQS1 dly(2T, 0.5T) = (0, 10)
6948 13:21:58.074068 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6949 13:21:58.077209 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6950 13:21:58.080716 best DQS0 dly(2T, 0.5T) = (0, 10)
6951 13:21:58.083756 best DQS1 dly(2T, 0.5T) = (0, 10)
6952 13:21:58.087240 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6953 13:21:58.087321 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6954 13:21:58.090490 Pre-setting of DQS Precalculation
6955 13:21:58.097249 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6956 13:21:58.103273 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6957 13:21:58.110389 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6958 13:21:58.110471
6959 13:21:58.110535
6960 13:21:58.113063 [Calibration Summary] 800 Mbps
6961 13:21:58.117006 CH 0, Rank 0
6962 13:21:58.117087 SW Impedance : PASS
6963 13:21:58.120337 DUTY Scan : NO K
6964 13:21:58.123418 ZQ Calibration : PASS
6965 13:21:58.123499 Jitter Meter : NO K
6966 13:21:58.126260 CBT Training : PASS
6967 13:21:58.130087 Write leveling : PASS
6968 13:21:58.130168 RX DQS gating : PASS
6969 13:21:58.133147 RX DQ/DQS(RDDQC) : PASS
6970 13:21:58.136255 TX DQ/DQS : PASS
6971 13:21:58.136336 RX DATLAT : PASS
6972 13:21:58.139556 RX DQ/DQS(Engine): PASS
6973 13:21:58.139640 TX OE : NO K
6974 13:21:58.142728 All Pass.
6975 13:21:58.142808
6976 13:21:58.142871 CH 0, Rank 1
6977 13:21:58.146082 SW Impedance : PASS
6978 13:21:58.149537 DUTY Scan : NO K
6979 13:21:58.149618 ZQ Calibration : PASS
6980 13:21:58.152849 Jitter Meter : NO K
6981 13:21:58.152929 CBT Training : PASS
6982 13:21:58.155840 Write leveling : NO K
6983 13:21:58.160452 RX DQS gating : PASS
6984 13:21:58.160532 RX DQ/DQS(RDDQC) : PASS
6985 13:21:58.163151 TX DQ/DQS : PASS
6986 13:21:58.166473 RX DATLAT : PASS
6987 13:21:58.166554 RX DQ/DQS(Engine): PASS
6988 13:21:58.169225 TX OE : NO K
6989 13:21:58.169306 All Pass.
6990 13:21:58.169369
6991 13:21:58.173680 CH 1, Rank 0
6992 13:21:58.173760 SW Impedance : PASS
6993 13:21:58.176070 DUTY Scan : NO K
6994 13:21:58.179298 ZQ Calibration : PASS
6995 13:21:58.179378 Jitter Meter : NO K
6996 13:21:58.182801 CBT Training : PASS
6997 13:21:58.185872 Write leveling : PASS
6998 13:21:58.185952 RX DQS gating : PASS
6999 13:21:58.188969 RX DQ/DQS(RDDQC) : PASS
7000 13:21:58.192535 TX DQ/DQS : PASS
7001 13:21:58.192615 RX DATLAT : PASS
7002 13:21:58.196192 RX DQ/DQS(Engine): PASS
7003 13:21:58.199252 TX OE : NO K
7004 13:21:58.199358 All Pass.
7005 13:21:58.199449
7006 13:21:58.199536 CH 1, Rank 1
7007 13:21:58.202374 SW Impedance : PASS
7008 13:21:58.205365 DUTY Scan : NO K
7009 13:21:58.205446 ZQ Calibration : PASS
7010 13:21:58.209000 Jitter Meter : NO K
7011 13:21:58.212162 CBT Training : PASS
7012 13:21:58.212242 Write leveling : NO K
7013 13:21:58.215465 RX DQS gating : PASS
7014 13:21:58.215545 RX DQ/DQS(RDDQC) : PASS
7015 13:21:58.218573 TX DQ/DQS : PASS
7016 13:21:58.222211 RX DATLAT : PASS
7017 13:21:58.222291 RX DQ/DQS(Engine): PASS
7018 13:21:58.225139 TX OE : NO K
7019 13:21:58.225220 All Pass.
7020 13:21:58.225284
7021 13:21:58.228354 DramC Write-DBI off
7022 13:21:58.232738 PER_BANK_REFRESH: Hybrid Mode
7023 13:21:58.232819 TX_TRACKING: ON
7024 13:21:58.241756 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7025 13:21:58.245009 [FAST_K] Save calibration result to emmc
7026 13:21:58.248568 dramc_set_vcore_voltage set vcore to 725000
7027 13:21:58.251800 Read voltage for 1600, 0
7028 13:21:58.251880 Vio18 = 0
7029 13:21:58.255454 Vcore = 725000
7030 13:21:58.255534 Vdram = 0
7031 13:21:58.255598 Vddq = 0
7032 13:21:58.255657 Vmddr = 0
7033 13:21:58.261749 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7034 13:21:58.268439 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7035 13:21:58.268520 MEM_TYPE=3, freq_sel=13
7036 13:21:58.271542 sv_algorithm_assistance_LP4_3733
7037 13:21:58.275005 ============ PULL DRAM RESETB DOWN ============
7038 13:21:58.281807 ========== PULL DRAM RESETB DOWN end =========
7039 13:21:58.284849 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7040 13:21:58.287760 ===================================
7041 13:21:58.291182 LPDDR4 DRAM CONFIGURATION
7042 13:21:58.294845 ===================================
7043 13:21:58.294994 EX_ROW_EN[0] = 0x0
7044 13:21:58.297760 EX_ROW_EN[1] = 0x0
7045 13:21:58.301669 LP4Y_EN = 0x0
7046 13:21:58.301750 WORK_FSP = 0x1
7047 13:21:58.304655 WL = 0x5
7048 13:21:58.304735 RL = 0x5
7049 13:21:58.307773 BL = 0x2
7050 13:21:58.307853 RPST = 0x0
7051 13:21:58.310983 RD_PRE = 0x0
7052 13:21:58.311062 WR_PRE = 0x1
7053 13:21:58.314029 WR_PST = 0x1
7054 13:21:58.314110 DBI_WR = 0x0
7055 13:21:58.317445 DBI_RD = 0x0
7056 13:21:58.317526 OTF = 0x1
7057 13:21:58.320594 ===================================
7058 13:21:58.323849 ===================================
7059 13:21:58.327293 ANA top config
7060 13:21:58.330675 ===================================
7061 13:21:58.333662 DLL_ASYNC_EN = 0
7062 13:21:58.333768 ALL_SLAVE_EN = 0
7063 13:21:58.337520 NEW_RANK_MODE = 1
7064 13:21:58.340765 DLL_IDLE_MODE = 1
7065 13:21:58.343621 LP45_APHY_COMB_EN = 1
7066 13:21:58.343727 TX_ODT_DIS = 0
7067 13:21:58.346943 NEW_8X_MODE = 1
7068 13:21:58.350049 ===================================
7069 13:21:58.353826 ===================================
7070 13:21:58.357113 data_rate = 3200
7071 13:21:58.360092 CKR = 1
7072 13:21:58.363855 DQ_P2S_RATIO = 8
7073 13:21:58.366707 ===================================
7074 13:21:58.369979 CA_P2S_RATIO = 8
7075 13:21:58.373160 DQ_CA_OPEN = 0
7076 13:21:58.373245 DQ_SEMI_OPEN = 0
7077 13:21:58.376419 CA_SEMI_OPEN = 0
7078 13:21:58.379805 CA_FULL_RATE = 0
7079 13:21:58.383155 DQ_CKDIV4_EN = 0
7080 13:21:58.386523 CA_CKDIV4_EN = 0
7081 13:21:58.389528 CA_PREDIV_EN = 0
7082 13:21:58.389609 PH8_DLY = 12
7083 13:21:58.392736 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7084 13:21:58.396566 DQ_AAMCK_DIV = 4
7085 13:21:58.399651 CA_AAMCK_DIV = 4
7086 13:21:58.403152 CA_ADMCK_DIV = 4
7087 13:21:58.406010 DQ_TRACK_CA_EN = 0
7088 13:21:58.409593 CA_PICK = 1600
7089 13:21:58.409674 CA_MCKIO = 1600
7090 13:21:58.412566 MCKIO_SEMI = 0
7091 13:21:58.416099 PLL_FREQ = 3068
7092 13:21:58.419213 DQ_UI_PI_RATIO = 32
7093 13:21:58.422476 CA_UI_PI_RATIO = 0
7094 13:21:58.425776 ===================================
7095 13:21:58.429266 ===================================
7096 13:21:58.432624 memory_type:LPDDR4
7097 13:21:58.432705 GP_NUM : 10
7098 13:21:58.435748 SRAM_EN : 1
7099 13:21:58.439033 MD32_EN : 0
7100 13:21:58.439113 ===================================
7101 13:21:58.442731 [ANA_INIT] >>>>>>>>>>>>>>
7102 13:21:58.445365 <<<<<< [CONFIGURE PHASE]: ANA_TX
7103 13:21:58.448906 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7104 13:21:58.452164 ===================================
7105 13:21:58.455630 data_rate = 3200,PCW = 0X7600
7106 13:21:58.459323 ===================================
7107 13:21:58.462170 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7108 13:21:58.469103 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7109 13:21:58.471789 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7110 13:21:58.478785 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7111 13:21:58.481884 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7112 13:21:58.485060 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7113 13:21:58.485142 [ANA_INIT] flow start
7114 13:21:58.488520 [ANA_INIT] PLL >>>>>>>>
7115 13:21:58.492134 [ANA_INIT] PLL <<<<<<<<
7116 13:21:58.494957 [ANA_INIT] MIDPI >>>>>>>>
7117 13:21:58.495063 [ANA_INIT] MIDPI <<<<<<<<
7118 13:21:58.498199 [ANA_INIT] DLL >>>>>>>>
7119 13:21:58.501146 [ANA_INIT] DLL <<<<<<<<
7120 13:21:58.501226 [ANA_INIT] flow end
7121 13:21:58.508188 ============ LP4 DIFF to SE enter ============
7122 13:21:58.511587 ============ LP4 DIFF to SE exit ============
7123 13:21:58.514827 [ANA_INIT] <<<<<<<<<<<<<
7124 13:21:58.518135 [Flow] Enable top DCM control >>>>>
7125 13:21:58.521155 [Flow] Enable top DCM control <<<<<
7126 13:21:58.521235 Enable DLL master slave shuffle
7127 13:21:58.528260 ==============================================================
7128 13:21:58.531304 Gating Mode config
7129 13:21:58.534212 ==============================================================
7130 13:21:58.537204 Config description:
7131 13:21:58.547247 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7132 13:21:58.553713 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7133 13:21:58.557111 SELPH_MODE 0: By rank 1: By Phase
7134 13:21:58.564211 ==============================================================
7135 13:21:58.566725 GAT_TRACK_EN = 1
7136 13:21:58.570237 RX_GATING_MODE = 2
7137 13:21:58.573933 RX_GATING_TRACK_MODE = 2
7138 13:21:58.576719 SELPH_MODE = 1
7139 13:21:58.580327 PICG_EARLY_EN = 1
7140 13:21:58.580407 VALID_LAT_VALUE = 1
7141 13:21:58.587506 ==============================================================
7142 13:21:58.589910 Enter into Gating configuration >>>>
7143 13:21:58.593852 Exit from Gating configuration <<<<
7144 13:21:58.597501 Enter into DVFS_PRE_config >>>>>
7145 13:21:58.606713 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7146 13:21:58.609909 Exit from DVFS_PRE_config <<<<<
7147 13:21:58.613323 Enter into PICG configuration >>>>
7148 13:21:58.616454 Exit from PICG configuration <<<<
7149 13:21:58.619480 [RX_INPUT] configuration >>>>>
7150 13:21:58.623582 [RX_INPUT] configuration <<<<<
7151 13:21:58.629540 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7152 13:21:58.633165 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7153 13:21:58.640134 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7154 13:21:58.646145 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7155 13:21:58.653035 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7156 13:21:58.659099 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7157 13:21:58.662674 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7158 13:21:58.666614 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7159 13:21:58.669402 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7160 13:21:58.675631 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7161 13:21:58.679237 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7162 13:21:58.682393 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7163 13:21:58.685876 ===================================
7164 13:21:58.688968 LPDDR4 DRAM CONFIGURATION
7165 13:21:58.692361 ===================================
7166 13:21:58.696175 EX_ROW_EN[0] = 0x0
7167 13:21:58.696257 EX_ROW_EN[1] = 0x0
7168 13:21:58.699018 LP4Y_EN = 0x0
7169 13:21:58.699099 WORK_FSP = 0x1
7170 13:21:58.702027 WL = 0x5
7171 13:21:58.702107 RL = 0x5
7172 13:21:58.705663 BL = 0x2
7173 13:21:58.705744 RPST = 0x0
7174 13:21:58.708917 RD_PRE = 0x0
7175 13:21:58.708997 WR_PRE = 0x1
7176 13:21:58.712463 WR_PST = 0x1
7177 13:21:58.712543 DBI_WR = 0x0
7178 13:21:58.715381 DBI_RD = 0x0
7179 13:21:58.715462 OTF = 0x1
7180 13:21:58.719251 ===================================
7181 13:21:58.725141 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7182 13:21:58.728401 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7183 13:21:58.732385 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7184 13:21:58.735035 ===================================
7185 13:21:58.738830 LPDDR4 DRAM CONFIGURATION
7186 13:21:58.741730 ===================================
7187 13:21:58.744918 EX_ROW_EN[0] = 0x10
7188 13:21:58.745000 EX_ROW_EN[1] = 0x0
7189 13:21:58.748513 LP4Y_EN = 0x0
7190 13:21:58.748597 WORK_FSP = 0x1
7191 13:21:58.751797 WL = 0x5
7192 13:21:58.751878 RL = 0x5
7193 13:21:58.754886 BL = 0x2
7194 13:21:58.754966 RPST = 0x0
7195 13:21:58.758042 RD_PRE = 0x0
7196 13:21:58.758122 WR_PRE = 0x1
7197 13:21:58.761354 WR_PST = 0x1
7198 13:21:58.761435 DBI_WR = 0x0
7199 13:21:58.764855 DBI_RD = 0x0
7200 13:21:58.764936 OTF = 0x1
7201 13:21:58.767853 ===================================
7202 13:21:58.775091 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7203 13:21:58.775193 ==
7204 13:21:58.777738 Dram Type= 6, Freq= 0, CH_0, rank 0
7205 13:21:58.784629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7206 13:21:58.784711 ==
7207 13:21:58.788072 [Duty_Offset_Calibration]
7208 13:21:58.788153 B0:2 B1:0 CA:4
7209 13:21:58.788217
7210 13:21:58.790802 [DutyScan_Calibration_Flow] k_type=0
7211 13:21:58.800079
7212 13:21:58.800160 ==CLK 0==
7213 13:21:58.803748 Final CLK duty delay cell = -4
7214 13:21:58.806308 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7215 13:21:58.810383 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7216 13:21:58.813409 [-4] AVG Duty = 4937%(X100)
7217 13:21:58.813490
7218 13:21:58.816440 CH0 CLK Duty spec in!! Max-Min= 187%
7219 13:21:58.819768 [DutyScan_Calibration_Flow] ====Done====
7220 13:21:58.819848
7221 13:21:58.823164 [DutyScan_Calibration_Flow] k_type=1
7222 13:21:58.840907
7223 13:21:58.840988 ==DQS 0 ==
7224 13:21:58.843709 Final DQS duty delay cell = 0
7225 13:21:58.847021 [0] MAX Duty = 5249%(X100), DQS PI = 38
7226 13:21:58.850089 [0] MIN Duty = 5093%(X100), DQS PI = 10
7227 13:21:58.853434 [0] AVG Duty = 5171%(X100)
7228 13:21:58.853515
7229 13:21:58.853579 ==DQS 1 ==
7230 13:21:58.856646 Final DQS duty delay cell = 0
7231 13:21:58.859702 [0] MAX Duty = 5187%(X100), DQS PI = 2
7232 13:21:58.863172 [0] MIN Duty = 4969%(X100), DQS PI = 12
7233 13:21:58.866969 [0] AVG Duty = 5078%(X100)
7234 13:21:58.867050
7235 13:21:58.869428 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7236 13:21:58.869509
7237 13:21:58.873717 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7238 13:21:58.876094 [DutyScan_Calibration_Flow] ====Done====
7239 13:21:58.876174
7240 13:21:58.879465 [DutyScan_Calibration_Flow] k_type=3
7241 13:21:58.897720
7242 13:21:58.897802 ==DQM 0 ==
7243 13:21:58.900704 Final DQM duty delay cell = 0
7244 13:21:58.903959 [0] MAX Duty = 5124%(X100), DQS PI = 20
7245 13:21:58.907310 [0] MIN Duty = 4875%(X100), DQS PI = 54
7246 13:21:58.910581 [0] AVG Duty = 4999%(X100)
7247 13:21:58.910661
7248 13:21:58.910725 ==DQM 1 ==
7249 13:21:58.914129 Final DQM duty delay cell = 0
7250 13:21:58.917198 [0] MAX Duty = 4969%(X100), DQS PI = 0
7251 13:21:58.920380 [0] MIN Duty = 4813%(X100), DQS PI = 16
7252 13:21:58.923697 [0] AVG Duty = 4891%(X100)
7253 13:21:58.923777
7254 13:21:58.927185 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7255 13:21:58.927266
7256 13:21:58.930678 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7257 13:21:58.933612 [DutyScan_Calibration_Flow] ====Done====
7258 13:21:58.933692
7259 13:21:58.937101 [DutyScan_Calibration_Flow] k_type=2
7260 13:21:58.954566
7261 13:21:58.954648 ==DQ 0 ==
7262 13:21:58.957753 Final DQ duty delay cell = 0
7263 13:21:58.961355 [0] MAX Duty = 5156%(X100), DQS PI = 20
7264 13:21:58.964409 [0] MIN Duty = 4969%(X100), DQS PI = 8
7265 13:21:58.964490 [0] AVG Duty = 5062%(X100)
7266 13:21:58.964554
7267 13:21:58.967891 ==DQ 1 ==
7268 13:21:58.970869 Final DQ duty delay cell = 0
7269 13:21:58.974312 [0] MAX Duty = 5218%(X100), DQS PI = 4
7270 13:21:58.977683 [0] MIN Duty = 4907%(X100), DQS PI = 34
7271 13:21:58.977764 [0] AVG Duty = 5062%(X100)
7272 13:21:58.977827
7273 13:21:58.981146 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7274 13:21:58.984568
7275 13:21:58.987461 CH0 DQ 1 Duty spec in!! Max-Min= 311%
7276 13:21:58.991145 [DutyScan_Calibration_Flow] ====Done====
7277 13:21:58.991226 ==
7278 13:21:58.994672 Dram Type= 6, Freq= 0, CH_1, rank 0
7279 13:21:58.997215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7280 13:21:58.997296 ==
7281 13:21:59.001591 [Duty_Offset_Calibration]
7282 13:21:59.001671 B0:0 B1:-1 CA:3
7283 13:21:59.001735
7284 13:21:59.004439 [DutyScan_Calibration_Flow] k_type=0
7285 13:21:59.014679
7286 13:21:59.014759 ==CLK 0==
7287 13:21:59.017096 Final CLK duty delay cell = -4
7288 13:21:59.020875 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7289 13:21:59.023494 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7290 13:21:59.026837 [-4] AVG Duty = 4937%(X100)
7291 13:21:59.026909
7292 13:21:59.030188 CH1 CLK Duty spec in!! Max-Min= 187%
7293 13:21:59.033797 [DutyScan_Calibration_Flow] ====Done====
7294 13:21:59.033881
7295 13:21:59.036807 [DutyScan_Calibration_Flow] k_type=1
7296 13:21:59.053462
7297 13:21:59.053544 ==DQS 0 ==
7298 13:21:59.056325 Final DQS duty delay cell = 0
7299 13:21:59.059748 [0] MAX Duty = 5250%(X100), DQS PI = 28
7300 13:21:59.063034 [0] MIN Duty = 4907%(X100), DQS PI = 58
7301 13:21:59.066305 [0] AVG Duty = 5078%(X100)
7302 13:21:59.066379
7303 13:21:59.066440 ==DQS 1 ==
7304 13:21:59.070095 Final DQS duty delay cell = -4
7305 13:21:59.073139 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7306 13:21:59.076586 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7307 13:21:59.079453 [-4] AVG Duty = 4922%(X100)
7308 13:21:59.079523
7309 13:21:59.082802 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7310 13:21:59.082873
7311 13:21:59.086291 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7312 13:21:59.089408 [DutyScan_Calibration_Flow] ====Done====
7313 13:21:59.089483
7314 13:21:59.092932 [DutyScan_Calibration_Flow] k_type=3
7315 13:21:59.110892
7316 13:21:59.110969 ==DQM 0 ==
7317 13:21:59.113715 Final DQM duty delay cell = 0
7318 13:21:59.116978 [0] MAX Duty = 5062%(X100), DQS PI = 30
7319 13:21:59.120591 [0] MIN Duty = 4782%(X100), DQS PI = 38
7320 13:21:59.124072 [0] AVG Duty = 4922%(X100)
7321 13:21:59.124148
7322 13:21:59.124208 ==DQM 1 ==
7323 13:21:59.126883 Final DQM duty delay cell = 0
7324 13:21:59.130272 [0] MAX Duty = 5000%(X100), DQS PI = 32
7325 13:21:59.133373 [0] MIN Duty = 4813%(X100), DQS PI = 0
7326 13:21:59.136658 [0] AVG Duty = 4906%(X100)
7327 13:21:59.136732
7328 13:21:59.140336 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7329 13:21:59.140406
7330 13:21:59.143586 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7331 13:21:59.146449 [DutyScan_Calibration_Flow] ====Done====
7332 13:21:59.146521
7333 13:21:59.149944 [DutyScan_Calibration_Flow] k_type=2
7334 13:21:59.166720
7335 13:21:59.166796 ==DQ 0 ==
7336 13:21:59.170043 Final DQ duty delay cell = -4
7337 13:21:59.173219 [-4] MAX Duty = 4969%(X100), DQS PI = 30
7338 13:21:59.176346 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7339 13:21:59.179801 [-4] AVG Duty = 4891%(X100)
7340 13:21:59.179868
7341 13:21:59.179965 ==DQ 1 ==
7342 13:21:59.182625 Final DQ duty delay cell = 0
7343 13:21:59.186060 [0] MAX Duty = 5031%(X100), DQS PI = 30
7344 13:21:59.189479 [0] MIN Duty = 4875%(X100), DQS PI = 0
7345 13:21:59.193026 [0] AVG Duty = 4953%(X100)
7346 13:21:59.193095
7347 13:21:59.196523 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7348 13:21:59.196596
7349 13:21:59.199170 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7350 13:21:59.202832 [DutyScan_Calibration_Flow] ====Done====
7351 13:21:59.206206 nWR fixed to 30
7352 13:21:59.209817 [ModeRegInit_LP4] CH0 RK0
7353 13:21:59.209892 [ModeRegInit_LP4] CH0 RK1
7354 13:21:59.212545 [ModeRegInit_LP4] CH1 RK0
7355 13:21:59.215957 [ModeRegInit_LP4] CH1 RK1
7356 13:21:59.216030 match AC timing 5
7357 13:21:59.223196 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7358 13:21:59.226234 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7359 13:21:59.229901 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7360 13:21:59.235786 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7361 13:21:59.239469 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7362 13:21:59.239542 [MiockJmeterHQA]
7363 13:21:59.239608
7364 13:21:59.242647 [DramcMiockJmeter] u1RxGatingPI = 0
7365 13:21:59.246338 0 : 4367, 4142
7366 13:21:59.246413 4 : 4252, 4027
7367 13:21:59.249142 8 : 4363, 4137
7368 13:21:59.249216 12 : 4252, 4027
7369 13:21:59.252266 16 : 4363, 4137
7370 13:21:59.252341 20 : 4252, 4027
7371 13:21:59.252403 24 : 4363, 4137
7372 13:21:59.255581 28 : 4252, 4027
7373 13:21:59.255651 32 : 4252, 4027
7374 13:21:59.259143 36 : 4253, 4026
7375 13:21:59.259215 40 : 4252, 4027
7376 13:21:59.262550 44 : 4363, 4137
7377 13:21:59.262626 48 : 4252, 4027
7378 13:21:59.265458 52 : 4363, 4138
7379 13:21:59.265533 56 : 4253, 4026
7380 13:21:59.265599 60 : 4253, 4027
7381 13:21:59.268684 64 : 4250, 4027
7382 13:21:59.268757 68 : 4360, 4137
7383 13:21:59.271743 72 : 4250, 4027
7384 13:21:59.271817 76 : 4360, 4137
7385 13:21:59.275347 80 : 4250, 4027
7386 13:21:59.275420 84 : 4250, 4027
7387 13:21:59.278532 88 : 4250, 4026
7388 13:21:59.278607 92 : 4255, 4031
7389 13:21:59.281846 96 : 4360, 3456
7390 13:21:59.281916 100 : 4250, 0
7391 13:21:59.281977 104 : 4360, 0
7392 13:21:59.285180 108 : 4361, 0
7393 13:21:59.285249 112 : 4255, 0
7394 13:21:59.285309 116 : 4250, 0
7395 13:21:59.288836 120 : 4250, 0
7396 13:21:59.288909 124 : 4252, 0
7397 13:21:59.291694 128 : 4250, 0
7398 13:21:59.291767 132 : 4250, 0
7399 13:21:59.291829 136 : 4252, 0
7400 13:21:59.294890 140 : 4250, 0
7401 13:21:59.294958 144 : 4250, 0
7402 13:21:59.298341 148 : 4250, 0
7403 13:21:59.298409 152 : 4361, 0
7404 13:21:59.298472 156 : 4361, 0
7405 13:21:59.301527 160 : 4363, 0
7406 13:21:59.301599 164 : 4250, 0
7407 13:21:59.304974 168 : 4250, 0
7408 13:21:59.305049 172 : 4250, 0
7409 13:21:59.305110 176 : 4250, 0
7410 13:21:59.308265 180 : 4250, 0
7411 13:21:59.308341 184 : 4250, 0
7412 13:21:59.308401 188 : 4250, 0
7413 13:21:59.311531 192 : 4361, 0
7414 13:21:59.311600 196 : 4250, 0
7415 13:21:59.315057 200 : 4250, 0
7416 13:21:59.315126 204 : 4250, 0
7417 13:21:59.315188 208 : 4360, 0
7418 13:21:59.318442 212 : 4361, 0
7419 13:21:59.318530 216 : 4250, 0
7420 13:21:59.321995 220 : 4250, 401
7421 13:21:59.322069 224 : 4250, 3824
7422 13:21:59.325186 228 : 4361, 4137
7423 13:21:59.325268 232 : 4250, 4027
7424 13:21:59.328381 236 : 4252, 4027
7425 13:21:59.328463 240 : 4250, 4027
7426 13:21:59.328528 244 : 4253, 4029
7427 13:21:59.331914 248 : 4250, 4027
7428 13:21:59.331987 252 : 4250, 4026
7429 13:21:59.334688 256 : 4250, 4027
7430 13:21:59.334756 260 : 4250, 4027
7431 13:21:59.338010 264 : 4250, 4027
7432 13:21:59.338091 268 : 4360, 4137
7433 13:21:59.341862 272 : 4361, 4137
7434 13:21:59.341943 276 : 4248, 4024
7435 13:21:59.344621 280 : 4361, 4138
7436 13:21:59.344702 284 : 4360, 4137
7437 13:21:59.348460 288 : 4250, 4026
7438 13:21:59.348542 292 : 4250, 4026
7439 13:21:59.351197 296 : 4250, 4027
7440 13:21:59.351278 300 : 4250, 4027
7441 13:21:59.354967 304 : 4250, 4026
7442 13:21:59.355052 308 : 4250, 4026
7443 13:21:59.355118 312 : 4250, 4026
7444 13:21:59.358150 316 : 4250, 4027
7445 13:21:59.358232 320 : 4360, 4137
7446 13:21:59.361141 324 : 4361, 4137
7447 13:21:59.361222 328 : 4250, 4027
7448 13:21:59.364527 332 : 4361, 4135
7449 13:21:59.364609 336 : 4360, 2235
7450 13:21:59.368321 340 : 4250, 9
7451 13:21:59.368403
7452 13:21:59.368467 MIOCK jitter meter ch=0
7453 13:21:59.368526
7454 13:21:59.370859 1T = (340-100) = 240 dly cells
7455 13:21:59.377470 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7456 13:21:59.377551 ==
7457 13:21:59.380919 Dram Type= 6, Freq= 0, CH_0, rank 0
7458 13:21:59.384168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7459 13:21:59.384250 ==
7460 13:21:59.391008 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7461 13:21:59.394387 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7462 13:21:59.400595 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7463 13:21:59.403944 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7464 13:21:59.414160 [CA 0] Center 44 (14~74) winsize 61
7465 13:21:59.418322 [CA 1] Center 43 (13~74) winsize 62
7466 13:21:59.420794 [CA 2] Center 38 (9~68) winsize 60
7467 13:21:59.424488 [CA 3] Center 38 (9~68) winsize 60
7468 13:21:59.427711 [CA 4] Center 36 (7~66) winsize 60
7469 13:21:59.430909 [CA 5] Center 36 (6~66) winsize 61
7470 13:21:59.430990
7471 13:21:59.433847 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7472 13:21:59.433927
7473 13:21:59.437213 [CATrainingPosCal] consider 1 rank data
7474 13:21:59.440654 u2DelayCellTimex100 = 271/100 ps
7475 13:21:59.448384 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7476 13:21:59.450547 CA1 delay=43 (13~74),Diff = 7 PI (25 cell)
7477 13:21:59.454335 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7478 13:21:59.456923 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7479 13:21:59.460768 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7480 13:21:59.463721 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7481 13:21:59.463810
7482 13:21:59.467052 CA PerBit enable=1, Macro0, CA PI delay=36
7483 13:21:59.467132
7484 13:21:59.470301 [CBTSetCACLKResult] CA Dly = 36
7485 13:21:59.473598 CS Dly: 11 (0~42)
7486 13:21:59.476847 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7487 13:21:59.480180 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7488 13:21:59.480260 ==
7489 13:21:59.483167 Dram Type= 6, Freq= 0, CH_0, rank 1
7490 13:21:59.489714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7491 13:21:59.489796 ==
7492 13:21:59.493505 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7493 13:21:59.499751 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7494 13:21:59.503009 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7495 13:21:59.510083 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7496 13:21:59.517503 [CA 0] Center 44 (14~75) winsize 62
7497 13:21:59.520857 [CA 1] Center 44 (14~74) winsize 61
7498 13:21:59.524762 [CA 2] Center 39 (10~69) winsize 60
7499 13:21:59.527651 [CA 3] Center 38 (9~68) winsize 60
7500 13:21:59.531175 [CA 4] Center 37 (7~67) winsize 61
7501 13:21:59.534247 [CA 5] Center 36 (7~66) winsize 60
7502 13:21:59.534317
7503 13:21:59.537379 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7504 13:21:59.537446
7505 13:21:59.544163 [CATrainingPosCal] consider 2 rank data
7506 13:21:59.544234 u2DelayCellTimex100 = 271/100 ps
7507 13:21:59.551579 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7508 13:21:59.554035 CA1 delay=44 (14~74),Diff = 8 PI (28 cell)
7509 13:21:59.558148 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7510 13:21:59.560187 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7511 13:21:59.563747 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7512 13:21:59.567112 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7513 13:21:59.567194
7514 13:21:59.570443 CA PerBit enable=1, Macro0, CA PI delay=36
7515 13:21:59.570524
7516 13:21:59.573629 [CBTSetCACLKResult] CA Dly = 36
7517 13:21:59.576979 CS Dly: 11 (0~43)
7518 13:21:59.580436 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7519 13:21:59.583751 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7520 13:21:59.583873
7521 13:21:59.587032 ----->DramcWriteLeveling(PI) begin...
7522 13:21:59.590236 ==
7523 13:21:59.590316 Dram Type= 6, Freq= 0, CH_0, rank 0
7524 13:21:59.597087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7525 13:21:59.597167 ==
7526 13:21:59.599901 Write leveling (Byte 0): 37 => 37
7527 13:21:59.603154 Write leveling (Byte 1): 27 => 27
7528 13:21:59.606625 DramcWriteLeveling(PI) end<-----
7529 13:21:59.606697
7530 13:21:59.606761 ==
7531 13:21:59.609893 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 13:21:59.613419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 13:21:59.613489 ==
7534 13:21:59.616559 [Gating] SW mode calibration
7535 13:21:59.622713 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7536 13:21:59.629814 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7537 13:21:59.633463 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7538 13:21:59.636140 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7539 13:21:59.642678 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7540 13:21:59.646093 1 4 12 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
7541 13:21:59.649291 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7542 13:21:59.656422 1 4 20 | B1->B0 | 2d2c 3434 | 1 1 | (0 0) (1 1)
7543 13:21:59.659298 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7544 13:21:59.662855 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7545 13:21:59.669836 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7546 13:21:59.672769 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7547 13:21:59.675959 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7548 13:21:59.682769 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
7549 13:21:59.685825 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7550 13:21:59.689012 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
7551 13:21:59.695702 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7552 13:21:59.698977 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7553 13:21:59.702410 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7554 13:21:59.708809 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7555 13:21:59.712216 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7556 13:21:59.715497 1 6 12 | B1->B0 | 2323 4242 | 0 1 | (0 0) (0 0)
7557 13:21:59.721888 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7558 13:21:59.725562 1 6 20 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7559 13:21:59.728888 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7560 13:21:59.735090 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7561 13:21:59.738360 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7562 13:21:59.741540 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7563 13:21:59.748788 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7564 13:21:59.751396 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7565 13:21:59.755252 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7566 13:21:59.761803 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7567 13:21:59.765008 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 13:21:59.768093 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 13:21:59.774719 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 13:21:59.778158 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 13:21:59.781400 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 13:21:59.787798 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 13:21:59.791281 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 13:21:59.794330 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 13:21:59.801088 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 13:21:59.804137 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 13:21:59.808188 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 13:21:59.813761 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7579 13:21:59.817183 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7580 13:21:59.820760 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7581 13:21:59.823702 Total UI for P1: 0, mck2ui 16
7582 13:21:59.827372 best dqsien dly found for B0: ( 1, 9, 6)
7583 13:21:59.833762 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7584 13:21:59.837749 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7585 13:21:59.840163 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 13:21:59.843663 Total UI for P1: 0, mck2ui 16
7587 13:21:59.846813 best dqsien dly found for B1: ( 1, 9, 20)
7588 13:21:59.851016 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
7589 13:21:59.853937 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7590 13:21:59.854018
7591 13:21:59.860647 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
7592 13:21:59.863505 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7593 13:21:59.863586 [Gating] SW calibration Done
7594 13:21:59.867108 ==
7595 13:21:59.870227 Dram Type= 6, Freq= 0, CH_0, rank 0
7596 13:21:59.873517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7597 13:21:59.873623 ==
7598 13:21:59.873717 RX Vref Scan: 0
7599 13:21:59.873780
7600 13:21:59.876663 RX Vref 0 -> 0, step: 1
7601 13:21:59.876745
7602 13:21:59.880215 RX Delay 0 -> 252, step: 8
7603 13:21:59.883175 iDelay=192, Bit 0, Center 135 (80 ~ 191) 112
7604 13:21:59.886471 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7605 13:21:59.893232 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7606 13:21:59.896853 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7607 13:21:59.899479 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7608 13:21:59.902777 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7609 13:21:59.906195 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7610 13:21:59.912493 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7611 13:21:59.915888 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7612 13:21:59.919351 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7613 13:21:59.922704 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7614 13:21:59.926061 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7615 13:21:59.932327 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7616 13:21:59.935712 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
7617 13:21:59.939329 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7618 13:21:59.942462 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7619 13:21:59.942543 ==
7620 13:21:59.945791 Dram Type= 6, Freq= 0, CH_0, rank 0
7621 13:21:59.952325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7622 13:21:59.952431 ==
7623 13:21:59.952523 DQS Delay:
7624 13:21:59.955446 DQS0 = 0, DQS1 = 0
7625 13:21:59.955552 DQM Delay:
7626 13:21:59.959296 DQM0 = 131, DQM1 = 127
7627 13:21:59.959380 DQ Delay:
7628 13:21:59.962736 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
7629 13:21:59.965178 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7630 13:21:59.968722 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
7631 13:21:59.972135 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
7632 13:21:59.972215
7633 13:21:59.972279
7634 13:21:59.972337 ==
7635 13:21:59.975279 Dram Type= 6, Freq= 0, CH_0, rank 0
7636 13:21:59.981643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7637 13:21:59.981724 ==
7638 13:21:59.981788
7639 13:21:59.981848
7640 13:21:59.981904 TX Vref Scan disable
7641 13:21:59.985164 == TX Byte 0 ==
7642 13:21:59.988768 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7643 13:21:59.995494 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7644 13:21:59.995600 == TX Byte 1 ==
7645 13:21:59.998875 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7646 13:22:00.005336 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7647 13:22:00.005417 ==
7648 13:22:00.008459 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 13:22:00.011750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 13:22:00.011856 ==
7651 13:22:00.026302
7652 13:22:00.029714 TX Vref early break, caculate TX vref
7653 13:22:00.033089 TX Vref=16, minBit 4, minWin=22, winSum=367
7654 13:22:00.036711 TX Vref=18, minBit 7, minWin=23, winSum=384
7655 13:22:00.039737 TX Vref=20, minBit 8, minWin=22, winSum=391
7656 13:22:00.043255 TX Vref=22, minBit 1, minWin=23, winSum=397
7657 13:22:00.046092 TX Vref=24, minBit 1, minWin=25, winSum=412
7658 13:22:00.052828 TX Vref=26, minBit 1, minWin=25, winSum=418
7659 13:22:00.056035 TX Vref=28, minBit 2, minWin=25, winSum=423
7660 13:22:00.059291 TX Vref=30, minBit 0, minWin=25, winSum=421
7661 13:22:00.062431 TX Vref=32, minBit 0, minWin=25, winSum=413
7662 13:22:00.065988 TX Vref=34, minBit 1, minWin=24, winSum=402
7663 13:22:00.073077 TX Vref=36, minBit 2, minWin=23, winSum=389
7664 13:22:00.076671 [TxChooseVref] Worse bit 2, Min win 25, Win sum 423, Final Vref 28
7665 13:22:00.076753
7666 13:22:00.079090 Final TX Range 0 Vref 28
7667 13:22:00.079171
7668 13:22:00.079236 ==
7669 13:22:00.082858 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 13:22:00.085942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 13:22:00.089385 ==
7672 13:22:00.089465
7673 13:22:00.089529
7674 13:22:00.089588 TX Vref Scan disable
7675 13:22:00.095918 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7676 13:22:00.096025 == TX Byte 0 ==
7677 13:22:00.099285 u2DelayCellOfst[0]=18 cells (5 PI)
7678 13:22:00.102515 u2DelayCellOfst[1]=18 cells (5 PI)
7679 13:22:00.106384 u2DelayCellOfst[2]=14 cells (4 PI)
7680 13:22:00.108953 u2DelayCellOfst[3]=14 cells (4 PI)
7681 13:22:00.112402 u2DelayCellOfst[4]=10 cells (3 PI)
7682 13:22:00.115504 u2DelayCellOfst[5]=0 cells (0 PI)
7683 13:22:00.119141 u2DelayCellOfst[6]=21 cells (6 PI)
7684 13:22:00.122166 u2DelayCellOfst[7]=21 cells (6 PI)
7685 13:22:00.125724 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7686 13:22:00.129099 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7687 13:22:00.132190 == TX Byte 1 ==
7688 13:22:00.135210 u2DelayCellOfst[8]=0 cells (0 PI)
7689 13:22:00.139327 u2DelayCellOfst[9]=0 cells (0 PI)
7690 13:22:00.142247 u2DelayCellOfst[10]=7 cells (2 PI)
7691 13:22:00.145298 u2DelayCellOfst[11]=3 cells (1 PI)
7692 13:22:00.148974 u2DelayCellOfst[12]=10 cells (3 PI)
7693 13:22:00.152344 u2DelayCellOfst[13]=10 cells (3 PI)
7694 13:22:00.155416 u2DelayCellOfst[14]=14 cells (4 PI)
7695 13:22:00.158667 u2DelayCellOfst[15]=10 cells (3 PI)
7696 13:22:00.162321 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7697 13:22:00.165199 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7698 13:22:00.168165 DramC Write-DBI on
7699 13:22:00.168246 ==
7700 13:22:00.171526 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 13:22:00.174718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 13:22:00.174800 ==
7703 13:22:00.174864
7704 13:22:00.174924
7705 13:22:00.177948 TX Vref Scan disable
7706 13:22:00.181450 == TX Byte 0 ==
7707 13:22:00.184652 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7708 13:22:00.184734 == TX Byte 1 ==
7709 13:22:00.191540 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7710 13:22:00.191647 DramC Write-DBI off
7711 13:22:00.191739
7712 13:22:00.191827 [DATLAT]
7713 13:22:00.195124 Freq=1600, CH0 RK0
7714 13:22:00.195205
7715 13:22:00.197787 DATLAT Default: 0xf
7716 13:22:00.197867 0, 0xFFFF, sum = 0
7717 13:22:00.201277 1, 0xFFFF, sum = 0
7718 13:22:00.201360 2, 0xFFFF, sum = 0
7719 13:22:00.205096 3, 0xFFFF, sum = 0
7720 13:22:00.205178 4, 0xFFFF, sum = 0
7721 13:22:00.208067 5, 0xFFFF, sum = 0
7722 13:22:00.208153 6, 0xFFFF, sum = 0
7723 13:22:00.211464 7, 0xFFFF, sum = 0
7724 13:22:00.211546 8, 0xFFFF, sum = 0
7725 13:22:00.214818 9, 0xFFFF, sum = 0
7726 13:22:00.214901 10, 0xFFFF, sum = 0
7727 13:22:00.218267 11, 0xFFFF, sum = 0
7728 13:22:00.218348 12, 0xFFFF, sum = 0
7729 13:22:00.221357 13, 0xFFFF, sum = 0
7730 13:22:00.221442 14, 0x0, sum = 1
7731 13:22:00.224361 15, 0x0, sum = 2
7732 13:22:00.224443 16, 0x0, sum = 3
7733 13:22:00.227523 17, 0x0, sum = 4
7734 13:22:00.227605 best_step = 15
7735 13:22:00.227668
7736 13:22:00.227728 ==
7737 13:22:00.231289 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 13:22:00.237363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 13:22:00.237445 ==
7740 13:22:00.237509 RX Vref Scan: 1
7741 13:22:00.237570
7742 13:22:00.240847 Set Vref Range= 24 -> 127
7743 13:22:00.240928
7744 13:22:00.244170 RX Vref 24 -> 127, step: 1
7745 13:22:00.244251
7746 13:22:00.247819 RX Delay 11 -> 252, step: 4
7747 13:22:00.247949
7748 13:22:00.250744 Set Vref, RX VrefLevel [Byte0]: 24
7749 13:22:00.254083 [Byte1]: 24
7750 13:22:00.254164
7751 13:22:00.257440 Set Vref, RX VrefLevel [Byte0]: 25
7752 13:22:00.260777 [Byte1]: 25
7753 13:22:00.260858
7754 13:22:00.264067 Set Vref, RX VrefLevel [Byte0]: 26
7755 13:22:00.267069 [Byte1]: 26
7756 13:22:00.270474
7757 13:22:00.270554 Set Vref, RX VrefLevel [Byte0]: 27
7758 13:22:00.274144 [Byte1]: 27
7759 13:22:00.278980
7760 13:22:00.279060 Set Vref, RX VrefLevel [Byte0]: 28
7761 13:22:00.281228 [Byte1]: 28
7762 13:22:00.285924
7763 13:22:00.286005 Set Vref, RX VrefLevel [Byte0]: 29
7764 13:22:00.289020 [Byte1]: 29
7765 13:22:00.293394
7766 13:22:00.293474 Set Vref, RX VrefLevel [Byte0]: 30
7767 13:22:00.296334 [Byte1]: 30
7768 13:22:00.301567
7769 13:22:00.301648 Set Vref, RX VrefLevel [Byte0]: 31
7770 13:22:00.304149 [Byte1]: 31
7771 13:22:00.309116
7772 13:22:00.309196 Set Vref, RX VrefLevel [Byte0]: 32
7773 13:22:00.311785 [Byte1]: 32
7774 13:22:00.316708
7775 13:22:00.316789 Set Vref, RX VrefLevel [Byte0]: 33
7776 13:22:00.319362 [Byte1]: 33
7777 13:22:00.323852
7778 13:22:00.323980 Set Vref, RX VrefLevel [Byte0]: 34
7779 13:22:00.327484 [Byte1]: 34
7780 13:22:00.332238
7781 13:22:00.332312 Set Vref, RX VrefLevel [Byte0]: 35
7782 13:22:00.334819 [Byte1]: 35
7783 13:22:00.338771
7784 13:22:00.338843 Set Vref, RX VrefLevel [Byte0]: 36
7785 13:22:00.342219 [Byte1]: 36
7786 13:22:00.346954
7787 13:22:00.347023 Set Vref, RX VrefLevel [Byte0]: 37
7788 13:22:00.350057 [Byte1]: 37
7789 13:22:00.354208
7790 13:22:00.354279 Set Vref, RX VrefLevel [Byte0]: 38
7791 13:22:00.357313 [Byte1]: 38
7792 13:22:00.361993
7793 13:22:00.362065 Set Vref, RX VrefLevel [Byte0]: 39
7794 13:22:00.365172 [Byte1]: 39
7795 13:22:00.369344
7796 13:22:00.369415 Set Vref, RX VrefLevel [Byte0]: 40
7797 13:22:00.372461 [Byte1]: 40
7798 13:22:00.377340
7799 13:22:00.377415 Set Vref, RX VrefLevel [Byte0]: 41
7800 13:22:00.380274 [Byte1]: 41
7801 13:22:00.384530
7802 13:22:00.384605 Set Vref, RX VrefLevel [Byte0]: 42
7803 13:22:00.387872 [Byte1]: 42
7804 13:22:00.392405
7805 13:22:00.392480 Set Vref, RX VrefLevel [Byte0]: 43
7806 13:22:00.395984 [Byte1]: 43
7807 13:22:00.399976
7808 13:22:00.400073 Set Vref, RX VrefLevel [Byte0]: 44
7809 13:22:00.403648 [Byte1]: 44
7810 13:22:00.407759
7811 13:22:00.407855 Set Vref, RX VrefLevel [Byte0]: 45
7812 13:22:00.411050 [Byte1]: 45
7813 13:22:00.415339
7814 13:22:00.415412 Set Vref, RX VrefLevel [Byte0]: 46
7815 13:22:00.418654 [Byte1]: 46
7816 13:22:00.423067
7817 13:22:00.423142 Set Vref, RX VrefLevel [Byte0]: 47
7818 13:22:00.426215 [Byte1]: 47
7819 13:22:00.430140
7820 13:22:00.430213 Set Vref, RX VrefLevel [Byte0]: 48
7821 13:22:00.433504 [Byte1]: 48
7822 13:22:00.437695
7823 13:22:00.437767 Set Vref, RX VrefLevel [Byte0]: 49
7824 13:22:00.441027 [Byte1]: 49
7825 13:22:00.445553
7826 13:22:00.445623 Set Vref, RX VrefLevel [Byte0]: 50
7827 13:22:00.449056 [Byte1]: 50
7828 13:22:00.453038
7829 13:22:00.453110 Set Vref, RX VrefLevel [Byte0]: 51
7830 13:22:00.456628 [Byte1]: 51
7831 13:22:00.460699
7832 13:22:00.460768 Set Vref, RX VrefLevel [Byte0]: 52
7833 13:22:00.464311 [Byte1]: 52
7834 13:22:00.468472
7835 13:22:00.468541 Set Vref, RX VrefLevel [Byte0]: 53
7836 13:22:00.471677 [Byte1]: 53
7837 13:22:00.476157
7838 13:22:00.476228 Set Vref, RX VrefLevel [Byte0]: 54
7839 13:22:00.479096 [Byte1]: 54
7840 13:22:00.483911
7841 13:22:00.484020 Set Vref, RX VrefLevel [Byte0]: 55
7842 13:22:00.486831 [Byte1]: 55
7843 13:22:00.491189
7844 13:22:00.491270 Set Vref, RX VrefLevel [Byte0]: 56
7845 13:22:00.494931 [Byte1]: 56
7846 13:22:00.499223
7847 13:22:00.499304 Set Vref, RX VrefLevel [Byte0]: 57
7848 13:22:00.501976 [Byte1]: 57
7849 13:22:00.506578
7850 13:22:00.506659 Set Vref, RX VrefLevel [Byte0]: 58
7851 13:22:00.509972 [Byte1]: 58
7852 13:22:00.514205
7853 13:22:00.514285 Set Vref, RX VrefLevel [Byte0]: 59
7854 13:22:00.517464 [Byte1]: 59
7855 13:22:00.521896
7856 13:22:00.521976 Set Vref, RX VrefLevel [Byte0]: 60
7857 13:22:00.524940 [Byte1]: 60
7858 13:22:00.529188
7859 13:22:00.529269 Set Vref, RX VrefLevel [Byte0]: 61
7860 13:22:00.532796 [Byte1]: 61
7861 13:22:00.536858
7862 13:22:00.536939 Set Vref, RX VrefLevel [Byte0]: 62
7863 13:22:00.540011 [Byte1]: 62
7864 13:22:00.544272
7865 13:22:00.547734 Set Vref, RX VrefLevel [Byte0]: 63
7866 13:22:00.550908 [Byte1]: 63
7867 13:22:00.550990
7868 13:22:00.554446 Set Vref, RX VrefLevel [Byte0]: 64
7869 13:22:00.557393 [Byte1]: 64
7870 13:22:00.557474
7871 13:22:00.560750 Set Vref, RX VrefLevel [Byte0]: 65
7872 13:22:00.564441 [Byte1]: 65
7873 13:22:00.567349
7874 13:22:00.567433 Set Vref, RX VrefLevel [Byte0]: 66
7875 13:22:00.570951 [Byte1]: 66
7876 13:22:00.574780
7877 13:22:00.574860 Set Vref, RX VrefLevel [Byte0]: 67
7878 13:22:00.578429 [Byte1]: 67
7879 13:22:00.582544
7880 13:22:00.582624 Set Vref, RX VrefLevel [Byte0]: 68
7881 13:22:00.585747 [Byte1]: 68
7882 13:22:00.590205
7883 13:22:00.590285 Set Vref, RX VrefLevel [Byte0]: 69
7884 13:22:00.593898 [Byte1]: 69
7885 13:22:00.597691
7886 13:22:00.597771 Set Vref, RX VrefLevel [Byte0]: 70
7887 13:22:00.601246 [Byte1]: 70
7888 13:22:00.605794
7889 13:22:00.605875 Set Vref, RX VrefLevel [Byte0]: 71
7890 13:22:00.608592 [Byte1]: 71
7891 13:22:00.613145
7892 13:22:00.613239 Set Vref, RX VrefLevel [Byte0]: 72
7893 13:22:00.616412 [Byte1]: 72
7894 13:22:00.620543
7895 13:22:00.620624 Set Vref, RX VrefLevel [Byte0]: 73
7896 13:22:00.623832 [Byte1]: 73
7897 13:22:00.628334
7898 13:22:00.628415 Set Vref, RX VrefLevel [Byte0]: 74
7899 13:22:00.632119 [Byte1]: 74
7900 13:22:00.636043
7901 13:22:00.636124 Set Vref, RX VrefLevel [Byte0]: 75
7902 13:22:00.639537 [Byte1]: 75
7903 13:22:00.643539
7904 13:22:00.643620 Final RX Vref Byte 0 = 54 to rank0
7905 13:22:00.646848 Final RX Vref Byte 1 = 57 to rank0
7906 13:22:00.650717 Final RX Vref Byte 0 = 54 to rank1
7907 13:22:00.653725 Final RX Vref Byte 1 = 57 to rank1==
7908 13:22:00.656596 Dram Type= 6, Freq= 0, CH_0, rank 0
7909 13:22:00.663323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7910 13:22:00.663405 ==
7911 13:22:00.663470 DQS Delay:
7912 13:22:00.667004 DQS0 = 0, DQS1 = 0
7913 13:22:00.667084 DQM Delay:
7914 13:22:00.667148 DQM0 = 128, DQM1 = 124
7915 13:22:00.669717 DQ Delay:
7916 13:22:00.672895 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7917 13:22:00.676280 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
7918 13:22:00.679559 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7919 13:22:00.683095 DQ12 =132, DQ13 =130, DQ14 =134, DQ15 =132
7920 13:22:00.683176
7921 13:22:00.683239
7922 13:22:00.683298
7923 13:22:00.686478 [DramC_TX_OE_Calibration] TA2
7924 13:22:00.689439 Original DQ_B0 (3 6) =30, OEN = 27
7925 13:22:00.692662 Original DQ_B1 (3 6) =30, OEN = 27
7926 13:22:00.696205 24, 0x0, End_B0=24 End_B1=24
7927 13:22:00.699523 25, 0x0, End_B0=25 End_B1=25
7928 13:22:00.699605 26, 0x0, End_B0=26 End_B1=26
7929 13:22:00.702721 27, 0x0, End_B0=27 End_B1=27
7930 13:22:00.705896 28, 0x0, End_B0=28 End_B1=28
7931 13:22:00.709256 29, 0x0, End_B0=29 End_B1=29
7932 13:22:00.709338 30, 0x0, End_B0=30 End_B1=30
7933 13:22:00.712529 31, 0x4141, End_B0=30 End_B1=30
7934 13:22:00.716090 Byte0 end_step=30 best_step=27
7935 13:22:00.719371 Byte1 end_step=30 best_step=27
7936 13:22:00.722627 Byte0 TX OE(2T, 0.5T) = (3, 3)
7937 13:22:00.726259 Byte1 TX OE(2T, 0.5T) = (3, 3)
7938 13:22:00.726340
7939 13:22:00.726404
7940 13:22:00.732823 [DQSOSCAuto] RK0, (LSB)MR18= 0x1512, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
7941 13:22:00.735715 CH0 RK0: MR19=303, MR18=1512
7942 13:22:00.742402 CH0_RK0: MR19=0x303, MR18=0x1512, DQSOSC=399, MR23=63, INC=23, DEC=15
7943 13:22:00.742484
7944 13:22:00.745836 ----->DramcWriteLeveling(PI) begin...
7945 13:22:00.745919 ==
7946 13:22:00.749074 Dram Type= 6, Freq= 0, CH_0, rank 1
7947 13:22:00.752135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7948 13:22:00.752217 ==
7949 13:22:00.755440 Write leveling (Byte 0): 35 => 35
7950 13:22:00.759518 Write leveling (Byte 1): 25 => 25
7951 13:22:00.762212 DramcWriteLeveling(PI) end<-----
7952 13:22:00.762293
7953 13:22:00.762357 ==
7954 13:22:00.765267 Dram Type= 6, Freq= 0, CH_0, rank 1
7955 13:22:00.769127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7956 13:22:00.771939 ==
7957 13:22:00.772021 [Gating] SW mode calibration
7958 13:22:00.782658 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7959 13:22:00.785508 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7960 13:22:00.789063 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7961 13:22:00.795452 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7962 13:22:00.798605 1 4 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
7963 13:22:00.802166 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7964 13:22:00.808387 1 4 16 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
7965 13:22:00.811882 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7966 13:22:00.815267 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7967 13:22:00.821632 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7968 13:22:00.824697 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7969 13:22:00.828178 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7970 13:22:00.834983 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
7971 13:22:00.838509 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
7972 13:22:00.841383 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7973 13:22:00.848902 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
7974 13:22:00.851380 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7975 13:22:00.854575 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7976 13:22:00.861467 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7977 13:22:00.864501 1 6 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7978 13:22:00.868235 1 6 8 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7979 13:22:00.874240 1 6 12 | B1->B0 | 2323 4545 | 0 1 | (0 0) (0 0)
7980 13:22:00.877705 1 6 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
7981 13:22:00.881176 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7982 13:22:00.887512 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7983 13:22:00.891434 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7984 13:22:00.894494 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7985 13:22:00.900843 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7986 13:22:00.904258 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7987 13:22:00.907668 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7988 13:22:00.914462 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7989 13:22:00.917465 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7990 13:22:00.920996 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 13:22:00.927247 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 13:22:00.930523 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 13:22:00.933845 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 13:22:00.940161 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 13:22:00.943668 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 13:22:00.947016 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 13:22:00.953188 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 13:22:00.956665 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 13:22:00.960398 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 13:22:00.966761 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 13:22:00.969783 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8002 13:22:00.973247 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8003 13:22:00.979629 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8004 13:22:00.982986 Total UI for P1: 0, mck2ui 16
8005 13:22:00.986471 best dqsien dly found for B0: ( 1, 9, 6)
8006 13:22:00.989401 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8007 13:22:00.993111 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8008 13:22:00.999250 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 13:22:01.003570 Total UI for P1: 0, mck2ui 16
8010 13:22:01.006373 best dqsien dly found for B1: ( 1, 9, 20)
8011 13:22:01.009468 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8012 13:22:01.012881 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8013 13:22:01.012963
8014 13:22:01.016903 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8015 13:22:01.019310 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8016 13:22:01.022630 [Gating] SW calibration Done
8017 13:22:01.022711 ==
8018 13:22:01.026002 Dram Type= 6, Freq= 0, CH_0, rank 1
8019 13:22:01.029540 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8020 13:22:01.029646 ==
8021 13:22:01.032365 RX Vref Scan: 0
8022 13:22:01.032446
8023 13:22:01.036229 RX Vref 0 -> 0, step: 1
8024 13:22:01.036310
8025 13:22:01.036374 RX Delay 0 -> 252, step: 8
8026 13:22:01.042775 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8027 13:22:01.045490 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8028 13:22:01.049093 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8029 13:22:01.052301 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8030 13:22:01.055495 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8031 13:22:01.062272 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8032 13:22:01.065269 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8033 13:22:01.068570 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8034 13:22:01.072223 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8035 13:22:01.074975 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8036 13:22:01.081841 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8037 13:22:01.085559 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8038 13:22:01.088719 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8039 13:22:01.091812 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8040 13:22:01.098373 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8041 13:22:01.101379 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8042 13:22:01.101459 ==
8043 13:22:01.104846 Dram Type= 6, Freq= 0, CH_0, rank 1
8044 13:22:01.108082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8045 13:22:01.108162 ==
8046 13:22:01.111761 DQS Delay:
8047 13:22:01.111842 DQS0 = 0, DQS1 = 0
8048 13:22:01.111930 DQM Delay:
8049 13:22:01.114631 DQM0 = 130, DQM1 = 127
8050 13:22:01.114712 DQ Delay:
8051 13:22:01.118169 DQ0 =127, DQ1 =135, DQ2 =127, DQ3 =127
8052 13:22:01.121549 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
8053 13:22:01.127931 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
8054 13:22:01.130930 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8055 13:22:01.131011
8056 13:22:01.131075
8057 13:22:01.131134 ==
8058 13:22:01.134478 Dram Type= 6, Freq= 0, CH_0, rank 1
8059 13:22:01.137778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8060 13:22:01.137860 ==
8061 13:22:01.137925
8062 13:22:01.137984
8063 13:22:01.141343 TX Vref Scan disable
8064 13:22:01.144250 == TX Byte 0 ==
8065 13:22:01.147701 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8066 13:22:01.150661 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8067 13:22:01.154296 == TX Byte 1 ==
8068 13:22:01.157844 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8069 13:22:01.161224 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8070 13:22:01.161345 ==
8071 13:22:01.164347 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 13:22:01.167596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 13:22:01.170541 ==
8074 13:22:01.183000
8075 13:22:01.186344 TX Vref early break, caculate TX vref
8076 13:22:01.189581 TX Vref=16, minBit 2, minWin=23, winSum=380
8077 13:22:01.192451 TX Vref=18, minBit 13, minWin=23, winSum=387
8078 13:22:01.196355 TX Vref=20, minBit 4, minWin=24, winSum=396
8079 13:22:01.199045 TX Vref=22, minBit 2, minWin=24, winSum=400
8080 13:22:01.205696 TX Vref=24, minBit 1, minWin=25, winSum=408
8081 13:22:01.208832 TX Vref=26, minBit 3, minWin=25, winSum=415
8082 13:22:01.212342 TX Vref=28, minBit 10, minWin=25, winSum=417
8083 13:22:01.216029 TX Vref=30, minBit 2, minWin=25, winSum=413
8084 13:22:01.218959 TX Vref=32, minBit 1, minWin=24, winSum=403
8085 13:22:01.222104 TX Vref=34, minBit 0, minWin=24, winSum=395
8086 13:22:01.229524 [TxChooseVref] Worse bit 10, Min win 25, Win sum 417, Final Vref 28
8087 13:22:01.229605
8088 13:22:01.232611 Final TX Range 0 Vref 28
8089 13:22:01.232693
8090 13:22:01.232757 ==
8091 13:22:01.235913 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 13:22:01.239345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 13:22:01.239426 ==
8094 13:22:01.239490
8095 13:22:01.242206
8096 13:22:01.242285 TX Vref Scan disable
8097 13:22:01.249366 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8098 13:22:01.249451 == TX Byte 0 ==
8099 13:22:01.252188 u2DelayCellOfst[0]=10 cells (3 PI)
8100 13:22:01.255347 u2DelayCellOfst[1]=14 cells (4 PI)
8101 13:22:01.258692 u2DelayCellOfst[2]=7 cells (2 PI)
8102 13:22:01.261871 u2DelayCellOfst[3]=10 cells (3 PI)
8103 13:22:01.265185 u2DelayCellOfst[4]=7 cells (2 PI)
8104 13:22:01.268579 u2DelayCellOfst[5]=0 cells (0 PI)
8105 13:22:01.271864 u2DelayCellOfst[6]=14 cells (4 PI)
8106 13:22:01.275545 u2DelayCellOfst[7]=14 cells (4 PI)
8107 13:22:01.278345 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8108 13:22:01.281896 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8109 13:22:01.284840 == TX Byte 1 ==
8110 13:22:01.288373 u2DelayCellOfst[8]=0 cells (0 PI)
8111 13:22:01.291509 u2DelayCellOfst[9]=0 cells (0 PI)
8112 13:22:01.295068 u2DelayCellOfst[10]=3 cells (1 PI)
8113 13:22:01.298141 u2DelayCellOfst[11]=3 cells (1 PI)
8114 13:22:01.298223 u2DelayCellOfst[12]=7 cells (2 PI)
8115 13:22:01.301670 u2DelayCellOfst[13]=7 cells (2 PI)
8116 13:22:01.305021 u2DelayCellOfst[14]=14 cells (4 PI)
8117 13:22:01.308236 u2DelayCellOfst[15]=7 cells (2 PI)
8118 13:22:01.314451 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8119 13:22:01.317942 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8120 13:22:01.318023 DramC Write-DBI on
8121 13:22:01.321112 ==
8122 13:22:01.324496 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 13:22:01.327794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 13:22:01.327874 ==
8125 13:22:01.328005
8126 13:22:01.328066
8127 13:22:01.331093 TX Vref Scan disable
8128 13:22:01.331173 == TX Byte 0 ==
8129 13:22:01.337628 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8130 13:22:01.337708 == TX Byte 1 ==
8131 13:22:01.341527 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8132 13:22:01.344193 DramC Write-DBI off
8133 13:22:01.344273
8134 13:22:01.344336 [DATLAT]
8135 13:22:01.347868 Freq=1600, CH0 RK1
8136 13:22:01.347985
8137 13:22:01.348048 DATLAT Default: 0xf
8138 13:22:01.350747 0, 0xFFFF, sum = 0
8139 13:22:01.350829 1, 0xFFFF, sum = 0
8140 13:22:01.354305 2, 0xFFFF, sum = 0
8141 13:22:01.354394 3, 0xFFFF, sum = 0
8142 13:22:01.357924 4, 0xFFFF, sum = 0
8143 13:22:01.360689 5, 0xFFFF, sum = 0
8144 13:22:01.360776 6, 0xFFFF, sum = 0
8145 13:22:01.364085 7, 0xFFFF, sum = 0
8146 13:22:01.364167 8, 0xFFFF, sum = 0
8147 13:22:01.367436 9, 0xFFFF, sum = 0
8148 13:22:01.367518 10, 0xFFFF, sum = 0
8149 13:22:01.370364 11, 0xFFFF, sum = 0
8150 13:22:01.370446 12, 0xFFFF, sum = 0
8151 13:22:01.373780 13, 0xFFFF, sum = 0
8152 13:22:01.373861 14, 0x0, sum = 1
8153 13:22:01.377076 15, 0x0, sum = 2
8154 13:22:01.377149 16, 0x0, sum = 3
8155 13:22:01.380622 17, 0x0, sum = 4
8156 13:22:01.380704 best_step = 15
8157 13:22:01.380767
8158 13:22:01.380827 ==
8159 13:22:01.383528 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 13:22:01.387366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 13:22:01.390195 ==
8162 13:22:01.390280 RX Vref Scan: 0
8163 13:22:01.390344
8164 13:22:01.394110 RX Vref 0 -> 0, step: 1
8165 13:22:01.394190
8166 13:22:01.397377 RX Delay 11 -> 252, step: 4
8167 13:22:01.400115 iDelay=191, Bit 0, Center 124 (75 ~ 174) 100
8168 13:22:01.403884 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8169 13:22:01.407356 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8170 13:22:01.413672 iDelay=191, Bit 3, Center 124 (71 ~ 178) 108
8171 13:22:01.416431 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8172 13:22:01.419765 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8173 13:22:01.423451 iDelay=191, Bit 6, Center 136 (87 ~ 186) 100
8174 13:22:01.426444 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8175 13:22:01.432919 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8176 13:22:01.436298 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8177 13:22:01.440366 iDelay=191, Bit 10, Center 124 (71 ~ 178) 108
8178 13:22:01.443494 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8179 13:22:01.449798 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8180 13:22:01.452880 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8181 13:22:01.456156 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8182 13:22:01.459770 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8183 13:22:01.459850 ==
8184 13:22:01.462797 Dram Type= 6, Freq= 0, CH_0, rank 1
8185 13:22:01.469052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8186 13:22:01.469133 ==
8187 13:22:01.469197 DQS Delay:
8188 13:22:01.473379 DQS0 = 0, DQS1 = 0
8189 13:22:01.473460 DQM Delay:
8190 13:22:01.473524 DQM0 = 127, DQM1 = 124
8191 13:22:01.475768 DQ Delay:
8192 13:22:01.479054 DQ0 =124, DQ1 =130, DQ2 =122, DQ3 =124
8193 13:22:01.482723 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
8194 13:22:01.485568 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =120
8195 13:22:01.489072 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8196 13:22:01.489151
8197 13:22:01.489215
8198 13:22:01.489273
8199 13:22:01.492614 [DramC_TX_OE_Calibration] TA2
8200 13:22:01.495442 Original DQ_B0 (3 6) =30, OEN = 27
8201 13:22:01.498382 Original DQ_B1 (3 6) =30, OEN = 27
8202 13:22:01.501703 24, 0x0, End_B0=24 End_B1=24
8203 13:22:01.505365 25, 0x0, End_B0=25 End_B1=25
8204 13:22:01.505446 26, 0x0, End_B0=26 End_B1=26
8205 13:22:01.509118 27, 0x0, End_B0=27 End_B1=27
8206 13:22:01.512302 28, 0x0, End_B0=28 End_B1=28
8207 13:22:01.515239 29, 0x0, End_B0=29 End_B1=29
8208 13:22:01.518333 30, 0x0, End_B0=30 End_B1=30
8209 13:22:01.518415 31, 0x4141, End_B0=30 End_B1=30
8210 13:22:01.522567 Byte0 end_step=30 best_step=27
8211 13:22:01.525071 Byte1 end_step=30 best_step=27
8212 13:22:01.528176 Byte0 TX OE(2T, 0.5T) = (3, 3)
8213 13:22:01.531708 Byte1 TX OE(2T, 0.5T) = (3, 3)
8214 13:22:01.531790
8215 13:22:01.531854
8216 13:22:01.537777 [DQSOSCAuto] RK1, (LSB)MR18= 0x1715, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
8217 13:22:01.541108 CH0 RK1: MR19=303, MR18=1715
8218 13:22:01.547976 CH0_RK1: MR19=0x303, MR18=0x1715, DQSOSC=398, MR23=63, INC=23, DEC=15
8219 13:22:01.551085 [RxdqsGatingPostProcess] freq 1600
8220 13:22:01.557736 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8221 13:22:01.561012 best DQS0 dly(2T, 0.5T) = (1, 1)
8222 13:22:01.561093 best DQS1 dly(2T, 0.5T) = (1, 1)
8223 13:22:01.564563 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8224 13:22:01.567766 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8225 13:22:01.570967 best DQS0 dly(2T, 0.5T) = (1, 1)
8226 13:22:01.574207 best DQS1 dly(2T, 0.5T) = (1, 1)
8227 13:22:01.577805 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8228 13:22:01.580496 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8229 13:22:01.583895 Pre-setting of DQS Precalculation
8230 13:22:01.591065 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8231 13:22:01.591146 ==
8232 13:22:01.593701 Dram Type= 6, Freq= 0, CH_1, rank 0
8233 13:22:01.597692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8234 13:22:01.597772 ==
8235 13:22:01.603770 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8236 13:22:01.606932 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8237 13:22:01.611061 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8238 13:22:01.616759 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8239 13:22:01.625900 [CA 0] Center 42 (12~72) winsize 61
8240 13:22:01.628818 [CA 1] Center 42 (12~72) winsize 61
8241 13:22:01.632795 [CA 2] Center 38 (9~67) winsize 59
8242 13:22:01.635208 [CA 3] Center 37 (8~66) winsize 59
8243 13:22:01.638404 [CA 4] Center 37 (7~68) winsize 62
8244 13:22:01.641849 [CA 5] Center 36 (7~66) winsize 60
8245 13:22:01.641930
8246 13:22:01.645441 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8247 13:22:01.645522
8248 13:22:01.649243 [CATrainingPosCal] consider 1 rank data
8249 13:22:01.651677 u2DelayCellTimex100 = 271/100 ps
8250 13:22:01.658290 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8251 13:22:01.661600 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8252 13:22:01.664992 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8253 13:22:01.668327 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8254 13:22:01.671708 CA4 delay=37 (7~68),Diff = 1 PI (3 cell)
8255 13:22:01.674882 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8256 13:22:01.674962
8257 13:22:01.678401 CA PerBit enable=1, Macro0, CA PI delay=36
8258 13:22:01.678482
8259 13:22:01.681780 [CBTSetCACLKResult] CA Dly = 36
8260 13:22:01.684720 CS Dly: 8 (0~39)
8261 13:22:01.688148 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8262 13:22:01.691228 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8263 13:22:01.691308 ==
8264 13:22:01.694723 Dram Type= 6, Freq= 0, CH_1, rank 1
8265 13:22:01.701481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8266 13:22:01.701562 ==
8267 13:22:01.704436 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8268 13:22:01.711482 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8269 13:22:01.714560 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8270 13:22:01.721186 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8271 13:22:01.728398 [CA 0] Center 42 (12~72) winsize 61
8272 13:22:01.731709 [CA 1] Center 42 (12~72) winsize 61
8273 13:22:01.735060 [CA 2] Center 38 (9~68) winsize 60
8274 13:22:01.738306 [CA 3] Center 37 (8~67) winsize 60
8275 13:22:01.741781 [CA 4] Center 37 (8~67) winsize 60
8276 13:22:01.744912 [CA 5] Center 37 (7~67) winsize 61
8277 13:22:01.744995
8278 13:22:01.748082 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8279 13:22:01.748189
8280 13:22:01.754601 [CATrainingPosCal] consider 2 rank data
8281 13:22:01.754706 u2DelayCellTimex100 = 271/100 ps
8282 13:22:01.761381 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8283 13:22:01.765355 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8284 13:22:01.768130 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8285 13:22:01.771606 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8286 13:22:01.775075 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8287 13:22:01.778373 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8288 13:22:01.778454
8289 13:22:01.781017 CA PerBit enable=1, Macro0, CA PI delay=36
8290 13:22:01.781099
8291 13:22:01.784401 [CBTSetCACLKResult] CA Dly = 36
8292 13:22:01.788188 CS Dly: 9 (0~42)
8293 13:22:01.791077 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8294 13:22:01.794130 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8295 13:22:01.794211
8296 13:22:01.797622 ----->DramcWriteLeveling(PI) begin...
8297 13:22:01.797704 ==
8298 13:22:01.801214 Dram Type= 6, Freq= 0, CH_1, rank 0
8299 13:22:01.807348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 13:22:01.807430 ==
8301 13:22:01.810923 Write leveling (Byte 0): 25 => 25
8302 13:22:01.814339 Write leveling (Byte 1): 27 => 27
8303 13:22:01.817407 DramcWriteLeveling(PI) end<-----
8304 13:22:01.817503
8305 13:22:01.817590 ==
8306 13:22:01.820741 Dram Type= 6, Freq= 0, CH_1, rank 0
8307 13:22:01.824209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 13:22:01.824290 ==
8309 13:22:01.827414 [Gating] SW mode calibration
8310 13:22:01.833882 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8311 13:22:01.840405 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8312 13:22:01.843854 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8313 13:22:01.846801 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8314 13:22:01.853589 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8315 13:22:01.856793 1 4 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8316 13:22:01.860308 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 13:22:01.866651 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 13:22:01.870681 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 13:22:01.872898 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 13:22:01.879567 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8321 13:22:01.883094 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 13:22:01.886254 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8323 13:22:01.893211 1 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (1 0)
8324 13:22:01.896609 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8325 13:22:01.899852 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 13:22:01.905935 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 13:22:01.909244 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 13:22:01.913409 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 13:22:01.919163 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 13:22:01.922687 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8331 13:22:01.925987 1 6 12 | B1->B0 | 2c2c 4444 | 0 0 | (0 0) (0 0)
8332 13:22:01.932380 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 13:22:01.935924 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 13:22:01.939128 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 13:22:01.945661 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 13:22:01.949799 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 13:22:01.952585 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 13:22:01.958997 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8339 13:22:01.961980 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8340 13:22:01.965246 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8341 13:22:01.971941 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 13:22:01.975346 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 13:22:01.978654 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 13:22:01.984974 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 13:22:01.988326 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 13:22:01.991777 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 13:22:01.998018 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 13:22:02.001802 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 13:22:02.004704 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 13:22:02.011862 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 13:22:02.014413 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 13:22:02.017963 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 13:22:02.025038 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 13:22:02.027683 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8355 13:22:02.031340 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8356 13:22:02.038148 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8357 13:22:02.038236 Total UI for P1: 0, mck2ui 16
8358 13:22:02.044467 best dqsien dly found for B0: ( 1, 9, 10)
8359 13:22:02.047706 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 13:22:02.050980 Total UI for P1: 0, mck2ui 16
8361 13:22:02.054575 best dqsien dly found for B1: ( 1, 9, 14)
8362 13:22:02.057723 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8363 13:22:02.060812 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8364 13:22:02.060947
8365 13:22:02.064436 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8366 13:22:02.067398 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8367 13:22:02.070939 [Gating] SW calibration Done
8368 13:22:02.071113 ==
8369 13:22:02.074033 Dram Type= 6, Freq= 0, CH_1, rank 0
8370 13:22:02.080686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8371 13:22:02.080929 ==
8372 13:22:02.081120 RX Vref Scan: 0
8373 13:22:02.081299
8374 13:22:02.084174 RX Vref 0 -> 0, step: 1
8375 13:22:02.084472
8376 13:22:02.087496 RX Delay 0 -> 252, step: 8
8377 13:22:02.090860 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8378 13:22:02.094085 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8379 13:22:02.097370 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8380 13:22:02.100647 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8381 13:22:02.107197 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8382 13:22:02.110616 iDelay=208, Bit 5, Center 147 (96 ~ 199) 104
8383 13:22:02.114165 iDelay=208, Bit 6, Center 151 (96 ~ 207) 112
8384 13:22:02.117329 iDelay=208, Bit 7, Center 127 (72 ~ 183) 112
8385 13:22:02.120589 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8386 13:22:02.127174 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8387 13:22:02.131877 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8388 13:22:02.134078 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8389 13:22:02.136989 iDelay=208, Bit 12, Center 139 (88 ~ 191) 104
8390 13:22:02.144009 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8391 13:22:02.146802 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8392 13:22:02.150579 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8393 13:22:02.151136 ==
8394 13:22:02.153634 Dram Type= 6, Freq= 0, CH_1, rank 0
8395 13:22:02.156554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8396 13:22:02.159719 ==
8397 13:22:02.159825 DQS Delay:
8398 13:22:02.159943 DQS0 = 0, DQS1 = 0
8399 13:22:02.163132 DQM Delay:
8400 13:22:02.163212 DQM0 = 136, DQM1 = 132
8401 13:22:02.166649 DQ Delay:
8402 13:22:02.169218 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8403 13:22:02.172713 DQ4 =131, DQ5 =147, DQ6 =151, DQ7 =127
8404 13:22:02.175720 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8405 13:22:02.179316 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8406 13:22:02.179416
8407 13:22:02.179504
8408 13:22:02.179590 ==
8409 13:22:02.183009 Dram Type= 6, Freq= 0, CH_1, rank 0
8410 13:22:02.185806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8411 13:22:02.185886 ==
8412 13:22:02.189022
8413 13:22:02.189095
8414 13:22:02.189154 TX Vref Scan disable
8415 13:22:02.192525 == TX Byte 0 ==
8416 13:22:02.196062 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8417 13:22:02.199235 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8418 13:22:02.202426 == TX Byte 1 ==
8419 13:22:02.205195 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8420 13:22:02.208830 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8421 13:22:02.211694 ==
8422 13:22:02.215624 Dram Type= 6, Freq= 0, CH_1, rank 0
8423 13:22:02.219514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8424 13:22:02.219597 ==
8425 13:22:02.231681
8426 13:22:02.234725 TX Vref early break, caculate TX vref
8427 13:22:02.238074 TX Vref=16, minBit 8, minWin=21, winSum=366
8428 13:22:02.241430 TX Vref=18, minBit 8, minWin=22, winSum=374
8429 13:22:02.244788 TX Vref=20, minBit 8, minWin=23, winSum=389
8430 13:22:02.248193 TX Vref=22, minBit 8, minWin=23, winSum=398
8431 13:22:02.252597 TX Vref=24, minBit 3, minWin=24, winSum=404
8432 13:22:02.258434 TX Vref=26, minBit 9, minWin=24, winSum=413
8433 13:22:02.261382 TX Vref=28, minBit 0, minWin=25, winSum=412
8434 13:22:02.264322 TX Vref=30, minBit 9, minWin=24, winSum=410
8435 13:22:02.268348 TX Vref=32, minBit 9, minWin=24, winSum=406
8436 13:22:02.271365 TX Vref=34, minBit 0, minWin=24, winSum=396
8437 13:22:02.278067 TX Vref=36, minBit 0, minWin=23, winSum=384
8438 13:22:02.281022 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 28
8439 13:22:02.281104
8440 13:22:02.284057 Final TX Range 0 Vref 28
8441 13:22:02.284139
8442 13:22:02.284206 ==
8443 13:22:02.287466 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 13:22:02.291155 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 13:22:02.293887 ==
8446 13:22:02.293968
8447 13:22:02.294031
8448 13:22:02.294090 TX Vref Scan disable
8449 13:22:02.301086 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8450 13:22:02.301167 == TX Byte 0 ==
8451 13:22:02.305000 u2DelayCellOfst[0]=14 cells (4 PI)
8452 13:22:02.307391 u2DelayCellOfst[1]=10 cells (3 PI)
8453 13:22:02.310803 u2DelayCellOfst[2]=0 cells (0 PI)
8454 13:22:02.314085 u2DelayCellOfst[3]=7 cells (2 PI)
8455 13:22:02.317637 u2DelayCellOfst[4]=7 cells (2 PI)
8456 13:22:02.320967 u2DelayCellOfst[5]=18 cells (5 PI)
8457 13:22:02.324142 u2DelayCellOfst[6]=14 cells (4 PI)
8458 13:22:02.327231 u2DelayCellOfst[7]=7 cells (2 PI)
8459 13:22:02.330683 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8460 13:22:02.334345 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8461 13:22:02.336961 == TX Byte 1 ==
8462 13:22:02.340557 u2DelayCellOfst[8]=0 cells (0 PI)
8463 13:22:02.343748 u2DelayCellOfst[9]=3 cells (1 PI)
8464 13:22:02.346837 u2DelayCellOfst[10]=10 cells (3 PI)
8465 13:22:02.350033 u2DelayCellOfst[11]=7 cells (2 PI)
8466 13:22:02.353614 u2DelayCellOfst[12]=14 cells (4 PI)
8467 13:22:02.356636 u2DelayCellOfst[13]=14 cells (4 PI)
8468 13:22:02.360896 u2DelayCellOfst[14]=18 cells (5 PI)
8469 13:22:02.360977 u2DelayCellOfst[15]=18 cells (5 PI)
8470 13:22:02.367044 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8471 13:22:02.370131 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8472 13:22:02.373318 DramC Write-DBI on
8473 13:22:02.373399 ==
8474 13:22:02.376653 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 13:22:02.379990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 13:22:02.380103 ==
8477 13:22:02.380202
8478 13:22:02.380292
8479 13:22:02.383267 TX Vref Scan disable
8480 13:22:02.383340 == TX Byte 0 ==
8481 13:22:02.389886 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8482 13:22:02.389994 == TX Byte 1 ==
8483 13:22:02.393341 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8484 13:22:02.396877 DramC Write-DBI off
8485 13:22:02.396950
8486 13:22:02.397014 [DATLAT]
8487 13:22:02.399608 Freq=1600, CH1 RK0
8488 13:22:02.399676
8489 13:22:02.399758 DATLAT Default: 0xf
8490 13:22:02.403692 0, 0xFFFF, sum = 0
8491 13:22:02.403791 1, 0xFFFF, sum = 0
8492 13:22:02.406560 2, 0xFFFF, sum = 0
8493 13:22:02.409695 3, 0xFFFF, sum = 0
8494 13:22:02.409795 4, 0xFFFF, sum = 0
8495 13:22:02.413360 5, 0xFFFF, sum = 0
8496 13:22:02.413430 6, 0xFFFF, sum = 0
8497 13:22:02.416263 7, 0xFFFF, sum = 0
8498 13:22:02.416332 8, 0xFFFF, sum = 0
8499 13:22:02.419427 9, 0xFFFF, sum = 0
8500 13:22:02.419496 10, 0xFFFF, sum = 0
8501 13:22:02.422897 11, 0xFFFF, sum = 0
8502 13:22:02.422982 12, 0xFFFF, sum = 0
8503 13:22:02.425998 13, 0xFFFF, sum = 0
8504 13:22:02.426068 14, 0x0, sum = 1
8505 13:22:02.429453 15, 0x0, sum = 2
8506 13:22:02.429551 16, 0x0, sum = 3
8507 13:22:02.432610 17, 0x0, sum = 4
8508 13:22:02.432709 best_step = 15
8509 13:22:02.432800
8510 13:22:02.432885 ==
8511 13:22:02.436543 Dram Type= 6, Freq= 0, CH_1, rank 0
8512 13:22:02.442480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8513 13:22:02.442585 ==
8514 13:22:02.442675 RX Vref Scan: 1
8515 13:22:02.442763
8516 13:22:02.446268 Set Vref Range= 24 -> 127
8517 13:22:02.446364
8518 13:22:02.448981 RX Vref 24 -> 127, step: 1
8519 13:22:02.449059
8520 13:22:02.449119 RX Delay 19 -> 252, step: 4
8521 13:22:02.449178
8522 13:22:02.452703 Set Vref, RX VrefLevel [Byte0]: 24
8523 13:22:02.455728 [Byte1]: 24
8524 13:22:02.460079
8525 13:22:02.460154 Set Vref, RX VrefLevel [Byte0]: 25
8526 13:22:02.463203 [Byte1]: 25
8527 13:22:02.467888
8528 13:22:02.467970 Set Vref, RX VrefLevel [Byte0]: 26
8529 13:22:02.470875 [Byte1]: 26
8530 13:22:02.475096
8531 13:22:02.475197 Set Vref, RX VrefLevel [Byte0]: 27
8532 13:22:02.478640 [Byte1]: 27
8533 13:22:02.482810
8534 13:22:02.482913 Set Vref, RX VrefLevel [Byte0]: 28
8535 13:22:02.486012 [Byte1]: 28
8536 13:22:02.490079
8537 13:22:02.490177 Set Vref, RX VrefLevel [Byte0]: 29
8538 13:22:02.493262 [Byte1]: 29
8539 13:22:02.498337
8540 13:22:02.498440 Set Vref, RX VrefLevel [Byte0]: 30
8541 13:22:02.501352 [Byte1]: 30
8542 13:22:02.505295
8543 13:22:02.505369 Set Vref, RX VrefLevel [Byte0]: 31
8544 13:22:02.508518 [Byte1]: 31
8545 13:22:02.512774
8546 13:22:02.512847 Set Vref, RX VrefLevel [Byte0]: 32
8547 13:22:02.516210 [Byte1]: 32
8548 13:22:02.520190
8549 13:22:02.520288 Set Vref, RX VrefLevel [Byte0]: 33
8550 13:22:02.524127 [Byte1]: 33
8551 13:22:02.528258
8552 13:22:02.528335 Set Vref, RX VrefLevel [Byte0]: 34
8553 13:22:02.531448 [Byte1]: 34
8554 13:22:02.535782
8555 13:22:02.535883 Set Vref, RX VrefLevel [Byte0]: 35
8556 13:22:02.539376 [Byte1]: 35
8557 13:22:02.543172
8558 13:22:02.543273 Set Vref, RX VrefLevel [Byte0]: 36
8559 13:22:02.546928 [Byte1]: 36
8560 13:22:02.550523
8561 13:22:02.553792 Set Vref, RX VrefLevel [Byte0]: 37
8562 13:22:02.557245 [Byte1]: 37
8563 13:22:02.557321
8564 13:22:02.560914 Set Vref, RX VrefLevel [Byte0]: 38
8565 13:22:02.563744 [Byte1]: 38
8566 13:22:02.563843
8567 13:22:02.567309 Set Vref, RX VrefLevel [Byte0]: 39
8568 13:22:02.570426 [Byte1]: 39
8569 13:22:02.570526
8570 13:22:02.575039 Set Vref, RX VrefLevel [Byte0]: 40
8571 13:22:02.577824 [Byte1]: 40
8572 13:22:02.581263
8573 13:22:02.581357 Set Vref, RX VrefLevel [Byte0]: 41
8574 13:22:02.584362 [Byte1]: 41
8575 13:22:02.588361
8576 13:22:02.588433 Set Vref, RX VrefLevel [Byte0]: 42
8577 13:22:02.591657 [Byte1]: 42
8578 13:22:02.596282
8579 13:22:02.596359 Set Vref, RX VrefLevel [Byte0]: 43
8580 13:22:02.599512 [Byte1]: 43
8581 13:22:02.603864
8582 13:22:02.604004 Set Vref, RX VrefLevel [Byte0]: 44
8583 13:22:02.607666 [Byte1]: 44
8584 13:22:02.611407
8585 13:22:02.611505 Set Vref, RX VrefLevel [Byte0]: 45
8586 13:22:02.614945 [Byte1]: 45
8587 13:22:02.619151
8588 13:22:02.619224 Set Vref, RX VrefLevel [Byte0]: 46
8589 13:22:02.622333 [Byte1]: 46
8590 13:22:02.626573
8591 13:22:02.626670 Set Vref, RX VrefLevel [Byte0]: 47
8592 13:22:02.629829 [Byte1]: 47
8593 13:22:02.633752
8594 13:22:02.633825 Set Vref, RX VrefLevel [Byte0]: 48
8595 13:22:02.637261 [Byte1]: 48
8596 13:22:02.641713
8597 13:22:02.641794 Set Vref, RX VrefLevel [Byte0]: 49
8598 13:22:02.645353 [Byte1]: 49
8599 13:22:02.649301
8600 13:22:02.649382 Set Vref, RX VrefLevel [Byte0]: 50
8601 13:22:02.653709 [Byte1]: 50
8602 13:22:02.656816
8603 13:22:02.656897 Set Vref, RX VrefLevel [Byte0]: 51
8604 13:22:02.660588 [Byte1]: 51
8605 13:22:02.664166
8606 13:22:02.664246 Set Vref, RX VrefLevel [Byte0]: 52
8607 13:22:02.667405 [Byte1]: 52
8608 13:22:02.671837
8609 13:22:02.671954 Set Vref, RX VrefLevel [Byte0]: 53
8610 13:22:02.675177 [Byte1]: 53
8611 13:22:02.679511
8612 13:22:02.679592 Set Vref, RX VrefLevel [Byte0]: 54
8613 13:22:02.682916 [Byte1]: 54
8614 13:22:02.686904
8615 13:22:02.686985 Set Vref, RX VrefLevel [Byte0]: 55
8616 13:22:02.690470 [Byte1]: 55
8617 13:22:02.695062
8618 13:22:02.695143 Set Vref, RX VrefLevel [Byte0]: 56
8619 13:22:02.697986 [Byte1]: 56
8620 13:22:02.702059
8621 13:22:02.702140 Set Vref, RX VrefLevel [Byte0]: 57
8622 13:22:02.705485 [Byte1]: 57
8623 13:22:02.709693
8624 13:22:02.709774 Set Vref, RX VrefLevel [Byte0]: 58
8625 13:22:02.713394 [Byte1]: 58
8626 13:22:02.717423
8627 13:22:02.717504 Set Vref, RX VrefLevel [Byte0]: 59
8628 13:22:02.720697 [Byte1]: 59
8629 13:22:02.725002
8630 13:22:02.725083 Set Vref, RX VrefLevel [Byte0]: 60
8631 13:22:02.727928 [Byte1]: 60
8632 13:22:02.732587
8633 13:22:02.732668 Set Vref, RX VrefLevel [Byte0]: 61
8634 13:22:02.735675 [Byte1]: 61
8635 13:22:02.740043
8636 13:22:02.740124 Set Vref, RX VrefLevel [Byte0]: 62
8637 13:22:02.743520 [Byte1]: 62
8638 13:22:02.747834
8639 13:22:02.747976 Set Vref, RX VrefLevel [Byte0]: 63
8640 13:22:02.751467 [Byte1]: 63
8641 13:22:02.755237
8642 13:22:02.755344 Set Vref, RX VrefLevel [Byte0]: 64
8643 13:22:02.758472 [Byte1]: 64
8644 13:22:02.763112
8645 13:22:02.763193 Set Vref, RX VrefLevel [Byte0]: 65
8646 13:22:02.766019 [Byte1]: 65
8647 13:22:02.770596
8648 13:22:02.770678 Set Vref, RX VrefLevel [Byte0]: 66
8649 13:22:02.773650 [Byte1]: 66
8650 13:22:02.777737
8651 13:22:02.777818 Set Vref, RX VrefLevel [Byte0]: 67
8652 13:22:02.784425 [Byte1]: 67
8653 13:22:02.784501
8654 13:22:02.788130 Set Vref, RX VrefLevel [Byte0]: 68
8655 13:22:02.790825 [Byte1]: 68
8656 13:22:02.790909
8657 13:22:02.794107 Set Vref, RX VrefLevel [Byte0]: 69
8658 13:22:02.797549 [Byte1]: 69
8659 13:22:02.797651
8660 13:22:02.801209 Set Vref, RX VrefLevel [Byte0]: 70
8661 13:22:02.803992 [Byte1]: 70
8662 13:22:02.808140
8663 13:22:02.808214 Final RX Vref Byte 0 = 56 to rank0
8664 13:22:02.811376 Final RX Vref Byte 1 = 60 to rank0
8665 13:22:02.814750 Final RX Vref Byte 0 = 56 to rank1
8666 13:22:02.817874 Final RX Vref Byte 1 = 60 to rank1==
8667 13:22:02.821401 Dram Type= 6, Freq= 0, CH_1, rank 0
8668 13:22:02.827937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8669 13:22:02.828027 ==
8670 13:22:02.828089 DQS Delay:
8671 13:22:02.831787 DQS0 = 0, DQS1 = 0
8672 13:22:02.831885 DQM Delay:
8673 13:22:02.832013 DQM0 = 133, DQM1 = 130
8674 13:22:02.834683 DQ Delay:
8675 13:22:02.837724 DQ0 =140, DQ1 =130, DQ2 =118, DQ3 =132
8676 13:22:02.841290 DQ4 =130, DQ5 =142, DQ6 =146, DQ7 =126
8677 13:22:02.844532 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =122
8678 13:22:02.848261 DQ12 =142, DQ13 =140, DQ14 =136, DQ15 =140
8679 13:22:02.848337
8680 13:22:02.848398
8681 13:22:02.848457
8682 13:22:02.851345 [DramC_TX_OE_Calibration] TA2
8683 13:22:02.854780 Original DQ_B0 (3 6) =30, OEN = 27
8684 13:22:02.858103 Original DQ_B1 (3 6) =30, OEN = 27
8685 13:22:02.861016 24, 0x0, End_B0=24 End_B1=24
8686 13:22:02.861094 25, 0x0, End_B0=25 End_B1=25
8687 13:22:02.864256 26, 0x0, End_B0=26 End_B1=26
8688 13:22:02.867681 27, 0x0, End_B0=27 End_B1=27
8689 13:22:02.870845 28, 0x0, End_B0=28 End_B1=28
8690 13:22:02.874284 29, 0x0, End_B0=29 End_B1=29
8691 13:22:02.874384 30, 0x0, End_B0=30 End_B1=30
8692 13:22:02.877914 31, 0x4141, End_B0=30 End_B1=30
8693 13:22:02.880767 Byte0 end_step=30 best_step=27
8694 13:22:02.883770 Byte1 end_step=30 best_step=27
8695 13:22:02.887494 Byte0 TX OE(2T, 0.5T) = (3, 3)
8696 13:22:02.890896 Byte1 TX OE(2T, 0.5T) = (3, 3)
8697 13:22:02.890990
8698 13:22:02.891076
8699 13:22:02.897078 [DQSOSCAuto] RK0, (LSB)MR18= 0xe18, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
8700 13:22:02.900842 CH1 RK0: MR19=303, MR18=E18
8701 13:22:02.907041 CH1_RK0: MR19=0x303, MR18=0xE18, DQSOSC=397, MR23=63, INC=23, DEC=15
8702 13:22:02.907146
8703 13:22:02.910282 ----->DramcWriteLeveling(PI) begin...
8704 13:22:02.910382 ==
8705 13:22:02.913958 Dram Type= 6, Freq= 0, CH_1, rank 1
8706 13:22:02.917503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8707 13:22:02.917575 ==
8708 13:22:02.920274 Write leveling (Byte 0): 25 => 25
8709 13:22:02.923568 Write leveling (Byte 1): 25 => 25
8710 13:22:02.926919 DramcWriteLeveling(PI) end<-----
8711 13:22:02.926992
8712 13:22:02.927053 ==
8713 13:22:02.930314 Dram Type= 6, Freq= 0, CH_1, rank 1
8714 13:22:02.933339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8715 13:22:02.933434 ==
8716 13:22:02.937029 [Gating] SW mode calibration
8717 13:22:02.943342 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8718 13:22:02.949749 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8719 13:22:02.953441 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8720 13:22:02.959800 1 4 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
8721 13:22:02.963319 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8722 13:22:02.966917 1 4 12 | B1->B0 | 2b2a 3434 | 1 1 | (0 0) (1 1)
8723 13:22:02.973038 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8724 13:22:02.976284 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8725 13:22:02.979920 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8726 13:22:02.986443 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8727 13:22:02.989685 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8728 13:22:02.992452 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8729 13:22:02.999347 1 5 8 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
8730 13:22:03.002203 1 5 12 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8731 13:22:03.005691 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8732 13:22:03.012475 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8733 13:22:03.015789 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8734 13:22:03.019017 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8735 13:22:03.025373 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8736 13:22:03.028692 1 6 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8737 13:22:03.032580 1 6 8 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8738 13:22:03.038854 1 6 12 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
8739 13:22:03.042062 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8740 13:22:03.045188 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8741 13:22:03.052142 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8742 13:22:03.055403 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8743 13:22:03.058432 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8744 13:22:03.065112 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8745 13:22:03.068525 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8746 13:22:03.072100 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8747 13:22:03.078205 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8748 13:22:03.082148 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8749 13:22:03.084887 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8750 13:22:03.091256 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8751 13:22:03.094848 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8752 13:22:03.098272 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8753 13:22:03.104407 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8754 13:22:03.107838 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8755 13:22:03.111128 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8756 13:22:03.117840 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8757 13:22:03.121514 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 13:22:03.125033 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 13:22:03.131512 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 13:22:03.134723 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8761 13:22:03.137948 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8762 13:22:03.144634 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8763 13:22:03.147674 Total UI for P1: 0, mck2ui 16
8764 13:22:03.150918 best dqsien dly found for B0: ( 1, 9, 6)
8765 13:22:03.154842 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 13:22:03.157366 Total UI for P1: 0, mck2ui 16
8767 13:22:03.160684 best dqsien dly found for B1: ( 1, 9, 10)
8768 13:22:03.164111 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8769 13:22:03.167404 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8770 13:22:03.167499
8771 13:22:03.170783 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8772 13:22:03.173992 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8773 13:22:03.177272 [Gating] SW calibration Done
8774 13:22:03.177342 ==
8775 13:22:03.180533 Dram Type= 6, Freq= 0, CH_1, rank 1
8776 13:22:03.187333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8777 13:22:03.187404 ==
8778 13:22:03.187464 RX Vref Scan: 0
8779 13:22:03.187531
8780 13:22:03.190776 RX Vref 0 -> 0, step: 1
8781 13:22:03.190868
8782 13:22:03.193727 RX Delay 0 -> 252, step: 8
8783 13:22:03.196945 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8784 13:22:03.201015 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8785 13:22:03.204018 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8786 13:22:03.209965 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8787 13:22:03.213467 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8788 13:22:03.216679 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8789 13:22:03.220400 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8790 13:22:03.223472 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8791 13:22:03.229799 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8792 13:22:03.233278 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8793 13:22:03.236255 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8794 13:22:03.239532 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8795 13:22:03.243843 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8796 13:22:03.249685 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8797 13:22:03.252905 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8798 13:22:03.256720 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8799 13:22:03.256802 ==
8800 13:22:03.259647 Dram Type= 6, Freq= 0, CH_1, rank 1
8801 13:22:03.262628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8802 13:22:03.266072 ==
8803 13:22:03.266154 DQS Delay:
8804 13:22:03.266217 DQS0 = 0, DQS1 = 0
8805 13:22:03.269337 DQM Delay:
8806 13:22:03.269418 DQM0 = 135, DQM1 = 131
8807 13:22:03.272684 DQ Delay:
8808 13:22:03.276752 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8809 13:22:03.279030 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =135
8810 13:22:03.282413 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8811 13:22:03.285756 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8812 13:22:03.285837
8813 13:22:03.285901
8814 13:22:03.285960 ==
8815 13:22:03.289309 Dram Type= 6, Freq= 0, CH_1, rank 1
8816 13:22:03.292564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8817 13:22:03.295401 ==
8818 13:22:03.295482
8819 13:22:03.295547
8820 13:22:03.295606 TX Vref Scan disable
8821 13:22:03.298684 == TX Byte 0 ==
8822 13:22:03.302337 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8823 13:22:03.306144 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8824 13:22:03.308582 == TX Byte 1 ==
8825 13:22:03.312463 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8826 13:22:03.315406 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8827 13:22:03.318660 ==
8828 13:22:03.321668 Dram Type= 6, Freq= 0, CH_1, rank 1
8829 13:22:03.325583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8830 13:22:03.325665 ==
8831 13:22:03.339057
8832 13:22:03.342676 TX Vref early break, caculate TX vref
8833 13:22:03.346080 TX Vref=16, minBit 9, minWin=21, winSum=377
8834 13:22:03.349803 TX Vref=18, minBit 9, minWin=22, winSum=384
8835 13:22:03.353091 TX Vref=20, minBit 9, minWin=22, winSum=390
8836 13:22:03.356437 TX Vref=22, minBit 9, minWin=22, winSum=398
8837 13:22:03.359075 TX Vref=24, minBit 9, minWin=24, winSum=407
8838 13:22:03.365522 TX Vref=26, minBit 9, minWin=24, winSum=415
8839 13:22:03.368886 TX Vref=28, minBit 3, minWin=25, winSum=415
8840 13:22:03.372663 TX Vref=30, minBit 8, minWin=25, winSum=417
8841 13:22:03.375409 TX Vref=32, minBit 0, minWin=25, winSum=413
8842 13:22:03.378502 TX Vref=34, minBit 9, minWin=23, winSum=403
8843 13:22:03.385267 TX Vref=36, minBit 0, minWin=24, winSum=398
8844 13:22:03.388682 TX Vref=38, minBit 0, minWin=23, winSum=384
8845 13:22:03.391873 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 30
8846 13:22:03.395793
8847 13:22:03.395872 Final TX Range 0 Vref 30
8848 13:22:03.395953
8849 13:22:03.396014 ==
8850 13:22:03.398718 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 13:22:03.405013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 13:22:03.405094 ==
8853 13:22:03.405156
8854 13:22:03.405214
8855 13:22:03.405270 TX Vref Scan disable
8856 13:22:03.412623 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8857 13:22:03.412703 == TX Byte 0 ==
8858 13:22:03.415726 u2DelayCellOfst[0]=18 cells (5 PI)
8859 13:22:03.418999 u2DelayCellOfst[1]=10 cells (3 PI)
8860 13:22:03.421998 u2DelayCellOfst[2]=0 cells (0 PI)
8861 13:22:03.425747 u2DelayCellOfst[3]=3 cells (1 PI)
8862 13:22:03.428490 u2DelayCellOfst[4]=7 cells (2 PI)
8863 13:22:03.432494 u2DelayCellOfst[5]=14 cells (4 PI)
8864 13:22:03.435198 u2DelayCellOfst[6]=14 cells (4 PI)
8865 13:22:03.438782 u2DelayCellOfst[7]=7 cells (2 PI)
8866 13:22:03.442169 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8867 13:22:03.445158 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8868 13:22:03.448660 == TX Byte 1 ==
8869 13:22:03.452106 u2DelayCellOfst[8]=0 cells (0 PI)
8870 13:22:03.454992 u2DelayCellOfst[9]=3 cells (1 PI)
8871 13:22:03.458638 u2DelayCellOfst[10]=14 cells (4 PI)
8872 13:22:03.461694 u2DelayCellOfst[11]=7 cells (2 PI)
8873 13:22:03.465318 u2DelayCellOfst[12]=18 cells (5 PI)
8874 13:22:03.468161 u2DelayCellOfst[13]=18 cells (5 PI)
8875 13:22:03.468241 u2DelayCellOfst[14]=21 cells (6 PI)
8876 13:22:03.472042 u2DelayCellOfst[15]=21 cells (6 PI)
8877 13:22:03.478242 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8878 13:22:03.481722 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8879 13:22:03.484817 DramC Write-DBI on
8880 13:22:03.484897 ==
8881 13:22:03.487746 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 13:22:03.491052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 13:22:03.491132 ==
8884 13:22:03.491195
8885 13:22:03.491254
8886 13:22:03.494866 TX Vref Scan disable
8887 13:22:03.494946 == TX Byte 0 ==
8888 13:22:03.501040 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8889 13:22:03.501122 == TX Byte 1 ==
8890 13:22:03.507412 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8891 13:22:03.507494 DramC Write-DBI off
8892 13:22:03.507559
8893 13:22:03.507619 [DATLAT]
8894 13:22:03.511470 Freq=1600, CH1 RK1
8895 13:22:03.511554
8896 13:22:03.514230 DATLAT Default: 0xf
8897 13:22:03.514312 0, 0xFFFF, sum = 0
8898 13:22:03.517525 1, 0xFFFF, sum = 0
8899 13:22:03.517607 2, 0xFFFF, sum = 0
8900 13:22:03.520943 3, 0xFFFF, sum = 0
8901 13:22:03.521026 4, 0xFFFF, sum = 0
8902 13:22:03.524332 5, 0xFFFF, sum = 0
8903 13:22:03.524415 6, 0xFFFF, sum = 0
8904 13:22:03.527537 7, 0xFFFF, sum = 0
8905 13:22:03.527620 8, 0xFFFF, sum = 0
8906 13:22:03.530822 9, 0xFFFF, sum = 0
8907 13:22:03.530905 10, 0xFFFF, sum = 0
8908 13:22:03.534148 11, 0xFFFF, sum = 0
8909 13:22:03.534230 12, 0xFFFF, sum = 0
8910 13:22:03.537539 13, 0xFFFF, sum = 0
8911 13:22:03.537621 14, 0x0, sum = 1
8912 13:22:03.540846 15, 0x0, sum = 2
8913 13:22:03.540929 16, 0x0, sum = 3
8914 13:22:03.543760 17, 0x0, sum = 4
8915 13:22:03.543843 best_step = 15
8916 13:22:03.543914
8917 13:22:03.544006 ==
8918 13:22:03.547166 Dram Type= 6, Freq= 0, CH_1, rank 1
8919 13:22:03.554036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8920 13:22:03.554118 ==
8921 13:22:03.554182 RX Vref Scan: 0
8922 13:22:03.554243
8923 13:22:03.556927 RX Vref 0 -> 0, step: 1
8924 13:22:03.557009
8925 13:22:03.561180 RX Delay 19 -> 252, step: 4
8926 13:22:03.563720 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8927 13:22:03.566897 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8928 13:22:03.574896 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8929 13:22:03.577257 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8930 13:22:03.580090 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8931 13:22:03.584125 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8932 13:22:03.587165 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8933 13:22:03.593641 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8934 13:22:03.596329 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8935 13:22:03.599602 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8936 13:22:03.603026 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8937 13:22:03.606188 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8938 13:22:03.612996 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8939 13:22:03.616984 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8940 13:22:03.620441 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8941 13:22:03.623042 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8942 13:22:03.623124 ==
8943 13:22:03.626231 Dram Type= 6, Freq= 0, CH_1, rank 1
8944 13:22:03.633330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8945 13:22:03.633413 ==
8946 13:22:03.633478 DQS Delay:
8947 13:22:03.636928 DQS0 = 0, DQS1 = 0
8948 13:22:03.637009 DQM Delay:
8949 13:22:03.637073 DQM0 = 133, DQM1 = 127
8950 13:22:03.639326 DQ Delay:
8951 13:22:03.642999 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =130
8952 13:22:03.645956 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =130
8953 13:22:03.649469 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
8954 13:22:03.652749 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =136
8955 13:22:03.652834
8956 13:22:03.652898
8957 13:22:03.652958
8958 13:22:03.656360 [DramC_TX_OE_Calibration] TA2
8959 13:22:03.659396 Original DQ_B0 (3 6) =30, OEN = 27
8960 13:22:03.662712 Original DQ_B1 (3 6) =30, OEN = 27
8961 13:22:03.666235 24, 0x0, End_B0=24 End_B1=24
8962 13:22:03.668928 25, 0x0, End_B0=25 End_B1=25
8963 13:22:03.669010 26, 0x0, End_B0=26 End_B1=26
8964 13:22:03.672191 27, 0x0, End_B0=27 End_B1=27
8965 13:22:03.675753 28, 0x0, End_B0=28 End_B1=28
8966 13:22:03.679788 29, 0x0, End_B0=29 End_B1=29
8967 13:22:03.679898 30, 0x0, End_B0=30 End_B1=30
8968 13:22:03.682129 31, 0x4141, End_B0=30 End_B1=30
8969 13:22:03.686010 Byte0 end_step=30 best_step=27
8970 13:22:03.688932 Byte1 end_step=30 best_step=27
8971 13:22:03.692223 Byte0 TX OE(2T, 0.5T) = (3, 3)
8972 13:22:03.695211 Byte1 TX OE(2T, 0.5T) = (3, 3)
8973 13:22:03.695293
8974 13:22:03.695357
8975 13:22:03.701819 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
8976 13:22:03.705241 CH1 RK1: MR19=303, MR18=E1C
8977 13:22:03.711893 CH1_RK1: MR19=0x303, MR18=0xE1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8978 13:22:03.716114 [RxdqsGatingPostProcess] freq 1600
8979 13:22:03.718319 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8980 13:22:03.721784 best DQS0 dly(2T, 0.5T) = (1, 1)
8981 13:22:03.725328 best DQS1 dly(2T, 0.5T) = (1, 1)
8982 13:22:03.728328 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8983 13:22:03.731437 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8984 13:22:03.735544 best DQS0 dly(2T, 0.5T) = (1, 1)
8985 13:22:03.738366 best DQS1 dly(2T, 0.5T) = (1, 1)
8986 13:22:03.741500 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8987 13:22:03.745065 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8988 13:22:03.748360 Pre-setting of DQS Precalculation
8989 13:22:03.751375 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8990 13:22:03.761561 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8991 13:22:03.767942 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8992 13:22:03.768024
8993 13:22:03.768090
8994 13:22:03.771743 [Calibration Summary] 3200 Mbps
8995 13:22:03.771824 CH 0, Rank 0
8996 13:22:03.774464 SW Impedance : PASS
8997 13:22:03.774546 DUTY Scan : NO K
8998 13:22:03.778374 ZQ Calibration : PASS
8999 13:22:03.781290 Jitter Meter : NO K
9000 13:22:03.781371 CBT Training : PASS
9001 13:22:03.785035 Write leveling : PASS
9002 13:22:03.787829 RX DQS gating : PASS
9003 13:22:03.787975 RX DQ/DQS(RDDQC) : PASS
9004 13:22:03.790921 TX DQ/DQS : PASS
9005 13:22:03.794258 RX DATLAT : PASS
9006 13:22:03.794340 RX DQ/DQS(Engine): PASS
9007 13:22:03.798562 TX OE : PASS
9008 13:22:03.798645 All Pass.
9009 13:22:03.798710
9010 13:22:03.800843 CH 0, Rank 1
9011 13:22:03.800956 SW Impedance : PASS
9012 13:22:03.804154 DUTY Scan : NO K
9013 13:22:03.808059 ZQ Calibration : PASS
9014 13:22:03.808141 Jitter Meter : NO K
9015 13:22:03.810681 CBT Training : PASS
9016 13:22:03.814346 Write leveling : PASS
9017 13:22:03.814446 RX DQS gating : PASS
9018 13:22:03.817313 RX DQ/DQS(RDDQC) : PASS
9019 13:22:03.820822 TX DQ/DQS : PASS
9020 13:22:03.820902 RX DATLAT : PASS
9021 13:22:03.823699 RX DQ/DQS(Engine): PASS
9022 13:22:03.823778 TX OE : PASS
9023 13:22:03.827457 All Pass.
9024 13:22:03.827537
9025 13:22:03.827599 CH 1, Rank 0
9026 13:22:03.830722 SW Impedance : PASS
9027 13:22:03.830802 DUTY Scan : NO K
9028 13:22:03.833861 ZQ Calibration : PASS
9029 13:22:03.837260 Jitter Meter : NO K
9030 13:22:03.837340 CBT Training : PASS
9031 13:22:03.840795 Write leveling : PASS
9032 13:22:03.843928 RX DQS gating : PASS
9033 13:22:03.844022 RX DQ/DQS(RDDQC) : PASS
9034 13:22:03.846985 TX DQ/DQS : PASS
9035 13:22:03.850365 RX DATLAT : PASS
9036 13:22:03.850445 RX DQ/DQS(Engine): PASS
9037 13:22:03.853725 TX OE : PASS
9038 13:22:03.853805 All Pass.
9039 13:22:03.853868
9040 13:22:03.856592 CH 1, Rank 1
9041 13:22:03.856694 SW Impedance : PASS
9042 13:22:03.860025 DUTY Scan : NO K
9043 13:22:03.863512 ZQ Calibration : PASS
9044 13:22:03.863623 Jitter Meter : NO K
9045 13:22:03.866720 CBT Training : PASS
9046 13:22:03.870111 Write leveling : PASS
9047 13:22:03.870184 RX DQS gating : PASS
9048 13:22:03.874108 RX DQ/DQS(RDDQC) : PASS
9049 13:22:03.876614 TX DQ/DQS : PASS
9050 13:22:03.876693 RX DATLAT : PASS
9051 13:22:03.880100 RX DQ/DQS(Engine): PASS
9052 13:22:03.883209 TX OE : PASS
9053 13:22:03.883288 All Pass.
9054 13:22:03.883351
9055 13:22:03.883409 DramC Write-DBI on
9056 13:22:03.886770 PER_BANK_REFRESH: Hybrid Mode
9057 13:22:03.890334 TX_TRACKING: ON
9058 13:22:03.896607 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9059 13:22:03.906390 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9060 13:22:03.913434 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9061 13:22:03.916233 [FAST_K] Save calibration result to emmc
9062 13:22:03.919362 sync common calibartion params.
9063 13:22:03.922868 sync cbt_mode0:1, 1:1
9064 13:22:03.922950 dram_init: ddr_geometry: 2
9065 13:22:03.925863 dram_init: ddr_geometry: 2
9066 13:22:03.929166 dram_init: ddr_geometry: 2
9067 13:22:03.932980 0:dram_rank_size:100000000
9068 13:22:03.933063 1:dram_rank_size:100000000
9069 13:22:03.940028 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9070 13:22:03.942247 DFS_SHUFFLE_HW_MODE: ON
9071 13:22:03.946294 dramc_set_vcore_voltage set vcore to 725000
9072 13:22:03.946376 Read voltage for 1600, 0
9073 13:22:03.949397 Vio18 = 0
9074 13:22:03.949478 Vcore = 725000
9075 13:22:03.949542 Vdram = 0
9076 13:22:03.952127 Vddq = 0
9077 13:22:03.952208 Vmddr = 0
9078 13:22:03.955392 switch to 3200 Mbps bootup
9079 13:22:03.955474 [DramcRunTimeConfig]
9080 13:22:03.958774 PHYPLL
9081 13:22:03.958856 DPM_CONTROL_AFTERK: ON
9082 13:22:03.962461 PER_BANK_REFRESH: ON
9083 13:22:03.965661 REFRESH_OVERHEAD_REDUCTION: ON
9084 13:22:03.965743 CMD_PICG_NEW_MODE: OFF
9085 13:22:03.968760 XRTWTW_NEW_MODE: ON
9086 13:22:03.968841 XRTRTR_NEW_MODE: ON
9087 13:22:03.972143 TX_TRACKING: ON
9088 13:22:03.972225 RDSEL_TRACKING: OFF
9089 13:22:03.975425 DQS Precalculation for DVFS: ON
9090 13:22:03.978735 RX_TRACKING: OFF
9091 13:22:03.978817 HW_GATING DBG: ON
9092 13:22:03.982373 ZQCS_ENABLE_LP4: ON
9093 13:22:03.982454 RX_PICG_NEW_MODE: ON
9094 13:22:03.985692 TX_PICG_NEW_MODE: ON
9095 13:22:03.985774 ENABLE_RX_DCM_DPHY: ON
9096 13:22:03.989337 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9097 13:22:03.991737 DUMMY_READ_FOR_TRACKING: OFF
9098 13:22:03.995803 !!! SPM_CONTROL_AFTERK: OFF
9099 13:22:03.998650 !!! SPM could not control APHY
9100 13:22:03.998733 IMPEDANCE_TRACKING: ON
9101 13:22:04.002076 TEMP_SENSOR: ON
9102 13:22:04.002157 HW_SAVE_FOR_SR: OFF
9103 13:22:04.005916 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9104 13:22:04.008660 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9105 13:22:04.012377 Read ODT Tracking: ON
9106 13:22:04.015323 Refresh Rate DeBounce: ON
9107 13:22:04.015404 DFS_NO_QUEUE_FLUSH: ON
9108 13:22:04.018766 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9109 13:22:04.022033 ENABLE_DFS_RUNTIME_MRW: OFF
9110 13:22:04.025163 DDR_RESERVE_NEW_MODE: ON
9111 13:22:04.025245 MR_CBT_SWITCH_FREQ: ON
9112 13:22:04.028232 =========================
9113 13:22:04.047347 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9114 13:22:04.050505 dram_init: ddr_geometry: 2
9115 13:22:04.068676 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9116 13:22:04.072157 dram_init: dram init end (result: 0)
9117 13:22:04.078775 DRAM-K: Full calibration passed in 24421 msecs
9118 13:22:04.082528 MRC: failed to locate region type 0.
9119 13:22:04.082610 DRAM rank0 size:0x100000000,
9120 13:22:04.085139 DRAM rank1 size=0x100000000
9121 13:22:04.095420 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9122 13:22:04.101575 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9123 13:22:04.111523 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9124 13:22:04.117871 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9125 13:22:04.117953 DRAM rank0 size:0x100000000,
9126 13:22:04.122158 DRAM rank1 size=0x100000000
9127 13:22:04.122240 CBMEM:
9128 13:22:04.124598 IMD: root @ 0xfffff000 254 entries.
9129 13:22:04.128438 IMD: root @ 0xffffec00 62 entries.
9130 13:22:04.131470 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9131 13:22:04.137805 WARNING: RO_VPD is uninitialized or empty.
9132 13:22:04.141561 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9133 13:22:04.148694 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9134 13:22:04.161492 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9135 13:22:04.173549 BS: romstage times (exec / console): total (unknown) / 23952 ms
9136 13:22:04.173631
9137 13:22:04.173695
9138 13:22:04.182808 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9139 13:22:04.186623 ARM64: Exception handlers installed.
9140 13:22:04.189752 ARM64: Testing exception
9141 13:22:04.193024 ARM64: Done test exception
9142 13:22:04.193103 Enumerating buses...
9143 13:22:04.196501 Show all devs... Before device enumeration.
9144 13:22:04.199481 Root Device: enabled 1
9145 13:22:04.202732 CPU_CLUSTER: 0: enabled 1
9146 13:22:04.202812 CPU: 00: enabled 1
9147 13:22:04.206176 Compare with tree...
9148 13:22:04.206256 Root Device: enabled 1
9149 13:22:04.209641 CPU_CLUSTER: 0: enabled 1
9150 13:22:04.212227 CPU: 00: enabled 1
9151 13:22:04.212307 Root Device scanning...
9152 13:22:04.215608 scan_static_bus for Root Device
9153 13:22:04.218930 CPU_CLUSTER: 0 enabled
9154 13:22:04.222362 scan_static_bus for Root Device done
9155 13:22:04.225989 scan_bus: bus Root Device finished in 8 msecs
9156 13:22:04.226071 done
9157 13:22:04.232160 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9158 13:22:04.235515 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9159 13:22:04.242985 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9160 13:22:04.248914 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9161 13:22:04.248996 Allocating resources...
9162 13:22:04.252088 Reading resources...
9163 13:22:04.255129 Root Device read_resources bus 0 link: 0
9164 13:22:04.259304 DRAM rank0 size:0x100000000,
9165 13:22:04.259381 DRAM rank1 size=0x100000000
9166 13:22:04.265160 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9167 13:22:04.265268 CPU: 00 missing read_resources
9168 13:22:04.272039 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9169 13:22:04.275403 Root Device read_resources bus 0 link: 0 done
9170 13:22:04.278483 Done reading resources.
9171 13:22:04.281940 Show resources in subtree (Root Device)...After reading.
9172 13:22:04.285185 Root Device child on link 0 CPU_CLUSTER: 0
9173 13:22:04.288442 CPU_CLUSTER: 0 child on link 0 CPU: 00
9174 13:22:04.297773 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9175 13:22:04.297885 CPU: 00
9176 13:22:04.305690 Root Device assign_resources, bus 0 link: 0
9177 13:22:04.307661 CPU_CLUSTER: 0 missing set_resources
9178 13:22:04.311136 Root Device assign_resources, bus 0 link: 0 done
9179 13:22:04.314755 Done setting resources.
9180 13:22:04.317985 Show resources in subtree (Root Device)...After assigning values.
9181 13:22:04.321423 Root Device child on link 0 CPU_CLUSTER: 0
9182 13:22:04.327696 CPU_CLUSTER: 0 child on link 0 CPU: 00
9183 13:22:04.334142 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9184 13:22:04.337575 CPU: 00
9185 13:22:04.337673 Done allocating resources.
9186 13:22:04.344110 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9187 13:22:04.347260 Enabling resources...
9188 13:22:04.347356 done.
9189 13:22:04.350244 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9190 13:22:04.353884 Initializing devices...
9191 13:22:04.353975 Root Device init
9192 13:22:04.357061 init hardware done!
9193 13:22:04.360161 0x00000018: ctrlr->caps
9194 13:22:04.360237 52.000 MHz: ctrlr->f_max
9195 13:22:04.363849 0.400 MHz: ctrlr->f_min
9196 13:22:04.366836 0x40ff8080: ctrlr->voltages
9197 13:22:04.366943 sclk: 390625
9198 13:22:04.367033 Bus Width = 1
9199 13:22:04.370280 sclk: 390625
9200 13:22:04.370381 Bus Width = 1
9201 13:22:04.373591 Early init status = 3
9202 13:22:04.376987 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9203 13:22:04.380408 in-header: 03 fc 00 00 01 00 00 00
9204 13:22:04.384233 in-data: 00
9205 13:22:04.387144 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9206 13:22:04.395779 in-header: 03 fd 00 00 00 00 00 00
9207 13:22:04.395888 in-data:
9208 13:22:04.399190 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9209 13:22:04.403871 in-header: 03 fc 00 00 01 00 00 00
9210 13:22:04.407024 in-data: 00
9211 13:22:04.410007 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9212 13:22:04.415644 in-header: 03 fd 00 00 00 00 00 00
9213 13:22:04.419713 in-data:
9214 13:22:04.422487 [SSUSB] Setting up USB HOST controller...
9215 13:22:04.425503 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9216 13:22:04.428945 [SSUSB] phy power-on done.
9217 13:22:04.432853 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9218 13:22:04.438890 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9219 13:22:04.442457 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9220 13:22:04.449186 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9221 13:22:04.455187 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9222 13:22:04.462031 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9223 13:22:04.468614 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9224 13:22:04.474895 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9225 13:22:04.478358 SPM: binary array size = 0x9dc
9226 13:22:04.481951 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9227 13:22:04.488587 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9228 13:22:04.494958 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9229 13:22:04.501592 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9230 13:22:04.504578 configure_display: Starting display init
9231 13:22:04.539091 anx7625_power_on_init: Init interface.
9232 13:22:04.542384 anx7625_disable_pd_protocol: Disabled PD feature.
9233 13:22:04.545781 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9234 13:22:04.573823 anx7625_start_dp_work: Secure OCM version=00
9235 13:22:04.576771 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9236 13:22:04.591551 sp_tx_get_edid_block: EDID Block = 1
9237 13:22:04.693970 Extracted contents:
9238 13:22:04.697240 header: 00 ff ff ff ff ff ff 00
9239 13:22:04.700624 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9240 13:22:04.704508 version: 01 04
9241 13:22:04.707175 basic params: 95 1f 11 78 0a
9242 13:22:04.710580 chroma info: 76 90 94 55 54 90 27 21 50 54
9243 13:22:04.713804 established: 00 00 00
9244 13:22:04.720526 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9245 13:22:04.723779 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9246 13:22:04.730628 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9247 13:22:04.736933 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9248 13:22:04.743423 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9249 13:22:04.747418 extensions: 00
9250 13:22:04.747521 checksum: fb
9251 13:22:04.747612
9252 13:22:04.750385 Manufacturer: IVO Model 57d Serial Number 0
9253 13:22:04.753063 Made week 0 of 2020
9254 13:22:04.757300 EDID version: 1.4
9255 13:22:04.757380 Digital display
9256 13:22:04.760052 6 bits per primary color channel
9257 13:22:04.760141 DisplayPort interface
9258 13:22:04.763200 Maximum image size: 31 cm x 17 cm
9259 13:22:04.766582 Gamma: 220%
9260 13:22:04.766662 Check DPMS levels
9261 13:22:04.769978 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9262 13:22:04.776807 First detailed timing is preferred timing
9263 13:22:04.776888 Established timings supported:
9264 13:22:04.780176 Standard timings supported:
9265 13:22:04.782926 Detailed timings
9266 13:22:04.786872 Hex of detail: 383680a07038204018303c0035ae10000019
9267 13:22:04.792872 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9268 13:22:04.796293 0780 0798 07c8 0820 hborder 0
9269 13:22:04.799721 0438 043b 0447 0458 vborder 0
9270 13:22:04.802497 -hsync -vsync
9271 13:22:04.802578 Did detailed timing
9272 13:22:04.809250 Hex of detail: 000000000000000000000000000000000000
9273 13:22:04.812537 Manufacturer-specified data, tag 0
9274 13:22:04.815593 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9275 13:22:04.818948 ASCII string: InfoVision
9276 13:22:04.822457 Hex of detail: 000000fe00523134304e574635205248200a
9277 13:22:04.825523 ASCII string: R140NWF5 RH
9278 13:22:04.825604 Checksum
9279 13:22:04.828786 Checksum: 0xfb (valid)
9280 13:22:04.832381 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9281 13:22:04.835325 DSI data_rate: 832800000 bps
9282 13:22:04.842380 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9283 13:22:04.845842 anx7625_parse_edid: pixelclock(138800).
9284 13:22:04.849621 hactive(1920), hsync(48), hfp(24), hbp(88)
9285 13:22:04.852074 vactive(1080), vsync(12), vfp(3), vbp(17)
9286 13:22:04.855162 anx7625_dsi_config: config dsi.
9287 13:22:04.861831 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9288 13:22:04.875783 anx7625_dsi_config: success to config DSI
9289 13:22:04.879971 anx7625_dp_start: MIPI phy setup OK.
9290 13:22:04.882500 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9291 13:22:04.886107 mtk_ddp_mode_set invalid vrefresh 60
9292 13:22:04.889226 main_disp_path_setup
9293 13:22:04.889305 ovl_layer_smi_id_en
9294 13:22:04.893176 ovl_layer_smi_id_en
9295 13:22:04.893255 ccorr_config
9296 13:22:04.893318 aal_config
9297 13:22:04.896489 gamma_config
9298 13:22:04.896569 postmask_config
9299 13:22:04.899311 dither_config
9300 13:22:04.903183 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9301 13:22:04.909252 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9302 13:22:04.912659 Root Device init finished in 554 msecs
9303 13:22:04.915790 CPU_CLUSTER: 0 init
9304 13:22:04.922222 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9305 13:22:04.929280 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9306 13:22:04.929382 APU_MBOX 0x190000b0 = 0x10001
9307 13:22:04.932358 APU_MBOX 0x190001b0 = 0x10001
9308 13:22:04.935984 APU_MBOX 0x190005b0 = 0x10001
9309 13:22:04.938989 APU_MBOX 0x190006b0 = 0x10001
9310 13:22:04.945103 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9311 13:22:04.954872 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9312 13:22:04.967464 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9313 13:22:04.973811 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9314 13:22:04.985999 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9315 13:22:04.995377 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9316 13:22:04.998828 CPU_CLUSTER: 0 init finished in 81 msecs
9317 13:22:05.001147 Devices initialized
9318 13:22:05.004687 Show all devs... After init.
9319 13:22:05.004780 Root Device: enabled 1
9320 13:22:05.007815 CPU_CLUSTER: 0: enabled 1
9321 13:22:05.011029 CPU: 00: enabled 1
9322 13:22:05.015088 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9323 13:22:05.017812 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9324 13:22:05.021294 ELOG: NV offset 0x57f000 size 0x1000
9325 13:22:05.028140 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9326 13:22:05.034735 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9327 13:22:05.037690 ELOG: Event(17) added with size 13 at 2023-09-06 13:22:05 UTC
9328 13:22:05.044103 out: cmd=0x121: 03 db 21 01 00 00 00 00
9329 13:22:05.048056 in-header: 03 30 00 00 2c 00 00 00
9330 13:22:05.057666 in-data: 2f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9331 13:22:05.064233 ELOG: Event(A1) added with size 10 at 2023-09-06 13:22:05 UTC
9332 13:22:05.070826 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9333 13:22:05.077526 ELOG: Event(A0) added with size 9 at 2023-09-06 13:22:05 UTC
9334 13:22:05.080571 elog_add_boot_reason: Logged dev mode boot
9335 13:22:05.087877 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9336 13:22:05.087992 Finalize devices...
9337 13:22:05.090435 Devices finalized
9338 13:22:05.093696 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9339 13:22:05.097458 Writing coreboot table at 0xffe64000
9340 13:22:05.100723 0. 000000000010a000-0000000000113fff: RAMSTAGE
9341 13:22:05.107443 1. 0000000040000000-00000000400fffff: RAM
9342 13:22:05.111051 2. 0000000040100000-000000004032afff: RAMSTAGE
9343 13:22:05.113620 3. 000000004032b000-00000000545fffff: RAM
9344 13:22:05.117136 4. 0000000054600000-000000005465ffff: BL31
9345 13:22:05.120635 5. 0000000054660000-00000000ffe63fff: RAM
9346 13:22:05.127574 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9347 13:22:05.130453 7. 0000000100000000-000000023fffffff: RAM
9348 13:22:05.133691 Passing 5 GPIOs to payload:
9349 13:22:05.136590 NAME | PORT | POLARITY | VALUE
9350 13:22:05.144075 EC in RW | 0x000000aa | low | undefined
9351 13:22:05.147003 EC interrupt | 0x00000005 | low | undefined
9352 13:22:05.150006 TPM interrupt | 0x000000ab | high | undefined
9353 13:22:05.156748 SD card detect | 0x00000011 | high | undefined
9354 13:22:05.159799 speaker enable | 0x00000093 | high | undefined
9355 13:22:05.162935 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9356 13:22:05.166330 in-header: 03 f9 00 00 02 00 00 00
9357 13:22:05.170151 in-data: 02 00
9358 13:22:05.173619 ADC[4]: Raw value=901847 ID=7
9359 13:22:05.173692 ADC[3]: Raw value=213916 ID=1
9360 13:22:05.176396 RAM Code: 0x71
9361 13:22:05.179642 ADC[6]: Raw value=74630 ID=0
9362 13:22:05.183141 ADC[5]: Raw value=213546 ID=1
9363 13:22:05.183249 SKU Code: 0x1
9364 13:22:05.189527 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 955a
9365 13:22:05.189604 coreboot table: 964 bytes.
9366 13:22:05.192884 IMD ROOT 0. 0xfffff000 0x00001000
9367 13:22:05.196010 IMD SMALL 1. 0xffffe000 0x00001000
9368 13:22:05.199775 RO MCACHE 2. 0xffffc000 0x00001104
9369 13:22:05.202912 CONSOLE 3. 0xfff7c000 0x00080000
9370 13:22:05.206094 FMAP 4. 0xfff7b000 0x00000452
9371 13:22:05.209274 TIME STAMP 5. 0xfff7a000 0x00000910
9372 13:22:05.213045 VBOOT WORK 6. 0xfff66000 0x00014000
9373 13:22:05.216577 RAMOOPS 7. 0xffe66000 0x00100000
9374 13:22:05.219760 COREBOOT 8. 0xffe64000 0x00002000
9375 13:22:05.222289 IMD small region:
9376 13:22:05.225706 IMD ROOT 0. 0xffffec00 0x00000400
9377 13:22:05.228887 VPD 1. 0xffffeb80 0x0000006c
9378 13:22:05.232164 MMC STATUS 2. 0xffffeb60 0x00000004
9379 13:22:05.238780 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9380 13:22:05.238881 Probing TPM: done!
9381 13:22:05.245661 Connected to device vid:did:rid of 1ae0:0028:00
9382 13:22:05.252821 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9383 13:22:05.255814 Initialized TPM device CR50 revision 0
9384 13:22:05.258869 Checking cr50 for pending updates
9385 13:22:05.264689 Reading cr50 TPM mode
9386 13:22:05.273030 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9387 13:22:05.279620 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9388 13:22:05.320057 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9389 13:22:05.323379 Checking segment from ROM address 0x40100000
9390 13:22:05.326436 Checking segment from ROM address 0x4010001c
9391 13:22:05.332908 Loading segment from ROM address 0x40100000
9392 13:22:05.332990 code (compression=0)
9393 13:22:05.342879 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9394 13:22:05.349340 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9395 13:22:05.349422 it's not compressed!
9396 13:22:05.356180 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9397 13:22:05.363169 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9398 13:22:05.380218 Loading segment from ROM address 0x4010001c
9399 13:22:05.380294 Entry Point 0x80000000
9400 13:22:05.383671 Loaded segments
9401 13:22:05.387091 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9402 13:22:05.393511 Jumping to boot code at 0x80000000(0xffe64000)
9403 13:22:05.400198 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9404 13:22:05.407752 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9405 13:22:05.414645 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9406 13:22:05.417987 Checking segment from ROM address 0x40100000
9407 13:22:05.421101 Checking segment from ROM address 0x4010001c
9408 13:22:05.427879 Loading segment from ROM address 0x40100000
9409 13:22:05.428002 code (compression=1)
9410 13:22:05.434643 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9411 13:22:05.444415 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9412 13:22:05.444496 using LZMA
9413 13:22:05.452945 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9414 13:22:05.459604 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9415 13:22:05.462817 Loading segment from ROM address 0x4010001c
9416 13:22:05.462897 Entry Point 0x54601000
9417 13:22:05.466723 Loaded segments
9418 13:22:05.469422 NOTICE: MT8192 bl31_setup
9419 13:22:05.476487 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9420 13:22:05.480042 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9421 13:22:05.483543 WARNING: region 0:
9422 13:22:05.486303 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9423 13:22:05.486384 WARNING: region 1:
9424 13:22:05.493277 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9425 13:22:05.497016 WARNING: region 2:
9426 13:22:05.499885 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9427 13:22:05.503087 WARNING: region 3:
9428 13:22:05.506268 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9429 13:22:05.509994 WARNING: region 4:
9430 13:22:05.516310 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9431 13:22:05.516391 WARNING: region 5:
9432 13:22:05.520181 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9433 13:22:05.523840 WARNING: region 6:
9434 13:22:05.526242 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9435 13:22:05.529682 WARNING: region 7:
9436 13:22:05.533028 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9437 13:22:05.539815 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9438 13:22:05.542829 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9439 13:22:05.545967 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9440 13:22:05.552599 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9441 13:22:05.556552 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9442 13:22:05.563053 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9443 13:22:05.566232 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9444 13:22:05.569726 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9445 13:22:05.575846 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9446 13:22:05.579012 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9447 13:22:05.582453 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9448 13:22:05.589114 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9449 13:22:05.592547 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9450 13:22:05.599239 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9451 13:22:05.602620 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9452 13:22:05.605925 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9453 13:22:05.612851 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9454 13:22:05.615855 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9455 13:22:05.619036 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9456 13:22:05.625964 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9457 13:22:05.629063 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9458 13:22:05.635603 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9459 13:22:05.639064 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9460 13:22:05.642194 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9461 13:22:05.649215 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9462 13:22:05.652557 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9463 13:22:05.658726 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9464 13:22:05.662159 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9465 13:22:05.665652 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9466 13:22:05.672744 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9467 13:22:05.675636 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9468 13:22:05.682118 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9469 13:22:05.685571 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9470 13:22:05.688591 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9471 13:22:05.692211 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9472 13:22:05.698716 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9473 13:22:05.702588 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9474 13:22:05.705194 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9475 13:22:05.708545 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9476 13:22:05.715301 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9477 13:22:05.719305 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9478 13:22:05.721793 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9479 13:22:05.725304 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9480 13:22:05.732223 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9481 13:22:05.735051 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9482 13:22:05.738824 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9483 13:22:05.742214 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9484 13:22:05.748166 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9485 13:22:05.752086 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9486 13:22:05.758284 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9487 13:22:05.762651 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9488 13:22:05.765464 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9489 13:22:05.771817 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9490 13:22:05.774914 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9491 13:22:05.781816 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9492 13:22:05.784925 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9493 13:22:05.791492 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9494 13:22:05.795045 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9495 13:22:05.798429 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9496 13:22:05.804818 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9497 13:22:05.808857 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9498 13:22:05.815151 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9499 13:22:05.818451 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9500 13:22:05.825581 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9501 13:22:05.828731 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9502 13:22:05.835090 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9503 13:22:05.838295 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9504 13:22:05.841734 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9505 13:22:05.848353 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9506 13:22:05.851613 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9507 13:22:05.858089 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9508 13:22:05.861576 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9509 13:22:05.868120 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9510 13:22:05.871629 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9511 13:22:05.874948 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9512 13:22:05.881817 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9513 13:22:05.884820 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9514 13:22:05.891301 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9515 13:22:05.894642 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9516 13:22:05.902081 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9517 13:22:05.904620 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9518 13:22:05.911048 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9519 13:22:05.914754 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9520 13:22:05.917869 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9521 13:22:05.924479 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9522 13:22:05.928026 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9523 13:22:05.935076 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9524 13:22:05.937955 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9525 13:22:05.944958 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9526 13:22:05.948093 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9527 13:22:05.951137 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9528 13:22:05.957844 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9529 13:22:05.961624 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9530 13:22:05.967771 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9531 13:22:05.971774 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9532 13:22:05.977701 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9533 13:22:05.980965 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9534 13:22:05.984658 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9535 13:22:05.987598 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9536 13:22:05.994157 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9537 13:22:05.997839 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9538 13:22:06.000651 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9539 13:22:06.007396 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9540 13:22:06.011197 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9541 13:22:06.017442 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9542 13:22:06.020989 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9543 13:22:06.024173 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9544 13:22:06.030284 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9545 13:22:06.033822 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9546 13:22:06.040470 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9547 13:22:06.043554 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9548 13:22:06.050141 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9549 13:22:06.053531 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9550 13:22:06.056846 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9551 13:22:06.063833 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9552 13:22:06.067316 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9553 13:22:06.070223 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9554 13:22:06.076791 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9555 13:22:06.080454 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9556 13:22:06.083340 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9557 13:22:06.086876 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9558 13:22:06.093713 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9559 13:22:06.096608 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9560 13:22:06.100387 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9561 13:22:06.106784 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9562 13:22:06.109758 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9563 13:22:06.113043 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9564 13:22:06.119964 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9565 13:22:06.122988 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9566 13:22:06.129862 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9567 13:22:06.133320 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9568 13:22:06.136219 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9569 13:22:06.143090 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9570 13:22:06.146570 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9571 13:22:06.153389 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9572 13:22:06.156790 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9573 13:22:06.160084 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9574 13:22:06.166144 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9575 13:22:06.169644 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9576 13:22:06.176333 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9577 13:22:06.180190 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9578 13:22:06.182777 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9579 13:22:06.189369 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9580 13:22:06.192753 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9581 13:22:06.199181 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9582 13:22:06.202951 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9583 13:22:06.205967 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9584 13:22:06.213065 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9585 13:22:06.216351 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9586 13:22:06.222797 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9587 13:22:06.225879 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9588 13:22:06.229452 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9589 13:22:06.236088 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9590 13:22:06.239131 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9591 13:22:06.242335 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9592 13:22:06.249381 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9593 13:22:06.252668 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9594 13:22:06.259130 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9595 13:22:06.262442 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9596 13:22:06.265754 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9597 13:22:06.271958 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9598 13:22:06.275612 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9599 13:22:06.281883 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9600 13:22:06.285813 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9601 13:22:06.288522 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9602 13:22:06.295450 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9603 13:22:06.299089 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9604 13:22:06.305253 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9605 13:22:06.308737 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9606 13:22:06.312248 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9607 13:22:06.318215 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9608 13:22:06.322239 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9609 13:22:06.328330 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9610 13:22:06.331609 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9611 13:22:06.337943 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9612 13:22:06.341137 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9613 13:22:06.344711 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9614 13:22:06.351358 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9615 13:22:06.354643 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9616 13:22:06.357884 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9617 13:22:06.364328 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9618 13:22:06.367670 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9619 13:22:06.374138 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9620 13:22:06.377378 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9621 13:22:06.384291 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9622 13:22:06.388676 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9623 13:22:06.391436 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9624 13:22:06.397444 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9625 13:22:06.400721 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9626 13:22:06.407756 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9627 13:22:06.410676 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9628 13:22:06.413854 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9629 13:22:06.421259 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9630 13:22:06.424440 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9631 13:22:06.430532 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9632 13:22:06.433961 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9633 13:22:06.440567 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9634 13:22:06.443512 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9635 13:22:06.446749 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9636 13:22:06.453960 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9637 13:22:06.456622 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9638 13:22:06.463331 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9639 13:22:06.466648 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9640 13:22:06.473420 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9641 13:22:06.476650 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9642 13:22:06.480343 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9643 13:22:06.486784 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9644 13:22:06.489770 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9645 13:22:06.496167 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9646 13:22:06.499959 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9647 13:22:06.505818 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9648 13:22:06.509581 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9649 13:22:06.513127 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9650 13:22:06.519761 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9651 13:22:06.522510 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9652 13:22:06.529455 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9653 13:22:06.533562 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9654 13:22:06.539304 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9655 13:22:06.542033 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9656 13:22:06.545715 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9657 13:22:06.552977 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9658 13:22:06.555706 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9659 13:22:06.562430 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9660 13:22:06.565629 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9661 13:22:06.572046 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9662 13:22:06.575634 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9663 13:22:06.578794 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9664 13:22:06.585647 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9665 13:22:06.588807 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9666 13:22:06.592096 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9667 13:22:06.598185 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9668 13:22:06.601454 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9669 13:22:06.604944 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9670 13:22:06.608382 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9671 13:22:06.615526 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9672 13:22:06.618645 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9673 13:22:06.624784 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9674 13:22:06.628436 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9675 13:22:06.631172 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9676 13:22:06.637856 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9677 13:22:06.640895 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9678 13:22:06.644624 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9679 13:22:06.651541 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9680 13:22:06.654317 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9681 13:22:06.657497 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9682 13:22:06.664356 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9683 13:22:06.667445 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9684 13:22:06.673919 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9685 13:22:06.677872 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9686 13:22:06.680936 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9687 13:22:06.687196 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9688 13:22:06.690555 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9689 13:22:06.697546 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9690 13:22:06.700362 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9691 13:22:06.703789 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9692 13:22:06.710890 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9693 13:22:06.713627 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9694 13:22:06.716734 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9695 13:22:06.723593 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9696 13:22:06.727480 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9697 13:22:06.733866 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9698 13:22:06.736660 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9699 13:22:06.740613 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9700 13:22:06.746592 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9701 13:22:06.750370 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9702 13:22:06.753307 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9703 13:22:06.759925 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9704 13:22:06.763044 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9705 13:22:06.769359 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9706 13:22:06.772889 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9707 13:22:06.776229 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9708 13:22:06.779620 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9709 13:22:06.782933 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9710 13:22:06.789881 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9711 13:22:06.792424 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9712 13:22:06.796126 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9713 13:22:06.799735 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9714 13:22:06.805937 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9715 13:22:06.810082 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9716 13:22:06.812206 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9717 13:22:06.818823 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9718 13:22:06.822253 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9719 13:22:06.825444 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9720 13:22:06.832737 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9721 13:22:06.835745 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9722 13:22:06.842438 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9723 13:22:06.845635 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9724 13:22:06.848861 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9725 13:22:06.855133 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9726 13:22:06.858949 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9727 13:22:06.865514 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9728 13:22:06.868936 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9729 13:22:06.875003 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9730 13:22:06.878473 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9731 13:22:06.881551 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9732 13:22:06.888503 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9733 13:22:06.892713 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9734 13:22:06.898698 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9735 13:22:06.901800 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9736 13:22:06.904989 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9737 13:22:06.911480 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9738 13:22:06.915163 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9739 13:22:06.921660 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9740 13:22:06.925422 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9741 13:22:06.931665 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9742 13:22:06.935004 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9743 13:22:06.938160 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9744 13:22:06.944676 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9745 13:22:06.948229 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9746 13:22:06.954564 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9747 13:22:06.957642 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9748 13:22:06.961359 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9749 13:22:06.968140 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9750 13:22:06.970999 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9751 13:22:06.977467 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9752 13:22:06.981182 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9753 13:22:06.984549 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9754 13:22:06.991012 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9755 13:22:06.995118 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9756 13:22:07.001288 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9757 13:22:07.004325 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9758 13:22:07.007623 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9759 13:22:07.014326 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9760 13:22:07.017779 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9761 13:22:07.024267 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9762 13:22:07.027233 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9763 13:22:07.033766 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9764 13:22:07.037413 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9765 13:22:07.041093 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9766 13:22:07.047059 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9767 13:22:07.050612 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9768 13:22:07.057820 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9769 13:22:07.060683 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9770 13:22:07.064109 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9771 13:22:07.070888 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9772 13:22:07.073828 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9773 13:22:07.080521 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9774 13:22:07.084260 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9775 13:22:07.086895 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9776 13:22:07.094195 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9777 13:22:07.096752 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9778 13:22:07.103782 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9779 13:22:07.107235 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9780 13:22:07.113513 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9781 13:22:07.116805 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9782 13:22:07.120010 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9783 13:22:07.126816 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9784 13:22:07.130179 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9785 13:22:07.137037 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9786 13:22:07.140164 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9787 13:22:07.143201 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9788 13:22:07.149723 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9789 13:22:07.153041 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9790 13:22:07.160608 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9791 13:22:07.163358 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9792 13:22:07.166370 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9793 13:22:07.172935 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9794 13:22:07.176498 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9795 13:22:07.183056 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9796 13:22:07.186462 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9797 13:22:07.193136 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9798 13:22:07.195970 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9799 13:22:07.203016 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9800 13:22:07.205725 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9801 13:22:07.209726 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9802 13:22:07.216479 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9803 13:22:07.219025 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9804 13:22:07.225996 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9805 13:22:07.229163 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9806 13:22:07.235988 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9807 13:22:07.239043 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9808 13:22:07.245801 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9809 13:22:07.248966 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9810 13:22:07.252550 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9811 13:22:07.258816 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9812 13:22:07.262034 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9813 13:22:07.268653 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9814 13:22:07.272125 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9815 13:22:07.278524 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9816 13:22:07.281992 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9817 13:22:07.288651 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9818 13:22:07.292156 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9819 13:22:07.295460 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9820 13:22:07.301657 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9821 13:22:07.305288 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9822 13:22:07.311528 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9823 13:22:07.314745 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9824 13:22:07.322479 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9825 13:22:07.325259 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9826 13:22:07.331695 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9827 13:22:07.334893 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9828 13:22:07.338549 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9829 13:22:07.344807 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9830 13:22:07.348686 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9831 13:22:07.354608 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9832 13:22:07.358450 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9833 13:22:07.364724 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9834 13:22:07.368206 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9835 13:22:07.374375 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9836 13:22:07.378393 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9837 13:22:07.384596 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9838 13:22:07.387427 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9839 13:22:07.391101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9840 13:22:07.398366 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9841 13:22:07.400745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9842 13:22:07.407725 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9843 13:22:07.411462 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9844 13:22:07.417988 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9845 13:22:07.420885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9846 13:22:07.424039 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9847 13:22:07.431480 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9848 13:22:07.434225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9849 13:22:07.440742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9850 13:22:07.444197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9851 13:22:07.450965 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9852 13:22:07.453957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9853 13:22:07.460427 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9854 13:22:07.464084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9855 13:22:07.470745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9856 13:22:07.474312 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9857 13:22:07.480433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9858 13:22:07.483507 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9859 13:22:07.490373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9860 13:22:07.493905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9861 13:22:07.500445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9862 13:22:07.503528 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9863 13:22:07.510576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9864 13:22:07.513747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9865 13:22:07.520457 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9866 13:22:07.523293 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9867 13:22:07.530086 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9868 13:22:07.533429 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9869 13:22:07.539840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9870 13:22:07.543768 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9871 13:22:07.550332 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9872 13:22:07.550842 INFO: [APUAPC] vio 0
9873 13:22:07.556994 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9874 13:22:07.560129 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9875 13:22:07.563443 INFO: [APUAPC] D0_APC_0: 0x400510
9876 13:22:07.566608 INFO: [APUAPC] D0_APC_1: 0x0
9877 13:22:07.570074 INFO: [APUAPC] D0_APC_2: 0x1540
9878 13:22:07.573615 INFO: [APUAPC] D0_APC_3: 0x0
9879 13:22:07.577231 INFO: [APUAPC] D1_APC_0: 0xffffffff
9880 13:22:07.579984 INFO: [APUAPC] D1_APC_1: 0xffffffff
9881 13:22:07.583332 INFO: [APUAPC] D1_APC_2: 0x3fffff
9882 13:22:07.586548 INFO: [APUAPC] D1_APC_3: 0x0
9883 13:22:07.590346 INFO: [APUAPC] D2_APC_0: 0xffffffff
9884 13:22:07.593888 INFO: [APUAPC] D2_APC_1: 0xffffffff
9885 13:22:07.596742 INFO: [APUAPC] D2_APC_2: 0x3fffff
9886 13:22:07.600231 INFO: [APUAPC] D2_APC_3: 0x0
9887 13:22:07.603245 INFO: [APUAPC] D3_APC_0: 0xffffffff
9888 13:22:07.607010 INFO: [APUAPC] D3_APC_1: 0xffffffff
9889 13:22:07.609628 INFO: [APUAPC] D3_APC_2: 0x3fffff
9890 13:22:07.613306 INFO: [APUAPC] D3_APC_3: 0x0
9891 13:22:07.616329 INFO: [APUAPC] D4_APC_0: 0xffffffff
9892 13:22:07.619628 INFO: [APUAPC] D4_APC_1: 0xffffffff
9893 13:22:07.622967 INFO: [APUAPC] D4_APC_2: 0x3fffff
9894 13:22:07.626453 INFO: [APUAPC] D4_APC_3: 0x0
9895 13:22:07.629597 INFO: [APUAPC] D5_APC_0: 0xffffffff
9896 13:22:07.633019 INFO: [APUAPC] D5_APC_1: 0xffffffff
9897 13:22:07.636240 INFO: [APUAPC] D5_APC_2: 0x3fffff
9898 13:22:07.636688 INFO: [APUAPC] D5_APC_3: 0x0
9899 13:22:07.639862 INFO: [APUAPC] D6_APC_0: 0xffffffff
9900 13:22:07.646112 INFO: [APUAPC] D6_APC_1: 0xffffffff
9901 13:22:07.649352 INFO: [APUAPC] D6_APC_2: 0x3fffff
9902 13:22:07.649772 INFO: [APUAPC] D6_APC_3: 0x0
9903 13:22:07.652892 INFO: [APUAPC] D7_APC_0: 0xffffffff
9904 13:22:07.656367 INFO: [APUAPC] D7_APC_1: 0xffffffff
9905 13:22:07.659373 INFO: [APUAPC] D7_APC_2: 0x3fffff
9906 13:22:07.663027 INFO: [APUAPC] D7_APC_3: 0x0
9907 13:22:07.666345 INFO: [APUAPC] D8_APC_0: 0xffffffff
9908 13:22:07.669585 INFO: [APUAPC] D8_APC_1: 0xffffffff
9909 13:22:07.672964 INFO: [APUAPC] D8_APC_2: 0x3fffff
9910 13:22:07.675760 INFO: [APUAPC] D8_APC_3: 0x0
9911 13:22:07.679435 INFO: [APUAPC] D9_APC_0: 0xffffffff
9912 13:22:07.682847 INFO: [APUAPC] D9_APC_1: 0xffffffff
9913 13:22:07.685640 INFO: [APUAPC] D9_APC_2: 0x3fffff
9914 13:22:07.689073 INFO: [APUAPC] D9_APC_3: 0x0
9915 13:22:07.692432 INFO: [APUAPC] D10_APC_0: 0xffffffff
9916 13:22:07.695574 INFO: [APUAPC] D10_APC_1: 0xffffffff
9917 13:22:07.698901 INFO: [APUAPC] D10_APC_2: 0x3fffff
9918 13:22:07.702227 INFO: [APUAPC] D10_APC_3: 0x0
9919 13:22:07.705786 INFO: [APUAPC] D11_APC_0: 0xffffffff
9920 13:22:07.709028 INFO: [APUAPC] D11_APC_1: 0xffffffff
9921 13:22:07.712253 INFO: [APUAPC] D11_APC_2: 0x3fffff
9922 13:22:07.716149 INFO: [APUAPC] D11_APC_3: 0x0
9923 13:22:07.719371 INFO: [APUAPC] D12_APC_0: 0xffffffff
9924 13:22:07.722902 INFO: [APUAPC] D12_APC_1: 0xffffffff
9925 13:22:07.725996 INFO: [APUAPC] D12_APC_2: 0x3fffff
9926 13:22:07.729373 INFO: [APUAPC] D12_APC_3: 0x0
9927 13:22:07.732013 INFO: [APUAPC] D13_APC_0: 0xffffffff
9928 13:22:07.735576 INFO: [APUAPC] D13_APC_1: 0xffffffff
9929 13:22:07.739002 INFO: [APUAPC] D13_APC_2: 0x3fffff
9930 13:22:07.742121 INFO: [APUAPC] D13_APC_3: 0x0
9931 13:22:07.745027 INFO: [APUAPC] D14_APC_0: 0xffffffff
9932 13:22:07.751740 INFO: [APUAPC] D14_APC_1: 0xffffffff
9933 13:22:07.755044 INFO: [APUAPC] D14_APC_2: 0x3fffff
9934 13:22:07.755466 INFO: [APUAPC] D14_APC_3: 0x0
9935 13:22:07.762028 INFO: [APUAPC] D15_APC_0: 0xffffffff
9936 13:22:07.764867 INFO: [APUAPC] D15_APC_1: 0xffffffff
9937 13:22:07.768287 INFO: [APUAPC] D15_APC_2: 0x3fffff
9938 13:22:07.768711 INFO: [APUAPC] D15_APC_3: 0x0
9939 13:22:07.771979 INFO: [APUAPC] APC_CON: 0x4
9940 13:22:07.775091 INFO: [NOCDAPC] D0_APC_0: 0x0
9941 13:22:07.778219 INFO: [NOCDAPC] D0_APC_1: 0x0
9942 13:22:07.781962 INFO: [NOCDAPC] D1_APC_0: 0x0
9943 13:22:07.784787 INFO: [NOCDAPC] D1_APC_1: 0xfff
9944 13:22:07.788556 INFO: [NOCDAPC] D2_APC_0: 0x0
9945 13:22:07.791056 INFO: [NOCDAPC] D2_APC_1: 0xfff
9946 13:22:07.794332 INFO: [NOCDAPC] D3_APC_0: 0x0
9947 13:22:07.797985 INFO: [NOCDAPC] D3_APC_1: 0xfff
9948 13:22:07.801211 INFO: [NOCDAPC] D4_APC_0: 0x0
9949 13:22:07.801648 INFO: [NOCDAPC] D4_APC_1: 0xfff
9950 13:22:07.804406 INFO: [NOCDAPC] D5_APC_0: 0x0
9951 13:22:07.807979 INFO: [NOCDAPC] D5_APC_1: 0xfff
9952 13:22:07.810859 INFO: [NOCDAPC] D6_APC_0: 0x0
9953 13:22:07.814716 INFO: [NOCDAPC] D6_APC_1: 0xfff
9954 13:22:07.817472 INFO: [NOCDAPC] D7_APC_0: 0x0
9955 13:22:07.820696 INFO: [NOCDAPC] D7_APC_1: 0xfff
9956 13:22:07.823955 INFO: [NOCDAPC] D8_APC_0: 0x0
9957 13:22:07.827443 INFO: [NOCDAPC] D8_APC_1: 0xfff
9958 13:22:07.830313 INFO: [NOCDAPC] D9_APC_0: 0x0
9959 13:22:07.833953 INFO: [NOCDAPC] D9_APC_1: 0xfff
9960 13:22:07.837309 INFO: [NOCDAPC] D10_APC_0: 0x0
9961 13:22:07.840766 INFO: [NOCDAPC] D10_APC_1: 0xfff
9962 13:22:07.841186 INFO: [NOCDAPC] D11_APC_0: 0x0
9963 13:22:07.843969 INFO: [NOCDAPC] D11_APC_1: 0xfff
9964 13:22:07.847197 INFO: [NOCDAPC] D12_APC_0: 0x0
9965 13:22:07.850296 INFO: [NOCDAPC] D12_APC_1: 0xfff
9966 13:22:07.854124 INFO: [NOCDAPC] D13_APC_0: 0x0
9967 13:22:07.857144 INFO: [NOCDAPC] D13_APC_1: 0xfff
9968 13:22:07.860359 INFO: [NOCDAPC] D14_APC_0: 0x0
9969 13:22:07.864000 INFO: [NOCDAPC] D14_APC_1: 0xfff
9970 13:22:07.867200 INFO: [NOCDAPC] D15_APC_0: 0x0
9971 13:22:07.870070 INFO: [NOCDAPC] D15_APC_1: 0xfff
9972 13:22:07.874154 INFO: [NOCDAPC] APC_CON: 0x4
9973 13:22:07.877235 INFO: [APUAPC] set_apusys_apc done
9974 13:22:07.880034 INFO: [DEVAPC] devapc_init done
9975 13:22:07.883587 INFO: GICv3 without legacy support detected.
9976 13:22:07.886556 INFO: ARM GICv3 driver initialized in EL3
9977 13:22:07.889837 INFO: Maximum SPI INTID supported: 639
9978 13:22:07.896623 INFO: BL31: Initializing runtime services
9979 13:22:07.899598 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9980 13:22:07.903141 INFO: SPM: enable CPC mode
9981 13:22:07.909219 INFO: mcdi ready for mcusys-off-idle and system suspend
9982 13:22:07.912848 INFO: BL31: Preparing for EL3 exit to normal world
9983 13:22:07.915864 INFO: Entry point address = 0x80000000
9984 13:22:07.919285 INFO: SPSR = 0x8
9985 13:22:07.924770
9986 13:22:07.924850
9987 13:22:07.924914
9988 13:22:07.928437 Starting depthcharge on Spherion...
9989 13:22:07.928518
9990 13:22:07.928583 Wipe memory regions:
9991 13:22:07.928643
9992 13:22:07.929293 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9993 13:22:07.929394 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
9994 13:22:07.929475 Setting prompt string to ['asurada:']
9995 13:22:07.929553 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
9996 13:22:07.931120 [0x00000040000000, 0x00000054600000)
9997 13:22:08.053669
9998 13:22:08.053798 [0x00000054660000, 0x00000080000000)
9999 13:22:08.313708
10000 13:22:08.313848 [0x000000821a7280, 0x000000ffe64000)
10001 13:22:09.058193
10002 13:22:09.058343 [0x00000100000000, 0x00000240000000)
10003 13:22:10.945905
10004 13:22:10.949444 Initializing XHCI USB controller at 0x11200000.
10005 13:22:11.988111
10006 13:22:11.991693 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10007 13:22:11.991778
10008 13:22:11.991843
10009 13:22:11.991927
10010 13:22:11.992226 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10012 13:22:12.092566 asurada: tftpboot 192.168.201.1 11445616/tftp-deploy-92azwfrb/kernel/image.itb 11445616/tftp-deploy-92azwfrb/kernel/cmdline
10013 13:22:12.092684 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10014 13:22:12.092767 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10015 13:22:12.097923 tftpboot 192.168.201.1 11445616/tftp-deploy-92azwfrb/kernel/image.ittp-deploy-92azwfrb/kernel/cmdline
10016 13:22:12.098007
10017 13:22:12.098071 Waiting for link
10018 13:22:12.255348
10019 13:22:12.255498 R8152: Initializing
10020 13:22:12.255565
10021 13:22:12.258403 Version 6 (ocp_data = 5c30)
10022 13:22:12.258486
10023 13:22:12.262093 R8152: Done initializing
10024 13:22:12.262175
10025 13:22:12.262239 Adding net device
10026 13:22:14.230087
10027 13:22:14.230654 done.
10028 13:22:14.231027
10029 13:22:14.231371 MAC: 00:24:32:30:7c:7b
10030 13:22:14.231818
10031 13:22:14.233146 Sending DHCP discover... done.
10032 13:22:14.233610
10033 13:22:14.236376 Waiting for reply... done.
10034 13:22:14.236841
10035 13:22:14.239281 Sending DHCP request... done.
10036 13:22:14.239742
10037 13:22:14.246097 Waiting for reply... done.
10038 13:22:14.246574
10039 13:22:14.246945 My ip is 192.168.201.14
10040 13:22:14.247375
10041 13:22:14.248652 The DHCP server ip is 192.168.201.1
10042 13:22:14.249193
10043 13:22:14.255160 TFTP server IP predefined by user: 192.168.201.1
10044 13:22:14.255590
10045 13:22:14.261948 Bootfile predefined by user: 11445616/tftp-deploy-92azwfrb/kernel/image.itb
10046 13:22:14.262465
10047 13:22:14.265186 Sending tftp read request... done.
10048 13:22:14.265610
10049 13:22:14.271794 Waiting for the transfer...
10050 13:22:14.272354
10051 13:22:14.932043 00000000 ################################################################
10052 13:22:14.932211
10053 13:22:15.486090 00080000 ################################################################
10054 13:22:15.486219
10055 13:22:16.044620 00100000 ################################################################
10056 13:22:16.044779
10057 13:22:16.622215 00180000 ################################################################
10058 13:22:16.622368
10059 13:22:17.241107 00200000 ################################################################
10060 13:22:17.241240
10061 13:22:17.800801 00280000 ################################################################
10062 13:22:17.800933
10063 13:22:18.354274 00300000 ################################################################
10064 13:22:18.354401
10065 13:22:18.955650 00380000 ################################################################
10066 13:22:18.955783
10067 13:22:19.576659 00400000 ################################################################
10068 13:22:19.577170
10069 13:22:20.250787 00480000 ################################################################
10070 13:22:20.251271
10071 13:22:20.938440 00500000 ################################################################
10072 13:22:20.938946
10073 13:22:21.627843 00580000 ################################################################
10074 13:22:21.628398
10075 13:22:22.288769 00600000 ################################################################
10076 13:22:22.289279
10077 13:22:22.954028 00680000 ################################################################
10078 13:22:22.954175
10079 13:22:23.584490 00700000 ################################################################
10080 13:22:23.584624
10081 13:22:24.259772 00780000 ################################################################
10082 13:22:24.260578
10083 13:22:24.942289 00800000 ################################################################
10084 13:22:24.942805
10085 13:22:25.589101 00880000 ################################################################
10086 13:22:25.589250
10087 13:22:26.228168 00900000 ################################################################
10088 13:22:26.228676
10089 13:22:26.887934 00980000 ################################################################
10090 13:22:26.888443
10091 13:22:27.567129 00a00000 ################################################################
10092 13:22:27.567636
10093 13:22:28.238397 00a80000 ################################################################
10094 13:22:28.238900
10095 13:22:28.926439 00b00000 ################################################################
10096 13:22:28.926945
10097 13:22:29.612743 00b80000 ################################################################
10098 13:22:29.613253
10099 13:22:30.288266 00c00000 ################################################################
10100 13:22:30.288773
10101 13:22:30.967581 00c80000 ################################################################
10102 13:22:30.968177
10103 13:22:31.658597 00d00000 ################################################################
10104 13:22:31.659121
10105 13:22:32.344709 00d80000 ################################################################
10106 13:22:32.345285
10107 13:22:33.024761 00e00000 ################################################################
10108 13:22:33.025268
10109 13:22:33.707850 00e80000 ################################################################
10110 13:22:33.708465
10111 13:22:34.385335 00f00000 ################################################################
10112 13:22:34.385865
10113 13:22:35.067504 00f80000 ################################################################
10114 13:22:35.068197
10115 13:22:35.661653 01000000 ################################################################
10116 13:22:35.661787
10117 13:22:36.261104 01080000 ################################################################
10118 13:22:36.261605
10119 13:22:36.866911 01100000 ################################################################
10120 13:22:36.867400
10121 13:22:37.471533 01180000 ################################################################
10122 13:22:37.471665
10123 13:22:38.050416 01200000 ################################################################
10124 13:22:38.050567
10125 13:22:38.697751 01280000 ################################################################
10126 13:22:38.697894
10127 13:22:39.316758 01300000 ################################################################
10128 13:22:39.316894
10129 13:22:39.965179 01380000 ################################################################
10130 13:22:39.965326
10131 13:22:40.622998 01400000 ################################################################
10132 13:22:40.623508
10133 13:22:41.308393 01480000 ################################################################
10134 13:22:41.308899
10135 13:22:42.000846 01500000 ################################################################
10136 13:22:42.001354
10137 13:22:42.685111 01580000 ################################################################
10138 13:22:42.685617
10139 13:22:43.311758 01600000 ################################################################
10140 13:22:43.311894
10141 13:22:43.922402 01680000 ################################################################
10142 13:22:43.922542
10143 13:22:44.556352 01700000 ################################################################
10144 13:22:44.556883
10145 13:22:45.248018 01780000 ################################################################
10146 13:22:45.248527
10147 13:22:45.936200 01800000 ################################################################
10148 13:22:45.936709
10149 13:22:46.568474 01880000 ################################################################
10150 13:22:46.568641
10151 13:22:47.189250 01900000 ################################################################
10152 13:22:47.189383
10153 13:22:47.812866 01980000 ################################################################
10154 13:22:47.813010
10155 13:22:48.417672 01a00000 ################################################################
10156 13:22:48.417805
10157 13:22:49.001657 01a80000 ################################################################
10158 13:22:49.001838
10159 13:22:49.663613 01b00000 ################################################################
10160 13:22:49.664149
10161 13:22:50.299304 01b80000 ################################################################
10162 13:22:50.299448
10163 13:22:50.960441 01c00000 ################################################################
10164 13:22:50.960949
10165 13:22:51.631078 01c80000 ################################################################
10166 13:22:51.631503
10167 13:22:52.310929 01d00000 ################################################################
10168 13:22:52.311480
10169 13:22:52.998031 01d80000 ################################################################
10170 13:22:52.998554
10171 13:22:53.673599 01e00000 ################################################################
10172 13:22:53.674154
10173 13:22:54.359935 01e80000 ################################################################
10174 13:22:54.360470
10175 13:22:55.044423 01f00000 ################################################################
10176 13:22:55.044946
10177 13:22:55.721331 01f80000 ################################################################
10178 13:22:55.721855
10179 13:22:56.394737 02000000 ################################################################
10180 13:22:56.395259
10181 13:22:57.084507 02080000 ################################################################
10182 13:22:57.085070
10183 13:22:57.780650 02100000 ################################################################
10184 13:22:57.781202
10185 13:22:58.453256 02180000 ################################################################
10186 13:22:58.453818
10187 13:22:59.128578 02200000 ################################################################
10188 13:22:59.129084
10189 13:22:59.813462 02280000 ################################################################
10190 13:22:59.813971
10191 13:23:00.502611 02300000 ################################################################
10192 13:23:00.503133
10193 13:23:01.170322 02380000 ################################################################
10194 13:23:01.170846
10195 13:23:01.820508 02400000 ################################################################
10196 13:23:01.821019
10197 13:23:02.434034 02480000 ################################################################
10198 13:23:02.434180
10199 13:23:03.049063 02500000 ################################################################
10200 13:23:03.049212
10201 13:23:03.644850 02580000 ################################################################
10202 13:23:03.644989
10203 13:23:04.294916 02600000 ################################################################
10204 13:23:04.295428
10205 13:23:04.988716 02680000 ################################################################
10206 13:23:04.989230
10207 13:23:05.672730 02700000 ################################################################
10208 13:23:05.673252
10209 13:23:06.347485 02780000 ################################################################
10210 13:23:06.348046
10211 13:23:07.018837 02800000 ################################################################
10212 13:23:07.019344
10213 13:23:07.689460 02880000 ################################################################
10214 13:23:07.690050
10215 13:23:08.282484 02900000 ################################################################
10216 13:23:08.282625
10217 13:23:08.928563 02980000 ################################################################
10218 13:23:08.929096
10219 13:23:09.610913 02a00000 ################################################################
10220 13:23:09.611428
10221 13:23:10.292508 02a80000 ################################################################
10222 13:23:10.293021
10223 13:23:10.985355 02b00000 ################################################################
10224 13:23:10.985876
10225 13:23:11.656710 02b80000 ################################################################
10226 13:23:11.657224
10227 13:23:12.320543 02c00000 ################################################################
10228 13:23:12.321059
10229 13:23:12.995461 02c80000 ################################################################
10230 13:23:12.996023
10231 13:23:13.685674 02d00000 ################################################################
10232 13:23:13.686181
10233 13:23:14.368644 02d80000 ################################################################
10234 13:23:14.368795
10235 13:23:14.999880 02e00000 ################################################################
10236 13:23:15.000076
10237 13:23:15.660588 02e80000 ################################################################
10238 13:23:15.661232
10239 13:23:16.339557 02f00000 ################################################################
10240 13:23:16.340102
10241 13:23:17.015891 02f80000 ################################################################
10242 13:23:17.016432
10243 13:23:17.140209 03000000 ############ done.
10244 13:23:17.140664
10245 13:23:17.143265 The bootfile was 50428034 bytes long.
10246 13:23:17.143782
10247 13:23:17.146465 Sending tftp read request... done.
10248 13:23:17.146882
10249 13:23:17.150633 Waiting for the transfer...
10250 13:23:17.151049
10251 13:23:17.151378 00000000 # done.
10252 13:23:17.151699
10253 13:23:17.157148 Command line loaded dynamically from TFTP file: 11445616/tftp-deploy-92azwfrb/kernel/cmdline
10254 13:23:17.157595
10255 13:23:17.174286 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10256 13:23:17.174811
10257 13:23:17.175136 Loading FIT.
10258 13:23:17.175439
10259 13:23:17.176967 Image ramdisk-1 has 39340497 bytes.
10260 13:23:17.177381
10261 13:23:17.181358 Image fdt-1 has 47278 bytes.
10262 13:23:17.181871
10263 13:23:17.183607 Image kernel-1 has 11038222 bytes.
10264 13:23:17.184065
10265 13:23:17.190352 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10266 13:23:17.190871
10267 13:23:17.210030 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10268 13:23:17.210555
10269 13:23:17.213546 Choosing best match conf-1 for compat google,spherion-rev2.
10270 13:23:17.218411
10271 13:23:17.222748 Connected to device vid:did:rid of 1ae0:0028:00
10272 13:23:17.229612
10273 13:23:17.233152 tpm_get_response: command 0x17b, return code 0x0
10274 13:23:17.233711
10275 13:23:17.236422 ec_init: CrosEC protocol v3 supported (256, 248)
10276 13:23:17.240874
10277 13:23:17.244195 tpm_cleanup: add release locality here.
10278 13:23:17.244734
10279 13:23:17.245101 Shutting down all USB controllers.
10280 13:23:17.247423
10281 13:23:17.247880 Removing current net device
10282 13:23:17.248301
10283 13:23:17.253425 Exiting depthcharge with code 4 at timestamp: 98571336
10284 13:23:17.253925
10285 13:23:17.257069 LZMA decompressing kernel-1 to 0x821a6718
10286 13:23:17.257489
10287 13:23:17.260429 LZMA decompressing kernel-1 to 0x40000000
10288 13:23:18.647849
10289 13:23:18.648460 jumping to kernel
10290 13:23:18.649986 end: 2.2.4 bootloader-commands (duration 00:01:11) [common]
10291 13:23:18.650508 start: 2.2.5 auto-login-action (timeout 00:03:15) [common]
10292 13:23:18.650908 Setting prompt string to ['Linux version [0-9]']
10293 13:23:18.651273 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10294 13:23:18.651642 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10295 13:23:18.729916
10296 13:23:18.733219 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10297 13:23:18.737074 start: 2.2.5.1 login-action (timeout 00:03:14) [common]
10298 13:23:18.737646 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10299 13:23:18.738036 Setting prompt string to []
10300 13:23:18.738457 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10301 13:23:18.738940 Using line separator: #'\n'#
10302 13:23:18.739338 No login prompt set.
10303 13:23:18.739704 Parsing kernel messages
10304 13:23:18.740073 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10305 13:23:18.740627 [login-action] Waiting for messages, (timeout 00:03:14)
10306 13:23:18.755897 [ 0.000000] Linux version 6.1.46-cip4 (KernelCI@build-j36642-arm64-gcc-10-defconfig-arm64-chromebook-rxg94) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Sep 6 13:11:19 UTC 2023
10307 13:23:18.758717 [ 0.000000] random: crng init done
10308 13:23:18.765384 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10309 13:23:18.768868 [ 0.000000] efi: UEFI not found.
10310 13:23:18.775350 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10311 13:23:18.781937 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10312 13:23:18.791744 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10313 13:23:18.802592 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10314 13:23:18.808916 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10315 13:23:18.815831 [ 0.000000] printk: bootconsole [mtk8250] enabled
10316 13:23:18.822158 [ 0.000000] NUMA: No NUMA configuration found
10317 13:23:18.828113 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10318 13:23:18.831663 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10319 13:23:18.836282 [ 0.000000] Zone ranges:
10320 13:23:18.841951 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10321 13:23:18.845334 [ 0.000000] DMA32 empty
10322 13:23:18.851543 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10323 13:23:18.855261 [ 0.000000] Movable zone start for each node
10324 13:23:18.859079 [ 0.000000] Early memory node ranges
10325 13:23:18.865049 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10326 13:23:18.871140 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10327 13:23:18.877645 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10328 13:23:18.884352 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10329 13:23:18.891119 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10330 13:23:18.897597 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10331 13:23:18.954290 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10332 13:23:18.960509 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10333 13:23:18.967170 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10334 13:23:18.970912 [ 0.000000] psci: probing for conduit method from DT.
10335 13:23:18.977662 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10336 13:23:18.979962 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10337 13:23:18.986938 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10338 13:23:18.990141 [ 0.000000] psci: SMC Calling Convention v1.2
10339 13:23:18.997188 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10340 13:23:18.999760 [ 0.000000] Detected VIPT I-cache on CPU0
10341 13:23:19.006785 [ 0.000000] CPU features: detected: GIC system register CPU interface
10342 13:23:19.013584 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10343 13:23:19.020855 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10344 13:23:19.026783 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10345 13:23:19.036305 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10346 13:23:19.043203 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10347 13:23:19.046621 [ 0.000000] alternatives: applying boot alternatives
10348 13:23:19.053003 [ 0.000000] Fallback order for Node 0: 0
10349 13:23:19.059485 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10350 13:23:19.062639 [ 0.000000] Policy zone: Normal
10351 13:23:19.076316 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10352 13:23:19.086042 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10353 13:23:19.097184 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10354 13:23:19.107447 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10355 13:23:19.114566 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10356 13:23:19.116958 <6>[ 0.000000] software IO TLB: area num 8.
10357 13:23:19.174065 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10358 13:23:19.322432 <6>[ 0.000000] Memory: 7931136K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 421632K reserved, 32768K cma-reserved)
10359 13:23:19.329483 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10360 13:23:19.335897 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10361 13:23:19.339358 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10362 13:23:19.346318 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10363 13:23:19.353165 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10364 13:23:19.355535 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10365 13:23:19.365575 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10366 13:23:19.372466 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10367 13:23:19.379099 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10368 13:23:19.385337 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10369 13:23:19.388656 <6>[ 0.000000] GICv3: 608 SPIs implemented
10370 13:23:19.392574 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10371 13:23:19.399050 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10372 13:23:19.402756 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10373 13:23:19.408404 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10374 13:23:19.422048 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10375 13:23:19.435024 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10376 13:23:19.442073 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10377 13:23:19.449894 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10378 13:23:19.462705 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10379 13:23:19.469035 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10380 13:23:19.476433 <6>[ 0.009185] Console: colour dummy device 80x25
10381 13:23:19.486190 <6>[ 0.013912] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10382 13:23:19.492941 <6>[ 0.024354] pid_max: default: 32768 minimum: 301
10383 13:23:19.495844 <6>[ 0.029226] LSM: Security Framework initializing
10384 13:23:19.502793 <6>[ 0.034166] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10385 13:23:19.512646 <6>[ 0.042028] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10386 13:23:19.522605 <6>[ 0.051462] cblist_init_generic: Setting adjustable number of callback queues.
10387 13:23:19.526322 <6>[ 0.058955] cblist_init_generic: Setting shift to 3 and lim to 1.
10388 13:23:19.535569 <6>[ 0.065332] cblist_init_generic: Setting adjustable number of callback queues.
10389 13:23:19.543342 <6>[ 0.072758] cblist_init_generic: Setting shift to 3 and lim to 1.
10390 13:23:19.546001 <6>[ 0.079158] rcu: Hierarchical SRCU implementation.
10391 13:23:19.551971 <6>[ 0.084171] rcu: Max phase no-delay instances is 1000.
10392 13:23:19.558516 <6>[ 0.091245] EFI services will not be available.
10393 13:23:19.562363 <6>[ 0.096212] smp: Bringing up secondary CPUs ...
10394 13:23:19.570341 <6>[ 0.101298] Detected VIPT I-cache on CPU1
10395 13:23:19.576980 <6>[ 0.101367] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10396 13:23:19.583786 <6>[ 0.101399] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10397 13:23:19.587030 <6>[ 0.101729] Detected VIPT I-cache on CPU2
10398 13:23:19.597052 <6>[ 0.101782] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10399 13:23:19.603683 <6>[ 0.101798] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10400 13:23:19.606453 <6>[ 0.102061] Detected VIPT I-cache on CPU3
10401 13:23:19.613045 <6>[ 0.102107] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10402 13:23:19.620022 <6>[ 0.102120] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10403 13:23:19.626724 <6>[ 0.102428] CPU features: detected: Spectre-v4
10404 13:23:19.630484 <6>[ 0.102434] CPU features: detected: Spectre-BHB
10405 13:23:19.633520 <6>[ 0.102439] Detected PIPT I-cache on CPU4
10406 13:23:19.640182 <6>[ 0.102495] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10407 13:23:19.646280 <6>[ 0.102511] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10408 13:23:19.652838 <6>[ 0.102801] Detected PIPT I-cache on CPU5
10409 13:23:19.659552 <6>[ 0.102861] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10410 13:23:19.665663 <6>[ 0.102878] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10411 13:23:19.669811 <6>[ 0.103162] Detected PIPT I-cache on CPU6
10412 13:23:19.679424 <6>[ 0.103225] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10413 13:23:19.686276 <6>[ 0.103242] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10414 13:23:19.689018 <6>[ 0.103541] Detected PIPT I-cache on CPU7
10415 13:23:19.695791 <6>[ 0.103605] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10416 13:23:19.701969 <6>[ 0.103622] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10417 13:23:19.705632 <6>[ 0.103668] smp: Brought up 1 node, 8 CPUs
10418 13:23:19.712015 <6>[ 0.244939] SMP: Total of 8 processors activated.
10419 13:23:19.718593 <6>[ 0.249860] CPU features: detected: 32-bit EL0 Support
10420 13:23:19.724823 <6>[ 0.255222] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10421 13:23:19.732028 <6>[ 0.264022] CPU features: detected: Common not Private translations
10422 13:23:19.738397 <6>[ 0.270497] CPU features: detected: CRC32 instructions
10423 13:23:19.745563 <6>[ 0.275848] CPU features: detected: RCpc load-acquire (LDAPR)
10424 13:23:19.748637 <6>[ 0.281829] CPU features: detected: LSE atomic instructions
10425 13:23:19.754875 <6>[ 0.287637] CPU features: detected: Privileged Access Never
10426 13:23:19.761603 <6>[ 0.293417] CPU features: detected: RAS Extension Support
10427 13:23:19.768407 <6>[ 0.299060] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10428 13:23:19.771554 <6>[ 0.306279] CPU: All CPU(s) started at EL2
10429 13:23:19.778044 <6>[ 0.310595] alternatives: applying system-wide alternatives
10430 13:23:19.788579 <6>[ 0.321295] devtmpfs: initialized
10431 13:23:19.804470 <6>[ 0.330122] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10432 13:23:19.810009 <6>[ 0.340085] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10433 13:23:19.816625 <6>[ 0.348101] pinctrl core: initialized pinctrl subsystem
10434 13:23:19.820780 <6>[ 0.354787] DMI not present or invalid.
10435 13:23:19.826488 <6>[ 0.359197] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10436 13:23:19.836749 <6>[ 0.366043] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10437 13:23:19.843342 <6>[ 0.373624] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10438 13:23:19.853512 <6>[ 0.381838] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10439 13:23:19.856240 <6>[ 0.390082] audit: initializing netlink subsys (disabled)
10440 13:23:19.867615 <5>[ 0.395764] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10441 13:23:19.872701 <6>[ 0.396447] thermal_sys: Registered thermal governor 'step_wise'
10442 13:23:19.879882 <6>[ 0.403732] thermal_sys: Registered thermal governor 'power_allocator'
10443 13:23:19.882455 <6>[ 0.409990] cpuidle: using governor menu
10444 13:23:19.889095 <6>[ 0.420950] NET: Registered PF_QIPCRTR protocol family
10445 13:23:19.895539 <6>[ 0.426426] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10446 13:23:19.902097 <6>[ 0.433531] ASID allocator initialised with 32768 entries
10447 13:23:19.905815 <6>[ 0.440106] Serial: AMBA PL011 UART driver
10448 13:23:19.915961 <4>[ 0.448841] Trying to register duplicate clock ID: 134
10449 13:23:19.969605 <6>[ 0.505957] KASLR enabled
10450 13:23:19.984129 <6>[ 0.513592] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10451 13:23:19.990636 <6>[ 0.520605] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10452 13:23:19.997123 <6>[ 0.527094] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10453 13:23:20.003834 <6>[ 0.534098] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10454 13:23:20.010089 <6>[ 0.540586] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10455 13:23:20.016531 <6>[ 0.547588] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10456 13:23:20.023205 <6>[ 0.554076] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10457 13:23:20.029978 <6>[ 0.561081] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10458 13:23:20.033528 <6>[ 0.568642] ACPI: Interpreter disabled.
10459 13:23:20.042665 <6>[ 0.575055] iommu: Default domain type: Translated
10460 13:23:20.049016 <6>[ 0.580170] iommu: DMA domain TLB invalidation policy: strict mode
10461 13:23:20.051993 <5>[ 0.586832] SCSI subsystem initialized
10462 13:23:20.059182 <6>[ 0.591004] usbcore: registered new interface driver usbfs
10463 13:23:20.065424 <6>[ 0.596733] usbcore: registered new interface driver hub
10464 13:23:20.069075 <6>[ 0.602282] usbcore: registered new device driver usb
10465 13:23:20.075275 <6>[ 0.608382] pps_core: LinuxPPS API ver. 1 registered
10466 13:23:20.084838 <6>[ 0.613577] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10467 13:23:20.088476 <6>[ 0.622921] PTP clock support registered
10468 13:23:20.091587 <6>[ 0.627160] EDAC MC: Ver: 3.0.0
10469 13:23:20.099520 <6>[ 0.632322] FPGA manager framework
10470 13:23:20.106324 <6>[ 0.636006] Advanced Linux Sound Architecture Driver Initialized.
10471 13:23:20.108673 <6>[ 0.642767] vgaarb: loaded
10472 13:23:20.115382 <6>[ 0.645928] clocksource: Switched to clocksource arch_sys_counter
10473 13:23:20.118963 <5>[ 0.652371] VFS: Disk quotas dquot_6.6.0
10474 13:23:20.126075 <6>[ 0.656558] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10475 13:23:20.128620 <6>[ 0.663726] pnp: PnP ACPI: disabled
10476 13:23:20.137494 <6>[ 0.670400] NET: Registered PF_INET protocol family
10477 13:23:20.146905 <6>[ 0.675993] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10478 13:23:20.158369 <6>[ 0.688324] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10479 13:23:20.168377 <6>[ 0.697141] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10480 13:23:20.174920 <6>[ 0.705113] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10481 13:23:20.181731 <6>[ 0.713813] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10482 13:23:20.193645 <6>[ 0.723557] TCP: Hash tables configured (established 65536 bind 65536)
10483 13:23:20.200427 <6>[ 0.730420] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10484 13:23:20.206841 <6>[ 0.737618] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10485 13:23:20.213392 <6>[ 0.745327] NET: Registered PF_UNIX/PF_LOCAL protocol family
10486 13:23:20.220289 <6>[ 0.751509] RPC: Registered named UNIX socket transport module.
10487 13:23:20.223251 <6>[ 0.757663] RPC: Registered udp transport module.
10488 13:23:20.229604 <6>[ 0.762595] RPC: Registered tcp transport module.
10489 13:23:20.236068 <6>[ 0.767527] RPC: Registered tcp NFSv4.1 backchannel transport module.
10490 13:23:20.239495 <6>[ 0.774196] PCI: CLS 0 bytes, default 64
10491 13:23:20.243046 <6>[ 0.778590] Unpacking initramfs...
10492 13:23:20.268382 <6>[ 0.798083] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10493 13:23:20.278181 <6>[ 0.806750] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10494 13:23:20.281626 <6>[ 0.815605] kvm [1]: IPA Size Limit: 40 bits
10495 13:23:20.288052 <6>[ 0.820135] kvm [1]: GICv3: no GICV resource entry
10496 13:23:20.291894 <6>[ 0.825156] kvm [1]: disabling GICv2 emulation
10497 13:23:20.297884 <6>[ 0.829845] kvm [1]: GIC system register CPU interface enabled
10498 13:23:20.301253 <6>[ 0.836007] kvm [1]: vgic interrupt IRQ18
10499 13:23:20.307780 <6>[ 0.840366] kvm [1]: VHE mode initialized successfully
10500 13:23:20.314383 <5>[ 0.846874] Initialise system trusted keyrings
10501 13:23:20.320937 <6>[ 0.851684] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10502 13:23:20.328641 <6>[ 0.861696] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10503 13:23:20.335716 <5>[ 0.868087] NFS: Registering the id_resolver key type
10504 13:23:20.338553 <5>[ 0.873390] Key type id_resolver registered
10505 13:23:20.346103 <5>[ 0.877806] Key type id_legacy registered
10506 13:23:20.351476 <6>[ 0.882086] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10507 13:23:20.358266 <6>[ 0.889007] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10508 13:23:20.364885 <6>[ 0.896724] 9p: Installing v9fs 9p2000 file system support
10509 13:23:20.403226 <5>[ 0.935507] Key type asymmetric registered
10510 13:23:20.405729 <5>[ 0.939838] Asymmetric key parser 'x509' registered
10511 13:23:20.415715 <6>[ 0.945038] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10512 13:23:20.419247 <6>[ 0.952655] io scheduler mq-deadline registered
10513 13:23:20.421744 <6>[ 0.957425] io scheduler kyber registered
10514 13:23:20.441512 <6>[ 0.974330] EINJ: ACPI disabled.
10515 13:23:20.473289 <4>[ 0.999632] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10516 13:23:20.482857 <4>[ 1.010247] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10517 13:23:20.498034 <6>[ 1.031050] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10518 13:23:20.505620 <6>[ 1.039115] printk: console [ttyS0] disabled
10519 13:23:20.534008 <6>[ 1.063761] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10520 13:23:20.540640 <6>[ 1.073243] printk: console [ttyS0] enabled
10521 13:23:20.543938 <6>[ 1.073243] printk: console [ttyS0] enabled
10522 13:23:20.550513 <6>[ 1.082142] printk: bootconsole [mtk8250] disabled
10523 13:23:20.553950 <6>[ 1.082142] printk: bootconsole [mtk8250] disabled
10524 13:23:20.560217 <6>[ 1.093452] SuperH (H)SCI(F) driver initialized
10525 13:23:20.563624 <6>[ 1.098740] msm_serial: driver initialized
10526 13:23:20.578247 <6>[ 1.107771] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10527 13:23:20.587621 <6>[ 1.116317] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10528 13:23:20.594361 <6>[ 1.124860] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10529 13:23:20.604237 <6>[ 1.133489] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10530 13:23:20.614123 <6>[ 1.142196] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10531 13:23:20.620644 <6>[ 1.150918] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10532 13:23:20.631117 <6>[ 1.159460] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10533 13:23:20.637569 <6>[ 1.168263] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10534 13:23:20.647718 <6>[ 1.176808] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10535 13:23:20.659262 <6>[ 1.192367] loop: module loaded
10536 13:23:20.665526 <6>[ 1.198322] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10537 13:23:20.688603 <4>[ 1.221673] mtk-pmic-keys: Failed to locate of_node [id: -1]
10538 13:23:20.695335 <6>[ 1.228566] megasas: 07.719.03.00-rc1
10539 13:23:20.704807 <6>[ 1.238215] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10540 13:23:20.712019 <6>[ 1.245313] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10541 13:23:20.729149 <6>[ 1.262188] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10542 13:23:20.785745 <6>[ 1.312369] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10543 13:23:21.835163 <6>[ 2.368686] Freeing initrd memory: 38416K
10544 13:23:21.845583 <6>[ 2.379096] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10545 13:23:21.856411 <6>[ 2.390029] tun: Universal TUN/TAP device driver, 1.6
10546 13:23:21.860244 <6>[ 2.396089] thunder_xcv, ver 1.0
10547 13:23:21.863220 <6>[ 2.399599] thunder_bgx, ver 1.0
10548 13:23:21.866194 <6>[ 2.403096] nicpf, ver 1.0
10549 13:23:21.877392 <6>[ 2.407087] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10550 13:23:21.880356 <6>[ 2.414561] hns3: Copyright (c) 2017 Huawei Corporation.
10551 13:23:21.887204 <6>[ 2.420151] hclge is initializing
10552 13:23:21.890643 <6>[ 2.423727] e1000: Intel(R) PRO/1000 Network Driver
10553 13:23:21.896860 <6>[ 2.428856] e1000: Copyright (c) 1999-2006 Intel Corporation.
10554 13:23:21.900384 <6>[ 2.434869] e1000e: Intel(R) PRO/1000 Network Driver
10555 13:23:21.906702 <6>[ 2.440084] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10556 13:23:21.913224 <6>[ 2.446268] igb: Intel(R) Gigabit Ethernet Network Driver
10557 13:23:21.920495 <6>[ 2.451918] igb: Copyright (c) 2007-2014 Intel Corporation.
10558 13:23:21.926577 <6>[ 2.457752] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10559 13:23:21.933125 <6>[ 2.464271] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10560 13:23:21.936843 <6>[ 2.470732] sky2: driver version 1.30
10561 13:23:21.943369 <6>[ 2.475716] VFIO - User Level meta-driver version: 0.3
10562 13:23:21.950491 <6>[ 2.483942] usbcore: registered new interface driver usb-storage
10563 13:23:21.956849 <6>[ 2.490382] usbcore: registered new device driver onboard-usb-hub
10564 13:23:21.965966 <6>[ 2.499478] mt6397-rtc mt6359-rtc: registered as rtc0
10565 13:23:21.976800 <6>[ 2.504944] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-06T13:23:22 UTC (1694006602)
10566 13:23:21.979390 <6>[ 2.514510] i2c_dev: i2c /dev entries driver
10567 13:23:21.996120 <6>[ 2.526212] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10568 13:23:22.016253 <6>[ 2.549187] cpu cpu0: EM: created perf domain
10569 13:23:22.018785 <6>[ 2.554173] cpu cpu4: EM: created perf domain
10570 13:23:22.026059 <6>[ 2.559767] sdhci: Secure Digital Host Controller Interface driver
10571 13:23:22.033155 <6>[ 2.566202] sdhci: Copyright(c) Pierre Ossman
10572 13:23:22.040229 <6>[ 2.571153] Synopsys Designware Multimedia Card Interface Driver
10573 13:23:22.046823 <6>[ 2.577782] sdhci-pltfm: SDHCI platform and OF driver helper
10574 13:23:22.049509 <6>[ 2.577881] mmc0: CQHCI version 5.10
10575 13:23:22.056203 <6>[ 2.588147] ledtrig-cpu: registered to indicate activity on CPUs
10576 13:23:22.063057 <6>[ 2.595199] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10577 13:23:22.069454 <6>[ 2.602277] usbcore: registered new interface driver usbhid
10578 13:23:22.072342 <6>[ 2.608100] usbhid: USB HID core driver
10579 13:23:22.079335 <6>[ 2.612308] spi_master spi0: will run message pump with realtime priority
10580 13:23:22.122735 <6>[ 2.649740] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10581 13:23:22.141885 <6>[ 2.664826] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10582 13:23:22.148443 <6>[ 2.679890] cros-ec-spi spi0.0: Chrome EC device registered
10583 13:23:22.152055 <6>[ 2.685964] mmc0: Command Queue Engine enabled
10584 13:23:22.158746 <6>[ 2.690695] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10585 13:23:22.164937 <6>[ 2.698320] mmcblk0: mmc0:0001 DA4128 116 GiB
10586 13:23:22.174034 <6>[ 2.707279] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10587 13:23:22.181612 <6>[ 2.714504] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10588 13:23:22.188107 <6>[ 2.720583] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10589 13:23:22.197583 <6>[ 2.725688] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10590 13:23:22.204290 <6>[ 2.726461] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10591 13:23:22.207472 <6>[ 2.736421] NET: Registered PF_PACKET protocol family
10592 13:23:22.213878 <6>[ 2.747016] 9pnet: Installing 9P2000 support
10593 13:23:22.218047 <5>[ 2.751579] Key type dns_resolver registered
10594 13:23:22.224548 <6>[ 2.756586] registered taskstats version 1
10595 13:23:22.227056 <5>[ 2.760970] Loading compiled-in X.509 certificates
10596 13:23:22.258112 <4>[ 2.784956] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10597 13:23:22.268395 <4>[ 2.795703] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10598 13:23:22.275218 <3>[ 2.806286] debugfs: File 'uA_load' in directory '/' already present!
10599 13:23:22.281195 <3>[ 2.812995] debugfs: File 'min_uV' in directory '/' already present!
10600 13:23:22.288313 <3>[ 2.819606] debugfs: File 'max_uV' in directory '/' already present!
10601 13:23:22.294792 <3>[ 2.826218] debugfs: File 'constraint_flags' in directory '/' already present!
10602 13:23:22.305734 <3>[ 2.835779] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10603 13:23:22.314517 <6>[ 2.848011] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10604 13:23:22.321745 <6>[ 2.854813] xhci-mtk 11200000.usb: xHCI Host Controller
10605 13:23:22.328271 <6>[ 2.860321] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10606 13:23:22.338214 <6>[ 2.868165] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10607 13:23:22.345808 <6>[ 2.877580] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10608 13:23:22.351383 <6>[ 2.883659] xhci-mtk 11200000.usb: xHCI Host Controller
10609 13:23:22.357816 <6>[ 2.889134] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10610 13:23:22.365044 <6>[ 2.896778] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10611 13:23:22.371127 <6>[ 2.904407] hub 1-0:1.0: USB hub found
10612 13:23:22.374183 <6>[ 2.908415] hub 1-0:1.0: 1 port detected
10613 13:23:22.380891 <6>[ 2.912680] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10614 13:23:22.387784 <6>[ 2.921217] hub 2-0:1.0: USB hub found
10615 13:23:22.391829 <6>[ 2.925222] hub 2-0:1.0: 1 port detected
10616 13:23:22.399685 <6>[ 2.932982] mtk-msdc 11f70000.mmc: Got CD GPIO
10617 13:23:22.410970 <6>[ 2.941233] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10618 13:23:22.417547 <6>[ 2.949269] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10619 13:23:22.427754 <4>[ 2.957178] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10620 13:23:22.437994 <6>[ 2.966709] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10621 13:23:22.444034 <6>[ 2.974785] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10622 13:23:22.454256 <6>[ 2.982931] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10623 13:23:22.460801 <6>[ 2.990867] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10624 13:23:22.467298 <6>[ 2.998684] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10625 13:23:22.477186 <6>[ 3.006502] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10626 13:23:22.487518 <6>[ 3.016937] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10627 13:23:22.493703 <6>[ 3.025324] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10628 13:23:22.503809 <6>[ 3.033662] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10629 13:23:22.513843 <6>[ 3.042007] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10630 13:23:22.519872 <6>[ 3.050346] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10631 13:23:22.530557 <6>[ 3.058684] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10632 13:23:22.536796 <6>[ 3.067021] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10633 13:23:22.546647 <6>[ 3.075358] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10634 13:23:22.553605 <6>[ 3.083696] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10635 13:23:22.562840 <6>[ 3.092034] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10636 13:23:22.570105 <6>[ 3.100372] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10637 13:23:22.579290 <6>[ 3.108709] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10638 13:23:22.586186 <6>[ 3.117047] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10639 13:23:22.596109 <6>[ 3.125385] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10640 13:23:22.603194 <6>[ 3.133723] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10641 13:23:22.609477 <6>[ 3.142484] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10642 13:23:22.615784 <6>[ 3.149645] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10643 13:23:22.622779 <6>[ 3.156422] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10644 13:23:22.630594 <6>[ 3.163190] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10645 13:23:22.640630 <6>[ 3.170133] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10646 13:23:22.646632 <6>[ 3.176983] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10647 13:23:22.656619 <6>[ 3.186115] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10648 13:23:22.666566 <6>[ 3.195235] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10649 13:23:22.676096 <6>[ 3.204533] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10650 13:23:22.686457 <6>[ 3.214006] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10651 13:23:22.692873 <6>[ 3.223474] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10652 13:23:22.702601 <6>[ 3.232595] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10653 13:23:22.712450 <6>[ 3.242079] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10654 13:23:22.722776 <6>[ 3.251199] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10655 13:23:22.732286 <6>[ 3.260494] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10656 13:23:22.742366 <6>[ 3.270654] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10657 13:23:22.752489 <6>[ 3.282687] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10658 13:23:22.780819 <6>[ 3.310479] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10659 13:23:22.808341 <6>[ 3.341328] hub 2-1:1.0: USB hub found
10660 13:23:22.811338 <6>[ 3.345727] hub 2-1:1.0: 3 ports detected
10661 13:23:22.932685 <6>[ 3.462195] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10662 13:23:23.086577 <6>[ 3.619993] hub 1-1:1.0: USB hub found
10663 13:23:23.089859 <6>[ 3.624453] hub 1-1:1.0: 4 ports detected
10664 13:23:23.168182 <6>[ 3.698516] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10665 13:23:23.411816 <6>[ 3.942326] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10666 13:23:23.544079 <6>[ 4.077843] hub 1-1.4:1.0: USB hub found
10667 13:23:23.547413 <6>[ 4.082483] hub 1-1.4:1.0: 2 ports detected
10668 13:23:23.844400 <6>[ 4.374247] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10669 13:23:24.035371 <6>[ 4.566246] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10670 13:23:35.029044 <6>[ 15.567227] ALSA device list:
10671 13:23:35.035737 <6>[ 15.570525] No soundcards found.
10672 13:23:35.043075 <6>[ 15.578471] Freeing unused kernel memory: 8384K
10673 13:23:35.046175 <6>[ 15.583559] Run /init as init process
10674 13:23:35.095966 <6>[ 15.631532] NET: Registered PF_INET6 protocol family
10675 13:23:35.102699 <6>[ 15.637938] Segment Routing with IPv6
10676 13:23:35.105835 <6>[ 15.641876] In-situ OAM (IOAM) with IPv6
10677 13:23:35.143434 <30>[ 15.659040] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10678 13:23:35.146680 <30>[ 15.683144] systemd[1]: Detected architecture arm64.
10679 13:23:35.149940
10680 13:23:35.153593 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10681 13:23:35.153677
10682 13:23:35.166669 <30>[ 15.702263] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10683 13:23:35.328230 <30>[ 15.860307] systemd[1]: Queued start job for default target Graphical Interface.
10684 13:23:35.359478 <30>[ 15.895128] systemd[1]: Created slice system-getty.slice.
10685 13:23:35.366209 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10686 13:23:35.383259 <30>[ 15.918666] systemd[1]: Created slice system-modprobe.slice.
10687 13:23:35.389881 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10688 13:23:35.407694 <30>[ 15.942927] systemd[1]: Created slice system-serial\x2dgetty.slice.
10689 13:23:35.417343 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10690 13:23:35.431620 <30>[ 15.967232] systemd[1]: Created slice User and Session Slice.
10691 13:23:35.438058 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10692 13:23:35.458775 <30>[ 15.990747] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10693 13:23:35.468139 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10694 13:23:35.486535 <30>[ 16.018737] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10695 13:23:35.494195 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10696 13:23:35.514613 <30>[ 16.042270] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10697 13:23:35.520069 <30>[ 16.054410] systemd[1]: Reached target Local Encrypted Volumes.
10698 13:23:35.526842 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10699 13:23:35.544309 <30>[ 16.078745] systemd[1]: Reached target Paths.
10700 13:23:35.546713 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10701 13:23:35.563166 <30>[ 16.098211] systemd[1]: Reached target Remote File Systems.
10702 13:23:35.569249 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10703 13:23:35.587262 <30>[ 16.122584] systemd[1]: Reached target Slices.
10704 13:23:35.593673 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10705 13:23:35.607528 <30>[ 16.142245] systemd[1]: Reached target Swap.
10706 13:23:35.610411 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10707 13:23:35.630517 <30>[ 16.162716] systemd[1]: Listening on initctl Compatibility Named Pipe.
10708 13:23:35.637254 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10709 13:23:35.643825 <30>[ 16.177903] systemd[1]: Listening on Journal Audit Socket.
10710 13:23:35.650652 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10711 13:23:35.663225 <30>[ 16.198691] systemd[1]: Listening on Journal Socket (/dev/log).
10712 13:23:35.669830 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10713 13:23:35.688084 <30>[ 16.223459] systemd[1]: Listening on Journal Socket.
10714 13:23:35.694670 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10715 13:23:35.711001 <30>[ 16.242913] systemd[1]: Listening on Network Service Netlink Socket.
10716 13:23:35.717388 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10717 13:23:35.731018 <30>[ 16.266753] systemd[1]: Listening on udev Control Socket.
10718 13:23:35.738270 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10719 13:23:35.755673 <30>[ 16.291308] systemd[1]: Listening on udev Kernel Socket.
10720 13:23:35.762606 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10721 13:23:35.814722 <30>[ 16.350253] systemd[1]: Mounting Huge Pages File System...
10722 13:23:35.821329 Mounting [0;1;39mHuge Pages File System[0m...
10723 13:23:35.836450 <30>[ 16.372012] systemd[1]: Mounting POSIX Message Queue File System...
10724 13:23:35.843246 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10725 13:23:35.860420 <30>[ 16.396160] systemd[1]: Mounting Kernel Debug File System...
10726 13:23:35.867039 Mounting [0;1;39mKernel Debug File System[0m...
10727 13:23:35.886236 <30>[ 16.418523] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10728 13:23:35.898331 <30>[ 16.430425] systemd[1]: Starting Create list of static device nodes for the current kernel...
10729 13:23:35.904909 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10730 13:23:35.927531 <30>[ 16.463006] systemd[1]: Starting Load Kernel Module configfs...
10731 13:23:35.934649 Starting [0;1;39mLoad Kernel Module configfs[0m...
10732 13:23:35.955129 <30>[ 16.490709] systemd[1]: Starting Load Kernel Module drm...
10733 13:23:35.961650 Starting [0;1;39mLoad Kernel Module drm[0m...
10734 13:23:35.978864 <30>[ 16.510747] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10735 13:23:35.993186 <30>[ 16.528784] systemd[1]: Starting Journal Service...
10736 13:23:35.996827 Starting [0;1;39mJournal Service[0m...
10737 13:23:36.020184 <30>[ 16.555888] systemd[1]: Starting Load Kernel Modules...
10738 13:23:36.026955 Starting [0;1;39mLoad Kernel Modules[0m...
10739 13:23:36.055210 <30>[ 16.586922] systemd[1]: Starting Remount Root and Kernel File Systems...
10740 13:23:36.061583 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10741 13:23:36.082717 <30>[ 16.618500] systemd[1]: Starting Coldplug All udev Devices...
10742 13:23:36.089294 Starting [0;1;39mColdplug All udev Devices[0m...
10743 13:23:36.110272 <30>[ 16.645731] systemd[1]: Started Journal Service.
10744 13:23:36.117308 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10745 13:23:36.132913 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10746 13:23:36.152149 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10747 13:23:36.167551 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10748 13:23:36.187394 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10749 13:23:36.205249 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10750 13:23:36.226201 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10751 13:23:36.244322 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10752 13:23:36.263798 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10753 13:23:36.278923 See 'systemctl status systemd-remount-fs.service' for details.
10754 13:23:36.332924 Mounting [0;1;39mKernel Configuration File System[0m...
10755 13:23:36.354729 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10756 13:23:36.366684 <46>[ 16.899170] systemd-journald[184]: Received client request to flush runtime journal.
10757 13:23:36.379044 Starting [0;1;39mLoad/Save Random Seed[0m...
10758 13:23:36.402046 Starting [0;1;39mApply Kernel Variables[0m...
10759 13:23:36.420317 Starting [0;1;39mCreate System Users[0m...
10760 13:23:36.439427 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10761 13:23:36.459454 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10762 13:23:36.479419 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10763 13:23:36.496601 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10764 13:23:36.512314 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10765 13:23:36.528755 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10766 13:23:36.579421 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10767 13:23:36.604523 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10768 13:23:36.622742 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10769 13:23:36.638779 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10770 13:23:36.687643 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10771 13:23:36.715610 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10772 13:23:36.742466 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10773 13:23:36.760956 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10774 13:23:36.812985 Starting [0;1;39mNetwork Service[0m...
10775 13:23:36.837205 Starting [0;1;39mNetwork Time Synchronization[0m...
10776 13:23:36.856969 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10777 13:23:36.885238 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10778 13:23:36.906467 <6>[ 17.438794] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10779 13:23:36.913183 <6>[ 17.446480] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10780 13:23:36.923094 <6>[ 17.446487] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10781 13:23:36.934449 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10782 13:23:36.967884 <6>[ 17.500344] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10783 13:23:36.974685 <3>[ 17.508603] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10784 13:23:36.981593 <6>[ 17.513478] remoteproc remoteproc0: scp is available
10785 13:23:36.988418 <3>[ 17.516823] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10786 13:23:36.994379 <6>[ 17.522080] remoteproc remoteproc0: powering up scp
10787 13:23:37.000876 <3>[ 17.530006] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10788 13:23:37.011366 <4>[ 17.532052] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10789 13:23:37.017833 <6>[ 17.535213] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10790 13:23:37.024309 <6>[ 17.559481] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10791 13:23:37.034839 <3>[ 17.563825] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10792 13:23:37.040983 Startin<4>[ 17.563941] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10793 13:23:37.050571 g [0;1;39mLoad/<3>[ 17.582599] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10794 13:23:37.057231 Save Screen …o<6>[ 17.584046] mc: Linux media interface: v0.10
10795 13:23:37.064122 <6>[ 17.584130] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10796 13:23:37.070838 f leds:white:kbd<6>[ 17.584147] pci_bus 0000:00: root bus resource [bus 00-ff]
10797 13:23:37.077807 <6>[ 17.584156] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10798 13:23:37.087246 <6>[ 17.584162] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10799 13:23:37.093760 <6>[ 17.584203] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10800 13:23:37.103426 _backlight[0m..<6>[ 17.584229] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10801 13:23:37.103565 .
10802 13:23:37.107111 <6>[ 17.584334] pci 0000:00:00.0: supports D1 D2
10803 13:23:37.116618 <6>[ 17.584339] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10804 13:23:37.120059 <6>[ 17.588774] usbcore: registered new interface driver r8152
10805 13:23:37.129691 <6>[ 17.591428] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10806 13:23:37.136353 <3>[ 17.591845] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10807 13:23:37.142827 <6>[ 17.592982] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10808 13:23:37.149366 <6>[ 17.593036] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10809 13:23:37.159272 <6>[ 17.593064] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10810 13:23:37.165921 <6>[ 17.593083] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10811 13:23:37.169655 <6>[ 17.593225] pci 0000:01:00.0: supports D1 D2
10812 13:23:37.176531 <6>[ 17.593232] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10813 13:23:37.185973 <6>[ 17.626814] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10814 13:23:37.192390 <3>[ 17.628409] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10815 13:23:37.198928 <6>[ 17.634773] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10816 13:23:37.209151 <6>[ 17.638605] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10817 13:23:37.219334 <3>[ 17.643535] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10818 13:23:37.228646 <6>[ 17.644789] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10819 13:23:37.235634 <3>[ 17.647481] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10820 13:23:37.242335 <3>[ 17.647588] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10821 13:23:37.252406 <3>[ 17.647592] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10822 13:23:37.258833 <3>[ 17.647595] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10823 13:23:37.269284 <3>[ 17.647650] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10824 13:23:37.275440 <3>[ 17.647656] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10825 13:23:37.283257 <3>[ 17.647659] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10826 13:23:37.293116 <3>[ 17.647668] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10827 13:23:37.299728 <3>[ 17.647671] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10828 13:23:37.309857 <3>[ 17.647687] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10829 13:23:37.316348 <6>[ 17.648607] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10830 13:23:37.323074 <6>[ 17.648621] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10831 13:23:37.332915 <6>[ 17.648639] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10832 13:23:37.339709 <6>[ 17.648652] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10833 13:23:37.349721 <6>[ 17.648666] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10834 13:23:37.353498 <6>[ 17.648679] pci 0000:00:00.0: PCI bridge to [bus 01]
10835 13:23:37.363528 <6>[ 17.648687] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10836 13:23:37.369562 <6>[ 17.649057] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10837 13:23:37.376339 <6>[ 17.675816] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10838 13:23:37.383235 <6>[ 17.687051] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10839 13:23:37.393240 <4>[ 17.689134] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10840 13:23:37.399306 <4>[ 17.689134] Fallback method does not support PEC.
10841 13:23:37.406889 <6>[ 17.690270] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10842 13:23:37.412443 <6>[ 17.690278] remoteproc remoteproc0: remote processor scp is now up
10843 13:23:37.419354 <6>[ 17.690281] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10844 13:23:37.425722 <6>[ 17.709593] videodev: Linux video capture interface: v2.00
10845 13:23:37.432730 <6>[ 17.757049] usbcore: registered new interface driver cdc_ether
10846 13:23:37.435553 <6>[ 17.787097] Bluetooth: Core ver 2.22
10847 13:23:37.447514 <3>[ 17.797474] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10848 13:23:37.451928 <3>[ 17.827330] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10849 13:23:37.461909 <3>[ 17.849070] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
10850 13:23:37.471801 <3>[ 17.877160] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10851 13:23:37.475473 <6>[ 17.881449] NET: Registered PF_BLUETOOTH protocol family
10852 13:23:37.485030 <4>[ 17.882773] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10853 13:23:37.491948 <4>[ 17.882780] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10854 13:23:37.498201 <6>[ 17.943503] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10855 13:23:37.504685 <6>[ 17.947366] Bluetooth: HCI device and connection manager initialized
10856 13:23:37.511561 <6>[ 17.960196] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10857 13:23:37.517730 <6>[ 17.966682] Bluetooth: HCI socket layer initialized
10858 13:23:37.521458 <6>[ 18.011200] r8152 2-1.3:1.0 eth0: v1.12.13
10859 13:23:37.528095 <6>[ 18.016035] usbcore: registered new interface driver r8153_ecm
10860 13:23:37.531268 <6>[ 18.016991] Bluetooth: L2CAP socket layer initialized
10861 13:23:37.542309 <6>[ 18.035007] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10862 13:23:37.545778 <6>[ 18.039900] Bluetooth: SCO socket layer initialized
10863 13:23:37.555532 <5>[ 18.042131] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10864 13:23:37.562526 <6>[ 18.043019] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10865 13:23:37.575008 <6>[ 18.044745] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10866 13:23:37.578554 <6>[ 18.044869] usbcore: registered new interface driver uvcvideo
10867 13:23:37.585443 <6>[ 18.048352] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10868 13:23:37.595309 <6>[ 18.058118] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10869 13:23:37.601981 <6>[ 18.063560] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10870 13:23:37.608028 <5>[ 18.063590] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10871 13:23:37.614712 <3>[ 18.081488] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10872 13:23:37.621610 <6>[ 18.095429] usbcore: registered new interface driver btusb
10873 13:23:37.627911 <3>[ 18.102047] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10874 13:23:37.641412 <4>[ 18.102427] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10875 13:23:37.644807 <3>[ 18.102436] Bluetooth: hci0: Failed to load firmware file (-2)
10876 13:23:37.651354 <3>[ 18.102439] Bluetooth: hci0: Failed to set up firmware (-2)
10877 13:23:37.661045 <4>[ 18.102441] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10878 13:23:37.667878 Starting [0;1;39mNetwork Name Resolution[0m...
10879 13:23:37.677726 <4>[ 18.207848] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10880 13:23:37.680883 <6>[ 18.217505] cfg80211: failed to load regulatory.db
10881 13:23:37.690449 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10882 13:23:37.707147 <3>[ 18.238945] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 13:23:37.715163 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10884 13:23:37.725822 <6>[ 18.257184] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10885 13:23:37.729074 <6>[ 18.264684] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10886 13:23:37.739578 <3>[ 18.268984] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10887 13:23:37.745824 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10888 13:23:37.755864 <6>[ 18.291451] mt7921e 0000:01:00.0: ASIC revision: 79610010
10889 13:23:37.770814 <3>[ 18.303203] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10890 13:23:37.780629 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10891 13:23:37.801753 <3>[ 18.333002] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 13:23:37.807525 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10893 13:23:37.862068 <4>[ 18.391058] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10894 13:23:37.944828 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10895 13:23:37.958622 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10896 13:23:37.979085 <4>[ 18.508283] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10897 13:23:37.986060 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10898 13:23:38.003678 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10899 13:23:38.021989 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10900 13:23:38.039438 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10901 13:23:38.058731 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10902 13:23:38.079039 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10903 13:23:38.100868 <4>[ 18.630129] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10904 13:23:38.108556 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10905 13:23:38.127270 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10906 13:23:38.139377 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10907 13:23:38.154339 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10908 13:23:38.174278 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10909 13:23:38.221692 <4>[ 18.750367] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10910 13:23:38.228218 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10911 13:23:38.262546 Starting [0;1;39mUser Login Management[0m...
10912 13:23:38.283027 Starting [0;1;39mPermit User Sessions[0m...
10913 13:23:38.302660 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10914 13:23:38.330421 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10915 13:23:38.346651 <4>[ 18.875612] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10916 13:23:38.364579 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10917 13:23:38.379683 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10918 13:23:38.404362 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10919 13:23:38.420407 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10920 13:23:38.439753 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10921 13:23:38.468784 [[0;32m OK [<4>[ 18.998884] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10922 13:23:38.475076 0m] Reached target [0;1;39mMulti-User System[0m.
10923 13:23:38.491715 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10924 13:23:38.551212 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10925 13:23:38.590866 [[0;32m OK [0m] Finished [0<4>[ 19.118757] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10926 13:23:38.594741 ;1;39mUpdate UTMP about System Runlevel Changes[0m.
10927 13:23:38.613075
10928 13:23:38.613231
10929 13:23:38.616456 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10930 13:23:38.616540
10931 13:23:38.619608 debian-bullseye-arm64 login: root (automatic login)
10932 13:23:38.619694
10933 13:23:38.619759
10934 13:23:38.634573 Linux debian-bullseye-arm64 6.1.46-cip4 #1 SMP PREEMPT Wed Sep 6 13:11:19 UTC 2023 aarch64
10935 13:23:38.634718
10936 13:23:38.641388 The programs included with the Debian GNU/Linux system are free software;
10937 13:23:38.647635 the exact distribution terms for each program are described in the
10938 13:23:38.651145 individual files in /usr/share/doc/*/copyright.
10939 13:23:38.651241
10940 13:23:38.657867 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10941 13:23:38.662145 permitted by applicable law.
10942 13:23:38.662505 Matched prompt #10: / #
10944 13:23:38.662712 Setting prompt string to ['/ #']
10945 13:23:38.662804 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10947 13:23:38.662996 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10948 13:23:38.663085 start: 2.2.6 expect-shell-connection (timeout 00:02:55) [common]
10949 13:23:38.663158 Setting prompt string to ['/ #']
10950 13:23:38.663218 Forcing a shell prompt, looking for ['/ #']
10952 13:23:38.713456 / #
10953 13:23:38.713642 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10954 13:23:38.713727 Waiting using forced prompt support (timeout 00:02:30)
10955 13:23:38.714045 <4>[ 19.243080] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10956 13:23:38.756173
10957 13:23:38.756546 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10958 13:23:38.756644 start: 2.2.7 export-device-env (timeout 00:02:54) [common]
10959 13:23:38.756741 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10960 13:23:38.756831 end: 2.2 depthcharge-retry (duration 00:02:06) [common]
10961 13:23:38.756913 end: 2 depthcharge-action (duration 00:02:06) [common]
10962 13:23:38.757003 start: 3 lava-test-retry (timeout 00:07:34) [common]
10963 13:23:38.757089 start: 3.1 lava-test-shell (timeout 00:07:34) [common]
10964 13:23:38.757161 Using namespace: common
10966 13:23:38.857555 / # #
10967 13:23:38.857748 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10968 13:23:38.857913 #<4>[ 19.362788] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10969 13:23:38.863465
10970 13:23:38.863740 Using /lava-11445616
10972 13:23:38.964090 / # export SHELL=/bin/sh
10973 13:23:38.964312 export SHELL=/bin/sh<4>[ 19.482074] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10974 13:23:38.969880
10976 13:23:39.070474 / # . /lava-11445616/environment
10977 13:23:39.070710 . /lava-11445616/environment<6>[ 19.580076] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307c7b: link becomes ready
10978 13:23:39.070828 <6>[ 19.588188] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10979 13:23:39.070893 <3>[ 19.602817] mt7921e 0000:01:00.0: hardware init failed
10980 13:23:39.076039
10982 13:23:39.176634 / # /lava-11445616/bin/lava-test-runner /lava-11445616/0
10983 13:23:39.176819 Test shell timeout: 10s (minimum of the action and connection timeout)
10984 13:23:39.182252 /lava-11445616/bin/lava-test-runner /lava-11445616/0
10985 13:23:39.205637 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
10986 13:23:39.212583 + cd /lava-11445616/0/tests/0_v4l2-compliance-mtk-vcodec-enc
10987 13:23:39.212704 + cat uuid
10988 13:23:39.215358 + UUID=11445616_1.5.2.3.1
10989 13:23:39.215442 + set +x
10990 13:23:39.222581 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 11445616_1.5.2.3.1>
10991 13:23:39.222861 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 11445616_1.5.2.3.1
10992 13:23:39.222947 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (11445616_1.5.2.3.1)
10993 13:23:39.223031 Skipping test definition patterns.
10994 13:23:39.225855 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
10995 13:23:39.231912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
10996 13:23:39.232205 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
10998 13:23:39.242122 device: /dev/video2<4>[ 19.772202] use of bytesused == 0 is deprecated and will be removed in the future,
10999 13:23:39.245203 <4>[ 19.781501] use the actual size instead.
11000 13:23:39.245301
11001 13:23:39.251687 <4>[ 19.787621] ------------[ cut here ]------------
11002 13:23:39.258777 <4>[ 19.792530] get_vaddr_frames() cannot follow VM_IO mapping
11003 13:23:39.268214 <4>[ 19.792663] WARNING: CPU: 2 PID: 311 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11004 13:23:39.317728 <4>[ 19.810768] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 btusb btintel mac80211 btmtk libarc4 btrtl mtk_vcodec_enc btbcm mtk_vcodec_common mtk_vpu uvcvideo cfg80211 v4l2_mem2mem videobuf2_vmalloc videobuf2_dma_contig cros_ec_rpmsg videobuf2_memops r8153_ecm videobuf2_v4l2 videobuf2_common bluetooth ecdh_generic cdc_ether videodev ecc usbnet crct10dif_ce sbs_battery rfkill r8152 mc elants_i2c elan_i2c cros_ec_chardev cros_ec_typec mtk_scp hid_google_hammer mtk_rpmsg hid_vivaldi_common mtk_scp_ipi pcie_mediatek_gen3 ip_tables x_tables ipv6
11005 13:23:39.327717 <4>[ 19.860153] CPU: 2 PID: 311 Comm: v4l2-compliance Not tainted 6.1.46-cip4 #1
11006 13:23:39.331784 <4>[ 19.867451] Hardware name: Google Spherion (rev0 - 3) (DT)
11007 13:23:39.340852 <4>[ 19.873186] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11008 13:23:39.344446 <4>[ 19.880397] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11009 13:23:39.350908 <4>[ 19.886488] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11010 13:23:39.354111 <4>[ 19.892578] sp : ffff8000090ab850
11011 13:23:39.364158 <4>[ 19.896142] x29: ffff8000090ab850 x28: ffffb5906299f000 x27: ffffb5906299b238
11012 13:23:39.370811 <4>[ 19.903529] x26: 0000000000000000 x25: ffffb5909222c0e0 x24: ffff6127ce609298
11013 13:23:39.377097 <4>[ 19.910915] x23: ffff6127cc10b400 x22: ffff6127c0d48410 x21: 0000000000000000
11014 13:23:39.383801 <4>[ 19.918301] x20: 00000000fffffff2 x19: ffff6127ccd8ad00 x18: fffffffffffe9760
11015 13:23:39.394388 <4>[ 19.925688] x17: 0000000000000000 x16: ffffb5909008bb90 x15: 0000000000000038
11016 13:23:39.400490 <4>[ 19.933074] x14: ffffb59092b134a8 x13: 000000000000064e x12: 000000000000021a
11017 13:23:39.406921 <4>[ 19.940461] x11: fffffffffffe9760 x10: fffffffffffe9728 x9 : 00000000fffff21a
11018 13:23:39.413603 <4>[ 19.947847] x8 : ffffb59092b134a8 x7 : ffffb59092b6b4a8 x6 : 0000000000001938
11019 13:23:39.420095 <4>[ 19.955234] x5 : ffff6128fef3fa18 x4 : 00000000fffff21a x3 : ffffab986caec000
11020 13:23:39.430073 <4>[ 19.962621] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff6127ca9049c0
11021 13:23:39.433559 <4>[ 19.970009] Call trace:
11022 13:23:39.436999 <4>[ 19.972705] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11023 13:23:39.443315 <4>[ 19.978450] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11024 13:23:39.449858 <4>[ 19.984452] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11025 13:23:39.456988 <4>[ 19.990803] __prepare_userptr+0x280/0x410 [videobuf2_common]
11026 13:23:39.462954 <4>[ 19.996807] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11027 13:23:39.466567 <4>[ 20.002463] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11028 13:23:39.472884 <4>[ 20.008640] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11029 13:23:39.479468 <4>[ 20.014139] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11030 13:23:39.486159 <4>[ 20.019897] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11031 13:23:39.489445 <4>[ 20.026162] v4l_prepare_buf+0x48/0x60 [videodev]
11032 13:23:39.495899 <4>[ 20.031193] __video_do_ioctl+0x184/0x3d0 [videodev]
11033 13:23:39.499670 <4>[ 20.036437] video_usercopy+0x358/0x680 [videodev]
11034 13:23:39.506078 <4>[ 20.041508] video_ioctl2+0x18/0x30 [videodev]
11035 13:23:39.509845 <4>[ 20.046232] v4l2_ioctl+0x40/0x60 [videodev]
11036 13:23:39.512877 <4>[ 20.050782] __arm64_sys_ioctl+0xa8/0xf0
11037 13:23:39.519272 <4>[ 20.054962] invoke_syscall+0x48/0x114
11038 13:23:39.522902 <4>[ 20.058967] el0_svc_common.constprop.0+0x44/0xec
11039 13:23:39.526084 <4>[ 20.063922] do_el0_svc+0x2c/0xd0
11040 13:23:39.529768 <4>[ 20.067489] el0_svc+0x2c/0x84
11041 13:23:39.533306 <4>[ 20.070796] el0t_64_sync_handler+0xb8/0xc0
11042 13:23:39.540232 <4>[ 20.075231] el0t_64_sync+0x18c/0x190
11043 13:23:39.542955 <4>[ 20.079146] ---[ end trace 0000000000000000 ]---
11044 13:23:39.558016 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11045 13:23:39.568202 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11046 13:23:39.574643
11047 13:23:39.589408 Compliance test for mtk-vcodec-enc device /dev/video2:
11048 13:23:39.600831
11049 13:23:39.612057 Driver Info:
11050 13:23:39.624149 Driver name : mtk-vcodec-enc
11051 13:23:39.640287 Card type : MT8192 video encoder
11052 13:23:39.653268 Bus info : platform:17020000.vcodec
11053 13:23:39.662028 Driver version : 6.1.46
11054 13:23:39.672962 Capabilities : 0x84204000
11055 13:23:39.688830 Video Memory-to-Memory Multiplanar
11056 13:23:39.695528 Streaming
11057 13:23:39.705859 Extended Pix Format
11058 13:23:39.717506 Device Capabilities
11059 13:23:39.730895 Device Caps : 0x04204000
11060 13:23:39.740584 Video Memory-to-Memory Multiplanar
11061 13:23:39.754120 Streaming
11062 13:23:39.768266 Extended Pix Format
11063 13:23:39.779831 Detected Stateful Encoder
11064 13:23:39.791514
11065 13:23:39.806213 Required ioctls:
11066 13:23:39.821640 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11067 13:23:39.821785 test VIDIOC_QUERYCAP: OK
11068 13:23:39.822038 Received signal: <TESTSET> START Required-ioctls
11069 13:23:39.822115 Starting test_set Required-ioctls
11070 13:23:39.848516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11071 13:23:39.848847 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11073 13:23:39.851491 test invalid ioctls: OK
11074 13:23:39.878770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11075 13:23:39.878920
11076 13:23:39.879163 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11078 13:23:39.889513 Allow for multiple opens:
11079 13:23:39.898171 <LAVA_SIGNAL_TESTSET STOP>
11080 13:23:39.898482 Received signal: <TESTSET> STOP
11081 13:23:39.898561 Closing test_set Required-ioctls
11082 13:23:39.909503 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11083 13:23:39.909812 Received signal: <TESTSET> START Allow-for-multiple-opens
11084 13:23:39.909890 Starting test_set Allow-for-multiple-opens
11085 13:23:39.912663 test second /dev/video2 open: OK
11086 13:23:39.935134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11087 13:23:39.935461 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11089 13:23:39.938113 test VIDIOC_QUERYCAP: OK
11090 13:23:39.958907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11091 13:23:39.959234 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11093 13:23:39.962804 test VIDIOC_G/S_PRIORITY: OK
11094 13:23:39.985060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11095 13:23:39.985389 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11097 13:23:39.988143 test for unlimited opens: OK
11098 13:23:40.008990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11099 13:23:40.009143
11100 13:23:40.009387 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11102 13:23:40.020304 Debug ioctls:
11103 13:23:40.032252 <LAVA_SIGNAL_TESTSET STOP>
11104 13:23:40.032584 Received signal: <TESTSET> STOP
11105 13:23:40.032658 Closing test_set Allow-for-multiple-opens
11106 13:23:40.041090 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11107 13:23:40.041375 Received signal: <TESTSET> START Debug-ioctls
11108 13:23:40.041451 Starting test_set Debug-ioctls
11109 13:23:40.044375 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11110 13:23:40.070291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11111 13:23:40.070619 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11113 13:23:40.076775 test VIDIOC_LOG_STATUS: OK (Not Supported)
11114 13:23:40.096338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11115 13:23:40.096485
11116 13:23:40.096726 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11118 13:23:40.108058 Input ioctls:
11119 13:23:40.115854 <LAVA_SIGNAL_TESTSET STOP>
11120 13:23:40.116203 Received signal: <TESTSET> STOP
11121 13:23:40.116280 Closing test_set Debug-ioctls
11122 13:23:40.125177 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11123 13:23:40.125468 Received signal: <TESTSET> START Input-ioctls
11124 13:23:40.125540 Starting test_set Input-ioctls
11125 13:23:40.128579 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11126 13:23:40.153325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11127 13:23:40.153656 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11129 13:23:40.156772 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11130 13:23:40.174771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11131 13:23:40.175102 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11133 13:23:40.181298 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11134 13:23:40.198463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11135 13:23:40.198788 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11137 13:23:40.205122 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11138 13:23:40.226613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11139 13:23:40.226942 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11141 13:23:40.232450 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11142 13:23:40.248680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11143 13:23:40.249007 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11145 13:23:40.251891 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11146 13:23:40.279343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11147 13:23:40.279669 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11149 13:23:40.282800 Inputs: 0 Audio Inputs: 0 Tuners: 0
11150 13:23:40.288467
11151 13:23:40.309054 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11152 13:23:40.335290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11153 13:23:40.335616 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11155 13:23:40.341916 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11156 13:23:40.359228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11157 13:23:40.359553 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11159 13:23:40.366014 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11160 13:23:40.385126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11161 13:23:40.385451 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11163 13:23:40.391099 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11164 13:23:40.411006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11165 13:23:40.411343 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11167 13:23:40.416742 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11168 13:23:40.435236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11169 13:23:40.435384
11170 13:23:40.435628 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11172 13:23:40.453983 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11173 13:23:40.476377 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11175 13:23:40.479929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11176 13:23:40.483175 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11177 13:23:40.505975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11178 13:23:40.506304 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11180 13:23:40.509693 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11181 13:23:40.529183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11182 13:23:40.529512 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11184 13:23:40.535152 test VIDIOC_G/S_EDID: OK (Not Supported)
11185 13:23:40.563865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11186 13:23:40.564031
11187 13:23:40.564277 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11189 13:23:40.572273 Control ioctls:
11190 13:23:40.577148 <LAVA_SIGNAL_TESTSET STOP>
11191 13:23:40.577429 Received signal: <TESTSET> STOP
11192 13:23:40.577503 Closing test_set Input-ioctls
11193 13:23:40.585781 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11194 13:23:40.586060 Received signal: <TESTSET> START Control-ioctls
11195 13:23:40.586133 Starting test_set Control-ioctls
11196 13:23:40.588640 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11197 13:23:40.610752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11198 13:23:40.610902 test VIDIOC_QUERYCTRL: OK
11199 13:23:40.611144 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11201 13:23:40.628210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11202 13:23:40.628534 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11204 13:23:40.631741 test VIDIOC_G/S_CTRL: OK
11205 13:23:40.650280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11206 13:23:40.650609 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11208 13:23:40.654020 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11209 13:23:40.674102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11210 13:23:40.674426 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11212 13:23:40.684947 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11213 13:23:40.687459 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11214 13:23:40.716448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11215 13:23:40.716774 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11217 13:23:40.719550 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11218 13:23:40.736513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11219 13:23:40.736838 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11221 13:23:40.739672 Standard Controls: 16 Private Controls: 0
11222 13:23:40.746641
11223 13:23:40.757218 Format ioctls:
11224 13:23:40.765388 <LAVA_SIGNAL_TESTSET STOP>
11225 13:23:40.765696 Received signal: <TESTSET> STOP
11226 13:23:40.765768 Closing test_set Control-ioctls
11227 13:23:40.773956 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11228 13:23:40.774247 Received signal: <TESTSET> START Format-ioctls
11229 13:23:40.774321 Starting test_set Format-ioctls
11230 13:23:40.776943 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11231 13:23:40.804164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11232 13:23:40.804493 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11234 13:23:40.806650 test VIDIOC_G/S_PARM: OK
11235 13:23:40.830318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11236 13:23:40.830644 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11238 13:23:40.833041 test VIDIOC_G_FBUF: OK (Not Supported)
11239 13:23:40.855114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11240 13:23:40.855440 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11242 13:23:40.859030 test VIDIOC_G_FMT: OK
11243 13:23:40.885117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11244 13:23:40.885447 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11246 13:23:40.887051 test VIDIOC_TRY_FMT: OK
11247 13:23:40.907449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11248 13:23:40.907778 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11250 13:23:40.916994 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11251 13:23:40.917112 test VIDIOC_S_FMT: FAIL
11252 13:23:40.941742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11253 13:23:40.942071 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11255 13:23:40.944823 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11256 13:23:40.971621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11257 13:23:40.971970 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11259 13:23:40.973480 test Cropping: OK
11260 13:23:40.995304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11261 13:23:40.995632 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11263 13:23:40.998340 test Composing: OK (Not Supported)
11264 13:23:41.020287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11265 13:23:41.020661 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11267 13:23:41.022820 test Scaling: OK (Not Supported)
11268 13:23:41.043652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11269 13:23:41.043803
11270 13:23:41.044050 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11272 13:23:41.054342 Codec ioctls:
11273 13:23:41.061020 <LAVA_SIGNAL_TESTSET STOP>
11274 13:23:41.061318 Received signal: <TESTSET> STOP
11275 13:23:41.061393 Closing test_set Format-ioctls
11276 13:23:41.071309 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11277 13:23:41.071606 Received signal: <TESTSET> START Codec-ioctls
11278 13:23:41.071681 Starting test_set Codec-ioctls
11279 13:23:41.074733 test VIDIOC_(TRY_)ENCODER_CMD: OK
11280 13:23:41.095076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11281 13:23:41.095397 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11283 13:23:41.101230 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11284 13:23:41.120639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11285 13:23:41.120964 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11287 13:23:41.126976 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11288 13:23:41.147353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11289 13:23:41.147505
11290 13:23:41.147749 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11292 13:23:41.157828 Buffer ioctls:
11293 13:23:41.164041 <LAVA_SIGNAL_TESTSET STOP>
11294 13:23:41.164330 Received signal: <TESTSET> STOP
11295 13:23:41.164405 Closing test_set Codec-ioctls
11296 13:23:41.173792 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11297 13:23:41.174093 Received signal: <TESTSET> START Buffer-ioctls
11298 13:23:41.174168 Starting test_set Buffer-ioctls
11299 13:23:41.176870 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11300 13:23:41.200201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11301 13:23:41.200356 test VIDIOC_EXPBUF: OK
11302 13:23:41.200599 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11304 13:23:41.221380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11305 13:23:41.221708 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11307 13:23:41.224321 test Requests: OK (Not Supported)
11308 13:23:41.246428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11309 13:23:41.246579
11310 13:23:41.246824 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11312 13:23:41.257517 Test input 0:
11313 13:23:41.268040
11314 13:23:41.278769 Streaming ioctls:
11315 13:23:41.289212 <LAVA_SIGNAL_TESTSET STOP>
11316 13:23:41.289540 Received signal: <TESTSET> STOP
11317 13:23:41.289613 Closing test_set Buffer-ioctls
11318 13:23:41.298702 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11319 13:23:41.298993 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11320 13:23:41.299071 Starting test_set Streaming-ioctls_Test-input-0
11321 13:23:41.301964 test read/write: OK (Not Supported)
11322 13:23:41.324994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11323 13:23:41.325327 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11325 13:23:41.331643 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11326 13:23:41.345690 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11327 13:23:41.352914 test blocking wait: FAIL
11328 13:23:41.378883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11329 13:23:41.379211 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11331 13:23:41.388278 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11332 13:23:41.391765 test MMAP (select): FAIL
11333 13:23:41.416275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11334 13:23:41.416602 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11336 13:23:41.423311 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11337 13:23:41.426312 test MMAP (epoll): FAIL
11338 13:23:41.450304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11339 13:23:41.450628 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11341 13:23:41.460324 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11342 13:23:41.466723 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11343 13:23:41.472698 test USERPTR (select): FAIL
11344 13:23:41.500330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11345 13:23:41.500627 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11347 13:23:41.506809 test DMABUF: Cannot test, specify --expbuf-device
11348 13:23:41.510585
11349 13:23:41.529840 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11350 13:23:41.533489 <LAVA_TEST_RUNNER EXIT>
11351 13:23:41.533751 ok: lava_test_shell seems to have completed
11352 13:23:41.533826 Marking unfinished test run as failed
11354 13:23:41.534720 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11355 13:23:41.534839 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11356 13:23:41.534927 end: 3 lava-test-retry (duration 00:00:03) [common]
11357 13:23:41.535013 start: 4 finalize (timeout 00:07:31) [common]
11358 13:23:41.535102 start: 4.1 power-off (timeout 00:00:30) [common]
11359 13:23:41.535252 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11360 13:23:41.611973 >> Command sent successfully.
11361 13:23:41.614399 Returned 0 in 0 seconds
11362 13:23:41.714822 end: 4.1 power-off (duration 00:00:00) [common]
11364 13:23:41.715176 start: 4.2 read-feedback (timeout 00:07:31) [common]
11365 13:23:41.715440 Listened to connection for namespace 'common' for up to 1s
11366 13:23:42.716048 Finalising connection for namespace 'common'
11367 13:23:42.716225 Disconnecting from shell: Finalise
11368 13:23:42.716302 / #
11369 13:23:42.816674 end: 4.2 read-feedback (duration 00:00:01) [common]
11370 13:23:42.816862 end: 4 finalize (duration 00:00:01) [common]
11371 13:23:42.816974 Cleaning after the job
11372 13:23:42.817079 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11445616/tftp-deploy-92azwfrb/ramdisk
11373 13:23:42.822750 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11445616/tftp-deploy-92azwfrb/kernel
11374 13:23:42.831091 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11445616/tftp-deploy-92azwfrb/dtb
11375 13:23:42.831284 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11445616/tftp-deploy-92azwfrb/modules
11376 13:23:42.838675 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11445616
11377 13:23:42.906461 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11445616
11378 13:23:42.906644 Job finished correctly